1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* Some ISA's have delay slots for instructions which read or write
241 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
242 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
243 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
244 delay slot in this ISA. The uses of this macro assume that any
245 ISA that has delay slots for one of these, has them for all. They
246 also assume that ISAs which don't have delays for these insns, don't
247 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
248 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
250 || (ISA) == ISA_MIPS2 \
251 || (ISA) == ISA_MIPS3 \
254 /* True if the given ABI requires 32-bit registers. */
255 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
257 /* Likewise 64-bit registers. */
258 #define ABI_NEEDS_64BIT_REGS(ABI) \
260 || (ABI) == N64_ABI \
263 /* Return true if ISA supports 64 bit gp register instructions. */
264 #define ISA_HAS_64BIT_REGS(ISA) ( \
266 || (ISA) == ISA_MIPS4 \
267 || (ISA) == ISA_MIPS5 \
268 || (ISA) == ISA_MIPS64 \
269 || (ISA) == ISA_MIPS64R2 \
272 /* Return true if ISA supports 64-bit right rotate (dror et al.)
274 #define ISA_HAS_DROR(ISA) ( \
275 (ISA) == ISA_MIPS64R2 \
278 /* Return true if ISA supports 32-bit right rotate (ror et al.)
280 #define ISA_HAS_ROR(ISA) ( \
281 (ISA) == ISA_MIPS32R2 \
282 || (ISA) == ISA_MIPS64R2 \
285 #define HAVE_32BIT_GPRS \
286 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
288 #define HAVE_32BIT_FPRS \
289 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
291 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
292 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
294 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
296 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
298 /* We can only have 64bit addresses if the object file format
300 #define HAVE_32BIT_ADDRESSES \
302 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
303 || ! HAVE_64BIT_OBJECTS) \
304 && mips_pic != EMBEDDED_PIC))
306 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
308 /* Addresses are loaded in different ways, depending on the address size
309 in use. The n32 ABI Documentation also mandates the use of additions
310 with overflow checking, but existing implementations don't follow it. */
311 #define ADDRESS_ADD_INSN \
312 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
314 #define ADDRESS_ADDI_INSN \
315 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
317 #define ADDRESS_LOAD_INSN \
318 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
320 #define ADDRESS_STORE_INSN \
321 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
323 /* Return true if the given CPU supports the MIPS16 ASE. */
324 #define CPU_HAS_MIPS16(cpu) \
325 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
326 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
328 /* Return true if the given CPU supports the MIPS3D ASE. */
329 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
332 /* Return true if the given CPU supports the MDMX ASE. */
333 #define CPU_HAS_MDMX(cpu) (FALSE \
336 /* True if CPU has a dror instruction. */
337 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
339 /* True if CPU has a ror instruction. */
340 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
342 /* Whether the processor uses hardware interlocks to protect
343 reads from the HI and LO registers, and thus does not
344 require nops to be inserted. */
346 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
347 || mips_opts.arch == CPU_VR5500 \
348 || mips_opts.arch == CPU_RM7000 \
349 || mips_opts.arch == CPU_SB1 \
352 /* Whether the processor uses hardware interlocks to protect reads
353 from the GPRs, and thus does not require nops to be inserted. */
354 #define gpr_interlocks \
355 (mips_opts.isa != ISA_MIPS1 \
356 || mips_opts.arch == CPU_VR5400 \
357 || mips_opts.arch == CPU_VR5500 \
358 || mips_opts.arch == CPU_R3900)
360 /* As with other "interlocks" this is used by hardware that has FP
361 (co-processor) interlocks. */
362 /* Itbl support may require additional care here. */
363 #define cop_interlocks (mips_opts.arch == CPU_R4300 \
364 || mips_opts.arch == CPU_VR5400 \
365 || mips_opts.arch == CPU_VR5500 \
366 || mips_opts.arch == CPU_SB1 \
369 /* Is this a mfhi or mflo instruction? */
370 #define MF_HILO_INSN(PINFO) \
371 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
373 /* MIPS PIC level. */
375 enum mips_pic_level mips_pic;
377 /* Warn about all NOPS that the assembler generates. */
378 static int warn_nops = 0;
380 /* 1 if we should generate 32 bit offsets from the $gp register in
381 SVR4_PIC mode. Currently has no meaning in other modes. */
382 static int mips_big_got = 0;
384 /* 1 if trap instructions should used for overflow rather than break
386 static int mips_trap = 0;
388 /* 1 if double width floating point constants should not be constructed
389 by assembling two single width halves into two single width floating
390 point registers which just happen to alias the double width destination
391 register. On some architectures this aliasing can be disabled by a bit
392 in the status register, and the setting of this bit cannot be determined
393 automatically at assemble time. */
394 static int mips_disable_float_construction;
396 /* Non-zero if any .set noreorder directives were used. */
398 static int mips_any_noreorder;
400 /* Non-zero if nops should be inserted when the register referenced in
401 an mfhi/mflo instruction is read in the next two instructions. */
402 static int mips_7000_hilo_fix;
404 /* The size of the small data section. */
405 static unsigned int g_switch_value = 8;
406 /* Whether the -G option was used. */
407 static int g_switch_seen = 0;
412 /* If we can determine in advance that GP optimization won't be
413 possible, we can skip the relaxation stuff that tries to produce
414 GP-relative references. This makes delay slot optimization work
417 This function can only provide a guess, but it seems to work for
418 gcc output. It needs to guess right for gcc, otherwise gcc
419 will put what it thinks is a GP-relative instruction in a branch
422 I don't know if a fix is needed for the SVR4_PIC mode. I've only
423 fixed it for the non-PIC mode. KR 95/04/07 */
424 static int nopic_need_relax (symbolS *, int);
426 /* handle of the OPCODE hash table */
427 static struct hash_control *op_hash = NULL;
429 /* The opcode hash table we use for the mips16. */
430 static struct hash_control *mips16_op_hash = NULL;
432 /* This array holds the chars that always start a comment. If the
433 pre-processor is disabled, these aren't very useful */
434 const char comment_chars[] = "#";
436 /* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
438 .line and .file directives will appear in the pre-processed output */
439 /* Note that input_file.c hand checks for '#' at the beginning of the
440 first line of the input file. This is because the compiler outputs
441 #NO_APP at the beginning of its output. */
442 /* Also note that C style comments are always supported. */
443 const char line_comment_chars[] = "#";
445 /* This array holds machine specific line separator characters. */
446 const char line_separator_chars[] = ";";
448 /* Chars that can be used to separate mant from exp in floating point nums */
449 const char EXP_CHARS[] = "eE";
451 /* Chars that mean this number is a floating point constant */
454 const char FLT_CHARS[] = "rRsSfFdDxXpP";
456 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
457 changed in read.c . Ideally it shouldn't have to know about it at all,
458 but nothing is ideal around here.
461 static char *insn_error;
463 static int auto_align = 1;
465 /* When outputting SVR4 PIC code, the assembler needs to know the
466 offset in the stack frame from which to restore the $gp register.
467 This is set by the .cprestore pseudo-op, and saved in this
469 static offsetT mips_cprestore_offset = -1;
471 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
472 more optimizations, it can use a register value instead of a memory-saved
473 offset and even an other register than $gp as global pointer. */
474 static offsetT mips_cpreturn_offset = -1;
475 static int mips_cpreturn_register = -1;
476 static int mips_gp_register = GP;
477 static int mips_gprel_offset = 0;
479 /* Whether mips_cprestore_offset has been set in the current function
480 (or whether it has already been warned about, if not). */
481 static int mips_cprestore_valid = 0;
483 /* This is the register which holds the stack frame, as set by the
484 .frame pseudo-op. This is needed to implement .cprestore. */
485 static int mips_frame_reg = SP;
487 /* Whether mips_frame_reg has been set in the current function
488 (or whether it has already been warned about, if not). */
489 static int mips_frame_reg_valid = 0;
491 /* To output NOP instructions correctly, we need to keep information
492 about the previous two instructions. */
494 /* Whether we are optimizing. The default value of 2 means to remove
495 unneeded NOPs and swap branch instructions when possible. A value
496 of 1 means to not swap branches. A value of 0 means to always
498 static int mips_optimize = 2;
500 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
501 equivalent to seeing no -g option at all. */
502 static int mips_debug = 0;
504 /* The previous instruction. */
505 static struct mips_cl_insn prev_insn;
507 /* The instruction before prev_insn. */
508 static struct mips_cl_insn prev_prev_insn;
510 /* If we don't want information for prev_insn or prev_prev_insn, we
511 point the insn_mo field at this dummy integer. */
512 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
514 /* Non-zero if prev_insn is valid. */
515 static int prev_insn_valid;
517 /* The frag for the previous instruction. */
518 static struct frag *prev_insn_frag;
520 /* The offset into prev_insn_frag for the previous instruction. */
521 static long prev_insn_where;
523 /* The reloc type for the previous instruction, if any. */
524 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
526 /* The reloc for the previous instruction, if any. */
527 static fixS *prev_insn_fixp[3];
529 /* Non-zero if the previous instruction was in a delay slot. */
530 static int prev_insn_is_delay_slot;
532 /* Non-zero if the previous instruction was in a .set noreorder. */
533 static int prev_insn_unreordered;
535 /* Non-zero if the previous instruction uses an extend opcode (if
537 static int prev_insn_extended;
539 /* Non-zero if the previous previous instruction was in a .set
541 static int prev_prev_insn_unreordered;
543 /* If this is set, it points to a frag holding nop instructions which
544 were inserted before the start of a noreorder section. If those
545 nops turn out to be unnecessary, the size of the frag can be
547 static fragS *prev_nop_frag;
549 /* The number of nop instructions we created in prev_nop_frag. */
550 static int prev_nop_frag_holds;
552 /* The number of nop instructions that we know we need in
554 static int prev_nop_frag_required;
556 /* The number of instructions we've seen since prev_nop_frag. */
557 static int prev_nop_frag_since;
559 /* For ECOFF and ELF, relocations against symbols are done in two
560 parts, with a HI relocation and a LO relocation. Each relocation
561 has only 16 bits of space to store an addend. This means that in
562 order for the linker to handle carries correctly, it must be able
563 to locate both the HI and the LO relocation. This means that the
564 relocations must appear in order in the relocation table.
566 In order to implement this, we keep track of each unmatched HI
567 relocation. We then sort them so that they immediately precede the
568 corresponding LO relocation. */
573 struct mips_hi_fixup *next;
576 /* The section this fixup is in. */
580 /* The list of unmatched HI relocs. */
582 static struct mips_hi_fixup *mips_hi_fixup_list;
584 /* The frag containing the last explicit relocation operator.
585 Null if explicit relocations have not been used. */
587 static fragS *prev_reloc_op_frag;
589 /* Map normal MIPS register numbers to mips16 register numbers. */
591 #define X ILLEGAL_REG
592 static const int mips32_to_16_reg_map[] =
594 X, X, 2, 3, 4, 5, 6, 7,
595 X, X, X, X, X, X, X, X,
596 0, 1, X, X, X, X, X, X,
597 X, X, X, X, X, X, X, X
601 /* Map mips16 register numbers to normal MIPS register numbers. */
603 static const unsigned int mips16_to_32_reg_map[] =
605 16, 17, 2, 3, 4, 5, 6, 7
608 static int mips_fix_4122_bugs;
610 /* We don't relax branches by default, since this causes us to expand
611 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
612 fail to compute the offset before expanding the macro to the most
613 efficient expansion. */
615 static int mips_relax_branch;
617 /* Since the MIPS does not have multiple forms of PC relative
618 instructions, we do not have to do relaxing as is done on other
619 platforms. However, we do have to handle GP relative addressing
620 correctly, which turns out to be a similar problem.
622 Every macro that refers to a symbol can occur in (at least) two
623 forms, one with GP relative addressing and one without. For
624 example, loading a global variable into a register generally uses
625 a macro instruction like this:
627 If i can be addressed off the GP register (this is true if it is in
628 the .sbss or .sdata section, or if it is known to be smaller than
629 the -G argument) this will generate the following instruction:
631 This instruction will use a GPREL reloc. If i can not be addressed
632 off the GP register, the following instruction sequence will be used:
635 In this case the first instruction will have a HI16 reloc, and the
636 second reloc will have a LO16 reloc. Both relocs will be against
639 The issue here is that we may not know whether i is GP addressable
640 until after we see the instruction that uses it. Therefore, we
641 want to be able to choose the final instruction sequence only at
642 the end of the assembly. This is similar to the way other
643 platforms choose the size of a PC relative instruction only at the
646 When generating position independent code we do not use GP
647 addressing in quite the same way, but the issue still arises as
648 external symbols and local symbols must be handled differently.
650 We handle these issues by actually generating both possible
651 instruction sequences. The longer one is put in a frag_var with
652 type rs_machine_dependent. We encode what to do with the frag in
653 the subtype field. We encode (1) the number of existing bytes to
654 replace, (2) the number of new bytes to use, (3) the offset from
655 the start of the existing bytes to the first reloc we must generate
656 (that is, the offset is applied from the start of the existing
657 bytes after they are replaced by the new bytes, if any), (4) the
658 offset from the start of the existing bytes to the second reloc,
659 (5) whether a third reloc is needed (the third reloc is always four
660 bytes after the second reloc), and (6) whether to warn if this
661 variant is used (this is sometimes needed if .set nomacro or .set
662 noat is in effect). All these numbers are reasonably small.
664 Generating two instruction sequences must be handled carefully to
665 ensure that delay slots are handled correctly. Fortunately, there
666 are a limited number of cases. When the second instruction
667 sequence is generated, append_insn is directed to maintain the
668 existing delay slot information, so it continues to apply to any
669 code after the second instruction sequence. This means that the
670 second instruction sequence must not impose any requirements not
671 required by the first instruction sequence.
673 These variant frags are then handled in functions called by the
674 machine independent code. md_estimate_size_before_relax returns
675 the final size of the frag. md_convert_frag sets up the final form
676 of the frag. tc_gen_reloc adjust the first reloc and adds a second
678 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
682 | (((reloc1) + 64) << 9) \
683 | (((reloc2) + 64) << 2) \
684 | ((reloc3) ? (1 << 1) : 0) \
686 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
687 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
688 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
689 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
690 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
691 #define RELAX_WARN(i) ((i) & 1)
693 /* Branch without likely bit. If label is out of range, we turn:
695 beq reg1, reg2, label
705 with the following opcode replacements:
712 bltzal <-> bgezal (with jal label instead of j label)
714 Even though keeping the delay slot instruction in the delay slot of
715 the branch would be more efficient, it would be very tricky to do
716 correctly, because we'd have to introduce a variable frag *after*
717 the delay slot instruction, and expand that instead. Let's do it
718 the easy way for now, even if the branch-not-taken case now costs
719 one additional instruction. Out-of-range branches are not supposed
720 to be common, anyway.
722 Branch likely. If label is out of range, we turn:
724 beql reg1, reg2, label
725 delay slot (annulled if branch not taken)
734 delay slot (executed only if branch taken)
737 It would be possible to generate a shorter sequence by losing the
738 likely bit, generating something like:
743 delay slot (executed only if branch taken)
755 bltzall -> bgezal (with jal label instead of j label)
756 bgezall -> bltzal (ditto)
759 but it's not clear that it would actually improve performance. */
760 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
763 | ((toofar) ? 1 : 0) \
765 | ((likely) ? 4 : 0) \
766 | ((uncond) ? 8 : 0)))
767 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
768 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
769 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
770 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
771 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
773 /* For mips16 code, we use an entirely different form of relaxation.
774 mips16 supports two versions of most instructions which take
775 immediate values: a small one which takes some small value, and a
776 larger one which takes a 16 bit value. Since branches also follow
777 this pattern, relaxing these values is required.
779 We can assemble both mips16 and normal MIPS code in a single
780 object. Therefore, we need to support this type of relaxation at
781 the same time that we support the relaxation described above. We
782 use the high bit of the subtype field to distinguish these cases.
784 The information we store for this type of relaxation is the
785 argument code found in the opcode file for this relocation, whether
786 the user explicitly requested a small or extended form, and whether
787 the relocation is in a jump or jal delay slot. That tells us the
788 size of the value, and how it should be stored. We also store
789 whether the fragment is considered to be extended or not. We also
790 store whether this is known to be a branch to a different section,
791 whether we have tried to relax this frag yet, and whether we have
792 ever extended a PC relative fragment because of a shift count. */
793 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
796 | ((small) ? 0x100 : 0) \
797 | ((ext) ? 0x200 : 0) \
798 | ((dslot) ? 0x400 : 0) \
799 | ((jal_dslot) ? 0x800 : 0))
800 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
801 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
802 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
803 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
804 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
805 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
806 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
807 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
808 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
809 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
810 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
811 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
813 /* Is the given value a sign-extended 32-bit value? */
814 #define IS_SEXT_32BIT_NUM(x) \
815 (((x) &~ (offsetT) 0x7fffffff) == 0 \
816 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
818 /* Is the given value a sign-extended 16-bit value? */
819 #define IS_SEXT_16BIT_NUM(x) \
820 (((x) &~ (offsetT) 0x7fff) == 0 \
821 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
824 /* Prototypes for static functions. */
826 #define internalError() \
827 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
829 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
831 static void append_insn
832 (char *place, struct mips_cl_insn *ip, expressionS *p,
833 bfd_reloc_code_real_type *r);
834 static void mips_no_prev_insn (int);
835 static void mips16_macro_build
836 (char *, int *, expressionS *, const char *, const char *, va_list);
837 static void load_register (int *, int, expressionS *, int);
838 static void macro (struct mips_cl_insn * ip);
839 static void mips16_macro (struct mips_cl_insn * ip);
840 #ifdef LOSING_COMPILER
841 static void macro2 (struct mips_cl_insn * ip);
843 static void mips_ip (char *str, struct mips_cl_insn * ip);
844 static void mips16_ip (char *str, struct mips_cl_insn * ip);
845 static void mips16_immed
846 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
847 unsigned long *, bfd_boolean *, unsigned short *);
848 static size_t my_getSmallExpression
849 (expressionS *, bfd_reloc_code_real_type *, char *);
850 static void my_getExpression (expressionS *, char *);
851 static void s_align (int);
852 static void s_change_sec (int);
853 static void s_change_section (int);
854 static void s_cons (int);
855 static void s_float_cons (int);
856 static void s_mips_globl (int);
857 static void s_option (int);
858 static void s_mipsset (int);
859 static void s_abicalls (int);
860 static void s_cpload (int);
861 static void s_cpsetup (int);
862 static void s_cplocal (int);
863 static void s_cprestore (int);
864 static void s_cpreturn (int);
865 static void s_gpvalue (int);
866 static void s_gpword (int);
867 static void s_gpdword (int);
868 static void s_cpadd (int);
869 static void s_insn (int);
870 static void md_obj_begin (void);
871 static void md_obj_end (void);
872 static void s_mips_ent (int);
873 static void s_mips_end (int);
874 static void s_mips_frame (int);
875 static void s_mips_mask (int reg_type);
876 static void s_mips_stab (int);
877 static void s_mips_weakext (int);
878 static void s_mips_file (int);
879 static void s_mips_loc (int);
880 static bfd_boolean pic_need_relax (symbolS *, asection *);
881 static int relaxed_branch_length (fragS *, asection *, int);
882 static int validate_mips_insn (const struct mips_opcode *);
884 /* Table and functions used to map between CPU/ISA names, and
885 ISA levels, and CPU numbers. */
889 const char *name; /* CPU or ISA name. */
890 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
891 int isa; /* ISA level. */
892 int cpu; /* CPU number (default CPU if ISA). */
895 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
896 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
897 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
901 The following pseudo-ops from the Kane and Heinrich MIPS book
902 should be defined here, but are currently unsupported: .alias,
903 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
905 The following pseudo-ops from the Kane and Heinrich MIPS book are
906 specific to the type of debugging information being generated, and
907 should be defined by the object format: .aent, .begin, .bend,
908 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
911 The following pseudo-ops from the Kane and Heinrich MIPS book are
912 not MIPS CPU specific, but are also not specific to the object file
913 format. This file is probably the best place to define them, but
914 they are not currently supported: .asm0, .endr, .lab, .repeat,
917 static const pseudo_typeS mips_pseudo_table[] =
919 /* MIPS specific pseudo-ops. */
920 {"option", s_option, 0},
921 {"set", s_mipsset, 0},
922 {"rdata", s_change_sec, 'r'},
923 {"sdata", s_change_sec, 's'},
924 {"livereg", s_ignore, 0},
925 {"abicalls", s_abicalls, 0},
926 {"cpload", s_cpload, 0},
927 {"cpsetup", s_cpsetup, 0},
928 {"cplocal", s_cplocal, 0},
929 {"cprestore", s_cprestore, 0},
930 {"cpreturn", s_cpreturn, 0},
931 {"gpvalue", s_gpvalue, 0},
932 {"gpword", s_gpword, 0},
933 {"gpdword", s_gpdword, 0},
934 {"cpadd", s_cpadd, 0},
937 /* Relatively generic pseudo-ops that happen to be used on MIPS
939 {"asciiz", stringer, 1},
940 {"bss", s_change_sec, 'b'},
943 {"dword", s_cons, 3},
944 {"weakext", s_mips_weakext, 0},
946 /* These pseudo-ops are defined in read.c, but must be overridden
947 here for one reason or another. */
948 {"align", s_align, 0},
950 {"data", s_change_sec, 'd'},
951 {"double", s_float_cons, 'd'},
952 {"float", s_float_cons, 'f'},
953 {"globl", s_mips_globl, 0},
954 {"global", s_mips_globl, 0},
955 {"hword", s_cons, 1},
960 {"section", s_change_section, 0},
961 {"short", s_cons, 1},
962 {"single", s_float_cons, 'f'},
963 {"stabn", s_mips_stab, 'n'},
964 {"text", s_change_sec, 't'},
967 { "extern", ecoff_directive_extern, 0},
972 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
974 /* These pseudo-ops should be defined by the object file format.
975 However, a.out doesn't support them, so we have versions here. */
976 {"aent", s_mips_ent, 1},
977 {"bgnb", s_ignore, 0},
978 {"end", s_mips_end, 0},
979 {"endb", s_ignore, 0},
980 {"ent", s_mips_ent, 0},
981 {"file", s_mips_file, 0},
982 {"fmask", s_mips_mask, 'F'},
983 {"frame", s_mips_frame, 0},
984 {"loc", s_mips_loc, 0},
985 {"mask", s_mips_mask, 'R'},
986 {"verstamp", s_ignore, 0},
990 extern void pop_insert (const pseudo_typeS *);
993 mips_pop_insert (void)
995 pop_insert (mips_pseudo_table);
996 if (! ECOFF_DEBUGGING)
997 pop_insert (mips_nonecoff_pseudo_table);
1000 /* Symbols labelling the current insn. */
1002 struct insn_label_list
1004 struct insn_label_list *next;
1008 static struct insn_label_list *insn_labels;
1009 static struct insn_label_list *free_insn_labels;
1011 static void mips_clear_insn_labels (void);
1014 mips_clear_insn_labels (void)
1016 register struct insn_label_list **pl;
1018 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1024 static char *expr_end;
1026 /* Expressions which appear in instructions. These are set by
1029 static expressionS imm_expr;
1030 static expressionS imm2_expr;
1031 static expressionS offset_expr;
1033 /* Relocs associated with imm_expr and offset_expr. */
1035 static bfd_reloc_code_real_type imm_reloc[3]
1036 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1037 static bfd_reloc_code_real_type offset_reloc[3]
1038 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1040 /* These are set by mips16_ip if an explicit extension is used. */
1042 static bfd_boolean mips16_small, mips16_ext;
1045 /* The pdr segment for per procedure frame/regmask info. Not used for
1048 static segT pdr_seg;
1051 /* The default target format to use. */
1054 mips_target_format (void)
1056 switch (OUTPUT_FLAVOR)
1058 case bfd_target_aout_flavour:
1059 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1060 case bfd_target_ecoff_flavour:
1061 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1062 case bfd_target_coff_flavour:
1064 case bfd_target_elf_flavour:
1066 /* This is traditional mips. */
1067 return (target_big_endian
1068 ? (HAVE_64BIT_OBJECTS
1069 ? "elf64-tradbigmips"
1071 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1072 : (HAVE_64BIT_OBJECTS
1073 ? "elf64-tradlittlemips"
1075 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1077 return (target_big_endian
1078 ? (HAVE_64BIT_OBJECTS
1081 ? "elf32-nbigmips" : "elf32-bigmips"))
1082 : (HAVE_64BIT_OBJECTS
1083 ? "elf64-littlemips"
1085 ? "elf32-nlittlemips" : "elf32-littlemips")));
1093 /* This function is called once, at assembler startup time. It should
1094 set up all the tables, etc. that the MD part of the assembler will need. */
1099 register const char *retval = NULL;
1103 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1104 as_warn (_("Could not set architecture and machine"));
1106 op_hash = hash_new ();
1108 for (i = 0; i < NUMOPCODES;)
1110 const char *name = mips_opcodes[i].name;
1112 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1115 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1116 mips_opcodes[i].name, retval);
1117 /* Probably a memory allocation problem? Give up now. */
1118 as_fatal (_("Broken assembler. No assembly attempted."));
1122 if (mips_opcodes[i].pinfo != INSN_MACRO)
1124 if (!validate_mips_insn (&mips_opcodes[i]))
1129 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1132 mips16_op_hash = hash_new ();
1135 while (i < bfd_mips16_num_opcodes)
1137 const char *name = mips16_opcodes[i].name;
1139 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1141 as_fatal (_("internal: can't hash `%s': %s"),
1142 mips16_opcodes[i].name, retval);
1145 if (mips16_opcodes[i].pinfo != INSN_MACRO
1146 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1147 != mips16_opcodes[i].match))
1149 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1150 mips16_opcodes[i].name, mips16_opcodes[i].args);
1155 while (i < bfd_mips16_num_opcodes
1156 && strcmp (mips16_opcodes[i].name, name) == 0);
1160 as_fatal (_("Broken assembler. No assembly attempted."));
1162 /* We add all the general register names to the symbol table. This
1163 helps us detect invalid uses of them. */
1164 for (i = 0; i < 32; i++)
1168 sprintf (buf, "$%d", i);
1169 symbol_table_insert (symbol_new (buf, reg_section, i,
1170 &zero_address_frag));
1172 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1173 &zero_address_frag));
1174 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1175 &zero_address_frag));
1176 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1177 &zero_address_frag));
1178 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1179 &zero_address_frag));
1180 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1181 &zero_address_frag));
1182 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1183 &zero_address_frag));
1184 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1185 &zero_address_frag));
1186 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1187 &zero_address_frag));
1188 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1189 &zero_address_frag));
1191 /* If we don't add these register names to the symbol table, they
1192 may end up being added as regular symbols by operand(), and then
1193 make it to the object file as undefined in case they're not
1194 regarded as local symbols. They're local in o32, since `$' is a
1195 local symbol prefix, but not in n32 or n64. */
1196 for (i = 0; i < 8; i++)
1200 sprintf (buf, "$fcc%i", i);
1201 symbol_table_insert (symbol_new (buf, reg_section, -1,
1202 &zero_address_frag));
1205 mips_no_prev_insn (FALSE);
1208 mips_cprmask[0] = 0;
1209 mips_cprmask[1] = 0;
1210 mips_cprmask[2] = 0;
1211 mips_cprmask[3] = 0;
1213 /* set the default alignment for the text section (2**2) */
1214 record_alignment (text_section, 2);
1216 if (USE_GLOBAL_POINTER_OPT)
1217 bfd_set_gp_size (stdoutput, g_switch_value);
1219 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1221 /* On a native system, sections must be aligned to 16 byte
1222 boundaries. When configured for an embedded ELF target, we
1224 if (strcmp (TARGET_OS, "elf") != 0)
1226 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1227 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1228 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1231 /* Create a .reginfo section for register masks and a .mdebug
1232 section for debugging information. */
1240 subseg = now_subseg;
1242 /* The ABI says this section should be loaded so that the
1243 running program can access it. However, we don't load it
1244 if we are configured for an embedded target */
1245 flags = SEC_READONLY | SEC_DATA;
1246 if (strcmp (TARGET_OS, "elf") != 0)
1247 flags |= SEC_ALLOC | SEC_LOAD;
1249 if (mips_abi != N64_ABI)
1251 sec = subseg_new (".reginfo", (subsegT) 0);
1253 bfd_set_section_flags (stdoutput, sec, flags);
1254 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1257 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1262 /* The 64-bit ABI uses a .MIPS.options section rather than
1263 .reginfo section. */
1264 sec = subseg_new (".MIPS.options", (subsegT) 0);
1265 bfd_set_section_flags (stdoutput, sec, flags);
1266 bfd_set_section_alignment (stdoutput, sec, 3);
1269 /* Set up the option header. */
1271 Elf_Internal_Options opthdr;
1274 opthdr.kind = ODK_REGINFO;
1275 opthdr.size = (sizeof (Elf_External_Options)
1276 + sizeof (Elf64_External_RegInfo));
1279 f = frag_more (sizeof (Elf_External_Options));
1280 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1281 (Elf_External_Options *) f);
1283 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1288 if (ECOFF_DEBUGGING)
1290 sec = subseg_new (".mdebug", (subsegT) 0);
1291 (void) bfd_set_section_flags (stdoutput, sec,
1292 SEC_HAS_CONTENTS | SEC_READONLY);
1293 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1296 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1298 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1299 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1300 SEC_READONLY | SEC_RELOC
1302 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1306 subseg_set (seg, subseg);
1310 if (! ECOFF_DEBUGGING)
1317 if (! ECOFF_DEBUGGING)
1322 md_assemble (char *str)
1324 struct mips_cl_insn insn;
1325 bfd_reloc_code_real_type unused_reloc[3]
1326 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1328 imm_expr.X_op = O_absent;
1329 imm2_expr.X_op = O_absent;
1330 offset_expr.X_op = O_absent;
1331 imm_reloc[0] = BFD_RELOC_UNUSED;
1332 imm_reloc[1] = BFD_RELOC_UNUSED;
1333 imm_reloc[2] = BFD_RELOC_UNUSED;
1334 offset_reloc[0] = BFD_RELOC_UNUSED;
1335 offset_reloc[1] = BFD_RELOC_UNUSED;
1336 offset_reloc[2] = BFD_RELOC_UNUSED;
1338 if (mips_opts.mips16)
1339 mips16_ip (str, &insn);
1342 mips_ip (str, &insn);
1343 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1344 str, insn.insn_opcode));
1349 as_bad ("%s `%s'", insn_error, str);
1353 if (insn.insn_mo->pinfo == INSN_MACRO)
1355 if (mips_opts.mips16)
1356 mips16_macro (&insn);
1362 if (imm_expr.X_op != O_absent)
1363 append_insn (NULL, &insn, &imm_expr, imm_reloc);
1364 else if (offset_expr.X_op != O_absent)
1365 append_insn (NULL, &insn, &offset_expr, offset_reloc);
1367 append_insn (NULL, &insn, NULL, unused_reloc);
1371 /* Return true if the given relocation might need a matching %lo().
1372 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1373 applied to local symbols. */
1375 static inline bfd_boolean
1376 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1378 return (reloc == BFD_RELOC_HI16_S
1379 || reloc == BFD_RELOC_MIPS_GOT16);
1382 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1385 static inline bfd_boolean
1386 fixup_has_matching_lo_p (fixS *fixp)
1388 return (fixp->fx_next != NULL
1389 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1390 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1391 && fixp->fx_offset == fixp->fx_next->fx_offset);
1394 /* See whether instruction IP reads register REG. CLASS is the type
1398 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1399 enum mips_regclass class)
1401 if (class == MIPS16_REG)
1403 assert (mips_opts.mips16);
1404 reg = mips16_to_32_reg_map[reg];
1405 class = MIPS_GR_REG;
1408 /* Don't report on general register ZERO, since it never changes. */
1409 if (class == MIPS_GR_REG && reg == ZERO)
1412 if (class == MIPS_FP_REG)
1414 assert (! mips_opts.mips16);
1415 /* If we are called with either $f0 or $f1, we must check $f0.
1416 This is not optimal, because it will introduce an unnecessary
1417 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1418 need to distinguish reading both $f0 and $f1 or just one of
1419 them. Note that we don't have to check the other way,
1420 because there is no instruction that sets both $f0 and $f1
1421 and requires a delay. */
1422 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1423 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1424 == (reg &~ (unsigned) 1)))
1426 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1427 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1428 == (reg &~ (unsigned) 1)))
1431 else if (! mips_opts.mips16)
1433 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1434 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1436 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1437 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1442 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1443 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1444 & MIPS16OP_MASK_RX)]
1447 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1448 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1449 & MIPS16OP_MASK_RY)]
1452 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1453 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1454 & MIPS16OP_MASK_MOVE32Z)]
1457 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1459 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1461 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1463 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1464 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1465 & MIPS16OP_MASK_REGR32) == reg)
1472 /* This function returns true if modifying a register requires a
1476 reg_needs_delay (unsigned int reg)
1478 unsigned long prev_pinfo;
1480 prev_pinfo = prev_insn.insn_mo->pinfo;
1481 if (! mips_opts.noreorder
1482 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1483 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1484 || (! gpr_interlocks
1485 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1487 /* A load from a coprocessor or from memory. All load
1488 delays delay the use of general register rt for one
1489 instruction on the r3000. The r6000 and r4000 use
1491 /* Itbl support may require additional care here. */
1492 know (prev_pinfo & INSN_WRITE_GPR_T);
1493 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1500 /* Mark instruction labels in mips16 mode. This permits the linker to
1501 handle them specially, such as generating jalx instructions when
1502 needed. We also make them odd for the duration of the assembly, in
1503 order to generate the right sort of code. We will make them even
1504 in the adjust_symtab routine, while leaving them marked. This is
1505 convenient for the debugger and the disassembler. The linker knows
1506 to make them odd again. */
1509 mips16_mark_labels (void)
1511 if (mips_opts.mips16)
1513 struct insn_label_list *l;
1516 for (l = insn_labels; l != NULL; l = l->next)
1519 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1520 S_SET_OTHER (l->label, STO_MIPS16);
1522 val = S_GET_VALUE (l->label);
1524 S_SET_VALUE (l->label, val + 1);
1529 /* Output an instruction. PLACE is where to put the instruction; if
1530 it is NULL, this uses frag_more to get room. IP is the instruction
1531 information. ADDRESS_EXPR is an operand of the instruction to be
1532 used with RELOC_TYPE. */
1535 append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr,
1536 bfd_reloc_code_real_type *reloc_type)
1538 register unsigned long prev_pinfo, pinfo;
1542 bfd_boolean force_new_frag = FALSE;
1544 /* Mark instruction labels in mips16 mode. */
1545 mips16_mark_labels ();
1547 prev_pinfo = prev_insn.insn_mo->pinfo;
1548 pinfo = ip->insn_mo->pinfo;
1550 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1554 /* If the previous insn required any delay slots, see if we need
1555 to insert a NOP or two. There are eight kinds of possible
1556 hazards, of which an instruction can have at most one type.
1557 (1) a load from memory delay
1558 (2) a load from a coprocessor delay
1559 (3) an unconditional branch delay
1560 (4) a conditional branch delay
1561 (5) a move to coprocessor register delay
1562 (6) a load coprocessor register from memory delay
1563 (7) a coprocessor condition code delay
1564 (8) a HI/LO special register delay
1566 There are a lot of optimizations we could do that we don't.
1567 In particular, we do not, in general, reorder instructions.
1568 If you use gcc with optimization, it will reorder
1569 instructions and generally do much more optimization then we
1570 do here; repeating all that work in the assembler would only
1571 benefit hand written assembly code, and does not seem worth
1574 /* This is how a NOP is emitted. */
1575 #define emit_nop() \
1577 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1578 : md_number_to_chars (frag_more (4), 0, 4))
1580 /* The previous insn might require a delay slot, depending upon
1581 the contents of the current insn. */
1582 if (! mips_opts.mips16
1583 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1584 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1585 && ! cop_interlocks)
1586 || (! gpr_interlocks
1587 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1589 /* A load from a coprocessor or from memory. All load
1590 delays delay the use of general register rt for one
1591 instruction on the r3000. The r6000 and r4000 use
1593 /* Itbl support may require additional care here. */
1594 know (prev_pinfo & INSN_WRITE_GPR_T);
1595 if (mips_optimize == 0
1596 || insn_uses_reg (ip,
1597 ((prev_insn.insn_opcode >> OP_SH_RT)
1602 else if (! mips_opts.mips16
1603 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1604 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1605 && ! cop_interlocks)
1606 || (mips_opts.isa == ISA_MIPS1
1607 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1609 /* A generic coprocessor delay. The previous instruction
1610 modified a coprocessor general or control register. If
1611 it modified a control register, we need to avoid any
1612 coprocessor instruction (this is probably not always
1613 required, but it sometimes is). If it modified a general
1614 register, we avoid using that register.
1616 On the r6000 and r4000 loading a coprocessor register
1617 from memory is interlocked, and does not require a delay.
1619 This case is not handled very well. There is no special
1620 knowledge of CP0 handling, and the coprocessors other
1621 than the floating point unit are not distinguished at
1623 /* Itbl support may require additional care here. FIXME!
1624 Need to modify this to include knowledge about
1625 user specified delays! */
1626 if (prev_pinfo & INSN_WRITE_FPR_T)
1628 if (mips_optimize == 0
1629 || insn_uses_reg (ip,
1630 ((prev_insn.insn_opcode >> OP_SH_FT)
1635 else if (prev_pinfo & INSN_WRITE_FPR_S)
1637 if (mips_optimize == 0
1638 || insn_uses_reg (ip,
1639 ((prev_insn.insn_opcode >> OP_SH_FS)
1646 /* We don't know exactly what the previous instruction
1647 does. If the current instruction uses a coprocessor
1648 register, we must insert a NOP. If previous
1649 instruction may set the condition codes, and the
1650 current instruction uses them, we must insert two
1652 /* Itbl support may require additional care here. */
1653 if (mips_optimize == 0
1654 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1655 && (pinfo & INSN_READ_COND_CODE)))
1657 else if (pinfo & INSN_COP)
1661 else if (! mips_opts.mips16
1662 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1663 && (prev_pinfo & INSN_WRITE_COND_CODE)
1664 && ! cop_interlocks)
1666 /* The previous instruction sets the coprocessor condition
1667 codes, but does not require a general coprocessor delay
1668 (this means it is a floating point comparison
1669 instruction). If this instruction uses the condition
1670 codes, we need to insert a single NOP. */
1671 /* Itbl support may require additional care here. */
1672 if (mips_optimize == 0
1673 || (pinfo & INSN_READ_COND_CODE))
1677 /* If we're fixing up mfhi/mflo for the r7000 and the
1678 previous insn was an mfhi/mflo and the current insn
1679 reads the register that the mfhi/mflo wrote to, then
1682 else if (mips_7000_hilo_fix
1683 && MF_HILO_INSN (prev_pinfo)
1684 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1691 /* If we're fixing up mfhi/mflo for the r7000 and the
1692 2nd previous insn was an mfhi/mflo and the current insn
1693 reads the register that the mfhi/mflo wrote to, then
1696 else if (mips_7000_hilo_fix
1697 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1698 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1706 else if (prev_pinfo & INSN_READ_LO)
1708 /* The previous instruction reads the LO register; if the
1709 current instruction writes to the LO register, we must
1710 insert two NOPS. Some newer processors have interlocks.
1711 Also the tx39's multiply instructions can be exectuted
1712 immediatly after a read from HI/LO (without the delay),
1713 though the tx39's divide insns still do require the
1715 if (! (hilo_interlocks
1716 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1717 && (mips_optimize == 0
1718 || (pinfo & INSN_WRITE_LO)))
1720 /* Most mips16 branch insns don't have a delay slot.
1721 If a read from LO is immediately followed by a branch
1722 to a write to LO we have a read followed by a write
1723 less than 2 insns away. We assume the target of
1724 a branch might be a write to LO, and insert a nop
1725 between a read and an immediately following branch. */
1726 else if (mips_opts.mips16
1727 && (mips_optimize == 0
1728 || (pinfo & MIPS16_INSN_BRANCH)))
1731 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1733 /* The previous instruction reads the HI register; if the
1734 current instruction writes to the HI register, we must
1735 insert a NOP. Some newer processors have interlocks.
1736 Also the note tx39's multiply above. */
1737 if (! (hilo_interlocks
1738 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1739 && (mips_optimize == 0
1740 || (pinfo & INSN_WRITE_HI)))
1742 /* Most mips16 branch insns don't have a delay slot.
1743 If a read from HI is immediately followed by a branch
1744 to a write to HI we have a read followed by a write
1745 less than 2 insns away. We assume the target of
1746 a branch might be a write to HI, and insert a nop
1747 between a read and an immediately following branch. */
1748 else if (mips_opts.mips16
1749 && (mips_optimize == 0
1750 || (pinfo & MIPS16_INSN_BRANCH)))
1754 /* If the previous instruction was in a noreorder section, then
1755 we don't want to insert the nop after all. */
1756 /* Itbl support may require additional care here. */
1757 if (prev_insn_unreordered)
1760 /* There are two cases which require two intervening
1761 instructions: 1) setting the condition codes using a move to
1762 coprocessor instruction which requires a general coprocessor
1763 delay and then reading the condition codes 2) reading the HI
1764 or LO register and then writing to it (except on processors
1765 which have interlocks). If we are not already emitting a NOP
1766 instruction, we must check for these cases compared to the
1767 instruction previous to the previous instruction. */
1768 if ((! mips_opts.mips16
1769 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1770 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1771 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1772 && (pinfo & INSN_READ_COND_CODE)
1773 && ! cop_interlocks)
1774 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1775 && (pinfo & INSN_WRITE_LO)
1776 && ! (hilo_interlocks
1777 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1778 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1779 && (pinfo & INSN_WRITE_HI)
1780 && ! (hilo_interlocks
1781 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1786 if (prev_prev_insn_unreordered)
1789 if (prev_prev_nop && nops == 0)
1792 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1794 /* We're out of bits in pinfo, so we must resort to string
1795 ops here. Shortcuts are selected based on opcodes being
1796 limited to the VR4122 instruction set. */
1798 const char *pn = prev_insn.insn_mo->name;
1799 const char *tn = ip->insn_mo->name;
1800 if (strncmp(pn, "macc", 4) == 0
1801 || strncmp(pn, "dmacc", 5) == 0)
1803 /* Errata 21 - [D]DIV[U] after [D]MACC */
1804 if (strstr (tn, "div"))
1809 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1810 if (pn[0] == 'd' /* dmacc */
1811 && (strncmp(tn, "dmult", 5) == 0
1812 || strncmp(tn, "dmacc", 5) == 0))
1817 /* Errata 24 - MT{LO,HI} after [D]MACC */
1818 if (strcmp (tn, "mtlo") == 0
1819 || strcmp (tn, "mthi") == 0)
1825 else if (strncmp(pn, "dmult", 5) == 0
1826 && (strncmp(tn, "dmult", 5) == 0
1827 || strncmp(tn, "dmacc", 5) == 0))
1829 /* Here is the rest of errata 23. */
1832 if (nops < min_nops)
1836 /* If we are being given a nop instruction, don't bother with
1837 one of the nops we would otherwise output. This will only
1838 happen when a nop instruction is used with mips_optimize set
1841 && ! mips_opts.noreorder
1842 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1845 /* Now emit the right number of NOP instructions. */
1846 if (nops > 0 && ! mips_opts.noreorder)
1849 unsigned long old_frag_offset;
1851 struct insn_label_list *l;
1853 old_frag = frag_now;
1854 old_frag_offset = frag_now_fix ();
1856 for (i = 0; i < nops; i++)
1861 listing_prev_line ();
1862 /* We may be at the start of a variant frag. In case we
1863 are, make sure there is enough space for the frag
1864 after the frags created by listing_prev_line. The
1865 argument to frag_grow here must be at least as large
1866 as the argument to all other calls to frag_grow in
1867 this file. We don't have to worry about being in the
1868 middle of a variant frag, because the variants insert
1869 all needed nop instructions themselves. */
1873 for (l = insn_labels; l != NULL; l = l->next)
1877 assert (S_GET_SEGMENT (l->label) == now_seg);
1878 symbol_set_frag (l->label, frag_now);
1879 val = (valueT) frag_now_fix ();
1880 /* mips16 text labels are stored as odd. */
1881 if (mips_opts.mips16)
1883 S_SET_VALUE (l->label, val);
1886 #ifndef NO_ECOFF_DEBUGGING
1887 if (ECOFF_DEBUGGING)
1888 ecoff_fix_loc (old_frag, old_frag_offset);
1891 else if (prev_nop_frag != NULL)
1893 /* We have a frag holding nops we may be able to remove. If
1894 we don't need any nops, we can decrease the size of
1895 prev_nop_frag by the size of one instruction. If we do
1896 need some nops, we count them in prev_nops_required. */
1897 if (prev_nop_frag_since == 0)
1901 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1902 --prev_nop_frag_holds;
1905 prev_nop_frag_required += nops;
1909 if (prev_prev_nop == 0)
1911 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1912 --prev_nop_frag_holds;
1915 ++prev_nop_frag_required;
1918 if (prev_nop_frag_holds <= prev_nop_frag_required)
1919 prev_nop_frag = NULL;
1921 ++prev_nop_frag_since;
1923 /* Sanity check: by the time we reach the second instruction
1924 after prev_nop_frag, we should have used up all the nops
1925 one way or another. */
1926 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1932 && *reloc_type == BFD_RELOC_16_PCREL_S2
1933 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1934 || pinfo & INSN_COND_BRANCH_LIKELY)
1935 && mips_relax_branch
1936 /* Don't try branch relaxation within .set nomacro, or within
1937 .set noat if we use $at for PIC computations. If it turns
1938 out that the branch was out-of-range, we'll get an error. */
1939 && !mips_opts.warn_about_macros
1940 && !(mips_opts.noat && mips_pic != NO_PIC)
1941 && !mips_opts.mips16)
1943 f = frag_var (rs_machine_dependent,
1944 relaxed_branch_length
1946 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
1947 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
1949 (pinfo & INSN_UNCOND_BRANCH_DELAY,
1950 pinfo & INSN_COND_BRANCH_LIKELY,
1951 pinfo & INSN_WRITE_GPR_31,
1953 address_expr->X_add_symbol,
1954 address_expr->X_add_number,
1956 *reloc_type = BFD_RELOC_UNUSED;
1958 else if (*reloc_type > BFD_RELOC_UNUSED)
1960 /* We need to set up a variant frag. */
1961 assert (mips_opts.mips16 && address_expr != NULL);
1962 f = frag_var (rs_machine_dependent, 4, 0,
1963 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1964 mips16_small, mips16_ext,
1966 & INSN_UNCOND_BRANCH_DELAY),
1967 (*prev_insn_reloc_type
1968 == BFD_RELOC_MIPS16_JMP)),
1969 make_expr_symbol (address_expr), 0, NULL);
1971 else if (place != NULL)
1973 else if (mips_opts.mips16
1975 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1977 /* Make sure there is enough room to swap this instruction with
1978 a following jump instruction. */
1984 if (mips_opts.mips16
1985 && mips_opts.noreorder
1986 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1987 as_warn (_("extended instruction in delay slot"));
1992 fixp[0] = fixp[1] = fixp[2] = NULL;
1993 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1995 if (address_expr->X_op == O_constant)
1999 switch (*reloc_type)
2002 ip->insn_opcode |= address_expr->X_add_number;
2005 case BFD_RELOC_MIPS_HIGHEST:
2006 tmp = (address_expr->X_add_number
2007 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2009 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2012 case BFD_RELOC_MIPS_HIGHER:
2013 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2014 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2017 case BFD_RELOC_HI16_S:
2018 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2022 case BFD_RELOC_HI16:
2023 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2026 case BFD_RELOC_LO16:
2027 case BFD_RELOC_MIPS_GOT_DISP:
2028 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2031 case BFD_RELOC_MIPS_JMP:
2032 if ((address_expr->X_add_number & 3) != 0)
2033 as_bad (_("jump to misaligned address (0x%lx)"),
2034 (unsigned long) address_expr->X_add_number);
2035 if (address_expr->X_add_number & ~0xfffffff)
2036 as_bad (_("jump address range overflow (0x%lx)"),
2037 (unsigned long) address_expr->X_add_number);
2038 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2041 case BFD_RELOC_MIPS16_JMP:
2042 if ((address_expr->X_add_number & 3) != 0)
2043 as_bad (_("jump to misaligned address (0x%lx)"),
2044 (unsigned long) address_expr->X_add_number);
2045 if (address_expr->X_add_number & ~0xfffffff)
2046 as_bad (_("jump address range overflow (0x%lx)"),
2047 (unsigned long) address_expr->X_add_number);
2049 (((address_expr->X_add_number & 0x7c0000) << 3)
2050 | ((address_expr->X_add_number & 0xf800000) >> 7)
2051 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2054 case BFD_RELOC_16_PCREL_S2:
2064 /* Don't generate a reloc if we are writing into a variant frag. */
2067 reloc_howto_type *howto;
2070 /* In a compound relocation, it is the final (outermost)
2071 operator that determines the relocated field. */
2072 for (i = 1; i < 3; i++)
2073 if (reloc_type[i] == BFD_RELOC_UNUSED)
2076 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2077 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2078 bfd_get_reloc_size(howto),
2080 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2083 /* These relocations can have an addend that won't fit in
2084 4 octets for 64bit assembly. */
2086 && ! howto->partial_inplace
2087 && (reloc_type[0] == BFD_RELOC_16
2088 || reloc_type[0] == BFD_RELOC_32
2089 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2090 || reloc_type[0] == BFD_RELOC_HI16_S
2091 || reloc_type[0] == BFD_RELOC_LO16
2092 || reloc_type[0] == BFD_RELOC_GPREL16
2093 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2094 || reloc_type[0] == BFD_RELOC_GPREL32
2095 || reloc_type[0] == BFD_RELOC_64
2096 || reloc_type[0] == BFD_RELOC_CTOR
2097 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2098 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2099 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2100 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2101 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2102 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2103 fixp[0]->fx_no_overflow = 1;
2105 if (reloc_needs_lo_p (*reloc_type))
2107 struct mips_hi_fixup *hi_fixup;
2109 /* Reuse the last entry if it already has a matching %lo. */
2110 hi_fixup = mips_hi_fixup_list;
2112 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2114 hi_fixup = ((struct mips_hi_fixup *)
2115 xmalloc (sizeof (struct mips_hi_fixup)));
2116 hi_fixup->next = mips_hi_fixup_list;
2117 mips_hi_fixup_list = hi_fixup;
2119 hi_fixup->fixp = fixp[0];
2120 hi_fixup->seg = now_seg;
2123 /* Add fixups for the second and third relocations, if given.
2124 Note that the ABI allows the second relocation to be
2125 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2126 moment we only use RSS_UNDEF, but we could add support
2127 for the others if it ever becomes necessary. */
2128 for (i = 1; i < 3; i++)
2129 if (reloc_type[i] != BFD_RELOC_UNUSED)
2131 address_expr->X_op = O_absent;
2132 address_expr->X_add_symbol = 0;
2133 address_expr->X_add_number = 0;
2135 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2136 fixp[0]->fx_size, address_expr,
2137 FALSE, reloc_type[i]);
2143 if (! mips_opts.mips16)
2145 md_number_to_chars (f, ip->insn_opcode, 4);
2147 dwarf2_emit_insn (4);
2150 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2152 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2153 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2155 dwarf2_emit_insn (4);
2162 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2165 md_number_to_chars (f, ip->insn_opcode, 2);
2167 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2171 /* Update the register mask information. */
2172 if (! mips_opts.mips16)
2174 if (pinfo & INSN_WRITE_GPR_D)
2175 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2176 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2177 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2178 if (pinfo & INSN_READ_GPR_S)
2179 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2180 if (pinfo & INSN_WRITE_GPR_31)
2181 mips_gprmask |= 1 << RA;
2182 if (pinfo & INSN_WRITE_FPR_D)
2183 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2184 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2185 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2186 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2187 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2188 if ((pinfo & INSN_READ_FPR_R) != 0)
2189 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2190 if (pinfo & INSN_COP)
2192 /* We don't keep enough information to sort these cases out.
2193 The itbl support does keep this information however, although
2194 we currently don't support itbl fprmats as part of the cop
2195 instruction. May want to add this support in the future. */
2197 /* Never set the bit for $0, which is always zero. */
2198 mips_gprmask &= ~1 << 0;
2202 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2203 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2204 & MIPS16OP_MASK_RX);
2205 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2206 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2207 & MIPS16OP_MASK_RY);
2208 if (pinfo & MIPS16_INSN_WRITE_Z)
2209 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2210 & MIPS16OP_MASK_RZ);
2211 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2212 mips_gprmask |= 1 << TREG;
2213 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2214 mips_gprmask |= 1 << SP;
2215 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2216 mips_gprmask |= 1 << RA;
2217 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2218 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2219 if (pinfo & MIPS16_INSN_READ_Z)
2220 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2221 & MIPS16OP_MASK_MOVE32Z);
2222 if (pinfo & MIPS16_INSN_READ_GPR_X)
2223 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2224 & MIPS16OP_MASK_REGR32);
2227 if (place == NULL && ! mips_opts.noreorder)
2229 /* Filling the branch delay slot is more complex. We try to
2230 switch the branch with the previous instruction, which we can
2231 do if the previous instruction does not set up a condition
2232 that the branch tests and if the branch is not itself the
2233 target of any branch. */
2234 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2235 || (pinfo & INSN_COND_BRANCH_DELAY))
2237 if (mips_optimize < 2
2238 /* If we have seen .set volatile or .set nomove, don't
2240 || mips_opts.nomove != 0
2241 /* If we had to emit any NOP instructions, then we
2242 already know we can not swap. */
2244 /* If we don't even know the previous insn, we can not
2246 || ! prev_insn_valid
2247 /* If the previous insn is already in a branch delay
2248 slot, then we can not swap. */
2249 || prev_insn_is_delay_slot
2250 /* If the previous previous insn was in a .set
2251 noreorder, we can't swap. Actually, the MIPS
2252 assembler will swap in this situation. However, gcc
2253 configured -with-gnu-as will generate code like
2259 in which we can not swap the bne and INSN. If gcc is
2260 not configured -with-gnu-as, it does not output the
2261 .set pseudo-ops. We don't have to check
2262 prev_insn_unreordered, because prev_insn_valid will
2263 be 0 in that case. We don't want to use
2264 prev_prev_insn_valid, because we do want to be able
2265 to swap at the start of a function. */
2266 || prev_prev_insn_unreordered
2267 /* If the branch is itself the target of a branch, we
2268 can not swap. We cheat on this; all we check for is
2269 whether there is a label on this instruction. If
2270 there are any branches to anything other than a
2271 label, users must use .set noreorder. */
2272 || insn_labels != NULL
2273 /* If the previous instruction is in a variant frag, we
2274 can not do the swap. This does not apply to the
2275 mips16, which uses variant frags for different
2277 || (! mips_opts.mips16
2278 && prev_insn_frag->fr_type == rs_machine_dependent)
2279 /* If the branch reads the condition codes, we don't
2280 even try to swap, because in the sequence
2285 we can not swap, and I don't feel like handling that
2287 || (! mips_opts.mips16
2288 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2289 && (pinfo & INSN_READ_COND_CODE))
2290 /* We can not swap with an instruction that requires a
2291 delay slot, becase the target of the branch might
2292 interfere with that instruction. */
2293 || (! mips_opts.mips16
2294 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2296 /* Itbl support may require additional care here. */
2297 & (INSN_LOAD_COPROC_DELAY
2298 | INSN_COPROC_MOVE_DELAY
2299 | INSN_WRITE_COND_CODE)))
2300 || (! (hilo_interlocks
2301 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2305 || (! mips_opts.mips16
2307 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2308 || (! mips_opts.mips16
2309 && mips_opts.isa == ISA_MIPS1
2310 /* Itbl support may require additional care here. */
2311 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2312 /* We can not swap with a branch instruction. */
2314 & (INSN_UNCOND_BRANCH_DELAY
2315 | INSN_COND_BRANCH_DELAY
2316 | INSN_COND_BRANCH_LIKELY))
2317 /* We do not swap with a trap instruction, since it
2318 complicates trap handlers to have the trap
2319 instruction be in a delay slot. */
2320 || (prev_pinfo & INSN_TRAP)
2321 /* If the branch reads a register that the previous
2322 instruction sets, we can not swap. */
2323 || (! mips_opts.mips16
2324 && (prev_pinfo & INSN_WRITE_GPR_T)
2325 && insn_uses_reg (ip,
2326 ((prev_insn.insn_opcode >> OP_SH_RT)
2329 || (! mips_opts.mips16
2330 && (prev_pinfo & INSN_WRITE_GPR_D)
2331 && insn_uses_reg (ip,
2332 ((prev_insn.insn_opcode >> OP_SH_RD)
2335 || (mips_opts.mips16
2336 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2337 && insn_uses_reg (ip,
2338 ((prev_insn.insn_opcode
2340 & MIPS16OP_MASK_RX),
2342 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2343 && insn_uses_reg (ip,
2344 ((prev_insn.insn_opcode
2346 & MIPS16OP_MASK_RY),
2348 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2349 && insn_uses_reg (ip,
2350 ((prev_insn.insn_opcode
2352 & MIPS16OP_MASK_RZ),
2354 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2355 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2356 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2357 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2358 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2359 && insn_uses_reg (ip,
2360 MIPS16OP_EXTRACT_REG32R (prev_insn.
2363 /* If the branch writes a register that the previous
2364 instruction sets, we can not swap (we know that
2365 branches write only to RD or to $31). */
2366 || (! mips_opts.mips16
2367 && (prev_pinfo & INSN_WRITE_GPR_T)
2368 && (((pinfo & INSN_WRITE_GPR_D)
2369 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2370 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2371 || ((pinfo & INSN_WRITE_GPR_31)
2372 && (((prev_insn.insn_opcode >> OP_SH_RT)
2375 || (! mips_opts.mips16
2376 && (prev_pinfo & INSN_WRITE_GPR_D)
2377 && (((pinfo & INSN_WRITE_GPR_D)
2378 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2379 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2380 || ((pinfo & INSN_WRITE_GPR_31)
2381 && (((prev_insn.insn_opcode >> OP_SH_RD)
2384 || (mips_opts.mips16
2385 && (pinfo & MIPS16_INSN_WRITE_31)
2386 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2387 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2388 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2390 /* If the branch writes a register that the previous
2391 instruction reads, we can not swap (we know that
2392 branches only write to RD or to $31). */
2393 || (! mips_opts.mips16
2394 && (pinfo & INSN_WRITE_GPR_D)
2395 && insn_uses_reg (&prev_insn,
2396 ((ip->insn_opcode >> OP_SH_RD)
2399 || (! mips_opts.mips16
2400 && (pinfo & INSN_WRITE_GPR_31)
2401 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2402 || (mips_opts.mips16
2403 && (pinfo & MIPS16_INSN_WRITE_31)
2404 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2405 /* If we are generating embedded PIC code, the branch
2406 might be expanded into a sequence which uses $at, so
2407 we can't swap with an instruction which reads it. */
2408 || (mips_pic == EMBEDDED_PIC
2409 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2410 /* If the previous previous instruction has a load
2411 delay, and sets a register that the branch reads, we
2413 || (! mips_opts.mips16
2414 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2415 /* Itbl support may require additional care here. */
2416 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2417 || (! gpr_interlocks
2418 && (prev_prev_insn.insn_mo->pinfo
2419 & INSN_LOAD_MEMORY_DELAY)))
2420 && insn_uses_reg (ip,
2421 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2424 /* If one instruction sets a condition code and the
2425 other one uses a condition code, we can not swap. */
2426 || ((pinfo & INSN_READ_COND_CODE)
2427 && (prev_pinfo & INSN_WRITE_COND_CODE))
2428 || ((pinfo & INSN_WRITE_COND_CODE)
2429 && (prev_pinfo & INSN_READ_COND_CODE))
2430 /* If the previous instruction uses the PC, we can not
2432 || (mips_opts.mips16
2433 && (prev_pinfo & MIPS16_INSN_READ_PC))
2434 /* If the previous instruction was extended, we can not
2436 || (mips_opts.mips16 && prev_insn_extended)
2437 /* If the previous instruction had a fixup in mips16
2438 mode, we can not swap. This normally means that the
2439 previous instruction was a 4 byte branch anyhow. */
2440 || (mips_opts.mips16 && prev_insn_fixp[0])
2441 /* If the previous instruction is a sync, sync.l, or
2442 sync.p, we can not swap. */
2443 || (prev_pinfo & INSN_SYNC))
2445 /* We could do even better for unconditional branches to
2446 portions of this object file; we could pick up the
2447 instruction at the destination, put it in the delay
2448 slot, and bump the destination address. */
2450 /* Update the previous insn information. */
2451 prev_prev_insn = *ip;
2452 prev_insn.insn_mo = &dummy_opcode;
2456 /* It looks like we can actually do the swap. */
2457 if (! mips_opts.mips16)
2462 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2463 memcpy (temp, prev_f, 4);
2464 memcpy (prev_f, f, 4);
2465 memcpy (f, temp, 4);
2466 if (prev_insn_fixp[0])
2468 prev_insn_fixp[0]->fx_frag = frag_now;
2469 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2471 if (prev_insn_fixp[1])
2473 prev_insn_fixp[1]->fx_frag = frag_now;
2474 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2476 if (prev_insn_fixp[2])
2478 prev_insn_fixp[2]->fx_frag = frag_now;
2479 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2481 if (prev_insn_fixp[0] && HAVE_NEWABI
2482 && prev_insn_frag != frag_now
2483 && (prev_insn_fixp[0]->fx_r_type
2484 == BFD_RELOC_MIPS_GOT_DISP
2485 || (prev_insn_fixp[0]->fx_r_type
2486 == BFD_RELOC_MIPS_CALL16)))
2488 /* To avoid confusion in tc_gen_reloc, we must
2489 ensure that this does not become a variant
2491 force_new_frag = TRUE;
2495 fixp[0]->fx_frag = prev_insn_frag;
2496 fixp[0]->fx_where = prev_insn_where;
2500 fixp[1]->fx_frag = prev_insn_frag;
2501 fixp[1]->fx_where = prev_insn_where;
2505 fixp[2]->fx_frag = prev_insn_frag;
2506 fixp[2]->fx_where = prev_insn_where;
2514 assert (prev_insn_fixp[0] == NULL);
2515 assert (prev_insn_fixp[1] == NULL);
2516 assert (prev_insn_fixp[2] == NULL);
2517 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2518 memcpy (temp, prev_f, 2);
2519 memcpy (prev_f, f, 2);
2520 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2522 assert (*reloc_type == BFD_RELOC_UNUSED);
2523 memcpy (f, temp, 2);
2527 memcpy (f, f + 2, 2);
2528 memcpy (f + 2, temp, 2);
2532 fixp[0]->fx_frag = prev_insn_frag;
2533 fixp[0]->fx_where = prev_insn_where;
2537 fixp[1]->fx_frag = prev_insn_frag;
2538 fixp[1]->fx_where = prev_insn_where;
2542 fixp[2]->fx_frag = prev_insn_frag;
2543 fixp[2]->fx_where = prev_insn_where;
2547 /* Update the previous insn information; leave prev_insn
2549 prev_prev_insn = *ip;
2551 prev_insn_is_delay_slot = 1;
2553 /* If that was an unconditional branch, forget the previous
2554 insn information. */
2555 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2557 prev_prev_insn.insn_mo = &dummy_opcode;
2558 prev_insn.insn_mo = &dummy_opcode;
2561 prev_insn_fixp[0] = NULL;
2562 prev_insn_fixp[1] = NULL;
2563 prev_insn_fixp[2] = NULL;
2564 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2565 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2566 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2567 prev_insn_extended = 0;
2569 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2571 /* We don't yet optimize a branch likely. What we should do
2572 is look at the target, copy the instruction found there
2573 into the delay slot, and increment the branch to jump to
2574 the next instruction. */
2576 /* Update the previous insn information. */
2577 prev_prev_insn = *ip;
2578 prev_insn.insn_mo = &dummy_opcode;
2579 prev_insn_fixp[0] = NULL;
2580 prev_insn_fixp[1] = NULL;
2581 prev_insn_fixp[2] = NULL;
2582 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2583 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2584 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2585 prev_insn_extended = 0;
2589 /* Update the previous insn information. */
2591 prev_prev_insn.insn_mo = &dummy_opcode;
2593 prev_prev_insn = prev_insn;
2596 /* Any time we see a branch, we always fill the delay slot
2597 immediately; since this insn is not a branch, we know it
2598 is not in a delay slot. */
2599 prev_insn_is_delay_slot = 0;
2601 prev_insn_fixp[0] = fixp[0];
2602 prev_insn_fixp[1] = fixp[1];
2603 prev_insn_fixp[2] = fixp[2];
2604 prev_insn_reloc_type[0] = reloc_type[0];
2605 prev_insn_reloc_type[1] = reloc_type[1];
2606 prev_insn_reloc_type[2] = reloc_type[2];
2607 if (mips_opts.mips16)
2608 prev_insn_extended = (ip->use_extend
2609 || *reloc_type > BFD_RELOC_UNUSED);
2612 prev_prev_insn_unreordered = prev_insn_unreordered;
2613 prev_insn_unreordered = 0;
2614 prev_insn_frag = frag_now;
2615 prev_insn_where = f - frag_now->fr_literal;
2616 prev_insn_valid = 1;
2618 else if (place == NULL)
2620 /* We need to record a bit of information even when we are not
2621 reordering, in order to determine the base address for mips16
2622 PC relative relocs. */
2623 prev_prev_insn = prev_insn;
2625 prev_insn_reloc_type[0] = reloc_type[0];
2626 prev_insn_reloc_type[1] = reloc_type[1];
2627 prev_insn_reloc_type[2] = reloc_type[2];
2628 prev_prev_insn_unreordered = prev_insn_unreordered;
2629 prev_insn_unreordered = 1;
2632 /* We just output an insn, so the next one doesn't have a label. */
2633 mips_clear_insn_labels ();
2635 /* We must ensure that the frag to which an instruction that was
2636 moved from a non-variant frag doesn't become a variant frag,
2637 otherwise tc_gen_reloc may get confused. */
2640 frag_wane (frag_now);
2645 /* This function forgets that there was any previous instruction or
2646 label. If PRESERVE is non-zero, it remembers enough information to
2647 know whether nops are needed before a noreorder section. */
2650 mips_no_prev_insn (int preserve)
2654 prev_insn.insn_mo = &dummy_opcode;
2655 prev_prev_insn.insn_mo = &dummy_opcode;
2656 prev_nop_frag = NULL;
2657 prev_nop_frag_holds = 0;
2658 prev_nop_frag_required = 0;
2659 prev_nop_frag_since = 0;
2661 prev_insn_valid = 0;
2662 prev_insn_is_delay_slot = 0;
2663 prev_insn_unreordered = 0;
2664 prev_insn_extended = 0;
2665 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2666 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2667 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2668 prev_prev_insn_unreordered = 0;
2669 mips_clear_insn_labels ();
2672 /* This function must be called whenever we turn on noreorder or emit
2673 something other than instructions. It inserts any NOPS which might
2674 be needed by the previous instruction, and clears the information
2675 kept for the previous instructions. The INSNS parameter is true if
2676 instructions are to follow. */
2679 mips_emit_delays (bfd_boolean insns)
2681 if (! mips_opts.noreorder)
2686 if ((! mips_opts.mips16
2687 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2688 && (! cop_interlocks
2689 && (prev_insn.insn_mo->pinfo
2690 & (INSN_LOAD_COPROC_DELAY
2691 | INSN_COPROC_MOVE_DELAY
2692 | INSN_WRITE_COND_CODE))))
2693 || (! hilo_interlocks
2694 && (prev_insn.insn_mo->pinfo
2697 || (! mips_opts.mips16
2699 && (prev_insn.insn_mo->pinfo
2700 & INSN_LOAD_MEMORY_DELAY))
2701 || (! mips_opts.mips16
2702 && mips_opts.isa == ISA_MIPS1
2703 && (prev_insn.insn_mo->pinfo
2704 & INSN_COPROC_MEMORY_DELAY)))
2706 /* Itbl support may require additional care here. */
2708 if ((! mips_opts.mips16
2709 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2710 && (! cop_interlocks
2711 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2712 || (! hilo_interlocks
2713 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2714 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2717 if (prev_insn_unreordered)
2720 else if ((! mips_opts.mips16
2721 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2722 && (! cop_interlocks
2723 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2724 || (! hilo_interlocks
2725 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2726 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2728 /* Itbl support may require additional care here. */
2729 if (! prev_prev_insn_unreordered)
2733 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2736 const char *pn = prev_insn.insn_mo->name;
2737 if (strncmp(pn, "macc", 4) == 0
2738 || strncmp(pn, "dmacc", 5) == 0
2739 || strncmp(pn, "dmult", 5) == 0)
2743 if (nops < min_nops)
2749 struct insn_label_list *l;
2753 /* Record the frag which holds the nop instructions, so
2754 that we can remove them if we don't need them. */
2755 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2756 prev_nop_frag = frag_now;
2757 prev_nop_frag_holds = nops;
2758 prev_nop_frag_required = 0;
2759 prev_nop_frag_since = 0;
2762 for (; nops > 0; --nops)
2767 /* Move on to a new frag, so that it is safe to simply
2768 decrease the size of prev_nop_frag. */
2769 frag_wane (frag_now);
2773 for (l = insn_labels; l != NULL; l = l->next)
2777 assert (S_GET_SEGMENT (l->label) == now_seg);
2778 symbol_set_frag (l->label, frag_now);
2779 val = (valueT) frag_now_fix ();
2780 /* mips16 text labels are stored as odd. */
2781 if (mips_opts.mips16)
2783 S_SET_VALUE (l->label, val);
2788 /* Mark instruction labels in mips16 mode. */
2790 mips16_mark_labels ();
2792 mips_no_prev_insn (insns);
2795 /* Build an instruction created by a macro expansion. This is passed
2796 a pointer to the count of instructions created so far, an
2797 expression, the name of the instruction to build, an operand format
2798 string, and corresponding arguments. */
2801 macro_build (char *place, int *counter, expressionS *ep, const char *name,
2802 const char *fmt, ...)
2804 struct mips_cl_insn insn;
2805 bfd_reloc_code_real_type r[3];
2808 va_start (args, fmt);
2811 * If the macro is about to expand into a second instruction,
2812 * print a warning if needed. We need to pass ip as a parameter
2813 * to generate a better warning message here...
2815 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2816 as_warn (_("Macro instruction expanded into multiple instructions"));
2819 * If the macro is about to expand into a second instruction,
2820 * and it is in a delay slot, print a warning.
2824 && mips_opts.noreorder
2825 && (prev_prev_insn.insn_mo->pinfo
2826 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2827 | INSN_COND_BRANCH_LIKELY)) != 0)
2828 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2831 ++*counter; /* bump instruction counter */
2833 if (mips_opts.mips16)
2835 mips16_macro_build (place, counter, ep, name, fmt, args);
2840 r[0] = BFD_RELOC_UNUSED;
2841 r[1] = BFD_RELOC_UNUSED;
2842 r[2] = BFD_RELOC_UNUSED;
2843 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2844 assert (insn.insn_mo);
2845 assert (strcmp (name, insn.insn_mo->name) == 0);
2847 /* Search until we get a match for NAME. */
2850 /* It is assumed here that macros will never generate
2851 MDMX or MIPS-3D instructions. */
2852 if (strcmp (fmt, insn.insn_mo->args) == 0
2853 && insn.insn_mo->pinfo != INSN_MACRO
2854 && OPCODE_IS_MEMBER (insn.insn_mo,
2856 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2858 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2862 assert (insn.insn_mo->name);
2863 assert (strcmp (name, insn.insn_mo->name) == 0);
2866 insn.insn_opcode = insn.insn_mo->match;
2884 insn.insn_opcode |= (va_arg (args, int)
2885 & OP_MASK_SHAMT) << OP_SH_SHAMT;
2890 /* Note that in the macro case, these arguments are already
2891 in MSB form. (When handling the instruction in the
2892 non-macro case, these arguments are sizes from which
2893 MSB values must be calculated.) */
2894 insn.insn_opcode |= (va_arg (args, int)
2895 & OP_MASK_INSMSB) << OP_SH_INSMSB;
2901 /* Note that in the macro case, these arguments are already
2902 in MSBD form. (When handling the instruction in the
2903 non-macro case, these arguments are sizes from which
2904 MSBD values must be calculated.) */
2905 insn.insn_opcode |= (va_arg (args, int)
2906 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
2917 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2921 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2926 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2932 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2937 int tmp = va_arg (args, int);
2939 insn.insn_opcode |= tmp << OP_SH_RT;
2940 insn.insn_opcode |= tmp << OP_SH_RD;
2946 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2953 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2957 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2961 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2965 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2969 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2976 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2982 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2983 assert (*r == BFD_RELOC_GPREL16
2984 || *r == BFD_RELOC_MIPS_LITERAL
2985 || *r == BFD_RELOC_MIPS_HIGHER
2986 || *r == BFD_RELOC_HI16_S
2987 || *r == BFD_RELOC_LO16
2988 || *r == BFD_RELOC_MIPS_GOT16
2989 || *r == BFD_RELOC_MIPS_CALL16
2990 || *r == BFD_RELOC_MIPS_GOT_DISP
2991 || *r == BFD_RELOC_MIPS_GOT_PAGE
2992 || *r == BFD_RELOC_MIPS_GOT_OFST
2993 || *r == BFD_RELOC_MIPS_GOT_LO16
2994 || *r == BFD_RELOC_MIPS_CALL_LO16
2995 || (ep->X_op == O_subtract
2996 && *r == BFD_RELOC_PCREL_LO16));
3000 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3002 && (ep->X_op == O_constant
3003 || (ep->X_op == O_symbol
3004 && (*r == BFD_RELOC_MIPS_HIGHEST
3005 || *r == BFD_RELOC_HI16_S
3006 || *r == BFD_RELOC_HI16
3007 || *r == BFD_RELOC_GPREL16
3008 || *r == BFD_RELOC_MIPS_GOT_HI16
3009 || *r == BFD_RELOC_MIPS_CALL_HI16))
3010 || (ep->X_op == O_subtract
3011 && *r == BFD_RELOC_PCREL_HI16_S)));
3015 assert (ep != NULL);
3017 * This allows macro() to pass an immediate expression for
3018 * creating short branches without creating a symbol.
3019 * Note that the expression still might come from the assembly
3020 * input, in which case the value is not checked for range nor
3021 * is a relocation entry generated (yuck).
3023 if (ep->X_op == O_constant)
3025 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3029 *r = BFD_RELOC_16_PCREL_S2;
3033 assert (ep != NULL);
3034 *r = BFD_RELOC_MIPS_JMP;
3038 insn.insn_opcode |= va_arg (args, unsigned long);
3047 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3049 append_insn (place, &insn, ep, r);
3053 mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED,
3054 expressionS *ep, const char *name, const char *fmt,
3057 struct mips_cl_insn insn;
3058 bfd_reloc_code_real_type r[3]
3059 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3061 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3062 assert (insn.insn_mo);
3063 assert (strcmp (name, insn.insn_mo->name) == 0);
3065 while (strcmp (fmt, insn.insn_mo->args) != 0
3066 || insn.insn_mo->pinfo == INSN_MACRO)
3069 assert (insn.insn_mo->name);
3070 assert (strcmp (name, insn.insn_mo->name) == 0);
3073 insn.insn_opcode = insn.insn_mo->match;
3074 insn.use_extend = FALSE;
3093 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3098 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3102 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3106 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3116 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3123 regno = va_arg (args, int);
3124 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3125 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3146 assert (ep != NULL);
3148 if (ep->X_op != O_constant)
3149 *r = (int) BFD_RELOC_UNUSED + c;
3152 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3153 FALSE, &insn.insn_opcode, &insn.use_extend,
3156 *r = BFD_RELOC_UNUSED;
3162 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3169 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3171 append_insn (place, &insn, ep, r);
3175 * Generate a "jalr" instruction with a relocation hint to the called
3176 * function. This occurs in NewABI PIC code.
3179 macro_build_jalr (int icnt, expressionS *ep)
3188 macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3190 fix_new_exp (frag_now, f - frag_now->fr_literal,
3191 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3195 * Generate a "lui" instruction.
3198 macro_build_lui (char *place, int *counter, expressionS *ep, int regnum)
3200 expressionS high_expr;
3201 struct mips_cl_insn insn;
3202 bfd_reloc_code_real_type r[3]
3203 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3204 const char *name = "lui";
3205 const char *fmt = "t,u";
3207 assert (! mips_opts.mips16);
3213 high_expr.X_op = O_constant;
3214 high_expr.X_add_number = ep->X_add_number;
3217 if (high_expr.X_op == O_constant)
3219 /* we can compute the instruction now without a relocation entry */
3220 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3222 *r = BFD_RELOC_UNUSED;
3226 assert (ep->X_op == O_symbol);
3227 /* _gp_disp is a special case, used from s_cpload. */
3228 assert (mips_pic == NO_PIC
3230 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3231 *r = BFD_RELOC_HI16_S;
3235 * If the macro is about to expand into a second instruction,
3236 * print a warning if needed. We need to pass ip as a parameter
3237 * to generate a better warning message here...
3239 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3240 as_warn (_("Macro instruction expanded into multiple instructions"));
3243 ++*counter; /* bump instruction counter */
3245 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3246 assert (insn.insn_mo);
3247 assert (strcmp (name, insn.insn_mo->name) == 0);
3248 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3250 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3251 if (*r == BFD_RELOC_UNUSED)
3253 insn.insn_opcode |= high_expr.X_add_number;
3254 append_insn (place, &insn, NULL, r);
3257 append_insn (place, &insn, &high_expr, r);
3260 /* Generate a sequence of instructions to do a load or store from a constant
3261 offset off of a base register (breg) into/from a target register (treg),
3262 using AT if necessary. */
3264 macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
3265 const char *op, int treg, int breg, int dbl)
3267 assert (ep->X_op == O_constant);
3269 /* Sign-extending 32-bit constants makes their handling easier. */
3272 if (ep->X_add_number & ~((bfd_vma) 0x7fffffff)
3273 && ~(ep->X_add_number | 0x7fffffff))
3274 as_bad (_("too large constant specified"));
3276 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3280 /* Right now, this routine can only handle signed 32-bit contants. */
3281 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3282 as_warn (_("operand overflow"));
3284 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3286 /* Signed 16-bit offset will fit in the op. Easy! */
3287 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3292 /* 32-bit offset, need multiple instructions and AT, like:
3293 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3294 addu $tempreg,$tempreg,$breg
3295 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3296 to handle the complete offset. */
3297 macro_build_lui (place, counter, ep, AT);
3300 macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
3304 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3308 as_warn (_("Macro used $at after \".set noat\""));
3313 * Generates code to set the $at register to true (one)
3314 * if reg is less than the immediate expression.
3317 set_at (int *counter, int reg, int unsignedp)
3319 if (imm_expr.X_op == O_constant
3320 && imm_expr.X_add_number >= -0x8000
3321 && imm_expr.X_add_number < 0x8000)
3322 macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
3323 "t,r,j", AT, reg, BFD_RELOC_LO16);
3326 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3327 macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
3328 "d,v,t", AT, reg, AT);
3332 /* Warn if an expression is not a constant. */
3335 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3337 if (ex->X_op == O_big)
3338 as_bad (_("unsupported large constant"));
3339 else if (ex->X_op != O_constant)
3340 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3343 /* Count the leading zeroes by performing a binary chop. This is a
3344 bulky bit of source, but performance is a LOT better for the
3345 majority of values than a simple loop to count the bits:
3346 for (lcnt = 0; (lcnt < 32); lcnt++)
3347 if ((v) & (1 << (31 - lcnt)))
3349 However it is not code size friendly, and the gain will drop a bit
3350 on certain cached systems.
3352 #define COUNT_TOP_ZEROES(v) \
3353 (((v) & ~0xffff) == 0 \
3354 ? ((v) & ~0xff) == 0 \
3355 ? ((v) & ~0xf) == 0 \
3356 ? ((v) & ~0x3) == 0 \
3357 ? ((v) & ~0x1) == 0 \
3362 : ((v) & ~0x7) == 0 \
3365 : ((v) & ~0x3f) == 0 \
3366 ? ((v) & ~0x1f) == 0 \
3369 : ((v) & ~0x7f) == 0 \
3372 : ((v) & ~0xfff) == 0 \
3373 ? ((v) & ~0x3ff) == 0 \
3374 ? ((v) & ~0x1ff) == 0 \
3377 : ((v) & ~0x7ff) == 0 \
3380 : ((v) & ~0x3fff) == 0 \
3381 ? ((v) & ~0x1fff) == 0 \
3384 : ((v) & ~0x7fff) == 0 \
3387 : ((v) & ~0xffffff) == 0 \
3388 ? ((v) & ~0xfffff) == 0 \
3389 ? ((v) & ~0x3ffff) == 0 \
3390 ? ((v) & ~0x1ffff) == 0 \
3393 : ((v) & ~0x7ffff) == 0 \
3396 : ((v) & ~0x3fffff) == 0 \
3397 ? ((v) & ~0x1fffff) == 0 \
3400 : ((v) & ~0x7fffff) == 0 \
3403 : ((v) & ~0xfffffff) == 0 \
3404 ? ((v) & ~0x3ffffff) == 0 \
3405 ? ((v) & ~0x1ffffff) == 0 \
3408 : ((v) & ~0x7ffffff) == 0 \
3411 : ((v) & ~0x3fffffff) == 0 \
3412 ? ((v) & ~0x1fffffff) == 0 \
3415 : ((v) & ~0x7fffffff) == 0 \
3420 * This routine generates the least number of instructions neccessary to load
3421 * an absolute expression value into a register.
3424 load_register (int *counter, int reg, expressionS *ep, int dbl)
3427 expressionS hi32, lo32;
3429 if (ep->X_op != O_big)
3431 assert (ep->X_op == O_constant);
3433 /* Sign-extending 32-bit constants makes their handling easier. */
3436 if (ep->X_add_number & ~((bfd_vma) 0x7fffffff)
3437 && ~(ep->X_add_number | 0x7fffffff))
3438 as_bad (_("too large constant specified"));
3440 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3444 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3446 /* We can handle 16 bit signed values with an addiu to
3447 $zero. No need to ever use daddiu here, since $zero and
3448 the result are always correct in 32 bit mode. */
3449 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3453 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3455 /* We can handle 16 bit unsigned values with an ori to
3457 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
3461 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3463 /* 32 bit values require an lui. */
3464 macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3465 if ((ep->X_add_number & 0xffff) != 0)
3466 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
3472 /* The value is larger than 32 bits. */
3474 if (HAVE_32BIT_GPRS)
3476 as_bad (_("Number (0x%lx) larger than 32 bits"),
3477 (unsigned long) ep->X_add_number);
3478 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3483 if (ep->X_op != O_big)
3486 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3487 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3488 hi32.X_add_number &= 0xffffffff;
3490 lo32.X_add_number &= 0xffffffff;
3494 assert (ep->X_add_number > 2);
3495 if (ep->X_add_number == 3)
3496 generic_bignum[3] = 0;
3497 else if (ep->X_add_number > 4)
3498 as_bad (_("Number larger than 64 bits"));
3499 lo32.X_op = O_constant;
3500 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3501 hi32.X_op = O_constant;
3502 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3505 if (hi32.X_add_number == 0)
3510 unsigned long hi, lo;
3512 if (hi32.X_add_number == (offsetT) 0xffffffff)
3514 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3516 macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
3520 if (lo32.X_add_number & 0x80000000)
3522 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3524 if (lo32.X_add_number & 0xffff)
3525 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
3531 /* Check for 16bit shifted constant. We know that hi32 is
3532 non-zero, so start the mask on the first bit of the hi32
3537 unsigned long himask, lomask;
3541 himask = 0xffff >> (32 - shift);
3542 lomask = (0xffff << shift) & 0xffffffff;
3546 himask = 0xffff << (shift - 32);
3549 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3550 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3554 tmp.X_op = O_constant;
3556 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3557 | (lo32.X_add_number >> shift));
3559 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3560 macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
3562 macro_build (NULL, counter, NULL,
3563 (shift >= 32) ? "dsll32" : "dsll",
3565 (shift >= 32) ? shift - 32 : shift);
3570 while (shift <= (64 - 16));
3572 /* Find the bit number of the lowest one bit, and store the
3573 shifted value in hi/lo. */
3574 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3575 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3579 while ((lo & 1) == 0)
3584 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3590 while ((hi & 1) == 0)
3599 /* Optimize if the shifted value is a (power of 2) - 1. */
3600 if ((hi == 0 && ((lo + 1) & lo) == 0)
3601 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3603 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3608 /* This instruction will set the register to be all
3610 tmp.X_op = O_constant;
3611 tmp.X_add_number = (offsetT) -1;
3612 macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
3617 macro_build (NULL, counter, NULL,
3618 (bit >= 32) ? "dsll32" : "dsll",
3620 (bit >= 32) ? bit - 32 : bit);
3622 macro_build (NULL, counter, NULL,
3623 (shift >= 32) ? "dsrl32" : "dsrl",
3625 (shift >= 32) ? shift - 32 : shift);
3630 /* Sign extend hi32 before calling load_register, because we can
3631 generally get better code when we load a sign extended value. */
3632 if ((hi32.X_add_number & 0x80000000) != 0)
3633 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3634 load_register (counter, reg, &hi32, 0);
3637 if ((lo32.X_add_number & 0xffff0000) == 0)
3641 macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
3649 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3651 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3653 macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
3659 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
3663 mid16.X_add_number >>= 16;
3664 macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
3666 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3669 if ((lo32.X_add_number & 0xffff) != 0)
3670 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3674 /* Load an address into a register. */
3677 load_address (int *counter, int reg, expressionS *ep, int *used_at)
3681 if (ep->X_op != O_constant
3682 && ep->X_op != O_symbol)
3684 as_bad (_("expression too complex"));
3685 ep->X_op = O_constant;
3688 if (ep->X_op == O_constant)
3690 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3694 if (mips_pic == NO_PIC)
3696 /* If this is a reference to a GP relative symbol, we want
3697 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3699 lui $reg,<sym> (BFD_RELOC_HI16_S)
3700 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3701 If we have an addend, we always use the latter form.
3703 With 64bit address space and a usable $at we want
3704 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3705 lui $at,<sym> (BFD_RELOC_HI16_S)
3706 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3707 daddiu $at,<sym> (BFD_RELOC_LO16)
3711 If $at is already in use, we use a path which is suboptimal
3712 on superscalar processors.
3713 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3714 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3716 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3718 daddiu $reg,<sym> (BFD_RELOC_LO16)
3720 if (HAVE_64BIT_ADDRESSES)
3722 /* We don't do GP optimization for now because RELAX_ENCODE can't
3723 hold the data for such large chunks. */
3725 if (*used_at == 0 && ! mips_opts.noat)
3727 macro_build (p, counter, ep, "lui", "t,u",
3728 reg, BFD_RELOC_MIPS_HIGHEST);
3729 macro_build (p, counter, ep, "lui", "t,u",
3730 AT, BFD_RELOC_HI16_S);
3731 macro_build (p, counter, ep, "daddiu", "t,r,j",
3732 reg, reg, BFD_RELOC_MIPS_HIGHER);
3733 macro_build (p, counter, ep, "daddiu", "t,r,j",
3734 AT, AT, BFD_RELOC_LO16);
3735 macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
3736 macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
3741 macro_build (p, counter, ep, "lui", "t,u",
3742 reg, BFD_RELOC_MIPS_HIGHEST);
3743 macro_build (p, counter, ep, "daddiu", "t,r,j",
3744 reg, reg, BFD_RELOC_MIPS_HIGHER);
3745 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3746 macro_build (p, counter, ep, "daddiu", "t,r,j",
3747 reg, reg, BFD_RELOC_HI16_S);
3748 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3749 macro_build (p, counter, ep, "daddiu", "t,r,j",
3750 reg, reg, BFD_RELOC_LO16);
3755 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3756 && ! nopic_need_relax (ep->X_add_symbol, 1))
3759 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3760 mips_gp_register, BFD_RELOC_GPREL16);
3761 p = frag_var (rs_machine_dependent, 8, 0,
3762 RELAX_ENCODE (4, 8, 0, 4, 0,
3763 mips_opts.warn_about_macros),
3764 ep->X_add_symbol, 0, NULL);
3766 macro_build_lui (p, counter, ep, reg);
3769 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3773 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3777 /* If this is a reference to an external symbol, we want
3778 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3780 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3782 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3783 If there is a constant, it must be added in after.
3785 If we have NewABI, we want
3786 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3787 unless we're referencing a global symbol with a non-zero
3788 offset, in which case cst must be added separately. */
3793 if (ep->X_add_number)
3795 frag_now->tc_frag_data.tc_fr_offset =
3796 ex.X_add_number = ep->X_add_number;
3797 ep->X_add_number = 0;
3798 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
3799 reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3800 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3801 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3802 ex.X_op = O_constant;
3803 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3804 reg, reg, BFD_RELOC_LO16);
3805 p = frag_var (rs_machine_dependent, 8, 0,
3806 RELAX_ENCODE (8, 4, 0, 0, 0,
3807 mips_opts.warn_about_macros),
3808 ep->X_add_symbol, 0, NULL);
3809 ep->X_add_number = ex.X_add_number;
3812 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3813 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3817 /* To avoid confusion in tc_gen_reloc, we must ensure
3818 that this does not become a variant frag. */
3819 frag_wane (frag_now);
3825 ex.X_add_number = ep->X_add_number;
3826 ep->X_add_number = 0;
3828 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3829 BFD_RELOC_MIPS_GOT16,
3831 macro_build (NULL, counter, NULL, "nop", "");
3832 p = frag_var (rs_machine_dependent, 4, 0,
3833 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3834 ep->X_add_symbol, 0, NULL);
3835 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3838 if (ex.X_add_number != 0)
3840 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3841 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3842 ex.X_op = O_constant;
3843 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3844 reg, reg, BFD_RELOC_LO16);
3848 else if (mips_pic == SVR4_PIC)
3853 /* This is the large GOT case. If this is a reference to an
3854 external symbol, we want
3855 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3857 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3859 Otherwise, for a reference to a local symbol in old ABI, we want
3860 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3862 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3863 If there is a constant, it must be added in after.
3865 In the NewABI, for local symbols, with or without offsets, we want:
3866 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3867 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3873 frag_now->tc_frag_data.tc_fr_offset =
3874 ex.X_add_number = ep->X_add_number;
3875 ep->X_add_number = 0;
3876 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3877 BFD_RELOC_MIPS_GOT_HI16);
3878 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3879 reg, mips_gp_register);
3880 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3881 BFD_RELOC_MIPS_GOT_LO16, reg);
3882 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3883 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3884 else if (ex.X_add_number)
3886 ex.X_op = O_constant;
3887 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3888 reg, reg, BFD_RELOC_LO16);
3891 ep->X_add_number = ex.X_add_number;
3892 p = frag_var (rs_machine_dependent, 8, 0,
3893 RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0,
3894 mips_opts.warn_about_macros),
3895 ep->X_add_symbol, 0, NULL);
3896 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3897 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3898 macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3899 reg, BFD_RELOC_MIPS_GOT_OFST);
3903 ex.X_add_number = ep->X_add_number;
3904 ep->X_add_number = 0;
3905 if (reg_needs_delay (mips_gp_register))
3910 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3911 BFD_RELOC_MIPS_GOT_HI16);
3912 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3913 reg, mips_gp_register);
3914 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3915 BFD_RELOC_MIPS_GOT_LO16, reg);
3916 p = frag_var (rs_machine_dependent, 12 + off, 0,
3917 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3918 mips_opts.warn_about_macros),
3919 ep->X_add_symbol, 0, NULL);
3922 /* We need a nop before loading from $gp. This special
3923 check is required because the lui which starts the main
3924 instruction stream does not refer to $gp, and so will not
3925 insert the nop which may be required. */
3926 macro_build (p, counter, NULL, "nop", "");
3929 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3930 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3932 macro_build (p, counter, NULL, "nop", "");
3934 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3937 if (ex.X_add_number != 0)
3939 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3940 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3941 ex.X_op = O_constant;
3942 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3943 reg, reg, BFD_RELOC_LO16);
3947 else if (mips_pic == EMBEDDED_PIC)
3950 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3952 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3953 mips_gp_register, BFD_RELOC_GPREL16);
3959 /* Move the contents of register SOURCE into register DEST. */
3962 move_register (int *counter, int dest, int source)
3964 macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
3965 "d,v,t", dest, source, 0);
3970 * This routine implements the seemingly endless macro or synthesized
3971 * instructions and addressing modes in the mips assembly language. Many
3972 * of these macros are simple and are similar to each other. These could
3973 * probably be handled by some kind of table or grammer aproach instead of
3974 * this verbose method. Others are not simple macros but are more like
3975 * optimizing code generation.
3976 * One interesting optimization is when several store macros appear
3977 * consecutivly that would load AT with the upper half of the same address.
3978 * The ensuing load upper instructions are ommited. This implies some kind
3979 * of global optimization. We currently only optimize within a single macro.
3980 * For many of the load and store macros if the address is specified as a
3981 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3982 * first load register 'at' with zero and use it as the base register. The
3983 * mips assembler simply uses register $zero. Just one tiny optimization
3987 macro (struct mips_cl_insn *ip)
3989 register int treg, sreg, dreg, breg;
4005 bfd_reloc_code_real_type r;
4006 int hold_mips_optimize;
4008 assert (! mips_opts.mips16);
4010 treg = (ip->insn_opcode >> 16) & 0x1f;
4011 dreg = (ip->insn_opcode >> 11) & 0x1f;
4012 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4013 mask = ip->insn_mo->mask;
4015 expr1.X_op = O_constant;
4016 expr1.X_op_symbol = NULL;
4017 expr1.X_add_symbol = NULL;
4018 expr1.X_add_number = 1;
4020 /* Umatched fixups should not be put in the same frag as a relaxable
4021 macro. For example, suppose we have:
4025 addiu $4,$4,%lo(l1) # 3
4027 If instructions 1 and 2 were put in the same frag, md_frob_file would
4028 move the fixup for #1 after the fixups for the "unrelaxed" version of
4029 #2. This would confuse tc_gen_reloc, which expects the relocations
4030 for #2 to be the last for that frag.
4032 Also, if tc_gen_reloc sees certain relocations in a variant frag,
4033 it assumes that they belong to a relaxable macro. We mustn't put
4034 other uses of such relocations into a variant frag.
4036 To avoid both problems, finish the current frag it contains a
4037 %reloc() operator. The macro then goes into a new frag. */
4038 if (prev_reloc_op_frag == frag_now)
4040 frag_wane (frag_now);
4054 mips_emit_delays (TRUE);
4055 ++mips_opts.noreorder;
4056 mips_any_noreorder = 1;
4058 expr1.X_add_number = 8;
4059 macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4061 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4063 move_register (&icnt, dreg, sreg);
4064 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
4067 --mips_opts.noreorder;
4088 if (imm_expr.X_op == O_constant
4089 && imm_expr.X_add_number >= -0x8000
4090 && imm_expr.X_add_number < 0x8000)
4092 macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4096 load_register (&icnt, AT, &imm_expr, dbl);
4097 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4116 if (imm_expr.X_op == O_constant
4117 && imm_expr.X_add_number >= 0
4118 && imm_expr.X_add_number < 0x10000)
4120 if (mask != M_NOR_I)
4121 macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
4125 macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
4127 macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
4132 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4133 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4150 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4152 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
4155 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4156 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4164 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4170 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4174 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4175 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4182 /* check for > max integer */
4183 maxnum = 0x7fffffff;
4184 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4191 if (imm_expr.X_op == O_constant
4192 && imm_expr.X_add_number >= maxnum
4193 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4196 /* result is always false */
4200 as_warn (_("Branch %s is always false (nop)"),
4202 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4207 as_warn (_("Branch likely %s is always false"),
4209 macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
4213 if (imm_expr.X_op != O_constant)
4214 as_bad (_("Unsupported large constant"));
4215 ++imm_expr.X_add_number;
4219 if (mask == M_BGEL_I)
4221 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4223 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4227 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4229 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4233 maxnum = 0x7fffffff;
4234 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4241 maxnum = - maxnum - 1;
4242 if (imm_expr.X_op == O_constant
4243 && imm_expr.X_add_number <= maxnum
4244 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4247 /* result is always true */
4248 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4249 macro_build (NULL, &icnt, &offset_expr, "b", "p");
4252 set_at (&icnt, sreg, 0);
4253 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4264 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4268 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4269 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4278 && imm_expr.X_op == O_constant
4279 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4281 if (imm_expr.X_op != O_constant)
4282 as_bad (_("Unsupported large constant"));
4283 ++imm_expr.X_add_number;
4287 if (mask == M_BGEUL_I)
4289 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4291 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4293 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4297 set_at (&icnt, sreg, 1);
4298 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4307 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4313 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4317 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4318 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4327 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4333 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4334 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4343 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4349 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4353 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4354 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4361 maxnum = 0x7fffffff;
4362 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4369 if (imm_expr.X_op == O_constant
4370 && imm_expr.X_add_number >= maxnum
4371 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4373 if (imm_expr.X_op != O_constant)
4374 as_bad (_("Unsupported large constant"));
4375 ++imm_expr.X_add_number;
4379 if (mask == M_BLTL_I)
4381 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4383 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4387 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4389 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4393 set_at (&icnt, sreg, 0);
4394 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4403 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4409 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4410 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4419 && imm_expr.X_op == O_constant
4420 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4422 if (imm_expr.X_op != O_constant)
4423 as_bad (_("Unsupported large constant"));
4424 ++imm_expr.X_add_number;
4428 if (mask == M_BLTUL_I)
4430 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4432 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4434 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4438 set_at (&icnt, sreg, 1);
4439 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4448 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4454 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4458 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4459 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4470 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4474 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4475 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4484 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4486 as_bad (_("Unsupported large constant"));
4491 pos = (unsigned long) imm_expr.X_add_number;
4492 size = (unsigned long) imm2_expr.X_add_number;
4497 as_bad (_("Improper position (%lu)"), pos);
4500 if (size == 0 || size > 64
4501 || (pos + size - 1) > 63)
4503 as_bad (_("Improper extract size (%lu, position %lu)"),
4508 if (size <= 32 && pos < 32)
4513 else if (size <= 32)
4523 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4524 fmt, treg, sreg, pos, size - 1);
4533 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4535 as_bad (_("Unsupported large constant"));
4540 pos = (unsigned long) imm_expr.X_add_number;
4541 size = (unsigned long) imm2_expr.X_add_number;
4546 as_bad (_("Improper position (%lu)"), pos);
4549 if (size == 0 || size > 64
4550 || (pos + size - 1) > 63)
4552 as_bad (_("Improper insert size (%lu, position %lu)"),
4557 if (pos < 32 && (pos + size - 1) < 32)
4572 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4573 fmt, treg, sreg, pos, pos + size - 1);
4589 as_warn (_("Divide by zero."));
4591 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4593 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4597 mips_emit_delays (TRUE);
4598 ++mips_opts.noreorder;
4599 mips_any_noreorder = 1;
4602 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4603 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4608 expr1.X_add_number = 8;
4609 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4610 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4612 macro_build (NULL, &icnt,NULL, "break", "c", 7);
4614 expr1.X_add_number = -1;
4615 macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
4616 AT, 0, BFD_RELOC_LO16);
4617 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4618 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4621 expr1.X_add_number = 1;
4622 macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4624 macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
4628 expr1.X_add_number = 0x80000000;
4629 macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
4634 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
4635 /* We want to close the noreorder block as soon as possible, so
4636 that later insns are available for delay slot filling. */
4637 --mips_opts.noreorder;
4641 expr1.X_add_number = 8;
4642 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4643 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4645 /* We want to close the noreorder block as soon as possible, so
4646 that later insns are available for delay slot filling. */
4647 --mips_opts.noreorder;
4649 macro_build (NULL, &icnt, NULL, "break", "c", 6);
4651 macro_build (NULL, &icnt, NULL, s, "d", dreg);
4690 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4692 as_warn (_("Divide by zero."));
4694 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4696 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4699 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4701 if (strcmp (s2, "mflo") == 0)
4702 move_register (&icnt, dreg, sreg);
4704 move_register (&icnt, dreg, 0);
4707 if (imm_expr.X_op == O_constant
4708 && imm_expr.X_add_number == -1
4709 && s[strlen (s) - 1] != 'u')
4711 if (strcmp (s2, "mflo") == 0)
4713 macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
4717 move_register (&icnt, dreg, 0);
4721 load_register (&icnt, AT, &imm_expr, dbl);
4722 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
4723 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4742 mips_emit_delays (TRUE);
4743 ++mips_opts.noreorder;
4744 mips_any_noreorder = 1;
4747 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4748 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4749 /* We want to close the noreorder block as soon as possible, so
4750 that later insns are available for delay slot filling. */
4751 --mips_opts.noreorder;
4755 expr1.X_add_number = 8;
4756 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4757 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4759 /* We want to close the noreorder block as soon as possible, so
4760 that later insns are available for delay slot filling. */
4761 --mips_opts.noreorder;
4762 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4764 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4770 /* Load the address of a symbol into a register. If breg is not
4771 zero, we then add a base register to it. */
4773 if (dbl && HAVE_32BIT_GPRS)
4774 as_warn (_("dla used to load 32-bit register"));
4776 if (! dbl && HAVE_64BIT_OBJECTS)
4777 as_warn (_("la used to load 64-bit address"));
4779 if (offset_expr.X_op == O_constant
4780 && offset_expr.X_add_number >= -0x8000
4781 && offset_expr.X_add_number < 0x8000)
4783 macro_build (NULL, &icnt, &offset_expr,
4784 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4785 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4800 /* When generating embedded PIC code, we permit expressions of
4803 la $treg,foo-bar($breg)
4804 where bar is an address in the current section. These are used
4805 when getting the addresses of functions. We don't permit
4806 X_add_number to be non-zero, because if the symbol is
4807 external the relaxing code needs to know that any addend is
4808 purely the offset to X_op_symbol. */
4809 if (mips_pic == EMBEDDED_PIC
4810 && offset_expr.X_op == O_subtract
4811 && (symbol_constant_p (offset_expr.X_op_symbol)
4812 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4813 : (symbol_equated_p (offset_expr.X_op_symbol)
4815 (symbol_get_value_expression (offset_expr.X_op_symbol)
4818 && (offset_expr.X_add_number == 0
4819 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4825 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4826 BFD_RELOC_PCREL_HI16_S);
4830 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4831 BFD_RELOC_PCREL_HI16_S);
4832 macro_build (NULL, &icnt, NULL,
4833 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4834 "d,v,t", tempreg, tempreg, breg);
4836 macro_build (NULL, &icnt, &offset_expr,
4837 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4838 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4844 if (offset_expr.X_op != O_symbol
4845 && offset_expr.X_op != O_constant)
4847 as_bad (_("expression too complex"));
4848 offset_expr.X_op = O_constant;
4851 if (offset_expr.X_op == O_constant)
4852 load_register (&icnt, tempreg, &offset_expr,
4853 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4854 ? (dbl || HAVE_64BIT_ADDRESSES)
4855 : HAVE_64BIT_ADDRESSES));
4856 else if (mips_pic == NO_PIC)
4858 /* If this is a reference to a GP relative symbol, we want
4859 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4861 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4862 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4863 If we have a constant, we need two instructions anyhow,
4864 so we may as well always use the latter form.
4866 With 64bit address space and a usable $at we want
4867 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4868 lui $at,<sym> (BFD_RELOC_HI16_S)
4869 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4870 daddiu $at,<sym> (BFD_RELOC_LO16)
4872 daddu $tempreg,$tempreg,$at
4874 If $at is already in use, we use a path which is suboptimal
4875 on superscalar processors.
4876 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4877 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4879 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4881 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4884 if (HAVE_64BIT_ADDRESSES)
4886 /* We don't do GP optimization for now because RELAX_ENCODE can't
4887 hold the data for such large chunks. */
4889 if (used_at == 0 && ! mips_opts.noat)
4891 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4892 tempreg, BFD_RELOC_MIPS_HIGHEST);
4893 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4894 AT, BFD_RELOC_HI16_S);
4895 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4896 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4897 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4898 AT, AT, BFD_RELOC_LO16);
4899 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
4900 tempreg, tempreg, 0);
4901 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
4902 tempreg, tempreg, AT);
4907 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4908 tempreg, BFD_RELOC_MIPS_HIGHEST);
4909 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4910 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4911 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4912 tempreg, tempreg, 16);
4913 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4914 tempreg, tempreg, BFD_RELOC_HI16_S);
4915 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4916 tempreg, tempreg, 16);
4917 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4918 tempreg, tempreg, BFD_RELOC_LO16);
4923 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4924 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4927 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4928 "t,r,j", tempreg, mips_gp_register,
4930 p = frag_var (rs_machine_dependent, 8, 0,
4931 RELAX_ENCODE (4, 8, 0, 4, 0,
4932 mips_opts.warn_about_macros),
4933 offset_expr.X_add_symbol, 0, NULL);
4935 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4938 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4939 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4942 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4944 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4946 /* If this is a reference to an external symbol, and there
4947 is no constant, we want
4948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4949 or if tempreg is PIC_CALL_REG
4950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4951 For a local symbol, we want
4952 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4954 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4956 If we have a small constant, and this is a reference to
4957 an external symbol, we want
4958 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4960 addiu $tempreg,$tempreg,<constant>
4961 For a local symbol, we want the same instruction
4962 sequence, but we output a BFD_RELOC_LO16 reloc on the
4965 If we have a large constant, and this is a reference to
4966 an external symbol, we want
4967 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4968 lui $at,<hiconstant>
4969 addiu $at,$at,<loconstant>
4970 addu $tempreg,$tempreg,$at
4971 For a local symbol, we want the same instruction
4972 sequence, but we output a BFD_RELOC_LO16 reloc on the
4976 expr1.X_add_number = offset_expr.X_add_number;
4977 offset_expr.X_add_number = 0;
4979 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4980 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4981 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
4982 tempreg, lw_reloc_type, mips_gp_register);
4983 if (expr1.X_add_number == 0)
4992 /* We're going to put in an addu instruction using
4993 tempreg, so we may as well insert the nop right
4995 macro_build (NULL, &icnt, NULL, "nop", "");
4998 p = frag_var (rs_machine_dependent, 8 - off, 0,
4999 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
5001 ? mips_opts.warn_about_macros
5003 offset_expr.X_add_symbol, 0, NULL);
5006 macro_build (p, &icnt, NULL, "nop", "");
5009 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5010 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5011 /* FIXME: If breg == 0, and the next instruction uses
5012 $tempreg, then if this variant case is used an extra
5013 nop will be generated. */
5015 else if (expr1.X_add_number >= -0x8000
5016 && expr1.X_add_number < 0x8000)
5018 macro_build (NULL, &icnt, NULL, "nop", "");
5019 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5020 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5021 frag_var (rs_machine_dependent, 0, 0,
5022 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5023 offset_expr.X_add_symbol, 0, NULL);
5029 /* If we are going to add in a base register, and the
5030 target register and the base register are the same,
5031 then we are using AT as a temporary register. Since
5032 we want to load the constant into AT, we add our
5033 current AT (from the global offset table) and the
5034 register into the register now, and pretend we were
5035 not using a base register. */
5040 macro_build (NULL, &icnt, NULL, "nop", "");
5041 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5048 /* Set mips_optimize around the lui instruction to avoid
5049 inserting an unnecessary nop after the lw. */
5050 hold_mips_optimize = mips_optimize;
5052 macro_build_lui (NULL, &icnt, &expr1, AT);
5053 mips_optimize = hold_mips_optimize;
5055 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5056 AT, AT, BFD_RELOC_LO16);
5057 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5058 tempreg, tempreg, AT);
5059 frag_var (rs_machine_dependent, 0, 0,
5060 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
5061 offset_expr.X_add_symbol, 0, NULL);
5065 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5068 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5071 /* If this is a reference to an external, and there is no
5072 constant, or local symbol (*), with or without a
5074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5075 or if tempreg is PIC_CALL_REG
5076 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5078 If we have a small constant, and this is a reference to
5079 an external symbol, we want
5080 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5081 addiu $tempreg,$tempreg,<constant>
5083 If we have a large constant, and this is a reference to
5084 an external symbol, we want
5085 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5086 lui $at,<hiconstant>
5087 addiu $at,$at,<loconstant>
5088 addu $tempreg,$tempreg,$at
5090 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5091 local symbols, even though it introduces an additional
5095 if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG)
5096 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5097 if (offset_expr.X_add_number)
5099 frag_now->tc_frag_data.tc_fr_offset =
5100 expr1.X_add_number = offset_expr.X_add_number;
5101 offset_expr.X_add_number = 0;
5103 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5104 "t,o(b)", tempreg, lw_reloc_type,
5107 if (expr1.X_add_number >= -0x8000
5108 && expr1.X_add_number < 0x8000)
5110 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5111 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5112 p = frag_var (rs_machine_dependent, 4, 0,
5113 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
5114 offset_expr.X_add_symbol, 0, NULL);
5116 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5120 /* If we are going to add in a base register, and the
5121 target register and the base register are the same,
5122 then we are using AT as a temporary register. Since
5123 we want to load the constant into AT, we add our
5124 current AT (from the global offset table) and the
5125 register into the register now, and pretend we were
5126 not using a base register. */
5131 assert (tempreg == AT);
5132 macro_build (NULL, &icnt,NULL, ADDRESS_ADD_INSN,
5133 "d,v,t", treg, AT, breg);
5138 macro_build_lui (NULL, &icnt, &expr1, AT);
5139 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5140 "t,r,j", AT, AT, BFD_RELOC_LO16);
5141 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5144 p = frag_var (rs_machine_dependent, 4 + adj, 0,
5145 RELAX_ENCODE (16 + adj, 4 + adj,
5147 offset_expr.X_add_symbol, 0, NULL);
5152 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5154 offset_expr.X_add_number = expr1.X_add_number;
5156 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5157 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5161 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5162 treg, tempreg, breg);
5169 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5170 "t,o(b)", tempreg, lw_reloc_type,
5172 if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP)
5173 p = frag_var (rs_machine_dependent, 0, 0,
5174 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5175 offset_expr.X_add_symbol, 0, NULL);
5180 /* To avoid confusion in tc_gen_reloc, we must ensure
5181 that this does not become a variant frag. */
5182 frag_wane (frag_now);
5186 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5190 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5191 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5192 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5194 /* This is the large GOT case. If this is a reference to an
5195 external symbol, and there is no constant, we want
5196 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5197 addu $tempreg,$tempreg,$gp
5198 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5199 or if tempreg is PIC_CALL_REG
5200 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5201 addu $tempreg,$tempreg,$gp
5202 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5203 For a local symbol, we want
5204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5206 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5208 If we have a small constant, and this is a reference to
5209 an external symbol, we want
5210 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5211 addu $tempreg,$tempreg,$gp
5212 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5214 addiu $tempreg,$tempreg,<constant>
5215 For a local symbol, we want
5216 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5218 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5220 If we have a large constant, and this is a reference to
5221 an external symbol, we want
5222 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5223 addu $tempreg,$tempreg,$gp
5224 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5225 lui $at,<hiconstant>
5226 addiu $at,$at,<loconstant>
5227 addu $tempreg,$tempreg,$at
5228 For a local symbol, we want
5229 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5230 lui $at,<hiconstant>
5231 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5232 addu $tempreg,$tempreg,$at
5235 expr1.X_add_number = offset_expr.X_add_number;
5236 offset_expr.X_add_number = 0;
5238 if (reg_needs_delay (mips_gp_register))
5242 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5244 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5245 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5247 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5248 tempreg, lui_reloc_type);
5249 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5250 tempreg, tempreg, mips_gp_register);
5251 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5252 tempreg, lw_reloc_type, tempreg);
5253 if (expr1.X_add_number == 0)
5261 /* We're going to put in an addu instruction using
5262 tempreg, so we may as well insert the nop right
5264 macro_build (NULL, &icnt, NULL, "nop", "");
5268 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5269 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5272 ? mips_opts.warn_about_macros
5274 offset_expr.X_add_symbol, 0, NULL);
5276 else if (expr1.X_add_number >= -0x8000
5277 && expr1.X_add_number < 0x8000)
5279 macro_build (NULL, &icnt, NULL, "nop", "");
5280 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5281 tempreg, tempreg, BFD_RELOC_LO16);
5283 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5284 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5286 ? mips_opts.warn_about_macros
5288 offset_expr.X_add_symbol, 0, NULL);
5294 /* If we are going to add in a base register, and the
5295 target register and the base register are the same,
5296 then we are using AT as a temporary register. Since
5297 we want to load the constant into AT, we add our
5298 current AT (from the global offset table) and the
5299 register into the register now, and pretend we were
5300 not using a base register. */
5308 assert (tempreg == AT);
5309 macro_build (NULL, &icnt, NULL, "nop", "");
5310 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5316 /* Set mips_optimize around the lui instruction to avoid
5317 inserting an unnecessary nop after the lw. */
5318 hold_mips_optimize = mips_optimize;
5320 macro_build_lui (NULL, &icnt, &expr1, AT);
5321 mips_optimize = hold_mips_optimize;
5323 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5324 AT, AT, BFD_RELOC_LO16);
5325 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5328 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5329 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5332 ? mips_opts.warn_about_macros
5334 offset_expr.X_add_symbol, 0, NULL);
5341 /* This is needed because this instruction uses $gp, but
5342 the first instruction on the main stream does not. */
5343 macro_build (p, &icnt, NULL, "nop", "");
5347 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5348 tempreg, local_reloc_type, mips_gp_register);
5350 if (expr1.X_add_number >= -0x8000
5351 && expr1.X_add_number < 0x8000)
5353 macro_build (p, &icnt, NULL, "nop", "");
5355 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5356 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5357 /* FIXME: If add_number is 0, and there was no base
5358 register, the external symbol case ended with a load,
5359 so if the symbol turns out to not be external, and
5360 the next instruction uses tempreg, an unnecessary nop
5361 will be inserted. */
5367 /* We must add in the base register now, as in the
5368 external symbol case. */
5369 assert (tempreg == AT);
5370 macro_build (p, &icnt, NULL, "nop", "");
5372 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5376 /* We set breg to 0 because we have arranged to add
5377 it in in both cases. */
5381 macro_build_lui (p, &icnt, &expr1, AT);
5383 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5384 AT, AT, BFD_RELOC_LO16);
5386 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5387 tempreg, tempreg, AT);
5391 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5394 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5395 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5398 /* This is the large GOT case. If this is a reference to an
5399 external symbol, and there is no constant, we want
5400 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5401 add $tempreg,$tempreg,$gp
5402 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5403 or if tempreg is PIC_CALL_REG
5404 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5405 add $tempreg,$tempreg,$gp
5406 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5408 If we have a small constant, and this is a reference to
5409 an external symbol, we want
5410 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5411 add $tempreg,$tempreg,$gp
5412 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5413 addi $tempreg,$tempreg,<constant>
5415 If we have a large constant, and this is a reference to
5416 an external symbol, we want
5417 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5418 addu $tempreg,$tempreg,$gp
5419 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5420 lui $at,<hiconstant>
5421 addi $at,$at,<loconstant>
5422 add $tempreg,$tempreg,$at
5424 If we have NewABI, and we know it's a local symbol, we want
5425 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5426 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5427 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5431 frag_now->tc_frag_data.tc_fr_offset =
5432 expr1.X_add_number = offset_expr.X_add_number;
5433 offset_expr.X_add_number = 0;
5435 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5437 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5438 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5440 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5441 tempreg, lui_reloc_type);
5442 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5443 tempreg, tempreg, mips_gp_register);
5444 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5445 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5447 if (expr1.X_add_number == 0)
5449 p = frag_var (rs_machine_dependent, 8, 0,
5450 RELAX_ENCODE (12, 8, 0, 4, 0,
5451 mips_opts.warn_about_macros),
5452 offset_expr.X_add_symbol, 0, NULL);
5454 else if (expr1.X_add_number >= -0x8000
5455 && expr1.X_add_number < 0x8000)
5457 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5458 tempreg, tempreg, BFD_RELOC_LO16);
5459 p = frag_var (rs_machine_dependent, 8, 0,
5460 RELAX_ENCODE (16, 8, 0, 4, 0,
5461 mips_opts.warn_about_macros),
5462 offset_expr.X_add_symbol, 0, NULL);
5464 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5468 /* If we are going to add in a base register, and the
5469 target register and the base register are the same,
5470 then we are using AT as a temporary register. Since
5471 we want to load the constant into AT, we add our
5472 current AT (from the global offset table) and the
5473 register into the register now, and pretend we were
5474 not using a base register. */
5479 assert (tempreg == AT);
5480 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5486 /* Set mips_optimize around the lui instruction to avoid
5487 inserting an unnecessary nop after the lw. */
5488 macro_build_lui (NULL, &icnt, &expr1, AT);
5489 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5490 "t,r,j", AT, AT, BFD_RELOC_LO16);
5491 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5494 p = frag_var (rs_machine_dependent, 8 + adj, 0,
5495 RELAX_ENCODE (24 + adj, 8 + adj,
5498 ? mips_opts.warn_about_macros
5500 offset_expr.X_add_symbol, 0, NULL);
5505 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5507 offset_expr.X_add_number = expr1.X_add_number;
5508 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5509 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5510 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5511 tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
5514 macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5515 treg, tempreg, breg);
5520 else if (mips_pic == EMBEDDED_PIC)
5523 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5525 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5526 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5535 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5536 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5538 s = ADDRESS_ADD_INSN;
5540 macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
5549 /* The j instruction may not be used in PIC code, since it
5550 requires an absolute address. We convert it to a b
5552 if (mips_pic == NO_PIC)
5553 macro_build (NULL, &icnt, &offset_expr, "j", "a");
5555 macro_build (NULL, &icnt, &offset_expr, "b", "p");
5558 /* The jal instructions must be handled as macros because when
5559 generating PIC code they expand to multi-instruction
5560 sequences. Normally they are simple instructions. */
5565 if (mips_pic == NO_PIC
5566 || mips_pic == EMBEDDED_PIC)
5567 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5568 else if (mips_pic == SVR4_PIC)
5570 if (sreg != PIC_CALL_REG)
5571 as_warn (_("MIPS PIC call to register other than $25"));
5573 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5576 if (mips_cprestore_offset < 0)
5577 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5580 if (! mips_frame_reg_valid)
5582 as_warn (_("No .frame pseudo-op used in PIC code"));
5583 /* Quiet this warning. */
5584 mips_frame_reg_valid = 1;
5586 if (! mips_cprestore_valid)
5588 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5589 /* Quiet this warning. */
5590 mips_cprestore_valid = 1;
5592 expr1.X_add_number = mips_cprestore_offset;
5593 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5597 HAVE_64BIT_ADDRESSES);
5607 if (mips_pic == NO_PIC)
5608 macro_build (NULL, &icnt, &offset_expr, "jal", "a");
5609 else if (mips_pic == SVR4_PIC)
5613 /* If this is a reference to an external symbol, and we are
5614 using a small GOT, we want
5615 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5619 lw $gp,cprestore($sp)
5620 The cprestore value is set using the .cprestore
5621 pseudo-op. If we are using a big GOT, we want
5622 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5624 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5628 lw $gp,cprestore($sp)
5629 If the symbol is not external, we want
5630 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5632 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5635 lw $gp,cprestore($sp)
5637 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5638 sequences above, minus nops, unless the symbol is local,
5639 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5646 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5647 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5649 frag_var (rs_machine_dependent, 0, 0,
5650 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5651 offset_expr.X_add_symbol, 0, NULL);
5656 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5657 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5658 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5659 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5660 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5661 "t,o(b)", PIC_CALL_REG,
5662 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5663 p = frag_var (rs_machine_dependent, 8, 0,
5664 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5665 offset_expr.X_add_symbol, 0, NULL);
5666 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5667 "t,o(b)", PIC_CALL_REG,
5668 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5669 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5670 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5671 BFD_RELOC_MIPS_GOT_OFST);
5674 macro_build_jalr (icnt, &offset_expr);
5681 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5682 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5684 macro_build (NULL, &icnt, NULL, "nop", "");
5685 p = frag_var (rs_machine_dependent, 4, 0,
5686 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5687 offset_expr.X_add_symbol, 0, NULL);
5693 if (reg_needs_delay (mips_gp_register))
5697 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5698 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5699 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5700 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5701 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5702 "t,o(b)", PIC_CALL_REG,
5703 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5704 macro_build (NULL, &icnt, NULL, "nop", "");
5705 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5706 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5708 offset_expr.X_add_symbol, 0, NULL);
5711 macro_build (p, &icnt, NULL, "nop", "");
5714 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5715 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5718 macro_build (p, &icnt, NULL, "nop", "");
5721 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5722 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5724 macro_build_jalr (icnt, &offset_expr);
5726 if (mips_cprestore_offset < 0)
5727 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5730 if (! mips_frame_reg_valid)
5732 as_warn (_("No .frame pseudo-op used in PIC code"));
5733 /* Quiet this warning. */
5734 mips_frame_reg_valid = 1;
5736 if (! mips_cprestore_valid)
5738 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5739 /* Quiet this warning. */
5740 mips_cprestore_valid = 1;
5742 if (mips_opts.noreorder)
5743 macro_build (NULL, &icnt, NULL, "nop", "");
5744 expr1.X_add_number = mips_cprestore_offset;
5745 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5749 HAVE_64BIT_ADDRESSES);
5753 else if (mips_pic == EMBEDDED_PIC)
5755 macro_build (NULL, &icnt, &offset_expr, "bal", "p");
5756 /* The linker may expand the call to a longer sequence which
5757 uses $at, so we must break rather than return. */
5782 /* Itbl support may require additional care here. */
5787 /* Itbl support may require additional care here. */
5792 /* Itbl support may require additional care here. */
5797 /* Itbl support may require additional care here. */
5809 if (mips_opts.arch == CPU_R4650)
5811 as_bad (_("opcode not supported on this processor"));
5815 /* Itbl support may require additional care here. */
5820 /* Itbl support may require additional care here. */
5825 /* Itbl support may require additional care here. */
5845 if (breg == treg || coproc || lr)
5867 /* Itbl support may require additional care here. */
5872 /* Itbl support may require additional care here. */
5877 /* Itbl support may require additional care here. */
5882 /* Itbl support may require additional care here. */
5898 if (mips_opts.arch == CPU_R4650)
5900 as_bad (_("opcode not supported on this processor"));
5905 /* Itbl support may require additional care here. */
5909 /* Itbl support may require additional care here. */
5914 /* Itbl support may require additional care here. */
5926 /* Itbl support may require additional care here. */
5927 if (mask == M_LWC1_AB
5928 || mask == M_SWC1_AB
5929 || mask == M_LDC1_AB
5930 || mask == M_SDC1_AB
5939 /* Sign-extending 32-bit constants makes their handling easier.
5940 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5942 if ((! HAVE_64BIT_ADDRESSES
5943 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5944 && (offset_expr.X_op == O_constant))
5946 if (offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)
5947 && ~(offset_expr.X_add_number | 0x7fffffff))
5948 as_bad (_("too large constant specified"));
5950 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5951 ^ 0x80000000) - 0x80000000);
5954 /* For embedded PIC, we allow loads where the offset is calculated
5955 by subtracting a symbol in the current segment from an unknown
5956 symbol, relative to a base register, e.g.:
5957 <op> $treg, <sym>-<localsym>($breg)
5958 This is used by the compiler for switch statements. */
5959 if (mips_pic == EMBEDDED_PIC
5960 && offset_expr.X_op == O_subtract
5961 && (symbol_constant_p (offset_expr.X_op_symbol)
5962 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5963 : (symbol_equated_p (offset_expr.X_op_symbol)
5965 (symbol_get_value_expression (offset_expr.X_op_symbol)
5969 && (offset_expr.X_add_number == 0
5970 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5972 /* For this case, we output the instructions:
5973 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5974 addiu $tempreg,$tempreg,$breg
5975 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5976 If the relocation would fit entirely in 16 bits, it would be
5978 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5979 instead, but that seems quite difficult. */
5980 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
5981 BFD_RELOC_PCREL_HI16_S);
5982 macro_build (NULL, &icnt, NULL,
5983 ((bfd_arch_bits_per_address (stdoutput) == 32
5984 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5985 ? "addu" : "daddu"),
5986 "d,v,t", tempreg, tempreg, breg);
5987 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
5988 BFD_RELOC_PCREL_LO16, tempreg);
5994 if (offset_expr.X_op != O_constant
5995 && offset_expr.X_op != O_symbol)
5997 as_bad (_("expression too complex"));
5998 offset_expr.X_op = O_constant;
6001 /* A constant expression in PIC code can be handled just as it
6002 is in non PIC code. */
6003 if (mips_pic == NO_PIC
6004 || offset_expr.X_op == O_constant)
6008 /* If this is a reference to a GP relative symbol, and there
6009 is no base register, we want
6010 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6011 Otherwise, if there is no base register, we want
6012 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6013 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6014 If we have a constant, we need two instructions anyhow,
6015 so we always use the latter form.
6017 If we have a base register, and this is a reference to a
6018 GP relative symbol, we want
6019 addu $tempreg,$breg,$gp
6020 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6022 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6023 addu $tempreg,$tempreg,$breg
6024 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6025 With a constant we always use the latter case.
6027 With 64bit address space and no base register and $at usable,
6029 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6030 lui $at,<sym> (BFD_RELOC_HI16_S)
6031 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6034 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6035 If we have a base register, we want
6036 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6037 lui $at,<sym> (BFD_RELOC_HI16_S)
6038 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6042 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6044 Without $at we can't generate the optimal path for superscalar
6045 processors here since this would require two temporary registers.
6046 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6047 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6049 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6051 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6052 If we have a base register, we want
6053 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6054 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6056 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6058 daddu $tempreg,$tempreg,$breg
6059 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6061 If we have 64-bit addresses, as an optimization, for
6062 addresses which are 32-bit constants (e.g. kseg0/kseg1
6063 addresses) we fall back to the 32-bit address generation
6064 mechanism since it is more efficient. Note that due to
6065 the signed offset used by memory operations, the 32-bit
6066 range is shifted down by 32768 here. This code should
6067 probably attempt to generate 64-bit constants more
6068 efficiently in general.
6070 As an extension for architectures with 64-bit registers,
6071 we don't truncate 64-bit addresses given as literal
6072 constants down to 32 bits, to support existing practice
6073 in the mips64 Linux (the kernel), that compiles source
6074 files with -mabi=64, assembling them as o32 or n32 (with
6075 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6076 the whole kernel is loaded into a memory region that is
6077 addressible with sign-extended 32-bit addresses, it is
6078 wasteful to compute the upper 32 bits of every
6079 non-literal address, that takes more space and time.
6080 Some day this should probably be implemented as an
6081 assembler option, such that the kernel doesn't have to
6082 use such ugly hacks, even though it will still have to
6083 end up converting the binary to ELF32 for a number of
6084 platforms whose boot loaders don't support ELF64
6086 if ((HAVE_64BIT_ADDRESSES
6087 && ! (offset_expr.X_op == O_constant
6088 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6090 && offset_expr.X_op == O_constant
6091 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6095 /* We don't do GP optimization for now because RELAX_ENCODE can't
6096 hold the data for such large chunks. */
6098 if (used_at == 0 && ! mips_opts.noat)
6100 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6101 tempreg, BFD_RELOC_MIPS_HIGHEST);
6102 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6103 AT, BFD_RELOC_HI16_S);
6104 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6105 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
6107 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6109 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
6110 tempreg, tempreg, 0);
6111 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6112 tempreg, tempreg, AT);
6113 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6114 BFD_RELOC_LO16, tempreg);
6119 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6120 tempreg, BFD_RELOC_MIPS_HIGHEST);
6121 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6122 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
6123 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
6124 tempreg, tempreg, 16);
6125 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6126 tempreg, tempreg, BFD_RELOC_HI16_S);
6127 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
6128 tempreg, tempreg, 16);
6130 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6131 tempreg, tempreg, breg);
6132 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6133 BFD_RELOC_LO16, tempreg);
6139 if (offset_expr.X_op == O_constant
6140 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6141 as_bad (_("load/store address overflow (max 32 bits)"));
6145 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6146 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6151 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6152 BFD_RELOC_GPREL16, mips_gp_register);
6153 p = frag_var (rs_machine_dependent, 8, 0,
6154 RELAX_ENCODE (4, 8, 0, 4, 0,
6155 (mips_opts.warn_about_macros
6157 && mips_opts.noat))),
6158 offset_expr.X_add_symbol, 0, NULL);
6161 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6164 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6165 BFD_RELOC_LO16, tempreg);
6169 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6170 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6175 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6176 tempreg, breg, mips_gp_register);
6177 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6178 BFD_RELOC_GPREL16, tempreg);
6179 p = frag_var (rs_machine_dependent, 12, 0,
6180 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6181 offset_expr.X_add_symbol, 0, NULL);
6183 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6186 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6187 tempreg, tempreg, breg);
6190 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6191 BFD_RELOC_LO16, tempreg);
6194 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6197 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6199 /* If this is a reference to an external symbol, we want
6200 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6202 <op> $treg,0($tempreg)
6204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6206 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6207 <op> $treg,0($tempreg)
6210 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6211 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6213 If there is a base register, we add it to $tempreg before
6214 the <op>. If there is a constant, we stick it in the
6215 <op> instruction. We don't handle constants larger than
6216 16 bits, because we have no way to load the upper 16 bits
6217 (actually, we could handle them for the subset of cases
6218 in which we are not using $at). */
6219 assert (offset_expr.X_op == O_symbol);
6222 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6223 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6226 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6227 tempreg, tempreg, breg);
6228 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6229 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6236 expr1.X_add_number = offset_expr.X_add_number;
6237 offset_expr.X_add_number = 0;
6238 if (expr1.X_add_number < -0x8000
6239 || expr1.X_add_number >= 0x8000)
6240 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6242 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6243 tempreg, lw_reloc_type, mips_gp_register);
6244 macro_build (NULL, &icnt, NULL, "nop", "");
6245 p = frag_var (rs_machine_dependent, 4, 0,
6246 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6247 offset_expr.X_add_symbol, 0, NULL);
6248 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6249 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
6251 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6252 tempreg, tempreg, breg);
6253 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6256 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6261 /* If this is a reference to an external symbol, we want
6262 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6263 addu $tempreg,$tempreg,$gp
6264 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6265 <op> $treg,0($tempreg)
6267 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6269 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6270 <op> $treg,0($tempreg)
6271 If there is a base register, we add it to $tempreg before
6272 the <op>. If there is a constant, we stick it in the
6273 <op> instruction. We don't handle constants larger than
6274 16 bits, because we have no way to load the upper 16 bits
6275 (actually, we could handle them for the subset of cases
6276 in which we are not using $at). */
6277 assert (offset_expr.X_op == O_symbol);
6278 expr1.X_add_number = offset_expr.X_add_number;
6279 offset_expr.X_add_number = 0;
6280 if (expr1.X_add_number < -0x8000
6281 || expr1.X_add_number >= 0x8000)
6282 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6283 if (reg_needs_delay (mips_gp_register))
6288 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6289 BFD_RELOC_MIPS_GOT_HI16);
6290 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6291 tempreg, tempreg, mips_gp_register);
6292 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6293 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6294 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
6295 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
6296 offset_expr.X_add_symbol, 0, NULL);
6299 macro_build (p, &icnt, NULL, "nop", "");
6302 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6303 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6305 macro_build (p, &icnt, NULL, "nop", "");
6307 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6308 tempreg, tempreg, BFD_RELOC_LO16);
6310 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6311 tempreg, tempreg, breg);
6312 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6315 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6318 int bregsz = breg != 0 ? 4 : 0;
6320 /* If this is a reference to an external symbol, we want
6321 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6322 add $tempreg,$tempreg,$gp
6323 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6324 <op> $treg,<ofst>($tempreg)
6325 Otherwise, for local symbols, we want:
6326 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6327 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6328 assert (offset_expr.X_op == O_symbol);
6329 frag_now->tc_frag_data.tc_fr_offset =
6330 expr1.X_add_number = offset_expr.X_add_number;
6331 offset_expr.X_add_number = 0;
6332 if (expr1.X_add_number < -0x8000
6333 || expr1.X_add_number >= 0x8000)
6334 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6336 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6337 BFD_RELOC_MIPS_GOT_HI16);
6338 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6339 tempreg, tempreg, mips_gp_register);
6340 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6341 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6343 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6344 tempreg, tempreg, breg);
6345 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6348 offset_expr.X_add_number = expr1.X_add_number;
6349 p = frag_var (rs_machine_dependent, 12 + bregsz, 0,
6350 RELAX_ENCODE (16 + bregsz, 8 + bregsz,
6351 0, 4 + bregsz, 0, 0),
6352 offset_expr.X_add_symbol, 0, NULL);
6353 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6354 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6356 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6357 tempreg, tempreg, breg);
6358 macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
6359 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6361 else if (mips_pic == EMBEDDED_PIC)
6363 /* If there is no base register, we want
6364 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6365 If there is a base register, we want
6366 addu $tempreg,$breg,$gp
6367 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6369 assert (offset_expr.X_op == O_symbol);
6372 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6373 BFD_RELOC_GPREL16, mips_gp_register);
6378 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6379 tempreg, breg, mips_gp_register);
6380 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6381 BFD_RELOC_GPREL16, tempreg);
6394 load_register (&icnt, treg, &imm_expr, 0);
6398 load_register (&icnt, treg, &imm_expr, 1);
6402 if (imm_expr.X_op == O_constant)
6404 load_register (&icnt, AT, &imm_expr, 0);
6405 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6410 assert (offset_expr.X_op == O_symbol
6411 && strcmp (segment_name (S_GET_SEGMENT
6412 (offset_expr.X_add_symbol)),
6414 && offset_expr.X_add_number == 0);
6415 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
6416 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6421 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6422 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6423 order 32 bits of the value and the low order 32 bits are either
6424 zero or in OFFSET_EXPR. */
6425 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6427 if (HAVE_64BIT_GPRS)
6428 load_register (&icnt, treg, &imm_expr, 1);
6433 if (target_big_endian)
6445 load_register (&icnt, hreg, &imm_expr, 0);
6448 if (offset_expr.X_op == O_absent)
6449 move_register (&icnt, lreg, 0);
6452 assert (offset_expr.X_op == O_constant);
6453 load_register (&icnt, lreg, &offset_expr, 0);
6460 /* We know that sym is in the .rdata section. First we get the
6461 upper 16 bits of the address. */
6462 if (mips_pic == NO_PIC)
6464 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6466 else if (mips_pic == SVR4_PIC)
6468 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6469 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6471 else if (mips_pic == EMBEDDED_PIC)
6473 /* For embedded PIC we pick up the entire address off $gp in
6474 a single instruction. */
6475 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6476 AT, mips_gp_register, BFD_RELOC_GPREL16);
6477 offset_expr.X_op = O_constant;
6478 offset_expr.X_add_number = 0;
6483 /* Now we load the register(s). */
6484 if (HAVE_64BIT_GPRS)
6485 macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
6486 BFD_RELOC_LO16, AT);
6489 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
6490 BFD_RELOC_LO16, AT);
6493 /* FIXME: How in the world do we deal with the possible
6495 offset_expr.X_add_number += 4;
6496 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6497 treg + 1, BFD_RELOC_LO16, AT);
6501 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6502 does not become a variant frag. */
6503 frag_wane (frag_now);
6509 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6510 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6511 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6512 the value and the low order 32 bits are either zero or in
6514 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6516 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6517 if (HAVE_64BIT_FPRS)
6519 assert (HAVE_64BIT_GPRS);
6520 macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
6524 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
6525 if (offset_expr.X_op == O_absent)
6526 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
6529 assert (offset_expr.X_op == O_constant);
6530 load_register (&icnt, AT, &offset_expr, 0);
6531 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6537 assert (offset_expr.X_op == O_symbol
6538 && offset_expr.X_add_number == 0);
6539 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6540 if (strcmp (s, ".lit8") == 0)
6542 if (mips_opts.isa != ISA_MIPS1)
6544 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6545 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6548 breg = mips_gp_register;
6549 r = BFD_RELOC_MIPS_LITERAL;
6554 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6555 if (mips_pic == SVR4_PIC)
6556 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6557 "t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
6561 /* FIXME: This won't work for a 64 bit address. */
6562 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6565 if (mips_opts.isa != ISA_MIPS1)
6567 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6568 BFD_RELOC_LO16, AT);
6570 /* To avoid confusion in tc_gen_reloc, we must ensure
6571 that this does not become a variant frag. */
6572 frag_wane (frag_now);
6583 if (mips_opts.arch == CPU_R4650)
6585 as_bad (_("opcode not supported on this processor"));
6588 /* Even on a big endian machine $fn comes before $fn+1. We have
6589 to adjust when loading from memory. */
6592 assert (mips_opts.isa == ISA_MIPS1);
6593 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6594 target_big_endian ? treg + 1 : treg, r, breg);
6595 /* FIXME: A possible overflow which I don't know how to deal
6597 offset_expr.X_add_number += 4;
6598 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6599 target_big_endian ? treg : treg + 1, r, breg);
6601 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6602 does not become a variant frag. */
6603 frag_wane (frag_now);
6612 * The MIPS assembler seems to check for X_add_number not
6613 * being double aligned and generating:
6616 * addiu at,at,%lo(foo+1)
6619 * But, the resulting address is the same after relocation so why
6620 * generate the extra instruction?
6622 if (mips_opts.arch == CPU_R4650)
6624 as_bad (_("opcode not supported on this processor"));
6627 /* Itbl support may require additional care here. */
6629 if (mips_opts.isa != ISA_MIPS1)
6640 if (mips_opts.arch == CPU_R4650)
6642 as_bad (_("opcode not supported on this processor"));
6646 if (mips_opts.isa != ISA_MIPS1)
6654 /* Itbl support may require additional care here. */
6659 if (HAVE_64BIT_GPRS)
6670 if (HAVE_64BIT_GPRS)
6680 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6681 loads for the case of doing a pair of loads to simulate an 'ld'.
6682 This is not currently done by the compiler, and assembly coders
6683 writing embedded-pic code can cope. */
6685 if (offset_expr.X_op != O_symbol
6686 && offset_expr.X_op != O_constant)
6688 as_bad (_("expression too complex"));
6689 offset_expr.X_op = O_constant;
6692 /* Even on a big endian machine $fn comes before $fn+1. We have
6693 to adjust when loading from memory. We set coproc if we must
6694 load $fn+1 first. */
6695 /* Itbl support may require additional care here. */
6696 if (! target_big_endian)
6699 if (mips_pic == NO_PIC
6700 || offset_expr.X_op == O_constant)
6704 /* If this is a reference to a GP relative symbol, we want
6705 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6706 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6707 If we have a base register, we use this
6709 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6710 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6711 If this is not a GP relative symbol, we want
6712 lui $at,<sym> (BFD_RELOC_HI16_S)
6713 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6714 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6715 If there is a base register, we add it to $at after the
6716 lui instruction. If there is a constant, we always use
6718 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6719 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6731 tempreg = mips_gp_register;
6738 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6739 AT, breg, mips_gp_register);
6745 /* Itbl support may require additional care here. */
6746 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6747 coproc ? treg + 1 : treg,
6748 BFD_RELOC_GPREL16, tempreg);
6749 offset_expr.X_add_number += 4;
6751 /* Set mips_optimize to 2 to avoid inserting an
6753 hold_mips_optimize = mips_optimize;
6755 /* Itbl support may require additional care here. */
6756 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6757 coproc ? treg : treg + 1,
6758 BFD_RELOC_GPREL16, tempreg);
6759 mips_optimize = hold_mips_optimize;
6761 p = frag_var (rs_machine_dependent, 12 + off, 0,
6762 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6763 used_at && mips_opts.noat),
6764 offset_expr.X_add_symbol, 0, NULL);
6766 /* We just generated two relocs. When tc_gen_reloc
6767 handles this case, it will skip the first reloc and
6768 handle the second. The second reloc already has an
6769 extra addend of 4, which we added above. We must
6770 subtract it out, and then subtract another 4 to make
6771 the first reloc come out right. The second reloc
6772 will come out right because we are going to add 4 to
6773 offset_expr when we build its instruction below.
6775 If we have a symbol, then we don't want to include
6776 the offset, because it will wind up being included
6777 when we generate the reloc. */
6779 if (offset_expr.X_op == O_constant)
6780 offset_expr.X_add_number -= 8;
6783 offset_expr.X_add_number = -4;
6784 offset_expr.X_op = O_constant;
6787 macro_build_lui (p, &icnt, &offset_expr, AT);
6792 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6797 /* Itbl support may require additional care here. */
6798 macro_build (p, &icnt, &offset_expr, s, fmt,
6799 coproc ? treg + 1 : treg,
6800 BFD_RELOC_LO16, AT);
6803 /* FIXME: How do we handle overflow here? */
6804 offset_expr.X_add_number += 4;
6805 /* Itbl support may require additional care here. */
6806 macro_build (p, &icnt, &offset_expr, s, fmt,
6807 coproc ? treg : treg + 1,
6808 BFD_RELOC_LO16, AT);
6810 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6814 /* If this is a reference to an external symbol, we want
6815 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6820 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6822 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6823 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6824 If there is a base register we add it to $at before the
6825 lwc1 instructions. If there is a constant we include it
6826 in the lwc1 instructions. */
6828 expr1.X_add_number = offset_expr.X_add_number;
6829 offset_expr.X_add_number = 0;
6830 if (expr1.X_add_number < -0x8000
6831 || expr1.X_add_number >= 0x8000 - 4)
6832 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6837 frag_grow (24 + off);
6838 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6839 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6840 macro_build (NULL, &icnt, NULL, "nop", "");
6842 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6844 /* Itbl support may require additional care here. */
6845 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6846 BFD_RELOC_LO16, AT);
6847 expr1.X_add_number += 4;
6849 /* Set mips_optimize to 2 to avoid inserting an undesired
6851 hold_mips_optimize = mips_optimize;
6853 /* Itbl support may require additional care here. */
6854 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6855 BFD_RELOC_LO16, AT);
6856 mips_optimize = hold_mips_optimize;
6858 (void) frag_var (rs_machine_dependent, 0, 0,
6859 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6860 offset_expr.X_add_symbol, 0, NULL);
6862 else if (mips_pic == SVR4_PIC)
6867 /* If this is a reference to an external symbol, we want
6868 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6870 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6875 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6877 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6878 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6879 If there is a base register we add it to $at before the
6880 lwc1 instructions. If there is a constant we include it
6881 in the lwc1 instructions. */
6883 expr1.X_add_number = offset_expr.X_add_number;
6884 offset_expr.X_add_number = 0;
6885 if (expr1.X_add_number < -0x8000
6886 || expr1.X_add_number >= 0x8000 - 4)
6887 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6888 if (reg_needs_delay (mips_gp_register))
6897 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
6898 BFD_RELOC_MIPS_GOT_HI16);
6899 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6900 AT, AT, mips_gp_register);
6901 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6902 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6903 macro_build (NULL, &icnt, NULL, "nop", "");
6905 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6907 /* Itbl support may require additional care here. */
6908 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6909 BFD_RELOC_LO16, AT);
6910 expr1.X_add_number += 4;
6912 /* Set mips_optimize to 2 to avoid inserting an undesired
6914 hold_mips_optimize = mips_optimize;
6916 /* Itbl support may require additional care here. */
6917 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6918 BFD_RELOC_LO16, AT);
6919 mips_optimize = hold_mips_optimize;
6920 expr1.X_add_number -= 4;
6922 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6923 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6924 8 + gpdel + off, 1, 0),
6925 offset_expr.X_add_symbol, 0, NULL);
6928 macro_build (p, &icnt, NULL, "nop", "");
6931 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6932 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6934 macro_build (p, &icnt, NULL, "nop", "");
6938 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6942 /* Itbl support may require additional care here. */
6943 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6944 BFD_RELOC_LO16, AT);
6946 expr1.X_add_number += 4;
6948 /* Set mips_optimize to 2 to avoid inserting an undesired
6950 hold_mips_optimize = mips_optimize;
6952 /* Itbl support may require additional care here. */
6953 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6954 BFD_RELOC_LO16, AT);
6955 mips_optimize = hold_mips_optimize;
6957 else if (mips_pic == EMBEDDED_PIC)
6959 /* If there is no base register, we use
6960 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6961 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6962 If we have a base register, we use
6964 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6965 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6969 tempreg = mips_gp_register;
6974 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6975 AT, breg, mips_gp_register);
6980 /* Itbl support may require additional care here. */
6981 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6982 coproc ? treg + 1 : treg,
6983 BFD_RELOC_GPREL16, tempreg);
6984 offset_expr.X_add_number += 4;
6985 /* Itbl support may require additional care here. */
6986 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6987 coproc ? treg : treg + 1,
6988 BFD_RELOC_GPREL16, tempreg);
7004 assert (HAVE_32BIT_ADDRESSES);
7005 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7006 BFD_RELOC_LO16, breg);
7007 offset_expr.X_add_number += 4;
7008 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
7009 BFD_RELOC_LO16, breg);
7012 /* New code added to support COPZ instructions.
7013 This code builds table entries out of the macros in mip_opcodes.
7014 R4000 uses interlocks to handle coproc delays.
7015 Other chips (like the R3000) require nops to be inserted for delays.
7017 FIXME: Currently, we require that the user handle delays.
7018 In order to fill delay slots for non-interlocked chips,
7019 we must have a way to specify delays based on the coprocessor.
7020 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7021 What are the side-effects of the cop instruction?
7022 What cache support might we have and what are its effects?
7023 Both coprocessor & memory require delays. how long???
7024 What registers are read/set/modified?
7026 If an itbl is provided to interpret cop instructions,
7027 this knowledge can be encoded in the itbl spec. */
7041 /* For now we just do C (same as Cz). The parameter will be
7042 stored in insn_opcode by mips_ip. */
7043 macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
7047 move_register (&icnt, dreg, sreg);
7050 #ifdef LOSING_COMPILER
7052 /* Try and see if this is a new itbl instruction.
7053 This code builds table entries out of the macros in mip_opcodes.
7054 FIXME: For now we just assemble the expression and pass it's
7055 value along as a 32-bit immediate.
7056 We may want to have the assembler assemble this value,
7057 so that we gain the assembler's knowledge of delay slots,
7059 Would it be more efficient to use mask (id) here? */
7060 if (itbl_have_entries
7061 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7063 s = ip->insn_mo->name;
7065 coproc = ITBL_DECODE_PNUM (immed_expr);;
7066 macro_build (NULL, &icnt, &immed_expr, s, "C");
7073 as_warn (_("Macro used $at after \".set noat\""));
7077 macro2 (struct mips_cl_insn *ip)
7079 register int treg, sreg, dreg, breg;
7095 bfd_reloc_code_real_type r;
7098 treg = (ip->insn_opcode >> 16) & 0x1f;
7099 dreg = (ip->insn_opcode >> 11) & 0x1f;
7100 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7101 mask = ip->insn_mo->mask;
7103 expr1.X_op = O_constant;
7104 expr1.X_op_symbol = NULL;
7105 expr1.X_add_symbol = NULL;
7106 expr1.X_add_number = 1;
7110 #endif /* LOSING_COMPILER */
7115 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7117 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7123 /* The MIPS assembler some times generates shifts and adds. I'm
7124 not trying to be that fancy. GCC should do this for us
7126 load_register (&icnt, AT, &imm_expr, dbl);
7127 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7129 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7142 mips_emit_delays (TRUE);
7143 ++mips_opts.noreorder;
7144 mips_any_noreorder = 1;
7146 load_register (&icnt, AT, &imm_expr, dbl);
7147 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7148 sreg, imm ? AT : treg);
7149 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7150 macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
7152 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7154 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
7157 expr1.X_add_number = 8;
7158 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
7159 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7160 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7162 --mips_opts.noreorder;
7163 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7176 mips_emit_delays (TRUE);
7177 ++mips_opts.noreorder;
7178 mips_any_noreorder = 1;
7180 load_register (&icnt, AT, &imm_expr, dbl);
7181 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7182 sreg, imm ? AT : treg);
7183 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7184 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7186 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
7189 expr1.X_add_number = 8;
7190 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
7191 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7192 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7194 --mips_opts.noreorder;
7198 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7210 macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
7211 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
7217 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7218 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7219 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7220 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7224 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7236 macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
7237 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
7243 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7244 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
7245 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
7246 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7254 if (imm_expr.X_op != O_constant)
7255 as_bad (_("Improper rotate count"));
7256 rot = imm_expr.X_add_number & 0x3f;
7257 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7259 rot = (64 - rot) & 0x3f;
7261 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7262 dreg, sreg, rot - 32);
7264 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7270 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7273 l = (rot < 0x20) ? "dsll" : "dsll32";
7274 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7276 macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
7277 macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
7278 (0x20 - rot) & 0x1f);
7279 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7287 if (imm_expr.X_op != O_constant)
7288 as_bad (_("Improper rotate count"));
7289 rot = imm_expr.X_add_number & 0x1f;
7290 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7292 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
7298 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7301 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
7302 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
7303 (0x20 - rot) & 0x1f);
7304 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7309 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7311 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
7314 macro_build (NULL, &icnt,NULL, "dsubu", "d,v,t", AT, 0, treg);
7315 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
7316 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7317 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7321 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7323 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
7326 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7327 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
7328 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
7329 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7337 if (imm_expr.X_op != O_constant)
7338 as_bad (_("Improper rotate count"));
7339 rot = imm_expr.X_add_number & 0x3f;
7340 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7343 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7344 dreg, sreg, rot - 32);
7346 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7352 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7355 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7356 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7358 macro_build ( NULL, &icnt,NULL, r, "d,w,<", AT, sreg, rot);
7359 macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
7360 (0x20 - rot) & 0x1f);
7361 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7369 if (imm_expr.X_op != O_constant)
7370 as_bad (_("Improper rotate count"));
7371 rot = imm_expr.X_add_number & 0x1f;
7372 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7374 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
7379 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7382 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
7383 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
7384 (0x20 - rot) & 0x1f);
7385 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7390 if (mips_opts.arch == CPU_R4650)
7392 as_bad (_("opcode not supported on this processor"));
7395 assert (mips_opts.isa == ISA_MIPS1);
7396 /* Even on a big endian machine $fn comes before $fn+1. We have
7397 to adjust when storing to memory. */
7398 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7399 target_big_endian ? treg + 1 : treg,
7400 BFD_RELOC_LO16, breg);
7401 offset_expr.X_add_number += 4;
7402 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7403 target_big_endian ? treg : treg + 1,
7404 BFD_RELOC_LO16, breg);
7409 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
7412 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7416 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7417 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7423 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7425 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7431 as_warn (_("Instruction %s: result is always false"),
7433 move_register (&icnt, dreg, 0);
7436 if (imm_expr.X_op == O_constant
7437 && imm_expr.X_add_number >= 0
7438 && imm_expr.X_add_number < 0x10000)
7440 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7444 else if (imm_expr.X_op == O_constant
7445 && imm_expr.X_add_number > -0x8000
7446 && imm_expr.X_add_number < 0)
7448 imm_expr.X_add_number = -imm_expr.X_add_number;
7449 macro_build (NULL, &icnt, &imm_expr,
7450 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7451 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7456 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7457 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7460 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7466 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7472 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
7473 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7477 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7479 if (imm_expr.X_op == O_constant
7480 && imm_expr.X_add_number >= -0x8000
7481 && imm_expr.X_add_number < 0x8000)
7483 macro_build (NULL, &icnt, &imm_expr,
7484 mask == M_SGE_I ? "slti" : "sltiu",
7485 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7490 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7491 macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
7492 "d,v,t", dreg, sreg, AT);
7495 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7501 case M_SGT: /* sreg > treg <==> treg < sreg */
7507 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7510 case M_SGT_I: /* sreg > I <==> I < sreg */
7516 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7517 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7520 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7526 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7527 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7531 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7537 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7538 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7539 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7544 if (imm_expr.X_op == O_constant
7545 && imm_expr.X_add_number >= -0x8000
7546 && imm_expr.X_add_number < 0x8000)
7548 macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
7552 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7553 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
7557 if (imm_expr.X_op == O_constant
7558 && imm_expr.X_add_number >= -0x8000
7559 && imm_expr.X_add_number < 0x8000)
7561 macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
7565 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7566 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
7571 macro_build (NULL, &icnt,NULL, "sltu","d,v,t", dreg, 0, treg);
7573 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7576 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7577 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7582 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7584 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7589 as_warn (_("Instruction %s: result is always true"),
7591 macro_build (NULL, &icnt, &expr1,
7592 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7593 "t,r,j", dreg, 0, BFD_RELOC_LO16);
7596 if (imm_expr.X_op == O_constant
7597 && imm_expr.X_add_number >= 0
7598 && imm_expr.X_add_number < 0x10000)
7600 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7604 else if (imm_expr.X_op == O_constant
7605 && imm_expr.X_add_number > -0x8000
7606 && imm_expr.X_add_number < 0)
7608 imm_expr.X_add_number = -imm_expr.X_add_number;
7609 macro_build (NULL, &icnt, &imm_expr,
7610 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7611 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7616 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7617 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7620 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7628 if (imm_expr.X_op == O_constant
7629 && imm_expr.X_add_number > -0x8000
7630 && imm_expr.X_add_number <= 0x8000)
7632 imm_expr.X_add_number = -imm_expr.X_add_number;
7633 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
7634 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7637 load_register (&icnt, AT, &imm_expr, dbl);
7638 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
7645 if (imm_expr.X_op == O_constant
7646 && imm_expr.X_add_number > -0x8000
7647 && imm_expr.X_add_number <= 0x8000)
7649 imm_expr.X_add_number = -imm_expr.X_add_number;
7650 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
7651 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7654 load_register (&icnt, AT, &imm_expr, dbl);
7655 macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
7677 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7678 macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
7683 assert (mips_opts.isa == ISA_MIPS1);
7684 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7685 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7688 * Is the double cfc1 instruction a bug in the mips assembler;
7689 * or is there a reason for it?
7691 mips_emit_delays (TRUE);
7692 ++mips_opts.noreorder;
7693 mips_any_noreorder = 1;
7694 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7695 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7696 macro_build (NULL, &icnt, NULL, "nop", "");
7697 expr1.X_add_number = 3;
7698 macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7700 expr1.X_add_number = 2;
7701 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7703 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
7704 macro_build (NULL, &icnt, NULL, "nop", "");
7705 macro_build (NULL, &icnt, NULL,
7706 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
7708 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
7709 macro_build (NULL, &icnt, NULL, "nop", "");
7710 --mips_opts.noreorder;
7719 if (offset_expr.X_add_number >= 0x7fff)
7720 as_bad (_("operand overflow"));
7721 if (! target_big_endian)
7722 ++offset_expr.X_add_number;
7723 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7724 BFD_RELOC_LO16, breg);
7725 if (! target_big_endian)
7726 --offset_expr.X_add_number;
7728 ++offset_expr.X_add_number;
7729 macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7730 BFD_RELOC_LO16, breg);
7731 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
7732 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7745 if (offset_expr.X_add_number >= 0x8000 - off)
7746 as_bad (_("operand overflow"));
7751 if (! target_big_endian)
7752 offset_expr.X_add_number += off;
7753 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7754 BFD_RELOC_LO16, breg);
7755 if (! target_big_endian)
7756 offset_expr.X_add_number -= off;
7758 offset_expr.X_add_number += off;
7759 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7760 BFD_RELOC_LO16, breg);
7762 /* If necessary, move the result in tempreg the final destination. */
7763 if (treg == tempreg)
7765 /* Protect second load's delay slot. */
7766 if (!gpr_interlocks)
7767 macro_build (NULL, &icnt, NULL, "nop", "");
7768 move_register (&icnt, treg, tempreg);
7782 load_address (&icnt, AT, &offset_expr, &used_at);
7784 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7786 if (! target_big_endian)
7787 expr1.X_add_number = off;
7789 expr1.X_add_number = 0;
7790 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7791 BFD_RELOC_LO16, AT);
7792 if (! target_big_endian)
7793 expr1.X_add_number = 0;
7795 expr1.X_add_number = off;
7796 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7797 BFD_RELOC_LO16, AT);
7803 load_address (&icnt, AT, &offset_expr, &used_at);
7805 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7807 if (target_big_endian)
7808 expr1.X_add_number = 0;
7809 macro_build (NULL, &icnt, &expr1,
7810 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7811 treg, BFD_RELOC_LO16, AT);
7812 if (target_big_endian)
7813 expr1.X_add_number = 1;
7815 expr1.X_add_number = 0;
7816 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
7817 AT, BFD_RELOC_LO16, AT);
7818 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7819 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7823 if (offset_expr.X_add_number >= 0x7fff)
7824 as_bad (_("operand overflow"));
7825 if (target_big_endian)
7826 ++offset_expr.X_add_number;
7827 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7828 BFD_RELOC_LO16, breg);
7829 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
7830 if (target_big_endian)
7831 --offset_expr.X_add_number;
7833 ++offset_expr.X_add_number;
7834 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7835 BFD_RELOC_LO16, breg);
7848 if (offset_expr.X_add_number >= 0x8000 - off)
7849 as_bad (_("operand overflow"));
7850 if (! target_big_endian)
7851 offset_expr.X_add_number += off;
7852 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7853 BFD_RELOC_LO16, breg);
7854 if (! target_big_endian)
7855 offset_expr.X_add_number -= off;
7857 offset_expr.X_add_number += off;
7858 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7859 BFD_RELOC_LO16, breg);
7873 load_address (&icnt, AT, &offset_expr, &used_at);
7875 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7877 if (! target_big_endian)
7878 expr1.X_add_number = off;
7880 expr1.X_add_number = 0;
7881 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7882 BFD_RELOC_LO16, AT);
7883 if (! target_big_endian)
7884 expr1.X_add_number = 0;
7886 expr1.X_add_number = off;
7887 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7888 BFD_RELOC_LO16, AT);
7893 load_address (&icnt, AT, &offset_expr, &used_at);
7895 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7897 if (! target_big_endian)
7898 expr1.X_add_number = 0;
7899 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7900 BFD_RELOC_LO16, AT);
7901 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
7902 if (! target_big_endian)
7903 expr1.X_add_number = 1;
7905 expr1.X_add_number = 0;
7906 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7907 BFD_RELOC_LO16, AT);
7908 if (! target_big_endian)
7909 expr1.X_add_number = 0;
7911 expr1.X_add_number = 1;
7912 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7913 BFD_RELOC_LO16, AT);
7914 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7915 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7919 /* FIXME: Check if this is one of the itbl macros, since they
7920 are added dynamically. */
7921 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7925 as_warn (_("Macro used $at after \".set noat\""));
7928 /* Implement macros in mips16 mode. */
7931 mips16_macro (struct mips_cl_insn *ip)
7934 int xreg, yreg, zreg, tmp;
7938 const char *s, *s2, *s3;
7940 mask = ip->insn_mo->mask;
7942 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7943 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7944 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7948 expr1.X_op = O_constant;
7949 expr1.X_op_symbol = NULL;
7950 expr1.X_add_symbol = NULL;
7951 expr1.X_add_number = 1;
7970 mips_emit_delays (TRUE);
7971 ++mips_opts.noreorder;
7972 mips_any_noreorder = 1;
7973 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
7975 expr1.X_add_number = 2;
7976 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7977 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7979 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7980 since that causes an overflow. We should do that as well,
7981 but I don't see how to do the comparisons without a temporary
7983 --mips_opts.noreorder;
7984 macro_build (NULL, &icnt, NULL, s, "x", zreg);
8003 mips_emit_delays (TRUE);
8004 ++mips_opts.noreorder;
8005 mips_any_noreorder = 1;
8006 macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
8007 expr1.X_add_number = 2;
8008 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
8009 macro_build (NULL, &icnt, NULL, "break", "6", 7);
8010 --mips_opts.noreorder;
8011 macro_build (NULL, &icnt, NULL, s2, "x", zreg);
8017 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
8019 macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
8027 if (imm_expr.X_op != O_constant)
8028 as_bad (_("Unsupported large constant"));
8029 imm_expr.X_add_number = -imm_expr.X_add_number;
8030 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
8035 if (imm_expr.X_op != O_constant)
8036 as_bad (_("Unsupported large constant"));
8037 imm_expr.X_add_number = -imm_expr.X_add_number;
8038 macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
8042 if (imm_expr.X_op != O_constant)
8043 as_bad (_("Unsupported large constant"));
8044 imm_expr.X_add_number = -imm_expr.X_add_number;
8045 macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
8067 goto do_reverse_branch;
8071 goto do_reverse_branch;
8083 goto do_reverse_branch;
8094 macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
8095 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8122 goto do_addone_branch_i;
8127 goto do_addone_branch_i;
8142 goto do_addone_branch_i;
8149 if (imm_expr.X_op != O_constant)
8150 as_bad (_("Unsupported large constant"));
8151 ++imm_expr.X_add_number;
8154 macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
8155 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8159 expr1.X_add_number = 0;
8160 macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
8162 move_register (&icnt, xreg, yreg);
8163 expr1.X_add_number = 2;
8164 macro_build (NULL, &icnt, &expr1, "bteqz", "p");
8165 macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
8169 /* For consistency checking, verify that all bits are specified either
8170 by the match/mask part of the instruction definition, or by the
8173 validate_mips_insn (const struct mips_opcode *opc)
8175 const char *p = opc->args;
8177 unsigned long used_bits = opc->mask;
8179 if ((used_bits & opc->match) != opc->match)
8181 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8182 opc->name, opc->args);
8185 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8195 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8196 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8197 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8198 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8199 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8200 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8201 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8202 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8203 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8206 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8207 c, opc->name, opc->args);
8211 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8212 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8214 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8215 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8216 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8217 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8219 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8220 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8222 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8223 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8225 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8226 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8227 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8228 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8229 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8230 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8231 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8232 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8233 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8234 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8235 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8236 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8237 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8238 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8239 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8240 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8241 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8243 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8244 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8245 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8246 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8248 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8249 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8250 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8251 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8252 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8253 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8254 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8255 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8256 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8259 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8260 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8261 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8262 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8263 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8267 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8268 c, opc->name, opc->args);
8272 if (used_bits != 0xffffffff)
8274 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8275 ~used_bits & 0xffffffff, opc->name, opc->args);
8281 /* This routine assembles an instruction into its binary format. As a
8282 side effect, it sets one of the global variables imm_reloc or
8283 offset_reloc to the type of relocation to do if one of the operands
8284 is an address expression. */
8287 mips_ip (char *str, struct mips_cl_insn *ip)
8292 struct mips_opcode *insn;
8295 unsigned int lastregno = 0;
8296 unsigned int lastpos = 0;
8297 unsigned int limlo, limhi;
8303 /* If the instruction contains a '.', we first try to match an instruction
8304 including the '.'. Then we try again without the '.'. */
8306 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8309 /* If we stopped on whitespace, then replace the whitespace with null for
8310 the call to hash_find. Save the character we replaced just in case we
8311 have to re-parse the instruction. */
8318 insn = (struct mips_opcode *) hash_find (op_hash, str);
8320 /* If we didn't find the instruction in the opcode table, try again, but
8321 this time with just the instruction up to, but not including the
8325 /* Restore the character we overwrite above (if any). */
8329 /* Scan up to the first '.' or whitespace. */
8331 *s != '\0' && *s != '.' && !ISSPACE (*s);
8335 /* If we did not find a '.', then we can quit now. */
8338 insn_error = "unrecognized opcode";
8342 /* Lookup the instruction in the hash table. */
8344 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8346 insn_error = "unrecognized opcode";
8356 assert (strcmp (insn->name, str) == 0);
8358 if (OPCODE_IS_MEMBER (insn,
8360 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8361 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8362 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8368 if (insn->pinfo != INSN_MACRO)
8370 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8376 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8377 && strcmp (insn->name, insn[1].name) == 0)
8386 static char buf[100];
8388 _("opcode not supported on this processor: %s (%s)"),
8389 mips_cpu_info_from_arch (mips_opts.arch)->name,
8390 mips_cpu_info_from_isa (mips_opts.isa)->name);
8400 ip->insn_opcode = insn->match;
8402 for (args = insn->args;; ++args)
8406 s += strspn (s, " \t");
8410 case '\0': /* end of args */
8423 ip->insn_opcode |= lastregno << OP_SH_RS;
8427 ip->insn_opcode |= lastregno << OP_SH_RT;
8431 ip->insn_opcode |= lastregno << OP_SH_FT;
8435 ip->insn_opcode |= lastregno << OP_SH_FS;
8441 /* Handle optional base register.
8442 Either the base register is omitted or
8443 we must have a left paren. */
8444 /* This is dependent on the next operand specifier
8445 is a base register specification. */
8446 assert (args[1] == 'b' || args[1] == '5'
8447 || args[1] == '-' || args[1] == '4');
8451 case ')': /* these must match exactly */
8458 case '+': /* Opcode extension character. */
8461 case 'A': /* ins/ext position, becomes LSB. */
8470 my_getExpression (&imm_expr, s);
8471 check_absolute_expr (ip, &imm_expr);
8472 if ((unsigned long) imm_expr.X_add_number < limlo
8473 || (unsigned long) imm_expr.X_add_number > limhi)
8475 as_bad (_("Improper position (%lu)"),
8476 (unsigned long) imm_expr.X_add_number);
8477 imm_expr.X_add_number = limlo;
8479 lastpos = imm_expr.X_add_number;
8480 ip->insn_opcode |= (imm_expr.X_add_number
8481 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8482 imm_expr.X_op = O_absent;
8486 case 'B': /* ins size, becomes MSB. */
8495 my_getExpression (&imm_expr, s);
8496 check_absolute_expr (ip, &imm_expr);
8497 /* Check for negative input so that small negative numbers
8498 will not succeed incorrectly. The checks against
8499 (pos+size) transitively check "size" itself,
8500 assuming that "pos" is reasonable. */
8501 if ((long) imm_expr.X_add_number < 0
8502 || ((unsigned long) imm_expr.X_add_number
8504 || ((unsigned long) imm_expr.X_add_number
8507 as_bad (_("Improper insert size (%lu, position %lu)"),
8508 (unsigned long) imm_expr.X_add_number,
8509 (unsigned long) lastpos);
8510 imm_expr.X_add_number = limlo - lastpos;
8512 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8513 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8514 imm_expr.X_op = O_absent;
8518 case 'C': /* ext size, becomes MSBD. */
8531 my_getExpression (&imm_expr, s);
8532 check_absolute_expr (ip, &imm_expr);
8533 /* Check for negative input so that small negative numbers
8534 will not succeed incorrectly. The checks against
8535 (pos+size) transitively check "size" itself,
8536 assuming that "pos" is reasonable. */
8537 if ((long) imm_expr.X_add_number < 0
8538 || ((unsigned long) imm_expr.X_add_number
8540 || ((unsigned long) imm_expr.X_add_number
8543 as_bad (_("Improper extract size (%lu, position %lu)"),
8544 (unsigned long) imm_expr.X_add_number,
8545 (unsigned long) lastpos);
8546 imm_expr.X_add_number = limlo - lastpos;
8548 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8549 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8550 imm_expr.X_op = O_absent;
8555 /* +D is for disassembly only; never match. */
8559 /* "+I" is like "I", except that imm2_expr is used. */
8560 my_getExpression (&imm2_expr, s);
8561 if (imm2_expr.X_op != O_big
8562 && imm2_expr.X_op != O_constant)
8563 insn_error = _("absolute expression required");
8568 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8569 *args, insn->name, insn->args);
8570 /* Further processing is fruitless. */
8575 case '<': /* must be at least one digit */
8577 * According to the manual, if the shift amount is greater
8578 * than 31 or less than 0, then the shift amount should be
8579 * mod 32. In reality the mips assembler issues an error.
8580 * We issue a warning and mask out all but the low 5 bits.
8582 my_getExpression (&imm_expr, s);
8583 check_absolute_expr (ip, &imm_expr);
8584 if ((unsigned long) imm_expr.X_add_number > 31)
8586 as_warn (_("Improper shift amount (%lu)"),
8587 (unsigned long) imm_expr.X_add_number);
8588 imm_expr.X_add_number &= OP_MASK_SHAMT;
8590 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8591 imm_expr.X_op = O_absent;
8595 case '>': /* shift amount minus 32 */
8596 my_getExpression (&imm_expr, s);
8597 check_absolute_expr (ip, &imm_expr);
8598 if ((unsigned long) imm_expr.X_add_number < 32
8599 || (unsigned long) imm_expr.X_add_number > 63)
8601 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8602 imm_expr.X_op = O_absent;
8606 case 'k': /* cache code */
8607 case 'h': /* prefx code */
8608 my_getExpression (&imm_expr, s);
8609 check_absolute_expr (ip, &imm_expr);
8610 if ((unsigned long) imm_expr.X_add_number > 31)
8612 as_warn (_("Invalid value for `%s' (%lu)"),
8614 (unsigned long) imm_expr.X_add_number);
8615 imm_expr.X_add_number &= 0x1f;
8618 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8620 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8621 imm_expr.X_op = O_absent;
8625 case 'c': /* break code */
8626 my_getExpression (&imm_expr, s);
8627 check_absolute_expr (ip, &imm_expr);
8628 if ((unsigned long) imm_expr.X_add_number > 1023)
8630 as_warn (_("Illegal break code (%lu)"),
8631 (unsigned long) imm_expr.X_add_number);
8632 imm_expr.X_add_number &= OP_MASK_CODE;
8634 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8635 imm_expr.X_op = O_absent;
8639 case 'q': /* lower break code */
8640 my_getExpression (&imm_expr, s);
8641 check_absolute_expr (ip, &imm_expr);
8642 if ((unsigned long) imm_expr.X_add_number > 1023)
8644 as_warn (_("Illegal lower break code (%lu)"),
8645 (unsigned long) imm_expr.X_add_number);
8646 imm_expr.X_add_number &= OP_MASK_CODE2;
8648 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8649 imm_expr.X_op = O_absent;
8653 case 'B': /* 20-bit syscall/break code. */
8654 my_getExpression (&imm_expr, s);
8655 check_absolute_expr (ip, &imm_expr);
8656 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8657 as_warn (_("Illegal 20-bit code (%lu)"),
8658 (unsigned long) imm_expr.X_add_number);
8659 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8660 imm_expr.X_op = O_absent;
8664 case 'C': /* Coprocessor code */
8665 my_getExpression (&imm_expr, s);
8666 check_absolute_expr (ip, &imm_expr);
8667 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8669 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8670 (unsigned long) imm_expr.X_add_number);
8671 imm_expr.X_add_number &= ((1 << 25) - 1);
8673 ip->insn_opcode |= imm_expr.X_add_number;
8674 imm_expr.X_op = O_absent;
8678 case 'J': /* 19-bit wait code. */
8679 my_getExpression (&imm_expr, s);
8680 check_absolute_expr (ip, &imm_expr);
8681 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8682 as_warn (_("Illegal 19-bit code (%lu)"),
8683 (unsigned long) imm_expr.X_add_number);
8684 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8685 imm_expr.X_op = O_absent;
8689 case 'P': /* Performance register */
8690 my_getExpression (&imm_expr, s);
8691 check_absolute_expr (ip, &imm_expr);
8692 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8694 as_warn (_("Invalid performance register (%lu)"),
8695 (unsigned long) imm_expr.X_add_number);
8696 imm_expr.X_add_number &= OP_MASK_PERFREG;
8698 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8699 imm_expr.X_op = O_absent;
8703 case 'b': /* base register */
8704 case 'd': /* destination register */
8705 case 's': /* source register */
8706 case 't': /* target register */
8707 case 'r': /* both target and source */
8708 case 'v': /* both dest and source */
8709 case 'w': /* both dest and target */
8710 case 'E': /* coprocessor target register */
8711 case 'G': /* coprocessor destination register */
8712 case 'K': /* 'rdhwr' destination register */
8713 case 'x': /* ignore register name */
8714 case 'z': /* must be zero register */
8715 case 'U': /* destination register (clo/clz). */
8730 while (ISDIGIT (*s));
8732 as_bad (_("Invalid register number (%d)"), regno);
8734 else if (*args == 'E' || *args == 'G' || *args == 'K')
8738 if (s[1] == 'r' && s[2] == 'a')
8743 else if (s[1] == 'f' && s[2] == 'p')
8748 else if (s[1] == 's' && s[2] == 'p')
8753 else if (s[1] == 'g' && s[2] == 'p')
8758 else if (s[1] == 'a' && s[2] == 't')
8763 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8768 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8773 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8778 else if (itbl_have_entries)
8783 p = s + 1; /* advance past '$' */
8784 n = itbl_get_field (&p); /* n is name */
8786 /* See if this is a register defined in an
8788 if (itbl_get_reg_val (n, &r))
8790 /* Get_field advances to the start of
8791 the next field, so we need to back
8792 rack to the end of the last field. */
8796 s = strchr (s, '\0');
8810 as_warn (_("Used $at without \".set noat\""));
8816 if (c == 'r' || c == 'v' || c == 'w')
8823 /* 'z' only matches $0. */
8824 if (c == 'z' && regno != 0)
8827 /* Now that we have assembled one operand, we use the args string
8828 * to figure out where it goes in the instruction. */
8835 ip->insn_opcode |= regno << OP_SH_RS;
8840 ip->insn_opcode |= regno << OP_SH_RD;
8843 ip->insn_opcode |= regno << OP_SH_RD;
8844 ip->insn_opcode |= regno << OP_SH_RT;
8849 ip->insn_opcode |= regno << OP_SH_RT;
8852 /* This case exists because on the r3000 trunc
8853 expands into a macro which requires a gp
8854 register. On the r6000 or r4000 it is
8855 assembled into a single instruction which
8856 ignores the register. Thus the insn version
8857 is MIPS_ISA2 and uses 'x', and the macro
8858 version is MIPS_ISA1 and uses 't'. */
8861 /* This case is for the div instruction, which
8862 acts differently if the destination argument
8863 is $0. This only matches $0, and is checked
8864 outside the switch. */
8867 /* Itbl operand; not yet implemented. FIXME ?? */
8869 /* What about all other operands like 'i', which
8870 can be specified in the opcode table? */
8880 ip->insn_opcode |= lastregno << OP_SH_RS;
8883 ip->insn_opcode |= lastregno << OP_SH_RT;
8888 case 'O': /* MDMX alignment immediate constant. */
8889 my_getExpression (&imm_expr, s);
8890 check_absolute_expr (ip, &imm_expr);
8891 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8893 as_warn ("Improper align amount (%ld), using low bits",
8894 (long) imm_expr.X_add_number);
8895 imm_expr.X_add_number &= OP_MASK_ALN;
8897 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8898 imm_expr.X_op = O_absent;
8902 case 'Q': /* MDMX vector, element sel, or const. */
8905 /* MDMX Immediate. */
8906 my_getExpression (&imm_expr, s);
8907 check_absolute_expr (ip, &imm_expr);
8908 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8910 as_warn (_("Invalid MDMX Immediate (%ld)"),
8911 (long) imm_expr.X_add_number);
8912 imm_expr.X_add_number &= OP_MASK_FT;
8914 imm_expr.X_add_number &= OP_MASK_FT;
8915 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8916 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8918 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8919 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8920 imm_expr.X_op = O_absent;
8924 /* Not MDMX Immediate. Fall through. */
8925 case 'X': /* MDMX destination register. */
8926 case 'Y': /* MDMX source register. */
8927 case 'Z': /* MDMX target register. */
8929 case 'D': /* floating point destination register */
8930 case 'S': /* floating point source register */
8931 case 'T': /* floating point target register */
8932 case 'R': /* floating point source register */
8936 /* Accept $fN for FP and MDMX register numbers, and in
8937 addition accept $vN for MDMX register numbers. */
8938 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8939 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8950 while (ISDIGIT (*s));
8953 as_bad (_("Invalid float register number (%d)"), regno);
8955 if ((regno & 1) != 0
8957 && ! (strcmp (str, "mtc1") == 0
8958 || strcmp (str, "mfc1") == 0
8959 || strcmp (str, "lwc1") == 0
8960 || strcmp (str, "swc1") == 0
8961 || strcmp (str, "l.s") == 0
8962 || strcmp (str, "s.s") == 0))
8963 as_warn (_("Float register should be even, was %d"),
8971 if (c == 'V' || c == 'W')
8982 ip->insn_opcode |= regno << OP_SH_FD;
8987 ip->insn_opcode |= regno << OP_SH_FS;
8990 /* This is like 'Z', but also needs to fix the MDMX
8991 vector/scalar select bits. Note that the
8992 scalar immediate case is handled above. */
8995 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8996 int max_el = (is_qh ? 3 : 7);
8998 my_getExpression(&imm_expr, s);
8999 check_absolute_expr (ip, &imm_expr);
9001 if (imm_expr.X_add_number > max_el)
9002 as_bad(_("Bad element selector %ld"),
9003 (long) imm_expr.X_add_number);
9004 imm_expr.X_add_number &= max_el;
9005 ip->insn_opcode |= (imm_expr.X_add_number
9009 as_warn(_("Expecting ']' found '%s'"), s);
9015 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9016 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9019 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9026 ip->insn_opcode |= regno << OP_SH_FT;
9029 ip->insn_opcode |= regno << OP_SH_FR;
9039 ip->insn_opcode |= lastregno << OP_SH_FS;
9042 ip->insn_opcode |= lastregno << OP_SH_FT;
9048 my_getExpression (&imm_expr, s);
9049 if (imm_expr.X_op != O_big
9050 && imm_expr.X_op != O_constant)
9051 insn_error = _("absolute expression required");
9056 my_getExpression (&offset_expr, s);
9057 *imm_reloc = BFD_RELOC_32;
9070 unsigned char temp[8];
9072 unsigned int length;
9077 /* These only appear as the last operand in an
9078 instruction, and every instruction that accepts
9079 them in any variant accepts them in all variants.
9080 This means we don't have to worry about backing out
9081 any changes if the instruction does not match.
9083 The difference between them is the size of the
9084 floating point constant and where it goes. For 'F'
9085 and 'L' the constant is 64 bits; for 'f' and 'l' it
9086 is 32 bits. Where the constant is placed is based
9087 on how the MIPS assembler does things:
9090 f -- immediate value
9093 The .lit4 and .lit8 sections are only used if
9094 permitted by the -G argument.
9096 When generating embedded PIC code, we use the
9097 .lit8 section but not the .lit4 section (we can do
9098 .lit4 inline easily; we need to put .lit8
9099 somewhere in the data segment, and using .lit8
9100 permits the linker to eventually combine identical
9103 The code below needs to know whether the target register
9104 is 32 or 64 bits wide. It relies on the fact 'f' and
9105 'F' are used with GPR-based instructions and 'l' and
9106 'L' are used with FPR-based instructions. */
9108 f64 = *args == 'F' || *args == 'L';
9109 using_gprs = *args == 'F' || *args == 'f';
9111 save_in = input_line_pointer;
9112 input_line_pointer = s;
9113 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9115 s = input_line_pointer;
9116 input_line_pointer = save_in;
9117 if (err != NULL && *err != '\0')
9119 as_bad (_("Bad floating point constant: %s"), err);
9120 memset (temp, '\0', sizeof temp);
9121 length = f64 ? 8 : 4;
9124 assert (length == (unsigned) (f64 ? 8 : 4));
9128 && (! USE_GLOBAL_POINTER_OPT
9129 || mips_pic == EMBEDDED_PIC
9130 || g_switch_value < 4
9131 || (temp[0] == 0 && temp[1] == 0)
9132 || (temp[2] == 0 && temp[3] == 0))))
9134 imm_expr.X_op = O_constant;
9135 if (! target_big_endian)
9136 imm_expr.X_add_number = bfd_getl32 (temp);
9138 imm_expr.X_add_number = bfd_getb32 (temp);
9141 && ! mips_disable_float_construction
9142 /* Constants can only be constructed in GPRs and
9143 copied to FPRs if the GPRs are at least as wide
9144 as the FPRs. Force the constant into memory if
9145 we are using 64-bit FPRs but the GPRs are only
9148 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9149 && ((temp[0] == 0 && temp[1] == 0)
9150 || (temp[2] == 0 && temp[3] == 0))
9151 && ((temp[4] == 0 && temp[5] == 0)
9152 || (temp[6] == 0 && temp[7] == 0)))
9154 /* The value is simple enough to load with a couple of
9155 instructions. If using 32-bit registers, set
9156 imm_expr to the high order 32 bits and offset_expr to
9157 the low order 32 bits. Otherwise, set imm_expr to
9158 the entire 64 bit constant. */
9159 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9161 imm_expr.X_op = O_constant;
9162 offset_expr.X_op = O_constant;
9163 if (! target_big_endian)
9165 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9166 offset_expr.X_add_number = bfd_getl32 (temp);
9170 imm_expr.X_add_number = bfd_getb32 (temp);
9171 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9173 if (offset_expr.X_add_number == 0)
9174 offset_expr.X_op = O_absent;
9176 else if (sizeof (imm_expr.X_add_number) > 4)
9178 imm_expr.X_op = O_constant;
9179 if (! target_big_endian)
9180 imm_expr.X_add_number = bfd_getl64 (temp);
9182 imm_expr.X_add_number = bfd_getb64 (temp);
9186 imm_expr.X_op = O_big;
9187 imm_expr.X_add_number = 4;
9188 if (! target_big_endian)
9190 generic_bignum[0] = bfd_getl16 (temp);
9191 generic_bignum[1] = bfd_getl16 (temp + 2);
9192 generic_bignum[2] = bfd_getl16 (temp + 4);
9193 generic_bignum[3] = bfd_getl16 (temp + 6);
9197 generic_bignum[0] = bfd_getb16 (temp + 6);
9198 generic_bignum[1] = bfd_getb16 (temp + 4);
9199 generic_bignum[2] = bfd_getb16 (temp + 2);
9200 generic_bignum[3] = bfd_getb16 (temp);
9206 const char *newname;
9209 /* Switch to the right section. */
9211 subseg = now_subseg;
9214 default: /* unused default case avoids warnings. */
9216 newname = RDATA_SECTION_NAME;
9217 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9218 || mips_pic == EMBEDDED_PIC)
9222 if (mips_pic == EMBEDDED_PIC)
9225 newname = RDATA_SECTION_NAME;
9228 assert (!USE_GLOBAL_POINTER_OPT
9229 || g_switch_value >= 4);
9233 new_seg = subseg_new (newname, (subsegT) 0);
9234 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9235 bfd_set_section_flags (stdoutput, new_seg,
9240 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9241 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9242 && strcmp (TARGET_OS, "elf") != 0)
9243 record_alignment (new_seg, 4);
9245 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9247 as_bad (_("Can't use floating point insn in this section"));
9249 /* Set the argument to the current address in the
9251 offset_expr.X_op = O_symbol;
9252 offset_expr.X_add_symbol =
9253 symbol_new ("L0\001", now_seg,
9254 (valueT) frag_now_fix (), frag_now);
9255 offset_expr.X_add_number = 0;
9257 /* Put the floating point number into the section. */
9258 p = frag_more ((int) length);
9259 memcpy (p, temp, length);
9261 /* Switch back to the original section. */
9262 subseg_set (seg, subseg);
9267 case 'i': /* 16 bit unsigned immediate */
9268 case 'j': /* 16 bit signed immediate */
9269 *imm_reloc = BFD_RELOC_LO16;
9270 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9273 offsetT minval, maxval;
9275 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9276 && strcmp (insn->name, insn[1].name) == 0);
9278 /* If the expression was written as an unsigned number,
9279 only treat it as signed if there are no more
9283 && sizeof (imm_expr.X_add_number) <= 4
9284 && imm_expr.X_op == O_constant
9285 && imm_expr.X_add_number < 0
9286 && imm_expr.X_unsigned
9290 /* For compatibility with older assemblers, we accept
9291 0x8000-0xffff as signed 16-bit numbers when only
9292 signed numbers are allowed. */
9294 minval = 0, maxval = 0xffff;
9296 minval = -0x8000, maxval = 0x7fff;
9298 minval = -0x8000, maxval = 0xffff;
9300 if (imm_expr.X_op != O_constant
9301 || imm_expr.X_add_number < minval
9302 || imm_expr.X_add_number > maxval)
9306 if (imm_expr.X_op == O_constant
9307 || imm_expr.X_op == O_big)
9308 as_bad (_("expression out of range"));
9314 case 'o': /* 16 bit offset */
9315 /* Check whether there is only a single bracketed expression
9316 left. If so, it must be the base register and the
9317 constant must be zero. */
9318 if (*s == '(' && strchr (s + 1, '(') == 0)
9320 offset_expr.X_op = O_constant;
9321 offset_expr.X_add_number = 0;
9325 /* If this value won't fit into a 16 bit offset, then go
9326 find a macro that will generate the 32 bit offset
9328 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9329 && (offset_expr.X_op != O_constant
9330 || offset_expr.X_add_number >= 0x8000
9331 || offset_expr.X_add_number < -0x8000))
9337 case 'p': /* pc relative offset */
9338 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9339 my_getExpression (&offset_expr, s);
9343 case 'u': /* upper 16 bits */
9344 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9345 && imm_expr.X_op == O_constant
9346 && (imm_expr.X_add_number < 0
9347 || imm_expr.X_add_number >= 0x10000))
9348 as_bad (_("lui expression not in range 0..65535"));
9352 case 'a': /* 26 bit address */
9353 my_getExpression (&offset_expr, s);
9355 *offset_reloc = BFD_RELOC_MIPS_JMP;
9358 case 'N': /* 3 bit branch condition code */
9359 case 'M': /* 3 bit compare condition code */
9360 if (strncmp (s, "$fcc", 4) != 0)
9370 while (ISDIGIT (*s));
9372 as_bad (_("Invalid condition code register $fcc%d"), regno);
9373 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9374 || strcmp(str + strlen(str) - 5, "any2f") == 0
9375 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9376 && (regno & 1) != 0)
9377 as_warn(_("Condition code register should be even for %s, was %d"),
9379 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9380 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9381 && (regno & 3) != 0)
9382 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9385 ip->insn_opcode |= regno << OP_SH_BCC;
9387 ip->insn_opcode |= regno << OP_SH_CCC;
9391 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9402 while (ISDIGIT (*s));
9405 c = 8; /* Invalid sel value. */
9408 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9409 ip->insn_opcode |= c;
9413 /* Must be at least one digit. */
9414 my_getExpression (&imm_expr, s);
9415 check_absolute_expr (ip, &imm_expr);
9417 if ((unsigned long) imm_expr.X_add_number
9418 > (unsigned long) OP_MASK_VECBYTE)
9420 as_bad (_("bad byte vector index (%ld)"),
9421 (long) imm_expr.X_add_number);
9422 imm_expr.X_add_number = 0;
9425 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9426 imm_expr.X_op = O_absent;
9431 my_getExpression (&imm_expr, s);
9432 check_absolute_expr (ip, &imm_expr);
9434 if ((unsigned long) imm_expr.X_add_number
9435 > (unsigned long) OP_MASK_VECALIGN)
9437 as_bad (_("bad byte vector index (%ld)"),
9438 (long) imm_expr.X_add_number);
9439 imm_expr.X_add_number = 0;
9442 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9443 imm_expr.X_op = O_absent;
9448 as_bad (_("bad char = '%c'\n"), *args);
9453 /* Args don't match. */
9454 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9455 !strcmp (insn->name, insn[1].name))
9459 insn_error = _("illegal operands");
9464 insn_error = _("illegal operands");
9469 /* This routine assembles an instruction into its binary format when
9470 assembling for the mips16. As a side effect, it sets one of the
9471 global variables imm_reloc or offset_reloc to the type of
9472 relocation to do if one of the operands is an address expression.
9473 It also sets mips16_small and mips16_ext if the user explicitly
9474 requested a small or extended instruction. */
9477 mips16_ip (char *str, struct mips_cl_insn *ip)
9481 struct mips_opcode *insn;
9484 unsigned int lastregno = 0;
9489 mips16_small = FALSE;
9492 for (s = str; ISLOWER (*s); ++s)
9504 if (s[1] == 't' && s[2] == ' ')
9507 mips16_small = TRUE;
9511 else if (s[1] == 'e' && s[2] == ' ')
9520 insn_error = _("unknown opcode");
9524 if (mips_opts.noautoextend && ! mips16_ext)
9525 mips16_small = TRUE;
9527 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9529 insn_error = _("unrecognized opcode");
9536 assert (strcmp (insn->name, str) == 0);
9539 ip->insn_opcode = insn->match;
9540 ip->use_extend = FALSE;
9541 imm_expr.X_op = O_absent;
9542 imm_reloc[0] = BFD_RELOC_UNUSED;
9543 imm_reloc[1] = BFD_RELOC_UNUSED;
9544 imm_reloc[2] = BFD_RELOC_UNUSED;
9545 imm2_expr.X_op = O_absent;
9546 offset_expr.X_op = O_absent;
9547 offset_reloc[0] = BFD_RELOC_UNUSED;
9548 offset_reloc[1] = BFD_RELOC_UNUSED;
9549 offset_reloc[2] = BFD_RELOC_UNUSED;
9550 for (args = insn->args; 1; ++args)
9557 /* In this switch statement we call break if we did not find
9558 a match, continue if we did find a match, or return if we
9567 /* Stuff the immediate value in now, if we can. */
9568 if (imm_expr.X_op == O_constant
9569 && *imm_reloc > BFD_RELOC_UNUSED
9570 && insn->pinfo != INSN_MACRO)
9572 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9573 imm_expr.X_add_number, TRUE, mips16_small,
9574 mips16_ext, &ip->insn_opcode,
9575 &ip->use_extend, &ip->extend);
9576 imm_expr.X_op = O_absent;
9577 *imm_reloc = BFD_RELOC_UNUSED;
9591 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9594 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9610 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9612 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9639 while (ISDIGIT (*s));
9642 as_bad (_("invalid register number (%d)"), regno);
9648 if (s[1] == 'r' && s[2] == 'a')
9653 else if (s[1] == 'f' && s[2] == 'p')
9658 else if (s[1] == 's' && s[2] == 'p')
9663 else if (s[1] == 'g' && s[2] == 'p')
9668 else if (s[1] == 'a' && s[2] == 't')
9673 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9678 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9683 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9696 if (c == 'v' || c == 'w')
9698 regno = mips16_to_32_reg_map[lastregno];
9712 regno = mips32_to_16_reg_map[regno];
9717 regno = ILLEGAL_REG;
9722 regno = ILLEGAL_REG;
9727 regno = ILLEGAL_REG;
9732 if (regno == AT && ! mips_opts.noat)
9733 as_warn (_("used $at without \".set noat\""));
9740 if (regno == ILLEGAL_REG)
9747 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9751 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9754 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9757 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9763 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9766 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9767 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9777 if (strncmp (s, "$pc", 3) == 0)
9801 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9803 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9804 and generate the appropriate reloc. If the text
9805 inside %gprel is not a symbol name with an
9806 optional offset, then we generate a normal reloc
9807 and will probably fail later. */
9808 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9809 if (imm_expr.X_op == O_symbol)
9812 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9814 ip->use_extend = TRUE;
9821 /* Just pick up a normal expression. */
9822 my_getExpression (&imm_expr, s);
9825 if (imm_expr.X_op == O_register)
9827 /* What we thought was an expression turned out to
9830 if (s[0] == '(' && args[1] == '(')
9832 /* It looks like the expression was omitted
9833 before a register indirection, which means
9834 that the expression is implicitly zero. We
9835 still set up imm_expr, so that we handle
9836 explicit extensions correctly. */
9837 imm_expr.X_op = O_constant;
9838 imm_expr.X_add_number = 0;
9839 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9846 /* We need to relax this instruction. */
9847 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9856 /* We use offset_reloc rather than imm_reloc for the PC
9857 relative operands. This lets macros with both
9858 immediate and address operands work correctly. */
9859 my_getExpression (&offset_expr, s);
9861 if (offset_expr.X_op == O_register)
9864 /* We need to relax this instruction. */
9865 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9869 case '6': /* break code */
9870 my_getExpression (&imm_expr, s);
9871 check_absolute_expr (ip, &imm_expr);
9872 if ((unsigned long) imm_expr.X_add_number > 63)
9874 as_warn (_("Invalid value for `%s' (%lu)"),
9876 (unsigned long) imm_expr.X_add_number);
9877 imm_expr.X_add_number &= 0x3f;
9879 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9880 imm_expr.X_op = O_absent;
9884 case 'a': /* 26 bit address */
9885 my_getExpression (&offset_expr, s);
9887 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9888 ip->insn_opcode <<= 16;
9891 case 'l': /* register list for entry macro */
9892 case 'L': /* register list for exit macro */
9902 int freg, reg1, reg2;
9904 while (*s == ' ' || *s == ',')
9908 as_bad (_("can't parse register list"));
9920 while (ISDIGIT (*s))
9942 as_bad (_("invalid register list"));
9947 while (ISDIGIT (*s))
9954 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9959 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9964 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9965 mask |= (reg2 - 3) << 3;
9966 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9967 mask |= (reg2 - 15) << 1;
9968 else if (reg1 == RA && reg2 == RA)
9972 as_bad (_("invalid register list"));
9976 /* The mask is filled in in the opcode table for the
9977 benefit of the disassembler. We remove it before
9978 applying the actual mask. */
9979 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9980 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9984 case 'e': /* extend code */
9985 my_getExpression (&imm_expr, s);
9986 check_absolute_expr (ip, &imm_expr);
9987 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9989 as_warn (_("Invalid value for `%s' (%lu)"),
9991 (unsigned long) imm_expr.X_add_number);
9992 imm_expr.X_add_number &= 0x7ff;
9994 ip->insn_opcode |= imm_expr.X_add_number;
9995 imm_expr.X_op = O_absent;
10005 /* Args don't match. */
10006 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10007 strcmp (insn->name, insn[1].name) == 0)
10014 insn_error = _("illegal operands");
10020 /* This structure holds information we know about a mips16 immediate
10023 struct mips16_immed_operand
10025 /* The type code used in the argument string in the opcode table. */
10027 /* The number of bits in the short form of the opcode. */
10029 /* The number of bits in the extended form of the opcode. */
10031 /* The amount by which the short form is shifted when it is used;
10032 for example, the sw instruction has a shift count of 2. */
10034 /* The amount by which the short form is shifted when it is stored
10035 into the instruction code. */
10037 /* Non-zero if the short form is unsigned. */
10039 /* Non-zero if the extended form is unsigned. */
10041 /* Non-zero if the value is PC relative. */
10045 /* The mips16 immediate operand types. */
10047 static const struct mips16_immed_operand mips16_immed_operands[] =
10049 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10050 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10051 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10052 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10053 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10054 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10055 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10056 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10057 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10058 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10059 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10060 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10061 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10062 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10063 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10064 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10065 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10066 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10067 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10068 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10069 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10072 #define MIPS16_NUM_IMMED \
10073 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10075 /* Handle a mips16 instruction with an immediate value. This or's the
10076 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10077 whether an extended value is needed; if one is needed, it sets
10078 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10079 If SMALL is true, an unextended opcode was explicitly requested.
10080 If EXT is true, an extended opcode was explicitly requested. If
10081 WARN is true, warn if EXT does not match reality. */
10084 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10085 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10086 unsigned long *insn, bfd_boolean *use_extend,
10087 unsigned short *extend)
10089 register const struct mips16_immed_operand *op;
10090 int mintiny, maxtiny;
10091 bfd_boolean needext;
10093 op = mips16_immed_operands;
10094 while (op->type != type)
10097 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10102 if (type == '<' || type == '>' || type == '[' || type == ']')
10105 maxtiny = 1 << op->nbits;
10110 maxtiny = (1 << op->nbits) - 1;
10115 mintiny = - (1 << (op->nbits - 1));
10116 maxtiny = (1 << (op->nbits - 1)) - 1;
10119 /* Branch offsets have an implicit 0 in the lowest bit. */
10120 if (type == 'p' || type == 'q')
10123 if ((val & ((1 << op->shift) - 1)) != 0
10124 || val < (mintiny << op->shift)
10125 || val > (maxtiny << op->shift))
10130 if (warn && ext && ! needext)
10131 as_warn_where (file, line,
10132 _("extended operand requested but not required"));
10133 if (small && needext)
10134 as_bad_where (file, line, _("invalid unextended operand value"));
10136 if (small || (! ext && ! needext))
10140 *use_extend = FALSE;
10141 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10142 insnval <<= op->op_shift;
10147 long minext, maxext;
10153 maxext = (1 << op->extbits) - 1;
10157 minext = - (1 << (op->extbits - 1));
10158 maxext = (1 << (op->extbits - 1)) - 1;
10160 if (val < minext || val > maxext)
10161 as_bad_where (file, line,
10162 _("operand value out of range for instruction"));
10164 *use_extend = TRUE;
10165 if (op->extbits == 16)
10167 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10170 else if (op->extbits == 15)
10172 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10177 extval = ((val & 0x1f) << 6) | (val & 0x20);
10181 *extend = (unsigned short) extval;
10186 static const struct percent_op_match
10189 bfd_reloc_code_real_type reloc;
10192 {"%lo", BFD_RELOC_LO16},
10194 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10195 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10196 {"%call16", BFD_RELOC_MIPS_CALL16},
10197 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10198 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10199 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10200 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10201 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10202 {"%got", BFD_RELOC_MIPS_GOT16},
10203 {"%gp_rel", BFD_RELOC_GPREL16},
10204 {"%half", BFD_RELOC_16},
10205 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10206 {"%higher", BFD_RELOC_MIPS_HIGHER},
10207 {"%neg", BFD_RELOC_MIPS_SUB},
10209 {"%hi", BFD_RELOC_HI16_S}
10213 /* Return true if *STR points to a relocation operator. When returning true,
10214 move *STR over the operator and store its relocation code in *RELOC.
10215 Leave both *STR and *RELOC alone when returning false. */
10218 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10222 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10223 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10225 *str += strlen (percent_op[i].str);
10226 *reloc = percent_op[i].reloc;
10228 /* Check whether the output BFD supports this relocation.
10229 If not, issue an error and fall back on something safe. */
10230 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10232 as_bad ("relocation %s isn't supported by the current ABI",
10233 percent_op[i].str);
10234 *reloc = BFD_RELOC_LO16;
10242 /* Parse string STR as a 16-bit relocatable operand. Store the
10243 expression in *EP and the relocations in the array starting
10244 at RELOC. Return the number of relocation operators used.
10246 On exit, EXPR_END points to the first character after the expression.
10247 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10250 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10253 bfd_reloc_code_real_type reversed_reloc[3];
10254 size_t reloc_index, i;
10255 int crux_depth, str_depth;
10258 /* Search for the start of the main expression, recoding relocations
10259 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10260 of the main expression and with CRUX_DEPTH containing the number
10261 of open brackets at that point. */
10268 crux_depth = str_depth;
10270 /* Skip over whitespace and brackets, keeping count of the number
10272 while (*str == ' ' || *str == '\t' || *str == '(')
10277 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10278 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10280 my_getExpression (ep, crux);
10283 /* Match every open bracket. */
10284 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10288 if (crux_depth > 0)
10289 as_bad ("unclosed '('");
10293 if (reloc_index == 0)
10294 reloc[0] = BFD_RELOC_LO16;
10297 prev_reloc_op_frag = frag_now;
10298 for (i = 0; i < reloc_index; i++)
10299 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10302 return reloc_index;
10306 my_getExpression (expressionS *ep, char *str)
10311 save_in = input_line_pointer;
10312 input_line_pointer = str;
10314 expr_end = input_line_pointer;
10315 input_line_pointer = save_in;
10317 /* If we are in mips16 mode, and this is an expression based on `.',
10318 then we bump the value of the symbol by 1 since that is how other
10319 text symbols are handled. We don't bother to handle complex
10320 expressions, just `.' plus or minus a constant. */
10321 if (mips_opts.mips16
10322 && ep->X_op == O_symbol
10323 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10324 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10325 && symbol_get_frag (ep->X_add_symbol) == frag_now
10326 && symbol_constant_p (ep->X_add_symbol)
10327 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10328 S_SET_VALUE (ep->X_add_symbol, val + 1);
10331 /* Turn a string in input_line_pointer into a floating point constant
10332 of type TYPE, and store the appropriate bytes in *LITP. The number
10333 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10334 returned, or NULL on OK. */
10337 md_atof (int type, char *litP, int *sizeP)
10340 LITTLENUM_TYPE words[4];
10356 return _("bad call to md_atof");
10359 t = atof_ieee (input_line_pointer, type, words);
10361 input_line_pointer = t;
10365 if (! target_big_endian)
10367 for (i = prec - 1; i >= 0; i--)
10369 md_number_to_chars (litP, words[i], 2);
10375 for (i = 0; i < prec; i++)
10377 md_number_to_chars (litP, words[i], 2);
10386 md_number_to_chars (char *buf, valueT val, int n)
10388 if (target_big_endian)
10389 number_to_chars_bigendian (buf, val, n);
10391 number_to_chars_littleendian (buf, val, n);
10395 static int support_64bit_objects(void)
10397 const char **list, **l;
10400 list = bfd_target_list ();
10401 for (l = list; *l != NULL; l++)
10403 /* This is traditional mips */
10404 if (strcmp (*l, "elf64-tradbigmips") == 0
10405 || strcmp (*l, "elf64-tradlittlemips") == 0)
10407 if (strcmp (*l, "elf64-bigmips") == 0
10408 || strcmp (*l, "elf64-littlemips") == 0)
10411 yes = (*l != NULL);
10415 #endif /* OBJ_ELF */
10417 const char *md_shortopts = "nO::g::G:";
10419 struct option md_longopts[] =
10421 /* Options which specify architecture. */
10422 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10423 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10424 {"march", required_argument, NULL, OPTION_MARCH},
10425 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10426 {"mtune", required_argument, NULL, OPTION_MTUNE},
10427 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10428 {"mips0", no_argument, NULL, OPTION_MIPS1},
10429 {"mips1", no_argument, NULL, OPTION_MIPS1},
10430 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10431 {"mips2", no_argument, NULL, OPTION_MIPS2},
10432 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10433 {"mips3", no_argument, NULL, OPTION_MIPS3},
10434 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10435 {"mips4", no_argument, NULL, OPTION_MIPS4},
10436 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10437 {"mips5", no_argument, NULL, OPTION_MIPS5},
10438 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10439 {"mips32", no_argument, NULL, OPTION_MIPS32},
10440 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10441 {"mips64", no_argument, NULL, OPTION_MIPS64},
10442 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10443 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10444 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10445 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10447 /* Options which specify Application Specific Extensions (ASEs). */
10448 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10449 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10450 {"mips16", no_argument, NULL, OPTION_MIPS16},
10451 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10452 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10453 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10454 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10455 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10456 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10457 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10458 {"mdmx", no_argument, NULL, OPTION_MDMX},
10459 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10460 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10462 /* Old-style architecture options. Don't add more of these. */
10463 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10464 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10465 {"m4650", no_argument, NULL, OPTION_M4650},
10466 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10467 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10468 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10469 {"m4010", no_argument, NULL, OPTION_M4010},
10470 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10471 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10472 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10473 {"m4100", no_argument, NULL, OPTION_M4100},
10474 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10475 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10476 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10477 {"m3900", no_argument, NULL, OPTION_M3900},
10478 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10479 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10481 /* Options which enable bug fixes. */
10482 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10483 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10484 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10485 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10486 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10487 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10488 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10489 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10490 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10491 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10493 /* Miscellaneous options. */
10494 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10495 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10496 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10497 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10498 {"trap", no_argument, NULL, OPTION_TRAP},
10499 {"no-break", no_argument, NULL, OPTION_TRAP},
10500 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10501 {"break", no_argument, NULL, OPTION_BREAK},
10502 {"no-trap", no_argument, NULL, OPTION_BREAK},
10503 #define OPTION_EB (OPTION_MISC_BASE + 3)
10504 {"EB", no_argument, NULL, OPTION_EB},
10505 #define OPTION_EL (OPTION_MISC_BASE + 4)
10506 {"EL", no_argument, NULL, OPTION_EL},
10507 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10508 {"mfp32", no_argument, NULL, OPTION_FP32},
10509 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10510 {"mgp32", no_argument, NULL, OPTION_GP32},
10511 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10512 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10513 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10514 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10515 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10516 {"mfp64", no_argument, NULL, OPTION_FP64},
10517 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10518 {"mgp64", no_argument, NULL, OPTION_GP64},
10519 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10520 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10521 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10522 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10524 /* ELF-specific options. */
10526 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10527 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10528 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10529 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10530 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10531 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10532 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10533 {"xgot", no_argument, NULL, OPTION_XGOT},
10534 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10535 {"mabi", required_argument, NULL, OPTION_MABI},
10536 #define OPTION_32 (OPTION_ELF_BASE + 4)
10537 {"32", no_argument, NULL, OPTION_32},
10538 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10539 {"n32", no_argument, NULL, OPTION_N32},
10540 #define OPTION_64 (OPTION_ELF_BASE + 6)
10541 {"64", no_argument, NULL, OPTION_64},
10542 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10543 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10544 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10545 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10546 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10547 {"mpdr", no_argument, NULL, OPTION_PDR},
10548 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10549 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10550 #endif /* OBJ_ELF */
10552 {NULL, no_argument, NULL, 0}
10554 size_t md_longopts_size = sizeof (md_longopts);
10556 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10557 NEW_VALUE. Warn if another value was already specified. Note:
10558 we have to defer parsing the -march and -mtune arguments in order
10559 to handle 'from-abi' correctly, since the ABI might be specified
10560 in a later argument. */
10563 mips_set_option_string (const char **string_ptr, const char *new_value)
10565 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10566 as_warn (_("A different %s was already specified, is now %s"),
10567 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10570 *string_ptr = new_value;
10574 md_parse_option (int c, char *arg)
10578 case OPTION_CONSTRUCT_FLOATS:
10579 mips_disable_float_construction = 0;
10582 case OPTION_NO_CONSTRUCT_FLOATS:
10583 mips_disable_float_construction = 1;
10595 target_big_endian = 1;
10599 target_big_endian = 0;
10607 if (arg && arg[1] == '0')
10617 mips_debug = atoi (arg);
10618 /* When the MIPS assembler sees -g or -g2, it does not do
10619 optimizations which limit full symbolic debugging. We take
10620 that to be equivalent to -O0. */
10621 if (mips_debug == 2)
10626 file_mips_isa = ISA_MIPS1;
10630 file_mips_isa = ISA_MIPS2;
10634 file_mips_isa = ISA_MIPS3;
10638 file_mips_isa = ISA_MIPS4;
10642 file_mips_isa = ISA_MIPS5;
10645 case OPTION_MIPS32:
10646 file_mips_isa = ISA_MIPS32;
10649 case OPTION_MIPS32R2:
10650 file_mips_isa = ISA_MIPS32R2;
10653 case OPTION_MIPS64R2:
10654 file_mips_isa = ISA_MIPS64R2;
10657 case OPTION_MIPS64:
10658 file_mips_isa = ISA_MIPS64;
10662 mips_set_option_string (&mips_tune_string, arg);
10666 mips_set_option_string (&mips_arch_string, arg);
10670 mips_set_option_string (&mips_arch_string, "4650");
10671 mips_set_option_string (&mips_tune_string, "4650");
10674 case OPTION_NO_M4650:
10678 mips_set_option_string (&mips_arch_string, "4010");
10679 mips_set_option_string (&mips_tune_string, "4010");
10682 case OPTION_NO_M4010:
10686 mips_set_option_string (&mips_arch_string, "4100");
10687 mips_set_option_string (&mips_tune_string, "4100");
10690 case OPTION_NO_M4100:
10694 mips_set_option_string (&mips_arch_string, "3900");
10695 mips_set_option_string (&mips_tune_string, "3900");
10698 case OPTION_NO_M3900:
10702 mips_opts.ase_mdmx = 1;
10705 case OPTION_NO_MDMX:
10706 mips_opts.ase_mdmx = 0;
10709 case OPTION_MIPS16:
10710 mips_opts.mips16 = 1;
10711 mips_no_prev_insn (FALSE);
10714 case OPTION_NO_MIPS16:
10715 mips_opts.mips16 = 0;
10716 mips_no_prev_insn (FALSE);
10719 case OPTION_MIPS3D:
10720 mips_opts.ase_mips3d = 1;
10723 case OPTION_NO_MIPS3D:
10724 mips_opts.ase_mips3d = 0;
10727 case OPTION_MEMBEDDED_PIC:
10728 mips_pic = EMBEDDED_PIC;
10729 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10731 as_bad (_("-G may not be used with embedded PIC code"));
10734 g_switch_value = 0x7fffffff;
10737 case OPTION_FIX_VR4122:
10738 mips_fix_4122_bugs = 1;
10741 case OPTION_NO_FIX_VR4122:
10742 mips_fix_4122_bugs = 0;
10745 case OPTION_RELAX_BRANCH:
10746 mips_relax_branch = 1;
10749 case OPTION_NO_RELAX_BRANCH:
10750 mips_relax_branch = 0;
10754 /* When generating ELF code, we permit -KPIC and -call_shared to
10755 select SVR4_PIC, and -non_shared to select no PIC. This is
10756 intended to be compatible with Irix 5. */
10757 case OPTION_CALL_SHARED:
10758 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10760 as_bad (_("-call_shared is supported only for ELF format"));
10763 mips_pic = SVR4_PIC;
10764 mips_abicalls = TRUE;
10765 if (g_switch_seen && g_switch_value != 0)
10767 as_bad (_("-G may not be used with SVR4 PIC code"));
10770 g_switch_value = 0;
10773 case OPTION_NON_SHARED:
10774 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10776 as_bad (_("-non_shared is supported only for ELF format"));
10780 mips_abicalls = FALSE;
10783 /* The -xgot option tells the assembler to use 32 offsets when
10784 accessing the got in SVR4_PIC mode. It is for Irix
10789 #endif /* OBJ_ELF */
10792 if (! USE_GLOBAL_POINTER_OPT)
10794 as_bad (_("-G is not supported for this configuration"));
10797 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10799 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10803 g_switch_value = atoi (arg);
10808 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10811 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10813 as_bad (_("-32 is supported for ELF format only"));
10816 mips_abi = O32_ABI;
10820 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10822 as_bad (_("-n32 is supported for ELF format only"));
10825 mips_abi = N32_ABI;
10829 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10831 as_bad (_("-64 is supported for ELF format only"));
10834 mips_abi = N64_ABI;
10835 if (! support_64bit_objects())
10836 as_fatal (_("No compiled in support for 64 bit object file format"));
10838 #endif /* OBJ_ELF */
10841 file_mips_gp32 = 1;
10845 file_mips_gp32 = 0;
10849 file_mips_fp32 = 1;
10853 file_mips_fp32 = 0;
10858 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10860 as_bad (_("-mabi is supported for ELF format only"));
10863 if (strcmp (arg, "32") == 0)
10864 mips_abi = O32_ABI;
10865 else if (strcmp (arg, "o64") == 0)
10866 mips_abi = O64_ABI;
10867 else if (strcmp (arg, "n32") == 0)
10868 mips_abi = N32_ABI;
10869 else if (strcmp (arg, "64") == 0)
10871 mips_abi = N64_ABI;
10872 if (! support_64bit_objects())
10873 as_fatal (_("No compiled in support for 64 bit object file "
10876 else if (strcmp (arg, "eabi") == 0)
10877 mips_abi = EABI_ABI;
10880 as_fatal (_("invalid abi -mabi=%s"), arg);
10884 #endif /* OBJ_ELF */
10886 case OPTION_M7000_HILO_FIX:
10887 mips_7000_hilo_fix = TRUE;
10890 case OPTION_MNO_7000_HILO_FIX:
10891 mips_7000_hilo_fix = FALSE;
10895 case OPTION_MDEBUG:
10896 mips_flag_mdebug = TRUE;
10899 case OPTION_NO_MDEBUG:
10900 mips_flag_mdebug = FALSE;
10904 mips_flag_pdr = TRUE;
10907 case OPTION_NO_PDR:
10908 mips_flag_pdr = FALSE;
10910 #endif /* OBJ_ELF */
10919 /* Set up globals to generate code for the ISA or processor
10920 described by INFO. */
10923 mips_set_architecture (const struct mips_cpu_info *info)
10927 file_mips_arch = info->cpu;
10928 mips_opts.arch = info->cpu;
10929 mips_opts.isa = info->isa;
10934 /* Likewise for tuning. */
10937 mips_set_tune (const struct mips_cpu_info *info)
10940 mips_tune = info->cpu;
10945 mips_after_parse_args (void)
10947 const struct mips_cpu_info *arch_info = 0;
10948 const struct mips_cpu_info *tune_info = 0;
10950 /* GP relative stuff not working for PE */
10951 if (strncmp (TARGET_OS, "pe", 2) == 0
10952 && g_switch_value != 0)
10955 as_bad (_("-G not supported in this configuration."));
10956 g_switch_value = 0;
10959 if (mips_abi == NO_ABI)
10960 mips_abi = MIPS_DEFAULT_ABI;
10962 /* The following code determines the architecture and register size.
10963 Similar code was added to GCC 3.3 (see override_options() in
10964 config/mips/mips.c). The GAS and GCC code should be kept in sync
10965 as much as possible. */
10967 if (mips_arch_string != 0)
10968 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10970 if (file_mips_isa != ISA_UNKNOWN)
10972 /* Handle -mipsN. At this point, file_mips_isa contains the
10973 ISA level specified by -mipsN, while arch_info->isa contains
10974 the -march selection (if any). */
10975 if (arch_info != 0)
10977 /* -march takes precedence over -mipsN, since it is more descriptive.
10978 There's no harm in specifying both as long as the ISA levels
10980 if (file_mips_isa != arch_info->isa)
10981 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10982 mips_cpu_info_from_isa (file_mips_isa)->name,
10983 mips_cpu_info_from_isa (arch_info->isa)->name);
10986 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10989 if (arch_info == 0)
10990 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10992 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10993 as_bad ("-march=%s is not compatible with the selected ABI",
10996 mips_set_architecture (arch_info);
10998 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10999 if (mips_tune_string != 0)
11000 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11002 if (tune_info == 0)
11003 mips_set_tune (arch_info);
11005 mips_set_tune (tune_info);
11007 if (file_mips_gp32 >= 0)
11009 /* The user specified the size of the integer registers. Make sure
11010 it agrees with the ABI and ISA. */
11011 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11012 as_bad (_("-mgp64 used with a 32-bit processor"));
11013 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11014 as_bad (_("-mgp32 used with a 64-bit ABI"));
11015 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11016 as_bad (_("-mgp64 used with a 32-bit ABI"));
11020 /* Infer the integer register size from the ABI and processor.
11021 Restrict ourselves to 32-bit registers if that's all the
11022 processor has, or if the ABI cannot handle 64-bit registers. */
11023 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11024 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11027 /* ??? GAS treats single-float processors as though they had 64-bit
11028 float registers (although it complains when double-precision
11029 instructions are used). As things stand, saying they have 32-bit
11030 registers would lead to spurious "register must be even" messages.
11031 So here we assume float registers are always the same size as
11032 integer ones, unless the user says otherwise. */
11033 if (file_mips_fp32 < 0)
11034 file_mips_fp32 = file_mips_gp32;
11036 /* End of GCC-shared inference code. */
11038 /* This flag is set when we have a 64-bit capable CPU but use only
11039 32-bit wide registers. Note that EABI does not use it. */
11040 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11041 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11042 || mips_abi == O32_ABI))
11043 mips_32bitmode = 1;
11045 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11046 as_bad (_("trap exception not supported at ISA 1"));
11048 /* If the selected architecture includes support for ASEs, enable
11049 generation of code for them. */
11050 if (mips_opts.mips16 == -1)
11051 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11052 if (mips_opts.ase_mips3d == -1)
11053 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
11054 if (mips_opts.ase_mdmx == -1)
11055 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
11057 file_mips_isa = mips_opts.isa;
11058 file_ase_mips16 = mips_opts.mips16;
11059 file_ase_mips3d = mips_opts.ase_mips3d;
11060 file_ase_mdmx = mips_opts.ase_mdmx;
11061 mips_opts.gp32 = file_mips_gp32;
11062 mips_opts.fp32 = file_mips_fp32;
11064 if (mips_flag_mdebug < 0)
11066 #ifdef OBJ_MAYBE_ECOFF
11067 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
11068 mips_flag_mdebug = 1;
11070 #endif /* OBJ_MAYBE_ECOFF */
11071 mips_flag_mdebug = 0;
11076 mips_init_after_args (void)
11078 /* initialize opcodes */
11079 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
11080 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
11084 md_pcrel_from (fixS *fixP)
11086 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11087 switch (fixP->fx_r_type)
11089 case BFD_RELOC_16_PCREL_S2:
11090 case BFD_RELOC_MIPS_JMP:
11091 /* Return the address of the delay slot. */
11098 /* This is called before the symbol table is processed. In order to
11099 work with gcc when using mips-tfile, we must keep all local labels.
11100 However, in other cases, we want to discard them. If we were
11101 called with -g, but we didn't see any debugging information, it may
11102 mean that gcc is smuggling debugging information through to
11103 mips-tfile, in which case we must generate all local labels. */
11106 mips_frob_file_before_adjust (void)
11108 #ifndef NO_ECOFF_DEBUGGING
11109 if (ECOFF_DEBUGGING
11111 && ! ecoff_debugging_seen)
11112 flag_keep_locals = 1;
11116 /* Sort any unmatched HI16_S relocs so that they immediately precede
11117 the corresponding LO reloc. This is called before md_apply_fix3 and
11118 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11119 explicit use of the %hi modifier. */
11122 mips_frob_file (void)
11124 struct mips_hi_fixup *l;
11126 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
11128 segment_info_type *seginfo;
11131 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
11133 /* If a GOT16 relocation turns out to be against a global symbol,
11134 there isn't supposed to be a matching LO. */
11135 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11136 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
11139 /* Check quickly whether the next fixup happens to be a matching %lo. */
11140 if (fixup_has_matching_lo_p (l->fixp))
11143 /* Look through the fixups for this segment for a matching %lo.
11144 When we find one, move the %hi just in front of it. We do
11145 this in two passes. In the first pass, we try to find a
11146 unique %lo. In the second pass, we permit multiple %hi
11147 relocs for a single %lo (this is a GNU extension). */
11148 seginfo = seg_info (l->seg);
11149 for (pass = 0; pass < 2; pass++)
11154 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
11156 /* Check whether this is a %lo fixup which matches l->fixp. */
11157 if (f->fx_r_type == BFD_RELOC_LO16
11158 && f->fx_addsy == l->fixp->fx_addsy
11159 && f->fx_offset == l->fixp->fx_offset
11162 || !reloc_needs_lo_p (prev->fx_r_type)
11163 || !fixup_has_matching_lo_p (prev)))
11167 /* Move l->fixp before f. */
11168 for (pf = &seginfo->fix_root;
11170 pf = &(*pf)->fx_next)
11171 assert (*pf != NULL);
11173 *pf = l->fixp->fx_next;
11175 l->fixp->fx_next = f;
11177 seginfo->fix_root = l->fixp;
11179 prev->fx_next = l->fixp;
11190 #if 0 /* GCC code motion plus incomplete dead code elimination
11191 can leave a %hi without a %lo. */
11193 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
11194 _("Unmatched %%hi reloc"));
11200 /* When generating embedded PIC code we need to use a special
11201 relocation to represent the difference of two symbols in the .text
11202 section (switch tables use a difference of this sort). See
11203 include/coff/mips.h for details. This macro checks whether this
11204 fixup requires the special reloc. */
11205 #define SWITCH_TABLE(fixp) \
11206 ((fixp)->fx_r_type == BFD_RELOC_32 \
11207 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11208 && (fixp)->fx_addsy != NULL \
11209 && (fixp)->fx_subsy != NULL \
11210 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11211 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11213 /* When generating embedded PIC code we must keep all PC relative
11214 relocations, in case the linker has to relax a call. We also need
11215 to keep relocations for switch table entries.
11217 We may have combined relocations without symbols in the N32/N64 ABI.
11218 We have to prevent gas from dropping them. */
11221 mips_force_relocation (fixS *fixp)
11223 if (generic_force_reloc (fixp))
11227 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11228 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11229 || fixp->fx_r_type == BFD_RELOC_HI16_S
11230 || fixp->fx_r_type == BFD_RELOC_LO16))
11233 return (mips_pic == EMBEDDED_PIC
11235 || SWITCH_TABLE (fixp)
11236 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11237 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11240 /* This hook is called before a fix is simplified. We don't really
11241 decide whether to skip a fix here. Rather, we turn global symbols
11242 used as branch targets into local symbols, such that they undergo
11243 simplification. We can only do this if the symbol is defined and
11244 it is in the same section as the branch. If this doesn't hold, we
11245 emit a better error message than just saying the relocation is not
11246 valid for the selected object format.
11248 FIXP is the fix-up we're going to try to simplify, SEG is the
11249 segment in which the fix up occurs. The return value should be
11250 non-zero to indicate the fix-up is valid for further
11251 simplifications. */
11254 mips_validate_fix (struct fix *fixP, asection *seg)
11256 /* There's a lot of discussion on whether it should be possible to
11257 use R_MIPS_PC16 to represent branch relocations. The outcome
11258 seems to be that it can, but gas/bfd are very broken in creating
11259 RELA relocations for this, so for now we only accept branches to
11260 symbols in the same section. Anything else is of dubious value,
11261 since there's no guarantee that at link time the symbol would be
11262 in range. Even for branches to local symbols this is arguably
11263 wrong, since it we assume the symbol is not going to be
11264 overridden, which should be possible per ELF library semantics,
11265 but then, there isn't a dynamic relocation that could be used to
11266 this effect, and the target would likely be out of range as well.
11268 Unfortunately, it seems that there is too much code out there
11269 that relies on branches to symbols that are global to be resolved
11270 as if they were local, like the IRIX tools do, so we do it as
11271 well, but with a warning so that people are reminded to fix their
11272 code. If we ever get back to using R_MIPS_PC16 for branch
11273 targets, this entire block should go away (and probably the
11274 whole function). */
11276 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11277 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11278 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11279 && mips_pic != EMBEDDED_PIC)
11280 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11283 if (! S_IS_DEFINED (fixP->fx_addsy))
11285 as_bad_where (fixP->fx_file, fixP->fx_line,
11286 _("Cannot branch to undefined symbol."));
11287 /* Avoid any further errors about this fixup. */
11290 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11292 as_bad_where (fixP->fx_file, fixP->fx_line,
11293 _("Cannot branch to symbol in another section."));
11296 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11298 symbolS *sym = fixP->fx_addsy;
11300 if (mips_pic == SVR4_PIC)
11301 as_warn_where (fixP->fx_file, fixP->fx_line,
11302 _("Pretending global symbol used as branch target is local."));
11304 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11305 S_GET_SEGMENT (sym),
11307 symbol_get_frag (sym));
11308 copy_symbol_attributes (fixP->fx_addsy, sym);
11309 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11310 assert (symbol_resolved_p (sym));
11311 symbol_mark_resolved (fixP->fx_addsy);
11320 mips_need_elf_addend_fixup (fixS *fixP)
11322 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
11324 if (mips_pic == EMBEDDED_PIC
11325 && S_IS_WEAK (fixP->fx_addsy))
11327 if (mips_pic != EMBEDDED_PIC
11328 && (S_IS_WEAK (fixP->fx_addsy)
11329 || S_IS_EXTERNAL (fixP->fx_addsy))
11330 && !S_IS_COMMON (fixP->fx_addsy))
11332 if (((bfd_get_section_flags (stdoutput,
11333 S_GET_SEGMENT (fixP->fx_addsy))
11334 & (SEC_LINK_ONCE | SEC_MERGE)) != 0)
11335 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
11337 sizeof (".gnu.linkonce") - 1))
11343 /* Apply a fixup to the object file. */
11346 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11350 static int previous_fx_r_type = 0;
11351 reloc_howto_type *howto;
11353 /* We ignore generic BFD relocations we don't know about. */
11354 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11358 assert (fixP->fx_size == 4
11359 || fixP->fx_r_type == BFD_RELOC_16
11360 || fixP->fx_r_type == BFD_RELOC_64
11361 || fixP->fx_r_type == BFD_RELOC_CTOR
11362 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11363 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11364 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11366 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11368 /* If we aren't adjusting this fixup to be against the section
11369 symbol, we need to adjust the value. */
11371 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
11373 if (mips_need_elf_addend_fixup (fixP)
11374 && howto->partial_inplace
11375 && fixP->fx_r_type != BFD_RELOC_GPREL16
11376 && fixP->fx_r_type != BFD_RELOC_GPREL32
11377 && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL)
11379 /* In this case, the bfd_install_relocation routine will
11380 incorrectly add the symbol value back in. We just want
11381 the addend to appear in the object file.
11383 The condition above used to include
11384 "&& (! fixP->fx_pcrel || howto->pcrel_offset)".
11386 However, howto can't be trusted here, because we
11387 might change the reloc type in tc_gen_reloc. We can
11388 check howto->partial_inplace because that conversion
11389 happens to preserve howto->partial_inplace; but it
11390 does not preserve howto->pcrel_offset. I've just
11391 eliminated the check, because all MIPS PC-relative
11392 relocations are marked howto->pcrel_offset.
11394 howto->pcrel_offset was originally added for
11395 R_MIPS_PC16, which is generated for code like
11404 *valP -= S_GET_VALUE (fixP->fx_addsy);
11407 /* This code was generated using trial and error and so is
11408 fragile and not trustworthy. If you change it, you should
11409 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11410 they still pass. */
11411 if (fixP->fx_pcrel)
11413 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11415 /* BFD's REL handling, for MIPS, is _very_ weird.
11416 This gives the right results, but it can't possibly
11417 be the way things are supposed to work. */
11418 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11423 /* We are not done if this is a composite relocation to set up gp. */
11424 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11425 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11426 || (fixP->fx_r_type == BFD_RELOC_64
11427 && (previous_fx_r_type == BFD_RELOC_GPREL32
11428 || previous_fx_r_type == BFD_RELOC_GPREL16))
11429 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11430 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11431 || fixP->fx_r_type == BFD_RELOC_LO16))))
11433 previous_fx_r_type = fixP->fx_r_type;
11435 switch (fixP->fx_r_type)
11437 case BFD_RELOC_MIPS_JMP:
11438 case BFD_RELOC_MIPS_SHIFT5:
11439 case BFD_RELOC_MIPS_SHIFT6:
11440 case BFD_RELOC_MIPS_GOT_DISP:
11441 case BFD_RELOC_MIPS_GOT_PAGE:
11442 case BFD_RELOC_MIPS_GOT_OFST:
11443 case BFD_RELOC_MIPS_SUB:
11444 case BFD_RELOC_MIPS_INSERT_A:
11445 case BFD_RELOC_MIPS_INSERT_B:
11446 case BFD_RELOC_MIPS_DELETE:
11447 case BFD_RELOC_MIPS_HIGHEST:
11448 case BFD_RELOC_MIPS_HIGHER:
11449 case BFD_RELOC_MIPS_SCN_DISP:
11450 case BFD_RELOC_MIPS_REL16:
11451 case BFD_RELOC_MIPS_RELGOT:
11452 case BFD_RELOC_MIPS_JALR:
11453 case BFD_RELOC_HI16:
11454 case BFD_RELOC_HI16_S:
11455 case BFD_RELOC_GPREL16:
11456 case BFD_RELOC_MIPS_LITERAL:
11457 case BFD_RELOC_MIPS_CALL16:
11458 case BFD_RELOC_MIPS_GOT16:
11459 case BFD_RELOC_GPREL32:
11460 case BFD_RELOC_MIPS_GOT_HI16:
11461 case BFD_RELOC_MIPS_GOT_LO16:
11462 case BFD_RELOC_MIPS_CALL_HI16:
11463 case BFD_RELOC_MIPS_CALL_LO16:
11464 case BFD_RELOC_MIPS16_GPREL:
11465 if (fixP->fx_pcrel)
11466 as_bad_where (fixP->fx_file, fixP->fx_line,
11467 _("Invalid PC relative reloc"));
11468 /* Nothing needed to do. The value comes from the reloc entry */
11471 case BFD_RELOC_MIPS16_JMP:
11472 /* We currently always generate a reloc against a symbol, which
11473 means that we don't want an addend even if the symbol is
11478 case BFD_RELOC_PCREL_HI16_S:
11479 /* The addend for this is tricky if it is internal, so we just
11480 do everything here rather than in bfd_install_relocation. */
11481 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11484 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11486 /* For an external symbol adjust by the address to make it
11487 pcrel_offset. We use the address of the RELLO reloc
11488 which follows this one. */
11489 *valP += (fixP->fx_next->fx_frag->fr_address
11490 + fixP->fx_next->fx_where);
11492 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11493 if (target_big_endian)
11495 md_number_to_chars (buf, *valP, 2);
11498 case BFD_RELOC_PCREL_LO16:
11499 /* The addend for this is tricky if it is internal, so we just
11500 do everything here rather than in bfd_install_relocation. */
11501 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11504 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11505 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11506 if (target_big_endian)
11508 md_number_to_chars (buf, *valP, 2);
11512 /* This is handled like BFD_RELOC_32, but we output a sign
11513 extended value if we are only 32 bits. */
11515 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11517 if (8 <= sizeof (valueT))
11518 md_number_to_chars (buf, *valP, 8);
11523 if ((*valP & 0x80000000) != 0)
11527 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11529 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11535 case BFD_RELOC_RVA:
11537 /* If we are deleting this reloc entry, we must fill in the
11538 value now. This can happen if we have a .word which is not
11539 resolved when it appears but is later defined. We also need
11540 to fill in the value if this is an embedded PIC switch table
11543 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11544 md_number_to_chars (buf, *valP, 4);
11548 /* If we are deleting this reloc entry, we must fill in the
11550 assert (fixP->fx_size == 2);
11552 md_number_to_chars (buf, *valP, 2);
11555 case BFD_RELOC_LO16:
11556 /* When handling an embedded PIC switch statement, we can wind
11557 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11560 if (*valP + 0x8000 > 0xffff)
11561 as_bad_where (fixP->fx_file, fixP->fx_line,
11562 _("relocation overflow"));
11563 if (target_big_endian)
11565 md_number_to_chars (buf, *valP, 2);
11569 case BFD_RELOC_16_PCREL_S2:
11570 if ((*valP & 0x3) != 0)
11571 as_bad_where (fixP->fx_file, fixP->fx_line,
11572 _("Branch to odd address (%lx)"), (long) *valP);
11575 * We need to save the bits in the instruction since fixup_segment()
11576 * might be deleting the relocation entry (i.e., a branch within
11577 * the current segment).
11579 if (! fixP->fx_done)
11582 /* update old instruction data */
11583 if (target_big_endian)
11584 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11586 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11588 if (*valP + 0x20000 <= 0x3ffff)
11590 insn |= (*valP >> 2) & 0xffff;
11591 md_number_to_chars (buf, insn, 4);
11593 else if (mips_pic == NO_PIC
11595 && fixP->fx_frag->fr_address >= text_section->vma
11596 && (fixP->fx_frag->fr_address
11597 < text_section->vma + text_section->_raw_size)
11598 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11599 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11600 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11602 /* The branch offset is too large. If this is an
11603 unconditional branch, and we are not generating PIC code,
11604 we can convert it to an absolute jump instruction. */
11605 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11606 insn = 0x0c000000; /* jal */
11608 insn = 0x08000000; /* j */
11609 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11611 fixP->fx_addsy = section_symbol (text_section);
11612 *valP += md_pcrel_from (fixP);
11613 md_number_to_chars (buf, insn, 4);
11617 /* If we got here, we have branch-relaxation disabled,
11618 and there's nothing we can do to fix this instruction
11619 without turning it into a longer sequence. */
11620 as_bad_where (fixP->fx_file, fixP->fx_line,
11621 _("Branch out of range"));
11625 case BFD_RELOC_VTABLE_INHERIT:
11628 && !S_IS_DEFINED (fixP->fx_addsy)
11629 && !S_IS_WEAK (fixP->fx_addsy))
11630 S_SET_WEAK (fixP->fx_addsy);
11633 case BFD_RELOC_VTABLE_ENTRY:
11641 /* Remember value for tc_gen_reloc. */
11642 fixP->fx_addnumber = *valP;
11647 printInsn (unsigned long oc)
11649 const struct mips_opcode *p;
11650 int treg, sreg, dreg, shamt;
11655 for (i = 0; i < NUMOPCODES; ++i)
11657 p = &mips_opcodes[i];
11658 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11660 printf ("%08lx %s\t", oc, p->name);
11661 treg = (oc >> 16) & 0x1f;
11662 sreg = (oc >> 21) & 0x1f;
11663 dreg = (oc >> 11) & 0x1f;
11664 shamt = (oc >> 6) & 0x1f;
11666 for (args = p->args;; ++args)
11677 printf ("%c", *args);
11681 assert (treg == sreg);
11682 printf ("$%d,$%d", treg, sreg);
11687 printf ("$%d", dreg);
11692 printf ("$%d", treg);
11696 printf ("0x%x", treg);
11701 printf ("$%d", sreg);
11705 printf ("0x%08lx", oc & 0x1ffffff);
11712 printf ("%d", imm);
11717 printf ("$%d", shamt);
11728 printf (_("%08lx UNDEFINED\n"), oc);
11739 name = input_line_pointer;
11740 c = get_symbol_end ();
11741 p = (symbolS *) symbol_find_or_make (name);
11742 *input_line_pointer = c;
11746 /* Align the current frag to a given power of two. The MIPS assembler
11747 also automatically adjusts any preceding label. */
11750 mips_align (int to, int fill, symbolS *label)
11752 mips_emit_delays (FALSE);
11753 frag_align (to, fill, 0);
11754 record_alignment (now_seg, to);
11757 assert (S_GET_SEGMENT (label) == now_seg);
11758 symbol_set_frag (label, frag_now);
11759 S_SET_VALUE (label, (valueT) frag_now_fix ());
11763 /* Align to a given power of two. .align 0 turns off the automatic
11764 alignment used by the data creating pseudo-ops. */
11767 s_align (int x ATTRIBUTE_UNUSED)
11770 register long temp_fill;
11771 long max_alignment = 15;
11775 o Note that the assembler pulls down any immediately preceeding label
11776 to the aligned address.
11777 o It's not documented but auto alignment is reinstated by
11778 a .align pseudo instruction.
11779 o Note also that after auto alignment is turned off the mips assembler
11780 issues an error on attempt to assemble an improperly aligned data item.
11785 temp = get_absolute_expression ();
11786 if (temp > max_alignment)
11787 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11790 as_warn (_("Alignment negative: 0 assumed."));
11793 if (*input_line_pointer == ',')
11795 ++input_line_pointer;
11796 temp_fill = get_absolute_expression ();
11803 mips_align (temp, (int) temp_fill,
11804 insn_labels != NULL ? insn_labels->label : NULL);
11811 demand_empty_rest_of_line ();
11815 mips_flush_pending_output (void)
11817 mips_emit_delays (FALSE);
11818 mips_clear_insn_labels ();
11822 s_change_sec (int sec)
11826 /* When generating embedded PIC code, we only use the .text, .lit8,
11827 .sdata and .sbss sections. We change the .data and .rdata
11828 pseudo-ops to use .sdata. */
11829 if (mips_pic == EMBEDDED_PIC
11830 && (sec == 'd' || sec == 'r'))
11834 /* The ELF backend needs to know that we are changing sections, so
11835 that .previous works correctly. We could do something like check
11836 for an obj_section_change_hook macro, but that might be confusing
11837 as it would not be appropriate to use it in the section changing
11838 functions in read.c, since obj-elf.c intercepts those. FIXME:
11839 This should be cleaner, somehow. */
11840 obj_elf_section_change_hook ();
11843 mips_emit_delays (FALSE);
11853 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11854 demand_empty_rest_of_line ();
11858 if (USE_GLOBAL_POINTER_OPT)
11860 seg = subseg_new (RDATA_SECTION_NAME,
11861 (subsegT) get_absolute_expression ());
11862 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11864 bfd_set_section_flags (stdoutput, seg,
11870 if (strcmp (TARGET_OS, "elf") != 0)
11871 record_alignment (seg, 4);
11873 demand_empty_rest_of_line ();
11877 as_bad (_("No read only data section in this object file format"));
11878 demand_empty_rest_of_line ();
11884 if (USE_GLOBAL_POINTER_OPT)
11886 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11887 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11889 bfd_set_section_flags (stdoutput, seg,
11890 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11892 if (strcmp (TARGET_OS, "elf") != 0)
11893 record_alignment (seg, 4);
11895 demand_empty_rest_of_line ();
11900 as_bad (_("Global pointers not supported; recompile -G 0"));
11901 demand_empty_rest_of_line ();
11910 s_change_section (int ignore ATTRIBUTE_UNUSED)
11913 char *section_name;
11918 int section_entry_size;
11919 int section_alignment;
11921 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11924 section_name = input_line_pointer;
11925 c = get_symbol_end ();
11927 next_c = *(input_line_pointer + 1);
11929 /* Do we have .section Name<,"flags">? */
11930 if (c != ',' || (c == ',' && next_c == '"'))
11932 /* just after name is now '\0'. */
11933 *input_line_pointer = c;
11934 input_line_pointer = section_name;
11935 obj_elf_section (ignore);
11938 input_line_pointer++;
11940 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11942 section_type = get_absolute_expression ();
11945 if (*input_line_pointer++ == ',')
11946 section_flag = get_absolute_expression ();
11949 if (*input_line_pointer++ == ',')
11950 section_entry_size = get_absolute_expression ();
11952 section_entry_size = 0;
11953 if (*input_line_pointer++ == ',')
11954 section_alignment = get_absolute_expression ();
11956 section_alignment = 0;
11958 section_name = xstrdup (section_name);
11960 obj_elf_change_section (section_name, section_type, section_flag,
11961 section_entry_size, 0, 0, 0);
11963 if (now_seg->name != section_name)
11964 free (section_name);
11965 #endif /* OBJ_ELF */
11969 mips_enable_auto_align (void)
11975 s_cons (int log_size)
11979 label = insn_labels != NULL ? insn_labels->label : NULL;
11980 mips_emit_delays (FALSE);
11981 if (log_size > 0 && auto_align)
11982 mips_align (log_size, 0, label);
11983 mips_clear_insn_labels ();
11984 cons (1 << log_size);
11988 s_float_cons (int type)
11992 label = insn_labels != NULL ? insn_labels->label : NULL;
11994 mips_emit_delays (FALSE);
11999 mips_align (3, 0, label);
12001 mips_align (2, 0, label);
12004 mips_clear_insn_labels ();
12009 /* Handle .globl. We need to override it because on Irix 5 you are
12012 where foo is an undefined symbol, to mean that foo should be
12013 considered to be the address of a function. */
12016 s_mips_globl (int x ATTRIBUTE_UNUSED)
12023 name = input_line_pointer;
12024 c = get_symbol_end ();
12025 symbolP = symbol_find_or_make (name);
12026 *input_line_pointer = c;
12027 SKIP_WHITESPACE ();
12029 /* On Irix 5, every global symbol that is not explicitly labelled as
12030 being a function is apparently labelled as being an object. */
12033 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12038 secname = input_line_pointer;
12039 c = get_symbol_end ();
12040 sec = bfd_get_section_by_name (stdoutput, secname);
12042 as_bad (_("%s: no such section"), secname);
12043 *input_line_pointer = c;
12045 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12046 flag = BSF_FUNCTION;
12049 symbol_get_bfdsym (symbolP)->flags |= flag;
12051 S_SET_EXTERNAL (symbolP);
12052 demand_empty_rest_of_line ();
12056 s_option (int x ATTRIBUTE_UNUSED)
12061 opt = input_line_pointer;
12062 c = get_symbol_end ();
12066 /* FIXME: What does this mean? */
12068 else if (strncmp (opt, "pic", 3) == 0)
12072 i = atoi (opt + 3);
12077 mips_pic = SVR4_PIC;
12078 mips_abicalls = TRUE;
12081 as_bad (_(".option pic%d not supported"), i);
12083 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
12085 if (g_switch_seen && g_switch_value != 0)
12086 as_warn (_("-G may not be used with SVR4 PIC code"));
12087 g_switch_value = 0;
12088 bfd_set_gp_size (stdoutput, 0);
12092 as_warn (_("Unrecognized option \"%s\""), opt);
12094 *input_line_pointer = c;
12095 demand_empty_rest_of_line ();
12098 /* This structure is used to hold a stack of .set values. */
12100 struct mips_option_stack
12102 struct mips_option_stack *next;
12103 struct mips_set_options options;
12106 static struct mips_option_stack *mips_opts_stack;
12108 /* Handle the .set pseudo-op. */
12111 s_mipsset (int x ATTRIBUTE_UNUSED)
12113 char *name = input_line_pointer, ch;
12115 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12116 ++input_line_pointer;
12117 ch = *input_line_pointer;
12118 *input_line_pointer = '\0';
12120 if (strcmp (name, "reorder") == 0)
12122 if (mips_opts.noreorder && prev_nop_frag != NULL)
12124 /* If we still have pending nops, we can discard them. The
12125 usual nop handling will insert any that are still
12127 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12128 * (mips_opts.mips16 ? 2 : 4));
12129 prev_nop_frag = NULL;
12131 mips_opts.noreorder = 0;
12133 else if (strcmp (name, "noreorder") == 0)
12135 mips_emit_delays (TRUE);
12136 mips_opts.noreorder = 1;
12137 mips_any_noreorder = 1;
12139 else if (strcmp (name, "at") == 0)
12141 mips_opts.noat = 0;
12143 else if (strcmp (name, "noat") == 0)
12145 mips_opts.noat = 1;
12147 else if (strcmp (name, "macro") == 0)
12149 mips_opts.warn_about_macros = 0;
12151 else if (strcmp (name, "nomacro") == 0)
12153 if (mips_opts.noreorder == 0)
12154 as_bad (_("`noreorder' must be set before `nomacro'"));
12155 mips_opts.warn_about_macros = 1;
12157 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12159 mips_opts.nomove = 0;
12161 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12163 mips_opts.nomove = 1;
12165 else if (strcmp (name, "bopt") == 0)
12167 mips_opts.nobopt = 0;
12169 else if (strcmp (name, "nobopt") == 0)
12171 mips_opts.nobopt = 1;
12173 else if (strcmp (name, "mips16") == 0
12174 || strcmp (name, "MIPS-16") == 0)
12175 mips_opts.mips16 = 1;
12176 else if (strcmp (name, "nomips16") == 0
12177 || strcmp (name, "noMIPS-16") == 0)
12178 mips_opts.mips16 = 0;
12179 else if (strcmp (name, "mips3d") == 0)
12180 mips_opts.ase_mips3d = 1;
12181 else if (strcmp (name, "nomips3d") == 0)
12182 mips_opts.ase_mips3d = 0;
12183 else if (strcmp (name, "mdmx") == 0)
12184 mips_opts.ase_mdmx = 1;
12185 else if (strcmp (name, "nomdmx") == 0)
12186 mips_opts.ase_mdmx = 0;
12187 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12191 /* Permit the user to change the ISA and architecture on the fly.
12192 Needless to say, misuse can cause serious problems. */
12193 if (strcmp (name, "mips0") == 0)
12196 mips_opts.isa = file_mips_isa;
12198 else if (strcmp (name, "mips1") == 0)
12199 mips_opts.isa = ISA_MIPS1;
12200 else if (strcmp (name, "mips2") == 0)
12201 mips_opts.isa = ISA_MIPS2;
12202 else if (strcmp (name, "mips3") == 0)
12203 mips_opts.isa = ISA_MIPS3;
12204 else if (strcmp (name, "mips4") == 0)
12205 mips_opts.isa = ISA_MIPS4;
12206 else if (strcmp (name, "mips5") == 0)
12207 mips_opts.isa = ISA_MIPS5;
12208 else if (strcmp (name, "mips32") == 0)
12209 mips_opts.isa = ISA_MIPS32;
12210 else if (strcmp (name, "mips32r2") == 0)
12211 mips_opts.isa = ISA_MIPS32R2;
12212 else if (strcmp (name, "mips64") == 0)
12213 mips_opts.isa = ISA_MIPS64;
12214 else if (strcmp (name, "mips64r2") == 0)
12215 mips_opts.isa = ISA_MIPS64R2;
12216 else if (strcmp (name, "arch=default") == 0)
12219 mips_opts.arch = file_mips_arch;
12220 mips_opts.isa = file_mips_isa;
12222 else if (strncmp (name, "arch=", 5) == 0)
12224 const struct mips_cpu_info *p;
12226 p = mips_parse_cpu("internal use", name + 5);
12228 as_bad (_("unknown architecture %s"), name + 5);
12231 mips_opts.arch = p->cpu;
12232 mips_opts.isa = p->isa;
12236 as_bad (_("unknown ISA level %s"), name + 4);
12238 switch (mips_opts.isa)
12246 mips_opts.gp32 = 1;
12247 mips_opts.fp32 = 1;
12254 mips_opts.gp32 = 0;
12255 mips_opts.fp32 = 0;
12258 as_bad (_("unknown ISA level %s"), name + 4);
12263 mips_opts.gp32 = file_mips_gp32;
12264 mips_opts.fp32 = file_mips_fp32;
12267 else if (strcmp (name, "autoextend") == 0)
12268 mips_opts.noautoextend = 0;
12269 else if (strcmp (name, "noautoextend") == 0)
12270 mips_opts.noautoextend = 1;
12271 else if (strcmp (name, "push") == 0)
12273 struct mips_option_stack *s;
12275 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12276 s->next = mips_opts_stack;
12277 s->options = mips_opts;
12278 mips_opts_stack = s;
12280 else if (strcmp (name, "pop") == 0)
12282 struct mips_option_stack *s;
12284 s = mips_opts_stack;
12286 as_bad (_(".set pop with no .set push"));
12289 /* If we're changing the reorder mode we need to handle
12290 delay slots correctly. */
12291 if (s->options.noreorder && ! mips_opts.noreorder)
12292 mips_emit_delays (TRUE);
12293 else if (! s->options.noreorder && mips_opts.noreorder)
12295 if (prev_nop_frag != NULL)
12297 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12298 * (mips_opts.mips16 ? 2 : 4));
12299 prev_nop_frag = NULL;
12303 mips_opts = s->options;
12304 mips_opts_stack = s->next;
12310 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12312 *input_line_pointer = ch;
12313 demand_empty_rest_of_line ();
12316 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12317 .option pic2. It means to generate SVR4 PIC calls. */
12320 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12322 mips_pic = SVR4_PIC;
12323 mips_abicalls = TRUE;
12324 if (USE_GLOBAL_POINTER_OPT)
12326 if (g_switch_seen && g_switch_value != 0)
12327 as_warn (_("-G may not be used with SVR4 PIC code"));
12328 g_switch_value = 0;
12330 bfd_set_gp_size (stdoutput, 0);
12331 demand_empty_rest_of_line ();
12334 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12335 PIC code. It sets the $gp register for the function based on the
12336 function address, which is in the register named in the argument.
12337 This uses a relocation against _gp_disp, which is handled specially
12338 by the linker. The result is:
12339 lui $gp,%hi(_gp_disp)
12340 addiu $gp,$gp,%lo(_gp_disp)
12341 addu $gp,$gp,.cpload argument
12342 The .cpload argument is normally $25 == $t9. */
12345 s_cpload (int ignore ATTRIBUTE_UNUSED)
12350 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12351 .cpload is ignored. */
12352 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12358 /* .cpload should be in a .set noreorder section. */
12359 if (mips_opts.noreorder == 0)
12360 as_warn (_(".cpload not in noreorder section"));
12362 ex.X_op = O_symbol;
12363 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12364 ex.X_op_symbol = NULL;
12365 ex.X_add_number = 0;
12367 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12368 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12370 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12371 macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
12372 mips_gp_register, BFD_RELOC_LO16);
12374 macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
12375 mips_gp_register, tc_get_register (0));
12377 demand_empty_rest_of_line ();
12380 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12381 .cpsetup $reg1, offset|$reg2, label
12383 If offset is given, this results in:
12384 sd $gp, offset($sp)
12385 lui $gp, %hi(%neg(%gp_rel(label)))
12386 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12387 daddu $gp, $gp, $reg1
12389 If $reg2 is given, this results in:
12390 daddu $reg2, $gp, $0
12391 lui $gp, %hi(%neg(%gp_rel(label)))
12392 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12393 daddu $gp, $gp, $reg1
12394 $reg1 is normally $25 == $t9. */
12396 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12398 expressionS ex_off;
12399 expressionS ex_sym;
12404 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12405 We also need NewABI support. */
12406 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12412 reg1 = tc_get_register (0);
12413 SKIP_WHITESPACE ();
12414 if (*input_line_pointer != ',')
12416 as_bad (_("missing argument separator ',' for .cpsetup"));
12420 ++input_line_pointer;
12421 SKIP_WHITESPACE ();
12422 if (*input_line_pointer == '$')
12424 mips_cpreturn_register = tc_get_register (0);
12425 mips_cpreturn_offset = -1;
12429 mips_cpreturn_offset = get_absolute_expression ();
12430 mips_cpreturn_register = -1;
12432 SKIP_WHITESPACE ();
12433 if (*input_line_pointer != ',')
12435 as_bad (_("missing argument separator ',' for .cpsetup"));
12439 ++input_line_pointer;
12440 SKIP_WHITESPACE ();
12441 expression (&ex_sym);
12443 if (mips_cpreturn_register == -1)
12445 ex_off.X_op = O_constant;
12446 ex_off.X_add_symbol = NULL;
12447 ex_off.X_op_symbol = NULL;
12448 ex_off.X_add_number = mips_cpreturn_offset;
12450 macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
12451 BFD_RELOC_LO16, SP);
12454 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
12455 mips_gp_register, 0);
12457 /* Ensure there's room for the next two instructions, so that `f'
12458 doesn't end up with an address in the wrong frag. */
12461 macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12462 BFD_RELOC_GPREL16);
12463 fix_new (frag_now, f - frag_now->fr_literal,
12464 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12465 fix_new (frag_now, f - frag_now->fr_literal,
12466 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12469 macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
12470 mips_gp_register, BFD_RELOC_GPREL16);
12471 fix_new (frag_now, f - frag_now->fr_literal,
12472 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12473 fix_new (frag_now, f - frag_now->fr_literal,
12474 4, NULL, 0, 0, BFD_RELOC_LO16);
12476 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12477 mips_gp_register, reg1);
12479 demand_empty_rest_of_line ();
12483 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12485 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12486 .cplocal is ignored. */
12487 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12493 mips_gp_register = tc_get_register (0);
12494 demand_empty_rest_of_line ();
12497 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12498 offset from $sp. The offset is remembered, and after making a PIC
12499 call $gp is restored from that location. */
12502 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12507 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12508 .cprestore is ignored. */
12509 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12515 mips_cprestore_offset = get_absolute_expression ();
12516 mips_cprestore_valid = 1;
12518 ex.X_op = O_constant;
12519 ex.X_add_symbol = NULL;
12520 ex.X_op_symbol = NULL;
12521 ex.X_add_number = mips_cprestore_offset;
12523 macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
12524 mips_gp_register, SP, HAVE_64BIT_ADDRESSES);
12526 demand_empty_rest_of_line ();
12529 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12530 was given in the preceeding .cpsetup, it results in:
12531 ld $gp, offset($sp)
12533 If a register $reg2 was given there, it results in:
12534 daddu $gp, $reg2, $0
12537 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12542 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12543 We also need NewABI support. */
12544 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12550 if (mips_cpreturn_register == -1)
12552 ex.X_op = O_constant;
12553 ex.X_add_symbol = NULL;
12554 ex.X_op_symbol = NULL;
12555 ex.X_add_number = mips_cpreturn_offset;
12557 macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
12558 BFD_RELOC_LO16, SP);
12561 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
12562 mips_cpreturn_register, 0);
12564 demand_empty_rest_of_line ();
12567 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12568 code. It sets the offset to use in gp_rel relocations. */
12571 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12573 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12574 We also need NewABI support. */
12575 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12581 mips_gprel_offset = get_absolute_expression ();
12583 demand_empty_rest_of_line ();
12586 /* Handle the .gpword pseudo-op. This is used when generating PIC
12587 code. It generates a 32 bit GP relative reloc. */
12590 s_gpword (int ignore ATTRIBUTE_UNUSED)
12596 /* When not generating PIC code, this is treated as .word. */
12597 if (mips_pic != SVR4_PIC)
12603 label = insn_labels != NULL ? insn_labels->label : NULL;
12604 mips_emit_delays (TRUE);
12606 mips_align (2, 0, label);
12607 mips_clear_insn_labels ();
12611 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12613 as_bad (_("Unsupported use of .gpword"));
12614 ignore_rest_of_line ();
12618 md_number_to_chars (p, 0, 4);
12619 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12620 BFD_RELOC_GPREL32);
12622 demand_empty_rest_of_line ();
12626 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12632 /* When not generating PIC code, this is treated as .dword. */
12633 if (mips_pic != SVR4_PIC)
12639 label = insn_labels != NULL ? insn_labels->label : NULL;
12640 mips_emit_delays (TRUE);
12642 mips_align (3, 0, label);
12643 mips_clear_insn_labels ();
12647 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12649 as_bad (_("Unsupported use of .gpdword"));
12650 ignore_rest_of_line ();
12654 md_number_to_chars (p, 0, 8);
12655 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12656 BFD_RELOC_GPREL32);
12658 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12659 ex.X_op = O_absent;
12660 ex.X_add_symbol = 0;
12661 ex.X_add_number = 0;
12662 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12665 demand_empty_rest_of_line ();
12668 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12669 tables in SVR4 PIC code. */
12672 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12677 /* This is ignored when not generating SVR4 PIC code. */
12678 if (mips_pic != SVR4_PIC)
12684 /* Add $gp to the register named as an argument. */
12685 reg = tc_get_register (0);
12686 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
12687 reg, reg, mips_gp_register);
12689 demand_empty_rest_of_line ();
12692 /* Handle the .insn pseudo-op. This marks instruction labels in
12693 mips16 mode. This permits the linker to handle them specially,
12694 such as generating jalx instructions when needed. We also make
12695 them odd for the duration of the assembly, in order to generate the
12696 right sort of code. We will make them even in the adjust_symtab
12697 routine, while leaving them marked. This is convenient for the
12698 debugger and the disassembler. The linker knows to make them odd
12702 s_insn (int ignore ATTRIBUTE_UNUSED)
12704 mips16_mark_labels ();
12706 demand_empty_rest_of_line ();
12709 /* Handle a .stabn directive. We need these in order to mark a label
12710 as being a mips16 text label correctly. Sometimes the compiler
12711 will emit a label, followed by a .stabn, and then switch sections.
12712 If the label and .stabn are in mips16 mode, then the label is
12713 really a mips16 text label. */
12716 s_mips_stab (int type)
12719 mips16_mark_labels ();
12724 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12728 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12735 name = input_line_pointer;
12736 c = get_symbol_end ();
12737 symbolP = symbol_find_or_make (name);
12738 S_SET_WEAK (symbolP);
12739 *input_line_pointer = c;
12741 SKIP_WHITESPACE ();
12743 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12745 if (S_IS_DEFINED (symbolP))
12747 as_bad ("ignoring attempt to redefine symbol %s",
12748 S_GET_NAME (symbolP));
12749 ignore_rest_of_line ();
12753 if (*input_line_pointer == ',')
12755 ++input_line_pointer;
12756 SKIP_WHITESPACE ();
12760 if (exp.X_op != O_symbol)
12762 as_bad ("bad .weakext directive");
12763 ignore_rest_of_line ();
12766 symbol_set_value_expression (symbolP, &exp);
12769 demand_empty_rest_of_line ();
12772 /* Parse a register string into a number. Called from the ECOFF code
12773 to parse .frame. The argument is non-zero if this is the frame
12774 register, so that we can record it in mips_frame_reg. */
12777 tc_get_register (int frame)
12781 SKIP_WHITESPACE ();
12782 if (*input_line_pointer++ != '$')
12784 as_warn (_("expected `$'"));
12787 else if (ISDIGIT (*input_line_pointer))
12789 reg = get_absolute_expression ();
12790 if (reg < 0 || reg >= 32)
12792 as_warn (_("Bad register number"));
12798 if (strncmp (input_line_pointer, "ra", 2) == 0)
12801 input_line_pointer += 2;
12803 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12806 input_line_pointer += 2;
12808 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12811 input_line_pointer += 2;
12813 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12816 input_line_pointer += 2;
12818 else if (strncmp (input_line_pointer, "at", 2) == 0)
12821 input_line_pointer += 2;
12823 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12826 input_line_pointer += 3;
12828 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12831 input_line_pointer += 3;
12833 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12836 input_line_pointer += 4;
12840 as_warn (_("Unrecognized register name"));
12842 while (ISALNUM(*input_line_pointer))
12843 input_line_pointer++;
12848 mips_frame_reg = reg != 0 ? reg : SP;
12849 mips_frame_reg_valid = 1;
12850 mips_cprestore_valid = 0;
12856 md_section_align (asection *seg, valueT addr)
12858 int align = bfd_get_section_alignment (stdoutput, seg);
12861 /* We don't need to align ELF sections to the full alignment.
12862 However, Irix 5 may prefer that we align them at least to a 16
12863 byte boundary. We don't bother to align the sections if we are
12864 targeted for an embedded system. */
12865 if (strcmp (TARGET_OS, "elf") == 0)
12871 return ((addr + (1 << align) - 1) & (-1 << align));
12874 /* Utility routine, called from above as well. If called while the
12875 input file is still being read, it's only an approximation. (For
12876 example, a symbol may later become defined which appeared to be
12877 undefined earlier.) */
12880 nopic_need_relax (symbolS *sym, int before_relaxing)
12885 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12887 const char *symname;
12890 /* Find out whether this symbol can be referenced off the $gp
12891 register. It can be if it is smaller than the -G size or if
12892 it is in the .sdata or .sbss section. Certain symbols can
12893 not be referenced off the $gp, although it appears as though
12895 symname = S_GET_NAME (sym);
12896 if (symname != (const char *) NULL
12897 && (strcmp (symname, "eprol") == 0
12898 || strcmp (symname, "etext") == 0
12899 || strcmp (symname, "_gp") == 0
12900 || strcmp (symname, "edata") == 0
12901 || strcmp (symname, "_fbss") == 0
12902 || strcmp (symname, "_fdata") == 0
12903 || strcmp (symname, "_ftext") == 0
12904 || strcmp (symname, "end") == 0
12905 || strcmp (symname, "_gp_disp") == 0))
12907 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12909 #ifndef NO_ECOFF_DEBUGGING
12910 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12911 && (symbol_get_obj (sym)->ecoff_extern_size
12912 <= g_switch_value))
12914 /* We must defer this decision until after the whole
12915 file has been read, since there might be a .extern
12916 after the first use of this symbol. */
12917 || (before_relaxing
12918 #ifndef NO_ECOFF_DEBUGGING
12919 && symbol_get_obj (sym)->ecoff_extern_size == 0
12921 && S_GET_VALUE (sym) == 0)
12922 || (S_GET_VALUE (sym) != 0
12923 && S_GET_VALUE (sym) <= g_switch_value)))
12927 const char *segname;
12929 segname = segment_name (S_GET_SEGMENT (sym));
12930 assert (strcmp (segname, ".lit8") != 0
12931 && strcmp (segname, ".lit4") != 0);
12932 change = (strcmp (segname, ".sdata") != 0
12933 && strcmp (segname, ".sbss") != 0
12934 && strncmp (segname, ".sdata.", 7) != 0
12935 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12940 /* We are not optimizing for the $gp register. */
12945 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12948 pic_need_relax (symbolS *sym, asection *segtype)
12951 bfd_boolean linkonce;
12953 /* Handle the case of a symbol equated to another symbol. */
12954 while (symbol_equated_reloc_p (sym))
12958 /* It's possible to get a loop here in a badly written
12960 n = symbol_get_value_expression (sym)->X_add_symbol;
12966 symsec = S_GET_SEGMENT (sym);
12968 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12970 if (symsec != segtype && ! S_IS_LOCAL (sym))
12972 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12976 /* The GNU toolchain uses an extension for ELF: a section
12977 beginning with the magic string .gnu.linkonce is a linkonce
12979 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12980 sizeof ".gnu.linkonce" - 1) == 0)
12984 /* This must duplicate the test in adjust_reloc_syms. */
12985 return (symsec != &bfd_und_section
12986 && symsec != &bfd_abs_section
12987 && ! bfd_is_com_section (symsec)
12990 /* A global or weak symbol is treated as external. */
12991 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12992 || (! S_IS_WEAK (sym)
12993 && (! S_IS_EXTERNAL (sym)
12994 || mips_pic == EMBEDDED_PIC)))
13000 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13001 extended opcode. SEC is the section the frag is in. */
13004 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13007 register const struct mips16_immed_operand *op;
13009 int mintiny, maxtiny;
13013 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13015 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13018 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13019 op = mips16_immed_operands;
13020 while (op->type != type)
13023 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13028 if (type == '<' || type == '>' || type == '[' || type == ']')
13031 maxtiny = 1 << op->nbits;
13036 maxtiny = (1 << op->nbits) - 1;
13041 mintiny = - (1 << (op->nbits - 1));
13042 maxtiny = (1 << (op->nbits - 1)) - 1;
13045 sym_frag = symbol_get_frag (fragp->fr_symbol);
13046 val = S_GET_VALUE (fragp->fr_symbol);
13047 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13053 /* We won't have the section when we are called from
13054 mips_relax_frag. However, we will always have been called
13055 from md_estimate_size_before_relax first. If this is a
13056 branch to a different section, we mark it as such. If SEC is
13057 NULL, and the frag is not marked, then it must be a branch to
13058 the same section. */
13061 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13066 /* Must have been called from md_estimate_size_before_relax. */
13069 fragp->fr_subtype =
13070 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13072 /* FIXME: We should support this, and let the linker
13073 catch branches and loads that are out of range. */
13074 as_bad_where (fragp->fr_file, fragp->fr_line,
13075 _("unsupported PC relative reference to different section"));
13079 if (fragp != sym_frag && sym_frag->fr_address == 0)
13080 /* Assume non-extended on the first relaxation pass.
13081 The address we have calculated will be bogus if this is
13082 a forward branch to another frag, as the forward frag
13083 will have fr_address == 0. */
13087 /* In this case, we know for sure that the symbol fragment is in
13088 the same section. If the relax_marker of the symbol fragment
13089 differs from the relax_marker of this fragment, we have not
13090 yet adjusted the symbol fragment fr_address. We want to add
13091 in STRETCH in order to get a better estimate of the address.
13092 This particularly matters because of the shift bits. */
13094 && sym_frag->relax_marker != fragp->relax_marker)
13098 /* Adjust stretch for any alignment frag. Note that if have
13099 been expanding the earlier code, the symbol may be
13100 defined in what appears to be an earlier frag. FIXME:
13101 This doesn't handle the fr_subtype field, which specifies
13102 a maximum number of bytes to skip when doing an
13104 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13106 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13109 stretch = - ((- stretch)
13110 & ~ ((1 << (int) f->fr_offset) - 1));
13112 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13121 addr = fragp->fr_address + fragp->fr_fix;
13123 /* The base address rules are complicated. The base address of
13124 a branch is the following instruction. The base address of a
13125 PC relative load or add is the instruction itself, but if it
13126 is in a delay slot (in which case it can not be extended) use
13127 the address of the instruction whose delay slot it is in. */
13128 if (type == 'p' || type == 'q')
13132 /* If we are currently assuming that this frag should be
13133 extended, then, the current address is two bytes
13135 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13138 /* Ignore the low bit in the target, since it will be set
13139 for a text label. */
13140 if ((val & 1) != 0)
13143 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13145 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13148 val -= addr & ~ ((1 << op->shift) - 1);
13150 /* Branch offsets have an implicit 0 in the lowest bit. */
13151 if (type == 'p' || type == 'q')
13154 /* If any of the shifted bits are set, we must use an extended
13155 opcode. If the address depends on the size of this
13156 instruction, this can lead to a loop, so we arrange to always
13157 use an extended opcode. We only check this when we are in
13158 the main relaxation loop, when SEC is NULL. */
13159 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13161 fragp->fr_subtype =
13162 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13166 /* If we are about to mark a frag as extended because the value
13167 is precisely maxtiny + 1, then there is a chance of an
13168 infinite loop as in the following code:
13173 In this case when the la is extended, foo is 0x3fc bytes
13174 away, so the la can be shrunk, but then foo is 0x400 away, so
13175 the la must be extended. To avoid this loop, we mark the
13176 frag as extended if it was small, and is about to become
13177 extended with a value of maxtiny + 1. */
13178 if (val == ((maxtiny + 1) << op->shift)
13179 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13182 fragp->fr_subtype =
13183 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13187 else if (symsec != absolute_section && sec != NULL)
13188 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13190 if ((val & ((1 << op->shift) - 1)) != 0
13191 || val < (mintiny << op->shift)
13192 || val > (maxtiny << op->shift))
13198 /* Compute the length of a branch sequence, and adjust the
13199 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13200 worst-case length is computed, with UPDATE being used to indicate
13201 whether an unconditional (-1), branch-likely (+1) or regular (0)
13202 branch is to be computed. */
13204 relaxed_branch_length (fragS *fragp, asection *sec, int update)
13206 bfd_boolean toofar;
13210 && S_IS_DEFINED (fragp->fr_symbol)
13211 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13216 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13218 addr = fragp->fr_address + fragp->fr_fix + 4;
13222 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13225 /* If the symbol is not defined or it's in a different segment,
13226 assume the user knows what's going on and emit a short
13232 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13234 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13235 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13236 RELAX_BRANCH_LINK (fragp->fr_subtype),
13242 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13245 if (mips_pic != NO_PIC)
13247 /* Additional space for PIC loading of target address. */
13249 if (mips_opts.isa == ISA_MIPS1)
13250 /* Additional space for $at-stabilizing nop. */
13254 /* If branch is conditional. */
13255 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13262 /* Estimate the size of a frag before relaxing. Unless this is the
13263 mips16, we are not really relaxing here, and the final size is
13264 encoded in the subtype information. For the mips16, we have to
13265 decide whether we are using an extended opcode or not. */
13268 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13272 if (RELAX_BRANCH_P (fragp->fr_subtype))
13275 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13277 return fragp->fr_var;
13280 if (RELAX_MIPS16_P (fragp->fr_subtype))
13281 /* We don't want to modify the EXTENDED bit here; it might get us
13282 into infinite loops. We change it only in mips_relax_frag(). */
13283 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13285 if (mips_pic == NO_PIC)
13286 change = nopic_need_relax (fragp->fr_symbol, 0);
13287 else if (mips_pic == SVR4_PIC)
13288 change = pic_need_relax (fragp->fr_symbol, segtype);
13294 /* Record the offset to the first reloc in the fr_opcode field.
13295 This lets md_convert_frag and tc_gen_reloc know that the code
13296 must be expanded. */
13297 fragp->fr_opcode = (fragp->fr_literal
13299 - RELAX_OLD (fragp->fr_subtype)
13300 + RELAX_RELOC1 (fragp->fr_subtype));
13301 /* FIXME: This really needs as_warn_where. */
13302 if (RELAX_WARN (fragp->fr_subtype))
13303 as_warn (_("AT used after \".set noat\" or macro used after "
13304 "\".set nomacro\""));
13306 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
13312 /* This is called to see whether a reloc against a defined symbol
13313 should be converted into a reloc against a section. Don't adjust
13314 MIPS16 jump relocations, so we don't have to worry about the format
13315 of the offset in the .o file. Don't adjust relocations against
13316 mips16 symbols, so that the linker can find them if it needs to set
13320 mips_fix_adjustable (fixS *fixp)
13322 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13325 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13326 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13329 if (fixp->fx_addsy == NULL)
13333 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13334 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13335 && fixp->fx_subsy == NULL)
13342 /* Translate internal representation of relocation info to BFD target
13346 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13348 static arelent *retval[4];
13350 bfd_reloc_code_real_type code;
13352 memset (retval, 0, sizeof(retval));
13353 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13354 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13355 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13356 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13358 if (mips_pic == EMBEDDED_PIC
13359 && SWITCH_TABLE (fixp))
13361 /* For a switch table entry we use a special reloc. The addend
13362 is actually the difference between the reloc address and the
13364 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13365 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13366 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13367 fixp->fx_r_type = BFD_RELOC_GPREL32;
13369 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
13371 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13372 reloc->addend = fixp->fx_addnumber;
13375 /* We use a special addend for an internal RELLO reloc. */
13376 if (symbol_section_p (fixp->fx_addsy))
13377 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13379 reloc->addend = fixp->fx_addnumber + reloc->address;
13382 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13384 assert (fixp->fx_next != NULL
13385 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13387 /* The reloc is relative to the RELLO; adjust the addend
13389 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13390 reloc->addend = fixp->fx_next->fx_addnumber;
13393 /* We use a special addend for an internal RELHI reloc. */
13394 if (symbol_section_p (fixp->fx_addsy))
13395 reloc->addend = (fixp->fx_next->fx_frag->fr_address
13396 + fixp->fx_next->fx_where
13397 - S_GET_VALUE (fixp->fx_subsy));
13399 reloc->addend = (fixp->fx_addnumber
13400 + fixp->fx_next->fx_frag->fr_address
13401 + fixp->fx_next->fx_where);
13404 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13405 reloc->addend = fixp->fx_addnumber;
13408 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13409 /* A gruesome hack which is a result of the gruesome gas reloc
13411 reloc->addend = reloc->address;
13413 reloc->addend = -reloc->address;
13416 /* If this is a variant frag, we may need to adjust the existing
13417 reloc and generate a new one. */
13418 if (fixp->fx_frag->fr_opcode != NULL
13419 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13421 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP
13423 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13424 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13425 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13426 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13427 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13428 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13433 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13435 /* If this is not the last reloc in this frag, then we have two
13436 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13437 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13438 the second one handle all of them. */
13439 if (fixp->fx_next != NULL
13440 && fixp->fx_frag == fixp->fx_next->fx_frag)
13442 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13443 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13444 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13445 && (fixp->fx_next->fx_r_type
13446 == BFD_RELOC_MIPS_GOT_LO16))
13447 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13448 && (fixp->fx_next->fx_r_type
13449 == BFD_RELOC_MIPS_CALL_LO16)));
13454 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13455 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13456 reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset;
13457 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13458 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13459 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13460 reloc2->address = (reloc->address
13461 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13462 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13463 reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy)
13464 + fixp->fx_frag->tc_frag_data.tc_fr_offset;
13465 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13466 assert (reloc2->howto != NULL);
13468 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13472 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13474 reloc3->address += 4;
13477 if (mips_pic == NO_PIC)
13479 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13480 fixp->fx_r_type = BFD_RELOC_HI16_S;
13482 else if (mips_pic == SVR4_PIC)
13484 switch (fixp->fx_r_type)
13488 case BFD_RELOC_MIPS_GOT16:
13490 case BFD_RELOC_MIPS_GOT_LO16:
13491 case BFD_RELOC_MIPS_CALL_LO16:
13494 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13495 reloc2->howto = bfd_reloc_type_lookup
13496 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13499 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13501 case BFD_RELOC_MIPS_CALL16:
13502 case BFD_RELOC_MIPS_GOT_OFST:
13503 case BFD_RELOC_MIPS_GOT_DISP:
13506 /* It may seem nonsensical to relax GOT_DISP to
13507 GOT_DISP, but we're actually turning a GOT_DISP
13508 without offset into a GOT_DISP with an offset,
13509 getting rid of the separate addition, which we can
13510 do when the symbol is found to be local. */
13511 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13515 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13523 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13524 entry to be used in the relocation's section offset. */
13525 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13527 reloc->address = reloc->addend;
13531 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13532 fixup_segment converted a non-PC relative reloc into a PC
13533 relative reloc. In such a case, we need to convert the reloc
13535 code = fixp->fx_r_type;
13536 if (fixp->fx_pcrel)
13541 code = BFD_RELOC_8_PCREL;
13544 code = BFD_RELOC_16_PCREL;
13547 code = BFD_RELOC_32_PCREL;
13550 code = BFD_RELOC_64_PCREL;
13552 case BFD_RELOC_8_PCREL:
13553 case BFD_RELOC_16_PCREL:
13554 case BFD_RELOC_32_PCREL:
13555 case BFD_RELOC_64_PCREL:
13556 case BFD_RELOC_16_PCREL_S2:
13557 case BFD_RELOC_PCREL_HI16_S:
13558 case BFD_RELOC_PCREL_LO16:
13561 as_bad_where (fixp->fx_file, fixp->fx_line,
13562 _("Cannot make %s relocation PC relative"),
13563 bfd_get_reloc_code_name (code));
13567 /* To support a PC relative reloc when generating embedded PIC code
13568 for ECOFF, we use a Cygnus extension. We check for that here to
13569 make sure that we don't let such a reloc escape normally. */
13570 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13571 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13572 && code == BFD_RELOC_16_PCREL_S2
13573 && mips_pic != EMBEDDED_PIC)
13574 reloc->howto = NULL;
13576 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13578 if (reloc->howto == NULL)
13580 as_bad_where (fixp->fx_file, fixp->fx_line,
13581 _("Can not represent %s relocation in this object file format"),
13582 bfd_get_reloc_code_name (code));
13589 /* Relax a machine dependent frag. This returns the amount by which
13590 the current size of the frag should change. */
13593 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13595 if (RELAX_BRANCH_P (fragp->fr_subtype))
13597 offsetT old_var = fragp->fr_var;
13599 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13601 return fragp->fr_var - old_var;
13604 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13607 if (mips16_extended_frag (fragp, NULL, stretch))
13609 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13611 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13616 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13618 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13625 /* Convert a machine dependent frag. */
13628 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13633 if (RELAX_BRANCH_P (fragp->fr_subtype))
13636 unsigned long insn;
13640 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13642 if (target_big_endian)
13643 insn = bfd_getb32 (buf);
13645 insn = bfd_getl32 (buf);
13647 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13649 /* We generate a fixup instead of applying it right now
13650 because, if there are linker relaxations, we're going to
13651 need the relocations. */
13652 exp.X_op = O_symbol;
13653 exp.X_add_symbol = fragp->fr_symbol;
13654 exp.X_add_number = fragp->fr_offset;
13656 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13658 BFD_RELOC_16_PCREL_S2);
13659 fixp->fx_file = fragp->fr_file;
13660 fixp->fx_line = fragp->fr_line;
13662 md_number_to_chars (buf, insn, 4);
13669 as_warn_where (fragp->fr_file, fragp->fr_line,
13670 _("relaxed out-of-range branch into a jump"));
13672 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13675 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13677 /* Reverse the branch. */
13678 switch ((insn >> 28) & 0xf)
13681 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13682 have the condition reversed by tweaking a single
13683 bit, and their opcodes all have 0x4???????. */
13684 assert ((insn & 0xf1000000) == 0x41000000);
13685 insn ^= 0x00010000;
13689 /* bltz 0x04000000 bgez 0x04010000
13690 bltzal 0x04100000 bgezal 0x04110000 */
13691 assert ((insn & 0xfc0e0000) == 0x04000000);
13692 insn ^= 0x00010000;
13696 /* beq 0x10000000 bne 0x14000000
13697 blez 0x18000000 bgtz 0x1c000000 */
13698 insn ^= 0x04000000;
13706 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13708 /* Clear the and-link bit. */
13709 assert ((insn & 0xfc1c0000) == 0x04100000);
13711 /* bltzal 0x04100000 bgezal 0x04110000
13712 bltzall 0x04120000 bgezall 0x04130000 */
13713 insn &= ~0x00100000;
13716 /* Branch over the branch (if the branch was likely) or the
13717 full jump (not likely case). Compute the offset from the
13718 current instruction to branch to. */
13719 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13723 /* How many bytes in instructions we've already emitted? */
13724 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13725 /* How many bytes in instructions from here to the end? */
13726 i = fragp->fr_var - i;
13728 /* Convert to instruction count. */
13730 /* Branch counts from the next instruction. */
13733 /* Branch over the jump. */
13734 md_number_to_chars (buf, insn, 4);
13738 md_number_to_chars (buf, 0, 4);
13741 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13743 /* beql $0, $0, 2f */
13745 /* Compute the PC offset from the current instruction to
13746 the end of the variable frag. */
13747 /* How many bytes in instructions we've already emitted? */
13748 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13749 /* How many bytes in instructions from here to the end? */
13750 i = fragp->fr_var - i;
13751 /* Convert to instruction count. */
13753 /* Don't decrement i, because we want to branch over the
13757 md_number_to_chars (buf, insn, 4);
13760 md_number_to_chars (buf, 0, 4);
13765 if (mips_pic == NO_PIC)
13768 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13769 ? 0x0c000000 : 0x08000000);
13770 exp.X_op = O_symbol;
13771 exp.X_add_symbol = fragp->fr_symbol;
13772 exp.X_add_number = fragp->fr_offset;
13774 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13775 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13776 fixp->fx_file = fragp->fr_file;
13777 fixp->fx_line = fragp->fr_line;
13779 md_number_to_chars (buf, insn, 4);
13784 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13785 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13786 exp.X_op = O_symbol;
13787 exp.X_add_symbol = fragp->fr_symbol;
13788 exp.X_add_number = fragp->fr_offset;
13790 if (fragp->fr_offset)
13792 exp.X_add_symbol = make_expr_symbol (&exp);
13793 exp.X_add_number = 0;
13796 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13797 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13798 fixp->fx_file = fragp->fr_file;
13799 fixp->fx_line = fragp->fr_line;
13801 md_number_to_chars (buf, insn, 4);
13804 if (mips_opts.isa == ISA_MIPS1)
13807 md_number_to_chars (buf, 0, 4);
13811 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13812 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13814 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13815 4, &exp, 0, BFD_RELOC_LO16);
13816 fixp->fx_file = fragp->fr_file;
13817 fixp->fx_line = fragp->fr_line;
13819 md_number_to_chars (buf, insn, 4);
13823 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13828 md_number_to_chars (buf, insn, 4);
13833 assert (buf == (bfd_byte *)fragp->fr_literal
13834 + fragp->fr_fix + fragp->fr_var);
13836 fragp->fr_fix += fragp->fr_var;
13841 if (RELAX_MIPS16_P (fragp->fr_subtype))
13844 register const struct mips16_immed_operand *op;
13845 bfd_boolean small, ext;
13848 unsigned long insn;
13849 bfd_boolean use_extend;
13850 unsigned short extend;
13852 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13853 op = mips16_immed_operands;
13854 while (op->type != type)
13857 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13868 resolve_symbol_value (fragp->fr_symbol);
13869 val = S_GET_VALUE (fragp->fr_symbol);
13874 addr = fragp->fr_address + fragp->fr_fix;
13876 /* The rules for the base address of a PC relative reloc are
13877 complicated; see mips16_extended_frag. */
13878 if (type == 'p' || type == 'q')
13883 /* Ignore the low bit in the target, since it will be
13884 set for a text label. */
13885 if ((val & 1) != 0)
13888 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13890 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13893 addr &= ~ (addressT) ((1 << op->shift) - 1);
13896 /* Make sure the section winds up with the alignment we have
13899 record_alignment (asec, op->shift);
13903 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13904 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13905 as_warn_where (fragp->fr_file, fragp->fr_line,
13906 _("extended instruction in delay slot"));
13908 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13910 if (target_big_endian)
13911 insn = bfd_getb16 (buf);
13913 insn = bfd_getl16 (buf);
13915 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13916 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13917 small, ext, &insn, &use_extend, &extend);
13921 md_number_to_chars (buf, 0xf000 | extend, 2);
13922 fragp->fr_fix += 2;
13926 md_number_to_chars (buf, insn, 2);
13927 fragp->fr_fix += 2;
13932 if (fragp->fr_opcode == NULL)
13935 old = RELAX_OLD (fragp->fr_subtype);
13936 new = RELAX_NEW (fragp->fr_subtype);
13937 fixptr = fragp->fr_literal + fragp->fr_fix;
13940 memmove (fixptr - old, fixptr, new);
13942 fragp->fr_fix += new - old;
13948 /* This function is called after the relocs have been generated.
13949 We've been storing mips16 text labels as odd. Here we convert them
13950 back to even for the convenience of the debugger. */
13953 mips_frob_file_after_relocs (void)
13956 unsigned int count, i;
13958 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13961 syms = bfd_get_outsymbols (stdoutput);
13962 count = bfd_get_symcount (stdoutput);
13963 for (i = 0; i < count; i++, syms++)
13965 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13966 && ((*syms)->value & 1) != 0)
13968 (*syms)->value &= ~1;
13969 /* If the symbol has an odd size, it was probably computed
13970 incorrectly, so adjust that as well. */
13971 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13972 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13979 /* This function is called whenever a label is defined. It is used
13980 when handling branch delays; if a branch has a label, we assume we
13981 can not move it. */
13984 mips_define_label (symbolS *sym)
13986 struct insn_label_list *l;
13988 if (free_insn_labels == NULL)
13989 l = (struct insn_label_list *) xmalloc (sizeof *l);
13992 l = free_insn_labels;
13993 free_insn_labels = l->next;
13997 l->next = insn_labels;
14001 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14003 /* Some special processing for a MIPS ELF file. */
14006 mips_elf_final_processing (void)
14008 /* Write out the register information. */
14009 if (mips_abi != N64_ABI)
14013 s.ri_gprmask = mips_gprmask;
14014 s.ri_cprmask[0] = mips_cprmask[0];
14015 s.ri_cprmask[1] = mips_cprmask[1];
14016 s.ri_cprmask[2] = mips_cprmask[2];
14017 s.ri_cprmask[3] = mips_cprmask[3];
14018 /* The gp_value field is set by the MIPS ELF backend. */
14020 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14021 ((Elf32_External_RegInfo *)
14022 mips_regmask_frag));
14026 Elf64_Internal_RegInfo s;
14028 s.ri_gprmask = mips_gprmask;
14030 s.ri_cprmask[0] = mips_cprmask[0];
14031 s.ri_cprmask[1] = mips_cprmask[1];
14032 s.ri_cprmask[2] = mips_cprmask[2];
14033 s.ri_cprmask[3] = mips_cprmask[3];
14034 /* The gp_value field is set by the MIPS ELF backend. */
14036 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14037 ((Elf64_External_RegInfo *)
14038 mips_regmask_frag));
14041 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14042 sort of BFD interface for this. */
14043 if (mips_any_noreorder)
14044 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14045 if (mips_pic != NO_PIC)
14047 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14048 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14051 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14053 /* Set MIPS ELF flags for ASEs. */
14054 if (file_ase_mips16)
14055 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14056 #if 0 /* XXX FIXME */
14057 if (file_ase_mips3d)
14058 elf_elfheader (stdoutput)->e_flags |= ???;
14061 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14063 /* Set the MIPS ELF ABI flags. */
14064 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14065 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14066 else if (mips_abi == O64_ABI)
14067 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14068 else if (mips_abi == EABI_ABI)
14070 if (!file_mips_gp32)
14071 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14073 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14075 else if (mips_abi == N32_ABI)
14076 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14078 /* Nothing to do for N64_ABI. */
14080 if (mips_32bitmode)
14081 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14084 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14086 typedef struct proc {
14088 unsigned long reg_mask;
14089 unsigned long reg_offset;
14090 unsigned long fpreg_mask;
14091 unsigned long fpreg_offset;
14092 unsigned long frame_offset;
14093 unsigned long frame_reg;
14094 unsigned long pc_reg;
14097 static procS cur_proc;
14098 static procS *cur_proc_ptr;
14099 static int numprocs;
14101 /* Fill in an rs_align_code fragment. */
14104 mips_handle_align (fragS *fragp)
14106 if (fragp->fr_type != rs_align_code)
14109 if (mips_opts.mips16)
14111 static const unsigned char be_nop[] = { 0x65, 0x00 };
14112 static const unsigned char le_nop[] = { 0x00, 0x65 };
14117 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14118 p = fragp->fr_literal + fragp->fr_fix;
14126 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
14130 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14134 md_obj_begin (void)
14141 /* check for premature end, nesting errors, etc */
14143 as_warn (_("missing .end at end of assembly"));
14152 if (*input_line_pointer == '-')
14154 ++input_line_pointer;
14157 if (!ISDIGIT (*input_line_pointer))
14158 as_bad (_("expected simple number"));
14159 if (input_line_pointer[0] == '0')
14161 if (input_line_pointer[1] == 'x')
14163 input_line_pointer += 2;
14164 while (ISXDIGIT (*input_line_pointer))
14167 val |= hex_value (*input_line_pointer++);
14169 return negative ? -val : val;
14173 ++input_line_pointer;
14174 while (ISDIGIT (*input_line_pointer))
14177 val |= *input_line_pointer++ - '0';
14179 return negative ? -val : val;
14182 if (!ISDIGIT (*input_line_pointer))
14184 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14185 *input_line_pointer, *input_line_pointer);
14186 as_warn (_("invalid number"));
14189 while (ISDIGIT (*input_line_pointer))
14192 val += *input_line_pointer++ - '0';
14194 return negative ? -val : val;
14197 /* The .file directive; just like the usual .file directive, but there
14198 is an initial number which is the ECOFF file index. In the non-ECOFF
14199 case .file implies DWARF-2. */
14202 s_mips_file (int x ATTRIBUTE_UNUSED)
14204 static int first_file_directive = 0;
14206 if (ECOFF_DEBUGGING)
14215 filename = dwarf2_directive_file (0);
14217 /* Versions of GCC up to 3.1 start files with a ".file"
14218 directive even for stabs output. Make sure that this
14219 ".file" is handled. Note that you need a version of GCC
14220 after 3.1 in order to support DWARF-2 on MIPS. */
14221 if (filename != NULL && ! first_file_directive)
14223 (void) new_logical_line (filename, -1);
14224 s_app_file_string (filename);
14226 first_file_directive = 1;
14230 /* The .loc directive, implying DWARF-2. */
14233 s_mips_loc (int x ATTRIBUTE_UNUSED)
14235 if (!ECOFF_DEBUGGING)
14236 dwarf2_directive_loc (0);
14239 /* The .end directive. */
14242 s_mips_end (int x ATTRIBUTE_UNUSED)
14246 /* Following functions need their own .frame and .cprestore directives. */
14247 mips_frame_reg_valid = 0;
14248 mips_cprestore_valid = 0;
14250 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14253 demand_empty_rest_of_line ();
14258 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14259 as_warn (_(".end not in text section"));
14263 as_warn (_(".end directive without a preceding .ent directive."));
14264 demand_empty_rest_of_line ();
14270 assert (S_GET_NAME (p));
14271 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14272 as_warn (_(".end symbol does not match .ent symbol."));
14274 if (debug_type == DEBUG_STABS)
14275 stabs_generate_asm_endfunc (S_GET_NAME (p),
14279 as_warn (_(".end directive missing or unknown symbol"));
14282 /* Generate a .pdr section. */
14283 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14286 segT saved_seg = now_seg;
14287 subsegT saved_subseg = now_subseg;
14292 dot = frag_now_fix ();
14294 #ifdef md_flush_pending_output
14295 md_flush_pending_output ();
14299 subseg_set (pdr_seg, 0);
14301 /* Write the symbol. */
14302 exp.X_op = O_symbol;
14303 exp.X_add_symbol = p;
14304 exp.X_add_number = 0;
14305 emit_expr (&exp, 4);
14307 fragp = frag_more (7 * 4);
14309 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14310 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14311 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14312 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14313 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14314 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14315 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14317 subseg_set (saved_seg, saved_subseg);
14319 #endif /* OBJ_ELF */
14321 cur_proc_ptr = NULL;
14324 /* The .aent and .ent directives. */
14327 s_mips_ent (int aent)
14331 symbolP = get_symbol ();
14332 if (*input_line_pointer == ',')
14333 ++input_line_pointer;
14334 SKIP_WHITESPACE ();
14335 if (ISDIGIT (*input_line_pointer)
14336 || *input_line_pointer == '-')
14339 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14340 as_warn (_(".ent or .aent not in text section."));
14342 if (!aent && cur_proc_ptr)
14343 as_warn (_("missing .end"));
14347 /* This function needs its own .frame and .cprestore directives. */
14348 mips_frame_reg_valid = 0;
14349 mips_cprestore_valid = 0;
14351 cur_proc_ptr = &cur_proc;
14352 memset (cur_proc_ptr, '\0', sizeof (procS));
14354 cur_proc_ptr->isym = symbolP;
14356 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14360 if (debug_type == DEBUG_STABS)
14361 stabs_generate_asm_func (S_GET_NAME (symbolP),
14362 S_GET_NAME (symbolP));
14365 demand_empty_rest_of_line ();
14368 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14369 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14370 s_mips_frame is used so that we can set the PDR information correctly.
14371 We can't use the ecoff routines because they make reference to the ecoff
14372 symbol table (in the mdebug section). */
14375 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14378 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14382 if (cur_proc_ptr == (procS *) NULL)
14384 as_warn (_(".frame outside of .ent"));
14385 demand_empty_rest_of_line ();
14389 cur_proc_ptr->frame_reg = tc_get_register (1);
14391 SKIP_WHITESPACE ();
14392 if (*input_line_pointer++ != ','
14393 || get_absolute_expression_and_terminator (&val) != ',')
14395 as_warn (_("Bad .frame directive"));
14396 --input_line_pointer;
14397 demand_empty_rest_of_line ();
14401 cur_proc_ptr->frame_offset = val;
14402 cur_proc_ptr->pc_reg = tc_get_register (0);
14404 demand_empty_rest_of_line ();
14407 #endif /* OBJ_ELF */
14411 /* The .fmask and .mask directives. If the mdebug section is present
14412 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14413 embedded targets, s_mips_mask is used so that we can set the PDR
14414 information correctly. We can't use the ecoff routines because they
14415 make reference to the ecoff symbol table (in the mdebug section). */
14418 s_mips_mask (int reg_type)
14421 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14425 if (cur_proc_ptr == (procS *) NULL)
14427 as_warn (_(".mask/.fmask outside of .ent"));
14428 demand_empty_rest_of_line ();
14432 if (get_absolute_expression_and_terminator (&mask) != ',')
14434 as_warn (_("Bad .mask/.fmask directive"));
14435 --input_line_pointer;
14436 demand_empty_rest_of_line ();
14440 off = get_absolute_expression ();
14442 if (reg_type == 'F')
14444 cur_proc_ptr->fpreg_mask = mask;
14445 cur_proc_ptr->fpreg_offset = off;
14449 cur_proc_ptr->reg_mask = mask;
14450 cur_proc_ptr->reg_offset = off;
14453 demand_empty_rest_of_line ();
14456 #endif /* OBJ_ELF */
14457 s_ignore (reg_type);
14460 /* The .loc directive. */
14470 assert (now_seg == text_section);
14472 lineno = get_number ();
14473 addroff = frag_now_fix ();
14475 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14476 S_SET_TYPE (symbolP, N_SLINE);
14477 S_SET_OTHER (symbolP, 0);
14478 S_SET_DESC (symbolP, lineno);
14479 symbolP->sy_segment = now_seg;
14483 /* A table describing all the processors gas knows about. Names are
14484 matched in the order listed.
14486 To ease comparison, please keep this table in the same order as
14487 gcc's mips_cpu_info_table[]. */
14488 static const struct mips_cpu_info mips_cpu_info_table[] =
14490 /* Entries for generic ISAs */
14491 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14492 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14493 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14494 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14495 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14496 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14497 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14498 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14499 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
14502 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14503 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14504 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14507 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14510 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14511 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14512 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14513 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14514 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14515 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14516 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14517 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14518 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14519 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14520 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14521 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14524 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14525 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14526 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14527 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14528 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14529 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14530 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14531 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14532 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14533 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14534 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14535 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14536 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14539 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14540 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14541 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14544 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14545 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14547 /* Broadcom SB-1 CPU core */
14548 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14555 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14556 with a final "000" replaced by "k". Ignore case.
14558 Note: this function is shared between GCC and GAS. */
14561 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14563 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14564 given++, canonical++;
14566 return ((*given == 0 && *canonical == 0)
14567 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14571 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14572 CPU name. We've traditionally allowed a lot of variation here.
14574 Note: this function is shared between GCC and GAS. */
14577 mips_matching_cpu_name_p (const char *canonical, const char *given)
14579 /* First see if the name matches exactly, or with a final "000"
14580 turned into "k". */
14581 if (mips_strict_matching_cpu_name_p (canonical, given))
14584 /* If not, try comparing based on numerical designation alone.
14585 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14586 if (TOLOWER (*given) == 'r')
14588 if (!ISDIGIT (*given))
14591 /* Skip over some well-known prefixes in the canonical name,
14592 hoping to find a number there too. */
14593 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14595 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14597 else if (TOLOWER (canonical[0]) == 'r')
14600 return mips_strict_matching_cpu_name_p (canonical, given);
14604 /* Parse an option that takes the name of a processor as its argument.
14605 OPTION is the name of the option and CPU_STRING is the argument.
14606 Return the corresponding processor enumeration if the CPU_STRING is
14607 recognized, otherwise report an error and return null.
14609 A similar function exists in GCC. */
14611 static const struct mips_cpu_info *
14612 mips_parse_cpu (const char *option, const char *cpu_string)
14614 const struct mips_cpu_info *p;
14616 /* 'from-abi' selects the most compatible architecture for the given
14617 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14618 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14619 version. Look first at the -mgp options, if given, otherwise base
14620 the choice on MIPS_DEFAULT_64BIT.
14622 Treat NO_ABI like the EABIs. One reason to do this is that the
14623 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14624 architecture. This code picks MIPS I for 'mips' and MIPS III for
14625 'mips64', just as we did in the days before 'from-abi'. */
14626 if (strcasecmp (cpu_string, "from-abi") == 0)
14628 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14629 return mips_cpu_info_from_isa (ISA_MIPS1);
14631 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14632 return mips_cpu_info_from_isa (ISA_MIPS3);
14634 if (file_mips_gp32 >= 0)
14635 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14637 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14642 /* 'default' has traditionally been a no-op. Probably not very useful. */
14643 if (strcasecmp (cpu_string, "default") == 0)
14646 for (p = mips_cpu_info_table; p->name != 0; p++)
14647 if (mips_matching_cpu_name_p (p->name, cpu_string))
14650 as_bad ("Bad value (%s) for %s", cpu_string, option);
14654 /* Return the canonical processor information for ISA (a member of the
14655 ISA_MIPS* enumeration). */
14657 static const struct mips_cpu_info *
14658 mips_cpu_info_from_isa (int isa)
14662 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14663 if (mips_cpu_info_table[i].is_isa
14664 && isa == mips_cpu_info_table[i].isa)
14665 return (&mips_cpu_info_table[i]);
14670 static const struct mips_cpu_info *
14671 mips_cpu_info_from_arch (int arch)
14675 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14676 if (arch == mips_cpu_info_table[i].cpu)
14677 return (&mips_cpu_info_table[i]);
14683 show (FILE *stream, const char *string, int *col_p, int *first_p)
14687 fprintf (stream, "%24s", "");
14692 fprintf (stream, ", ");
14696 if (*col_p + strlen (string) > 72)
14698 fprintf (stream, "\n%24s", "");
14702 fprintf (stream, "%s", string);
14703 *col_p += strlen (string);
14709 md_show_usage (FILE *stream)
14714 fprintf (stream, _("\
14716 -membedded-pic generate embedded position independent code\n\
14717 -EB generate big endian output\n\
14718 -EL generate little endian output\n\
14719 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14720 -G NUM allow referencing objects up to NUM bytes\n\
14721 implicitly with the gp register [default 8]\n"));
14722 fprintf (stream, _("\
14723 -mips1 generate MIPS ISA I instructions\n\
14724 -mips2 generate MIPS ISA II instructions\n\
14725 -mips3 generate MIPS ISA III instructions\n\
14726 -mips4 generate MIPS ISA IV instructions\n\
14727 -mips5 generate MIPS ISA V instructions\n\
14728 -mips32 generate MIPS32 ISA instructions\n\
14729 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14730 -mips64 generate MIPS64 ISA instructions\n\
14731 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14732 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14736 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14737 show (stream, mips_cpu_info_table[i].name, &column, &first);
14738 show (stream, "from-abi", &column, &first);
14739 fputc ('\n', stream);
14741 fprintf (stream, _("\
14742 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14743 -no-mCPU don't generate code specific to CPU.\n\
14744 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14748 show (stream, "3900", &column, &first);
14749 show (stream, "4010", &column, &first);
14750 show (stream, "4100", &column, &first);
14751 show (stream, "4650", &column, &first);
14752 fputc ('\n', stream);
14754 fprintf (stream, _("\
14755 -mips16 generate mips16 instructions\n\
14756 -no-mips16 do not generate mips16 instructions\n"));
14757 fprintf (stream, _("\
14758 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14759 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14760 -O0 remove unneeded NOPs, do not swap branches\n\
14761 -O remove unneeded NOPs and swap branches\n\
14762 -n warn about NOPs generated from macros\n\
14763 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14764 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14765 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14767 fprintf (stream, _("\
14768 -KPIC, -call_shared generate SVR4 position independent code\n\
14769 -non_shared do not generate position independent code\n\
14770 -xgot assume a 32 bit GOT\n\
14771 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14772 -mabi=ABI create ABI conformant object file for:\n"));
14776 show (stream, "32", &column, &first);
14777 show (stream, "o64", &column, &first);
14778 show (stream, "n32", &column, &first);
14779 show (stream, "64", &column, &first);
14780 show (stream, "eabi", &column, &first);
14782 fputc ('\n', stream);
14784 fprintf (stream, _("\
14785 -32 create o32 ABI object file (default)\n\
14786 -n32 create n32 ABI object file\n\
14787 -64 create 64 ABI object file\n"));
14792 mips_dwarf2_format (void)
14794 if (mips_abi == N64_ABI)
14797 return dwarf2_format_64bit_irix;
14799 return dwarf2_format_64bit;
14803 return dwarf2_format_32bit;