1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
1171 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1174 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1179 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1186 /* Sign-extend 16-bit value X. */
1187 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1189 /* Is the given value a sign-extended 32-bit value? */
1190 #define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1194 /* Is the given value a sign-extended 16-bit value? */
1195 #define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1199 /* Is the given value a sign-extended 12-bit value? */
1200 #define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1203 /* Is the given value a sign-extended 9-bit value? */
1204 #define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1207 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208 #define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1212 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1214 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1217 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1218 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1223 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
1228 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229 #define MIPS16_EXTEND (0xf000U << 16)
1231 /* Whether or not we are emitting a branch-likely macro. */
1232 static bfd_boolean emit_branch_likely_macro = FALSE;
1234 /* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes[2];
1251 /* The symbol on which the choice of sequence depends. */
1255 /* Global variables used to decide whether a macro needs a warning. */
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p;
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length;
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1268 unsigned int sizes[2];
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes[2];
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns[2];
1287 /* The first variant frag for this macro. */
1289 } mips_macro_warning;
1291 /* Prototypes for static functions. */
1293 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1295 static void append_insn
1296 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1297 bfd_boolean expansionp);
1298 static void mips_no_prev_insn (void);
1299 static void macro_build (expressionS *, const char *, const char *, ...);
1300 static void mips16_macro_build
1301 (expressionS *, const char *, const char *, va_list *);
1302 static void load_register (int, expressionS *, int);
1303 static void macro_start (void);
1304 static void macro_end (void);
1305 static void macro (struct mips_cl_insn *ip, char *str);
1306 static void mips16_macro (struct mips_cl_insn * ip);
1307 static void mips_ip (char *str, struct mips_cl_insn * ip);
1308 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1309 static void mips16_immed
1310 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1311 unsigned int, unsigned long *);
1312 static size_t my_getSmallExpression
1313 (expressionS *, bfd_reloc_code_real_type *, char *);
1314 static void my_getExpression (expressionS *, char *);
1315 static void s_align (int);
1316 static void s_change_sec (int);
1317 static void s_change_section (int);
1318 static void s_cons (int);
1319 static void s_float_cons (int);
1320 static void s_mips_globl (int);
1321 static void s_option (int);
1322 static void s_mipsset (int);
1323 static void s_abicalls (int);
1324 static void s_cpload (int);
1325 static void s_cpsetup (int);
1326 static void s_cplocal (int);
1327 static void s_cprestore (int);
1328 static void s_cpreturn (int);
1329 static void s_dtprelword (int);
1330 static void s_dtpreldword (int);
1331 static void s_tprelword (int);
1332 static void s_tpreldword (int);
1333 static void s_gpvalue (int);
1334 static void s_gpword (int);
1335 static void s_gpdword (int);
1336 static void s_ehword (int);
1337 static void s_cpadd (int);
1338 static void s_insn (int);
1339 static void s_nan (int);
1340 static void s_module (int);
1341 static void s_mips_ent (int);
1342 static void s_mips_end (int);
1343 static void s_mips_frame (int);
1344 static void s_mips_mask (int reg_type);
1345 static void s_mips_stab (int);
1346 static void s_mips_weakext (int);
1347 static void s_mips_file (int);
1348 static void s_mips_loc (int);
1349 static bfd_boolean pic_need_relax (symbolS *, asection *);
1350 static int relaxed_branch_length (fragS *, asection *, int);
1351 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1352 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1353 static void file_mips_check_options (void);
1355 /* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1358 struct mips_cpu_info
1360 const char *name; /* CPU or ISA name. */
1361 int flags; /* MIPS_CPU_* flags. */
1362 int ase; /* Set of ASEs implemented by the CPU. */
1363 int isa; /* ISA level. */
1364 int cpu; /* CPU number (default CPU if ISA). */
1367 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1369 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1371 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1373 /* Command-line options. */
1374 const char *md_shortopts = "O::g::G:";
1378 OPTION_MARCH = OPTION_MD_BASE,
1410 OPTION_NO_SMARTMIPS,
1420 OPTION_NO_MICROMIPS,
1423 OPTION_COMPAT_ARCH_BASE,
1432 OPTION_M7000_HILO_FIX,
1433 OPTION_MNO_7000_HILO_FIX,
1437 OPTION_NO_FIX_RM7000,
1438 OPTION_FIX_LOONGSON2F_JUMP,
1439 OPTION_NO_FIX_LOONGSON2F_JUMP,
1440 OPTION_FIX_LOONGSON2F_NOP,
1441 OPTION_NO_FIX_LOONGSON2F_NOP,
1443 OPTION_NO_FIX_VR4120,
1445 OPTION_NO_FIX_VR4130,
1446 OPTION_FIX_CN63XXP1,
1447 OPTION_NO_FIX_CN63XXP1,
1454 OPTION_CONSTRUCT_FLOATS,
1455 OPTION_NO_CONSTRUCT_FLOATS,
1459 OPTION_RELAX_BRANCH,
1460 OPTION_NO_RELAX_BRANCH,
1469 OPTION_SINGLE_FLOAT,
1470 OPTION_DOUBLE_FLOAT,
1483 OPTION_MVXWORKS_PIC,
1486 OPTION_NO_ODD_SPREG,
1490 struct option md_longopts[] =
1492 /* Options which specify architecture. */
1493 {"march", required_argument, NULL, OPTION_MARCH},
1494 {"mtune", required_argument, NULL, OPTION_MTUNE},
1495 {"mips0", no_argument, NULL, OPTION_MIPS1},
1496 {"mips1", no_argument, NULL, OPTION_MIPS1},
1497 {"mips2", no_argument, NULL, OPTION_MIPS2},
1498 {"mips3", no_argument, NULL, OPTION_MIPS3},
1499 {"mips4", no_argument, NULL, OPTION_MIPS4},
1500 {"mips5", no_argument, NULL, OPTION_MIPS5},
1501 {"mips32", no_argument, NULL, OPTION_MIPS32},
1502 {"mips64", no_argument, NULL, OPTION_MIPS64},
1503 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1504 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1505 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1506 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1507 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1508 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1509 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1510 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1512 /* Options which specify Application Specific Extensions (ASEs). */
1513 {"mips16", no_argument, NULL, OPTION_MIPS16},
1514 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1515 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1516 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1517 {"mdmx", no_argument, NULL, OPTION_MDMX},
1518 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1519 {"mdsp", no_argument, NULL, OPTION_DSP},
1520 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1521 {"mmt", no_argument, NULL, OPTION_MT},
1522 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1523 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1524 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1525 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1526 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1527 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1528 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1529 {"meva", no_argument, NULL, OPTION_EVA},
1530 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1531 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1532 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1533 {"mmcu", no_argument, NULL, OPTION_MCU},
1534 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1535 {"mvirt", no_argument, NULL, OPTION_VIRT},
1536 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1537 {"mmsa", no_argument, NULL, OPTION_MSA},
1538 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1539 {"mxpa", no_argument, NULL, OPTION_XPA},
1540 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1542 /* Old-style architecture options. Don't add more of these. */
1543 {"m4650", no_argument, NULL, OPTION_M4650},
1544 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1545 {"m4010", no_argument, NULL, OPTION_M4010},
1546 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1547 {"m4100", no_argument, NULL, OPTION_M4100},
1548 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1549 {"m3900", no_argument, NULL, OPTION_M3900},
1550 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1552 /* Options which enable bug fixes. */
1553 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1554 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1555 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1556 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1557 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1558 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1559 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1560 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1561 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1562 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1563 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1564 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1565 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1566 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1567 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1568 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1569 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1571 /* Miscellaneous options. */
1572 {"trap", no_argument, NULL, OPTION_TRAP},
1573 {"no-break", no_argument, NULL, OPTION_TRAP},
1574 {"break", no_argument, NULL, OPTION_BREAK},
1575 {"no-trap", no_argument, NULL, OPTION_BREAK},
1576 {"EB", no_argument, NULL, OPTION_EB},
1577 {"EL", no_argument, NULL, OPTION_EL},
1578 {"mfp32", no_argument, NULL, OPTION_FP32},
1579 {"mgp32", no_argument, NULL, OPTION_GP32},
1580 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1581 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1582 {"mfp64", no_argument, NULL, OPTION_FP64},
1583 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1584 {"mgp64", no_argument, NULL, OPTION_GP64},
1585 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1586 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1587 {"minsn32", no_argument, NULL, OPTION_INSN32},
1588 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1589 {"mshared", no_argument, NULL, OPTION_MSHARED},
1590 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1591 {"msym32", no_argument, NULL, OPTION_MSYM32},
1592 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1593 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1594 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1595 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1596 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1597 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1598 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1600 /* Strictly speaking this next option is ELF specific,
1601 but we allow it for other ports as well in order to
1602 make testing easier. */
1603 {"32", no_argument, NULL, OPTION_32},
1605 /* ELF-specific options. */
1606 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1607 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1608 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1609 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1610 {"xgot", no_argument, NULL, OPTION_XGOT},
1611 {"mabi", required_argument, NULL, OPTION_MABI},
1612 {"n32", no_argument, NULL, OPTION_N32},
1613 {"64", no_argument, NULL, OPTION_64},
1614 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1615 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1616 {"mpdr", no_argument, NULL, OPTION_PDR},
1617 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1618 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1619 {"mnan", required_argument, NULL, OPTION_NAN},
1621 {NULL, no_argument, NULL, 0}
1623 size_t md_longopts_size = sizeof (md_longopts);
1625 /* Information about either an Application Specific Extension or an
1626 optional architecture feature that, for simplicity, we treat in the
1627 same way as an ASE. */
1630 /* The name of the ASE, used in both the command-line and .set options. */
1633 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1634 and 64-bit architectures, the flags here refer to the subset that
1635 is available on both. */
1638 /* The ASE_* flag used for instructions that are available on 64-bit
1639 architectures but that are not included in FLAGS. */
1640 unsigned int flags64;
1642 /* The command-line options that turn the ASE on and off. */
1646 /* The minimum required architecture revisions for MIPS32, MIPS64,
1647 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1650 int micromips32_rev;
1651 int micromips64_rev;
1653 /* The architecture where the ASE was removed or -1 if the extension has not
1658 /* A table of all supported ASEs. */
1659 static const struct mips_ase mips_ases[] = {
1660 { "dsp", ASE_DSP, ASE_DSP64,
1661 OPTION_DSP, OPTION_NO_DSP,
1665 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1666 OPTION_DSPR2, OPTION_NO_DSPR2,
1670 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1671 OPTION_DSPR3, OPTION_NO_DSPR3,
1675 { "eva", ASE_EVA, 0,
1676 OPTION_EVA, OPTION_NO_EVA,
1680 { "mcu", ASE_MCU, 0,
1681 OPTION_MCU, OPTION_NO_MCU,
1685 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1686 { "mdmx", ASE_MDMX, 0,
1687 OPTION_MDMX, OPTION_NO_MDMX,
1691 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1692 { "mips3d", ASE_MIPS3D, 0,
1693 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1698 OPTION_MT, OPTION_NO_MT,
1702 { "smartmips", ASE_SMARTMIPS, 0,
1703 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1707 { "virt", ASE_VIRT, ASE_VIRT64,
1708 OPTION_VIRT, OPTION_NO_VIRT,
1712 { "msa", ASE_MSA, ASE_MSA64,
1713 OPTION_MSA, OPTION_NO_MSA,
1717 { "xpa", ASE_XPA, 0,
1718 OPTION_XPA, OPTION_NO_XPA,
1723 /* The set of ASEs that require -mfp64. */
1724 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1726 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1727 static const unsigned int mips_ase_groups[] = {
1728 ASE_DSP | ASE_DSPR2 | ASE_DSPR3
1733 The following pseudo-ops from the Kane and Heinrich MIPS book
1734 should be defined here, but are currently unsupported: .alias,
1735 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1737 The following pseudo-ops from the Kane and Heinrich MIPS book are
1738 specific to the type of debugging information being generated, and
1739 should be defined by the object format: .aent, .begin, .bend,
1740 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1743 The following pseudo-ops from the Kane and Heinrich MIPS book are
1744 not MIPS CPU specific, but are also not specific to the object file
1745 format. This file is probably the best place to define them, but
1746 they are not currently supported: .asm0, .endr, .lab, .struct. */
1748 static const pseudo_typeS mips_pseudo_table[] =
1750 /* MIPS specific pseudo-ops. */
1751 {"option", s_option, 0},
1752 {"set", s_mipsset, 0},
1753 {"rdata", s_change_sec, 'r'},
1754 {"sdata", s_change_sec, 's'},
1755 {"livereg", s_ignore, 0},
1756 {"abicalls", s_abicalls, 0},
1757 {"cpload", s_cpload, 0},
1758 {"cpsetup", s_cpsetup, 0},
1759 {"cplocal", s_cplocal, 0},
1760 {"cprestore", s_cprestore, 0},
1761 {"cpreturn", s_cpreturn, 0},
1762 {"dtprelword", s_dtprelword, 0},
1763 {"dtpreldword", s_dtpreldword, 0},
1764 {"tprelword", s_tprelword, 0},
1765 {"tpreldword", s_tpreldword, 0},
1766 {"gpvalue", s_gpvalue, 0},
1767 {"gpword", s_gpword, 0},
1768 {"gpdword", s_gpdword, 0},
1769 {"ehword", s_ehword, 0},
1770 {"cpadd", s_cpadd, 0},
1771 {"insn", s_insn, 0},
1773 {"module", s_module, 0},
1775 /* Relatively generic pseudo-ops that happen to be used on MIPS
1777 {"asciiz", stringer, 8 + 1},
1778 {"bss", s_change_sec, 'b'},
1780 {"half", s_cons, 1},
1781 {"dword", s_cons, 3},
1782 {"weakext", s_mips_weakext, 0},
1783 {"origin", s_org, 0},
1784 {"repeat", s_rept, 0},
1786 /* For MIPS this is non-standard, but we define it for consistency. */
1787 {"sbss", s_change_sec, 'B'},
1789 /* These pseudo-ops are defined in read.c, but must be overridden
1790 here for one reason or another. */
1791 {"align", s_align, 0},
1792 {"byte", s_cons, 0},
1793 {"data", s_change_sec, 'd'},
1794 {"double", s_float_cons, 'd'},
1795 {"float", s_float_cons, 'f'},
1796 {"globl", s_mips_globl, 0},
1797 {"global", s_mips_globl, 0},
1798 {"hword", s_cons, 1},
1800 {"long", s_cons, 2},
1801 {"octa", s_cons, 4},
1802 {"quad", s_cons, 3},
1803 {"section", s_change_section, 0},
1804 {"short", s_cons, 1},
1805 {"single", s_float_cons, 'f'},
1806 {"stabd", s_mips_stab, 'd'},
1807 {"stabn", s_mips_stab, 'n'},
1808 {"stabs", s_mips_stab, 's'},
1809 {"text", s_change_sec, 't'},
1810 {"word", s_cons, 2},
1812 { "extern", ecoff_directive_extern, 0},
1817 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1819 /* These pseudo-ops should be defined by the object file format.
1820 However, a.out doesn't support them, so we have versions here. */
1821 {"aent", s_mips_ent, 1},
1822 {"bgnb", s_ignore, 0},
1823 {"end", s_mips_end, 0},
1824 {"endb", s_ignore, 0},
1825 {"ent", s_mips_ent, 0},
1826 {"file", s_mips_file, 0},
1827 {"fmask", s_mips_mask, 'F'},
1828 {"frame", s_mips_frame, 0},
1829 {"loc", s_mips_loc, 0},
1830 {"mask", s_mips_mask, 'R'},
1831 {"verstamp", s_ignore, 0},
1835 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1836 purpose of the `.dc.a' internal pseudo-op. */
1839 mips_address_bytes (void)
1841 file_mips_check_options ();
1842 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1845 extern void pop_insert (const pseudo_typeS *);
1848 mips_pop_insert (void)
1850 pop_insert (mips_pseudo_table);
1851 if (! ECOFF_DEBUGGING)
1852 pop_insert (mips_nonecoff_pseudo_table);
1855 /* Symbols labelling the current insn. */
1857 struct insn_label_list
1859 struct insn_label_list *next;
1863 static struct insn_label_list *free_insn_labels;
1864 #define label_list tc_segment_info_data.labels
1866 static void mips_clear_insn_labels (void);
1867 static void mips_mark_labels (void);
1868 static void mips_compressed_mark_labels (void);
1871 mips_clear_insn_labels (void)
1873 struct insn_label_list **pl;
1874 segment_info_type *si;
1878 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1881 si = seg_info (now_seg);
1882 *pl = si->label_list;
1883 si->label_list = NULL;
1887 /* Mark instruction labels in MIPS16/microMIPS mode. */
1890 mips_mark_labels (void)
1892 if (HAVE_CODE_COMPRESSION)
1893 mips_compressed_mark_labels ();
1896 static char *expr_end;
1898 /* An expression in a macro instruction. This is set by mips_ip and
1899 mips16_ip and when populated is always an O_constant. */
1901 static expressionS imm_expr;
1903 /* The relocatable field in an instruction and the relocs associated
1904 with it. These variables are used for instructions like LUI and
1905 JAL as well as true offsets. They are also used for address
1906 operands in macros. */
1908 static expressionS offset_expr;
1909 static bfd_reloc_code_real_type offset_reloc[3]
1910 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1912 /* This is set to the resulting size of the instruction to be produced
1913 by mips16_ip if an explicit extension is used or by mips_ip if an
1914 explicit size is supplied. */
1916 static unsigned int forced_insn_length;
1918 /* True if we are assembling an instruction. All dot symbols defined during
1919 this time should be treated as code labels. */
1921 static bfd_boolean mips_assembling_insn;
1923 /* The pdr segment for per procedure frame/regmask info. Not used for
1926 static segT pdr_seg;
1928 /* The default target format to use. */
1930 #if defined (TE_FreeBSD)
1931 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1932 #elif defined (TE_TMIPS)
1933 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1935 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1939 mips_target_format (void)
1941 switch (OUTPUT_FLAVOR)
1943 case bfd_target_elf_flavour:
1945 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1946 return (target_big_endian
1947 ? "elf32-bigmips-vxworks"
1948 : "elf32-littlemips-vxworks");
1950 return (target_big_endian
1951 ? (HAVE_64BIT_OBJECTS
1952 ? ELF_TARGET ("elf64-", "big")
1954 ? ELF_TARGET ("elf32-n", "big")
1955 : ELF_TARGET ("elf32-", "big")))
1956 : (HAVE_64BIT_OBJECTS
1957 ? ELF_TARGET ("elf64-", "little")
1959 ? ELF_TARGET ("elf32-n", "little")
1960 : ELF_TARGET ("elf32-", "little"))));
1967 /* Return the ISA revision that is currently in use, or 0 if we are
1968 generating code for MIPS V or below. */
1973 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1976 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1979 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1982 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1985 /* microMIPS implies revision 2 or above. */
1986 if (mips_opts.micromips)
1989 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1995 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1998 mips_ase_mask (unsigned int flags)
2002 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2003 if (flags & mips_ase_groups[i])
2004 flags |= mips_ase_groups[i];
2008 /* Check whether the current ISA supports ASE. Issue a warning if
2012 mips_check_isa_supports_ase (const struct mips_ase *ase)
2016 static unsigned int warned_isa;
2017 static unsigned int warned_fp32;
2019 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2020 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2022 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2023 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2024 && (warned_isa & ase->flags) != ase->flags)
2026 warned_isa |= ase->flags;
2027 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2028 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2030 as_warn (_("the %d-bit %s architecture does not support the"
2031 " `%s' extension"), size, base, ase->name);
2033 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2034 ase->name, base, size, min_rev);
2036 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2037 && (warned_isa & ase->flags) != ase->flags)
2039 warned_isa |= ase->flags;
2040 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2041 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2042 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2043 ase->name, base, size, ase->rem_rev);
2046 if ((ase->flags & FP64_ASES)
2047 && mips_opts.fp != 64
2048 && (warned_fp32 & ase->flags) != ase->flags)
2050 warned_fp32 |= ase->flags;
2051 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2055 /* Check all enabled ASEs to see whether they are supported by the
2056 chosen architecture. */
2059 mips_check_isa_supports_ases (void)
2061 unsigned int i, mask;
2063 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2065 mask = mips_ase_mask (mips_ases[i].flags);
2066 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2067 mips_check_isa_supports_ase (&mips_ases[i]);
2071 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2072 that were affected. */
2075 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2076 bfd_boolean enabled_p)
2080 mask = mips_ase_mask (ase->flags);
2083 opts->ase |= ase->flags;
2087 /* Return the ASE called NAME, or null if none. */
2089 static const struct mips_ase *
2090 mips_lookup_ase (const char *name)
2094 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2095 if (strcmp (name, mips_ases[i].name) == 0)
2096 return &mips_ases[i];
2100 /* Return the length of a microMIPS instruction in bytes. If bits of
2101 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2102 otherwise it is a 32-bit instruction. */
2104 static inline unsigned int
2105 micromips_insn_length (const struct mips_opcode *mo)
2107 return (mo->mask >> 16) == 0 ? 2 : 4;
2110 /* Return the length of MIPS16 instruction OPCODE. */
2112 static inline unsigned int
2113 mips16_opcode_length (unsigned long opcode)
2115 return (opcode >> 16) == 0 ? 2 : 4;
2118 /* Return the length of instruction INSN. */
2120 static inline unsigned int
2121 insn_length (const struct mips_cl_insn *insn)
2123 if (mips_opts.micromips)
2124 return micromips_insn_length (insn->insn_mo);
2125 else if (mips_opts.mips16)
2126 return mips16_opcode_length (insn->insn_opcode);
2131 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2134 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2139 insn->insn_opcode = mo->match;
2142 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2143 insn->fixp[i] = NULL;
2144 insn->fixed_p = (mips_opts.noreorder > 0);
2145 insn->noreorder_p = (mips_opts.noreorder > 0);
2146 insn->mips16_absolute_jump_p = 0;
2147 insn->complete_p = 0;
2148 insn->cleared_p = 0;
2151 /* Get a list of all the operands in INSN. */
2153 static const struct mips_operand_array *
2154 insn_operands (const struct mips_cl_insn *insn)
2156 if (insn->insn_mo >= &mips_opcodes[0]
2157 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2158 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2160 if (insn->insn_mo >= &mips16_opcodes[0]
2161 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2162 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2164 if (insn->insn_mo >= µmips_opcodes[0]
2165 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2166 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2171 /* Get a description of operand OPNO of INSN. */
2173 static const struct mips_operand *
2174 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2176 const struct mips_operand_array *operands;
2178 operands = insn_operands (insn);
2179 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2181 return operands->operand[opno];
2184 /* Install UVAL as the value of OPERAND in INSN. */
2187 insn_insert_operand (struct mips_cl_insn *insn,
2188 const struct mips_operand *operand, unsigned int uval)
2190 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2193 /* Extract the value of OPERAND from INSN. */
2195 static inline unsigned
2196 insn_extract_operand (const struct mips_cl_insn *insn,
2197 const struct mips_operand *operand)
2199 return mips_extract_operand (operand, insn->insn_opcode);
2202 /* Record the current MIPS16/microMIPS mode in now_seg. */
2205 mips_record_compressed_mode (void)
2207 segment_info_type *si;
2209 si = seg_info (now_seg);
2210 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2211 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2212 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2213 si->tc_segment_info_data.micromips = mips_opts.micromips;
2216 /* Read a standard MIPS instruction from BUF. */
2218 static unsigned long
2219 read_insn (char *buf)
2221 if (target_big_endian)
2222 return bfd_getb32 ((bfd_byte *) buf);
2224 return bfd_getl32 ((bfd_byte *) buf);
2227 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2231 write_insn (char *buf, unsigned int insn)
2233 md_number_to_chars (buf, insn, 4);
2237 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2238 has length LENGTH. */
2240 static unsigned long
2241 read_compressed_insn (char *buf, unsigned int length)
2247 for (i = 0; i < length; i += 2)
2250 if (target_big_endian)
2251 insn |= bfd_getb16 ((char *) buf);
2253 insn |= bfd_getl16 ((char *) buf);
2259 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2260 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2263 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2267 for (i = 0; i < length; i += 2)
2268 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2269 return buf + length;
2272 /* Install INSN at the location specified by its "frag" and "where" fields. */
2275 install_insn (const struct mips_cl_insn *insn)
2277 char *f = insn->frag->fr_literal + insn->where;
2278 if (HAVE_CODE_COMPRESSION)
2279 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2281 write_insn (f, insn->insn_opcode);
2282 mips_record_compressed_mode ();
2285 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2286 and install the opcode in the new location. */
2289 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2294 insn->where = where;
2295 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2296 if (insn->fixp[i] != NULL)
2298 insn->fixp[i]->fx_frag = frag;
2299 insn->fixp[i]->fx_where = where;
2301 install_insn (insn);
2304 /* Add INSN to the end of the output. */
2307 add_fixed_insn (struct mips_cl_insn *insn)
2309 char *f = frag_more (insn_length (insn));
2310 move_insn (insn, frag_now, f - frag_now->fr_literal);
2313 /* Start a variant frag and move INSN to the start of the variant part,
2314 marking it as fixed. The other arguments are as for frag_var. */
2317 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2318 relax_substateT subtype, symbolS *symbol, offsetT offset)
2320 frag_grow (max_chars);
2321 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2323 frag_var (rs_machine_dependent, max_chars, var,
2324 subtype, symbol, offset, NULL);
2327 /* Insert N copies of INSN into the history buffer, starting at
2328 position FIRST. Neither FIRST nor N need to be clipped. */
2331 insert_into_history (unsigned int first, unsigned int n,
2332 const struct mips_cl_insn *insn)
2334 if (mips_relax.sequence != 2)
2338 for (i = ARRAY_SIZE (history); i-- > first;)
2340 history[i] = history[i - n];
2346 /* Clear the error in insn_error. */
2349 clear_insn_error (void)
2351 memset (&insn_error, 0, sizeof (insn_error));
2354 /* Possibly record error message MSG for the current instruction.
2355 If the error is about a particular argument, ARGNUM is the 1-based
2356 number of that argument, otherwise it is 0. FORMAT is the format
2357 of MSG. Return true if MSG was used, false if the current message
2361 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2366 /* Give priority to errors against specific arguments, and to
2367 the first whole-instruction message. */
2373 /* Keep insn_error if it is against a later argument. */
2374 if (argnum < insn_error.min_argnum)
2377 /* If both errors are against the same argument but are different,
2378 give up on reporting a specific error for this argument.
2379 See the comment about mips_insn_error for details. */
2380 if (argnum == insn_error.min_argnum
2382 && strcmp (insn_error.msg, msg) != 0)
2385 insn_error.min_argnum += 1;
2389 insn_error.min_argnum = argnum;
2390 insn_error.format = format;
2391 insn_error.msg = msg;
2395 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2396 as for set_insn_error_format. */
2399 set_insn_error (int argnum, const char *msg)
2401 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2404 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2405 as for set_insn_error_format. */
2408 set_insn_error_i (int argnum, const char *msg, int i)
2410 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2414 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2415 are as for set_insn_error_format. */
2418 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2420 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2422 insn_error.u.ss[0] = s1;
2423 insn_error.u.ss[1] = s2;
2427 /* Report the error in insn_error, which is against assembly code STR. */
2430 report_insn_error (const char *str)
2432 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2434 switch (insn_error.format)
2441 as_bad (msg, insn_error.u.i, str);
2445 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2449 free ((char *) msg);
2452 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2453 the idea is to make it obvious at a glance that each errata is
2457 init_vr4120_conflicts (void)
2459 #define CONFLICT(FIRST, SECOND) \
2460 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2462 /* Errata 21 - [D]DIV[U] after [D]MACC */
2463 CONFLICT (MACC, DIV);
2464 CONFLICT (DMACC, DIV);
2466 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2467 CONFLICT (DMULT, DMULT);
2468 CONFLICT (DMULT, DMACC);
2469 CONFLICT (DMACC, DMULT);
2470 CONFLICT (DMACC, DMACC);
2472 /* Errata 24 - MT{LO,HI} after [D]MACC */
2473 CONFLICT (MACC, MTHILO);
2474 CONFLICT (DMACC, MTHILO);
2476 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2477 instruction is executed immediately after a MACC or DMACC
2478 instruction, the result of [either instruction] is incorrect." */
2479 CONFLICT (MACC, MULT);
2480 CONFLICT (MACC, DMULT);
2481 CONFLICT (DMACC, MULT);
2482 CONFLICT (DMACC, DMULT);
2484 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2485 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2486 DDIV or DDIVU instruction, the result of the MACC or
2487 DMACC instruction is incorrect.". */
2488 CONFLICT (DMULT, MACC);
2489 CONFLICT (DMULT, DMACC);
2490 CONFLICT (DIV, MACC);
2491 CONFLICT (DIV, DMACC);
2501 #define RNUM_MASK 0x00000ff
2502 #define RTYPE_MASK 0x0ffff00
2503 #define RTYPE_NUM 0x0000100
2504 #define RTYPE_FPU 0x0000200
2505 #define RTYPE_FCC 0x0000400
2506 #define RTYPE_VEC 0x0000800
2507 #define RTYPE_GP 0x0001000
2508 #define RTYPE_CP0 0x0002000
2509 #define RTYPE_PC 0x0004000
2510 #define RTYPE_ACC 0x0008000
2511 #define RTYPE_CCC 0x0010000
2512 #define RTYPE_VI 0x0020000
2513 #define RTYPE_VF 0x0040000
2514 #define RTYPE_R5900_I 0x0080000
2515 #define RTYPE_R5900_Q 0x0100000
2516 #define RTYPE_R5900_R 0x0200000
2517 #define RTYPE_R5900_ACC 0x0400000
2518 #define RTYPE_MSA 0x0800000
2519 #define RWARN 0x8000000
2521 #define GENERIC_REGISTER_NUMBERS \
2522 {"$0", RTYPE_NUM | 0}, \
2523 {"$1", RTYPE_NUM | 1}, \
2524 {"$2", RTYPE_NUM | 2}, \
2525 {"$3", RTYPE_NUM | 3}, \
2526 {"$4", RTYPE_NUM | 4}, \
2527 {"$5", RTYPE_NUM | 5}, \
2528 {"$6", RTYPE_NUM | 6}, \
2529 {"$7", RTYPE_NUM | 7}, \
2530 {"$8", RTYPE_NUM | 8}, \
2531 {"$9", RTYPE_NUM | 9}, \
2532 {"$10", RTYPE_NUM | 10}, \
2533 {"$11", RTYPE_NUM | 11}, \
2534 {"$12", RTYPE_NUM | 12}, \
2535 {"$13", RTYPE_NUM | 13}, \
2536 {"$14", RTYPE_NUM | 14}, \
2537 {"$15", RTYPE_NUM | 15}, \
2538 {"$16", RTYPE_NUM | 16}, \
2539 {"$17", RTYPE_NUM | 17}, \
2540 {"$18", RTYPE_NUM | 18}, \
2541 {"$19", RTYPE_NUM | 19}, \
2542 {"$20", RTYPE_NUM | 20}, \
2543 {"$21", RTYPE_NUM | 21}, \
2544 {"$22", RTYPE_NUM | 22}, \
2545 {"$23", RTYPE_NUM | 23}, \
2546 {"$24", RTYPE_NUM | 24}, \
2547 {"$25", RTYPE_NUM | 25}, \
2548 {"$26", RTYPE_NUM | 26}, \
2549 {"$27", RTYPE_NUM | 27}, \
2550 {"$28", RTYPE_NUM | 28}, \
2551 {"$29", RTYPE_NUM | 29}, \
2552 {"$30", RTYPE_NUM | 30}, \
2553 {"$31", RTYPE_NUM | 31}
2555 #define FPU_REGISTER_NAMES \
2556 {"$f0", RTYPE_FPU | 0}, \
2557 {"$f1", RTYPE_FPU | 1}, \
2558 {"$f2", RTYPE_FPU | 2}, \
2559 {"$f3", RTYPE_FPU | 3}, \
2560 {"$f4", RTYPE_FPU | 4}, \
2561 {"$f5", RTYPE_FPU | 5}, \
2562 {"$f6", RTYPE_FPU | 6}, \
2563 {"$f7", RTYPE_FPU | 7}, \
2564 {"$f8", RTYPE_FPU | 8}, \
2565 {"$f9", RTYPE_FPU | 9}, \
2566 {"$f10", RTYPE_FPU | 10}, \
2567 {"$f11", RTYPE_FPU | 11}, \
2568 {"$f12", RTYPE_FPU | 12}, \
2569 {"$f13", RTYPE_FPU | 13}, \
2570 {"$f14", RTYPE_FPU | 14}, \
2571 {"$f15", RTYPE_FPU | 15}, \
2572 {"$f16", RTYPE_FPU | 16}, \
2573 {"$f17", RTYPE_FPU | 17}, \
2574 {"$f18", RTYPE_FPU | 18}, \
2575 {"$f19", RTYPE_FPU | 19}, \
2576 {"$f20", RTYPE_FPU | 20}, \
2577 {"$f21", RTYPE_FPU | 21}, \
2578 {"$f22", RTYPE_FPU | 22}, \
2579 {"$f23", RTYPE_FPU | 23}, \
2580 {"$f24", RTYPE_FPU | 24}, \
2581 {"$f25", RTYPE_FPU | 25}, \
2582 {"$f26", RTYPE_FPU | 26}, \
2583 {"$f27", RTYPE_FPU | 27}, \
2584 {"$f28", RTYPE_FPU | 28}, \
2585 {"$f29", RTYPE_FPU | 29}, \
2586 {"$f30", RTYPE_FPU | 30}, \
2587 {"$f31", RTYPE_FPU | 31}
2589 #define FPU_CONDITION_CODE_NAMES \
2590 {"$fcc0", RTYPE_FCC | 0}, \
2591 {"$fcc1", RTYPE_FCC | 1}, \
2592 {"$fcc2", RTYPE_FCC | 2}, \
2593 {"$fcc3", RTYPE_FCC | 3}, \
2594 {"$fcc4", RTYPE_FCC | 4}, \
2595 {"$fcc5", RTYPE_FCC | 5}, \
2596 {"$fcc6", RTYPE_FCC | 6}, \
2597 {"$fcc7", RTYPE_FCC | 7}
2599 #define COPROC_CONDITION_CODE_NAMES \
2600 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2601 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2602 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2603 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2604 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2605 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2606 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2607 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2609 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2610 {"$a4", RTYPE_GP | 8}, \
2611 {"$a5", RTYPE_GP | 9}, \
2612 {"$a6", RTYPE_GP | 10}, \
2613 {"$a7", RTYPE_GP | 11}, \
2614 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2615 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2616 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2617 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2618 {"$t0", RTYPE_GP | 12}, \
2619 {"$t1", RTYPE_GP | 13}, \
2620 {"$t2", RTYPE_GP | 14}, \
2621 {"$t3", RTYPE_GP | 15}
2623 #define O32_SYMBOLIC_REGISTER_NAMES \
2624 {"$t0", RTYPE_GP | 8}, \
2625 {"$t1", RTYPE_GP | 9}, \
2626 {"$t2", RTYPE_GP | 10}, \
2627 {"$t3", RTYPE_GP | 11}, \
2628 {"$t4", RTYPE_GP | 12}, \
2629 {"$t5", RTYPE_GP | 13}, \
2630 {"$t6", RTYPE_GP | 14}, \
2631 {"$t7", RTYPE_GP | 15}, \
2632 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2633 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2634 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2635 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2637 /* Remaining symbolic register names */
2638 #define SYMBOLIC_REGISTER_NAMES \
2639 {"$zero", RTYPE_GP | 0}, \
2640 {"$at", RTYPE_GP | 1}, \
2641 {"$AT", RTYPE_GP | 1}, \
2642 {"$v0", RTYPE_GP | 2}, \
2643 {"$v1", RTYPE_GP | 3}, \
2644 {"$a0", RTYPE_GP | 4}, \
2645 {"$a1", RTYPE_GP | 5}, \
2646 {"$a2", RTYPE_GP | 6}, \
2647 {"$a3", RTYPE_GP | 7}, \
2648 {"$s0", RTYPE_GP | 16}, \
2649 {"$s1", RTYPE_GP | 17}, \
2650 {"$s2", RTYPE_GP | 18}, \
2651 {"$s3", RTYPE_GP | 19}, \
2652 {"$s4", RTYPE_GP | 20}, \
2653 {"$s5", RTYPE_GP | 21}, \
2654 {"$s6", RTYPE_GP | 22}, \
2655 {"$s7", RTYPE_GP | 23}, \
2656 {"$t8", RTYPE_GP | 24}, \
2657 {"$t9", RTYPE_GP | 25}, \
2658 {"$k0", RTYPE_GP | 26}, \
2659 {"$kt0", RTYPE_GP | 26}, \
2660 {"$k1", RTYPE_GP | 27}, \
2661 {"$kt1", RTYPE_GP | 27}, \
2662 {"$gp", RTYPE_GP | 28}, \
2663 {"$sp", RTYPE_GP | 29}, \
2664 {"$s8", RTYPE_GP | 30}, \
2665 {"$fp", RTYPE_GP | 30}, \
2666 {"$ra", RTYPE_GP | 31}
2668 #define MIPS16_SPECIAL_REGISTER_NAMES \
2669 {"$pc", RTYPE_PC | 0}
2671 #define MDMX_VECTOR_REGISTER_NAMES \
2672 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2673 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2674 {"$v2", RTYPE_VEC | 2}, \
2675 {"$v3", RTYPE_VEC | 3}, \
2676 {"$v4", RTYPE_VEC | 4}, \
2677 {"$v5", RTYPE_VEC | 5}, \
2678 {"$v6", RTYPE_VEC | 6}, \
2679 {"$v7", RTYPE_VEC | 7}, \
2680 {"$v8", RTYPE_VEC | 8}, \
2681 {"$v9", RTYPE_VEC | 9}, \
2682 {"$v10", RTYPE_VEC | 10}, \
2683 {"$v11", RTYPE_VEC | 11}, \
2684 {"$v12", RTYPE_VEC | 12}, \
2685 {"$v13", RTYPE_VEC | 13}, \
2686 {"$v14", RTYPE_VEC | 14}, \
2687 {"$v15", RTYPE_VEC | 15}, \
2688 {"$v16", RTYPE_VEC | 16}, \
2689 {"$v17", RTYPE_VEC | 17}, \
2690 {"$v18", RTYPE_VEC | 18}, \
2691 {"$v19", RTYPE_VEC | 19}, \
2692 {"$v20", RTYPE_VEC | 20}, \
2693 {"$v21", RTYPE_VEC | 21}, \
2694 {"$v22", RTYPE_VEC | 22}, \
2695 {"$v23", RTYPE_VEC | 23}, \
2696 {"$v24", RTYPE_VEC | 24}, \
2697 {"$v25", RTYPE_VEC | 25}, \
2698 {"$v26", RTYPE_VEC | 26}, \
2699 {"$v27", RTYPE_VEC | 27}, \
2700 {"$v28", RTYPE_VEC | 28}, \
2701 {"$v29", RTYPE_VEC | 29}, \
2702 {"$v30", RTYPE_VEC | 30}, \
2703 {"$v31", RTYPE_VEC | 31}
2705 #define R5900_I_NAMES \
2706 {"$I", RTYPE_R5900_I | 0}
2708 #define R5900_Q_NAMES \
2709 {"$Q", RTYPE_R5900_Q | 0}
2711 #define R5900_R_NAMES \
2712 {"$R", RTYPE_R5900_R | 0}
2714 #define R5900_ACC_NAMES \
2715 {"$ACC", RTYPE_R5900_ACC | 0 }
2717 #define MIPS_DSP_ACCUMULATOR_NAMES \
2718 {"$ac0", RTYPE_ACC | 0}, \
2719 {"$ac1", RTYPE_ACC | 1}, \
2720 {"$ac2", RTYPE_ACC | 2}, \
2721 {"$ac3", RTYPE_ACC | 3}
2723 static const struct regname reg_names[] = {
2724 GENERIC_REGISTER_NUMBERS,
2726 FPU_CONDITION_CODE_NAMES,
2727 COPROC_CONDITION_CODE_NAMES,
2729 /* The $txx registers depends on the abi,
2730 these will be added later into the symbol table from
2731 one of the tables below once mips_abi is set after
2732 parsing of arguments from the command line. */
2733 SYMBOLIC_REGISTER_NAMES,
2735 MIPS16_SPECIAL_REGISTER_NAMES,
2736 MDMX_VECTOR_REGISTER_NAMES,
2741 MIPS_DSP_ACCUMULATOR_NAMES,
2745 static const struct regname reg_names_o32[] = {
2746 O32_SYMBOLIC_REGISTER_NAMES,
2750 static const struct regname reg_names_n32n64[] = {
2751 N32N64_SYMBOLIC_REGISTER_NAMES,
2755 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2756 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2757 of these register symbols, return the associated vector register,
2758 otherwise return SYMVAL itself. */
2761 mips_prefer_vec_regno (unsigned int symval)
2763 if ((symval & -2) == (RTYPE_GP | 2))
2764 return RTYPE_VEC | (symval & 1);
2768 /* Return true if string [S, E) is a valid register name, storing its
2769 symbol value in *SYMVAL_PTR if so. */
2772 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2777 /* Terminate name. */
2781 /* Look up the name. */
2782 symbol = symbol_find (s);
2785 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2788 *symval_ptr = S_GET_VALUE (symbol);
2792 /* Return true if the string at *SPTR is a valid register name. Allow it
2793 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2796 When returning true, move *SPTR past the register, store the
2797 register's symbol value in *SYMVAL_PTR and the channel mask in
2798 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2799 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2800 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2803 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2804 unsigned int *channels_ptr)
2808 unsigned int channels, symval, bit;
2810 /* Find end of name. */
2812 if (is_name_beginner (*e))
2814 while (is_part_of_name (*e))
2818 if (!mips_parse_register_1 (s, e, &symval))
2823 /* Eat characters from the end of the string that are valid
2824 channel suffixes. The preceding register must be $ACC or
2825 end with a digit, so there is no ambiguity. */
2828 for (q = "wzyx"; *q; q++, bit <<= 1)
2829 if (m > s && m[-1] == *q)
2836 || !mips_parse_register_1 (s, m, &symval)
2837 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2842 *symval_ptr = symval;
2844 *channels_ptr = channels;
2848 /* Check if SPTR points at a valid register specifier according to TYPES.
2849 If so, then return 1, advance S to consume the specifier and store
2850 the register's number in REGNOP, otherwise return 0. */
2853 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2857 if (mips_parse_register (s, ®no, NULL))
2859 if (types & RTYPE_VEC)
2860 regno = mips_prefer_vec_regno (regno);
2869 as_warn (_("unrecognized register name `%s'"), *s);
2874 return regno <= RNUM_MASK;
2877 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2878 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2881 mips_parse_vu0_channels (char *s, unsigned int *channels)
2886 for (i = 0; i < 4; i++)
2887 if (*s == "xyzw"[i])
2889 *channels |= 1 << (3 - i);
2895 /* Token types for parsed operand lists. */
2896 enum mips_operand_token_type {
2897 /* A plain register, e.g. $f2. */
2900 /* A 4-bit XYZW channel mask. */
2903 /* A constant vector index, e.g. [1]. */
2906 /* A register vector index, e.g. [$2]. */
2909 /* A continuous range of registers, e.g. $s0-$s4. */
2912 /* A (possibly relocated) expression. */
2915 /* A floating-point value. */
2918 /* A single character. This can be '(', ')' or ',', but '(' only appears
2922 /* A doubled character, either "--" or "++". */
2925 /* The end of the operand list. */
2929 /* A parsed operand token. */
2930 struct mips_operand_token
2932 /* The type of token. */
2933 enum mips_operand_token_type type;
2936 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2939 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2940 unsigned int channels;
2942 /* The integer value of an OT_INTEGER_INDEX. */
2945 /* The two register symbol values involved in an OT_REG_RANGE. */
2947 unsigned int regno1;
2948 unsigned int regno2;
2951 /* The value of an OT_INTEGER. The value is represented as an
2952 expression and the relocation operators that were applied to
2953 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2954 relocation operators were used. */
2957 bfd_reloc_code_real_type relocs[3];
2960 /* The binary data for an OT_FLOAT constant, and the number of bytes
2963 unsigned char data[8];
2967 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2972 /* An obstack used to construct lists of mips_operand_tokens. */
2973 static struct obstack mips_operand_tokens;
2975 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2978 mips_add_token (struct mips_operand_token *token,
2979 enum mips_operand_token_type type)
2982 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2985 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2986 and OT_REG tokens for them if so, and return a pointer to the first
2987 unconsumed character. Return null otherwise. */
2990 mips_parse_base_start (char *s)
2992 struct mips_operand_token token;
2993 unsigned int regno, channels;
2994 bfd_boolean decrement_p;
3000 SKIP_SPACE_TABS (s);
3002 /* Only match "--" as part of a base expression. In other contexts "--X"
3003 is a double negative. */
3004 decrement_p = (s[0] == '-' && s[1] == '-');
3008 SKIP_SPACE_TABS (s);
3011 /* Allow a channel specifier because that leads to better error messages
3012 than treating something like "$vf0x++" as an expression. */
3013 if (!mips_parse_register (&s, ®no, &channels))
3017 mips_add_token (&token, OT_CHAR);
3022 mips_add_token (&token, OT_DOUBLE_CHAR);
3025 token.u.regno = regno;
3026 mips_add_token (&token, OT_REG);
3030 token.u.channels = channels;
3031 mips_add_token (&token, OT_CHANNELS);
3034 /* For consistency, only match "++" as part of base expressions too. */
3035 SKIP_SPACE_TABS (s);
3036 if (s[0] == '+' && s[1] == '+')
3040 mips_add_token (&token, OT_DOUBLE_CHAR);
3046 /* Parse one or more tokens from S. Return a pointer to the first
3047 unconsumed character on success. Return null if an error was found
3048 and store the error text in insn_error. FLOAT_FORMAT is as for
3049 mips_parse_arguments. */
3052 mips_parse_argument_token (char *s, char float_format)
3054 char *end, *save_in;
3056 unsigned int regno1, regno2, channels;
3057 struct mips_operand_token token;
3059 /* First look for "($reg", since we want to treat that as an
3060 OT_CHAR and OT_REG rather than an expression. */
3061 end = mips_parse_base_start (s);
3065 /* Handle other characters that end up as OT_CHARs. */
3066 if (*s == ')' || *s == ',')
3069 mips_add_token (&token, OT_CHAR);
3074 /* Handle tokens that start with a register. */
3075 if (mips_parse_register (&s, ®no1, &channels))
3079 /* A register and a VU0 channel suffix. */
3080 token.u.regno = regno1;
3081 mips_add_token (&token, OT_REG);
3083 token.u.channels = channels;
3084 mips_add_token (&token, OT_CHANNELS);
3088 SKIP_SPACE_TABS (s);
3091 /* A register range. */
3093 SKIP_SPACE_TABS (s);
3094 if (!mips_parse_register (&s, ®no2, NULL))
3096 set_insn_error (0, _("invalid register range"));
3100 token.u.reg_range.regno1 = regno1;
3101 token.u.reg_range.regno2 = regno2;
3102 mips_add_token (&token, OT_REG_RANGE);
3106 /* Add the register itself. */
3107 token.u.regno = regno1;
3108 mips_add_token (&token, OT_REG);
3110 /* Check for a vector index. */
3114 SKIP_SPACE_TABS (s);
3115 if (mips_parse_register (&s, &token.u.regno, NULL))
3116 mips_add_token (&token, OT_REG_INDEX);
3119 expressionS element;
3121 my_getExpression (&element, s);
3122 if (element.X_op != O_constant)
3124 set_insn_error (0, _("vector element must be constant"));
3128 token.u.index = element.X_add_number;
3129 mips_add_token (&token, OT_INTEGER_INDEX);
3131 SKIP_SPACE_TABS (s);
3134 set_insn_error (0, _("missing `]'"));
3144 /* First try to treat expressions as floats. */
3145 save_in = input_line_pointer;
3146 input_line_pointer = s;
3147 err = md_atof (float_format, (char *) token.u.flt.data,
3148 &token.u.flt.length);
3149 end = input_line_pointer;
3150 input_line_pointer = save_in;
3153 set_insn_error (0, err);
3158 mips_add_token (&token, OT_FLOAT);
3163 /* Treat everything else as an integer expression. */
3164 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3165 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3166 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3167 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3169 mips_add_token (&token, OT_INTEGER);
3173 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3174 if expressions should be treated as 32-bit floating-point constants,
3175 'd' if they should be treated as 64-bit floating-point constants,
3176 or 0 if they should be treated as integer expressions (the usual case).
3178 Return a list of tokens on success, otherwise return 0. The caller
3179 must obstack_free the list after use. */
3181 static struct mips_operand_token *
3182 mips_parse_arguments (char *s, char float_format)
3184 struct mips_operand_token token;
3186 SKIP_SPACE_TABS (s);
3189 s = mips_parse_argument_token (s, float_format);
3192 obstack_free (&mips_operand_tokens,
3193 obstack_finish (&mips_operand_tokens));
3196 SKIP_SPACE_TABS (s);
3198 mips_add_token (&token, OT_END);
3199 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3202 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3203 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3206 is_opcode_valid (const struct mips_opcode *mo)
3208 int isa = mips_opts.isa;
3209 int ase = mips_opts.ase;
3213 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3214 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3215 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3216 ase |= mips_ases[i].flags64;
3218 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3221 /* Check whether the instruction or macro requires single-precision or
3222 double-precision floating-point support. Note that this information is
3223 stored differently in the opcode table for insns and macros. */
3224 if (mo->pinfo == INSN_MACRO)
3226 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3227 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3231 fp_s = mo->pinfo & FP_S;
3232 fp_d = mo->pinfo & FP_D;
3235 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3238 if (fp_s && mips_opts.soft_float)
3244 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3245 selected ISA and architecture. */
3248 is_opcode_valid_16 (const struct mips_opcode *mo)
3250 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3253 /* Return TRUE if the size of the microMIPS opcode MO matches one
3254 explicitly requested. Always TRUE in the standard MIPS mode. */
3257 is_size_valid (const struct mips_opcode *mo)
3259 if (!mips_opts.micromips)
3262 if (mips_opts.insn32)
3264 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3266 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3269 if (!forced_insn_length)
3271 if (mo->pinfo == INSN_MACRO)
3273 return forced_insn_length == micromips_insn_length (mo);
3276 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3277 of the preceding instruction. Always TRUE in the standard MIPS mode.
3279 We don't accept macros in 16-bit delay slots to avoid a case where
3280 a macro expansion fails because it relies on a preceding 32-bit real
3281 instruction to have matched and does not handle the operands correctly.
3282 The only macros that may expand to 16-bit instructions are JAL that
3283 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3284 and BGT (that likewise cannot be placed in a delay slot) that decay to
3285 a NOP. In all these cases the macros precede any corresponding real
3286 instruction definitions in the opcode table, so they will match in the
3287 second pass where the size of the delay slot is ignored and therefore
3288 produce correct code. */
3291 is_delay_slot_valid (const struct mips_opcode *mo)
3293 if (!mips_opts.micromips)
3296 if (mo->pinfo == INSN_MACRO)
3297 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3298 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3299 && micromips_insn_length (mo) != 4)
3301 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3302 && micromips_insn_length (mo) != 2)
3308 /* For consistency checking, verify that all bits of OPCODE are specified
3309 either by the match/mask part of the instruction definition, or by the
3310 operand list. Also build up a list of operands in OPERANDS.
3312 INSN_BITS says which bits of the instruction are significant.
3313 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3314 provides the mips_operand description of each operand. DECODE_OPERAND
3315 is null for MIPS16 instructions. */
3318 validate_mips_insn (const struct mips_opcode *opcode,
3319 unsigned long insn_bits,
3320 const struct mips_operand *(*decode_operand) (const char *),
3321 struct mips_operand_array *operands)
3324 unsigned long used_bits, doubled, undefined, opno, mask;
3325 const struct mips_operand *operand;
3327 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3328 if ((mask & opcode->match) != opcode->match)
3330 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3331 opcode->name, opcode->args);
3336 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3337 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3338 for (s = opcode->args; *s; ++s)
3351 if (!decode_operand)
3352 operand = decode_mips16_operand (*s, FALSE);
3354 operand = decode_operand (s);
3355 if (!operand && opcode->pinfo != INSN_MACRO)
3357 as_bad (_("internal: unknown operand type: %s %s"),
3358 opcode->name, opcode->args);
3361 gas_assert (opno < MAX_OPERANDS);
3362 operands->operand[opno] = operand;
3363 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3365 used_bits = mips_insert_operand (operand, used_bits, -1);
3366 if (operand->type == OP_MDMX_IMM_REG)
3367 /* Bit 5 is the format selector (OB vs QH). The opcode table
3368 has separate entries for each format. */
3369 used_bits &= ~(1 << (operand->lsb + 5));
3370 if (operand->type == OP_ENTRY_EXIT_LIST)
3371 used_bits &= ~(mask & 0x700);
3373 /* Skip prefix characters. */
3374 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3379 doubled = used_bits & mask & insn_bits;
3382 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3383 " %s %s"), doubled, opcode->name, opcode->args);
3387 undefined = ~used_bits & insn_bits;
3388 if (opcode->pinfo != INSN_MACRO && undefined)
3390 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3391 undefined, opcode->name, opcode->args);
3394 used_bits &= ~insn_bits;
3397 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3398 used_bits, opcode->name, opcode->args);
3404 /* The MIPS16 version of validate_mips_insn. */
3407 validate_mips16_insn (const struct mips_opcode *opcode,
3408 struct mips_operand_array *operands)
3410 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3412 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3413 instruction. Use TMP to describe the full instruction. */
3414 struct mips_opcode tmp;
3419 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3421 return validate_mips_insn (opcode, 0xffff, 0, operands);
3424 /* The microMIPS version of validate_mips_insn. */
3427 validate_micromips_insn (const struct mips_opcode *opc,
3428 struct mips_operand_array *operands)
3430 unsigned long insn_bits;
3431 unsigned long major;
3432 unsigned int length;
3434 if (opc->pinfo == INSN_MACRO)
3435 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3438 length = micromips_insn_length (opc);
3439 if (length != 2 && length != 4)
3441 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3442 "%s %s"), length, opc->name, opc->args);
3445 major = opc->match >> (10 + 8 * (length - 2));
3446 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3447 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3449 as_bad (_("internal error: bad microMIPS opcode "
3450 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3454 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3455 insn_bits = 1 << 4 * length;
3456 insn_bits <<= 4 * length;
3458 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3462 /* This function is called once, at assembler startup time. It should set up
3463 all the tables, etc. that the MD part of the assembler will need. */
3468 const char *retval = NULL;
3472 if (mips_pic != NO_PIC)
3474 if (g_switch_seen && g_switch_value != 0)
3475 as_bad (_("-G may not be used in position-independent code"));
3478 else if (mips_abicalls)
3480 if (g_switch_seen && g_switch_value != 0)
3481 as_bad (_("-G may not be used with abicalls"));
3485 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3486 as_warn (_("could not set architecture and machine"));
3488 op_hash = hash_new ();
3490 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3491 for (i = 0; i < NUMOPCODES;)
3493 const char *name = mips_opcodes[i].name;
3495 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3498 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3499 mips_opcodes[i].name, retval);
3500 /* Probably a memory allocation problem? Give up now. */
3501 as_fatal (_("broken assembler, no assembly attempted"));
3505 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3506 decode_mips_operand, &mips_operands[i]))
3508 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3510 create_insn (&nop_insn, mips_opcodes + i);
3511 if (mips_fix_loongson2f_nop)
3512 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3513 nop_insn.fixed_p = 1;
3517 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3520 mips16_op_hash = hash_new ();
3521 mips16_operands = XCNEWVEC (struct mips_operand_array,
3522 bfd_mips16_num_opcodes);
3525 while (i < bfd_mips16_num_opcodes)
3527 const char *name = mips16_opcodes[i].name;
3529 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3531 as_fatal (_("internal: can't hash `%s': %s"),
3532 mips16_opcodes[i].name, retval);
3535 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3537 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3539 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3540 mips16_nop_insn.fixed_p = 1;
3544 while (i < bfd_mips16_num_opcodes
3545 && strcmp (mips16_opcodes[i].name, name) == 0);
3548 micromips_op_hash = hash_new ();
3549 micromips_operands = XCNEWVEC (struct mips_operand_array,
3550 bfd_micromips_num_opcodes);
3553 while (i < bfd_micromips_num_opcodes)
3555 const char *name = micromips_opcodes[i].name;
3557 retval = hash_insert (micromips_op_hash, name,
3558 (void *) µmips_opcodes[i]);
3560 as_fatal (_("internal: can't hash `%s': %s"),
3561 micromips_opcodes[i].name, retval);
3564 struct mips_cl_insn *micromips_nop_insn;
3566 if (!validate_micromips_insn (µmips_opcodes[i],
3567 µmips_operands[i]))
3570 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3572 if (micromips_insn_length (micromips_opcodes + i) == 2)
3573 micromips_nop_insn = µmips_nop16_insn;
3574 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3575 micromips_nop_insn = µmips_nop32_insn;
3579 if (micromips_nop_insn->insn_mo == NULL
3580 && strcmp (name, "nop") == 0)
3582 create_insn (micromips_nop_insn, micromips_opcodes + i);
3583 micromips_nop_insn->fixed_p = 1;
3587 while (++i < bfd_micromips_num_opcodes
3588 && strcmp (micromips_opcodes[i].name, name) == 0);
3592 as_fatal (_("broken assembler, no assembly attempted"));
3594 /* We add all the general register names to the symbol table. This
3595 helps us detect invalid uses of them. */
3596 for (i = 0; reg_names[i].name; i++)
3597 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3598 reg_names[i].num, /* & RNUM_MASK, */
3599 &zero_address_frag));
3601 for (i = 0; reg_names_n32n64[i].name; i++)
3602 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3603 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3604 &zero_address_frag));
3606 for (i = 0; reg_names_o32[i].name; i++)
3607 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3608 reg_names_o32[i].num, /* & RNUM_MASK, */
3609 &zero_address_frag));
3611 for (i = 0; i < 32; i++)
3615 /* R5900 VU0 floating-point register. */
3616 sprintf (regname, "$vf%d", i);
3617 symbol_table_insert (symbol_new (regname, reg_section,
3618 RTYPE_VF | i, &zero_address_frag));
3620 /* R5900 VU0 integer register. */
3621 sprintf (regname, "$vi%d", i);
3622 symbol_table_insert (symbol_new (regname, reg_section,
3623 RTYPE_VI | i, &zero_address_frag));
3626 sprintf (regname, "$w%d", i);
3627 symbol_table_insert (symbol_new (regname, reg_section,
3628 RTYPE_MSA | i, &zero_address_frag));
3631 obstack_init (&mips_operand_tokens);
3633 mips_no_prev_insn ();
3636 mips_cprmask[0] = 0;
3637 mips_cprmask[1] = 0;
3638 mips_cprmask[2] = 0;
3639 mips_cprmask[3] = 0;
3641 /* set the default alignment for the text section (2**2) */
3642 record_alignment (text_section, 2);
3644 bfd_set_gp_size (stdoutput, g_switch_value);
3646 /* On a native system other than VxWorks, sections must be aligned
3647 to 16 byte boundaries. When configured for an embedded ELF
3648 target, we don't bother. */
3649 if (strncmp (TARGET_OS, "elf", 3) != 0
3650 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3652 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3653 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3654 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3657 /* Create a .reginfo section for register masks and a .mdebug
3658 section for debugging information. */
3666 subseg = now_subseg;
3668 /* The ABI says this section should be loaded so that the
3669 running program can access it. However, we don't load it
3670 if we are configured for an embedded target */
3671 flags = SEC_READONLY | SEC_DATA;
3672 if (strncmp (TARGET_OS, "elf", 3) != 0)
3673 flags |= SEC_ALLOC | SEC_LOAD;
3675 if (mips_abi != N64_ABI)
3677 sec = subseg_new (".reginfo", (subsegT) 0);
3679 bfd_set_section_flags (stdoutput, sec, flags);
3680 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3682 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3686 /* The 64-bit ABI uses a .MIPS.options section rather than
3687 .reginfo section. */
3688 sec = subseg_new (".MIPS.options", (subsegT) 0);
3689 bfd_set_section_flags (stdoutput, sec, flags);
3690 bfd_set_section_alignment (stdoutput, sec, 3);
3692 /* Set up the option header. */
3694 Elf_Internal_Options opthdr;
3697 opthdr.kind = ODK_REGINFO;
3698 opthdr.size = (sizeof (Elf_External_Options)
3699 + sizeof (Elf64_External_RegInfo));
3702 f = frag_more (sizeof (Elf_External_Options));
3703 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3704 (Elf_External_Options *) f);
3706 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3710 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3711 bfd_set_section_flags (stdoutput, sec,
3712 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3713 bfd_set_section_alignment (stdoutput, sec, 3);
3714 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3716 if (ECOFF_DEBUGGING)
3718 sec = subseg_new (".mdebug", (subsegT) 0);
3719 (void) bfd_set_section_flags (stdoutput, sec,
3720 SEC_HAS_CONTENTS | SEC_READONLY);
3721 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3723 else if (mips_flag_pdr)
3725 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3726 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3727 SEC_READONLY | SEC_RELOC
3729 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3732 subseg_set (seg, subseg);
3735 if (mips_fix_vr4120)
3736 init_vr4120_conflicts ();
3740 fpabi_incompatible_with (int fpabi, const char *what)
3742 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3743 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3747 fpabi_requires (int fpabi, const char *what)
3749 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3750 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3753 /* Check -mabi and register sizes against the specified FP ABI. */
3755 check_fpabi (int fpabi)
3759 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3760 if (file_mips_opts.soft_float)
3761 fpabi_incompatible_with (fpabi, "softfloat");
3762 else if (file_mips_opts.single_float)
3763 fpabi_incompatible_with (fpabi, "singlefloat");
3764 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3765 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3766 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3767 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3770 case Val_GNU_MIPS_ABI_FP_XX:
3771 if (mips_abi != O32_ABI)
3772 fpabi_requires (fpabi, "-mabi=32");
3773 else if (file_mips_opts.soft_float)
3774 fpabi_incompatible_with (fpabi, "softfloat");
3775 else if (file_mips_opts.single_float)
3776 fpabi_incompatible_with (fpabi, "singlefloat");
3777 else if (file_mips_opts.fp != 0)
3778 fpabi_requires (fpabi, "fp=xx");
3781 case Val_GNU_MIPS_ABI_FP_64A:
3782 case Val_GNU_MIPS_ABI_FP_64:
3783 if (mips_abi != O32_ABI)
3784 fpabi_requires (fpabi, "-mabi=32");
3785 else if (file_mips_opts.soft_float)
3786 fpabi_incompatible_with (fpabi, "softfloat");
3787 else if (file_mips_opts.single_float)
3788 fpabi_incompatible_with (fpabi, "singlefloat");
3789 else if (file_mips_opts.fp != 64)
3790 fpabi_requires (fpabi, "fp=64");
3791 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3792 fpabi_incompatible_with (fpabi, "nooddspreg");
3793 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3794 fpabi_requires (fpabi, "nooddspreg");
3797 case Val_GNU_MIPS_ABI_FP_SINGLE:
3798 if (file_mips_opts.soft_float)
3799 fpabi_incompatible_with (fpabi, "softfloat");
3800 else if (!file_mips_opts.single_float)
3801 fpabi_requires (fpabi, "singlefloat");
3804 case Val_GNU_MIPS_ABI_FP_SOFT:
3805 if (!file_mips_opts.soft_float)
3806 fpabi_requires (fpabi, "softfloat");
3809 case Val_GNU_MIPS_ABI_FP_OLD_64:
3810 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3811 Tag_GNU_MIPS_ABI_FP, fpabi);
3814 case Val_GNU_MIPS_ABI_FP_NAN2008:
3815 /* Silently ignore compatibility value. */
3819 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3820 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3825 /* Perform consistency checks on the current options. */
3828 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3830 /* Check the size of integer registers agrees with the ABI and ISA. */
3831 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3832 as_bad (_("`gp=64' used with a 32-bit processor"));
3834 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3835 as_bad (_("`gp=32' used with a 64-bit ABI"));
3837 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3838 as_bad (_("`gp=64' used with a 32-bit ABI"));
3840 /* Check the size of the float registers agrees with the ABI and ISA. */
3844 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3845 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3846 else if (opts->single_float == 1)
3847 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3850 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3851 as_bad (_("`fp=64' used with a 32-bit fpu"));
3853 && ABI_NEEDS_32BIT_REGS (mips_abi)
3854 && !ISA_HAS_MXHC1 (opts->isa))
3855 as_warn (_("`fp=64' used with a 32-bit ABI"));
3859 && ABI_NEEDS_64BIT_REGS (mips_abi))
3860 as_warn (_("`fp=32' used with a 64-bit ABI"));
3861 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
3862 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3865 as_bad (_("Unknown size of floating point registers"));
3869 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3870 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3872 if (opts->micromips == 1 && opts->mips16 == 1)
3873 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3874 else if (ISA_IS_R6 (opts->isa)
3875 && (opts->micromips == 1
3876 || opts->mips16 == 1))
3877 as_fatal (_("`%s' cannot be used with `%s'"),
3878 opts->micromips ? "micromips" : "mips16",
3879 mips_cpu_info_from_isa (opts->isa)->name);
3881 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3882 as_fatal (_("branch relaxation is not supported in `%s'"),
3883 mips_cpu_info_from_isa (opts->isa)->name);
3886 /* Perform consistency checks on the module level options exactly once.
3887 This is a deferred check that happens:
3888 at the first .set directive
3889 or, at the first pseudo op that generates code (inc .dc.a)
3890 or, at the first instruction
3894 file_mips_check_options (void)
3896 const struct mips_cpu_info *arch_info = 0;
3898 if (file_mips_opts_checked)
3901 /* The following code determines the register size.
3902 Similar code was added to GCC 3.3 (see override_options() in
3903 config/mips/mips.c). The GAS and GCC code should be kept in sync
3904 as much as possible. */
3906 if (file_mips_opts.gp < 0)
3908 /* Infer the integer register size from the ABI and processor.
3909 Restrict ourselves to 32-bit registers if that's all the
3910 processor has, or if the ABI cannot handle 64-bit registers. */
3911 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3912 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3916 if (file_mips_opts.fp < 0)
3918 /* No user specified float register size.
3919 ??? GAS treats single-float processors as though they had 64-bit
3920 float registers (although it complains when double-precision
3921 instructions are used). As things stand, saying they have 32-bit
3922 registers would lead to spurious "register must be even" messages.
3923 So here we assume float registers are never smaller than the
3925 if (file_mips_opts.gp == 64)
3926 /* 64-bit integer registers implies 64-bit float registers. */
3927 file_mips_opts.fp = 64;
3928 else if ((file_mips_opts.ase & FP64_ASES)
3929 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3930 /* Handle ASEs that require 64-bit float registers, if possible. */
3931 file_mips_opts.fp = 64;
3932 else if (ISA_IS_R6 (mips_opts.isa))
3933 /* R6 implies 64-bit float registers. */
3934 file_mips_opts.fp = 64;
3936 /* 32-bit float registers. */
3937 file_mips_opts.fp = 32;
3940 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3942 /* Disable operations on odd-numbered floating-point registers by default
3943 when using the FPXX ABI. */
3944 if (file_mips_opts.oddspreg < 0)
3946 if (file_mips_opts.fp == 0)
3947 file_mips_opts.oddspreg = 0;
3949 file_mips_opts.oddspreg = 1;
3952 /* End of GCC-shared inference code. */
3954 /* This flag is set when we have a 64-bit capable CPU but use only
3955 32-bit wide registers. Note that EABI does not use it. */
3956 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3957 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3958 || mips_abi == O32_ABI))
3961 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3962 as_bad (_("trap exception not supported at ISA 1"));
3964 /* If the selected architecture includes support for ASEs, enable
3965 generation of code for them. */
3966 if (file_mips_opts.mips16 == -1)
3967 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3968 if (file_mips_opts.micromips == -1)
3969 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3972 if (mips_nan2008 == -1)
3973 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3974 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3975 as_fatal (_("`%s' does not support legacy NaN"),
3976 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3978 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3979 being selected implicitly. */
3980 if (file_mips_opts.fp != 64)
3981 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3983 /* If the user didn't explicitly select or deselect a particular ASE,
3984 use the default setting for the CPU. */
3985 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
3987 /* Set up the current options. These may change throughout assembly. */
3988 mips_opts = file_mips_opts;
3990 mips_check_isa_supports_ases ();
3991 mips_check_options (&file_mips_opts, TRUE);
3992 file_mips_opts_checked = TRUE;
3994 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3995 as_warn (_("could not set architecture and machine"));
3999 md_assemble (char *str)
4001 struct mips_cl_insn insn;
4002 bfd_reloc_code_real_type unused_reloc[3]
4003 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4005 file_mips_check_options ();
4007 imm_expr.X_op = O_absent;
4008 offset_expr.X_op = O_absent;
4009 offset_reloc[0] = BFD_RELOC_UNUSED;
4010 offset_reloc[1] = BFD_RELOC_UNUSED;
4011 offset_reloc[2] = BFD_RELOC_UNUSED;
4013 mips_mark_labels ();
4014 mips_assembling_insn = TRUE;
4015 clear_insn_error ();
4017 if (mips_opts.mips16)
4018 mips16_ip (str, &insn);
4021 mips_ip (str, &insn);
4022 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4023 str, insn.insn_opcode));
4027 report_insn_error (str);
4028 else if (insn.insn_mo->pinfo == INSN_MACRO)
4031 if (mips_opts.mips16)
4032 mips16_macro (&insn);
4039 if (offset_expr.X_op != O_absent)
4040 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4042 append_insn (&insn, NULL, unused_reloc, FALSE);
4045 mips_assembling_insn = FALSE;
4048 /* Convenience functions for abstracting away the differences between
4049 MIPS16 and non-MIPS16 relocations. */
4051 static inline bfd_boolean
4052 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4056 case BFD_RELOC_MIPS16_JMP:
4057 case BFD_RELOC_MIPS16_GPREL:
4058 case BFD_RELOC_MIPS16_GOT16:
4059 case BFD_RELOC_MIPS16_CALL16:
4060 case BFD_RELOC_MIPS16_HI16_S:
4061 case BFD_RELOC_MIPS16_HI16:
4062 case BFD_RELOC_MIPS16_LO16:
4063 case BFD_RELOC_MIPS16_16_PCREL_S1:
4071 static inline bfd_boolean
4072 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4076 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4077 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4078 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4079 case BFD_RELOC_MICROMIPS_GPREL16:
4080 case BFD_RELOC_MICROMIPS_JMP:
4081 case BFD_RELOC_MICROMIPS_HI16:
4082 case BFD_RELOC_MICROMIPS_HI16_S:
4083 case BFD_RELOC_MICROMIPS_LO16:
4084 case BFD_RELOC_MICROMIPS_LITERAL:
4085 case BFD_RELOC_MICROMIPS_GOT16:
4086 case BFD_RELOC_MICROMIPS_CALL16:
4087 case BFD_RELOC_MICROMIPS_GOT_HI16:
4088 case BFD_RELOC_MICROMIPS_GOT_LO16:
4089 case BFD_RELOC_MICROMIPS_CALL_HI16:
4090 case BFD_RELOC_MICROMIPS_CALL_LO16:
4091 case BFD_RELOC_MICROMIPS_SUB:
4092 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4093 case BFD_RELOC_MICROMIPS_GOT_OFST:
4094 case BFD_RELOC_MICROMIPS_GOT_DISP:
4095 case BFD_RELOC_MICROMIPS_HIGHEST:
4096 case BFD_RELOC_MICROMIPS_HIGHER:
4097 case BFD_RELOC_MICROMIPS_SCN_DISP:
4098 case BFD_RELOC_MICROMIPS_JALR:
4106 static inline bfd_boolean
4107 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4109 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4112 static inline bfd_boolean
4113 b_reloc_p (bfd_reloc_code_real_type reloc)
4115 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4116 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4117 || reloc == BFD_RELOC_16_PCREL_S2
4118 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
4119 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4120 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4121 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4124 static inline bfd_boolean
4125 got16_reloc_p (bfd_reloc_code_real_type reloc)
4127 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4128 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4131 static inline bfd_boolean
4132 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4134 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4135 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4138 static inline bfd_boolean
4139 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4141 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4142 || reloc == BFD_RELOC_MICROMIPS_LO16);
4145 static inline bfd_boolean
4146 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4148 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4151 static inline bfd_boolean
4152 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4154 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4155 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4158 /* Return true if RELOC is a PC-relative relocation that does not have
4159 full address range. */
4161 static inline bfd_boolean
4162 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4166 case BFD_RELOC_16_PCREL_S2:
4167 case BFD_RELOC_MIPS16_16_PCREL_S1:
4168 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4169 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4170 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4171 case BFD_RELOC_MIPS_21_PCREL_S2:
4172 case BFD_RELOC_MIPS_26_PCREL_S2:
4173 case BFD_RELOC_MIPS_18_PCREL_S3:
4174 case BFD_RELOC_MIPS_19_PCREL_S2:
4177 case BFD_RELOC_32_PCREL:
4178 case BFD_RELOC_HI16_S_PCREL:
4179 case BFD_RELOC_LO16_PCREL:
4180 return HAVE_64BIT_ADDRESSES;
4187 /* Return true if the given relocation might need a matching %lo().
4188 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4189 need a matching %lo() when applied to local symbols. */
4191 static inline bfd_boolean
4192 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4194 return (HAVE_IN_PLACE_ADDENDS
4195 && (hi16_reloc_p (reloc)
4196 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4197 all GOT16 relocations evaluate to "G". */
4198 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4201 /* Return the type of %lo() reloc needed by RELOC, given that
4202 reloc_needs_lo_p. */
4204 static inline bfd_reloc_code_real_type
4205 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4207 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4208 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4212 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4215 static inline bfd_boolean
4216 fixup_has_matching_lo_p (fixS *fixp)
4218 return (fixp->fx_next != NULL
4219 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4220 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4221 && fixp->fx_offset == fixp->fx_next->fx_offset);
4224 /* Move all labels in LABELS to the current insertion point. TEXT_P
4225 says whether the labels refer to text or data. */
4228 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4230 struct insn_label_list *l;
4233 for (l = labels; l != NULL; l = l->next)
4235 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4236 symbol_set_frag (l->label, frag_now);
4237 val = (valueT) frag_now_fix ();
4238 /* MIPS16/microMIPS text labels are stored as odd. */
4239 if (text_p && HAVE_CODE_COMPRESSION)
4241 S_SET_VALUE (l->label, val);
4245 /* Move all labels in insn_labels to the current insertion point
4246 and treat them as text labels. */
4249 mips_move_text_labels (void)
4251 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4255 s_is_linkonce (symbolS *sym, segT from_seg)
4257 bfd_boolean linkonce = FALSE;
4258 segT symseg = S_GET_SEGMENT (sym);
4260 if (symseg != from_seg && !S_IS_LOCAL (sym))
4262 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4264 /* The GNU toolchain uses an extension for ELF: a section
4265 beginning with the magic string .gnu.linkonce is a
4266 linkonce section. */
4267 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4268 sizeof ".gnu.linkonce" - 1) == 0)
4274 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4275 linker to handle them specially, such as generating jalx instructions
4276 when needed. We also make them odd for the duration of the assembly,
4277 in order to generate the right sort of code. We will make them even
4278 in the adjust_symtab routine, while leaving them marked. This is
4279 convenient for the debugger and the disassembler. The linker knows
4280 to make them odd again. */
4283 mips_compressed_mark_label (symbolS *label)
4285 gas_assert (HAVE_CODE_COMPRESSION);
4287 if (mips_opts.mips16)
4288 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4290 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4291 if ((S_GET_VALUE (label) & 1) == 0
4292 /* Don't adjust the address if the label is global or weak, or
4293 in a link-once section, since we'll be emitting symbol reloc
4294 references to it which will be patched up by the linker, and
4295 the final value of the symbol may or may not be MIPS16/microMIPS. */
4296 && !S_IS_WEAK (label)
4297 && !S_IS_EXTERNAL (label)
4298 && !s_is_linkonce (label, now_seg))
4299 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4302 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4305 mips_compressed_mark_labels (void)
4307 struct insn_label_list *l;
4309 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4310 mips_compressed_mark_label (l->label);
4313 /* End the current frag. Make it a variant frag and record the
4317 relax_close_frag (void)
4319 mips_macro_warning.first_frag = frag_now;
4320 frag_var (rs_machine_dependent, 0, 0,
4321 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4322 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4324 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4325 mips_relax.first_fixup = 0;
4328 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4329 See the comment above RELAX_ENCODE for more details. */
4332 relax_start (symbolS *symbol)
4334 gas_assert (mips_relax.sequence == 0);
4335 mips_relax.sequence = 1;
4336 mips_relax.symbol = symbol;
4339 /* Start generating the second version of a relaxable sequence.
4340 See the comment above RELAX_ENCODE for more details. */
4345 gas_assert (mips_relax.sequence == 1);
4346 mips_relax.sequence = 2;
4349 /* End the current relaxable sequence. */
4354 gas_assert (mips_relax.sequence == 2);
4355 relax_close_frag ();
4356 mips_relax.sequence = 0;
4359 /* Return true if IP is a delayed branch or jump. */
4361 static inline bfd_boolean
4362 delayed_branch_p (const struct mips_cl_insn *ip)
4364 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4365 | INSN_COND_BRANCH_DELAY
4366 | INSN_COND_BRANCH_LIKELY)) != 0;
4369 /* Return true if IP is a compact branch or jump. */
4371 static inline bfd_boolean
4372 compact_branch_p (const struct mips_cl_insn *ip)
4374 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4375 | INSN2_COND_BRANCH)) != 0;
4378 /* Return true if IP is an unconditional branch or jump. */
4380 static inline bfd_boolean
4381 uncond_branch_p (const struct mips_cl_insn *ip)
4383 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4384 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4387 /* Return true if IP is a branch-likely instruction. */
4389 static inline bfd_boolean
4390 branch_likely_p (const struct mips_cl_insn *ip)
4392 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4395 /* Return the type of nop that should be used to fill the delay slot
4396 of delayed branch IP. */
4398 static struct mips_cl_insn *
4399 get_delay_slot_nop (const struct mips_cl_insn *ip)
4401 if (mips_opts.micromips
4402 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4403 return µmips_nop32_insn;
4407 /* Return a mask that has bit N set if OPCODE reads the register(s)
4411 insn_read_mask (const struct mips_opcode *opcode)
4413 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4416 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4420 insn_write_mask (const struct mips_opcode *opcode)
4422 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4425 /* Return a mask of the registers specified by operand OPERAND of INSN.
4426 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4430 operand_reg_mask (const struct mips_cl_insn *insn,
4431 const struct mips_operand *operand,
4432 unsigned int type_mask)
4434 unsigned int uval, vsel;
4436 switch (operand->type)
4443 case OP_ADDIUSP_INT:
4444 case OP_ENTRY_EXIT_LIST:
4445 case OP_REPEAT_DEST_REG:
4446 case OP_REPEAT_PREV_REG:
4449 case OP_VU0_MATCH_SUFFIX:
4454 case OP_OPTIONAL_REG:
4456 const struct mips_reg_operand *reg_op;
4458 reg_op = (const struct mips_reg_operand *) operand;
4459 if (!(type_mask & (1 << reg_op->reg_type)))
4461 uval = insn_extract_operand (insn, operand);
4462 return 1 << mips_decode_reg_operand (reg_op, uval);
4467 const struct mips_reg_pair_operand *pair_op;
4469 pair_op = (const struct mips_reg_pair_operand *) operand;
4470 if (!(type_mask & (1 << pair_op->reg_type)))
4472 uval = insn_extract_operand (insn, operand);
4473 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4476 case OP_CLO_CLZ_DEST:
4477 if (!(type_mask & (1 << OP_REG_GP)))
4479 uval = insn_extract_operand (insn, operand);
4480 return (1 << (uval & 31)) | (1 << (uval >> 5));
4483 if (!(type_mask & (1 << OP_REG_GP)))
4485 uval = insn_extract_operand (insn, operand);
4486 gas_assert ((uval & 31) == (uval >> 5));
4487 return 1 << (uval & 31);
4490 case OP_NON_ZERO_REG:
4491 if (!(type_mask & (1 << OP_REG_GP)))
4493 uval = insn_extract_operand (insn, operand);
4494 return 1 << (uval & 31);
4496 case OP_LWM_SWM_LIST:
4499 case OP_SAVE_RESTORE_LIST:
4502 case OP_MDMX_IMM_REG:
4503 if (!(type_mask & (1 << OP_REG_VEC)))
4505 uval = insn_extract_operand (insn, operand);
4507 if ((vsel & 0x18) == 0x18)
4509 return 1 << (uval & 31);
4512 if (!(type_mask & (1 << OP_REG_GP)))
4514 return 1 << insn_extract_operand (insn, operand);
4519 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4520 where bit N of OPNO_MASK is set if operand N should be included.
4521 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4525 insn_reg_mask (const struct mips_cl_insn *insn,
4526 unsigned int type_mask, unsigned int opno_mask)
4528 unsigned int opno, reg_mask;
4532 while (opno_mask != 0)
4535 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4542 /* Return the mask of core registers that IP reads. */
4545 gpr_read_mask (const struct mips_cl_insn *ip)
4547 unsigned long pinfo, pinfo2;
4550 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4551 pinfo = ip->insn_mo->pinfo;
4552 pinfo2 = ip->insn_mo->pinfo2;
4553 if (pinfo & INSN_UDI)
4555 /* UDI instructions have traditionally been assumed to read RS
4557 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4558 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4560 if (pinfo & INSN_READ_GPR_24)
4562 if (pinfo2 & INSN2_READ_GPR_16)
4564 if (pinfo2 & INSN2_READ_SP)
4566 if (pinfo2 & INSN2_READ_GPR_31)
4568 /* Don't include register 0. */
4572 /* Return the mask of core registers that IP writes. */
4575 gpr_write_mask (const struct mips_cl_insn *ip)
4577 unsigned long pinfo, pinfo2;
4580 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4581 pinfo = ip->insn_mo->pinfo;
4582 pinfo2 = ip->insn_mo->pinfo2;
4583 if (pinfo & INSN_WRITE_GPR_24)
4585 if (pinfo & INSN_WRITE_GPR_31)
4587 if (pinfo & INSN_UDI)
4588 /* UDI instructions have traditionally been assumed to write to RD. */
4589 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4590 if (pinfo2 & INSN2_WRITE_SP)
4592 /* Don't include register 0. */
4596 /* Return the mask of floating-point registers that IP reads. */
4599 fpr_read_mask (const struct mips_cl_insn *ip)
4601 unsigned long pinfo;
4604 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4605 | (1 << OP_REG_MSA)),
4606 insn_read_mask (ip->insn_mo));
4607 pinfo = ip->insn_mo->pinfo;
4608 /* Conservatively treat all operands to an FP_D instruction are doubles.
4609 (This is overly pessimistic for things like cvt.d.s.) */
4610 if (FPR_SIZE != 64 && (pinfo & FP_D))
4615 /* Return the mask of floating-point registers that IP writes. */
4618 fpr_write_mask (const struct mips_cl_insn *ip)
4620 unsigned long pinfo;
4623 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4624 | (1 << OP_REG_MSA)),
4625 insn_write_mask (ip->insn_mo));
4626 pinfo = ip->insn_mo->pinfo;
4627 /* Conservatively treat all operands to an FP_D instruction are doubles.
4628 (This is overly pessimistic for things like cvt.s.d.) */
4629 if (FPR_SIZE != 64 && (pinfo & FP_D))
4634 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4635 Check whether that is allowed. */
4638 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4640 const char *s = insn->name;
4641 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4643 && mips_opts.oddspreg;
4645 if (insn->pinfo == INSN_MACRO)
4646 /* Let a macro pass, we'll catch it later when it is expanded. */
4649 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4650 otherwise it depends on oddspreg. */
4651 if ((insn->pinfo & FP_S)
4652 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4653 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4654 return FPR_SIZE == 32 || oddspreg;
4656 /* Allow odd registers for single-precision ops and double-precision if the
4657 floating-point registers are 64-bit wide. */
4658 switch (insn->pinfo & (FP_S | FP_D))
4664 return FPR_SIZE == 64;
4669 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4670 s = strchr (insn->name, '.');
4671 if (s != NULL && opnum == 2)
4672 s = strchr (s + 1, '.');
4673 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4676 return FPR_SIZE == 64;
4679 /* Information about an instruction argument that we're trying to match. */
4680 struct mips_arg_info
4682 /* The instruction so far. */
4683 struct mips_cl_insn *insn;
4685 /* The first unconsumed operand token. */
4686 struct mips_operand_token *token;
4688 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4691 /* The 1-based argument number, for error reporting. This does not
4692 count elided optional registers, etc.. */
4695 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4696 unsigned int last_regno;
4698 /* If the first operand was an OP_REG, this is the register that it
4699 specified, otherwise it is ILLEGAL_REG. */
4700 unsigned int dest_regno;
4702 /* The value of the last OP_INT operand. Only used for OP_MSB,
4703 where it gives the lsb position. */
4704 unsigned int last_op_int;
4706 /* If true, match routines should assume that no later instruction
4707 alternative matches and should therefore be as accomodating as
4708 possible. Match routines should not report errors if something
4709 is only invalid for !LAX_MATCH. */
4710 bfd_boolean lax_match;
4712 /* True if a reference to the current AT register was seen. */
4713 bfd_boolean seen_at;
4716 /* Record that the argument is out of range. */
4719 match_out_of_range (struct mips_arg_info *arg)
4721 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4724 /* Record that the argument isn't constant but needs to be. */
4727 match_not_constant (struct mips_arg_info *arg)
4729 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4733 /* Try to match an OT_CHAR token for character CH. Consume the token
4734 and return true on success, otherwise return false. */
4737 match_char (struct mips_arg_info *arg, char ch)
4739 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4749 /* Try to get an expression from the next tokens in ARG. Consume the
4750 tokens and return true on success, storing the expression value in
4751 VALUE and relocation types in R. */
4754 match_expression (struct mips_arg_info *arg, expressionS *value,
4755 bfd_reloc_code_real_type *r)
4757 /* If the next token is a '(' that was parsed as being part of a base
4758 expression, assume we have an elided offset. The later match will fail
4759 if this turns out to be wrong. */
4760 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4762 value->X_op = O_constant;
4763 value->X_add_number = 0;
4764 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4768 /* Reject register-based expressions such as "0+$2" and "(($2))".
4769 For plain registers the default error seems more appropriate. */
4770 if (arg->token->type == OT_INTEGER
4771 && arg->token->u.integer.value.X_op == O_register)
4773 set_insn_error (arg->argnum, _("register value used as expression"));
4777 if (arg->token->type == OT_INTEGER)
4779 *value = arg->token->u.integer.value;
4780 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4786 (arg->argnum, _("operand %d must be an immediate expression"),
4791 /* Try to get a constant expression from the next tokens in ARG. Consume
4792 the tokens and return return true on success, storing the constant value
4793 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4797 match_const_int (struct mips_arg_info *arg, offsetT *value)
4800 bfd_reloc_code_real_type r[3];
4802 if (!match_expression (arg, &ex, r))
4805 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4806 *value = ex.X_add_number;
4809 match_not_constant (arg);
4815 /* Return the RTYPE_* flags for a register operand of type TYPE that
4816 appears in instruction OPCODE. */
4819 convert_reg_type (const struct mips_opcode *opcode,
4820 enum mips_reg_operand_type type)
4825 return RTYPE_NUM | RTYPE_GP;
4828 /* Allow vector register names for MDMX if the instruction is a 64-bit
4829 FPR load, store or move (including moves to and from GPRs). */
4830 if ((mips_opts.ase & ASE_MDMX)
4831 && (opcode->pinfo & FP_D)
4832 && (opcode->pinfo & (INSN_COPROC_MOVE
4833 | INSN_COPROC_MEMORY_DELAY
4836 | INSN_STORE_MEMORY)))
4837 return RTYPE_FPU | RTYPE_VEC;
4841 if (opcode->pinfo & (FP_D | FP_S))
4842 return RTYPE_CCC | RTYPE_FCC;
4846 if (opcode->membership & INSN_5400)
4848 return RTYPE_FPU | RTYPE_VEC;
4854 if (opcode->name[strlen (opcode->name) - 1] == '0')
4855 return RTYPE_NUM | RTYPE_CP0;
4862 return RTYPE_NUM | RTYPE_VI;
4865 return RTYPE_NUM | RTYPE_VF;
4867 case OP_REG_R5900_I:
4868 return RTYPE_R5900_I;
4870 case OP_REG_R5900_Q:
4871 return RTYPE_R5900_Q;
4873 case OP_REG_R5900_R:
4874 return RTYPE_R5900_R;
4876 case OP_REG_R5900_ACC:
4877 return RTYPE_R5900_ACC;
4882 case OP_REG_MSA_CTRL:
4888 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4891 check_regno (struct mips_arg_info *arg,
4892 enum mips_reg_operand_type type, unsigned int regno)
4894 if (AT && type == OP_REG_GP && regno == AT)
4895 arg->seen_at = TRUE;
4897 if (type == OP_REG_FP
4899 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4901 /* This was a warning prior to introducing O32 FPXX and FP64 support
4902 so maintain a warning for FP32 but raise an error for the new
4905 as_warn (_("float register should be even, was %d"), regno);
4907 as_bad (_("float register should be even, was %d"), regno);
4910 if (type == OP_REG_CCC)
4915 name = arg->insn->insn_mo->name;
4916 length = strlen (name);
4917 if ((regno & 1) != 0
4918 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4919 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4920 as_warn (_("condition code register should be even for %s, was %d"),
4923 if ((regno & 3) != 0
4924 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4925 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4930 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4931 a register of type TYPE. Return true on success, storing the register
4932 number in *REGNO and warning about any dubious uses. */
4935 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4936 unsigned int symval, unsigned int *regno)
4938 if (type == OP_REG_VEC)
4939 symval = mips_prefer_vec_regno (symval);
4940 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4943 *regno = symval & RNUM_MASK;
4944 check_regno (arg, type, *regno);
4948 /* Try to interpret the next token in ARG as a register of type TYPE.
4949 Consume the token and return true on success, storing the register
4950 number in *REGNO. Return false on failure. */
4953 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4954 unsigned int *regno)
4956 if (arg->token->type == OT_REG
4957 && match_regno (arg, type, arg->token->u.regno, regno))
4965 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4966 Consume the token and return true on success, storing the register numbers
4967 in *REGNO1 and *REGNO2. Return false on failure. */
4970 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4971 unsigned int *regno1, unsigned int *regno2)
4973 if (match_reg (arg, type, regno1))
4978 if (arg->token->type == OT_REG_RANGE
4979 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4980 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4981 && *regno1 <= *regno2)
4989 /* OP_INT matcher. */
4992 match_int_operand (struct mips_arg_info *arg,
4993 const struct mips_operand *operand_base)
4995 const struct mips_int_operand *operand;
4997 int min_val, max_val, factor;
5000 operand = (const struct mips_int_operand *) operand_base;
5001 factor = 1 << operand->shift;
5002 min_val = mips_int_operand_min (operand);
5003 max_val = mips_int_operand_max (operand);
5005 if (operand_base->lsb == 0
5006 && operand_base->size == 16
5007 && operand->shift == 0
5008 && operand->bias == 0
5009 && (operand->max_val == 32767 || operand->max_val == 65535))
5011 /* The operand can be relocated. */
5012 if (!match_expression (arg, &offset_expr, offset_reloc))
5015 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5016 /* Relocation operators were used. Accept the arguent and
5017 leave the relocation value in offset_expr and offset_relocs
5018 for the caller to process. */
5021 if (offset_expr.X_op != O_constant)
5023 /* Accept non-constant operands if no later alternative matches,
5024 leaving it for the caller to process. */
5025 if (!arg->lax_match)
5027 offset_reloc[0] = BFD_RELOC_LO16;
5031 /* Clear the global state; we're going to install the operand
5033 sval = offset_expr.X_add_number;
5034 offset_expr.X_op = O_absent;
5036 /* For compatibility with older assemblers, we accept
5037 0x8000-0xffff as signed 16-bit numbers when only
5038 signed numbers are allowed. */
5041 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5042 if (!arg->lax_match && sval <= max_val)
5048 if (!match_const_int (arg, &sval))
5052 arg->last_op_int = sval;
5054 if (sval < min_val || sval > max_val || sval % factor)
5056 match_out_of_range (arg);
5060 uval = (unsigned int) sval >> operand->shift;
5061 uval -= operand->bias;
5063 /* Handle -mfix-cn63xxp1. */
5065 && mips_fix_cn63xxp1
5066 && !mips_opts.micromips
5067 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5082 /* The rest must be changed to 28. */
5087 insn_insert_operand (arg->insn, operand_base, uval);
5091 /* OP_MAPPED_INT matcher. */
5094 match_mapped_int_operand (struct mips_arg_info *arg,
5095 const struct mips_operand *operand_base)
5097 const struct mips_mapped_int_operand *operand;
5098 unsigned int uval, num_vals;
5101 operand = (const struct mips_mapped_int_operand *) operand_base;
5102 if (!match_const_int (arg, &sval))
5105 num_vals = 1 << operand_base->size;
5106 for (uval = 0; uval < num_vals; uval++)
5107 if (operand->int_map[uval] == sval)
5109 if (uval == num_vals)
5111 match_out_of_range (arg);
5115 insn_insert_operand (arg->insn, operand_base, uval);
5119 /* OP_MSB matcher. */
5122 match_msb_operand (struct mips_arg_info *arg,
5123 const struct mips_operand *operand_base)
5125 const struct mips_msb_operand *operand;
5126 int min_val, max_val, max_high;
5127 offsetT size, sval, high;
5129 operand = (const struct mips_msb_operand *) operand_base;
5130 min_val = operand->bias;
5131 max_val = min_val + (1 << operand_base->size) - 1;
5132 max_high = operand->opsize;
5134 if (!match_const_int (arg, &size))
5137 high = size + arg->last_op_int;
5138 sval = operand->add_lsb ? high : size;
5140 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5142 match_out_of_range (arg);
5145 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5149 /* OP_REG matcher. */
5152 match_reg_operand (struct mips_arg_info *arg,
5153 const struct mips_operand *operand_base)
5155 const struct mips_reg_operand *operand;
5156 unsigned int regno, uval, num_vals;
5158 operand = (const struct mips_reg_operand *) operand_base;
5159 if (!match_reg (arg, operand->reg_type, ®no))
5162 if (operand->reg_map)
5164 num_vals = 1 << operand->root.size;
5165 for (uval = 0; uval < num_vals; uval++)
5166 if (operand->reg_map[uval] == regno)
5168 if (num_vals == uval)
5174 arg->last_regno = regno;
5175 if (arg->opnum == 1)
5176 arg->dest_regno = regno;
5177 insn_insert_operand (arg->insn, operand_base, uval);
5181 /* OP_REG_PAIR matcher. */
5184 match_reg_pair_operand (struct mips_arg_info *arg,
5185 const struct mips_operand *operand_base)
5187 const struct mips_reg_pair_operand *operand;
5188 unsigned int regno1, regno2, uval, num_vals;
5190 operand = (const struct mips_reg_pair_operand *) operand_base;
5191 if (!match_reg (arg, operand->reg_type, ®no1)
5192 || !match_char (arg, ',')
5193 || !match_reg (arg, operand->reg_type, ®no2))
5196 num_vals = 1 << operand_base->size;
5197 for (uval = 0; uval < num_vals; uval++)
5198 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5200 if (uval == num_vals)
5203 insn_insert_operand (arg->insn, operand_base, uval);
5207 /* OP_PCREL matcher. The caller chooses the relocation type. */
5210 match_pcrel_operand (struct mips_arg_info *arg)
5212 bfd_reloc_code_real_type r[3];
5214 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5217 /* OP_PERF_REG matcher. */
5220 match_perf_reg_operand (struct mips_arg_info *arg,
5221 const struct mips_operand *operand)
5225 if (!match_const_int (arg, &sval))
5230 || (mips_opts.arch == CPU_R5900
5231 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5232 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5234 set_insn_error (arg->argnum, _("invalid performance register"));
5238 insn_insert_operand (arg->insn, operand, sval);
5242 /* OP_ADDIUSP matcher. */
5245 match_addiusp_operand (struct mips_arg_info *arg,
5246 const struct mips_operand *operand)
5251 if (!match_const_int (arg, &sval))
5256 match_out_of_range (arg);
5261 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5263 match_out_of_range (arg);
5267 uval = (unsigned int) sval;
5268 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5269 insn_insert_operand (arg->insn, operand, uval);
5273 /* OP_CLO_CLZ_DEST matcher. */
5276 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5277 const struct mips_operand *operand)
5281 if (!match_reg (arg, OP_REG_GP, ®no))
5284 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5288 /* OP_CHECK_PREV matcher. */
5291 match_check_prev_operand (struct mips_arg_info *arg,
5292 const struct mips_operand *operand_base)
5294 const struct mips_check_prev_operand *operand;
5297 operand = (const struct mips_check_prev_operand *) operand_base;
5299 if (!match_reg (arg, OP_REG_GP, ®no))
5302 if (!operand->zero_ok && regno == 0)
5305 if ((operand->less_than_ok && regno < arg->last_regno)
5306 || (operand->greater_than_ok && regno > arg->last_regno)
5307 || (operand->equal_ok && regno == arg->last_regno))
5309 arg->last_regno = regno;
5310 insn_insert_operand (arg->insn, operand_base, regno);
5317 /* OP_SAME_RS_RT matcher. */
5320 match_same_rs_rt_operand (struct mips_arg_info *arg,
5321 const struct mips_operand *operand)
5325 if (!match_reg (arg, OP_REG_GP, ®no))
5330 set_insn_error (arg->argnum, _("the source register must not be $0"));
5334 arg->last_regno = regno;
5336 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5340 /* OP_LWM_SWM_LIST matcher. */
5343 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5344 const struct mips_operand *operand)
5346 unsigned int reglist, sregs, ra, regno1, regno2;
5347 struct mips_arg_info reset;
5350 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5354 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5359 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5362 while (match_char (arg, ',')
5363 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5366 if (operand->size == 2)
5368 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5374 and any permutations of these. */
5375 if ((reglist & 0xfff1ffff) != 0x80010000)
5378 sregs = (reglist >> 17) & 7;
5383 /* The list must include at least one of ra and s0-sN,
5384 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5385 which are $23 and $30 respectively.) E.g.:
5393 and any permutations of these. */
5394 if ((reglist & 0x3f00ffff) != 0)
5397 ra = (reglist >> 27) & 0x10;
5398 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5401 if ((sregs & -sregs) != sregs)
5404 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5408 /* OP_ENTRY_EXIT_LIST matcher. */
5411 match_entry_exit_operand (struct mips_arg_info *arg,
5412 const struct mips_operand *operand)
5415 bfd_boolean is_exit;
5417 /* The format is the same for both ENTRY and EXIT, but the constraints
5419 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5420 mask = (is_exit ? 7 << 3 : 0);
5423 unsigned int regno1, regno2;
5424 bfd_boolean is_freg;
5426 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5428 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5433 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5436 mask |= (5 + regno2) << 3;
5438 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5439 mask |= (regno2 - 3) << 3;
5440 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5441 mask |= (regno2 - 15) << 1;
5442 else if (regno1 == RA && regno2 == RA)
5447 while (match_char (arg, ','));
5449 insn_insert_operand (arg->insn, operand, mask);
5453 /* OP_SAVE_RESTORE_LIST matcher. */
5456 match_save_restore_list_operand (struct mips_arg_info *arg)
5458 unsigned int opcode, args, statics, sregs;
5459 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5462 opcode = arg->insn->insn_opcode;
5464 num_frame_sizes = 0;
5470 unsigned int regno1, regno2;
5472 if (arg->token->type == OT_INTEGER)
5474 /* Handle the frame size. */
5475 if (!match_const_int (arg, &frame_size))
5477 num_frame_sizes += 1;
5481 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5484 while (regno1 <= regno2)
5486 if (regno1 >= 4 && regno1 <= 7)
5488 if (num_frame_sizes == 0)
5490 args |= 1 << (regno1 - 4);
5492 /* statics $a0-$a3 */
5493 statics |= 1 << (regno1 - 4);
5495 else if (regno1 >= 16 && regno1 <= 23)
5497 sregs |= 1 << (regno1 - 16);
5498 else if (regno1 == 30)
5501 else if (regno1 == 31)
5502 /* Add $ra to insn. */
5512 while (match_char (arg, ','));
5514 /* Encode args/statics combination. */
5517 else if (args == 0xf)
5518 /* All $a0-$a3 are args. */
5519 opcode |= MIPS16_ALL_ARGS << 16;
5520 else if (statics == 0xf)
5521 /* All $a0-$a3 are statics. */
5522 opcode |= MIPS16_ALL_STATICS << 16;
5525 /* Count arg registers. */
5535 /* Count static registers. */
5537 while (statics & 0x8)
5539 statics = (statics << 1) & 0xf;
5545 /* Encode args/statics. */
5546 opcode |= ((num_args << 2) | num_statics) << 16;
5549 /* Encode $s0/$s1. */
5550 if (sregs & (1 << 0)) /* $s0 */
5552 if (sregs & (1 << 1)) /* $s1 */
5556 /* Encode $s2-$s8. */
5565 opcode |= num_sregs << 24;
5567 /* Encode frame size. */
5568 if (num_frame_sizes == 0)
5570 set_insn_error (arg->argnum, _("missing frame size"));
5573 if (num_frame_sizes > 1)
5575 set_insn_error (arg->argnum, _("frame size specified twice"));
5578 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5580 set_insn_error (arg->argnum, _("invalid frame size"));
5583 if (frame_size != 128 || (opcode >> 16) != 0)
5586 opcode |= (((frame_size & 0xf0) << 16)
5587 | (frame_size & 0x0f));
5590 /* Finally build the instruction. */
5591 if ((opcode >> 16) != 0 || frame_size == 0)
5592 opcode |= MIPS16_EXTEND;
5593 arg->insn->insn_opcode = opcode;
5597 /* OP_MDMX_IMM_REG matcher. */
5600 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5601 const struct mips_operand *operand)
5603 unsigned int regno, uval;
5605 const struct mips_opcode *opcode;
5607 /* The mips_opcode records whether this is an octobyte or quadhalf
5608 instruction. Start out with that bit in place. */
5609 opcode = arg->insn->insn_mo;
5610 uval = mips_extract_operand (operand, opcode->match);
5611 is_qh = (uval != 0);
5613 if (arg->token->type == OT_REG)
5615 if ((opcode->membership & INSN_5400)
5616 && strcmp (opcode->name, "rzu.ob") == 0)
5618 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5623 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5627 /* Check whether this is a vector register or a broadcast of
5628 a single element. */
5629 if (arg->token->type == OT_INTEGER_INDEX)
5631 if (arg->token->u.index > (is_qh ? 3 : 7))
5633 set_insn_error (arg->argnum, _("invalid element selector"));
5636 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5641 /* A full vector. */
5642 if ((opcode->membership & INSN_5400)
5643 && (strcmp (opcode->name, "sll.ob") == 0
5644 || strcmp (opcode->name, "srl.ob") == 0))
5646 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5652 uval |= MDMX_FMTSEL_VEC_QH << 5;
5654 uval |= MDMX_FMTSEL_VEC_OB << 5;
5662 if (!match_const_int (arg, &sval))
5664 if (sval < 0 || sval > 31)
5666 match_out_of_range (arg);
5669 uval |= (sval & 31);
5671 uval |= MDMX_FMTSEL_IMM_QH << 5;
5673 uval |= MDMX_FMTSEL_IMM_OB << 5;
5675 insn_insert_operand (arg->insn, operand, uval);
5679 /* OP_IMM_INDEX matcher. */
5682 match_imm_index_operand (struct mips_arg_info *arg,
5683 const struct mips_operand *operand)
5685 unsigned int max_val;
5687 if (arg->token->type != OT_INTEGER_INDEX)
5690 max_val = (1 << operand->size) - 1;
5691 if (arg->token->u.index > max_val)
5693 match_out_of_range (arg);
5696 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5701 /* OP_REG_INDEX matcher. */
5704 match_reg_index_operand (struct mips_arg_info *arg,
5705 const struct mips_operand *operand)
5709 if (arg->token->type != OT_REG_INDEX)
5712 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5715 insn_insert_operand (arg->insn, operand, regno);
5720 /* OP_PC matcher. */
5723 match_pc_operand (struct mips_arg_info *arg)
5725 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5733 /* OP_NON_ZERO_REG matcher. */
5736 match_non_zero_reg_operand (struct mips_arg_info *arg,
5737 const struct mips_operand *operand)
5741 if (!match_reg (arg, OP_REG_GP, ®no))
5747 arg->last_regno = regno;
5748 insn_insert_operand (arg->insn, operand, regno);
5752 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5753 register that we need to match. */
5756 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5760 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5763 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5764 the length of the value in bytes (4 for float, 8 for double) and
5765 USING_GPRS says whether the destination is a GPR rather than an FPR.
5767 Return the constant in IMM and OFFSET as follows:
5769 - If the constant should be loaded via memory, set IMM to O_absent and
5770 OFFSET to the memory address.
5772 - Otherwise, if the constant should be loaded into two 32-bit registers,
5773 set IMM to the O_constant to load into the high register and OFFSET
5774 to the corresponding value for the low register.
5776 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5778 These constants only appear as the last operand in an instruction,
5779 and every instruction that accepts them in any variant accepts them
5780 in all variants. This means we don't have to worry about backing out
5781 any changes if the instruction does not match. We just match
5782 unconditionally and report an error if the constant is invalid. */
5785 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5786 expressionS *offset, int length, bfd_boolean using_gprs)
5791 const char *newname;
5792 unsigned char *data;
5794 /* Where the constant is placed is based on how the MIPS assembler
5797 length == 4 && using_gprs -- immediate value only
5798 length == 8 && using_gprs -- .rdata or immediate value
5799 length == 4 && !using_gprs -- .lit4 or immediate value
5800 length == 8 && !using_gprs -- .lit8 or immediate value
5802 The .lit4 and .lit8 sections are only used if permitted by the
5804 if (arg->token->type != OT_FLOAT)
5806 set_insn_error (arg->argnum, _("floating-point expression required"));
5810 gas_assert (arg->token->u.flt.length == length);
5811 data = arg->token->u.flt.data;
5814 /* Handle 32-bit constants for which an immediate value is best. */
5817 || g_switch_value < 4
5818 || (data[0] == 0 && data[1] == 0)
5819 || (data[2] == 0 && data[3] == 0)))
5821 imm->X_op = O_constant;
5822 if (!target_big_endian)
5823 imm->X_add_number = bfd_getl32 (data);
5825 imm->X_add_number = bfd_getb32 (data);
5826 offset->X_op = O_absent;
5830 /* Handle 64-bit constants for which an immediate value is best. */
5832 && !mips_disable_float_construction
5833 /* Constants can only be constructed in GPRs and copied to FPRs if the
5834 GPRs are at least as wide as the FPRs or MTHC1 is available.
5835 Unlike most tests for 32-bit floating-point registers this check
5836 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5837 permit 64-bit moves without MXHC1.
5838 Force the constant into memory otherwise. */
5841 || ISA_HAS_MXHC1 (mips_opts.isa)
5843 && ((data[0] == 0 && data[1] == 0)
5844 || (data[2] == 0 && data[3] == 0))
5845 && ((data[4] == 0 && data[5] == 0)
5846 || (data[6] == 0 && data[7] == 0)))
5848 /* The value is simple enough to load with a couple of instructions.
5849 If using 32-bit registers, set IMM to the high order 32 bits and
5850 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5852 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
5854 imm->X_op = O_constant;
5855 offset->X_op = O_constant;
5856 if (!target_big_endian)
5858 imm->X_add_number = bfd_getl32 (data + 4);
5859 offset->X_add_number = bfd_getl32 (data);
5863 imm->X_add_number = bfd_getb32 (data);
5864 offset->X_add_number = bfd_getb32 (data + 4);
5866 if (offset->X_add_number == 0)
5867 offset->X_op = O_absent;
5871 imm->X_op = O_constant;
5872 if (!target_big_endian)
5873 imm->X_add_number = bfd_getl64 (data);
5875 imm->X_add_number = bfd_getb64 (data);
5876 offset->X_op = O_absent;
5881 /* Switch to the right section. */
5883 subseg = now_subseg;
5886 gas_assert (!using_gprs && g_switch_value >= 4);
5891 if (using_gprs || g_switch_value < 8)
5892 newname = RDATA_SECTION_NAME;
5897 new_seg = subseg_new (newname, (subsegT) 0);
5898 bfd_set_section_flags (stdoutput, new_seg,
5899 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5900 frag_align (length == 4 ? 2 : 3, 0, 0);
5901 if (strncmp (TARGET_OS, "elf", 3) != 0)
5902 record_alignment (new_seg, 4);
5904 record_alignment (new_seg, length == 4 ? 2 : 3);
5906 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
5908 /* Set the argument to the current address in the section. */
5909 imm->X_op = O_absent;
5910 offset->X_op = O_symbol;
5911 offset->X_add_symbol = symbol_temp_new_now ();
5912 offset->X_add_number = 0;
5914 /* Put the floating point number into the section. */
5915 p = frag_more (length);
5916 memcpy (p, data, length);
5918 /* Switch back to the original section. */
5919 subseg_set (seg, subseg);
5923 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5927 match_vu0_suffix_operand (struct mips_arg_info *arg,
5928 const struct mips_operand *operand,
5929 bfd_boolean match_p)
5933 /* The operand can be an XYZW mask or a single 2-bit channel index
5934 (with X being 0). */
5935 gas_assert (operand->size == 2 || operand->size == 4);
5937 /* The suffix can be omitted when it is already part of the opcode. */
5938 if (arg->token->type != OT_CHANNELS)
5941 uval = arg->token->u.channels;
5942 if (operand->size == 2)
5944 /* Check that a single bit is set and convert it into a 2-bit index. */
5945 if ((uval & -uval) != uval)
5947 uval = 4 - ffs (uval);
5950 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5955 insn_insert_operand (arg->insn, operand, uval);
5959 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5960 of the argument text if the match is successful, otherwise return null. */
5963 match_operand (struct mips_arg_info *arg,
5964 const struct mips_operand *operand)
5966 switch (operand->type)
5969 return match_int_operand (arg, operand);
5972 return match_mapped_int_operand (arg, operand);
5975 return match_msb_operand (arg, operand);
5978 case OP_OPTIONAL_REG:
5979 return match_reg_operand (arg, operand);
5982 return match_reg_pair_operand (arg, operand);
5985 return match_pcrel_operand (arg);
5988 return match_perf_reg_operand (arg, operand);
5990 case OP_ADDIUSP_INT:
5991 return match_addiusp_operand (arg, operand);
5993 case OP_CLO_CLZ_DEST:
5994 return match_clo_clz_dest_operand (arg, operand);
5996 case OP_LWM_SWM_LIST:
5997 return match_lwm_swm_list_operand (arg, operand);
5999 case OP_ENTRY_EXIT_LIST:
6000 return match_entry_exit_operand (arg, operand);
6002 case OP_SAVE_RESTORE_LIST:
6003 return match_save_restore_list_operand (arg);
6005 case OP_MDMX_IMM_REG:
6006 return match_mdmx_imm_reg_operand (arg, operand);
6008 case OP_REPEAT_DEST_REG:
6009 return match_tied_reg_operand (arg, arg->dest_regno);
6011 case OP_REPEAT_PREV_REG:
6012 return match_tied_reg_operand (arg, arg->last_regno);
6015 return match_pc_operand (arg);
6018 return match_vu0_suffix_operand (arg, operand, FALSE);
6020 case OP_VU0_MATCH_SUFFIX:
6021 return match_vu0_suffix_operand (arg, operand, TRUE);
6024 return match_imm_index_operand (arg, operand);
6027 return match_reg_index_operand (arg, operand);
6030 return match_same_rs_rt_operand (arg, operand);
6033 return match_check_prev_operand (arg, operand);
6035 case OP_NON_ZERO_REG:
6036 return match_non_zero_reg_operand (arg, operand);
6041 /* ARG is the state after successfully matching an instruction.
6042 Issue any queued-up warnings. */
6045 check_completed_insn (struct mips_arg_info *arg)
6050 as_warn (_("used $at without \".set noat\""));
6052 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6056 /* Return true if modifying general-purpose register REG needs a delay. */
6059 reg_needs_delay (unsigned int reg)
6061 unsigned long prev_pinfo;
6063 prev_pinfo = history[0].insn_mo->pinfo;
6064 if (!mips_opts.noreorder
6065 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6066 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6067 && (gpr_write_mask (&history[0]) & (1 << reg)))
6073 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6074 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6075 by VR4120 errata. */
6078 classify_vr4120_insn (const char *name)
6080 if (strncmp (name, "macc", 4) == 0)
6081 return FIX_VR4120_MACC;
6082 if (strncmp (name, "dmacc", 5) == 0)
6083 return FIX_VR4120_DMACC;
6084 if (strncmp (name, "mult", 4) == 0)
6085 return FIX_VR4120_MULT;
6086 if (strncmp (name, "dmult", 5) == 0)
6087 return FIX_VR4120_DMULT;
6088 if (strstr (name, "div"))
6089 return FIX_VR4120_DIV;
6090 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6091 return FIX_VR4120_MTHILO;
6092 return NUM_FIX_VR4120_CLASSES;
6095 #define INSN_ERET 0x42000018
6096 #define INSN_DERET 0x4200001f
6097 #define INSN_DMULT 0x1c
6098 #define INSN_DMULTU 0x1d
6100 /* Return the number of instructions that must separate INSN1 and INSN2,
6101 where INSN1 is the earlier instruction. Return the worst-case value
6102 for any INSN2 if INSN2 is null. */
6105 insns_between (const struct mips_cl_insn *insn1,
6106 const struct mips_cl_insn *insn2)
6108 unsigned long pinfo1, pinfo2;
6111 /* If INFO2 is null, pessimistically assume that all flags are set for
6112 the second instruction. */
6113 pinfo1 = insn1->insn_mo->pinfo;
6114 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6116 /* For most targets, write-after-read dependencies on the HI and LO
6117 registers must be separated by at least two instructions. */
6118 if (!hilo_interlocks)
6120 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6122 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6126 /* If we're working around r7000 errata, there must be two instructions
6127 between an mfhi or mflo and any instruction that uses the result. */
6128 if (mips_7000_hilo_fix
6129 && !mips_opts.micromips
6130 && MF_HILO_INSN (pinfo1)
6131 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6134 /* If we're working around 24K errata, one instruction is required
6135 if an ERET or DERET is followed by a branch instruction. */
6136 if (mips_fix_24k && !mips_opts.micromips)
6138 if (insn1->insn_opcode == INSN_ERET
6139 || insn1->insn_opcode == INSN_DERET)
6142 || insn2->insn_opcode == INSN_ERET
6143 || insn2->insn_opcode == INSN_DERET
6144 || delayed_branch_p (insn2))
6149 /* If we're working around PMC RM7000 errata, there must be three
6150 nops between a dmult and a load instruction. */
6151 if (mips_fix_rm7000 && !mips_opts.micromips)
6153 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6154 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6156 if (pinfo2 & INSN_LOAD_MEMORY)
6161 /* If working around VR4120 errata, check for combinations that need
6162 a single intervening instruction. */
6163 if (mips_fix_vr4120 && !mips_opts.micromips)
6165 unsigned int class1, class2;
6167 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6168 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6172 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6173 if (vr4120_conflicts[class1] & (1 << class2))
6178 if (!HAVE_CODE_COMPRESSION)
6180 /* Check for GPR or coprocessor load delays. All such delays
6181 are on the RT register. */
6182 /* Itbl support may require additional care here. */
6183 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6184 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6186 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6190 /* Check for generic coprocessor hazards.
6192 This case is not handled very well. There is no special
6193 knowledge of CP0 handling, and the coprocessors other than
6194 the floating point unit are not distinguished at all. */
6195 /* Itbl support may require additional care here. FIXME!
6196 Need to modify this to include knowledge about
6197 user specified delays! */
6198 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6199 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6201 /* Handle cases where INSN1 writes to a known general coprocessor
6202 register. There must be a one instruction delay before INSN2
6203 if INSN2 reads that register, otherwise no delay is needed. */
6204 mask = fpr_write_mask (insn1);
6207 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6212 /* Read-after-write dependencies on the control registers
6213 require a two-instruction gap. */
6214 if ((pinfo1 & INSN_WRITE_COND_CODE)
6215 && (pinfo2 & INSN_READ_COND_CODE))
6218 /* We don't know exactly what INSN1 does. If INSN2 is
6219 also a coprocessor instruction, assume there must be
6220 a one instruction gap. */
6221 if (pinfo2 & INSN_COP)
6226 /* Check for read-after-write dependencies on the coprocessor
6227 control registers in cases where INSN1 does not need a general
6228 coprocessor delay. This means that INSN1 is a floating point
6229 comparison instruction. */
6230 /* Itbl support may require additional care here. */
6231 else if (!cop_interlocks
6232 && (pinfo1 & INSN_WRITE_COND_CODE)
6233 && (pinfo2 & INSN_READ_COND_CODE))
6237 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6238 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6240 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6241 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6242 || (insn2 && delayed_branch_p (insn2))))
6248 /* Return the number of nops that would be needed to work around the
6249 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6250 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6251 that are contained within the first IGNORE instructions of HIST. */
6254 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6255 const struct mips_cl_insn *insn)
6260 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6261 are not affected by the errata. */
6263 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6264 || strcmp (insn->insn_mo->name, "mtlo") == 0
6265 || strcmp (insn->insn_mo->name, "mthi") == 0))
6268 /* Search for the first MFLO or MFHI. */
6269 for (i = 0; i < MAX_VR4130_NOPS; i++)
6270 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6272 /* Extract the destination register. */
6273 mask = gpr_write_mask (&hist[i]);
6275 /* No nops are needed if INSN reads that register. */
6276 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6279 /* ...or if any of the intervening instructions do. */
6280 for (j = 0; j < i; j++)
6281 if (gpr_read_mask (&hist[j]) & mask)
6285 return MAX_VR4130_NOPS - i;
6290 #define BASE_REG_EQ(INSN1, INSN2) \
6291 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6292 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6294 /* Return the minimum alignment for this store instruction. */
6297 fix_24k_align_to (const struct mips_opcode *mo)
6299 if (strcmp (mo->name, "sh") == 0)
6302 if (strcmp (mo->name, "swc1") == 0
6303 || strcmp (mo->name, "swc2") == 0
6304 || strcmp (mo->name, "sw") == 0
6305 || strcmp (mo->name, "sc") == 0
6306 || strcmp (mo->name, "s.s") == 0)
6309 if (strcmp (mo->name, "sdc1") == 0
6310 || strcmp (mo->name, "sdc2") == 0
6311 || strcmp (mo->name, "s.d") == 0)
6318 struct fix_24k_store_info
6320 /* Immediate offset, if any, for this store instruction. */
6322 /* Alignment required by this store instruction. */
6324 /* True for register offsets. */
6325 int register_offset;
6328 /* Comparison function used by qsort. */
6331 fix_24k_sort (const void *a, const void *b)
6333 const struct fix_24k_store_info *pos1 = a;
6334 const struct fix_24k_store_info *pos2 = b;
6336 return (pos1->off - pos2->off);
6339 /* INSN is a store instruction. Try to record the store information
6340 in STINFO. Return false if the information isn't known. */
6343 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6344 const struct mips_cl_insn *insn)
6346 /* The instruction must have a known offset. */
6347 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6350 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6351 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6355 /* Return the number of nops that would be needed to work around the 24k
6356 "lost data on stores during refill" errata if instruction INSN
6357 immediately followed the 2 instructions described by HIST.
6358 Ignore hazards that are contained within the first IGNORE
6359 instructions of HIST.
6361 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6362 for the data cache refills and store data. The following describes
6363 the scenario where the store data could be lost.
6365 * A data cache miss, due to either a load or a store, causing fill
6366 data to be supplied by the memory subsystem
6367 * The first three doublewords of fill data are returned and written
6369 * A sequence of four stores occurs in consecutive cycles around the
6370 final doubleword of the fill:
6374 * Zero, One or more instructions
6377 The four stores A-D must be to different doublewords of the line that
6378 is being filled. The fourth instruction in the sequence above permits
6379 the fill of the final doubleword to be transferred from the FSB into
6380 the cache. In the sequence above, the stores may be either integer
6381 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6382 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6383 different doublewords on the line. If the floating point unit is
6384 running in 1:2 mode, it is not possible to create the sequence above
6385 using only floating point store instructions.
6387 In this case, the cache line being filled is incorrectly marked
6388 invalid, thereby losing the data from any store to the line that
6389 occurs between the original miss and the completion of the five
6390 cycle sequence shown above.
6392 The workarounds are:
6394 * Run the data cache in write-through mode.
6395 * Insert a non-store instruction between
6396 Store A and Store B or Store B and Store C. */
6399 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6400 const struct mips_cl_insn *insn)
6402 struct fix_24k_store_info pos[3];
6403 int align, i, base_offset;
6408 /* If the previous instruction wasn't a store, there's nothing to
6410 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6413 /* If the instructions after the previous one are unknown, we have
6414 to assume the worst. */
6418 /* Check whether we are dealing with three consecutive stores. */
6419 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6420 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6423 /* If we don't know the relationship between the store addresses,
6424 assume the worst. */
6425 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6426 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6429 if (!fix_24k_record_store_info (&pos[0], insn)
6430 || !fix_24k_record_store_info (&pos[1], &hist[0])
6431 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6434 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6436 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6437 X bytes and such that the base register + X is known to be aligned
6440 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6444 align = pos[0].align_to;
6445 base_offset = pos[0].off;
6446 for (i = 1; i < 3; i++)
6447 if (align < pos[i].align_to)
6449 align = pos[i].align_to;
6450 base_offset = pos[i].off;
6452 for (i = 0; i < 3; i++)
6453 pos[i].off -= base_offset;
6456 pos[0].off &= ~align + 1;
6457 pos[1].off &= ~align + 1;
6458 pos[2].off &= ~align + 1;
6460 /* If any two stores write to the same chunk, they also write to the
6461 same doubleword. The offsets are still sorted at this point. */
6462 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6465 /* A range of at least 9 bytes is needed for the stores to be in
6466 non-overlapping doublewords. */
6467 if (pos[2].off - pos[0].off <= 8)
6470 if (pos[2].off - pos[1].off >= 24
6471 || pos[1].off - pos[0].off >= 24
6472 || pos[2].off - pos[0].off >= 32)
6478 /* Return the number of nops that would be needed if instruction INSN
6479 immediately followed the MAX_NOPS instructions given by HIST,
6480 where HIST[0] is the most recent instruction. Ignore hazards
6481 between INSN and the first IGNORE instructions in HIST.
6483 If INSN is null, return the worse-case number of nops for any
6487 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6488 const struct mips_cl_insn *insn)
6490 int i, nops, tmp_nops;
6493 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6495 tmp_nops = insns_between (hist + i, insn) - i;
6496 if (tmp_nops > nops)
6500 if (mips_fix_vr4130 && !mips_opts.micromips)
6502 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6503 if (tmp_nops > nops)
6507 if (mips_fix_24k && !mips_opts.micromips)
6509 tmp_nops = nops_for_24k (ignore, hist, insn);
6510 if (tmp_nops > nops)
6517 /* The variable arguments provide NUM_INSNS extra instructions that
6518 might be added to HIST. Return the largest number of nops that
6519 would be needed after the extended sequence, ignoring hazards
6520 in the first IGNORE instructions. */
6523 nops_for_sequence (int num_insns, int ignore,
6524 const struct mips_cl_insn *hist, ...)
6527 struct mips_cl_insn buffer[MAX_NOPS];
6528 struct mips_cl_insn *cursor;
6531 va_start (args, hist);
6532 cursor = buffer + num_insns;
6533 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6534 while (cursor > buffer)
6535 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6537 nops = nops_for_insn (ignore, buffer, NULL);
6542 /* Like nops_for_insn, but if INSN is a branch, take into account the
6543 worst-case delay for the branch target. */
6546 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6547 const struct mips_cl_insn *insn)
6551 nops = nops_for_insn (ignore, hist, insn);
6552 if (delayed_branch_p (insn))
6554 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6555 hist, insn, get_delay_slot_nop (insn));
6556 if (tmp_nops > nops)
6559 else if (compact_branch_p (insn))
6561 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6562 if (tmp_nops > nops)
6568 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6571 fix_loongson2f_nop (struct mips_cl_insn * ip)
6573 gas_assert (!HAVE_CODE_COMPRESSION);
6574 if (strcmp (ip->insn_mo->name, "nop") == 0)
6575 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6578 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6579 jr target pc &= 'hffff_ffff_cfff_ffff. */
6582 fix_loongson2f_jump (struct mips_cl_insn * ip)
6584 gas_assert (!HAVE_CODE_COMPRESSION);
6585 if (strcmp (ip->insn_mo->name, "j") == 0
6586 || strcmp (ip->insn_mo->name, "jr") == 0
6587 || strcmp (ip->insn_mo->name, "jalr") == 0)
6595 sreg = EXTRACT_OPERAND (0, RS, *ip);
6596 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6599 ep.X_op = O_constant;
6600 ep.X_add_number = 0xcfff0000;
6601 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6602 ep.X_add_number = 0xffff;
6603 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6604 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6609 fix_loongson2f (struct mips_cl_insn * ip)
6611 if (mips_fix_loongson2f_nop)
6612 fix_loongson2f_nop (ip);
6614 if (mips_fix_loongson2f_jump)
6615 fix_loongson2f_jump (ip);
6618 /* IP is a branch that has a delay slot, and we need to fill it
6619 automatically. Return true if we can do that by swapping IP
6620 with the previous instruction.
6621 ADDRESS_EXPR is an operand of the instruction to be used with
6625 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6626 bfd_reloc_code_real_type *reloc_type)
6628 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6629 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6630 unsigned int fpr_read, prev_fpr_write;
6632 /* -O2 and above is required for this optimization. */
6633 if (mips_optimize < 2)
6636 /* If we have seen .set volatile or .set nomove, don't optimize. */
6637 if (mips_opts.nomove)
6640 /* We can't swap if the previous instruction's position is fixed. */
6641 if (history[0].fixed_p)
6644 /* If the previous previous insn was in a .set noreorder, we can't
6645 swap. Actually, the MIPS assembler will swap in this situation.
6646 However, gcc configured -with-gnu-as will generate code like
6654 in which we can not swap the bne and INSN. If gcc is not configured
6655 -with-gnu-as, it does not output the .set pseudo-ops. */
6656 if (history[1].noreorder_p)
6659 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6660 This means that the previous instruction was a 4-byte one anyhow. */
6661 if (mips_opts.mips16 && history[0].fixp[0])
6664 /* If the branch is itself the target of a branch, we can not swap.
6665 We cheat on this; all we check for is whether there is a label on
6666 this instruction. If there are any branches to anything other than
6667 a label, users must use .set noreorder. */
6668 if (seg_info (now_seg)->label_list)
6671 /* If the previous instruction is in a variant frag other than this
6672 branch's one, we cannot do the swap. This does not apply to
6673 MIPS16 code, which uses variant frags for different purposes. */
6674 if (!mips_opts.mips16
6676 && history[0].frag->fr_type == rs_machine_dependent)
6679 /* We do not swap with instructions that cannot architecturally
6680 be placed in a branch delay slot, such as SYNC or ERET. We
6681 also refrain from swapping with a trap instruction, since it
6682 complicates trap handlers to have the trap instruction be in
6684 prev_pinfo = history[0].insn_mo->pinfo;
6685 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6688 /* Check for conflicts between the branch and the instructions
6689 before the candidate delay slot. */
6690 if (nops_for_insn (0, history + 1, ip) > 0)
6693 /* Check for conflicts between the swapped sequence and the
6694 target of the branch. */
6695 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6698 /* If the branch reads a register that the previous
6699 instruction sets, we can not swap. */
6700 gpr_read = gpr_read_mask (ip);
6701 prev_gpr_write = gpr_write_mask (&history[0]);
6702 if (gpr_read & prev_gpr_write)
6705 fpr_read = fpr_read_mask (ip);
6706 prev_fpr_write = fpr_write_mask (&history[0]);
6707 if (fpr_read & prev_fpr_write)
6710 /* If the branch writes a register that the previous
6711 instruction sets, we can not swap. */
6712 gpr_write = gpr_write_mask (ip);
6713 if (gpr_write & prev_gpr_write)
6716 /* If the branch writes a register that the previous
6717 instruction reads, we can not swap. */
6718 prev_gpr_read = gpr_read_mask (&history[0]);
6719 if (gpr_write & prev_gpr_read)
6722 /* If one instruction sets a condition code and the
6723 other one uses a condition code, we can not swap. */
6724 pinfo = ip->insn_mo->pinfo;
6725 if ((pinfo & INSN_READ_COND_CODE)
6726 && (prev_pinfo & INSN_WRITE_COND_CODE))
6728 if ((pinfo & INSN_WRITE_COND_CODE)
6729 && (prev_pinfo & INSN_READ_COND_CODE))
6732 /* If the previous instruction uses the PC, we can not swap. */
6733 prev_pinfo2 = history[0].insn_mo->pinfo2;
6734 if (prev_pinfo2 & INSN2_READ_PC)
6737 /* If the previous instruction has an incorrect size for a fixed
6738 branch delay slot in microMIPS mode, we cannot swap. */
6739 pinfo2 = ip->insn_mo->pinfo2;
6740 if (mips_opts.micromips
6741 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6742 && insn_length (history) != 2)
6744 if (mips_opts.micromips
6745 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6746 && insn_length (history) != 4)
6749 /* On R5900 short loops need to be fixed by inserting a nop in
6750 the branch delay slots.
6751 A short loop can be terminated too early. */
6752 if (mips_opts.arch == CPU_R5900
6753 /* Check if instruction has a parameter, ignore "j $31". */
6754 && (address_expr != NULL)
6755 /* Parameter must be 16 bit. */
6756 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6757 /* Branch to same segment. */
6758 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6759 /* Branch to same code fragment. */
6760 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6761 /* Can only calculate branch offset if value is known. */
6762 && symbol_constant_p (address_expr->X_add_symbol)
6763 /* Check if branch is really conditional. */
6764 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6765 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6766 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6769 /* Check if loop is shorter than 6 instructions including
6770 branch and delay slot. */
6771 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
6778 /* When the loop includes branches or jumps,
6779 it is not a short loop. */
6780 for (i = 0; i < (distance / 4); i++)
6782 if ((history[i].cleared_p)
6783 || delayed_branch_p (&history[i]))
6791 /* Insert nop after branch to fix short loop. */
6800 /* Decide how we should add IP to the instruction stream.
6801 ADDRESS_EXPR is an operand of the instruction to be used with
6804 static enum append_method
6805 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6806 bfd_reloc_code_real_type *reloc_type)
6808 /* The relaxed version of a macro sequence must be inherently
6810 if (mips_relax.sequence == 2)
6813 /* We must not dabble with instructions in a ".set norerorder" block. */
6814 if (mips_opts.noreorder)
6817 /* Otherwise, it's our responsibility to fill branch delay slots. */
6818 if (delayed_branch_p (ip))
6820 if (!branch_likely_p (ip)
6821 && can_swap_branch_p (ip, address_expr, reloc_type))
6824 if (mips_opts.mips16
6825 && ISA_SUPPORTS_MIPS16E
6826 && gpr_read_mask (ip) != 0)
6827 return APPEND_ADD_COMPACT;
6829 return APPEND_ADD_WITH_NOP;
6835 /* IP is a MIPS16 instruction whose opcode we have just changed.
6836 Point IP->insn_mo to the new opcode's definition. */
6839 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6841 const struct mips_opcode *mo, *end;
6843 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6844 for (mo = ip->insn_mo; mo < end; mo++)
6845 if ((ip->insn_opcode & mo->mask) == mo->match)
6853 /* For microMIPS macros, we need to generate a local number label
6854 as the target of branches. */
6855 #define MICROMIPS_LABEL_CHAR '\037'
6856 static unsigned long micromips_target_label;
6857 static char micromips_target_name[32];
6860 micromips_label_name (void)
6862 char *p = micromips_target_name;
6863 char symbol_name_temporary[24];
6871 l = micromips_target_label;
6872 #ifdef LOCAL_LABEL_PREFIX
6873 *p++ = LOCAL_LABEL_PREFIX;
6876 *p++ = MICROMIPS_LABEL_CHAR;
6879 symbol_name_temporary[i++] = l % 10 + '0';
6884 *p++ = symbol_name_temporary[--i];
6887 return micromips_target_name;
6891 micromips_label_expr (expressionS *label_expr)
6893 label_expr->X_op = O_symbol;
6894 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6895 label_expr->X_add_number = 0;
6899 micromips_label_inc (void)
6901 micromips_target_label++;
6902 *micromips_target_name = '\0';
6906 micromips_add_label (void)
6910 s = colon (micromips_label_name ());
6911 micromips_label_inc ();
6912 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6915 /* If assembling microMIPS code, then return the microMIPS reloc
6916 corresponding to the requested one if any. Otherwise return
6917 the reloc unchanged. */
6919 static bfd_reloc_code_real_type
6920 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6922 static const bfd_reloc_code_real_type relocs[][2] =
6924 /* Keep sorted incrementally by the left-hand key. */
6925 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6926 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6927 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6928 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6929 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6930 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6931 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6932 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6933 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6934 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6935 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6936 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6937 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6938 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6939 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6940 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6941 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6942 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6943 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6944 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6945 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6946 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6947 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6948 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6949 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6950 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6951 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6953 bfd_reloc_code_real_type r;
6956 if (!mips_opts.micromips)
6958 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6964 return relocs[i][1];
6969 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6970 Return true on success, storing the resolved value in RESULT. */
6973 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6978 case BFD_RELOC_MIPS_HIGHEST:
6979 case BFD_RELOC_MICROMIPS_HIGHEST:
6980 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6983 case BFD_RELOC_MIPS_HIGHER:
6984 case BFD_RELOC_MICROMIPS_HIGHER:
6985 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6988 case BFD_RELOC_HI16_S:
6989 case BFD_RELOC_HI16_S_PCREL:
6990 case BFD_RELOC_MICROMIPS_HI16_S:
6991 case BFD_RELOC_MIPS16_HI16_S:
6992 *result = ((operand + 0x8000) >> 16) & 0xffff;
6995 case BFD_RELOC_HI16:
6996 case BFD_RELOC_MICROMIPS_HI16:
6997 case BFD_RELOC_MIPS16_HI16:
6998 *result = (operand >> 16) & 0xffff;
7001 case BFD_RELOC_LO16:
7002 case BFD_RELOC_LO16_PCREL:
7003 case BFD_RELOC_MICROMIPS_LO16:
7004 case BFD_RELOC_MIPS16_LO16:
7005 *result = operand & 0xffff;
7008 case BFD_RELOC_UNUSED:
7017 /* Output an instruction. IP is the instruction information.
7018 ADDRESS_EXPR is an operand of the instruction to be used with
7019 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7020 a macro expansion. */
7023 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7024 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7026 unsigned long prev_pinfo2, pinfo;
7027 bfd_boolean relaxed_branch = FALSE;
7028 enum append_method method;
7029 bfd_boolean relax32;
7032 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7033 fix_loongson2f (ip);
7035 file_ase_mips16 |= mips_opts.mips16;
7036 file_ase_micromips |= mips_opts.micromips;
7038 prev_pinfo2 = history[0].insn_mo->pinfo2;
7039 pinfo = ip->insn_mo->pinfo;
7041 if (mips_opts.micromips
7043 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7044 && micromips_insn_length (ip->insn_mo) != 2)
7045 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7046 && micromips_insn_length (ip->insn_mo) != 4)))
7047 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7048 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7050 if (address_expr == NULL)
7052 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7053 && reloc_type[1] == BFD_RELOC_UNUSED
7054 && reloc_type[2] == BFD_RELOC_UNUSED
7055 && address_expr->X_op == O_constant)
7057 switch (*reloc_type)
7059 case BFD_RELOC_MIPS_JMP:
7063 /* Shift is 2, unusually, for microMIPS JALX. */
7064 shift = (mips_opts.micromips
7065 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7066 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7067 as_bad (_("jump to misaligned address (0x%lx)"),
7068 (unsigned long) address_expr->X_add_number);
7069 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7075 case BFD_RELOC_MIPS16_JMP:
7076 if ((address_expr->X_add_number & 3) != 0)
7077 as_bad (_("jump to misaligned address (0x%lx)"),
7078 (unsigned long) address_expr->X_add_number);
7080 (((address_expr->X_add_number & 0x7c0000) << 3)
7081 | ((address_expr->X_add_number & 0xf800000) >> 7)
7082 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7086 case BFD_RELOC_16_PCREL_S2:
7090 shift = mips_opts.micromips ? 1 : 2;
7091 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7092 as_bad (_("branch to misaligned address (0x%lx)"),
7093 (unsigned long) address_expr->X_add_number);
7094 if (!mips_relax_branch)
7096 if ((address_expr->X_add_number + (1 << (shift + 15)))
7097 & ~((1 << (shift + 16)) - 1))
7098 as_bad (_("branch address range overflow (0x%lx)"),
7099 (unsigned long) address_expr->X_add_number);
7100 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7106 case BFD_RELOC_MIPS_21_PCREL_S2:
7111 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7112 as_bad (_("branch to misaligned address (0x%lx)"),
7113 (unsigned long) address_expr->X_add_number);
7114 if ((address_expr->X_add_number + (1 << (shift + 20)))
7115 & ~((1 << (shift + 21)) - 1))
7116 as_bad (_("branch address range overflow (0x%lx)"),
7117 (unsigned long) address_expr->X_add_number);
7118 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7123 case BFD_RELOC_MIPS_26_PCREL_S2:
7128 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7129 as_bad (_("branch to misaligned address (0x%lx)"),
7130 (unsigned long) address_expr->X_add_number);
7131 if ((address_expr->X_add_number + (1 << (shift + 25)))
7132 & ~((1 << (shift + 26)) - 1))
7133 as_bad (_("branch address range overflow (0x%lx)"),
7134 (unsigned long) address_expr->X_add_number);
7135 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7144 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7147 ip->insn_opcode |= value & 0xffff;
7155 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7157 /* There are a lot of optimizations we could do that we don't.
7158 In particular, we do not, in general, reorder instructions.
7159 If you use gcc with optimization, it will reorder
7160 instructions and generally do much more optimization then we
7161 do here; repeating all that work in the assembler would only
7162 benefit hand written assembly code, and does not seem worth
7164 int nops = (mips_optimize == 0
7165 ? nops_for_insn (0, history, NULL)
7166 : nops_for_insn_or_target (0, history, ip));
7170 unsigned long old_frag_offset;
7173 old_frag = frag_now;
7174 old_frag_offset = frag_now_fix ();
7176 for (i = 0; i < nops; i++)
7177 add_fixed_insn (NOP_INSN);
7178 insert_into_history (0, nops, NOP_INSN);
7182 listing_prev_line ();
7183 /* We may be at the start of a variant frag. In case we
7184 are, make sure there is enough space for the frag
7185 after the frags created by listing_prev_line. The
7186 argument to frag_grow here must be at least as large
7187 as the argument to all other calls to frag_grow in
7188 this file. We don't have to worry about being in the
7189 middle of a variant frag, because the variants insert
7190 all needed nop instructions themselves. */
7194 mips_move_text_labels ();
7196 #ifndef NO_ECOFF_DEBUGGING
7197 if (ECOFF_DEBUGGING)
7198 ecoff_fix_loc (old_frag, old_frag_offset);
7202 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7206 /* Work out how many nops in prev_nop_frag are needed by IP,
7207 ignoring hazards generated by the first prev_nop_frag_since
7209 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7210 gas_assert (nops <= prev_nop_frag_holds);
7212 /* Enforce NOPS as a minimum. */
7213 if (nops > prev_nop_frag_required)
7214 prev_nop_frag_required = nops;
7216 if (prev_nop_frag_holds == prev_nop_frag_required)
7218 /* Settle for the current number of nops. Update the history
7219 accordingly (for the benefit of any future .set reorder code). */
7220 prev_nop_frag = NULL;
7221 insert_into_history (prev_nop_frag_since,
7222 prev_nop_frag_holds, NOP_INSN);
7226 /* Allow this instruction to replace one of the nops that was
7227 tentatively added to prev_nop_frag. */
7228 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7229 prev_nop_frag_holds--;
7230 prev_nop_frag_since++;
7234 method = get_append_method (ip, address_expr, reloc_type);
7235 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7237 dwarf2_emit_insn (0);
7238 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7239 so "move" the instruction address accordingly.
7241 Also, it doesn't seem appropriate for the assembler to reorder .loc
7242 entries. If this instruction is a branch that we are going to swap
7243 with the previous instruction, the two instructions should be
7244 treated as a unit, and the debug information for both instructions
7245 should refer to the start of the branch sequence. Using the
7246 current position is certainly wrong when swapping a 32-bit branch
7247 and a 16-bit delay slot, since the current position would then be
7248 in the middle of a branch. */
7249 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7251 relax32 = (mips_relax_branch
7252 /* Don't try branch relaxation within .set nomacro, or within
7253 .set noat if we use $at for PIC computations. If it turns
7254 out that the branch was out-of-range, we'll get an error. */
7255 && !mips_opts.warn_about_macros
7256 && (mips_opts.at || mips_pic == NO_PIC)
7257 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7258 as they have no complementing branches. */
7259 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7261 if (!HAVE_CODE_COMPRESSION
7264 && *reloc_type == BFD_RELOC_16_PCREL_S2
7265 && delayed_branch_p (ip))
7267 relaxed_branch = TRUE;
7268 add_relaxed_insn (ip, (relaxed_branch_length
7270 uncond_branch_p (ip) ? -1
7271 : branch_likely_p (ip) ? 1
7275 uncond_branch_p (ip),
7276 branch_likely_p (ip),
7277 pinfo & INSN_WRITE_GPR_31,
7279 address_expr->X_add_symbol,
7280 address_expr->X_add_number);
7281 *reloc_type = BFD_RELOC_UNUSED;
7283 else if (mips_opts.micromips
7285 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7286 || *reloc_type > BFD_RELOC_UNUSED)
7287 && (delayed_branch_p (ip) || compact_branch_p (ip))
7288 /* Don't try branch relaxation when users specify
7289 16-bit/32-bit instructions. */
7290 && !forced_insn_length)
7292 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
7293 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7294 int uncond = uncond_branch_p (ip) ? -1 : 0;
7295 int compact = compact_branch_p (ip);
7296 int al = pinfo & INSN_WRITE_GPR_31;
7299 gas_assert (address_expr != NULL);
7300 gas_assert (!mips_relax.sequence);
7302 relaxed_branch = TRUE;
7303 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7304 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
7305 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
7307 address_expr->X_add_symbol,
7308 address_expr->X_add_number);
7309 *reloc_type = BFD_RELOC_UNUSED;
7311 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7316 /* We need to set up a variant frag. */
7317 gas_assert (address_expr != NULL);
7318 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7319 symbol created by `make_expr_symbol' may not get a necessary
7320 external relocation produced. */
7321 if (address_expr->X_op == O_symbol)
7323 symbol = address_expr->X_add_symbol;
7324 offset = address_expr->X_add_number;
7328 symbol = make_expr_symbol (address_expr);
7331 add_relaxed_insn (ip, 4, 0,
7333 (*reloc_type - BFD_RELOC_UNUSED,
7334 forced_insn_length == 2, forced_insn_length == 4,
7335 delayed_branch_p (&history[0]),
7336 history[0].mips16_absolute_jump_p),
7339 else if (mips_opts.mips16 && insn_length (ip) == 2)
7341 if (!delayed_branch_p (ip))
7342 /* Make sure there is enough room to swap this instruction with
7343 a following jump instruction. */
7345 add_fixed_insn (ip);
7349 if (mips_opts.mips16
7350 && mips_opts.noreorder
7351 && delayed_branch_p (&history[0]))
7352 as_warn (_("extended instruction in delay slot"));
7354 if (mips_relax.sequence)
7356 /* If we've reached the end of this frag, turn it into a variant
7357 frag and record the information for the instructions we've
7359 if (frag_room () < 4)
7360 relax_close_frag ();
7361 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7364 if (mips_relax.sequence != 2)
7366 if (mips_macro_warning.first_insn_sizes[0] == 0)
7367 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7368 mips_macro_warning.sizes[0] += insn_length (ip);
7369 mips_macro_warning.insns[0]++;
7371 if (mips_relax.sequence != 1)
7373 if (mips_macro_warning.first_insn_sizes[1] == 0)
7374 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7375 mips_macro_warning.sizes[1] += insn_length (ip);
7376 mips_macro_warning.insns[1]++;
7379 if (mips_opts.mips16)
7382 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7384 add_fixed_insn (ip);
7387 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7389 bfd_reloc_code_real_type final_type[3];
7390 reloc_howto_type *howto0;
7391 reloc_howto_type *howto;
7394 /* Perform any necessary conversion to microMIPS relocations
7395 and find out how many relocations there actually are. */
7396 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7397 final_type[i] = micromips_map_reloc (reloc_type[i]);
7399 /* In a compound relocation, it is the final (outermost)
7400 operator that determines the relocated field. */
7401 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7406 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7407 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7408 bfd_get_reloc_size (howto),
7410 howto0 && howto0->pc_relative,
7413 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7414 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7415 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7417 /* These relocations can have an addend that won't fit in
7418 4 octets for 64bit assembly. */
7420 && ! howto->partial_inplace
7421 && (reloc_type[0] == BFD_RELOC_16
7422 || reloc_type[0] == BFD_RELOC_32
7423 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7424 || reloc_type[0] == BFD_RELOC_GPREL16
7425 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7426 || reloc_type[0] == BFD_RELOC_GPREL32
7427 || reloc_type[0] == BFD_RELOC_64
7428 || reloc_type[0] == BFD_RELOC_CTOR
7429 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7430 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7431 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7432 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7433 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7434 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7435 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7436 || hi16_reloc_p (reloc_type[0])
7437 || lo16_reloc_p (reloc_type[0])))
7438 ip->fixp[0]->fx_no_overflow = 1;
7440 /* These relocations can have an addend that won't fit in 2 octets. */
7441 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7442 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7443 ip->fixp[0]->fx_no_overflow = 1;
7445 if (mips_relax.sequence)
7447 if (mips_relax.first_fixup == 0)
7448 mips_relax.first_fixup = ip->fixp[0];
7450 else if (reloc_needs_lo_p (*reloc_type))
7452 struct mips_hi_fixup *hi_fixup;
7454 /* Reuse the last entry if it already has a matching %lo. */
7455 hi_fixup = mips_hi_fixup_list;
7457 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7459 hi_fixup = XNEW (struct mips_hi_fixup);
7460 hi_fixup->next = mips_hi_fixup_list;
7461 mips_hi_fixup_list = hi_fixup;
7463 hi_fixup->fixp = ip->fixp[0];
7464 hi_fixup->seg = now_seg;
7467 /* Add fixups for the second and third relocations, if given.
7468 Note that the ABI allows the second relocation to be
7469 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7470 moment we only use RSS_UNDEF, but we could add support
7471 for the others if it ever becomes necessary. */
7472 for (i = 1; i < 3; i++)
7473 if (reloc_type[i] != BFD_RELOC_UNUSED)
7475 ip->fixp[i] = fix_new (ip->frag, ip->where,
7476 ip->fixp[0]->fx_size, NULL, 0,
7477 FALSE, final_type[i]);
7479 /* Use fx_tcbit to mark compound relocs. */
7480 ip->fixp[0]->fx_tcbit = 1;
7481 ip->fixp[i]->fx_tcbit = 1;
7486 /* Update the register mask information. */
7487 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7488 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7493 insert_into_history (0, 1, ip);
7496 case APPEND_ADD_WITH_NOP:
7498 struct mips_cl_insn *nop;
7500 insert_into_history (0, 1, ip);
7501 nop = get_delay_slot_nop (ip);
7502 add_fixed_insn (nop);
7503 insert_into_history (0, 1, nop);
7504 if (mips_relax.sequence)
7505 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7509 case APPEND_ADD_COMPACT:
7510 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7511 gas_assert (mips_opts.mips16);
7512 ip->insn_opcode |= 0x0080;
7513 find_altered_mips16_opcode (ip);
7515 insert_into_history (0, 1, ip);
7520 struct mips_cl_insn delay = history[0];
7521 if (mips_opts.mips16)
7523 know (delay.frag == ip->frag);
7524 move_insn (ip, delay.frag, delay.where);
7525 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7527 else if (relaxed_branch || delay.frag != ip->frag)
7529 /* Add the delay slot instruction to the end of the
7530 current frag and shrink the fixed part of the
7531 original frag. If the branch occupies the tail of
7532 the latter, move it backwards to cover the gap. */
7533 delay.frag->fr_fix -= branch_disp;
7534 if (delay.frag == ip->frag)
7535 move_insn (ip, ip->frag, ip->where - branch_disp);
7536 add_fixed_insn (&delay);
7540 /* If this is not a relaxed branch and we are in the
7541 same frag, then just swap the instructions. */
7542 move_insn (ip, delay.frag, delay.where);
7543 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7547 insert_into_history (0, 1, &delay);
7552 /* If we have just completed an unconditional branch, clear the history. */
7553 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7554 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7558 mips_no_prev_insn ();
7560 for (i = 0; i < ARRAY_SIZE (history); i++)
7561 history[i].cleared_p = 1;
7564 /* We need to emit a label at the end of branch-likely macros. */
7565 if (emit_branch_likely_macro)
7567 emit_branch_likely_macro = FALSE;
7568 micromips_add_label ();
7571 /* We just output an insn, so the next one doesn't have a label. */
7572 mips_clear_insn_labels ();
7575 /* Forget that there was any previous instruction or label.
7576 When BRANCH is true, the branch history is also flushed. */
7579 mips_no_prev_insn (void)
7581 prev_nop_frag = NULL;
7582 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7583 mips_clear_insn_labels ();
7586 /* This function must be called before we emit something other than
7587 instructions. It is like mips_no_prev_insn except that it inserts
7588 any NOPS that might be needed by previous instructions. */
7591 mips_emit_delays (void)
7593 if (! mips_opts.noreorder)
7595 int nops = nops_for_insn (0, history, NULL);
7599 add_fixed_insn (NOP_INSN);
7600 mips_move_text_labels ();
7603 mips_no_prev_insn ();
7606 /* Start a (possibly nested) noreorder block. */
7609 start_noreorder (void)
7611 if (mips_opts.noreorder == 0)
7616 /* None of the instructions before the .set noreorder can be moved. */
7617 for (i = 0; i < ARRAY_SIZE (history); i++)
7618 history[i].fixed_p = 1;
7620 /* Insert any nops that might be needed between the .set noreorder
7621 block and the previous instructions. We will later remove any
7622 nops that turn out not to be needed. */
7623 nops = nops_for_insn (0, history, NULL);
7626 if (mips_optimize != 0)
7628 /* Record the frag which holds the nop instructions, so
7629 that we can remove them if we don't need them. */
7630 frag_grow (nops * NOP_INSN_SIZE);
7631 prev_nop_frag = frag_now;
7632 prev_nop_frag_holds = nops;
7633 prev_nop_frag_required = 0;
7634 prev_nop_frag_since = 0;
7637 for (; nops > 0; --nops)
7638 add_fixed_insn (NOP_INSN);
7640 /* Move on to a new frag, so that it is safe to simply
7641 decrease the size of prev_nop_frag. */
7642 frag_wane (frag_now);
7644 mips_move_text_labels ();
7646 mips_mark_labels ();
7647 mips_clear_insn_labels ();
7649 mips_opts.noreorder++;
7650 mips_any_noreorder = 1;
7653 /* End a nested noreorder block. */
7656 end_noreorder (void)
7658 mips_opts.noreorder--;
7659 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7661 /* Commit to inserting prev_nop_frag_required nops and go back to
7662 handling nop insertion the .set reorder way. */
7663 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7665 insert_into_history (prev_nop_frag_since,
7666 prev_nop_frag_required, NOP_INSN);
7667 prev_nop_frag = NULL;
7671 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7672 higher bits unset. */
7675 normalize_constant_expr (expressionS *ex)
7677 if (ex->X_op == O_constant
7678 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7679 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7683 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7684 all higher bits unset. */
7687 normalize_address_expr (expressionS *ex)
7689 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7690 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7691 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7692 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7696 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7697 Return true if the match was successful.
7699 OPCODE_EXTRA is a value that should be ORed into the opcode
7700 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7701 there are more alternatives after OPCODE and SOFT_MATCH is
7702 as for mips_arg_info. */
7705 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7706 struct mips_operand_token *tokens, unsigned int opcode_extra,
7707 bfd_boolean lax_match, bfd_boolean complete_p)
7710 struct mips_arg_info arg;
7711 const struct mips_operand *operand;
7714 imm_expr.X_op = O_absent;
7715 offset_expr.X_op = O_absent;
7716 offset_reloc[0] = BFD_RELOC_UNUSED;
7717 offset_reloc[1] = BFD_RELOC_UNUSED;
7718 offset_reloc[2] = BFD_RELOC_UNUSED;
7720 create_insn (insn, opcode);
7721 /* When no opcode suffix is specified, assume ".xyzw". */
7722 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7723 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7725 insn->insn_opcode |= opcode_extra;
7726 memset (&arg, 0, sizeof (arg));
7730 arg.last_regno = ILLEGAL_REG;
7731 arg.dest_regno = ILLEGAL_REG;
7732 arg.lax_match = lax_match;
7733 for (args = opcode->args;; ++args)
7735 if (arg.token->type == OT_END)
7737 /* Handle unary instructions in which only one operand is given.
7738 The source is then the same as the destination. */
7739 if (arg.opnum == 1 && *args == ',')
7741 operand = (mips_opts.micromips
7742 ? decode_micromips_operand (args + 1)
7743 : decode_mips_operand (args + 1));
7744 if (operand && mips_optional_operand_p (operand))
7752 /* Treat elided base registers as $0. */
7753 if (strcmp (args, "(b)") == 0)
7761 /* The register suffix is optional. */
7766 /* Fail the match if there were too few operands. */
7770 /* Successful match. */
7773 clear_insn_error ();
7774 if (arg.dest_regno == arg.last_regno
7775 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7779 (0, _("source and destination must be different"));
7780 else if (arg.last_regno == 31)
7782 (0, _("a destination register must be supplied"));
7784 else if (arg.last_regno == 31
7785 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7786 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7787 set_insn_error (0, _("the source register must not be $31"));
7788 check_completed_insn (&arg);
7792 /* Fail the match if the line has too many operands. */
7796 /* Handle characters that need to match exactly. */
7797 if (*args == '(' || *args == ')' || *args == ',')
7799 if (match_char (&arg, *args))
7806 if (arg.token->type == OT_DOUBLE_CHAR
7807 && arg.token->u.ch == *args)
7815 /* Handle special macro operands. Work out the properties of
7824 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7828 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7837 *offset_reloc = BFD_RELOC_MIPS_JMP;
7841 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7845 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7851 if (!match_const_int (&arg, &imm_expr.X_add_number))
7853 imm_expr.X_op = O_constant;
7855 normalize_constant_expr (&imm_expr);
7859 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7861 /* Assume that the offset has been elided and that what
7862 we saw was a base register. The match will fail later
7863 if that assumption turns out to be wrong. */
7864 offset_expr.X_op = O_constant;
7865 offset_expr.X_add_number = 0;
7869 if (!match_expression (&arg, &offset_expr, offset_reloc))
7871 normalize_address_expr (&offset_expr);
7876 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7882 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7888 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7894 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7900 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7904 *offset_reloc = BFD_RELOC_MIPS_JMP;
7908 gas_assert (mips_opts.micromips);
7914 if (!forced_insn_length)
7915 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7917 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7919 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7925 operand = (mips_opts.micromips
7926 ? decode_micromips_operand (args)
7927 : decode_mips_operand (args));
7931 /* Skip prefixes. */
7932 if (*args == '+' || *args == 'm' || *args == '-')
7935 if (mips_optional_operand_p (operand)
7937 && (arg.token[0].type != OT_REG
7938 || arg.token[1].type == OT_END))
7940 /* Assume that the register has been elided and is the
7941 same as the first operand. */
7946 if (!match_operand (&arg, operand))
7951 /* Like match_insn, but for MIPS16. */
7954 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7955 struct mips_operand_token *tokens)
7958 const struct mips_operand *operand;
7959 const struct mips_operand *ext_operand;
7960 struct mips_arg_info arg;
7963 create_insn (insn, opcode);
7964 imm_expr.X_op = O_absent;
7965 offset_expr.X_op = O_absent;
7966 offset_reloc[0] = BFD_RELOC_UNUSED;
7967 offset_reloc[1] = BFD_RELOC_UNUSED;
7968 offset_reloc[2] = BFD_RELOC_UNUSED;
7971 memset (&arg, 0, sizeof (arg));
7975 arg.last_regno = ILLEGAL_REG;
7976 arg.dest_regno = ILLEGAL_REG;
7978 for (args = opcode->args;; ++args)
7982 if (arg.token->type == OT_END)
7986 /* Handle unary instructions in which only one operand is given.
7987 The source is then the same as the destination. */
7988 if (arg.opnum == 1 && *args == ',')
7990 operand = decode_mips16_operand (args[1], FALSE);
7991 if (operand && mips_optional_operand_p (operand))
7999 /* Fail the match if there were too few operands. */
8003 /* Successful match. Stuff the immediate value in now, if
8005 clear_insn_error ();
8006 if (opcode->pinfo == INSN_MACRO)
8008 gas_assert (relax_char == 0 || relax_char == 'p');
8009 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8012 && offset_expr.X_op == O_constant
8013 && calculate_reloc (*offset_reloc,
8014 offset_expr.X_add_number,
8017 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8018 forced_insn_length, &insn->insn_opcode);
8019 offset_expr.X_op = O_absent;
8020 *offset_reloc = BFD_RELOC_UNUSED;
8022 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8024 if (forced_insn_length == 2)
8025 set_insn_error (0, _("invalid unextended operand value"));
8026 forced_insn_length = 4;
8027 insn->insn_opcode |= MIPS16_EXTEND;
8029 else if (relax_char)
8030 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8032 check_completed_insn (&arg);
8036 /* Fail the match if the line has too many operands. */
8040 /* Handle characters that need to match exactly. */
8041 if (*args == '(' || *args == ')' || *args == ',')
8043 if (match_char (&arg, *args))
8061 if (!match_const_int (&arg, &imm_expr.X_add_number))
8063 imm_expr.X_op = O_constant;
8065 normalize_constant_expr (&imm_expr);
8070 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8071 insn->insn_opcode <<= 16;
8075 operand = decode_mips16_operand (c, FALSE);
8079 /* '6' is a special case. It is used for BREAK and SDBBP,
8080 whose operands are only meaningful to the software that decodes
8081 them. This means that there is no architectural reason why
8082 they cannot be prefixed by EXTEND, but in practice,
8083 exception handlers will only look at the instruction
8084 itself. We therefore allow '6' to be extended when
8085 disassembling but not when assembling. */
8086 if (operand->type != OP_PCREL && c != '6')
8088 ext_operand = decode_mips16_operand (c, TRUE);
8089 if (operand != ext_operand)
8091 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8093 offset_expr.X_op = O_constant;
8094 offset_expr.X_add_number = 0;
8099 /* We need the OT_INTEGER check because some MIPS16
8100 immediate variants are listed before the register ones. */
8101 if (arg.token->type != OT_INTEGER
8102 || !match_expression (&arg, &offset_expr, offset_reloc))
8105 /* '8' is used for SLTI(U) and has traditionally not
8106 been allowed to take relocation operators. */
8107 if (offset_reloc[0] != BFD_RELOC_UNUSED
8108 && (ext_operand->size != 16 || c == '8'))
8116 if (mips_optional_operand_p (operand)
8118 && (arg.token[0].type != OT_REG
8119 || arg.token[1].type == OT_END))
8121 /* Assume that the register has been elided and is the
8122 same as the first operand. */
8127 if (!match_operand (&arg, operand))
8132 /* Record that the current instruction is invalid for the current ISA. */
8135 match_invalid_for_isa (void)
8138 (0, _("opcode not supported on this processor: %s (%s)"),
8139 mips_cpu_info_from_arch (mips_opts.arch)->name,
8140 mips_cpu_info_from_isa (mips_opts.isa)->name);
8143 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8144 Return true if a definite match or failure was found, storing any match
8145 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8146 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8147 tried and failed to match under normal conditions and now want to try a
8148 more relaxed match. */
8151 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8152 const struct mips_opcode *past, struct mips_operand_token *tokens,
8153 int opcode_extra, bfd_boolean lax_match)
8155 const struct mips_opcode *opcode;
8156 const struct mips_opcode *invalid_delay_slot;
8157 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8159 /* Search for a match, ignoring alternatives that don't satisfy the
8160 current ISA or forced_length. */
8161 invalid_delay_slot = 0;
8162 seen_valid_for_isa = FALSE;
8163 seen_valid_for_size = FALSE;
8167 gas_assert (strcmp (opcode->name, first->name) == 0);
8168 if (is_opcode_valid (opcode))
8170 seen_valid_for_isa = TRUE;
8171 if (is_size_valid (opcode))
8173 bfd_boolean delay_slot_ok;
8175 seen_valid_for_size = TRUE;
8176 delay_slot_ok = is_delay_slot_valid (opcode);
8177 if (match_insn (insn, opcode, tokens, opcode_extra,
8178 lax_match, delay_slot_ok))
8182 if (!invalid_delay_slot)
8183 invalid_delay_slot = opcode;
8192 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8194 /* If the only matches we found had the wrong length for the delay slot,
8195 pick the first such match. We'll issue an appropriate warning later. */
8196 if (invalid_delay_slot)
8198 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8204 /* Handle the case where we didn't try to match an instruction because
8205 all the alternatives were incompatible with the current ISA. */
8206 if (!seen_valid_for_isa)
8208 match_invalid_for_isa ();
8212 /* Handle the case where we didn't try to match an instruction because
8213 all the alternatives were of the wrong size. */
8214 if (!seen_valid_for_size)
8216 if (mips_opts.insn32)
8217 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8220 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8221 8 * forced_insn_length);
8228 /* Like match_insns, but for MIPS16. */
8231 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8232 struct mips_operand_token *tokens)
8234 const struct mips_opcode *opcode;
8235 bfd_boolean seen_valid_for_isa;
8237 /* Search for a match, ignoring alternatives that don't satisfy the
8238 current ISA. There are no separate entries for extended forms so
8239 we deal with forced_length later. */
8240 seen_valid_for_isa = FALSE;
8244 gas_assert (strcmp (opcode->name, first->name) == 0);
8245 if (is_opcode_valid_16 (opcode))
8247 seen_valid_for_isa = TRUE;
8248 if (match_mips16_insn (insn, opcode, tokens))
8253 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8254 && strcmp (opcode->name, first->name) == 0);
8256 /* Handle the case where we didn't try to match an instruction because
8257 all the alternatives were incompatible with the current ISA. */
8258 if (!seen_valid_for_isa)
8260 match_invalid_for_isa ();
8267 /* Set up global variables for the start of a new macro. */
8272 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8273 memset (&mips_macro_warning.first_insn_sizes, 0,
8274 sizeof (mips_macro_warning.first_insn_sizes));
8275 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8276 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8277 && delayed_branch_p (&history[0]));
8278 switch (history[0].insn_mo->pinfo2
8279 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8281 case INSN2_BRANCH_DELAY_32BIT:
8282 mips_macro_warning.delay_slot_length = 4;
8284 case INSN2_BRANCH_DELAY_16BIT:
8285 mips_macro_warning.delay_slot_length = 2;
8288 mips_macro_warning.delay_slot_length = 0;
8291 mips_macro_warning.first_frag = NULL;
8294 /* Given that a macro is longer than one instruction or of the wrong size,
8295 return the appropriate warning for it. Return null if no warning is
8296 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8297 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8298 and RELAX_NOMACRO. */
8301 macro_warning (relax_substateT subtype)
8303 if (subtype & RELAX_DELAY_SLOT)
8304 return _("macro instruction expanded into multiple instructions"
8305 " in a branch delay slot");
8306 else if (subtype & RELAX_NOMACRO)
8307 return _("macro instruction expanded into multiple instructions");
8308 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8309 | RELAX_DELAY_SLOT_SIZE_SECOND))
8310 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8311 ? _("macro instruction expanded into a wrong size instruction"
8312 " in a 16-bit branch delay slot")
8313 : _("macro instruction expanded into a wrong size instruction"
8314 " in a 32-bit branch delay slot"));
8319 /* Finish up a macro. Emit warnings as appropriate. */
8324 /* Relaxation warning flags. */
8325 relax_substateT subtype = 0;
8327 /* Check delay slot size requirements. */
8328 if (mips_macro_warning.delay_slot_length == 2)
8329 subtype |= RELAX_DELAY_SLOT_16BIT;
8330 if (mips_macro_warning.delay_slot_length != 0)
8332 if (mips_macro_warning.delay_slot_length
8333 != mips_macro_warning.first_insn_sizes[0])
8334 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8335 if (mips_macro_warning.delay_slot_length
8336 != mips_macro_warning.first_insn_sizes[1])
8337 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8340 /* Check instruction count requirements. */
8341 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8343 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8344 subtype |= RELAX_SECOND_LONGER;
8345 if (mips_opts.warn_about_macros)
8346 subtype |= RELAX_NOMACRO;
8347 if (mips_macro_warning.delay_slot_p)
8348 subtype |= RELAX_DELAY_SLOT;
8351 /* If both alternatives fail to fill a delay slot correctly,
8352 emit the warning now. */
8353 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8354 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8359 s = subtype & (RELAX_DELAY_SLOT_16BIT
8360 | RELAX_DELAY_SLOT_SIZE_FIRST
8361 | RELAX_DELAY_SLOT_SIZE_SECOND);
8362 msg = macro_warning (s);
8364 as_warn ("%s", msg);
8368 /* If both implementations are longer than 1 instruction, then emit the
8370 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8375 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8376 msg = macro_warning (s);
8378 as_warn ("%s", msg);
8382 /* If any flags still set, then one implementation might need a warning
8383 and the other either will need one of a different kind or none at all.
8384 Pass any remaining flags over to relaxation. */
8385 if (mips_macro_warning.first_frag != NULL)
8386 mips_macro_warning.first_frag->fr_subtype |= subtype;
8389 /* Instruction operand formats used in macros that vary between
8390 standard MIPS and microMIPS code. */
8392 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8393 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8394 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8395 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8396 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8397 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8398 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8399 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8401 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8402 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8403 : cop12_fmt[mips_opts.micromips])
8404 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8405 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8406 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8407 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8408 : mem12_fmt[mips_opts.micromips])
8409 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8410 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8411 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8413 /* Read a macro's relocation codes from *ARGS and store them in *R.
8414 The first argument in *ARGS will be either the code for a single
8415 relocation or -1 followed by the three codes that make up a
8416 composite relocation. */
8419 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8423 next = va_arg (*args, int);
8425 r[0] = (bfd_reloc_code_real_type) next;
8428 for (i = 0; i < 3; i++)
8429 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8430 /* This function is only used for 16-bit relocation fields.
8431 To make the macro code simpler, treat an unrelocated value
8432 in the same way as BFD_RELOC_LO16. */
8433 if (r[0] == BFD_RELOC_UNUSED)
8434 r[0] = BFD_RELOC_LO16;
8438 /* Build an instruction created by a macro expansion. This is passed
8439 a pointer to the count of instructions created so far, an
8440 expression, the name of the instruction to build, an operand format
8441 string, and corresponding arguments. */
8444 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8446 const struct mips_opcode *mo = NULL;
8447 bfd_reloc_code_real_type r[3];
8448 const struct mips_opcode *amo;
8449 const struct mips_operand *operand;
8450 struct hash_control *hash;
8451 struct mips_cl_insn insn;
8455 va_start (args, fmt);
8457 if (mips_opts.mips16)
8459 mips16_macro_build (ep, name, fmt, &args);
8464 r[0] = BFD_RELOC_UNUSED;
8465 r[1] = BFD_RELOC_UNUSED;
8466 r[2] = BFD_RELOC_UNUSED;
8467 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8468 amo = (struct mips_opcode *) hash_find (hash, name);
8470 gas_assert (strcmp (name, amo->name) == 0);
8474 /* Search until we get a match for NAME. It is assumed here that
8475 macros will never generate MDMX, MIPS-3D, or MT instructions.
8476 We try to match an instruction that fulfils the branch delay
8477 slot instruction length requirement (if any) of the previous
8478 instruction. While doing this we record the first instruction
8479 seen that matches all the other conditions and use it anyway
8480 if the requirement cannot be met; we will issue an appropriate
8481 warning later on. */
8482 if (strcmp (fmt, amo->args) == 0
8483 && amo->pinfo != INSN_MACRO
8484 && is_opcode_valid (amo)
8485 && is_size_valid (amo))
8487 if (is_delay_slot_valid (amo))
8497 gas_assert (amo->name);
8499 while (strcmp (name, amo->name) == 0);
8502 create_insn (&insn, mo);
8515 macro_read_relocs (&args, r);
8516 gas_assert (*r == BFD_RELOC_GPREL16
8517 || *r == BFD_RELOC_MIPS_HIGHER
8518 || *r == BFD_RELOC_HI16_S
8519 || *r == BFD_RELOC_LO16
8520 || *r == BFD_RELOC_MIPS_GOT_OFST);
8524 macro_read_relocs (&args, r);
8528 macro_read_relocs (&args, r);
8529 gas_assert (ep != NULL
8530 && (ep->X_op == O_constant
8531 || (ep->X_op == O_symbol
8532 && (*r == BFD_RELOC_MIPS_HIGHEST
8533 || *r == BFD_RELOC_HI16_S
8534 || *r == BFD_RELOC_HI16
8535 || *r == BFD_RELOC_GPREL16
8536 || *r == BFD_RELOC_MIPS_GOT_HI16
8537 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8541 gas_assert (ep != NULL);
8544 * This allows macro() to pass an immediate expression for
8545 * creating short branches without creating a symbol.
8547 * We don't allow branch relaxation for these branches, as
8548 * they should only appear in ".set nomacro" anyway.
8550 if (ep->X_op == O_constant)
8552 /* For microMIPS we always use relocations for branches.
8553 So we should not resolve immediate values. */
8554 gas_assert (!mips_opts.micromips);
8556 if ((ep->X_add_number & 3) != 0)
8557 as_bad (_("branch to misaligned address (0x%lx)"),
8558 (unsigned long) ep->X_add_number);
8559 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8560 as_bad (_("branch address range overflow (0x%lx)"),
8561 (unsigned long) ep->X_add_number);
8562 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8566 *r = BFD_RELOC_16_PCREL_S2;
8570 gas_assert (ep != NULL);
8571 *r = BFD_RELOC_MIPS_JMP;
8575 operand = (mips_opts.micromips
8576 ? decode_micromips_operand (fmt)
8577 : decode_mips_operand (fmt));
8581 uval = va_arg (args, int);
8582 if (operand->type == OP_CLO_CLZ_DEST)
8583 uval |= (uval << 5);
8584 insn_insert_operand (&insn, operand, uval);
8586 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8592 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8594 append_insn (&insn, ep, r, TRUE);
8598 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8601 struct mips_opcode *mo;
8602 struct mips_cl_insn insn;
8603 const struct mips_operand *operand;
8604 bfd_reloc_code_real_type r[3]
8605 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8607 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8609 gas_assert (strcmp (name, mo->name) == 0);
8611 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8614 gas_assert (mo->name);
8615 gas_assert (strcmp (name, mo->name) == 0);
8618 create_insn (&insn, mo);
8656 gas_assert (ep != NULL);
8658 if (ep->X_op != O_constant)
8659 *r = (int) BFD_RELOC_UNUSED + c;
8660 else if (calculate_reloc (*r, ep->X_add_number, &value))
8662 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8664 *r = BFD_RELOC_UNUSED;
8670 operand = decode_mips16_operand (c, FALSE);
8674 insn_insert_operand (&insn, operand, va_arg (*args, int));
8679 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8681 append_insn (&insn, ep, r, TRUE);
8685 * Generate a "jalr" instruction with a relocation hint to the called
8686 * function. This occurs in NewABI PIC code.
8689 macro_build_jalr (expressionS *ep, int cprestore)
8691 static const bfd_reloc_code_real_type jalr_relocs[2]
8692 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8693 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8697 if (MIPS_JALR_HINT_P (ep))
8702 if (mips_opts.micromips)
8704 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8705 ? "jalr" : "jalrs");
8706 if (MIPS_JALR_HINT_P (ep)
8708 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8709 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8711 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8714 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
8715 if (MIPS_JALR_HINT_P (ep))
8716 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
8720 * Generate a "lui" instruction.
8723 macro_build_lui (expressionS *ep, int regnum)
8725 gas_assert (! mips_opts.mips16);
8727 if (ep->X_op != O_constant)
8729 gas_assert (ep->X_op == O_symbol);
8730 /* _gp_disp is a special case, used from s_cpload.
8731 __gnu_local_gp is used if mips_no_shared. */
8732 gas_assert (mips_pic == NO_PIC
8734 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8735 || (! mips_in_shared
8736 && strcmp (S_GET_NAME (ep->X_add_symbol),
8737 "__gnu_local_gp") == 0));
8740 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
8743 /* Generate a sequence of instructions to do a load or store from a constant
8744 offset off of a base register (breg) into/from a target register (treg),
8745 using AT if necessary. */
8747 macro_build_ldst_constoffset (expressionS *ep, const char *op,
8748 int treg, int breg, int dbl)
8750 gas_assert (ep->X_op == O_constant);
8752 /* Sign-extending 32-bit constants makes their handling easier. */
8754 normalize_constant_expr (ep);
8756 /* Right now, this routine can only handle signed 32-bit constants. */
8757 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
8758 as_warn (_("operand overflow"));
8760 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8762 /* Signed 16-bit offset will fit in the op. Easy! */
8763 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8767 /* 32-bit offset, need multiple instructions and AT, like:
8768 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8769 addu $tempreg,$tempreg,$breg
8770 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8771 to handle the complete offset. */
8772 macro_build_lui (ep, AT);
8773 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8774 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8777 as_bad (_("macro used $at after \".set noat\""));
8782 * Generates code to set the $at register to true (one)
8783 * if reg is less than the immediate expression.
8786 set_at (int reg, int unsignedp)
8788 if (imm_expr.X_add_number >= -0x8000
8789 && imm_expr.X_add_number < 0x8000)
8790 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8791 AT, reg, BFD_RELOC_LO16);
8794 load_register (AT, &imm_expr, GPR_SIZE == 64);
8795 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8799 /* Count the leading zeroes by performing a binary chop. This is a
8800 bulky bit of source, but performance is a LOT better for the
8801 majority of values than a simple loop to count the bits:
8802 for (lcnt = 0; (lcnt < 32); lcnt++)
8803 if ((v) & (1 << (31 - lcnt)))
8805 However it is not code size friendly, and the gain will drop a bit
8806 on certain cached systems.
8808 #define COUNT_TOP_ZEROES(v) \
8809 (((v) & ~0xffff) == 0 \
8810 ? ((v) & ~0xff) == 0 \
8811 ? ((v) & ~0xf) == 0 \
8812 ? ((v) & ~0x3) == 0 \
8813 ? ((v) & ~0x1) == 0 \
8818 : ((v) & ~0x7) == 0 \
8821 : ((v) & ~0x3f) == 0 \
8822 ? ((v) & ~0x1f) == 0 \
8825 : ((v) & ~0x7f) == 0 \
8828 : ((v) & ~0xfff) == 0 \
8829 ? ((v) & ~0x3ff) == 0 \
8830 ? ((v) & ~0x1ff) == 0 \
8833 : ((v) & ~0x7ff) == 0 \
8836 : ((v) & ~0x3fff) == 0 \
8837 ? ((v) & ~0x1fff) == 0 \
8840 : ((v) & ~0x7fff) == 0 \
8843 : ((v) & ~0xffffff) == 0 \
8844 ? ((v) & ~0xfffff) == 0 \
8845 ? ((v) & ~0x3ffff) == 0 \
8846 ? ((v) & ~0x1ffff) == 0 \
8849 : ((v) & ~0x7ffff) == 0 \
8852 : ((v) & ~0x3fffff) == 0 \
8853 ? ((v) & ~0x1fffff) == 0 \
8856 : ((v) & ~0x7fffff) == 0 \
8859 : ((v) & ~0xfffffff) == 0 \
8860 ? ((v) & ~0x3ffffff) == 0 \
8861 ? ((v) & ~0x1ffffff) == 0 \
8864 : ((v) & ~0x7ffffff) == 0 \
8867 : ((v) & ~0x3fffffff) == 0 \
8868 ? ((v) & ~0x1fffffff) == 0 \
8871 : ((v) & ~0x7fffffff) == 0 \
8876 * This routine generates the least number of instructions necessary to load
8877 * an absolute expression value into a register.
8880 load_register (int reg, expressionS *ep, int dbl)
8883 expressionS hi32, lo32;
8885 if (ep->X_op != O_big)
8887 gas_assert (ep->X_op == O_constant);
8889 /* Sign-extending 32-bit constants makes their handling easier. */
8891 normalize_constant_expr (ep);
8893 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8895 /* We can handle 16 bit signed values with an addiu to
8896 $zero. No need to ever use daddiu here, since $zero and
8897 the result are always correct in 32 bit mode. */
8898 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8901 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8903 /* We can handle 16 bit unsigned values with an ori to
8905 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8908 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8910 /* 32 bit values require an lui. */
8911 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8912 if ((ep->X_add_number & 0xffff) != 0)
8913 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8918 /* The value is larger than 32 bits. */
8920 if (!dbl || GPR_SIZE == 32)
8924 sprintf_vma (value, ep->X_add_number);
8925 as_bad (_("number (0x%s) larger than 32 bits"), value);
8926 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8930 if (ep->X_op != O_big)
8933 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8934 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8935 hi32.X_add_number &= 0xffffffff;
8937 lo32.X_add_number &= 0xffffffff;
8941 gas_assert (ep->X_add_number > 2);
8942 if (ep->X_add_number == 3)
8943 generic_bignum[3] = 0;
8944 else if (ep->X_add_number > 4)
8945 as_bad (_("number larger than 64 bits"));
8946 lo32.X_op = O_constant;
8947 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8948 hi32.X_op = O_constant;
8949 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8952 if (hi32.X_add_number == 0)
8957 unsigned long hi, lo;
8959 if (hi32.X_add_number == (offsetT) 0xffffffff)
8961 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8963 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8966 if (lo32.X_add_number & 0x80000000)
8968 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8969 if (lo32.X_add_number & 0xffff)
8970 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8975 /* Check for 16bit shifted constant. We know that hi32 is
8976 non-zero, so start the mask on the first bit of the hi32
8981 unsigned long himask, lomask;
8985 himask = 0xffff >> (32 - shift);
8986 lomask = (0xffff << shift) & 0xffffffff;
8990 himask = 0xffff << (shift - 32);
8993 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8994 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8998 tmp.X_op = O_constant;
9000 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9001 | (lo32.X_add_number >> shift));
9003 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
9004 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9005 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9006 reg, reg, (shift >= 32) ? shift - 32 : shift);
9011 while (shift <= (64 - 16));
9013 /* Find the bit number of the lowest one bit, and store the
9014 shifted value in hi/lo. */
9015 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9016 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9020 while ((lo & 1) == 0)
9025 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9031 while ((hi & 1) == 0)
9040 /* Optimize if the shifted value is a (power of 2) - 1. */
9041 if ((hi == 0 && ((lo + 1) & lo) == 0)
9042 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9044 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9049 /* This instruction will set the register to be all
9051 tmp.X_op = O_constant;
9052 tmp.X_add_number = (offsetT) -1;
9053 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9057 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9058 reg, reg, (bit >= 32) ? bit - 32 : bit);
9060 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9061 reg, reg, (shift >= 32) ? shift - 32 : shift);
9066 /* Sign extend hi32 before calling load_register, because we can
9067 generally get better code when we load a sign extended value. */
9068 if ((hi32.X_add_number & 0x80000000) != 0)
9069 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9070 load_register (reg, &hi32, 0);
9073 if ((lo32.X_add_number & 0xffff0000) == 0)
9077 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9085 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9087 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9088 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9094 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9098 mid16.X_add_number >>= 16;
9099 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9100 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9103 if ((lo32.X_add_number & 0xffff) != 0)
9104 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9108 load_delay_nop (void)
9110 if (!gpr_interlocks)
9111 macro_build (NULL, "nop", "");
9114 /* Load an address into a register. */
9117 load_address (int reg, expressionS *ep, int *used_at)
9119 if (ep->X_op != O_constant
9120 && ep->X_op != O_symbol)
9122 as_bad (_("expression too complex"));
9123 ep->X_op = O_constant;
9126 if (ep->X_op == O_constant)
9128 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9132 if (mips_pic == NO_PIC)
9134 /* If this is a reference to a GP relative symbol, we want
9135 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9137 lui $reg,<sym> (BFD_RELOC_HI16_S)
9138 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9139 If we have an addend, we always use the latter form.
9141 With 64bit address space and a usable $at we want
9142 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9143 lui $at,<sym> (BFD_RELOC_HI16_S)
9144 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9145 daddiu $at,<sym> (BFD_RELOC_LO16)
9149 If $at is already in use, we use a path which is suboptimal
9150 on superscalar processors.
9151 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9152 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9154 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9156 daddiu $reg,<sym> (BFD_RELOC_LO16)
9158 For GP relative symbols in 64bit address space we can use
9159 the same sequence as in 32bit address space. */
9160 if (HAVE_64BIT_SYMBOLS)
9162 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9163 && !nopic_need_relax (ep->X_add_symbol, 1))
9165 relax_start (ep->X_add_symbol);
9166 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9167 mips_gp_register, BFD_RELOC_GPREL16);
9171 if (*used_at == 0 && mips_opts.at)
9173 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9174 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9175 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9176 BFD_RELOC_MIPS_HIGHER);
9177 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9178 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9179 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9184 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9185 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9186 BFD_RELOC_MIPS_HIGHER);
9187 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9188 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9189 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9190 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9193 if (mips_relax.sequence)
9198 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9199 && !nopic_need_relax (ep->X_add_symbol, 1))
9201 relax_start (ep->X_add_symbol);
9202 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9203 mips_gp_register, BFD_RELOC_GPREL16);
9206 macro_build_lui (ep, reg);
9207 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9208 reg, reg, BFD_RELOC_LO16);
9209 if (mips_relax.sequence)
9213 else if (!mips_big_got)
9217 /* If this is a reference to an external symbol, we want
9218 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9220 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9222 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9223 If there is a constant, it must be added in after.
9225 If we have NewABI, we want
9226 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9227 unless we're referencing a global symbol with a non-zero
9228 offset, in which case cst must be added separately. */
9231 if (ep->X_add_number)
9233 ex.X_add_number = ep->X_add_number;
9234 ep->X_add_number = 0;
9235 relax_start (ep->X_add_symbol);
9236 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9237 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9238 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9239 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9240 ex.X_op = O_constant;
9241 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9242 reg, reg, BFD_RELOC_LO16);
9243 ep->X_add_number = ex.X_add_number;
9246 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9247 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9248 if (mips_relax.sequence)
9253 ex.X_add_number = ep->X_add_number;
9254 ep->X_add_number = 0;
9255 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9256 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9258 relax_start (ep->X_add_symbol);
9260 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9264 if (ex.X_add_number != 0)
9266 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9267 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9268 ex.X_op = O_constant;
9269 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9270 reg, reg, BFD_RELOC_LO16);
9274 else if (mips_big_got)
9278 /* This is the large GOT case. If this is a reference to an
9279 external symbol, we want
9280 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9282 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9284 Otherwise, for a reference to a local symbol in old ABI, we want
9285 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9287 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9288 If there is a constant, it must be added in after.
9290 In the NewABI, for local symbols, with or without offsets, we want:
9291 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9292 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9296 ex.X_add_number = ep->X_add_number;
9297 ep->X_add_number = 0;
9298 relax_start (ep->X_add_symbol);
9299 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9300 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9301 reg, reg, mips_gp_register);
9302 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9303 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9304 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9305 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9306 else if (ex.X_add_number)
9308 ex.X_op = O_constant;
9309 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9313 ep->X_add_number = ex.X_add_number;
9315 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9316 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9317 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9318 BFD_RELOC_MIPS_GOT_OFST);
9323 ex.X_add_number = ep->X_add_number;
9324 ep->X_add_number = 0;
9325 relax_start (ep->X_add_symbol);
9326 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9328 reg, reg, mips_gp_register);
9329 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9330 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9332 if (reg_needs_delay (mips_gp_register))
9334 /* We need a nop before loading from $gp. This special
9335 check is required because the lui which starts the main
9336 instruction stream does not refer to $gp, and so will not
9337 insert the nop which may be required. */
9338 macro_build (NULL, "nop", "");
9340 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9341 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9343 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9347 if (ex.X_add_number != 0)
9349 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9350 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9351 ex.X_op = O_constant;
9352 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9360 if (!mips_opts.at && *used_at == 1)
9361 as_bad (_("macro used $at after \".set noat\""));
9364 /* Move the contents of register SOURCE into register DEST. */
9367 move_register (int dest, int source)
9369 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9370 instruction specifically requires a 32-bit one. */
9371 if (mips_opts.micromips
9372 && !mips_opts.insn32
9373 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9374 macro_build (NULL, "move", "mp,mj", dest, source);
9376 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9379 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9380 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9381 The two alternatives are:
9383 Global symbol Local sybmol
9384 ------------- ------------
9385 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9387 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9389 load_got_offset emits the first instruction and add_got_offset
9390 emits the second for a 16-bit offset or add_got_offset_hilo emits
9391 a sequence to add a 32-bit offset using a scratch register. */
9394 load_got_offset (int dest, expressionS *local)
9399 global.X_add_number = 0;
9401 relax_start (local->X_add_symbol);
9402 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9403 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9405 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9406 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9411 add_got_offset (int dest, expressionS *local)
9415 global.X_op = O_constant;
9416 global.X_op_symbol = NULL;
9417 global.X_add_symbol = NULL;
9418 global.X_add_number = local->X_add_number;
9420 relax_start (local->X_add_symbol);
9421 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9422 dest, dest, BFD_RELOC_LO16);
9424 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9429 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9432 int hold_mips_optimize;
9434 global.X_op = O_constant;
9435 global.X_op_symbol = NULL;
9436 global.X_add_symbol = NULL;
9437 global.X_add_number = local->X_add_number;
9439 relax_start (local->X_add_symbol);
9440 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9442 /* Set mips_optimize around the lui instruction to avoid
9443 inserting an unnecessary nop after the lw. */
9444 hold_mips_optimize = mips_optimize;
9446 macro_build_lui (&global, tmp);
9447 mips_optimize = hold_mips_optimize;
9448 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9451 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9454 /* Emit a sequence of instructions to emulate a branch likely operation.
9455 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9456 is its complementing branch with the original condition negated.
9457 CALL is set if the original branch specified the link operation.
9458 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9460 Code like this is produced in the noreorder mode:
9465 delay slot (executed only if branch taken)
9473 delay slot (executed only if branch taken)
9476 In the reorder mode the delay slot would be filled with a nop anyway,
9477 so code produced is simply:
9482 This function is used when producing code for the microMIPS ASE that
9483 does not implement branch likely instructions in hardware. */
9486 macro_build_branch_likely (const char *br, const char *brneg,
9487 int call, expressionS *ep, const char *fmt,
9488 unsigned int sreg, unsigned int treg)
9490 int noreorder = mips_opts.noreorder;
9493 gas_assert (mips_opts.micromips);
9497 micromips_label_expr (&expr1);
9498 macro_build (&expr1, brneg, fmt, sreg, treg);
9499 macro_build (NULL, "nop", "");
9500 macro_build (ep, call ? "bal" : "b", "p");
9502 /* Set to true so that append_insn adds a label. */
9503 emit_branch_likely_macro = TRUE;
9507 macro_build (ep, br, fmt, sreg, treg);
9508 macro_build (NULL, "nop", "");
9513 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9514 the condition code tested. EP specifies the branch target. */
9517 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9544 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9547 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9548 the register tested. EP specifies the branch target. */
9551 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9553 const char *brneg = NULL;
9563 br = mips_opts.micromips ? "bgez" : "bgezl";
9567 gas_assert (mips_opts.micromips);
9568 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9576 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9583 br = mips_opts.micromips ? "blez" : "blezl";
9590 br = mips_opts.micromips ? "bltz" : "bltzl";
9594 gas_assert (mips_opts.micromips);
9595 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9602 if (mips_opts.micromips && brneg)
9603 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9605 macro_build (ep, br, "s,p", sreg);
9608 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9609 TREG as the registers tested. EP specifies the branch target. */
9612 macro_build_branch_rsrt (int type, expressionS *ep,
9613 unsigned int sreg, unsigned int treg)
9615 const char *brneg = NULL;
9627 br = mips_opts.micromips ? "beq" : "beql";
9636 br = mips_opts.micromips ? "bne" : "bnel";
9642 if (mips_opts.micromips && brneg)
9643 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9645 macro_build (ep, br, "s,t,p", sreg, treg);
9648 /* Return the high part that should be loaded in order to make the low
9649 part of VALUE accessible using an offset of OFFBITS bits. */
9652 offset_high_part (offsetT value, unsigned int offbits)
9659 bias = 1 << (offbits - 1);
9660 low_mask = bias * 2 - 1;
9661 return (value + bias) & ~low_mask;
9664 /* Return true if the value stored in offset_expr and offset_reloc
9665 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9666 amount that the caller wants to add without inducing overflow
9667 and ALIGN is the known alignment of the value in bytes. */
9670 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9674 /* Accept any relocation operator if overflow isn't a concern. */
9675 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9678 /* These relocations are guaranteed not to overflow in correct links. */
9679 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9680 || gprel16_reloc_p (*offset_reloc))
9683 if (offset_expr.X_op == O_constant
9684 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9685 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9692 * This routine implements the seemingly endless macro or synthesized
9693 * instructions and addressing modes in the mips assembly language. Many
9694 * of these macros are simple and are similar to each other. These could
9695 * probably be handled by some kind of table or grammar approach instead of
9696 * this verbose method. Others are not simple macros but are more like
9697 * optimizing code generation.
9698 * One interesting optimization is when several store macros appear
9699 * consecutively that would load AT with the upper half of the same address.
9700 * The ensuing load upper instructions are ommited. This implies some kind
9701 * of global optimization. We currently only optimize within a single macro.
9702 * For many of the load and store macros if the address is specified as a
9703 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9704 * first load register 'at' with zero and use it as the base register. The
9705 * mips assembler simply uses register $zero. Just one tiny optimization
9709 macro (struct mips_cl_insn *ip, char *str)
9711 const struct mips_operand_array *operands;
9712 unsigned int breg, i;
9713 unsigned int tempreg;
9716 expressionS label_expr;
9731 bfd_boolean large_offset;
9733 int hold_mips_optimize;
9735 unsigned int op[MAX_OPERANDS];
9737 gas_assert (! mips_opts.mips16);
9739 operands = insn_operands (ip);
9740 for (i = 0; i < MAX_OPERANDS; i++)
9741 if (operands->operand[i])
9742 op[i] = insn_extract_operand (ip, operands->operand[i]);
9746 mask = ip->insn_mo->mask;
9748 label_expr.X_op = O_constant;
9749 label_expr.X_op_symbol = NULL;
9750 label_expr.X_add_symbol = NULL;
9751 label_expr.X_add_number = 0;
9753 expr1.X_op = O_constant;
9754 expr1.X_op_symbol = NULL;
9755 expr1.X_add_symbol = NULL;
9756 expr1.X_add_number = 1;
9772 if (mips_opts.micromips)
9773 micromips_label_expr (&label_expr);
9775 label_expr.X_add_number = 8;
9776 macro_build (&label_expr, "bgez", "s,p", op[1]);
9778 macro_build (NULL, "nop", "");
9780 move_register (op[0], op[1]);
9781 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
9782 if (mips_opts.micromips)
9783 micromips_add_label ();
9800 if (!mips_opts.micromips)
9802 if (imm_expr.X_add_number >= -0x200
9803 && imm_expr.X_add_number < 0x200)
9805 macro_build (NULL, s, "t,r,.", op[0], op[1],
9806 (int) imm_expr.X_add_number);
9815 if (imm_expr.X_add_number >= -0x8000
9816 && imm_expr.X_add_number < 0x8000)
9818 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9823 load_register (AT, &imm_expr, dbl);
9824 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9843 if (imm_expr.X_add_number >= 0
9844 && imm_expr.X_add_number < 0x10000)
9846 if (mask != M_NOR_I)
9847 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9850 macro_build (&imm_expr, "ori", "t,r,i",
9851 op[0], op[1], BFD_RELOC_LO16);
9852 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9858 load_register (AT, &imm_expr, GPR_SIZE == 64);
9859 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9863 switch (imm_expr.X_add_number)
9866 macro_build (NULL, "nop", "");
9869 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9873 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9874 (int) imm_expr.X_add_number);
9877 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9878 (unsigned long) imm_expr.X_add_number);
9887 gas_assert (mips_opts.micromips);
9888 macro_build_branch_ccl (mask, &offset_expr,
9889 EXTRACT_OPERAND (1, BCC, *ip));
9896 if (imm_expr.X_add_number == 0)
9902 load_register (op[1], &imm_expr, GPR_SIZE == 64);
9907 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9914 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9915 else if (op[0] == 0)
9916 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9920 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9921 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9922 &offset_expr, AT, ZERO);
9932 macro_build_branch_rs (mask, &offset_expr, op[0]);
9938 /* Check for > max integer. */
9939 if (imm_expr.X_add_number >= GPR_SMAX)
9942 /* Result is always false. */
9944 macro_build (NULL, "nop", "");
9946 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9949 ++imm_expr.X_add_number;
9953 if (mask == M_BGEL_I)
9955 if (imm_expr.X_add_number == 0)
9957 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9958 &offset_expr, op[0]);
9961 if (imm_expr.X_add_number == 1)
9963 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9964 &offset_expr, op[0]);
9967 if (imm_expr.X_add_number <= GPR_SMIN)
9970 /* result is always true */
9971 as_warn (_("branch %s is always true"), ip->insn_mo->name);
9972 macro_build (&offset_expr, "b", "p");
9977 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9978 &offset_expr, AT, ZERO);
9986 else if (op[0] == 0)
9987 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9988 &offset_expr, ZERO, op[1]);
9992 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9993 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9994 &offset_expr, AT, ZERO);
10003 && imm_expr.X_add_number == -1))
10005 ++imm_expr.X_add_number;
10009 if (mask == M_BGEUL_I)
10011 if (imm_expr.X_add_number == 0)
10013 else if (imm_expr.X_add_number == 1)
10014 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10015 &offset_expr, op[0], ZERO);
10020 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10021 &offset_expr, AT, ZERO);
10029 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10030 else if (op[0] == 0)
10031 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10035 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10036 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10037 &offset_expr, AT, ZERO);
10045 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10046 &offset_expr, op[0], ZERO);
10047 else if (op[0] == 0)
10052 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10053 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10054 &offset_expr, AT, ZERO);
10062 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10063 else if (op[0] == 0)
10064 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10068 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10069 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10070 &offset_expr, AT, ZERO);
10077 if (imm_expr.X_add_number >= GPR_SMAX)
10079 ++imm_expr.X_add_number;
10083 if (mask == M_BLTL_I)
10085 if (imm_expr.X_add_number == 0)
10086 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10087 else if (imm_expr.X_add_number == 1)
10088 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10093 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10094 &offset_expr, AT, ZERO);
10102 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10103 &offset_expr, op[0], ZERO);
10104 else if (op[0] == 0)
10109 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10110 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10111 &offset_expr, AT, ZERO);
10120 && imm_expr.X_add_number == -1))
10122 ++imm_expr.X_add_number;
10126 if (mask == M_BLTUL_I)
10128 if (imm_expr.X_add_number == 0)
10130 else if (imm_expr.X_add_number == 1)
10131 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10132 &offset_expr, op[0], ZERO);
10137 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10138 &offset_expr, AT, ZERO);
10146 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10147 else if (op[0] == 0)
10148 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10152 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10153 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10154 &offset_expr, AT, ZERO);
10163 else if (op[0] == 0)
10164 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10165 &offset_expr, ZERO, op[1]);
10169 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10170 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10171 &offset_expr, AT, ZERO);
10187 as_warn (_("divide by zero"));
10189 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10191 macro_build (NULL, "break", BRK_FMT, 7);
10195 start_noreorder ();
10198 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10199 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10203 if (mips_opts.micromips)
10204 micromips_label_expr (&label_expr);
10206 label_expr.X_add_number = 8;
10207 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10208 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10209 macro_build (NULL, "break", BRK_FMT, 7);
10210 if (mips_opts.micromips)
10211 micromips_add_label ();
10213 expr1.X_add_number = -1;
10215 load_register (AT, &expr1, dbl);
10216 if (mips_opts.micromips)
10217 micromips_label_expr (&label_expr);
10219 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10220 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10223 expr1.X_add_number = 1;
10224 load_register (AT, &expr1, dbl);
10225 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10229 expr1.X_add_number = 0x80000000;
10230 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10234 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10235 /* We want to close the noreorder block as soon as possible, so
10236 that later insns are available for delay slot filling. */
10241 if (mips_opts.micromips)
10242 micromips_label_expr (&label_expr);
10244 label_expr.X_add_number = 8;
10245 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10246 macro_build (NULL, "nop", "");
10248 /* We want to close the noreorder block as soon as possible, so
10249 that later insns are available for delay slot filling. */
10252 macro_build (NULL, "break", BRK_FMT, 6);
10254 if (mips_opts.micromips)
10255 micromips_add_label ();
10256 macro_build (NULL, s, MFHL_FMT, op[0]);
10295 if (imm_expr.X_add_number == 0)
10297 as_warn (_("divide by zero"));
10299 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10301 macro_build (NULL, "break", BRK_FMT, 7);
10304 if (imm_expr.X_add_number == 1)
10306 if (strcmp (s2, "mflo") == 0)
10307 move_register (op[0], op[1]);
10309 move_register (op[0], ZERO);
10312 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10314 if (strcmp (s2, "mflo") == 0)
10315 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10317 move_register (op[0], ZERO);
10322 load_register (AT, &imm_expr, dbl);
10323 macro_build (NULL, s, "z,s,t", op[1], AT);
10324 macro_build (NULL, s2, MFHL_FMT, op[0]);
10343 start_noreorder ();
10346 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10347 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10348 /* We want to close the noreorder block as soon as possible, so
10349 that later insns are available for delay slot filling. */
10354 if (mips_opts.micromips)
10355 micromips_label_expr (&label_expr);
10357 label_expr.X_add_number = 8;
10358 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10359 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10361 /* We want to close the noreorder block as soon as possible, so
10362 that later insns are available for delay slot filling. */
10364 macro_build (NULL, "break", BRK_FMT, 7);
10365 if (mips_opts.micromips)
10366 micromips_add_label ();
10368 macro_build (NULL, s2, MFHL_FMT, op[0]);
10380 /* Load the address of a symbol into a register. If breg is not
10381 zero, we then add a base register to it. */
10384 if (dbl && GPR_SIZE == 32)
10385 as_warn (_("dla used to load 32-bit register; recommend using la "
10388 if (!dbl && HAVE_64BIT_OBJECTS)
10389 as_warn (_("la used to load 64-bit address; recommend using dla "
10392 if (small_offset_p (0, align, 16))
10394 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10395 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10399 if (mips_opts.at && (op[0] == breg))
10407 if (offset_expr.X_op != O_symbol
10408 && offset_expr.X_op != O_constant)
10410 as_bad (_("expression too complex"));
10411 offset_expr.X_op = O_constant;
10414 if (offset_expr.X_op == O_constant)
10415 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10416 else if (mips_pic == NO_PIC)
10418 /* If this is a reference to a GP relative symbol, we want
10419 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10421 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10422 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10423 If we have a constant, we need two instructions anyhow,
10424 so we may as well always use the latter form.
10426 With 64bit address space and a usable $at we want
10427 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10428 lui $at,<sym> (BFD_RELOC_HI16_S)
10429 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10430 daddiu $at,<sym> (BFD_RELOC_LO16)
10432 daddu $tempreg,$tempreg,$at
10434 If $at is already in use, we use a path which is suboptimal
10435 on superscalar processors.
10436 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10437 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10439 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10441 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10443 For GP relative symbols in 64bit address space we can use
10444 the same sequence as in 32bit address space. */
10445 if (HAVE_64BIT_SYMBOLS)
10447 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10448 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10450 relax_start (offset_expr.X_add_symbol);
10451 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10452 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10456 if (used_at == 0 && mips_opts.at)
10458 macro_build (&offset_expr, "lui", LUI_FMT,
10459 tempreg, BFD_RELOC_MIPS_HIGHEST);
10460 macro_build (&offset_expr, "lui", LUI_FMT,
10461 AT, BFD_RELOC_HI16_S);
10462 macro_build (&offset_expr, "daddiu", "t,r,j",
10463 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10464 macro_build (&offset_expr, "daddiu", "t,r,j",
10465 AT, AT, BFD_RELOC_LO16);
10466 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10467 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10472 macro_build (&offset_expr, "lui", LUI_FMT,
10473 tempreg, BFD_RELOC_MIPS_HIGHEST);
10474 macro_build (&offset_expr, "daddiu", "t,r,j",
10475 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10476 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10477 macro_build (&offset_expr, "daddiu", "t,r,j",
10478 tempreg, tempreg, BFD_RELOC_HI16_S);
10479 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10480 macro_build (&offset_expr, "daddiu", "t,r,j",
10481 tempreg, tempreg, BFD_RELOC_LO16);
10484 if (mips_relax.sequence)
10489 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10490 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10492 relax_start (offset_expr.X_add_symbol);
10493 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10494 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10497 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10498 as_bad (_("offset too large"));
10499 macro_build_lui (&offset_expr, tempreg);
10500 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10501 tempreg, tempreg, BFD_RELOC_LO16);
10502 if (mips_relax.sequence)
10506 else if (!mips_big_got && !HAVE_NEWABI)
10508 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10510 /* If this is a reference to an external symbol, and there
10511 is no constant, we want
10512 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10513 or for lca or if tempreg is PIC_CALL_REG
10514 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10515 For a local symbol, we want
10516 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10518 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10520 If we have a small constant, and this is a reference to
10521 an external symbol, we want
10522 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10524 addiu $tempreg,$tempreg,<constant>
10525 For a local symbol, we want the same instruction
10526 sequence, but we output a BFD_RELOC_LO16 reloc on the
10529 If we have a large constant, and this is a reference to
10530 an external symbol, we want
10531 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10532 lui $at,<hiconstant>
10533 addiu $at,$at,<loconstant>
10534 addu $tempreg,$tempreg,$at
10535 For a local symbol, we want the same instruction
10536 sequence, but we output a BFD_RELOC_LO16 reloc on the
10540 if (offset_expr.X_add_number == 0)
10542 if (mips_pic == SVR4_PIC
10544 && (call || tempreg == PIC_CALL_REG))
10545 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10547 relax_start (offset_expr.X_add_symbol);
10548 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10549 lw_reloc_type, mips_gp_register);
10552 /* We're going to put in an addu instruction using
10553 tempreg, so we may as well insert the nop right
10558 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10559 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10561 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10562 tempreg, tempreg, BFD_RELOC_LO16);
10564 /* FIXME: If breg == 0, and the next instruction uses
10565 $tempreg, then if this variant case is used an extra
10566 nop will be generated. */
10568 else if (offset_expr.X_add_number >= -0x8000
10569 && offset_expr.X_add_number < 0x8000)
10571 load_got_offset (tempreg, &offset_expr);
10573 add_got_offset (tempreg, &offset_expr);
10577 expr1.X_add_number = offset_expr.X_add_number;
10578 offset_expr.X_add_number =
10579 SEXT_16BIT (offset_expr.X_add_number);
10580 load_got_offset (tempreg, &offset_expr);
10581 offset_expr.X_add_number = expr1.X_add_number;
10582 /* If we are going to add in a base register, and the
10583 target register and the base register are the same,
10584 then we are using AT as a temporary register. Since
10585 we want to load the constant into AT, we add our
10586 current AT (from the global offset table) and the
10587 register into the register now, and pretend we were
10588 not using a base register. */
10592 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10597 add_got_offset_hilo (tempreg, &offset_expr, AT);
10601 else if (!mips_big_got && HAVE_NEWABI)
10603 int add_breg_early = 0;
10605 /* If this is a reference to an external, and there is no
10606 constant, or local symbol (*), with or without a
10608 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10609 or for lca or if tempreg is PIC_CALL_REG
10610 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10612 If we have a small constant, and this is a reference to
10613 an external symbol, we want
10614 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10615 addiu $tempreg,$tempreg,<constant>
10617 If we have a large constant, and this is a reference to
10618 an external symbol, we want
10619 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10620 lui $at,<hiconstant>
10621 addiu $at,$at,<loconstant>
10622 addu $tempreg,$tempreg,$at
10624 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10625 local symbols, even though it introduces an additional
10628 if (offset_expr.X_add_number)
10630 expr1.X_add_number = offset_expr.X_add_number;
10631 offset_expr.X_add_number = 0;
10633 relax_start (offset_expr.X_add_symbol);
10634 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10635 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10637 if (expr1.X_add_number >= -0x8000
10638 && expr1.X_add_number < 0x8000)
10640 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10641 tempreg, tempreg, BFD_RELOC_LO16);
10643 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10647 /* If we are going to add in a base register, and the
10648 target register and the base register are the same,
10649 then we are using AT as a temporary register. Since
10650 we want to load the constant into AT, we add our
10651 current AT (from the global offset table) and the
10652 register into the register now, and pretend we were
10653 not using a base register. */
10658 gas_assert (tempreg == AT);
10659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10662 add_breg_early = 1;
10665 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10666 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10672 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10675 offset_expr.X_add_number = expr1.X_add_number;
10677 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10678 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10679 if (add_breg_early)
10681 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10682 op[0], tempreg, breg);
10688 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10690 relax_start (offset_expr.X_add_symbol);
10691 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10692 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10694 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10695 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10700 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10701 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10704 else if (mips_big_got && !HAVE_NEWABI)
10707 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10708 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10709 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10711 /* This is the large GOT case. If this is a reference to an
10712 external symbol, and there is no constant, we want
10713 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10714 addu $tempreg,$tempreg,$gp
10715 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10716 or for lca or if tempreg is PIC_CALL_REG
10717 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10718 addu $tempreg,$tempreg,$gp
10719 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10720 For a local symbol, we want
10721 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10723 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10725 If we have a small constant, and this is a reference to
10726 an external symbol, we want
10727 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10728 addu $tempreg,$tempreg,$gp
10729 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10731 addiu $tempreg,$tempreg,<constant>
10732 For a local symbol, we want
10733 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10735 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10737 If we have a large constant, and this is a reference to
10738 an external symbol, we want
10739 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10740 addu $tempreg,$tempreg,$gp
10741 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10742 lui $at,<hiconstant>
10743 addiu $at,$at,<loconstant>
10744 addu $tempreg,$tempreg,$at
10745 For a local symbol, we want
10746 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10747 lui $at,<hiconstant>
10748 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10749 addu $tempreg,$tempreg,$at
10752 expr1.X_add_number = offset_expr.X_add_number;
10753 offset_expr.X_add_number = 0;
10754 relax_start (offset_expr.X_add_symbol);
10755 gpdelay = reg_needs_delay (mips_gp_register);
10756 if (expr1.X_add_number == 0 && breg == 0
10757 && (call || tempreg == PIC_CALL_REG))
10759 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10760 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10762 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10763 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10764 tempreg, tempreg, mips_gp_register);
10765 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10766 tempreg, lw_reloc_type, tempreg);
10767 if (expr1.X_add_number == 0)
10771 /* We're going to put in an addu instruction using
10772 tempreg, so we may as well insert the nop right
10777 else if (expr1.X_add_number >= -0x8000
10778 && expr1.X_add_number < 0x8000)
10781 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10782 tempreg, tempreg, BFD_RELOC_LO16);
10788 /* If we are going to add in a base register, and the
10789 target register and the base register are the same,
10790 then we are using AT as a temporary register. Since
10791 we want to load the constant into AT, we add our
10792 current AT (from the global offset table) and the
10793 register into the register now, and pretend we were
10794 not using a base register. */
10799 gas_assert (tempreg == AT);
10801 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10806 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10807 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10811 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10816 /* This is needed because this instruction uses $gp, but
10817 the first instruction on the main stream does not. */
10818 macro_build (NULL, "nop", "");
10821 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10822 local_reloc_type, mips_gp_register);
10823 if (expr1.X_add_number >= -0x8000
10824 && expr1.X_add_number < 0x8000)
10827 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10828 tempreg, tempreg, BFD_RELOC_LO16);
10829 /* FIXME: If add_number is 0, and there was no base
10830 register, the external symbol case ended with a load,
10831 so if the symbol turns out to not be external, and
10832 the next instruction uses tempreg, an unnecessary nop
10833 will be inserted. */
10839 /* We must add in the base register now, as in the
10840 external symbol case. */
10841 gas_assert (tempreg == AT);
10843 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10846 /* We set breg to 0 because we have arranged to add
10847 it in in both cases. */
10851 macro_build_lui (&expr1, AT);
10852 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10853 AT, AT, BFD_RELOC_LO16);
10854 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10855 tempreg, tempreg, AT);
10860 else if (mips_big_got && HAVE_NEWABI)
10862 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10863 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10864 int add_breg_early = 0;
10866 /* This is the large GOT case. If this is a reference to an
10867 external symbol, and there is no constant, we want
10868 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10869 add $tempreg,$tempreg,$gp
10870 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10871 or for lca or if tempreg is PIC_CALL_REG
10872 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10873 add $tempreg,$tempreg,$gp
10874 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10876 If we have a small constant, and this is a reference to
10877 an external symbol, we want
10878 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10879 add $tempreg,$tempreg,$gp
10880 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10881 addi $tempreg,$tempreg,<constant>
10883 If we have a large constant, and this is a reference to
10884 an external symbol, we want
10885 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10886 addu $tempreg,$tempreg,$gp
10887 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10888 lui $at,<hiconstant>
10889 addi $at,$at,<loconstant>
10890 add $tempreg,$tempreg,$at
10892 If we have NewABI, and we know it's a local symbol, we want
10893 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10894 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10895 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10897 relax_start (offset_expr.X_add_symbol);
10899 expr1.X_add_number = offset_expr.X_add_number;
10900 offset_expr.X_add_number = 0;
10902 if (expr1.X_add_number == 0 && breg == 0
10903 && (call || tempreg == PIC_CALL_REG))
10905 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10906 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10908 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10909 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10910 tempreg, tempreg, mips_gp_register);
10911 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10912 tempreg, lw_reloc_type, tempreg);
10914 if (expr1.X_add_number == 0)
10916 else if (expr1.X_add_number >= -0x8000
10917 && expr1.X_add_number < 0x8000)
10919 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10920 tempreg, tempreg, BFD_RELOC_LO16);
10922 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10926 /* If we are going to add in a base register, and the
10927 target register and the base register are the same,
10928 then we are using AT as a temporary register. Since
10929 we want to load the constant into AT, we add our
10930 current AT (from the global offset table) and the
10931 register into the register now, and pretend we were
10932 not using a base register. */
10937 gas_assert (tempreg == AT);
10938 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10941 add_breg_early = 1;
10944 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10945 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10950 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10953 offset_expr.X_add_number = expr1.X_add_number;
10954 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10955 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10956 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10957 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10958 if (add_breg_early)
10960 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10961 op[0], tempreg, breg);
10971 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10975 gas_assert (!mips_opts.micromips);
10976 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10980 gas_assert (!mips_opts.micromips);
10981 macro_build (NULL, "c2", "C", 0x02);
10985 gas_assert (!mips_opts.micromips);
10986 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10990 gas_assert (!mips_opts.micromips);
10991 macro_build (NULL, "c2", "C", 3);
10995 gas_assert (!mips_opts.micromips);
10996 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
11000 /* The j instruction may not be used in PIC code, since it
11001 requires an absolute address. We convert it to a b
11003 if (mips_pic == NO_PIC)
11004 macro_build (&offset_expr, "j", "a");
11006 macro_build (&offset_expr, "b", "p");
11009 /* The jal instructions must be handled as macros because when
11010 generating PIC code they expand to multi-instruction
11011 sequences. Normally they are simple instructions. */
11015 /* Fall through. */
11017 gas_assert (mips_opts.micromips);
11018 if (mips_opts.insn32)
11020 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11028 /* Fall through. */
11031 if (mips_pic == NO_PIC)
11033 s = jals ? "jalrs" : "jalr";
11034 if (mips_opts.micromips
11035 && !mips_opts.insn32
11037 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11038 macro_build (NULL, s, "mj", op[1]);
11040 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11044 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11045 && mips_cprestore_offset >= 0);
11047 if (op[1] != PIC_CALL_REG)
11048 as_warn (_("MIPS PIC call to register other than $25"));
11050 s = ((mips_opts.micromips
11051 && !mips_opts.insn32
11052 && (!mips_opts.noreorder || cprestore))
11053 ? "jalrs" : "jalr");
11054 if (mips_opts.micromips
11055 && !mips_opts.insn32
11057 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11058 macro_build (NULL, s, "mj", op[1]);
11060 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11061 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11063 if (mips_cprestore_offset < 0)
11064 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11067 if (!mips_frame_reg_valid)
11069 as_warn (_("no .frame pseudo-op used in PIC code"));
11070 /* Quiet this warning. */
11071 mips_frame_reg_valid = 1;
11073 if (!mips_cprestore_valid)
11075 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11076 /* Quiet this warning. */
11077 mips_cprestore_valid = 1;
11079 if (mips_opts.noreorder)
11080 macro_build (NULL, "nop", "");
11081 expr1.X_add_number = mips_cprestore_offset;
11082 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11085 HAVE_64BIT_ADDRESSES);
11093 gas_assert (mips_opts.micromips);
11094 if (mips_opts.insn32)
11096 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11100 /* Fall through. */
11102 if (mips_pic == NO_PIC)
11103 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11104 else if (mips_pic == SVR4_PIC)
11106 /* If this is a reference to an external symbol, and we are
11107 using a small GOT, we want
11108 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11112 lw $gp,cprestore($sp)
11113 The cprestore value is set using the .cprestore
11114 pseudo-op. If we are using a big GOT, we want
11115 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11117 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11121 lw $gp,cprestore($sp)
11122 If the symbol is not external, we want
11123 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11125 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11128 lw $gp,cprestore($sp)
11130 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11131 sequences above, minus nops, unless the symbol is local,
11132 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11138 relax_start (offset_expr.X_add_symbol);
11139 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11140 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11143 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11144 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11150 relax_start (offset_expr.X_add_symbol);
11151 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11152 BFD_RELOC_MIPS_CALL_HI16);
11153 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11154 PIC_CALL_REG, mips_gp_register);
11155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11156 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11159 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11160 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11162 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11163 PIC_CALL_REG, PIC_CALL_REG,
11164 BFD_RELOC_MIPS_GOT_OFST);
11168 macro_build_jalr (&offset_expr, 0);
11172 relax_start (offset_expr.X_add_symbol);
11175 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11176 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11185 gpdelay = reg_needs_delay (mips_gp_register);
11186 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11187 BFD_RELOC_MIPS_CALL_HI16);
11188 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11189 PIC_CALL_REG, mips_gp_register);
11190 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11191 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11196 macro_build (NULL, "nop", "");
11198 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11199 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11202 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11203 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11205 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11207 if (mips_cprestore_offset < 0)
11208 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11211 if (!mips_frame_reg_valid)
11213 as_warn (_("no .frame pseudo-op used in PIC code"));
11214 /* Quiet this warning. */
11215 mips_frame_reg_valid = 1;
11217 if (!mips_cprestore_valid)
11219 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11220 /* Quiet this warning. */
11221 mips_cprestore_valid = 1;
11223 if (mips_opts.noreorder)
11224 macro_build (NULL, "nop", "");
11225 expr1.X_add_number = mips_cprestore_offset;
11226 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11229 HAVE_64BIT_ADDRESSES);
11233 else if (mips_pic == VXWORKS_PIC)
11234 as_bad (_("non-PIC jump used in PIC library"));
11341 gas_assert (!mips_opts.micromips);
11344 /* Itbl support may require additional care here. */
11350 /* Itbl support may require additional care here. */
11356 offbits = (mips_opts.micromips ? 12
11357 : ISA_IS_R6 (mips_opts.isa) ? 11
11359 /* Itbl support may require additional care here. */
11363 gas_assert (!mips_opts.micromips);
11366 /* Itbl support may require additional care here. */
11372 offbits = (mips_opts.micromips ? 12 : 16);
11377 offbits = (mips_opts.micromips ? 12 : 16);
11382 /* Itbl support may require additional care here. */
11388 offbits = (mips_opts.micromips ? 12
11389 : ISA_IS_R6 (mips_opts.isa) ? 11
11391 /* Itbl support may require additional care here. */
11397 /* Itbl support may require additional care here. */
11403 /* Itbl support may require additional care here. */
11409 offbits = (mips_opts.micromips ? 12 : 16);
11414 offbits = (mips_opts.micromips ? 12 : 16);
11419 offbits = (mips_opts.micromips ? 12
11420 : ISA_IS_R6 (mips_opts.isa) ? 9
11426 offbits = (mips_opts.micromips ? 12
11427 : ISA_IS_R6 (mips_opts.isa) ? 9
11433 offbits = (mips_opts.micromips ? 12 : 16);
11436 gas_assert (mips_opts.micromips);
11443 gas_assert (mips_opts.micromips);
11450 gas_assert (mips_opts.micromips);
11456 gas_assert (mips_opts.micromips);
11463 /* We don't want to use $0 as tempreg. */
11464 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11467 tempreg = op[0] + lp;
11483 gas_assert (!mips_opts.micromips);
11486 /* Itbl support may require additional care here. */
11492 /* Itbl support may require additional care here. */
11498 offbits = (mips_opts.micromips ? 12
11499 : ISA_IS_R6 (mips_opts.isa) ? 11
11501 /* Itbl support may require additional care here. */
11505 gas_assert (!mips_opts.micromips);
11508 /* Itbl support may require additional care here. */
11514 offbits = (mips_opts.micromips ? 12 : 16);
11519 offbits = (mips_opts.micromips ? 12 : 16);
11524 offbits = (mips_opts.micromips ? 12
11525 : ISA_IS_R6 (mips_opts.isa) ? 9
11531 offbits = (mips_opts.micromips ? 12
11532 : ISA_IS_R6 (mips_opts.isa) ? 9
11537 fmt = (mips_opts.micromips ? "k,~(b)"
11538 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11540 offbits = (mips_opts.micromips ? 12
11541 : ISA_IS_R6 (mips_opts.isa) ? 9
11551 fmt = (mips_opts.micromips ? "k,~(b)"
11552 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11554 offbits = (mips_opts.micromips ? 12
11555 : ISA_IS_R6 (mips_opts.isa) ? 9
11567 /* Itbl support may require additional care here. */
11572 offbits = (mips_opts.micromips ? 12
11573 : ISA_IS_R6 (mips_opts.isa) ? 11
11575 /* Itbl support may require additional care here. */
11581 /* Itbl support may require additional care here. */
11585 gas_assert (!mips_opts.micromips);
11588 /* Itbl support may require additional care here. */
11594 offbits = (mips_opts.micromips ? 12 : 16);
11599 offbits = (mips_opts.micromips ? 12 : 16);
11602 gas_assert (mips_opts.micromips);
11608 gas_assert (mips_opts.micromips);
11614 gas_assert (mips_opts.micromips);
11620 gas_assert (mips_opts.micromips);
11629 if (small_offset_p (0, align, 16))
11631 /* The first case exists for M_LD_AB and M_SD_AB, which are
11632 macros for o32 but which should act like normal instructions
11635 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11636 offset_reloc[1], offset_reloc[2], breg);
11637 else if (small_offset_p (0, align, offbits))
11640 macro_build (NULL, s, fmt, op[0], breg);
11642 macro_build (NULL, s, fmt, op[0],
11643 (int) offset_expr.X_add_number, breg);
11649 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11650 tempreg, breg, -1, offset_reloc[0],
11651 offset_reloc[1], offset_reloc[2]);
11653 macro_build (NULL, s, fmt, op[0], tempreg);
11655 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11663 if (offset_expr.X_op != O_constant
11664 && offset_expr.X_op != O_symbol)
11666 as_bad (_("expression too complex"));
11667 offset_expr.X_op = O_constant;
11670 if (HAVE_32BIT_ADDRESSES
11671 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11675 sprintf_vma (value, offset_expr.X_add_number);
11676 as_bad (_("number (0x%s) larger than 32 bits"), value);
11679 /* A constant expression in PIC code can be handled just as it
11680 is in non PIC code. */
11681 if (offset_expr.X_op == O_constant)
11683 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11684 offbits == 0 ? 16 : offbits);
11685 offset_expr.X_add_number -= expr1.X_add_number;
11687 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11689 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11690 tempreg, tempreg, breg);
11693 if (offset_expr.X_add_number != 0)
11694 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
11695 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
11696 macro_build (NULL, s, fmt, op[0], tempreg);
11698 else if (offbits == 16)
11699 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11701 macro_build (NULL, s, fmt, op[0],
11702 (int) offset_expr.X_add_number, tempreg);
11704 else if (offbits != 16)
11706 /* The offset field is too narrow to be used for a low-part
11707 relocation, so load the whole address into the auxillary
11709 load_address (tempreg, &offset_expr, &used_at);
11711 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11712 tempreg, tempreg, breg);
11714 macro_build (NULL, s, fmt, op[0], tempreg);
11716 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11718 else if (mips_pic == NO_PIC)
11720 /* If this is a reference to a GP relative symbol, and there
11721 is no base register, we want
11722 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11723 Otherwise, if there is no base register, we want
11724 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11725 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11726 If we have a constant, we need two instructions anyhow,
11727 so we always use the latter form.
11729 If we have a base register, and this is a reference to a
11730 GP relative symbol, we want
11731 addu $tempreg,$breg,$gp
11732 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11734 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11735 addu $tempreg,$tempreg,$breg
11736 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11737 With a constant we always use the latter case.
11739 With 64bit address space and no base register and $at usable,
11741 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11742 lui $at,<sym> (BFD_RELOC_HI16_S)
11743 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11746 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11747 If we have a base register, we want
11748 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11749 lui $at,<sym> (BFD_RELOC_HI16_S)
11750 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11754 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11756 Without $at we can't generate the optimal path for superscalar
11757 processors here since this would require two temporary registers.
11758 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11759 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11761 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11763 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11764 If we have a base register, we want
11765 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11766 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11768 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11770 daddu $tempreg,$tempreg,$breg
11771 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11773 For GP relative symbols in 64bit address space we can use
11774 the same sequence as in 32bit address space. */
11775 if (HAVE_64BIT_SYMBOLS)
11777 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11778 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11780 relax_start (offset_expr.X_add_symbol);
11783 macro_build (&offset_expr, s, fmt, op[0],
11784 BFD_RELOC_GPREL16, mips_gp_register);
11788 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11789 tempreg, breg, mips_gp_register);
11790 macro_build (&offset_expr, s, fmt, op[0],
11791 BFD_RELOC_GPREL16, tempreg);
11796 if (used_at == 0 && mips_opts.at)
11798 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11799 BFD_RELOC_MIPS_HIGHEST);
11800 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11802 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11803 tempreg, BFD_RELOC_MIPS_HIGHER);
11805 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11806 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11807 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11808 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11814 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11815 BFD_RELOC_MIPS_HIGHEST);
11816 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11817 tempreg, BFD_RELOC_MIPS_HIGHER);
11818 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11819 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11820 tempreg, BFD_RELOC_HI16_S);
11821 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11823 macro_build (NULL, "daddu", "d,v,t",
11824 tempreg, tempreg, breg);
11825 macro_build (&offset_expr, s, fmt, op[0],
11826 BFD_RELOC_LO16, tempreg);
11829 if (mips_relax.sequence)
11836 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11837 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11839 relax_start (offset_expr.X_add_symbol);
11840 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11844 macro_build_lui (&offset_expr, tempreg);
11845 macro_build (&offset_expr, s, fmt, op[0],
11846 BFD_RELOC_LO16, tempreg);
11847 if (mips_relax.sequence)
11852 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11853 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11855 relax_start (offset_expr.X_add_symbol);
11856 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11857 tempreg, breg, mips_gp_register);
11858 macro_build (&offset_expr, s, fmt, op[0],
11859 BFD_RELOC_GPREL16, tempreg);
11862 macro_build_lui (&offset_expr, tempreg);
11863 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11864 tempreg, tempreg, breg);
11865 macro_build (&offset_expr, s, fmt, op[0],
11866 BFD_RELOC_LO16, tempreg);
11867 if (mips_relax.sequence)
11871 else if (!mips_big_got)
11873 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11875 /* If this is a reference to an external symbol, we want
11876 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11878 <op> op[0],0($tempreg)
11880 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11882 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11883 <op> op[0],0($tempreg)
11885 For NewABI, we want
11886 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11887 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11889 If there is a base register, we add it to $tempreg before
11890 the <op>. If there is a constant, we stick it in the
11891 <op> instruction. We don't handle constants larger than
11892 16 bits, because we have no way to load the upper 16 bits
11893 (actually, we could handle them for the subset of cases
11894 in which we are not using $at). */
11895 gas_assert (offset_expr.X_op == O_symbol);
11898 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11899 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11901 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11902 tempreg, tempreg, breg);
11903 macro_build (&offset_expr, s, fmt, op[0],
11904 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11907 expr1.X_add_number = offset_expr.X_add_number;
11908 offset_expr.X_add_number = 0;
11909 if (expr1.X_add_number < -0x8000
11910 || expr1.X_add_number >= 0x8000)
11911 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11912 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11913 lw_reloc_type, mips_gp_register);
11915 relax_start (offset_expr.X_add_symbol);
11917 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11918 tempreg, BFD_RELOC_LO16);
11921 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11922 tempreg, tempreg, breg);
11923 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11925 else if (mips_big_got && !HAVE_NEWABI)
11929 /* If this is a reference to an external symbol, we want
11930 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11931 addu $tempreg,$tempreg,$gp
11932 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11933 <op> op[0],0($tempreg)
11935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11937 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11938 <op> op[0],0($tempreg)
11939 If there is a base register, we add it to $tempreg before
11940 the <op>. If there is a constant, we stick it in the
11941 <op> instruction. We don't handle constants larger than
11942 16 bits, because we have no way to load the upper 16 bits
11943 (actually, we could handle them for the subset of cases
11944 in which we are not using $at). */
11945 gas_assert (offset_expr.X_op == O_symbol);
11946 expr1.X_add_number = offset_expr.X_add_number;
11947 offset_expr.X_add_number = 0;
11948 if (expr1.X_add_number < -0x8000
11949 || expr1.X_add_number >= 0x8000)
11950 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11951 gpdelay = reg_needs_delay (mips_gp_register);
11952 relax_start (offset_expr.X_add_symbol);
11953 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11954 BFD_RELOC_MIPS_GOT_HI16);
11955 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11957 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11958 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11961 macro_build (NULL, "nop", "");
11962 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11963 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11965 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11966 tempreg, BFD_RELOC_LO16);
11970 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11971 tempreg, tempreg, breg);
11972 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11974 else if (mips_big_got && HAVE_NEWABI)
11976 /* If this is a reference to an external symbol, we want
11977 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11978 add $tempreg,$tempreg,$gp
11979 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11980 <op> op[0],<ofst>($tempreg)
11981 Otherwise, for local symbols, we want:
11982 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11983 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11984 gas_assert (offset_expr.X_op == O_symbol);
11985 expr1.X_add_number = offset_expr.X_add_number;
11986 offset_expr.X_add_number = 0;
11987 if (expr1.X_add_number < -0x8000
11988 || expr1.X_add_number >= 0x8000)
11989 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11990 relax_start (offset_expr.X_add_symbol);
11991 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11992 BFD_RELOC_MIPS_GOT_HI16);
11993 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11995 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11996 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11998 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11999 tempreg, tempreg, breg);
12000 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12003 offset_expr.X_add_number = expr1.X_add_number;
12004 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12005 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12007 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12008 tempreg, tempreg, breg);
12009 macro_build (&offset_expr, s, fmt, op[0],
12010 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12019 gas_assert (mips_opts.micromips);
12020 gas_assert (mips_opts.insn32);
12021 start_noreorder ();
12022 macro_build (NULL, "jr", "s", RA);
12023 expr1.X_add_number = op[0] << 2;
12024 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12029 gas_assert (mips_opts.micromips);
12030 gas_assert (mips_opts.insn32);
12031 macro_build (NULL, "jr", "s", op[0]);
12032 if (mips_opts.noreorder)
12033 macro_build (NULL, "nop", "");
12038 load_register (op[0], &imm_expr, 0);
12042 load_register (op[0], &imm_expr, 1);
12046 if (imm_expr.X_op == O_constant)
12049 load_register (AT, &imm_expr, 0);
12050 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12055 gas_assert (imm_expr.X_op == O_absent
12056 && offset_expr.X_op == O_symbol
12057 && strcmp (segment_name (S_GET_SEGMENT
12058 (offset_expr.X_add_symbol)),
12060 && offset_expr.X_add_number == 0);
12061 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12062 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12067 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12068 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12069 order 32 bits of the value and the low order 32 bits are either
12070 zero or in OFFSET_EXPR. */
12071 if (imm_expr.X_op == O_constant)
12073 if (GPR_SIZE == 64)
12074 load_register (op[0], &imm_expr, 1);
12079 if (target_big_endian)
12091 load_register (hreg, &imm_expr, 0);
12094 if (offset_expr.X_op == O_absent)
12095 move_register (lreg, 0);
12098 gas_assert (offset_expr.X_op == O_constant);
12099 load_register (lreg, &offset_expr, 0);
12105 gas_assert (imm_expr.X_op == O_absent);
12107 /* We know that sym is in the .rdata section. First we get the
12108 upper 16 bits of the address. */
12109 if (mips_pic == NO_PIC)
12111 macro_build_lui (&offset_expr, AT);
12116 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12117 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12121 /* Now we load the register(s). */
12122 if (GPR_SIZE == 64)
12125 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12126 BFD_RELOC_LO16, AT);
12131 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12132 BFD_RELOC_LO16, AT);
12135 /* FIXME: How in the world do we deal with the possible
12137 offset_expr.X_add_number += 4;
12138 macro_build (&offset_expr, "lw", "t,o(b)",
12139 op[0] + 1, BFD_RELOC_LO16, AT);
12145 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12146 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12147 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12148 the value and the low order 32 bits are either zero or in
12150 if (imm_expr.X_op == O_constant)
12153 load_register (AT, &imm_expr, FPR_SIZE == 64);
12154 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12155 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12158 if (ISA_HAS_MXHC1 (mips_opts.isa))
12159 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12160 else if (FPR_SIZE != 32)
12161 as_bad (_("Unable to generate `%s' compliant code "
12163 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12165 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12166 if (offset_expr.X_op == O_absent)
12167 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12170 gas_assert (offset_expr.X_op == O_constant);
12171 load_register (AT, &offset_expr, 0);
12172 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12178 gas_assert (imm_expr.X_op == O_absent
12179 && offset_expr.X_op == O_symbol
12180 && offset_expr.X_add_number == 0);
12181 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12182 if (strcmp (s, ".lit8") == 0)
12184 op[2] = mips_gp_register;
12185 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12186 offset_reloc[1] = BFD_RELOC_UNUSED;
12187 offset_reloc[2] = BFD_RELOC_UNUSED;
12191 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12193 if (mips_pic != NO_PIC)
12194 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12195 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12198 /* FIXME: This won't work for a 64 bit address. */
12199 macro_build_lui (&offset_expr, AT);
12203 offset_reloc[0] = BFD_RELOC_LO16;
12204 offset_reloc[1] = BFD_RELOC_UNUSED;
12205 offset_reloc[2] = BFD_RELOC_UNUSED;
12212 * The MIPS assembler seems to check for X_add_number not
12213 * being double aligned and generating:
12214 * lui at,%hi(foo+1)
12216 * addiu at,at,%lo(foo+1)
12219 * But, the resulting address is the same after relocation so why
12220 * generate the extra instruction?
12222 /* Itbl support may require additional care here. */
12225 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12234 gas_assert (!mips_opts.micromips);
12235 /* Itbl support may require additional care here. */
12238 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12258 if (GPR_SIZE == 64)
12268 if (GPR_SIZE == 64)
12276 /* Even on a big endian machine $fn comes before $fn+1. We have
12277 to adjust when loading from memory. We set coproc if we must
12278 load $fn+1 first. */
12279 /* Itbl support may require additional care here. */
12280 if (!target_big_endian)
12284 if (small_offset_p (0, align, 16))
12287 if (!small_offset_p (4, align, 16))
12289 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12290 -1, offset_reloc[0], offset_reloc[1],
12292 expr1.X_add_number = 0;
12296 offset_reloc[0] = BFD_RELOC_LO16;
12297 offset_reloc[1] = BFD_RELOC_UNUSED;
12298 offset_reloc[2] = BFD_RELOC_UNUSED;
12300 if (strcmp (s, "lw") == 0 && op[0] == breg)
12302 ep->X_add_number += 4;
12303 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12304 offset_reloc[1], offset_reloc[2], breg);
12305 ep->X_add_number -= 4;
12306 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12307 offset_reloc[1], offset_reloc[2], breg);
12311 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12312 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12314 ep->X_add_number += 4;
12315 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12316 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12322 if (offset_expr.X_op != O_symbol
12323 && offset_expr.X_op != O_constant)
12325 as_bad (_("expression too complex"));
12326 offset_expr.X_op = O_constant;
12329 if (HAVE_32BIT_ADDRESSES
12330 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12334 sprintf_vma (value, offset_expr.X_add_number);
12335 as_bad (_("number (0x%s) larger than 32 bits"), value);
12338 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12340 /* If this is a reference to a GP relative symbol, we want
12341 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12342 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12343 If we have a base register, we use this
12345 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12346 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12347 If this is not a GP relative symbol, we want
12348 lui $at,<sym> (BFD_RELOC_HI16_S)
12349 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12350 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12351 If there is a base register, we add it to $at after the
12352 lui instruction. If there is a constant, we always use
12354 if (offset_expr.X_op == O_symbol
12355 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12356 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12358 relax_start (offset_expr.X_add_symbol);
12361 tempreg = mips_gp_register;
12365 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12366 AT, breg, mips_gp_register);
12371 /* Itbl support may require additional care here. */
12372 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12373 BFD_RELOC_GPREL16, tempreg);
12374 offset_expr.X_add_number += 4;
12376 /* Set mips_optimize to 2 to avoid inserting an
12378 hold_mips_optimize = mips_optimize;
12380 /* Itbl support may require additional care here. */
12381 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12382 BFD_RELOC_GPREL16, tempreg);
12383 mips_optimize = hold_mips_optimize;
12387 offset_expr.X_add_number -= 4;
12390 if (offset_high_part (offset_expr.X_add_number, 16)
12391 != offset_high_part (offset_expr.X_add_number + 4, 16))
12393 load_address (AT, &offset_expr, &used_at);
12394 offset_expr.X_op = O_constant;
12395 offset_expr.X_add_number = 0;
12398 macro_build_lui (&offset_expr, AT);
12400 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12401 /* Itbl support may require additional care here. */
12402 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12403 BFD_RELOC_LO16, AT);
12404 /* FIXME: How do we handle overflow here? */
12405 offset_expr.X_add_number += 4;
12406 /* Itbl support may require additional care here. */
12407 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12408 BFD_RELOC_LO16, AT);
12409 if (mips_relax.sequence)
12412 else if (!mips_big_got)
12414 /* If this is a reference to an external symbol, we want
12415 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12418 <op> op[0]+1,4($at)
12420 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12422 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12423 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12424 If there is a base register we add it to $at before the
12425 lwc1 instructions. If there is a constant we include it
12426 in the lwc1 instructions. */
12428 expr1.X_add_number = offset_expr.X_add_number;
12429 if (expr1.X_add_number < -0x8000
12430 || expr1.X_add_number >= 0x8000 - 4)
12431 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12432 load_got_offset (AT, &offset_expr);
12435 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12437 /* Set mips_optimize to 2 to avoid inserting an undesired
12439 hold_mips_optimize = mips_optimize;
12442 /* Itbl support may require additional care here. */
12443 relax_start (offset_expr.X_add_symbol);
12444 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12445 BFD_RELOC_LO16, AT);
12446 expr1.X_add_number += 4;
12447 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12448 BFD_RELOC_LO16, AT);
12450 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12451 BFD_RELOC_LO16, AT);
12452 offset_expr.X_add_number += 4;
12453 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12454 BFD_RELOC_LO16, AT);
12457 mips_optimize = hold_mips_optimize;
12459 else if (mips_big_got)
12463 /* If this is a reference to an external symbol, we want
12464 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12466 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12469 <op> op[0]+1,4($at)
12471 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12473 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12474 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12475 If there is a base register we add it to $at before the
12476 lwc1 instructions. If there is a constant we include it
12477 in the lwc1 instructions. */
12479 expr1.X_add_number = offset_expr.X_add_number;
12480 offset_expr.X_add_number = 0;
12481 if (expr1.X_add_number < -0x8000
12482 || expr1.X_add_number >= 0x8000 - 4)
12483 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12484 gpdelay = reg_needs_delay (mips_gp_register);
12485 relax_start (offset_expr.X_add_symbol);
12486 macro_build (&offset_expr, "lui", LUI_FMT,
12487 AT, BFD_RELOC_MIPS_GOT_HI16);
12488 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12489 AT, AT, mips_gp_register);
12490 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12491 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12494 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12495 /* Itbl support may require additional care here. */
12496 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12497 BFD_RELOC_LO16, AT);
12498 expr1.X_add_number += 4;
12500 /* Set mips_optimize to 2 to avoid inserting an undesired
12502 hold_mips_optimize = mips_optimize;
12504 /* Itbl support may require additional care here. */
12505 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12506 BFD_RELOC_LO16, AT);
12507 mips_optimize = hold_mips_optimize;
12508 expr1.X_add_number -= 4;
12511 offset_expr.X_add_number = expr1.X_add_number;
12513 macro_build (NULL, "nop", "");
12514 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12515 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12518 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12519 /* Itbl support may require additional care here. */
12520 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12521 BFD_RELOC_LO16, AT);
12522 offset_expr.X_add_number += 4;
12524 /* Set mips_optimize to 2 to avoid inserting an undesired
12526 hold_mips_optimize = mips_optimize;
12528 /* Itbl support may require additional care here. */
12529 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12530 BFD_RELOC_LO16, AT);
12531 mips_optimize = hold_mips_optimize;
12545 gas_assert (!mips_opts.micromips);
12550 /* New code added to support COPZ instructions.
12551 This code builds table entries out of the macros in mip_opcodes.
12552 R4000 uses interlocks to handle coproc delays.
12553 Other chips (like the R3000) require nops to be inserted for delays.
12555 FIXME: Currently, we require that the user handle delays.
12556 In order to fill delay slots for non-interlocked chips,
12557 we must have a way to specify delays based on the coprocessor.
12558 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12559 What are the side-effects of the cop instruction?
12560 What cache support might we have and what are its effects?
12561 Both coprocessor & memory require delays. how long???
12562 What registers are read/set/modified?
12564 If an itbl is provided to interpret cop instructions,
12565 this knowledge can be encoded in the itbl spec. */
12579 gas_assert (!mips_opts.micromips);
12580 /* For now we just do C (same as Cz). The parameter will be
12581 stored in insn_opcode by mips_ip. */
12582 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12586 move_register (op[0], op[1]);
12590 gas_assert (mips_opts.micromips);
12591 gas_assert (mips_opts.insn32);
12592 move_register (micromips_to_32_reg_h_map1[op[0]],
12593 micromips_to_32_reg_m_map[op[1]]);
12594 move_register (micromips_to_32_reg_h_map2[op[0]],
12595 micromips_to_32_reg_n_map[op[2]]);
12601 if (mips_opts.arch == CPU_R5900)
12602 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12606 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12607 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12614 /* The MIPS assembler some times generates shifts and adds. I'm
12615 not trying to be that fancy. GCC should do this for us
12618 load_register (AT, &imm_expr, dbl);
12619 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12620 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12633 start_noreorder ();
12636 load_register (AT, &imm_expr, dbl);
12637 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12638 op[1], imm ? AT : op[2]);
12639 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12640 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12641 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12643 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12646 if (mips_opts.micromips)
12647 micromips_label_expr (&label_expr);
12649 label_expr.X_add_number = 8;
12650 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12651 macro_build (NULL, "nop", "");
12652 macro_build (NULL, "break", BRK_FMT, 6);
12653 if (mips_opts.micromips)
12654 micromips_add_label ();
12657 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12670 start_noreorder ();
12673 load_register (AT, &imm_expr, dbl);
12674 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
12675 op[1], imm ? AT : op[2]);
12676 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12677 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12679 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
12682 if (mips_opts.micromips)
12683 micromips_label_expr (&label_expr);
12685 label_expr.X_add_number = 8;
12686 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
12687 macro_build (NULL, "nop", "");
12688 macro_build (NULL, "break", BRK_FMT, 6);
12689 if (mips_opts.micromips)
12690 micromips_add_label ();
12696 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12698 if (op[0] == op[1])
12705 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12706 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12710 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12711 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12712 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12713 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12717 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12719 if (op[0] == op[1])
12726 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12727 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12731 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12732 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12733 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12734 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12743 rot = imm_expr.X_add_number & 0x3f;
12744 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12746 rot = (64 - rot) & 0x3f;
12748 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12750 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12755 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12758 l = (rot < 0x20) ? "dsll" : "dsll32";
12759 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12762 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12763 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12764 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12772 rot = imm_expr.X_add_number & 0x1f;
12773 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12775 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12776 (32 - rot) & 0x1f);
12781 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12785 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12786 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12787 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12792 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12794 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12798 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12799 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12800 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12801 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12805 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12807 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12811 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12812 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12813 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12814 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12823 rot = imm_expr.X_add_number & 0x3f;
12824 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12827 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12829 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12834 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12837 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12838 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12841 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12842 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12843 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12851 rot = imm_expr.X_add_number & 0x1f;
12852 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12854 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12859 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12863 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12864 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12865 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12871 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12872 else if (op[2] == 0)
12873 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12876 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12877 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12882 if (imm_expr.X_add_number == 0)
12884 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12889 as_warn (_("instruction %s: result is always false"),
12890 ip->insn_mo->name);
12891 move_register (op[0], 0);
12894 if (CPU_HAS_SEQ (mips_opts.arch)
12895 && -512 <= imm_expr.X_add_number
12896 && imm_expr.X_add_number < 512)
12898 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12899 (int) imm_expr.X_add_number);
12902 if (imm_expr.X_add_number >= 0
12903 && imm_expr.X_add_number < 0x10000)
12904 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12905 else if (imm_expr.X_add_number > -0x8000
12906 && imm_expr.X_add_number < 0)
12908 imm_expr.X_add_number = -imm_expr.X_add_number;
12909 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
12910 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12912 else if (CPU_HAS_SEQ (mips_opts.arch))
12915 load_register (AT, &imm_expr, GPR_SIZE == 64);
12916 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12921 load_register (AT, &imm_expr, GPR_SIZE == 64);
12922 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12925 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12928 case M_SGE: /* X >= Y <==> not (X < Y) */
12934 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12935 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12938 case M_SGE_I: /* X >= I <==> not (X < I) */
12940 if (imm_expr.X_add_number >= -0x8000
12941 && imm_expr.X_add_number < 0x8000)
12942 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12943 op[0], op[1], BFD_RELOC_LO16);
12946 load_register (AT, &imm_expr, GPR_SIZE == 64);
12947 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12951 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12954 case M_SGT: /* X > Y <==> Y < X */
12960 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12963 case M_SGT_I: /* X > I <==> I < X */
12970 load_register (AT, &imm_expr, GPR_SIZE == 64);
12971 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12974 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12980 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12981 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12984 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12991 load_register (AT, &imm_expr, GPR_SIZE == 64);
12992 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12993 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12997 if (imm_expr.X_add_number >= -0x8000
12998 && imm_expr.X_add_number < 0x8000)
13000 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13005 load_register (AT, &imm_expr, GPR_SIZE == 64);
13006 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
13010 if (imm_expr.X_add_number >= -0x8000
13011 && imm_expr.X_add_number < 0x8000)
13013 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
13018 load_register (AT, &imm_expr, GPR_SIZE == 64);
13019 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13024 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13025 else if (op[2] == 0)
13026 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13029 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13030 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13035 if (imm_expr.X_add_number == 0)
13037 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13042 as_warn (_("instruction %s: result is always true"),
13043 ip->insn_mo->name);
13044 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13045 op[0], 0, BFD_RELOC_LO16);
13048 if (CPU_HAS_SEQ (mips_opts.arch)
13049 && -512 <= imm_expr.X_add_number
13050 && imm_expr.X_add_number < 512)
13052 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13053 (int) imm_expr.X_add_number);
13056 if (imm_expr.X_add_number >= 0
13057 && imm_expr.X_add_number < 0x10000)
13059 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13062 else if (imm_expr.X_add_number > -0x8000
13063 && imm_expr.X_add_number < 0)
13065 imm_expr.X_add_number = -imm_expr.X_add_number;
13066 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13067 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13069 else if (CPU_HAS_SEQ (mips_opts.arch))
13072 load_register (AT, &imm_expr, GPR_SIZE == 64);
13073 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13078 load_register (AT, &imm_expr, GPR_SIZE == 64);
13079 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13082 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13097 if (!mips_opts.micromips)
13099 if (imm_expr.X_add_number > -0x200
13100 && imm_expr.X_add_number <= 0x200)
13102 macro_build (NULL, s, "t,r,.", op[0], op[1],
13103 (int) -imm_expr.X_add_number);
13112 if (imm_expr.X_add_number > -0x8000
13113 && imm_expr.X_add_number <= 0x8000)
13115 imm_expr.X_add_number = -imm_expr.X_add_number;
13116 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13121 load_register (AT, &imm_expr, dbl);
13122 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13144 load_register (AT, &imm_expr, GPR_SIZE == 64);
13145 macro_build (NULL, s, "s,t", op[0], AT);
13150 gas_assert (!mips_opts.micromips);
13151 gas_assert (mips_opts.isa == ISA_MIPS1);
13155 * Is the double cfc1 instruction a bug in the mips assembler;
13156 * or is there a reason for it?
13158 start_noreorder ();
13159 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13160 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13161 macro_build (NULL, "nop", "");
13162 expr1.X_add_number = 3;
13163 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13164 expr1.X_add_number = 2;
13165 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13166 macro_build (NULL, "ctc1", "t,G", AT, RA);
13167 macro_build (NULL, "nop", "");
13168 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13170 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13171 macro_build (NULL, "nop", "");
13188 offbits = (mips_opts.micromips ? 12 : 16);
13194 offbits = (mips_opts.micromips ? 12 : 16);
13206 offbits = (mips_opts.micromips ? 12 : 16);
13213 offbits = (mips_opts.micromips ? 12 : 16);
13219 large_offset = !small_offset_p (off, align, offbits);
13221 expr1.X_add_number = 0;
13226 if (small_offset_p (0, align, 16))
13227 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13228 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13231 load_address (tempreg, ep, &used_at);
13233 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13234 tempreg, tempreg, breg);
13236 offset_reloc[0] = BFD_RELOC_LO16;
13237 offset_reloc[1] = BFD_RELOC_UNUSED;
13238 offset_reloc[2] = BFD_RELOC_UNUSED;
13243 else if (!ust && op[0] == breg)
13254 if (!target_big_endian)
13255 ep->X_add_number += off;
13257 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13259 macro_build (ep, s, "t,o(b)", tempreg, -1,
13260 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13262 if (!target_big_endian)
13263 ep->X_add_number -= off;
13265 ep->X_add_number += off;
13267 macro_build (NULL, s2, "t,~(b)",
13268 tempreg, (int) ep->X_add_number, breg);
13270 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13271 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13273 /* If necessary, move the result in tempreg to the final destination. */
13274 if (!ust && op[0] != tempreg)
13276 /* Protect second load's delay slot. */
13278 move_register (op[0], tempreg);
13284 if (target_big_endian == ust)
13285 ep->X_add_number += off;
13286 tempreg = ust || large_offset ? op[0] : AT;
13287 macro_build (ep, s, "t,o(b)", tempreg, -1,
13288 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13290 /* For halfword transfers we need a temporary register to shuffle
13291 bytes. Unfortunately for M_USH_A we have none available before
13292 the next store as AT holds the base address. We deal with this
13293 case by clobbering TREG and then restoring it as with ULH. */
13294 tempreg = ust == large_offset ? op[0] : AT;
13296 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13298 if (target_big_endian == ust)
13299 ep->X_add_number -= off;
13301 ep->X_add_number += off;
13302 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13303 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13305 /* For M_USH_A re-retrieve the LSB. */
13306 if (ust && large_offset)
13308 if (target_big_endian)
13309 ep->X_add_number += off;
13311 ep->X_add_number -= off;
13312 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13313 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13315 /* For ULH and M_USH_A OR the LSB in. */
13316 if (!ust || large_offset)
13318 tempreg = !large_offset ? AT : op[0];
13319 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13320 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13325 /* FIXME: Check if this is one of the itbl macros, since they
13326 are added dynamically. */
13327 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13330 if (!mips_opts.at && used_at)
13331 as_bad (_("macro used $at after \".set noat\""));
13334 /* Implement macros in mips16 mode. */
13337 mips16_macro (struct mips_cl_insn *ip)
13339 const struct mips_operand_array *operands;
13344 const char *s, *s2, *s3;
13345 unsigned int op[MAX_OPERANDS];
13348 mask = ip->insn_mo->mask;
13350 operands = insn_operands (ip);
13351 for (i = 0; i < MAX_OPERANDS; i++)
13352 if (operands->operand[i])
13353 op[i] = insn_extract_operand (ip, operands->operand[i]);
13357 expr1.X_op = O_constant;
13358 expr1.X_op_symbol = NULL;
13359 expr1.X_add_symbol = NULL;
13360 expr1.X_add_number = 1;
13379 start_noreorder ();
13380 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
13381 expr1.X_add_number = 2;
13382 macro_build (&expr1, "bnez", "x,p", op[2]);
13383 macro_build (NULL, "break", "6", 7);
13385 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13386 since that causes an overflow. We should do that as well,
13387 but I don't see how to do the comparisons without a temporary
13390 macro_build (NULL, s, "x", op[0]);
13409 start_noreorder ();
13410 macro_build (NULL, s, "0,x,y", op[1], op[2]);
13411 expr1.X_add_number = 2;
13412 macro_build (&expr1, "bnez", "x,p", op[2]);
13413 macro_build (NULL, "break", "6", 7);
13415 macro_build (NULL, s2, "x", op[0]);
13421 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13422 macro_build (NULL, "mflo", "x", op[0]);
13430 imm_expr.X_add_number = -imm_expr.X_add_number;
13431 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
13435 imm_expr.X_add_number = -imm_expr.X_add_number;
13436 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13440 imm_expr.X_add_number = -imm_expr.X_add_number;
13441 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13463 goto do_reverse_branch;
13467 goto do_reverse_branch;
13479 goto do_reverse_branch;
13490 macro_build (NULL, s, "x,y", op[0], op[1]);
13491 macro_build (&offset_expr, s2, "p");
13518 goto do_addone_branch_i;
13523 goto do_addone_branch_i;
13538 goto do_addone_branch_i;
13544 do_addone_branch_i:
13545 ++imm_expr.X_add_number;
13548 macro_build (&imm_expr, s, s3, op[0]);
13549 macro_build (&offset_expr, s2, "p");
13553 expr1.X_add_number = 0;
13554 macro_build (&expr1, "slti", "x,8", op[1]);
13555 if (op[0] != op[1])
13556 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13557 expr1.X_add_number = 2;
13558 macro_build (&expr1, "bteqz", "p");
13559 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13564 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13565 opcode bits in *OPCODE_EXTRA. */
13567 static struct mips_opcode *
13568 mips_lookup_insn (struct hash_control *hash, const char *start,
13569 ssize_t length, unsigned int *opcode_extra)
13571 char *name, *dot, *p;
13572 unsigned int mask, suffix;
13574 struct mips_opcode *insn;
13576 /* Make a copy of the instruction so that we can fiddle with it. */
13577 name = xstrndup (start, length);
13579 /* Look up the instruction as-is. */
13580 insn = (struct mips_opcode *) hash_find (hash, name);
13584 dot = strchr (name, '.');
13587 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13588 p = mips_parse_vu0_channels (dot + 1, &mask);
13589 if (*p == 0 && mask != 0)
13592 insn = (struct mips_opcode *) hash_find (hash, name);
13594 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13596 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13602 if (mips_opts.micromips)
13604 /* See if there's an instruction size override suffix,
13605 either `16' or `32', at the end of the mnemonic proper,
13606 that defines the operation, i.e. before the first `.'
13607 character if any. Strip it and retry. */
13608 opend = dot != NULL ? dot - name : length;
13609 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13611 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13617 memcpy (name + opend - 2, name + opend, length - opend + 1);
13618 insn = (struct mips_opcode *) hash_find (hash, name);
13621 forced_insn_length = suffix;
13633 /* Assemble an instruction into its binary format. If the instruction
13634 is a macro, set imm_expr and offset_expr to the values associated
13635 with "I" and "A" operands respectively. Otherwise store the value
13636 of the relocatable field (if any) in offset_expr. In both cases
13637 set offset_reloc to the relocation operators applied to offset_expr. */
13640 mips_ip (char *str, struct mips_cl_insn *insn)
13642 const struct mips_opcode *first, *past;
13643 struct hash_control *hash;
13646 struct mips_operand_token *tokens;
13647 unsigned int opcode_extra;
13649 if (mips_opts.micromips)
13651 hash = micromips_op_hash;
13652 past = µmips_opcodes[bfd_micromips_num_opcodes];
13657 past = &mips_opcodes[NUMOPCODES];
13659 forced_insn_length = 0;
13662 /* We first try to match an instruction up to a space or to the end. */
13663 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13666 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13669 set_insn_error (0, _("unrecognized opcode"));
13673 if (strcmp (first->name, "li.s") == 0)
13675 else if (strcmp (first->name, "li.d") == 0)
13679 tokens = mips_parse_arguments (str + end, format);
13683 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13684 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
13685 set_insn_error (0, _("invalid operands"));
13687 obstack_free (&mips_operand_tokens, tokens);
13690 /* As for mips_ip, but used when assembling MIPS16 code.
13691 Also set forced_insn_length to the resulting instruction size in
13692 bytes if the user explicitly requested a small or extended instruction. */
13695 mips16_ip (char *str, struct mips_cl_insn *insn)
13698 struct mips_opcode *first;
13699 struct mips_operand_token *tokens;
13701 forced_insn_length = 0;
13703 for (s = str; ISLOWER (*s); ++s)
13717 if (s[1] == 't' && s[2] == ' ')
13719 forced_insn_length = 2;
13723 else if (s[1] == 'e' && s[2] == ' ')
13725 forced_insn_length = 4;
13729 /* Fall through. */
13731 set_insn_error (0, _("unrecognized opcode"));
13735 if (mips_opts.noautoextend && !forced_insn_length)
13736 forced_insn_length = 2;
13739 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13744 set_insn_error (0, _("unrecognized opcode"));
13748 tokens = mips_parse_arguments (s, 0);
13752 if (!match_mips16_insns (insn, first, tokens))
13753 set_insn_error (0, _("invalid operands"));
13755 obstack_free (&mips_operand_tokens, tokens);
13758 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13759 NBITS is the number of significant bits in VAL. */
13761 static unsigned long
13762 mips16_immed_extend (offsetT val, unsigned int nbits)
13767 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13770 else if (nbits == 15)
13772 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13777 extval = ((val & 0x1f) << 6) | (val & 0x20);
13780 return (extval << 16) | val;
13783 /* Like decode_mips16_operand, but require the operand to be defined and
13784 require it to be an integer. */
13786 static const struct mips_int_operand *
13787 mips16_immed_operand (int type, bfd_boolean extended_p)
13789 const struct mips_operand *operand;
13791 operand = decode_mips16_operand (type, extended_p);
13792 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13794 return (const struct mips_int_operand *) operand;
13797 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13800 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13801 bfd_reloc_code_real_type reloc, offsetT sval)
13803 int min_val, max_val;
13805 min_val = mips_int_operand_min (operand);
13806 max_val = mips_int_operand_max (operand);
13807 if (reloc != BFD_RELOC_UNUSED)
13810 sval = SEXT_16BIT (sval);
13815 return (sval >= min_val
13817 && (sval & ((1 << operand->shift) - 1)) == 0);
13820 /* Install immediate value VAL into MIPS16 instruction *INSN,
13821 extending it if necessary. The instruction in *INSN may
13822 already be extended.
13824 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13825 if none. In the former case, VAL is a 16-bit number with no
13826 defined signedness.
13828 TYPE is the type of the immediate field. USER_INSN_LENGTH
13829 is the length that the user requested, or 0 if none. */
13832 mips16_immed (const char *file, unsigned int line, int type,
13833 bfd_reloc_code_real_type reloc, offsetT val,
13834 unsigned int user_insn_length, unsigned long *insn)
13836 const struct mips_int_operand *operand;
13837 unsigned int uval, length;
13839 operand = mips16_immed_operand (type, FALSE);
13840 if (!mips16_immed_in_range_p (operand, reloc, val))
13842 /* We need an extended instruction. */
13843 if (user_insn_length == 2)
13844 as_bad_where (file, line, _("invalid unextended operand value"));
13846 *insn |= MIPS16_EXTEND;
13848 else if (user_insn_length == 4)
13850 /* The operand doesn't force an unextended instruction to be extended.
13851 Warn if the user wanted an extended instruction anyway. */
13852 *insn |= MIPS16_EXTEND;
13853 as_warn_where (file, line,
13854 _("extended operand requested but not required"));
13857 length = mips16_opcode_length (*insn);
13860 operand = mips16_immed_operand (type, TRUE);
13861 if (!mips16_immed_in_range_p (operand, reloc, val))
13862 as_bad_where (file, line,
13863 _("operand value out of range for instruction"));
13865 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13867 *insn = mips_insert_operand (&operand->root, *insn, uval);
13869 *insn |= mips16_immed_extend (uval, operand->root.size);
13872 struct percent_op_match
13875 bfd_reloc_code_real_type reloc;
13878 static const struct percent_op_match mips_percent_op[] =
13880 {"%lo", BFD_RELOC_LO16},
13881 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13882 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13883 {"%call16", BFD_RELOC_MIPS_CALL16},
13884 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13885 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13886 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13887 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13888 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13889 {"%got", BFD_RELOC_MIPS_GOT16},
13890 {"%gp_rel", BFD_RELOC_GPREL16},
13891 {"%half", BFD_RELOC_16},
13892 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13893 {"%higher", BFD_RELOC_MIPS_HIGHER},
13894 {"%neg", BFD_RELOC_MIPS_SUB},
13895 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13896 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13897 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13898 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13899 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13900 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13901 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13902 {"%hi", BFD_RELOC_HI16_S},
13903 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
13904 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
13907 static const struct percent_op_match mips16_percent_op[] =
13909 {"%lo", BFD_RELOC_MIPS16_LO16},
13910 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13911 {"%got", BFD_RELOC_MIPS16_GOT16},
13912 {"%call16", BFD_RELOC_MIPS16_CALL16},
13913 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13914 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13915 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13916 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13917 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13918 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13919 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13920 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13924 /* Return true if *STR points to a relocation operator. When returning true,
13925 move *STR over the operator and store its relocation code in *RELOC.
13926 Leave both *STR and *RELOC alone when returning false. */
13929 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13931 const struct percent_op_match *percent_op;
13934 if (mips_opts.mips16)
13936 percent_op = mips16_percent_op;
13937 limit = ARRAY_SIZE (mips16_percent_op);
13941 percent_op = mips_percent_op;
13942 limit = ARRAY_SIZE (mips_percent_op);
13945 for (i = 0; i < limit; i++)
13946 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13948 int len = strlen (percent_op[i].str);
13950 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13953 *str += strlen (percent_op[i].str);
13954 *reloc = percent_op[i].reloc;
13956 /* Check whether the output BFD supports this relocation.
13957 If not, issue an error and fall back on something safe. */
13958 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13960 as_bad (_("relocation %s isn't supported by the current ABI"),
13961 percent_op[i].str);
13962 *reloc = BFD_RELOC_UNUSED;
13970 /* Parse string STR as a 16-bit relocatable operand. Store the
13971 expression in *EP and the relocations in the array starting
13972 at RELOC. Return the number of relocation operators used.
13974 On exit, EXPR_END points to the first character after the expression. */
13977 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13980 bfd_reloc_code_real_type reversed_reloc[3];
13981 size_t reloc_index, i;
13982 int crux_depth, str_depth;
13985 /* Search for the start of the main expression, recoding relocations
13986 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13987 of the main expression and with CRUX_DEPTH containing the number
13988 of open brackets at that point. */
13995 crux_depth = str_depth;
13997 /* Skip over whitespace and brackets, keeping count of the number
13999 while (*str == ' ' || *str == '\t' || *str == '(')
14004 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14005 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14007 my_getExpression (ep, crux);
14010 /* Match every open bracket. */
14011 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14015 if (crux_depth > 0)
14016 as_bad (_("unclosed '('"));
14020 if (reloc_index != 0)
14022 prev_reloc_op_frag = frag_now;
14023 for (i = 0; i < reloc_index; i++)
14024 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14027 return reloc_index;
14031 my_getExpression (expressionS *ep, char *str)
14035 save_in = input_line_pointer;
14036 input_line_pointer = str;
14038 expr_end = input_line_pointer;
14039 input_line_pointer = save_in;
14043 md_atof (int type, char *litP, int *sizeP)
14045 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14049 md_number_to_chars (char *buf, valueT val, int n)
14051 if (target_big_endian)
14052 number_to_chars_bigendian (buf, val, n);
14054 number_to_chars_littleendian (buf, val, n);
14057 static int support_64bit_objects(void)
14059 const char **list, **l;
14062 list = bfd_target_list ();
14063 for (l = list; *l != NULL; l++)
14064 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14065 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14067 yes = (*l != NULL);
14072 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14073 NEW_VALUE. Warn if another value was already specified. Note:
14074 we have to defer parsing the -march and -mtune arguments in order
14075 to handle 'from-abi' correctly, since the ABI might be specified
14076 in a later argument. */
14079 mips_set_option_string (const char **string_ptr, const char *new_value)
14081 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14082 as_warn (_("a different %s was already specified, is now %s"),
14083 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14086 *string_ptr = new_value;
14090 md_parse_option (int c, const char *arg)
14094 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14095 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14097 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14098 c == mips_ases[i].option_on);
14104 case OPTION_CONSTRUCT_FLOATS:
14105 mips_disable_float_construction = 0;
14108 case OPTION_NO_CONSTRUCT_FLOATS:
14109 mips_disable_float_construction = 1;
14121 target_big_endian = 1;
14125 target_big_endian = 0;
14131 else if (arg[0] == '0')
14133 else if (arg[0] == '1')
14143 mips_debug = atoi (arg);
14147 file_mips_opts.isa = ISA_MIPS1;
14151 file_mips_opts.isa = ISA_MIPS2;
14155 file_mips_opts.isa = ISA_MIPS3;
14159 file_mips_opts.isa = ISA_MIPS4;
14163 file_mips_opts.isa = ISA_MIPS5;
14166 case OPTION_MIPS32:
14167 file_mips_opts.isa = ISA_MIPS32;
14170 case OPTION_MIPS32R2:
14171 file_mips_opts.isa = ISA_MIPS32R2;
14174 case OPTION_MIPS32R3:
14175 file_mips_opts.isa = ISA_MIPS32R3;
14178 case OPTION_MIPS32R5:
14179 file_mips_opts.isa = ISA_MIPS32R5;
14182 case OPTION_MIPS32R6:
14183 file_mips_opts.isa = ISA_MIPS32R6;
14186 case OPTION_MIPS64R2:
14187 file_mips_opts.isa = ISA_MIPS64R2;
14190 case OPTION_MIPS64R3:
14191 file_mips_opts.isa = ISA_MIPS64R3;
14194 case OPTION_MIPS64R5:
14195 file_mips_opts.isa = ISA_MIPS64R5;
14198 case OPTION_MIPS64R6:
14199 file_mips_opts.isa = ISA_MIPS64R6;
14202 case OPTION_MIPS64:
14203 file_mips_opts.isa = ISA_MIPS64;
14207 mips_set_option_string (&mips_tune_string, arg);
14211 mips_set_option_string (&mips_arch_string, arg);
14215 mips_set_option_string (&mips_arch_string, "4650");
14216 mips_set_option_string (&mips_tune_string, "4650");
14219 case OPTION_NO_M4650:
14223 mips_set_option_string (&mips_arch_string, "4010");
14224 mips_set_option_string (&mips_tune_string, "4010");
14227 case OPTION_NO_M4010:
14231 mips_set_option_string (&mips_arch_string, "4100");
14232 mips_set_option_string (&mips_tune_string, "4100");
14235 case OPTION_NO_M4100:
14239 mips_set_option_string (&mips_arch_string, "3900");
14240 mips_set_option_string (&mips_tune_string, "3900");
14243 case OPTION_NO_M3900:
14246 case OPTION_MICROMIPS:
14247 if (file_mips_opts.mips16 == 1)
14249 as_bad (_("-mmicromips cannot be used with -mips16"));
14252 file_mips_opts.micromips = 1;
14253 mips_no_prev_insn ();
14256 case OPTION_NO_MICROMIPS:
14257 file_mips_opts.micromips = 0;
14258 mips_no_prev_insn ();
14261 case OPTION_MIPS16:
14262 if (file_mips_opts.micromips == 1)
14264 as_bad (_("-mips16 cannot be used with -micromips"));
14267 file_mips_opts.mips16 = 1;
14268 mips_no_prev_insn ();
14271 case OPTION_NO_MIPS16:
14272 file_mips_opts.mips16 = 0;
14273 mips_no_prev_insn ();
14276 case OPTION_FIX_24K:
14280 case OPTION_NO_FIX_24K:
14284 case OPTION_FIX_RM7000:
14285 mips_fix_rm7000 = 1;
14288 case OPTION_NO_FIX_RM7000:
14289 mips_fix_rm7000 = 0;
14292 case OPTION_FIX_LOONGSON2F_JUMP:
14293 mips_fix_loongson2f_jump = TRUE;
14296 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14297 mips_fix_loongson2f_jump = FALSE;
14300 case OPTION_FIX_LOONGSON2F_NOP:
14301 mips_fix_loongson2f_nop = TRUE;
14304 case OPTION_NO_FIX_LOONGSON2F_NOP:
14305 mips_fix_loongson2f_nop = FALSE;
14308 case OPTION_FIX_VR4120:
14309 mips_fix_vr4120 = 1;
14312 case OPTION_NO_FIX_VR4120:
14313 mips_fix_vr4120 = 0;
14316 case OPTION_FIX_VR4130:
14317 mips_fix_vr4130 = 1;
14320 case OPTION_NO_FIX_VR4130:
14321 mips_fix_vr4130 = 0;
14324 case OPTION_FIX_CN63XXP1:
14325 mips_fix_cn63xxp1 = TRUE;
14328 case OPTION_NO_FIX_CN63XXP1:
14329 mips_fix_cn63xxp1 = FALSE;
14332 case OPTION_RELAX_BRANCH:
14333 mips_relax_branch = 1;
14336 case OPTION_NO_RELAX_BRANCH:
14337 mips_relax_branch = 0;
14340 case OPTION_INSN32:
14341 file_mips_opts.insn32 = TRUE;
14344 case OPTION_NO_INSN32:
14345 file_mips_opts.insn32 = FALSE;
14348 case OPTION_MSHARED:
14349 mips_in_shared = TRUE;
14352 case OPTION_MNO_SHARED:
14353 mips_in_shared = FALSE;
14356 case OPTION_MSYM32:
14357 file_mips_opts.sym32 = TRUE;
14360 case OPTION_MNO_SYM32:
14361 file_mips_opts.sym32 = FALSE;
14364 /* When generating ELF code, we permit -KPIC and -call_shared to
14365 select SVR4_PIC, and -non_shared to select no PIC. This is
14366 intended to be compatible with Irix 5. */
14367 case OPTION_CALL_SHARED:
14368 mips_pic = SVR4_PIC;
14369 mips_abicalls = TRUE;
14372 case OPTION_CALL_NONPIC:
14374 mips_abicalls = TRUE;
14377 case OPTION_NON_SHARED:
14379 mips_abicalls = FALSE;
14382 /* The -xgot option tells the assembler to use 32 bit offsets
14383 when accessing the got in SVR4_PIC mode. It is for Irix
14390 g_switch_value = atoi (arg);
14394 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14397 mips_abi = O32_ABI;
14401 mips_abi = N32_ABI;
14405 mips_abi = N64_ABI;
14406 if (!support_64bit_objects())
14407 as_fatal (_("no compiled in support for 64 bit object file format"));
14411 file_mips_opts.gp = 32;
14415 file_mips_opts.gp = 64;
14419 file_mips_opts.fp = 32;
14423 file_mips_opts.fp = 0;
14427 file_mips_opts.fp = 64;
14430 case OPTION_ODD_SPREG:
14431 file_mips_opts.oddspreg = 1;
14434 case OPTION_NO_ODD_SPREG:
14435 file_mips_opts.oddspreg = 0;
14438 case OPTION_SINGLE_FLOAT:
14439 file_mips_opts.single_float = 1;
14442 case OPTION_DOUBLE_FLOAT:
14443 file_mips_opts.single_float = 0;
14446 case OPTION_SOFT_FLOAT:
14447 file_mips_opts.soft_float = 1;
14450 case OPTION_HARD_FLOAT:
14451 file_mips_opts.soft_float = 0;
14455 if (strcmp (arg, "32") == 0)
14456 mips_abi = O32_ABI;
14457 else if (strcmp (arg, "o64") == 0)
14458 mips_abi = O64_ABI;
14459 else if (strcmp (arg, "n32") == 0)
14460 mips_abi = N32_ABI;
14461 else if (strcmp (arg, "64") == 0)
14463 mips_abi = N64_ABI;
14464 if (! support_64bit_objects())
14465 as_fatal (_("no compiled in support for 64 bit object file "
14468 else if (strcmp (arg, "eabi") == 0)
14469 mips_abi = EABI_ABI;
14472 as_fatal (_("invalid abi -mabi=%s"), arg);
14477 case OPTION_M7000_HILO_FIX:
14478 mips_7000_hilo_fix = TRUE;
14481 case OPTION_MNO_7000_HILO_FIX:
14482 mips_7000_hilo_fix = FALSE;
14485 case OPTION_MDEBUG:
14486 mips_flag_mdebug = TRUE;
14489 case OPTION_NO_MDEBUG:
14490 mips_flag_mdebug = FALSE;
14494 mips_flag_pdr = TRUE;
14497 case OPTION_NO_PDR:
14498 mips_flag_pdr = FALSE;
14501 case OPTION_MVXWORKS_PIC:
14502 mips_pic = VXWORKS_PIC;
14506 if (strcmp (arg, "2008") == 0)
14508 else if (strcmp (arg, "legacy") == 0)
14512 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14521 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14526 /* Set up globals to tune for the ISA or processor described by INFO. */
14529 mips_set_tune (const struct mips_cpu_info *info)
14532 mips_tune = info->cpu;
14537 mips_after_parse_args (void)
14539 const struct mips_cpu_info *arch_info = 0;
14540 const struct mips_cpu_info *tune_info = 0;
14542 /* GP relative stuff not working for PE */
14543 if (strncmp (TARGET_OS, "pe", 2) == 0)
14545 if (g_switch_seen && g_switch_value != 0)
14546 as_bad (_("-G not supported in this configuration"));
14547 g_switch_value = 0;
14550 if (mips_abi == NO_ABI)
14551 mips_abi = MIPS_DEFAULT_ABI;
14553 /* The following code determines the architecture.
14554 Similar code was added to GCC 3.3 (see override_options() in
14555 config/mips/mips.c). The GAS and GCC code should be kept in sync
14556 as much as possible. */
14558 if (mips_arch_string != 0)
14559 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14561 if (file_mips_opts.isa != ISA_UNKNOWN)
14563 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14564 ISA level specified by -mipsN, while arch_info->isa contains
14565 the -march selection (if any). */
14566 if (arch_info != 0)
14568 /* -march takes precedence over -mipsN, since it is more descriptive.
14569 There's no harm in specifying both as long as the ISA levels
14571 if (file_mips_opts.isa != arch_info->isa)
14572 as_bad (_("-%s conflicts with the other architecture options,"
14573 " which imply -%s"),
14574 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14575 mips_cpu_info_from_isa (arch_info->isa)->name);
14578 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14581 if (arch_info == 0)
14583 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14584 gas_assert (arch_info);
14587 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14588 as_bad (_("-march=%s is not compatible with the selected ABI"),
14591 file_mips_opts.arch = arch_info->cpu;
14592 file_mips_opts.isa = arch_info->isa;
14594 /* Set up initial mips_opts state. */
14595 mips_opts = file_mips_opts;
14597 /* The register size inference code is now placed in
14598 file_mips_check_options. */
14600 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14602 if (mips_tune_string != 0)
14603 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14605 if (tune_info == 0)
14606 mips_set_tune (arch_info);
14608 mips_set_tune (tune_info);
14610 if (mips_flag_mdebug < 0)
14611 mips_flag_mdebug = 0;
14615 mips_init_after_args (void)
14617 /* initialize opcodes */
14618 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14619 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14623 md_pcrel_from (fixS *fixP)
14625 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14626 switch (fixP->fx_r_type)
14628 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14629 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14630 /* Return the address of the delay slot. */
14633 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14634 case BFD_RELOC_MICROMIPS_JMP:
14635 case BFD_RELOC_MIPS16_16_PCREL_S1:
14636 case BFD_RELOC_16_PCREL_S2:
14637 case BFD_RELOC_MIPS_21_PCREL_S2:
14638 case BFD_RELOC_MIPS_26_PCREL_S2:
14639 case BFD_RELOC_MIPS_JMP:
14640 /* Return the address of the delay slot. */
14643 case BFD_RELOC_MIPS_18_PCREL_S3:
14644 /* Return the aligned address of the doubleword containing
14645 the instruction. */
14653 /* This is called before the symbol table is processed. In order to
14654 work with gcc when using mips-tfile, we must keep all local labels.
14655 However, in other cases, we want to discard them. If we were
14656 called with -g, but we didn't see any debugging information, it may
14657 mean that gcc is smuggling debugging information through to
14658 mips-tfile, in which case we must generate all local labels. */
14661 mips_frob_file_before_adjust (void)
14663 #ifndef NO_ECOFF_DEBUGGING
14664 if (ECOFF_DEBUGGING
14666 && ! ecoff_debugging_seen)
14667 flag_keep_locals = 1;
14671 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14672 the corresponding LO16 reloc. This is called before md_apply_fix and
14673 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14674 relocation operators.
14676 For our purposes, a %lo() expression matches a %got() or %hi()
14679 (a) it refers to the same symbol; and
14680 (b) the offset applied in the %lo() expression is no lower than
14681 the offset applied in the %got() or %hi().
14683 (b) allows us to cope with code like:
14686 lh $4,%lo(foo+2)($4)
14688 ...which is legal on RELA targets, and has a well-defined behaviour
14689 if the user knows that adding 2 to "foo" will not induce a carry to
14692 When several %lo()s match a particular %got() or %hi(), we use the
14693 following rules to distinguish them:
14695 (1) %lo()s with smaller offsets are a better match than %lo()s with
14698 (2) %lo()s with no matching %got() or %hi() are better than those
14699 that already have a matching %got() or %hi().
14701 (3) later %lo()s are better than earlier %lo()s.
14703 These rules are applied in order.
14705 (1) means, among other things, that %lo()s with identical offsets are
14706 chosen if they exist.
14708 (2) means that we won't associate several high-part relocations with
14709 the same low-part relocation unless there's no alternative. Having
14710 several high parts for the same low part is a GNU extension; this rule
14711 allows careful users to avoid it.
14713 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14714 with the last high-part relocation being at the front of the list.
14715 It therefore makes sense to choose the last matching low-part
14716 relocation, all other things being equal. It's also easier
14717 to code that way. */
14720 mips_frob_file (void)
14722 struct mips_hi_fixup *l;
14723 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14725 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14727 segment_info_type *seginfo;
14728 bfd_boolean matched_lo_p;
14729 fixS **hi_pos, **lo_pos, **pos;
14731 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14733 /* If a GOT16 relocation turns out to be against a global symbol,
14734 there isn't supposed to be a matching LO. Ignore %gots against
14735 constants; we'll report an error for those later. */
14736 if (got16_reloc_p (l->fixp->fx_r_type)
14737 && !(l->fixp->fx_addsy
14738 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14741 /* Check quickly whether the next fixup happens to be a matching %lo. */
14742 if (fixup_has_matching_lo_p (l->fixp))
14745 seginfo = seg_info (l->seg);
14747 /* Set HI_POS to the position of this relocation in the chain.
14748 Set LO_POS to the position of the chosen low-part relocation.
14749 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14750 relocation that matches an immediately-preceding high-part
14754 matched_lo_p = FALSE;
14755 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14757 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14759 if (*pos == l->fixp)
14762 if ((*pos)->fx_r_type == looking_for_rtype
14763 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14764 && (*pos)->fx_offset >= l->fixp->fx_offset
14766 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14768 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14771 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14772 && fixup_has_matching_lo_p (*pos));
14775 /* If we found a match, remove the high-part relocation from its
14776 current position and insert it before the low-part relocation.
14777 Make the offsets match so that fixup_has_matching_lo_p()
14780 We don't warn about unmatched high-part relocations since some
14781 versions of gcc have been known to emit dead "lui ...%hi(...)"
14783 if (lo_pos != NULL)
14785 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14786 if (l->fixp->fx_next != *lo_pos)
14788 *hi_pos = l->fixp->fx_next;
14789 l->fixp->fx_next = *lo_pos;
14797 mips_force_relocation (fixS *fixp)
14799 if (generic_force_reloc (fixp))
14802 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14803 so that the linker relaxation can update targets. */
14804 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14805 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14806 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14809 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14810 if (ISA_IS_R6 (file_mips_opts.isa)
14811 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14812 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14813 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14814 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14815 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14816 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14817 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14823 /* Read the instruction associated with RELOC from BUF. */
14825 static unsigned int
14826 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14828 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14829 return read_compressed_insn (buf, 4);
14831 return read_insn (buf);
14834 /* Write instruction INSN to BUF, given that it has been relocated
14838 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14839 unsigned long insn)
14841 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14842 write_compressed_insn (buf, insn, 4);
14844 write_insn (buf, insn);
14847 /* Apply a fixup to the object file. */
14850 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14853 unsigned long insn;
14854 reloc_howto_type *howto;
14856 if (fixP->fx_pcrel)
14857 switch (fixP->fx_r_type)
14859 case BFD_RELOC_16_PCREL_S2:
14860 case BFD_RELOC_MIPS16_16_PCREL_S1:
14861 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14862 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14863 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14864 case BFD_RELOC_32_PCREL:
14865 case BFD_RELOC_MIPS_21_PCREL_S2:
14866 case BFD_RELOC_MIPS_26_PCREL_S2:
14867 case BFD_RELOC_MIPS_18_PCREL_S3:
14868 case BFD_RELOC_MIPS_19_PCREL_S2:
14869 case BFD_RELOC_HI16_S_PCREL:
14870 case BFD_RELOC_LO16_PCREL:
14874 fixP->fx_r_type = BFD_RELOC_32_PCREL;
14878 as_bad_where (fixP->fx_file, fixP->fx_line,
14879 _("PC-relative reference to a different section"));
14883 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14884 that have no MIPS ELF equivalent. */
14885 if (fixP->fx_r_type != BFD_RELOC_8)
14887 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14892 gas_assert (fixP->fx_size == 2
14893 || fixP->fx_size == 4
14894 || fixP->fx_r_type == BFD_RELOC_8
14895 || fixP->fx_r_type == BFD_RELOC_16
14896 || fixP->fx_r_type == BFD_RELOC_64
14897 || fixP->fx_r_type == BFD_RELOC_CTOR
14898 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14899 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14900 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14901 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14902 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
14903 || fixP->fx_r_type == BFD_RELOC_NONE);
14905 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14907 /* Don't treat parts of a composite relocation as done. There are two
14910 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14911 should nevertheless be emitted if the first part is.
14913 (2) In normal usage, composite relocations are never assembly-time
14914 constants. The easiest way of dealing with the pathological
14915 exceptions is to generate a relocation against STN_UNDEF and
14916 leave everything up to the linker. */
14917 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14920 switch (fixP->fx_r_type)
14922 case BFD_RELOC_MIPS_TLS_GD:
14923 case BFD_RELOC_MIPS_TLS_LDM:
14924 case BFD_RELOC_MIPS_TLS_DTPREL32:
14925 case BFD_RELOC_MIPS_TLS_DTPREL64:
14926 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14927 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14928 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14929 case BFD_RELOC_MIPS_TLS_TPREL32:
14930 case BFD_RELOC_MIPS_TLS_TPREL64:
14931 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14932 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14933 case BFD_RELOC_MICROMIPS_TLS_GD:
14934 case BFD_RELOC_MICROMIPS_TLS_LDM:
14935 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14936 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14937 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14938 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14939 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14940 case BFD_RELOC_MIPS16_TLS_GD:
14941 case BFD_RELOC_MIPS16_TLS_LDM:
14942 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14943 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14944 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14945 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14946 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14947 if (fixP->fx_addsy)
14948 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14950 as_bad_where (fixP->fx_file, fixP->fx_line,
14951 _("TLS relocation against a constant"));
14954 case BFD_RELOC_MIPS_JMP:
14955 case BFD_RELOC_MIPS_SHIFT5:
14956 case BFD_RELOC_MIPS_SHIFT6:
14957 case BFD_RELOC_MIPS_GOT_DISP:
14958 case BFD_RELOC_MIPS_GOT_PAGE:
14959 case BFD_RELOC_MIPS_GOT_OFST:
14960 case BFD_RELOC_MIPS_SUB:
14961 case BFD_RELOC_MIPS_INSERT_A:
14962 case BFD_RELOC_MIPS_INSERT_B:
14963 case BFD_RELOC_MIPS_DELETE:
14964 case BFD_RELOC_MIPS_HIGHEST:
14965 case BFD_RELOC_MIPS_HIGHER:
14966 case BFD_RELOC_MIPS_SCN_DISP:
14967 case BFD_RELOC_MIPS_REL16:
14968 case BFD_RELOC_MIPS_RELGOT:
14969 case BFD_RELOC_MIPS_JALR:
14970 case BFD_RELOC_HI16:
14971 case BFD_RELOC_HI16_S:
14972 case BFD_RELOC_LO16:
14973 case BFD_RELOC_GPREL16:
14974 case BFD_RELOC_MIPS_LITERAL:
14975 case BFD_RELOC_MIPS_CALL16:
14976 case BFD_RELOC_MIPS_GOT16:
14977 case BFD_RELOC_GPREL32:
14978 case BFD_RELOC_MIPS_GOT_HI16:
14979 case BFD_RELOC_MIPS_GOT_LO16:
14980 case BFD_RELOC_MIPS_CALL_HI16:
14981 case BFD_RELOC_MIPS_CALL_LO16:
14982 case BFD_RELOC_HI16_S_PCREL:
14983 case BFD_RELOC_LO16_PCREL:
14984 case BFD_RELOC_MIPS16_GPREL:
14985 case BFD_RELOC_MIPS16_GOT16:
14986 case BFD_RELOC_MIPS16_CALL16:
14987 case BFD_RELOC_MIPS16_HI16:
14988 case BFD_RELOC_MIPS16_HI16_S:
14989 case BFD_RELOC_MIPS16_LO16:
14990 case BFD_RELOC_MIPS16_JMP:
14991 case BFD_RELOC_MICROMIPS_JMP:
14992 case BFD_RELOC_MICROMIPS_GOT_DISP:
14993 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14994 case BFD_RELOC_MICROMIPS_GOT_OFST:
14995 case BFD_RELOC_MICROMIPS_SUB:
14996 case BFD_RELOC_MICROMIPS_HIGHEST:
14997 case BFD_RELOC_MICROMIPS_HIGHER:
14998 case BFD_RELOC_MICROMIPS_SCN_DISP:
14999 case BFD_RELOC_MICROMIPS_JALR:
15000 case BFD_RELOC_MICROMIPS_HI16:
15001 case BFD_RELOC_MICROMIPS_HI16_S:
15002 case BFD_RELOC_MICROMIPS_LO16:
15003 case BFD_RELOC_MICROMIPS_GPREL16:
15004 case BFD_RELOC_MICROMIPS_LITERAL:
15005 case BFD_RELOC_MICROMIPS_CALL16:
15006 case BFD_RELOC_MICROMIPS_GOT16:
15007 case BFD_RELOC_MICROMIPS_GOT_HI16:
15008 case BFD_RELOC_MICROMIPS_GOT_LO16:
15009 case BFD_RELOC_MICROMIPS_CALL_HI16:
15010 case BFD_RELOC_MICROMIPS_CALL_LO16:
15011 case BFD_RELOC_MIPS_EH:
15016 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15018 insn = read_reloc_insn (buf, fixP->fx_r_type);
15019 if (mips16_reloc_p (fixP->fx_r_type))
15020 insn |= mips16_immed_extend (value, 16);
15022 insn |= (value & 0xffff);
15023 write_reloc_insn (buf, fixP->fx_r_type, insn);
15026 as_bad_where (fixP->fx_file, fixP->fx_line,
15027 _("unsupported constant in relocation"));
15032 /* This is handled like BFD_RELOC_32, but we output a sign
15033 extended value if we are only 32 bits. */
15036 if (8 <= sizeof (valueT))
15037 md_number_to_chars (buf, *valP, 8);
15042 if ((*valP & 0x80000000) != 0)
15046 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15047 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15052 case BFD_RELOC_RVA:
15054 case BFD_RELOC_32_PCREL:
15057 /* If we are deleting this reloc entry, we must fill in the
15058 value now. This can happen if we have a .word which is not
15059 resolved when it appears but is later defined. */
15061 md_number_to_chars (buf, *valP, fixP->fx_size);
15064 case BFD_RELOC_MIPS_21_PCREL_S2:
15065 if ((*valP & 0x3) != 0)
15066 as_bad_where (fixP->fx_file, fixP->fx_line,
15067 _("branch to misaligned address (%lx)"), (long) *valP);
15068 if (!fixP->fx_done)
15071 if (*valP + 0x400000 <= 0x7fffff)
15073 insn = read_insn (buf);
15074 insn |= (*valP >> 2) & 0x1fffff;
15075 write_insn (buf, insn);
15078 as_bad_where (fixP->fx_file, fixP->fx_line,
15079 _("branch out of range"));
15082 case BFD_RELOC_MIPS_26_PCREL_S2:
15083 if ((*valP & 0x3) != 0)
15084 as_bad_where (fixP->fx_file, fixP->fx_line,
15085 _("branch to misaligned address (%lx)"), (long) *valP);
15086 if (!fixP->fx_done)
15089 if (*valP + 0x8000000 <= 0xfffffff)
15091 insn = read_insn (buf);
15092 insn |= (*valP >> 2) & 0x3ffffff;
15093 write_insn (buf, insn);
15096 as_bad_where (fixP->fx_file, fixP->fx_line,
15097 _("branch out of range"));
15100 case BFD_RELOC_MIPS_18_PCREL_S3:
15101 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15102 as_bad_where (fixP->fx_file, fixP->fx_line,
15103 _("PC-relative access using misaligned symbol (%lx)"),
15104 (long) S_GET_VALUE (fixP->fx_addsy));
15105 if ((fixP->fx_offset & 0x7) != 0)
15106 as_bad_where (fixP->fx_file, fixP->fx_line,
15107 _("PC-relative access using misaligned offset (%lx)"),
15108 (long) fixP->fx_offset);
15109 if (!fixP->fx_done)
15112 if (*valP + 0x100000 <= 0x1fffff)
15114 insn = read_insn (buf);
15115 insn |= (*valP >> 3) & 0x3ffff;
15116 write_insn (buf, insn);
15119 as_bad_where (fixP->fx_file, fixP->fx_line,
15120 _("PC-relative access out of range"));
15123 case BFD_RELOC_MIPS_19_PCREL_S2:
15124 if ((*valP & 0x3) != 0)
15125 as_bad_where (fixP->fx_file, fixP->fx_line,
15126 _("PC-relative access to misaligned address (%lx)"),
15128 if (!fixP->fx_done)
15131 if (*valP + 0x100000 <= 0x1fffff)
15133 insn = read_insn (buf);
15134 insn |= (*valP >> 2) & 0x7ffff;
15135 write_insn (buf, insn);
15138 as_bad_where (fixP->fx_file, fixP->fx_line,
15139 _("PC-relative access out of range"));
15142 case BFD_RELOC_16_PCREL_S2:
15143 if ((*valP & 0x3) != 0)
15144 as_bad_where (fixP->fx_file, fixP->fx_line,
15145 _("branch to misaligned address (%lx)"), (long) *valP);
15147 /* We need to save the bits in the instruction since fixup_segment()
15148 might be deleting the relocation entry (i.e., a branch within
15149 the current segment). */
15150 if (! fixP->fx_done)
15153 /* Update old instruction data. */
15154 insn = read_insn (buf);
15156 if (*valP + 0x20000 <= 0x3ffff)
15158 insn |= (*valP >> 2) & 0xffff;
15159 write_insn (buf, insn);
15161 else if (mips_pic == NO_PIC
15163 && fixP->fx_frag->fr_address >= text_section->vma
15164 && (fixP->fx_frag->fr_address
15165 < text_section->vma + bfd_get_section_size (text_section))
15166 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15167 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15168 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15170 /* The branch offset is too large. If this is an
15171 unconditional branch, and we are not generating PIC code,
15172 we can convert it to an absolute jump instruction. */
15173 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15174 insn = 0x0c000000; /* jal */
15176 insn = 0x08000000; /* j */
15177 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15179 fixP->fx_addsy = section_symbol (text_section);
15180 *valP += md_pcrel_from (fixP);
15181 write_insn (buf, insn);
15185 /* If we got here, we have branch-relaxation disabled,
15186 and there's nothing we can do to fix this instruction
15187 without turning it into a longer sequence. */
15188 as_bad_where (fixP->fx_file, fixP->fx_line,
15189 _("branch out of range"));
15193 case BFD_RELOC_MIPS16_16_PCREL_S1:
15194 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15195 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15196 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15197 /* We adjust the offset back to even. */
15198 if ((*valP & 0x1) != 0)
15201 if (! fixP->fx_done)
15204 /* Should never visit here, because we keep the relocation. */
15208 case BFD_RELOC_VTABLE_INHERIT:
15211 && !S_IS_DEFINED (fixP->fx_addsy)
15212 && !S_IS_WEAK (fixP->fx_addsy))
15213 S_SET_WEAK (fixP->fx_addsy);
15216 case BFD_RELOC_NONE:
15217 case BFD_RELOC_VTABLE_ENTRY:
15225 /* Remember value for tc_gen_reloc. */
15226 fixP->fx_addnumber = *valP;
15236 c = get_symbol_name (&name);
15237 p = (symbolS *) symbol_find_or_make (name);
15238 (void) restore_line_pointer (c);
15242 /* Align the current frag to a given power of two. If a particular
15243 fill byte should be used, FILL points to an integer that contains
15244 that byte, otherwise FILL is null.
15246 This function used to have the comment:
15248 The MIPS assembler also automatically adjusts any preceding label.
15250 The implementation therefore applied the adjustment to a maximum of
15251 one label. However, other label adjustments are applied to batches
15252 of labels, and adjusting just one caused problems when new labels
15253 were added for the sake of debugging or unwind information.
15254 We therefore adjust all preceding labels (given as LABELS) instead. */
15257 mips_align (int to, int *fill, struct insn_label_list *labels)
15259 mips_emit_delays ();
15260 mips_record_compressed_mode ();
15261 if (fill == NULL && subseg_text_p (now_seg))
15262 frag_align_code (to, 0);
15264 frag_align (to, fill ? *fill : 0, 0);
15265 record_alignment (now_seg, to);
15266 mips_move_labels (labels, FALSE);
15269 /* Align to a given power of two. .align 0 turns off the automatic
15270 alignment used by the data creating pseudo-ops. */
15273 s_align (int x ATTRIBUTE_UNUSED)
15275 int temp, fill_value, *fill_ptr;
15276 long max_alignment = 28;
15278 /* o Note that the assembler pulls down any immediately preceding label
15279 to the aligned address.
15280 o It's not documented but auto alignment is reinstated by
15281 a .align pseudo instruction.
15282 o Note also that after auto alignment is turned off the mips assembler
15283 issues an error on attempt to assemble an improperly aligned data item.
15286 temp = get_absolute_expression ();
15287 if (temp > max_alignment)
15288 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15291 as_warn (_("alignment negative, 0 assumed"));
15294 if (*input_line_pointer == ',')
15296 ++input_line_pointer;
15297 fill_value = get_absolute_expression ();
15298 fill_ptr = &fill_value;
15304 segment_info_type *si = seg_info (now_seg);
15305 struct insn_label_list *l = si->label_list;
15306 /* Auto alignment should be switched on by next section change. */
15308 mips_align (temp, fill_ptr, l);
15315 demand_empty_rest_of_line ();
15319 s_change_sec (int sec)
15323 /* The ELF backend needs to know that we are changing sections, so
15324 that .previous works correctly. We could do something like check
15325 for an obj_section_change_hook macro, but that might be confusing
15326 as it would not be appropriate to use it in the section changing
15327 functions in read.c, since obj-elf.c intercepts those. FIXME:
15328 This should be cleaner, somehow. */
15329 obj_elf_section_change_hook ();
15331 mips_emit_delays ();
15342 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15343 demand_empty_rest_of_line ();
15347 seg = subseg_new (RDATA_SECTION_NAME,
15348 (subsegT) get_absolute_expression ());
15349 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15350 | SEC_READONLY | SEC_RELOC
15352 if (strncmp (TARGET_OS, "elf", 3) != 0)
15353 record_alignment (seg, 4);
15354 demand_empty_rest_of_line ();
15358 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15359 bfd_set_section_flags (stdoutput, seg,
15360 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15361 if (strncmp (TARGET_OS, "elf", 3) != 0)
15362 record_alignment (seg, 4);
15363 demand_empty_rest_of_line ();
15367 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15368 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15369 if (strncmp (TARGET_OS, "elf", 3) != 0)
15370 record_alignment (seg, 4);
15371 demand_empty_rest_of_line ();
15379 s_change_section (int ignore ATTRIBUTE_UNUSED)
15382 char *section_name;
15387 int section_entry_size;
15388 int section_alignment;
15390 saved_ilp = input_line_pointer;
15391 endc = get_symbol_name (§ion_name);
15392 c = (endc == '"' ? input_line_pointer[1] : endc);
15394 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
15396 /* Do we have .section Name<,"flags">? */
15397 if (c != ',' || (c == ',' && next_c == '"'))
15399 /* Just after name is now '\0'. */
15400 (void) restore_line_pointer (endc);
15401 input_line_pointer = saved_ilp;
15402 obj_elf_section (ignore);
15406 section_name = xstrdup (section_name);
15407 c = restore_line_pointer (endc);
15409 input_line_pointer++;
15411 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15413 section_type = get_absolute_expression ();
15417 if (*input_line_pointer++ == ',')
15418 section_flag = get_absolute_expression ();
15422 if (*input_line_pointer++ == ',')
15423 section_entry_size = get_absolute_expression ();
15425 section_entry_size = 0;
15427 if (*input_line_pointer++ == ',')
15428 section_alignment = get_absolute_expression ();
15430 section_alignment = 0;
15432 /* FIXME: really ignore? */
15433 (void) section_alignment;
15435 /* When using the generic form of .section (as implemented by obj-elf.c),
15436 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15437 traditionally had to fall back on the more common @progbits instead.
15439 There's nothing really harmful in this, since bfd will correct
15440 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15441 means that, for backwards compatibility, the special_section entries
15442 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15444 Even so, we shouldn't force users of the MIPS .section syntax to
15445 incorrectly label the sections as SHT_PROGBITS. The best compromise
15446 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15447 generic type-checking code. */
15448 if (section_type == SHT_MIPS_DWARF)
15449 section_type = SHT_PROGBITS;
15451 obj_elf_change_section (section_name, section_type, section_flag,
15452 section_entry_size, 0, 0, 0);
15454 if (now_seg->name != section_name)
15455 free (section_name);
15459 mips_enable_auto_align (void)
15465 s_cons (int log_size)
15467 segment_info_type *si = seg_info (now_seg);
15468 struct insn_label_list *l = si->label_list;
15470 mips_emit_delays ();
15471 if (log_size > 0 && auto_align)
15472 mips_align (log_size, 0, l);
15473 cons (1 << log_size);
15474 mips_clear_insn_labels ();
15478 s_float_cons (int type)
15480 segment_info_type *si = seg_info (now_seg);
15481 struct insn_label_list *l = si->label_list;
15483 mips_emit_delays ();
15488 mips_align (3, 0, l);
15490 mips_align (2, 0, l);
15494 mips_clear_insn_labels ();
15497 /* Handle .globl. We need to override it because on Irix 5 you are
15500 where foo is an undefined symbol, to mean that foo should be
15501 considered to be the address of a function. */
15504 s_mips_globl (int x ATTRIBUTE_UNUSED)
15513 c = get_symbol_name (&name);
15514 symbolP = symbol_find_or_make (name);
15515 S_SET_EXTERNAL (symbolP);
15517 *input_line_pointer = c;
15518 SKIP_WHITESPACE_AFTER_NAME ();
15520 /* On Irix 5, every global symbol that is not explicitly labelled as
15521 being a function is apparently labelled as being an object. */
15524 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15525 && (*input_line_pointer != ','))
15530 c = get_symbol_name (&secname);
15531 sec = bfd_get_section_by_name (stdoutput, secname);
15533 as_bad (_("%s: no such section"), secname);
15534 (void) restore_line_pointer (c);
15536 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15537 flag = BSF_FUNCTION;
15540 symbol_get_bfdsym (symbolP)->flags |= flag;
15542 c = *input_line_pointer;
15545 input_line_pointer++;
15546 SKIP_WHITESPACE ();
15547 if (is_end_of_line[(unsigned char) *input_line_pointer])
15553 demand_empty_rest_of_line ();
15557 s_option (int x ATTRIBUTE_UNUSED)
15562 c = get_symbol_name (&opt);
15566 /* FIXME: What does this mean? */
15568 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
15572 i = atoi (opt + 3);
15573 if (i != 0 && i != 2)
15574 as_bad (_(".option pic%d not supported"), i);
15575 else if (mips_pic == VXWORKS_PIC)
15576 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
15581 mips_pic = SVR4_PIC;
15582 mips_abicalls = TRUE;
15585 if (mips_pic == SVR4_PIC)
15587 if (g_switch_seen && g_switch_value != 0)
15588 as_warn (_("-G may not be used with SVR4 PIC code"));
15589 g_switch_value = 0;
15590 bfd_set_gp_size (stdoutput, 0);
15594 as_warn (_("unrecognized option \"%s\""), opt);
15596 (void) restore_line_pointer (c);
15597 demand_empty_rest_of_line ();
15600 /* This structure is used to hold a stack of .set values. */
15602 struct mips_option_stack
15604 struct mips_option_stack *next;
15605 struct mips_set_options options;
15608 static struct mips_option_stack *mips_opts_stack;
15610 /* Return status for .set/.module option handling. */
15612 enum code_option_type
15614 /* Unrecognized option. */
15615 OPTION_TYPE_BAD = -1,
15617 /* Ordinary option. */
15618 OPTION_TYPE_NORMAL,
15620 /* ISA changing option. */
15624 /* Handle common .set/.module options. Return status indicating option
15627 static enum code_option_type
15628 parse_code_option (char * name)
15630 bfd_boolean isa_set = FALSE;
15631 const struct mips_ase *ase;
15633 if (strncmp (name, "at=", 3) == 0)
15635 char *s = name + 3;
15637 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15638 as_bad (_("unrecognized register name `%s'"), s);
15640 else if (strcmp (name, "at") == 0)
15641 mips_opts.at = ATREG;
15642 else if (strcmp (name, "noat") == 0)
15643 mips_opts.at = ZERO;
15644 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15645 mips_opts.nomove = 0;
15646 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15647 mips_opts.nomove = 1;
15648 else if (strcmp (name, "bopt") == 0)
15649 mips_opts.nobopt = 0;
15650 else if (strcmp (name, "nobopt") == 0)
15651 mips_opts.nobopt = 1;
15652 else if (strcmp (name, "gp=32") == 0)
15654 else if (strcmp (name, "gp=64") == 0)
15656 else if (strcmp (name, "fp=32") == 0)
15658 else if (strcmp (name, "fp=xx") == 0)
15660 else if (strcmp (name, "fp=64") == 0)
15662 else if (strcmp (name, "softfloat") == 0)
15663 mips_opts.soft_float = 1;
15664 else if (strcmp (name, "hardfloat") == 0)
15665 mips_opts.soft_float = 0;
15666 else if (strcmp (name, "singlefloat") == 0)
15667 mips_opts.single_float = 1;
15668 else if (strcmp (name, "doublefloat") == 0)
15669 mips_opts.single_float = 0;
15670 else if (strcmp (name, "nooddspreg") == 0)
15671 mips_opts.oddspreg = 0;
15672 else if (strcmp (name, "oddspreg") == 0)
15673 mips_opts.oddspreg = 1;
15674 else if (strcmp (name, "mips16") == 0
15675 || strcmp (name, "MIPS-16") == 0)
15676 mips_opts.mips16 = 1;
15677 else if (strcmp (name, "nomips16") == 0
15678 || strcmp (name, "noMIPS-16") == 0)
15679 mips_opts.mips16 = 0;
15680 else if (strcmp (name, "micromips") == 0)
15681 mips_opts.micromips = 1;
15682 else if (strcmp (name, "nomicromips") == 0)
15683 mips_opts.micromips = 0;
15684 else if (name[0] == 'n'
15686 && (ase = mips_lookup_ase (name + 2)))
15687 mips_set_ase (ase, &mips_opts, FALSE);
15688 else if ((ase = mips_lookup_ase (name)))
15689 mips_set_ase (ase, &mips_opts, TRUE);
15690 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
15692 /* Permit the user to change the ISA and architecture on the fly.
15693 Needless to say, misuse can cause serious problems. */
15694 if (strncmp (name, "arch=", 5) == 0)
15696 const struct mips_cpu_info *p;
15698 p = mips_parse_cpu ("internal use", name + 5);
15700 as_bad (_("unknown architecture %s"), name + 5);
15703 mips_opts.arch = p->cpu;
15704 mips_opts.isa = p->isa;
15708 else if (strncmp (name, "mips", 4) == 0)
15710 const struct mips_cpu_info *p;
15712 p = mips_parse_cpu ("internal use", name);
15714 as_bad (_("unknown ISA level %s"), name + 4);
15717 mips_opts.arch = p->cpu;
15718 mips_opts.isa = p->isa;
15723 as_bad (_("unknown ISA or architecture %s"), name);
15725 else if (strcmp (name, "autoextend") == 0)
15726 mips_opts.noautoextend = 0;
15727 else if (strcmp (name, "noautoextend") == 0)
15728 mips_opts.noautoextend = 1;
15729 else if (strcmp (name, "insn32") == 0)
15730 mips_opts.insn32 = TRUE;
15731 else if (strcmp (name, "noinsn32") == 0)
15732 mips_opts.insn32 = FALSE;
15733 else if (strcmp (name, "sym32") == 0)
15734 mips_opts.sym32 = TRUE;
15735 else if (strcmp (name, "nosym32") == 0)
15736 mips_opts.sym32 = FALSE;
15738 return OPTION_TYPE_BAD;
15740 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
15743 /* Handle the .set pseudo-op. */
15746 s_mipsset (int x ATTRIBUTE_UNUSED)
15748 enum code_option_type type = OPTION_TYPE_NORMAL;
15749 char *name = input_line_pointer, ch;
15751 file_mips_check_options ();
15753 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15754 ++input_line_pointer;
15755 ch = *input_line_pointer;
15756 *input_line_pointer = '\0';
15758 if (strchr (name, ','))
15760 /* Generic ".set" directive; use the generic handler. */
15761 *input_line_pointer = ch;
15762 input_line_pointer = name;
15767 if (strcmp (name, "reorder") == 0)
15769 if (mips_opts.noreorder)
15772 else if (strcmp (name, "noreorder") == 0)
15774 if (!mips_opts.noreorder)
15775 start_noreorder ();
15777 else if (strcmp (name, "macro") == 0)
15778 mips_opts.warn_about_macros = 0;
15779 else if (strcmp (name, "nomacro") == 0)
15781 if (mips_opts.noreorder == 0)
15782 as_bad (_("`noreorder' must be set before `nomacro'"));
15783 mips_opts.warn_about_macros = 1;
15785 else if (strcmp (name, "gp=default") == 0)
15786 mips_opts.gp = file_mips_opts.gp;
15787 else if (strcmp (name, "fp=default") == 0)
15788 mips_opts.fp = file_mips_opts.fp;
15789 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15791 mips_opts.isa = file_mips_opts.isa;
15792 mips_opts.arch = file_mips_opts.arch;
15793 mips_opts.gp = file_mips_opts.gp;
15794 mips_opts.fp = file_mips_opts.fp;
15796 else if (strcmp (name, "push") == 0)
15798 struct mips_option_stack *s;
15800 s = XNEW (struct mips_option_stack);
15801 s->next = mips_opts_stack;
15802 s->options = mips_opts;
15803 mips_opts_stack = s;
15805 else if (strcmp (name, "pop") == 0)
15807 struct mips_option_stack *s;
15809 s = mips_opts_stack;
15811 as_bad (_(".set pop with no .set push"));
15814 /* If we're changing the reorder mode we need to handle
15815 delay slots correctly. */
15816 if (s->options.noreorder && ! mips_opts.noreorder)
15817 start_noreorder ();
15818 else if (! s->options.noreorder && mips_opts.noreorder)
15821 mips_opts = s->options;
15822 mips_opts_stack = s->next;
15828 type = parse_code_option (name);
15829 if (type == OPTION_TYPE_BAD)
15830 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
15833 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15834 registers based on what is supported by the arch/cpu. */
15835 if (type == OPTION_TYPE_ISA)
15837 switch (mips_opts.isa)
15842 /* MIPS I cannot support FPXX. */
15844 /* fall-through. */
15851 if (mips_opts.fp != 0)
15867 if (mips_opts.fp != 0)
15869 if (mips_opts.arch == CPU_R5900)
15876 as_bad (_("unknown ISA level %s"), name + 4);
15881 mips_check_options (&mips_opts, FALSE);
15883 mips_check_isa_supports_ases ();
15884 *input_line_pointer = ch;
15885 demand_empty_rest_of_line ();
15888 /* Handle the .module pseudo-op. */
15891 s_module (int ignore ATTRIBUTE_UNUSED)
15893 char *name = input_line_pointer, ch;
15895 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15896 ++input_line_pointer;
15897 ch = *input_line_pointer;
15898 *input_line_pointer = '\0';
15900 if (!file_mips_opts_checked)
15902 if (parse_code_option (name) == OPTION_TYPE_BAD)
15903 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
15905 /* Update module level settings from mips_opts. */
15906 file_mips_opts = mips_opts;
15909 as_bad (_(".module is not permitted after generating code"));
15911 *input_line_pointer = ch;
15912 demand_empty_rest_of_line ();
15915 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15916 .option pic2. It means to generate SVR4 PIC calls. */
15919 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15921 mips_pic = SVR4_PIC;
15922 mips_abicalls = TRUE;
15924 if (g_switch_seen && g_switch_value != 0)
15925 as_warn (_("-G may not be used with SVR4 PIC code"));
15926 g_switch_value = 0;
15928 bfd_set_gp_size (stdoutput, 0);
15929 demand_empty_rest_of_line ();
15932 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15933 PIC code. It sets the $gp register for the function based on the
15934 function address, which is in the register named in the argument.
15935 This uses a relocation against _gp_disp, which is handled specially
15936 by the linker. The result is:
15937 lui $gp,%hi(_gp_disp)
15938 addiu $gp,$gp,%lo(_gp_disp)
15939 addu $gp,$gp,.cpload argument
15940 The .cpload argument is normally $25 == $t9.
15942 The -mno-shared option changes this to:
15943 lui $gp,%hi(__gnu_local_gp)
15944 addiu $gp,$gp,%lo(__gnu_local_gp)
15945 and the argument is ignored. This saves an instruction, but the
15946 resulting code is not position independent; it uses an absolute
15947 address for __gnu_local_gp. Thus code assembled with -mno-shared
15948 can go into an ordinary executable, but not into a shared library. */
15951 s_cpload (int ignore ATTRIBUTE_UNUSED)
15957 file_mips_check_options ();
15959 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15960 .cpload is ignored. */
15961 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15967 if (mips_opts.mips16)
15969 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15970 ignore_rest_of_line ();
15974 /* .cpload should be in a .set noreorder section. */
15975 if (mips_opts.noreorder == 0)
15976 as_warn (_(".cpload not in noreorder section"));
15978 reg = tc_get_register (0);
15980 /* If we need to produce a 64-bit address, we are better off using
15981 the default instruction sequence. */
15982 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15984 ex.X_op = O_symbol;
15985 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15987 ex.X_op_symbol = NULL;
15988 ex.X_add_number = 0;
15990 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15991 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15993 mips_mark_labels ();
15994 mips_assembling_insn = TRUE;
15997 macro_build_lui (&ex, mips_gp_register);
15998 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15999 mips_gp_register, BFD_RELOC_LO16);
16001 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16002 mips_gp_register, reg);
16005 mips_assembling_insn = FALSE;
16006 demand_empty_rest_of_line ();
16009 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16010 .cpsetup $reg1, offset|$reg2, label
16012 If offset is given, this results in:
16013 sd $gp, offset($sp)
16014 lui $gp, %hi(%neg(%gp_rel(label)))
16015 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16016 daddu $gp, $gp, $reg1
16018 If $reg2 is given, this results in:
16020 lui $gp, %hi(%neg(%gp_rel(label)))
16021 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16022 daddu $gp, $gp, $reg1
16023 $reg1 is normally $25 == $t9.
16025 The -mno-shared option replaces the last three instructions with
16027 addiu $gp,$gp,%lo(_gp) */
16030 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16032 expressionS ex_off;
16033 expressionS ex_sym;
16036 file_mips_check_options ();
16038 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16039 We also need NewABI support. */
16040 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16046 if (mips_opts.mips16)
16048 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16049 ignore_rest_of_line ();
16053 reg1 = tc_get_register (0);
16054 SKIP_WHITESPACE ();
16055 if (*input_line_pointer != ',')
16057 as_bad (_("missing argument separator ',' for .cpsetup"));
16061 ++input_line_pointer;
16062 SKIP_WHITESPACE ();
16063 if (*input_line_pointer == '$')
16065 mips_cpreturn_register = tc_get_register (0);
16066 mips_cpreturn_offset = -1;
16070 mips_cpreturn_offset = get_absolute_expression ();
16071 mips_cpreturn_register = -1;
16073 SKIP_WHITESPACE ();
16074 if (*input_line_pointer != ',')
16076 as_bad (_("missing argument separator ',' for .cpsetup"));
16080 ++input_line_pointer;
16081 SKIP_WHITESPACE ();
16082 expression (&ex_sym);
16084 mips_mark_labels ();
16085 mips_assembling_insn = TRUE;
16088 if (mips_cpreturn_register == -1)
16090 ex_off.X_op = O_constant;
16091 ex_off.X_add_symbol = NULL;
16092 ex_off.X_op_symbol = NULL;
16093 ex_off.X_add_number = mips_cpreturn_offset;
16095 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16096 BFD_RELOC_LO16, SP);
16099 move_register (mips_cpreturn_register, mips_gp_register);
16101 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16103 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16104 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16107 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16108 mips_gp_register, -1, BFD_RELOC_GPREL16,
16109 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16111 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16112 mips_gp_register, reg1);
16118 ex.X_op = O_symbol;
16119 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16120 ex.X_op_symbol = NULL;
16121 ex.X_add_number = 0;
16123 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16124 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16126 macro_build_lui (&ex, mips_gp_register);
16127 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16128 mips_gp_register, BFD_RELOC_LO16);
16133 mips_assembling_insn = FALSE;
16134 demand_empty_rest_of_line ();
16138 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16140 file_mips_check_options ();
16142 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16143 .cplocal is ignored. */
16144 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16150 if (mips_opts.mips16)
16152 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16153 ignore_rest_of_line ();
16157 mips_gp_register = tc_get_register (0);
16158 demand_empty_rest_of_line ();
16161 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16162 offset from $sp. The offset is remembered, and after making a PIC
16163 call $gp is restored from that location. */
16166 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16170 file_mips_check_options ();
16172 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16173 .cprestore is ignored. */
16174 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16180 if (mips_opts.mips16)
16182 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16183 ignore_rest_of_line ();
16187 mips_cprestore_offset = get_absolute_expression ();
16188 mips_cprestore_valid = 1;
16190 ex.X_op = O_constant;
16191 ex.X_add_symbol = NULL;
16192 ex.X_op_symbol = NULL;
16193 ex.X_add_number = mips_cprestore_offset;
16195 mips_mark_labels ();
16196 mips_assembling_insn = TRUE;
16199 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16200 SP, HAVE_64BIT_ADDRESSES);
16203 mips_assembling_insn = FALSE;
16204 demand_empty_rest_of_line ();
16207 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16208 was given in the preceding .cpsetup, it results in:
16209 ld $gp, offset($sp)
16211 If a register $reg2 was given there, it results in:
16212 or $gp, $reg2, $0 */
16215 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16219 file_mips_check_options ();
16221 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16222 We also need NewABI support. */
16223 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16229 if (mips_opts.mips16)
16231 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16232 ignore_rest_of_line ();
16236 mips_mark_labels ();
16237 mips_assembling_insn = TRUE;
16240 if (mips_cpreturn_register == -1)
16242 ex.X_op = O_constant;
16243 ex.X_add_symbol = NULL;
16244 ex.X_op_symbol = NULL;
16245 ex.X_add_number = mips_cpreturn_offset;
16247 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16250 move_register (mips_gp_register, mips_cpreturn_register);
16254 mips_assembling_insn = FALSE;
16255 demand_empty_rest_of_line ();
16258 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16259 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16260 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16261 debug information or MIPS16 TLS. */
16264 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16265 bfd_reloc_code_real_type rtype)
16272 if (ex.X_op != O_symbol)
16274 as_bad (_("unsupported use of %s"), dirstr);
16275 ignore_rest_of_line ();
16278 p = frag_more (bytes);
16279 md_number_to_chars (p, 0, bytes);
16280 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16281 demand_empty_rest_of_line ();
16282 mips_clear_insn_labels ();
16285 /* Handle .dtprelword. */
16288 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16290 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16293 /* Handle .dtpreldword. */
16296 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16298 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16301 /* Handle .tprelword. */
16304 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16306 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16309 /* Handle .tpreldword. */
16312 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16314 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16317 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16318 code. It sets the offset to use in gp_rel relocations. */
16321 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16323 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16324 We also need NewABI support. */
16325 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16331 mips_gprel_offset = get_absolute_expression ();
16333 demand_empty_rest_of_line ();
16336 /* Handle the .gpword pseudo-op. This is used when generating PIC
16337 code. It generates a 32 bit GP relative reloc. */
16340 s_gpword (int ignore ATTRIBUTE_UNUSED)
16342 segment_info_type *si;
16343 struct insn_label_list *l;
16347 /* When not generating PIC code, this is treated as .word. */
16348 if (mips_pic != SVR4_PIC)
16354 si = seg_info (now_seg);
16355 l = si->label_list;
16356 mips_emit_delays ();
16358 mips_align (2, 0, l);
16361 mips_clear_insn_labels ();
16363 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16365 as_bad (_("unsupported use of .gpword"));
16366 ignore_rest_of_line ();
16370 md_number_to_chars (p, 0, 4);
16371 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16372 BFD_RELOC_GPREL32);
16374 demand_empty_rest_of_line ();
16378 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16380 segment_info_type *si;
16381 struct insn_label_list *l;
16385 /* When not generating PIC code, this is treated as .dword. */
16386 if (mips_pic != SVR4_PIC)
16392 si = seg_info (now_seg);
16393 l = si->label_list;
16394 mips_emit_delays ();
16396 mips_align (3, 0, l);
16399 mips_clear_insn_labels ();
16401 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16403 as_bad (_("unsupported use of .gpdword"));
16404 ignore_rest_of_line ();
16408 md_number_to_chars (p, 0, 8);
16409 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16410 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16412 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16413 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16414 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16416 demand_empty_rest_of_line ();
16419 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16420 tables. It generates a R_MIPS_EH reloc. */
16423 s_ehword (int ignore ATTRIBUTE_UNUSED)
16428 mips_emit_delays ();
16431 mips_clear_insn_labels ();
16433 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16435 as_bad (_("unsupported use of .ehword"));
16436 ignore_rest_of_line ();
16440 md_number_to_chars (p, 0, 4);
16441 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16442 BFD_RELOC_32_PCREL);
16444 demand_empty_rest_of_line ();
16447 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16448 tables in SVR4 PIC code. */
16451 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16455 file_mips_check_options ();
16457 /* This is ignored when not generating SVR4 PIC code. */
16458 if (mips_pic != SVR4_PIC)
16464 mips_mark_labels ();
16465 mips_assembling_insn = TRUE;
16467 /* Add $gp to the register named as an argument. */
16469 reg = tc_get_register (0);
16470 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16473 mips_assembling_insn = FALSE;
16474 demand_empty_rest_of_line ();
16477 /* Handle the .insn pseudo-op. This marks instruction labels in
16478 mips16/micromips mode. This permits the linker to handle them specially,
16479 such as generating jalx instructions when needed. We also make
16480 them odd for the duration of the assembly, in order to generate the
16481 right sort of code. We will make them even in the adjust_symtab
16482 routine, while leaving them marked. This is convenient for the
16483 debugger and the disassembler. The linker knows to make them odd
16487 s_insn (int ignore ATTRIBUTE_UNUSED)
16489 file_mips_check_options ();
16490 file_ase_mips16 |= mips_opts.mips16;
16491 file_ase_micromips |= mips_opts.micromips;
16493 mips_mark_labels ();
16495 demand_empty_rest_of_line ();
16498 /* Handle the .nan pseudo-op. */
16501 s_nan (int ignore ATTRIBUTE_UNUSED)
16503 static const char str_legacy[] = "legacy";
16504 static const char str_2008[] = "2008";
16507 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16509 if (i == sizeof (str_2008) - 1
16510 && memcmp (input_line_pointer, str_2008, i) == 0)
16512 else if (i == sizeof (str_legacy) - 1
16513 && memcmp (input_line_pointer, str_legacy, i) == 0)
16515 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16518 as_bad (_("`%s' does not support legacy NaN"),
16519 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16522 as_bad (_("bad .nan directive"));
16524 input_line_pointer += i;
16525 demand_empty_rest_of_line ();
16528 /* Handle a .stab[snd] directive. Ideally these directives would be
16529 implemented in a transparent way, so that removing them would not
16530 have any effect on the generated instructions. However, s_stab
16531 internally changes the section, so in practice we need to decide
16532 now whether the preceding label marks compressed code. We do not
16533 support changing the compression mode of a label after a .stab*
16534 directive, such as in:
16540 so the current mode wins. */
16543 s_mips_stab (int type)
16545 mips_mark_labels ();
16549 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16552 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16559 c = get_symbol_name (&name);
16560 symbolP = symbol_find_or_make (name);
16561 S_SET_WEAK (symbolP);
16562 *input_line_pointer = c;
16564 SKIP_WHITESPACE_AFTER_NAME ();
16566 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16568 if (S_IS_DEFINED (symbolP))
16570 as_bad (_("ignoring attempt to redefine symbol %s"),
16571 S_GET_NAME (symbolP));
16572 ignore_rest_of_line ();
16576 if (*input_line_pointer == ',')
16578 ++input_line_pointer;
16579 SKIP_WHITESPACE ();
16583 if (exp.X_op != O_symbol)
16585 as_bad (_("bad .weakext directive"));
16586 ignore_rest_of_line ();
16589 symbol_set_value_expression (symbolP, &exp);
16592 demand_empty_rest_of_line ();
16595 /* Parse a register string into a number. Called from the ECOFF code
16596 to parse .frame. The argument is non-zero if this is the frame
16597 register, so that we can record it in mips_frame_reg. */
16600 tc_get_register (int frame)
16604 SKIP_WHITESPACE ();
16605 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16609 mips_frame_reg = reg != 0 ? reg : SP;
16610 mips_frame_reg_valid = 1;
16611 mips_cprestore_valid = 0;
16617 md_section_align (asection *seg, valueT addr)
16619 int align = bfd_get_section_alignment (stdoutput, seg);
16621 /* We don't need to align ELF sections to the full alignment.
16622 However, Irix 5 may prefer that we align them at least to a 16
16623 byte boundary. We don't bother to align the sections if we
16624 are targeted for an embedded system. */
16625 if (strncmp (TARGET_OS, "elf", 3) == 0)
16630 return ((addr + (1 << align) - 1) & -(1 << align));
16633 /* Utility routine, called from above as well. If called while the
16634 input file is still being read, it's only an approximation. (For
16635 example, a symbol may later become defined which appeared to be
16636 undefined earlier.) */
16639 nopic_need_relax (symbolS *sym, int before_relaxing)
16644 if (g_switch_value > 0)
16646 const char *symname;
16649 /* Find out whether this symbol can be referenced off the $gp
16650 register. It can be if it is smaller than the -G size or if
16651 it is in the .sdata or .sbss section. Certain symbols can
16652 not be referenced off the $gp, although it appears as though
16654 symname = S_GET_NAME (sym);
16655 if (symname != (const char *) NULL
16656 && (strcmp (symname, "eprol") == 0
16657 || strcmp (symname, "etext") == 0
16658 || strcmp (symname, "_gp") == 0
16659 || strcmp (symname, "edata") == 0
16660 || strcmp (symname, "_fbss") == 0
16661 || strcmp (symname, "_fdata") == 0
16662 || strcmp (symname, "_ftext") == 0
16663 || strcmp (symname, "end") == 0
16664 || strcmp (symname, "_gp_disp") == 0))
16666 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16668 #ifndef NO_ECOFF_DEBUGGING
16669 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16670 && (symbol_get_obj (sym)->ecoff_extern_size
16671 <= g_switch_value))
16673 /* We must defer this decision until after the whole
16674 file has been read, since there might be a .extern
16675 after the first use of this symbol. */
16676 || (before_relaxing
16677 #ifndef NO_ECOFF_DEBUGGING
16678 && symbol_get_obj (sym)->ecoff_extern_size == 0
16680 && S_GET_VALUE (sym) == 0)
16681 || (S_GET_VALUE (sym) != 0
16682 && S_GET_VALUE (sym) <= g_switch_value)))
16686 const char *segname;
16688 segname = segment_name (S_GET_SEGMENT (sym));
16689 gas_assert (strcmp (segname, ".lit8") != 0
16690 && strcmp (segname, ".lit4") != 0);
16691 change = (strcmp (segname, ".sdata") != 0
16692 && strcmp (segname, ".sbss") != 0
16693 && strncmp (segname, ".sdata.", 7) != 0
16694 && strncmp (segname, ".sbss.", 6) != 0
16695 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16696 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16701 /* We are not optimizing for the $gp register. */
16706 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16709 pic_need_relax (symbolS *sym, asection *segtype)
16713 /* Handle the case of a symbol equated to another symbol. */
16714 while (symbol_equated_reloc_p (sym))
16718 /* It's possible to get a loop here in a badly written program. */
16719 n = symbol_get_value_expression (sym)->X_add_symbol;
16725 if (symbol_section_p (sym))
16728 symsec = S_GET_SEGMENT (sym);
16730 /* This must duplicate the test in adjust_reloc_syms. */
16731 return (!bfd_is_und_section (symsec)
16732 && !bfd_is_abs_section (symsec)
16733 && !bfd_is_com_section (symsec)
16734 && !s_is_linkonce (sym, segtype)
16735 /* A global or weak symbol is treated as external. */
16736 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
16740 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16741 extended opcode. SEC is the section the frag is in. */
16744 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16747 const struct mips_int_operand *operand;
16752 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16754 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16757 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16758 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16759 operand = mips16_immed_operand (type, FALSE);
16760 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
16761 || (operand->root.type == OP_PCREL
16763 : !bfd_is_abs_section (symsec)))
16766 sym_frag = symbol_get_frag (fragp->fr_symbol);
16767 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16769 if (operand->root.type == OP_PCREL)
16771 const struct mips_pcrel_operand *pcrel_op;
16775 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16778 pcrel_op = (const struct mips_pcrel_operand *) operand;
16780 /* If the relax_marker of the symbol fragment differs from the
16781 relax_marker of this fragment, we have not yet adjusted the
16782 symbol fragment fr_address. We want to add in STRETCH in
16783 order to get a better estimate of the address. This
16784 particularly matters because of the shift bits. */
16786 && sym_frag->relax_marker != fragp->relax_marker)
16790 /* Adjust stretch for any alignment frag. Note that if have
16791 been expanding the earlier code, the symbol may be
16792 defined in what appears to be an earlier frag. FIXME:
16793 This doesn't handle the fr_subtype field, which specifies
16794 a maximum number of bytes to skip when doing an
16796 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16798 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16801 stretch = - ((- stretch)
16802 & ~ ((1 << (int) f->fr_offset) - 1));
16804 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16813 addr = fragp->fr_address + fragp->fr_fix;
16815 /* The base address rules are complicated. The base address of
16816 a branch is the following instruction. The base address of a
16817 PC relative load or add is the instruction itself, but if it
16818 is in a delay slot (in which case it can not be extended) use
16819 the address of the instruction whose delay slot it is in. */
16820 if (pcrel_op->include_isa_bit)
16824 /* If we are currently assuming that this frag should be
16825 extended, then, the current address is two bytes
16827 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16830 /* Ignore the low bit in the target, since it will be set
16831 for a text label. */
16834 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16836 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16839 val -= addr & -(1 << pcrel_op->align_log2);
16841 /* If any of the shifted bits are set, we must use an extended
16842 opcode. If the address depends on the size of this
16843 instruction, this can lead to a loop, so we arrange to always
16844 use an extended opcode. */
16845 if ((val & ((1 << operand->shift) - 1)) != 0)
16847 fragp->fr_subtype =
16848 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16852 /* If we are about to mark a frag as extended because the value
16853 is precisely the next value above maxtiny, then there is a
16854 chance of an infinite loop as in the following code:
16859 In this case when the la is extended, foo is 0x3fc bytes
16860 away, so the la can be shrunk, but then foo is 0x400 away, so
16861 the la must be extended. To avoid this loop, we mark the
16862 frag as extended if it was small, and is about to become
16863 extended with the next value above maxtiny. */
16864 maxtiny = mips_int_operand_max (operand);
16865 if (val == maxtiny + (1 << operand->shift)
16866 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16868 fragp->fr_subtype =
16869 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16874 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16877 /* Compute the length of a branch sequence, and adjust the
16878 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16879 worst-case length is computed, with UPDATE being used to indicate
16880 whether an unconditional (-1), branch-likely (+1) or regular (0)
16881 branch is to be computed. */
16883 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16885 bfd_boolean toofar;
16889 && S_IS_DEFINED (fragp->fr_symbol)
16890 && !S_IS_WEAK (fragp->fr_symbol)
16891 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16896 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16898 addr = fragp->fr_address + fragp->fr_fix + 4;
16902 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16905 /* If the symbol is not defined or it's in a different segment,
16906 we emit the long sequence. */
16909 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16911 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16912 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16913 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16914 RELAX_BRANCH_LINK (fragp->fr_subtype),
16920 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16923 if (mips_pic != NO_PIC)
16925 /* Additional space for PIC loading of target address. */
16927 if (mips_opts.isa == ISA_MIPS1)
16928 /* Additional space for $at-stabilizing nop. */
16932 /* If branch is conditional. */
16933 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16940 /* Compute the length of a branch sequence, and adjust the
16941 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16942 worst-case length is computed, with UPDATE being used to indicate
16943 whether an unconditional (-1), or regular (0) branch is to be
16947 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16949 bfd_boolean toofar;
16953 && S_IS_DEFINED (fragp->fr_symbol)
16954 && !S_IS_WEAK (fragp->fr_symbol)
16955 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16960 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16961 /* Ignore the low bit in the target, since it will be set
16962 for a text label. */
16963 if ((val & 1) != 0)
16966 addr = fragp->fr_address + fragp->fr_fix + 4;
16970 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16973 /* If the symbol is not defined or it's in a different segment,
16974 we emit the long sequence. */
16977 if (fragp && update
16978 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16979 fragp->fr_subtype = (toofar
16980 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16981 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16986 bfd_boolean compact_known = fragp != NULL;
16987 bfd_boolean compact = FALSE;
16988 bfd_boolean uncond;
16991 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16993 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16995 uncond = update < 0;
16997 /* If label is out of range, we turn branch <br>:
16999 <br> label # 4 bytes
17005 nop # 2 bytes if compact && !PIC
17008 if (mips_pic == NO_PIC && (!compact_known || compact))
17011 /* If assembling PIC code, we further turn:
17017 lw/ld at, %got(label)(gp) # 4 bytes
17018 d/addiu at, %lo(label) # 4 bytes
17021 if (mips_pic != NO_PIC)
17024 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17026 <brneg> 0f # 4 bytes
17027 nop # 2 bytes if !compact
17030 length += (compact_known && compact) ? 4 : 6;
17036 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17037 bit accordingly. */
17040 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17042 bfd_boolean toofar;
17045 && S_IS_DEFINED (fragp->fr_symbol)
17046 && !S_IS_WEAK (fragp->fr_symbol)
17047 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17053 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17054 /* Ignore the low bit in the target, since it will be set
17055 for a text label. */
17056 if ((val & 1) != 0)
17059 /* Assume this is a 2-byte branch. */
17060 addr = fragp->fr_address + fragp->fr_fix + 2;
17062 /* We try to avoid the infinite loop by not adding 2 more bytes for
17067 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17069 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17070 else if (type == 'E')
17071 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17076 /* If the symbol is not defined or it's in a different segment,
17077 we emit a normal 32-bit branch. */
17080 if (fragp && update
17081 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17083 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17084 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17092 /* Estimate the size of a frag before relaxing. Unless this is the
17093 mips16, we are not really relaxing here, and the final size is
17094 encoded in the subtype information. For the mips16, we have to
17095 decide whether we are using an extended opcode or not. */
17098 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17102 if (RELAX_BRANCH_P (fragp->fr_subtype))
17105 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17107 return fragp->fr_var;
17110 if (RELAX_MIPS16_P (fragp->fr_subtype))
17111 /* We don't want to modify the EXTENDED bit here; it might get us
17112 into infinite loops. We change it only in mips_relax_frag(). */
17113 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17115 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17119 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17120 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17121 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17122 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17123 fragp->fr_var = length;
17128 if (mips_pic == NO_PIC)
17129 change = nopic_need_relax (fragp->fr_symbol, 0);
17130 else if (mips_pic == SVR4_PIC)
17131 change = pic_need_relax (fragp->fr_symbol, segtype);
17132 else if (mips_pic == VXWORKS_PIC)
17133 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17140 fragp->fr_subtype |= RELAX_USE_SECOND;
17141 return -RELAX_FIRST (fragp->fr_subtype);
17144 return -RELAX_SECOND (fragp->fr_subtype);
17147 /* This is called to see whether a reloc against a defined symbol
17148 should be converted into a reloc against a section. */
17151 mips_fix_adjustable (fixS *fixp)
17153 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17154 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17157 if (fixp->fx_addsy == NULL)
17160 /* Allow relocs used for EH tables. */
17161 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17164 /* If symbol SYM is in a mergeable section, relocations of the form
17165 SYM + 0 can usually be made section-relative. The mergeable data
17166 is then identified by the section offset rather than by the symbol.
17168 However, if we're generating REL LO16 relocations, the offset is split
17169 between the LO16 and parterning high part relocation. The linker will
17170 need to recalculate the complete offset in order to correctly identify
17173 The linker has traditionally not looked for the parterning high part
17174 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17175 placed anywhere. Rather than break backwards compatibility by changing
17176 this, it seems better not to force the issue, and instead keep the
17177 original symbol. This will work with either linker behavior. */
17178 if ((lo16_reloc_p (fixp->fx_r_type)
17179 || reloc_needs_lo_p (fixp->fx_r_type))
17180 && HAVE_IN_PLACE_ADDENDS
17181 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17184 /* There is no place to store an in-place offset for JALR relocations. */
17185 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17188 /* Likewise an in-range offset of limited PC-relative relocations may
17189 overflow the in-place relocatable field if recalculated against the
17190 start address of the symbol's containing section.
17192 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17193 section relative to allow linker relaxations to be performed later on. */
17194 if (limited_pcrel_reloc_p (fixp->fx_r_type)
17195 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
17198 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17199 to a floating-point stub. The same is true for non-R_MIPS16_26
17200 relocations against MIPS16 functions; in this case, the stub becomes
17201 the function's canonical address.
17203 Floating-point stubs are stored in unique .mips16.call.* or
17204 .mips16.fn.* sections. If a stub T for function F is in section S,
17205 the first relocation in section S must be against F; this is how the
17206 linker determines the target function. All relocations that might
17207 resolve to T must also be against F. We therefore have the following
17208 restrictions, which are given in an intentionally-redundant way:
17210 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17213 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17214 if that stub might be used.
17216 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17219 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17220 that stub might be used.
17222 There is a further restriction:
17224 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17225 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17226 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17227 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17228 against MIPS16 or microMIPS symbols because we need to keep the
17229 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17230 detection and JAL to JALX instruction conversion in the linker.
17232 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17233 against a MIPS16 symbol. We deal with (5) by additionally leaving
17234 alone any jump and branch relocations against a microMIPS symbol.
17236 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17237 relocation against some symbol R, no relocation against R may be
17238 reduced. (Note that this deals with (2) as well as (1) because
17239 relocations against global symbols will never be reduced on ELF
17240 targets.) This approach is a little simpler than trying to detect
17241 stub sections, and gives the "all or nothing" per-symbol consistency
17242 that we have for MIPS16 symbols. */
17243 if (fixp->fx_subsy == NULL
17244 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17245 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17246 && (jmp_reloc_p (fixp->fx_r_type)
17247 || b_reloc_p (fixp->fx_r_type)))
17248 || *symbol_get_tc (fixp->fx_addsy)))
17254 /* Translate internal representation of relocation info to BFD target
17258 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17260 static arelent *retval[4];
17262 bfd_reloc_code_real_type code;
17264 memset (retval, 0, sizeof(retval));
17265 reloc = retval[0] = XCNEW (arelent);
17266 reloc->sym_ptr_ptr = XNEW (asymbol *);
17267 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17268 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17270 if (fixp->fx_pcrel)
17272 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17273 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
17274 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17275 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17276 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17277 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17278 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17279 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17280 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17281 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17282 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17283 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
17285 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17286 Relocations want only the symbol offset. */
17287 switch (fixp->fx_r_type)
17289 case BFD_RELOC_MIPS_18_PCREL_S3:
17290 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
17293 reloc->addend = fixp->fx_addnumber + reloc->address;
17297 else if (HAVE_IN_PLACE_ADDENDS
17298 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
17299 && (read_compressed_insn (fixp->fx_frag->fr_literal
17300 + fixp->fx_where, 4) >> 26) == 0x3c)
17302 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17303 addend accordingly. */
17304 reloc->addend = fixp->fx_addnumber >> 1;
17307 reloc->addend = fixp->fx_addnumber;
17309 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17310 entry to be used in the relocation's section offset. */
17311 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17313 reloc->address = reloc->addend;
17317 code = fixp->fx_r_type;
17319 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17320 if (reloc->howto == NULL)
17322 as_bad_where (fixp->fx_file, fixp->fx_line,
17323 _("cannot represent %s relocation in this object file"
17325 bfd_get_reloc_code_name (code));
17332 /* Relax a machine dependent frag. This returns the amount by which
17333 the current size of the frag should change. */
17336 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17338 if (RELAX_BRANCH_P (fragp->fr_subtype))
17340 offsetT old_var = fragp->fr_var;
17342 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17344 return fragp->fr_var - old_var;
17347 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17349 offsetT old_var = fragp->fr_var;
17350 offsetT new_var = 4;
17352 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17353 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17354 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17355 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17356 fragp->fr_var = new_var;
17358 return new_var - old_var;
17361 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17364 if (mips16_extended_frag (fragp, sec, stretch))
17366 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17368 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17373 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17375 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17382 /* Convert a machine dependent frag. */
17385 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17387 if (RELAX_BRANCH_P (fragp->fr_subtype))
17390 unsigned long insn;
17394 buf = fragp->fr_literal + fragp->fr_fix;
17395 insn = read_insn (buf);
17397 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17399 /* We generate a fixup instead of applying it right now
17400 because, if there are linker relaxations, we're going to
17401 need the relocations. */
17402 exp.X_op = O_symbol;
17403 exp.X_add_symbol = fragp->fr_symbol;
17404 exp.X_add_number = fragp->fr_offset;
17406 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17407 BFD_RELOC_16_PCREL_S2);
17408 fixp->fx_file = fragp->fr_file;
17409 fixp->fx_line = fragp->fr_line;
17411 buf = write_insn (buf, insn);
17417 as_warn_where (fragp->fr_file, fragp->fr_line,
17418 _("relaxed out-of-range branch into a jump"));
17420 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17423 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17425 /* Reverse the branch. */
17426 switch ((insn >> 28) & 0xf)
17429 if ((insn & 0xff000000) == 0x47000000
17430 || (insn & 0xff600000) == 0x45600000)
17432 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17433 reversed by tweaking bit 23. */
17434 insn ^= 0x00800000;
17438 /* bc[0-3][tf]l? instructions can have the condition
17439 reversed by tweaking a single TF bit, and their
17440 opcodes all have 0x4???????. */
17441 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17442 insn ^= 0x00010000;
17447 /* bltz 0x04000000 bgez 0x04010000
17448 bltzal 0x04100000 bgezal 0x04110000 */
17449 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17450 insn ^= 0x00010000;
17454 /* beq 0x10000000 bne 0x14000000
17455 blez 0x18000000 bgtz 0x1c000000 */
17456 insn ^= 0x04000000;
17464 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17466 /* Clear the and-link bit. */
17467 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17469 /* bltzal 0x04100000 bgezal 0x04110000
17470 bltzall 0x04120000 bgezall 0x04130000 */
17471 insn &= ~0x00100000;
17474 /* Branch over the branch (if the branch was likely) or the
17475 full jump (not likely case). Compute the offset from the
17476 current instruction to branch to. */
17477 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17481 /* How many bytes in instructions we've already emitted? */
17482 i = buf - fragp->fr_literal - fragp->fr_fix;
17483 /* How many bytes in instructions from here to the end? */
17484 i = fragp->fr_var - i;
17486 /* Convert to instruction count. */
17488 /* Branch counts from the next instruction. */
17491 /* Branch over the jump. */
17492 buf = write_insn (buf, insn);
17495 buf = write_insn (buf, 0);
17497 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17499 /* beql $0, $0, 2f */
17501 /* Compute the PC offset from the current instruction to
17502 the end of the variable frag. */
17503 /* How many bytes in instructions we've already emitted? */
17504 i = buf - fragp->fr_literal - fragp->fr_fix;
17505 /* How many bytes in instructions from here to the end? */
17506 i = fragp->fr_var - i;
17507 /* Convert to instruction count. */
17509 /* Don't decrement i, because we want to branch over the
17513 buf = write_insn (buf, insn);
17514 buf = write_insn (buf, 0);
17518 if (mips_pic == NO_PIC)
17521 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17522 ? 0x0c000000 : 0x08000000);
17523 exp.X_op = O_symbol;
17524 exp.X_add_symbol = fragp->fr_symbol;
17525 exp.X_add_number = fragp->fr_offset;
17527 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17528 FALSE, BFD_RELOC_MIPS_JMP);
17529 fixp->fx_file = fragp->fr_file;
17530 fixp->fx_line = fragp->fr_line;
17532 buf = write_insn (buf, insn);
17536 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17538 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17539 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17540 insn |= at << OP_SH_RT;
17541 exp.X_op = O_symbol;
17542 exp.X_add_symbol = fragp->fr_symbol;
17543 exp.X_add_number = fragp->fr_offset;
17545 if (fragp->fr_offset)
17547 exp.X_add_symbol = make_expr_symbol (&exp);
17548 exp.X_add_number = 0;
17551 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17552 FALSE, BFD_RELOC_MIPS_GOT16);
17553 fixp->fx_file = fragp->fr_file;
17554 fixp->fx_line = fragp->fr_line;
17556 buf = write_insn (buf, insn);
17558 if (mips_opts.isa == ISA_MIPS1)
17560 buf = write_insn (buf, 0);
17562 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17563 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17564 insn |= at << OP_SH_RS | at << OP_SH_RT;
17566 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17567 FALSE, BFD_RELOC_LO16);
17568 fixp->fx_file = fragp->fr_file;
17569 fixp->fx_line = fragp->fr_line;
17571 buf = write_insn (buf, insn);
17574 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17578 insn |= at << OP_SH_RS;
17580 buf = write_insn (buf, insn);
17584 fragp->fr_fix += fragp->fr_var;
17585 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17589 /* Relax microMIPS branches. */
17590 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17592 char *buf = fragp->fr_literal + fragp->fr_fix;
17593 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17594 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17595 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17596 bfd_boolean short_ds;
17597 unsigned long insn;
17601 exp.X_op = O_symbol;
17602 exp.X_add_symbol = fragp->fr_symbol;
17603 exp.X_add_number = fragp->fr_offset;
17605 fragp->fr_fix += fragp->fr_var;
17607 /* Handle 16-bit branches that fit or are forced to fit. */
17608 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17610 /* We generate a fixup instead of applying it right now,
17611 because if there is linker relaxation, we're going to
17612 need the relocations. */
17614 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17615 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17616 else if (type == 'E')
17617 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17618 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17622 fixp->fx_file = fragp->fr_file;
17623 fixp->fx_line = fragp->fr_line;
17625 /* These relocations can have an addend that won't fit in
17627 fixp->fx_no_overflow = 1;
17632 /* Handle 32-bit branches that fit or are forced to fit. */
17633 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17634 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17636 /* We generate a fixup instead of applying it right now,
17637 because if there is linker relaxation, we're going to
17638 need the relocations. */
17639 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17640 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17641 fixp->fx_file = fragp->fr_file;
17642 fixp->fx_line = fragp->fr_line;
17648 /* Relax 16-bit branches to 32-bit branches. */
17651 insn = read_compressed_insn (buf, 2);
17653 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17654 insn = 0x94000000; /* beq */
17655 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17657 unsigned long regno;
17659 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17660 regno = micromips_to_32_reg_d_map [regno];
17661 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17662 insn |= regno << MICROMIPSOP_SH_RS;
17667 /* Nothing else to do, just write it out. */
17668 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17669 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17671 buf = write_compressed_insn (buf, insn, 4);
17672 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17677 insn = read_compressed_insn (buf, 4);
17679 /* Relax 32-bit branches to a sequence of instructions. */
17680 as_warn_where (fragp->fr_file, fragp->fr_line,
17681 _("relaxed out-of-range branch into a jump"));
17683 /* Set the short-delay-slot bit. */
17684 short_ds = al && (insn & 0x02000000) != 0;
17686 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17690 /* Reverse the branch. */
17691 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17692 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17693 insn ^= 0x20000000;
17694 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17695 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17696 || (insn & 0xffe00000) == 0x40800000 /* blez */
17697 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17698 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17699 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17700 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17701 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17702 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17703 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17704 insn ^= 0x00400000;
17705 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17706 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17707 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17708 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17709 insn ^= 0x00200000;
17710 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
17712 || (insn & 0xff600000) == 0x81600000) /* BZ.V
17714 insn ^= 0x00800000;
17720 /* Clear the and-link and short-delay-slot bits. */
17721 gas_assert ((insn & 0xfda00000) == 0x40200000);
17723 /* bltzal 0x40200000 bgezal 0x40600000 */
17724 /* bltzals 0x42200000 bgezals 0x42600000 */
17725 insn &= ~0x02200000;
17728 /* Make a label at the end for use with the branch. */
17729 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17730 micromips_label_inc ();
17731 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17734 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17735 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17736 fixp->fx_file = fragp->fr_file;
17737 fixp->fx_line = fragp->fr_line;
17739 /* Branch over the jump. */
17740 buf = write_compressed_insn (buf, insn, 4);
17743 buf = write_compressed_insn (buf, 0x0c00, 2);
17746 if (mips_pic == NO_PIC)
17748 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17750 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17751 insn = al ? jal : 0xd4000000;
17753 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17754 BFD_RELOC_MICROMIPS_JMP);
17755 fixp->fx_file = fragp->fr_file;
17756 fixp->fx_line = fragp->fr_line;
17758 buf = write_compressed_insn (buf, insn, 4);
17761 buf = write_compressed_insn (buf, 0x0c00, 2);
17765 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17766 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17767 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17769 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17770 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17771 insn |= at << MICROMIPSOP_SH_RT;
17773 if (exp.X_add_number)
17775 exp.X_add_symbol = make_expr_symbol (&exp);
17776 exp.X_add_number = 0;
17779 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17780 BFD_RELOC_MICROMIPS_GOT16);
17781 fixp->fx_file = fragp->fr_file;
17782 fixp->fx_line = fragp->fr_line;
17784 buf = write_compressed_insn (buf, insn, 4);
17786 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17787 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17788 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17790 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17791 BFD_RELOC_MICROMIPS_LO16);
17792 fixp->fx_file = fragp->fr_file;
17793 fixp->fx_line = fragp->fr_line;
17795 buf = write_compressed_insn (buf, insn, 4);
17797 /* jr/jrc/jalr/jalrs $at */
17798 insn = al ? jalr : jr;
17799 insn |= at << MICROMIPSOP_SH_MJ;
17801 buf = write_compressed_insn (buf, insn, 2);
17804 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17808 if (RELAX_MIPS16_P (fragp->fr_subtype))
17811 const struct mips_int_operand *operand;
17814 unsigned int user_length, length;
17815 unsigned long insn;
17819 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17820 operand = mips16_immed_operand (type, FALSE);
17822 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17823 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
17824 if (operand->root.type == OP_PCREL)
17826 const struct mips_pcrel_operand *pcrel_op;
17829 pcrel_op = (const struct mips_pcrel_operand *) operand;
17830 addr = fragp->fr_address + fragp->fr_fix;
17832 /* The rules for the base address of a PC relative reloc are
17833 complicated; see mips16_extended_frag. */
17834 if (pcrel_op->include_isa_bit)
17839 /* Ignore the low bit in the target, since it will be
17840 set for a text label. */
17843 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17845 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17848 addr &= -(1 << pcrel_op->align_log2);
17851 /* Make sure the section winds up with the alignment we have
17853 if (operand->shift > 0)
17854 record_alignment (asec, operand->shift);
17858 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17859 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17860 as_warn_where (fragp->fr_file, fragp->fr_line,
17861 _("extended instruction in delay slot"));
17863 buf = fragp->fr_literal + fragp->fr_fix;
17865 insn = read_compressed_insn (buf, 2);
17867 insn |= MIPS16_EXTEND;
17869 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17871 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17876 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17877 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
17878 || (operand->root.type == OP_PCREL
17880 : !bfd_is_abs_section (symsec)))
17882 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
17890 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
17893 as_bad_where (fragp->fr_file, fragp->fr_line,
17894 _("unsupported relocation"));
17897 if (reloc != BFD_RELOC_NONE)
17901 exp.X_op = O_symbol;
17902 exp.X_add_symbol = fragp->fr_symbol;
17903 exp.X_add_number = fragp->fr_offset;
17905 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp,
17908 fixp->fx_file = fragp->fr_file;
17909 fixp->fx_line = fragp->fr_line;
17911 /* These relocations can have an addend that won't fit
17913 fixp->fx_no_overflow = 1;
17917 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17918 BFD_RELOC_UNUSED, val, user_length, &insn);
17920 length = (ext ? 4 : 2);
17921 gas_assert (mips16_opcode_length (insn) == length);
17922 write_compressed_insn (buf, insn, length);
17923 fragp->fr_fix += length;
17927 relax_substateT subtype = fragp->fr_subtype;
17928 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17929 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17933 first = RELAX_FIRST (subtype);
17934 second = RELAX_SECOND (subtype);
17935 fixp = (fixS *) fragp->fr_opcode;
17937 /* If the delay slot chosen does not match the size of the instruction,
17938 then emit a warning. */
17939 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17940 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17945 s = subtype & (RELAX_DELAY_SLOT_16BIT
17946 | RELAX_DELAY_SLOT_SIZE_FIRST
17947 | RELAX_DELAY_SLOT_SIZE_SECOND);
17948 msg = macro_warning (s);
17950 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17954 /* Possibly emit a warning if we've chosen the longer option. */
17955 if (use_second == second_longer)
17961 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17962 msg = macro_warning (s);
17964 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17968 /* Go through all the fixups for the first sequence. Disable them
17969 (by marking them as done) if we're going to use the second
17970 sequence instead. */
17972 && fixp->fx_frag == fragp
17973 && fixp->fx_where < fragp->fr_fix - second)
17975 if (subtype & RELAX_USE_SECOND)
17977 fixp = fixp->fx_next;
17980 /* Go through the fixups for the second sequence. Disable them if
17981 we're going to use the first sequence, otherwise adjust their
17982 addresses to account for the relaxation. */
17983 while (fixp && fixp->fx_frag == fragp)
17985 if (subtype & RELAX_USE_SECOND)
17986 fixp->fx_where -= first;
17989 fixp = fixp->fx_next;
17992 /* Now modify the frag contents. */
17993 if (subtype & RELAX_USE_SECOND)
17997 start = fragp->fr_literal + fragp->fr_fix - first - second;
17998 memmove (start, start + first, second);
17999 fragp->fr_fix -= first;
18002 fragp->fr_fix -= second;
18006 /* This function is called after the relocs have been generated.
18007 We've been storing mips16 text labels as odd. Here we convert them
18008 back to even for the convenience of the debugger. */
18011 mips_frob_file_after_relocs (void)
18014 unsigned int count, i;
18016 syms = bfd_get_outsymbols (stdoutput);
18017 count = bfd_get_symcount (stdoutput);
18018 for (i = 0; i < count; i++, syms++)
18019 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18020 && ((*syms)->value & 1) != 0)
18022 (*syms)->value &= ~1;
18023 /* If the symbol has an odd size, it was probably computed
18024 incorrectly, so adjust that as well. */
18025 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18026 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18030 /* This function is called whenever a label is defined, including fake
18031 labels instantiated off the dot special symbol. It is used when
18032 handling branch delays; if a branch has a label, we assume we cannot
18033 move it. This also bumps the value of the symbol by 1 in compressed
18037 mips_record_label (symbolS *sym)
18039 segment_info_type *si = seg_info (now_seg);
18040 struct insn_label_list *l;
18042 if (free_insn_labels == NULL)
18043 l = XNEW (struct insn_label_list);
18046 l = free_insn_labels;
18047 free_insn_labels = l->next;
18051 l->next = si->label_list;
18052 si->label_list = l;
18055 /* This function is called as tc_frob_label() whenever a label is defined
18056 and adds a DWARF-2 record we only want for true labels. */
18059 mips_define_label (symbolS *sym)
18061 mips_record_label (sym);
18062 dwarf2_emit_label (sym);
18065 /* This function is called by tc_new_dot_label whenever a new dot symbol
18069 mips_add_dot_label (symbolS *sym)
18071 mips_record_label (sym);
18072 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18073 mips_compressed_mark_label (sym);
18076 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18077 static unsigned int
18078 mips_convert_ase_flags (int ase)
18080 unsigned int ext_ases = 0;
18083 ext_ases |= AFL_ASE_DSP;
18084 if (ase & ASE_DSPR2)
18085 ext_ases |= AFL_ASE_DSPR2;
18086 if (ase & ASE_DSPR3)
18087 ext_ases |= AFL_ASE_DSPR3;
18089 ext_ases |= AFL_ASE_EVA;
18091 ext_ases |= AFL_ASE_MCU;
18092 if (ase & ASE_MDMX)
18093 ext_ases |= AFL_ASE_MDMX;
18094 if (ase & ASE_MIPS3D)
18095 ext_ases |= AFL_ASE_MIPS3D;
18097 ext_ases |= AFL_ASE_MT;
18098 if (ase & ASE_SMARTMIPS)
18099 ext_ases |= AFL_ASE_SMARTMIPS;
18100 if (ase & ASE_VIRT)
18101 ext_ases |= AFL_ASE_VIRT;
18103 ext_ases |= AFL_ASE_MSA;
18105 ext_ases |= AFL_ASE_XPA;
18109 /* Some special processing for a MIPS ELF file. */
18112 mips_elf_final_processing (void)
18115 Elf_Internal_ABIFlags_v0 flags;
18119 switch (file_mips_opts.isa)
18122 flags.isa_level = 1;
18125 flags.isa_level = 2;
18128 flags.isa_level = 3;
18131 flags.isa_level = 4;
18134 flags.isa_level = 5;
18137 flags.isa_level = 32;
18141 flags.isa_level = 32;
18145 flags.isa_level = 32;
18149 flags.isa_level = 32;
18153 flags.isa_level = 32;
18157 flags.isa_level = 64;
18161 flags.isa_level = 64;
18165 flags.isa_level = 64;
18169 flags.isa_level = 64;
18173 flags.isa_level = 64;
18178 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18179 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18180 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18181 : (file_mips_opts.fp == 64) ? AFL_REG_64
18183 flags.cpr2_size = AFL_REG_NONE;
18184 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18185 Tag_GNU_MIPS_ABI_FP);
18186 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18187 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18188 if (file_ase_mips16)
18189 flags.ases |= AFL_ASE_MIPS16;
18190 if (file_ase_micromips)
18191 flags.ases |= AFL_ASE_MICROMIPS;
18193 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18194 || file_mips_opts.fp == 64)
18195 && file_mips_opts.oddspreg)
18196 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18199 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18200 ((Elf_External_ABIFlags_v0 *)
18203 /* Write out the register information. */
18204 if (mips_abi != N64_ABI)
18208 s.ri_gprmask = mips_gprmask;
18209 s.ri_cprmask[0] = mips_cprmask[0];
18210 s.ri_cprmask[1] = mips_cprmask[1];
18211 s.ri_cprmask[2] = mips_cprmask[2];
18212 s.ri_cprmask[3] = mips_cprmask[3];
18213 /* The gp_value field is set by the MIPS ELF backend. */
18215 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18216 ((Elf32_External_RegInfo *)
18217 mips_regmask_frag));
18221 Elf64_Internal_RegInfo s;
18223 s.ri_gprmask = mips_gprmask;
18225 s.ri_cprmask[0] = mips_cprmask[0];
18226 s.ri_cprmask[1] = mips_cprmask[1];
18227 s.ri_cprmask[2] = mips_cprmask[2];
18228 s.ri_cprmask[3] = mips_cprmask[3];
18229 /* The gp_value field is set by the MIPS ELF backend. */
18231 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18232 ((Elf64_External_RegInfo *)
18233 mips_regmask_frag));
18236 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18237 sort of BFD interface for this. */
18238 if (mips_any_noreorder)
18239 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18240 if (mips_pic != NO_PIC)
18242 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18243 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18246 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18248 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18249 defined at present; this might need to change in future. */
18250 if (file_ase_mips16)
18251 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18252 if (file_ase_micromips)
18253 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18254 if (file_mips_opts.ase & ASE_MDMX)
18255 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18257 /* Set the MIPS ELF ABI flags. */
18258 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18259 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18260 else if (mips_abi == O64_ABI)
18261 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18262 else if (mips_abi == EABI_ABI)
18264 if (file_mips_opts.gp == 64)
18265 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18267 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18269 else if (mips_abi == N32_ABI)
18270 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18272 /* Nothing to do for N64_ABI. */
18274 if (mips_32bitmode)
18275 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18277 if (mips_nan2008 == 1)
18278 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18280 /* 32 bit code with 64 bit FP registers. */
18281 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18282 Tag_GNU_MIPS_ABI_FP);
18283 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
18284 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
18287 typedef struct proc {
18289 symbolS *func_end_sym;
18290 unsigned long reg_mask;
18291 unsigned long reg_offset;
18292 unsigned long fpreg_mask;
18293 unsigned long fpreg_offset;
18294 unsigned long frame_offset;
18295 unsigned long frame_reg;
18296 unsigned long pc_reg;
18299 static procS cur_proc;
18300 static procS *cur_proc_ptr;
18301 static int numprocs;
18303 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18304 as "2", and a normal nop as "0". */
18306 #define NOP_OPCODE_MIPS 0
18307 #define NOP_OPCODE_MIPS16 1
18308 #define NOP_OPCODE_MICROMIPS 2
18311 mips_nop_opcode (void)
18313 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18314 return NOP_OPCODE_MICROMIPS;
18315 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18316 return NOP_OPCODE_MIPS16;
18318 return NOP_OPCODE_MIPS;
18321 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18322 32-bit microMIPS NOPs here (if applicable). */
18325 mips_handle_align (fragS *fragp)
18329 int bytes, size, excess;
18332 if (fragp->fr_type != rs_align_code)
18335 p = fragp->fr_literal + fragp->fr_fix;
18337 switch (nop_opcode)
18339 case NOP_OPCODE_MICROMIPS:
18340 opcode = micromips_nop32_insn.insn_opcode;
18343 case NOP_OPCODE_MIPS16:
18344 opcode = mips16_nop_insn.insn_opcode;
18347 case NOP_OPCODE_MIPS:
18349 opcode = nop_insn.insn_opcode;
18354 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18355 excess = bytes % size;
18357 /* Handle the leading part if we're not inserting a whole number of
18358 instructions, and make it the end of the fixed part of the frag.
18359 Try to fit in a short microMIPS NOP if applicable and possible,
18360 and use zeroes otherwise. */
18361 gas_assert (excess < 4);
18362 fragp->fr_fix += excess;
18367 /* Fall through. */
18369 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18371 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18375 /* Fall through. */
18378 /* Fall through. */
18383 md_number_to_chars (p, opcode, size);
18384 fragp->fr_var = size;
18393 if (*input_line_pointer == '-')
18395 ++input_line_pointer;
18398 if (!ISDIGIT (*input_line_pointer))
18399 as_bad (_("expected simple number"));
18400 if (input_line_pointer[0] == '0')
18402 if (input_line_pointer[1] == 'x')
18404 input_line_pointer += 2;
18405 while (ISXDIGIT (*input_line_pointer))
18408 val |= hex_value (*input_line_pointer++);
18410 return negative ? -val : val;
18414 ++input_line_pointer;
18415 while (ISDIGIT (*input_line_pointer))
18418 val |= *input_line_pointer++ - '0';
18420 return negative ? -val : val;
18423 if (!ISDIGIT (*input_line_pointer))
18425 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18426 *input_line_pointer, *input_line_pointer);
18427 as_warn (_("invalid number"));
18430 while (ISDIGIT (*input_line_pointer))
18433 val += *input_line_pointer++ - '0';
18435 return negative ? -val : val;
18438 /* The .file directive; just like the usual .file directive, but there
18439 is an initial number which is the ECOFF file index. In the non-ECOFF
18440 case .file implies DWARF-2. */
18443 s_mips_file (int x ATTRIBUTE_UNUSED)
18445 static int first_file_directive = 0;
18447 if (ECOFF_DEBUGGING)
18456 filename = dwarf2_directive_file (0);
18458 /* Versions of GCC up to 3.1 start files with a ".file"
18459 directive even for stabs output. Make sure that this
18460 ".file" is handled. Note that you need a version of GCC
18461 after 3.1 in order to support DWARF-2 on MIPS. */
18462 if (filename != NULL && ! first_file_directive)
18464 (void) new_logical_line (filename, -1);
18465 s_app_file_string (filename, 0);
18467 first_file_directive = 1;
18471 /* The .loc directive, implying DWARF-2. */
18474 s_mips_loc (int x ATTRIBUTE_UNUSED)
18476 if (!ECOFF_DEBUGGING)
18477 dwarf2_directive_loc (0);
18480 /* The .end directive. */
18483 s_mips_end (int x ATTRIBUTE_UNUSED)
18487 /* Following functions need their own .frame and .cprestore directives. */
18488 mips_frame_reg_valid = 0;
18489 mips_cprestore_valid = 0;
18491 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18494 demand_empty_rest_of_line ();
18499 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18500 as_warn (_(".end not in text section"));
18504 as_warn (_(".end directive without a preceding .ent directive"));
18505 demand_empty_rest_of_line ();
18511 gas_assert (S_GET_NAME (p));
18512 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18513 as_warn (_(".end symbol does not match .ent symbol"));
18515 if (debug_type == DEBUG_STABS)
18516 stabs_generate_asm_endfunc (S_GET_NAME (p),
18520 as_warn (_(".end directive missing or unknown symbol"));
18522 /* Create an expression to calculate the size of the function. */
18523 if (p && cur_proc_ptr)
18525 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18526 expressionS *exp = XNEW (expressionS);
18529 exp->X_op = O_subtract;
18530 exp->X_add_symbol = symbol_temp_new_now ();
18531 exp->X_op_symbol = p;
18532 exp->X_add_number = 0;
18534 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18537 /* Generate a .pdr section. */
18538 if (!ECOFF_DEBUGGING && mips_flag_pdr)
18540 segT saved_seg = now_seg;
18541 subsegT saved_subseg = now_subseg;
18545 #ifdef md_flush_pending_output
18546 md_flush_pending_output ();
18549 gas_assert (pdr_seg);
18550 subseg_set (pdr_seg, 0);
18552 /* Write the symbol. */
18553 exp.X_op = O_symbol;
18554 exp.X_add_symbol = p;
18555 exp.X_add_number = 0;
18556 emit_expr (&exp, 4);
18558 fragp = frag_more (7 * 4);
18560 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18561 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18562 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18563 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18564 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18565 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18566 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18568 subseg_set (saved_seg, saved_subseg);
18571 cur_proc_ptr = NULL;
18574 /* The .aent and .ent directives. */
18577 s_mips_ent (int aent)
18581 symbolP = get_symbol ();
18582 if (*input_line_pointer == ',')
18583 ++input_line_pointer;
18584 SKIP_WHITESPACE ();
18585 if (ISDIGIT (*input_line_pointer)
18586 || *input_line_pointer == '-')
18589 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18590 as_warn (_(".ent or .aent not in text section"));
18592 if (!aent && cur_proc_ptr)
18593 as_warn (_("missing .end"));
18597 /* This function needs its own .frame and .cprestore directives. */
18598 mips_frame_reg_valid = 0;
18599 mips_cprestore_valid = 0;
18601 cur_proc_ptr = &cur_proc;
18602 memset (cur_proc_ptr, '\0', sizeof (procS));
18604 cur_proc_ptr->func_sym = symbolP;
18608 if (debug_type == DEBUG_STABS)
18609 stabs_generate_asm_func (S_GET_NAME (symbolP),
18610 S_GET_NAME (symbolP));
18613 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18615 demand_empty_rest_of_line ();
18618 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18619 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18620 s_mips_frame is used so that we can set the PDR information correctly.
18621 We can't use the ecoff routines because they make reference to the ecoff
18622 symbol table (in the mdebug section). */
18625 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18627 if (ECOFF_DEBUGGING)
18633 if (cur_proc_ptr == (procS *) NULL)
18635 as_warn (_(".frame outside of .ent"));
18636 demand_empty_rest_of_line ();
18640 cur_proc_ptr->frame_reg = tc_get_register (1);
18642 SKIP_WHITESPACE ();
18643 if (*input_line_pointer++ != ','
18644 || get_absolute_expression_and_terminator (&val) != ',')
18646 as_warn (_("bad .frame directive"));
18647 --input_line_pointer;
18648 demand_empty_rest_of_line ();
18652 cur_proc_ptr->frame_offset = val;
18653 cur_proc_ptr->pc_reg = tc_get_register (0);
18655 demand_empty_rest_of_line ();
18659 /* The .fmask and .mask directives. If the mdebug section is present
18660 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18661 embedded targets, s_mips_mask is used so that we can set the PDR
18662 information correctly. We can't use the ecoff routines because they
18663 make reference to the ecoff symbol table (in the mdebug section). */
18666 s_mips_mask (int reg_type)
18668 if (ECOFF_DEBUGGING)
18669 s_ignore (reg_type);
18674 if (cur_proc_ptr == (procS *) NULL)
18676 as_warn (_(".mask/.fmask outside of .ent"));
18677 demand_empty_rest_of_line ();
18681 if (get_absolute_expression_and_terminator (&mask) != ',')
18683 as_warn (_("bad .mask/.fmask directive"));
18684 --input_line_pointer;
18685 demand_empty_rest_of_line ();
18689 off = get_absolute_expression ();
18691 if (reg_type == 'F')
18693 cur_proc_ptr->fpreg_mask = mask;
18694 cur_proc_ptr->fpreg_offset = off;
18698 cur_proc_ptr->reg_mask = mask;
18699 cur_proc_ptr->reg_offset = off;
18702 demand_empty_rest_of_line ();
18706 /* A table describing all the processors gas knows about. Names are
18707 matched in the order listed.
18709 To ease comparison, please keep this table in the same order as
18710 gcc's mips_cpu_info_table[]. */
18711 static const struct mips_cpu_info mips_cpu_info_table[] =
18713 /* Entries for generic ISAs */
18714 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
18715 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
18716 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
18717 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
18718 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
18719 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
18720 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18721 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
18722 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
18723 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
18724 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
18725 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
18726 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
18727 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
18728 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
18731 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
18732 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
18733 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
18736 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
18739 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
18740 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
18741 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
18742 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
18743 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
18744 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
18745 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
18746 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
18747 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
18748 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
18749 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
18750 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
18751 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
18752 /* ST Microelectronics Loongson 2E and 2F cores */
18753 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
18754 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
18757 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
18758 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
18759 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
18760 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
18761 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
18762 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
18763 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
18764 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
18765 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
18766 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
18767 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
18768 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
18769 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
18770 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
18771 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
18774 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18775 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18776 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18777 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18779 /* MIPS 32 Release 2 */
18780 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18781 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18782 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18783 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18784 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18785 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18786 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18787 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18788 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18789 ISA_MIPS32R2, CPU_MIPS32R2 },
18790 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18791 ISA_MIPS32R2, CPU_MIPS32R2 },
18792 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18793 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18794 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18795 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18796 /* Deprecated forms of the above. */
18797 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18798 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18799 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18800 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18801 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18802 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18803 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18804 /* Deprecated forms of the above. */
18805 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18806 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18807 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18808 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18809 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18810 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18811 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18812 /* Deprecated forms of the above. */
18813 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18814 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18815 /* 34Kn is a 34kc without DSP. */
18816 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18817 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18818 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18819 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18820 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18821 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18822 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18823 /* Deprecated forms of the above. */
18824 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18825 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18826 /* 1004K cores are multiprocessor versions of the 34K. */
18827 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18828 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18829 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18830 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18831 /* interaptiv is the new name for 1004kf */
18832 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18834 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18835 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18836 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18837 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
18840 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18841 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18842 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18843 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18845 /* Broadcom SB-1 CPU core */
18846 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18847 /* Broadcom SB-1A CPU core */
18848 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18850 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
18852 /* MIPS 64 Release 2 */
18854 /* Cavium Networks Octeon CPU core */
18855 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
18856 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
18857 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
18858 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
18861 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
18864 XLP is mostly like XLR, with the prominent exception that it is
18865 MIPS64R2 rather than MIPS64. */
18866 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
18868 /* MIPS 64 Release 6 */
18869 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
18870 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
18873 { NULL, 0, 0, 0, 0 }
18877 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18878 with a final "000" replaced by "k". Ignore case.
18880 Note: this function is shared between GCC and GAS. */
18883 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
18885 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18886 given++, canonical++;
18888 return ((*given == 0 && *canonical == 0)
18889 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18893 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18894 CPU name. We've traditionally allowed a lot of variation here.
18896 Note: this function is shared between GCC and GAS. */
18899 mips_matching_cpu_name_p (const char *canonical, const char *given)
18901 /* First see if the name matches exactly, or with a final "000"
18902 turned into "k". */
18903 if (mips_strict_matching_cpu_name_p (canonical, given))
18906 /* If not, try comparing based on numerical designation alone.
18907 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18908 if (TOLOWER (*given) == 'r')
18910 if (!ISDIGIT (*given))
18913 /* Skip over some well-known prefixes in the canonical name,
18914 hoping to find a number there too. */
18915 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18917 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18919 else if (TOLOWER (canonical[0]) == 'r')
18922 return mips_strict_matching_cpu_name_p (canonical, given);
18926 /* Parse an option that takes the name of a processor as its argument.
18927 OPTION is the name of the option and CPU_STRING is the argument.
18928 Return the corresponding processor enumeration if the CPU_STRING is
18929 recognized, otherwise report an error and return null.
18931 A similar function exists in GCC. */
18933 static const struct mips_cpu_info *
18934 mips_parse_cpu (const char *option, const char *cpu_string)
18936 const struct mips_cpu_info *p;
18938 /* 'from-abi' selects the most compatible architecture for the given
18939 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18940 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18941 version. Look first at the -mgp options, if given, otherwise base
18942 the choice on MIPS_DEFAULT_64BIT.
18944 Treat NO_ABI like the EABIs. One reason to do this is that the
18945 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18946 architecture. This code picks MIPS I for 'mips' and MIPS III for
18947 'mips64', just as we did in the days before 'from-abi'. */
18948 if (strcasecmp (cpu_string, "from-abi") == 0)
18950 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18951 return mips_cpu_info_from_isa (ISA_MIPS1);
18953 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18954 return mips_cpu_info_from_isa (ISA_MIPS3);
18956 if (file_mips_opts.gp >= 0)
18957 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
18958 ? ISA_MIPS1 : ISA_MIPS3);
18960 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18965 /* 'default' has traditionally been a no-op. Probably not very useful. */
18966 if (strcasecmp (cpu_string, "default") == 0)
18969 for (p = mips_cpu_info_table; p->name != 0; p++)
18970 if (mips_matching_cpu_name_p (p->name, cpu_string))
18973 as_bad (_("bad value (%s) for %s"), cpu_string, option);
18977 /* Return the canonical processor information for ISA (a member of the
18978 ISA_MIPS* enumeration). */
18980 static const struct mips_cpu_info *
18981 mips_cpu_info_from_isa (int isa)
18985 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18986 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18987 && isa == mips_cpu_info_table[i].isa)
18988 return (&mips_cpu_info_table[i]);
18993 static const struct mips_cpu_info *
18994 mips_cpu_info_from_arch (int arch)
18998 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18999 if (arch == mips_cpu_info_table[i].cpu)
19000 return (&mips_cpu_info_table[i]);
19006 show (FILE *stream, const char *string, int *col_p, int *first_p)
19010 fprintf (stream, "%24s", "");
19015 fprintf (stream, ", ");
19019 if (*col_p + strlen (string) > 72)
19021 fprintf (stream, "\n%24s", "");
19025 fprintf (stream, "%s", string);
19026 *col_p += strlen (string);
19032 md_show_usage (FILE *stream)
19037 fprintf (stream, _("\
19039 -EB generate big endian output\n\
19040 -EL generate little endian output\n\
19041 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19042 -G NUM allow referencing objects up to NUM bytes\n\
19043 implicitly with the gp register [default 8]\n"));
19044 fprintf (stream, _("\
19045 -mips1 generate MIPS ISA I instructions\n\
19046 -mips2 generate MIPS ISA II instructions\n\
19047 -mips3 generate MIPS ISA III instructions\n\
19048 -mips4 generate MIPS ISA IV instructions\n\
19049 -mips5 generate MIPS ISA V instructions\n\
19050 -mips32 generate MIPS32 ISA instructions\n\
19051 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19052 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19053 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19054 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19055 -mips64 generate MIPS64 ISA instructions\n\
19056 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19057 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19058 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19059 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19060 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19064 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19065 show (stream, mips_cpu_info_table[i].name, &column, &first);
19066 show (stream, "from-abi", &column, &first);
19067 fputc ('\n', stream);
19069 fprintf (stream, _("\
19070 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19071 -no-mCPU don't generate code specific to CPU.\n\
19072 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19076 show (stream, "3900", &column, &first);
19077 show (stream, "4010", &column, &first);
19078 show (stream, "4100", &column, &first);
19079 show (stream, "4650", &column, &first);
19080 fputc ('\n', stream);
19082 fprintf (stream, _("\
19083 -mips16 generate mips16 instructions\n\
19084 -no-mips16 do not generate mips16 instructions\n"));
19085 fprintf (stream, _("\
19086 -mmicromips generate microMIPS instructions\n\
19087 -mno-micromips do not generate microMIPS instructions\n"));
19088 fprintf (stream, _("\
19089 -msmartmips generate smartmips instructions\n\
19090 -mno-smartmips do not generate smartmips instructions\n"));
19091 fprintf (stream, _("\
19092 -mdsp generate DSP instructions\n\
19093 -mno-dsp do not generate DSP instructions\n"));
19094 fprintf (stream, _("\
19095 -mdspr2 generate DSP R2 instructions\n\
19096 -mno-dspr2 do not generate DSP R2 instructions\n"));
19097 fprintf (stream, _("\
19098 -mdspr3 generate DSP R3 instructions\n\
19099 -mno-dspr3 do not generate DSP R3 instructions\n"));
19100 fprintf (stream, _("\
19101 -mmt generate MT instructions\n\
19102 -mno-mt do not generate MT instructions\n"));
19103 fprintf (stream, _("\
19104 -mmcu generate MCU instructions\n\
19105 -mno-mcu do not generate MCU instructions\n"));
19106 fprintf (stream, _("\
19107 -mmsa generate MSA instructions\n\
19108 -mno-msa do not generate MSA instructions\n"));
19109 fprintf (stream, _("\
19110 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19111 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19112 fprintf (stream, _("\
19113 -mvirt generate Virtualization instructions\n\
19114 -mno-virt do not generate Virtualization instructions\n"));
19115 fprintf (stream, _("\
19116 -minsn32 only generate 32-bit microMIPS instructions\n\
19117 -mno-insn32 generate all microMIPS instructions\n"));
19118 fprintf (stream, _("\
19119 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19120 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19121 -mfix-vr4120 work around certain VR4120 errata\n\
19122 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19123 -mfix-24k insert a nop after ERET and DERET instructions\n\
19124 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19125 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19126 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19127 -msym32 assume all symbols have 32-bit values\n\
19128 -O0 remove unneeded NOPs, do not swap branches\n\
19129 -O remove unneeded NOPs and swap branches\n\
19130 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19131 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19132 fprintf (stream, _("\
19133 -mhard-float allow floating-point instructions\n\
19134 -msoft-float do not allow floating-point instructions\n\
19135 -msingle-float only allow 32-bit floating-point operations\n\
19136 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19137 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19138 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19139 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19143 show (stream, "legacy", &column, &first);
19144 show (stream, "2008", &column, &first);
19146 fputc ('\n', stream);
19148 fprintf (stream, _("\
19149 -KPIC, -call_shared generate SVR4 position independent code\n\
19150 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19151 -mvxworks-pic generate VxWorks position independent code\n\
19152 -non_shared do not generate code that can operate with DSOs\n\
19153 -xgot assume a 32 bit GOT\n\
19154 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19155 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19156 position dependent (non shared) code\n\
19157 -mabi=ABI create ABI conformant object file for:\n"));
19161 show (stream, "32", &column, &first);
19162 show (stream, "o64", &column, &first);
19163 show (stream, "n32", &column, &first);
19164 show (stream, "64", &column, &first);
19165 show (stream, "eabi", &column, &first);
19167 fputc ('\n', stream);
19169 fprintf (stream, _("\
19170 -32 create o32 ABI object file (default)\n\
19171 -n32 create n32 ABI object file\n\
19172 -64 create 64 ABI object file\n"));
19177 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19179 if (HAVE_64BIT_SYMBOLS)
19180 return dwarf2_format_64bit_irix;
19182 return dwarf2_format_32bit;
19187 mips_dwarf2_addr_size (void)
19189 if (HAVE_64BIT_OBJECTS)
19195 /* Standard calling conventions leave the CFA at SP on entry. */
19197 mips_cfi_frame_initial_instructions (void)
19199 cfi_add_CFA_def_cfa_register (SP);
19203 tc_mips_regname_to_dw2regnum (char *regname)
19205 unsigned int regnum = -1;
19208 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
19214 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19215 Given a symbolic attribute NAME, return the proper integer value.
19216 Returns -1 if the attribute is not known. */
19219 mips_convert_symbolic_attribute (const char *name)
19221 static const struct
19226 attribute_table[] =
19228 #define T(tag) {#tag, tag}
19229 T (Tag_GNU_MIPS_ABI_FP),
19230 T (Tag_GNU_MIPS_ABI_MSA),
19238 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19239 if (streq (name, attribute_table[i].name))
19240 return attribute_table[i].tag;
19248 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19250 mips_emit_delays ();
19252 as_warn (_("missing .end at end of assembly"));
19254 /* Just in case no code was emitted, do the consistency check. */
19255 file_mips_check_options ();
19257 /* Set a floating-point ABI if the user did not. */
19258 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19260 /* Perform consistency checks on the floating-point ABI. */
19261 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19262 Tag_GNU_MIPS_ABI_FP);
19263 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19264 check_fpabi (fpabi);
19268 /* Soft-float gets precedence over single-float, the two options should
19269 not be used together so this should not matter. */
19270 if (file_mips_opts.soft_float == 1)
19271 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19272 /* Single-float gets precedence over all double_float cases. */
19273 else if (file_mips_opts.single_float == 1)
19274 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19277 switch (file_mips_opts.fp)
19280 if (file_mips_opts.gp == 32)
19281 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19284 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19287 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19288 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19289 else if (file_mips_opts.gp == 32)
19290 fpabi = Val_GNU_MIPS_ABI_FP_64;
19292 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19297 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19298 Tag_GNU_MIPS_ABI_FP, fpabi);
19302 /* Returns the relocation type required for a particular CFI encoding. */
19304 bfd_reloc_code_real_type
19305 mips_cfi_reloc_for_encoding (int encoding)
19307 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
19308 return BFD_RELOC_32_PCREL;
19309 else return BFD_RELOC_NONE;