1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi = NO_ABI;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls = FALSE;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared = TRUE;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). These are set to -1
208 if they have not been initialized. Changed by `.set <asename>', by
209 command line options, and based on the default architecture. */
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
222 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
223 1 if we are, and -1 if the value has not been initialized. Changed
224 by `.set micromips' and `.set nomicromips', and the -mmicromips
225 and -mno-micromips command line options, and the default CPU. */
227 /* Non-zero if we should not reorder instructions. Changed by `.set
228 reorder' and `.set noreorder'. */
230 /* Non-zero if we should not permit the register designated "assembler
231 temporary" to be used in instructions. The value is the register
232 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
233 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
235 /* Non-zero if we should warn when a macro instruction expands into
236 more than one machine instruction. Changed by `.set nomacro' and
238 int warn_about_macros;
239 /* Non-zero if we should not move instructions. Changed by `.set
240 move', `.set volatile', `.set nomove', and `.set novolatile'. */
242 /* Non-zero if we should not optimize branches by moving the target
243 of the branch into the delay slot. Actually, we don't perform
244 this optimization anyhow. Changed by `.set bopt' and `.set
247 /* Non-zero if we should not autoextend mips16 instructions.
248 Changed by `.set autoextend' and `.set noautoextend'. */
250 /* Restrict general purpose registers and floating point registers
251 to 32 bit. This is initially determined when -mgp32 or -mfp32
252 is passed but can changed if the assembler code uses .set mipsN. */
255 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
256 command line option, and the default CPU. */
258 /* True if ".set sym32" is in effect. */
260 /* True if floating-point operations are not allowed. Changed by .set
261 softfloat or .set hardfloat, by command line options -msoft-float or
262 -mhard-float. The default is false. */
263 bfd_boolean soft_float;
265 /* True if only single-precision floating-point operations are allowed.
266 Changed by .set singlefloat or .set doublefloat, command-line options
267 -msingle-float or -mdouble-float. The default is false. */
268 bfd_boolean single_float;
271 /* This is the struct we use to hold the current set of options. Note
272 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
273 -1 to indicate that they have not been initialized. */
275 /* True if -mgp32 was passed. */
276 static int file_mips_gp32 = -1;
278 /* True if -mfp32 was passed. */
279 static int file_mips_fp32 = -1;
281 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
282 static int file_mips_soft_float = 0;
284 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
285 static int file_mips_single_float = 0;
287 static struct mips_set_options mips_opts =
289 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
290 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
291 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
292 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
293 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
294 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* True if -mips3d was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_mips3d;
333 /* True if -mdmx was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mdmx;
337 /* True if -msmartmips was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_smartmips;
341 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
342 || mips_opts.isa == ISA_MIPS32R2)
344 /* True if -mdsp was passed or implied by arguments passed on the
345 command line (e.g., by -march). */
346 static int file_ase_dsp;
348 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
349 || mips_opts.isa == ISA_MIPS64R2 \
350 || mips_opts.micromips)
352 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mdspr2 was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_dspr2;
358 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2 \
360 || mips_opts.micromips)
362 /* True if -mmt was passed or implied by arguments passed on the
363 command line (e.g., by -march). */
364 static int file_ase_mt;
366 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
367 || mips_opts.isa == ISA_MIPS64R2)
369 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2 \
371 || mips_opts.micromips)
373 /* The argument of the -march= flag. The architecture we are assembling. */
374 static int file_mips_arch = CPU_UNKNOWN;
375 static const char *mips_arch_string;
377 /* The argument of the -mtune= flag. The architecture for which we
379 static int mips_tune = CPU_UNKNOWN;
380 static const char *mips_tune_string;
382 /* True when generating 32-bit code for a 64-bit processor. */
383 static int mips_32bitmode = 0;
385 /* True if the given ABI requires 32-bit registers. */
386 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
388 /* Likewise 64-bit registers. */
389 #define ABI_NEEDS_64BIT_REGS(ABI) \
391 || (ABI) == N64_ABI \
394 /* Return true if ISA supports 64 bit wide gp registers. */
395 #define ISA_HAS_64BIT_REGS(ISA) \
396 ((ISA) == ISA_MIPS3 \
397 || (ISA) == ISA_MIPS4 \
398 || (ISA) == ISA_MIPS5 \
399 || (ISA) == ISA_MIPS64 \
400 || (ISA) == ISA_MIPS64R2)
402 /* Return true if ISA supports 64 bit wide float registers. */
403 #define ISA_HAS_64BIT_FPRS(ISA) \
404 ((ISA) == ISA_MIPS3 \
405 || (ISA) == ISA_MIPS4 \
406 || (ISA) == ISA_MIPS5 \
407 || (ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64 \
409 || (ISA) == ISA_MIPS64R2)
411 /* Return true if ISA supports 64-bit right rotate (dror et al.)
413 #define ISA_HAS_DROR(ISA) \
414 ((ISA) == ISA_MIPS64R2 \
415 || (mips_opts.micromips \
416 && ISA_HAS_64BIT_REGS (ISA)) \
419 /* Return true if ISA supports 32-bit right rotate (ror et al.)
421 #define ISA_HAS_ROR(ISA) \
422 ((ISA) == ISA_MIPS32R2 \
423 || (ISA) == ISA_MIPS64R2 \
424 || mips_opts.ase_smartmips \
425 || mips_opts.micromips \
428 /* Return true if ISA supports single-precision floats in odd registers. */
429 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
430 ((ISA) == ISA_MIPS32 \
431 || (ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS64 \
433 || (ISA) == ISA_MIPS64R2)
435 /* Return true if ISA supports move to/from high part of a 64-bit
436 floating-point register. */
437 #define ISA_HAS_MXHC1(ISA) \
438 ((ISA) == ISA_MIPS32R2 \
439 || (ISA) == ISA_MIPS64R2)
441 #define HAVE_32BIT_GPRS \
442 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
444 #define HAVE_32BIT_FPRS \
445 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
447 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
448 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
450 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
452 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
454 /* True if relocations are stored in-place. */
455 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
457 /* The ABI-derived address size. */
458 #define HAVE_64BIT_ADDRESSES \
459 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
460 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
462 /* The size of symbolic constants (i.e., expressions of the form
463 "SYMBOL" or "SYMBOL + OFFSET"). */
464 #define HAVE_32BIT_SYMBOLS \
465 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
466 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
468 /* Addresses are loaded in different ways, depending on the address size
469 in use. The n32 ABI Documentation also mandates the use of additions
470 with overflow checking, but existing implementations don't follow it. */
471 #define ADDRESS_ADD_INSN \
472 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
474 #define ADDRESS_ADDI_INSN \
475 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
477 #define ADDRESS_LOAD_INSN \
478 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
480 #define ADDRESS_STORE_INSN \
481 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
483 /* Return true if the given CPU supports the MIPS16 ASE. */
484 #define CPU_HAS_MIPS16(cpu) \
485 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
486 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
488 /* Return true if the given CPU supports the microMIPS ASE. */
489 #define CPU_HAS_MICROMIPS(cpu) 0
491 /* True if CPU has a dror instruction. */
492 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
494 /* True if CPU has a ror instruction. */
495 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
497 /* True if CPU is in the Octeon family */
498 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
500 /* True if CPU has seq/sne and seqi/snei instructions. */
501 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
574 has been selected. This implies, in particular, that addresses of text
575 labels have their LSB set. */
576 #define HAVE_CODE_COMPRESSION \
577 ((mips_opts.mips16 | mips_opts.micromips) != 0)
579 /* MIPS PIC level. */
581 enum mips_pic_level mips_pic;
583 /* 1 if we should generate 32 bit offsets from the $gp register in
584 SVR4_PIC mode. Currently has no meaning in other modes. */
585 static int mips_big_got = 0;
587 /* 1 if trap instructions should used for overflow rather than break
589 static int mips_trap = 0;
591 /* 1 if double width floating point constants should not be constructed
592 by assembling two single width halves into two single width floating
593 point registers which just happen to alias the double width destination
594 register. On some architectures this aliasing can be disabled by a bit
595 in the status register, and the setting of this bit cannot be determined
596 automatically at assemble time. */
597 static int mips_disable_float_construction;
599 /* Non-zero if any .set noreorder directives were used. */
601 static int mips_any_noreorder;
603 /* Non-zero if nops should be inserted when the register referenced in
604 an mfhi/mflo instruction is read in the next two instructions. */
605 static int mips_7000_hilo_fix;
607 /* The size of objects in the small data section. */
608 static unsigned int g_switch_value = 8;
609 /* Whether the -G option was used. */
610 static int g_switch_seen = 0;
615 /* If we can determine in advance that GP optimization won't be
616 possible, we can skip the relaxation stuff that tries to produce
617 GP-relative references. This makes delay slot optimization work
620 This function can only provide a guess, but it seems to work for
621 gcc output. It needs to guess right for gcc, otherwise gcc
622 will put what it thinks is a GP-relative instruction in a branch
625 I don't know if a fix is needed for the SVR4_PIC mode. I've only
626 fixed it for the non-PIC mode. KR 95/04/07 */
627 static int nopic_need_relax (symbolS *, int);
629 /* handle of the OPCODE hash table */
630 static struct hash_control *op_hash = NULL;
632 /* The opcode hash table we use for the mips16. */
633 static struct hash_control *mips16_op_hash = NULL;
635 /* The opcode hash table we use for the microMIPS ASE. */
636 static struct hash_control *micromips_op_hash = NULL;
638 /* This array holds the chars that always start a comment. If the
639 pre-processor is disabled, these aren't very useful */
640 const char comment_chars[] = "#";
642 /* This array holds the chars that only start a comment at the beginning of
643 a line. If the line seems to have the form '# 123 filename'
644 .line and .file directives will appear in the pre-processed output */
645 /* Note that input_file.c hand checks for '#' at the beginning of the
646 first line of the input file. This is because the compiler outputs
647 #NO_APP at the beginning of its output. */
648 /* Also note that C style comments are always supported. */
649 const char line_comment_chars[] = "#";
651 /* This array holds machine specific line separator characters. */
652 const char line_separator_chars[] = ";";
654 /* Chars that can be used to separate mant from exp in floating point nums */
655 const char EXP_CHARS[] = "eE";
657 /* Chars that mean this number is a floating point constant */
660 const char FLT_CHARS[] = "rRsSfFdDxXpP";
662 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
663 changed in read.c . Ideally it shouldn't have to know about it at all,
664 but nothing is ideal around here.
667 static char *insn_error;
669 static int auto_align = 1;
671 /* When outputting SVR4 PIC code, the assembler needs to know the
672 offset in the stack frame from which to restore the $gp register.
673 This is set by the .cprestore pseudo-op, and saved in this
675 static offsetT mips_cprestore_offset = -1;
677 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
678 more optimizations, it can use a register value instead of a memory-saved
679 offset and even an other register than $gp as global pointer. */
680 static offsetT mips_cpreturn_offset = -1;
681 static int mips_cpreturn_register = -1;
682 static int mips_gp_register = GP;
683 static int mips_gprel_offset = 0;
685 /* Whether mips_cprestore_offset has been set in the current function
686 (or whether it has already been warned about, if not). */
687 static int mips_cprestore_valid = 0;
689 /* This is the register which holds the stack frame, as set by the
690 .frame pseudo-op. This is needed to implement .cprestore. */
691 static int mips_frame_reg = SP;
693 /* Whether mips_frame_reg has been set in the current function
694 (or whether it has already been warned about, if not). */
695 static int mips_frame_reg_valid = 0;
697 /* To output NOP instructions correctly, we need to keep information
698 about the previous two instructions. */
700 /* Whether we are optimizing. The default value of 2 means to remove
701 unneeded NOPs and swap branch instructions when possible. A value
702 of 1 means to not swap branches. A value of 0 means to always
704 static int mips_optimize = 2;
706 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
707 equivalent to seeing no -g option at all. */
708 static int mips_debug = 0;
710 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
711 #define MAX_VR4130_NOPS 4
713 /* The maximum number of NOPs needed to fill delay slots. */
714 #define MAX_DELAY_NOPS 2
716 /* The maximum number of NOPs needed for any purpose. */
719 /* A list of previous instructions, with index 0 being the most recent.
720 We need to look back MAX_NOPS instructions when filling delay slots
721 or working around processor errata. We need to look back one
722 instruction further if we're thinking about using history[0] to
723 fill a branch delay slot. */
724 static struct mips_cl_insn history[1 + MAX_NOPS];
726 /* Nop instructions used by emit_nop. */
727 static struct mips_cl_insn nop_insn;
728 static struct mips_cl_insn mips16_nop_insn;
729 static struct mips_cl_insn micromips_nop16_insn;
730 static struct mips_cl_insn micromips_nop32_insn;
732 /* The appropriate nop for the current mode. */
733 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
734 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
736 /* The size of NOP_INSN in bytes. */
737 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
739 /* If this is set, it points to a frag holding nop instructions which
740 were inserted before the start of a noreorder section. If those
741 nops turn out to be unnecessary, the size of the frag can be
743 static fragS *prev_nop_frag;
745 /* The number of nop instructions we created in prev_nop_frag. */
746 static int prev_nop_frag_holds;
748 /* The number of nop instructions that we know we need in
750 static int prev_nop_frag_required;
752 /* The number of instructions we've seen since prev_nop_frag. */
753 static int prev_nop_frag_since;
755 /* For ECOFF and ELF, relocations against symbols are done in two
756 parts, with a HI relocation and a LO relocation. Each relocation
757 has only 16 bits of space to store an addend. This means that in
758 order for the linker to handle carries correctly, it must be able
759 to locate both the HI and the LO relocation. This means that the
760 relocations must appear in order in the relocation table.
762 In order to implement this, we keep track of each unmatched HI
763 relocation. We then sort them so that they immediately precede the
764 corresponding LO relocation. */
769 struct mips_hi_fixup *next;
772 /* The section this fixup is in. */
776 /* The list of unmatched HI relocs. */
778 static struct mips_hi_fixup *mips_hi_fixup_list;
780 /* The frag containing the last explicit relocation operator.
781 Null if explicit relocations have not been used. */
783 static fragS *prev_reloc_op_frag;
785 /* Map normal MIPS register numbers to mips16 register numbers. */
787 #define X ILLEGAL_REG
788 static const int mips32_to_16_reg_map[] =
790 X, X, 2, 3, 4, 5, 6, 7,
791 X, X, X, X, X, X, X, X,
792 0, 1, X, X, X, X, X, X,
793 X, X, X, X, X, X, X, X
797 /* Map mips16 register numbers to normal MIPS register numbers. */
799 static const unsigned int mips16_to_32_reg_map[] =
801 16, 17, 2, 3, 4, 5, 6, 7
804 /* Map normal MIPS register numbers to microMIPS register numbers. */
806 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
807 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
808 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
809 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
810 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
811 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
812 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
814 #define X ILLEGAL_REG
815 /* reg type h: 4, 5, 6. */
816 static const int mips32_to_micromips_reg_h_map[] =
818 X, X, X, X, 4, 5, 6, X,
819 X, X, X, X, X, X, X, X,
820 X, X, X, X, X, X, X, X,
821 X, X, X, X, X, X, X, X
824 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
825 static const int mips32_to_micromips_reg_m_map[] =
827 0, X, 2, 3, X, X, X, X,
828 X, X, X, X, X, X, X, X,
829 4, 1, 5, 6, 7, X, X, X,
830 X, X, X, X, X, X, X, X
833 /* reg type q: 0, 2-7. 17. */
834 static const int mips32_to_micromips_reg_q_map[] =
836 0, X, 2, 3, 4, 5, 6, 7,
837 X, X, X, X, X, X, X, X,
838 X, 1, X, X, X, X, X, X,
839 X, X, X, X, X, X, X, X
842 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
845 /* Map microMIPS register numbers to normal MIPS register numbers. */
847 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
848 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
849 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
850 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
851 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
852 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
854 /* The microMIPS registers with type h. */
855 static const unsigned int micromips_to_32_reg_h_map[] =
857 5, 5, 6, 4, 4, 4, 4, 4
860 /* The microMIPS registers with type i. */
861 static const unsigned int micromips_to_32_reg_i_map[] =
863 6, 7, 7, 21, 22, 5, 6, 7
866 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
868 /* The microMIPS registers with type m. */
869 static const unsigned int micromips_to_32_reg_m_map[] =
871 0, 17, 2, 3, 16, 18, 19, 20
874 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
876 /* The microMIPS registers with type q. */
877 static const unsigned int micromips_to_32_reg_q_map[] =
879 0, 17, 2, 3, 4, 5, 6, 7
882 /* microMIPS imm type B. */
883 static const int micromips_imm_b_map[] =
885 1, 4, 8, 12, 16, 20, 24, -1
888 /* microMIPS imm type C. */
889 static const int micromips_imm_c_map[] =
891 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
894 /* Classifies the kind of instructions we're interested in when
895 implementing -mfix-vr4120. */
896 enum fix_vr4120_class
904 NUM_FIX_VR4120_CLASSES
907 /* ...likewise -mfix-loongson2f-jump. */
908 static bfd_boolean mips_fix_loongson2f_jump;
910 /* ...likewise -mfix-loongson2f-nop. */
911 static bfd_boolean mips_fix_loongson2f_nop;
913 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
914 static bfd_boolean mips_fix_loongson2f;
916 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
917 there must be at least one other instruction between an instruction
918 of type X and an instruction of type Y. */
919 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
921 /* True if -mfix-vr4120 is in force. */
922 static int mips_fix_vr4120;
924 /* ...likewise -mfix-vr4130. */
925 static int mips_fix_vr4130;
927 /* ...likewise -mfix-24k. */
928 static int mips_fix_24k;
930 /* ...likewise -mfix-cn63xxp1 */
931 static bfd_boolean mips_fix_cn63xxp1;
933 /* We don't relax branches by default, since this causes us to expand
934 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
935 fail to compute the offset before expanding the macro to the most
936 efficient expansion. */
938 static int mips_relax_branch;
940 /* The expansion of many macros depends on the type of symbol that
941 they refer to. For example, when generating position-dependent code,
942 a macro that refers to a symbol may have two different expansions,
943 one which uses GP-relative addresses and one which uses absolute
944 addresses. When generating SVR4-style PIC, a macro may have
945 different expansions for local and global symbols.
947 We handle these situations by generating both sequences and putting
948 them in variant frags. In position-dependent code, the first sequence
949 will be the GP-relative one and the second sequence will be the
950 absolute one. In SVR4 PIC, the first sequence will be for global
951 symbols and the second will be for local symbols.
953 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
954 SECOND are the lengths of the two sequences in bytes. These fields
955 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
956 the subtype has the following flags:
959 Set if it has been decided that we should use the second
960 sequence instead of the first.
963 Set in the first variant frag if the macro's second implementation
964 is longer than its first. This refers to the macro as a whole,
965 not an individual relaxation.
968 Set in the first variant frag if the macro appeared in a .set nomacro
969 block and if one alternative requires a warning but the other does not.
972 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
975 RELAX_DELAY_SLOT_16BIT
976 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
979 RELAX_DELAY_SLOT_SIZE_FIRST
980 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
981 the macro is of the wrong size for the branch delay slot.
983 RELAX_DELAY_SLOT_SIZE_SECOND
984 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
985 the macro is of the wrong size for the branch delay slot.
987 The frag's "opcode" points to the first fixup for relaxable code.
989 Relaxable macros are generated using a sequence such as:
991 relax_start (SYMBOL);
992 ... generate first expansion ...
994 ... generate second expansion ...
997 The code and fixups for the unwanted alternative are discarded
998 by md_convert_frag. */
999 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1001 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1002 #define RELAX_SECOND(X) ((X) & 0xff)
1003 #define RELAX_USE_SECOND 0x10000
1004 #define RELAX_SECOND_LONGER 0x20000
1005 #define RELAX_NOMACRO 0x40000
1006 #define RELAX_DELAY_SLOT 0x80000
1007 #define RELAX_DELAY_SLOT_16BIT 0x100000
1008 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1009 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1011 /* Branch without likely bit. If label is out of range, we turn:
1013 beq reg1, reg2, label
1023 with the following opcode replacements:
1030 bltzal <-> bgezal (with jal label instead of j label)
1032 Even though keeping the delay slot instruction in the delay slot of
1033 the branch would be more efficient, it would be very tricky to do
1034 correctly, because we'd have to introduce a variable frag *after*
1035 the delay slot instruction, and expand that instead. Let's do it
1036 the easy way for now, even if the branch-not-taken case now costs
1037 one additional instruction. Out-of-range branches are not supposed
1038 to be common, anyway.
1040 Branch likely. If label is out of range, we turn:
1042 beql reg1, reg2, label
1043 delay slot (annulled if branch not taken)
1052 delay slot (executed only if branch taken)
1055 It would be possible to generate a shorter sequence by losing the
1056 likely bit, generating something like:
1061 delay slot (executed only if branch taken)
1073 bltzall -> bgezal (with jal label instead of j label)
1074 bgezall -> bltzal (ditto)
1077 but it's not clear that it would actually improve performance. */
1078 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1079 ((relax_substateT) \
1082 | ((toofar) ? 0x20 : 0) \
1083 | ((link) ? 0x40 : 0) \
1084 | ((likely) ? 0x80 : 0) \
1085 | ((uncond) ? 0x100 : 0)))
1086 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1087 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1088 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1089 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1090 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1091 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1093 /* For mips16 code, we use an entirely different form of relaxation.
1094 mips16 supports two versions of most instructions which take
1095 immediate values: a small one which takes some small value, and a
1096 larger one which takes a 16 bit value. Since branches also follow
1097 this pattern, relaxing these values is required.
1099 We can assemble both mips16 and normal MIPS code in a single
1100 object. Therefore, we need to support this type of relaxation at
1101 the same time that we support the relaxation described above. We
1102 use the high bit of the subtype field to distinguish these cases.
1104 The information we store for this type of relaxation is the
1105 argument code found in the opcode file for this relocation, whether
1106 the user explicitly requested a small or extended form, and whether
1107 the relocation is in a jump or jal delay slot. That tells us the
1108 size of the value, and how it should be stored. We also store
1109 whether the fragment is considered to be extended or not. We also
1110 store whether this is known to be a branch to a different section,
1111 whether we have tried to relax this frag yet, and whether we have
1112 ever extended a PC relative fragment because of a shift count. */
1113 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1116 | ((small) ? 0x100 : 0) \
1117 | ((ext) ? 0x200 : 0) \
1118 | ((dslot) ? 0x400 : 0) \
1119 | ((jal_dslot) ? 0x800 : 0))
1120 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1121 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1123 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1124 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1125 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1126 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1127 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1128 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1129 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1130 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1131 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1133 /* For microMIPS code, we use relaxation similar to one we use for
1134 MIPS16 code. Some instructions that take immediate values support
1135 two encodings: a small one which takes some small value, and a
1136 larger one which takes a 16 bit value. As some branches also follow
1137 this pattern, relaxing these values is required.
1139 We can assemble both microMIPS and normal MIPS code in a single
1140 object. Therefore, we need to support this type of relaxation at
1141 the same time that we support the relaxation described above. We
1142 use one of the high bits of the subtype field to distinguish these
1145 The information we store for this type of relaxation is the argument
1146 code found in the opcode file for this relocation, the register
1147 selected as the assembler temporary, whether the branch is
1148 unconditional, whether it is compact, whether it stores the link
1149 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1150 branches to a sequence of instructions is enabled, and whether the
1151 displacement of a branch is too large to fit as an immediate argument
1152 of a 16-bit and a 32-bit branch, respectively. */
1153 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1154 relax32, toofar16, toofar32) \
1157 | (((at) & 0x1f) << 8) \
1158 | ((uncond) ? 0x2000 : 0) \
1159 | ((compact) ? 0x4000 : 0) \
1160 | ((link) ? 0x8000 : 0) \
1161 | ((relax32) ? 0x10000 : 0) \
1162 | ((toofar16) ? 0x20000 : 0) \
1163 | ((toofar32) ? 0x40000 : 0))
1164 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1165 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1166 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1167 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1168 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1169 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1170 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1172 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1173 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1174 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1175 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1176 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1177 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1179 /* Is the given value a sign-extended 32-bit value? */
1180 #define IS_SEXT_32BIT_NUM(x) \
1181 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1182 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1184 /* Is the given value a sign-extended 16-bit value? */
1185 #define IS_SEXT_16BIT_NUM(x) \
1186 (((x) &~ (offsetT) 0x7fff) == 0 \
1187 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1189 /* Is the given value a sign-extended 12-bit value? */
1190 #define IS_SEXT_12BIT_NUM(x) \
1191 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1193 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1194 #define IS_ZEXT_32BIT_NUM(x) \
1195 (((x) &~ (offsetT) 0xffffffff) == 0 \
1196 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1198 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1199 VALUE << SHIFT. VALUE is evaluated exactly once. */
1200 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1201 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1202 | (((VALUE) & (MASK)) << (SHIFT)))
1204 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1206 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1207 (((STRUCT) >> (SHIFT)) & (MASK))
1209 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1210 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1212 include/opcode/mips.h specifies operand fields using the macros
1213 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1214 with "MIPS16OP" instead of "OP". */
1215 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1218 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1219 OP_MASK_##FIELD, OP_SH_##FIELD); \
1221 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1224 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1225 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1226 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1228 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1229 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1231 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1232 : EXTRACT_BITS ((INSN).insn_opcode, \
1233 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1234 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1235 EXTRACT_BITS ((INSN).insn_opcode, \
1236 MIPS16OP_MASK_##FIELD, \
1237 MIPS16OP_SH_##FIELD)
1239 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1240 #define MIPS16_EXTEND (0xf000U << 16)
1242 /* Whether or not we are emitting a branch-likely macro. */
1243 static bfd_boolean emit_branch_likely_macro = FALSE;
1245 /* Global variables used when generating relaxable macros. See the
1246 comment above RELAX_ENCODE for more details about how relaxation
1249 /* 0 if we're not emitting a relaxable macro.
1250 1 if we're emitting the first of the two relaxation alternatives.
1251 2 if we're emitting the second alternative. */
1254 /* The first relaxable fixup in the current frag. (In other words,
1255 the first fixup that refers to relaxable code.) */
1258 /* sizes[0] says how many bytes of the first alternative are stored in
1259 the current frag. Likewise sizes[1] for the second alternative. */
1260 unsigned int sizes[2];
1262 /* The symbol on which the choice of sequence depends. */
1266 /* Global variables used to decide whether a macro needs a warning. */
1268 /* True if the macro is in a branch delay slot. */
1269 bfd_boolean delay_slot_p;
1271 /* Set to the length in bytes required if the macro is in a delay slot
1272 that requires a specific length of instruction, otherwise zero. */
1273 unsigned int delay_slot_length;
1275 /* For relaxable macros, sizes[0] is the length of the first alternative
1276 in bytes and sizes[1] is the length of the second alternative.
1277 For non-relaxable macros, both elements give the length of the
1279 unsigned int sizes[2];
1281 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1282 instruction of the first alternative in bytes and first_insn_sizes[1]
1283 is the length of the first instruction of the second alternative.
1284 For non-relaxable macros, both elements give the length of the first
1285 instruction in bytes.
1287 Set to zero if we haven't yet seen the first instruction. */
1288 unsigned int first_insn_sizes[2];
1290 /* For relaxable macros, insns[0] is the number of instructions for the
1291 first alternative and insns[1] is the number of instructions for the
1294 For non-relaxable macros, both elements give the number of
1295 instructions for the macro. */
1296 unsigned int insns[2];
1298 /* The first variant frag for this macro. */
1300 } mips_macro_warning;
1302 /* Prototypes for static functions. */
1304 #define internalError() \
1305 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1307 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1309 static void append_insn
1310 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1311 bfd_boolean expansionp);
1312 static void mips_no_prev_insn (void);
1313 static void macro_build (expressionS *, const char *, const char *, ...);
1314 static void mips16_macro_build
1315 (expressionS *, const char *, const char *, va_list *);
1316 static void load_register (int, expressionS *, int);
1317 static void macro_start (void);
1318 static void macro_end (void);
1319 static void macro (struct mips_cl_insn * ip);
1320 static void mips16_macro (struct mips_cl_insn * ip);
1321 static void mips_ip (char *str, struct mips_cl_insn * ip);
1322 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1323 static void mips16_immed
1324 (char *, unsigned int, int, offsetT, unsigned int, unsigned long *);
1325 static size_t my_getSmallExpression
1326 (expressionS *, bfd_reloc_code_real_type *, char *);
1327 static void my_getExpression (expressionS *, char *);
1328 static void s_align (int);
1329 static void s_change_sec (int);
1330 static void s_change_section (int);
1331 static void s_cons (int);
1332 static void s_float_cons (int);
1333 static void s_mips_globl (int);
1334 static void s_option (int);
1335 static void s_mipsset (int);
1336 static void s_abicalls (int);
1337 static void s_cpload (int);
1338 static void s_cpsetup (int);
1339 static void s_cplocal (int);
1340 static void s_cprestore (int);
1341 static void s_cpreturn (int);
1342 static void s_dtprelword (int);
1343 static void s_dtpreldword (int);
1344 static void s_tprelword (int);
1345 static void s_tpreldword (int);
1346 static void s_gpvalue (int);
1347 static void s_gpword (int);
1348 static void s_gpdword (int);
1349 static void s_cpadd (int);
1350 static void s_insn (int);
1351 static void md_obj_begin (void);
1352 static void md_obj_end (void);
1353 static void s_mips_ent (int);
1354 static void s_mips_end (int);
1355 static void s_mips_frame (int);
1356 static void s_mips_mask (int reg_type);
1357 static void s_mips_stab (int);
1358 static void s_mips_weakext (int);
1359 static void s_mips_file (int);
1360 static void s_mips_loc (int);
1361 static bfd_boolean pic_need_relax (symbolS *, asection *);
1362 static int relaxed_branch_length (fragS *, asection *, int);
1363 static int validate_mips_insn (const struct mips_opcode *);
1364 static int validate_micromips_insn (const struct mips_opcode *);
1365 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1366 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1368 /* Table and functions used to map between CPU/ISA names, and
1369 ISA levels, and CPU numbers. */
1371 struct mips_cpu_info
1373 const char *name; /* CPU or ISA name. */
1374 int flags; /* ASEs available, or ISA flag. */
1375 int isa; /* ISA level. */
1376 int cpu; /* CPU number (default CPU if ISA). */
1379 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1380 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1381 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1382 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1383 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1384 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1385 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1386 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1388 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1389 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1390 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1394 The following pseudo-ops from the Kane and Heinrich MIPS book
1395 should be defined here, but are currently unsupported: .alias,
1396 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1398 The following pseudo-ops from the Kane and Heinrich MIPS book are
1399 specific to the type of debugging information being generated, and
1400 should be defined by the object format: .aent, .begin, .bend,
1401 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1404 The following pseudo-ops from the Kane and Heinrich MIPS book are
1405 not MIPS CPU specific, but are also not specific to the object file
1406 format. This file is probably the best place to define them, but
1407 they are not currently supported: .asm0, .endr, .lab, .struct. */
1409 static const pseudo_typeS mips_pseudo_table[] =
1411 /* MIPS specific pseudo-ops. */
1412 {"option", s_option, 0},
1413 {"set", s_mipsset, 0},
1414 {"rdata", s_change_sec, 'r'},
1415 {"sdata", s_change_sec, 's'},
1416 {"livereg", s_ignore, 0},
1417 {"abicalls", s_abicalls, 0},
1418 {"cpload", s_cpload, 0},
1419 {"cpsetup", s_cpsetup, 0},
1420 {"cplocal", s_cplocal, 0},
1421 {"cprestore", s_cprestore, 0},
1422 {"cpreturn", s_cpreturn, 0},
1423 {"dtprelword", s_dtprelword, 0},
1424 {"dtpreldword", s_dtpreldword, 0},
1425 {"tprelword", s_tprelword, 0},
1426 {"tpreldword", s_tpreldword, 0},
1427 {"gpvalue", s_gpvalue, 0},
1428 {"gpword", s_gpword, 0},
1429 {"gpdword", s_gpdword, 0},
1430 {"cpadd", s_cpadd, 0},
1431 {"insn", s_insn, 0},
1433 /* Relatively generic pseudo-ops that happen to be used on MIPS
1435 {"asciiz", stringer, 8 + 1},
1436 {"bss", s_change_sec, 'b'},
1438 {"half", s_cons, 1},
1439 {"dword", s_cons, 3},
1440 {"weakext", s_mips_weakext, 0},
1441 {"origin", s_org, 0},
1442 {"repeat", s_rept, 0},
1444 /* For MIPS this is non-standard, but we define it for consistency. */
1445 {"sbss", s_change_sec, 'B'},
1447 /* These pseudo-ops are defined in read.c, but must be overridden
1448 here for one reason or another. */
1449 {"align", s_align, 0},
1450 {"byte", s_cons, 0},
1451 {"data", s_change_sec, 'd'},
1452 {"double", s_float_cons, 'd'},
1453 {"float", s_float_cons, 'f'},
1454 {"globl", s_mips_globl, 0},
1455 {"global", s_mips_globl, 0},
1456 {"hword", s_cons, 1},
1458 {"long", s_cons, 2},
1459 {"octa", s_cons, 4},
1460 {"quad", s_cons, 3},
1461 {"section", s_change_section, 0},
1462 {"short", s_cons, 1},
1463 {"single", s_float_cons, 'f'},
1464 {"stabn", s_mips_stab, 'n'},
1465 {"text", s_change_sec, 't'},
1466 {"word", s_cons, 2},
1468 { "extern", ecoff_directive_extern, 0},
1473 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1475 /* These pseudo-ops should be defined by the object file format.
1476 However, a.out doesn't support them, so we have versions here. */
1477 {"aent", s_mips_ent, 1},
1478 {"bgnb", s_ignore, 0},
1479 {"end", s_mips_end, 0},
1480 {"endb", s_ignore, 0},
1481 {"ent", s_mips_ent, 0},
1482 {"file", s_mips_file, 0},
1483 {"fmask", s_mips_mask, 'F'},
1484 {"frame", s_mips_frame, 0},
1485 {"loc", s_mips_loc, 0},
1486 {"mask", s_mips_mask, 'R'},
1487 {"verstamp", s_ignore, 0},
1491 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1492 purpose of the `.dc.a' internal pseudo-op. */
1495 mips_address_bytes (void)
1497 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1500 extern void pop_insert (const pseudo_typeS *);
1503 mips_pop_insert (void)
1505 pop_insert (mips_pseudo_table);
1506 if (! ECOFF_DEBUGGING)
1507 pop_insert (mips_nonecoff_pseudo_table);
1510 /* Symbols labelling the current insn. */
1512 struct insn_label_list
1514 struct insn_label_list *next;
1518 static struct insn_label_list *free_insn_labels;
1519 #define label_list tc_segment_info_data.labels
1521 static void mips_clear_insn_labels (void);
1522 static void mips_mark_labels (void);
1523 static void mips_compressed_mark_labels (void);
1526 mips_clear_insn_labels (void)
1528 register struct insn_label_list **pl;
1529 segment_info_type *si;
1533 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1536 si = seg_info (now_seg);
1537 *pl = si->label_list;
1538 si->label_list = NULL;
1542 /* Mark instruction labels in MIPS16/microMIPS mode. */
1545 mips_mark_labels (void)
1547 if (HAVE_CODE_COMPRESSION)
1548 mips_compressed_mark_labels ();
1551 static char *expr_end;
1553 /* Expressions which appear in instructions. These are set by
1556 static expressionS imm_expr;
1557 static expressionS imm2_expr;
1558 static expressionS offset_expr;
1560 /* Relocs associated with imm_expr and offset_expr. */
1562 static bfd_reloc_code_real_type imm_reloc[3]
1563 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1564 static bfd_reloc_code_real_type offset_reloc[3]
1565 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1567 /* This is set to the resulting size of the instruction to be produced
1568 by mips16_ip if an explicit extension is used or by mips_ip if an
1569 explicit size is supplied. */
1571 static unsigned int forced_insn_length;
1574 /* The pdr segment for per procedure frame/regmask info. Not used for
1577 static segT pdr_seg;
1580 /* The default target format to use. */
1582 #if defined (TE_FreeBSD)
1583 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1584 #elif defined (TE_TMIPS)
1585 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1587 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1591 mips_target_format (void)
1593 switch (OUTPUT_FLAVOR)
1595 case bfd_target_ecoff_flavour:
1596 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1597 case bfd_target_coff_flavour:
1599 case bfd_target_elf_flavour:
1601 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1602 return (target_big_endian
1603 ? "elf32-bigmips-vxworks"
1604 : "elf32-littlemips-vxworks");
1606 return (target_big_endian
1607 ? (HAVE_64BIT_OBJECTS
1608 ? ELF_TARGET ("elf64-", "big")
1610 ? ELF_TARGET ("elf32-n", "big")
1611 : ELF_TARGET ("elf32-", "big")))
1612 : (HAVE_64BIT_OBJECTS
1613 ? ELF_TARGET ("elf64-", "little")
1615 ? ELF_TARGET ("elf32-n", "little")
1616 : ELF_TARGET ("elf32-", "little"))));
1623 /* Return the length of a microMIPS instruction in bytes. If bits of
1624 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1625 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1626 major opcode) will require further modifications to the opcode
1629 static inline unsigned int
1630 micromips_insn_length (const struct mips_opcode *mo)
1632 return (mo->mask >> 16) == 0 ? 2 : 4;
1635 /* Return the length of MIPS16 instruction OPCODE. */
1637 static inline unsigned int
1638 mips16_opcode_length (unsigned long opcode)
1640 return (opcode >> 16) == 0 ? 2 : 4;
1643 /* Return the length of instruction INSN. */
1645 static inline unsigned int
1646 insn_length (const struct mips_cl_insn *insn)
1648 if (mips_opts.micromips)
1649 return micromips_insn_length (insn->insn_mo);
1650 else if (mips_opts.mips16)
1651 return mips16_opcode_length (insn->insn_opcode);
1656 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1659 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1664 insn->insn_opcode = mo->match;
1667 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1668 insn->fixp[i] = NULL;
1669 insn->fixed_p = (mips_opts.noreorder > 0);
1670 insn->noreorder_p = (mips_opts.noreorder > 0);
1671 insn->mips16_absolute_jump_p = 0;
1672 insn->complete_p = 0;
1675 /* Record the current MIPS16/microMIPS mode in now_seg. */
1678 mips_record_compressed_mode (void)
1680 segment_info_type *si;
1682 si = seg_info (now_seg);
1683 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1684 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1685 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1686 si->tc_segment_info_data.micromips = mips_opts.micromips;
1689 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1690 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1693 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1697 for (i = 0; i < length; i += 2)
1698 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1699 return buf + length;
1702 /* Install INSN at the location specified by its "frag" and "where" fields. */
1705 install_insn (const struct mips_cl_insn *insn)
1707 char *f = insn->frag->fr_literal + insn->where;
1708 if (HAVE_CODE_COMPRESSION)
1709 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1711 md_number_to_chars (f, insn->insn_opcode, 4);
1712 mips_record_compressed_mode ();
1715 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1716 and install the opcode in the new location. */
1719 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1724 insn->where = where;
1725 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1726 if (insn->fixp[i] != NULL)
1728 insn->fixp[i]->fx_frag = frag;
1729 insn->fixp[i]->fx_where = where;
1731 install_insn (insn);
1734 /* Add INSN to the end of the output. */
1737 add_fixed_insn (struct mips_cl_insn *insn)
1739 char *f = frag_more (insn_length (insn));
1740 move_insn (insn, frag_now, f - frag_now->fr_literal);
1743 /* Start a variant frag and move INSN to the start of the variant part,
1744 marking it as fixed. The other arguments are as for frag_var. */
1747 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1748 relax_substateT subtype, symbolS *symbol, offsetT offset)
1750 frag_grow (max_chars);
1751 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1753 frag_var (rs_machine_dependent, max_chars, var,
1754 subtype, symbol, offset, NULL);
1757 /* Insert N copies of INSN into the history buffer, starting at
1758 position FIRST. Neither FIRST nor N need to be clipped. */
1761 insert_into_history (unsigned int first, unsigned int n,
1762 const struct mips_cl_insn *insn)
1764 if (mips_relax.sequence != 2)
1768 for (i = ARRAY_SIZE (history); i-- > first;)
1770 history[i] = history[i - n];
1776 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1777 the idea is to make it obvious at a glance that each errata is
1781 init_vr4120_conflicts (void)
1783 #define CONFLICT(FIRST, SECOND) \
1784 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1786 /* Errata 21 - [D]DIV[U] after [D]MACC */
1787 CONFLICT (MACC, DIV);
1788 CONFLICT (DMACC, DIV);
1790 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1791 CONFLICT (DMULT, DMULT);
1792 CONFLICT (DMULT, DMACC);
1793 CONFLICT (DMACC, DMULT);
1794 CONFLICT (DMACC, DMACC);
1796 /* Errata 24 - MT{LO,HI} after [D]MACC */
1797 CONFLICT (MACC, MTHILO);
1798 CONFLICT (DMACC, MTHILO);
1800 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1801 instruction is executed immediately after a MACC or DMACC
1802 instruction, the result of [either instruction] is incorrect." */
1803 CONFLICT (MACC, MULT);
1804 CONFLICT (MACC, DMULT);
1805 CONFLICT (DMACC, MULT);
1806 CONFLICT (DMACC, DMULT);
1808 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1809 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1810 DDIV or DDIVU instruction, the result of the MACC or
1811 DMACC instruction is incorrect.". */
1812 CONFLICT (DMULT, MACC);
1813 CONFLICT (DMULT, DMACC);
1814 CONFLICT (DIV, MACC);
1815 CONFLICT (DIV, DMACC);
1825 #define RTYPE_MASK 0x1ff00
1826 #define RTYPE_NUM 0x00100
1827 #define RTYPE_FPU 0x00200
1828 #define RTYPE_FCC 0x00400
1829 #define RTYPE_VEC 0x00800
1830 #define RTYPE_GP 0x01000
1831 #define RTYPE_CP0 0x02000
1832 #define RTYPE_PC 0x04000
1833 #define RTYPE_ACC 0x08000
1834 #define RTYPE_CCC 0x10000
1835 #define RNUM_MASK 0x000ff
1836 #define RWARN 0x80000
1838 #define GENERIC_REGISTER_NUMBERS \
1839 {"$0", RTYPE_NUM | 0}, \
1840 {"$1", RTYPE_NUM | 1}, \
1841 {"$2", RTYPE_NUM | 2}, \
1842 {"$3", RTYPE_NUM | 3}, \
1843 {"$4", RTYPE_NUM | 4}, \
1844 {"$5", RTYPE_NUM | 5}, \
1845 {"$6", RTYPE_NUM | 6}, \
1846 {"$7", RTYPE_NUM | 7}, \
1847 {"$8", RTYPE_NUM | 8}, \
1848 {"$9", RTYPE_NUM | 9}, \
1849 {"$10", RTYPE_NUM | 10}, \
1850 {"$11", RTYPE_NUM | 11}, \
1851 {"$12", RTYPE_NUM | 12}, \
1852 {"$13", RTYPE_NUM | 13}, \
1853 {"$14", RTYPE_NUM | 14}, \
1854 {"$15", RTYPE_NUM | 15}, \
1855 {"$16", RTYPE_NUM | 16}, \
1856 {"$17", RTYPE_NUM | 17}, \
1857 {"$18", RTYPE_NUM | 18}, \
1858 {"$19", RTYPE_NUM | 19}, \
1859 {"$20", RTYPE_NUM | 20}, \
1860 {"$21", RTYPE_NUM | 21}, \
1861 {"$22", RTYPE_NUM | 22}, \
1862 {"$23", RTYPE_NUM | 23}, \
1863 {"$24", RTYPE_NUM | 24}, \
1864 {"$25", RTYPE_NUM | 25}, \
1865 {"$26", RTYPE_NUM | 26}, \
1866 {"$27", RTYPE_NUM | 27}, \
1867 {"$28", RTYPE_NUM | 28}, \
1868 {"$29", RTYPE_NUM | 29}, \
1869 {"$30", RTYPE_NUM | 30}, \
1870 {"$31", RTYPE_NUM | 31}
1872 #define FPU_REGISTER_NAMES \
1873 {"$f0", RTYPE_FPU | 0}, \
1874 {"$f1", RTYPE_FPU | 1}, \
1875 {"$f2", RTYPE_FPU | 2}, \
1876 {"$f3", RTYPE_FPU | 3}, \
1877 {"$f4", RTYPE_FPU | 4}, \
1878 {"$f5", RTYPE_FPU | 5}, \
1879 {"$f6", RTYPE_FPU | 6}, \
1880 {"$f7", RTYPE_FPU | 7}, \
1881 {"$f8", RTYPE_FPU | 8}, \
1882 {"$f9", RTYPE_FPU | 9}, \
1883 {"$f10", RTYPE_FPU | 10}, \
1884 {"$f11", RTYPE_FPU | 11}, \
1885 {"$f12", RTYPE_FPU | 12}, \
1886 {"$f13", RTYPE_FPU | 13}, \
1887 {"$f14", RTYPE_FPU | 14}, \
1888 {"$f15", RTYPE_FPU | 15}, \
1889 {"$f16", RTYPE_FPU | 16}, \
1890 {"$f17", RTYPE_FPU | 17}, \
1891 {"$f18", RTYPE_FPU | 18}, \
1892 {"$f19", RTYPE_FPU | 19}, \
1893 {"$f20", RTYPE_FPU | 20}, \
1894 {"$f21", RTYPE_FPU | 21}, \
1895 {"$f22", RTYPE_FPU | 22}, \
1896 {"$f23", RTYPE_FPU | 23}, \
1897 {"$f24", RTYPE_FPU | 24}, \
1898 {"$f25", RTYPE_FPU | 25}, \
1899 {"$f26", RTYPE_FPU | 26}, \
1900 {"$f27", RTYPE_FPU | 27}, \
1901 {"$f28", RTYPE_FPU | 28}, \
1902 {"$f29", RTYPE_FPU | 29}, \
1903 {"$f30", RTYPE_FPU | 30}, \
1904 {"$f31", RTYPE_FPU | 31}
1906 #define FPU_CONDITION_CODE_NAMES \
1907 {"$fcc0", RTYPE_FCC | 0}, \
1908 {"$fcc1", RTYPE_FCC | 1}, \
1909 {"$fcc2", RTYPE_FCC | 2}, \
1910 {"$fcc3", RTYPE_FCC | 3}, \
1911 {"$fcc4", RTYPE_FCC | 4}, \
1912 {"$fcc5", RTYPE_FCC | 5}, \
1913 {"$fcc6", RTYPE_FCC | 6}, \
1914 {"$fcc7", RTYPE_FCC | 7}
1916 #define COPROC_CONDITION_CODE_NAMES \
1917 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1918 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1919 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1920 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1921 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1922 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1923 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1924 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1926 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1927 {"$a4", RTYPE_GP | 8}, \
1928 {"$a5", RTYPE_GP | 9}, \
1929 {"$a6", RTYPE_GP | 10}, \
1930 {"$a7", RTYPE_GP | 11}, \
1931 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1932 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1933 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1934 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1935 {"$t0", RTYPE_GP | 12}, \
1936 {"$t1", RTYPE_GP | 13}, \
1937 {"$t2", RTYPE_GP | 14}, \
1938 {"$t3", RTYPE_GP | 15}
1940 #define O32_SYMBOLIC_REGISTER_NAMES \
1941 {"$t0", RTYPE_GP | 8}, \
1942 {"$t1", RTYPE_GP | 9}, \
1943 {"$t2", RTYPE_GP | 10}, \
1944 {"$t3", RTYPE_GP | 11}, \
1945 {"$t4", RTYPE_GP | 12}, \
1946 {"$t5", RTYPE_GP | 13}, \
1947 {"$t6", RTYPE_GP | 14}, \
1948 {"$t7", RTYPE_GP | 15}, \
1949 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1950 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1951 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1952 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1954 /* Remaining symbolic register names */
1955 #define SYMBOLIC_REGISTER_NAMES \
1956 {"$zero", RTYPE_GP | 0}, \
1957 {"$at", RTYPE_GP | 1}, \
1958 {"$AT", RTYPE_GP | 1}, \
1959 {"$v0", RTYPE_GP | 2}, \
1960 {"$v1", RTYPE_GP | 3}, \
1961 {"$a0", RTYPE_GP | 4}, \
1962 {"$a1", RTYPE_GP | 5}, \
1963 {"$a2", RTYPE_GP | 6}, \
1964 {"$a3", RTYPE_GP | 7}, \
1965 {"$s0", RTYPE_GP | 16}, \
1966 {"$s1", RTYPE_GP | 17}, \
1967 {"$s2", RTYPE_GP | 18}, \
1968 {"$s3", RTYPE_GP | 19}, \
1969 {"$s4", RTYPE_GP | 20}, \
1970 {"$s5", RTYPE_GP | 21}, \
1971 {"$s6", RTYPE_GP | 22}, \
1972 {"$s7", RTYPE_GP | 23}, \
1973 {"$t8", RTYPE_GP | 24}, \
1974 {"$t9", RTYPE_GP | 25}, \
1975 {"$k0", RTYPE_GP | 26}, \
1976 {"$kt0", RTYPE_GP | 26}, \
1977 {"$k1", RTYPE_GP | 27}, \
1978 {"$kt1", RTYPE_GP | 27}, \
1979 {"$gp", RTYPE_GP | 28}, \
1980 {"$sp", RTYPE_GP | 29}, \
1981 {"$s8", RTYPE_GP | 30}, \
1982 {"$fp", RTYPE_GP | 30}, \
1983 {"$ra", RTYPE_GP | 31}
1985 #define MIPS16_SPECIAL_REGISTER_NAMES \
1986 {"$pc", RTYPE_PC | 0}
1988 #define MDMX_VECTOR_REGISTER_NAMES \
1989 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1990 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1991 {"$v2", RTYPE_VEC | 2}, \
1992 {"$v3", RTYPE_VEC | 3}, \
1993 {"$v4", RTYPE_VEC | 4}, \
1994 {"$v5", RTYPE_VEC | 5}, \
1995 {"$v6", RTYPE_VEC | 6}, \
1996 {"$v7", RTYPE_VEC | 7}, \
1997 {"$v8", RTYPE_VEC | 8}, \
1998 {"$v9", RTYPE_VEC | 9}, \
1999 {"$v10", RTYPE_VEC | 10}, \
2000 {"$v11", RTYPE_VEC | 11}, \
2001 {"$v12", RTYPE_VEC | 12}, \
2002 {"$v13", RTYPE_VEC | 13}, \
2003 {"$v14", RTYPE_VEC | 14}, \
2004 {"$v15", RTYPE_VEC | 15}, \
2005 {"$v16", RTYPE_VEC | 16}, \
2006 {"$v17", RTYPE_VEC | 17}, \
2007 {"$v18", RTYPE_VEC | 18}, \
2008 {"$v19", RTYPE_VEC | 19}, \
2009 {"$v20", RTYPE_VEC | 20}, \
2010 {"$v21", RTYPE_VEC | 21}, \
2011 {"$v22", RTYPE_VEC | 22}, \
2012 {"$v23", RTYPE_VEC | 23}, \
2013 {"$v24", RTYPE_VEC | 24}, \
2014 {"$v25", RTYPE_VEC | 25}, \
2015 {"$v26", RTYPE_VEC | 26}, \
2016 {"$v27", RTYPE_VEC | 27}, \
2017 {"$v28", RTYPE_VEC | 28}, \
2018 {"$v29", RTYPE_VEC | 29}, \
2019 {"$v30", RTYPE_VEC | 30}, \
2020 {"$v31", RTYPE_VEC | 31}
2022 #define MIPS_DSP_ACCUMULATOR_NAMES \
2023 {"$ac0", RTYPE_ACC | 0}, \
2024 {"$ac1", RTYPE_ACC | 1}, \
2025 {"$ac2", RTYPE_ACC | 2}, \
2026 {"$ac3", RTYPE_ACC | 3}
2028 static const struct regname reg_names[] = {
2029 GENERIC_REGISTER_NUMBERS,
2031 FPU_CONDITION_CODE_NAMES,
2032 COPROC_CONDITION_CODE_NAMES,
2034 /* The $txx registers depends on the abi,
2035 these will be added later into the symbol table from
2036 one of the tables below once mips_abi is set after
2037 parsing of arguments from the command line. */
2038 SYMBOLIC_REGISTER_NAMES,
2040 MIPS16_SPECIAL_REGISTER_NAMES,
2041 MDMX_VECTOR_REGISTER_NAMES,
2042 MIPS_DSP_ACCUMULATOR_NAMES,
2046 static const struct regname reg_names_o32[] = {
2047 O32_SYMBOLIC_REGISTER_NAMES,
2051 static const struct regname reg_names_n32n64[] = {
2052 N32N64_SYMBOLIC_REGISTER_NAMES,
2056 /* Check if S points at a valid register specifier according to TYPES.
2057 If so, then return 1, advance S to consume the specifier and store
2058 the register's number in REGNOP, otherwise return 0. */
2061 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2068 /* Find end of name. */
2070 if (is_name_beginner (*e))
2072 while (is_part_of_name (*e))
2075 /* Terminate name. */
2079 /* Look for a register symbol. */
2080 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2082 int r = S_GET_VALUE (symbolP);
2084 reg = r & RNUM_MASK;
2085 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2086 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2087 reg = (r & RNUM_MASK) - 2;
2089 /* Else see if this is a register defined in an itbl entry. */
2090 else if ((types & RTYPE_GP) && itbl_have_entries)
2097 if (itbl_get_reg_val (n, &r))
2098 reg = r & RNUM_MASK;
2101 /* Advance to next token if a register was recognised. */
2104 else if (types & RWARN)
2105 as_warn (_("Unrecognized register name `%s'"), *s);
2113 /* Check if S points at a valid register list according to TYPES.
2114 If so, then return 1, advance S to consume the list and store
2115 the registers present on the list as a bitmask of ones in REGLISTP,
2116 otherwise return 0. A valid list comprises a comma-separated
2117 enumeration of valid single registers and/or dash-separated
2118 contiguous register ranges as determined by their numbers.
2120 As a special exception if one of s0-s7 registers is specified as
2121 the range's lower delimiter and s8 (fp) is its upper one, then no
2122 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2123 are selected; they have to be listed separately if needed. */
2126 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2128 unsigned int reglist = 0;
2129 unsigned int lastregno;
2130 bfd_boolean ok = TRUE;
2131 unsigned int regmask;
2132 char *s_endlist = *s;
2136 while (reg_lookup (s, types, ®no))
2142 ok = reg_lookup (s, types, &lastregno);
2143 if (ok && lastregno < regno)
2149 if (lastregno == FP && regno >= S0 && regno <= S7)
2154 regmask = 1 << lastregno;
2155 regmask = (regmask << 1) - 1;
2156 regmask ^= (1 << regno) - 1;
2170 *reglistp = reglist;
2171 return ok && reglist != 0;
2174 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2175 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2178 is_opcode_valid (const struct mips_opcode *mo)
2180 int isa = mips_opts.isa;
2183 if (mips_opts.ase_mdmx)
2185 if (mips_opts.ase_dsp)
2187 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2189 if (mips_opts.ase_dspr2)
2191 if (mips_opts.ase_mt)
2193 if (mips_opts.ase_mips3d)
2195 if (mips_opts.ase_smartmips)
2196 isa |= INSN_SMARTMIPS;
2197 if (mips_opts.ase_mcu)
2200 if (!opcode_is_member (mo, isa, mips_opts.arch))
2203 /* Check whether the instruction or macro requires single-precision or
2204 double-precision floating-point support. Note that this information is
2205 stored differently in the opcode table for insns and macros. */
2206 if (mo->pinfo == INSN_MACRO)
2208 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2209 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2213 fp_s = mo->pinfo & FP_S;
2214 fp_d = mo->pinfo & FP_D;
2217 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2220 if (fp_s && mips_opts.soft_float)
2226 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2227 selected ISA and architecture. */
2230 is_opcode_valid_16 (const struct mips_opcode *mo)
2232 return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
2235 /* Return TRUE if the size of the microMIPS opcode MO matches one
2236 explicitly requested. Always TRUE in the standard MIPS mode. */
2239 is_size_valid (const struct mips_opcode *mo)
2241 if (!mips_opts.micromips)
2244 if (!forced_insn_length)
2246 if (mo->pinfo == INSN_MACRO)
2248 return forced_insn_length == micromips_insn_length (mo);
2251 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2252 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2255 is_delay_slot_valid (const struct mips_opcode *mo)
2257 if (!mips_opts.micromips)
2260 if (mo->pinfo == INSN_MACRO)
2262 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2263 && micromips_insn_length (mo) != 4)
2265 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2266 && micromips_insn_length (mo) != 2)
2272 /* This function is called once, at assembler startup time. It should set up
2273 all the tables, etc. that the MD part of the assembler will need. */
2278 const char *retval = NULL;
2282 if (mips_pic != NO_PIC)
2284 if (g_switch_seen && g_switch_value != 0)
2285 as_bad (_("-G may not be used in position-independent code"));
2289 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2290 as_warn (_("Could not set architecture and machine"));
2292 op_hash = hash_new ();
2294 for (i = 0; i < NUMOPCODES;)
2296 const char *name = mips_opcodes[i].name;
2298 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2301 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2302 mips_opcodes[i].name, retval);
2303 /* Probably a memory allocation problem? Give up now. */
2304 as_fatal (_("Broken assembler. No assembly attempted."));
2308 if (mips_opcodes[i].pinfo != INSN_MACRO)
2310 if (!validate_mips_insn (&mips_opcodes[i]))
2312 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2314 create_insn (&nop_insn, mips_opcodes + i);
2315 if (mips_fix_loongson2f_nop)
2316 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2317 nop_insn.fixed_p = 1;
2322 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2325 mips16_op_hash = hash_new ();
2328 while (i < bfd_mips16_num_opcodes)
2330 const char *name = mips16_opcodes[i].name;
2332 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2334 as_fatal (_("internal: can't hash `%s': %s"),
2335 mips16_opcodes[i].name, retval);
2338 if (mips16_opcodes[i].pinfo != INSN_MACRO
2339 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2340 != mips16_opcodes[i].match))
2342 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2343 mips16_opcodes[i].name, mips16_opcodes[i].args);
2346 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2348 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2349 mips16_nop_insn.fixed_p = 1;
2353 while (i < bfd_mips16_num_opcodes
2354 && strcmp (mips16_opcodes[i].name, name) == 0);
2357 micromips_op_hash = hash_new ();
2360 while (i < bfd_micromips_num_opcodes)
2362 const char *name = micromips_opcodes[i].name;
2364 retval = hash_insert (micromips_op_hash, name,
2365 (void *) µmips_opcodes[i]);
2367 as_fatal (_("internal: can't hash `%s': %s"),
2368 micromips_opcodes[i].name, retval);
2370 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2372 struct mips_cl_insn *micromips_nop_insn;
2374 if (!validate_micromips_insn (µmips_opcodes[i]))
2377 if (micromips_insn_length (micromips_opcodes + i) == 2)
2378 micromips_nop_insn = µmips_nop16_insn;
2379 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2380 micromips_nop_insn = µmips_nop32_insn;
2384 if (micromips_nop_insn->insn_mo == NULL
2385 && strcmp (name, "nop") == 0)
2387 create_insn (micromips_nop_insn, micromips_opcodes + i);
2388 micromips_nop_insn->fixed_p = 1;
2391 while (++i < bfd_micromips_num_opcodes
2392 && strcmp (micromips_opcodes[i].name, name) == 0);
2396 as_fatal (_("Broken assembler. No assembly attempted."));
2398 /* We add all the general register names to the symbol table. This
2399 helps us detect invalid uses of them. */
2400 for (i = 0; reg_names[i].name; i++)
2401 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2402 reg_names[i].num, /* & RNUM_MASK, */
2403 &zero_address_frag));
2405 for (i = 0; reg_names_n32n64[i].name; i++)
2406 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2407 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2408 &zero_address_frag));
2410 for (i = 0; reg_names_o32[i].name; i++)
2411 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2412 reg_names_o32[i].num, /* & RNUM_MASK, */
2413 &zero_address_frag));
2415 mips_no_prev_insn ();
2418 mips_cprmask[0] = 0;
2419 mips_cprmask[1] = 0;
2420 mips_cprmask[2] = 0;
2421 mips_cprmask[3] = 0;
2423 /* set the default alignment for the text section (2**2) */
2424 record_alignment (text_section, 2);
2426 bfd_set_gp_size (stdoutput, g_switch_value);
2431 /* On a native system other than VxWorks, sections must be aligned
2432 to 16 byte boundaries. When configured for an embedded ELF
2433 target, we don't bother. */
2434 if (strncmp (TARGET_OS, "elf", 3) != 0
2435 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2437 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2438 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2439 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2442 /* Create a .reginfo section for register masks and a .mdebug
2443 section for debugging information. */
2451 subseg = now_subseg;
2453 /* The ABI says this section should be loaded so that the
2454 running program can access it. However, we don't load it
2455 if we are configured for an embedded target */
2456 flags = SEC_READONLY | SEC_DATA;
2457 if (strncmp (TARGET_OS, "elf", 3) != 0)
2458 flags |= SEC_ALLOC | SEC_LOAD;
2460 if (mips_abi != N64_ABI)
2462 sec = subseg_new (".reginfo", (subsegT) 0);
2464 bfd_set_section_flags (stdoutput, sec, flags);
2465 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2467 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2471 /* The 64-bit ABI uses a .MIPS.options section rather than
2472 .reginfo section. */
2473 sec = subseg_new (".MIPS.options", (subsegT) 0);
2474 bfd_set_section_flags (stdoutput, sec, flags);
2475 bfd_set_section_alignment (stdoutput, sec, 3);
2477 /* Set up the option header. */
2479 Elf_Internal_Options opthdr;
2482 opthdr.kind = ODK_REGINFO;
2483 opthdr.size = (sizeof (Elf_External_Options)
2484 + sizeof (Elf64_External_RegInfo));
2487 f = frag_more (sizeof (Elf_External_Options));
2488 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2489 (Elf_External_Options *) f);
2491 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2495 if (ECOFF_DEBUGGING)
2497 sec = subseg_new (".mdebug", (subsegT) 0);
2498 (void) bfd_set_section_flags (stdoutput, sec,
2499 SEC_HAS_CONTENTS | SEC_READONLY);
2500 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2502 else if (mips_flag_pdr)
2504 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2505 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2506 SEC_READONLY | SEC_RELOC
2508 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2511 subseg_set (seg, subseg);
2514 #endif /* OBJ_ELF */
2516 if (! ECOFF_DEBUGGING)
2519 if (mips_fix_vr4120)
2520 init_vr4120_conflicts ();
2526 mips_emit_delays ();
2527 if (! ECOFF_DEBUGGING)
2532 md_assemble (char *str)
2534 struct mips_cl_insn insn;
2535 bfd_reloc_code_real_type unused_reloc[3]
2536 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2538 imm_expr.X_op = O_absent;
2539 imm2_expr.X_op = O_absent;
2540 offset_expr.X_op = O_absent;
2541 imm_reloc[0] = BFD_RELOC_UNUSED;
2542 imm_reloc[1] = BFD_RELOC_UNUSED;
2543 imm_reloc[2] = BFD_RELOC_UNUSED;
2544 offset_reloc[0] = BFD_RELOC_UNUSED;
2545 offset_reloc[1] = BFD_RELOC_UNUSED;
2546 offset_reloc[2] = BFD_RELOC_UNUSED;
2548 if (mips_opts.mips16)
2549 mips16_ip (str, &insn);
2552 mips_ip (str, &insn);
2553 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2554 str, insn.insn_opcode));
2559 as_bad ("%s `%s'", insn_error, str);
2563 if (insn.insn_mo->pinfo == INSN_MACRO)
2566 if (mips_opts.mips16)
2567 mips16_macro (&insn);
2574 if (imm_expr.X_op != O_absent)
2575 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2576 else if (offset_expr.X_op != O_absent)
2577 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2579 append_insn (&insn, NULL, unused_reloc, FALSE);
2583 /* Convenience functions for abstracting away the differences between
2584 MIPS16 and non-MIPS16 relocations. */
2586 static inline bfd_boolean
2587 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2591 case BFD_RELOC_MIPS16_JMP:
2592 case BFD_RELOC_MIPS16_GPREL:
2593 case BFD_RELOC_MIPS16_GOT16:
2594 case BFD_RELOC_MIPS16_CALL16:
2595 case BFD_RELOC_MIPS16_HI16_S:
2596 case BFD_RELOC_MIPS16_HI16:
2597 case BFD_RELOC_MIPS16_LO16:
2605 static inline bfd_boolean
2606 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2610 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2611 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2612 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2613 case BFD_RELOC_MICROMIPS_GPREL16:
2614 case BFD_RELOC_MICROMIPS_JMP:
2615 case BFD_RELOC_MICROMIPS_HI16:
2616 case BFD_RELOC_MICROMIPS_HI16_S:
2617 case BFD_RELOC_MICROMIPS_LO16:
2618 case BFD_RELOC_MICROMIPS_LITERAL:
2619 case BFD_RELOC_MICROMIPS_GOT16:
2620 case BFD_RELOC_MICROMIPS_CALL16:
2621 case BFD_RELOC_MICROMIPS_GOT_HI16:
2622 case BFD_RELOC_MICROMIPS_GOT_LO16:
2623 case BFD_RELOC_MICROMIPS_CALL_HI16:
2624 case BFD_RELOC_MICROMIPS_CALL_LO16:
2625 case BFD_RELOC_MICROMIPS_SUB:
2626 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2627 case BFD_RELOC_MICROMIPS_GOT_OFST:
2628 case BFD_RELOC_MICROMIPS_GOT_DISP:
2629 case BFD_RELOC_MICROMIPS_HIGHEST:
2630 case BFD_RELOC_MICROMIPS_HIGHER:
2631 case BFD_RELOC_MICROMIPS_SCN_DISP:
2632 case BFD_RELOC_MICROMIPS_JALR:
2640 static inline bfd_boolean
2641 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2643 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2646 static inline bfd_boolean
2647 got16_reloc_p (bfd_reloc_code_real_type reloc)
2649 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2650 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2653 static inline bfd_boolean
2654 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2656 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2657 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2660 static inline bfd_boolean
2661 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2663 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2664 || reloc == BFD_RELOC_MICROMIPS_LO16);
2667 static inline bfd_boolean
2668 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2670 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2673 /* Return true if the given relocation might need a matching %lo().
2674 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2675 need a matching %lo() when applied to local symbols. */
2677 static inline bfd_boolean
2678 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2680 return (HAVE_IN_PLACE_ADDENDS
2681 && (hi16_reloc_p (reloc)
2682 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2683 all GOT16 relocations evaluate to "G". */
2684 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2687 /* Return the type of %lo() reloc needed by RELOC, given that
2688 reloc_needs_lo_p. */
2690 static inline bfd_reloc_code_real_type
2691 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2693 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2694 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2698 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2701 static inline bfd_boolean
2702 fixup_has_matching_lo_p (fixS *fixp)
2704 return (fixp->fx_next != NULL
2705 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2706 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2707 && fixp->fx_offset == fixp->fx_next->fx_offset);
2710 /* This function returns true if modifying a register requires a
2714 reg_needs_delay (unsigned int reg)
2716 unsigned long prev_pinfo;
2718 prev_pinfo = history[0].insn_mo->pinfo;
2719 if (! mips_opts.noreorder
2720 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2721 && ! gpr_interlocks)
2722 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2723 && ! cop_interlocks)))
2725 /* A load from a coprocessor or from memory. All load delays
2726 delay the use of general register rt for one instruction. */
2727 /* Itbl support may require additional care here. */
2728 know (prev_pinfo & INSN_WRITE_GPR_T);
2729 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2736 /* Move all labels in LABELS to the current insertion point. TEXT_P
2737 says whether the labels refer to text or data. */
2740 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2742 struct insn_label_list *l;
2745 for (l = labels; l != NULL; l = l->next)
2747 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2748 symbol_set_frag (l->label, frag_now);
2749 val = (valueT) frag_now_fix ();
2750 /* MIPS16/microMIPS text labels are stored as odd. */
2751 if (text_p && HAVE_CODE_COMPRESSION)
2753 S_SET_VALUE (l->label, val);
2757 /* Move all labels in insn_labels to the current insertion point
2758 and treat them as text labels. */
2761 mips_move_text_labels (void)
2763 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2767 s_is_linkonce (symbolS *sym, segT from_seg)
2769 bfd_boolean linkonce = FALSE;
2770 segT symseg = S_GET_SEGMENT (sym);
2772 if (symseg != from_seg && !S_IS_LOCAL (sym))
2774 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2777 /* The GNU toolchain uses an extension for ELF: a section
2778 beginning with the magic string .gnu.linkonce is a
2779 linkonce section. */
2780 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2781 sizeof ".gnu.linkonce" - 1) == 0)
2788 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2789 linker to handle them specially, such as generating jalx instructions
2790 when needed. We also make them odd for the duration of the assembly,
2791 in order to generate the right sort of code. We will make them even
2792 in the adjust_symtab routine, while leaving them marked. This is
2793 convenient for the debugger and the disassembler. The linker knows
2794 to make them odd again. */
2797 mips_compressed_mark_labels (void)
2799 segment_info_type *si = seg_info (now_seg);
2800 struct insn_label_list *l;
2802 gas_assert (HAVE_CODE_COMPRESSION);
2804 for (l = si->label_list; l != NULL; l = l->next)
2806 symbolS *label = l->label;
2808 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2811 if (mips_opts.mips16)
2812 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2814 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2817 if ((S_GET_VALUE (label) & 1) == 0
2818 /* Don't adjust the address if the label is global or weak, or
2819 in a link-once section, since we'll be emitting symbol reloc
2820 references to it which will be patched up by the linker, and
2821 the final value of the symbol may or may not be MIPS16/microMIPS. */
2822 && ! S_IS_WEAK (label)
2823 && ! S_IS_EXTERNAL (label)
2824 && ! s_is_linkonce (label, now_seg))
2825 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2829 /* End the current frag. Make it a variant frag and record the
2833 relax_close_frag (void)
2835 mips_macro_warning.first_frag = frag_now;
2836 frag_var (rs_machine_dependent, 0, 0,
2837 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2838 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2840 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2841 mips_relax.first_fixup = 0;
2844 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2845 See the comment above RELAX_ENCODE for more details. */
2848 relax_start (symbolS *symbol)
2850 gas_assert (mips_relax.sequence == 0);
2851 mips_relax.sequence = 1;
2852 mips_relax.symbol = symbol;
2855 /* Start generating the second version of a relaxable sequence.
2856 See the comment above RELAX_ENCODE for more details. */
2861 gas_assert (mips_relax.sequence == 1);
2862 mips_relax.sequence = 2;
2865 /* End the current relaxable sequence. */
2870 gas_assert (mips_relax.sequence == 2);
2871 relax_close_frag ();
2872 mips_relax.sequence = 0;
2875 /* Return true if IP is a delayed branch or jump. */
2877 static inline bfd_boolean
2878 delayed_branch_p (const struct mips_cl_insn *ip)
2880 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2881 | INSN_COND_BRANCH_DELAY
2882 | INSN_COND_BRANCH_LIKELY)) != 0;
2885 /* Return true if IP is a compact branch or jump. */
2887 static inline bfd_boolean
2888 compact_branch_p (const struct mips_cl_insn *ip)
2890 if (mips_opts.mips16)
2891 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2892 | MIPS16_INSN_COND_BRANCH)) != 0;
2894 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2895 | INSN2_COND_BRANCH)) != 0;
2898 /* Return true if IP is an unconditional branch or jump. */
2900 static inline bfd_boolean
2901 uncond_branch_p (const struct mips_cl_insn *ip)
2903 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2904 || (mips_opts.mips16
2905 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2906 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2909 /* Return true if IP is a branch-likely instruction. */
2911 static inline bfd_boolean
2912 branch_likely_p (const struct mips_cl_insn *ip)
2914 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2917 /* Return the type of nop that should be used to fill the delay slot
2918 of delayed branch IP. */
2920 static struct mips_cl_insn *
2921 get_delay_slot_nop (const struct mips_cl_insn *ip)
2923 if (mips_opts.micromips
2924 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2925 return µmips_nop32_insn;
2929 /* Return the mask of core registers that IP reads or writes. */
2932 gpr_mod_mask (const struct mips_cl_insn *ip)
2934 unsigned long pinfo2;
2938 pinfo2 = ip->insn_mo->pinfo2;
2939 if (mips_opts.micromips)
2941 if (pinfo2 & INSN2_MOD_GPR_MD)
2942 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2943 if (pinfo2 & INSN2_MOD_GPR_MF)
2944 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2945 if (pinfo2 & INSN2_MOD_SP)
2951 /* Return the mask of core registers that IP reads. */
2954 gpr_read_mask (const struct mips_cl_insn *ip)
2956 unsigned long pinfo, pinfo2;
2959 mask = gpr_mod_mask (ip);
2960 pinfo = ip->insn_mo->pinfo;
2961 pinfo2 = ip->insn_mo->pinfo2;
2962 if (mips_opts.mips16)
2964 if (pinfo & MIPS16_INSN_READ_X)
2965 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2966 if (pinfo & MIPS16_INSN_READ_Y)
2967 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2968 if (pinfo & MIPS16_INSN_READ_T)
2970 if (pinfo & MIPS16_INSN_READ_SP)
2972 if (pinfo & MIPS16_INSN_READ_31)
2974 if (pinfo & MIPS16_INSN_READ_Z)
2975 mask |= 1 << (mips16_to_32_reg_map
2976 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2977 if (pinfo & MIPS16_INSN_READ_GPR_X)
2978 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2982 if (pinfo2 & INSN2_READ_GPR_D)
2983 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
2984 if (pinfo & INSN_READ_GPR_T)
2985 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
2986 if (pinfo & INSN_READ_GPR_S)
2987 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
2988 if (pinfo2 & INSN2_READ_GP)
2990 if (pinfo2 & INSN2_READ_GPR_31)
2992 if (pinfo2 & INSN2_READ_GPR_Z)
2993 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
2995 if (mips_opts.micromips)
2997 if (pinfo2 & INSN2_READ_GPR_MC)
2998 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
2999 if (pinfo2 & INSN2_READ_GPR_ME)
3000 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3001 if (pinfo2 & INSN2_READ_GPR_MG)
3002 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3003 if (pinfo2 & INSN2_READ_GPR_MJ)
3004 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3005 if (pinfo2 & INSN2_READ_GPR_MMN)
3007 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3008 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3010 if (pinfo2 & INSN2_READ_GPR_MP)
3011 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3012 if (pinfo2 & INSN2_READ_GPR_MQ)
3013 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3015 /* Don't include register 0. */
3019 /* Return the mask of core registers that IP writes. */
3022 gpr_write_mask (const struct mips_cl_insn *ip)
3024 unsigned long pinfo, pinfo2;
3027 mask = gpr_mod_mask (ip);
3028 pinfo = ip->insn_mo->pinfo;
3029 pinfo2 = ip->insn_mo->pinfo2;
3030 if (mips_opts.mips16)
3032 if (pinfo & MIPS16_INSN_WRITE_X)
3033 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3034 if (pinfo & MIPS16_INSN_WRITE_Y)
3035 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3036 if (pinfo & MIPS16_INSN_WRITE_Z)
3037 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3038 if (pinfo & MIPS16_INSN_WRITE_T)
3040 if (pinfo & MIPS16_INSN_WRITE_SP)
3042 if (pinfo & MIPS16_INSN_WRITE_31)
3044 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3045 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3049 if (pinfo & INSN_WRITE_GPR_D)
3050 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3051 if (pinfo & INSN_WRITE_GPR_T)
3052 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3053 if (pinfo & INSN_WRITE_GPR_S)
3054 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3055 if (pinfo & INSN_WRITE_GPR_31)
3057 if (pinfo2 & INSN2_WRITE_GPR_Z)
3058 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3060 if (mips_opts.micromips)
3062 if (pinfo2 & INSN2_WRITE_GPR_MB)
3063 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3064 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3066 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3067 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3069 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3070 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3071 if (pinfo2 & INSN2_WRITE_GPR_MP)
3072 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3074 /* Don't include register 0. */
3078 /* Return the mask of floating-point registers that IP reads. */
3081 fpr_read_mask (const struct mips_cl_insn *ip)
3083 unsigned long pinfo, pinfo2;
3087 pinfo = ip->insn_mo->pinfo;
3088 pinfo2 = ip->insn_mo->pinfo2;
3089 if (!mips_opts.mips16)
3091 if (pinfo2 & INSN2_READ_FPR_D)
3092 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3093 if (pinfo & INSN_READ_FPR_S)
3094 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3095 if (pinfo & INSN_READ_FPR_T)
3096 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3097 if (pinfo & INSN_READ_FPR_R)
3098 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3099 if (pinfo2 & INSN2_READ_FPR_Z)
3100 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3102 /* Conservatively treat all operands to an FP_D instruction are doubles.
3103 (This is overly pessimistic for things like cvt.d.s.) */
3104 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3109 /* Return the mask of floating-point registers that IP writes. */
3112 fpr_write_mask (const struct mips_cl_insn *ip)
3114 unsigned long pinfo, pinfo2;
3118 pinfo = ip->insn_mo->pinfo;
3119 pinfo2 = ip->insn_mo->pinfo2;
3120 if (!mips_opts.mips16)
3122 if (pinfo & INSN_WRITE_FPR_D)
3123 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3124 if (pinfo & INSN_WRITE_FPR_S)
3125 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3126 if (pinfo & INSN_WRITE_FPR_T)
3127 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3128 if (pinfo2 & INSN2_WRITE_FPR_Z)
3129 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3131 /* Conservatively treat all operands to an FP_D instruction are doubles.
3132 (This is overly pessimistic for things like cvt.s.d.) */
3133 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3138 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3139 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3140 by VR4120 errata. */
3143 classify_vr4120_insn (const char *name)
3145 if (strncmp (name, "macc", 4) == 0)
3146 return FIX_VR4120_MACC;
3147 if (strncmp (name, "dmacc", 5) == 0)
3148 return FIX_VR4120_DMACC;
3149 if (strncmp (name, "mult", 4) == 0)
3150 return FIX_VR4120_MULT;
3151 if (strncmp (name, "dmult", 5) == 0)
3152 return FIX_VR4120_DMULT;
3153 if (strstr (name, "div"))
3154 return FIX_VR4120_DIV;
3155 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3156 return FIX_VR4120_MTHILO;
3157 return NUM_FIX_VR4120_CLASSES;
3160 #define INSN_ERET 0x42000018
3161 #define INSN_DERET 0x4200001f
3163 /* Return the number of instructions that must separate INSN1 and INSN2,
3164 where INSN1 is the earlier instruction. Return the worst-case value
3165 for any INSN2 if INSN2 is null. */
3168 insns_between (const struct mips_cl_insn *insn1,
3169 const struct mips_cl_insn *insn2)
3171 unsigned long pinfo1, pinfo2;
3174 /* This function needs to know which pinfo flags are set for INSN2
3175 and which registers INSN2 uses. The former is stored in PINFO2 and
3176 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3177 will have every flag set and INSN2_USES_GPR will always return true. */
3178 pinfo1 = insn1->insn_mo->pinfo;
3179 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3181 #define INSN2_USES_GPR(REG) \
3182 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3184 /* For most targets, write-after-read dependencies on the HI and LO
3185 registers must be separated by at least two instructions. */
3186 if (!hilo_interlocks)
3188 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3190 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3194 /* If we're working around r7000 errata, there must be two instructions
3195 between an mfhi or mflo and any instruction that uses the result. */
3196 if (mips_7000_hilo_fix
3197 && !mips_opts.micromips
3198 && MF_HILO_INSN (pinfo1)
3199 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3202 /* If we're working around 24K errata, one instruction is required
3203 if an ERET or DERET is followed by a branch instruction. */
3204 if (mips_fix_24k && !mips_opts.micromips)
3206 if (insn1->insn_opcode == INSN_ERET
3207 || insn1->insn_opcode == INSN_DERET)
3210 || insn2->insn_opcode == INSN_ERET
3211 || insn2->insn_opcode == INSN_DERET
3212 || delayed_branch_p (insn2))
3217 /* If working around VR4120 errata, check for combinations that need
3218 a single intervening instruction. */
3219 if (mips_fix_vr4120 && !mips_opts.micromips)
3221 unsigned int class1, class2;
3223 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3224 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3228 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3229 if (vr4120_conflicts[class1] & (1 << class2))
3234 if (!HAVE_CODE_COMPRESSION)
3236 /* Check for GPR or coprocessor load delays. All such delays
3237 are on the RT register. */
3238 /* Itbl support may require additional care here. */
3239 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3240 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3242 know (pinfo1 & INSN_WRITE_GPR_T);
3243 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3247 /* Check for generic coprocessor hazards.
3249 This case is not handled very well. There is no special
3250 knowledge of CP0 handling, and the coprocessors other than
3251 the floating point unit are not distinguished at all. */
3252 /* Itbl support may require additional care here. FIXME!
3253 Need to modify this to include knowledge about
3254 user specified delays! */
3255 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3256 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3258 /* Handle cases where INSN1 writes to a known general coprocessor
3259 register. There must be a one instruction delay before INSN2
3260 if INSN2 reads that register, otherwise no delay is needed. */
3261 mask = fpr_write_mask (insn1);
3264 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3269 /* Read-after-write dependencies on the control registers
3270 require a two-instruction gap. */
3271 if ((pinfo1 & INSN_WRITE_COND_CODE)
3272 && (pinfo2 & INSN_READ_COND_CODE))
3275 /* We don't know exactly what INSN1 does. If INSN2 is
3276 also a coprocessor instruction, assume there must be
3277 a one instruction gap. */
3278 if (pinfo2 & INSN_COP)
3283 /* Check for read-after-write dependencies on the coprocessor
3284 control registers in cases where INSN1 does not need a general
3285 coprocessor delay. This means that INSN1 is a floating point
3286 comparison instruction. */
3287 /* Itbl support may require additional care here. */
3288 else if (!cop_interlocks
3289 && (pinfo1 & INSN_WRITE_COND_CODE)
3290 && (pinfo2 & INSN_READ_COND_CODE))
3294 #undef INSN2_USES_GPR
3299 /* Return the number of nops that would be needed to work around the
3300 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3301 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3302 that are contained within the first IGNORE instructions of HIST. */
3305 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3306 const struct mips_cl_insn *insn)
3311 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3312 are not affected by the errata. */
3314 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3315 || strcmp (insn->insn_mo->name, "mtlo") == 0
3316 || strcmp (insn->insn_mo->name, "mthi") == 0))
3319 /* Search for the first MFLO or MFHI. */
3320 for (i = 0; i < MAX_VR4130_NOPS; i++)
3321 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3323 /* Extract the destination register. */
3324 mask = gpr_write_mask (&hist[i]);
3326 /* No nops are needed if INSN reads that register. */
3327 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3330 /* ...or if any of the intervening instructions do. */
3331 for (j = 0; j < i; j++)
3332 if (gpr_read_mask (&hist[j]) & mask)
3336 return MAX_VR4130_NOPS - i;
3341 #define BASE_REG_EQ(INSN1, INSN2) \
3342 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3343 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3345 /* Return the minimum alignment for this store instruction. */
3348 fix_24k_align_to (const struct mips_opcode *mo)
3350 if (strcmp (mo->name, "sh") == 0)
3353 if (strcmp (mo->name, "swc1") == 0
3354 || strcmp (mo->name, "swc2") == 0
3355 || strcmp (mo->name, "sw") == 0
3356 || strcmp (mo->name, "sc") == 0
3357 || strcmp (mo->name, "s.s") == 0)
3360 if (strcmp (mo->name, "sdc1") == 0
3361 || strcmp (mo->name, "sdc2") == 0
3362 || strcmp (mo->name, "s.d") == 0)
3369 struct fix_24k_store_info
3371 /* Immediate offset, if any, for this store instruction. */
3373 /* Alignment required by this store instruction. */
3375 /* True for register offsets. */
3376 int register_offset;
3379 /* Comparison function used by qsort. */
3382 fix_24k_sort (const void *a, const void *b)
3384 const struct fix_24k_store_info *pos1 = a;
3385 const struct fix_24k_store_info *pos2 = b;
3387 return (pos1->off - pos2->off);
3390 /* INSN is a store instruction. Try to record the store information
3391 in STINFO. Return false if the information isn't known. */
3394 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3395 const struct mips_cl_insn *insn)
3397 /* The instruction must have a known offset. */
3398 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3401 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3402 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3406 /* Return the number of nops that would be needed to work around the 24k
3407 "lost data on stores during refill" errata if instruction INSN
3408 immediately followed the 2 instructions described by HIST.
3409 Ignore hazards that are contained within the first IGNORE
3410 instructions of HIST.
3412 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3413 for the data cache refills and store data. The following describes
3414 the scenario where the store data could be lost.
3416 * A data cache miss, due to either a load or a store, causing fill
3417 data to be supplied by the memory subsystem
3418 * The first three doublewords of fill data are returned and written
3420 * A sequence of four stores occurs in consecutive cycles around the
3421 final doubleword of the fill:
3425 * Zero, One or more instructions
3428 The four stores A-D must be to different doublewords of the line that
3429 is being filled. The fourth instruction in the sequence above permits
3430 the fill of the final doubleword to be transferred from the FSB into
3431 the cache. In the sequence above, the stores may be either integer
3432 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3433 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3434 different doublewords on the line. If the floating point unit is
3435 running in 1:2 mode, it is not possible to create the sequence above
3436 using only floating point store instructions.
3438 In this case, the cache line being filled is incorrectly marked
3439 invalid, thereby losing the data from any store to the line that
3440 occurs between the original miss and the completion of the five
3441 cycle sequence shown above.
3443 The workarounds are:
3445 * Run the data cache in write-through mode.
3446 * Insert a non-store instruction between
3447 Store A and Store B or Store B and Store C. */
3450 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3451 const struct mips_cl_insn *insn)
3453 struct fix_24k_store_info pos[3];
3454 int align, i, base_offset;
3459 /* If the previous instruction wasn't a store, there's nothing to
3461 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3464 /* If the instructions after the previous one are unknown, we have
3465 to assume the worst. */
3469 /* Check whether we are dealing with three consecutive stores. */
3470 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3471 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3474 /* If we don't know the relationship between the store addresses,
3475 assume the worst. */
3476 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3477 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3480 if (!fix_24k_record_store_info (&pos[0], insn)
3481 || !fix_24k_record_store_info (&pos[1], &hist[0])
3482 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3485 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3487 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3488 X bytes and such that the base register + X is known to be aligned
3491 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3495 align = pos[0].align_to;
3496 base_offset = pos[0].off;
3497 for (i = 1; i < 3; i++)
3498 if (align < pos[i].align_to)
3500 align = pos[i].align_to;
3501 base_offset = pos[i].off;
3503 for (i = 0; i < 3; i++)
3504 pos[i].off -= base_offset;
3507 pos[0].off &= ~align + 1;
3508 pos[1].off &= ~align + 1;
3509 pos[2].off &= ~align + 1;
3511 /* If any two stores write to the same chunk, they also write to the
3512 same doubleword. The offsets are still sorted at this point. */
3513 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3516 /* A range of at least 9 bytes is needed for the stores to be in
3517 non-overlapping doublewords. */
3518 if (pos[2].off - pos[0].off <= 8)
3521 if (pos[2].off - pos[1].off >= 24
3522 || pos[1].off - pos[0].off >= 24
3523 || pos[2].off - pos[0].off >= 32)
3529 /* Return the number of nops that would be needed if instruction INSN
3530 immediately followed the MAX_NOPS instructions given by HIST,
3531 where HIST[0] is the most recent instruction. Ignore hazards
3532 between INSN and the first IGNORE instructions in HIST.
3534 If INSN is null, return the worse-case number of nops for any
3538 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3539 const struct mips_cl_insn *insn)
3541 int i, nops, tmp_nops;
3544 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3546 tmp_nops = insns_between (hist + i, insn) - i;
3547 if (tmp_nops > nops)
3551 if (mips_fix_vr4130 && !mips_opts.micromips)
3553 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3554 if (tmp_nops > nops)
3558 if (mips_fix_24k && !mips_opts.micromips)
3560 tmp_nops = nops_for_24k (ignore, hist, insn);
3561 if (tmp_nops > nops)
3568 /* The variable arguments provide NUM_INSNS extra instructions that
3569 might be added to HIST. Return the largest number of nops that
3570 would be needed after the extended sequence, ignoring hazards
3571 in the first IGNORE instructions. */
3574 nops_for_sequence (int num_insns, int ignore,
3575 const struct mips_cl_insn *hist, ...)
3578 struct mips_cl_insn buffer[MAX_NOPS];
3579 struct mips_cl_insn *cursor;
3582 va_start (args, hist);
3583 cursor = buffer + num_insns;
3584 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3585 while (cursor > buffer)
3586 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3588 nops = nops_for_insn (ignore, buffer, NULL);
3593 /* Like nops_for_insn, but if INSN is a branch, take into account the
3594 worst-case delay for the branch target. */
3597 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3598 const struct mips_cl_insn *insn)
3602 nops = nops_for_insn (ignore, hist, insn);
3603 if (delayed_branch_p (insn))
3605 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3606 hist, insn, get_delay_slot_nop (insn));
3607 if (tmp_nops > nops)
3610 else if (compact_branch_p (insn))
3612 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3613 if (tmp_nops > nops)
3619 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3622 fix_loongson2f_nop (struct mips_cl_insn * ip)
3624 gas_assert (!HAVE_CODE_COMPRESSION);
3625 if (strcmp (ip->insn_mo->name, "nop") == 0)
3626 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3629 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3630 jr target pc &= 'hffff_ffff_cfff_ffff. */
3633 fix_loongson2f_jump (struct mips_cl_insn * ip)
3635 gas_assert (!HAVE_CODE_COMPRESSION);
3636 if (strcmp (ip->insn_mo->name, "j") == 0
3637 || strcmp (ip->insn_mo->name, "jr") == 0
3638 || strcmp (ip->insn_mo->name, "jalr") == 0)
3646 sreg = EXTRACT_OPERAND (0, RS, *ip);
3647 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3650 ep.X_op = O_constant;
3651 ep.X_add_number = 0xcfff0000;
3652 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3653 ep.X_add_number = 0xffff;
3654 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3655 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3660 fix_loongson2f (struct mips_cl_insn * ip)
3662 if (mips_fix_loongson2f_nop)
3663 fix_loongson2f_nop (ip);
3665 if (mips_fix_loongson2f_jump)
3666 fix_loongson2f_jump (ip);
3669 /* IP is a branch that has a delay slot, and we need to fill it
3670 automatically. Return true if we can do that by swapping IP
3671 with the previous instruction. */
3674 can_swap_branch_p (struct mips_cl_insn *ip)
3676 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3677 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3679 /* -O2 and above is required for this optimization. */
3680 if (mips_optimize < 2)
3683 /* If we have seen .set volatile or .set nomove, don't optimize. */
3684 if (mips_opts.nomove)
3687 /* We can't swap if the previous instruction's position is fixed. */
3688 if (history[0].fixed_p)
3691 /* If the previous previous insn was in a .set noreorder, we can't
3692 swap. Actually, the MIPS assembler will swap in this situation.
3693 However, gcc configured -with-gnu-as will generate code like
3701 in which we can not swap the bne and INSN. If gcc is not configured
3702 -with-gnu-as, it does not output the .set pseudo-ops. */
3703 if (history[1].noreorder_p)
3706 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3707 This means that the previous instruction was a 4-byte one anyhow. */
3708 if (mips_opts.mips16 && history[0].fixp[0])
3711 /* If the branch is itself the target of a branch, we can not swap.
3712 We cheat on this; all we check for is whether there is a label on
3713 this instruction. If there are any branches to anything other than
3714 a label, users must use .set noreorder. */
3715 if (seg_info (now_seg)->label_list)
3718 /* If the previous instruction is in a variant frag other than this
3719 branch's one, we cannot do the swap. This does not apply to
3720 MIPS16 code, which uses variant frags for different purposes. */
3721 if (!mips_opts.mips16
3723 && history[0].frag->fr_type == rs_machine_dependent)
3726 /* We do not swap with instructions that cannot architecturally
3727 be placed in a branch delay slot, such as SYNC or ERET. We
3728 also refrain from swapping with a trap instruction, since it
3729 complicates trap handlers to have the trap instruction be in
3731 prev_pinfo = history[0].insn_mo->pinfo;
3732 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3735 /* Check for conflicts between the branch and the instructions
3736 before the candidate delay slot. */
3737 if (nops_for_insn (0, history + 1, ip) > 0)
3740 /* Check for conflicts between the swapped sequence and the
3741 target of the branch. */
3742 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3745 /* If the branch reads a register that the previous
3746 instruction sets, we can not swap. */
3747 gpr_read = gpr_read_mask (ip);
3748 prev_gpr_write = gpr_write_mask (&history[0]);
3749 if (gpr_read & prev_gpr_write)
3752 /* If the branch writes a register that the previous
3753 instruction sets, we can not swap. */
3754 gpr_write = gpr_write_mask (ip);
3755 if (gpr_write & prev_gpr_write)
3758 /* If the branch writes a register that the previous
3759 instruction reads, we can not swap. */
3760 prev_gpr_read = gpr_read_mask (&history[0]);
3761 if (gpr_write & prev_gpr_read)
3764 /* If one instruction sets a condition code and the
3765 other one uses a condition code, we can not swap. */
3766 pinfo = ip->insn_mo->pinfo;
3767 if ((pinfo & INSN_READ_COND_CODE)
3768 && (prev_pinfo & INSN_WRITE_COND_CODE))
3770 if ((pinfo & INSN_WRITE_COND_CODE)
3771 && (prev_pinfo & INSN_READ_COND_CODE))
3774 /* If the previous instruction uses the PC, we can not swap. */
3775 prev_pinfo2 = history[0].insn_mo->pinfo2;
3776 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3778 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3781 /* If the previous instruction has an incorrect size for a fixed
3782 branch delay slot in microMIPS mode, we cannot swap. */
3783 pinfo2 = ip->insn_mo->pinfo2;
3784 if (mips_opts.micromips
3785 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3786 && insn_length (history) != 2)
3788 if (mips_opts.micromips
3789 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3790 && insn_length (history) != 4)
3796 /* Decide how we should add IP to the instruction stream. */
3798 static enum append_method
3799 get_append_method (struct mips_cl_insn *ip)
3801 unsigned long pinfo;
3803 /* The relaxed version of a macro sequence must be inherently
3805 if (mips_relax.sequence == 2)
3808 /* We must not dabble with instructions in a ".set norerorder" block. */
3809 if (mips_opts.noreorder)
3812 /* Otherwise, it's our responsibility to fill branch delay slots. */
3813 if (delayed_branch_p (ip))
3815 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3818 pinfo = ip->insn_mo->pinfo;
3819 if (mips_opts.mips16
3820 && ISA_SUPPORTS_MIPS16E
3821 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3822 return APPEND_ADD_COMPACT;
3824 return APPEND_ADD_WITH_NOP;
3830 /* IP is a MIPS16 instruction whose opcode we have just changed.
3831 Point IP->insn_mo to the new opcode's definition. */
3834 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3836 const struct mips_opcode *mo, *end;
3838 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3839 for (mo = ip->insn_mo; mo < end; mo++)
3840 if ((ip->insn_opcode & mo->mask) == mo->match)
3848 /* For microMIPS macros, we need to generate a local number label
3849 as the target of branches. */
3850 #define MICROMIPS_LABEL_CHAR '\037'
3851 static unsigned long micromips_target_label;
3852 static char micromips_target_name[32];
3855 micromips_label_name (void)
3857 char *p = micromips_target_name;
3858 char symbol_name_temporary[24];
3866 l = micromips_target_label;
3867 #ifdef LOCAL_LABEL_PREFIX
3868 *p++ = LOCAL_LABEL_PREFIX;
3871 *p++ = MICROMIPS_LABEL_CHAR;
3874 symbol_name_temporary[i++] = l % 10 + '0';
3879 *p++ = symbol_name_temporary[--i];
3882 return micromips_target_name;
3886 micromips_label_expr (expressionS *label_expr)
3888 label_expr->X_op = O_symbol;
3889 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3890 label_expr->X_add_number = 0;
3894 micromips_label_inc (void)
3896 micromips_target_label++;
3897 *micromips_target_name = '\0';
3901 micromips_add_label (void)
3905 s = colon (micromips_label_name ());
3906 micromips_label_inc ();
3907 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3909 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3915 /* If assembling microMIPS code, then return the microMIPS reloc
3916 corresponding to the requested one if any. Otherwise return
3917 the reloc unchanged. */
3919 static bfd_reloc_code_real_type
3920 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3922 static const bfd_reloc_code_real_type relocs[][2] =
3924 /* Keep sorted incrementally by the left-hand key. */
3925 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3926 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3927 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3928 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3929 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3930 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3931 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3932 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3933 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3934 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3935 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3936 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3937 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3938 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3939 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3940 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3941 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3942 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3943 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3944 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3945 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3946 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3947 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3948 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3949 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3950 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3951 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
3953 bfd_reloc_code_real_type r;
3956 if (!mips_opts.micromips)
3958 for (i = 0; i < ARRAY_SIZE (relocs); i++)
3964 return relocs[i][1];
3969 /* Output an instruction. IP is the instruction information.
3970 ADDRESS_EXPR is an operand of the instruction to be used with
3971 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3972 a macro expansion. */
3975 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3976 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
3978 unsigned long prev_pinfo2, pinfo;
3979 bfd_boolean relaxed_branch = FALSE;
3980 enum append_method method;
3981 bfd_boolean relax32;
3984 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
3985 fix_loongson2f (ip);
3987 mips_mark_labels ();
3989 file_ase_mips16 |= mips_opts.mips16;
3990 file_ase_micromips |= mips_opts.micromips;
3992 prev_pinfo2 = history[0].insn_mo->pinfo2;
3993 pinfo = ip->insn_mo->pinfo;
3995 if (mips_opts.micromips
3997 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3998 && micromips_insn_length (ip->insn_mo) != 2)
3999 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4000 && micromips_insn_length (ip->insn_mo) != 4)))
4001 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4002 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4004 if (address_expr == NULL)
4006 else if (*reloc_type <= BFD_RELOC_UNUSED
4007 && address_expr->X_op == O_constant)
4012 switch (*reloc_type)
4015 ip->insn_opcode |= address_expr->X_add_number;
4018 case BFD_RELOC_MIPS_HIGHEST:
4019 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
4020 ip->insn_opcode |= tmp & 0xffff;
4023 case BFD_RELOC_MIPS_HIGHER:
4024 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
4025 ip->insn_opcode |= tmp & 0xffff;
4028 case BFD_RELOC_HI16_S:
4029 tmp = (address_expr->X_add_number + 0x8000) >> 16;
4030 ip->insn_opcode |= tmp & 0xffff;
4033 case BFD_RELOC_HI16:
4034 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4037 case BFD_RELOC_UNUSED:
4038 case BFD_RELOC_LO16:
4039 case BFD_RELOC_MIPS_GOT_DISP:
4040 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4043 case BFD_RELOC_MIPS_JMP:
4047 shift = mips_opts.micromips ? 1 : 2;
4048 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4049 as_bad (_("jump to misaligned address (0x%lx)"),
4050 (unsigned long) address_expr->X_add_number);
4051 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4057 case BFD_RELOC_MIPS16_JMP:
4058 if ((address_expr->X_add_number & 3) != 0)
4059 as_bad (_("jump to misaligned address (0x%lx)"),
4060 (unsigned long) address_expr->X_add_number);
4062 (((address_expr->X_add_number & 0x7c0000) << 3)
4063 | ((address_expr->X_add_number & 0xf800000) >> 7)
4064 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4068 case BFD_RELOC_16_PCREL_S2:
4072 shift = mips_opts.micromips ? 1 : 2;
4073 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4074 as_bad (_("branch to misaligned address (0x%lx)"),
4075 (unsigned long) address_expr->X_add_number);
4076 if (!mips_relax_branch)
4078 if ((address_expr->X_add_number + (1 << (shift + 15)))
4079 & ~((1 << (shift + 16)) - 1))
4080 as_bad (_("branch address range overflow (0x%lx)"),
4081 (unsigned long) address_expr->X_add_number);
4082 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4094 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4096 /* There are a lot of optimizations we could do that we don't.
4097 In particular, we do not, in general, reorder instructions.
4098 If you use gcc with optimization, it will reorder
4099 instructions and generally do much more optimization then we
4100 do here; repeating all that work in the assembler would only
4101 benefit hand written assembly code, and does not seem worth
4103 int nops = (mips_optimize == 0
4104 ? nops_for_insn (0, history, NULL)
4105 : nops_for_insn_or_target (0, history, ip));
4109 unsigned long old_frag_offset;
4112 old_frag = frag_now;
4113 old_frag_offset = frag_now_fix ();
4115 for (i = 0; i < nops; i++)
4116 add_fixed_insn (NOP_INSN);
4117 insert_into_history (0, nops, NOP_INSN);
4121 listing_prev_line ();
4122 /* We may be at the start of a variant frag. In case we
4123 are, make sure there is enough space for the frag
4124 after the frags created by listing_prev_line. The
4125 argument to frag_grow here must be at least as large
4126 as the argument to all other calls to frag_grow in
4127 this file. We don't have to worry about being in the
4128 middle of a variant frag, because the variants insert
4129 all needed nop instructions themselves. */
4133 mips_move_text_labels ();
4135 #ifndef NO_ECOFF_DEBUGGING
4136 if (ECOFF_DEBUGGING)
4137 ecoff_fix_loc (old_frag, old_frag_offset);
4141 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4145 /* Work out how many nops in prev_nop_frag are needed by IP,
4146 ignoring hazards generated by the first prev_nop_frag_since
4148 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4149 gas_assert (nops <= prev_nop_frag_holds);
4151 /* Enforce NOPS as a minimum. */
4152 if (nops > prev_nop_frag_required)
4153 prev_nop_frag_required = nops;
4155 if (prev_nop_frag_holds == prev_nop_frag_required)
4157 /* Settle for the current number of nops. Update the history
4158 accordingly (for the benefit of any future .set reorder code). */
4159 prev_nop_frag = NULL;
4160 insert_into_history (prev_nop_frag_since,
4161 prev_nop_frag_holds, NOP_INSN);
4165 /* Allow this instruction to replace one of the nops that was
4166 tentatively added to prev_nop_frag. */
4167 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4168 prev_nop_frag_holds--;
4169 prev_nop_frag_since++;
4173 method = get_append_method (ip);
4174 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4177 /* The value passed to dwarf2_emit_insn is the distance between
4178 the beginning of the current instruction and the address that
4179 should be recorded in the debug tables. This is normally the
4182 For MIPS16/microMIPS debug info we want to use ISA-encoded
4183 addresses, so we use -1 for an address higher by one than the
4186 If the instruction produced is a branch that we will swap with
4187 the preceding instruction, then we add the displacement by which
4188 the branch will be moved backwards. This is more appropriate
4189 and for MIPS16/microMIPS code also prevents a debugger from
4190 placing a breakpoint in the middle of the branch (and corrupting
4191 code if software breakpoints are used). */
4192 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4195 relax32 = (mips_relax_branch
4196 /* Don't try branch relaxation within .set nomacro, or within
4197 .set noat if we use $at for PIC computations. If it turns
4198 out that the branch was out-of-range, we'll get an error. */
4199 && !mips_opts.warn_about_macros
4200 && (mips_opts.at || mips_pic == NO_PIC)
4201 /* Don't relax BPOSGE32/64 as they have no complementing
4203 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4205 if (!HAVE_CODE_COMPRESSION
4208 && *reloc_type == BFD_RELOC_16_PCREL_S2
4209 && delayed_branch_p (ip))
4211 relaxed_branch = TRUE;
4212 add_relaxed_insn (ip, (relaxed_branch_length
4214 uncond_branch_p (ip) ? -1
4215 : branch_likely_p (ip) ? 1
4219 uncond_branch_p (ip),
4220 branch_likely_p (ip),
4221 pinfo & INSN_WRITE_GPR_31,
4223 address_expr->X_add_symbol,
4224 address_expr->X_add_number);
4225 *reloc_type = BFD_RELOC_UNUSED;
4227 else if (mips_opts.micromips
4229 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4230 || *reloc_type > BFD_RELOC_UNUSED)
4231 && (delayed_branch_p (ip) || compact_branch_p (ip))
4232 /* Don't try branch relaxation when users specify
4233 16-bit/32-bit instructions. */
4234 && !forced_insn_length)
4236 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4237 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4238 int uncond = uncond_branch_p (ip) ? -1 : 0;
4239 int compact = compact_branch_p (ip);
4240 int al = pinfo & INSN_WRITE_GPR_31;
4243 gas_assert (address_expr != NULL);
4244 gas_assert (!mips_relax.sequence);
4246 relaxed_branch = TRUE;
4247 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4248 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4249 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4251 address_expr->X_add_symbol,
4252 address_expr->X_add_number);
4253 *reloc_type = BFD_RELOC_UNUSED;
4255 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4257 /* We need to set up a variant frag. */
4258 gas_assert (address_expr != NULL);
4259 add_relaxed_insn (ip, 4, 0,
4261 (*reloc_type - BFD_RELOC_UNUSED,
4262 forced_insn_length == 2, forced_insn_length == 4,
4263 delayed_branch_p (&history[0]),
4264 history[0].mips16_absolute_jump_p),
4265 make_expr_symbol (address_expr), 0);
4267 else if (mips_opts.mips16 && insn_length (ip) == 2)
4269 if (!delayed_branch_p (ip))
4270 /* Make sure there is enough room to swap this instruction with
4271 a following jump instruction. */
4273 add_fixed_insn (ip);
4277 if (mips_opts.mips16
4278 && mips_opts.noreorder
4279 && delayed_branch_p (&history[0]))
4280 as_warn (_("extended instruction in delay slot"));
4282 if (mips_relax.sequence)
4284 /* If we've reached the end of this frag, turn it into a variant
4285 frag and record the information for the instructions we've
4287 if (frag_room () < 4)
4288 relax_close_frag ();
4289 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4292 if (mips_relax.sequence != 2)
4294 if (mips_macro_warning.first_insn_sizes[0] == 0)
4295 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4296 mips_macro_warning.sizes[0] += insn_length (ip);
4297 mips_macro_warning.insns[0]++;
4299 if (mips_relax.sequence != 1)
4301 if (mips_macro_warning.first_insn_sizes[1] == 0)
4302 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4303 mips_macro_warning.sizes[1] += insn_length (ip);
4304 mips_macro_warning.insns[1]++;
4307 if (mips_opts.mips16)
4310 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4312 add_fixed_insn (ip);
4315 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4317 bfd_reloc_code_real_type final_type[3];
4318 reloc_howto_type *howto0;
4319 reloc_howto_type *howto;
4322 /* Perform any necessary conversion to microMIPS relocations
4323 and find out how many relocations there actually are. */
4324 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4325 final_type[i] = micromips_map_reloc (reloc_type[i]);
4327 /* In a compound relocation, it is the final (outermost)
4328 operator that determines the relocated field. */
4329 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4333 /* To reproduce this failure try assembling gas/testsuites/
4334 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4336 as_bad (_("Unsupported MIPS relocation number %d"),
4338 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4342 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4343 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4344 bfd_get_reloc_size (howto),
4346 howto0 && howto0->pc_relative,
4349 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4350 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4351 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4353 /* These relocations can have an addend that won't fit in
4354 4 octets for 64bit assembly. */
4356 && ! howto->partial_inplace
4357 && (reloc_type[0] == BFD_RELOC_16
4358 || reloc_type[0] == BFD_RELOC_32
4359 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4360 || reloc_type[0] == BFD_RELOC_GPREL16
4361 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4362 || reloc_type[0] == BFD_RELOC_GPREL32
4363 || reloc_type[0] == BFD_RELOC_64
4364 || reloc_type[0] == BFD_RELOC_CTOR
4365 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4366 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4367 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4368 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4369 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4370 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4371 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4372 || hi16_reloc_p (reloc_type[0])
4373 || lo16_reloc_p (reloc_type[0])))
4374 ip->fixp[0]->fx_no_overflow = 1;
4376 if (mips_relax.sequence)
4378 if (mips_relax.first_fixup == 0)
4379 mips_relax.first_fixup = ip->fixp[0];
4381 else if (reloc_needs_lo_p (*reloc_type))
4383 struct mips_hi_fixup *hi_fixup;
4385 /* Reuse the last entry if it already has a matching %lo. */
4386 hi_fixup = mips_hi_fixup_list;
4388 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4390 hi_fixup = ((struct mips_hi_fixup *)
4391 xmalloc (sizeof (struct mips_hi_fixup)));
4392 hi_fixup->next = mips_hi_fixup_list;
4393 mips_hi_fixup_list = hi_fixup;
4395 hi_fixup->fixp = ip->fixp[0];
4396 hi_fixup->seg = now_seg;
4399 /* Add fixups for the second and third relocations, if given.
4400 Note that the ABI allows the second relocation to be
4401 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4402 moment we only use RSS_UNDEF, but we could add support
4403 for the others if it ever becomes necessary. */
4404 for (i = 1; i < 3; i++)
4405 if (reloc_type[i] != BFD_RELOC_UNUSED)
4407 ip->fixp[i] = fix_new (ip->frag, ip->where,
4408 ip->fixp[0]->fx_size, NULL, 0,
4409 FALSE, final_type[i]);
4411 /* Use fx_tcbit to mark compound relocs. */
4412 ip->fixp[0]->fx_tcbit = 1;
4413 ip->fixp[i]->fx_tcbit = 1;
4418 /* Update the register mask information. */
4419 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4420 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4425 insert_into_history (0, 1, ip);
4428 case APPEND_ADD_WITH_NOP:
4430 struct mips_cl_insn *nop;
4432 insert_into_history (0, 1, ip);
4433 nop = get_delay_slot_nop (ip);
4434 add_fixed_insn (nop);
4435 insert_into_history (0, 1, nop);
4436 if (mips_relax.sequence)
4437 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4441 case APPEND_ADD_COMPACT:
4442 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4443 gas_assert (mips_opts.mips16);
4444 ip->insn_opcode |= 0x0080;
4445 find_altered_mips16_opcode (ip);
4447 insert_into_history (0, 1, ip);
4452 struct mips_cl_insn delay = history[0];
4453 if (mips_opts.mips16)
4455 know (delay.frag == ip->frag);
4456 move_insn (ip, delay.frag, delay.where);
4457 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4459 else if (relaxed_branch || delay.frag != ip->frag)
4461 /* Add the delay slot instruction to the end of the
4462 current frag and shrink the fixed part of the
4463 original frag. If the branch occupies the tail of
4464 the latter, move it backwards to cover the gap. */
4465 delay.frag->fr_fix -= branch_disp;
4466 if (delay.frag == ip->frag)
4467 move_insn (ip, ip->frag, ip->where - branch_disp);
4468 add_fixed_insn (&delay);
4472 move_insn (&delay, ip->frag,
4473 ip->where - branch_disp + insn_length (ip));
4474 move_insn (ip, history[0].frag, history[0].where);
4478 insert_into_history (0, 1, &delay);
4483 /* If we have just completed an unconditional branch, clear the history. */
4484 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4485 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4486 mips_no_prev_insn ();
4488 /* We need to emit a label at the end of branch-likely macros. */
4489 if (emit_branch_likely_macro)
4491 emit_branch_likely_macro = FALSE;
4492 micromips_add_label ();
4495 /* We just output an insn, so the next one doesn't have a label. */
4496 mips_clear_insn_labels ();
4499 /* Forget that there was any previous instruction or label. */
4502 mips_no_prev_insn (void)
4504 prev_nop_frag = NULL;
4505 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4506 mips_clear_insn_labels ();
4509 /* This function must be called before we emit something other than
4510 instructions. It is like mips_no_prev_insn except that it inserts
4511 any NOPS that might be needed by previous instructions. */
4514 mips_emit_delays (void)
4516 if (! mips_opts.noreorder)
4518 int nops = nops_for_insn (0, history, NULL);
4522 add_fixed_insn (NOP_INSN);
4523 mips_move_text_labels ();
4526 mips_no_prev_insn ();
4529 /* Start a (possibly nested) noreorder block. */
4532 start_noreorder (void)
4534 if (mips_opts.noreorder == 0)
4539 /* None of the instructions before the .set noreorder can be moved. */
4540 for (i = 0; i < ARRAY_SIZE (history); i++)
4541 history[i].fixed_p = 1;
4543 /* Insert any nops that might be needed between the .set noreorder
4544 block and the previous instructions. We will later remove any
4545 nops that turn out not to be needed. */
4546 nops = nops_for_insn (0, history, NULL);
4549 if (mips_optimize != 0)
4551 /* Record the frag which holds the nop instructions, so
4552 that we can remove them if we don't need them. */
4553 frag_grow (nops * NOP_INSN_SIZE);
4554 prev_nop_frag = frag_now;
4555 prev_nop_frag_holds = nops;
4556 prev_nop_frag_required = 0;
4557 prev_nop_frag_since = 0;
4560 for (; nops > 0; --nops)
4561 add_fixed_insn (NOP_INSN);
4563 /* Move on to a new frag, so that it is safe to simply
4564 decrease the size of prev_nop_frag. */
4565 frag_wane (frag_now);
4567 mips_move_text_labels ();
4569 mips_mark_labels ();
4570 mips_clear_insn_labels ();
4572 mips_opts.noreorder++;
4573 mips_any_noreorder = 1;
4576 /* End a nested noreorder block. */
4579 end_noreorder (void)
4581 mips_opts.noreorder--;
4582 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4584 /* Commit to inserting prev_nop_frag_required nops and go back to
4585 handling nop insertion the .set reorder way. */
4586 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4588 insert_into_history (prev_nop_frag_since,
4589 prev_nop_frag_required, NOP_INSN);
4590 prev_nop_frag = NULL;
4594 /* Set up global variables for the start of a new macro. */
4599 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4600 memset (&mips_macro_warning.first_insn_sizes, 0,
4601 sizeof (mips_macro_warning.first_insn_sizes));
4602 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4603 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4604 && delayed_branch_p (&history[0]));
4605 switch (history[0].insn_mo->pinfo2
4606 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4608 case INSN2_BRANCH_DELAY_32BIT:
4609 mips_macro_warning.delay_slot_length = 4;
4611 case INSN2_BRANCH_DELAY_16BIT:
4612 mips_macro_warning.delay_slot_length = 2;
4615 mips_macro_warning.delay_slot_length = 0;
4618 mips_macro_warning.first_frag = NULL;
4621 /* Given that a macro is longer than one instruction or of the wrong size,
4622 return the appropriate warning for it. Return null if no warning is
4623 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4624 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4625 and RELAX_NOMACRO. */
4628 macro_warning (relax_substateT subtype)
4630 if (subtype & RELAX_DELAY_SLOT)
4631 return _("Macro instruction expanded into multiple instructions"
4632 " in a branch delay slot");
4633 else if (subtype & RELAX_NOMACRO)
4634 return _("Macro instruction expanded into multiple instructions");
4635 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4636 | RELAX_DELAY_SLOT_SIZE_SECOND))
4637 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4638 ? _("Macro instruction expanded into a wrong size instruction"
4639 " in a 16-bit branch delay slot")
4640 : _("Macro instruction expanded into a wrong size instruction"
4641 " in a 32-bit branch delay slot"));
4646 /* Finish up a macro. Emit warnings as appropriate. */
4651 /* Relaxation warning flags. */
4652 relax_substateT subtype = 0;
4654 /* Check delay slot size requirements. */
4655 if (mips_macro_warning.delay_slot_length == 2)
4656 subtype |= RELAX_DELAY_SLOT_16BIT;
4657 if (mips_macro_warning.delay_slot_length != 0)
4659 if (mips_macro_warning.delay_slot_length
4660 != mips_macro_warning.first_insn_sizes[0])
4661 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4662 if (mips_macro_warning.delay_slot_length
4663 != mips_macro_warning.first_insn_sizes[1])
4664 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4667 /* Check instruction count requirements. */
4668 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4670 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4671 subtype |= RELAX_SECOND_LONGER;
4672 if (mips_opts.warn_about_macros)
4673 subtype |= RELAX_NOMACRO;
4674 if (mips_macro_warning.delay_slot_p)
4675 subtype |= RELAX_DELAY_SLOT;
4678 /* If both alternatives fail to fill a delay slot correctly,
4679 emit the warning now. */
4680 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4681 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4686 s = subtype & (RELAX_DELAY_SLOT_16BIT
4687 | RELAX_DELAY_SLOT_SIZE_FIRST
4688 | RELAX_DELAY_SLOT_SIZE_SECOND);
4689 msg = macro_warning (s);
4691 as_warn ("%s", msg);
4695 /* If both implementations are longer than 1 instruction, then emit the
4697 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4702 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4703 msg = macro_warning (s);
4705 as_warn ("%s", msg);
4709 /* If any flags still set, then one implementation might need a warning
4710 and the other either will need one of a different kind or none at all.
4711 Pass any remaining flags over to relaxation. */
4712 if (mips_macro_warning.first_frag != NULL)
4713 mips_macro_warning.first_frag->fr_subtype |= subtype;
4716 /* Instruction operand formats used in macros that vary between
4717 standard MIPS and microMIPS code. */
4719 static const char * const brk_fmt[2] = { "c", "mF" };
4720 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4721 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4722 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4723 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4724 static const char * const mfhl_fmt[2] = { "d", "mj" };
4725 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4726 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4728 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4729 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4730 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4731 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4732 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4733 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4734 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4735 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4737 /* Read a macro's relocation codes from *ARGS and store them in *R.
4738 The first argument in *ARGS will be either the code for a single
4739 relocation or -1 followed by the three codes that make up a
4740 composite relocation. */
4743 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4747 next = va_arg (*args, int);
4749 r[0] = (bfd_reloc_code_real_type) next;
4751 for (i = 0; i < 3; i++)
4752 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4755 /* Build an instruction created by a macro expansion. This is passed
4756 a pointer to the count of instructions created so far, an
4757 expression, the name of the instruction to build, an operand format
4758 string, and corresponding arguments. */
4761 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4763 const struct mips_opcode *mo = NULL;
4764 bfd_reloc_code_real_type r[3];
4765 const struct mips_opcode *amo;
4766 struct hash_control *hash;
4767 struct mips_cl_insn insn;
4770 va_start (args, fmt);
4772 if (mips_opts.mips16)
4774 mips16_macro_build (ep, name, fmt, &args);
4779 r[0] = BFD_RELOC_UNUSED;
4780 r[1] = BFD_RELOC_UNUSED;
4781 r[2] = BFD_RELOC_UNUSED;
4782 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4783 amo = (struct mips_opcode *) hash_find (hash, name);
4785 gas_assert (strcmp (name, amo->name) == 0);
4789 /* Search until we get a match for NAME. It is assumed here that
4790 macros will never generate MDMX, MIPS-3D, or MT instructions.
4791 We try to match an instruction that fulfils the branch delay
4792 slot instruction length requirement (if any) of the previous
4793 instruction. While doing this we record the first instruction
4794 seen that matches all the other conditions and use it anyway
4795 if the requirement cannot be met; we will issue an appropriate
4796 warning later on. */
4797 if (strcmp (fmt, amo->args) == 0
4798 && amo->pinfo != INSN_MACRO
4799 && is_opcode_valid (amo)
4800 && is_size_valid (amo))
4802 if (is_delay_slot_valid (amo))
4812 gas_assert (amo->name);
4814 while (strcmp (name, amo->name) == 0);
4817 create_insn (&insn, mo);
4835 INSERT_OPERAND (mips_opts.micromips,
4836 EXTLSB, insn, va_arg (args, int));
4841 /* Note that in the macro case, these arguments are already
4842 in MSB form. (When handling the instruction in the
4843 non-macro case, these arguments are sizes from which
4844 MSB values must be calculated.) */
4845 INSERT_OPERAND (mips_opts.micromips,
4846 INSMSB, insn, va_arg (args, int));
4852 /* Note that in the macro case, these arguments are already
4853 in MSBD form. (When handling the instruction in the
4854 non-macro case, these arguments are sizes from which
4855 MSBD values must be calculated.) */
4856 INSERT_OPERAND (mips_opts.micromips,
4857 EXTMSBD, insn, va_arg (args, int));
4861 gas_assert (!mips_opts.micromips);
4862 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4871 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
4875 gas_assert (mips_opts.micromips);
4879 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4883 gas_assert (!mips_opts.micromips);
4884 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4888 gas_assert (!mips_opts.micromips);
4890 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4894 if (mips_opts.micromips)
4895 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4897 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4901 gas_assert (!mips_opts.micromips);
4903 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
4907 gas_assert (!mips_opts.micromips);
4909 int tmp = va_arg (args, int);
4911 INSERT_OPERAND (0, RT, insn, tmp);
4912 INSERT_OPERAND (0, RD, insn, tmp);
4918 gas_assert (!mips_opts.micromips);
4919 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
4926 INSERT_OPERAND (mips_opts.micromips,
4927 SHAMT, insn, va_arg (args, int));
4931 gas_assert (!mips_opts.micromips);
4932 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
4936 gas_assert (!mips_opts.micromips);
4937 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
4941 gas_assert (!mips_opts.micromips);
4942 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4946 gas_assert (!mips_opts.micromips);
4947 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
4954 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
4959 macro_read_relocs (&args, r);
4960 gas_assert (*r == BFD_RELOC_GPREL16
4961 || *r == BFD_RELOC_MIPS_HIGHER
4962 || *r == BFD_RELOC_HI16_S
4963 || *r == BFD_RELOC_LO16
4964 || *r == BFD_RELOC_MIPS_GOT_OFST);
4968 macro_read_relocs (&args, r);
4972 macro_read_relocs (&args, r);
4973 gas_assert (ep != NULL
4974 && (ep->X_op == O_constant
4975 || (ep->X_op == O_symbol
4976 && (*r == BFD_RELOC_MIPS_HIGHEST
4977 || *r == BFD_RELOC_HI16_S
4978 || *r == BFD_RELOC_HI16
4979 || *r == BFD_RELOC_GPREL16
4980 || *r == BFD_RELOC_MIPS_GOT_HI16
4981 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4985 gas_assert (ep != NULL);
4988 * This allows macro() to pass an immediate expression for
4989 * creating short branches without creating a symbol.
4991 * We don't allow branch relaxation for these branches, as
4992 * they should only appear in ".set nomacro" anyway.
4994 if (ep->X_op == O_constant)
4996 /* For microMIPS we always use relocations for branches.
4997 So we should not resolve immediate values. */
4998 gas_assert (!mips_opts.micromips);
5000 if ((ep->X_add_number & 3) != 0)
5001 as_bad (_("branch to misaligned address (0x%lx)"),
5002 (unsigned long) ep->X_add_number);
5003 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5004 as_bad (_("branch address range overflow (0x%lx)"),
5005 (unsigned long) ep->X_add_number);
5006 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5010 *r = BFD_RELOC_16_PCREL_S2;
5014 gas_assert (ep != NULL);
5015 *r = BFD_RELOC_MIPS_JMP;
5019 gas_assert (!mips_opts.micromips);
5020 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5024 INSERT_OPERAND (mips_opts.micromips,
5025 CACHE, insn, va_arg (args, unsigned long));
5029 gas_assert (mips_opts.micromips);
5030 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5034 gas_assert (mips_opts.micromips);
5035 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5039 INSERT_OPERAND (mips_opts.micromips,
5040 3BITPOS, insn, va_arg (args, unsigned int));
5044 INSERT_OPERAND (mips_opts.micromips,
5045 OFFSET12, insn, va_arg (args, unsigned long));
5049 gas_assert (mips_opts.micromips);
5050 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5053 case 'm': /* Opcode extension character. */
5054 gas_assert (mips_opts.micromips);
5058 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5062 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5066 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5080 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5082 append_insn (&insn, ep, r, TRUE);
5086 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5089 struct mips_opcode *mo;
5090 struct mips_cl_insn insn;
5091 bfd_reloc_code_real_type r[3]
5092 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5094 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5096 gas_assert (strcmp (name, mo->name) == 0);
5098 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5101 gas_assert (mo->name);
5102 gas_assert (strcmp (name, mo->name) == 0);
5105 create_insn (&insn, mo);
5123 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5128 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5132 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5136 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5146 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5153 regno = va_arg (*args, int);
5154 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5155 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5176 gas_assert (ep != NULL);
5178 if (ep->X_op != O_constant)
5179 *r = (int) BFD_RELOC_UNUSED + c;
5182 mips16_immed (NULL, 0, c, ep->X_add_number,
5183 0, &insn.insn_opcode);
5185 *r = BFD_RELOC_UNUSED;
5191 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5198 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5200 append_insn (&insn, ep, r, TRUE);
5204 * Sign-extend 32-bit mode constants that have bit 31 set and all
5205 * higher bits unset.
5208 normalize_constant_expr (expressionS *ex)
5210 if (ex->X_op == O_constant
5211 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5212 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5217 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5218 * all higher bits unset.
5221 normalize_address_expr (expressionS *ex)
5223 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5224 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5225 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5226 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5231 * Generate a "jalr" instruction with a relocation hint to the called
5232 * function. This occurs in NewABI PIC code.
5235 macro_build_jalr (expressionS *ep, int cprestore)
5237 static const bfd_reloc_code_real_type jalr_relocs[2]
5238 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5239 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5243 if (MIPS_JALR_HINT_P (ep))
5248 if (mips_opts.micromips)
5250 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5251 if (MIPS_JALR_HINT_P (ep))
5252 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5254 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5257 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5258 if (MIPS_JALR_HINT_P (ep))
5259 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5263 * Generate a "lui" instruction.
5266 macro_build_lui (expressionS *ep, int regnum)
5268 gas_assert (! mips_opts.mips16);
5270 if (ep->X_op != O_constant)
5272 gas_assert (ep->X_op == O_symbol);
5273 /* _gp_disp is a special case, used from s_cpload.
5274 __gnu_local_gp is used if mips_no_shared. */
5275 gas_assert (mips_pic == NO_PIC
5277 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5278 || (! mips_in_shared
5279 && strcmp (S_GET_NAME (ep->X_add_symbol),
5280 "__gnu_local_gp") == 0));
5283 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5286 /* Generate a sequence of instructions to do a load or store from a constant
5287 offset off of a base register (breg) into/from a target register (treg),
5288 using AT if necessary. */
5290 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5291 int treg, int breg, int dbl)
5293 gas_assert (ep->X_op == O_constant);
5295 /* Sign-extending 32-bit constants makes their handling easier. */
5297 normalize_constant_expr (ep);
5299 /* Right now, this routine can only handle signed 32-bit constants. */
5300 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5301 as_warn (_("operand overflow"));
5303 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5305 /* Signed 16-bit offset will fit in the op. Easy! */
5306 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5310 /* 32-bit offset, need multiple instructions and AT, like:
5311 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5312 addu $tempreg,$tempreg,$breg
5313 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5314 to handle the complete offset. */
5315 macro_build_lui (ep, AT);
5316 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5317 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5320 as_bad (_("Macro used $at after \".set noat\""));
5325 * Generates code to set the $at register to true (one)
5326 * if reg is less than the immediate expression.
5329 set_at (int reg, int unsignedp)
5331 if (imm_expr.X_op == O_constant
5332 && imm_expr.X_add_number >= -0x8000
5333 && imm_expr.X_add_number < 0x8000)
5334 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5335 AT, reg, BFD_RELOC_LO16);
5338 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5339 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5343 /* Warn if an expression is not a constant. */
5346 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5348 if (ex->X_op == O_big)
5349 as_bad (_("unsupported large constant"));
5350 else if (ex->X_op != O_constant)
5351 as_bad (_("Instruction %s requires absolute expression"),
5354 if (HAVE_32BIT_GPRS)
5355 normalize_constant_expr (ex);
5358 /* Count the leading zeroes by performing a binary chop. This is a
5359 bulky bit of source, but performance is a LOT better for the
5360 majority of values than a simple loop to count the bits:
5361 for (lcnt = 0; (lcnt < 32); lcnt++)
5362 if ((v) & (1 << (31 - lcnt)))
5364 However it is not code size friendly, and the gain will drop a bit
5365 on certain cached systems.
5367 #define COUNT_TOP_ZEROES(v) \
5368 (((v) & ~0xffff) == 0 \
5369 ? ((v) & ~0xff) == 0 \
5370 ? ((v) & ~0xf) == 0 \
5371 ? ((v) & ~0x3) == 0 \
5372 ? ((v) & ~0x1) == 0 \
5377 : ((v) & ~0x7) == 0 \
5380 : ((v) & ~0x3f) == 0 \
5381 ? ((v) & ~0x1f) == 0 \
5384 : ((v) & ~0x7f) == 0 \
5387 : ((v) & ~0xfff) == 0 \
5388 ? ((v) & ~0x3ff) == 0 \
5389 ? ((v) & ~0x1ff) == 0 \
5392 : ((v) & ~0x7ff) == 0 \
5395 : ((v) & ~0x3fff) == 0 \
5396 ? ((v) & ~0x1fff) == 0 \
5399 : ((v) & ~0x7fff) == 0 \
5402 : ((v) & ~0xffffff) == 0 \
5403 ? ((v) & ~0xfffff) == 0 \
5404 ? ((v) & ~0x3ffff) == 0 \
5405 ? ((v) & ~0x1ffff) == 0 \
5408 : ((v) & ~0x7ffff) == 0 \
5411 : ((v) & ~0x3fffff) == 0 \
5412 ? ((v) & ~0x1fffff) == 0 \
5415 : ((v) & ~0x7fffff) == 0 \
5418 : ((v) & ~0xfffffff) == 0 \
5419 ? ((v) & ~0x3ffffff) == 0 \
5420 ? ((v) & ~0x1ffffff) == 0 \
5423 : ((v) & ~0x7ffffff) == 0 \
5426 : ((v) & ~0x3fffffff) == 0 \
5427 ? ((v) & ~0x1fffffff) == 0 \
5430 : ((v) & ~0x7fffffff) == 0 \
5435 * This routine generates the least number of instructions necessary to load
5436 * an absolute expression value into a register.
5439 load_register (int reg, expressionS *ep, int dbl)
5442 expressionS hi32, lo32;
5444 if (ep->X_op != O_big)
5446 gas_assert (ep->X_op == O_constant);
5448 /* Sign-extending 32-bit constants makes their handling easier. */
5450 normalize_constant_expr (ep);
5452 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5454 /* We can handle 16 bit signed values with an addiu to
5455 $zero. No need to ever use daddiu here, since $zero and
5456 the result are always correct in 32 bit mode. */
5457 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5460 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5462 /* We can handle 16 bit unsigned values with an ori to
5464 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5467 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5469 /* 32 bit values require an lui. */
5470 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5471 if ((ep->X_add_number & 0xffff) != 0)
5472 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5477 /* The value is larger than 32 bits. */
5479 if (!dbl || HAVE_32BIT_GPRS)
5483 sprintf_vma (value, ep->X_add_number);
5484 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5485 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5489 if (ep->X_op != O_big)
5492 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5493 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5494 hi32.X_add_number &= 0xffffffff;
5496 lo32.X_add_number &= 0xffffffff;
5500 gas_assert (ep->X_add_number > 2);
5501 if (ep->X_add_number == 3)
5502 generic_bignum[3] = 0;
5503 else if (ep->X_add_number > 4)
5504 as_bad (_("Number larger than 64 bits"));
5505 lo32.X_op = O_constant;
5506 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5507 hi32.X_op = O_constant;
5508 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5511 if (hi32.X_add_number == 0)
5516 unsigned long hi, lo;
5518 if (hi32.X_add_number == (offsetT) 0xffffffff)
5520 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5522 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5525 if (lo32.X_add_number & 0x80000000)
5527 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5528 if (lo32.X_add_number & 0xffff)
5529 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5534 /* Check for 16bit shifted constant. We know that hi32 is
5535 non-zero, so start the mask on the first bit of the hi32
5540 unsigned long himask, lomask;
5544 himask = 0xffff >> (32 - shift);
5545 lomask = (0xffff << shift) & 0xffffffff;
5549 himask = 0xffff << (shift - 32);
5552 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5553 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5557 tmp.X_op = O_constant;
5559 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5560 | (lo32.X_add_number >> shift));
5562 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5563 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5564 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5565 reg, reg, (shift >= 32) ? shift - 32 : shift);
5570 while (shift <= (64 - 16));
5572 /* Find the bit number of the lowest one bit, and store the
5573 shifted value in hi/lo. */
5574 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5575 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5579 while ((lo & 1) == 0)
5584 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5590 while ((hi & 1) == 0)
5599 /* Optimize if the shifted value is a (power of 2) - 1. */
5600 if ((hi == 0 && ((lo + 1) & lo) == 0)
5601 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5603 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5608 /* This instruction will set the register to be all
5610 tmp.X_op = O_constant;
5611 tmp.X_add_number = (offsetT) -1;
5612 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5616 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5617 reg, reg, (bit >= 32) ? bit - 32 : bit);
5619 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5620 reg, reg, (shift >= 32) ? shift - 32 : shift);
5625 /* Sign extend hi32 before calling load_register, because we can
5626 generally get better code when we load a sign extended value. */
5627 if ((hi32.X_add_number & 0x80000000) != 0)
5628 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5629 load_register (reg, &hi32, 0);
5632 if ((lo32.X_add_number & 0xffff0000) == 0)
5636 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5644 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5646 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5647 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5653 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5657 mid16.X_add_number >>= 16;
5658 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5659 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5662 if ((lo32.X_add_number & 0xffff) != 0)
5663 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5667 load_delay_nop (void)
5669 if (!gpr_interlocks)
5670 macro_build (NULL, "nop", "");
5673 /* Load an address into a register. */
5676 load_address (int reg, expressionS *ep, int *used_at)
5678 if (ep->X_op != O_constant
5679 && ep->X_op != O_symbol)
5681 as_bad (_("expression too complex"));
5682 ep->X_op = O_constant;
5685 if (ep->X_op == O_constant)
5687 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5691 if (mips_pic == NO_PIC)
5693 /* If this is a reference to a GP relative symbol, we want
5694 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5696 lui $reg,<sym> (BFD_RELOC_HI16_S)
5697 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5698 If we have an addend, we always use the latter form.
5700 With 64bit address space and a usable $at we want
5701 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5702 lui $at,<sym> (BFD_RELOC_HI16_S)
5703 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5704 daddiu $at,<sym> (BFD_RELOC_LO16)
5708 If $at is already in use, we use a path which is suboptimal
5709 on superscalar processors.
5710 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5711 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5713 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5715 daddiu $reg,<sym> (BFD_RELOC_LO16)
5717 For GP relative symbols in 64bit address space we can use
5718 the same sequence as in 32bit address space. */
5719 if (HAVE_64BIT_SYMBOLS)
5721 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5722 && !nopic_need_relax (ep->X_add_symbol, 1))
5724 relax_start (ep->X_add_symbol);
5725 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5726 mips_gp_register, BFD_RELOC_GPREL16);
5730 if (*used_at == 0 && mips_opts.at)
5732 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5733 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5734 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5735 BFD_RELOC_MIPS_HIGHER);
5736 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5737 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5738 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5743 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5744 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5745 BFD_RELOC_MIPS_HIGHER);
5746 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5747 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5748 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5749 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5752 if (mips_relax.sequence)
5757 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5758 && !nopic_need_relax (ep->X_add_symbol, 1))
5760 relax_start (ep->X_add_symbol);
5761 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5762 mips_gp_register, BFD_RELOC_GPREL16);
5765 macro_build_lui (ep, reg);
5766 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5767 reg, reg, BFD_RELOC_LO16);
5768 if (mips_relax.sequence)
5772 else if (!mips_big_got)
5776 /* If this is a reference to an external symbol, we want
5777 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5779 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5781 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5782 If there is a constant, it must be added in after.
5784 If we have NewABI, we want
5785 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5786 unless we're referencing a global symbol with a non-zero
5787 offset, in which case cst must be added separately. */
5790 if (ep->X_add_number)
5792 ex.X_add_number = ep->X_add_number;
5793 ep->X_add_number = 0;
5794 relax_start (ep->X_add_symbol);
5795 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5796 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5797 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5798 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5799 ex.X_op = O_constant;
5800 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5801 reg, reg, BFD_RELOC_LO16);
5802 ep->X_add_number = ex.X_add_number;
5805 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5806 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5807 if (mips_relax.sequence)
5812 ex.X_add_number = ep->X_add_number;
5813 ep->X_add_number = 0;
5814 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5815 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5817 relax_start (ep->X_add_symbol);
5819 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5823 if (ex.X_add_number != 0)
5825 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5826 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5827 ex.X_op = O_constant;
5828 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5829 reg, reg, BFD_RELOC_LO16);
5833 else if (mips_big_got)
5837 /* This is the large GOT case. If this is a reference to an
5838 external symbol, we want
5839 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5841 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5843 Otherwise, for a reference to a local symbol in old ABI, we want
5844 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5846 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5847 If there is a constant, it must be added in after.
5849 In the NewABI, for local symbols, with or without offsets, we want:
5850 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5851 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5855 ex.X_add_number = ep->X_add_number;
5856 ep->X_add_number = 0;
5857 relax_start (ep->X_add_symbol);
5858 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5859 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5860 reg, reg, mips_gp_register);
5861 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5862 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5863 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5864 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5865 else if (ex.X_add_number)
5867 ex.X_op = O_constant;
5868 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5872 ep->X_add_number = ex.X_add_number;
5874 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5875 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5876 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5877 BFD_RELOC_MIPS_GOT_OFST);
5882 ex.X_add_number = ep->X_add_number;
5883 ep->X_add_number = 0;
5884 relax_start (ep->X_add_symbol);
5885 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5886 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5887 reg, reg, mips_gp_register);
5888 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5889 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5891 if (reg_needs_delay (mips_gp_register))
5893 /* We need a nop before loading from $gp. This special
5894 check is required because the lui which starts the main
5895 instruction stream does not refer to $gp, and so will not
5896 insert the nop which may be required. */
5897 macro_build (NULL, "nop", "");
5899 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5900 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5902 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5906 if (ex.X_add_number != 0)
5908 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5909 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5910 ex.X_op = O_constant;
5911 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5919 if (!mips_opts.at && *used_at == 1)
5920 as_bad (_("Macro used $at after \".set noat\""));
5923 /* Move the contents of register SOURCE into register DEST. */
5926 move_register (int dest, int source)
5928 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5929 instruction specifically requires a 32-bit one. */
5930 if (mips_opts.micromips
5931 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5932 macro_build (NULL, "move", "mp,mj", dest, source);
5934 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5938 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5939 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5940 The two alternatives are:
5942 Global symbol Local sybmol
5943 ------------- ------------
5944 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5946 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5948 load_got_offset emits the first instruction and add_got_offset
5949 emits the second for a 16-bit offset or add_got_offset_hilo emits
5950 a sequence to add a 32-bit offset using a scratch register. */
5953 load_got_offset (int dest, expressionS *local)
5958 global.X_add_number = 0;
5960 relax_start (local->X_add_symbol);
5961 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5962 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5964 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5965 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5970 add_got_offset (int dest, expressionS *local)
5974 global.X_op = O_constant;
5975 global.X_op_symbol = NULL;
5976 global.X_add_symbol = NULL;
5977 global.X_add_number = local->X_add_number;
5979 relax_start (local->X_add_symbol);
5980 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5981 dest, dest, BFD_RELOC_LO16);
5983 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5988 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5991 int hold_mips_optimize;
5993 global.X_op = O_constant;
5994 global.X_op_symbol = NULL;
5995 global.X_add_symbol = NULL;
5996 global.X_add_number = local->X_add_number;
5998 relax_start (local->X_add_symbol);
5999 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6001 /* Set mips_optimize around the lui instruction to avoid
6002 inserting an unnecessary nop after the lw. */
6003 hold_mips_optimize = mips_optimize;
6005 macro_build_lui (&global, tmp);
6006 mips_optimize = hold_mips_optimize;
6007 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6010 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6013 /* Emit a sequence of instructions to emulate a branch likely operation.
6014 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6015 is its complementing branch with the original condition negated.
6016 CALL is set if the original branch specified the link operation.
6017 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6019 Code like this is produced in the noreorder mode:
6024 delay slot (executed only if branch taken)
6032 delay slot (executed only if branch taken)
6035 In the reorder mode the delay slot would be filled with a nop anyway,
6036 so code produced is simply:
6041 This function is used when producing code for the microMIPS ASE that
6042 does not implement branch likely instructions in hardware. */
6045 macro_build_branch_likely (const char *br, const char *brneg,
6046 int call, expressionS *ep, const char *fmt,
6047 unsigned int sreg, unsigned int treg)
6049 int noreorder = mips_opts.noreorder;
6052 gas_assert (mips_opts.micromips);
6056 micromips_label_expr (&expr1);
6057 macro_build (&expr1, brneg, fmt, sreg, treg);
6058 macro_build (NULL, "nop", "");
6059 macro_build (ep, call ? "bal" : "b", "p");
6061 /* Set to true so that append_insn adds a label. */
6062 emit_branch_likely_macro = TRUE;
6066 macro_build (ep, br, fmt, sreg, treg);
6067 macro_build (NULL, "nop", "");
6072 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6073 the condition code tested. EP specifies the branch target. */
6076 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6103 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6106 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6107 the register tested. EP specifies the branch target. */
6110 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6112 const char *brneg = NULL;
6122 br = mips_opts.micromips ? "bgez" : "bgezl";
6126 gas_assert (mips_opts.micromips);
6135 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6142 br = mips_opts.micromips ? "blez" : "blezl";
6149 br = mips_opts.micromips ? "bltz" : "bltzl";
6153 gas_assert (mips_opts.micromips);
6161 if (mips_opts.micromips && brneg)
6162 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6164 macro_build (ep, br, "s,p", sreg);
6167 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6168 TREG as the registers tested. EP specifies the branch target. */
6171 macro_build_branch_rsrt (int type, expressionS *ep,
6172 unsigned int sreg, unsigned int treg)
6174 const char *brneg = NULL;
6186 br = mips_opts.micromips ? "beq" : "beql";
6195 br = mips_opts.micromips ? "bne" : "bnel";
6201 if (mips_opts.micromips && brneg)
6202 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6204 macro_build (ep, br, "s,t,p", sreg, treg);
6209 * This routine implements the seemingly endless macro or synthesized
6210 * instructions and addressing modes in the mips assembly language. Many
6211 * of these macros are simple and are similar to each other. These could
6212 * probably be handled by some kind of table or grammar approach instead of
6213 * this verbose method. Others are not simple macros but are more like
6214 * optimizing code generation.
6215 * One interesting optimization is when several store macros appear
6216 * consecutively that would load AT with the upper half of the same address.
6217 * The ensuing load upper instructions are ommited. This implies some kind
6218 * of global optimization. We currently only optimize within a single macro.
6219 * For many of the load and store macros if the address is specified as a
6220 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6221 * first load register 'at' with zero and use it as the base register. The
6222 * mips assembler simply uses register $zero. Just one tiny optimization
6226 macro (struct mips_cl_insn *ip)
6228 unsigned int treg, sreg, dreg, breg;
6229 unsigned int tempreg;
6232 expressionS label_expr;
6251 bfd_reloc_code_real_type r;
6252 int hold_mips_optimize;
6254 gas_assert (! mips_opts.mips16);
6256 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6257 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6258 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6259 mask = ip->insn_mo->mask;
6261 label_expr.X_op = O_constant;
6262 label_expr.X_op_symbol = NULL;
6263 label_expr.X_add_symbol = NULL;
6264 label_expr.X_add_number = 0;
6266 expr1.X_op = O_constant;
6267 expr1.X_op_symbol = NULL;
6268 expr1.X_add_symbol = NULL;
6269 expr1.X_add_number = 1;
6284 if (mips_opts.micromips)
6285 micromips_label_expr (&label_expr);
6287 label_expr.X_add_number = 8;
6288 macro_build (&label_expr, "bgez", "s,p", sreg);
6290 macro_build (NULL, "nop", "");
6292 move_register (dreg, sreg);
6293 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6294 if (mips_opts.micromips)
6295 micromips_add_label ();
6312 if (!mips_opts.micromips)
6314 if (imm_expr.X_op == O_constant
6315 && imm_expr.X_add_number >= -0x200
6316 && imm_expr.X_add_number < 0x200)
6318 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6327 if (imm_expr.X_op == O_constant
6328 && imm_expr.X_add_number >= -0x8000
6329 && imm_expr.X_add_number < 0x8000)
6331 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6336 load_register (AT, &imm_expr, dbl);
6337 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6356 if (imm_expr.X_op == O_constant
6357 && imm_expr.X_add_number >= 0
6358 && imm_expr.X_add_number < 0x10000)
6360 if (mask != M_NOR_I)
6361 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6364 macro_build (&imm_expr, "ori", "t,r,i",
6365 treg, sreg, BFD_RELOC_LO16);
6366 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6372 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6373 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6377 switch (imm_expr.X_add_number)
6380 macro_build (NULL, "nop", "");
6383 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6387 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6388 (int) imm_expr.X_add_number);
6391 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6392 (unsigned long) imm_expr.X_add_number);
6401 gas_assert (mips_opts.micromips);
6402 macro_build_branch_ccl (mask, &offset_expr,
6403 EXTRACT_OPERAND (1, BCC, *ip));
6410 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6416 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6421 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6428 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6430 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6434 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6435 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6436 &offset_expr, AT, ZERO);
6446 macro_build_branch_rs (mask, &offset_expr, sreg);
6452 /* Check for > max integer. */
6453 maxnum = 0x7fffffff;
6454 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6461 if (imm_expr.X_op == O_constant
6462 && imm_expr.X_add_number >= maxnum
6463 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6466 /* Result is always false. */
6468 macro_build (NULL, "nop", "");
6470 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6473 if (imm_expr.X_op != O_constant)
6474 as_bad (_("Unsupported large constant"));
6475 ++imm_expr.X_add_number;
6479 if (mask == M_BGEL_I)
6481 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6483 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6484 &offset_expr, sreg);
6487 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6489 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6490 &offset_expr, sreg);
6493 maxnum = 0x7fffffff;
6494 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6501 maxnum = - maxnum - 1;
6502 if (imm_expr.X_op == O_constant
6503 && imm_expr.X_add_number <= maxnum
6504 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6507 /* result is always true */
6508 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6509 macro_build (&offset_expr, "b", "p");
6514 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6515 &offset_expr, AT, ZERO);
6524 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6525 &offset_expr, ZERO, treg);
6529 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6530 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6531 &offset_expr, AT, ZERO);
6540 && imm_expr.X_op == O_constant
6541 && imm_expr.X_add_number == -1))
6543 if (imm_expr.X_op != O_constant)
6544 as_bad (_("Unsupported large constant"));
6545 ++imm_expr.X_add_number;
6549 if (mask == M_BGEUL_I)
6551 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6553 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6554 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6555 &offset_expr, sreg, ZERO);
6560 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6561 &offset_expr, AT, ZERO);
6569 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6571 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6575 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6576 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6577 &offset_expr, AT, ZERO);
6585 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6586 &offset_expr, sreg, ZERO);
6592 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6593 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6594 &offset_expr, AT, ZERO);
6602 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6604 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6608 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6609 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6610 &offset_expr, AT, ZERO);
6617 maxnum = 0x7fffffff;
6618 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6625 if (imm_expr.X_op == O_constant
6626 && imm_expr.X_add_number >= maxnum
6627 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6629 if (imm_expr.X_op != O_constant)
6630 as_bad (_("Unsupported large constant"));
6631 ++imm_expr.X_add_number;
6635 if (mask == M_BLTL_I)
6637 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6638 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6639 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6640 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6645 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6646 &offset_expr, AT, ZERO);
6654 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6655 &offset_expr, sreg, ZERO);
6661 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6662 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6663 &offset_expr, AT, ZERO);
6672 && imm_expr.X_op == O_constant
6673 && imm_expr.X_add_number == -1))
6675 if (imm_expr.X_op != O_constant)
6676 as_bad (_("Unsupported large constant"));
6677 ++imm_expr.X_add_number;
6681 if (mask == M_BLTUL_I)
6683 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6685 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6686 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6687 &offset_expr, sreg, ZERO);
6692 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6693 &offset_expr, AT, ZERO);
6701 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6703 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6707 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6708 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6709 &offset_expr, AT, ZERO);
6719 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6720 &offset_expr, ZERO, treg);
6724 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6725 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6726 &offset_expr, AT, ZERO);
6732 /* Use unsigned arithmetic. */
6736 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6738 as_bad (_("Unsupported large constant"));
6743 pos = imm_expr.X_add_number;
6744 size = imm2_expr.X_add_number;
6749 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6752 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6754 as_bad (_("Improper extract size (%lu, position %lu)"),
6755 (unsigned long) size, (unsigned long) pos);
6759 if (size <= 32 && pos < 32)
6764 else if (size <= 32)
6774 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6781 /* Use unsigned arithmetic. */
6785 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6787 as_bad (_("Unsupported large constant"));
6792 pos = imm_expr.X_add_number;
6793 size = imm2_expr.X_add_number;
6798 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6801 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6803 as_bad (_("Improper insert size (%lu, position %lu)"),
6804 (unsigned long) size, (unsigned long) pos);
6808 if (pos < 32 && (pos + size - 1) < 32)
6823 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6824 (int) (pos + size - 1));
6840 as_warn (_("Divide by zero."));
6842 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6844 macro_build (NULL, "break", BRK_FMT, 7);
6851 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6852 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6856 if (mips_opts.micromips)
6857 micromips_label_expr (&label_expr);
6859 label_expr.X_add_number = 8;
6860 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6861 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6862 macro_build (NULL, "break", BRK_FMT, 7);
6863 if (mips_opts.micromips)
6864 micromips_add_label ();
6866 expr1.X_add_number = -1;
6868 load_register (AT, &expr1, dbl);
6869 if (mips_opts.micromips)
6870 micromips_label_expr (&label_expr);
6872 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6873 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6876 expr1.X_add_number = 1;
6877 load_register (AT, &expr1, dbl);
6878 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6882 expr1.X_add_number = 0x80000000;
6883 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6887 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6888 /* We want to close the noreorder block as soon as possible, so
6889 that later insns are available for delay slot filling. */
6894 if (mips_opts.micromips)
6895 micromips_label_expr (&label_expr);
6897 label_expr.X_add_number = 8;
6898 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6899 macro_build (NULL, "nop", "");
6901 /* We want to close the noreorder block as soon as possible, so
6902 that later insns are available for delay slot filling. */
6905 macro_build (NULL, "break", BRK_FMT, 6);
6907 if (mips_opts.micromips)
6908 micromips_add_label ();
6909 macro_build (NULL, s, MFHL_FMT, dreg);
6948 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6950 as_warn (_("Divide by zero."));
6952 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6954 macro_build (NULL, "break", BRK_FMT, 7);
6957 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6959 if (strcmp (s2, "mflo") == 0)
6960 move_register (dreg, sreg);
6962 move_register (dreg, ZERO);
6965 if (imm_expr.X_op == O_constant
6966 && imm_expr.X_add_number == -1
6967 && s[strlen (s) - 1] != 'u')
6969 if (strcmp (s2, "mflo") == 0)
6971 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
6974 move_register (dreg, ZERO);
6979 load_register (AT, &imm_expr, dbl);
6980 macro_build (NULL, s, "z,s,t", sreg, AT);
6981 macro_build (NULL, s2, MFHL_FMT, dreg);
7003 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7004 macro_build (NULL, s, "z,s,t", sreg, treg);
7005 /* We want to close the noreorder block as soon as possible, so
7006 that later insns are available for delay slot filling. */
7011 if (mips_opts.micromips)
7012 micromips_label_expr (&label_expr);
7014 label_expr.X_add_number = 8;
7015 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7016 macro_build (NULL, s, "z,s,t", sreg, treg);
7018 /* We want to close the noreorder block as soon as possible, so
7019 that later insns are available for delay slot filling. */
7021 macro_build (NULL, "break", BRK_FMT, 7);
7022 if (mips_opts.micromips)
7023 micromips_add_label ();
7025 macro_build (NULL, s2, MFHL_FMT, dreg);
7037 /* Load the address of a symbol into a register. If breg is not
7038 zero, we then add a base register to it. */
7040 if (dbl && HAVE_32BIT_GPRS)
7041 as_warn (_("dla used to load 32-bit register"));
7043 if (!dbl && HAVE_64BIT_OBJECTS)
7044 as_warn (_("la used to load 64-bit address"));
7046 if (offset_expr.X_op == O_constant
7047 && offset_expr.X_add_number >= -0x8000
7048 && offset_expr.X_add_number < 0x8000)
7050 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7051 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7055 if (mips_opts.at && (treg == breg))
7065 if (offset_expr.X_op != O_symbol
7066 && offset_expr.X_op != O_constant)
7068 as_bad (_("Expression too complex"));
7069 offset_expr.X_op = O_constant;
7072 if (offset_expr.X_op == O_constant)
7073 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7074 else if (mips_pic == NO_PIC)
7076 /* If this is a reference to a GP relative symbol, we want
7077 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7079 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7080 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7081 If we have a constant, we need two instructions anyhow,
7082 so we may as well always use the latter form.
7084 With 64bit address space and a usable $at we want
7085 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7086 lui $at,<sym> (BFD_RELOC_HI16_S)
7087 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7088 daddiu $at,<sym> (BFD_RELOC_LO16)
7090 daddu $tempreg,$tempreg,$at
7092 If $at is already in use, we use a path which is suboptimal
7093 on superscalar processors.
7094 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7095 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7097 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7099 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7101 For GP relative symbols in 64bit address space we can use
7102 the same sequence as in 32bit address space. */
7103 if (HAVE_64BIT_SYMBOLS)
7105 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7106 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7108 relax_start (offset_expr.X_add_symbol);
7109 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7110 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7114 if (used_at == 0 && mips_opts.at)
7116 macro_build (&offset_expr, "lui", LUI_FMT,
7117 tempreg, BFD_RELOC_MIPS_HIGHEST);
7118 macro_build (&offset_expr, "lui", LUI_FMT,
7119 AT, BFD_RELOC_HI16_S);
7120 macro_build (&offset_expr, "daddiu", "t,r,j",
7121 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7122 macro_build (&offset_expr, "daddiu", "t,r,j",
7123 AT, AT, BFD_RELOC_LO16);
7124 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7125 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7130 macro_build (&offset_expr, "lui", LUI_FMT,
7131 tempreg, BFD_RELOC_MIPS_HIGHEST);
7132 macro_build (&offset_expr, "daddiu", "t,r,j",
7133 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7134 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7135 macro_build (&offset_expr, "daddiu", "t,r,j",
7136 tempreg, tempreg, BFD_RELOC_HI16_S);
7137 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7138 macro_build (&offset_expr, "daddiu", "t,r,j",
7139 tempreg, tempreg, BFD_RELOC_LO16);
7142 if (mips_relax.sequence)
7147 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7148 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7150 relax_start (offset_expr.X_add_symbol);
7151 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7152 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7155 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7156 as_bad (_("Offset too large"));
7157 macro_build_lui (&offset_expr, tempreg);
7158 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7159 tempreg, tempreg, BFD_RELOC_LO16);
7160 if (mips_relax.sequence)
7164 else if (!mips_big_got && !HAVE_NEWABI)
7166 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7168 /* If this is a reference to an external symbol, and there
7169 is no constant, we want
7170 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7171 or for lca or if tempreg is PIC_CALL_REG
7172 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7173 For a local symbol, we want
7174 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7176 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7178 If we have a small constant, and this is a reference to
7179 an external symbol, we want
7180 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7182 addiu $tempreg,$tempreg,<constant>
7183 For a local symbol, we want the same instruction
7184 sequence, but we output a BFD_RELOC_LO16 reloc on the
7187 If we have a large constant, and this is a reference to
7188 an external symbol, we want
7189 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7190 lui $at,<hiconstant>
7191 addiu $at,$at,<loconstant>
7192 addu $tempreg,$tempreg,$at
7193 For a local symbol, we want the same instruction
7194 sequence, but we output a BFD_RELOC_LO16 reloc on the
7198 if (offset_expr.X_add_number == 0)
7200 if (mips_pic == SVR4_PIC
7202 && (call || tempreg == PIC_CALL_REG))
7203 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7205 relax_start (offset_expr.X_add_symbol);
7206 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7207 lw_reloc_type, mips_gp_register);
7210 /* We're going to put in an addu instruction using
7211 tempreg, so we may as well insert the nop right
7216 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7217 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7219 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7220 tempreg, tempreg, BFD_RELOC_LO16);
7222 /* FIXME: If breg == 0, and the next instruction uses
7223 $tempreg, then if this variant case is used an extra
7224 nop will be generated. */
7226 else if (offset_expr.X_add_number >= -0x8000
7227 && offset_expr.X_add_number < 0x8000)
7229 load_got_offset (tempreg, &offset_expr);
7231 add_got_offset (tempreg, &offset_expr);
7235 expr1.X_add_number = offset_expr.X_add_number;
7236 offset_expr.X_add_number =
7237 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
7238 load_got_offset (tempreg, &offset_expr);
7239 offset_expr.X_add_number = expr1.X_add_number;
7240 /* If we are going to add in a base register, and the
7241 target register and the base register are the same,
7242 then we are using AT as a temporary register. Since
7243 we want to load the constant into AT, we add our
7244 current AT (from the global offset table) and the
7245 register into the register now, and pretend we were
7246 not using a base register. */
7250 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7255 add_got_offset_hilo (tempreg, &offset_expr, AT);
7259 else if (!mips_big_got && HAVE_NEWABI)
7261 int add_breg_early = 0;
7263 /* If this is a reference to an external, and there is no
7264 constant, or local symbol (*), with or without a
7266 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7267 or for lca or if tempreg is PIC_CALL_REG
7268 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7270 If we have a small constant, and this is a reference to
7271 an external symbol, we want
7272 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7273 addiu $tempreg,$tempreg,<constant>
7275 If we have a large constant, and this is a reference to
7276 an external symbol, we want
7277 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7278 lui $at,<hiconstant>
7279 addiu $at,$at,<loconstant>
7280 addu $tempreg,$tempreg,$at
7282 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7283 local symbols, even though it introduces an additional
7286 if (offset_expr.X_add_number)
7288 expr1.X_add_number = offset_expr.X_add_number;
7289 offset_expr.X_add_number = 0;
7291 relax_start (offset_expr.X_add_symbol);
7292 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7293 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7295 if (expr1.X_add_number >= -0x8000
7296 && expr1.X_add_number < 0x8000)
7298 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7299 tempreg, tempreg, BFD_RELOC_LO16);
7301 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7303 /* If we are going to add in a base register, and the
7304 target register and the base register are the same,
7305 then we are using AT as a temporary register. Since
7306 we want to load the constant into AT, we add our
7307 current AT (from the global offset table) and the
7308 register into the register now, and pretend we were
7309 not using a base register. */
7314 gas_assert (tempreg == AT);
7315 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7321 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7322 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7328 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7331 offset_expr.X_add_number = expr1.X_add_number;
7333 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7334 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7337 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7338 treg, tempreg, breg);
7344 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7346 relax_start (offset_expr.X_add_symbol);
7347 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7348 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7350 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7351 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7356 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7357 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7360 else if (mips_big_got && !HAVE_NEWABI)
7363 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7364 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7365 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7367 /* This is the large GOT case. If this is a reference to an
7368 external symbol, and there is no constant, we want
7369 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7370 addu $tempreg,$tempreg,$gp
7371 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7372 or for lca or if tempreg is PIC_CALL_REG
7373 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7374 addu $tempreg,$tempreg,$gp
7375 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7376 For a local symbol, we want
7377 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7379 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7381 If we have a small constant, and this is a reference to
7382 an external symbol, we want
7383 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7384 addu $tempreg,$tempreg,$gp
7385 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7387 addiu $tempreg,$tempreg,<constant>
7388 For a local symbol, we want
7389 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7391 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7393 If we have a large constant, and this is a reference to
7394 an external symbol, we want
7395 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7396 addu $tempreg,$tempreg,$gp
7397 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7398 lui $at,<hiconstant>
7399 addiu $at,$at,<loconstant>
7400 addu $tempreg,$tempreg,$at
7401 For a local symbol, we want
7402 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7403 lui $at,<hiconstant>
7404 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7405 addu $tempreg,$tempreg,$at
7408 expr1.X_add_number = offset_expr.X_add_number;
7409 offset_expr.X_add_number = 0;
7410 relax_start (offset_expr.X_add_symbol);
7411 gpdelay = reg_needs_delay (mips_gp_register);
7412 if (expr1.X_add_number == 0 && breg == 0
7413 && (call || tempreg == PIC_CALL_REG))
7415 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7416 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7418 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7419 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7420 tempreg, tempreg, mips_gp_register);
7421 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7422 tempreg, lw_reloc_type, tempreg);
7423 if (expr1.X_add_number == 0)
7427 /* We're going to put in an addu instruction using
7428 tempreg, so we may as well insert the nop right
7433 else if (expr1.X_add_number >= -0x8000
7434 && expr1.X_add_number < 0x8000)
7437 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7438 tempreg, tempreg, BFD_RELOC_LO16);
7442 /* If we are going to add in a base register, and the
7443 target register and the base register are the same,
7444 then we are using AT as a temporary register. Since
7445 we want to load the constant into AT, we add our
7446 current AT (from the global offset table) and the
7447 register into the register now, and pretend we were
7448 not using a base register. */
7453 gas_assert (tempreg == AT);
7455 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7460 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7461 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7465 offset_expr.X_add_number =
7466 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
7471 /* This is needed because this instruction uses $gp, but
7472 the first instruction on the main stream does not. */
7473 macro_build (NULL, "nop", "");
7476 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7477 local_reloc_type, mips_gp_register);
7478 if (expr1.X_add_number >= -0x8000
7479 && expr1.X_add_number < 0x8000)
7482 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7483 tempreg, tempreg, BFD_RELOC_LO16);
7484 /* FIXME: If add_number is 0, and there was no base
7485 register, the external symbol case ended with a load,
7486 so if the symbol turns out to not be external, and
7487 the next instruction uses tempreg, an unnecessary nop
7488 will be inserted. */
7494 /* We must add in the base register now, as in the
7495 external symbol case. */
7496 gas_assert (tempreg == AT);
7498 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7501 /* We set breg to 0 because we have arranged to add
7502 it in in both cases. */
7506 macro_build_lui (&expr1, AT);
7507 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7508 AT, AT, BFD_RELOC_LO16);
7509 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7510 tempreg, tempreg, AT);
7515 else if (mips_big_got && HAVE_NEWABI)
7517 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7518 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7519 int add_breg_early = 0;
7521 /* This is the large GOT case. If this is a reference to an
7522 external symbol, and there is no constant, we want
7523 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7524 add $tempreg,$tempreg,$gp
7525 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7526 or for lca or if tempreg is PIC_CALL_REG
7527 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7528 add $tempreg,$tempreg,$gp
7529 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7531 If we have a small constant, and this is a reference to
7532 an external symbol, we want
7533 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7534 add $tempreg,$tempreg,$gp
7535 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7536 addi $tempreg,$tempreg,<constant>
7538 If we have a large constant, and this is a reference to
7539 an external symbol, we want
7540 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7541 addu $tempreg,$tempreg,$gp
7542 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7543 lui $at,<hiconstant>
7544 addi $at,$at,<loconstant>
7545 add $tempreg,$tempreg,$at
7547 If we have NewABI, and we know it's a local symbol, we want
7548 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7549 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7550 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7552 relax_start (offset_expr.X_add_symbol);
7554 expr1.X_add_number = offset_expr.X_add_number;
7555 offset_expr.X_add_number = 0;
7557 if (expr1.X_add_number == 0 && breg == 0
7558 && (call || tempreg == PIC_CALL_REG))
7560 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7561 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7563 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7564 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7565 tempreg, tempreg, mips_gp_register);
7566 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7567 tempreg, lw_reloc_type, tempreg);
7569 if (expr1.X_add_number == 0)
7571 else if (expr1.X_add_number >= -0x8000
7572 && expr1.X_add_number < 0x8000)
7574 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7575 tempreg, tempreg, BFD_RELOC_LO16);
7577 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7579 /* If we are going to add in a base register, and the
7580 target register and the base register are the same,
7581 then we are using AT as a temporary register. Since
7582 we want to load the constant into AT, we add our
7583 current AT (from the global offset table) and the
7584 register into the register now, and pretend we were
7585 not using a base register. */
7590 gas_assert (tempreg == AT);
7591 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7597 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7598 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7603 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7606 offset_expr.X_add_number = expr1.X_add_number;
7607 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7608 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7609 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7610 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7613 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7614 treg, tempreg, breg);
7624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7628 gas_assert (!mips_opts.micromips);
7630 unsigned long temp = (treg << 16) | (0x01);
7631 macro_build (NULL, "c2", "C", temp);
7636 gas_assert (!mips_opts.micromips);
7638 unsigned long temp = (0x02);
7639 macro_build (NULL, "c2", "C", temp);
7644 gas_assert (!mips_opts.micromips);
7646 unsigned long temp = (treg << 16) | (0x02);
7647 macro_build (NULL, "c2", "C", temp);
7652 gas_assert (!mips_opts.micromips);
7653 macro_build (NULL, "c2", "C", 3);
7657 gas_assert (!mips_opts.micromips);
7659 unsigned long temp = (treg << 16) | 0x03;
7660 macro_build (NULL, "c2", "C", temp);
7665 /* The j instruction may not be used in PIC code, since it
7666 requires an absolute address. We convert it to a b
7668 if (mips_pic == NO_PIC)
7669 macro_build (&offset_expr, "j", "a");
7671 macro_build (&offset_expr, "b", "p");
7674 /* The jal instructions must be handled as macros because when
7675 generating PIC code they expand to multi-instruction
7676 sequences. Normally they are simple instructions. */
7681 gas_assert (mips_opts.micromips);
7689 if (mips_pic == NO_PIC)
7691 s = jals ? "jalrs" : "jalr";
7692 if (mips_opts.micromips && dreg == RA)
7693 macro_build (NULL, s, "mj", sreg);
7695 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7699 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7700 && mips_cprestore_offset >= 0);
7702 if (sreg != PIC_CALL_REG)
7703 as_warn (_("MIPS PIC call to register other than $25"));
7705 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7706 ? "jalrs" : "jalr");
7707 if (mips_opts.micromips && dreg == RA)
7708 macro_build (NULL, s, "mj", sreg);
7710 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7711 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7713 if (mips_cprestore_offset < 0)
7714 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7717 if (!mips_frame_reg_valid)
7719 as_warn (_("No .frame pseudo-op used in PIC code"));
7720 /* Quiet this warning. */
7721 mips_frame_reg_valid = 1;
7723 if (!mips_cprestore_valid)
7725 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7726 /* Quiet this warning. */
7727 mips_cprestore_valid = 1;
7729 if (mips_opts.noreorder)
7730 macro_build (NULL, "nop", "");
7731 expr1.X_add_number = mips_cprestore_offset;
7732 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7735 HAVE_64BIT_ADDRESSES);
7743 gas_assert (mips_opts.micromips);
7747 if (mips_pic == NO_PIC)
7748 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7749 else if (mips_pic == SVR4_PIC)
7751 /* If this is a reference to an external symbol, and we are
7752 using a small GOT, we want
7753 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7757 lw $gp,cprestore($sp)
7758 The cprestore value is set using the .cprestore
7759 pseudo-op. If we are using a big GOT, we want
7760 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7762 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7766 lw $gp,cprestore($sp)
7767 If the symbol is not external, we want
7768 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7770 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7773 lw $gp,cprestore($sp)
7775 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7776 sequences above, minus nops, unless the symbol is local,
7777 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7783 relax_start (offset_expr.X_add_symbol);
7784 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7785 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7788 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7789 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7795 relax_start (offset_expr.X_add_symbol);
7796 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7797 BFD_RELOC_MIPS_CALL_HI16);
7798 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7799 PIC_CALL_REG, mips_gp_register);
7800 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7801 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7804 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7805 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7807 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7808 PIC_CALL_REG, PIC_CALL_REG,
7809 BFD_RELOC_MIPS_GOT_OFST);
7813 macro_build_jalr (&offset_expr, 0);
7817 relax_start (offset_expr.X_add_symbol);
7820 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7821 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7830 gpdelay = reg_needs_delay (mips_gp_register);
7831 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7832 BFD_RELOC_MIPS_CALL_HI16);
7833 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7834 PIC_CALL_REG, mips_gp_register);
7835 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7836 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7841 macro_build (NULL, "nop", "");
7843 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7844 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7847 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7848 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7850 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7852 if (mips_cprestore_offset < 0)
7853 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7856 if (!mips_frame_reg_valid)
7858 as_warn (_("No .frame pseudo-op used in PIC code"));
7859 /* Quiet this warning. */
7860 mips_frame_reg_valid = 1;
7862 if (!mips_cprestore_valid)
7864 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7865 /* Quiet this warning. */
7866 mips_cprestore_valid = 1;
7868 if (mips_opts.noreorder)
7869 macro_build (NULL, "nop", "");
7870 expr1.X_add_number = mips_cprestore_offset;
7871 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7874 HAVE_64BIT_ADDRESSES);
7878 else if (mips_pic == VXWORKS_PIC)
7879 as_bad (_("Non-PIC jump used in PIC library"));
7889 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7897 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7928 gas_assert (!mips_opts.micromips);
7931 /* Itbl support may require additional care here. */
7938 /* Itbl support may require additional care here. */
7946 off12 = mips_opts.micromips;
7947 /* Itbl support may require additional care here. */
7952 gas_assert (!mips_opts.micromips);
7955 /* Itbl support may require additional care here. */
7963 off12 = mips_opts.micromips;
7970 off12 = mips_opts.micromips;
7976 /* Itbl support may require additional care here. */
7984 off12 = mips_opts.micromips;
7985 /* Itbl support may require additional care here. */
7992 /* Itbl support may require additional care here. */
8000 off12 = mips_opts.micromips;
8007 off12 = mips_opts.micromips;
8014 off12 = mips_opts.micromips;
8021 off12 = mips_opts.micromips;
8028 off12 = mips_opts.micromips;
8033 gas_assert (mips_opts.micromips);
8042 gas_assert (mips_opts.micromips);
8051 gas_assert (mips_opts.micromips);
8059 gas_assert (mips_opts.micromips);
8066 if (breg == treg + lp)
8069 tempreg = treg + lp;
8089 gas_assert (!mips_opts.micromips);
8092 /* Itbl support may require additional care here. */
8099 /* Itbl support may require additional care here. */
8107 off12 = mips_opts.micromips;
8108 /* Itbl support may require additional care here. */
8113 gas_assert (!mips_opts.micromips);
8116 /* Itbl support may require additional care here. */
8124 off12 = mips_opts.micromips;
8131 off12 = mips_opts.micromips;
8138 off12 = mips_opts.micromips;
8145 off12 = mips_opts.micromips;
8151 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8152 off12 = mips_opts.micromips;
8158 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8159 off12 = mips_opts.micromips;
8166 /* Itbl support may require additional care here. */
8173 off12 = mips_opts.micromips;
8174 /* Itbl support may require additional care here. */
8179 gas_assert (!mips_opts.micromips);
8182 /* Itbl support may require additional care here. */
8190 off12 = mips_opts.micromips;
8197 off12 = mips_opts.micromips;
8202 gas_assert (mips_opts.micromips);
8210 gas_assert (mips_opts.micromips);
8218 gas_assert (mips_opts.micromips);
8226 gas_assert (mips_opts.micromips);
8235 if (offset_expr.X_op != O_constant
8236 && offset_expr.X_op != O_symbol)
8238 as_bad (_("Expression too complex"));
8239 offset_expr.X_op = O_constant;
8242 if (HAVE_32BIT_ADDRESSES
8243 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8247 sprintf_vma (value, offset_expr.X_add_number);
8248 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8251 /* A constant expression in PIC code can be handled just as it
8252 is in non PIC code. */
8253 if (offset_expr.X_op == O_constant)
8257 expr1.X_add_number = offset_expr.X_add_number;
8258 normalize_address_expr (&expr1);
8259 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8261 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8262 & ~(bfd_vma) 0xffff);
8265 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8267 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8268 & ~(bfd_vma) 0xfff);
8273 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8275 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8276 tempreg, tempreg, breg);
8281 if (offset_expr.X_add_number == 0)
8284 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8285 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8286 macro_build (NULL, s, fmt, treg, tempreg);
8289 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8291 macro_build (NULL, s, fmt,
8292 treg, (unsigned long) offset_expr.X_add_number, breg);
8294 else if (off12 || off0)
8296 /* A 12-bit or 0-bit offset field is too narrow to be used
8297 for a low-part relocation, so load the whole address into
8298 the auxillary register. In the case of "A(b)" addresses,
8299 we first load absolute address "A" into the register and
8300 then add base register "b". In the case of "o(b)" addresses,
8301 we simply need to add 16-bit offset "o" to base register "b", and
8302 offset_reloc already contains the relocations associated
8306 load_address (tempreg, &offset_expr, &used_at);
8308 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8309 tempreg, tempreg, breg);
8312 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8314 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8315 expr1.X_add_number = 0;
8317 macro_build (NULL, s, fmt, treg, tempreg);
8319 macro_build (NULL, s, fmt,
8320 treg, (unsigned long) expr1.X_add_number, tempreg);
8322 else if (mips_pic == NO_PIC)
8324 /* If this is a reference to a GP relative symbol, and there
8325 is no base register, we want
8326 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8327 Otherwise, if there is no base register, we want
8328 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8329 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8330 If we have a constant, we need two instructions anyhow,
8331 so we always use the latter form.
8333 If we have a base register, and this is a reference to a
8334 GP relative symbol, we want
8335 addu $tempreg,$breg,$gp
8336 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8338 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8339 addu $tempreg,$tempreg,$breg
8340 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8341 With a constant we always use the latter case.
8343 With 64bit address space and no base register and $at usable,
8345 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8346 lui $at,<sym> (BFD_RELOC_HI16_S)
8347 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8350 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8351 If we have a base register, we want
8352 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8353 lui $at,<sym> (BFD_RELOC_HI16_S)
8354 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8358 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8360 Without $at we can't generate the optimal path for superscalar
8361 processors here since this would require two temporary registers.
8362 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8363 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8365 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8367 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8368 If we have a base register, we want
8369 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8370 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8372 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8374 daddu $tempreg,$tempreg,$breg
8375 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8377 For GP relative symbols in 64bit address space we can use
8378 the same sequence as in 32bit address space. */
8379 if (HAVE_64BIT_SYMBOLS)
8381 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8382 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8384 relax_start (offset_expr.X_add_symbol);
8387 macro_build (&offset_expr, s, fmt, treg,
8388 BFD_RELOC_GPREL16, mips_gp_register);
8392 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8393 tempreg, breg, mips_gp_register);
8394 macro_build (&offset_expr, s, fmt, treg,
8395 BFD_RELOC_GPREL16, tempreg);
8400 if (used_at == 0 && mips_opts.at)
8402 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8403 BFD_RELOC_MIPS_HIGHEST);
8404 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8406 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8407 tempreg, BFD_RELOC_MIPS_HIGHER);
8409 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8410 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8411 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8412 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8418 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8419 BFD_RELOC_MIPS_HIGHEST);
8420 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8421 tempreg, BFD_RELOC_MIPS_HIGHER);
8422 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8423 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8424 tempreg, BFD_RELOC_HI16_S);
8425 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8427 macro_build (NULL, "daddu", "d,v,t",
8428 tempreg, tempreg, breg);
8429 macro_build (&offset_expr, s, fmt, treg,
8430 BFD_RELOC_LO16, tempreg);
8433 if (mips_relax.sequence)
8440 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8441 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8443 relax_start (offset_expr.X_add_symbol);
8444 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8448 macro_build_lui (&offset_expr, tempreg);
8449 macro_build (&offset_expr, s, fmt, treg,
8450 BFD_RELOC_LO16, tempreg);
8451 if (mips_relax.sequence)
8456 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8457 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8459 relax_start (offset_expr.X_add_symbol);
8460 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8461 tempreg, breg, mips_gp_register);
8462 macro_build (&offset_expr, s, fmt, treg,
8463 BFD_RELOC_GPREL16, tempreg);
8466 macro_build_lui (&offset_expr, tempreg);
8467 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8468 tempreg, tempreg, breg);
8469 macro_build (&offset_expr, s, fmt, treg,
8470 BFD_RELOC_LO16, tempreg);
8471 if (mips_relax.sequence)
8475 else if (!mips_big_got)
8477 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8479 /* If this is a reference to an external symbol, we want
8480 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8482 <op> $treg,0($tempreg)
8484 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8486 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8487 <op> $treg,0($tempreg)
8490 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8491 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8493 If there is a base register, we add it to $tempreg before
8494 the <op>. If there is a constant, we stick it in the
8495 <op> instruction. We don't handle constants larger than
8496 16 bits, because we have no way to load the upper 16 bits
8497 (actually, we could handle them for the subset of cases
8498 in which we are not using $at). */
8499 gas_assert (offset_expr.X_op == O_symbol);
8502 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8503 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8505 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8506 tempreg, tempreg, breg);
8507 macro_build (&offset_expr, s, fmt, treg,
8508 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8511 expr1.X_add_number = offset_expr.X_add_number;
8512 offset_expr.X_add_number = 0;
8513 if (expr1.X_add_number < -0x8000
8514 || expr1.X_add_number >= 0x8000)
8515 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8516 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8517 lw_reloc_type, mips_gp_register);
8519 relax_start (offset_expr.X_add_symbol);
8521 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8522 tempreg, BFD_RELOC_LO16);
8525 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8526 tempreg, tempreg, breg);
8527 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8529 else if (mips_big_got && !HAVE_NEWABI)
8533 /* If this is a reference to an external symbol, we want
8534 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8535 addu $tempreg,$tempreg,$gp
8536 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8537 <op> $treg,0($tempreg)
8539 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8541 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8542 <op> $treg,0($tempreg)
8543 If there is a base register, we add it to $tempreg before
8544 the <op>. If there is a constant, we stick it in the
8545 <op> instruction. We don't handle constants larger than
8546 16 bits, because we have no way to load the upper 16 bits
8547 (actually, we could handle them for the subset of cases
8548 in which we are not using $at). */
8549 gas_assert (offset_expr.X_op == O_symbol);
8550 expr1.X_add_number = offset_expr.X_add_number;
8551 offset_expr.X_add_number = 0;
8552 if (expr1.X_add_number < -0x8000
8553 || expr1.X_add_number >= 0x8000)
8554 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8555 gpdelay = reg_needs_delay (mips_gp_register);
8556 relax_start (offset_expr.X_add_symbol);
8557 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8558 BFD_RELOC_MIPS_GOT_HI16);
8559 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8561 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8562 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8565 macro_build (NULL, "nop", "");
8566 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8567 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8569 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8570 tempreg, BFD_RELOC_LO16);
8574 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8575 tempreg, tempreg, breg);
8576 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8578 else if (mips_big_got && HAVE_NEWABI)
8580 /* If this is a reference to an external symbol, we want
8581 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8582 add $tempreg,$tempreg,$gp
8583 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8584 <op> $treg,<ofst>($tempreg)
8585 Otherwise, for local symbols, we want:
8586 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8587 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8588 gas_assert (offset_expr.X_op == O_symbol);
8589 expr1.X_add_number = offset_expr.X_add_number;
8590 offset_expr.X_add_number = 0;
8591 if (expr1.X_add_number < -0x8000
8592 || expr1.X_add_number >= 0x8000)
8593 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8594 relax_start (offset_expr.X_add_symbol);
8595 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8596 BFD_RELOC_MIPS_GOT_HI16);
8597 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8599 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8600 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8602 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8603 tempreg, tempreg, breg);
8604 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8607 offset_expr.X_add_number = expr1.X_add_number;
8608 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8609 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8611 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8612 tempreg, tempreg, breg);
8613 macro_build (&offset_expr, s, fmt, treg,
8614 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8624 load_register (treg, &imm_expr, 0);
8628 load_register (treg, &imm_expr, 1);
8632 if (imm_expr.X_op == O_constant)
8635 load_register (AT, &imm_expr, 0);
8636 macro_build (NULL, "mtc1", "t,G", AT, treg);
8641 gas_assert (offset_expr.X_op == O_symbol
8642 && strcmp (segment_name (S_GET_SEGMENT
8643 (offset_expr.X_add_symbol)),
8645 && offset_expr.X_add_number == 0);
8646 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8647 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8652 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8653 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8654 order 32 bits of the value and the low order 32 bits are either
8655 zero or in OFFSET_EXPR. */
8656 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8658 if (HAVE_64BIT_GPRS)
8659 load_register (treg, &imm_expr, 1);
8664 if (target_big_endian)
8676 load_register (hreg, &imm_expr, 0);
8679 if (offset_expr.X_op == O_absent)
8680 move_register (lreg, 0);
8683 gas_assert (offset_expr.X_op == O_constant);
8684 load_register (lreg, &offset_expr, 0);
8691 /* We know that sym is in the .rdata section. First we get the
8692 upper 16 bits of the address. */
8693 if (mips_pic == NO_PIC)
8695 macro_build_lui (&offset_expr, AT);
8700 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8701 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8705 /* Now we load the register(s). */
8706 if (HAVE_64BIT_GPRS)
8709 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8714 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8717 /* FIXME: How in the world do we deal with the possible
8719 offset_expr.X_add_number += 4;
8720 macro_build (&offset_expr, "lw", "t,o(b)",
8721 treg + 1, BFD_RELOC_LO16, AT);
8727 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8728 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8729 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8730 the value and the low order 32 bits are either zero or in
8732 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8735 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8736 if (HAVE_64BIT_FPRS)
8738 gas_assert (HAVE_64BIT_GPRS);
8739 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8743 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8744 if (offset_expr.X_op == O_absent)
8745 macro_build (NULL, "mtc1", "t,G", 0, treg);
8748 gas_assert (offset_expr.X_op == O_constant);
8749 load_register (AT, &offset_expr, 0);
8750 macro_build (NULL, "mtc1", "t,G", AT, treg);
8756 gas_assert (offset_expr.X_op == O_symbol
8757 && offset_expr.X_add_number == 0);
8758 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8759 if (strcmp (s, ".lit8") == 0)
8761 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8763 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8764 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8767 breg = mips_gp_register;
8768 r = BFD_RELOC_MIPS_LITERAL;
8773 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8775 if (mips_pic != NO_PIC)
8776 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8777 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8780 /* FIXME: This won't work for a 64 bit address. */
8781 macro_build_lui (&offset_expr, AT);
8784 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8786 macro_build (&offset_expr, "ldc1", "T,o(b)",
8787 treg, BFD_RELOC_LO16, AT);
8796 /* Even on a big endian machine $fn comes before $fn+1. We have
8797 to adjust when loading from memory. */
8800 gas_assert (!mips_opts.micromips);
8801 gas_assert (mips_opts.isa == ISA_MIPS1);
8802 macro_build (&offset_expr, "lwc1", "T,o(b)",
8803 target_big_endian ? treg + 1 : treg, r, breg);
8804 /* FIXME: A possible overflow which I don't know how to deal
8806 offset_expr.X_add_number += 4;
8807 macro_build (&offset_expr, "lwc1", "T,o(b)",
8808 target_big_endian ? treg : treg + 1, r, breg);
8812 gas_assert (!mips_opts.micromips);
8813 gas_assert (mips_opts.isa == ISA_MIPS1);
8814 /* Even on a big endian machine $fn comes before $fn+1. We have
8815 to adjust when storing to memory. */
8816 macro_build (&offset_expr, "swc1", "T,o(b)",
8817 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8818 offset_expr.X_add_number += 4;
8819 macro_build (&offset_expr, "swc1", "T,o(b)",
8820 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8824 gas_assert (!mips_opts.micromips);
8826 * The MIPS assembler seems to check for X_add_number not
8827 * being double aligned and generating:
8830 * addiu at,at,%lo(foo+1)
8833 * But, the resulting address is the same after relocation so why
8834 * generate the extra instruction?
8836 /* Itbl support may require additional care here. */
8839 if (mips_opts.isa != ISA_MIPS1)
8848 gas_assert (!mips_opts.micromips);
8849 /* Itbl support may require additional care here. */
8852 if (mips_opts.isa != ISA_MIPS1)
8862 if (HAVE_64BIT_GPRS)
8872 if (HAVE_64BIT_GPRS)
8880 if (offset_expr.X_op != O_symbol
8881 && offset_expr.X_op != O_constant)
8883 as_bad (_("Expression too complex"));
8884 offset_expr.X_op = O_constant;
8887 if (HAVE_32BIT_ADDRESSES
8888 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8892 sprintf_vma (value, offset_expr.X_add_number);
8893 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8896 /* Even on a big endian machine $fn comes before $fn+1. We have
8897 to adjust when loading from memory. We set coproc if we must
8898 load $fn+1 first. */
8899 /* Itbl support may require additional care here. */
8900 if (!target_big_endian)
8903 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
8905 /* If this is a reference to a GP relative symbol, we want
8906 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8907 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8908 If we have a base register, we use this
8910 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8911 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8912 If this is not a GP relative symbol, we want
8913 lui $at,<sym> (BFD_RELOC_HI16_S)
8914 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8915 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8916 If there is a base register, we add it to $at after the
8917 lui instruction. If there is a constant, we always use
8919 if (offset_expr.X_op == O_symbol
8920 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8921 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8923 relax_start (offset_expr.X_add_symbol);
8926 tempreg = mips_gp_register;
8930 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8931 AT, breg, mips_gp_register);
8936 /* Itbl support may require additional care here. */
8937 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8938 BFD_RELOC_GPREL16, tempreg);
8939 offset_expr.X_add_number += 4;
8941 /* Set mips_optimize to 2 to avoid inserting an
8943 hold_mips_optimize = mips_optimize;
8945 /* Itbl support may require additional care here. */
8946 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8947 BFD_RELOC_GPREL16, tempreg);
8948 mips_optimize = hold_mips_optimize;
8952 offset_expr.X_add_number -= 4;
8955 macro_build_lui (&offset_expr, AT);
8957 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8958 /* Itbl support may require additional care here. */
8959 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8960 BFD_RELOC_LO16, AT);
8961 /* FIXME: How do we handle overflow here? */
8962 offset_expr.X_add_number += 4;
8963 /* Itbl support may require additional care here. */
8964 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8965 BFD_RELOC_LO16, AT);
8966 if (mips_relax.sequence)
8969 else if (!mips_big_got)
8971 /* If this is a reference to an external symbol, we want
8972 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8977 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8979 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8980 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8981 If there is a base register we add it to $at before the
8982 lwc1 instructions. If there is a constant we include it
8983 in the lwc1 instructions. */
8985 expr1.X_add_number = offset_expr.X_add_number;
8986 if (expr1.X_add_number < -0x8000
8987 || expr1.X_add_number >= 0x8000 - 4)
8988 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8989 load_got_offset (AT, &offset_expr);
8992 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8994 /* Set mips_optimize to 2 to avoid inserting an undesired
8996 hold_mips_optimize = mips_optimize;
8999 /* Itbl support may require additional care here. */
9000 relax_start (offset_expr.X_add_symbol);
9001 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9002 BFD_RELOC_LO16, AT);
9003 expr1.X_add_number += 4;
9004 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9005 BFD_RELOC_LO16, AT);
9007 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9008 BFD_RELOC_LO16, AT);
9009 offset_expr.X_add_number += 4;
9010 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9011 BFD_RELOC_LO16, AT);
9014 mips_optimize = hold_mips_optimize;
9016 else if (mips_big_got)
9020 /* If this is a reference to an external symbol, we want
9021 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9023 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9028 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9030 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9031 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9032 If there is a base register we add it to $at before the
9033 lwc1 instructions. If there is a constant we include it
9034 in the lwc1 instructions. */
9036 expr1.X_add_number = offset_expr.X_add_number;
9037 offset_expr.X_add_number = 0;
9038 if (expr1.X_add_number < -0x8000
9039 || expr1.X_add_number >= 0x8000 - 4)
9040 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9041 gpdelay = reg_needs_delay (mips_gp_register);
9042 relax_start (offset_expr.X_add_symbol);
9043 macro_build (&offset_expr, "lui", LUI_FMT,
9044 AT, BFD_RELOC_MIPS_GOT_HI16);
9045 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9046 AT, AT, mips_gp_register);
9047 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9048 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9051 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9052 /* Itbl support may require additional care here. */
9053 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9054 BFD_RELOC_LO16, AT);
9055 expr1.X_add_number += 4;
9057 /* Set mips_optimize to 2 to avoid inserting an undesired
9059 hold_mips_optimize = mips_optimize;
9061 /* Itbl support may require additional care here. */
9062 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9063 BFD_RELOC_LO16, AT);
9064 mips_optimize = hold_mips_optimize;
9065 expr1.X_add_number -= 4;
9068 offset_expr.X_add_number = expr1.X_add_number;
9070 macro_build (NULL, "nop", "");
9071 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9072 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9075 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9076 /* Itbl support may require additional care here. */
9077 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9078 BFD_RELOC_LO16, AT);
9079 offset_expr.X_add_number += 4;
9081 /* Set mips_optimize to 2 to avoid inserting an undesired
9083 hold_mips_optimize = mips_optimize;
9085 /* Itbl support may require additional care here. */
9086 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9087 BFD_RELOC_LO16, AT);
9088 mips_optimize = hold_mips_optimize;
9097 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9100 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9102 macro_build (&offset_expr, s, "t,o(b)", treg,
9103 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9105 if (!HAVE_64BIT_GPRS)
9107 offset_expr.X_add_number += 4;
9108 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9109 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9130 /* New code added to support COPZ instructions.
9131 This code builds table entries out of the macros in mip_opcodes.
9132 R4000 uses interlocks to handle coproc delays.
9133 Other chips (like the R3000) require nops to be inserted for delays.
9135 FIXME: Currently, we require that the user handle delays.
9136 In order to fill delay slots for non-interlocked chips,
9137 we must have a way to specify delays based on the coprocessor.
9138 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9139 What are the side-effects of the cop instruction?
9140 What cache support might we have and what are its effects?
9141 Both coprocessor & memory require delays. how long???
9142 What registers are read/set/modified?
9144 If an itbl is provided to interpret cop instructions,
9145 this knowledge can be encoded in the itbl spec. */
9159 gas_assert (!mips_opts.micromips);
9160 /* For now we just do C (same as Cz). The parameter will be
9161 stored in insn_opcode by mips_ip. */
9162 macro_build (NULL, s, "C", ip->insn_opcode);
9166 move_register (dreg, sreg);
9172 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9173 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9179 /* The MIPS assembler some times generates shifts and adds. I'm
9180 not trying to be that fancy. GCC should do this for us
9183 load_register (AT, &imm_expr, dbl);
9184 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9185 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9201 load_register (AT, &imm_expr, dbl);
9202 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9203 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9204 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9205 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9207 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9210 if (mips_opts.micromips)
9211 micromips_label_expr (&label_expr);
9213 label_expr.X_add_number = 8;
9214 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9215 macro_build (NULL, "nop", "");
9216 macro_build (NULL, "break", BRK_FMT, 6);
9217 if (mips_opts.micromips)
9218 micromips_add_label ();
9221 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9237 load_register (AT, &imm_expr, dbl);
9238 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9239 sreg, imm ? AT : treg);
9240 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9241 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9243 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9246 if (mips_opts.micromips)
9247 micromips_label_expr (&label_expr);
9249 label_expr.X_add_number = 8;
9250 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9251 macro_build (NULL, "nop", "");
9252 macro_build (NULL, "break", BRK_FMT, 6);
9253 if (mips_opts.micromips)
9254 micromips_add_label ();
9260 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9271 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9272 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9276 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9277 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9278 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9279 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9283 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9294 macro_build (NULL, "negu", "d,w", tempreg, treg);
9295 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9299 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9300 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9301 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9302 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9311 if (imm_expr.X_op != O_constant)
9312 as_bad (_("Improper rotate count"));
9313 rot = imm_expr.X_add_number & 0x3f;
9314 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9316 rot = (64 - rot) & 0x3f;
9318 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9320 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9325 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9328 l = (rot < 0x20) ? "dsll" : "dsll32";
9329 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9332 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9333 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9334 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9342 if (imm_expr.X_op != O_constant)
9343 as_bad (_("Improper rotate count"));
9344 rot = imm_expr.X_add_number & 0x1f;
9345 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9347 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9352 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9356 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9357 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9358 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9363 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9365 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9369 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9370 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9371 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9372 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9376 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9378 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9382 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9383 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9384 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9385 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9394 if (imm_expr.X_op != O_constant)
9395 as_bad (_("Improper rotate count"));
9396 rot = imm_expr.X_add_number & 0x3f;
9397 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9400 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9402 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9407 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9410 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9411 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9414 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9415 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9416 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9424 if (imm_expr.X_op != O_constant)
9425 as_bad (_("Improper rotate count"));
9426 rot = imm_expr.X_add_number & 0x1f;
9427 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9429 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9434 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9438 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9439 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9440 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9446 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9448 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9451 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9452 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9457 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9459 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9464 as_warn (_("Instruction %s: result is always false"),
9466 move_register (dreg, 0);
9469 if (CPU_HAS_SEQ (mips_opts.arch)
9470 && -512 <= imm_expr.X_add_number
9471 && imm_expr.X_add_number < 512)
9473 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9474 (int) imm_expr.X_add_number);
9477 if (imm_expr.X_op == O_constant
9478 && imm_expr.X_add_number >= 0
9479 && imm_expr.X_add_number < 0x10000)
9481 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9483 else if (imm_expr.X_op == O_constant
9484 && imm_expr.X_add_number > -0x8000
9485 && imm_expr.X_add_number < 0)
9487 imm_expr.X_add_number = -imm_expr.X_add_number;
9488 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9489 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9491 else if (CPU_HAS_SEQ (mips_opts.arch))
9494 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9495 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9500 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9501 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9504 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9507 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9513 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9514 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9517 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9519 if (imm_expr.X_op == O_constant
9520 && imm_expr.X_add_number >= -0x8000
9521 && imm_expr.X_add_number < 0x8000)
9523 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9524 dreg, sreg, BFD_RELOC_LO16);
9528 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9529 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9533 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9536 case M_SGT: /* sreg > treg <==> treg < sreg */
9542 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9545 case M_SGT_I: /* sreg > I <==> I < sreg */
9552 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9553 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9556 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9562 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9563 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9566 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9573 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9574 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9575 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9579 if (imm_expr.X_op == O_constant
9580 && imm_expr.X_add_number >= -0x8000
9581 && imm_expr.X_add_number < 0x8000)
9583 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9587 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9588 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9592 if (imm_expr.X_op == O_constant
9593 && imm_expr.X_add_number >= -0x8000
9594 && imm_expr.X_add_number < 0x8000)
9596 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9601 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9602 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9607 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9609 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9612 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9613 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9618 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9620 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9625 as_warn (_("Instruction %s: result is always true"),
9627 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9628 dreg, 0, BFD_RELOC_LO16);
9631 if (CPU_HAS_SEQ (mips_opts.arch)
9632 && -512 <= imm_expr.X_add_number
9633 && imm_expr.X_add_number < 512)
9635 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9636 (int) imm_expr.X_add_number);
9639 if (imm_expr.X_op == O_constant
9640 && imm_expr.X_add_number >= 0
9641 && imm_expr.X_add_number < 0x10000)
9643 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9645 else if (imm_expr.X_op == O_constant
9646 && imm_expr.X_add_number > -0x8000
9647 && imm_expr.X_add_number < 0)
9649 imm_expr.X_add_number = -imm_expr.X_add_number;
9650 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9651 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9653 else if (CPU_HAS_SEQ (mips_opts.arch))
9656 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9657 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9662 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9663 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9666 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9681 if (!mips_opts.micromips)
9683 if (imm_expr.X_op == O_constant
9684 && imm_expr.X_add_number > -0x200
9685 && imm_expr.X_add_number <= 0x200)
9687 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9696 if (imm_expr.X_op == O_constant
9697 && imm_expr.X_add_number > -0x8000
9698 && imm_expr.X_add_number <= 0x8000)
9700 imm_expr.X_add_number = -imm_expr.X_add_number;
9701 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9706 load_register (AT, &imm_expr, dbl);
9707 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9729 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9730 macro_build (NULL, s, "s,t", sreg, AT);
9735 gas_assert (!mips_opts.micromips);
9736 gas_assert (mips_opts.isa == ISA_MIPS1);
9738 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9739 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9742 * Is the double cfc1 instruction a bug in the mips assembler;
9743 * or is there a reason for it?
9746 macro_build (NULL, "cfc1", "t,G", treg, RA);
9747 macro_build (NULL, "cfc1", "t,G", treg, RA);
9748 macro_build (NULL, "nop", "");
9749 expr1.X_add_number = 3;
9750 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9751 expr1.X_add_number = 2;
9752 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9753 macro_build (NULL, "ctc1", "t,G", AT, RA);
9754 macro_build (NULL, "nop", "");
9755 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9757 macro_build (NULL, "ctc1", "t,G", treg, RA);
9758 macro_build (NULL, "nop", "");
9781 off12 = mips_opts.micromips;
9789 off12 = mips_opts.micromips;
9805 off12 = mips_opts.micromips;
9814 off12 = mips_opts.micromips;
9819 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9820 as_bad (_("Operand overflow"));
9823 expr1.X_add_number = 0;
9828 load_address (tempreg, ep, &used_at);
9830 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9831 tempreg, tempreg, breg);
9837 && (offset_expr.X_op != O_constant
9838 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9839 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9843 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9844 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9849 else if (!ust && treg == breg)
9860 if (!target_big_endian)
9861 ep->X_add_number += off;
9863 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9865 macro_build (NULL, s, "t,~(b)",
9866 tempreg, (unsigned long) ep->X_add_number, breg);
9868 if (!target_big_endian)
9869 ep->X_add_number -= off;
9871 ep->X_add_number += off;
9873 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9875 macro_build (NULL, s2, "t,~(b)",
9876 tempreg, (unsigned long) ep->X_add_number, breg);
9878 /* If necessary, move the result in tempreg to the final destination. */
9879 if (!ust && treg != tempreg)
9881 /* Protect second load's delay slot. */
9883 move_register (treg, tempreg);
9889 if (target_big_endian == ust)
9890 ep->X_add_number += off;
9891 tempreg = ust || ab ? treg : AT;
9892 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9894 /* For halfword transfers we need a temporary register to shuffle
9895 bytes. Unfortunately for M_USH_A we have none available before
9896 the next store as AT holds the base address. We deal with this
9897 case by clobbering TREG and then restoring it as with ULH. */
9898 tempreg = ust == ab ? treg : AT;
9900 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9902 if (target_big_endian == ust)
9903 ep->X_add_number -= off;
9905 ep->X_add_number += off;
9906 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9908 /* For M_USH_A re-retrieve the LSB. */
9911 if (target_big_endian)
9912 ep->X_add_number += off;
9914 ep->X_add_number -= off;
9915 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9917 /* For ULH and M_USH_A OR the LSB in. */
9920 tempreg = !ab ? AT : treg;
9921 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9922 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9927 /* FIXME: Check if this is one of the itbl macros, since they
9928 are added dynamically. */
9929 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9932 if (!mips_opts.at && used_at)
9933 as_bad (_("Macro used $at after \".set noat\""));
9936 /* Implement macros in mips16 mode. */
9939 mips16_macro (struct mips_cl_insn *ip)
9942 int xreg, yreg, zreg, tmp;
9945 const char *s, *s2, *s3;
9947 mask = ip->insn_mo->mask;
9949 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
9950 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
9951 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
9953 expr1.X_op = O_constant;
9954 expr1.X_op_symbol = NULL;
9955 expr1.X_add_symbol = NULL;
9956 expr1.X_add_number = 1;
9976 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
9977 expr1.X_add_number = 2;
9978 macro_build (&expr1, "bnez", "x,p", yreg);
9979 macro_build (NULL, "break", "6", 7);
9981 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9982 since that causes an overflow. We should do that as well,
9983 but I don't see how to do the comparisons without a temporary
9986 macro_build (NULL, s, "x", zreg);
10005 start_noreorder ();
10006 macro_build (NULL, s, "0,x,y", xreg, yreg);
10007 expr1.X_add_number = 2;
10008 macro_build (&expr1, "bnez", "x,p", yreg);
10009 macro_build (NULL, "break", "6", 7);
10011 macro_build (NULL, s2, "x", zreg);
10017 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10018 macro_build (NULL, "mflo", "x", zreg);
10026 if (imm_expr.X_op != O_constant)
10027 as_bad (_("Unsupported large constant"));
10028 imm_expr.X_add_number = -imm_expr.X_add_number;
10029 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10033 if (imm_expr.X_op != O_constant)
10034 as_bad (_("Unsupported large constant"));
10035 imm_expr.X_add_number = -imm_expr.X_add_number;
10036 macro_build (&imm_expr, "addiu", "x,k", xreg);
10040 if (imm_expr.X_op != O_constant)
10041 as_bad (_("Unsupported large constant"));
10042 imm_expr.X_add_number = -imm_expr.X_add_number;
10043 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10065 goto do_reverse_branch;
10069 goto do_reverse_branch;
10081 goto do_reverse_branch;
10092 macro_build (NULL, s, "x,y", xreg, yreg);
10093 macro_build (&offset_expr, s2, "p");
10120 goto do_addone_branch_i;
10125 goto do_addone_branch_i;
10140 goto do_addone_branch_i;
10146 do_addone_branch_i:
10147 if (imm_expr.X_op != O_constant)
10148 as_bad (_("Unsupported large constant"));
10149 ++imm_expr.X_add_number;
10152 macro_build (&imm_expr, s, s3, xreg);
10153 macro_build (&offset_expr, s2, "p");
10157 expr1.X_add_number = 0;
10158 macro_build (&expr1, "slti", "x,8", yreg);
10160 move_register (xreg, yreg);
10161 expr1.X_add_number = 2;
10162 macro_build (&expr1, "bteqz", "p");
10163 macro_build (NULL, "neg", "x,w", xreg, xreg);
10167 /* For consistency checking, verify that all bits are specified either
10168 by the match/mask part of the instruction definition, or by the
10171 validate_mips_insn (const struct mips_opcode *opc)
10173 const char *p = opc->args;
10175 unsigned long used_bits = opc->mask;
10177 if ((used_bits & opc->match) != opc->match)
10179 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10180 opc->name, opc->args);
10183 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10193 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10194 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10195 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10196 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10197 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10198 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10199 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10200 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10201 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10202 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10203 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10204 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10205 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10207 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10208 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10209 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10210 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10211 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10212 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10213 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10214 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10215 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10216 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10217 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10218 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10219 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10220 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10221 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10224 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10225 c, opc->name, opc->args);
10229 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10230 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10232 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10233 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10234 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10235 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10237 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10238 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10240 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10241 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10243 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10244 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10245 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10246 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10247 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10248 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10249 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10250 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10251 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10252 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10253 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10254 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10255 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10256 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10257 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10258 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10259 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10261 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10262 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10263 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10264 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10266 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10267 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10268 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10269 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10270 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10271 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10272 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10273 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10274 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10277 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10278 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10279 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10280 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10281 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10284 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10285 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10286 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10287 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10288 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10289 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10290 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10291 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10292 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10293 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10294 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10295 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10296 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10297 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10298 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10299 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10300 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10301 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10302 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10303 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10305 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10306 c, opc->name, opc->args);
10310 if (used_bits != 0xffffffff)
10312 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10313 ~used_bits & 0xffffffff, opc->name, opc->args);
10319 /* For consistency checking, verify that the length implied matches the
10320 major opcode and that all bits are specified either by the match/mask
10321 part of the instruction definition, or by the operand list. */
10324 validate_micromips_insn (const struct mips_opcode *opc)
10326 unsigned long match = opc->match;
10327 unsigned long mask = opc->mask;
10328 const char *p = opc->args;
10329 unsigned long insn_bits;
10330 unsigned long used_bits;
10331 unsigned long major;
10332 unsigned int length;
10336 if ((mask & match) != match)
10338 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10339 opc->name, opc->args);
10342 length = micromips_insn_length (opc);
10343 if (length != 2 && length != 4)
10345 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10346 "%s %s"), length, opc->name, opc->args);
10349 major = match >> (10 + 8 * (length - 2));
10350 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10351 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10353 as_bad (_("Internal error: bad microMIPS opcode "
10354 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10358 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10359 insn_bits = 1 << 4 * length;
10360 insn_bits <<= 4 * length;
10363 #define USE_BITS(field) \
10364 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10375 case 'A': USE_BITS (EXTLSB); break;
10376 case 'B': USE_BITS (INSMSB); break;
10377 case 'C': USE_BITS (EXTMSBD); break;
10378 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10379 case 'E': USE_BITS (EXTLSB); break;
10380 case 'F': USE_BITS (INSMSB); break;
10381 case 'G': USE_BITS (EXTMSBD); break;
10382 case 'H': USE_BITS (EXTMSBD); break;
10384 as_bad (_("Internal error: bad mips opcode "
10385 "(unknown extension operand type `%c%c'): %s %s"),
10386 e, c, opc->name, opc->args);
10394 case 'A': USE_BITS (IMMA); break;
10395 case 'B': USE_BITS (IMMB); break;
10396 case 'C': USE_BITS (IMMC); break;
10397 case 'D': USE_BITS (IMMD); break;
10398 case 'E': USE_BITS (IMME); break;
10399 case 'F': USE_BITS (IMMF); break;
10400 case 'G': USE_BITS (IMMG); break;
10401 case 'H': USE_BITS (IMMH); break;
10402 case 'I': USE_BITS (IMMI); break;
10403 case 'J': USE_BITS (IMMJ); break;
10404 case 'L': USE_BITS (IMML); break;
10405 case 'M': USE_BITS (IMMM); break;
10406 case 'N': USE_BITS (IMMN); break;
10407 case 'O': USE_BITS (IMMO); break;
10408 case 'P': USE_BITS (IMMP); break;
10409 case 'Q': USE_BITS (IMMQ); break;
10410 case 'U': USE_BITS (IMMU); break;
10411 case 'W': USE_BITS (IMMW); break;
10412 case 'X': USE_BITS (IMMX); break;
10413 case 'Y': USE_BITS (IMMY); break;
10416 case 'b': USE_BITS (MB); break;
10417 case 'c': USE_BITS (MC); break;
10418 case 'd': USE_BITS (MD); break;
10419 case 'e': USE_BITS (ME); break;
10420 case 'f': USE_BITS (MF); break;
10421 case 'g': USE_BITS (MG); break;
10422 case 'h': USE_BITS (MH); break;
10423 case 'i': USE_BITS (MI); break;
10424 case 'j': USE_BITS (MJ); break;
10425 case 'l': USE_BITS (ML); break;
10426 case 'm': USE_BITS (MM); break;
10427 case 'n': USE_BITS (MN); break;
10428 case 'p': USE_BITS (MP); break;
10429 case 'q': USE_BITS (MQ); break;
10437 as_bad (_("Internal error: bad mips opcode "
10438 "(unknown extension operand type `%c%c'): %s %s"),
10439 e, c, opc->name, opc->args);
10443 case '.': USE_BITS (OFFSET10); break;
10444 case '1': USE_BITS (STYPE); break;
10445 case '2': USE_BITS (BP); break;
10446 case '3': USE_BITS (SA3); break;
10447 case '4': USE_BITS (SA4); break;
10448 case '5': USE_BITS (IMM8); break;
10449 case '6': USE_BITS (RS); break;
10450 case '7': USE_BITS (DSPACC); break;
10451 case '8': USE_BITS (WRDSP); break;
10452 case '0': USE_BITS (DSPSFT); break;
10453 case '<': USE_BITS (SHAMT); break;
10454 case '>': USE_BITS (SHAMT); break;
10455 case '@': USE_BITS (IMM10); break;
10456 case 'B': USE_BITS (CODE10); break;
10457 case 'C': USE_BITS (COPZ); break;
10458 case 'D': USE_BITS (FD); break;
10459 case 'E': USE_BITS (RT); break;
10460 case 'G': USE_BITS (RS); break;
10461 case 'H': USE_BITS (SEL); break;
10462 case 'K': USE_BITS (RS); break;
10463 case 'M': USE_BITS (CCC); break;
10464 case 'N': USE_BITS (BCC); break;
10465 case 'R': USE_BITS (FR); break;
10466 case 'S': USE_BITS (FS); break;
10467 case 'T': USE_BITS (FT); break;
10468 case 'V': USE_BITS (FS); break;
10469 case '\\': USE_BITS (3BITPOS); break;
10470 case '^': USE_BITS (RD); break;
10471 case 'a': USE_BITS (TARGET); break;
10472 case 'b': USE_BITS (RS); break;
10473 case 'c': USE_BITS (CODE); break;
10474 case 'd': USE_BITS (RD); break;
10475 case 'h': USE_BITS (PREFX); break;
10476 case 'i': USE_BITS (IMMEDIATE); break;
10477 case 'j': USE_BITS (DELTA); break;
10478 case 'k': USE_BITS (CACHE); break;
10479 case 'n': USE_BITS (RT); break;
10480 case 'o': USE_BITS (DELTA); break;
10481 case 'p': USE_BITS (DELTA); break;
10482 case 'q': USE_BITS (CODE2); break;
10483 case 'r': USE_BITS (RS); break;
10484 case 's': USE_BITS (RS); break;
10485 case 't': USE_BITS (RT); break;
10486 case 'u': USE_BITS (IMMEDIATE); break;
10487 case 'v': USE_BITS (RS); break;
10488 case 'w': USE_BITS (RT); break;
10489 case 'y': USE_BITS (RS3); break;
10491 case '|': USE_BITS (TRAP); break;
10492 case '~': USE_BITS (OFFSET12); break;
10494 as_bad (_("Internal error: bad microMIPS opcode "
10495 "(unknown operand type `%c'): %s %s"),
10496 c, opc->name, opc->args);
10500 if (used_bits != insn_bits)
10502 if (~used_bits & insn_bits)
10503 as_bad (_("Internal error: bad microMIPS opcode "
10504 "(bits 0x%lx undefined): %s %s"),
10505 ~used_bits & insn_bits, opc->name, opc->args);
10506 if (used_bits & ~insn_bits)
10507 as_bad (_("Internal error: bad microMIPS opcode "
10508 "(bits 0x%lx defined): %s %s"),
10509 used_bits & ~insn_bits, opc->name, opc->args);
10515 /* UDI immediates. */
10516 struct mips_immed {
10518 unsigned int shift;
10519 unsigned long mask;
10523 static const struct mips_immed mips_immed[] = {
10524 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10525 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10526 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10527 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10531 /* Check whether an odd floating-point register is allowed. */
10533 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10535 const char *s = insn->name;
10537 if (insn->pinfo == INSN_MACRO)
10538 /* Let a macro pass, we'll catch it later when it is expanded. */
10541 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10543 /* Allow odd registers for single-precision ops. */
10544 switch (insn->pinfo & (FP_S | FP_D))
10548 return 1; /* both single precision - ok */
10550 return 0; /* both double precision - fail */
10555 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10556 s = strchr (insn->name, '.');
10558 s = s != NULL ? strchr (s + 1, '.') : NULL;
10559 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10562 /* Single-precision coprocessor loads and moves are OK too. */
10563 if ((insn->pinfo & FP_S)
10564 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10565 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10571 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10572 taking bits from BIT up. */
10574 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10576 return (ep->X_op == O_constant
10577 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10578 && ep->X_add_number >= min << bit
10579 && ep->X_add_number < max << bit);
10582 /* This routine assembles an instruction into its binary format. As a
10583 side effect, it sets one of the global variables imm_reloc or
10584 offset_reloc to the type of relocation to do if one of the operands
10585 is an address expression. */
10588 mips_ip (char *str, struct mips_cl_insn *ip)
10590 bfd_boolean wrong_delay_slot_insns = FALSE;
10591 bfd_boolean need_delay_slot_ok = TRUE;
10592 struct mips_opcode *firstinsn = NULL;
10593 const struct mips_opcode *past;
10594 struct hash_control *hash;
10598 struct mips_opcode *insn;
10600 unsigned int regno;
10601 unsigned int lastregno;
10602 unsigned int destregno = 0;
10603 unsigned int lastpos = 0;
10604 unsigned int limlo, limhi;
10606 offsetT min_range, max_range;
10610 unsigned int rtype;
10616 if (mips_opts.micromips)
10618 hash = micromips_op_hash;
10619 past = µmips_opcodes[bfd_micromips_num_opcodes];
10624 past = &mips_opcodes[NUMOPCODES];
10626 forced_insn_length = 0;
10629 /* We first try to match an instruction up to a space or to the end. */
10630 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10633 /* Make a copy of the instruction so that we can fiddle with it. */
10634 name = alloca (end + 1);
10635 memcpy (name, str, end);
10640 insn = (struct mips_opcode *) hash_find (hash, name);
10642 if (insn != NULL || !mips_opts.micromips)
10644 if (forced_insn_length)
10647 /* See if there's an instruction size override suffix,
10648 either `16' or `32', at the end of the mnemonic proper,
10649 that defines the operation, i.e. before the first `.'
10650 character if any. Strip it and retry. */
10651 dot = strchr (name, '.');
10652 opend = dot != NULL ? dot - name : end;
10655 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10656 forced_insn_length = 2;
10657 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10658 forced_insn_length = 4;
10661 memcpy (name + opend - 2, name + opend, end - opend + 1);
10665 insn_error = _("Unrecognized opcode");
10669 /* For microMIPS instructions placed in a fixed-length branch delay slot
10670 we make up to two passes over the relevant fragment of the opcode
10671 table. First we try instructions that meet the delay slot's length
10672 requirement. If none matched, then we retry with the remaining ones
10673 and if one matches, then we use it and then issue an appropriate
10674 warning later on. */
10675 argsStart = s = str + end;
10678 bfd_boolean delay_slot_ok;
10679 bfd_boolean size_ok;
10682 gas_assert (strcmp (insn->name, name) == 0);
10684 ok = is_opcode_valid (insn);
10685 size_ok = is_size_valid (insn);
10686 delay_slot_ok = is_delay_slot_valid (insn);
10687 if (!delay_slot_ok && !wrong_delay_slot_insns)
10690 wrong_delay_slot_insns = TRUE;
10692 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10694 static char buf[256];
10696 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10701 if (wrong_delay_slot_insns && need_delay_slot_ok)
10703 gas_assert (firstinsn);
10704 need_delay_slot_ok = FALSE;
10714 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10715 mips_cpu_info_from_arch (mips_opts.arch)->name,
10716 mips_cpu_info_from_isa (mips_opts.isa)->name);
10718 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10719 8 * forced_insn_length);
10725 create_insn (ip, insn);
10728 lastregno = 0xffffffff;
10729 for (args = insn->args;; ++args)
10733 s += strspn (s, " \t");
10737 case '\0': /* end of args */
10743 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10744 code) or 14 (for microMIPS code). */
10745 my_getExpression (&imm_expr, s);
10746 check_absolute_expr (ip, &imm_expr);
10747 if ((unsigned long) imm_expr.X_add_number != 1
10748 && (unsigned long) imm_expr.X_add_number != 3)
10750 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10751 (unsigned long) imm_expr.X_add_number);
10753 INSERT_OPERAND (mips_opts.micromips,
10754 BP, *ip, imm_expr.X_add_number);
10755 imm_expr.X_op = O_absent;
10760 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10761 code) or 21 (for microMIPS code). */
10763 unsigned long mask = (mips_opts.micromips
10764 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
10766 my_getExpression (&imm_expr, s);
10767 check_absolute_expr (ip, &imm_expr);
10768 if ((unsigned long) imm_expr.X_add_number > mask)
10769 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10770 mask, (unsigned long) imm_expr.X_add_number);
10771 INSERT_OPERAND (mips_opts.micromips,
10772 SA3, *ip, imm_expr.X_add_number);
10773 imm_expr.X_op = O_absent;
10779 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10780 code) or 21 (for microMIPS code). */
10782 unsigned long mask = (mips_opts.micromips
10783 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
10785 my_getExpression (&imm_expr, s);
10786 check_absolute_expr (ip, &imm_expr);
10787 if ((unsigned long) imm_expr.X_add_number > mask)
10788 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10789 mask, (unsigned long) imm_expr.X_add_number);
10790 INSERT_OPERAND (mips_opts.micromips,
10791 SA4, *ip, imm_expr.X_add_number);
10792 imm_expr.X_op = O_absent;
10798 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10799 code) or 16 (for microMIPS code). */
10801 unsigned long mask = (mips_opts.micromips
10802 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
10804 my_getExpression (&imm_expr, s);
10805 check_absolute_expr (ip, &imm_expr);
10806 if ((unsigned long) imm_expr.X_add_number > mask)
10807 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10808 mask, (unsigned long) imm_expr.X_add_number);
10809 INSERT_OPERAND (mips_opts.micromips,
10810 IMM8, *ip, imm_expr.X_add_number);
10811 imm_expr.X_op = O_absent;
10817 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
10818 code) or 21 (for microMIPS code). */
10820 unsigned long mask = (mips_opts.micromips
10821 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
10823 my_getExpression (&imm_expr, s);
10824 check_absolute_expr (ip, &imm_expr);
10825 if ((unsigned long) imm_expr.X_add_number > mask)
10826 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10827 mask, (unsigned long) imm_expr.X_add_number);
10828 INSERT_OPERAND (mips_opts.micromips,
10829 RS, *ip, imm_expr.X_add_number);
10830 imm_expr.X_op = O_absent;
10835 case '7': /* Four DSP accumulators in bits 11,12. */
10836 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
10837 && s[3] >= '0' && s[3] <= '3')
10839 regno = s[3] - '0';
10841 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
10845 as_bad (_("Invalid dsp acc register"));
10849 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
10850 code) or 14 (for microMIPS code). */
10852 unsigned long mask = (mips_opts.micromips
10853 ? MICROMIPSOP_MASK_WRDSP
10856 my_getExpression (&imm_expr, s);
10857 check_absolute_expr (ip, &imm_expr);
10858 if ((unsigned long) imm_expr.X_add_number > mask)
10859 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10860 mask, (unsigned long) imm_expr.X_add_number);
10861 INSERT_OPERAND (mips_opts.micromips,
10862 WRDSP, *ip, imm_expr.X_add_number);
10863 imm_expr.X_op = O_absent;
10868 case '9': /* Four DSP accumulators in bits 21,22. */
10869 gas_assert (!mips_opts.micromips);
10870 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
10871 && s[3] >= '0' && s[3] <= '3')
10873 regno = s[3] - '0';
10875 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10879 as_bad (_("Invalid dsp acc register"));
10883 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
10884 code) or 20 (for microMIPS code). */
10886 long mask = (mips_opts.micromips
10887 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
10889 my_getExpression (&imm_expr, s);
10890 check_absolute_expr (ip, &imm_expr);
10891 min_range = -((mask + 1) >> 1);
10892 max_range = ((mask + 1) >> 1) - 1;
10893 if (imm_expr.X_add_number < min_range
10894 || imm_expr.X_add_number > max_range)
10895 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10896 (long) min_range, (long) max_range,
10897 (long) imm_expr.X_add_number);
10898 INSERT_OPERAND (mips_opts.micromips,
10899 DSPSFT, *ip, imm_expr.X_add_number);
10900 imm_expr.X_op = O_absent;
10905 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10906 gas_assert (!mips_opts.micromips);
10907 my_getExpression (&imm_expr, s);
10908 check_absolute_expr (ip, &imm_expr);
10909 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10911 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10913 (unsigned long) imm_expr.X_add_number);
10915 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
10916 imm_expr.X_op = O_absent;
10920 case ':': /* DSP 7-bit signed immediate in bit 19. */
10921 gas_assert (!mips_opts.micromips);
10922 my_getExpression (&imm_expr, s);
10923 check_absolute_expr (ip, &imm_expr);
10924 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10925 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10926 if (imm_expr.X_add_number < min_range ||
10927 imm_expr.X_add_number > max_range)
10929 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10930 (long) min_range, (long) max_range,
10931 (long) imm_expr.X_add_number);
10933 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
10934 imm_expr.X_op = O_absent;
10938 case '@': /* DSP 10-bit signed immediate in bit 16. */
10940 long mask = (mips_opts.micromips
10941 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
10943 my_getExpression (&imm_expr, s);
10944 check_absolute_expr (ip, &imm_expr);
10945 min_range = -((mask + 1) >> 1);
10946 max_range = ((mask + 1) >> 1) - 1;
10947 if (imm_expr.X_add_number < min_range
10948 || imm_expr.X_add_number > max_range)
10949 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10950 (long) min_range, (long) max_range,
10951 (long) imm_expr.X_add_number);
10952 INSERT_OPERAND (mips_opts.micromips,
10953 IMM10, *ip, imm_expr.X_add_number);
10954 imm_expr.X_op = O_absent;
10959 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
10960 gas_assert (mips_opts.micromips);
10961 my_getExpression (&imm_expr, s);
10962 check_absolute_expr (ip, &imm_expr);
10963 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
10964 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10965 MICROMIPSOP_MASK_RD,
10966 (unsigned long) imm_expr.X_add_number);
10967 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
10968 imm_expr.X_op = O_absent;
10972 case '!': /* MT usermode flag bit. */
10973 gas_assert (!mips_opts.micromips);
10974 my_getExpression (&imm_expr, s);
10975 check_absolute_expr (ip, &imm_expr);
10976 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
10977 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10978 (unsigned long) imm_expr.X_add_number);
10979 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
10980 imm_expr.X_op = O_absent;
10984 case '$': /* MT load high flag bit. */
10985 gas_assert (!mips_opts.micromips);
10986 my_getExpression (&imm_expr, s);
10987 check_absolute_expr (ip, &imm_expr);
10988 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
10989 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10990 (unsigned long) imm_expr.X_add_number);
10991 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
10992 imm_expr.X_op = O_absent;
10996 case '*': /* Four DSP accumulators in bits 18,19. */
10997 gas_assert (!mips_opts.micromips);
10998 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10999 s[3] >= '0' && s[3] <= '3')
11001 regno = s[3] - '0';
11003 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11007 as_bad (_("Invalid dsp/smartmips acc register"));
11010 case '&': /* Four DSP accumulators in bits 13,14. */
11011 gas_assert (!mips_opts.micromips);
11012 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11013 s[3] >= '0' && s[3] <= '3')
11015 regno = s[3] - '0';
11017 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11021 as_bad (_("Invalid dsp/smartmips acc register"));
11024 case '\\': /* 3-bit bit position. */
11026 unsigned long mask = (mips_opts.micromips
11027 ? MICROMIPSOP_MASK_3BITPOS
11028 : OP_MASK_3BITPOS);
11030 my_getExpression (&imm_expr, s);
11031 check_absolute_expr (ip, &imm_expr);
11032 if ((unsigned long) imm_expr.X_add_number > mask)
11033 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11035 mask, (unsigned long) imm_expr.X_add_number);
11036 INSERT_OPERAND (mips_opts.micromips,
11037 3BITPOS, *ip, imm_expr.X_add_number);
11038 imm_expr.X_op = O_absent;
11052 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11056 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11060 gas_assert (!mips_opts.micromips);
11061 INSERT_OPERAND (0, FT, *ip, lastregno);
11065 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11071 /* Handle optional base register.
11072 Either the base register is omitted or
11073 we must have a left paren. */
11074 /* This is dependent on the next operand specifier
11075 is a base register specification. */
11076 gas_assert (args[1] == 'b'
11077 || (mips_opts.micromips
11079 && (args[2] == 'l' || args[2] == 'n'
11080 || args[2] == 's' || args[2] == 'a')));
11081 if (*s == '\0' && args[1] == 'b')
11083 /* Fall through. */
11085 case ')': /* These must match exactly. */
11090 case '[': /* These must match exactly. */
11092 gas_assert (!mips_opts.micromips);
11097 case '+': /* Opcode extension character. */
11100 case '1': /* UDI immediates. */
11104 gas_assert (!mips_opts.micromips);
11106 const struct mips_immed *imm = mips_immed;
11108 while (imm->type && imm->type != *args)
11112 my_getExpression (&imm_expr, s);
11113 check_absolute_expr (ip, &imm_expr);
11114 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11116 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11117 imm->desc ? imm->desc : ip->insn_mo->name,
11118 (unsigned long) imm_expr.X_add_number,
11119 (unsigned long) imm_expr.X_add_number);
11120 imm_expr.X_add_number &= imm->mask;
11122 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11124 imm_expr.X_op = O_absent;
11129 case 'A': /* ins/ext position, becomes LSB. */
11138 my_getExpression (&imm_expr, s);
11139 check_absolute_expr (ip, &imm_expr);
11140 if ((unsigned long) imm_expr.X_add_number < limlo
11141 || (unsigned long) imm_expr.X_add_number > limhi)
11143 as_bad (_("Improper position (%lu)"),
11144 (unsigned long) imm_expr.X_add_number);
11145 imm_expr.X_add_number = limlo;
11147 lastpos = imm_expr.X_add_number;
11148 INSERT_OPERAND (mips_opts.micromips,
11149 EXTLSB, *ip, imm_expr.X_add_number);
11150 imm_expr.X_op = O_absent;
11154 case 'B': /* ins size, becomes MSB. */
11163 my_getExpression (&imm_expr, s);
11164 check_absolute_expr (ip, &imm_expr);
11165 /* Check for negative input so that small negative numbers
11166 will not succeed incorrectly. The checks against
11167 (pos+size) transitively check "size" itself,
11168 assuming that "pos" is reasonable. */
11169 if ((long) imm_expr.X_add_number < 0
11170 || ((unsigned long) imm_expr.X_add_number
11172 || ((unsigned long) imm_expr.X_add_number
11173 + lastpos) > limhi)
11175 as_bad (_("Improper insert size (%lu, position %lu)"),
11176 (unsigned long) imm_expr.X_add_number,
11177 (unsigned long) lastpos);
11178 imm_expr.X_add_number = limlo - lastpos;
11180 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11181 lastpos + imm_expr.X_add_number - 1);
11182 imm_expr.X_op = O_absent;
11186 case 'C': /* ext size, becomes MSBD. */
11199 my_getExpression (&imm_expr, s);
11200 check_absolute_expr (ip, &imm_expr);
11201 /* Check for negative input so that small negative numbers
11202 will not succeed incorrectly. The checks against
11203 (pos+size) transitively check "size" itself,
11204 assuming that "pos" is reasonable. */
11205 if ((long) imm_expr.X_add_number < 0
11206 || ((unsigned long) imm_expr.X_add_number
11208 || ((unsigned long) imm_expr.X_add_number
11209 + lastpos) > limhi)
11211 as_bad (_("Improper extract size (%lu, position %lu)"),
11212 (unsigned long) imm_expr.X_add_number,
11213 (unsigned long) lastpos);
11214 imm_expr.X_add_number = limlo - lastpos;
11216 INSERT_OPERAND (mips_opts.micromips,
11217 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11218 imm_expr.X_op = O_absent;
11223 /* +D is for disassembly only; never match. */
11227 /* "+I" is like "I", except that imm2_expr is used. */
11228 my_getExpression (&imm2_expr, s);
11229 if (imm2_expr.X_op != O_big
11230 && imm2_expr.X_op != O_constant)
11231 insn_error = _("absolute expression required");
11232 if (HAVE_32BIT_GPRS)
11233 normalize_constant_expr (&imm2_expr);
11237 case 'T': /* Coprocessor register. */
11238 gas_assert (!mips_opts.micromips);
11239 /* +T is for disassembly only; never match. */
11242 case 't': /* Coprocessor register number. */
11243 gas_assert (!mips_opts.micromips);
11244 if (s[0] == '$' && ISDIGIT (s[1]))
11254 while (ISDIGIT (*s));
11256 as_bad (_("Invalid register number (%d)"), regno);
11259 INSERT_OPERAND (0, RT, *ip, regno);
11264 as_bad (_("Invalid coprocessor 0 register number"));
11268 /* bbit[01] and bbit[01]32 bit index. Give error if index
11269 is not in the valid range. */
11270 gas_assert (!mips_opts.micromips);
11271 my_getExpression (&imm_expr, s);
11272 check_absolute_expr (ip, &imm_expr);
11273 if ((unsigned) imm_expr.X_add_number > 31)
11275 as_bad (_("Improper bit index (%lu)"),
11276 (unsigned long) imm_expr.X_add_number);
11277 imm_expr.X_add_number = 0;
11279 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11280 imm_expr.X_op = O_absent;
11285 /* bbit[01] bit index when bbit is used but we generate
11286 bbit[01]32 because the index is over 32. Move to the
11287 next candidate if index is not in the valid range. */
11288 gas_assert (!mips_opts.micromips);
11289 my_getExpression (&imm_expr, s);
11290 check_absolute_expr (ip, &imm_expr);
11291 if ((unsigned) imm_expr.X_add_number < 32
11292 || (unsigned) imm_expr.X_add_number > 63)
11294 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11295 imm_expr.X_op = O_absent;
11300 /* cins, cins32, exts and exts32 position field. Give error
11301 if it's not in the valid range. */
11302 gas_assert (!mips_opts.micromips);
11303 my_getExpression (&imm_expr, s);
11304 check_absolute_expr (ip, &imm_expr);
11305 if ((unsigned) imm_expr.X_add_number > 31)
11307 as_bad (_("Improper position (%lu)"),
11308 (unsigned long) imm_expr.X_add_number);
11309 imm_expr.X_add_number = 0;
11311 /* Make the pos explicit to simplify +S. */
11312 lastpos = imm_expr.X_add_number + 32;
11313 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11314 imm_expr.X_op = O_absent;
11319 /* cins, cins32, exts and exts32 position field. Move to
11320 the next candidate if it's not in the valid range. */
11321 gas_assert (!mips_opts.micromips);
11322 my_getExpression (&imm_expr, s);
11323 check_absolute_expr (ip, &imm_expr);
11324 if ((unsigned) imm_expr.X_add_number < 32
11325 || (unsigned) imm_expr.X_add_number > 63)
11327 lastpos = imm_expr.X_add_number;
11328 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11329 imm_expr.X_op = O_absent;
11334 /* cins and exts length-minus-one field. */
11335 gas_assert (!mips_opts.micromips);
11336 my_getExpression (&imm_expr, s);
11337 check_absolute_expr (ip, &imm_expr);
11338 if ((unsigned long) imm_expr.X_add_number > 31)
11340 as_bad (_("Improper size (%lu)"),
11341 (unsigned long) imm_expr.X_add_number);
11342 imm_expr.X_add_number = 0;
11344 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11345 imm_expr.X_op = O_absent;
11350 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11351 length-minus-one field. */
11352 gas_assert (!mips_opts.micromips);
11353 my_getExpression (&imm_expr, s);
11354 check_absolute_expr (ip, &imm_expr);
11355 if ((long) imm_expr.X_add_number < 0
11356 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11358 as_bad (_("Improper size (%lu)"),
11359 (unsigned long) imm_expr.X_add_number);
11360 imm_expr.X_add_number = 0;
11362 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11363 imm_expr.X_op = O_absent;
11368 /* seqi/snei immediate field. */
11369 gas_assert (!mips_opts.micromips);
11370 my_getExpression (&imm_expr, s);
11371 check_absolute_expr (ip, &imm_expr);
11372 if ((long) imm_expr.X_add_number < -512
11373 || (long) imm_expr.X_add_number >= 512)
11375 as_bad (_("Improper immediate (%ld)"),
11376 (long) imm_expr.X_add_number);
11377 imm_expr.X_add_number = 0;
11379 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11380 imm_expr.X_op = O_absent;
11384 case 'a': /* 8-bit signed offset in bit 6 */
11385 gas_assert (!mips_opts.micromips);
11386 my_getExpression (&imm_expr, s);
11387 check_absolute_expr (ip, &imm_expr);
11388 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11389 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11390 if (imm_expr.X_add_number < min_range
11391 || imm_expr.X_add_number > max_range)
11393 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11394 (long) min_range, (long) max_range,
11395 (long) imm_expr.X_add_number);
11397 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11398 imm_expr.X_op = O_absent;
11402 case 'b': /* 8-bit signed offset in bit 3 */
11403 gas_assert (!mips_opts.micromips);
11404 my_getExpression (&imm_expr, s);
11405 check_absolute_expr (ip, &imm_expr);
11406 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11407 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11408 if (imm_expr.X_add_number < min_range
11409 || imm_expr.X_add_number > max_range)
11411 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11412 (long) min_range, (long) max_range,
11413 (long) imm_expr.X_add_number);
11415 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11416 imm_expr.X_op = O_absent;
11420 case 'c': /* 9-bit signed offset in bit 6 */
11421 gas_assert (!mips_opts.micromips);
11422 my_getExpression (&imm_expr, s);
11423 check_absolute_expr (ip, &imm_expr);
11424 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11425 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11426 /* We check the offset range before adjusted. */
11429 if (imm_expr.X_add_number < min_range
11430 || imm_expr.X_add_number > max_range)
11432 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11433 (long) min_range, (long) max_range,
11434 (long) imm_expr.X_add_number);
11436 if (imm_expr.X_add_number & 0xf)
11438 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11439 (long) imm_expr.X_add_number);
11441 /* Right shift 4 bits to adjust the offset operand. */
11442 INSERT_OPERAND (0, OFFSET_C, *ip,
11443 imm_expr.X_add_number >> 4);
11444 imm_expr.X_op = O_absent;
11449 gas_assert (!mips_opts.micromips);
11450 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11452 if (regno == AT && mips_opts.at)
11454 if (mips_opts.at == ATREG)
11455 as_warn (_("used $at without \".set noat\""));
11457 as_warn (_("used $%u with \".set at=$%u\""),
11458 regno, mips_opts.at);
11460 INSERT_OPERAND (0, RZ, *ip, regno);
11464 gas_assert (!mips_opts.micromips);
11465 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11467 INSERT_OPERAND (0, FZ, *ip, regno);
11471 as_bad (_("Internal error: bad %s opcode "
11472 "(unknown extension operand type `+%c'): %s %s"),
11473 mips_opts.micromips ? "microMIPS" : "MIPS",
11474 *args, insn->name, insn->args);
11475 /* Further processing is fruitless. */
11480 case '.': /* 10-bit offset. */
11481 gas_assert (mips_opts.micromips);
11482 case '~': /* 12-bit offset. */
11484 int shift = *args == '.' ? 9 : 11;
11487 /* Check whether there is only a single bracketed expression
11488 left. If so, it must be the base register and the
11489 constant must be zero. */
11490 if (*s == '(' && strchr (s + 1, '(') == 0)
11493 /* If this value won't fit into the offset, then go find
11494 a macro that will generate a 16- or 32-bit offset code
11496 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11497 if ((i == 0 && (imm_expr.X_op != O_constant
11498 || imm_expr.X_add_number >= 1 << shift
11499 || imm_expr.X_add_number < -1 << shift))
11502 imm_expr.X_op = O_absent;
11506 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11508 INSERT_OPERAND (mips_opts.micromips,
11509 OFFSET12, *ip, imm_expr.X_add_number);
11510 imm_expr.X_op = O_absent;
11515 case '<': /* must be at least one digit */
11517 * According to the manual, if the shift amount is greater
11518 * than 31 or less than 0, then the shift amount should be
11519 * mod 32. In reality the mips assembler issues an error.
11520 * We issue a warning and mask out all but the low 5 bits.
11522 my_getExpression (&imm_expr, s);
11523 check_absolute_expr (ip, &imm_expr);
11524 if ((unsigned long) imm_expr.X_add_number > 31)
11525 as_warn (_("Improper shift amount (%lu)"),
11526 (unsigned long) imm_expr.X_add_number);
11527 INSERT_OPERAND (mips_opts.micromips,
11528 SHAMT, *ip, imm_expr.X_add_number);
11529 imm_expr.X_op = O_absent;
11533 case '>': /* shift amount minus 32 */
11534 my_getExpression (&imm_expr, s);
11535 check_absolute_expr (ip, &imm_expr);
11536 if ((unsigned long) imm_expr.X_add_number < 32
11537 || (unsigned long) imm_expr.X_add_number > 63)
11539 INSERT_OPERAND (mips_opts.micromips,
11540 SHAMT, *ip, imm_expr.X_add_number - 32);
11541 imm_expr.X_op = O_absent;
11545 case 'k': /* CACHE code. */
11546 case 'h': /* PREFX code. */
11547 case '1': /* SYNC type. */
11548 my_getExpression (&imm_expr, s);
11549 check_absolute_expr (ip, &imm_expr);
11550 if ((unsigned long) imm_expr.X_add_number > 31)
11551 as_warn (_("Invalid value for `%s' (%lu)"),
11553 (unsigned long) imm_expr.X_add_number);
11557 if (mips_fix_cn63xxp1
11558 && !mips_opts.micromips
11559 && strcmp ("pref", insn->name) == 0)
11560 switch (imm_expr.X_add_number)
11569 case 31: /* These are ok. */
11572 default: /* The rest must be changed to 28. */
11573 imm_expr.X_add_number = 28;
11576 INSERT_OPERAND (mips_opts.micromips,
11577 CACHE, *ip, imm_expr.X_add_number);
11580 INSERT_OPERAND (mips_opts.micromips,
11581 PREFX, *ip, imm_expr.X_add_number);
11584 INSERT_OPERAND (mips_opts.micromips,
11585 STYPE, *ip, imm_expr.X_add_number);
11588 imm_expr.X_op = O_absent;
11592 case 'c': /* BREAK code. */
11594 unsigned long mask = (mips_opts.micromips
11595 ? MICROMIPSOP_MASK_CODE
11598 my_getExpression (&imm_expr, s);
11599 check_absolute_expr (ip, &imm_expr);
11600 if ((unsigned long) imm_expr.X_add_number > mask)
11601 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11603 mask, (unsigned long) imm_expr.X_add_number);
11604 INSERT_OPERAND (mips_opts.micromips,
11605 CODE, *ip, imm_expr.X_add_number);
11606 imm_expr.X_op = O_absent;
11611 case 'q': /* Lower BREAK code. */
11613 unsigned long mask = (mips_opts.micromips
11614 ? MICROMIPSOP_MASK_CODE2
11617 my_getExpression (&imm_expr, s);
11618 check_absolute_expr (ip, &imm_expr);
11619 if ((unsigned long) imm_expr.X_add_number > mask)
11620 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11622 mask, (unsigned long) imm_expr.X_add_number);
11623 INSERT_OPERAND (mips_opts.micromips,
11624 CODE2, *ip, imm_expr.X_add_number);
11625 imm_expr.X_op = O_absent;
11630 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11632 unsigned long mask = (mips_opts.micromips
11633 ? MICROMIPSOP_MASK_CODE10
11636 my_getExpression (&imm_expr, s);
11637 check_absolute_expr (ip, &imm_expr);
11638 if ((unsigned long) imm_expr.X_add_number > mask)
11639 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11641 mask, (unsigned long) imm_expr.X_add_number);
11642 if (mips_opts.micromips)
11643 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11645 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11646 imm_expr.X_op = O_absent;
11651 case 'C': /* 25- or 23-bit coprocessor code. */
11653 unsigned long mask = (mips_opts.micromips
11654 ? MICROMIPSOP_MASK_COPZ
11657 my_getExpression (&imm_expr, s);
11658 check_absolute_expr (ip, &imm_expr);
11659 if ((unsigned long) imm_expr.X_add_number > mask)
11660 as_warn (_("Coproccesor code > %u bits (%lu)"),
11661 mips_opts.micromips ? 23U : 25U,
11662 (unsigned long) imm_expr.X_add_number);
11663 INSERT_OPERAND (mips_opts.micromips,
11664 COPZ, *ip, imm_expr.X_add_number);
11665 imm_expr.X_op = O_absent;
11670 case 'J': /* 19-bit WAIT code. */
11671 gas_assert (!mips_opts.micromips);
11672 my_getExpression (&imm_expr, s);
11673 check_absolute_expr (ip, &imm_expr);
11674 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11676 as_warn (_("Illegal 19-bit code (%lu)"),
11677 (unsigned long) imm_expr.X_add_number);
11678 imm_expr.X_add_number &= OP_MASK_CODE19;
11680 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11681 imm_expr.X_op = O_absent;
11685 case 'P': /* Performance register. */
11686 gas_assert (!mips_opts.micromips);
11687 my_getExpression (&imm_expr, s);
11688 check_absolute_expr (ip, &imm_expr);
11689 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11690 as_warn (_("Invalid performance register (%lu)"),
11691 (unsigned long) imm_expr.X_add_number);
11692 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11693 imm_expr.X_op = O_absent;
11697 case 'G': /* Coprocessor destination register. */
11699 unsigned long opcode = ip->insn_opcode;
11700 unsigned long mask;
11701 unsigned int types;
11704 if (mips_opts.micromips)
11706 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11707 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11708 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11712 case 0x000000fc: /* mfc0 */
11713 case 0x000002fc: /* mtc0 */
11714 case 0x580000fc: /* dmfc0 */
11715 case 0x580002fc: /* dmtc0 */
11725 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11726 cop0 = opcode == OP_OP_COP0;
11728 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11729 ok = reg_lookup (&s, types, ®no);
11730 if (mips_opts.micromips)
11731 INSERT_OPERAND (1, RS, *ip, regno);
11733 INSERT_OPERAND (0, RD, *ip, regno);
11742 case 'y': /* ALNV.PS source register. */
11743 gas_assert (mips_opts.micromips);
11745 case 'x': /* Ignore register name. */
11746 case 'U': /* Destination register (CLO/CLZ). */
11747 case 'g': /* Coprocessor destination register. */
11748 gas_assert (!mips_opts.micromips);
11749 case 'b': /* Base register. */
11750 case 'd': /* Destination register. */
11751 case 's': /* Source register. */
11752 case 't': /* Target register. */
11753 case 'r': /* Both target and source. */
11754 case 'v': /* Both dest and source. */
11755 case 'w': /* Both dest and target. */
11756 case 'E': /* Coprocessor target register. */
11757 case 'K': /* RDHWR destination register. */
11758 case 'z': /* Must be zero register. */
11761 if (*args == 'E' || *args == 'K')
11762 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11765 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11766 if (regno == AT && mips_opts.at)
11768 if (mips_opts.at == ATREG)
11769 as_warn (_("Used $at without \".set noat\""));
11771 as_warn (_("Used $%u with \".set at=$%u\""),
11772 regno, mips_opts.at);
11782 if (c == 'r' || c == 'v' || c == 'w')
11789 /* 'z' only matches $0. */
11790 if (c == 'z' && regno != 0)
11793 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11795 if (regno == lastregno)
11798 = _("Source and destination must be different");
11801 if (regno == 31 && lastregno == 0xffffffff)
11804 = _("A destination register must be supplied");
11808 /* Now that we have assembled one operand, we use the args
11809 string to figure out where it goes in the instruction. */
11816 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11820 if (mips_opts.micromips)
11821 INSERT_OPERAND (1, RS, *ip, regno);
11823 INSERT_OPERAND (0, RD, *ip, regno);
11828 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11832 gas_assert (!mips_opts.micromips);
11833 INSERT_OPERAND (0, RD, *ip, regno);
11834 INSERT_OPERAND (0, RT, *ip, regno);
11840 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11844 gas_assert (mips_opts.micromips);
11845 INSERT_OPERAND (1, RS3, *ip, regno);
11849 /* This case exists because on the r3000 trunc
11850 expands into a macro which requires a gp
11851 register. On the r6000 or r4000 it is
11852 assembled into a single instruction which
11853 ignores the register. Thus the insn version
11854 is MIPS_ISA2 and uses 'x', and the macro
11855 version is MIPS_ISA1 and uses 't'. */
11859 /* This case is for the div instruction, which
11860 acts differently if the destination argument
11861 is $0. This only matches $0, and is checked
11862 outside the switch. */
11872 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11876 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11881 case 'O': /* MDMX alignment immediate constant. */
11882 gas_assert (!mips_opts.micromips);
11883 my_getExpression (&imm_expr, s);
11884 check_absolute_expr (ip, &imm_expr);
11885 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11886 as_warn (_("Improper align amount (%ld), using low bits"),
11887 (long) imm_expr.X_add_number);
11888 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11889 imm_expr.X_op = O_absent;
11893 case 'Q': /* MDMX vector, element sel, or const. */
11896 /* MDMX Immediate. */
11897 gas_assert (!mips_opts.micromips);
11898 my_getExpression (&imm_expr, s);
11899 check_absolute_expr (ip, &imm_expr);
11900 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
11901 as_warn (_("Invalid MDMX Immediate (%ld)"),
11902 (long) imm_expr.X_add_number);
11903 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
11904 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11905 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11907 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
11908 imm_expr.X_op = O_absent;
11912 /* Not MDMX Immediate. Fall through. */
11913 case 'X': /* MDMX destination register. */
11914 case 'Y': /* MDMX source register. */
11915 case 'Z': /* MDMX target register. */
11918 gas_assert (!mips_opts.micromips);
11919 case 'D': /* Floating point destination register. */
11920 case 'S': /* Floating point source register. */
11921 case 'T': /* Floating point target register. */
11922 case 'R': /* Floating point source register. */
11926 || (mips_opts.ase_mdmx
11927 && (ip->insn_mo->pinfo & FP_D)
11928 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11929 | INSN_COPROC_MEMORY_DELAY
11930 | INSN_LOAD_COPROC_DELAY
11931 | INSN_LOAD_MEMORY_DELAY
11932 | INSN_STORE_MEMORY))))
11933 rtype |= RTYPE_VEC;
11935 if (reg_lookup (&s, rtype, ®no))
11937 if ((regno & 1) != 0
11939 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
11940 as_warn (_("Float register should be even, was %d"),
11948 if (c == 'V' || c == 'W')
11959 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
11965 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
11969 /* This is like 'Z', but also needs to fix the MDMX
11970 vector/scalar select bits. Note that the
11971 scalar immediate case is handled above. */
11974 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
11975 int max_el = (is_qh ? 3 : 7);
11977 my_getExpression(&imm_expr, s);
11978 check_absolute_expr (ip, &imm_expr);
11980 if (imm_expr.X_add_number > max_el)
11981 as_bad (_("Bad element selector %ld"),
11982 (long) imm_expr.X_add_number);
11983 imm_expr.X_add_number &= max_el;
11984 ip->insn_opcode |= (imm_expr.X_add_number
11987 imm_expr.X_op = O_absent;
11989 as_warn (_("Expecting ']' found '%s'"), s);
11995 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11996 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
11999 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12002 /* Fall through. */
12006 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12010 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12020 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12024 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12030 my_getExpression (&imm_expr, s);
12031 if (imm_expr.X_op != O_big
12032 && imm_expr.X_op != O_constant)
12033 insn_error = _("absolute expression required");
12034 if (HAVE_32BIT_GPRS)
12035 normalize_constant_expr (&imm_expr);
12040 my_getExpression (&offset_expr, s);
12041 normalize_address_expr (&offset_expr);
12042 *imm_reloc = BFD_RELOC_32;
12055 unsigned char temp[8];
12057 unsigned int length;
12062 /* These only appear as the last operand in an
12063 instruction, and every instruction that accepts
12064 them in any variant accepts them in all variants.
12065 This means we don't have to worry about backing out
12066 any changes if the instruction does not match.
12068 The difference between them is the size of the
12069 floating point constant and where it goes. For 'F'
12070 and 'L' the constant is 64 bits; for 'f' and 'l' it
12071 is 32 bits. Where the constant is placed is based
12072 on how the MIPS assembler does things:
12075 f -- immediate value
12078 The .lit4 and .lit8 sections are only used if
12079 permitted by the -G argument.
12081 The code below needs to know whether the target register
12082 is 32 or 64 bits wide. It relies on the fact 'f' and
12083 'F' are used with GPR-based instructions and 'l' and
12084 'L' are used with FPR-based instructions. */
12086 f64 = *args == 'F' || *args == 'L';
12087 using_gprs = *args == 'F' || *args == 'f';
12089 save_in = input_line_pointer;
12090 input_line_pointer = s;
12091 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12093 s = input_line_pointer;
12094 input_line_pointer = save_in;
12095 if (err != NULL && *err != '\0')
12097 as_bad (_("Bad floating point constant: %s"), err);
12098 memset (temp, '\0', sizeof temp);
12099 length = f64 ? 8 : 4;
12102 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12106 && (g_switch_value < 4
12107 || (temp[0] == 0 && temp[1] == 0)
12108 || (temp[2] == 0 && temp[3] == 0))))
12110 imm_expr.X_op = O_constant;
12111 if (!target_big_endian)
12112 imm_expr.X_add_number = bfd_getl32 (temp);
12114 imm_expr.X_add_number = bfd_getb32 (temp);
12116 else if (length > 4
12117 && !mips_disable_float_construction
12118 /* Constants can only be constructed in GPRs and
12119 copied to FPRs if the GPRs are at least as wide
12120 as the FPRs. Force the constant into memory if
12121 we are using 64-bit FPRs but the GPRs are only
12124 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12125 && ((temp[0] == 0 && temp[1] == 0)
12126 || (temp[2] == 0 && temp[3] == 0))
12127 && ((temp[4] == 0 && temp[5] == 0)
12128 || (temp[6] == 0 && temp[7] == 0)))
12130 /* The value is simple enough to load with a couple of
12131 instructions. If using 32-bit registers, set
12132 imm_expr to the high order 32 bits and offset_expr to
12133 the low order 32 bits. Otherwise, set imm_expr to
12134 the entire 64 bit constant. */
12135 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12137 imm_expr.X_op = O_constant;
12138 offset_expr.X_op = O_constant;
12139 if (!target_big_endian)
12141 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12142 offset_expr.X_add_number = bfd_getl32 (temp);
12146 imm_expr.X_add_number = bfd_getb32 (temp);
12147 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12149 if (offset_expr.X_add_number == 0)
12150 offset_expr.X_op = O_absent;
12152 else if (sizeof (imm_expr.X_add_number) > 4)
12154 imm_expr.X_op = O_constant;
12155 if (!target_big_endian)
12156 imm_expr.X_add_number = bfd_getl64 (temp);
12158 imm_expr.X_add_number = bfd_getb64 (temp);
12162 imm_expr.X_op = O_big;
12163 imm_expr.X_add_number = 4;
12164 if (!target_big_endian)
12166 generic_bignum[0] = bfd_getl16 (temp);
12167 generic_bignum[1] = bfd_getl16 (temp + 2);
12168 generic_bignum[2] = bfd_getl16 (temp + 4);
12169 generic_bignum[3] = bfd_getl16 (temp + 6);
12173 generic_bignum[0] = bfd_getb16 (temp + 6);
12174 generic_bignum[1] = bfd_getb16 (temp + 4);
12175 generic_bignum[2] = bfd_getb16 (temp + 2);
12176 generic_bignum[3] = bfd_getb16 (temp);
12182 const char *newname;
12185 /* Switch to the right section. */
12187 subseg = now_subseg;
12190 default: /* unused default case avoids warnings. */
12192 newname = RDATA_SECTION_NAME;
12193 if (g_switch_value >= 8)
12197 newname = RDATA_SECTION_NAME;
12200 gas_assert (g_switch_value >= 4);
12204 new_seg = subseg_new (newname, (subsegT) 0);
12206 bfd_set_section_flags (stdoutput, new_seg,
12211 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12212 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12213 record_alignment (new_seg, 4);
12215 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12216 if (seg == now_seg)
12217 as_bad (_("Can't use floating point insn in this section"));
12219 /* Set the argument to the current address in the
12221 offset_expr.X_op = O_symbol;
12222 offset_expr.X_add_symbol = symbol_temp_new_now ();
12223 offset_expr.X_add_number = 0;
12225 /* Put the floating point number into the section. */
12226 p = frag_more ((int) length);
12227 memcpy (p, temp, length);
12229 /* Switch back to the original section. */
12230 subseg_set (seg, subseg);
12235 case 'i': /* 16-bit unsigned immediate. */
12236 case 'j': /* 16-bit signed immediate. */
12237 *imm_reloc = BFD_RELOC_LO16;
12238 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12241 offsetT minval, maxval;
12243 more = (insn + 1 < past
12244 && strcmp (insn->name, insn[1].name) == 0);
12246 /* If the expression was written as an unsigned number,
12247 only treat it as signed if there are no more
12251 && sizeof (imm_expr.X_add_number) <= 4
12252 && imm_expr.X_op == O_constant
12253 && imm_expr.X_add_number < 0
12254 && imm_expr.X_unsigned
12255 && HAVE_64BIT_GPRS)
12258 /* For compatibility with older assemblers, we accept
12259 0x8000-0xffff as signed 16-bit numbers when only
12260 signed numbers are allowed. */
12262 minval = 0, maxval = 0xffff;
12264 minval = -0x8000, maxval = 0x7fff;
12266 minval = -0x8000, maxval = 0xffff;
12268 if (imm_expr.X_op != O_constant
12269 || imm_expr.X_add_number < minval
12270 || imm_expr.X_add_number > maxval)
12274 if (imm_expr.X_op == O_constant
12275 || imm_expr.X_op == O_big)
12276 as_bad (_("Expression out of range"));
12282 case 'o': /* 16-bit offset. */
12283 offset_reloc[0] = BFD_RELOC_LO16;
12284 offset_reloc[1] = BFD_RELOC_UNUSED;
12285 offset_reloc[2] = BFD_RELOC_UNUSED;
12287 /* Check whether there is only a single bracketed expression
12288 left. If so, it must be the base register and the
12289 constant must be zero. */
12290 if (*s == '(' && strchr (s + 1, '(') == 0)
12292 offset_expr.X_op = O_constant;
12293 offset_expr.X_add_number = 0;
12297 /* If this value won't fit into a 16 bit offset, then go
12298 find a macro that will generate the 32 bit offset
12300 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12301 && (offset_expr.X_op != O_constant
12302 || offset_expr.X_add_number >= 0x8000
12303 || offset_expr.X_add_number < -0x8000))
12309 case 'p': /* PC-relative offset. */
12310 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12311 my_getExpression (&offset_expr, s);
12315 case 'u': /* Upper 16 bits. */
12316 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12317 && imm_expr.X_op == O_constant
12318 && (imm_expr.X_add_number < 0
12319 || imm_expr.X_add_number >= 0x10000))
12320 as_bad (_("lui expression (%lu) not in range 0..65535"),
12321 (unsigned long) imm_expr.X_add_number);
12325 case 'a': /* 26-bit address. */
12326 *offset_reloc = BFD_RELOC_MIPS_JMP;
12327 my_getExpression (&offset_expr, s);
12331 case 'N': /* 3-bit branch condition code. */
12332 case 'M': /* 3-bit compare condition code. */
12334 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12335 rtype |= RTYPE_FCC;
12336 if (!reg_lookup (&s, rtype, ®no))
12338 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12339 || strcmp (str + strlen (str) - 5, "any2f") == 0
12340 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12341 && (regno & 1) != 0)
12342 as_warn (_("Condition code register should be even for %s, "
12345 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12346 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12347 && (regno & 3) != 0)
12348 as_warn (_("Condition code register should be 0 or 4 for %s, "
12352 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12354 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12358 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12369 while (ISDIGIT (*s));
12372 c = 8; /* Invalid sel value. */
12375 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12376 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12380 gas_assert (!mips_opts.micromips);
12381 /* Must be at least one digit. */
12382 my_getExpression (&imm_expr, s);
12383 check_absolute_expr (ip, &imm_expr);
12385 if ((unsigned long) imm_expr.X_add_number
12386 > (unsigned long) OP_MASK_VECBYTE)
12388 as_bad (_("bad byte vector index (%ld)"),
12389 (long) imm_expr.X_add_number);
12390 imm_expr.X_add_number = 0;
12393 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12394 imm_expr.X_op = O_absent;
12399 gas_assert (!mips_opts.micromips);
12400 my_getExpression (&imm_expr, s);
12401 check_absolute_expr (ip, &imm_expr);
12403 if ((unsigned long) imm_expr.X_add_number
12404 > (unsigned long) OP_MASK_VECALIGN)
12406 as_bad (_("bad byte vector index (%ld)"),
12407 (long) imm_expr.X_add_number);
12408 imm_expr.X_add_number = 0;
12411 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12412 imm_expr.X_op = O_absent;
12416 case 'm': /* Opcode extension character. */
12417 gas_assert (mips_opts.micromips);
12422 if (strncmp (s, "$pc", 3) == 0)
12450 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12451 if (regno == AT && mips_opts.at)
12453 if (mips_opts.at == ATREG)
12454 as_warn (_("Used $at without \".set noat\""));
12456 as_warn (_("Used $%u with \".set at=$%u\""),
12457 regno, mips_opts.at);
12463 gas_assert (args[1] == ',');
12469 gas_assert (args[1] == ',');
12471 continue; /* Nothing to do. */
12477 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12479 if (regno == lastregno)
12482 = _("Source and destination must be different");
12485 if (regno == 31 && lastregno == 0xffffffff)
12488 = _("A destination register must be supplied");
12499 gas_assert (args[1] == ',');
12506 gas_assert (args[1] == ',');
12509 continue; /* Nothing to do. */
12513 /* Make sure regno is the same as lastregno. */
12514 if (c == 't' && regno != lastregno)
12517 /* Make sure regno is the same as destregno. */
12518 if (c == 'x' && regno != destregno)
12521 /* We need to save regno, before regno maps to the
12522 microMIPS register encoding. */
12532 regno = ILLEGAL_REG;
12536 regno = mips32_to_micromips_reg_b_map[regno];
12540 regno = mips32_to_micromips_reg_c_map[regno];
12544 regno = mips32_to_micromips_reg_d_map[regno];
12548 regno = mips32_to_micromips_reg_e_map[regno];
12552 regno = mips32_to_micromips_reg_f_map[regno];
12556 regno = mips32_to_micromips_reg_g_map[regno];
12560 regno = mips32_to_micromips_reg_h_map[regno];
12564 switch (EXTRACT_OPERAND (1, MI, *ip))
12569 else if (regno == 22)
12571 else if (regno == 5)
12573 else if (regno == 6)
12575 else if (regno == 7)
12578 regno = ILLEGAL_REG;
12584 else if (regno == 7)
12587 regno = ILLEGAL_REG;
12594 regno = ILLEGAL_REG;
12598 regno = ILLEGAL_REG;
12604 regno = mips32_to_micromips_reg_l_map[regno];
12608 regno = mips32_to_micromips_reg_m_map[regno];
12612 regno = mips32_to_micromips_reg_n_map[regno];
12616 regno = mips32_to_micromips_reg_q_map[regno];
12621 regno = ILLEGAL_REG;
12626 regno = ILLEGAL_REG;
12631 regno = ILLEGAL_REG;
12634 case 'j': /* Do nothing. */
12644 if (regno == ILLEGAL_REG)
12650 INSERT_OPERAND (1, MB, *ip, regno);
12654 INSERT_OPERAND (1, MC, *ip, regno);
12658 INSERT_OPERAND (1, MD, *ip, regno);
12662 INSERT_OPERAND (1, ME, *ip, regno);
12666 INSERT_OPERAND (1, MF, *ip, regno);
12670 INSERT_OPERAND (1, MG, *ip, regno);
12674 INSERT_OPERAND (1, MH, *ip, regno);
12678 INSERT_OPERAND (1, MI, *ip, regno);
12682 INSERT_OPERAND (1, MJ, *ip, regno);
12686 INSERT_OPERAND (1, ML, *ip, regno);
12690 INSERT_OPERAND (1, MM, *ip, regno);
12694 INSERT_OPERAND (1, MN, *ip, regno);
12698 INSERT_OPERAND (1, MP, *ip, regno);
12702 INSERT_OPERAND (1, MQ, *ip, regno);
12705 case 'a': /* Do nothing. */
12706 case 's': /* Do nothing. */
12707 case 't': /* Do nothing. */
12708 case 'x': /* Do nothing. */
12709 case 'y': /* Do nothing. */
12710 case 'z': /* Do nothing. */
12720 bfd_reloc_code_real_type r[3];
12724 /* Check whether there is only a single bracketed
12725 expression left. If so, it must be the base register
12726 and the constant must be zero. */
12727 if (*s == '(' && strchr (s + 1, '(') == 0)
12729 INSERT_OPERAND (1, IMMA, *ip, 0);
12733 if (my_getSmallExpression (&ep, r, s) > 0
12734 || !expr_const_in_range (&ep, -64, 64, 2))
12737 imm = ep.X_add_number >> 2;
12738 INSERT_OPERAND (1, IMMA, *ip, imm);
12745 bfd_reloc_code_real_type r[3];
12749 if (my_getSmallExpression (&ep, r, s) > 0
12750 || ep.X_op != O_constant)
12753 for (imm = 0; imm < 8; imm++)
12754 if (micromips_imm_b_map[imm] == ep.X_add_number)
12759 INSERT_OPERAND (1, IMMB, *ip, imm);
12766 bfd_reloc_code_real_type r[3];
12770 if (my_getSmallExpression (&ep, r, s) > 0
12771 || ep.X_op != O_constant)
12774 for (imm = 0; imm < 16; imm++)
12775 if (micromips_imm_c_map[imm] == ep.X_add_number)
12780 INSERT_OPERAND (1, IMMC, *ip, imm);
12785 case 'D': /* pc relative offset */
12786 case 'E': /* pc relative offset */
12787 my_getExpression (&offset_expr, s);
12788 if (offset_expr.X_op == O_register)
12791 if (!forced_insn_length)
12792 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12794 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12796 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12802 bfd_reloc_code_real_type r[3];
12806 if (my_getSmallExpression (&ep, r, s) > 0
12807 || !expr_const_in_range (&ep, 0, 16, 0))
12810 imm = ep.X_add_number;
12811 INSERT_OPERAND (1, IMMF, *ip, imm);
12818 bfd_reloc_code_real_type r[3];
12822 /* Check whether there is only a single bracketed
12823 expression left. If so, it must be the base register
12824 and the constant must be zero. */
12825 if (*s == '(' && strchr (s + 1, '(') == 0)
12827 INSERT_OPERAND (1, IMMG, *ip, 0);
12831 if (my_getSmallExpression (&ep, r, s) > 0
12832 || !expr_const_in_range (&ep, -1, 15, 0))
12835 imm = ep.X_add_number & 15;
12836 INSERT_OPERAND (1, IMMG, *ip, imm);
12843 bfd_reloc_code_real_type r[3];
12847 /* Check whether there is only a single bracketed
12848 expression left. If so, it must be the base register
12849 and the constant must be zero. */
12850 if (*s == '(' && strchr (s + 1, '(') == 0)
12852 INSERT_OPERAND (1, IMMH, *ip, 0);
12856 if (my_getSmallExpression (&ep, r, s) > 0
12857 || !expr_const_in_range (&ep, 0, 16, 1))
12860 imm = ep.X_add_number >> 1;
12861 INSERT_OPERAND (1, IMMH, *ip, imm);
12868 bfd_reloc_code_real_type r[3];
12872 if (my_getSmallExpression (&ep, r, s) > 0
12873 || !expr_const_in_range (&ep, -1, 127, 0))
12876 imm = ep.X_add_number & 127;
12877 INSERT_OPERAND (1, IMMI, *ip, imm);
12884 bfd_reloc_code_real_type r[3];
12888 /* Check whether there is only a single bracketed
12889 expression left. If so, it must be the base register
12890 and the constant must be zero. */
12891 if (*s == '(' && strchr (s + 1, '(') == 0)
12893 INSERT_OPERAND (1, IMMJ, *ip, 0);
12897 if (my_getSmallExpression (&ep, r, s) > 0
12898 || !expr_const_in_range (&ep, 0, 16, 2))
12901 imm = ep.X_add_number >> 2;
12902 INSERT_OPERAND (1, IMMJ, *ip, imm);
12909 bfd_reloc_code_real_type r[3];
12913 /* Check whether there is only a single bracketed
12914 expression left. If so, it must be the base register
12915 and the constant must be zero. */
12916 if (*s == '(' && strchr (s + 1, '(') == 0)
12918 INSERT_OPERAND (1, IMML, *ip, 0);
12922 if (my_getSmallExpression (&ep, r, s) > 0
12923 || !expr_const_in_range (&ep, 0, 16, 0))
12926 imm = ep.X_add_number;
12927 INSERT_OPERAND (1, IMML, *ip, imm);
12934 bfd_reloc_code_real_type r[3];
12938 if (my_getSmallExpression (&ep, r, s) > 0
12939 || !expr_const_in_range (&ep, 1, 9, 0))
12942 imm = ep.X_add_number & 7;
12943 INSERT_OPERAND (1, IMMM, *ip, imm);
12948 case 'N': /* Register list for lwm and swm. */
12950 /* A comma-separated list of registers and/or
12951 dash-separated contiguous ranges including
12952 both ra and a set of one or more registers
12953 starting at s0 up to s3 which have to be
12960 and any permutations of these. */
12961 unsigned int reglist;
12964 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
12967 if ((reglist & 0xfff1ffff) != 0x80010000)
12970 reglist = (reglist >> 17) & 7;
12972 if ((reglist & -reglist) != reglist)
12975 imm = ffs (reglist) - 1;
12976 INSERT_OPERAND (1, IMMN, *ip, imm);
12980 case 'O': /* sdbbp 4-bit code. */
12982 bfd_reloc_code_real_type r[3];
12986 if (my_getSmallExpression (&ep, r, s) > 0
12987 || !expr_const_in_range (&ep, 0, 16, 0))
12990 imm = ep.X_add_number;
12991 INSERT_OPERAND (1, IMMO, *ip, imm);
12998 bfd_reloc_code_real_type r[3];
13002 if (my_getSmallExpression (&ep, r, s) > 0
13003 || !expr_const_in_range (&ep, 0, 32, 2))
13006 imm = ep.X_add_number >> 2;
13007 INSERT_OPERAND (1, IMMP, *ip, imm);
13014 bfd_reloc_code_real_type r[3];
13018 if (my_getSmallExpression (&ep, r, s) > 0
13019 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13022 imm = ep.X_add_number >> 2;
13023 INSERT_OPERAND (1, IMMQ, *ip, imm);
13030 bfd_reloc_code_real_type r[3];
13034 /* Check whether there is only a single bracketed
13035 expression left. If so, it must be the base register
13036 and the constant must be zero. */
13037 if (*s == '(' && strchr (s + 1, '(') == 0)
13039 INSERT_OPERAND (1, IMMU, *ip, 0);
13043 if (my_getSmallExpression (&ep, r, s) > 0
13044 || !expr_const_in_range (&ep, 0, 32, 2))
13047 imm = ep.X_add_number >> 2;
13048 INSERT_OPERAND (1, IMMU, *ip, imm);
13055 bfd_reloc_code_real_type r[3];
13059 if (my_getSmallExpression (&ep, r, s) > 0
13060 || !expr_const_in_range (&ep, 0, 64, 2))
13063 imm = ep.X_add_number >> 2;
13064 INSERT_OPERAND (1, IMMW, *ip, imm);
13071 bfd_reloc_code_real_type r[3];
13075 if (my_getSmallExpression (&ep, r, s) > 0
13076 || !expr_const_in_range (&ep, -8, 8, 0))
13079 imm = ep.X_add_number;
13080 INSERT_OPERAND (1, IMMX, *ip, imm);
13087 bfd_reloc_code_real_type r[3];
13091 if (my_getSmallExpression (&ep, r, s) > 0
13092 || expr_const_in_range (&ep, -2, 2, 2)
13093 || !expr_const_in_range (&ep, -258, 258, 2))
13096 imm = ep.X_add_number >> 2;
13097 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13098 INSERT_OPERAND (1, IMMY, *ip, imm);
13105 bfd_reloc_code_real_type r[3];
13108 if (my_getSmallExpression (&ep, r, s) > 0
13109 || !expr_const_in_range (&ep, 0, 1, 0))
13116 as_bad (_("Internal error: bad microMIPS opcode "
13117 "(unknown extension operand type `m%c'): %s %s"),
13118 *args, insn->name, insn->args);
13119 /* Further processing is fruitless. */
13124 case 'n': /* Register list for 32-bit lwm and swm. */
13125 gas_assert (mips_opts.micromips);
13127 /* A comma-separated list of registers and/or
13128 dash-separated contiguous ranges including
13129 at least one of ra and a set of one or more
13130 registers starting at s0 up to s7 and then
13131 s8 which have to be consecutive, e.g.:
13139 and any permutations of these. */
13140 unsigned int reglist;
13144 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13147 if ((reglist & 0x3f00ffff) != 0)
13150 ra = (reglist >> 27) & 0x10;
13151 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13153 if ((reglist & -reglist) != reglist)
13156 imm = (ffs (reglist) - 1) | ra;
13157 INSERT_OPERAND (1, RT, *ip, imm);
13158 imm_expr.X_op = O_absent;
13162 case '|': /* 4-bit trap code. */
13163 gas_assert (mips_opts.micromips);
13164 my_getExpression (&imm_expr, s);
13165 check_absolute_expr (ip, &imm_expr);
13166 if ((unsigned long) imm_expr.X_add_number
13167 > MICROMIPSOP_MASK_TRAP)
13168 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13169 (unsigned long) imm_expr.X_add_number,
13170 ip->insn_mo->name);
13171 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13172 imm_expr.X_op = O_absent;
13177 as_bad (_("Bad char = '%c'\n"), *args);
13182 /* Args don't match. */
13184 insn_error = _("Illegal operands");
13185 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13190 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13192 gas_assert (firstinsn);
13193 need_delay_slot_ok = FALSE;
13202 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13204 /* This routine assembles an instruction into its binary format when
13205 assembling for the mips16. As a side effect, it sets one of the
13206 global variables imm_reloc or offset_reloc to the type of relocation
13207 to do if one of the operands is an address expression. It also sets
13208 forced_insn_length to the resulting instruction size in bytes if the
13209 user explicitly requested a small or extended instruction. */
13212 mips16_ip (char *str, struct mips_cl_insn *ip)
13216 struct mips_opcode *insn;
13218 unsigned int regno;
13219 unsigned int lastregno = 0;
13225 forced_insn_length = 0;
13227 for (s = str; ISLOWER (*s); ++s)
13239 if (s[1] == 't' && s[2] == ' ')
13242 forced_insn_length = 2;
13246 else if (s[1] == 'e' && s[2] == ' ')
13249 forced_insn_length = 4;
13253 /* Fall through. */
13255 insn_error = _("unknown opcode");
13259 if (mips_opts.noautoextend && !forced_insn_length)
13260 forced_insn_length = 2;
13262 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13264 insn_error = _("unrecognized opcode");
13273 gas_assert (strcmp (insn->name, str) == 0);
13275 ok = is_opcode_valid_16 (insn);
13278 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13279 && strcmp (insn->name, insn[1].name) == 0)
13288 static char buf[100];
13290 _("Opcode not supported on this processor: %s (%s)"),
13291 mips_cpu_info_from_arch (mips_opts.arch)->name,
13292 mips_cpu_info_from_isa (mips_opts.isa)->name);
13299 create_insn (ip, insn);
13300 imm_expr.X_op = O_absent;
13301 imm_reloc[0] = BFD_RELOC_UNUSED;
13302 imm_reloc[1] = BFD_RELOC_UNUSED;
13303 imm_reloc[2] = BFD_RELOC_UNUSED;
13304 imm2_expr.X_op = O_absent;
13305 offset_expr.X_op = O_absent;
13306 offset_reloc[0] = BFD_RELOC_UNUSED;
13307 offset_reloc[1] = BFD_RELOC_UNUSED;
13308 offset_reloc[2] = BFD_RELOC_UNUSED;
13309 for (args = insn->args; 1; ++args)
13316 /* In this switch statement we call break if we did not find
13317 a match, continue if we did find a match, or return if we
13326 /* Stuff the immediate value in now, if we can. */
13327 if (imm_expr.X_op == O_constant
13328 && *imm_reloc > BFD_RELOC_UNUSED
13329 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13330 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
13331 && insn->pinfo != INSN_MACRO)
13335 switch (*offset_reloc)
13337 case BFD_RELOC_MIPS16_HI16_S:
13338 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13341 case BFD_RELOC_MIPS16_HI16:
13342 tmp = imm_expr.X_add_number >> 16;
13345 case BFD_RELOC_MIPS16_LO16:
13346 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13350 case BFD_RELOC_UNUSED:
13351 tmp = imm_expr.X_add_number;
13357 *offset_reloc = BFD_RELOC_UNUSED;
13359 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13360 tmp, forced_insn_length, &ip->insn_opcode);
13361 imm_expr.X_op = O_absent;
13362 *imm_reloc = BFD_RELOC_UNUSED;
13376 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13379 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13395 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13397 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13401 /* Fall through. */
13412 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13414 if (c == 'v' || c == 'w')
13417 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13419 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13430 if (c == 'v' || c == 'w')
13432 regno = mips16_to_32_reg_map[lastregno];
13446 regno = mips32_to_16_reg_map[regno];
13451 regno = ILLEGAL_REG;
13456 regno = ILLEGAL_REG;
13461 regno = ILLEGAL_REG;
13466 if (regno == AT && mips_opts.at)
13468 if (mips_opts.at == ATREG)
13469 as_warn (_("used $at without \".set noat\""));
13471 as_warn (_("used $%u with \".set at=$%u\""),
13472 regno, mips_opts.at);
13480 if (regno == ILLEGAL_REG)
13487 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13491 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13494 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13497 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13503 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13506 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13507 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13517 if (strncmp (s, "$pc", 3) == 0)
13534 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13537 if (imm_expr.X_op != O_constant)
13539 forced_insn_length = 4;
13540 ip->insn_opcode |= MIPS16_EXTEND;
13544 /* We need to relax this instruction. */
13545 *offset_reloc = *imm_reloc;
13546 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13551 *imm_reloc = BFD_RELOC_UNUSED;
13552 /* Fall through. */
13559 my_getExpression (&imm_expr, s);
13560 if (imm_expr.X_op == O_register)
13562 /* What we thought was an expression turned out to
13565 if (s[0] == '(' && args[1] == '(')
13567 /* It looks like the expression was omitted
13568 before a register indirection, which means
13569 that the expression is implicitly zero. We
13570 still set up imm_expr, so that we handle
13571 explicit extensions correctly. */
13572 imm_expr.X_op = O_constant;
13573 imm_expr.X_add_number = 0;
13574 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13581 /* We need to relax this instruction. */
13582 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13591 /* We use offset_reloc rather than imm_reloc for the PC
13592 relative operands. This lets macros with both
13593 immediate and address operands work correctly. */
13594 my_getExpression (&offset_expr, s);
13596 if (offset_expr.X_op == O_register)
13599 /* We need to relax this instruction. */
13600 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13604 case '6': /* break code */
13605 my_getExpression (&imm_expr, s);
13606 check_absolute_expr (ip, &imm_expr);
13607 if ((unsigned long) imm_expr.X_add_number > 63)
13608 as_warn (_("Invalid value for `%s' (%lu)"),
13610 (unsigned long) imm_expr.X_add_number);
13611 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13612 imm_expr.X_op = O_absent;
13616 case 'a': /* 26 bit address */
13617 my_getExpression (&offset_expr, s);
13619 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13620 ip->insn_opcode <<= 16;
13623 case 'l': /* register list for entry macro */
13624 case 'L': /* register list for exit macro */
13634 unsigned int freg, reg1, reg2;
13636 while (*s == ' ' || *s == ',')
13638 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13640 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13644 as_bad (_("can't parse register list"));
13654 if (!reg_lookup (&s, freg ? RTYPE_FPU
13655 : (RTYPE_GP | RTYPE_NUM), ®2))
13657 as_bad (_("invalid register list"));
13661 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13663 mask &= ~ (7 << 3);
13666 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13668 mask &= ~ (7 << 3);
13671 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13672 mask |= (reg2 - 3) << 3;
13673 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13674 mask |= (reg2 - 15) << 1;
13675 else if (reg1 == RA && reg2 == RA)
13679 as_bad (_("invalid register list"));
13683 /* The mask is filled in in the opcode table for the
13684 benefit of the disassembler. We remove it before
13685 applying the actual mask. */
13686 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13687 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13691 case 'm': /* Register list for save insn. */
13692 case 'M': /* Register list for restore insn. */
13694 int opcode = ip->insn_opcode;
13695 int framesz = 0, seen_framesz = 0;
13696 int nargs = 0, statics = 0, sregs = 0;
13700 unsigned int reg1, reg2;
13702 SKIP_SPACE_TABS (s);
13705 SKIP_SPACE_TABS (s);
13707 my_getExpression (&imm_expr, s);
13708 if (imm_expr.X_op == O_constant)
13710 /* Handle the frame size. */
13713 as_bad (_("more than one frame size in list"));
13717 framesz = imm_expr.X_add_number;
13718 imm_expr.X_op = O_absent;
13723 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13725 as_bad (_("can't parse register list"));
13737 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13740 as_bad (_("can't parse register list"));
13745 while (reg1 <= reg2)
13747 if (reg1 >= 4 && reg1 <= 7)
13751 nargs |= 1 << (reg1 - 4);
13753 /* statics $a0-$a3 */
13754 statics |= 1 << (reg1 - 4);
13756 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13759 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13761 else if (reg1 == 31)
13763 /* Add $ra to insn. */
13768 as_bad (_("unexpected register in list"));
13776 /* Encode args/statics combination. */
13777 if (nargs & statics)
13778 as_bad (_("arg/static registers overlap"));
13779 else if (nargs == 0xf)
13780 /* All $a0-$a3 are args. */
13781 opcode |= MIPS16_ALL_ARGS << 16;
13782 else if (statics == 0xf)
13783 /* All $a0-$a3 are statics. */
13784 opcode |= MIPS16_ALL_STATICS << 16;
13787 int narg = 0, nstat = 0;
13789 /* Count arg registers. */
13790 while (nargs & 0x1)
13796 as_bad (_("invalid arg register list"));
13798 /* Count static registers. */
13799 while (statics & 0x8)
13801 statics = (statics << 1) & 0xf;
13805 as_bad (_("invalid static register list"));
13807 /* Encode args/statics. */
13808 opcode |= ((narg << 2) | nstat) << 16;
13811 /* Encode $s0/$s1. */
13812 if (sregs & (1 << 0)) /* $s0 */
13814 if (sregs & (1 << 1)) /* $s1 */
13820 /* Count regs $s2-$s8. */
13828 as_bad (_("invalid static register list"));
13829 /* Encode $s2-$s8. */
13830 opcode |= nsreg << 24;
13833 /* Encode frame size. */
13835 as_bad (_("missing frame size"));
13836 else if ((framesz & 7) != 0 || framesz < 0
13837 || framesz > 0xff * 8)
13838 as_bad (_("invalid frame size"));
13839 else if (framesz != 128 || (opcode >> 16) != 0)
13842 opcode |= (((framesz & 0xf0) << 16)
13843 | (framesz & 0x0f));
13846 /* Finally build the instruction. */
13847 if ((opcode >> 16) != 0 || framesz == 0)
13848 opcode |= MIPS16_EXTEND;
13849 ip->insn_opcode = opcode;
13853 case 'e': /* extend code */
13854 my_getExpression (&imm_expr, s);
13855 check_absolute_expr (ip, &imm_expr);
13856 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13858 as_warn (_("Invalid value for `%s' (%lu)"),
13860 (unsigned long) imm_expr.X_add_number);
13861 imm_expr.X_add_number &= 0x7ff;
13863 ip->insn_opcode |= imm_expr.X_add_number;
13864 imm_expr.X_op = O_absent;
13874 /* Args don't match. */
13875 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13876 strcmp (insn->name, insn[1].name) == 0)
13883 insn_error = _("illegal operands");
13889 /* This structure holds information we know about a mips16 immediate
13892 struct mips16_immed_operand
13894 /* The type code used in the argument string in the opcode table. */
13896 /* The number of bits in the short form of the opcode. */
13898 /* The number of bits in the extended form of the opcode. */
13900 /* The amount by which the short form is shifted when it is used;
13901 for example, the sw instruction has a shift count of 2. */
13903 /* The amount by which the short form is shifted when it is stored
13904 into the instruction code. */
13906 /* Non-zero if the short form is unsigned. */
13908 /* Non-zero if the extended form is unsigned. */
13910 /* Non-zero if the value is PC relative. */
13914 /* The mips16 immediate operand types. */
13916 static const struct mips16_immed_operand mips16_immed_operands[] =
13918 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13919 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13920 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13921 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13922 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13923 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13924 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13925 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13926 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13927 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13928 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13929 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13930 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13931 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13932 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13933 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13934 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13935 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13936 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13937 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13938 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13941 #define MIPS16_NUM_IMMED \
13942 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13944 /* Install immediate value VAL into MIPS16 instruction *INSN,
13945 extending it if necessary. The instruction in *INSN may
13946 already be extended.
13948 TYPE is the type of the immediate field. USER_INSN_LENGTH is the
13949 length that the user requested, or 0 if none. */
13952 mips16_immed (char *file, unsigned int line, int type, offsetT val,
13953 unsigned int user_insn_length, unsigned long *insn)
13955 const struct mips16_immed_operand *op;
13956 int mintiny, maxtiny;
13958 op = mips16_immed_operands;
13959 while (op->type != type)
13962 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13967 if (type == '<' || type == '>' || type == '[' || type == ']')
13970 maxtiny = 1 << op->nbits;
13975 maxtiny = (1 << op->nbits) - 1;
13980 mintiny = - (1 << (op->nbits - 1));
13981 maxtiny = (1 << (op->nbits - 1)) - 1;
13984 /* Branch offsets have an implicit 0 in the lowest bit. */
13985 if (type == 'p' || type == 'q')
13988 if ((val & ((1 << op->shift) - 1)) != 0
13989 || val < (mintiny << op->shift)
13990 || val > (maxtiny << op->shift))
13992 /* We need an extended instruction. */
13993 if (user_insn_length == 2)
13994 as_bad_where (file, line, _("invalid unextended operand value"));
13996 *insn |= MIPS16_EXTEND;
13998 else if (user_insn_length == 4)
14000 /* The operand doesn't force an unextended instruction to be extended.
14001 Warn if the user wanted an extended instruction anyway. */
14002 *insn |= MIPS16_EXTEND;
14003 as_warn_where (file, line,
14004 _("extended operand requested but not required"));
14007 if (mips16_opcode_length (*insn) == 2)
14011 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14012 insnval <<= op->op_shift;
14017 long minext, maxext;
14023 maxext = (1 << op->extbits) - 1;
14027 minext = - (1 << (op->extbits - 1));
14028 maxext = (1 << (op->extbits - 1)) - 1;
14030 if (val < minext || val > maxext)
14031 as_bad_where (file, line,
14032 _("operand value out of range for instruction"));
14034 if (op->extbits == 16)
14036 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14039 else if (op->extbits == 15)
14041 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14046 extval = ((val & 0x1f) << 6) | (val & 0x20);
14050 *insn |= (extval << 16) | val;
14054 struct percent_op_match
14057 bfd_reloc_code_real_type reloc;
14060 static const struct percent_op_match mips_percent_op[] =
14062 {"%lo", BFD_RELOC_LO16},
14064 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14065 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14066 {"%call16", BFD_RELOC_MIPS_CALL16},
14067 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14068 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14069 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14070 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14071 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14072 {"%got", BFD_RELOC_MIPS_GOT16},
14073 {"%gp_rel", BFD_RELOC_GPREL16},
14074 {"%half", BFD_RELOC_16},
14075 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14076 {"%higher", BFD_RELOC_MIPS_HIGHER},
14077 {"%neg", BFD_RELOC_MIPS_SUB},
14078 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14079 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14080 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14081 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14082 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14083 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14084 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14086 {"%hi", BFD_RELOC_HI16_S}
14089 static const struct percent_op_match mips16_percent_op[] =
14091 {"%lo", BFD_RELOC_MIPS16_LO16},
14092 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14093 {"%got", BFD_RELOC_MIPS16_GOT16},
14094 {"%call16", BFD_RELOC_MIPS16_CALL16},
14095 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14096 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14097 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14098 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14099 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14100 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14101 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14102 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14106 /* Return true if *STR points to a relocation operator. When returning true,
14107 move *STR over the operator and store its relocation code in *RELOC.
14108 Leave both *STR and *RELOC alone when returning false. */
14111 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14113 const struct percent_op_match *percent_op;
14116 if (mips_opts.mips16)
14118 percent_op = mips16_percent_op;
14119 limit = ARRAY_SIZE (mips16_percent_op);
14123 percent_op = mips_percent_op;
14124 limit = ARRAY_SIZE (mips_percent_op);
14127 for (i = 0; i < limit; i++)
14128 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14130 int len = strlen (percent_op[i].str);
14132 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14135 *str += strlen (percent_op[i].str);
14136 *reloc = percent_op[i].reloc;
14138 /* Check whether the output BFD supports this relocation.
14139 If not, issue an error and fall back on something safe. */
14140 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14142 as_bad (_("relocation %s isn't supported by the current ABI"),
14143 percent_op[i].str);
14144 *reloc = BFD_RELOC_UNUSED;
14152 /* Parse string STR as a 16-bit relocatable operand. Store the
14153 expression in *EP and the relocations in the array starting
14154 at RELOC. Return the number of relocation operators used.
14156 On exit, EXPR_END points to the first character after the expression. */
14159 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14162 bfd_reloc_code_real_type reversed_reloc[3];
14163 size_t reloc_index, i;
14164 int crux_depth, str_depth;
14167 /* Search for the start of the main expression, recoding relocations
14168 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14169 of the main expression and with CRUX_DEPTH containing the number
14170 of open brackets at that point. */
14177 crux_depth = str_depth;
14179 /* Skip over whitespace and brackets, keeping count of the number
14181 while (*str == ' ' || *str == '\t' || *str == '(')
14186 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14187 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14189 my_getExpression (ep, crux);
14192 /* Match every open bracket. */
14193 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14197 if (crux_depth > 0)
14198 as_bad (_("unclosed '('"));
14202 if (reloc_index != 0)
14204 prev_reloc_op_frag = frag_now;
14205 for (i = 0; i < reloc_index; i++)
14206 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14209 return reloc_index;
14213 my_getExpression (expressionS *ep, char *str)
14217 save_in = input_line_pointer;
14218 input_line_pointer = str;
14220 expr_end = input_line_pointer;
14221 input_line_pointer = save_in;
14225 md_atof (int type, char *litP, int *sizeP)
14227 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14231 md_number_to_chars (char *buf, valueT val, int n)
14233 if (target_big_endian)
14234 number_to_chars_bigendian (buf, val, n);
14236 number_to_chars_littleendian (buf, val, n);
14240 static int support_64bit_objects(void)
14242 const char **list, **l;
14245 list = bfd_target_list ();
14246 for (l = list; *l != NULL; l++)
14247 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14248 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14250 yes = (*l != NULL);
14254 #endif /* OBJ_ELF */
14256 const char *md_shortopts = "O::g::G:";
14260 OPTION_MARCH = OPTION_MD_BASE,
14282 OPTION_NO_SMARTMIPS,
14286 OPTION_NO_MICROMIPS,
14289 OPTION_COMPAT_ARCH_BASE,
14298 OPTION_M7000_HILO_FIX,
14299 OPTION_MNO_7000_HILO_FIX,
14302 OPTION_FIX_LOONGSON2F_JUMP,
14303 OPTION_NO_FIX_LOONGSON2F_JUMP,
14304 OPTION_FIX_LOONGSON2F_NOP,
14305 OPTION_NO_FIX_LOONGSON2F_NOP,
14307 OPTION_NO_FIX_VR4120,
14309 OPTION_NO_FIX_VR4130,
14310 OPTION_FIX_CN63XXP1,
14311 OPTION_NO_FIX_CN63XXP1,
14318 OPTION_CONSTRUCT_FLOATS,
14319 OPTION_NO_CONSTRUCT_FLOATS,
14322 OPTION_RELAX_BRANCH,
14323 OPTION_NO_RELAX_BRANCH,
14330 OPTION_SINGLE_FLOAT,
14331 OPTION_DOUBLE_FLOAT,
14334 OPTION_CALL_SHARED,
14335 OPTION_CALL_NONPIC,
14345 OPTION_MVXWORKS_PIC,
14346 #endif /* OBJ_ELF */
14350 struct option md_longopts[] =
14352 /* Options which specify architecture. */
14353 {"march", required_argument, NULL, OPTION_MARCH},
14354 {"mtune", required_argument, NULL, OPTION_MTUNE},
14355 {"mips0", no_argument, NULL, OPTION_MIPS1},
14356 {"mips1", no_argument, NULL, OPTION_MIPS1},
14357 {"mips2", no_argument, NULL, OPTION_MIPS2},
14358 {"mips3", no_argument, NULL, OPTION_MIPS3},
14359 {"mips4", no_argument, NULL, OPTION_MIPS4},
14360 {"mips5", no_argument, NULL, OPTION_MIPS5},
14361 {"mips32", no_argument, NULL, OPTION_MIPS32},
14362 {"mips64", no_argument, NULL, OPTION_MIPS64},
14363 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14364 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14366 /* Options which specify Application Specific Extensions (ASEs). */
14367 {"mips16", no_argument, NULL, OPTION_MIPS16},
14368 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14369 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14370 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14371 {"mdmx", no_argument, NULL, OPTION_MDMX},
14372 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14373 {"mdsp", no_argument, NULL, OPTION_DSP},
14374 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14375 {"mmt", no_argument, NULL, OPTION_MT},
14376 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14377 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14378 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14379 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14380 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14381 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14382 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14383 {"mmcu", no_argument, NULL, OPTION_MCU},
14384 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14386 /* Old-style architecture options. Don't add more of these. */
14387 {"m4650", no_argument, NULL, OPTION_M4650},
14388 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14389 {"m4010", no_argument, NULL, OPTION_M4010},
14390 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14391 {"m4100", no_argument, NULL, OPTION_M4100},
14392 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14393 {"m3900", no_argument, NULL, OPTION_M3900},
14394 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14396 /* Options which enable bug fixes. */
14397 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14398 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14399 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14400 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14401 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14402 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14403 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14404 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14405 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14406 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14407 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14408 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14409 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14410 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14411 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14413 /* Miscellaneous options. */
14414 {"trap", no_argument, NULL, OPTION_TRAP},
14415 {"no-break", no_argument, NULL, OPTION_TRAP},
14416 {"break", no_argument, NULL, OPTION_BREAK},
14417 {"no-trap", no_argument, NULL, OPTION_BREAK},
14418 {"EB", no_argument, NULL, OPTION_EB},
14419 {"EL", no_argument, NULL, OPTION_EL},
14420 {"mfp32", no_argument, NULL, OPTION_FP32},
14421 {"mgp32", no_argument, NULL, OPTION_GP32},
14422 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14423 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14424 {"mfp64", no_argument, NULL, OPTION_FP64},
14425 {"mgp64", no_argument, NULL, OPTION_GP64},
14426 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14427 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14428 {"mshared", no_argument, NULL, OPTION_MSHARED},
14429 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14430 {"msym32", no_argument, NULL, OPTION_MSYM32},
14431 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14432 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14433 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14434 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14435 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14437 /* Strictly speaking this next option is ELF specific,
14438 but we allow it for other ports as well in order to
14439 make testing easier. */
14440 {"32", no_argument, NULL, OPTION_32},
14442 /* ELF-specific options. */
14444 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14445 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14446 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14447 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14448 {"xgot", no_argument, NULL, OPTION_XGOT},
14449 {"mabi", required_argument, NULL, OPTION_MABI},
14450 {"n32", no_argument, NULL, OPTION_N32},
14451 {"64", no_argument, NULL, OPTION_64},
14452 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14453 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14454 {"mpdr", no_argument, NULL, OPTION_PDR},
14455 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14456 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14457 #endif /* OBJ_ELF */
14459 {NULL, no_argument, NULL, 0}
14461 size_t md_longopts_size = sizeof (md_longopts);
14463 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14464 NEW_VALUE. Warn if another value was already specified. Note:
14465 we have to defer parsing the -march and -mtune arguments in order
14466 to handle 'from-abi' correctly, since the ABI might be specified
14467 in a later argument. */
14470 mips_set_option_string (const char **string_ptr, const char *new_value)
14472 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14473 as_warn (_("A different %s was already specified, is now %s"),
14474 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14477 *string_ptr = new_value;
14481 md_parse_option (int c, char *arg)
14485 case OPTION_CONSTRUCT_FLOATS:
14486 mips_disable_float_construction = 0;
14489 case OPTION_NO_CONSTRUCT_FLOATS:
14490 mips_disable_float_construction = 1;
14502 target_big_endian = 1;
14506 target_big_endian = 0;
14512 else if (arg[0] == '0')
14514 else if (arg[0] == '1')
14524 mips_debug = atoi (arg);
14528 file_mips_isa = ISA_MIPS1;
14532 file_mips_isa = ISA_MIPS2;
14536 file_mips_isa = ISA_MIPS3;
14540 file_mips_isa = ISA_MIPS4;
14544 file_mips_isa = ISA_MIPS5;
14547 case OPTION_MIPS32:
14548 file_mips_isa = ISA_MIPS32;
14551 case OPTION_MIPS32R2:
14552 file_mips_isa = ISA_MIPS32R2;
14555 case OPTION_MIPS64R2:
14556 file_mips_isa = ISA_MIPS64R2;
14559 case OPTION_MIPS64:
14560 file_mips_isa = ISA_MIPS64;
14564 mips_set_option_string (&mips_tune_string, arg);
14568 mips_set_option_string (&mips_arch_string, arg);
14572 mips_set_option_string (&mips_arch_string, "4650");
14573 mips_set_option_string (&mips_tune_string, "4650");
14576 case OPTION_NO_M4650:
14580 mips_set_option_string (&mips_arch_string, "4010");
14581 mips_set_option_string (&mips_tune_string, "4010");
14584 case OPTION_NO_M4010:
14588 mips_set_option_string (&mips_arch_string, "4100");
14589 mips_set_option_string (&mips_tune_string, "4100");
14592 case OPTION_NO_M4100:
14596 mips_set_option_string (&mips_arch_string, "3900");
14597 mips_set_option_string (&mips_tune_string, "3900");
14600 case OPTION_NO_M3900:
14604 mips_opts.ase_mdmx = 1;
14607 case OPTION_NO_MDMX:
14608 mips_opts.ase_mdmx = 0;
14612 mips_opts.ase_dsp = 1;
14613 mips_opts.ase_dspr2 = 0;
14616 case OPTION_NO_DSP:
14617 mips_opts.ase_dsp = 0;
14618 mips_opts.ase_dspr2 = 0;
14622 mips_opts.ase_dspr2 = 1;
14623 mips_opts.ase_dsp = 1;
14626 case OPTION_NO_DSPR2:
14627 mips_opts.ase_dspr2 = 0;
14628 mips_opts.ase_dsp = 0;
14632 mips_opts.ase_mt = 1;
14636 mips_opts.ase_mt = 0;
14640 mips_opts.ase_mcu = 1;
14643 case OPTION_NO_MCU:
14644 mips_opts.ase_mcu = 0;
14647 case OPTION_MICROMIPS:
14648 if (mips_opts.mips16 == 1)
14650 as_bad (_("-mmicromips cannot be used with -mips16"));
14653 mips_opts.micromips = 1;
14654 mips_no_prev_insn ();
14657 case OPTION_NO_MICROMIPS:
14658 mips_opts.micromips = 0;
14659 mips_no_prev_insn ();
14662 case OPTION_MIPS16:
14663 if (mips_opts.micromips == 1)
14665 as_bad (_("-mips16 cannot be used with -micromips"));
14668 mips_opts.mips16 = 1;
14669 mips_no_prev_insn ();
14672 case OPTION_NO_MIPS16:
14673 mips_opts.mips16 = 0;
14674 mips_no_prev_insn ();
14677 case OPTION_MIPS3D:
14678 mips_opts.ase_mips3d = 1;
14681 case OPTION_NO_MIPS3D:
14682 mips_opts.ase_mips3d = 0;
14685 case OPTION_SMARTMIPS:
14686 mips_opts.ase_smartmips = 1;
14689 case OPTION_NO_SMARTMIPS:
14690 mips_opts.ase_smartmips = 0;
14693 case OPTION_FIX_24K:
14697 case OPTION_NO_FIX_24K:
14701 case OPTION_FIX_LOONGSON2F_JUMP:
14702 mips_fix_loongson2f_jump = TRUE;
14705 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14706 mips_fix_loongson2f_jump = FALSE;
14709 case OPTION_FIX_LOONGSON2F_NOP:
14710 mips_fix_loongson2f_nop = TRUE;
14713 case OPTION_NO_FIX_LOONGSON2F_NOP:
14714 mips_fix_loongson2f_nop = FALSE;
14717 case OPTION_FIX_VR4120:
14718 mips_fix_vr4120 = 1;
14721 case OPTION_NO_FIX_VR4120:
14722 mips_fix_vr4120 = 0;
14725 case OPTION_FIX_VR4130:
14726 mips_fix_vr4130 = 1;
14729 case OPTION_NO_FIX_VR4130:
14730 mips_fix_vr4130 = 0;
14733 case OPTION_FIX_CN63XXP1:
14734 mips_fix_cn63xxp1 = TRUE;
14737 case OPTION_NO_FIX_CN63XXP1:
14738 mips_fix_cn63xxp1 = FALSE;
14741 case OPTION_RELAX_BRANCH:
14742 mips_relax_branch = 1;
14745 case OPTION_NO_RELAX_BRANCH:
14746 mips_relax_branch = 0;
14749 case OPTION_MSHARED:
14750 mips_in_shared = TRUE;
14753 case OPTION_MNO_SHARED:
14754 mips_in_shared = FALSE;
14757 case OPTION_MSYM32:
14758 mips_opts.sym32 = TRUE;
14761 case OPTION_MNO_SYM32:
14762 mips_opts.sym32 = FALSE;
14766 /* When generating ELF code, we permit -KPIC and -call_shared to
14767 select SVR4_PIC, and -non_shared to select no PIC. This is
14768 intended to be compatible with Irix 5. */
14769 case OPTION_CALL_SHARED:
14772 as_bad (_("-call_shared is supported only for ELF format"));
14775 mips_pic = SVR4_PIC;
14776 mips_abicalls = TRUE;
14779 case OPTION_CALL_NONPIC:
14782 as_bad (_("-call_nonpic is supported only for ELF format"));
14786 mips_abicalls = TRUE;
14789 case OPTION_NON_SHARED:
14792 as_bad (_("-non_shared is supported only for ELF format"));
14796 mips_abicalls = FALSE;
14799 /* The -xgot option tells the assembler to use 32 bit offsets
14800 when accessing the got in SVR4_PIC mode. It is for Irix
14805 #endif /* OBJ_ELF */
14808 g_switch_value = atoi (arg);
14812 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14816 mips_abi = O32_ABI;
14817 /* We silently ignore -32 for non-ELF targets. This greatly
14818 simplifies the construction of the MIPS GAS test cases. */
14825 as_bad (_("-n32 is supported for ELF format only"));
14828 mips_abi = N32_ABI;
14834 as_bad (_("-64 is supported for ELF format only"));
14837 mips_abi = N64_ABI;
14838 if (!support_64bit_objects())
14839 as_fatal (_("No compiled in support for 64 bit object file format"));
14841 #endif /* OBJ_ELF */
14844 file_mips_gp32 = 1;
14848 file_mips_gp32 = 0;
14852 file_mips_fp32 = 1;
14856 file_mips_fp32 = 0;
14859 case OPTION_SINGLE_FLOAT:
14860 file_mips_single_float = 1;
14863 case OPTION_DOUBLE_FLOAT:
14864 file_mips_single_float = 0;
14867 case OPTION_SOFT_FLOAT:
14868 file_mips_soft_float = 1;
14871 case OPTION_HARD_FLOAT:
14872 file_mips_soft_float = 0;
14879 as_bad (_("-mabi is supported for ELF format only"));
14882 if (strcmp (arg, "32") == 0)
14883 mips_abi = O32_ABI;
14884 else if (strcmp (arg, "o64") == 0)
14885 mips_abi = O64_ABI;
14886 else if (strcmp (arg, "n32") == 0)
14887 mips_abi = N32_ABI;
14888 else if (strcmp (arg, "64") == 0)
14890 mips_abi = N64_ABI;
14891 if (! support_64bit_objects())
14892 as_fatal (_("No compiled in support for 64 bit object file "
14895 else if (strcmp (arg, "eabi") == 0)
14896 mips_abi = EABI_ABI;
14899 as_fatal (_("invalid abi -mabi=%s"), arg);
14903 #endif /* OBJ_ELF */
14905 case OPTION_M7000_HILO_FIX:
14906 mips_7000_hilo_fix = TRUE;
14909 case OPTION_MNO_7000_HILO_FIX:
14910 mips_7000_hilo_fix = FALSE;
14914 case OPTION_MDEBUG:
14915 mips_flag_mdebug = TRUE;
14918 case OPTION_NO_MDEBUG:
14919 mips_flag_mdebug = FALSE;
14923 mips_flag_pdr = TRUE;
14926 case OPTION_NO_PDR:
14927 mips_flag_pdr = FALSE;
14930 case OPTION_MVXWORKS_PIC:
14931 mips_pic = VXWORKS_PIC;
14933 #endif /* OBJ_ELF */
14939 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14944 /* Set up globals to generate code for the ISA or processor
14945 described by INFO. */
14948 mips_set_architecture (const struct mips_cpu_info *info)
14952 file_mips_arch = info->cpu;
14953 mips_opts.arch = info->cpu;
14954 mips_opts.isa = info->isa;
14959 /* Likewise for tuning. */
14962 mips_set_tune (const struct mips_cpu_info *info)
14965 mips_tune = info->cpu;
14970 mips_after_parse_args (void)
14972 const struct mips_cpu_info *arch_info = 0;
14973 const struct mips_cpu_info *tune_info = 0;
14975 /* GP relative stuff not working for PE */
14976 if (strncmp (TARGET_OS, "pe", 2) == 0)
14978 if (g_switch_seen && g_switch_value != 0)
14979 as_bad (_("-G not supported in this configuration."));
14980 g_switch_value = 0;
14983 if (mips_abi == NO_ABI)
14984 mips_abi = MIPS_DEFAULT_ABI;
14986 /* The following code determines the architecture and register size.
14987 Similar code was added to GCC 3.3 (see override_options() in
14988 config/mips/mips.c). The GAS and GCC code should be kept in sync
14989 as much as possible. */
14991 if (mips_arch_string != 0)
14992 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14994 if (file_mips_isa != ISA_UNKNOWN)
14996 /* Handle -mipsN. At this point, file_mips_isa contains the
14997 ISA level specified by -mipsN, while arch_info->isa contains
14998 the -march selection (if any). */
14999 if (arch_info != 0)
15001 /* -march takes precedence over -mipsN, since it is more descriptive.
15002 There's no harm in specifying both as long as the ISA levels
15004 if (file_mips_isa != arch_info->isa)
15005 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15006 mips_cpu_info_from_isa (file_mips_isa)->name,
15007 mips_cpu_info_from_isa (arch_info->isa)->name);
15010 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15013 if (arch_info == 0)
15015 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15016 gas_assert (arch_info);
15019 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15020 as_bad (_("-march=%s is not compatible with the selected ABI"),
15023 mips_set_architecture (arch_info);
15025 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15026 if (mips_tune_string != 0)
15027 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15029 if (tune_info == 0)
15030 mips_set_tune (arch_info);
15032 mips_set_tune (tune_info);
15034 if (file_mips_gp32 >= 0)
15036 /* The user specified the size of the integer registers. Make sure
15037 it agrees with the ABI and ISA. */
15038 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15039 as_bad (_("-mgp64 used with a 32-bit processor"));
15040 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15041 as_bad (_("-mgp32 used with a 64-bit ABI"));
15042 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15043 as_bad (_("-mgp64 used with a 32-bit ABI"));
15047 /* Infer the integer register size from the ABI and processor.
15048 Restrict ourselves to 32-bit registers if that's all the
15049 processor has, or if the ABI cannot handle 64-bit registers. */
15050 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15051 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15054 switch (file_mips_fp32)
15058 /* No user specified float register size.
15059 ??? GAS treats single-float processors as though they had 64-bit
15060 float registers (although it complains when double-precision
15061 instructions are used). As things stand, saying they have 32-bit
15062 registers would lead to spurious "register must be even" messages.
15063 So here we assume float registers are never smaller than the
15065 if (file_mips_gp32 == 0)
15066 /* 64-bit integer registers implies 64-bit float registers. */
15067 file_mips_fp32 = 0;
15068 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15069 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15070 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15071 file_mips_fp32 = 0;
15073 /* 32-bit float registers. */
15074 file_mips_fp32 = 1;
15077 /* The user specified the size of the float registers. Check if it
15078 agrees with the ABI and ISA. */
15080 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15081 as_bad (_("-mfp64 used with a 32-bit fpu"));
15082 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15083 && !ISA_HAS_MXHC1 (mips_opts.isa))
15084 as_warn (_("-mfp64 used with a 32-bit ABI"));
15087 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15088 as_warn (_("-mfp32 used with a 64-bit ABI"));
15092 /* End of GCC-shared inference code. */
15094 /* This flag is set when we have a 64-bit capable CPU but use only
15095 32-bit wide registers. Note that EABI does not use it. */
15096 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15097 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15098 || mips_abi == O32_ABI))
15099 mips_32bitmode = 1;
15101 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15102 as_bad (_("trap exception not supported at ISA 1"));
15104 /* If the selected architecture includes support for ASEs, enable
15105 generation of code for them. */
15106 if (mips_opts.mips16 == -1)
15107 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15108 if (mips_opts.micromips == -1)
15109 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15110 if (mips_opts.ase_mips3d == -1)
15111 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15112 && file_mips_fp32 == 0) ? 1 : 0;
15113 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15114 as_bad (_("-mfp32 used with -mips3d"));
15116 if (mips_opts.ase_mdmx == -1)
15117 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15118 && file_mips_fp32 == 0) ? 1 : 0;
15119 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15120 as_bad (_("-mfp32 used with -mdmx"));
15122 if (mips_opts.ase_smartmips == -1)
15123 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15124 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15125 as_warn (_("%s ISA does not support SmartMIPS"),
15126 mips_cpu_info_from_isa (mips_opts.isa)->name);
15128 if (mips_opts.ase_dsp == -1)
15129 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15130 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15131 as_warn (_("%s ISA does not support DSP ASE"),
15132 mips_cpu_info_from_isa (mips_opts.isa)->name);
15134 if (mips_opts.ase_dspr2 == -1)
15136 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15137 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15139 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15140 as_warn (_("%s ISA does not support DSP R2 ASE"),
15141 mips_cpu_info_from_isa (mips_opts.isa)->name);
15143 if (mips_opts.ase_mt == -1)
15144 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15145 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15146 as_warn (_("%s ISA does not support MT ASE"),
15147 mips_cpu_info_from_isa (mips_opts.isa)->name);
15149 if (mips_opts.ase_mcu == -1)
15150 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15151 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15152 as_warn (_("%s ISA does not support MCU ASE"),
15153 mips_cpu_info_from_isa (mips_opts.isa)->name);
15155 file_mips_isa = mips_opts.isa;
15156 file_ase_mips3d = mips_opts.ase_mips3d;
15157 file_ase_mdmx = mips_opts.ase_mdmx;
15158 file_ase_smartmips = mips_opts.ase_smartmips;
15159 file_ase_dsp = mips_opts.ase_dsp;
15160 file_ase_dspr2 = mips_opts.ase_dspr2;
15161 file_ase_mt = mips_opts.ase_mt;
15162 mips_opts.gp32 = file_mips_gp32;
15163 mips_opts.fp32 = file_mips_fp32;
15164 mips_opts.soft_float = file_mips_soft_float;
15165 mips_opts.single_float = file_mips_single_float;
15167 if (mips_flag_mdebug < 0)
15169 #ifdef OBJ_MAYBE_ECOFF
15170 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15171 mips_flag_mdebug = 1;
15173 #endif /* OBJ_MAYBE_ECOFF */
15174 mips_flag_mdebug = 0;
15179 mips_init_after_args (void)
15181 /* initialize opcodes */
15182 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15183 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15187 md_pcrel_from (fixS *fixP)
15189 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15190 switch (fixP->fx_r_type)
15192 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15193 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15194 /* Return the address of the delay slot. */
15197 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15198 case BFD_RELOC_MICROMIPS_JMP:
15199 case BFD_RELOC_16_PCREL_S2:
15200 case BFD_RELOC_MIPS_JMP:
15201 /* Return the address of the delay slot. */
15205 /* We have no relocation type for PC relative MIPS16 instructions. */
15206 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15207 as_bad_where (fixP->fx_file, fixP->fx_line,
15208 _("PC relative MIPS16 instruction references a different section"));
15213 /* This is called before the symbol table is processed. In order to
15214 work with gcc when using mips-tfile, we must keep all local labels.
15215 However, in other cases, we want to discard them. If we were
15216 called with -g, but we didn't see any debugging information, it may
15217 mean that gcc is smuggling debugging information through to
15218 mips-tfile, in which case we must generate all local labels. */
15221 mips_frob_file_before_adjust (void)
15223 #ifndef NO_ECOFF_DEBUGGING
15224 if (ECOFF_DEBUGGING
15226 && ! ecoff_debugging_seen)
15227 flag_keep_locals = 1;
15231 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15232 the corresponding LO16 reloc. This is called before md_apply_fix and
15233 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15234 relocation operators.
15236 For our purposes, a %lo() expression matches a %got() or %hi()
15239 (a) it refers to the same symbol; and
15240 (b) the offset applied in the %lo() expression is no lower than
15241 the offset applied in the %got() or %hi().
15243 (b) allows us to cope with code like:
15246 lh $4,%lo(foo+2)($4)
15248 ...which is legal on RELA targets, and has a well-defined behaviour
15249 if the user knows that adding 2 to "foo" will not induce a carry to
15252 When several %lo()s match a particular %got() or %hi(), we use the
15253 following rules to distinguish them:
15255 (1) %lo()s with smaller offsets are a better match than %lo()s with
15258 (2) %lo()s with no matching %got() or %hi() are better than those
15259 that already have a matching %got() or %hi().
15261 (3) later %lo()s are better than earlier %lo()s.
15263 These rules are applied in order.
15265 (1) means, among other things, that %lo()s with identical offsets are
15266 chosen if they exist.
15268 (2) means that we won't associate several high-part relocations with
15269 the same low-part relocation unless there's no alternative. Having
15270 several high parts for the same low part is a GNU extension; this rule
15271 allows careful users to avoid it.
15273 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15274 with the last high-part relocation being at the front of the list.
15275 It therefore makes sense to choose the last matching low-part
15276 relocation, all other things being equal. It's also easier
15277 to code that way. */
15280 mips_frob_file (void)
15282 struct mips_hi_fixup *l;
15283 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15285 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15287 segment_info_type *seginfo;
15288 bfd_boolean matched_lo_p;
15289 fixS **hi_pos, **lo_pos, **pos;
15291 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15293 /* If a GOT16 relocation turns out to be against a global symbol,
15294 there isn't supposed to be a matching LO. */
15295 if (got16_reloc_p (l->fixp->fx_r_type)
15296 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15299 /* Check quickly whether the next fixup happens to be a matching %lo. */
15300 if (fixup_has_matching_lo_p (l->fixp))
15303 seginfo = seg_info (l->seg);
15305 /* Set HI_POS to the position of this relocation in the chain.
15306 Set LO_POS to the position of the chosen low-part relocation.
15307 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15308 relocation that matches an immediately-preceding high-part
15312 matched_lo_p = FALSE;
15313 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15315 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15317 if (*pos == l->fixp)
15320 if ((*pos)->fx_r_type == looking_for_rtype
15321 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15322 && (*pos)->fx_offset >= l->fixp->fx_offset
15324 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15326 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15329 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15330 && fixup_has_matching_lo_p (*pos));
15333 /* If we found a match, remove the high-part relocation from its
15334 current position and insert it before the low-part relocation.
15335 Make the offsets match so that fixup_has_matching_lo_p()
15338 We don't warn about unmatched high-part relocations since some
15339 versions of gcc have been known to emit dead "lui ...%hi(...)"
15341 if (lo_pos != NULL)
15343 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15344 if (l->fixp->fx_next != *lo_pos)
15346 *hi_pos = l->fixp->fx_next;
15347 l->fixp->fx_next = *lo_pos;
15354 /* We may have combined relocations without symbols in the N32/N64 ABI.
15355 We have to prevent gas from dropping them. */
15358 mips_force_relocation (fixS *fixp)
15360 if (generic_force_reloc (fixp))
15363 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15364 so that the linker relaxation can update targets. */
15365 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15366 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15367 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15371 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15372 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
15373 || hi16_reloc_p (fixp->fx_r_type)
15374 || lo16_reloc_p (fixp->fx_r_type)))
15380 /* Apply a fixup to the object file. */
15383 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15387 reloc_howto_type *howto;
15389 /* We ignore generic BFD relocations we don't know about. */
15390 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15394 gas_assert (fixP->fx_size == 2
15395 || fixP->fx_size == 4
15396 || fixP->fx_r_type == BFD_RELOC_16
15397 || fixP->fx_r_type == BFD_RELOC_64
15398 || fixP->fx_r_type == BFD_RELOC_CTOR
15399 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15400 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15401 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15402 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15403 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15405 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
15407 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15408 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15409 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15410 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15412 /* Don't treat parts of a composite relocation as done. There are two
15415 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15416 should nevertheless be emitted if the first part is.
15418 (2) In normal usage, composite relocations are never assembly-time
15419 constants. The easiest way of dealing with the pathological
15420 exceptions is to generate a relocation against STN_UNDEF and
15421 leave everything up to the linker. */
15422 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15425 switch (fixP->fx_r_type)
15427 case BFD_RELOC_MIPS_TLS_GD:
15428 case BFD_RELOC_MIPS_TLS_LDM:
15429 case BFD_RELOC_MIPS_TLS_DTPREL32:
15430 case BFD_RELOC_MIPS_TLS_DTPREL64:
15431 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15432 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15433 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15434 case BFD_RELOC_MIPS_TLS_TPREL32:
15435 case BFD_RELOC_MIPS_TLS_TPREL64:
15436 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15437 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15438 case BFD_RELOC_MICROMIPS_TLS_GD:
15439 case BFD_RELOC_MICROMIPS_TLS_LDM:
15440 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15441 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15442 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15443 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15444 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15445 case BFD_RELOC_MIPS16_TLS_GD:
15446 case BFD_RELOC_MIPS16_TLS_LDM:
15447 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15448 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15449 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15450 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15451 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15452 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15455 case BFD_RELOC_MIPS_JMP:
15456 case BFD_RELOC_MIPS_SHIFT5:
15457 case BFD_RELOC_MIPS_SHIFT6:
15458 case BFD_RELOC_MIPS_GOT_DISP:
15459 case BFD_RELOC_MIPS_GOT_PAGE:
15460 case BFD_RELOC_MIPS_GOT_OFST:
15461 case BFD_RELOC_MIPS_SUB:
15462 case BFD_RELOC_MIPS_INSERT_A:
15463 case BFD_RELOC_MIPS_INSERT_B:
15464 case BFD_RELOC_MIPS_DELETE:
15465 case BFD_RELOC_MIPS_HIGHEST:
15466 case BFD_RELOC_MIPS_HIGHER:
15467 case BFD_RELOC_MIPS_SCN_DISP:
15468 case BFD_RELOC_MIPS_REL16:
15469 case BFD_RELOC_MIPS_RELGOT:
15470 case BFD_RELOC_MIPS_JALR:
15471 case BFD_RELOC_HI16:
15472 case BFD_RELOC_HI16_S:
15473 case BFD_RELOC_GPREL16:
15474 case BFD_RELOC_MIPS_LITERAL:
15475 case BFD_RELOC_MIPS_CALL16:
15476 case BFD_RELOC_MIPS_GOT16:
15477 case BFD_RELOC_GPREL32:
15478 case BFD_RELOC_MIPS_GOT_HI16:
15479 case BFD_RELOC_MIPS_GOT_LO16:
15480 case BFD_RELOC_MIPS_CALL_HI16:
15481 case BFD_RELOC_MIPS_CALL_LO16:
15482 case BFD_RELOC_MIPS16_GPREL:
15483 case BFD_RELOC_MIPS16_GOT16:
15484 case BFD_RELOC_MIPS16_CALL16:
15485 case BFD_RELOC_MIPS16_HI16:
15486 case BFD_RELOC_MIPS16_HI16_S:
15487 case BFD_RELOC_MIPS16_JMP:
15488 case BFD_RELOC_MICROMIPS_JMP:
15489 case BFD_RELOC_MICROMIPS_GOT_DISP:
15490 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15491 case BFD_RELOC_MICROMIPS_GOT_OFST:
15492 case BFD_RELOC_MICROMIPS_SUB:
15493 case BFD_RELOC_MICROMIPS_HIGHEST:
15494 case BFD_RELOC_MICROMIPS_HIGHER:
15495 case BFD_RELOC_MICROMIPS_SCN_DISP:
15496 case BFD_RELOC_MICROMIPS_JALR:
15497 case BFD_RELOC_MICROMIPS_HI16:
15498 case BFD_RELOC_MICROMIPS_HI16_S:
15499 case BFD_RELOC_MICROMIPS_GPREL16:
15500 case BFD_RELOC_MICROMIPS_LITERAL:
15501 case BFD_RELOC_MICROMIPS_CALL16:
15502 case BFD_RELOC_MICROMIPS_GOT16:
15503 case BFD_RELOC_MICROMIPS_GOT_HI16:
15504 case BFD_RELOC_MICROMIPS_GOT_LO16:
15505 case BFD_RELOC_MICROMIPS_CALL_HI16:
15506 case BFD_RELOC_MICROMIPS_CALL_LO16:
15507 /* Nothing needed to do. The value comes from the reloc entry. */
15511 /* This is handled like BFD_RELOC_32, but we output a sign
15512 extended value if we are only 32 bits. */
15515 if (8 <= sizeof (valueT))
15516 md_number_to_chars ((char *) buf, *valP, 8);
15521 if ((*valP & 0x80000000) != 0)
15525 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
15527 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
15533 case BFD_RELOC_RVA:
15536 /* If we are deleting this reloc entry, we must fill in the
15537 value now. This can happen if we have a .word which is not
15538 resolved when it appears but is later defined. */
15540 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
15543 case BFD_RELOC_LO16:
15544 case BFD_RELOC_MIPS16_LO16:
15545 case BFD_RELOC_MICROMIPS_LO16:
15546 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15547 may be safe to remove, but if so it's not obvious. */
15548 /* When handling an embedded PIC switch statement, we can wind
15549 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15552 if (*valP + 0x8000 > 0xffff)
15553 as_bad_where (fixP->fx_file, fixP->fx_line,
15554 _("relocation overflow"));
15555 /* 32-bit microMIPS instructions are divided into two halfwords.
15556 Relocations always refer to the second halfword, regardless
15558 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
15560 md_number_to_chars ((char *) buf, *valP, 2);
15564 case BFD_RELOC_16_PCREL_S2:
15565 if ((*valP & 0x3) != 0)
15566 as_bad_where (fixP->fx_file, fixP->fx_line,
15567 _("Branch to misaligned address (%lx)"), (long) *valP);
15569 /* We need to save the bits in the instruction since fixup_segment()
15570 might be deleting the relocation entry (i.e., a branch within
15571 the current segment). */
15572 if (! fixP->fx_done)
15575 /* Update old instruction data. */
15576 if (target_big_endian)
15577 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
15579 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
15581 if (*valP + 0x20000 <= 0x3ffff)
15583 insn |= (*valP >> 2) & 0xffff;
15584 md_number_to_chars ((char *) buf, insn, 4);
15586 else if (mips_pic == NO_PIC
15588 && fixP->fx_frag->fr_address >= text_section->vma
15589 && (fixP->fx_frag->fr_address
15590 < text_section->vma + bfd_get_section_size (text_section))
15591 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15592 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15593 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15595 /* The branch offset is too large. If this is an
15596 unconditional branch, and we are not generating PIC code,
15597 we can convert it to an absolute jump instruction. */
15598 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15599 insn = 0x0c000000; /* jal */
15601 insn = 0x08000000; /* j */
15602 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15604 fixP->fx_addsy = section_symbol (text_section);
15605 *valP += md_pcrel_from (fixP);
15606 md_number_to_chars ((char *) buf, insn, 4);
15610 /* If we got here, we have branch-relaxation disabled,
15611 and there's nothing we can do to fix this instruction
15612 without turning it into a longer sequence. */
15613 as_bad_where (fixP->fx_file, fixP->fx_line,
15614 _("Branch out of range"));
15618 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15619 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15620 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15621 /* We adjust the offset back to even. */
15622 if ((*valP & 0x1) != 0)
15625 if (! fixP->fx_done)
15628 /* Should never visit here, because we keep the relocation. */
15632 case BFD_RELOC_VTABLE_INHERIT:
15635 && !S_IS_DEFINED (fixP->fx_addsy)
15636 && !S_IS_WEAK (fixP->fx_addsy))
15637 S_SET_WEAK (fixP->fx_addsy);
15640 case BFD_RELOC_VTABLE_ENTRY:
15648 /* Remember value for tc_gen_reloc. */
15649 fixP->fx_addnumber = *valP;
15659 name = input_line_pointer;
15660 c = get_symbol_end ();
15661 p = (symbolS *) symbol_find_or_make (name);
15662 *input_line_pointer = c;
15666 /* Align the current frag to a given power of two. If a particular
15667 fill byte should be used, FILL points to an integer that contains
15668 that byte, otherwise FILL is null.
15670 This function used to have the comment:
15672 The MIPS assembler also automatically adjusts any preceding label.
15674 The implementation therefore applied the adjustment to a maximum of
15675 one label. However, other label adjustments are applied to batches
15676 of labels, and adjusting just one caused problems when new labels
15677 were added for the sake of debugging or unwind information.
15678 We therefore adjust all preceding labels (given as LABELS) instead. */
15681 mips_align (int to, int *fill, struct insn_label_list *labels)
15683 mips_emit_delays ();
15684 mips_record_compressed_mode ();
15685 if (fill == NULL && subseg_text_p (now_seg))
15686 frag_align_code (to, 0);
15688 frag_align (to, fill ? *fill : 0, 0);
15689 record_alignment (now_seg, to);
15690 mips_move_labels (labels, FALSE);
15693 /* Align to a given power of two. .align 0 turns off the automatic
15694 alignment used by the data creating pseudo-ops. */
15697 s_align (int x ATTRIBUTE_UNUSED)
15699 int temp, fill_value, *fill_ptr;
15700 long max_alignment = 28;
15702 /* o Note that the assembler pulls down any immediately preceding label
15703 to the aligned address.
15704 o It's not documented but auto alignment is reinstated by
15705 a .align pseudo instruction.
15706 o Note also that after auto alignment is turned off the mips assembler
15707 issues an error on attempt to assemble an improperly aligned data item.
15710 temp = get_absolute_expression ();
15711 if (temp > max_alignment)
15712 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15715 as_warn (_("Alignment negative: 0 assumed."));
15718 if (*input_line_pointer == ',')
15720 ++input_line_pointer;
15721 fill_value = get_absolute_expression ();
15722 fill_ptr = &fill_value;
15728 segment_info_type *si = seg_info (now_seg);
15729 struct insn_label_list *l = si->label_list;
15730 /* Auto alignment should be switched on by next section change. */
15732 mips_align (temp, fill_ptr, l);
15739 demand_empty_rest_of_line ();
15743 s_change_sec (int sec)
15748 /* The ELF backend needs to know that we are changing sections, so
15749 that .previous works correctly. We could do something like check
15750 for an obj_section_change_hook macro, but that might be confusing
15751 as it would not be appropriate to use it in the section changing
15752 functions in read.c, since obj-elf.c intercepts those. FIXME:
15753 This should be cleaner, somehow. */
15755 obj_elf_section_change_hook ();
15758 mips_emit_delays ();
15769 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15770 demand_empty_rest_of_line ();
15774 seg = subseg_new (RDATA_SECTION_NAME,
15775 (subsegT) get_absolute_expression ());
15778 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15779 | SEC_READONLY | SEC_RELOC
15781 if (strncmp (TARGET_OS, "elf", 3) != 0)
15782 record_alignment (seg, 4);
15784 demand_empty_rest_of_line ();
15788 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15791 bfd_set_section_flags (stdoutput, seg,
15792 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15793 if (strncmp (TARGET_OS, "elf", 3) != 0)
15794 record_alignment (seg, 4);
15796 demand_empty_rest_of_line ();
15800 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15803 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15804 if (strncmp (TARGET_OS, "elf", 3) != 0)
15805 record_alignment (seg, 4);
15807 demand_empty_rest_of_line ();
15815 s_change_section (int ignore ATTRIBUTE_UNUSED)
15818 char *section_name;
15823 int section_entry_size;
15824 int section_alignment;
15829 section_name = input_line_pointer;
15830 c = get_symbol_end ();
15832 next_c = *(input_line_pointer + 1);
15834 /* Do we have .section Name<,"flags">? */
15835 if (c != ',' || (c == ',' && next_c == '"'))
15837 /* just after name is now '\0'. */
15838 *input_line_pointer = c;
15839 input_line_pointer = section_name;
15840 obj_elf_section (ignore);
15843 input_line_pointer++;
15845 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15847 section_type = get_absolute_expression ();
15850 if (*input_line_pointer++ == ',')
15851 section_flag = get_absolute_expression ();
15854 if (*input_line_pointer++ == ',')
15855 section_entry_size = get_absolute_expression ();
15857 section_entry_size = 0;
15858 if (*input_line_pointer++ == ',')
15859 section_alignment = get_absolute_expression ();
15861 section_alignment = 0;
15862 /* FIXME: really ignore? */
15863 (void) section_alignment;
15865 section_name = xstrdup (section_name);
15867 /* When using the generic form of .section (as implemented by obj-elf.c),
15868 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15869 traditionally had to fall back on the more common @progbits instead.
15871 There's nothing really harmful in this, since bfd will correct
15872 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15873 means that, for backwards compatibility, the special_section entries
15874 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15876 Even so, we shouldn't force users of the MIPS .section syntax to
15877 incorrectly label the sections as SHT_PROGBITS. The best compromise
15878 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15879 generic type-checking code. */
15880 if (section_type == SHT_MIPS_DWARF)
15881 section_type = SHT_PROGBITS;
15883 obj_elf_change_section (section_name, section_type, section_flag,
15884 section_entry_size, 0, 0, 0);
15886 if (now_seg->name != section_name)
15887 free (section_name);
15888 #endif /* OBJ_ELF */
15892 mips_enable_auto_align (void)
15898 s_cons (int log_size)
15900 segment_info_type *si = seg_info (now_seg);
15901 struct insn_label_list *l = si->label_list;
15903 mips_emit_delays ();
15904 if (log_size > 0 && auto_align)
15905 mips_align (log_size, 0, l);
15906 cons (1 << log_size);
15907 mips_clear_insn_labels ();
15911 s_float_cons (int type)
15913 segment_info_type *si = seg_info (now_seg);
15914 struct insn_label_list *l = si->label_list;
15916 mips_emit_delays ();
15921 mips_align (3, 0, l);
15923 mips_align (2, 0, l);
15927 mips_clear_insn_labels ();
15930 /* Handle .globl. We need to override it because on Irix 5 you are
15933 where foo is an undefined symbol, to mean that foo should be
15934 considered to be the address of a function. */
15937 s_mips_globl (int x ATTRIBUTE_UNUSED)
15946 name = input_line_pointer;
15947 c = get_symbol_end ();
15948 symbolP = symbol_find_or_make (name);
15949 S_SET_EXTERNAL (symbolP);
15951 *input_line_pointer = c;
15952 SKIP_WHITESPACE ();
15954 /* On Irix 5, every global symbol that is not explicitly labelled as
15955 being a function is apparently labelled as being an object. */
15958 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15959 && (*input_line_pointer != ','))
15964 secname = input_line_pointer;
15965 c = get_symbol_end ();
15966 sec = bfd_get_section_by_name (stdoutput, secname);
15968 as_bad (_("%s: no such section"), secname);
15969 *input_line_pointer = c;
15971 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15972 flag = BSF_FUNCTION;
15975 symbol_get_bfdsym (symbolP)->flags |= flag;
15977 c = *input_line_pointer;
15980 input_line_pointer++;
15981 SKIP_WHITESPACE ();
15982 if (is_end_of_line[(unsigned char) *input_line_pointer])
15988 demand_empty_rest_of_line ();
15992 s_option (int x ATTRIBUTE_UNUSED)
15997 opt = input_line_pointer;
15998 c = get_symbol_end ();
16002 /* FIXME: What does this mean? */
16004 else if (strncmp (opt, "pic", 3) == 0)
16008 i = atoi (opt + 3);
16013 mips_pic = SVR4_PIC;
16014 mips_abicalls = TRUE;
16017 as_bad (_(".option pic%d not supported"), i);
16019 if (mips_pic == SVR4_PIC)
16021 if (g_switch_seen && g_switch_value != 0)
16022 as_warn (_("-G may not be used with SVR4 PIC code"));
16023 g_switch_value = 0;
16024 bfd_set_gp_size (stdoutput, 0);
16028 as_warn (_("Unrecognized option \"%s\""), opt);
16030 *input_line_pointer = c;
16031 demand_empty_rest_of_line ();
16034 /* This structure is used to hold a stack of .set values. */
16036 struct mips_option_stack
16038 struct mips_option_stack *next;
16039 struct mips_set_options options;
16042 static struct mips_option_stack *mips_opts_stack;
16044 /* Handle the .set pseudo-op. */
16047 s_mipsset (int x ATTRIBUTE_UNUSED)
16049 char *name = input_line_pointer, ch;
16051 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16052 ++input_line_pointer;
16053 ch = *input_line_pointer;
16054 *input_line_pointer = '\0';
16056 if (strcmp (name, "reorder") == 0)
16058 if (mips_opts.noreorder)
16061 else if (strcmp (name, "noreorder") == 0)
16063 if (!mips_opts.noreorder)
16064 start_noreorder ();
16066 else if (strncmp (name, "at=", 3) == 0)
16068 char *s = name + 3;
16070 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16071 as_bad (_("Unrecognized register name `%s'"), s);
16073 else if (strcmp (name, "at") == 0)
16075 mips_opts.at = ATREG;
16077 else if (strcmp (name, "noat") == 0)
16079 mips_opts.at = ZERO;
16081 else if (strcmp (name, "macro") == 0)
16083 mips_opts.warn_about_macros = 0;
16085 else if (strcmp (name, "nomacro") == 0)
16087 if (mips_opts.noreorder == 0)
16088 as_bad (_("`noreorder' must be set before `nomacro'"));
16089 mips_opts.warn_about_macros = 1;
16091 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16093 mips_opts.nomove = 0;
16095 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16097 mips_opts.nomove = 1;
16099 else if (strcmp (name, "bopt") == 0)
16101 mips_opts.nobopt = 0;
16103 else if (strcmp (name, "nobopt") == 0)
16105 mips_opts.nobopt = 1;
16107 else if (strcmp (name, "gp=default") == 0)
16108 mips_opts.gp32 = file_mips_gp32;
16109 else if (strcmp (name, "gp=32") == 0)
16110 mips_opts.gp32 = 1;
16111 else if (strcmp (name, "gp=64") == 0)
16113 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16114 as_warn (_("%s isa does not support 64-bit registers"),
16115 mips_cpu_info_from_isa (mips_opts.isa)->name);
16116 mips_opts.gp32 = 0;
16118 else if (strcmp (name, "fp=default") == 0)
16119 mips_opts.fp32 = file_mips_fp32;
16120 else if (strcmp (name, "fp=32") == 0)
16121 mips_opts.fp32 = 1;
16122 else if (strcmp (name, "fp=64") == 0)
16124 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16125 as_warn (_("%s isa does not support 64-bit floating point registers"),
16126 mips_cpu_info_from_isa (mips_opts.isa)->name);
16127 mips_opts.fp32 = 0;
16129 else if (strcmp (name, "softfloat") == 0)
16130 mips_opts.soft_float = 1;
16131 else if (strcmp (name, "hardfloat") == 0)
16132 mips_opts.soft_float = 0;
16133 else if (strcmp (name, "singlefloat") == 0)
16134 mips_opts.single_float = 1;
16135 else if (strcmp (name, "doublefloat") == 0)
16136 mips_opts.single_float = 0;
16137 else if (strcmp (name, "mips16") == 0
16138 || strcmp (name, "MIPS-16") == 0)
16140 if (mips_opts.micromips == 1)
16141 as_fatal (_("`mips16' cannot be used with `micromips'"));
16142 mips_opts.mips16 = 1;
16144 else if (strcmp (name, "nomips16") == 0
16145 || strcmp (name, "noMIPS-16") == 0)
16146 mips_opts.mips16 = 0;
16147 else if (strcmp (name, "micromips") == 0)
16149 if (mips_opts.mips16 == 1)
16150 as_fatal (_("`micromips' cannot be used with `mips16'"));
16151 mips_opts.micromips = 1;
16153 else if (strcmp (name, "nomicromips") == 0)
16154 mips_opts.micromips = 0;
16155 else if (strcmp (name, "smartmips") == 0)
16157 if (!ISA_SUPPORTS_SMARTMIPS)
16158 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16159 mips_cpu_info_from_isa (mips_opts.isa)->name);
16160 mips_opts.ase_smartmips = 1;
16162 else if (strcmp (name, "nosmartmips") == 0)
16163 mips_opts.ase_smartmips = 0;
16164 else if (strcmp (name, "mips3d") == 0)
16165 mips_opts.ase_mips3d = 1;
16166 else if (strcmp (name, "nomips3d") == 0)
16167 mips_opts.ase_mips3d = 0;
16168 else if (strcmp (name, "mdmx") == 0)
16169 mips_opts.ase_mdmx = 1;
16170 else if (strcmp (name, "nomdmx") == 0)
16171 mips_opts.ase_mdmx = 0;
16172 else if (strcmp (name, "dsp") == 0)
16174 if (!ISA_SUPPORTS_DSP_ASE)
16175 as_warn (_("%s ISA does not support DSP ASE"),
16176 mips_cpu_info_from_isa (mips_opts.isa)->name);
16177 mips_opts.ase_dsp = 1;
16178 mips_opts.ase_dspr2 = 0;
16180 else if (strcmp (name, "nodsp") == 0)
16182 mips_opts.ase_dsp = 0;
16183 mips_opts.ase_dspr2 = 0;
16185 else if (strcmp (name, "dspr2") == 0)
16187 if (!ISA_SUPPORTS_DSPR2_ASE)
16188 as_warn (_("%s ISA does not support DSP R2 ASE"),
16189 mips_cpu_info_from_isa (mips_opts.isa)->name);
16190 mips_opts.ase_dspr2 = 1;
16191 mips_opts.ase_dsp = 1;
16193 else if (strcmp (name, "nodspr2") == 0)
16195 mips_opts.ase_dspr2 = 0;
16196 mips_opts.ase_dsp = 0;
16198 else if (strcmp (name, "mt") == 0)
16200 if (!ISA_SUPPORTS_MT_ASE)
16201 as_warn (_("%s ISA does not support MT ASE"),
16202 mips_cpu_info_from_isa (mips_opts.isa)->name);
16203 mips_opts.ase_mt = 1;
16205 else if (strcmp (name, "nomt") == 0)
16206 mips_opts.ase_mt = 0;
16207 else if (strcmp (name, "mcu") == 0)
16208 mips_opts.ase_mcu = 1;
16209 else if (strcmp (name, "nomcu") == 0)
16210 mips_opts.ase_mcu = 0;
16211 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16215 /* Permit the user to change the ISA and architecture on the fly.
16216 Needless to say, misuse can cause serious problems. */
16217 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16220 mips_opts.isa = file_mips_isa;
16221 mips_opts.arch = file_mips_arch;
16223 else if (strncmp (name, "arch=", 5) == 0)
16225 const struct mips_cpu_info *p;
16227 p = mips_parse_cpu("internal use", name + 5);
16229 as_bad (_("unknown architecture %s"), name + 5);
16232 mips_opts.arch = p->cpu;
16233 mips_opts.isa = p->isa;
16236 else if (strncmp (name, "mips", 4) == 0)
16238 const struct mips_cpu_info *p;
16240 p = mips_parse_cpu("internal use", name);
16242 as_bad (_("unknown ISA level %s"), name + 4);
16245 mips_opts.arch = p->cpu;
16246 mips_opts.isa = p->isa;
16250 as_bad (_("unknown ISA or architecture %s"), name);
16252 switch (mips_opts.isa)
16260 mips_opts.gp32 = 1;
16261 mips_opts.fp32 = 1;
16268 mips_opts.gp32 = 0;
16269 mips_opts.fp32 = 0;
16272 as_bad (_("unknown ISA level %s"), name + 4);
16277 mips_opts.gp32 = file_mips_gp32;
16278 mips_opts.fp32 = file_mips_fp32;
16281 else if (strcmp (name, "autoextend") == 0)
16282 mips_opts.noautoextend = 0;
16283 else if (strcmp (name, "noautoextend") == 0)
16284 mips_opts.noautoextend = 1;
16285 else if (strcmp (name, "push") == 0)
16287 struct mips_option_stack *s;
16289 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16290 s->next = mips_opts_stack;
16291 s->options = mips_opts;
16292 mips_opts_stack = s;
16294 else if (strcmp (name, "pop") == 0)
16296 struct mips_option_stack *s;
16298 s = mips_opts_stack;
16300 as_bad (_(".set pop with no .set push"));
16303 /* If we're changing the reorder mode we need to handle
16304 delay slots correctly. */
16305 if (s->options.noreorder && ! mips_opts.noreorder)
16306 start_noreorder ();
16307 else if (! s->options.noreorder && mips_opts.noreorder)
16310 mips_opts = s->options;
16311 mips_opts_stack = s->next;
16315 else if (strcmp (name, "sym32") == 0)
16316 mips_opts.sym32 = TRUE;
16317 else if (strcmp (name, "nosym32") == 0)
16318 mips_opts.sym32 = FALSE;
16319 else if (strchr (name, ','))
16321 /* Generic ".set" directive; use the generic handler. */
16322 *input_line_pointer = ch;
16323 input_line_pointer = name;
16329 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16331 *input_line_pointer = ch;
16332 demand_empty_rest_of_line ();
16335 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16336 .option pic2. It means to generate SVR4 PIC calls. */
16339 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16341 mips_pic = SVR4_PIC;
16342 mips_abicalls = TRUE;
16344 if (g_switch_seen && g_switch_value != 0)
16345 as_warn (_("-G may not be used with SVR4 PIC code"));
16346 g_switch_value = 0;
16348 bfd_set_gp_size (stdoutput, 0);
16349 demand_empty_rest_of_line ();
16352 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16353 PIC code. It sets the $gp register for the function based on the
16354 function address, which is in the register named in the argument.
16355 This uses a relocation against _gp_disp, which is handled specially
16356 by the linker. The result is:
16357 lui $gp,%hi(_gp_disp)
16358 addiu $gp,$gp,%lo(_gp_disp)
16359 addu $gp,$gp,.cpload argument
16360 The .cpload argument is normally $25 == $t9.
16362 The -mno-shared option changes this to:
16363 lui $gp,%hi(__gnu_local_gp)
16364 addiu $gp,$gp,%lo(__gnu_local_gp)
16365 and the argument is ignored. This saves an instruction, but the
16366 resulting code is not position independent; it uses an absolute
16367 address for __gnu_local_gp. Thus code assembled with -mno-shared
16368 can go into an ordinary executable, but not into a shared library. */
16371 s_cpload (int ignore ATTRIBUTE_UNUSED)
16377 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16378 .cpload is ignored. */
16379 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16385 if (mips_opts.mips16)
16387 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16388 ignore_rest_of_line ();
16392 /* .cpload should be in a .set noreorder section. */
16393 if (mips_opts.noreorder == 0)
16394 as_warn (_(".cpload not in noreorder section"));
16396 reg = tc_get_register (0);
16398 /* If we need to produce a 64-bit address, we are better off using
16399 the default instruction sequence. */
16400 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16402 ex.X_op = O_symbol;
16403 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16405 ex.X_op_symbol = NULL;
16406 ex.X_add_number = 0;
16408 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16409 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16412 macro_build_lui (&ex, mips_gp_register);
16413 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16414 mips_gp_register, BFD_RELOC_LO16);
16416 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16417 mips_gp_register, reg);
16420 demand_empty_rest_of_line ();
16423 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16424 .cpsetup $reg1, offset|$reg2, label
16426 If offset is given, this results in:
16427 sd $gp, offset($sp)
16428 lui $gp, %hi(%neg(%gp_rel(label)))
16429 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16430 daddu $gp, $gp, $reg1
16432 If $reg2 is given, this results in:
16433 daddu $reg2, $gp, $0
16434 lui $gp, %hi(%neg(%gp_rel(label)))
16435 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16436 daddu $gp, $gp, $reg1
16437 $reg1 is normally $25 == $t9.
16439 The -mno-shared option replaces the last three instructions with
16441 addiu $gp,$gp,%lo(_gp) */
16444 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16446 expressionS ex_off;
16447 expressionS ex_sym;
16450 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16451 We also need NewABI support. */
16452 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16458 if (mips_opts.mips16)
16460 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16461 ignore_rest_of_line ();
16465 reg1 = tc_get_register (0);
16466 SKIP_WHITESPACE ();
16467 if (*input_line_pointer != ',')
16469 as_bad (_("missing argument separator ',' for .cpsetup"));
16473 ++input_line_pointer;
16474 SKIP_WHITESPACE ();
16475 if (*input_line_pointer == '$')
16477 mips_cpreturn_register = tc_get_register (0);
16478 mips_cpreturn_offset = -1;
16482 mips_cpreturn_offset = get_absolute_expression ();
16483 mips_cpreturn_register = -1;
16485 SKIP_WHITESPACE ();
16486 if (*input_line_pointer != ',')
16488 as_bad (_("missing argument separator ',' for .cpsetup"));
16492 ++input_line_pointer;
16493 SKIP_WHITESPACE ();
16494 expression (&ex_sym);
16497 if (mips_cpreturn_register == -1)
16499 ex_off.X_op = O_constant;
16500 ex_off.X_add_symbol = NULL;
16501 ex_off.X_op_symbol = NULL;
16502 ex_off.X_add_number = mips_cpreturn_offset;
16504 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16505 BFD_RELOC_LO16, SP);
16508 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16509 mips_gp_register, 0);
16511 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16513 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16514 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16517 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16518 mips_gp_register, -1, BFD_RELOC_GPREL16,
16519 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16521 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16522 mips_gp_register, reg1);
16528 ex.X_op = O_symbol;
16529 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16530 ex.X_op_symbol = NULL;
16531 ex.X_add_number = 0;
16533 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16534 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16536 macro_build_lui (&ex, mips_gp_register);
16537 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16538 mips_gp_register, BFD_RELOC_LO16);
16543 demand_empty_rest_of_line ();
16547 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16549 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16550 .cplocal is ignored. */
16551 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16557 if (mips_opts.mips16)
16559 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16560 ignore_rest_of_line ();
16564 mips_gp_register = tc_get_register (0);
16565 demand_empty_rest_of_line ();
16568 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16569 offset from $sp. The offset is remembered, and after making a PIC
16570 call $gp is restored from that location. */
16573 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16577 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16578 .cprestore is ignored. */
16579 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16585 if (mips_opts.mips16)
16587 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16588 ignore_rest_of_line ();
16592 mips_cprestore_offset = get_absolute_expression ();
16593 mips_cprestore_valid = 1;
16595 ex.X_op = O_constant;
16596 ex.X_add_symbol = NULL;
16597 ex.X_op_symbol = NULL;
16598 ex.X_add_number = mips_cprestore_offset;
16601 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16602 SP, HAVE_64BIT_ADDRESSES);
16605 demand_empty_rest_of_line ();
16608 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16609 was given in the preceding .cpsetup, it results in:
16610 ld $gp, offset($sp)
16612 If a register $reg2 was given there, it results in:
16613 daddu $gp, $reg2, $0 */
16616 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16620 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16621 We also need NewABI support. */
16622 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16628 if (mips_opts.mips16)
16630 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16631 ignore_rest_of_line ();
16636 if (mips_cpreturn_register == -1)
16638 ex.X_op = O_constant;
16639 ex.X_add_symbol = NULL;
16640 ex.X_op_symbol = NULL;
16641 ex.X_add_number = mips_cpreturn_offset;
16643 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16646 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16647 mips_cpreturn_register, 0);
16650 demand_empty_rest_of_line ();
16653 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16654 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16655 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16656 debug information or MIPS16 TLS. */
16659 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16660 bfd_reloc_code_real_type rtype)
16667 if (ex.X_op != O_symbol)
16669 as_bad (_("Unsupported use of %s"), dirstr);
16670 ignore_rest_of_line ();
16673 p = frag_more (bytes);
16674 md_number_to_chars (p, 0, bytes);
16675 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16676 demand_empty_rest_of_line ();
16677 mips_clear_insn_labels ();
16680 /* Handle .dtprelword. */
16683 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16685 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16688 /* Handle .dtpreldword. */
16691 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16693 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16696 /* Handle .tprelword. */
16699 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16701 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16704 /* Handle .tpreldword. */
16707 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16709 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16712 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16713 code. It sets the offset to use in gp_rel relocations. */
16716 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16718 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16719 We also need NewABI support. */
16720 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16726 mips_gprel_offset = get_absolute_expression ();
16728 demand_empty_rest_of_line ();
16731 /* Handle the .gpword pseudo-op. This is used when generating PIC
16732 code. It generates a 32 bit GP relative reloc. */
16735 s_gpword (int ignore ATTRIBUTE_UNUSED)
16737 segment_info_type *si;
16738 struct insn_label_list *l;
16742 /* When not generating PIC code, this is treated as .word. */
16743 if (mips_pic != SVR4_PIC)
16749 si = seg_info (now_seg);
16750 l = si->label_list;
16751 mips_emit_delays ();
16753 mips_align (2, 0, l);
16756 mips_clear_insn_labels ();
16758 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16760 as_bad (_("Unsupported use of .gpword"));
16761 ignore_rest_of_line ();
16765 md_number_to_chars (p, 0, 4);
16766 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16767 BFD_RELOC_GPREL32);
16769 demand_empty_rest_of_line ();
16773 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16775 segment_info_type *si;
16776 struct insn_label_list *l;
16780 /* When not generating PIC code, this is treated as .dword. */
16781 if (mips_pic != SVR4_PIC)
16787 si = seg_info (now_seg);
16788 l = si->label_list;
16789 mips_emit_delays ();
16791 mips_align (3, 0, l);
16794 mips_clear_insn_labels ();
16796 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16798 as_bad (_("Unsupported use of .gpdword"));
16799 ignore_rest_of_line ();
16803 md_number_to_chars (p, 0, 8);
16804 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16805 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16807 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16808 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16809 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16811 demand_empty_rest_of_line ();
16814 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16815 tables in SVR4 PIC code. */
16818 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16822 /* This is ignored when not generating SVR4 PIC code. */
16823 if (mips_pic != SVR4_PIC)
16829 /* Add $gp to the register named as an argument. */
16831 reg = tc_get_register (0);
16832 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16835 demand_empty_rest_of_line ();
16838 /* Handle the .insn pseudo-op. This marks instruction labels in
16839 mips16/micromips mode. This permits the linker to handle them specially,
16840 such as generating jalx instructions when needed. We also make
16841 them odd for the duration of the assembly, in order to generate the
16842 right sort of code. We will make them even in the adjust_symtab
16843 routine, while leaving them marked. This is convenient for the
16844 debugger and the disassembler. The linker knows to make them odd
16848 s_insn (int ignore ATTRIBUTE_UNUSED)
16850 mips_mark_labels ();
16852 demand_empty_rest_of_line ();
16855 /* Handle a .stabn directive. We need these in order to mark a label
16856 as being a mips16 text label correctly. Sometimes the compiler
16857 will emit a label, followed by a .stabn, and then switch sections.
16858 If the label and .stabn are in mips16 mode, then the label is
16859 really a mips16 text label. */
16862 s_mips_stab (int type)
16865 mips_mark_labels ();
16870 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16873 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16880 name = input_line_pointer;
16881 c = get_symbol_end ();
16882 symbolP = symbol_find_or_make (name);
16883 S_SET_WEAK (symbolP);
16884 *input_line_pointer = c;
16886 SKIP_WHITESPACE ();
16888 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16890 if (S_IS_DEFINED (symbolP))
16892 as_bad (_("ignoring attempt to redefine symbol %s"),
16893 S_GET_NAME (symbolP));
16894 ignore_rest_of_line ();
16898 if (*input_line_pointer == ',')
16900 ++input_line_pointer;
16901 SKIP_WHITESPACE ();
16905 if (exp.X_op != O_symbol)
16907 as_bad (_("bad .weakext directive"));
16908 ignore_rest_of_line ();
16911 symbol_set_value_expression (symbolP, &exp);
16914 demand_empty_rest_of_line ();
16917 /* Parse a register string into a number. Called from the ECOFF code
16918 to parse .frame. The argument is non-zero if this is the frame
16919 register, so that we can record it in mips_frame_reg. */
16922 tc_get_register (int frame)
16926 SKIP_WHITESPACE ();
16927 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16931 mips_frame_reg = reg != 0 ? reg : SP;
16932 mips_frame_reg_valid = 1;
16933 mips_cprestore_valid = 0;
16939 md_section_align (asection *seg, valueT addr)
16941 int align = bfd_get_section_alignment (stdoutput, seg);
16945 /* We don't need to align ELF sections to the full alignment.
16946 However, Irix 5 may prefer that we align them at least to a 16
16947 byte boundary. We don't bother to align the sections if we
16948 are targeted for an embedded system. */
16949 if (strncmp (TARGET_OS, "elf", 3) == 0)
16955 return ((addr + (1 << align) - 1) & (-1 << align));
16958 /* Utility routine, called from above as well. If called while the
16959 input file is still being read, it's only an approximation. (For
16960 example, a symbol may later become defined which appeared to be
16961 undefined earlier.) */
16964 nopic_need_relax (symbolS *sym, int before_relaxing)
16969 if (g_switch_value > 0)
16971 const char *symname;
16974 /* Find out whether this symbol can be referenced off the $gp
16975 register. It can be if it is smaller than the -G size or if
16976 it is in the .sdata or .sbss section. Certain symbols can
16977 not be referenced off the $gp, although it appears as though
16979 symname = S_GET_NAME (sym);
16980 if (symname != (const char *) NULL
16981 && (strcmp (symname, "eprol") == 0
16982 || strcmp (symname, "etext") == 0
16983 || strcmp (symname, "_gp") == 0
16984 || strcmp (symname, "edata") == 0
16985 || strcmp (symname, "_fbss") == 0
16986 || strcmp (symname, "_fdata") == 0
16987 || strcmp (symname, "_ftext") == 0
16988 || strcmp (symname, "end") == 0
16989 || strcmp (symname, "_gp_disp") == 0))
16991 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16993 #ifndef NO_ECOFF_DEBUGGING
16994 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16995 && (symbol_get_obj (sym)->ecoff_extern_size
16996 <= g_switch_value))
16998 /* We must defer this decision until after the whole
16999 file has been read, since there might be a .extern
17000 after the first use of this symbol. */
17001 || (before_relaxing
17002 #ifndef NO_ECOFF_DEBUGGING
17003 && symbol_get_obj (sym)->ecoff_extern_size == 0
17005 && S_GET_VALUE (sym) == 0)
17006 || (S_GET_VALUE (sym) != 0
17007 && S_GET_VALUE (sym) <= g_switch_value)))
17011 const char *segname;
17013 segname = segment_name (S_GET_SEGMENT (sym));
17014 gas_assert (strcmp (segname, ".lit8") != 0
17015 && strcmp (segname, ".lit4") != 0);
17016 change = (strcmp (segname, ".sdata") != 0
17017 && strcmp (segname, ".sbss") != 0
17018 && strncmp (segname, ".sdata.", 7) != 0
17019 && strncmp (segname, ".sbss.", 6) != 0
17020 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17021 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17026 /* We are not optimizing for the $gp register. */
17031 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17034 pic_need_relax (symbolS *sym, asection *segtype)
17038 /* Handle the case of a symbol equated to another symbol. */
17039 while (symbol_equated_reloc_p (sym))
17043 /* It's possible to get a loop here in a badly written program. */
17044 n = symbol_get_value_expression (sym)->X_add_symbol;
17050 if (symbol_section_p (sym))
17053 symsec = S_GET_SEGMENT (sym);
17055 /* This must duplicate the test in adjust_reloc_syms. */
17056 return (!bfd_is_und_section (symsec)
17057 && !bfd_is_abs_section (symsec)
17058 && !bfd_is_com_section (symsec)
17059 && !s_is_linkonce (sym, segtype)
17061 /* A global or weak symbol is treated as external. */
17062 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17068 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17069 extended opcode. SEC is the section the frag is in. */
17072 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17075 const struct mips16_immed_operand *op;
17077 int mintiny, maxtiny;
17081 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17083 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17086 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17087 op = mips16_immed_operands;
17088 while (op->type != type)
17091 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17096 if (type == '<' || type == '>' || type == '[' || type == ']')
17099 maxtiny = 1 << op->nbits;
17104 maxtiny = (1 << op->nbits) - 1;
17109 mintiny = - (1 << (op->nbits - 1));
17110 maxtiny = (1 << (op->nbits - 1)) - 1;
17113 sym_frag = symbol_get_frag (fragp->fr_symbol);
17114 val = S_GET_VALUE (fragp->fr_symbol);
17115 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17121 /* We won't have the section when we are called from
17122 mips_relax_frag. However, we will always have been called
17123 from md_estimate_size_before_relax first. If this is a
17124 branch to a different section, we mark it as such. If SEC is
17125 NULL, and the frag is not marked, then it must be a branch to
17126 the same section. */
17129 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17134 /* Must have been called from md_estimate_size_before_relax. */
17137 fragp->fr_subtype =
17138 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17140 /* FIXME: We should support this, and let the linker
17141 catch branches and loads that are out of range. */
17142 as_bad_where (fragp->fr_file, fragp->fr_line,
17143 _("unsupported PC relative reference to different section"));
17147 if (fragp != sym_frag && sym_frag->fr_address == 0)
17148 /* Assume non-extended on the first relaxation pass.
17149 The address we have calculated will be bogus if this is
17150 a forward branch to another frag, as the forward frag
17151 will have fr_address == 0. */
17155 /* In this case, we know for sure that the symbol fragment is in
17156 the same section. If the relax_marker of the symbol fragment
17157 differs from the relax_marker of this fragment, we have not
17158 yet adjusted the symbol fragment fr_address. We want to add
17159 in STRETCH in order to get a better estimate of the address.
17160 This particularly matters because of the shift bits. */
17162 && sym_frag->relax_marker != fragp->relax_marker)
17166 /* Adjust stretch for any alignment frag. Note that if have
17167 been expanding the earlier code, the symbol may be
17168 defined in what appears to be an earlier frag. FIXME:
17169 This doesn't handle the fr_subtype field, which specifies
17170 a maximum number of bytes to skip when doing an
17172 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17174 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17177 stretch = - ((- stretch)
17178 & ~ ((1 << (int) f->fr_offset) - 1));
17180 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17189 addr = fragp->fr_address + fragp->fr_fix;
17191 /* The base address rules are complicated. The base address of
17192 a branch is the following instruction. The base address of a
17193 PC relative load or add is the instruction itself, but if it
17194 is in a delay slot (in which case it can not be extended) use
17195 the address of the instruction whose delay slot it is in. */
17196 if (type == 'p' || type == 'q')
17200 /* If we are currently assuming that this frag should be
17201 extended, then, the current address is two bytes
17203 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17206 /* Ignore the low bit in the target, since it will be set
17207 for a text label. */
17208 if ((val & 1) != 0)
17211 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17213 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17216 val -= addr & ~ ((1 << op->shift) - 1);
17218 /* Branch offsets have an implicit 0 in the lowest bit. */
17219 if (type == 'p' || type == 'q')
17222 /* If any of the shifted bits are set, we must use an extended
17223 opcode. If the address depends on the size of this
17224 instruction, this can lead to a loop, so we arrange to always
17225 use an extended opcode. We only check this when we are in
17226 the main relaxation loop, when SEC is NULL. */
17227 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17229 fragp->fr_subtype =
17230 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17234 /* If we are about to mark a frag as extended because the value
17235 is precisely maxtiny + 1, then there is a chance of an
17236 infinite loop as in the following code:
17241 In this case when the la is extended, foo is 0x3fc bytes
17242 away, so the la can be shrunk, but then foo is 0x400 away, so
17243 the la must be extended. To avoid this loop, we mark the
17244 frag as extended if it was small, and is about to become
17245 extended with a value of maxtiny + 1. */
17246 if (val == ((maxtiny + 1) << op->shift)
17247 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17250 fragp->fr_subtype =
17251 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17255 else if (symsec != absolute_section && sec != NULL)
17256 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17258 if ((val & ((1 << op->shift) - 1)) != 0
17259 || val < (mintiny << op->shift)
17260 || val > (maxtiny << op->shift))
17266 /* Compute the length of a branch sequence, and adjust the
17267 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17268 worst-case length is computed, with UPDATE being used to indicate
17269 whether an unconditional (-1), branch-likely (+1) or regular (0)
17270 branch is to be computed. */
17272 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17274 bfd_boolean toofar;
17278 && S_IS_DEFINED (fragp->fr_symbol)
17279 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17284 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17286 addr = fragp->fr_address + fragp->fr_fix + 4;
17290 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17293 /* If the symbol is not defined or it's in a different segment,
17294 assume the user knows what's going on and emit a short
17300 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17302 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17303 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17304 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17305 RELAX_BRANCH_LINK (fragp->fr_subtype),
17311 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17314 if (mips_pic != NO_PIC)
17316 /* Additional space for PIC loading of target address. */
17318 if (mips_opts.isa == ISA_MIPS1)
17319 /* Additional space for $at-stabilizing nop. */
17323 /* If branch is conditional. */
17324 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17331 /* Compute the length of a branch sequence, and adjust the
17332 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17333 worst-case length is computed, with UPDATE being used to indicate
17334 whether an unconditional (-1), or regular (0) branch is to be
17338 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17340 bfd_boolean toofar;
17344 && S_IS_DEFINED (fragp->fr_symbol)
17345 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17350 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17351 /* Ignore the low bit in the target, since it will be set
17352 for a text label. */
17353 if ((val & 1) != 0)
17356 addr = fragp->fr_address + fragp->fr_fix + 4;
17360 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17363 /* If the symbol is not defined or it's in a different segment,
17364 assume the user knows what's going on and emit a short
17370 if (fragp && update
17371 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17372 fragp->fr_subtype = (toofar
17373 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17374 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17379 bfd_boolean compact_known = fragp != NULL;
17380 bfd_boolean compact = FALSE;
17381 bfd_boolean uncond;
17384 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17386 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17388 uncond = update < 0;
17390 /* If label is out of range, we turn branch <br>:
17392 <br> label # 4 bytes
17398 nop # 2 bytes if compact && !PIC
17401 if (mips_pic == NO_PIC && (!compact_known || compact))
17404 /* If assembling PIC code, we further turn:
17410 lw/ld at, %got(label)(gp) # 4 bytes
17411 d/addiu at, %lo(label) # 4 bytes
17414 if (mips_pic != NO_PIC)
17417 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17419 <brneg> 0f # 4 bytes
17420 nop # 2 bytes if !compact
17423 length += (compact_known && compact) ? 4 : 6;
17429 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17430 bit accordingly. */
17433 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17435 bfd_boolean toofar;
17438 && S_IS_DEFINED (fragp->fr_symbol)
17439 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17445 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17446 /* Ignore the low bit in the target, since it will be set
17447 for a text label. */
17448 if ((val & 1) != 0)
17451 /* Assume this is a 2-byte branch. */
17452 addr = fragp->fr_address + fragp->fr_fix + 2;
17454 /* We try to avoid the infinite loop by not adding 2 more bytes for
17459 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17461 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17462 else if (type == 'E')
17463 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17468 /* If the symbol is not defined or it's in a different segment,
17469 we emit a normal 32-bit branch. */
17472 if (fragp && update
17473 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17475 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17476 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17484 /* Estimate the size of a frag before relaxing. Unless this is the
17485 mips16, we are not really relaxing here, and the final size is
17486 encoded in the subtype information. For the mips16, we have to
17487 decide whether we are using an extended opcode or not. */
17490 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17494 if (RELAX_BRANCH_P (fragp->fr_subtype))
17497 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17499 return fragp->fr_var;
17502 if (RELAX_MIPS16_P (fragp->fr_subtype))
17503 /* We don't want to modify the EXTENDED bit here; it might get us
17504 into infinite loops. We change it only in mips_relax_frag(). */
17505 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17507 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17511 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17512 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17513 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17514 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17515 fragp->fr_var = length;
17520 if (mips_pic == NO_PIC)
17521 change = nopic_need_relax (fragp->fr_symbol, 0);
17522 else if (mips_pic == SVR4_PIC)
17523 change = pic_need_relax (fragp->fr_symbol, segtype);
17524 else if (mips_pic == VXWORKS_PIC)
17525 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17532 fragp->fr_subtype |= RELAX_USE_SECOND;
17533 return -RELAX_FIRST (fragp->fr_subtype);
17536 return -RELAX_SECOND (fragp->fr_subtype);
17539 /* This is called to see whether a reloc against a defined symbol
17540 should be converted into a reloc against a section. */
17543 mips_fix_adjustable (fixS *fixp)
17545 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17546 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17549 if (fixp->fx_addsy == NULL)
17552 /* If symbol SYM is in a mergeable section, relocations of the form
17553 SYM + 0 can usually be made section-relative. The mergeable data
17554 is then identified by the section offset rather than by the symbol.
17556 However, if we're generating REL LO16 relocations, the offset is split
17557 between the LO16 and parterning high part relocation. The linker will
17558 need to recalculate the complete offset in order to correctly identify
17561 The linker has traditionally not looked for the parterning high part
17562 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17563 placed anywhere. Rather than break backwards compatibility by changing
17564 this, it seems better not to force the issue, and instead keep the
17565 original symbol. This will work with either linker behavior. */
17566 if ((lo16_reloc_p (fixp->fx_r_type)
17567 || reloc_needs_lo_p (fixp->fx_r_type))
17568 && HAVE_IN_PLACE_ADDENDS
17569 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17572 /* There is no place to store an in-place offset for JALR relocations.
17573 Likewise an in-range offset of PC-relative relocations may overflow
17574 the in-place relocatable field if recalculated against the start
17575 address of the symbol's containing section. */
17576 if (HAVE_IN_PLACE_ADDENDS
17577 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17581 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17582 to a floating-point stub. The same is true for non-R_MIPS16_26
17583 relocations against MIPS16 functions; in this case, the stub becomes
17584 the function's canonical address.
17586 Floating-point stubs are stored in unique .mips16.call.* or
17587 .mips16.fn.* sections. If a stub T for function F is in section S,
17588 the first relocation in section S must be against F; this is how the
17589 linker determines the target function. All relocations that might
17590 resolve to T must also be against F. We therefore have the following
17591 restrictions, which are given in an intentionally-redundant way:
17593 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17596 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17597 if that stub might be used.
17599 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17602 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17603 that stub might be used.
17605 There is a further restriction:
17607 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17608 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17609 targets with in-place addends; the relocation field cannot
17610 encode the low bit.
17612 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17613 against a MIPS16 symbol. We deal with (5) by by not reducing any
17614 such relocations on REL targets.
17616 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17617 relocation against some symbol R, no relocation against R may be
17618 reduced. (Note that this deals with (2) as well as (1) because
17619 relocations against global symbols will never be reduced on ELF
17620 targets.) This approach is a little simpler than trying to detect
17621 stub sections, and gives the "all or nothing" per-symbol consistency
17622 that we have for MIPS16 symbols. */
17624 && fixp->fx_subsy == NULL
17625 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17626 || *symbol_get_tc (fixp->fx_addsy)
17627 || (HAVE_IN_PLACE_ADDENDS
17628 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17629 && jmp_reloc_p (fixp->fx_r_type))))
17636 /* Translate internal representation of relocation info to BFD target
17640 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17642 static arelent *retval[4];
17644 bfd_reloc_code_real_type code;
17646 memset (retval, 0, sizeof(retval));
17647 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17648 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17649 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17650 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17652 if (fixp->fx_pcrel)
17654 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17655 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17656 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17657 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17659 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17660 Relocations want only the symbol offset. */
17661 reloc->addend = fixp->fx_addnumber + reloc->address;
17664 /* A gruesome hack which is a result of the gruesome gas
17665 reloc handling. What's worse, for COFF (as opposed to
17666 ECOFF), we might need yet another copy of reloc->address.
17667 See bfd_install_relocation. */
17668 reloc->addend += reloc->address;
17672 reloc->addend = fixp->fx_addnumber;
17674 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17675 entry to be used in the relocation's section offset. */
17676 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17678 reloc->address = reloc->addend;
17682 code = fixp->fx_r_type;
17684 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17685 if (reloc->howto == NULL)
17687 as_bad_where (fixp->fx_file, fixp->fx_line,
17688 _("Can not represent %s relocation in this object file format"),
17689 bfd_get_reloc_code_name (code));
17696 /* Relax a machine dependent frag. This returns the amount by which
17697 the current size of the frag should change. */
17700 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17702 if (RELAX_BRANCH_P (fragp->fr_subtype))
17704 offsetT old_var = fragp->fr_var;
17706 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17708 return fragp->fr_var - old_var;
17711 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17713 offsetT old_var = fragp->fr_var;
17714 offsetT new_var = 4;
17716 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17717 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17718 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17719 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17720 fragp->fr_var = new_var;
17722 return new_var - old_var;
17725 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17728 if (mips16_extended_frag (fragp, NULL, stretch))
17730 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17732 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17737 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17739 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17746 /* Convert a machine dependent frag. */
17749 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17751 if (RELAX_BRANCH_P (fragp->fr_subtype))
17754 unsigned long insn;
17758 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
17760 if (target_big_endian)
17761 insn = bfd_getb32 (buf);
17763 insn = bfd_getl32 (buf);
17765 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17767 /* We generate a fixup instead of applying it right now
17768 because, if there are linker relaxations, we're going to
17769 need the relocations. */
17770 exp.X_op = O_symbol;
17771 exp.X_add_symbol = fragp->fr_symbol;
17772 exp.X_add_number = fragp->fr_offset;
17774 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17775 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
17776 fixp->fx_file = fragp->fr_file;
17777 fixp->fx_line = fragp->fr_line;
17779 md_number_to_chars ((char *) buf, insn, 4);
17786 as_warn_where (fragp->fr_file, fragp->fr_line,
17787 _("Relaxed out-of-range branch into a jump"));
17789 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17792 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17794 /* Reverse the branch. */
17795 switch ((insn >> 28) & 0xf)
17798 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17799 have the condition reversed by tweaking a single
17800 bit, and their opcodes all have 0x4???????. */
17801 gas_assert ((insn & 0xf1000000) == 0x41000000);
17802 insn ^= 0x00010000;
17806 /* bltz 0x04000000 bgez 0x04010000
17807 bltzal 0x04100000 bgezal 0x04110000 */
17808 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17809 insn ^= 0x00010000;
17813 /* beq 0x10000000 bne 0x14000000
17814 blez 0x18000000 bgtz 0x1c000000 */
17815 insn ^= 0x04000000;
17823 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17825 /* Clear the and-link bit. */
17826 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17828 /* bltzal 0x04100000 bgezal 0x04110000
17829 bltzall 0x04120000 bgezall 0x04130000 */
17830 insn &= ~0x00100000;
17833 /* Branch over the branch (if the branch was likely) or the
17834 full jump (not likely case). Compute the offset from the
17835 current instruction to branch to. */
17836 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17840 /* How many bytes in instructions we've already emitted? */
17841 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17842 /* How many bytes in instructions from here to the end? */
17843 i = fragp->fr_var - i;
17845 /* Convert to instruction count. */
17847 /* Branch counts from the next instruction. */
17850 /* Branch over the jump. */
17851 md_number_to_chars ((char *) buf, insn, 4);
17855 md_number_to_chars ((char *) buf, 0, 4);
17858 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17860 /* beql $0, $0, 2f */
17862 /* Compute the PC offset from the current instruction to
17863 the end of the variable frag. */
17864 /* How many bytes in instructions we've already emitted? */
17865 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17866 /* How many bytes in instructions from here to the end? */
17867 i = fragp->fr_var - i;
17868 /* Convert to instruction count. */
17870 /* Don't decrement i, because we want to branch over the
17874 md_number_to_chars ((char *) buf, insn, 4);
17877 md_number_to_chars ((char *) buf, 0, 4);
17882 if (mips_pic == NO_PIC)
17885 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17886 ? 0x0c000000 : 0x08000000);
17887 exp.X_op = O_symbol;
17888 exp.X_add_symbol = fragp->fr_symbol;
17889 exp.X_add_number = fragp->fr_offset;
17891 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17892 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
17893 fixp->fx_file = fragp->fr_file;
17894 fixp->fx_line = fragp->fr_line;
17896 md_number_to_chars ((char *) buf, insn, 4);
17901 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17903 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17904 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17905 insn |= at << OP_SH_RT;
17906 exp.X_op = O_symbol;
17907 exp.X_add_symbol = fragp->fr_symbol;
17908 exp.X_add_number = fragp->fr_offset;
17910 if (fragp->fr_offset)
17912 exp.X_add_symbol = make_expr_symbol (&exp);
17913 exp.X_add_number = 0;
17916 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17917 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
17918 fixp->fx_file = fragp->fr_file;
17919 fixp->fx_line = fragp->fr_line;
17921 md_number_to_chars ((char *) buf, insn, 4);
17924 if (mips_opts.isa == ISA_MIPS1)
17927 md_number_to_chars ((char *) buf, 0, 4);
17931 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17932 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17933 insn |= at << OP_SH_RS | at << OP_SH_RT;
17935 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17936 4, &exp, FALSE, BFD_RELOC_LO16);
17937 fixp->fx_file = fragp->fr_file;
17938 fixp->fx_line = fragp->fr_line;
17940 md_number_to_chars ((char *) buf, insn, 4);
17944 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17948 insn |= at << OP_SH_RS;
17950 md_number_to_chars ((char *) buf, insn, 4);
17955 gas_assert (buf == (bfd_byte *)fragp->fr_literal
17956 + fragp->fr_fix + fragp->fr_var);
17958 fragp->fr_fix += fragp->fr_var;
17963 /* Relax microMIPS branches. */
17964 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17966 bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
17967 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17968 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17969 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17970 bfd_boolean short_ds;
17971 unsigned long insn;
17975 exp.X_op = O_symbol;
17976 exp.X_add_symbol = fragp->fr_symbol;
17977 exp.X_add_number = fragp->fr_offset;
17979 fragp->fr_fix += fragp->fr_var;
17981 /* Handle 16-bit branches that fit or are forced to fit. */
17982 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17984 /* We generate a fixup instead of applying it right now,
17985 because if there is linker relaxation, we're going to
17986 need the relocations. */
17988 fixp = fix_new_exp (fragp,
17989 buf - (bfd_byte *) fragp->fr_literal,
17991 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17992 else if (type == 'E')
17993 fixp = fix_new_exp (fragp,
17994 buf - (bfd_byte *) fragp->fr_literal,
17996 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18000 fixp->fx_file = fragp->fr_file;
18001 fixp->fx_line = fragp->fr_line;
18003 /* These relocations can have an addend that won't fit in
18005 fixp->fx_no_overflow = 1;
18010 /* Handle 32-bit branches that fit or are forced to fit. */
18011 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18012 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18014 /* We generate a fixup instead of applying it right now,
18015 because if there is linker relaxation, we're going to
18016 need the relocations. */
18017 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18018 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18019 fixp->fx_file = fragp->fr_file;
18020 fixp->fx_line = fragp->fr_line;
18026 /* Relax 16-bit branches to 32-bit branches. */
18029 if (target_big_endian)
18030 insn = bfd_getb16 (buf);
18032 insn = bfd_getl16 (buf);
18034 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18035 insn = 0x94000000; /* beq */
18036 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18038 unsigned long regno;
18040 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18041 regno = micromips_to_32_reg_d_map [regno];
18042 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18043 insn |= regno << MICROMIPSOP_SH_RS;
18048 /* Nothing else to do, just write it out. */
18049 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18050 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18052 md_number_to_chars ((char *) buf, insn >> 16, 2);
18054 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18057 gas_assert (buf == ((bfd_byte *) fragp->fr_literal
18064 unsigned long next;
18066 if (target_big_endian)
18068 insn = bfd_getb16 (buf);
18069 next = bfd_getb16 (buf + 2);
18073 insn = bfd_getl16 (buf);
18074 next = bfd_getl16 (buf + 2);
18076 insn = (insn << 16) | next;
18079 /* Relax 32-bit branches to a sequence of instructions. */
18080 as_warn_where (fragp->fr_file, fragp->fr_line,
18081 _("Relaxed out-of-range branch into a jump"));
18083 /* Set the short-delay-slot bit. */
18084 short_ds = al && (insn & 0x02000000) != 0;
18086 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18090 /* Reverse the branch. */
18091 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18092 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18093 insn ^= 0x20000000;
18094 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18095 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18096 || (insn & 0xffe00000) == 0x40800000 /* blez */
18097 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18098 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18099 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18100 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18101 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18102 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18103 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18104 insn ^= 0x00400000;
18105 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18106 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18107 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18108 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18109 insn ^= 0x00200000;
18115 /* Clear the and-link and short-delay-slot bits. */
18116 gas_assert ((insn & 0xfda00000) == 0x40200000);
18118 /* bltzal 0x40200000 bgezal 0x40600000 */
18119 /* bltzals 0x42200000 bgezals 0x42600000 */
18120 insn &= ~0x02200000;
18123 /* Make a label at the end for use with the branch. */
18124 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18125 micromips_label_inc ();
18126 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18128 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18132 fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
18133 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18134 fixp->fx_file = fragp->fr_file;
18135 fixp->fx_line = fragp->fr_line;
18137 /* Branch over the jump. */
18138 md_number_to_chars ((char *) buf, insn >> 16, 2);
18140 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18147 md_number_to_chars ((char *) buf, insn, 2);
18152 if (mips_pic == NO_PIC)
18154 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18156 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18157 insn = al ? jal : 0xd4000000;
18159 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18160 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
18161 fixp->fx_file = fragp->fr_file;
18162 fixp->fx_line = fragp->fr_line;
18164 md_number_to_chars ((char *) buf, insn >> 16, 2);
18166 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18173 md_number_to_chars ((char *) buf, insn, 2);
18179 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18180 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18181 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18183 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18184 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18185 insn |= at << MICROMIPSOP_SH_RT;
18187 if (exp.X_add_number)
18189 exp.X_add_symbol = make_expr_symbol (&exp);
18190 exp.X_add_number = 0;
18193 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18194 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
18195 fixp->fx_file = fragp->fr_file;
18196 fixp->fx_line = fragp->fr_line;
18198 md_number_to_chars ((char *) buf, insn >> 16, 2);
18200 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18203 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18204 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18205 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18207 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18208 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
18209 fixp->fx_file = fragp->fr_file;
18210 fixp->fx_line = fragp->fr_line;
18212 md_number_to_chars ((char *) buf, insn >> 16, 2);
18214 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18217 /* jr/jrc/jalr/jalrs $at */
18218 insn = al ? jalr : jr;
18219 insn |= at << MICROMIPSOP_SH_MJ;
18221 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18225 gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
18229 if (RELAX_MIPS16_P (fragp->fr_subtype))
18232 const struct mips16_immed_operand *op;
18235 unsigned int user_length, length;
18236 unsigned long insn;
18239 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18240 op = mips16_immed_operands;
18241 while (op->type != type)
18244 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18245 val = resolve_symbol_value (fragp->fr_symbol);
18250 addr = fragp->fr_address + fragp->fr_fix;
18252 /* The rules for the base address of a PC relative reloc are
18253 complicated; see mips16_extended_frag. */
18254 if (type == 'p' || type == 'q')
18259 /* Ignore the low bit in the target, since it will be
18260 set for a text label. */
18261 if ((val & 1) != 0)
18264 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18266 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18269 addr &= ~ (addressT) ((1 << op->shift) - 1);
18272 /* Make sure the section winds up with the alignment we have
18275 record_alignment (asec, op->shift);
18279 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18280 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18281 as_warn_where (fragp->fr_file, fragp->fr_line,
18282 _("extended instruction in delay slot"));
18284 buf = fragp->fr_literal + fragp->fr_fix;
18286 if (target_big_endian)
18287 insn = bfd_getb16 ((bfd_byte *) buf);
18289 insn = bfd_getl16 ((bfd_byte *) buf);
18292 insn |= MIPS16_EXTEND;
18294 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18296 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18301 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
18302 user_length, &insn);
18304 length = (ext ? 4 : 2);
18305 gas_assert (mips16_opcode_length (insn) == length);
18306 write_compressed_insn (buf, insn, length);
18307 fragp->fr_fix += length;
18311 relax_substateT subtype = fragp->fr_subtype;
18312 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18313 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18317 first = RELAX_FIRST (subtype);
18318 second = RELAX_SECOND (subtype);
18319 fixp = (fixS *) fragp->fr_opcode;
18321 /* If the delay slot chosen does not match the size of the instruction,
18322 then emit a warning. */
18323 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18324 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18329 s = subtype & (RELAX_DELAY_SLOT_16BIT
18330 | RELAX_DELAY_SLOT_SIZE_FIRST
18331 | RELAX_DELAY_SLOT_SIZE_SECOND);
18332 msg = macro_warning (s);
18334 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18338 /* Possibly emit a warning if we've chosen the longer option. */
18339 if (use_second == second_longer)
18345 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18346 msg = macro_warning (s);
18348 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18352 /* Go through all the fixups for the first sequence. Disable them
18353 (by marking them as done) if we're going to use the second
18354 sequence instead. */
18356 && fixp->fx_frag == fragp
18357 && fixp->fx_where < fragp->fr_fix - second)
18359 if (subtype & RELAX_USE_SECOND)
18361 fixp = fixp->fx_next;
18364 /* Go through the fixups for the second sequence. Disable them if
18365 we're going to use the first sequence, otherwise adjust their
18366 addresses to account for the relaxation. */
18367 while (fixp && fixp->fx_frag == fragp)
18369 if (subtype & RELAX_USE_SECOND)
18370 fixp->fx_where -= first;
18373 fixp = fixp->fx_next;
18376 /* Now modify the frag contents. */
18377 if (subtype & RELAX_USE_SECOND)
18381 start = fragp->fr_literal + fragp->fr_fix - first - second;
18382 memmove (start, start + first, second);
18383 fragp->fr_fix -= first;
18386 fragp->fr_fix -= second;
18392 /* This function is called after the relocs have been generated.
18393 We've been storing mips16 text labels as odd. Here we convert them
18394 back to even for the convenience of the debugger. */
18397 mips_frob_file_after_relocs (void)
18400 unsigned int count, i;
18405 syms = bfd_get_outsymbols (stdoutput);
18406 count = bfd_get_symcount (stdoutput);
18407 for (i = 0; i < count; i++, syms++)
18408 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18409 && ((*syms)->value & 1) != 0)
18411 (*syms)->value &= ~1;
18412 /* If the symbol has an odd size, it was probably computed
18413 incorrectly, so adjust that as well. */
18414 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18415 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18421 /* This function is called whenever a label is defined, including fake
18422 labels instantiated off the dot special symbol. It is used when
18423 handling branch delays; if a branch has a label, we assume we cannot
18424 move it. This also bumps the value of the symbol by 1 in compressed
18428 mips_record_label (symbolS *sym)
18430 segment_info_type *si = seg_info (now_seg);
18431 struct insn_label_list *l;
18433 if (free_insn_labels == NULL)
18434 l = (struct insn_label_list *) xmalloc (sizeof *l);
18437 l = free_insn_labels;
18438 free_insn_labels = l->next;
18442 l->next = si->label_list;
18443 si->label_list = l;
18446 /* This function is called as tc_frob_label() whenever a label is defined
18447 and adds a DWARF-2 record we only want for true labels. */
18450 mips_define_label (symbolS *sym)
18452 mips_record_label (sym);
18454 dwarf2_emit_label (sym);
18458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18460 /* Some special processing for a MIPS ELF file. */
18463 mips_elf_final_processing (void)
18465 /* Write out the register information. */
18466 if (mips_abi != N64_ABI)
18470 s.ri_gprmask = mips_gprmask;
18471 s.ri_cprmask[0] = mips_cprmask[0];
18472 s.ri_cprmask[1] = mips_cprmask[1];
18473 s.ri_cprmask[2] = mips_cprmask[2];
18474 s.ri_cprmask[3] = mips_cprmask[3];
18475 /* The gp_value field is set by the MIPS ELF backend. */
18477 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18478 ((Elf32_External_RegInfo *)
18479 mips_regmask_frag));
18483 Elf64_Internal_RegInfo s;
18485 s.ri_gprmask = mips_gprmask;
18487 s.ri_cprmask[0] = mips_cprmask[0];
18488 s.ri_cprmask[1] = mips_cprmask[1];
18489 s.ri_cprmask[2] = mips_cprmask[2];
18490 s.ri_cprmask[3] = mips_cprmask[3];
18491 /* The gp_value field is set by the MIPS ELF backend. */
18493 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18494 ((Elf64_External_RegInfo *)
18495 mips_regmask_frag));
18498 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18499 sort of BFD interface for this. */
18500 if (mips_any_noreorder)
18501 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18502 if (mips_pic != NO_PIC)
18504 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18505 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18508 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18510 /* Set MIPS ELF flags for ASEs. */
18511 /* We may need to define a new flag for DSP ASE, and set this flag when
18512 file_ase_dsp is true. */
18513 /* Same for DSP R2. */
18514 /* We may need to define a new flag for MT ASE, and set this flag when
18515 file_ase_mt is true. */
18516 if (file_ase_mips16)
18517 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18518 if (file_ase_micromips)
18519 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18520 #if 0 /* XXX FIXME */
18521 if (file_ase_mips3d)
18522 elf_elfheader (stdoutput)->e_flags |= ???;
18525 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18527 /* Set the MIPS ELF ABI flags. */
18528 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18529 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18530 else if (mips_abi == O64_ABI)
18531 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18532 else if (mips_abi == EABI_ABI)
18534 if (!file_mips_gp32)
18535 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18537 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18539 else if (mips_abi == N32_ABI)
18540 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18542 /* Nothing to do for N64_ABI. */
18544 if (mips_32bitmode)
18545 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18547 #if 0 /* XXX FIXME */
18548 /* 32 bit code with 64 bit FP registers. */
18549 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18550 elf_elfheader (stdoutput)->e_flags |= ???;
18554 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18556 typedef struct proc {
18558 symbolS *func_end_sym;
18559 unsigned long reg_mask;
18560 unsigned long reg_offset;
18561 unsigned long fpreg_mask;
18562 unsigned long fpreg_offset;
18563 unsigned long frame_offset;
18564 unsigned long frame_reg;
18565 unsigned long pc_reg;
18568 static procS cur_proc;
18569 static procS *cur_proc_ptr;
18570 static int numprocs;
18572 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18573 as "2", and a normal nop as "0". */
18575 #define NOP_OPCODE_MIPS 0
18576 #define NOP_OPCODE_MIPS16 1
18577 #define NOP_OPCODE_MICROMIPS 2
18580 mips_nop_opcode (void)
18582 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18583 return NOP_OPCODE_MICROMIPS;
18584 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18585 return NOP_OPCODE_MIPS16;
18587 return NOP_OPCODE_MIPS;
18590 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18591 32-bit microMIPS NOPs here (if applicable). */
18594 mips_handle_align (fragS *fragp)
18598 int bytes, size, excess;
18601 if (fragp->fr_type != rs_align_code)
18604 p = fragp->fr_literal + fragp->fr_fix;
18606 switch (nop_opcode)
18608 case NOP_OPCODE_MICROMIPS:
18609 opcode = micromips_nop32_insn.insn_opcode;
18612 case NOP_OPCODE_MIPS16:
18613 opcode = mips16_nop_insn.insn_opcode;
18616 case NOP_OPCODE_MIPS:
18618 opcode = nop_insn.insn_opcode;
18623 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18624 excess = bytes % size;
18626 /* Handle the leading part if we're not inserting a whole number of
18627 instructions, and make it the end of the fixed part of the frag.
18628 Try to fit in a short microMIPS NOP if applicable and possible,
18629 and use zeroes otherwise. */
18630 gas_assert (excess < 4);
18631 fragp->fr_fix += excess;
18636 /* Fall through. */
18638 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18640 md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
18645 /* Fall through. */
18648 /* Fall through. */
18653 md_number_to_chars (p, opcode, size);
18654 fragp->fr_var = size;
18658 md_obj_begin (void)
18665 /* Check for premature end, nesting errors, etc. */
18667 as_warn (_("missing .end at end of assembly"));
18676 if (*input_line_pointer == '-')
18678 ++input_line_pointer;
18681 if (!ISDIGIT (*input_line_pointer))
18682 as_bad (_("expected simple number"));
18683 if (input_line_pointer[0] == '0')
18685 if (input_line_pointer[1] == 'x')
18687 input_line_pointer += 2;
18688 while (ISXDIGIT (*input_line_pointer))
18691 val |= hex_value (*input_line_pointer++);
18693 return negative ? -val : val;
18697 ++input_line_pointer;
18698 while (ISDIGIT (*input_line_pointer))
18701 val |= *input_line_pointer++ - '0';
18703 return negative ? -val : val;
18706 if (!ISDIGIT (*input_line_pointer))
18708 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18709 *input_line_pointer, *input_line_pointer);
18710 as_warn (_("invalid number"));
18713 while (ISDIGIT (*input_line_pointer))
18716 val += *input_line_pointer++ - '0';
18718 return negative ? -val : val;
18721 /* The .file directive; just like the usual .file directive, but there
18722 is an initial number which is the ECOFF file index. In the non-ECOFF
18723 case .file implies DWARF-2. */
18726 s_mips_file (int x ATTRIBUTE_UNUSED)
18728 static int first_file_directive = 0;
18730 if (ECOFF_DEBUGGING)
18739 filename = dwarf2_directive_file (0);
18741 /* Versions of GCC up to 3.1 start files with a ".file"
18742 directive even for stabs output. Make sure that this
18743 ".file" is handled. Note that you need a version of GCC
18744 after 3.1 in order to support DWARF-2 on MIPS. */
18745 if (filename != NULL && ! first_file_directive)
18747 (void) new_logical_line (filename, -1);
18748 s_app_file_string (filename, 0);
18750 first_file_directive = 1;
18754 /* The .loc directive, implying DWARF-2. */
18757 s_mips_loc (int x ATTRIBUTE_UNUSED)
18759 if (!ECOFF_DEBUGGING)
18760 dwarf2_directive_loc (0);
18763 /* The .end directive. */
18766 s_mips_end (int x ATTRIBUTE_UNUSED)
18770 /* Following functions need their own .frame and .cprestore directives. */
18771 mips_frame_reg_valid = 0;
18772 mips_cprestore_valid = 0;
18774 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18777 demand_empty_rest_of_line ();
18782 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18783 as_warn (_(".end not in text section"));
18787 as_warn (_(".end directive without a preceding .ent directive."));
18788 demand_empty_rest_of_line ();
18794 gas_assert (S_GET_NAME (p));
18795 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18796 as_warn (_(".end symbol does not match .ent symbol."));
18798 if (debug_type == DEBUG_STABS)
18799 stabs_generate_asm_endfunc (S_GET_NAME (p),
18803 as_warn (_(".end directive missing or unknown symbol"));
18806 /* Create an expression to calculate the size of the function. */
18807 if (p && cur_proc_ptr)
18809 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18810 expressionS *exp = xmalloc (sizeof (expressionS));
18813 exp->X_op = O_subtract;
18814 exp->X_add_symbol = symbol_temp_new_now ();
18815 exp->X_op_symbol = p;
18816 exp->X_add_number = 0;
18818 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18821 /* Generate a .pdr section. */
18822 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18824 segT saved_seg = now_seg;
18825 subsegT saved_subseg = now_subseg;
18829 #ifdef md_flush_pending_output
18830 md_flush_pending_output ();
18833 gas_assert (pdr_seg);
18834 subseg_set (pdr_seg, 0);
18836 /* Write the symbol. */
18837 exp.X_op = O_symbol;
18838 exp.X_add_symbol = p;
18839 exp.X_add_number = 0;
18840 emit_expr (&exp, 4);
18842 fragp = frag_more (7 * 4);
18844 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18845 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18846 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18847 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18848 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18849 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18850 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18852 subseg_set (saved_seg, saved_subseg);
18854 #endif /* OBJ_ELF */
18856 cur_proc_ptr = NULL;
18859 /* The .aent and .ent directives. */
18862 s_mips_ent (int aent)
18866 symbolP = get_symbol ();
18867 if (*input_line_pointer == ',')
18868 ++input_line_pointer;
18869 SKIP_WHITESPACE ();
18870 if (ISDIGIT (*input_line_pointer)
18871 || *input_line_pointer == '-')
18874 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18875 as_warn (_(".ent or .aent not in text section."));
18877 if (!aent && cur_proc_ptr)
18878 as_warn (_("missing .end"));
18882 /* This function needs its own .frame and .cprestore directives. */
18883 mips_frame_reg_valid = 0;
18884 mips_cprestore_valid = 0;
18886 cur_proc_ptr = &cur_proc;
18887 memset (cur_proc_ptr, '\0', sizeof (procS));
18889 cur_proc_ptr->func_sym = symbolP;
18893 if (debug_type == DEBUG_STABS)
18894 stabs_generate_asm_func (S_GET_NAME (symbolP),
18895 S_GET_NAME (symbolP));
18898 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18900 demand_empty_rest_of_line ();
18903 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18904 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18905 s_mips_frame is used so that we can set the PDR information correctly.
18906 We can't use the ecoff routines because they make reference to the ecoff
18907 symbol table (in the mdebug section). */
18910 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18913 if (IS_ELF && !ECOFF_DEBUGGING)
18917 if (cur_proc_ptr == (procS *) NULL)
18919 as_warn (_(".frame outside of .ent"));
18920 demand_empty_rest_of_line ();
18924 cur_proc_ptr->frame_reg = tc_get_register (1);
18926 SKIP_WHITESPACE ();
18927 if (*input_line_pointer++ != ','
18928 || get_absolute_expression_and_terminator (&val) != ',')
18930 as_warn (_("Bad .frame directive"));
18931 --input_line_pointer;
18932 demand_empty_rest_of_line ();
18936 cur_proc_ptr->frame_offset = val;
18937 cur_proc_ptr->pc_reg = tc_get_register (0);
18939 demand_empty_rest_of_line ();
18942 #endif /* OBJ_ELF */
18946 /* The .fmask and .mask directives. If the mdebug section is present
18947 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18948 embedded targets, s_mips_mask is used so that we can set the PDR
18949 information correctly. We can't use the ecoff routines because they
18950 make reference to the ecoff symbol table (in the mdebug section). */
18953 s_mips_mask (int reg_type)
18956 if (IS_ELF && !ECOFF_DEBUGGING)
18960 if (cur_proc_ptr == (procS *) NULL)
18962 as_warn (_(".mask/.fmask outside of .ent"));
18963 demand_empty_rest_of_line ();
18967 if (get_absolute_expression_and_terminator (&mask) != ',')
18969 as_warn (_("Bad .mask/.fmask directive"));
18970 --input_line_pointer;
18971 demand_empty_rest_of_line ();
18975 off = get_absolute_expression ();
18977 if (reg_type == 'F')
18979 cur_proc_ptr->fpreg_mask = mask;
18980 cur_proc_ptr->fpreg_offset = off;
18984 cur_proc_ptr->reg_mask = mask;
18985 cur_proc_ptr->reg_offset = off;
18988 demand_empty_rest_of_line ();
18991 #endif /* OBJ_ELF */
18992 s_ignore (reg_type);
18995 /* A table describing all the processors gas knows about. Names are
18996 matched in the order listed.
18998 To ease comparison, please keep this table in the same order as
18999 gcc's mips_cpu_info_table[]. */
19000 static const struct mips_cpu_info mips_cpu_info_table[] =
19002 /* Entries for generic ISAs */
19003 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
19004 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
19005 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
19006 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
19007 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
19008 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
19009 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
19010 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
19011 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
19014 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
19015 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
19016 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
19019 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19022 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19023 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19024 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19025 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19026 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19027 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19028 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19029 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19030 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19031 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19032 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19033 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19034 /* ST Microelectronics Loongson 2E and 2F cores */
19035 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19036 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19039 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19040 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19041 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19042 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19043 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19044 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19045 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19046 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19047 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19048 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19049 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19050 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19051 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19052 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19053 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19056 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19057 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19058 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19059 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19061 /* MIPS 32 Release 2 */
19062 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19063 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19064 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19065 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19066 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19067 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19068 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19069 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19070 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19071 ISA_MIPS32R2, CPU_MIPS32R2 },
19072 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19073 ISA_MIPS32R2, CPU_MIPS32R2 },
19074 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19075 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19076 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19077 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19078 /* Deprecated forms of the above. */
19079 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19080 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19081 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19082 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19083 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19084 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19085 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19086 /* Deprecated forms of the above. */
19087 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19088 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19089 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19090 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19091 ISA_MIPS32R2, CPU_MIPS32R2 },
19092 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19093 ISA_MIPS32R2, CPU_MIPS32R2 },
19094 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19095 ISA_MIPS32R2, CPU_MIPS32R2 },
19096 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19097 ISA_MIPS32R2, CPU_MIPS32R2 },
19098 /* Deprecated forms of the above. */
19099 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19100 ISA_MIPS32R2, CPU_MIPS32R2 },
19101 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19102 ISA_MIPS32R2, CPU_MIPS32R2 },
19103 /* 34Kn is a 34kc without DSP. */
19104 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19105 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19106 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19107 ISA_MIPS32R2, CPU_MIPS32R2 },
19108 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19109 ISA_MIPS32R2, CPU_MIPS32R2 },
19110 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19111 ISA_MIPS32R2, CPU_MIPS32R2 },
19112 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19113 ISA_MIPS32R2, CPU_MIPS32R2 },
19114 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19115 ISA_MIPS32R2, CPU_MIPS32R2 },
19116 /* Deprecated forms of the above. */
19117 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19118 ISA_MIPS32R2, CPU_MIPS32R2 },
19119 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19120 ISA_MIPS32R2, CPU_MIPS32R2 },
19121 /* 1004K cores are multiprocessor versions of the 34K. */
19122 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19123 ISA_MIPS32R2, CPU_MIPS32R2 },
19124 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19125 ISA_MIPS32R2, CPU_MIPS32R2 },
19126 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19127 ISA_MIPS32R2, CPU_MIPS32R2 },
19128 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19129 ISA_MIPS32R2, CPU_MIPS32R2 },
19132 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19133 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19134 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19135 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19137 /* Broadcom SB-1 CPU core */
19138 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19139 ISA_MIPS64, CPU_SB1 },
19140 /* Broadcom SB-1A CPU core */
19141 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19142 ISA_MIPS64, CPU_SB1 },
19144 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19146 /* MIPS 64 Release 2 */
19148 /* Cavium Networks Octeon CPU core */
19149 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19150 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19151 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19154 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19157 XLP is mostly like XLR, with the prominent exception that it is
19158 MIPS64R2 rather than MIPS64. */
19159 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19166 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19167 with a final "000" replaced by "k". Ignore case.
19169 Note: this function is shared between GCC and GAS. */
19172 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19174 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19175 given++, canonical++;
19177 return ((*given == 0 && *canonical == 0)
19178 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19182 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19183 CPU name. We've traditionally allowed a lot of variation here.
19185 Note: this function is shared between GCC and GAS. */
19188 mips_matching_cpu_name_p (const char *canonical, const char *given)
19190 /* First see if the name matches exactly, or with a final "000"
19191 turned into "k". */
19192 if (mips_strict_matching_cpu_name_p (canonical, given))
19195 /* If not, try comparing based on numerical designation alone.
19196 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19197 if (TOLOWER (*given) == 'r')
19199 if (!ISDIGIT (*given))
19202 /* Skip over some well-known prefixes in the canonical name,
19203 hoping to find a number there too. */
19204 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19206 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19208 else if (TOLOWER (canonical[0]) == 'r')
19211 return mips_strict_matching_cpu_name_p (canonical, given);
19215 /* Parse an option that takes the name of a processor as its argument.
19216 OPTION is the name of the option and CPU_STRING is the argument.
19217 Return the corresponding processor enumeration if the CPU_STRING is
19218 recognized, otherwise report an error and return null.
19220 A similar function exists in GCC. */
19222 static const struct mips_cpu_info *
19223 mips_parse_cpu (const char *option, const char *cpu_string)
19225 const struct mips_cpu_info *p;
19227 /* 'from-abi' selects the most compatible architecture for the given
19228 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19229 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19230 version. Look first at the -mgp options, if given, otherwise base
19231 the choice on MIPS_DEFAULT_64BIT.
19233 Treat NO_ABI like the EABIs. One reason to do this is that the
19234 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19235 architecture. This code picks MIPS I for 'mips' and MIPS III for
19236 'mips64', just as we did in the days before 'from-abi'. */
19237 if (strcasecmp (cpu_string, "from-abi") == 0)
19239 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19240 return mips_cpu_info_from_isa (ISA_MIPS1);
19242 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19243 return mips_cpu_info_from_isa (ISA_MIPS3);
19245 if (file_mips_gp32 >= 0)
19246 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19248 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19253 /* 'default' has traditionally been a no-op. Probably not very useful. */
19254 if (strcasecmp (cpu_string, "default") == 0)
19257 for (p = mips_cpu_info_table; p->name != 0; p++)
19258 if (mips_matching_cpu_name_p (p->name, cpu_string))
19261 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19265 /* Return the canonical processor information for ISA (a member of the
19266 ISA_MIPS* enumeration). */
19268 static const struct mips_cpu_info *
19269 mips_cpu_info_from_isa (int isa)
19273 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19274 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19275 && isa == mips_cpu_info_table[i].isa)
19276 return (&mips_cpu_info_table[i]);
19281 static const struct mips_cpu_info *
19282 mips_cpu_info_from_arch (int arch)
19286 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19287 if (arch == mips_cpu_info_table[i].cpu)
19288 return (&mips_cpu_info_table[i]);
19294 show (FILE *stream, const char *string, int *col_p, int *first_p)
19298 fprintf (stream, "%24s", "");
19303 fprintf (stream, ", ");
19307 if (*col_p + strlen (string) > 72)
19309 fprintf (stream, "\n%24s", "");
19313 fprintf (stream, "%s", string);
19314 *col_p += strlen (string);
19320 md_show_usage (FILE *stream)
19325 fprintf (stream, _("\
19327 -EB generate big endian output\n\
19328 -EL generate little endian output\n\
19329 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19330 -G NUM allow referencing objects up to NUM bytes\n\
19331 implicitly with the gp register [default 8]\n"));
19332 fprintf (stream, _("\
19333 -mips1 generate MIPS ISA I instructions\n\
19334 -mips2 generate MIPS ISA II instructions\n\
19335 -mips3 generate MIPS ISA III instructions\n\
19336 -mips4 generate MIPS ISA IV instructions\n\
19337 -mips5 generate MIPS ISA V instructions\n\
19338 -mips32 generate MIPS32 ISA instructions\n\
19339 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19340 -mips64 generate MIPS64 ISA instructions\n\
19341 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19342 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19346 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19347 show (stream, mips_cpu_info_table[i].name, &column, &first);
19348 show (stream, "from-abi", &column, &first);
19349 fputc ('\n', stream);
19351 fprintf (stream, _("\
19352 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19353 -no-mCPU don't generate code specific to CPU.\n\
19354 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19358 show (stream, "3900", &column, &first);
19359 show (stream, "4010", &column, &first);
19360 show (stream, "4100", &column, &first);
19361 show (stream, "4650", &column, &first);
19362 fputc ('\n', stream);
19364 fprintf (stream, _("\
19365 -mips16 generate mips16 instructions\n\
19366 -no-mips16 do not generate mips16 instructions\n"));
19367 fprintf (stream, _("\
19368 -mmicromips generate microMIPS instructions\n\
19369 -mno-micromips do not generate microMIPS instructions\n"));
19370 fprintf (stream, _("\
19371 -msmartmips generate smartmips instructions\n\
19372 -mno-smartmips do not generate smartmips instructions\n"));
19373 fprintf (stream, _("\
19374 -mdsp generate DSP instructions\n\
19375 -mno-dsp do not generate DSP instructions\n"));
19376 fprintf (stream, _("\
19377 -mdspr2 generate DSP R2 instructions\n\
19378 -mno-dspr2 do not generate DSP R2 instructions\n"));
19379 fprintf (stream, _("\
19380 -mmt generate MT instructions\n\
19381 -mno-mt do not generate MT instructions\n"));
19382 fprintf (stream, _("\
19383 -mmcu generate MCU instructions\n\
19384 -mno-mcu do not generate MCU instructions\n"));
19385 fprintf (stream, _("\
19386 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19387 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19388 -mfix-vr4120 work around certain VR4120 errata\n\
19389 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19390 -mfix-24k insert a nop after ERET and DERET instructions\n\
19391 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19392 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19393 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19394 -msym32 assume all symbols have 32-bit values\n\
19395 -O0 remove unneeded NOPs, do not swap branches\n\
19396 -O remove unneeded NOPs and swap branches\n\
19397 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19398 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19399 fprintf (stream, _("\
19400 -mhard-float allow floating-point instructions\n\
19401 -msoft-float do not allow floating-point instructions\n\
19402 -msingle-float only allow 32-bit floating-point operations\n\
19403 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19404 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19407 fprintf (stream, _("\
19408 -KPIC, -call_shared generate SVR4 position independent code\n\
19409 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19410 -mvxworks-pic generate VxWorks position independent code\n\
19411 -non_shared do not generate code that can operate with DSOs\n\
19412 -xgot assume a 32 bit GOT\n\
19413 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19414 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19415 position dependent (non shared) code\n\
19416 -mabi=ABI create ABI conformant object file for:\n"));
19420 show (stream, "32", &column, &first);
19421 show (stream, "o64", &column, &first);
19422 show (stream, "n32", &column, &first);
19423 show (stream, "64", &column, &first);
19424 show (stream, "eabi", &column, &first);
19426 fputc ('\n', stream);
19428 fprintf (stream, _("\
19429 -32 create o32 ABI object file (default)\n\
19430 -n32 create n32 ABI object file\n\
19431 -64 create 64 ABI object file\n"));
19437 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19439 if (HAVE_64BIT_SYMBOLS)
19440 return dwarf2_format_64bit_irix;
19442 return dwarf2_format_32bit;
19447 mips_dwarf2_addr_size (void)
19449 if (HAVE_64BIT_OBJECTS)
19455 /* Standard calling conventions leave the CFA at SP on entry. */
19457 mips_cfi_frame_initial_instructions (void)
19459 cfi_add_CFA_def_cfa_register (SP);
19463 tc_mips_regname_to_dw2regnum (char *regname)
19465 unsigned int regnum = -1;
19468 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))