1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
79 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
80 static char *mips_regmask_frag;
86 #define PIC_CALL_REG 25
94 #define ILLEGAL_REG (32)
96 /* Allow override of standard little-endian ECOFF format. */
98 #ifndef ECOFF_LITTLE_FORMAT
99 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
102 extern int target_big_endian;
104 /* The name of the readonly data section. */
105 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
107 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
109 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
111 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
115 /* The ABI to use. */
126 /* MIPS ABI we are using for this output file. */
127 static enum mips_abi_level mips_abi = NO_ABI;
129 /* Whether or not we have code that can call pic code. */
130 int mips_abicalls = FALSE;
132 /* This is the set of options which may be modified by the .set
133 pseudo-op. We use a struct so that .set push and .set pop are more
136 struct mips_set_options
138 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
139 if it has not been initialized. Changed by `.set mipsN', and the
140 -mipsN command line option, and the default CPU. */
142 /* Enabled Application Specific Extensions (ASEs). These are set to -1
143 if they have not been initialized. Changed by `.set <asename>', by
144 command line options, and based on the default architecture. */
147 /* Whether we are assembling for the mips16 processor. 0 if we are
148 not, 1 if we are, and -1 if the value has not been initialized.
149 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
150 -nomips16 command line options, and the default CPU. */
152 /* Non-zero if we should not reorder instructions. Changed by `.set
153 reorder' and `.set noreorder'. */
155 /* Non-zero if we should not permit the $at ($1) register to be used
156 in instructions. Changed by `.set at' and `.set noat'. */
158 /* Non-zero if we should warn when a macro instruction expands into
159 more than one machine instruction. Changed by `.set nomacro' and
161 int warn_about_macros;
162 /* Non-zero if we should not move instructions. Changed by `.set
163 move', `.set volatile', `.set nomove', and `.set novolatile'. */
165 /* Non-zero if we should not optimize branches by moving the target
166 of the branch into the delay slot. Actually, we don't perform
167 this optimization anyhow. Changed by `.set bopt' and `.set
170 /* Non-zero if we should not autoextend mips16 instructions.
171 Changed by `.set autoextend' and `.set noautoextend'. */
173 /* Restrict general purpose registers and floating point registers
174 to 32 bit. This is initially determined when -mgp32 or -mfp32
175 is passed but can changed if the assembler code uses .set mipsN. */
178 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
179 command line option, and the default CPU. */
183 /* True if -mgp32 was passed. */
184 static int file_mips_gp32 = -1;
186 /* True if -mfp32 was passed. */
187 static int file_mips_fp32 = -1;
189 /* This is the struct we use to hold the current set of options. Note
190 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
191 -1 to indicate that they have not been initialized. */
193 static struct mips_set_options mips_opts =
195 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
198 /* These variables are filled in with the masks of registers used.
199 The object format code reads them and puts them in the appropriate
201 unsigned long mips_gprmask;
202 unsigned long mips_cprmask[4];
204 /* MIPS ISA we are using for this output file. */
205 static int file_mips_isa = ISA_UNKNOWN;
207 /* True if -mips16 was passed or implied by arguments passed on the
208 command line (e.g., by -march). */
209 static int file_ase_mips16;
211 /* True if -mips3d was passed or implied by arguments passed on the
212 command line (e.g., by -march). */
213 static int file_ase_mips3d;
215 /* True if -mdmx was passed or implied by arguments passed on the
216 command line (e.g., by -march). */
217 static int file_ase_mdmx;
219 /* The argument of the -march= flag. The architecture we are assembling. */
220 static int file_mips_arch = CPU_UNKNOWN;
221 static const char *mips_arch_string;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune = CPU_UNKNOWN;
226 static const char *mips_tune_string;
228 /* True when generating 32-bit code for a 64-bit processor. */
229 static int mips_32bitmode = 0;
231 /* Some ISA's have delay slots for instructions which read or write
232 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
233 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
234 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
235 delay slot in this ISA. The uses of this macro assume that any
236 ISA that has delay slots for one of these, has them for all. They
237 also assume that ISAs which don't have delays for these insns, don't
238 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
239 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
241 || (ISA) == ISA_MIPS2 \
242 || (ISA) == ISA_MIPS3 \
245 /* True if the given ABI requires 32-bit registers. */
246 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
248 /* Likewise 64-bit registers. */
249 #define ABI_NEEDS_64BIT_REGS(ABI) \
251 || (ABI) == N64_ABI \
254 /* Return true if ISA supports 64 bit gp register instructions. */
255 #define ISA_HAS_64BIT_REGS(ISA) ( \
257 || (ISA) == ISA_MIPS4 \
258 || (ISA) == ISA_MIPS5 \
259 || (ISA) == ISA_MIPS64 \
262 /* Return true if ISA supports 64-bit right rotate (dror et al.)
264 #define ISA_HAS_DROR(ISA) ( \
268 /* Return true if ISA supports 32-bit right rotate (ror et al.)
270 #define ISA_HAS_ROR(ISA) ( \
271 (ISA) == ISA_MIPS32R2 \
274 #define HAVE_32BIT_GPRS \
275 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_32BIT_FPRS \
278 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
280 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
281 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
283 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
285 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
287 /* We can only have 64bit addresses if the object file format
289 #define HAVE_32BIT_ADDRESSES \
291 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
292 || ! HAVE_64BIT_OBJECTS) \
293 && mips_pic != EMBEDDED_PIC))
295 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
296 #define HAVE_64BIT_ADDRESS_CONSTANTS (HAVE_64BIT_ADDRESSES \
299 /* Addresses are loaded in different ways, depending on the address size
300 in use. The n32 ABI Documentation also mandates the use of additions
301 with overflow checking, but existing implementations don't follow it. */
302 #define ADDRESS_ADD_INSN \
303 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
305 #define ADDRESS_ADDI_INSN \
306 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
308 #define ADDRESS_LOAD_INSN \
309 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
311 #define ADDRESS_STORE_INSN \
312 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
314 /* Return true if the given CPU supports the MIPS16 ASE. */
315 #define CPU_HAS_MIPS16(cpu) \
316 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
317 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
319 /* Return true if the given CPU supports the MIPS3D ASE. */
320 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
323 /* Return true if the given CPU supports the MDMX ASE. */
324 #define CPU_HAS_MDMX(cpu) (FALSE \
327 /* True if CPU has a dror instruction. */
328 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
330 /* True if CPU has a ror instruction. */
331 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
333 /* Whether the processor uses hardware interlocks to protect
334 reads from the HI and LO registers, and thus does not
335 require nops to be inserted. */
337 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
338 || mips_opts.arch == CPU_VR5500 \
339 || mips_opts.arch == CPU_RM7000 \
340 || mips_opts.arch == CPU_SB1 \
343 /* Whether the processor uses hardware interlocks to protect reads
344 from the GPRs, and thus does not require nops to be inserted. */
345 #define gpr_interlocks \
346 (mips_opts.isa != ISA_MIPS1 \
347 || mips_opts.arch == CPU_VR5400 \
348 || mips_opts.arch == CPU_VR5500 \
349 || mips_opts.arch == CPU_R3900)
351 /* As with other "interlocks" this is used by hardware that has FP
352 (co-processor) interlocks. */
353 /* Itbl support may require additional care here. */
354 #define cop_interlocks (mips_opts.arch == CPU_R4300 \
355 || mips_opts.arch == CPU_VR5400 \
356 || mips_opts.arch == CPU_VR5500 \
357 || mips_opts.arch == CPU_SB1 \
360 /* Is this a mfhi or mflo instruction? */
361 #define MF_HILO_INSN(PINFO) \
362 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
364 /* MIPS PIC level. */
366 enum mips_pic_level mips_pic;
368 /* Warn about all NOPS that the assembler generates. */
369 static int warn_nops = 0;
371 /* 1 if we should generate 32 bit offsets from the $gp register in
372 SVR4_PIC mode. Currently has no meaning in other modes. */
373 static int mips_big_got = 0;
375 /* 1 if trap instructions should used for overflow rather than break
377 static int mips_trap = 0;
379 /* 1 if double width floating point constants should not be constructed
380 by assembling two single width halves into two single width floating
381 point registers which just happen to alias the double width destination
382 register. On some architectures this aliasing can be disabled by a bit
383 in the status register, and the setting of this bit cannot be determined
384 automatically at assemble time. */
385 static int mips_disable_float_construction;
387 /* Non-zero if any .set noreorder directives were used. */
389 static int mips_any_noreorder;
391 /* Non-zero if nops should be inserted when the register referenced in
392 an mfhi/mflo instruction is read in the next two instructions. */
393 static int mips_7000_hilo_fix;
395 /* The size of the small data section. */
396 static unsigned int g_switch_value = 8;
397 /* Whether the -G option was used. */
398 static int g_switch_seen = 0;
403 /* If we can determine in advance that GP optimization won't be
404 possible, we can skip the relaxation stuff that tries to produce
405 GP-relative references. This makes delay slot optimization work
408 This function can only provide a guess, but it seems to work for
409 gcc output. It needs to guess right for gcc, otherwise gcc
410 will put what it thinks is a GP-relative instruction in a branch
413 I don't know if a fix is needed for the SVR4_PIC mode. I've only
414 fixed it for the non-PIC mode. KR 95/04/07 */
415 static int nopic_need_relax (symbolS *, int);
417 /* handle of the OPCODE hash table */
418 static struct hash_control *op_hash = NULL;
420 /* The opcode hash table we use for the mips16. */
421 static struct hash_control *mips16_op_hash = NULL;
423 /* This array holds the chars that always start a comment. If the
424 pre-processor is disabled, these aren't very useful */
425 const char comment_chars[] = "#";
427 /* This array holds the chars that only start a comment at the beginning of
428 a line. If the line seems to have the form '# 123 filename'
429 .line and .file directives will appear in the pre-processed output */
430 /* Note that input_file.c hand checks for '#' at the beginning of the
431 first line of the input file. This is because the compiler outputs
432 #NO_APP at the beginning of its output. */
433 /* Also note that C style comments are always supported. */
434 const char line_comment_chars[] = "#";
436 /* This array holds machine specific line separator characters. */
437 const char line_separator_chars[] = ";";
439 /* Chars that can be used to separate mant from exp in floating point nums */
440 const char EXP_CHARS[] = "eE";
442 /* Chars that mean this number is a floating point constant */
445 const char FLT_CHARS[] = "rRsSfFdDxXpP";
447 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
448 changed in read.c . Ideally it shouldn't have to know about it at all,
449 but nothing is ideal around here.
452 static char *insn_error;
454 static int auto_align = 1;
456 /* When outputting SVR4 PIC code, the assembler needs to know the
457 offset in the stack frame from which to restore the $gp register.
458 This is set by the .cprestore pseudo-op, and saved in this
460 static offsetT mips_cprestore_offset = -1;
462 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
463 more optimizations, it can use a register value instead of a memory-saved
464 offset and even an other register than $gp as global pointer. */
465 static offsetT mips_cpreturn_offset = -1;
466 static int mips_cpreturn_register = -1;
467 static int mips_gp_register = GP;
468 static int mips_gprel_offset = 0;
470 /* Whether mips_cprestore_offset has been set in the current function
471 (or whether it has already been warned about, if not). */
472 static int mips_cprestore_valid = 0;
474 /* This is the register which holds the stack frame, as set by the
475 .frame pseudo-op. This is needed to implement .cprestore. */
476 static int mips_frame_reg = SP;
478 /* Whether mips_frame_reg has been set in the current function
479 (or whether it has already been warned about, if not). */
480 static int mips_frame_reg_valid = 0;
482 /* To output NOP instructions correctly, we need to keep information
483 about the previous two instructions. */
485 /* Whether we are optimizing. The default value of 2 means to remove
486 unneeded NOPs and swap branch instructions when possible. A value
487 of 1 means to not swap branches. A value of 0 means to always
489 static int mips_optimize = 2;
491 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
492 equivalent to seeing no -g option at all. */
493 static int mips_debug = 0;
495 /* The previous instruction. */
496 static struct mips_cl_insn prev_insn;
498 /* The instruction before prev_insn. */
499 static struct mips_cl_insn prev_prev_insn;
501 /* If we don't want information for prev_insn or prev_prev_insn, we
502 point the insn_mo field at this dummy integer. */
503 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
505 /* Non-zero if prev_insn is valid. */
506 static int prev_insn_valid;
508 /* The frag for the previous instruction. */
509 static struct frag *prev_insn_frag;
511 /* The offset into prev_insn_frag for the previous instruction. */
512 static long prev_insn_where;
514 /* The reloc type for the previous instruction, if any. */
515 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
517 /* The reloc for the previous instruction, if any. */
518 static fixS *prev_insn_fixp[3];
520 /* Non-zero if the previous instruction was in a delay slot. */
521 static int prev_insn_is_delay_slot;
523 /* Non-zero if the previous instruction was in a .set noreorder. */
524 static int prev_insn_unreordered;
526 /* Non-zero if the previous instruction uses an extend opcode (if
528 static int prev_insn_extended;
530 /* Non-zero if the previous previous instruction was in a .set
532 static int prev_prev_insn_unreordered;
534 /* If this is set, it points to a frag holding nop instructions which
535 were inserted before the start of a noreorder section. If those
536 nops turn out to be unnecessary, the size of the frag can be
538 static fragS *prev_nop_frag;
540 /* The number of nop instructions we created in prev_nop_frag. */
541 static int prev_nop_frag_holds;
543 /* The number of nop instructions that we know we need in
545 static int prev_nop_frag_required;
547 /* The number of instructions we've seen since prev_nop_frag. */
548 static int prev_nop_frag_since;
550 /* For ECOFF and ELF, relocations against symbols are done in two
551 parts, with a HI relocation and a LO relocation. Each relocation
552 has only 16 bits of space to store an addend. This means that in
553 order for the linker to handle carries correctly, it must be able
554 to locate both the HI and the LO relocation. This means that the
555 relocations must appear in order in the relocation table.
557 In order to implement this, we keep track of each unmatched HI
558 relocation. We then sort them so that they immediately precede the
559 corresponding LO relocation. */
564 struct mips_hi_fixup *next;
567 /* The section this fixup is in. */
571 /* The list of unmatched HI relocs. */
573 static struct mips_hi_fixup *mips_hi_fixup_list;
575 /* The frag containing the last explicit relocation operator.
576 Null if explicit relocations have not been used. */
578 static fragS *prev_reloc_op_frag;
580 /* Map normal MIPS register numbers to mips16 register numbers. */
582 #define X ILLEGAL_REG
583 static const int mips32_to_16_reg_map[] =
585 X, X, 2, 3, 4, 5, 6, 7,
586 X, X, X, X, X, X, X, X,
587 0, 1, X, X, X, X, X, X,
588 X, X, X, X, X, X, X, X
592 /* Map mips16 register numbers to normal MIPS register numbers. */
594 static const unsigned int mips16_to_32_reg_map[] =
596 16, 17, 2, 3, 4, 5, 6, 7
599 static int mips_fix_4122_bugs;
601 /* We don't relax branches by default, since this causes us to expand
602 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
603 fail to compute the offset before expanding the macro to the most
604 efficient expansion. */
606 static int mips_relax_branch;
608 /* Since the MIPS does not have multiple forms of PC relative
609 instructions, we do not have to do relaxing as is done on other
610 platforms. However, we do have to handle GP relative addressing
611 correctly, which turns out to be a similar problem.
613 Every macro that refers to a symbol can occur in (at least) two
614 forms, one with GP relative addressing and one without. For
615 example, loading a global variable into a register generally uses
616 a macro instruction like this:
618 If i can be addressed off the GP register (this is true if it is in
619 the .sbss or .sdata section, or if it is known to be smaller than
620 the -G argument) this will generate the following instruction:
622 This instruction will use a GPREL reloc. If i can not be addressed
623 off the GP register, the following instruction sequence will be used:
626 In this case the first instruction will have a HI16 reloc, and the
627 second reloc will have a LO16 reloc. Both relocs will be against
630 The issue here is that we may not know whether i is GP addressable
631 until after we see the instruction that uses it. Therefore, we
632 want to be able to choose the final instruction sequence only at
633 the end of the assembly. This is similar to the way other
634 platforms choose the size of a PC relative instruction only at the
637 When generating position independent code we do not use GP
638 addressing in quite the same way, but the issue still arises as
639 external symbols and local symbols must be handled differently.
641 We handle these issues by actually generating both possible
642 instruction sequences. The longer one is put in a frag_var with
643 type rs_machine_dependent. We encode what to do with the frag in
644 the subtype field. We encode (1) the number of existing bytes to
645 replace, (2) the number of new bytes to use, (3) the offset from
646 the start of the existing bytes to the first reloc we must generate
647 (that is, the offset is applied from the start of the existing
648 bytes after they are replaced by the new bytes, if any), (4) the
649 offset from the start of the existing bytes to the second reloc,
650 (5) whether a third reloc is needed (the third reloc is always four
651 bytes after the second reloc), and (6) whether to warn if this
652 variant is used (this is sometimes needed if .set nomacro or .set
653 noat is in effect). All these numbers are reasonably small.
655 Generating two instruction sequences must be handled carefully to
656 ensure that delay slots are handled correctly. Fortunately, there
657 are a limited number of cases. When the second instruction
658 sequence is generated, append_insn is directed to maintain the
659 existing delay slot information, so it continues to apply to any
660 code after the second instruction sequence. This means that the
661 second instruction sequence must not impose any requirements not
662 required by the first instruction sequence.
664 These variant frags are then handled in functions called by the
665 machine independent code. md_estimate_size_before_relax returns
666 the final size of the frag. md_convert_frag sets up the final form
667 of the frag. tc_gen_reloc adjust the first reloc and adds a second
669 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
673 | (((reloc1) + 64) << 9) \
674 | (((reloc2) + 64) << 2) \
675 | ((reloc3) ? (1 << 1) : 0) \
677 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
678 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
679 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
680 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
681 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
682 #define RELAX_WARN(i) ((i) & 1)
684 /* Branch without likely bit. If label is out of range, we turn:
686 beq reg1, reg2, label
696 with the following opcode replacements:
703 bltzal <-> bgezal (with jal label instead of j label)
705 Even though keeping the delay slot instruction in the delay slot of
706 the branch would be more efficient, it would be very tricky to do
707 correctly, because we'd have to introduce a variable frag *after*
708 the delay slot instruction, and expand that instead. Let's do it
709 the easy way for now, even if the branch-not-taken case now costs
710 one additional instruction. Out-of-range branches are not supposed
711 to be common, anyway.
713 Branch likely. If label is out of range, we turn:
715 beql reg1, reg2, label
716 delay slot (annulled if branch not taken)
725 delay slot (executed only if branch taken)
728 It would be possible to generate a shorter sequence by losing the
729 likely bit, generating something like:
734 delay slot (executed only if branch taken)
746 bltzall -> bgezal (with jal label instead of j label)
747 bgezall -> bltzal (ditto)
750 but it's not clear that it would actually improve performance. */
751 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
754 | ((toofar) ? 1 : 0) \
756 | ((likely) ? 4 : 0) \
757 | ((uncond) ? 8 : 0)))
758 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
759 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
760 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
761 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
762 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
764 /* For mips16 code, we use an entirely different form of relaxation.
765 mips16 supports two versions of most instructions which take
766 immediate values: a small one which takes some small value, and a
767 larger one which takes a 16 bit value. Since branches also follow
768 this pattern, relaxing these values is required.
770 We can assemble both mips16 and normal MIPS code in a single
771 object. Therefore, we need to support this type of relaxation at
772 the same time that we support the relaxation described above. We
773 use the high bit of the subtype field to distinguish these cases.
775 The information we store for this type of relaxation is the
776 argument code found in the opcode file for this relocation, whether
777 the user explicitly requested a small or extended form, and whether
778 the relocation is in a jump or jal delay slot. That tells us the
779 size of the value, and how it should be stored. We also store
780 whether the fragment is considered to be extended or not. We also
781 store whether this is known to be a branch to a different section,
782 whether we have tried to relax this frag yet, and whether we have
783 ever extended a PC relative fragment because of a shift count. */
784 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
787 | ((small) ? 0x100 : 0) \
788 | ((ext) ? 0x200 : 0) \
789 | ((dslot) ? 0x400 : 0) \
790 | ((jal_dslot) ? 0x800 : 0))
791 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
792 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
793 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
794 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
795 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
796 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
797 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
798 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
799 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
800 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
801 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
802 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
804 /* Is the given value a sign-extended 32-bit value? */
805 #define IS_SEXT_32BIT_NUM(x) \
806 (((x) &~ (offsetT) 0x7fffffff) == 0 \
807 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
809 /* Is the given value a sign-extended 16-bit value? */
810 #define IS_SEXT_16BIT_NUM(x) \
811 (((x) &~ (offsetT) 0x7fff) == 0 \
812 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
815 /* Prototypes for static functions. */
817 #define internalError() \
818 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
820 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
822 static void append_insn
823 (char *place, struct mips_cl_insn *ip, expressionS *p,
824 bfd_reloc_code_real_type *r);
825 static void mips_no_prev_insn (int);
826 static void mips16_macro_build
827 (char *, int *, expressionS *, const char *, const char *, va_list);
828 static void load_register (int *, int, expressionS *, int);
829 static void macro (struct mips_cl_insn * ip);
830 static void mips16_macro (struct mips_cl_insn * ip);
831 #ifdef LOSING_COMPILER
832 static void macro2 (struct mips_cl_insn * ip);
834 static void mips_ip (char *str, struct mips_cl_insn * ip);
835 static void mips16_ip (char *str, struct mips_cl_insn * ip);
836 static void mips16_immed
837 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
838 unsigned long *, bfd_boolean *, unsigned short *);
839 static size_t my_getSmallExpression
840 (expressionS *, bfd_reloc_code_real_type *, char *);
841 static void my_getExpression (expressionS *, char *);
842 static void s_align (int);
843 static void s_change_sec (int);
844 static void s_change_section (int);
845 static void s_cons (int);
846 static void s_float_cons (int);
847 static void s_mips_globl (int);
848 static void s_option (int);
849 static void s_mipsset (int);
850 static void s_abicalls (int);
851 static void s_cpload (int);
852 static void s_cpsetup (int);
853 static void s_cplocal (int);
854 static void s_cprestore (int);
855 static void s_cpreturn (int);
856 static void s_gpvalue (int);
857 static void s_gpword (int);
858 static void s_gpdword (int);
859 static void s_cpadd (int);
860 static void s_insn (int);
861 static void md_obj_begin (void);
862 static void md_obj_end (void);
863 static void s_mips_ent (int);
864 static void s_mips_end (int);
865 static void s_mips_frame (int);
866 static void s_mips_mask (int reg_type);
867 static void s_mips_stab (int);
868 static void s_mips_weakext (int);
869 static void s_mips_file (int);
870 static void s_mips_loc (int);
871 static bfd_boolean pic_need_relax (symbolS *, asection *);
872 static int relaxed_branch_length (fragS *, asection *, int);
873 static int validate_mips_insn (const struct mips_opcode *);
875 /* Table and functions used to map between CPU/ISA names, and
876 ISA levels, and CPU numbers. */
880 const char *name; /* CPU or ISA name. */
881 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
882 int isa; /* ISA level. */
883 int cpu; /* CPU number (default CPU if ISA). */
886 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
887 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
888 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
892 The following pseudo-ops from the Kane and Heinrich MIPS book
893 should be defined here, but are currently unsupported: .alias,
894 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
896 The following pseudo-ops from the Kane and Heinrich MIPS book are
897 specific to the type of debugging information being generated, and
898 should be defined by the object format: .aent, .begin, .bend,
899 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
902 The following pseudo-ops from the Kane and Heinrich MIPS book are
903 not MIPS CPU specific, but are also not specific to the object file
904 format. This file is probably the best place to define them, but
905 they are not currently supported: .asm0, .endr, .lab, .repeat,
908 static const pseudo_typeS mips_pseudo_table[] =
910 /* MIPS specific pseudo-ops. */
911 {"option", s_option, 0},
912 {"set", s_mipsset, 0},
913 {"rdata", s_change_sec, 'r'},
914 {"sdata", s_change_sec, 's'},
915 {"livereg", s_ignore, 0},
916 {"abicalls", s_abicalls, 0},
917 {"cpload", s_cpload, 0},
918 {"cpsetup", s_cpsetup, 0},
919 {"cplocal", s_cplocal, 0},
920 {"cprestore", s_cprestore, 0},
921 {"cpreturn", s_cpreturn, 0},
922 {"gpvalue", s_gpvalue, 0},
923 {"gpword", s_gpword, 0},
924 {"gpdword", s_gpdword, 0},
925 {"cpadd", s_cpadd, 0},
928 /* Relatively generic pseudo-ops that happen to be used on MIPS
930 {"asciiz", stringer, 1},
931 {"bss", s_change_sec, 'b'},
934 {"dword", s_cons, 3},
935 {"weakext", s_mips_weakext, 0},
937 /* These pseudo-ops are defined in read.c, but must be overridden
938 here for one reason or another. */
939 {"align", s_align, 0},
941 {"data", s_change_sec, 'd'},
942 {"double", s_float_cons, 'd'},
943 {"float", s_float_cons, 'f'},
944 {"globl", s_mips_globl, 0},
945 {"global", s_mips_globl, 0},
946 {"hword", s_cons, 1},
951 {"section", s_change_section, 0},
952 {"short", s_cons, 1},
953 {"single", s_float_cons, 'f'},
954 {"stabn", s_mips_stab, 'n'},
955 {"text", s_change_sec, 't'},
958 { "extern", ecoff_directive_extern, 0},
963 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
965 /* These pseudo-ops should be defined by the object file format.
966 However, a.out doesn't support them, so we have versions here. */
967 {"aent", s_mips_ent, 1},
968 {"bgnb", s_ignore, 0},
969 {"end", s_mips_end, 0},
970 {"endb", s_ignore, 0},
971 {"ent", s_mips_ent, 0},
972 {"file", s_mips_file, 0},
973 {"fmask", s_mips_mask, 'F'},
974 {"frame", s_mips_frame, 0},
975 {"loc", s_mips_loc, 0},
976 {"mask", s_mips_mask, 'R'},
977 {"verstamp", s_ignore, 0},
981 extern void pop_insert (const pseudo_typeS *);
984 mips_pop_insert (void)
986 pop_insert (mips_pseudo_table);
987 if (! ECOFF_DEBUGGING)
988 pop_insert (mips_nonecoff_pseudo_table);
991 /* Symbols labelling the current insn. */
993 struct insn_label_list
995 struct insn_label_list *next;
999 static struct insn_label_list *insn_labels;
1000 static struct insn_label_list *free_insn_labels;
1002 static void mips_clear_insn_labels (void);
1005 mips_clear_insn_labels (void)
1007 register struct insn_label_list **pl;
1009 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1015 static char *expr_end;
1017 /* Expressions which appear in instructions. These are set by
1020 static expressionS imm_expr;
1021 static expressionS offset_expr;
1023 /* Relocs associated with imm_expr and offset_expr. */
1025 static bfd_reloc_code_real_type imm_reloc[3]
1026 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1027 static bfd_reloc_code_real_type offset_reloc[3]
1028 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1030 /* These are set by mips16_ip if an explicit extension is used. */
1032 static bfd_boolean mips16_small, mips16_ext;
1035 /* The pdr segment for per procedure frame/regmask info. Not used for
1038 static segT pdr_seg;
1041 /* The default target format to use. */
1044 mips_target_format (void)
1046 switch (OUTPUT_FLAVOR)
1048 case bfd_target_aout_flavour:
1049 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1050 case bfd_target_ecoff_flavour:
1051 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1052 case bfd_target_coff_flavour:
1054 case bfd_target_elf_flavour:
1056 /* This is traditional mips. */
1057 return (target_big_endian
1058 ? (HAVE_64BIT_OBJECTS
1059 ? "elf64-tradbigmips"
1061 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1062 : (HAVE_64BIT_OBJECTS
1063 ? "elf64-tradlittlemips"
1065 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1067 return (target_big_endian
1068 ? (HAVE_64BIT_OBJECTS
1071 ? "elf32-nbigmips" : "elf32-bigmips"))
1072 : (HAVE_64BIT_OBJECTS
1073 ? "elf64-littlemips"
1075 ? "elf32-nlittlemips" : "elf32-littlemips")));
1083 /* This function is called once, at assembler startup time. It should
1084 set up all the tables, etc. that the MD part of the assembler will need. */
1089 register const char *retval = NULL;
1093 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1094 as_warn (_("Could not set architecture and machine"));
1096 op_hash = hash_new ();
1098 for (i = 0; i < NUMOPCODES;)
1100 const char *name = mips_opcodes[i].name;
1102 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1105 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1106 mips_opcodes[i].name, retval);
1107 /* Probably a memory allocation problem? Give up now. */
1108 as_fatal (_("Broken assembler. No assembly attempted."));
1112 if (mips_opcodes[i].pinfo != INSN_MACRO)
1114 if (!validate_mips_insn (&mips_opcodes[i]))
1119 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1122 mips16_op_hash = hash_new ();
1125 while (i < bfd_mips16_num_opcodes)
1127 const char *name = mips16_opcodes[i].name;
1129 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1131 as_fatal (_("internal: can't hash `%s': %s"),
1132 mips16_opcodes[i].name, retval);
1135 if (mips16_opcodes[i].pinfo != INSN_MACRO
1136 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1137 != mips16_opcodes[i].match))
1139 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1140 mips16_opcodes[i].name, mips16_opcodes[i].args);
1145 while (i < bfd_mips16_num_opcodes
1146 && strcmp (mips16_opcodes[i].name, name) == 0);
1150 as_fatal (_("Broken assembler. No assembly attempted."));
1152 /* We add all the general register names to the symbol table. This
1153 helps us detect invalid uses of them. */
1154 for (i = 0; i < 32; i++)
1158 sprintf (buf, "$%d", i);
1159 symbol_table_insert (symbol_new (buf, reg_section, i,
1160 &zero_address_frag));
1162 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1163 &zero_address_frag));
1164 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1165 &zero_address_frag));
1166 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1167 &zero_address_frag));
1168 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1169 &zero_address_frag));
1170 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1171 &zero_address_frag));
1172 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1173 &zero_address_frag));
1174 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1175 &zero_address_frag));
1176 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1177 &zero_address_frag));
1178 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1179 &zero_address_frag));
1181 /* If we don't add these register names to the symbol table, they
1182 may end up being added as regular symbols by operand(), and then
1183 make it to the object file as undefined in case they're not
1184 regarded as local symbols. They're local in o32, since `$' is a
1185 local symbol prefix, but not in n32 or n64. */
1186 for (i = 0; i < 8; i++)
1190 sprintf (buf, "$fcc%i", i);
1191 symbol_table_insert (symbol_new (buf, reg_section, -1,
1192 &zero_address_frag));
1195 mips_no_prev_insn (FALSE);
1198 mips_cprmask[0] = 0;
1199 mips_cprmask[1] = 0;
1200 mips_cprmask[2] = 0;
1201 mips_cprmask[3] = 0;
1203 /* set the default alignment for the text section (2**2) */
1204 record_alignment (text_section, 2);
1206 if (USE_GLOBAL_POINTER_OPT)
1207 bfd_set_gp_size (stdoutput, g_switch_value);
1209 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1211 /* On a native system, sections must be aligned to 16 byte
1212 boundaries. When configured for an embedded ELF target, we
1214 if (strcmp (TARGET_OS, "elf") != 0)
1216 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1217 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1218 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1221 /* Create a .reginfo section for register masks and a .mdebug
1222 section for debugging information. */
1230 subseg = now_subseg;
1232 /* The ABI says this section should be loaded so that the
1233 running program can access it. However, we don't load it
1234 if we are configured for an embedded target */
1235 flags = SEC_READONLY | SEC_DATA;
1236 if (strcmp (TARGET_OS, "elf") != 0)
1237 flags |= SEC_ALLOC | SEC_LOAD;
1239 if (mips_abi != N64_ABI)
1241 sec = subseg_new (".reginfo", (subsegT) 0);
1243 bfd_set_section_flags (stdoutput, sec, flags);
1244 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1247 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1252 /* The 64-bit ABI uses a .MIPS.options section rather than
1253 .reginfo section. */
1254 sec = subseg_new (".MIPS.options", (subsegT) 0);
1255 bfd_set_section_flags (stdoutput, sec, flags);
1256 bfd_set_section_alignment (stdoutput, sec, 3);
1259 /* Set up the option header. */
1261 Elf_Internal_Options opthdr;
1264 opthdr.kind = ODK_REGINFO;
1265 opthdr.size = (sizeof (Elf_External_Options)
1266 + sizeof (Elf64_External_RegInfo));
1269 f = frag_more (sizeof (Elf_External_Options));
1270 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1271 (Elf_External_Options *) f);
1273 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1278 if (ECOFF_DEBUGGING)
1280 sec = subseg_new (".mdebug", (subsegT) 0);
1281 (void) bfd_set_section_flags (stdoutput, sec,
1282 SEC_HAS_CONTENTS | SEC_READONLY);
1283 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1286 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1288 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1289 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1290 SEC_READONLY | SEC_RELOC
1292 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1296 subseg_set (seg, subseg);
1300 if (! ECOFF_DEBUGGING)
1307 if (! ECOFF_DEBUGGING)
1312 md_assemble (char *str)
1314 struct mips_cl_insn insn;
1315 bfd_reloc_code_real_type unused_reloc[3]
1316 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1318 imm_expr.X_op = O_absent;
1319 offset_expr.X_op = O_absent;
1320 imm_reloc[0] = BFD_RELOC_UNUSED;
1321 imm_reloc[1] = BFD_RELOC_UNUSED;
1322 imm_reloc[2] = BFD_RELOC_UNUSED;
1323 offset_reloc[0] = BFD_RELOC_UNUSED;
1324 offset_reloc[1] = BFD_RELOC_UNUSED;
1325 offset_reloc[2] = BFD_RELOC_UNUSED;
1327 if (mips_opts.mips16)
1328 mips16_ip (str, &insn);
1331 mips_ip (str, &insn);
1332 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1333 str, insn.insn_opcode));
1338 as_bad ("%s `%s'", insn_error, str);
1342 if (insn.insn_mo->pinfo == INSN_MACRO)
1344 if (mips_opts.mips16)
1345 mips16_macro (&insn);
1351 if (imm_expr.X_op != O_absent)
1352 append_insn (NULL, &insn, &imm_expr, imm_reloc);
1353 else if (offset_expr.X_op != O_absent)
1354 append_insn (NULL, &insn, &offset_expr, offset_reloc);
1356 append_insn (NULL, &insn, NULL, unused_reloc);
1360 /* Return true if the given relocation might need a matching %lo().
1361 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1362 applied to local symbols. */
1364 static inline bfd_boolean
1365 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1367 return (reloc == BFD_RELOC_HI16_S
1368 || reloc == BFD_RELOC_MIPS_GOT16);
1371 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1374 static inline bfd_boolean
1375 fixup_has_matching_lo_p (fixS *fixp)
1377 return (fixp->fx_next != NULL
1378 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1379 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1380 && fixp->fx_offset == fixp->fx_next->fx_offset);
1383 /* See whether instruction IP reads register REG. CLASS is the type
1387 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1388 enum mips_regclass class)
1390 if (class == MIPS16_REG)
1392 assert (mips_opts.mips16);
1393 reg = mips16_to_32_reg_map[reg];
1394 class = MIPS_GR_REG;
1397 /* Don't report on general register ZERO, since it never changes. */
1398 if (class == MIPS_GR_REG && reg == ZERO)
1401 if (class == MIPS_FP_REG)
1403 assert (! mips_opts.mips16);
1404 /* If we are called with either $f0 or $f1, we must check $f0.
1405 This is not optimal, because it will introduce an unnecessary
1406 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1407 need to distinguish reading both $f0 and $f1 or just one of
1408 them. Note that we don't have to check the other way,
1409 because there is no instruction that sets both $f0 and $f1
1410 and requires a delay. */
1411 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1412 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1413 == (reg &~ (unsigned) 1)))
1415 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1416 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1417 == (reg &~ (unsigned) 1)))
1420 else if (! mips_opts.mips16)
1422 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1423 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1425 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1426 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1431 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1432 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1433 & MIPS16OP_MASK_RX)]
1436 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1437 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1438 & MIPS16OP_MASK_RY)]
1441 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1442 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1443 & MIPS16OP_MASK_MOVE32Z)]
1446 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1448 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1450 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1452 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1453 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1454 & MIPS16OP_MASK_REGR32) == reg)
1461 /* This function returns true if modifying a register requires a
1465 reg_needs_delay (unsigned int reg)
1467 unsigned long prev_pinfo;
1469 prev_pinfo = prev_insn.insn_mo->pinfo;
1470 if (! mips_opts.noreorder
1471 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1472 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1473 || (! gpr_interlocks
1474 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1476 /* A load from a coprocessor or from memory. All load
1477 delays delay the use of general register rt for one
1478 instruction on the r3000. The r6000 and r4000 use
1480 /* Itbl support may require additional care here. */
1481 know (prev_pinfo & INSN_WRITE_GPR_T);
1482 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1489 /* Mark instruction labels in mips16 mode. This permits the linker to
1490 handle them specially, such as generating jalx instructions when
1491 needed. We also make them odd for the duration of the assembly, in
1492 order to generate the right sort of code. We will make them even
1493 in the adjust_symtab routine, while leaving them marked. This is
1494 convenient for the debugger and the disassembler. The linker knows
1495 to make them odd again. */
1498 mips16_mark_labels (void)
1500 if (mips_opts.mips16)
1502 struct insn_label_list *l;
1505 for (l = insn_labels; l != NULL; l = l->next)
1508 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1509 S_SET_OTHER (l->label, STO_MIPS16);
1511 val = S_GET_VALUE (l->label);
1513 S_SET_VALUE (l->label, val + 1);
1518 /* Output an instruction. PLACE is where to put the instruction; if
1519 it is NULL, this uses frag_more to get room. IP is the instruction
1520 information. ADDRESS_EXPR is an operand of the instruction to be
1521 used with RELOC_TYPE. */
1524 append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr,
1525 bfd_reloc_code_real_type *reloc_type)
1527 register unsigned long prev_pinfo, pinfo;
1531 bfd_boolean force_new_frag = FALSE;
1533 /* Mark instruction labels in mips16 mode. */
1534 mips16_mark_labels ();
1536 prev_pinfo = prev_insn.insn_mo->pinfo;
1537 pinfo = ip->insn_mo->pinfo;
1539 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1543 /* If the previous insn required any delay slots, see if we need
1544 to insert a NOP or two. There are eight kinds of possible
1545 hazards, of which an instruction can have at most one type.
1546 (1) a load from memory delay
1547 (2) a load from a coprocessor delay
1548 (3) an unconditional branch delay
1549 (4) a conditional branch delay
1550 (5) a move to coprocessor register delay
1551 (6) a load coprocessor register from memory delay
1552 (7) a coprocessor condition code delay
1553 (8) a HI/LO special register delay
1555 There are a lot of optimizations we could do that we don't.
1556 In particular, we do not, in general, reorder instructions.
1557 If you use gcc with optimization, it will reorder
1558 instructions and generally do much more optimization then we
1559 do here; repeating all that work in the assembler would only
1560 benefit hand written assembly code, and does not seem worth
1563 /* This is how a NOP is emitted. */
1564 #define emit_nop() \
1566 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1567 : md_number_to_chars (frag_more (4), 0, 4))
1569 /* The previous insn might require a delay slot, depending upon
1570 the contents of the current insn. */
1571 if (! mips_opts.mips16
1572 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1573 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1574 && ! cop_interlocks)
1575 || (! gpr_interlocks
1576 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1578 /* A load from a coprocessor or from memory. All load
1579 delays delay the use of general register rt for one
1580 instruction on the r3000. The r6000 and r4000 use
1582 /* Itbl support may require additional care here. */
1583 know (prev_pinfo & INSN_WRITE_GPR_T);
1584 if (mips_optimize == 0
1585 || insn_uses_reg (ip,
1586 ((prev_insn.insn_opcode >> OP_SH_RT)
1591 else if (! mips_opts.mips16
1592 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1593 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1594 && ! cop_interlocks)
1595 || (mips_opts.isa == ISA_MIPS1
1596 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1598 /* A generic coprocessor delay. The previous instruction
1599 modified a coprocessor general or control register. If
1600 it modified a control register, we need to avoid any
1601 coprocessor instruction (this is probably not always
1602 required, but it sometimes is). If it modified a general
1603 register, we avoid using that register.
1605 On the r6000 and r4000 loading a coprocessor register
1606 from memory is interlocked, and does not require a delay.
1608 This case is not handled very well. There is no special
1609 knowledge of CP0 handling, and the coprocessors other
1610 than the floating point unit are not distinguished at
1612 /* Itbl support may require additional care here. FIXME!
1613 Need to modify this to include knowledge about
1614 user specified delays! */
1615 if (prev_pinfo & INSN_WRITE_FPR_T)
1617 if (mips_optimize == 0
1618 || insn_uses_reg (ip,
1619 ((prev_insn.insn_opcode >> OP_SH_FT)
1624 else if (prev_pinfo & INSN_WRITE_FPR_S)
1626 if (mips_optimize == 0
1627 || insn_uses_reg (ip,
1628 ((prev_insn.insn_opcode >> OP_SH_FS)
1635 /* We don't know exactly what the previous instruction
1636 does. If the current instruction uses a coprocessor
1637 register, we must insert a NOP. If previous
1638 instruction may set the condition codes, and the
1639 current instruction uses them, we must insert two
1641 /* Itbl support may require additional care here. */
1642 if (mips_optimize == 0
1643 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1644 && (pinfo & INSN_READ_COND_CODE)))
1646 else if (pinfo & INSN_COP)
1650 else if (! mips_opts.mips16
1651 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1652 && (prev_pinfo & INSN_WRITE_COND_CODE)
1653 && ! cop_interlocks)
1655 /* The previous instruction sets the coprocessor condition
1656 codes, but does not require a general coprocessor delay
1657 (this means it is a floating point comparison
1658 instruction). If this instruction uses the condition
1659 codes, we need to insert a single NOP. */
1660 /* Itbl support may require additional care here. */
1661 if (mips_optimize == 0
1662 || (pinfo & INSN_READ_COND_CODE))
1666 /* If we're fixing up mfhi/mflo for the r7000 and the
1667 previous insn was an mfhi/mflo and the current insn
1668 reads the register that the mfhi/mflo wrote to, then
1671 else if (mips_7000_hilo_fix
1672 && MF_HILO_INSN (prev_pinfo)
1673 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1680 /* If we're fixing up mfhi/mflo for the r7000 and the
1681 2nd previous insn was an mfhi/mflo and the current insn
1682 reads the register that the mfhi/mflo wrote to, then
1685 else if (mips_7000_hilo_fix
1686 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1687 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1695 else if (prev_pinfo & INSN_READ_LO)
1697 /* The previous instruction reads the LO register; if the
1698 current instruction writes to the LO register, we must
1699 insert two NOPS. Some newer processors have interlocks.
1700 Also the tx39's multiply instructions can be exectuted
1701 immediatly after a read from HI/LO (without the delay),
1702 though the tx39's divide insns still do require the
1704 if (! (hilo_interlocks
1705 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1706 && (mips_optimize == 0
1707 || (pinfo & INSN_WRITE_LO)))
1709 /* Most mips16 branch insns don't have a delay slot.
1710 If a read from LO is immediately followed by a branch
1711 to a write to LO we have a read followed by a write
1712 less than 2 insns away. We assume the target of
1713 a branch might be a write to LO, and insert a nop
1714 between a read and an immediately following branch. */
1715 else if (mips_opts.mips16
1716 && (mips_optimize == 0
1717 || (pinfo & MIPS16_INSN_BRANCH)))
1720 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1722 /* The previous instruction reads the HI register; if the
1723 current instruction writes to the HI register, we must
1724 insert a NOP. Some newer processors have interlocks.
1725 Also the note tx39's multiply above. */
1726 if (! (hilo_interlocks
1727 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1728 && (mips_optimize == 0
1729 || (pinfo & INSN_WRITE_HI)))
1731 /* Most mips16 branch insns don't have a delay slot.
1732 If a read from HI is immediately followed by a branch
1733 to a write to HI we have a read followed by a write
1734 less than 2 insns away. We assume the target of
1735 a branch might be a write to HI, and insert a nop
1736 between a read and an immediately following branch. */
1737 else if (mips_opts.mips16
1738 && (mips_optimize == 0
1739 || (pinfo & MIPS16_INSN_BRANCH)))
1743 /* If the previous instruction was in a noreorder section, then
1744 we don't want to insert the nop after all. */
1745 /* Itbl support may require additional care here. */
1746 if (prev_insn_unreordered)
1749 /* There are two cases which require two intervening
1750 instructions: 1) setting the condition codes using a move to
1751 coprocessor instruction which requires a general coprocessor
1752 delay and then reading the condition codes 2) reading the HI
1753 or LO register and then writing to it (except on processors
1754 which have interlocks). If we are not already emitting a NOP
1755 instruction, we must check for these cases compared to the
1756 instruction previous to the previous instruction. */
1757 if ((! mips_opts.mips16
1758 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1759 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1760 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1761 && (pinfo & INSN_READ_COND_CODE)
1762 && ! cop_interlocks)
1763 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1764 && (pinfo & INSN_WRITE_LO)
1765 && ! (hilo_interlocks
1766 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1767 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1768 && (pinfo & INSN_WRITE_HI)
1769 && ! (hilo_interlocks
1770 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1775 if (prev_prev_insn_unreordered)
1778 if (prev_prev_nop && nops == 0)
1781 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1783 /* We're out of bits in pinfo, so we must resort to string
1784 ops here. Shortcuts are selected based on opcodes being
1785 limited to the VR4122 instruction set. */
1787 const char *pn = prev_insn.insn_mo->name;
1788 const char *tn = ip->insn_mo->name;
1789 if (strncmp(pn, "macc", 4) == 0
1790 || strncmp(pn, "dmacc", 5) == 0)
1792 /* Errata 21 - [D]DIV[U] after [D]MACC */
1793 if (strstr (tn, "div"))
1798 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1799 if (pn[0] == 'd' /* dmacc */
1800 && (strncmp(tn, "dmult", 5) == 0
1801 || strncmp(tn, "dmacc", 5) == 0))
1806 /* Errata 24 - MT{LO,HI} after [D]MACC */
1807 if (strcmp (tn, "mtlo") == 0
1808 || strcmp (tn, "mthi") == 0)
1814 else if (strncmp(pn, "dmult", 5) == 0
1815 && (strncmp(tn, "dmult", 5) == 0
1816 || strncmp(tn, "dmacc", 5) == 0))
1818 /* Here is the rest of errata 23. */
1821 if (nops < min_nops)
1825 /* If we are being given a nop instruction, don't bother with
1826 one of the nops we would otherwise output. This will only
1827 happen when a nop instruction is used with mips_optimize set
1830 && ! mips_opts.noreorder
1831 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1834 /* Now emit the right number of NOP instructions. */
1835 if (nops > 0 && ! mips_opts.noreorder)
1838 unsigned long old_frag_offset;
1840 struct insn_label_list *l;
1842 old_frag = frag_now;
1843 old_frag_offset = frag_now_fix ();
1845 for (i = 0; i < nops; i++)
1850 listing_prev_line ();
1851 /* We may be at the start of a variant frag. In case we
1852 are, make sure there is enough space for the frag
1853 after the frags created by listing_prev_line. The
1854 argument to frag_grow here must be at least as large
1855 as the argument to all other calls to frag_grow in
1856 this file. We don't have to worry about being in the
1857 middle of a variant frag, because the variants insert
1858 all needed nop instructions themselves. */
1862 for (l = insn_labels; l != NULL; l = l->next)
1866 assert (S_GET_SEGMENT (l->label) == now_seg);
1867 symbol_set_frag (l->label, frag_now);
1868 val = (valueT) frag_now_fix ();
1869 /* mips16 text labels are stored as odd. */
1870 if (mips_opts.mips16)
1872 S_SET_VALUE (l->label, val);
1875 #ifndef NO_ECOFF_DEBUGGING
1876 if (ECOFF_DEBUGGING)
1877 ecoff_fix_loc (old_frag, old_frag_offset);
1880 else if (prev_nop_frag != NULL)
1882 /* We have a frag holding nops we may be able to remove. If
1883 we don't need any nops, we can decrease the size of
1884 prev_nop_frag by the size of one instruction. If we do
1885 need some nops, we count them in prev_nops_required. */
1886 if (prev_nop_frag_since == 0)
1890 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1891 --prev_nop_frag_holds;
1894 prev_nop_frag_required += nops;
1898 if (prev_prev_nop == 0)
1900 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1901 --prev_nop_frag_holds;
1904 ++prev_nop_frag_required;
1907 if (prev_nop_frag_holds <= prev_nop_frag_required)
1908 prev_nop_frag = NULL;
1910 ++prev_nop_frag_since;
1912 /* Sanity check: by the time we reach the second instruction
1913 after prev_nop_frag, we should have used up all the nops
1914 one way or another. */
1915 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1921 && *reloc_type == BFD_RELOC_16_PCREL_S2
1922 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1923 || pinfo & INSN_COND_BRANCH_LIKELY)
1924 && mips_relax_branch
1925 /* Don't try branch relaxation within .set nomacro, or within
1926 .set noat if we use $at for PIC computations. If it turns
1927 out that the branch was out-of-range, we'll get an error. */
1928 && !mips_opts.warn_about_macros
1929 && !(mips_opts.noat && mips_pic != NO_PIC)
1930 && !mips_opts.mips16)
1932 f = frag_var (rs_machine_dependent,
1933 relaxed_branch_length
1935 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
1936 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
1938 (pinfo & INSN_UNCOND_BRANCH_DELAY,
1939 pinfo & INSN_COND_BRANCH_LIKELY,
1940 pinfo & INSN_WRITE_GPR_31,
1942 address_expr->X_add_symbol,
1943 address_expr->X_add_number,
1945 *reloc_type = BFD_RELOC_UNUSED;
1947 else if (*reloc_type > BFD_RELOC_UNUSED)
1949 /* We need to set up a variant frag. */
1950 assert (mips_opts.mips16 && address_expr != NULL);
1951 f = frag_var (rs_machine_dependent, 4, 0,
1952 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1953 mips16_small, mips16_ext,
1955 & INSN_UNCOND_BRANCH_DELAY),
1956 (*prev_insn_reloc_type
1957 == BFD_RELOC_MIPS16_JMP)),
1958 make_expr_symbol (address_expr), 0, NULL);
1960 else if (place != NULL)
1962 else if (mips_opts.mips16
1964 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1966 /* Make sure there is enough room to swap this instruction with
1967 a following jump instruction. */
1973 if (mips_opts.mips16
1974 && mips_opts.noreorder
1975 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1976 as_warn (_("extended instruction in delay slot"));
1981 fixp[0] = fixp[1] = fixp[2] = NULL;
1982 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1984 if (address_expr->X_op == O_constant)
1988 switch (*reloc_type)
1991 ip->insn_opcode |= address_expr->X_add_number;
1994 case BFD_RELOC_MIPS_HIGHEST:
1995 tmp = (address_expr->X_add_number
1996 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
1998 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2001 case BFD_RELOC_MIPS_HIGHER:
2002 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2003 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2006 case BFD_RELOC_HI16_S:
2007 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2011 case BFD_RELOC_HI16:
2012 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2015 case BFD_RELOC_LO16:
2016 case BFD_RELOC_MIPS_GOT_DISP:
2017 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2020 case BFD_RELOC_MIPS_JMP:
2021 if ((address_expr->X_add_number & 3) != 0)
2022 as_bad (_("jump to misaligned address (0x%lx)"),
2023 (unsigned long) address_expr->X_add_number);
2024 if (address_expr->X_add_number & ~0xfffffff)
2025 as_bad (_("jump address range overflow (0x%lx)"),
2026 (unsigned long) address_expr->X_add_number);
2027 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2030 case BFD_RELOC_MIPS16_JMP:
2031 if ((address_expr->X_add_number & 3) != 0)
2032 as_bad (_("jump to misaligned address (0x%lx)"),
2033 (unsigned long) address_expr->X_add_number);
2034 if (address_expr->X_add_number & ~0xfffffff)
2035 as_bad (_("jump address range overflow (0x%lx)"),
2036 (unsigned long) address_expr->X_add_number);
2038 (((address_expr->X_add_number & 0x7c0000) << 3)
2039 | ((address_expr->X_add_number & 0xf800000) >> 7)
2040 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2043 case BFD_RELOC_16_PCREL_S2:
2053 /* Don't generate a reloc if we are writing into a variant frag. */
2056 reloc_howto_type *howto;
2059 /* In a compound relocation, it is the final (outermost)
2060 operator that determines the relocated field. */
2061 for (i = 1; i < 3; i++)
2062 if (reloc_type[i] == BFD_RELOC_UNUSED)
2065 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2066 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2067 bfd_get_reloc_size(howto),
2069 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2072 /* These relocations can have an addend that won't fit in
2073 4 octets for 64bit assembly. */
2075 && ! howto->partial_inplace
2076 && (reloc_type[0] == BFD_RELOC_16
2077 || reloc_type[0] == BFD_RELOC_32
2078 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2079 || reloc_type[0] == BFD_RELOC_HI16_S
2080 || reloc_type[0] == BFD_RELOC_LO16
2081 || reloc_type[0] == BFD_RELOC_GPREL16
2082 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2083 || reloc_type[0] == BFD_RELOC_GPREL32
2084 || reloc_type[0] == BFD_RELOC_64
2085 || reloc_type[0] == BFD_RELOC_CTOR
2086 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2087 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2088 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2089 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2090 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2091 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2092 fixp[0]->fx_no_overflow = 1;
2094 if (reloc_needs_lo_p (*reloc_type))
2096 struct mips_hi_fixup *hi_fixup;
2098 /* Reuse the last entry if it already has a matching %lo. */
2099 hi_fixup = mips_hi_fixup_list;
2101 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2103 hi_fixup = ((struct mips_hi_fixup *)
2104 xmalloc (sizeof (struct mips_hi_fixup)));
2105 hi_fixup->next = mips_hi_fixup_list;
2106 mips_hi_fixup_list = hi_fixup;
2108 hi_fixup->fixp = fixp[0];
2109 hi_fixup->seg = now_seg;
2112 /* Add fixups for the second and third relocations, if given.
2113 Note that the ABI allows the second relocation to be
2114 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2115 moment we only use RSS_UNDEF, but we could add support
2116 for the others if it ever becomes necessary. */
2117 for (i = 1; i < 3; i++)
2118 if (reloc_type[i] != BFD_RELOC_UNUSED)
2120 address_expr->X_op = O_absent;
2121 address_expr->X_add_symbol = 0;
2122 address_expr->X_add_number = 0;
2124 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2125 fixp[0]->fx_size, address_expr,
2126 FALSE, reloc_type[i]);
2132 if (! mips_opts.mips16)
2134 md_number_to_chars (f, ip->insn_opcode, 4);
2136 dwarf2_emit_insn (4);
2139 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2141 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2142 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2144 dwarf2_emit_insn (4);
2151 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2154 md_number_to_chars (f, ip->insn_opcode, 2);
2156 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2160 /* Update the register mask information. */
2161 if (! mips_opts.mips16)
2163 if (pinfo & INSN_WRITE_GPR_D)
2164 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2165 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2166 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2167 if (pinfo & INSN_READ_GPR_S)
2168 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2169 if (pinfo & INSN_WRITE_GPR_31)
2170 mips_gprmask |= 1 << RA;
2171 if (pinfo & INSN_WRITE_FPR_D)
2172 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2173 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2174 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2175 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2176 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2177 if ((pinfo & INSN_READ_FPR_R) != 0)
2178 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2179 if (pinfo & INSN_COP)
2181 /* We don't keep enough information to sort these cases out.
2182 The itbl support does keep this information however, although
2183 we currently don't support itbl fprmats as part of the cop
2184 instruction. May want to add this support in the future. */
2186 /* Never set the bit for $0, which is always zero. */
2187 mips_gprmask &= ~1 << 0;
2191 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2192 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2193 & MIPS16OP_MASK_RX);
2194 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2195 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2196 & MIPS16OP_MASK_RY);
2197 if (pinfo & MIPS16_INSN_WRITE_Z)
2198 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2199 & MIPS16OP_MASK_RZ);
2200 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2201 mips_gprmask |= 1 << TREG;
2202 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2203 mips_gprmask |= 1 << SP;
2204 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2205 mips_gprmask |= 1 << RA;
2206 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2207 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2208 if (pinfo & MIPS16_INSN_READ_Z)
2209 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2210 & MIPS16OP_MASK_MOVE32Z);
2211 if (pinfo & MIPS16_INSN_READ_GPR_X)
2212 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2213 & MIPS16OP_MASK_REGR32);
2216 if (place == NULL && ! mips_opts.noreorder)
2218 /* Filling the branch delay slot is more complex. We try to
2219 switch the branch with the previous instruction, which we can
2220 do if the previous instruction does not set up a condition
2221 that the branch tests and if the branch is not itself the
2222 target of any branch. */
2223 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2224 || (pinfo & INSN_COND_BRANCH_DELAY))
2226 if (mips_optimize < 2
2227 /* If we have seen .set volatile or .set nomove, don't
2229 || mips_opts.nomove != 0
2230 /* If we had to emit any NOP instructions, then we
2231 already know we can not swap. */
2233 /* If we don't even know the previous insn, we can not
2235 || ! prev_insn_valid
2236 /* If the previous insn is already in a branch delay
2237 slot, then we can not swap. */
2238 || prev_insn_is_delay_slot
2239 /* If the previous previous insn was in a .set
2240 noreorder, we can't swap. Actually, the MIPS
2241 assembler will swap in this situation. However, gcc
2242 configured -with-gnu-as will generate code like
2248 in which we can not swap the bne and INSN. If gcc is
2249 not configured -with-gnu-as, it does not output the
2250 .set pseudo-ops. We don't have to check
2251 prev_insn_unreordered, because prev_insn_valid will
2252 be 0 in that case. We don't want to use
2253 prev_prev_insn_valid, because we do want to be able
2254 to swap at the start of a function. */
2255 || prev_prev_insn_unreordered
2256 /* If the branch is itself the target of a branch, we
2257 can not swap. We cheat on this; all we check for is
2258 whether there is a label on this instruction. If
2259 there are any branches to anything other than a
2260 label, users must use .set noreorder. */
2261 || insn_labels != NULL
2262 /* If the previous instruction is in a variant frag, we
2263 can not do the swap. This does not apply to the
2264 mips16, which uses variant frags for different
2266 || (! mips_opts.mips16
2267 && prev_insn_frag->fr_type == rs_machine_dependent)
2268 /* If the branch reads the condition codes, we don't
2269 even try to swap, because in the sequence
2274 we can not swap, and I don't feel like handling that
2276 || (! mips_opts.mips16
2277 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2278 && (pinfo & INSN_READ_COND_CODE))
2279 /* We can not swap with an instruction that requires a
2280 delay slot, becase the target of the branch might
2281 interfere with that instruction. */
2282 || (! mips_opts.mips16
2283 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2285 /* Itbl support may require additional care here. */
2286 & (INSN_LOAD_COPROC_DELAY
2287 | INSN_COPROC_MOVE_DELAY
2288 | INSN_WRITE_COND_CODE)))
2289 || (! (hilo_interlocks
2290 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2294 || (! mips_opts.mips16
2296 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2297 || (! mips_opts.mips16
2298 && mips_opts.isa == ISA_MIPS1
2299 /* Itbl support may require additional care here. */
2300 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2301 /* We can not swap with a branch instruction. */
2303 & (INSN_UNCOND_BRANCH_DELAY
2304 | INSN_COND_BRANCH_DELAY
2305 | INSN_COND_BRANCH_LIKELY))
2306 /* We do not swap with a trap instruction, since it
2307 complicates trap handlers to have the trap
2308 instruction be in a delay slot. */
2309 || (prev_pinfo & INSN_TRAP)
2310 /* If the branch reads a register that the previous
2311 instruction sets, we can not swap. */
2312 || (! mips_opts.mips16
2313 && (prev_pinfo & INSN_WRITE_GPR_T)
2314 && insn_uses_reg (ip,
2315 ((prev_insn.insn_opcode >> OP_SH_RT)
2318 || (! mips_opts.mips16
2319 && (prev_pinfo & INSN_WRITE_GPR_D)
2320 && insn_uses_reg (ip,
2321 ((prev_insn.insn_opcode >> OP_SH_RD)
2324 || (mips_opts.mips16
2325 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2326 && insn_uses_reg (ip,
2327 ((prev_insn.insn_opcode
2329 & MIPS16OP_MASK_RX),
2331 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2332 && insn_uses_reg (ip,
2333 ((prev_insn.insn_opcode
2335 & MIPS16OP_MASK_RY),
2337 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2338 && insn_uses_reg (ip,
2339 ((prev_insn.insn_opcode
2341 & MIPS16OP_MASK_RZ),
2343 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2344 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2345 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2346 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2347 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2348 && insn_uses_reg (ip,
2349 MIPS16OP_EXTRACT_REG32R (prev_insn.
2352 /* If the branch writes a register that the previous
2353 instruction sets, we can not swap (we know that
2354 branches write only to RD or to $31). */
2355 || (! mips_opts.mips16
2356 && (prev_pinfo & INSN_WRITE_GPR_T)
2357 && (((pinfo & INSN_WRITE_GPR_D)
2358 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2359 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2360 || ((pinfo & INSN_WRITE_GPR_31)
2361 && (((prev_insn.insn_opcode >> OP_SH_RT)
2364 || (! mips_opts.mips16
2365 && (prev_pinfo & INSN_WRITE_GPR_D)
2366 && (((pinfo & INSN_WRITE_GPR_D)
2367 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2368 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2369 || ((pinfo & INSN_WRITE_GPR_31)
2370 && (((prev_insn.insn_opcode >> OP_SH_RD)
2373 || (mips_opts.mips16
2374 && (pinfo & MIPS16_INSN_WRITE_31)
2375 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2376 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2377 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2379 /* If the branch writes a register that the previous
2380 instruction reads, we can not swap (we know that
2381 branches only write to RD or to $31). */
2382 || (! mips_opts.mips16
2383 && (pinfo & INSN_WRITE_GPR_D)
2384 && insn_uses_reg (&prev_insn,
2385 ((ip->insn_opcode >> OP_SH_RD)
2388 || (! mips_opts.mips16
2389 && (pinfo & INSN_WRITE_GPR_31)
2390 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2391 || (mips_opts.mips16
2392 && (pinfo & MIPS16_INSN_WRITE_31)
2393 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2394 /* If we are generating embedded PIC code, the branch
2395 might be expanded into a sequence which uses $at, so
2396 we can't swap with an instruction which reads it. */
2397 || (mips_pic == EMBEDDED_PIC
2398 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2399 /* If the previous previous instruction has a load
2400 delay, and sets a register that the branch reads, we
2402 || (! mips_opts.mips16
2403 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2404 /* Itbl support may require additional care here. */
2405 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2406 || (! gpr_interlocks
2407 && (prev_prev_insn.insn_mo->pinfo
2408 & INSN_LOAD_MEMORY_DELAY)))
2409 && insn_uses_reg (ip,
2410 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2413 /* If one instruction sets a condition code and the
2414 other one uses a condition code, we can not swap. */
2415 || ((pinfo & INSN_READ_COND_CODE)
2416 && (prev_pinfo & INSN_WRITE_COND_CODE))
2417 || ((pinfo & INSN_WRITE_COND_CODE)
2418 && (prev_pinfo & INSN_READ_COND_CODE))
2419 /* If the previous instruction uses the PC, we can not
2421 || (mips_opts.mips16
2422 && (prev_pinfo & MIPS16_INSN_READ_PC))
2423 /* If the previous instruction was extended, we can not
2425 || (mips_opts.mips16 && prev_insn_extended)
2426 /* If the previous instruction had a fixup in mips16
2427 mode, we can not swap. This normally means that the
2428 previous instruction was a 4 byte branch anyhow. */
2429 || (mips_opts.mips16 && prev_insn_fixp[0])
2430 /* If the previous instruction is a sync, sync.l, or
2431 sync.p, we can not swap. */
2432 || (prev_pinfo & INSN_SYNC))
2434 /* We could do even better for unconditional branches to
2435 portions of this object file; we could pick up the
2436 instruction at the destination, put it in the delay
2437 slot, and bump the destination address. */
2439 /* Update the previous insn information. */
2440 prev_prev_insn = *ip;
2441 prev_insn.insn_mo = &dummy_opcode;
2445 /* It looks like we can actually do the swap. */
2446 if (! mips_opts.mips16)
2451 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2452 memcpy (temp, prev_f, 4);
2453 memcpy (prev_f, f, 4);
2454 memcpy (f, temp, 4);
2455 if (prev_insn_fixp[0])
2457 prev_insn_fixp[0]->fx_frag = frag_now;
2458 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2460 if (prev_insn_fixp[1])
2462 prev_insn_fixp[1]->fx_frag = frag_now;
2463 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2465 if (prev_insn_fixp[2])
2467 prev_insn_fixp[2]->fx_frag = frag_now;
2468 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2470 if (prev_insn_fixp[0] && HAVE_NEWABI
2471 && prev_insn_frag != frag_now
2472 && (prev_insn_fixp[0]->fx_r_type
2473 == BFD_RELOC_MIPS_GOT_DISP
2474 || (prev_insn_fixp[0]->fx_r_type
2475 == BFD_RELOC_MIPS_CALL16)))
2477 /* To avoid confusion in tc_gen_reloc, we must
2478 ensure that this does not become a variant
2480 force_new_frag = TRUE;
2484 fixp[0]->fx_frag = prev_insn_frag;
2485 fixp[0]->fx_where = prev_insn_where;
2489 fixp[1]->fx_frag = prev_insn_frag;
2490 fixp[1]->fx_where = prev_insn_where;
2494 fixp[2]->fx_frag = prev_insn_frag;
2495 fixp[2]->fx_where = prev_insn_where;
2503 assert (prev_insn_fixp[0] == NULL);
2504 assert (prev_insn_fixp[1] == NULL);
2505 assert (prev_insn_fixp[2] == NULL);
2506 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2507 memcpy (temp, prev_f, 2);
2508 memcpy (prev_f, f, 2);
2509 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2511 assert (*reloc_type == BFD_RELOC_UNUSED);
2512 memcpy (f, temp, 2);
2516 memcpy (f, f + 2, 2);
2517 memcpy (f + 2, temp, 2);
2521 fixp[0]->fx_frag = prev_insn_frag;
2522 fixp[0]->fx_where = prev_insn_where;
2526 fixp[1]->fx_frag = prev_insn_frag;
2527 fixp[1]->fx_where = prev_insn_where;
2531 fixp[2]->fx_frag = prev_insn_frag;
2532 fixp[2]->fx_where = prev_insn_where;
2536 /* Update the previous insn information; leave prev_insn
2538 prev_prev_insn = *ip;
2540 prev_insn_is_delay_slot = 1;
2542 /* If that was an unconditional branch, forget the previous
2543 insn information. */
2544 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2546 prev_prev_insn.insn_mo = &dummy_opcode;
2547 prev_insn.insn_mo = &dummy_opcode;
2550 prev_insn_fixp[0] = NULL;
2551 prev_insn_fixp[1] = NULL;
2552 prev_insn_fixp[2] = NULL;
2553 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2554 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2555 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2556 prev_insn_extended = 0;
2558 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2560 /* We don't yet optimize a branch likely. What we should do
2561 is look at the target, copy the instruction found there
2562 into the delay slot, and increment the branch to jump to
2563 the next instruction. */
2565 /* Update the previous insn information. */
2566 prev_prev_insn = *ip;
2567 prev_insn.insn_mo = &dummy_opcode;
2568 prev_insn_fixp[0] = NULL;
2569 prev_insn_fixp[1] = NULL;
2570 prev_insn_fixp[2] = NULL;
2571 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2572 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2573 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2574 prev_insn_extended = 0;
2578 /* Update the previous insn information. */
2580 prev_prev_insn.insn_mo = &dummy_opcode;
2582 prev_prev_insn = prev_insn;
2585 /* Any time we see a branch, we always fill the delay slot
2586 immediately; since this insn is not a branch, we know it
2587 is not in a delay slot. */
2588 prev_insn_is_delay_slot = 0;
2590 prev_insn_fixp[0] = fixp[0];
2591 prev_insn_fixp[1] = fixp[1];
2592 prev_insn_fixp[2] = fixp[2];
2593 prev_insn_reloc_type[0] = reloc_type[0];
2594 prev_insn_reloc_type[1] = reloc_type[1];
2595 prev_insn_reloc_type[2] = reloc_type[2];
2596 if (mips_opts.mips16)
2597 prev_insn_extended = (ip->use_extend
2598 || *reloc_type > BFD_RELOC_UNUSED);
2601 prev_prev_insn_unreordered = prev_insn_unreordered;
2602 prev_insn_unreordered = 0;
2603 prev_insn_frag = frag_now;
2604 prev_insn_where = f - frag_now->fr_literal;
2605 prev_insn_valid = 1;
2607 else if (place == NULL)
2609 /* We need to record a bit of information even when we are not
2610 reordering, in order to determine the base address for mips16
2611 PC relative relocs. */
2612 prev_prev_insn = prev_insn;
2614 prev_insn_reloc_type[0] = reloc_type[0];
2615 prev_insn_reloc_type[1] = reloc_type[1];
2616 prev_insn_reloc_type[2] = reloc_type[2];
2617 prev_prev_insn_unreordered = prev_insn_unreordered;
2618 prev_insn_unreordered = 1;
2621 /* We just output an insn, so the next one doesn't have a label. */
2622 mips_clear_insn_labels ();
2624 /* We must ensure that the frag to which an instruction that was
2625 moved from a non-variant frag doesn't become a variant frag,
2626 otherwise tc_gen_reloc may get confused. */
2629 frag_wane (frag_now);
2634 /* This function forgets that there was any previous instruction or
2635 label. If PRESERVE is non-zero, it remembers enough information to
2636 know whether nops are needed before a noreorder section. */
2639 mips_no_prev_insn (int preserve)
2643 prev_insn.insn_mo = &dummy_opcode;
2644 prev_prev_insn.insn_mo = &dummy_opcode;
2645 prev_nop_frag = NULL;
2646 prev_nop_frag_holds = 0;
2647 prev_nop_frag_required = 0;
2648 prev_nop_frag_since = 0;
2650 prev_insn_valid = 0;
2651 prev_insn_is_delay_slot = 0;
2652 prev_insn_unreordered = 0;
2653 prev_insn_extended = 0;
2654 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2655 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2656 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2657 prev_prev_insn_unreordered = 0;
2658 mips_clear_insn_labels ();
2661 /* This function must be called whenever we turn on noreorder or emit
2662 something other than instructions. It inserts any NOPS which might
2663 be needed by the previous instruction, and clears the information
2664 kept for the previous instructions. The INSNS parameter is true if
2665 instructions are to follow. */
2668 mips_emit_delays (bfd_boolean insns)
2670 if (! mips_opts.noreorder)
2675 if ((! mips_opts.mips16
2676 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2677 && (! cop_interlocks
2678 && (prev_insn.insn_mo->pinfo
2679 & (INSN_LOAD_COPROC_DELAY
2680 | INSN_COPROC_MOVE_DELAY
2681 | INSN_WRITE_COND_CODE))))
2682 || (! hilo_interlocks
2683 && (prev_insn.insn_mo->pinfo
2686 || (! mips_opts.mips16
2688 && (prev_insn.insn_mo->pinfo
2689 & INSN_LOAD_MEMORY_DELAY))
2690 || (! mips_opts.mips16
2691 && mips_opts.isa == ISA_MIPS1
2692 && (prev_insn.insn_mo->pinfo
2693 & INSN_COPROC_MEMORY_DELAY)))
2695 /* Itbl support may require additional care here. */
2697 if ((! mips_opts.mips16
2698 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2699 && (! cop_interlocks
2700 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2701 || (! hilo_interlocks
2702 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2703 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2706 if (prev_insn_unreordered)
2709 else if ((! mips_opts.mips16
2710 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2711 && (! cop_interlocks
2712 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2713 || (! hilo_interlocks
2714 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2715 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2717 /* Itbl support may require additional care here. */
2718 if (! prev_prev_insn_unreordered)
2722 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2725 const char *pn = prev_insn.insn_mo->name;
2726 if (strncmp(pn, "macc", 4) == 0
2727 || strncmp(pn, "dmacc", 5) == 0
2728 || strncmp(pn, "dmult", 5) == 0)
2732 if (nops < min_nops)
2738 struct insn_label_list *l;
2742 /* Record the frag which holds the nop instructions, so
2743 that we can remove them if we don't need them. */
2744 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2745 prev_nop_frag = frag_now;
2746 prev_nop_frag_holds = nops;
2747 prev_nop_frag_required = 0;
2748 prev_nop_frag_since = 0;
2751 for (; nops > 0; --nops)
2756 /* Move on to a new frag, so that it is safe to simply
2757 decrease the size of prev_nop_frag. */
2758 frag_wane (frag_now);
2762 for (l = insn_labels; l != NULL; l = l->next)
2766 assert (S_GET_SEGMENT (l->label) == now_seg);
2767 symbol_set_frag (l->label, frag_now);
2768 val = (valueT) frag_now_fix ();
2769 /* mips16 text labels are stored as odd. */
2770 if (mips_opts.mips16)
2772 S_SET_VALUE (l->label, val);
2777 /* Mark instruction labels in mips16 mode. */
2779 mips16_mark_labels ();
2781 mips_no_prev_insn (insns);
2784 /* Build an instruction created by a macro expansion. This is passed
2785 a pointer to the count of instructions created so far, an
2786 expression, the name of the instruction to build, an operand format
2787 string, and corresponding arguments. */
2790 macro_build (char *place, int *counter, expressionS *ep, const char *name,
2791 const char *fmt, ...)
2793 struct mips_cl_insn insn;
2794 bfd_reloc_code_real_type r[3];
2797 va_start (args, fmt);
2800 * If the macro is about to expand into a second instruction,
2801 * print a warning if needed. We need to pass ip as a parameter
2802 * to generate a better warning message here...
2804 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2805 as_warn (_("Macro instruction expanded into multiple instructions"));
2808 * If the macro is about to expand into a second instruction,
2809 * and it is in a delay slot, print a warning.
2813 && mips_opts.noreorder
2814 && (prev_prev_insn.insn_mo->pinfo
2815 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2816 | INSN_COND_BRANCH_LIKELY)) != 0)
2817 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2820 ++*counter; /* bump instruction counter */
2822 if (mips_opts.mips16)
2824 mips16_macro_build (place, counter, ep, name, fmt, args);
2829 r[0] = BFD_RELOC_UNUSED;
2830 r[1] = BFD_RELOC_UNUSED;
2831 r[2] = BFD_RELOC_UNUSED;
2832 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2833 assert (insn.insn_mo);
2834 assert (strcmp (name, insn.insn_mo->name) == 0);
2836 /* Search until we get a match for NAME. */
2839 /* It is assumed here that macros will never generate
2840 MDMX or MIPS-3D instructions. */
2841 if (strcmp (fmt, insn.insn_mo->args) == 0
2842 && insn.insn_mo->pinfo != INSN_MACRO
2843 && OPCODE_IS_MEMBER (insn.insn_mo,
2845 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2847 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2851 assert (insn.insn_mo->name);
2852 assert (strcmp (name, insn.insn_mo->name) == 0);
2855 insn.insn_opcode = insn.insn_mo->match;
2871 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2875 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2880 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2886 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2891 int tmp = va_arg (args, int);
2893 insn.insn_opcode |= tmp << OP_SH_RT;
2894 insn.insn_opcode |= tmp << OP_SH_RD;
2900 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2907 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2911 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2915 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2919 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2923 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2930 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2936 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2937 assert (*r == BFD_RELOC_GPREL16
2938 || *r == BFD_RELOC_MIPS_LITERAL
2939 || *r == BFD_RELOC_MIPS_HIGHER
2940 || *r == BFD_RELOC_HI16_S
2941 || *r == BFD_RELOC_LO16
2942 || *r == BFD_RELOC_MIPS_GOT16
2943 || *r == BFD_RELOC_MIPS_CALL16
2944 || *r == BFD_RELOC_MIPS_GOT_DISP
2945 || *r == BFD_RELOC_MIPS_GOT_PAGE
2946 || *r == BFD_RELOC_MIPS_GOT_OFST
2947 || *r == BFD_RELOC_MIPS_GOT_LO16
2948 || *r == BFD_RELOC_MIPS_CALL_LO16
2949 || (ep->X_op == O_subtract
2950 && *r == BFD_RELOC_PCREL_LO16));
2954 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2956 && (ep->X_op == O_constant
2957 || (ep->X_op == O_symbol
2958 && (*r == BFD_RELOC_MIPS_HIGHEST
2959 || *r == BFD_RELOC_HI16_S
2960 || *r == BFD_RELOC_HI16
2961 || *r == BFD_RELOC_GPREL16
2962 || *r == BFD_RELOC_MIPS_GOT_HI16
2963 || *r == BFD_RELOC_MIPS_CALL_HI16))
2964 || (ep->X_op == O_subtract
2965 && *r == BFD_RELOC_PCREL_HI16_S)));
2969 assert (ep != NULL);
2971 * This allows macro() to pass an immediate expression for
2972 * creating short branches without creating a symbol.
2973 * Note that the expression still might come from the assembly
2974 * input, in which case the value is not checked for range nor
2975 * is a relocation entry generated (yuck).
2977 if (ep->X_op == O_constant)
2979 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2983 *r = BFD_RELOC_16_PCREL_S2;
2987 assert (ep != NULL);
2988 *r = BFD_RELOC_MIPS_JMP;
2992 insn.insn_opcode |= va_arg (args, unsigned long);
3001 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3003 append_insn (place, &insn, ep, r);
3007 mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED,
3008 expressionS *ep, const char *name, const char *fmt,
3011 struct mips_cl_insn insn;
3012 bfd_reloc_code_real_type r[3]
3013 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3015 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3016 assert (insn.insn_mo);
3017 assert (strcmp (name, insn.insn_mo->name) == 0);
3019 while (strcmp (fmt, insn.insn_mo->args) != 0
3020 || insn.insn_mo->pinfo == INSN_MACRO)
3023 assert (insn.insn_mo->name);
3024 assert (strcmp (name, insn.insn_mo->name) == 0);
3027 insn.insn_opcode = insn.insn_mo->match;
3028 insn.use_extend = FALSE;
3047 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3052 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3056 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3060 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3070 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3077 regno = va_arg (args, int);
3078 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3079 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3100 assert (ep != NULL);
3102 if (ep->X_op != O_constant)
3103 *r = (int) BFD_RELOC_UNUSED + c;
3106 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3107 FALSE, &insn.insn_opcode, &insn.use_extend,
3110 *r = BFD_RELOC_UNUSED;
3116 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3123 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3125 append_insn (place, &insn, ep, r);
3129 * Generate a "jalr" instruction with a relocation hint to the called
3130 * function. This occurs in NewABI PIC code.
3133 macro_build_jalr (int icnt, expressionS *ep)
3142 macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3144 fix_new_exp (frag_now, f - frag_now->fr_literal,
3145 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3149 * Generate a "lui" instruction.
3152 macro_build_lui (char *place, int *counter, expressionS *ep, int regnum)
3154 expressionS high_expr;
3155 struct mips_cl_insn insn;
3156 bfd_reloc_code_real_type r[3]
3157 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3158 const char *name = "lui";
3159 const char *fmt = "t,u";
3161 assert (! mips_opts.mips16);
3167 high_expr.X_op = O_constant;
3168 high_expr.X_add_number = ep->X_add_number;
3171 if (high_expr.X_op == O_constant)
3173 /* we can compute the instruction now without a relocation entry */
3174 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3176 *r = BFD_RELOC_UNUSED;
3180 assert (ep->X_op == O_symbol);
3181 /* _gp_disp is a special case, used from s_cpload. */
3182 assert (mips_pic == NO_PIC
3184 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3185 *r = BFD_RELOC_HI16_S;
3189 * If the macro is about to expand into a second instruction,
3190 * print a warning if needed. We need to pass ip as a parameter
3191 * to generate a better warning message here...
3193 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3194 as_warn (_("Macro instruction expanded into multiple instructions"));
3197 ++*counter; /* bump instruction counter */
3199 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3200 assert (insn.insn_mo);
3201 assert (strcmp (name, insn.insn_mo->name) == 0);
3202 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3204 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3205 if (*r == BFD_RELOC_UNUSED)
3207 insn.insn_opcode |= high_expr.X_add_number;
3208 append_insn (place, &insn, NULL, r);
3211 append_insn (place, &insn, &high_expr, r);
3214 /* Generate a sequence of instructions to do a load or store from a constant
3215 offset off of a base register (breg) into/from a target register (treg),
3216 using AT if necessary. */
3218 macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
3219 const char *op, int treg, int breg)
3221 assert (ep->X_op == O_constant);
3223 /* Right now, this routine can only handle signed 32-bit contants. */
3224 if (! IS_SEXT_32BIT_NUM(ep->X_add_number))
3225 as_warn (_("operand overflow"));
3227 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3229 /* Signed 16-bit offset will fit in the op. Easy! */
3230 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3235 /* 32-bit offset, need multiple instructions and AT, like:
3236 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3237 addu $tempreg,$tempreg,$breg
3238 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3239 to handle the complete offset. */
3240 macro_build_lui (place, counter, ep, AT);
3243 macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
3247 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3251 as_warn (_("Macro used $at after \".set noat\""));
3256 * Generates code to set the $at register to true (one)
3257 * if reg is less than the immediate expression.
3260 set_at (int *counter, int reg, int unsignedp)
3262 if (imm_expr.X_op == O_constant
3263 && imm_expr.X_add_number >= -0x8000
3264 && imm_expr.X_add_number < 0x8000)
3265 macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
3266 "t,r,j", AT, reg, BFD_RELOC_LO16);
3269 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3270 macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
3271 "d,v,t", AT, reg, AT);
3275 /* Warn if an expression is not a constant. */
3278 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3280 if (ex->X_op == O_big)
3281 as_bad (_("unsupported large constant"));
3282 else if (ex->X_op != O_constant)
3283 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3286 /* Count the leading zeroes by performing a binary chop. This is a
3287 bulky bit of source, but performance is a LOT better for the
3288 majority of values than a simple loop to count the bits:
3289 for (lcnt = 0; (lcnt < 32); lcnt++)
3290 if ((v) & (1 << (31 - lcnt)))
3292 However it is not code size friendly, and the gain will drop a bit
3293 on certain cached systems.
3295 #define COUNT_TOP_ZEROES(v) \
3296 (((v) & ~0xffff) == 0 \
3297 ? ((v) & ~0xff) == 0 \
3298 ? ((v) & ~0xf) == 0 \
3299 ? ((v) & ~0x3) == 0 \
3300 ? ((v) & ~0x1) == 0 \
3305 : ((v) & ~0x7) == 0 \
3308 : ((v) & ~0x3f) == 0 \
3309 ? ((v) & ~0x1f) == 0 \
3312 : ((v) & ~0x7f) == 0 \
3315 : ((v) & ~0xfff) == 0 \
3316 ? ((v) & ~0x3ff) == 0 \
3317 ? ((v) & ~0x1ff) == 0 \
3320 : ((v) & ~0x7ff) == 0 \
3323 : ((v) & ~0x3fff) == 0 \
3324 ? ((v) & ~0x1fff) == 0 \
3327 : ((v) & ~0x7fff) == 0 \
3330 : ((v) & ~0xffffff) == 0 \
3331 ? ((v) & ~0xfffff) == 0 \
3332 ? ((v) & ~0x3ffff) == 0 \
3333 ? ((v) & ~0x1ffff) == 0 \
3336 : ((v) & ~0x7ffff) == 0 \
3339 : ((v) & ~0x3fffff) == 0 \
3340 ? ((v) & ~0x1fffff) == 0 \
3343 : ((v) & ~0x7fffff) == 0 \
3346 : ((v) & ~0xfffffff) == 0 \
3347 ? ((v) & ~0x3ffffff) == 0 \
3348 ? ((v) & ~0x1ffffff) == 0 \
3351 : ((v) & ~0x7ffffff) == 0 \
3354 : ((v) & ~0x3fffffff) == 0 \
3355 ? ((v) & ~0x1fffffff) == 0 \
3358 : ((v) & ~0x7fffffff) == 0 \
3363 * This routine generates the least number of instructions neccessary to load
3364 * an absolute expression value into a register.
3367 load_register (int *counter, int reg, expressionS *ep, int dbl)
3370 expressionS hi32, lo32;
3372 if (ep->X_op != O_big)
3374 assert (ep->X_op == O_constant);
3375 if (ep->X_add_number < 0x8000
3376 && (ep->X_add_number >= 0
3377 || (ep->X_add_number >= -0x8000
3380 || sizeof (ep->X_add_number) > 4))))
3382 /* We can handle 16 bit signed values with an addiu to
3383 $zero. No need to ever use daddiu here, since $zero and
3384 the result are always correct in 32 bit mode. */
3385 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3389 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3391 /* We can handle 16 bit unsigned values with an ori to
3393 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
3397 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3400 || sizeof (ep->X_add_number) > 4
3401 || (ep->X_add_number & 0x80000000) == 0))
3402 || ((HAVE_32BIT_GPRS || ! dbl)
3403 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3406 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3407 == ~ (offsetT) 0xffffffff)))
3409 /* 32 bit values require an lui. */
3410 macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3411 if ((ep->X_add_number & 0xffff) != 0)
3412 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
3418 /* The value is larger than 32 bits. */
3420 if (HAVE_32BIT_GPRS)
3422 as_bad (_("Number (0x%lx) larger than 32 bits"),
3423 (unsigned long) ep->X_add_number);
3424 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3429 if (ep->X_op != O_big)
3432 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3433 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3434 hi32.X_add_number &= 0xffffffff;
3436 lo32.X_add_number &= 0xffffffff;
3440 assert (ep->X_add_number > 2);
3441 if (ep->X_add_number == 3)
3442 generic_bignum[3] = 0;
3443 else if (ep->X_add_number > 4)
3444 as_bad (_("Number larger than 64 bits"));
3445 lo32.X_op = O_constant;
3446 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3447 hi32.X_op = O_constant;
3448 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3451 if (hi32.X_add_number == 0)
3456 unsigned long hi, lo;
3458 if (hi32.X_add_number == (offsetT) 0xffffffff)
3460 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3462 macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
3466 if (lo32.X_add_number & 0x80000000)
3468 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3470 if (lo32.X_add_number & 0xffff)
3471 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
3477 /* Check for 16bit shifted constant. We know that hi32 is
3478 non-zero, so start the mask on the first bit of the hi32
3483 unsigned long himask, lomask;
3487 himask = 0xffff >> (32 - shift);
3488 lomask = (0xffff << shift) & 0xffffffff;
3492 himask = 0xffff << (shift - 32);
3495 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3496 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3500 tmp.X_op = O_constant;
3502 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3503 | (lo32.X_add_number >> shift));
3505 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3506 macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
3508 macro_build (NULL, counter, NULL,
3509 (shift >= 32) ? "dsll32" : "dsll",
3511 (shift >= 32) ? shift - 32 : shift);
3516 while (shift <= (64 - 16));
3518 /* Find the bit number of the lowest one bit, and store the
3519 shifted value in hi/lo. */
3520 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3521 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3525 while ((lo & 1) == 0)
3530 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3536 while ((hi & 1) == 0)
3545 /* Optimize if the shifted value is a (power of 2) - 1. */
3546 if ((hi == 0 && ((lo + 1) & lo) == 0)
3547 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3549 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3554 /* This instruction will set the register to be all
3556 tmp.X_op = O_constant;
3557 tmp.X_add_number = (offsetT) -1;
3558 macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
3563 macro_build (NULL, counter, NULL,
3564 (bit >= 32) ? "dsll32" : "dsll",
3566 (bit >= 32) ? bit - 32 : bit);
3568 macro_build (NULL, counter, NULL,
3569 (shift >= 32) ? "dsrl32" : "dsrl",
3571 (shift >= 32) ? shift - 32 : shift);
3576 /* Sign extend hi32 before calling load_register, because we can
3577 generally get better code when we load a sign extended value. */
3578 if ((hi32.X_add_number & 0x80000000) != 0)
3579 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3580 load_register (counter, reg, &hi32, 0);
3583 if ((lo32.X_add_number & 0xffff0000) == 0)
3587 macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
3595 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3597 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3599 macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
3605 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
3609 mid16.X_add_number >>= 16;
3610 macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
3612 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3615 if ((lo32.X_add_number & 0xffff) != 0)
3616 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3620 /* Load an address into a register. */
3623 load_address (int *counter, int reg, expressionS *ep, int *used_at)
3627 if (ep->X_op != O_constant
3628 && ep->X_op != O_symbol)
3630 as_bad (_("expression too complex"));
3631 ep->X_op = O_constant;
3634 if (ep->X_op == O_constant)
3636 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3640 if (mips_pic == NO_PIC)
3642 /* If this is a reference to a GP relative symbol, we want
3643 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3645 lui $reg,<sym> (BFD_RELOC_HI16_S)
3646 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3647 If we have an addend, we always use the latter form.
3649 With 64bit address space and a usable $at we want
3650 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3651 lui $at,<sym> (BFD_RELOC_HI16_S)
3652 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3653 daddiu $at,<sym> (BFD_RELOC_LO16)
3657 If $at is already in use, we use a path which is suboptimal
3658 on superscalar processors.
3659 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3660 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3662 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3664 daddiu $reg,<sym> (BFD_RELOC_LO16)
3666 if (HAVE_64BIT_ADDRESSES)
3668 /* We don't do GP optimization for now because RELAX_ENCODE can't
3669 hold the data for such large chunks. */
3671 if (*used_at == 0 && ! mips_opts.noat)
3673 macro_build (p, counter, ep, "lui", "t,u",
3674 reg, BFD_RELOC_MIPS_HIGHEST);
3675 macro_build (p, counter, ep, "lui", "t,u",
3676 AT, BFD_RELOC_HI16_S);
3677 macro_build (p, counter, ep, "daddiu", "t,r,j",
3678 reg, reg, BFD_RELOC_MIPS_HIGHER);
3679 macro_build (p, counter, ep, "daddiu", "t,r,j",
3680 AT, AT, BFD_RELOC_LO16);
3681 macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
3682 macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
3687 macro_build (p, counter, ep, "lui", "t,u",
3688 reg, BFD_RELOC_MIPS_HIGHEST);
3689 macro_build (p, counter, ep, "daddiu", "t,r,j",
3690 reg, reg, BFD_RELOC_MIPS_HIGHER);
3691 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3692 macro_build (p, counter, ep, "daddiu", "t,r,j",
3693 reg, reg, BFD_RELOC_HI16_S);
3694 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3695 macro_build (p, counter, ep, "daddiu", "t,r,j",
3696 reg, reg, BFD_RELOC_LO16);
3701 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3702 && ! nopic_need_relax (ep->X_add_symbol, 1))
3705 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3706 mips_gp_register, BFD_RELOC_GPREL16);
3707 p = frag_var (rs_machine_dependent, 8, 0,
3708 RELAX_ENCODE (4, 8, 0, 4, 0,
3709 mips_opts.warn_about_macros),
3710 ep->X_add_symbol, 0, NULL);
3712 macro_build_lui (p, counter, ep, reg);
3715 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3719 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3723 /* If this is a reference to an external symbol, we want
3724 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3726 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3728 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3729 If there is a constant, it must be added in after.
3731 If we have NewABI, we want
3732 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3733 unless we're referencing a global symbol with a non-zero
3734 offset, in which case cst must be added separately. */
3739 if (ep->X_add_number)
3741 frag_now->tc_frag_data.tc_fr_offset =
3742 ex.X_add_number = ep->X_add_number;
3743 ep->X_add_number = 0;
3744 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
3745 reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3746 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3747 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3748 ex.X_op = O_constant;
3749 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3750 reg, reg, BFD_RELOC_LO16);
3751 p = frag_var (rs_machine_dependent, 8, 0,
3752 RELAX_ENCODE (8, 4, 0, 0, 0,
3753 mips_opts.warn_about_macros),
3754 ep->X_add_symbol, 0, NULL);
3755 ep->X_add_number = ex.X_add_number;
3758 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3759 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3763 /* To avoid confusion in tc_gen_reloc, we must ensure
3764 that this does not become a variant frag. */
3765 frag_wane (frag_now);
3771 ex.X_add_number = ep->X_add_number;
3772 ep->X_add_number = 0;
3774 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3775 BFD_RELOC_MIPS_GOT16,
3777 macro_build (NULL, counter, NULL, "nop", "");
3778 p = frag_var (rs_machine_dependent, 4, 0,
3779 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3780 ep->X_add_symbol, 0, NULL);
3781 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3784 if (ex.X_add_number != 0)
3786 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3787 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3788 ex.X_op = O_constant;
3789 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3790 reg, reg, BFD_RELOC_LO16);
3794 else if (mips_pic == SVR4_PIC)
3799 /* This is the large GOT case. If this is a reference to an
3800 external symbol, we want
3801 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3803 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3805 Otherwise, for a reference to a local symbol in old ABI, we want
3806 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3808 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3809 If there is a constant, it must be added in after.
3811 In the NewABI, for local symbols, with or without offsets, we want:
3812 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3813 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3819 frag_now->tc_frag_data.tc_fr_offset =
3820 ex.X_add_number = ep->X_add_number;
3821 ep->X_add_number = 0;
3822 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3823 BFD_RELOC_MIPS_GOT_HI16);
3824 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3825 reg, mips_gp_register);
3826 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3827 BFD_RELOC_MIPS_GOT_LO16, reg);
3828 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3829 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3830 else if (ex.X_add_number)
3832 ex.X_op = O_constant;
3833 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3834 reg, reg, BFD_RELOC_LO16);
3837 ep->X_add_number = ex.X_add_number;
3838 p = frag_var (rs_machine_dependent, 8, 0,
3839 RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0,
3840 mips_opts.warn_about_macros),
3841 ep->X_add_symbol, 0, NULL);
3842 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3843 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3844 macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3845 reg, BFD_RELOC_MIPS_GOT_OFST);
3849 ex.X_add_number = ep->X_add_number;
3850 ep->X_add_number = 0;
3851 if (reg_needs_delay (mips_gp_register))
3856 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3857 BFD_RELOC_MIPS_GOT_HI16);
3858 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3859 reg, mips_gp_register);
3860 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3861 BFD_RELOC_MIPS_GOT_LO16, reg);
3862 p = frag_var (rs_machine_dependent, 12 + off, 0,
3863 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3864 mips_opts.warn_about_macros),
3865 ep->X_add_symbol, 0, NULL);
3868 /* We need a nop before loading from $gp. This special
3869 check is required because the lui which starts the main
3870 instruction stream does not refer to $gp, and so will not
3871 insert the nop which may be required. */
3872 macro_build (p, counter, NULL, "nop", "");
3875 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3876 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3878 macro_build (p, counter, NULL, "nop", "");
3880 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3883 if (ex.X_add_number != 0)
3885 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3886 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3887 ex.X_op = O_constant;
3888 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3889 reg, reg, BFD_RELOC_LO16);
3893 else if (mips_pic == EMBEDDED_PIC)
3896 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3898 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3899 mips_gp_register, BFD_RELOC_GPREL16);
3905 /* Move the contents of register SOURCE into register DEST. */
3908 move_register (int *counter, int dest, int source)
3910 macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
3911 "d,v,t", dest, source, 0);
3916 * This routine implements the seemingly endless macro or synthesized
3917 * instructions and addressing modes in the mips assembly language. Many
3918 * of these macros are simple and are similar to each other. These could
3919 * probably be handled by some kind of table or grammer aproach instead of
3920 * this verbose method. Others are not simple macros but are more like
3921 * optimizing code generation.
3922 * One interesting optimization is when several store macros appear
3923 * consecutivly that would load AT with the upper half of the same address.
3924 * The ensuing load upper instructions are ommited. This implies some kind
3925 * of global optimization. We currently only optimize within a single macro.
3926 * For many of the load and store macros if the address is specified as a
3927 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3928 * first load register 'at' with zero and use it as the base register. The
3929 * mips assembler simply uses register $zero. Just one tiny optimization
3933 macro (struct mips_cl_insn *ip)
3935 register int treg, sreg, dreg, breg;
3951 bfd_reloc_code_real_type r;
3952 int hold_mips_optimize;
3954 assert (! mips_opts.mips16);
3956 treg = (ip->insn_opcode >> 16) & 0x1f;
3957 dreg = (ip->insn_opcode >> 11) & 0x1f;
3958 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3959 mask = ip->insn_mo->mask;
3961 expr1.X_op = O_constant;
3962 expr1.X_op_symbol = NULL;
3963 expr1.X_add_symbol = NULL;
3964 expr1.X_add_number = 1;
3966 /* Umatched fixups should not be put in the same frag as a relaxable
3967 macro. For example, suppose we have:
3971 addiu $4,$4,%lo(l1) # 3
3973 If instructions 1 and 2 were put in the same frag, md_frob_file would
3974 move the fixup for #1 after the fixups for the "unrelaxed" version of
3975 #2. This would confuse tc_gen_reloc, which expects the relocations
3976 for #2 to be the last for that frag.
3978 Also, if tc_gen_reloc sees certain relocations in a variant frag,
3979 it assumes that they belong to a relaxable macro. We mustn't put
3980 other uses of such relocations into a variant frag.
3982 To avoid both problems, finish the current frag it contains a
3983 %reloc() operator. The macro then goes into a new frag. */
3984 if (prev_reloc_op_frag == frag_now)
3986 frag_wane (frag_now);
4000 mips_emit_delays (TRUE);
4001 ++mips_opts.noreorder;
4002 mips_any_noreorder = 1;
4004 expr1.X_add_number = 8;
4005 macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4007 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4009 move_register (&icnt, dreg, sreg);
4010 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
4013 --mips_opts.noreorder;
4034 if (imm_expr.X_op == O_constant
4035 && imm_expr.X_add_number >= -0x8000
4036 && imm_expr.X_add_number < 0x8000)
4038 macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4042 load_register (&icnt, AT, &imm_expr, dbl);
4043 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4062 if (imm_expr.X_op == O_constant
4063 && imm_expr.X_add_number >= 0
4064 && imm_expr.X_add_number < 0x10000)
4066 if (mask != M_NOR_I)
4067 macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
4071 macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
4073 macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
4078 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4079 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4096 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4098 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
4101 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4102 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4110 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4116 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4120 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4121 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4128 /* check for > max integer */
4129 maxnum = 0x7fffffff;
4130 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4137 if (imm_expr.X_op == O_constant
4138 && imm_expr.X_add_number >= maxnum
4139 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4142 /* result is always false */
4146 as_warn (_("Branch %s is always false (nop)"),
4148 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4153 as_warn (_("Branch likely %s is always false"),
4155 macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
4159 if (imm_expr.X_op != O_constant)
4160 as_bad (_("Unsupported large constant"));
4161 ++imm_expr.X_add_number;
4165 if (mask == M_BGEL_I)
4167 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4169 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4173 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4175 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4179 maxnum = 0x7fffffff;
4180 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4187 maxnum = - maxnum - 1;
4188 if (imm_expr.X_op == O_constant
4189 && imm_expr.X_add_number <= maxnum
4190 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4193 /* result is always true */
4194 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4195 macro_build (NULL, &icnt, &offset_expr, "b", "p");
4198 set_at (&icnt, sreg, 0);
4199 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4210 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4214 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4215 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4224 && imm_expr.X_op == O_constant
4225 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4227 if (imm_expr.X_op != O_constant)
4228 as_bad (_("Unsupported large constant"));
4229 ++imm_expr.X_add_number;
4233 if (mask == M_BGEUL_I)
4235 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4237 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4239 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4243 set_at (&icnt, sreg, 1);
4244 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4253 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4259 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4263 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4264 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4273 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4279 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4280 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4289 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4295 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4299 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4300 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4307 maxnum = 0x7fffffff;
4308 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4315 if (imm_expr.X_op == O_constant
4316 && imm_expr.X_add_number >= maxnum
4317 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4319 if (imm_expr.X_op != O_constant)
4320 as_bad (_("Unsupported large constant"));
4321 ++imm_expr.X_add_number;
4325 if (mask == M_BLTL_I)
4327 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4329 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4333 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4335 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4339 set_at (&icnt, sreg, 0);
4340 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4349 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4355 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4356 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4365 && imm_expr.X_op == O_constant
4366 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4368 if (imm_expr.X_op != O_constant)
4369 as_bad (_("Unsupported large constant"));
4370 ++imm_expr.X_add_number;
4374 if (mask == M_BLTUL_I)
4376 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4378 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4380 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4384 set_at (&icnt, sreg, 1);
4385 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4394 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4400 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4404 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4405 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4416 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4420 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4421 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4437 as_warn (_("Divide by zero."));
4439 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4441 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4445 mips_emit_delays (TRUE);
4446 ++mips_opts.noreorder;
4447 mips_any_noreorder = 1;
4450 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4451 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4456 expr1.X_add_number = 8;
4457 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4458 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4460 macro_build (NULL, &icnt,NULL, "break", "c", 7);
4462 expr1.X_add_number = -1;
4463 macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
4464 AT, 0, BFD_RELOC_LO16);
4465 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4466 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4469 expr1.X_add_number = 1;
4470 macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4472 macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
4476 expr1.X_add_number = 0x80000000;
4477 macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
4482 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
4483 /* We want to close the noreorder block as soon as possible, so
4484 that later insns are available for delay slot filling. */
4485 --mips_opts.noreorder;
4489 expr1.X_add_number = 8;
4490 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4491 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4493 /* We want to close the noreorder block as soon as possible, so
4494 that later insns are available for delay slot filling. */
4495 --mips_opts.noreorder;
4497 macro_build (NULL, &icnt, NULL, "break", "c", 6);
4499 macro_build (NULL, &icnt, NULL, s, "d", dreg);
4538 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4540 as_warn (_("Divide by zero."));
4542 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4544 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4547 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4549 if (strcmp (s2, "mflo") == 0)
4550 move_register (&icnt, dreg, sreg);
4552 move_register (&icnt, dreg, 0);
4555 if (imm_expr.X_op == O_constant
4556 && imm_expr.X_add_number == -1
4557 && s[strlen (s) - 1] != 'u')
4559 if (strcmp (s2, "mflo") == 0)
4561 macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
4565 move_register (&icnt, dreg, 0);
4569 load_register (&icnt, AT, &imm_expr, dbl);
4570 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
4571 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4590 mips_emit_delays (TRUE);
4591 ++mips_opts.noreorder;
4592 mips_any_noreorder = 1;
4595 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4596 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4597 /* We want to close the noreorder block as soon as possible, so
4598 that later insns are available for delay slot filling. */
4599 --mips_opts.noreorder;
4603 expr1.X_add_number = 8;
4604 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4605 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4607 /* We want to close the noreorder block as soon as possible, so
4608 that later insns are available for delay slot filling. */
4609 --mips_opts.noreorder;
4610 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4612 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4618 /* Load the address of a symbol into a register. If breg is not
4619 zero, we then add a base register to it. */
4621 if (dbl && HAVE_32BIT_GPRS)
4622 as_warn (_("dla used to load 32-bit register"));
4624 if (! dbl && HAVE_64BIT_OBJECTS)
4625 as_warn (_("la used to load 64-bit address"));
4627 if (offset_expr.X_op == O_constant
4628 && offset_expr.X_add_number >= -0x8000
4629 && offset_expr.X_add_number < 0x8000)
4631 macro_build (NULL, &icnt, &offset_expr,
4632 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4633 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4648 /* When generating embedded PIC code, we permit expressions of
4651 la $treg,foo-bar($breg)
4652 where bar is an address in the current section. These are used
4653 when getting the addresses of functions. We don't permit
4654 X_add_number to be non-zero, because if the symbol is
4655 external the relaxing code needs to know that any addend is
4656 purely the offset to X_op_symbol. */
4657 if (mips_pic == EMBEDDED_PIC
4658 && offset_expr.X_op == O_subtract
4659 && (symbol_constant_p (offset_expr.X_op_symbol)
4660 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4661 : (symbol_equated_p (offset_expr.X_op_symbol)
4663 (symbol_get_value_expression (offset_expr.X_op_symbol)
4666 && (offset_expr.X_add_number == 0
4667 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4673 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4674 BFD_RELOC_PCREL_HI16_S);
4678 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4679 BFD_RELOC_PCREL_HI16_S);
4680 macro_build (NULL, &icnt, NULL,
4681 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4682 "d,v,t", tempreg, tempreg, breg);
4684 macro_build (NULL, &icnt, &offset_expr,
4685 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4686 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4692 if (offset_expr.X_op != O_symbol
4693 && offset_expr.X_op != O_constant)
4695 as_bad (_("expression too complex"));
4696 offset_expr.X_op = O_constant;
4699 if (offset_expr.X_op == O_constant)
4700 load_register (&icnt, tempreg, &offset_expr,
4701 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4702 ? (dbl || HAVE_64BIT_ADDRESSES)
4703 : HAVE_64BIT_ADDRESSES));
4704 else if (mips_pic == NO_PIC)
4706 /* If this is a reference to a GP relative symbol, we want
4707 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4709 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4710 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4711 If we have a constant, we need two instructions anyhow,
4712 so we may as well always use the latter form.
4714 With 64bit address space and a usable $at we want
4715 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4716 lui $at,<sym> (BFD_RELOC_HI16_S)
4717 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4718 daddiu $at,<sym> (BFD_RELOC_LO16)
4720 daddu $tempreg,$tempreg,$at
4722 If $at is already in use, we use a path which is suboptimal
4723 on superscalar processors.
4724 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4725 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4727 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4729 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4732 if (HAVE_64BIT_ADDRESSES)
4734 /* We don't do GP optimization for now because RELAX_ENCODE can't
4735 hold the data for such large chunks. */
4737 if (used_at == 0 && ! mips_opts.noat)
4739 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4740 tempreg, BFD_RELOC_MIPS_HIGHEST);
4741 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4742 AT, BFD_RELOC_HI16_S);
4743 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4744 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4745 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4746 AT, AT, BFD_RELOC_LO16);
4747 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
4748 tempreg, tempreg, 0);
4749 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
4750 tempreg, tempreg, AT);
4755 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4756 tempreg, BFD_RELOC_MIPS_HIGHEST);
4757 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4758 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4759 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4760 tempreg, tempreg, 16);
4761 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4762 tempreg, tempreg, BFD_RELOC_HI16_S);
4763 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4764 tempreg, tempreg, 16);
4765 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4766 tempreg, tempreg, BFD_RELOC_LO16);
4771 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4772 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4775 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4776 "t,r,j", tempreg, mips_gp_register,
4778 p = frag_var (rs_machine_dependent, 8, 0,
4779 RELAX_ENCODE (4, 8, 0, 4, 0,
4780 mips_opts.warn_about_macros),
4781 offset_expr.X_add_symbol, 0, NULL);
4783 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4786 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4787 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4790 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4792 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4794 /* If this is a reference to an external symbol, and there
4795 is no constant, we want
4796 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4797 or if tempreg is PIC_CALL_REG
4798 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4799 For a local symbol, we want
4800 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4802 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4804 If we have a small constant, and this is a reference to
4805 an external symbol, we want
4806 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4808 addiu $tempreg,$tempreg,<constant>
4809 For a local symbol, we want the same instruction
4810 sequence, but we output a BFD_RELOC_LO16 reloc on the
4813 If we have a large constant, and this is a reference to
4814 an external symbol, we want
4815 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4816 lui $at,<hiconstant>
4817 addiu $at,$at,<loconstant>
4818 addu $tempreg,$tempreg,$at
4819 For a local symbol, we want the same instruction
4820 sequence, but we output a BFD_RELOC_LO16 reloc on the
4824 expr1.X_add_number = offset_expr.X_add_number;
4825 offset_expr.X_add_number = 0;
4827 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4828 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4829 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
4830 tempreg, lw_reloc_type, mips_gp_register);
4831 if (expr1.X_add_number == 0)
4840 /* We're going to put in an addu instruction using
4841 tempreg, so we may as well insert the nop right
4843 macro_build (NULL, &icnt, NULL, "nop", "");
4846 p = frag_var (rs_machine_dependent, 8 - off, 0,
4847 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4849 ? mips_opts.warn_about_macros
4851 offset_expr.X_add_symbol, 0, NULL);
4854 macro_build (p, &icnt, NULL, "nop", "");
4857 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
4858 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4859 /* FIXME: If breg == 0, and the next instruction uses
4860 $tempreg, then if this variant case is used an extra
4861 nop will be generated. */
4863 else if (expr1.X_add_number >= -0x8000
4864 && expr1.X_add_number < 0x8000)
4866 macro_build (NULL, &icnt, NULL, "nop", "");
4867 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
4868 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4869 frag_var (rs_machine_dependent, 0, 0,
4870 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4871 offset_expr.X_add_symbol, 0, NULL);
4877 /* If we are going to add in a base register, and the
4878 target register and the base register are the same,
4879 then we are using AT as a temporary register. Since
4880 we want to load the constant into AT, we add our
4881 current AT (from the global offset table) and the
4882 register into the register now, and pretend we were
4883 not using a base register. */
4888 macro_build (NULL, &icnt, NULL, "nop", "");
4889 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
4896 /* Set mips_optimize around the lui instruction to avoid
4897 inserting an unnecessary nop after the lw. */
4898 hold_mips_optimize = mips_optimize;
4900 macro_build_lui (NULL, &icnt, &expr1, AT);
4901 mips_optimize = hold_mips_optimize;
4903 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
4904 AT, AT, BFD_RELOC_LO16);
4905 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
4906 tempreg, tempreg, AT);
4907 frag_var (rs_machine_dependent, 0, 0,
4908 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4909 offset_expr.X_add_symbol, 0, NULL);
4913 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
4916 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
4919 /* If this is a reference to an external, and there is no
4920 constant, or local symbol (*), with or without a
4922 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4923 or if tempreg is PIC_CALL_REG
4924 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4926 If we have a small constant, and this is a reference to
4927 an external symbol, we want
4928 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4929 addiu $tempreg,$tempreg,<constant>
4931 If we have a large constant, and this is a reference to
4932 an external symbol, we want
4933 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4934 lui $at,<hiconstant>
4935 addiu $at,$at,<loconstant>
4936 addu $tempreg,$tempreg,$at
4938 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
4939 local symbols, even though it introduces an additional
4943 if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG)
4944 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4945 if (offset_expr.X_add_number)
4947 frag_now->tc_frag_data.tc_fr_offset =
4948 expr1.X_add_number = offset_expr.X_add_number;
4949 offset_expr.X_add_number = 0;
4951 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
4952 "t,o(b)", tempreg, lw_reloc_type,
4955 if (expr1.X_add_number >= -0x8000
4956 && expr1.X_add_number < 0x8000)
4958 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
4959 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4960 p = frag_var (rs_machine_dependent, 4, 0,
4961 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
4962 offset_expr.X_add_symbol, 0, NULL);
4964 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number))
4968 /* If we are going to add in a base register, and the
4969 target register and the base register are the same,
4970 then we are using AT as a temporary register. Since
4971 we want to load the constant into AT, we add our
4972 current AT (from the global offset table) and the
4973 register into the register now, and pretend we were
4974 not using a base register. */
4979 assert (tempreg == AT);
4980 macro_build (NULL, &icnt,NULL, ADDRESS_ADD_INSN,
4981 "d,v,t", treg, AT, breg);
4986 macro_build_lui (NULL, &icnt, &expr1, AT);
4987 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
4988 "t,r,j", AT, AT, BFD_RELOC_LO16);
4989 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
4992 p = frag_var (rs_machine_dependent, 4 + adj, 0,
4993 RELAX_ENCODE (16 + adj, 4 + adj,
4995 offset_expr.X_add_symbol, 0, NULL);
5000 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5002 offset_expr.X_add_number = expr1.X_add_number;
5004 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5005 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5009 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5010 treg, tempreg, breg);
5017 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5018 "t,o(b)", tempreg, lw_reloc_type,
5020 if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP)
5021 p = frag_var (rs_machine_dependent, 0, 0,
5022 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5023 offset_expr.X_add_symbol, 0, NULL);
5028 /* To avoid confusion in tc_gen_reloc, we must ensure
5029 that this does not become a variant frag. */
5030 frag_wane (frag_now);
5034 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5038 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5039 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5040 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5042 /* This is the large GOT case. If this is a reference to an
5043 external symbol, and there is no constant, we want
5044 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5045 addu $tempreg,$tempreg,$gp
5046 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5047 or if tempreg is PIC_CALL_REG
5048 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5049 addu $tempreg,$tempreg,$gp
5050 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5051 For a local symbol, we want
5052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5054 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5056 If we have a small constant, and this is a reference to
5057 an external symbol, we want
5058 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5059 addu $tempreg,$tempreg,$gp
5060 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5062 addiu $tempreg,$tempreg,<constant>
5063 For a local symbol, we want
5064 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5066 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5068 If we have a large constant, and this is a reference to
5069 an external symbol, we want
5070 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5071 addu $tempreg,$tempreg,$gp
5072 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5073 lui $at,<hiconstant>
5074 addiu $at,$at,<loconstant>
5075 addu $tempreg,$tempreg,$at
5076 For a local symbol, we want
5077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5078 lui $at,<hiconstant>
5079 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5080 addu $tempreg,$tempreg,$at
5083 expr1.X_add_number = offset_expr.X_add_number;
5084 offset_expr.X_add_number = 0;
5086 if (reg_needs_delay (mips_gp_register))
5090 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5092 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5093 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5095 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5096 tempreg, lui_reloc_type);
5097 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5098 tempreg, tempreg, mips_gp_register);
5099 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5100 tempreg, lw_reloc_type, tempreg);
5101 if (expr1.X_add_number == 0)
5109 /* We're going to put in an addu instruction using
5110 tempreg, so we may as well insert the nop right
5112 macro_build (NULL, &icnt, NULL, "nop", "");
5116 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5117 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5120 ? mips_opts.warn_about_macros
5122 offset_expr.X_add_symbol, 0, NULL);
5124 else if (expr1.X_add_number >= -0x8000
5125 && expr1.X_add_number < 0x8000)
5127 macro_build (NULL, &icnt, NULL, "nop", "");
5128 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5129 tempreg, tempreg, BFD_RELOC_LO16);
5131 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5132 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5134 ? mips_opts.warn_about_macros
5136 offset_expr.X_add_symbol, 0, NULL);
5142 /* If we are going to add in a base register, and the
5143 target register and the base register are the same,
5144 then we are using AT as a temporary register. Since
5145 we want to load the constant into AT, we add our
5146 current AT (from the global offset table) and the
5147 register into the register now, and pretend we were
5148 not using a base register. */
5156 assert (tempreg == AT);
5157 macro_build (NULL, &icnt, NULL, "nop", "");
5158 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5164 /* Set mips_optimize around the lui instruction to avoid
5165 inserting an unnecessary nop after the lw. */
5166 hold_mips_optimize = mips_optimize;
5168 macro_build_lui (NULL, &icnt, &expr1, AT);
5169 mips_optimize = hold_mips_optimize;
5171 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5172 AT, AT, BFD_RELOC_LO16);
5173 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5176 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5177 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5180 ? mips_opts.warn_about_macros
5182 offset_expr.X_add_symbol, 0, NULL);
5189 /* This is needed because this instruction uses $gp, but
5190 the first instruction on the main stream does not. */
5191 macro_build (p, &icnt, NULL, "nop", "");
5195 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5196 tempreg, local_reloc_type, mips_gp_register);
5198 if (expr1.X_add_number >= -0x8000
5199 && expr1.X_add_number < 0x8000)
5201 macro_build (p, &icnt, NULL, "nop", "");
5203 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5204 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5205 /* FIXME: If add_number is 0, and there was no base
5206 register, the external symbol case ended with a load,
5207 so if the symbol turns out to not be external, and
5208 the next instruction uses tempreg, an unnecessary nop
5209 will be inserted. */
5215 /* We must add in the base register now, as in the
5216 external symbol case. */
5217 assert (tempreg == AT);
5218 macro_build (p, &icnt, NULL, "nop", "");
5220 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5224 /* We set breg to 0 because we have arranged to add
5225 it in in both cases. */
5229 macro_build_lui (p, &icnt, &expr1, AT);
5231 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5232 AT, AT, BFD_RELOC_LO16);
5234 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5235 tempreg, tempreg, AT);
5239 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5242 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5243 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5246 /* This is the large GOT case. If this is a reference to an
5247 external symbol, and there is no constant, we want
5248 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5249 add $tempreg,$tempreg,$gp
5250 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5251 or if tempreg is PIC_CALL_REG
5252 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5253 add $tempreg,$tempreg,$gp
5254 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5256 If we have a small constant, and this is a reference to
5257 an external symbol, we want
5258 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5259 add $tempreg,$tempreg,$gp
5260 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5261 addi $tempreg,$tempreg,<constant>
5263 If we have a large constant, and this is a reference to
5264 an external symbol, we want
5265 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5266 addu $tempreg,$tempreg,$gp
5267 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5268 lui $at,<hiconstant>
5269 addi $at,$at,<loconstant>
5270 add $tempreg,$tempreg,$at
5272 If we have NewABI, and we know it's a local symbol, we want
5273 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5274 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5275 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5279 frag_now->tc_frag_data.tc_fr_offset =
5280 expr1.X_add_number = offset_expr.X_add_number;
5281 offset_expr.X_add_number = 0;
5283 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5285 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5286 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5288 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5289 tempreg, lui_reloc_type);
5290 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5291 tempreg, tempreg, mips_gp_register);
5292 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5293 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5295 if (expr1.X_add_number == 0)
5297 p = frag_var (rs_machine_dependent, 8, 0,
5298 RELAX_ENCODE (12, 8, 0, 4, 0,
5299 mips_opts.warn_about_macros),
5300 offset_expr.X_add_symbol, 0, NULL);
5302 else if (expr1.X_add_number >= -0x8000
5303 && expr1.X_add_number < 0x8000)
5305 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5306 tempreg, tempreg, BFD_RELOC_LO16);
5307 p = frag_var (rs_machine_dependent, 8, 0,
5308 RELAX_ENCODE (16, 8, 0, 4, 0,
5309 mips_opts.warn_about_macros),
5310 offset_expr.X_add_symbol, 0, NULL);
5312 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number))
5316 /* If we are going to add in a base register, and the
5317 target register and the base register are the same,
5318 then we are using AT as a temporary register. Since
5319 we want to load the constant into AT, we add our
5320 current AT (from the global offset table) and the
5321 register into the register now, and pretend we were
5322 not using a base register. */
5327 assert (tempreg == AT);
5328 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5334 /* Set mips_optimize around the lui instruction to avoid
5335 inserting an unnecessary nop after the lw. */
5336 macro_build_lui (NULL, &icnt, &expr1, AT);
5337 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5338 "t,r,j", AT, AT, BFD_RELOC_LO16);
5339 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5342 p = frag_var (rs_machine_dependent, 8 + adj, 0,
5343 RELAX_ENCODE (24 + adj, 8 + adj,
5346 ? mips_opts.warn_about_macros
5348 offset_expr.X_add_symbol, 0, NULL);
5353 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5355 offset_expr.X_add_number = expr1.X_add_number;
5356 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5357 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5358 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5359 tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
5362 macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5363 treg, tempreg, breg);
5368 else if (mips_pic == EMBEDDED_PIC)
5371 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5373 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5374 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5383 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5384 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5386 s = ADDRESS_ADD_INSN;
5388 macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
5397 /* The j instruction may not be used in PIC code, since it
5398 requires an absolute address. We convert it to a b
5400 if (mips_pic == NO_PIC)
5401 macro_build (NULL, &icnt, &offset_expr, "j", "a");
5403 macro_build (NULL, &icnt, &offset_expr, "b", "p");
5406 /* The jal instructions must be handled as macros because when
5407 generating PIC code they expand to multi-instruction
5408 sequences. Normally they are simple instructions. */
5413 if (mips_pic == NO_PIC
5414 || mips_pic == EMBEDDED_PIC)
5415 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5416 else if (mips_pic == SVR4_PIC)
5418 if (sreg != PIC_CALL_REG)
5419 as_warn (_("MIPS PIC call to register other than $25"));
5421 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5424 if (mips_cprestore_offset < 0)
5425 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5428 if (! mips_frame_reg_valid)
5430 as_warn (_("No .frame pseudo-op used in PIC code"));
5431 /* Quiet this warning. */
5432 mips_frame_reg_valid = 1;
5434 if (! mips_cprestore_valid)
5436 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5437 /* Quiet this warning. */
5438 mips_cprestore_valid = 1;
5440 expr1.X_add_number = mips_cprestore_offset;
5441 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5454 if (mips_pic == NO_PIC)
5455 macro_build (NULL, &icnt, &offset_expr, "jal", "a");
5456 else if (mips_pic == SVR4_PIC)
5460 /* If this is a reference to an external symbol, and we are
5461 using a small GOT, we want
5462 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5466 lw $gp,cprestore($sp)
5467 The cprestore value is set using the .cprestore
5468 pseudo-op. If we are using a big GOT, we want
5469 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5471 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5475 lw $gp,cprestore($sp)
5476 If the symbol is not external, we want
5477 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5479 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5482 lw $gp,cprestore($sp)
5484 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5485 sequences above, minus nops, unless the symbol is local,
5486 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5493 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5494 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5496 frag_var (rs_machine_dependent, 0, 0,
5497 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5498 offset_expr.X_add_symbol, 0, NULL);
5503 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5504 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5505 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5506 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5507 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5508 "t,o(b)", PIC_CALL_REG,
5509 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5510 p = frag_var (rs_machine_dependent, 8, 0,
5511 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5512 offset_expr.X_add_symbol, 0, NULL);
5513 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5514 "t,o(b)", PIC_CALL_REG,
5515 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5516 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5517 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5518 BFD_RELOC_MIPS_GOT_OFST);
5521 macro_build_jalr (icnt, &offset_expr);
5528 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5529 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5531 macro_build (NULL, &icnt, NULL, "nop", "");
5532 p = frag_var (rs_machine_dependent, 4, 0,
5533 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5534 offset_expr.X_add_symbol, 0, NULL);
5540 if (reg_needs_delay (mips_gp_register))
5544 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5545 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5546 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5547 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5548 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5549 "t,o(b)", PIC_CALL_REG,
5550 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5551 macro_build (NULL, &icnt, NULL, "nop", "");
5552 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5553 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5555 offset_expr.X_add_symbol, 0, NULL);
5558 macro_build (p, &icnt, NULL, "nop", "");
5561 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5562 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5565 macro_build (p, &icnt, NULL, "nop", "");
5568 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5569 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5571 macro_build_jalr (icnt, &offset_expr);
5573 if (mips_cprestore_offset < 0)
5574 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5577 if (! mips_frame_reg_valid)
5579 as_warn (_("No .frame pseudo-op used in PIC code"));
5580 /* Quiet this warning. */
5581 mips_frame_reg_valid = 1;
5583 if (! mips_cprestore_valid)
5585 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5586 /* Quiet this warning. */
5587 mips_cprestore_valid = 1;
5589 if (mips_opts.noreorder)
5590 macro_build (NULL, &icnt, NULL, "nop", "");
5591 expr1.X_add_number = mips_cprestore_offset;
5592 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5599 else if (mips_pic == EMBEDDED_PIC)
5601 macro_build (NULL, &icnt, &offset_expr, "bal", "p");
5602 /* The linker may expand the call to a longer sequence which
5603 uses $at, so we must break rather than return. */
5628 /* Itbl support may require additional care here. */
5633 /* Itbl support may require additional care here. */
5638 /* Itbl support may require additional care here. */
5643 /* Itbl support may require additional care here. */
5655 if (mips_opts.arch == CPU_R4650)
5657 as_bad (_("opcode not supported on this processor"));
5661 /* Itbl support may require additional care here. */
5666 /* Itbl support may require additional care here. */
5671 /* Itbl support may require additional care here. */
5691 if (breg == treg || coproc || lr)
5713 /* Itbl support may require additional care here. */
5718 /* Itbl support may require additional care here. */
5723 /* Itbl support may require additional care here. */
5728 /* Itbl support may require additional care here. */
5744 if (mips_opts.arch == CPU_R4650)
5746 as_bad (_("opcode not supported on this processor"));
5751 /* Itbl support may require additional care here. */
5755 /* Itbl support may require additional care here. */
5760 /* Itbl support may require additional care here. */
5772 /* Itbl support may require additional care here. */
5773 if (mask == M_LWC1_AB
5774 || mask == M_SWC1_AB
5775 || mask == M_LDC1_AB
5776 || mask == M_SDC1_AB
5785 /* For embedded PIC, we allow loads where the offset is calculated
5786 by subtracting a symbol in the current segment from an unknown
5787 symbol, relative to a base register, e.g.:
5788 <op> $treg, <sym>-<localsym>($breg)
5789 This is used by the compiler for switch statements. */
5790 if (mips_pic == EMBEDDED_PIC
5791 && offset_expr.X_op == O_subtract
5792 && (symbol_constant_p (offset_expr.X_op_symbol)
5793 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5794 : (symbol_equated_p (offset_expr.X_op_symbol)
5796 (symbol_get_value_expression (offset_expr.X_op_symbol)
5800 && (offset_expr.X_add_number == 0
5801 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5803 /* For this case, we output the instructions:
5804 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5805 addiu $tempreg,$tempreg,$breg
5806 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5807 If the relocation would fit entirely in 16 bits, it would be
5809 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5810 instead, but that seems quite difficult. */
5811 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
5812 BFD_RELOC_PCREL_HI16_S);
5813 macro_build (NULL, &icnt, NULL,
5814 ((bfd_arch_bits_per_address (stdoutput) == 32
5815 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5816 ? "addu" : "daddu"),
5817 "d,v,t", tempreg, tempreg, breg);
5818 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
5819 BFD_RELOC_PCREL_LO16, tempreg);
5825 if (offset_expr.X_op != O_constant
5826 && offset_expr.X_op != O_symbol)
5828 as_bad (_("expression too complex"));
5829 offset_expr.X_op = O_constant;
5832 /* A constant expression in PIC code can be handled just as it
5833 is in non PIC code. */
5834 if (mips_pic == NO_PIC
5835 || offset_expr.X_op == O_constant)
5839 /* If this is a reference to a GP relative symbol, and there
5840 is no base register, we want
5841 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5842 Otherwise, if there is no base register, we want
5843 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5844 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5845 If we have a constant, we need two instructions anyhow,
5846 so we always use the latter form.
5848 If we have a base register, and this is a reference to a
5849 GP relative symbol, we want
5850 addu $tempreg,$breg,$gp
5851 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5853 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5854 addu $tempreg,$tempreg,$breg
5855 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5856 With a constant we always use the latter case.
5858 With 64bit address space and no base register and $at usable,
5860 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5861 lui $at,<sym> (BFD_RELOC_HI16_S)
5862 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5865 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5866 If we have a base register, we want
5867 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5868 lui $at,<sym> (BFD_RELOC_HI16_S)
5869 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5873 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5875 Without $at we can't generate the optimal path for superscalar
5876 processors here since this would require two temporary registers.
5877 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5878 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5880 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5882 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5883 If we have a base register, we want
5884 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5885 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5887 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5889 daddu $tempreg,$tempreg,$breg
5890 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5892 If we have 64-bit addresses, as an optimization, for
5893 addresses which are 32-bit constants (e.g. kseg0/kseg1
5894 addresses) we fall back to the 32-bit address generation
5895 mechanism since it is more efficient. Note that due to
5896 the signed offset used by memory operations, the 32-bit
5897 range is shifted down by 32768 here. This code should
5898 probably attempt to generate 64-bit constants more
5899 efficiently in general.
5901 As an extension for architectures with 64-bit registers,
5902 we don't truncate 64-bit addresses given as literal
5903 constants down to 32 bits, to support existing practice
5904 in the mips64 Linux (the kernel), that compiles source
5905 files with -mabi=64, assembling them as o32 or n32 (with
5906 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5907 the whole kernel is loaded into a memory region that is
5908 addressible with sign-extended 32-bit addresses, it is
5909 wasteful to compute the upper 32 bits of every
5910 non-literal address, that takes more space and time.
5911 Some day this should probably be implemented as an
5912 assembler option, such that the kernel doesn't have to
5913 use such ugly hacks, even though it will still have to
5914 end up converting the binary to ELF32 for a number of
5915 platforms whose boot loaders don't support ELF64
5917 if ((offset_expr.X_op != O_constant && HAVE_64BIT_ADDRESSES)
5918 || (offset_expr.X_op == O_constant
5919 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)
5920 && HAVE_64BIT_ADDRESS_CONSTANTS))
5924 /* We don't do GP optimization for now because RELAX_ENCODE can't
5925 hold the data for such large chunks. */
5927 if (used_at == 0 && ! mips_opts.noat)
5929 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5930 tempreg, BFD_RELOC_MIPS_HIGHEST);
5931 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5932 AT, BFD_RELOC_HI16_S);
5933 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5934 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5936 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5938 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
5939 tempreg, tempreg, 0);
5940 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5941 tempreg, tempreg, AT);
5942 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5943 BFD_RELOC_LO16, tempreg);
5948 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5949 tempreg, BFD_RELOC_MIPS_HIGHEST);
5950 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5951 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5952 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
5953 tempreg, tempreg, 16);
5954 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5955 tempreg, tempreg, BFD_RELOC_HI16_S);
5956 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
5957 tempreg, tempreg, 16);
5959 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5960 tempreg, tempreg, breg);
5961 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5962 BFD_RELOC_LO16, tempreg);
5967 else if (offset_expr.X_op == O_constant
5968 && !HAVE_64BIT_ADDRESS_CONSTANTS
5969 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5970 as_bad (_("load/store address overflow (max 32 bits)"));
5974 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5975 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5980 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
5981 BFD_RELOC_GPREL16, mips_gp_register);
5982 p = frag_var (rs_machine_dependent, 8, 0,
5983 RELAX_ENCODE (4, 8, 0, 4, 0,
5984 (mips_opts.warn_about_macros
5986 && mips_opts.noat))),
5987 offset_expr.X_add_symbol, 0, NULL);
5990 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5993 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5994 BFD_RELOC_LO16, tempreg);
5998 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5999 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6004 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6005 tempreg, breg, mips_gp_register);
6006 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6007 BFD_RELOC_GPREL16, tempreg);
6008 p = frag_var (rs_machine_dependent, 12, 0,
6009 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6010 offset_expr.X_add_symbol, 0, NULL);
6012 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6015 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6016 tempreg, tempreg, breg);
6019 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6020 BFD_RELOC_LO16, tempreg);
6023 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6026 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6028 /* If this is a reference to an external symbol, we want
6029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6031 <op> $treg,0($tempreg)
6033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6035 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6036 <op> $treg,0($tempreg)
6039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6040 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6042 If there is a base register, we add it to $tempreg before
6043 the <op>. If there is a constant, we stick it in the
6044 <op> instruction. We don't handle constants larger than
6045 16 bits, because we have no way to load the upper 16 bits
6046 (actually, we could handle them for the subset of cases
6047 in which we are not using $at). */
6048 assert (offset_expr.X_op == O_symbol);
6051 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6052 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6055 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6056 tempreg, tempreg, breg);
6057 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6058 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6065 expr1.X_add_number = offset_expr.X_add_number;
6066 offset_expr.X_add_number = 0;
6067 if (expr1.X_add_number < -0x8000
6068 || expr1.X_add_number >= 0x8000)
6069 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6071 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6072 tempreg, lw_reloc_type, mips_gp_register);
6073 macro_build (NULL, &icnt, NULL, "nop", "");
6074 p = frag_var (rs_machine_dependent, 4, 0,
6075 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6076 offset_expr.X_add_symbol, 0, NULL);
6077 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6078 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
6080 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6081 tempreg, tempreg, breg);
6082 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6085 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6090 /* If this is a reference to an external symbol, we want
6091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6092 addu $tempreg,$tempreg,$gp
6093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6094 <op> $treg,0($tempreg)
6096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6098 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6099 <op> $treg,0($tempreg)
6100 If there is a base register, we add it to $tempreg before
6101 the <op>. If there is a constant, we stick it in the
6102 <op> instruction. We don't handle constants larger than
6103 16 bits, because we have no way to load the upper 16 bits
6104 (actually, we could handle them for the subset of cases
6105 in which we are not using $at). */
6106 assert (offset_expr.X_op == O_symbol);
6107 expr1.X_add_number = offset_expr.X_add_number;
6108 offset_expr.X_add_number = 0;
6109 if (expr1.X_add_number < -0x8000
6110 || expr1.X_add_number >= 0x8000)
6111 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6112 if (reg_needs_delay (mips_gp_register))
6117 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6118 BFD_RELOC_MIPS_GOT_HI16);
6119 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6120 tempreg, tempreg, mips_gp_register);
6121 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6122 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6123 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
6124 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
6125 offset_expr.X_add_symbol, 0, NULL);
6128 macro_build (p, &icnt, NULL, "nop", "");
6131 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6132 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6134 macro_build (p, &icnt, NULL, "nop", "");
6136 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6137 tempreg, tempreg, BFD_RELOC_LO16);
6139 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6140 tempreg, tempreg, breg);
6141 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6144 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6147 int bregsz = breg != 0 ? 4 : 0;
6149 /* If this is a reference to an external symbol, we want
6150 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6151 add $tempreg,$tempreg,$gp
6152 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6153 <op> $treg,<ofst>($tempreg)
6154 Otherwise, for local symbols, we want:
6155 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6156 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6157 assert (offset_expr.X_op == O_symbol);
6158 frag_now->tc_frag_data.tc_fr_offset =
6159 expr1.X_add_number = offset_expr.X_add_number;
6160 offset_expr.X_add_number = 0;
6161 if (expr1.X_add_number < -0x8000
6162 || expr1.X_add_number >= 0x8000)
6163 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6165 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6166 BFD_RELOC_MIPS_GOT_HI16);
6167 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6168 tempreg, tempreg, mips_gp_register);
6169 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6170 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6172 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6173 tempreg, tempreg, breg);
6174 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6177 offset_expr.X_add_number = expr1.X_add_number;
6178 p = frag_var (rs_machine_dependent, 12 + bregsz, 0,
6179 RELAX_ENCODE (16 + bregsz, 8 + bregsz,
6180 0, 4 + bregsz, 0, 0),
6181 offset_expr.X_add_symbol, 0, NULL);
6182 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6183 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6185 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6186 tempreg, tempreg, breg);
6187 macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
6188 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6190 else if (mips_pic == EMBEDDED_PIC)
6192 /* If there is no base register, we want
6193 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6194 If there is a base register, we want
6195 addu $tempreg,$breg,$gp
6196 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6198 assert (offset_expr.X_op == O_symbol);
6201 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6202 BFD_RELOC_GPREL16, mips_gp_register);
6207 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6208 tempreg, breg, mips_gp_register);
6209 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6210 BFD_RELOC_GPREL16, tempreg);
6223 load_register (&icnt, treg, &imm_expr, 0);
6227 load_register (&icnt, treg, &imm_expr, 1);
6231 if (imm_expr.X_op == O_constant)
6233 load_register (&icnt, AT, &imm_expr, 0);
6234 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6239 assert (offset_expr.X_op == O_symbol
6240 && strcmp (segment_name (S_GET_SEGMENT
6241 (offset_expr.X_add_symbol)),
6243 && offset_expr.X_add_number == 0);
6244 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
6245 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6250 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6251 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6252 order 32 bits of the value and the low order 32 bits are either
6253 zero or in OFFSET_EXPR. */
6254 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6256 if (HAVE_64BIT_GPRS)
6257 load_register (&icnt, treg, &imm_expr, 1);
6262 if (target_big_endian)
6274 load_register (&icnt, hreg, &imm_expr, 0);
6277 if (offset_expr.X_op == O_absent)
6278 move_register (&icnt, lreg, 0);
6281 assert (offset_expr.X_op == O_constant);
6282 load_register (&icnt, lreg, &offset_expr, 0);
6289 /* We know that sym is in the .rdata section. First we get the
6290 upper 16 bits of the address. */
6291 if (mips_pic == NO_PIC)
6293 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6295 else if (mips_pic == SVR4_PIC)
6297 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6298 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6300 else if (mips_pic == EMBEDDED_PIC)
6302 /* For embedded PIC we pick up the entire address off $gp in
6303 a single instruction. */
6304 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6305 AT, mips_gp_register, BFD_RELOC_GPREL16);
6306 offset_expr.X_op = O_constant;
6307 offset_expr.X_add_number = 0;
6312 /* Now we load the register(s). */
6313 if (HAVE_64BIT_GPRS)
6314 macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
6315 BFD_RELOC_LO16, AT);
6318 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
6319 BFD_RELOC_LO16, AT);
6322 /* FIXME: How in the world do we deal with the possible
6324 offset_expr.X_add_number += 4;
6325 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6326 treg + 1, BFD_RELOC_LO16, AT);
6330 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6331 does not become a variant frag. */
6332 frag_wane (frag_now);
6338 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6339 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6340 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6341 the value and the low order 32 bits are either zero or in
6343 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6345 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6346 if (HAVE_64BIT_FPRS)
6348 assert (HAVE_64BIT_GPRS);
6349 macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
6353 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
6354 if (offset_expr.X_op == O_absent)
6355 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
6358 assert (offset_expr.X_op == O_constant);
6359 load_register (&icnt, AT, &offset_expr, 0);
6360 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6366 assert (offset_expr.X_op == O_symbol
6367 && offset_expr.X_add_number == 0);
6368 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6369 if (strcmp (s, ".lit8") == 0)
6371 if (mips_opts.isa != ISA_MIPS1)
6373 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6374 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6377 breg = mips_gp_register;
6378 r = BFD_RELOC_MIPS_LITERAL;
6383 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6384 if (mips_pic == SVR4_PIC)
6385 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6386 "t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
6390 /* FIXME: This won't work for a 64 bit address. */
6391 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6394 if (mips_opts.isa != ISA_MIPS1)
6396 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6397 BFD_RELOC_LO16, AT);
6399 /* To avoid confusion in tc_gen_reloc, we must ensure
6400 that this does not become a variant frag. */
6401 frag_wane (frag_now);
6412 if (mips_opts.arch == CPU_R4650)
6414 as_bad (_("opcode not supported on this processor"));
6417 /* Even on a big endian machine $fn comes before $fn+1. We have
6418 to adjust when loading from memory. */
6421 assert (mips_opts.isa == ISA_MIPS1);
6422 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6423 target_big_endian ? treg + 1 : treg, r, breg);
6424 /* FIXME: A possible overflow which I don't know how to deal
6426 offset_expr.X_add_number += 4;
6427 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6428 target_big_endian ? treg : treg + 1, r, breg);
6430 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6431 does not become a variant frag. */
6432 frag_wane (frag_now);
6441 * The MIPS assembler seems to check for X_add_number not
6442 * being double aligned and generating:
6445 * addiu at,at,%lo(foo+1)
6448 * But, the resulting address is the same after relocation so why
6449 * generate the extra instruction?
6451 if (mips_opts.arch == CPU_R4650)
6453 as_bad (_("opcode not supported on this processor"));
6456 /* Itbl support may require additional care here. */
6458 if (mips_opts.isa != ISA_MIPS1)
6469 if (mips_opts.arch == CPU_R4650)
6471 as_bad (_("opcode not supported on this processor"));
6475 if (mips_opts.isa != ISA_MIPS1)
6483 /* Itbl support may require additional care here. */
6488 if (HAVE_64BIT_GPRS)
6499 if (HAVE_64BIT_GPRS)
6509 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6510 loads for the case of doing a pair of loads to simulate an 'ld'.
6511 This is not currently done by the compiler, and assembly coders
6512 writing embedded-pic code can cope. */
6514 if (offset_expr.X_op != O_symbol
6515 && offset_expr.X_op != O_constant)
6517 as_bad (_("expression too complex"));
6518 offset_expr.X_op = O_constant;
6521 /* Even on a big endian machine $fn comes before $fn+1. We have
6522 to adjust when loading from memory. We set coproc if we must
6523 load $fn+1 first. */
6524 /* Itbl support may require additional care here. */
6525 if (! target_big_endian)
6528 if (mips_pic == NO_PIC
6529 || offset_expr.X_op == O_constant)
6533 /* If this is a reference to a GP relative symbol, we want
6534 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6535 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6536 If we have a base register, we use this
6538 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6539 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6540 If this is not a GP relative symbol, we want
6541 lui $at,<sym> (BFD_RELOC_HI16_S)
6542 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6543 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6544 If there is a base register, we add it to $at after the
6545 lui instruction. If there is a constant, we always use
6547 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6548 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6560 tempreg = mips_gp_register;
6567 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6568 AT, breg, mips_gp_register);
6574 /* Itbl support may require additional care here. */
6575 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6576 coproc ? treg + 1 : treg,
6577 BFD_RELOC_GPREL16, tempreg);
6578 offset_expr.X_add_number += 4;
6580 /* Set mips_optimize to 2 to avoid inserting an
6582 hold_mips_optimize = mips_optimize;
6584 /* Itbl support may require additional care here. */
6585 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6586 coproc ? treg : treg + 1,
6587 BFD_RELOC_GPREL16, tempreg);
6588 mips_optimize = hold_mips_optimize;
6590 p = frag_var (rs_machine_dependent, 12 + off, 0,
6591 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6592 used_at && mips_opts.noat),
6593 offset_expr.X_add_symbol, 0, NULL);
6595 /* We just generated two relocs. When tc_gen_reloc
6596 handles this case, it will skip the first reloc and
6597 handle the second. The second reloc already has an
6598 extra addend of 4, which we added above. We must
6599 subtract it out, and then subtract another 4 to make
6600 the first reloc come out right. The second reloc
6601 will come out right because we are going to add 4 to
6602 offset_expr when we build its instruction below.
6604 If we have a symbol, then we don't want to include
6605 the offset, because it will wind up being included
6606 when we generate the reloc. */
6608 if (offset_expr.X_op == O_constant)
6609 offset_expr.X_add_number -= 8;
6612 offset_expr.X_add_number = -4;
6613 offset_expr.X_op = O_constant;
6616 macro_build_lui (p, &icnt, &offset_expr, AT);
6621 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6626 /* Itbl support may require additional care here. */
6627 macro_build (p, &icnt, &offset_expr, s, fmt,
6628 coproc ? treg + 1 : treg,
6629 BFD_RELOC_LO16, AT);
6632 /* FIXME: How do we handle overflow here? */
6633 offset_expr.X_add_number += 4;
6634 /* Itbl support may require additional care here. */
6635 macro_build (p, &icnt, &offset_expr, s, fmt,
6636 coproc ? treg : treg + 1,
6637 BFD_RELOC_LO16, AT);
6639 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6643 /* If this is a reference to an external symbol, we want
6644 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6649 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6651 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6652 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6653 If there is a base register we add it to $at before the
6654 lwc1 instructions. If there is a constant we include it
6655 in the lwc1 instructions. */
6657 expr1.X_add_number = offset_expr.X_add_number;
6658 offset_expr.X_add_number = 0;
6659 if (expr1.X_add_number < -0x8000
6660 || expr1.X_add_number >= 0x8000 - 4)
6661 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6666 frag_grow (24 + off);
6667 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6668 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6669 macro_build (NULL, &icnt, NULL, "nop", "");
6671 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6673 /* Itbl support may require additional care here. */
6674 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6675 BFD_RELOC_LO16, AT);
6676 expr1.X_add_number += 4;
6678 /* Set mips_optimize to 2 to avoid inserting an undesired
6680 hold_mips_optimize = mips_optimize;
6682 /* Itbl support may require additional care here. */
6683 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6684 BFD_RELOC_LO16, AT);
6685 mips_optimize = hold_mips_optimize;
6687 (void) frag_var (rs_machine_dependent, 0, 0,
6688 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6689 offset_expr.X_add_symbol, 0, NULL);
6691 else if (mips_pic == SVR4_PIC)
6696 /* If this is a reference to an external symbol, we want
6697 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6699 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6704 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6706 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6707 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6708 If there is a base register we add it to $at before the
6709 lwc1 instructions. If there is a constant we include it
6710 in the lwc1 instructions. */
6712 expr1.X_add_number = offset_expr.X_add_number;
6713 offset_expr.X_add_number = 0;
6714 if (expr1.X_add_number < -0x8000
6715 || expr1.X_add_number >= 0x8000 - 4)
6716 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6717 if (reg_needs_delay (mips_gp_register))
6726 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
6727 BFD_RELOC_MIPS_GOT_HI16);
6728 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6729 AT, AT, mips_gp_register);
6730 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6731 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6732 macro_build (NULL, &icnt, NULL, "nop", "");
6734 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6736 /* Itbl support may require additional care here. */
6737 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6738 BFD_RELOC_LO16, AT);
6739 expr1.X_add_number += 4;
6741 /* Set mips_optimize to 2 to avoid inserting an undesired
6743 hold_mips_optimize = mips_optimize;
6745 /* Itbl support may require additional care here. */
6746 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6747 BFD_RELOC_LO16, AT);
6748 mips_optimize = hold_mips_optimize;
6749 expr1.X_add_number -= 4;
6751 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6752 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6753 8 + gpdel + off, 1, 0),
6754 offset_expr.X_add_symbol, 0, NULL);
6757 macro_build (p, &icnt, NULL, "nop", "");
6760 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6761 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6763 macro_build (p, &icnt, NULL, "nop", "");
6767 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6771 /* Itbl support may require additional care here. */
6772 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6773 BFD_RELOC_LO16, AT);
6775 expr1.X_add_number += 4;
6777 /* Set mips_optimize to 2 to avoid inserting an undesired
6779 hold_mips_optimize = mips_optimize;
6781 /* Itbl support may require additional care here. */
6782 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6783 BFD_RELOC_LO16, AT);
6784 mips_optimize = hold_mips_optimize;
6786 else if (mips_pic == EMBEDDED_PIC)
6788 /* If there is no base register, we use
6789 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6790 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6791 If we have a base register, we use
6793 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6794 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6798 tempreg = mips_gp_register;
6803 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6804 AT, breg, mips_gp_register);
6809 /* Itbl support may require additional care here. */
6810 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6811 coproc ? treg + 1 : treg,
6812 BFD_RELOC_GPREL16, tempreg);
6813 offset_expr.X_add_number += 4;
6814 /* Itbl support may require additional care here. */
6815 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6816 coproc ? treg : treg + 1,
6817 BFD_RELOC_GPREL16, tempreg);
6833 assert (HAVE_32BIT_ADDRESSES);
6834 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6835 BFD_RELOC_LO16, breg);
6836 offset_expr.X_add_number += 4;
6837 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6838 BFD_RELOC_LO16, breg);
6841 /* New code added to support COPZ instructions.
6842 This code builds table entries out of the macros in mip_opcodes.
6843 R4000 uses interlocks to handle coproc delays.
6844 Other chips (like the R3000) require nops to be inserted for delays.
6846 FIXME: Currently, we require that the user handle delays.
6847 In order to fill delay slots for non-interlocked chips,
6848 we must have a way to specify delays based on the coprocessor.
6849 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6850 What are the side-effects of the cop instruction?
6851 What cache support might we have and what are its effects?
6852 Both coprocessor & memory require delays. how long???
6853 What registers are read/set/modified?
6855 If an itbl is provided to interpret cop instructions,
6856 this knowledge can be encoded in the itbl spec. */
6870 /* For now we just do C (same as Cz). The parameter will be
6871 stored in insn_opcode by mips_ip. */
6872 macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
6876 move_register (&icnt, dreg, sreg);
6879 #ifdef LOSING_COMPILER
6881 /* Try and see if this is a new itbl instruction.
6882 This code builds table entries out of the macros in mip_opcodes.
6883 FIXME: For now we just assemble the expression and pass it's
6884 value along as a 32-bit immediate.
6885 We may want to have the assembler assemble this value,
6886 so that we gain the assembler's knowledge of delay slots,
6888 Would it be more efficient to use mask (id) here? */
6889 if (itbl_have_entries
6890 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6892 s = ip->insn_mo->name;
6894 coproc = ITBL_DECODE_PNUM (immed_expr);;
6895 macro_build (NULL, &icnt, &immed_expr, s, "C");
6902 as_warn (_("Macro used $at after \".set noat\""));
6906 macro2 (struct mips_cl_insn *ip)
6908 register int treg, sreg, dreg, breg;
6924 bfd_reloc_code_real_type r;
6927 treg = (ip->insn_opcode >> 16) & 0x1f;
6928 dreg = (ip->insn_opcode >> 11) & 0x1f;
6929 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6930 mask = ip->insn_mo->mask;
6932 expr1.X_op = O_constant;
6933 expr1.X_op_symbol = NULL;
6934 expr1.X_add_symbol = NULL;
6935 expr1.X_add_number = 1;
6939 #endif /* LOSING_COMPILER */
6944 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
6946 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
6952 /* The MIPS assembler some times generates shifts and adds. I'm
6953 not trying to be that fancy. GCC should do this for us
6955 load_register (&icnt, AT, &imm_expr, dbl);
6956 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
6958 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
6971 mips_emit_delays (TRUE);
6972 ++mips_opts.noreorder;
6973 mips_any_noreorder = 1;
6975 load_register (&icnt, AT, &imm_expr, dbl);
6976 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
6977 sreg, imm ? AT : treg);
6978 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
6979 macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
6981 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
6983 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
6986 expr1.X_add_number = 8;
6987 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
6988 macro_build (NULL, &icnt, NULL, "nop", "", 0);
6989 macro_build (NULL, &icnt, NULL, "break", "c", 6);
6991 --mips_opts.noreorder;
6992 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7005 mips_emit_delays (TRUE);
7006 ++mips_opts.noreorder;
7007 mips_any_noreorder = 1;
7009 load_register (&icnt, AT, &imm_expr, dbl);
7010 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7011 sreg, imm ? AT : treg);
7012 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7013 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7015 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
7018 expr1.X_add_number = 8;
7019 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
7020 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7021 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7023 --mips_opts.noreorder;
7027 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7039 macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
7040 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
7046 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7047 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7048 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7049 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7053 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7065 macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
7066 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
7072 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7073 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
7074 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
7075 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7083 if (imm_expr.X_op != O_constant)
7084 as_bad (_("Improper rotate count"));
7085 rot = imm_expr.X_add_number & 0x3f;
7086 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7088 rot = (64 - rot) & 0x3f;
7090 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7091 dreg, sreg, rot - 32);
7093 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7099 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7102 l = (rot < 0x20) ? "dsll" : "dsll32";
7103 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7105 macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
7106 macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
7107 (0x20 - rot) & 0x1f);
7108 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7116 if (imm_expr.X_op != O_constant)
7117 as_bad (_("Improper rotate count"));
7118 rot = imm_expr.X_add_number & 0x1f;
7119 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7121 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
7127 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7130 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
7131 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
7132 (0x20 - rot) & 0x1f);
7133 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7138 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7140 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
7143 macro_build (NULL, &icnt,NULL, "dsubu", "d,v,t", AT, 0, treg);
7144 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
7145 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7146 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7150 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7152 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
7155 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7156 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
7157 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
7158 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7166 if (imm_expr.X_op != O_constant)
7167 as_bad (_("Improper rotate count"));
7168 rot = imm_expr.X_add_number & 0x3f;
7169 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7172 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7173 dreg, sreg, rot - 32);
7175 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7181 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7184 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7185 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7187 macro_build ( NULL, &icnt,NULL, r, "d,w,<", AT, sreg, rot);
7188 macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
7189 (0x20 - rot) & 0x1f);
7190 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7198 if (imm_expr.X_op != O_constant)
7199 as_bad (_("Improper rotate count"));
7200 rot = imm_expr.X_add_number & 0x1f;
7201 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7203 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
7208 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7211 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
7212 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
7213 (0x20 - rot) & 0x1f);
7214 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7219 if (mips_opts.arch == CPU_R4650)
7221 as_bad (_("opcode not supported on this processor"));
7224 assert (mips_opts.isa == ISA_MIPS1);
7225 /* Even on a big endian machine $fn comes before $fn+1. We have
7226 to adjust when storing to memory. */
7227 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7228 target_big_endian ? treg + 1 : treg,
7229 BFD_RELOC_LO16, breg);
7230 offset_expr.X_add_number += 4;
7231 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7232 target_big_endian ? treg : treg + 1,
7233 BFD_RELOC_LO16, breg);
7238 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
7241 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7245 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7246 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7252 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7254 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7260 as_warn (_("Instruction %s: result is always false"),
7262 move_register (&icnt, dreg, 0);
7265 if (imm_expr.X_op == O_constant
7266 && imm_expr.X_add_number >= 0
7267 && imm_expr.X_add_number < 0x10000)
7269 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7273 else if (imm_expr.X_op == O_constant
7274 && imm_expr.X_add_number > -0x8000
7275 && imm_expr.X_add_number < 0)
7277 imm_expr.X_add_number = -imm_expr.X_add_number;
7278 macro_build (NULL, &icnt, &imm_expr,
7279 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7280 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7285 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7286 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7289 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7295 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7301 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
7302 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7306 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7308 if (imm_expr.X_op == O_constant
7309 && imm_expr.X_add_number >= -0x8000
7310 && imm_expr.X_add_number < 0x8000)
7312 macro_build (NULL, &icnt, &imm_expr,
7313 mask == M_SGE_I ? "slti" : "sltiu",
7314 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7319 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7320 macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
7321 "d,v,t", dreg, sreg, AT);
7324 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7330 case M_SGT: /* sreg > treg <==> treg < sreg */
7336 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7339 case M_SGT_I: /* sreg > I <==> I < sreg */
7345 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7346 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7349 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7355 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7356 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7360 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7366 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7367 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7368 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7373 if (imm_expr.X_op == O_constant
7374 && imm_expr.X_add_number >= -0x8000
7375 && imm_expr.X_add_number < 0x8000)
7377 macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
7381 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7382 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
7386 if (imm_expr.X_op == O_constant
7387 && imm_expr.X_add_number >= -0x8000
7388 && imm_expr.X_add_number < 0x8000)
7390 macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
7394 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7395 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
7400 macro_build (NULL, &icnt,NULL, "sltu","d,v,t", dreg, 0, treg);
7402 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7405 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7406 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7411 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7413 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7418 as_warn (_("Instruction %s: result is always true"),
7420 macro_build (NULL, &icnt, &expr1,
7421 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7422 "t,r,j", dreg, 0, BFD_RELOC_LO16);
7425 if (imm_expr.X_op == O_constant
7426 && imm_expr.X_add_number >= 0
7427 && imm_expr.X_add_number < 0x10000)
7429 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7433 else if (imm_expr.X_op == O_constant
7434 && imm_expr.X_add_number > -0x8000
7435 && imm_expr.X_add_number < 0)
7437 imm_expr.X_add_number = -imm_expr.X_add_number;
7438 macro_build (NULL, &icnt, &imm_expr,
7439 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7440 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7445 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7446 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7449 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7457 if (imm_expr.X_op == O_constant
7458 && imm_expr.X_add_number > -0x8000
7459 && imm_expr.X_add_number <= 0x8000)
7461 imm_expr.X_add_number = -imm_expr.X_add_number;
7462 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
7463 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7466 load_register (&icnt, AT, &imm_expr, dbl);
7467 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
7474 if (imm_expr.X_op == O_constant
7475 && imm_expr.X_add_number > -0x8000
7476 && imm_expr.X_add_number <= 0x8000)
7478 imm_expr.X_add_number = -imm_expr.X_add_number;
7479 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
7480 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7483 load_register (&icnt, AT, &imm_expr, dbl);
7484 macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
7506 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7507 macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
7512 assert (mips_opts.isa == ISA_MIPS1);
7513 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7514 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7517 * Is the double cfc1 instruction a bug in the mips assembler;
7518 * or is there a reason for it?
7520 mips_emit_delays (TRUE);
7521 ++mips_opts.noreorder;
7522 mips_any_noreorder = 1;
7523 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7524 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7525 macro_build (NULL, &icnt, NULL, "nop", "");
7526 expr1.X_add_number = 3;
7527 macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7529 expr1.X_add_number = 2;
7530 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7532 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
7533 macro_build (NULL, &icnt, NULL, "nop", "");
7534 macro_build (NULL, &icnt, NULL,
7535 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
7537 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
7538 macro_build (NULL, &icnt, NULL, "nop", "");
7539 --mips_opts.noreorder;
7548 if (offset_expr.X_add_number >= 0x7fff)
7549 as_bad (_("operand overflow"));
7550 if (! target_big_endian)
7551 ++offset_expr.X_add_number;
7552 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7553 BFD_RELOC_LO16, breg);
7554 if (! target_big_endian)
7555 --offset_expr.X_add_number;
7557 ++offset_expr.X_add_number;
7558 macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7559 BFD_RELOC_LO16, breg);
7560 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
7561 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7574 if (offset_expr.X_add_number >= 0x8000 - off)
7575 as_bad (_("operand overflow"));
7580 if (! target_big_endian)
7581 offset_expr.X_add_number += off;
7582 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7583 BFD_RELOC_LO16, breg);
7584 if (! target_big_endian)
7585 offset_expr.X_add_number -= off;
7587 offset_expr.X_add_number += off;
7588 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7589 BFD_RELOC_LO16, breg);
7591 /* If necessary, move the result in tempreg the final destination. */
7592 if (treg == tempreg)
7594 /* Protect second load's delay slot. */
7595 if (!gpr_interlocks)
7596 macro_build (NULL, &icnt, NULL, "nop", "");
7597 move_register (&icnt, treg, tempreg);
7611 load_address (&icnt, AT, &offset_expr, &used_at);
7613 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7615 if (! target_big_endian)
7616 expr1.X_add_number = off;
7618 expr1.X_add_number = 0;
7619 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7620 BFD_RELOC_LO16, AT);
7621 if (! target_big_endian)
7622 expr1.X_add_number = 0;
7624 expr1.X_add_number = off;
7625 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7626 BFD_RELOC_LO16, AT);
7632 load_address (&icnt, AT, &offset_expr, &used_at);
7634 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7636 if (target_big_endian)
7637 expr1.X_add_number = 0;
7638 macro_build (NULL, &icnt, &expr1,
7639 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7640 treg, BFD_RELOC_LO16, AT);
7641 if (target_big_endian)
7642 expr1.X_add_number = 1;
7644 expr1.X_add_number = 0;
7645 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
7646 AT, BFD_RELOC_LO16, AT);
7647 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7648 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7652 if (offset_expr.X_add_number >= 0x7fff)
7653 as_bad (_("operand overflow"));
7654 if (target_big_endian)
7655 ++offset_expr.X_add_number;
7656 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7657 BFD_RELOC_LO16, breg);
7658 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
7659 if (target_big_endian)
7660 --offset_expr.X_add_number;
7662 ++offset_expr.X_add_number;
7663 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7664 BFD_RELOC_LO16, breg);
7677 if (offset_expr.X_add_number >= 0x8000 - off)
7678 as_bad (_("operand overflow"));
7679 if (! target_big_endian)
7680 offset_expr.X_add_number += off;
7681 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7682 BFD_RELOC_LO16, breg);
7683 if (! target_big_endian)
7684 offset_expr.X_add_number -= off;
7686 offset_expr.X_add_number += off;
7687 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7688 BFD_RELOC_LO16, breg);
7702 load_address (&icnt, AT, &offset_expr, &used_at);
7704 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7706 if (! target_big_endian)
7707 expr1.X_add_number = off;
7709 expr1.X_add_number = 0;
7710 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7711 BFD_RELOC_LO16, AT);
7712 if (! target_big_endian)
7713 expr1.X_add_number = 0;
7715 expr1.X_add_number = off;
7716 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7717 BFD_RELOC_LO16, AT);
7722 load_address (&icnt, AT, &offset_expr, &used_at);
7724 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7726 if (! target_big_endian)
7727 expr1.X_add_number = 0;
7728 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7729 BFD_RELOC_LO16, AT);
7730 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
7731 if (! target_big_endian)
7732 expr1.X_add_number = 1;
7734 expr1.X_add_number = 0;
7735 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7736 BFD_RELOC_LO16, AT);
7737 if (! target_big_endian)
7738 expr1.X_add_number = 0;
7740 expr1.X_add_number = 1;
7741 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7742 BFD_RELOC_LO16, AT);
7743 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7744 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7748 /* FIXME: Check if this is one of the itbl macros, since they
7749 are added dynamically. */
7750 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7754 as_warn (_("Macro used $at after \".set noat\""));
7757 /* Implement macros in mips16 mode. */
7760 mips16_macro (struct mips_cl_insn *ip)
7763 int xreg, yreg, zreg, tmp;
7767 const char *s, *s2, *s3;
7769 mask = ip->insn_mo->mask;
7771 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7772 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7773 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7777 expr1.X_op = O_constant;
7778 expr1.X_op_symbol = NULL;
7779 expr1.X_add_symbol = NULL;
7780 expr1.X_add_number = 1;
7799 mips_emit_delays (TRUE);
7800 ++mips_opts.noreorder;
7801 mips_any_noreorder = 1;
7802 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
7804 expr1.X_add_number = 2;
7805 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7806 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7808 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7809 since that causes an overflow. We should do that as well,
7810 but I don't see how to do the comparisons without a temporary
7812 --mips_opts.noreorder;
7813 macro_build (NULL, &icnt, NULL, s, "x", zreg);
7832 mips_emit_delays (TRUE);
7833 ++mips_opts.noreorder;
7834 mips_any_noreorder = 1;
7835 macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
7836 expr1.X_add_number = 2;
7837 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7838 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7839 --mips_opts.noreorder;
7840 macro_build (NULL, &icnt, NULL, s2, "x", zreg);
7846 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
7848 macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
7856 if (imm_expr.X_op != O_constant)
7857 as_bad (_("Unsupported large constant"));
7858 imm_expr.X_add_number = -imm_expr.X_add_number;
7859 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
7864 if (imm_expr.X_op != O_constant)
7865 as_bad (_("Unsupported large constant"));
7866 imm_expr.X_add_number = -imm_expr.X_add_number;
7867 macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
7871 if (imm_expr.X_op != O_constant)
7872 as_bad (_("Unsupported large constant"));
7873 imm_expr.X_add_number = -imm_expr.X_add_number;
7874 macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
7896 goto do_reverse_branch;
7900 goto do_reverse_branch;
7912 goto do_reverse_branch;
7923 macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
7924 macro_build (NULL, &icnt, &offset_expr, s2, "p");
7951 goto do_addone_branch_i;
7956 goto do_addone_branch_i;
7971 goto do_addone_branch_i;
7978 if (imm_expr.X_op != O_constant)
7979 as_bad (_("Unsupported large constant"));
7980 ++imm_expr.X_add_number;
7983 macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
7984 macro_build (NULL, &icnt, &offset_expr, s2, "p");
7988 expr1.X_add_number = 0;
7989 macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
7991 move_register (&icnt, xreg, yreg);
7992 expr1.X_add_number = 2;
7993 macro_build (NULL, &icnt, &expr1, "bteqz", "p");
7994 macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
7998 /* For consistency checking, verify that all bits are specified either
7999 by the match/mask part of the instruction definition, or by the
8002 validate_mips_insn (const struct mips_opcode *opc)
8004 const char *p = opc->args;
8006 unsigned long used_bits = opc->mask;
8008 if ((used_bits & opc->match) != opc->match)
8010 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8011 opc->name, opc->args);
8014 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8024 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8025 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8026 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8027 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8028 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8030 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8031 c, opc->name, opc->args);
8035 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8036 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8038 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8039 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8040 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8041 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8043 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8044 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8046 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8047 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8049 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8050 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8051 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8052 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8053 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8054 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8055 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8056 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8057 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8058 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8059 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8060 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8061 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8062 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8063 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8064 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8065 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8067 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8068 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8069 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8070 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8072 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8073 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8074 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8075 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8076 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8077 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8078 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8079 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8080 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8083 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8084 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8085 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8086 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8087 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8091 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8092 c, opc->name, opc->args);
8096 if (used_bits != 0xffffffff)
8098 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8099 ~used_bits & 0xffffffff, opc->name, opc->args);
8105 /* This routine assembles an instruction into its binary format. As a
8106 side effect, it sets one of the global variables imm_reloc or
8107 offset_reloc to the type of relocation to do if one of the operands
8108 is an address expression. */
8111 mips_ip (char *str, struct mips_cl_insn *ip)
8116 struct mips_opcode *insn;
8119 unsigned int lastregno = 0;
8120 unsigned int lastpos = 0;
8121 unsigned int limlo, limhi;
8127 /* If the instruction contains a '.', we first try to match an instruction
8128 including the '.'. Then we try again without the '.'. */
8130 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8133 /* If we stopped on whitespace, then replace the whitespace with null for
8134 the call to hash_find. Save the character we replaced just in case we
8135 have to re-parse the instruction. */
8142 insn = (struct mips_opcode *) hash_find (op_hash, str);
8144 /* If we didn't find the instruction in the opcode table, try again, but
8145 this time with just the instruction up to, but not including the
8149 /* Restore the character we overwrite above (if any). */
8153 /* Scan up to the first '.' or whitespace. */
8155 *s != '\0' && *s != '.' && !ISSPACE (*s);
8159 /* If we did not find a '.', then we can quit now. */
8162 insn_error = "unrecognized opcode";
8166 /* Lookup the instruction in the hash table. */
8168 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8170 insn_error = "unrecognized opcode";
8180 assert (strcmp (insn->name, str) == 0);
8182 if (OPCODE_IS_MEMBER (insn,
8184 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8185 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8186 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8192 if (insn->pinfo != INSN_MACRO)
8194 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8200 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8201 && strcmp (insn->name, insn[1].name) == 0)
8210 static char buf[100];
8212 _("opcode not supported on this processor: %s (%s)"),
8213 mips_cpu_info_from_arch (mips_opts.arch)->name,
8214 mips_cpu_info_from_isa (mips_opts.isa)->name);
8224 ip->insn_opcode = insn->match;
8226 for (args = insn->args;; ++args)
8230 s += strspn (s, " \t");
8234 case '\0': /* end of args */
8247 ip->insn_opcode |= lastregno << OP_SH_RS;
8251 ip->insn_opcode |= lastregno << OP_SH_RT;
8255 ip->insn_opcode |= lastregno << OP_SH_FT;
8259 ip->insn_opcode |= lastregno << OP_SH_FS;
8265 /* Handle optional base register.
8266 Either the base register is omitted or
8267 we must have a left paren. */
8268 /* This is dependent on the next operand specifier
8269 is a base register specification. */
8270 assert (args[1] == 'b' || args[1] == '5'
8271 || args[1] == '-' || args[1] == '4');
8275 case ')': /* these must match exactly */
8282 case '+': /* Opcode extension character. */
8285 case 'A': /* ins/ext position, becomes LSB. */
8288 my_getExpression (&imm_expr, s);
8289 check_absolute_expr (ip, &imm_expr);
8290 if ((unsigned long) imm_expr.X_add_number < limlo
8291 || (unsigned long) imm_expr.X_add_number > limhi)
8293 as_bad (_("Improper position (%lu)"),
8294 (unsigned long) imm_expr.X_add_number);
8295 imm_expr.X_add_number = limlo;
8297 lastpos = imm_expr.X_add_number;
8298 ip->insn_opcode |= (imm_expr.X_add_number
8299 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8300 imm_expr.X_op = O_absent;
8304 case 'B': /* ins size, becomes MSB. */
8307 my_getExpression (&imm_expr, s);
8308 check_absolute_expr (ip, &imm_expr);
8309 /* Check for negative input so that small negative numbers
8310 will not succeed incorrectly. The checks against
8311 (pos+size) transitively check "size" itself,
8312 assuming that "pos" is reasonable. */
8313 if ((long) imm_expr.X_add_number < 0
8314 || ((unsigned long) imm_expr.X_add_number
8316 || ((unsigned long) imm_expr.X_add_number
8319 as_bad (_("Improper insert size (%lu, position %lu)"),
8320 (unsigned long) imm_expr.X_add_number,
8321 (unsigned long) lastpos);
8322 imm_expr.X_add_number = limlo - lastpos;
8324 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8325 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8326 imm_expr.X_op = O_absent;
8330 case 'C': /* ext size, becomes MSBD. */
8333 my_getExpression (&imm_expr, s);
8334 check_absolute_expr (ip, &imm_expr);
8335 /* Check for negative input so that small negative numbers
8336 will not succeed incorrectly. The checks against
8337 (pos+size) transitively check "size" itself,
8338 assuming that "pos" is reasonable. */
8339 if ((long) imm_expr.X_add_number < 0
8340 || ((unsigned long) imm_expr.X_add_number
8342 || ((unsigned long) imm_expr.X_add_number
8345 as_bad (_("Improper extract size (%lu, position %lu)"),
8346 (unsigned long) imm_expr.X_add_number,
8347 (unsigned long) lastpos);
8348 imm_expr.X_add_number = limlo - lastpos;
8350 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8351 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8352 imm_expr.X_op = O_absent;
8357 /* +D is for disassembly only; never match. */
8361 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8362 *args, insn->name, insn->args);
8363 /* Further processing is fruitless. */
8368 case '<': /* must be at least one digit */
8370 * According to the manual, if the shift amount is greater
8371 * than 31 or less than 0, then the shift amount should be
8372 * mod 32. In reality the mips assembler issues an error.
8373 * We issue a warning and mask out all but the low 5 bits.
8375 my_getExpression (&imm_expr, s);
8376 check_absolute_expr (ip, &imm_expr);
8377 if ((unsigned long) imm_expr.X_add_number > 31)
8379 as_warn (_("Improper shift amount (%lu)"),
8380 (unsigned long) imm_expr.X_add_number);
8381 imm_expr.X_add_number &= OP_MASK_SHAMT;
8383 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8384 imm_expr.X_op = O_absent;
8388 case '>': /* shift amount minus 32 */
8389 my_getExpression (&imm_expr, s);
8390 check_absolute_expr (ip, &imm_expr);
8391 if ((unsigned long) imm_expr.X_add_number < 32
8392 || (unsigned long) imm_expr.X_add_number > 63)
8394 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8395 imm_expr.X_op = O_absent;
8399 case 'k': /* cache code */
8400 case 'h': /* prefx code */
8401 my_getExpression (&imm_expr, s);
8402 check_absolute_expr (ip, &imm_expr);
8403 if ((unsigned long) imm_expr.X_add_number > 31)
8405 as_warn (_("Invalid value for `%s' (%lu)"),
8407 (unsigned long) imm_expr.X_add_number);
8408 imm_expr.X_add_number &= 0x1f;
8411 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8413 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8414 imm_expr.X_op = O_absent;
8418 case 'c': /* break code */
8419 my_getExpression (&imm_expr, s);
8420 check_absolute_expr (ip, &imm_expr);
8421 if ((unsigned long) imm_expr.X_add_number > 1023)
8423 as_warn (_("Illegal break code (%lu)"),
8424 (unsigned long) imm_expr.X_add_number);
8425 imm_expr.X_add_number &= OP_MASK_CODE;
8427 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8428 imm_expr.X_op = O_absent;
8432 case 'q': /* lower break code */
8433 my_getExpression (&imm_expr, s);
8434 check_absolute_expr (ip, &imm_expr);
8435 if ((unsigned long) imm_expr.X_add_number > 1023)
8437 as_warn (_("Illegal lower break code (%lu)"),
8438 (unsigned long) imm_expr.X_add_number);
8439 imm_expr.X_add_number &= OP_MASK_CODE2;
8441 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8442 imm_expr.X_op = O_absent;
8446 case 'B': /* 20-bit syscall/break code. */
8447 my_getExpression (&imm_expr, s);
8448 check_absolute_expr (ip, &imm_expr);
8449 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8450 as_warn (_("Illegal 20-bit code (%lu)"),
8451 (unsigned long) imm_expr.X_add_number);
8452 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8453 imm_expr.X_op = O_absent;
8457 case 'C': /* Coprocessor code */
8458 my_getExpression (&imm_expr, s);
8459 check_absolute_expr (ip, &imm_expr);
8460 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8462 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8463 (unsigned long) imm_expr.X_add_number);
8464 imm_expr.X_add_number &= ((1 << 25) - 1);
8466 ip->insn_opcode |= imm_expr.X_add_number;
8467 imm_expr.X_op = O_absent;
8471 case 'J': /* 19-bit wait code. */
8472 my_getExpression (&imm_expr, s);
8473 check_absolute_expr (ip, &imm_expr);
8474 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8475 as_warn (_("Illegal 19-bit code (%lu)"),
8476 (unsigned long) imm_expr.X_add_number);
8477 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8478 imm_expr.X_op = O_absent;
8482 case 'P': /* Performance register */
8483 my_getExpression (&imm_expr, s);
8484 check_absolute_expr (ip, &imm_expr);
8485 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8487 as_warn (_("Invalid performance register (%lu)"),
8488 (unsigned long) imm_expr.X_add_number);
8489 imm_expr.X_add_number &= OP_MASK_PERFREG;
8491 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8492 imm_expr.X_op = O_absent;
8496 case 'b': /* base register */
8497 case 'd': /* destination register */
8498 case 's': /* source register */
8499 case 't': /* target register */
8500 case 'r': /* both target and source */
8501 case 'v': /* both dest and source */
8502 case 'w': /* both dest and target */
8503 case 'E': /* coprocessor target register */
8504 case 'G': /* coprocessor destination register */
8505 case 'K': /* 'rdhwr' destination register */
8506 case 'x': /* ignore register name */
8507 case 'z': /* must be zero register */
8508 case 'U': /* destination register (clo/clz). */
8523 while (ISDIGIT (*s));
8525 as_bad (_("Invalid register number (%d)"), regno);
8527 else if (*args == 'E' || *args == 'G' || *args == 'K')
8531 if (s[1] == 'r' && s[2] == 'a')
8536 else if (s[1] == 'f' && s[2] == 'p')
8541 else if (s[1] == 's' && s[2] == 'p')
8546 else if (s[1] == 'g' && s[2] == 'p')
8551 else if (s[1] == 'a' && s[2] == 't')
8556 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8561 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8566 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8571 else if (itbl_have_entries)
8576 p = s + 1; /* advance past '$' */
8577 n = itbl_get_field (&p); /* n is name */
8579 /* See if this is a register defined in an
8581 if (itbl_get_reg_val (n, &r))
8583 /* Get_field advances to the start of
8584 the next field, so we need to back
8585 rack to the end of the last field. */
8589 s = strchr (s, '\0');
8603 as_warn (_("Used $at without \".set noat\""));
8609 if (c == 'r' || c == 'v' || c == 'w')
8616 /* 'z' only matches $0. */
8617 if (c == 'z' && regno != 0)
8620 /* Now that we have assembled one operand, we use the args string
8621 * to figure out where it goes in the instruction. */
8628 ip->insn_opcode |= regno << OP_SH_RS;
8633 ip->insn_opcode |= regno << OP_SH_RD;
8636 ip->insn_opcode |= regno << OP_SH_RD;
8637 ip->insn_opcode |= regno << OP_SH_RT;
8642 ip->insn_opcode |= regno << OP_SH_RT;
8645 /* This case exists because on the r3000 trunc
8646 expands into a macro which requires a gp
8647 register. On the r6000 or r4000 it is
8648 assembled into a single instruction which
8649 ignores the register. Thus the insn version
8650 is MIPS_ISA2 and uses 'x', and the macro
8651 version is MIPS_ISA1 and uses 't'. */
8654 /* This case is for the div instruction, which
8655 acts differently if the destination argument
8656 is $0. This only matches $0, and is checked
8657 outside the switch. */
8660 /* Itbl operand; not yet implemented. FIXME ?? */
8662 /* What about all other operands like 'i', which
8663 can be specified in the opcode table? */
8673 ip->insn_opcode |= lastregno << OP_SH_RS;
8676 ip->insn_opcode |= lastregno << OP_SH_RT;
8681 case 'O': /* MDMX alignment immediate constant. */
8682 my_getExpression (&imm_expr, s);
8683 check_absolute_expr (ip, &imm_expr);
8684 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8686 as_warn ("Improper align amount (%ld), using low bits",
8687 (long) imm_expr.X_add_number);
8688 imm_expr.X_add_number &= OP_MASK_ALN;
8690 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8691 imm_expr.X_op = O_absent;
8695 case 'Q': /* MDMX vector, element sel, or const. */
8698 /* MDMX Immediate. */
8699 my_getExpression (&imm_expr, s);
8700 check_absolute_expr (ip, &imm_expr);
8701 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8703 as_warn (_("Invalid MDMX Immediate (%ld)"),
8704 (long) imm_expr.X_add_number);
8705 imm_expr.X_add_number &= OP_MASK_FT;
8707 imm_expr.X_add_number &= OP_MASK_FT;
8708 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8709 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8711 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8712 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8713 imm_expr.X_op = O_absent;
8717 /* Not MDMX Immediate. Fall through. */
8718 case 'X': /* MDMX destination register. */
8719 case 'Y': /* MDMX source register. */
8720 case 'Z': /* MDMX target register. */
8722 case 'D': /* floating point destination register */
8723 case 'S': /* floating point source register */
8724 case 'T': /* floating point target register */
8725 case 'R': /* floating point source register */
8729 /* Accept $fN for FP and MDMX register numbers, and in
8730 addition accept $vN for MDMX register numbers. */
8731 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8732 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8743 while (ISDIGIT (*s));
8746 as_bad (_("Invalid float register number (%d)"), regno);
8748 if ((regno & 1) != 0
8750 && ! (strcmp (str, "mtc1") == 0
8751 || strcmp (str, "mfc1") == 0
8752 || strcmp (str, "lwc1") == 0
8753 || strcmp (str, "swc1") == 0
8754 || strcmp (str, "l.s") == 0
8755 || strcmp (str, "s.s") == 0))
8756 as_warn (_("Float register should be even, was %d"),
8764 if (c == 'V' || c == 'W')
8775 ip->insn_opcode |= regno << OP_SH_FD;
8780 ip->insn_opcode |= regno << OP_SH_FS;
8783 /* This is like 'Z', but also needs to fix the MDMX
8784 vector/scalar select bits. Note that the
8785 scalar immediate case is handled above. */
8788 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8789 int max_el = (is_qh ? 3 : 7);
8791 my_getExpression(&imm_expr, s);
8792 check_absolute_expr (ip, &imm_expr);
8794 if (imm_expr.X_add_number > max_el)
8795 as_bad(_("Bad element selector %ld"),
8796 (long) imm_expr.X_add_number);
8797 imm_expr.X_add_number &= max_el;
8798 ip->insn_opcode |= (imm_expr.X_add_number
8802 as_warn(_("Expecting ']' found '%s'"), s);
8808 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8809 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8812 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8819 ip->insn_opcode |= regno << OP_SH_FT;
8822 ip->insn_opcode |= regno << OP_SH_FR;
8832 ip->insn_opcode |= lastregno << OP_SH_FS;
8835 ip->insn_opcode |= lastregno << OP_SH_FT;
8841 my_getExpression (&imm_expr, s);
8842 if (imm_expr.X_op != O_big
8843 && imm_expr.X_op != O_constant)
8844 insn_error = _("absolute expression required");
8849 my_getExpression (&offset_expr, s);
8850 *imm_reloc = BFD_RELOC_32;
8863 unsigned char temp[8];
8865 unsigned int length;
8870 /* These only appear as the last operand in an
8871 instruction, and every instruction that accepts
8872 them in any variant accepts them in all variants.
8873 This means we don't have to worry about backing out
8874 any changes if the instruction does not match.
8876 The difference between them is the size of the
8877 floating point constant and where it goes. For 'F'
8878 and 'L' the constant is 64 bits; for 'f' and 'l' it
8879 is 32 bits. Where the constant is placed is based
8880 on how the MIPS assembler does things:
8883 f -- immediate value
8886 The .lit4 and .lit8 sections are only used if
8887 permitted by the -G argument.
8889 When generating embedded PIC code, we use the
8890 .lit8 section but not the .lit4 section (we can do
8891 .lit4 inline easily; we need to put .lit8
8892 somewhere in the data segment, and using .lit8
8893 permits the linker to eventually combine identical
8896 The code below needs to know whether the target register
8897 is 32 or 64 bits wide. It relies on the fact 'f' and
8898 'F' are used with GPR-based instructions and 'l' and
8899 'L' are used with FPR-based instructions. */
8901 f64 = *args == 'F' || *args == 'L';
8902 using_gprs = *args == 'F' || *args == 'f';
8904 save_in = input_line_pointer;
8905 input_line_pointer = s;
8906 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8908 s = input_line_pointer;
8909 input_line_pointer = save_in;
8910 if (err != NULL && *err != '\0')
8912 as_bad (_("Bad floating point constant: %s"), err);
8913 memset (temp, '\0', sizeof temp);
8914 length = f64 ? 8 : 4;
8917 assert (length == (unsigned) (f64 ? 8 : 4));
8921 && (! USE_GLOBAL_POINTER_OPT
8922 || mips_pic == EMBEDDED_PIC
8923 || g_switch_value < 4
8924 || (temp[0] == 0 && temp[1] == 0)
8925 || (temp[2] == 0 && temp[3] == 0))))
8927 imm_expr.X_op = O_constant;
8928 if (! target_big_endian)
8929 imm_expr.X_add_number = bfd_getl32 (temp);
8931 imm_expr.X_add_number = bfd_getb32 (temp);
8934 && ! mips_disable_float_construction
8935 /* Constants can only be constructed in GPRs and
8936 copied to FPRs if the GPRs are at least as wide
8937 as the FPRs. Force the constant into memory if
8938 we are using 64-bit FPRs but the GPRs are only
8941 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8942 && ((temp[0] == 0 && temp[1] == 0)
8943 || (temp[2] == 0 && temp[3] == 0))
8944 && ((temp[4] == 0 && temp[5] == 0)
8945 || (temp[6] == 0 && temp[7] == 0)))
8947 /* The value is simple enough to load with a couple of
8948 instructions. If using 32-bit registers, set
8949 imm_expr to the high order 32 bits and offset_expr to
8950 the low order 32 bits. Otherwise, set imm_expr to
8951 the entire 64 bit constant. */
8952 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8954 imm_expr.X_op = O_constant;
8955 offset_expr.X_op = O_constant;
8956 if (! target_big_endian)
8958 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8959 offset_expr.X_add_number = bfd_getl32 (temp);
8963 imm_expr.X_add_number = bfd_getb32 (temp);
8964 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8966 if (offset_expr.X_add_number == 0)
8967 offset_expr.X_op = O_absent;
8969 else if (sizeof (imm_expr.X_add_number) > 4)
8971 imm_expr.X_op = O_constant;
8972 if (! target_big_endian)
8973 imm_expr.X_add_number = bfd_getl64 (temp);
8975 imm_expr.X_add_number = bfd_getb64 (temp);
8979 imm_expr.X_op = O_big;
8980 imm_expr.X_add_number = 4;
8981 if (! target_big_endian)
8983 generic_bignum[0] = bfd_getl16 (temp);
8984 generic_bignum[1] = bfd_getl16 (temp + 2);
8985 generic_bignum[2] = bfd_getl16 (temp + 4);
8986 generic_bignum[3] = bfd_getl16 (temp + 6);
8990 generic_bignum[0] = bfd_getb16 (temp + 6);
8991 generic_bignum[1] = bfd_getb16 (temp + 4);
8992 generic_bignum[2] = bfd_getb16 (temp + 2);
8993 generic_bignum[3] = bfd_getb16 (temp);
8999 const char *newname;
9002 /* Switch to the right section. */
9004 subseg = now_subseg;
9007 default: /* unused default case avoids warnings. */
9009 newname = RDATA_SECTION_NAME;
9010 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9011 || mips_pic == EMBEDDED_PIC)
9015 if (mips_pic == EMBEDDED_PIC)
9018 newname = RDATA_SECTION_NAME;
9021 assert (!USE_GLOBAL_POINTER_OPT
9022 || g_switch_value >= 4);
9026 new_seg = subseg_new (newname, (subsegT) 0);
9027 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9028 bfd_set_section_flags (stdoutput, new_seg,
9033 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9034 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9035 && strcmp (TARGET_OS, "elf") != 0)
9036 record_alignment (new_seg, 4);
9038 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9040 as_bad (_("Can't use floating point insn in this section"));
9042 /* Set the argument to the current address in the
9044 offset_expr.X_op = O_symbol;
9045 offset_expr.X_add_symbol =
9046 symbol_new ("L0\001", now_seg,
9047 (valueT) frag_now_fix (), frag_now);
9048 offset_expr.X_add_number = 0;
9050 /* Put the floating point number into the section. */
9051 p = frag_more ((int) length);
9052 memcpy (p, temp, length);
9054 /* Switch back to the original section. */
9055 subseg_set (seg, subseg);
9060 case 'i': /* 16 bit unsigned immediate */
9061 case 'j': /* 16 bit signed immediate */
9062 *imm_reloc = BFD_RELOC_LO16;
9063 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9066 offsetT minval, maxval;
9068 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9069 && strcmp (insn->name, insn[1].name) == 0);
9071 /* If the expression was written as an unsigned number,
9072 only treat it as signed if there are no more
9076 && sizeof (imm_expr.X_add_number) <= 4
9077 && imm_expr.X_op == O_constant
9078 && imm_expr.X_add_number < 0
9079 && imm_expr.X_unsigned
9083 /* For compatibility with older assemblers, we accept
9084 0x8000-0xffff as signed 16-bit numbers when only
9085 signed numbers are allowed. */
9087 minval = 0, maxval = 0xffff;
9089 minval = -0x8000, maxval = 0x7fff;
9091 minval = -0x8000, maxval = 0xffff;
9093 if (imm_expr.X_op != O_constant
9094 || imm_expr.X_add_number < minval
9095 || imm_expr.X_add_number > maxval)
9099 if (imm_expr.X_op == O_constant
9100 || imm_expr.X_op == O_big)
9101 as_bad (_("expression out of range"));
9107 case 'o': /* 16 bit offset */
9108 /* Check whether there is only a single bracketed expression
9109 left. If so, it must be the base register and the
9110 constant must be zero. */
9111 if (*s == '(' && strchr (s + 1, '(') == 0)
9113 offset_expr.X_op = O_constant;
9114 offset_expr.X_add_number = 0;
9118 /* If this value won't fit into a 16 bit offset, then go
9119 find a macro that will generate the 32 bit offset
9121 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9122 && (offset_expr.X_op != O_constant
9123 || offset_expr.X_add_number >= 0x8000
9124 || offset_expr.X_add_number < -0x8000))
9130 case 'p': /* pc relative offset */
9131 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9132 my_getExpression (&offset_expr, s);
9136 case 'u': /* upper 16 bits */
9137 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9138 && imm_expr.X_op == O_constant
9139 && (imm_expr.X_add_number < 0
9140 || imm_expr.X_add_number >= 0x10000))
9141 as_bad (_("lui expression not in range 0..65535"));
9145 case 'a': /* 26 bit address */
9146 my_getExpression (&offset_expr, s);
9148 *offset_reloc = BFD_RELOC_MIPS_JMP;
9151 case 'N': /* 3 bit branch condition code */
9152 case 'M': /* 3 bit compare condition code */
9153 if (strncmp (s, "$fcc", 4) != 0)
9163 while (ISDIGIT (*s));
9165 as_bad (_("invalid condition code register $fcc%d"), regno);
9167 ip->insn_opcode |= regno << OP_SH_BCC;
9169 ip->insn_opcode |= regno << OP_SH_CCC;
9173 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9184 while (ISDIGIT (*s));
9187 c = 8; /* Invalid sel value. */
9190 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9191 ip->insn_opcode |= c;
9195 /* Must be at least one digit. */
9196 my_getExpression (&imm_expr, s);
9197 check_absolute_expr (ip, &imm_expr);
9199 if ((unsigned long) imm_expr.X_add_number
9200 > (unsigned long) OP_MASK_VECBYTE)
9202 as_bad (_("bad byte vector index (%ld)"),
9203 (long) imm_expr.X_add_number);
9204 imm_expr.X_add_number = 0;
9207 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9208 imm_expr.X_op = O_absent;
9213 my_getExpression (&imm_expr, s);
9214 check_absolute_expr (ip, &imm_expr);
9216 if ((unsigned long) imm_expr.X_add_number
9217 > (unsigned long) OP_MASK_VECALIGN)
9219 as_bad (_("bad byte vector index (%ld)"),
9220 (long) imm_expr.X_add_number);
9221 imm_expr.X_add_number = 0;
9224 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9225 imm_expr.X_op = O_absent;
9230 as_bad (_("bad char = '%c'\n"), *args);
9235 /* Args don't match. */
9236 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9237 !strcmp (insn->name, insn[1].name))
9241 insn_error = _("illegal operands");
9246 insn_error = _("illegal operands");
9251 /* This routine assembles an instruction into its binary format when
9252 assembling for the mips16. As a side effect, it sets one of the
9253 global variables imm_reloc or offset_reloc to the type of
9254 relocation to do if one of the operands is an address expression.
9255 It also sets mips16_small and mips16_ext if the user explicitly
9256 requested a small or extended instruction. */
9259 mips16_ip (char *str, struct mips_cl_insn *ip)
9263 struct mips_opcode *insn;
9266 unsigned int lastregno = 0;
9271 mips16_small = FALSE;
9274 for (s = str; ISLOWER (*s); ++s)
9286 if (s[1] == 't' && s[2] == ' ')
9289 mips16_small = TRUE;
9293 else if (s[1] == 'e' && s[2] == ' ')
9302 insn_error = _("unknown opcode");
9306 if (mips_opts.noautoextend && ! mips16_ext)
9307 mips16_small = TRUE;
9309 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9311 insn_error = _("unrecognized opcode");
9318 assert (strcmp (insn->name, str) == 0);
9321 ip->insn_opcode = insn->match;
9322 ip->use_extend = FALSE;
9323 imm_expr.X_op = O_absent;
9324 imm_reloc[0] = BFD_RELOC_UNUSED;
9325 imm_reloc[1] = BFD_RELOC_UNUSED;
9326 imm_reloc[2] = BFD_RELOC_UNUSED;
9327 offset_expr.X_op = O_absent;
9328 offset_reloc[0] = BFD_RELOC_UNUSED;
9329 offset_reloc[1] = BFD_RELOC_UNUSED;
9330 offset_reloc[2] = BFD_RELOC_UNUSED;
9331 for (args = insn->args; 1; ++args)
9338 /* In this switch statement we call break if we did not find
9339 a match, continue if we did find a match, or return if we
9348 /* Stuff the immediate value in now, if we can. */
9349 if (imm_expr.X_op == O_constant
9350 && *imm_reloc > BFD_RELOC_UNUSED
9351 && insn->pinfo != INSN_MACRO)
9353 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9354 imm_expr.X_add_number, TRUE, mips16_small,
9355 mips16_ext, &ip->insn_opcode,
9356 &ip->use_extend, &ip->extend);
9357 imm_expr.X_op = O_absent;
9358 *imm_reloc = BFD_RELOC_UNUSED;
9372 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9375 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9391 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9393 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9420 while (ISDIGIT (*s));
9423 as_bad (_("invalid register number (%d)"), regno);
9429 if (s[1] == 'r' && s[2] == 'a')
9434 else if (s[1] == 'f' && s[2] == 'p')
9439 else if (s[1] == 's' && s[2] == 'p')
9444 else if (s[1] == 'g' && s[2] == 'p')
9449 else if (s[1] == 'a' && s[2] == 't')
9454 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9459 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9464 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9477 if (c == 'v' || c == 'w')
9479 regno = mips16_to_32_reg_map[lastregno];
9493 regno = mips32_to_16_reg_map[regno];
9498 regno = ILLEGAL_REG;
9503 regno = ILLEGAL_REG;
9508 regno = ILLEGAL_REG;
9513 if (regno == AT && ! mips_opts.noat)
9514 as_warn (_("used $at without \".set noat\""));
9521 if (regno == ILLEGAL_REG)
9528 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9532 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9535 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9538 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9544 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9547 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9548 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9558 if (strncmp (s, "$pc", 3) == 0)
9582 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9584 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9585 and generate the appropriate reloc. If the text
9586 inside %gprel is not a symbol name with an
9587 optional offset, then we generate a normal reloc
9588 and will probably fail later. */
9589 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9590 if (imm_expr.X_op == O_symbol)
9593 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9595 ip->use_extend = TRUE;
9602 /* Just pick up a normal expression. */
9603 my_getExpression (&imm_expr, s);
9606 if (imm_expr.X_op == O_register)
9608 /* What we thought was an expression turned out to
9611 if (s[0] == '(' && args[1] == '(')
9613 /* It looks like the expression was omitted
9614 before a register indirection, which means
9615 that the expression is implicitly zero. We
9616 still set up imm_expr, so that we handle
9617 explicit extensions correctly. */
9618 imm_expr.X_op = O_constant;
9619 imm_expr.X_add_number = 0;
9620 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9627 /* We need to relax this instruction. */
9628 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9637 /* We use offset_reloc rather than imm_reloc for the PC
9638 relative operands. This lets macros with both
9639 immediate and address operands work correctly. */
9640 my_getExpression (&offset_expr, s);
9642 if (offset_expr.X_op == O_register)
9645 /* We need to relax this instruction. */
9646 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9650 case '6': /* break code */
9651 my_getExpression (&imm_expr, s);
9652 check_absolute_expr (ip, &imm_expr);
9653 if ((unsigned long) imm_expr.X_add_number > 63)
9655 as_warn (_("Invalid value for `%s' (%lu)"),
9657 (unsigned long) imm_expr.X_add_number);
9658 imm_expr.X_add_number &= 0x3f;
9660 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9661 imm_expr.X_op = O_absent;
9665 case 'a': /* 26 bit address */
9666 my_getExpression (&offset_expr, s);
9668 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9669 ip->insn_opcode <<= 16;
9672 case 'l': /* register list for entry macro */
9673 case 'L': /* register list for exit macro */
9683 int freg, reg1, reg2;
9685 while (*s == ' ' || *s == ',')
9689 as_bad (_("can't parse register list"));
9701 while (ISDIGIT (*s))
9723 as_bad (_("invalid register list"));
9728 while (ISDIGIT (*s))
9735 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9740 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9745 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9746 mask |= (reg2 - 3) << 3;
9747 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9748 mask |= (reg2 - 15) << 1;
9749 else if (reg1 == RA && reg2 == RA)
9753 as_bad (_("invalid register list"));
9757 /* The mask is filled in in the opcode table for the
9758 benefit of the disassembler. We remove it before
9759 applying the actual mask. */
9760 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9761 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9765 case 'e': /* extend code */
9766 my_getExpression (&imm_expr, s);
9767 check_absolute_expr (ip, &imm_expr);
9768 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9770 as_warn (_("Invalid value for `%s' (%lu)"),
9772 (unsigned long) imm_expr.X_add_number);
9773 imm_expr.X_add_number &= 0x7ff;
9775 ip->insn_opcode |= imm_expr.X_add_number;
9776 imm_expr.X_op = O_absent;
9786 /* Args don't match. */
9787 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9788 strcmp (insn->name, insn[1].name) == 0)
9795 insn_error = _("illegal operands");
9801 /* This structure holds information we know about a mips16 immediate
9804 struct mips16_immed_operand
9806 /* The type code used in the argument string in the opcode table. */
9808 /* The number of bits in the short form of the opcode. */
9810 /* The number of bits in the extended form of the opcode. */
9812 /* The amount by which the short form is shifted when it is used;
9813 for example, the sw instruction has a shift count of 2. */
9815 /* The amount by which the short form is shifted when it is stored
9816 into the instruction code. */
9818 /* Non-zero if the short form is unsigned. */
9820 /* Non-zero if the extended form is unsigned. */
9822 /* Non-zero if the value is PC relative. */
9826 /* The mips16 immediate operand types. */
9828 static const struct mips16_immed_operand mips16_immed_operands[] =
9830 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9831 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9832 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9833 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9834 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9835 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9836 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9837 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9838 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9839 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9840 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9841 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9842 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9843 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9844 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9845 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9846 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9847 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9848 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9849 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9850 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9853 #define MIPS16_NUM_IMMED \
9854 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9856 /* Handle a mips16 instruction with an immediate value. This or's the
9857 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9858 whether an extended value is needed; if one is needed, it sets
9859 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9860 If SMALL is true, an unextended opcode was explicitly requested.
9861 If EXT is true, an extended opcode was explicitly requested. If
9862 WARN is true, warn if EXT does not match reality. */
9865 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9866 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9867 unsigned long *insn, bfd_boolean *use_extend,
9868 unsigned short *extend)
9870 register const struct mips16_immed_operand *op;
9871 int mintiny, maxtiny;
9872 bfd_boolean needext;
9874 op = mips16_immed_operands;
9875 while (op->type != type)
9878 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9883 if (type == '<' || type == '>' || type == '[' || type == ']')
9886 maxtiny = 1 << op->nbits;
9891 maxtiny = (1 << op->nbits) - 1;
9896 mintiny = - (1 << (op->nbits - 1));
9897 maxtiny = (1 << (op->nbits - 1)) - 1;
9900 /* Branch offsets have an implicit 0 in the lowest bit. */
9901 if (type == 'p' || type == 'q')
9904 if ((val & ((1 << op->shift) - 1)) != 0
9905 || val < (mintiny << op->shift)
9906 || val > (maxtiny << op->shift))
9911 if (warn && ext && ! needext)
9912 as_warn_where (file, line,
9913 _("extended operand requested but not required"));
9914 if (small && needext)
9915 as_bad_where (file, line, _("invalid unextended operand value"));
9917 if (small || (! ext && ! needext))
9921 *use_extend = FALSE;
9922 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9923 insnval <<= op->op_shift;
9928 long minext, maxext;
9934 maxext = (1 << op->extbits) - 1;
9938 minext = - (1 << (op->extbits - 1));
9939 maxext = (1 << (op->extbits - 1)) - 1;
9941 if (val < minext || val > maxext)
9942 as_bad_where (file, line,
9943 _("operand value out of range for instruction"));
9946 if (op->extbits == 16)
9948 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9951 else if (op->extbits == 15)
9953 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9958 extval = ((val & 0x1f) << 6) | (val & 0x20);
9962 *extend = (unsigned short) extval;
9967 static const struct percent_op_match
9970 bfd_reloc_code_real_type reloc;
9973 {"%lo", BFD_RELOC_LO16},
9975 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9976 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9977 {"%call16", BFD_RELOC_MIPS_CALL16},
9978 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9979 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9980 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9981 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9982 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9983 {"%got", BFD_RELOC_MIPS_GOT16},
9984 {"%gp_rel", BFD_RELOC_GPREL16},
9985 {"%half", BFD_RELOC_16},
9986 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9987 {"%higher", BFD_RELOC_MIPS_HIGHER},
9988 {"%neg", BFD_RELOC_MIPS_SUB},
9990 {"%hi", BFD_RELOC_HI16_S}
9994 /* Return true if *STR points to a relocation operator. When returning true,
9995 move *STR over the operator and store its relocation code in *RELOC.
9996 Leave both *STR and *RELOC alone when returning false. */
9999 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10003 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10004 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10006 *str += strlen (percent_op[i].str);
10007 *reloc = percent_op[i].reloc;
10009 /* Check whether the output BFD supports this relocation.
10010 If not, issue an error and fall back on something safe. */
10011 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10013 as_bad ("relocation %s isn't supported by the current ABI",
10014 percent_op[i].str);
10015 *reloc = BFD_RELOC_LO16;
10023 /* Parse string STR as a 16-bit relocatable operand. Store the
10024 expression in *EP and the relocations in the array starting
10025 at RELOC. Return the number of relocation operators used.
10027 On exit, EXPR_END points to the first character after the expression.
10028 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10031 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10034 bfd_reloc_code_real_type reversed_reloc[3];
10035 size_t reloc_index, i;
10036 int crux_depth, str_depth;
10039 /* Search for the start of the main expression, recoding relocations
10040 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10041 of the main expression and with CRUX_DEPTH containing the number
10042 of open brackets at that point. */
10049 crux_depth = str_depth;
10051 /* Skip over whitespace and brackets, keeping count of the number
10053 while (*str == ' ' || *str == '\t' || *str == '(')
10058 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10059 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10061 my_getExpression (ep, crux);
10064 /* Match every open bracket. */
10065 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10069 if (crux_depth > 0)
10070 as_bad ("unclosed '('");
10074 if (reloc_index == 0)
10075 reloc[0] = BFD_RELOC_LO16;
10078 prev_reloc_op_frag = frag_now;
10079 for (i = 0; i < reloc_index; i++)
10080 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10083 return reloc_index;
10087 my_getExpression (expressionS *ep, char *str)
10092 save_in = input_line_pointer;
10093 input_line_pointer = str;
10095 expr_end = input_line_pointer;
10096 input_line_pointer = save_in;
10098 /* If we are in mips16 mode, and this is an expression based on `.',
10099 then we bump the value of the symbol by 1 since that is how other
10100 text symbols are handled. We don't bother to handle complex
10101 expressions, just `.' plus or minus a constant. */
10102 if (mips_opts.mips16
10103 && ep->X_op == O_symbol
10104 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10105 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10106 && symbol_get_frag (ep->X_add_symbol) == frag_now
10107 && symbol_constant_p (ep->X_add_symbol)
10108 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10109 S_SET_VALUE (ep->X_add_symbol, val + 1);
10112 /* Turn a string in input_line_pointer into a floating point constant
10113 of type TYPE, and store the appropriate bytes in *LITP. The number
10114 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10115 returned, or NULL on OK. */
10118 md_atof (int type, char *litP, int *sizeP)
10121 LITTLENUM_TYPE words[4];
10137 return _("bad call to md_atof");
10140 t = atof_ieee (input_line_pointer, type, words);
10142 input_line_pointer = t;
10146 if (! target_big_endian)
10148 for (i = prec - 1; i >= 0; i--)
10150 md_number_to_chars (litP, words[i], 2);
10156 for (i = 0; i < prec; i++)
10158 md_number_to_chars (litP, words[i], 2);
10167 md_number_to_chars (char *buf, valueT val, int n)
10169 if (target_big_endian)
10170 number_to_chars_bigendian (buf, val, n);
10172 number_to_chars_littleendian (buf, val, n);
10176 static int support_64bit_objects(void)
10178 const char **list, **l;
10181 list = bfd_target_list ();
10182 for (l = list; *l != NULL; l++)
10184 /* This is traditional mips */
10185 if (strcmp (*l, "elf64-tradbigmips") == 0
10186 || strcmp (*l, "elf64-tradlittlemips") == 0)
10188 if (strcmp (*l, "elf64-bigmips") == 0
10189 || strcmp (*l, "elf64-littlemips") == 0)
10192 yes = (*l != NULL);
10196 #endif /* OBJ_ELF */
10198 const char *md_shortopts = "nO::g::G:";
10200 struct option md_longopts[] =
10202 /* Options which specify architecture. */
10203 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10204 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10205 {"march", required_argument, NULL, OPTION_MARCH},
10206 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10207 {"mtune", required_argument, NULL, OPTION_MTUNE},
10208 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10209 {"mips0", no_argument, NULL, OPTION_MIPS1},
10210 {"mips1", no_argument, NULL, OPTION_MIPS1},
10211 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10212 {"mips2", no_argument, NULL, OPTION_MIPS2},
10213 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10214 {"mips3", no_argument, NULL, OPTION_MIPS3},
10215 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10216 {"mips4", no_argument, NULL, OPTION_MIPS4},
10217 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10218 {"mips5", no_argument, NULL, OPTION_MIPS5},
10219 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10220 {"mips32", no_argument, NULL, OPTION_MIPS32},
10221 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10222 {"mips64", no_argument, NULL, OPTION_MIPS64},
10223 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10224 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10226 /* Options which specify Application Specific Extensions (ASEs). */
10227 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10)
10228 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10229 {"mips16", no_argument, NULL, OPTION_MIPS16},
10230 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10231 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10232 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10233 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10234 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10235 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10236 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10237 {"mdmx", no_argument, NULL, OPTION_MDMX},
10238 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10239 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10241 /* Old-style architecture options. Don't add more of these. */
10242 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10243 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10244 {"m4650", no_argument, NULL, OPTION_M4650},
10245 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10246 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10247 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10248 {"m4010", no_argument, NULL, OPTION_M4010},
10249 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10250 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10251 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10252 {"m4100", no_argument, NULL, OPTION_M4100},
10253 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10254 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10255 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10256 {"m3900", no_argument, NULL, OPTION_M3900},
10257 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10258 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10260 /* Options which enable bug fixes. */
10261 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10262 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10263 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10264 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10265 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10266 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10267 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10268 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10269 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10270 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10272 /* Miscellaneous options. */
10273 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10274 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10275 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10276 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10277 {"trap", no_argument, NULL, OPTION_TRAP},
10278 {"no-break", no_argument, NULL, OPTION_TRAP},
10279 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10280 {"break", no_argument, NULL, OPTION_BREAK},
10281 {"no-trap", no_argument, NULL, OPTION_BREAK},
10282 #define OPTION_EB (OPTION_MISC_BASE + 3)
10283 {"EB", no_argument, NULL, OPTION_EB},
10284 #define OPTION_EL (OPTION_MISC_BASE + 4)
10285 {"EL", no_argument, NULL, OPTION_EL},
10286 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10287 {"mfp32", no_argument, NULL, OPTION_FP32},
10288 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10289 {"mgp32", no_argument, NULL, OPTION_GP32},
10290 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10291 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10292 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10293 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10294 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10295 {"mfp64", no_argument, NULL, OPTION_FP64},
10296 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10297 {"mgp64", no_argument, NULL, OPTION_GP64},
10298 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10299 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10300 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10301 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10303 /* ELF-specific options. */
10305 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10306 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10307 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10308 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10309 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10310 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10311 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10312 {"xgot", no_argument, NULL, OPTION_XGOT},
10313 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10314 {"mabi", required_argument, NULL, OPTION_MABI},
10315 #define OPTION_32 (OPTION_ELF_BASE + 4)
10316 {"32", no_argument, NULL, OPTION_32},
10317 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10318 {"n32", no_argument, NULL, OPTION_N32},
10319 #define OPTION_64 (OPTION_ELF_BASE + 6)
10320 {"64", no_argument, NULL, OPTION_64},
10321 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10322 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10323 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10324 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10325 #endif /* OBJ_ELF */
10327 {NULL, no_argument, NULL, 0}
10329 size_t md_longopts_size = sizeof (md_longopts);
10331 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10332 NEW_VALUE. Warn if another value was already specified. Note:
10333 we have to defer parsing the -march and -mtune arguments in order
10334 to handle 'from-abi' correctly, since the ABI might be specified
10335 in a later argument. */
10338 mips_set_option_string (const char **string_ptr, const char *new_value)
10340 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10341 as_warn (_("A different %s was already specified, is now %s"),
10342 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10345 *string_ptr = new_value;
10349 md_parse_option (int c, char *arg)
10353 case OPTION_CONSTRUCT_FLOATS:
10354 mips_disable_float_construction = 0;
10357 case OPTION_NO_CONSTRUCT_FLOATS:
10358 mips_disable_float_construction = 1;
10370 target_big_endian = 1;
10374 target_big_endian = 0;
10382 if (arg && arg[1] == '0')
10392 mips_debug = atoi (arg);
10393 /* When the MIPS assembler sees -g or -g2, it does not do
10394 optimizations which limit full symbolic debugging. We take
10395 that to be equivalent to -O0. */
10396 if (mips_debug == 2)
10401 file_mips_isa = ISA_MIPS1;
10405 file_mips_isa = ISA_MIPS2;
10409 file_mips_isa = ISA_MIPS3;
10413 file_mips_isa = ISA_MIPS4;
10417 file_mips_isa = ISA_MIPS5;
10420 case OPTION_MIPS32:
10421 file_mips_isa = ISA_MIPS32;
10424 case OPTION_MIPS32R2:
10425 file_mips_isa = ISA_MIPS32R2;
10428 case OPTION_MIPS64:
10429 file_mips_isa = ISA_MIPS64;
10433 mips_set_option_string (&mips_tune_string, arg);
10437 mips_set_option_string (&mips_arch_string, arg);
10441 mips_set_option_string (&mips_arch_string, "4650");
10442 mips_set_option_string (&mips_tune_string, "4650");
10445 case OPTION_NO_M4650:
10449 mips_set_option_string (&mips_arch_string, "4010");
10450 mips_set_option_string (&mips_tune_string, "4010");
10453 case OPTION_NO_M4010:
10457 mips_set_option_string (&mips_arch_string, "4100");
10458 mips_set_option_string (&mips_tune_string, "4100");
10461 case OPTION_NO_M4100:
10465 mips_set_option_string (&mips_arch_string, "3900");
10466 mips_set_option_string (&mips_tune_string, "3900");
10469 case OPTION_NO_M3900:
10473 mips_opts.ase_mdmx = 1;
10476 case OPTION_NO_MDMX:
10477 mips_opts.ase_mdmx = 0;
10480 case OPTION_MIPS16:
10481 mips_opts.mips16 = 1;
10482 mips_no_prev_insn (FALSE);
10485 case OPTION_NO_MIPS16:
10486 mips_opts.mips16 = 0;
10487 mips_no_prev_insn (FALSE);
10490 case OPTION_MIPS3D:
10491 mips_opts.ase_mips3d = 1;
10494 case OPTION_NO_MIPS3D:
10495 mips_opts.ase_mips3d = 0;
10498 case OPTION_MEMBEDDED_PIC:
10499 mips_pic = EMBEDDED_PIC;
10500 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10502 as_bad (_("-G may not be used with embedded PIC code"));
10505 g_switch_value = 0x7fffffff;
10508 case OPTION_FIX_VR4122:
10509 mips_fix_4122_bugs = 1;
10512 case OPTION_NO_FIX_VR4122:
10513 mips_fix_4122_bugs = 0;
10516 case OPTION_RELAX_BRANCH:
10517 mips_relax_branch = 1;
10520 case OPTION_NO_RELAX_BRANCH:
10521 mips_relax_branch = 0;
10525 /* When generating ELF code, we permit -KPIC and -call_shared to
10526 select SVR4_PIC, and -non_shared to select no PIC. This is
10527 intended to be compatible with Irix 5. */
10528 case OPTION_CALL_SHARED:
10529 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10531 as_bad (_("-call_shared is supported only for ELF format"));
10534 mips_pic = SVR4_PIC;
10535 mips_abicalls = TRUE;
10536 if (g_switch_seen && g_switch_value != 0)
10538 as_bad (_("-G may not be used with SVR4 PIC code"));
10541 g_switch_value = 0;
10544 case OPTION_NON_SHARED:
10545 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10547 as_bad (_("-non_shared is supported only for ELF format"));
10551 mips_abicalls = FALSE;
10554 /* The -xgot option tells the assembler to use 32 offsets when
10555 accessing the got in SVR4_PIC mode. It is for Irix
10560 #endif /* OBJ_ELF */
10563 if (! USE_GLOBAL_POINTER_OPT)
10565 as_bad (_("-G is not supported for this configuration"));
10568 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10570 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10574 g_switch_value = atoi (arg);
10579 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10582 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10584 as_bad (_("-32 is supported for ELF format only"));
10587 mips_abi = O32_ABI;
10591 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10593 as_bad (_("-n32 is supported for ELF format only"));
10596 mips_abi = N32_ABI;
10600 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10602 as_bad (_("-64 is supported for ELF format only"));
10605 mips_abi = N64_ABI;
10606 if (! support_64bit_objects())
10607 as_fatal (_("No compiled in support for 64 bit object file format"));
10609 #endif /* OBJ_ELF */
10612 file_mips_gp32 = 1;
10616 file_mips_gp32 = 0;
10620 file_mips_fp32 = 1;
10624 file_mips_fp32 = 0;
10629 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10631 as_bad (_("-mabi is supported for ELF format only"));
10634 if (strcmp (arg, "32") == 0)
10635 mips_abi = O32_ABI;
10636 else if (strcmp (arg, "o64") == 0)
10637 mips_abi = O64_ABI;
10638 else if (strcmp (arg, "n32") == 0)
10639 mips_abi = N32_ABI;
10640 else if (strcmp (arg, "64") == 0)
10642 mips_abi = N64_ABI;
10643 if (! support_64bit_objects())
10644 as_fatal (_("No compiled in support for 64 bit object file "
10647 else if (strcmp (arg, "eabi") == 0)
10648 mips_abi = EABI_ABI;
10651 as_fatal (_("invalid abi -mabi=%s"), arg);
10655 #endif /* OBJ_ELF */
10657 case OPTION_M7000_HILO_FIX:
10658 mips_7000_hilo_fix = TRUE;
10661 case OPTION_MNO_7000_HILO_FIX:
10662 mips_7000_hilo_fix = FALSE;
10666 case OPTION_MDEBUG:
10667 mips_flag_mdebug = TRUE;
10670 case OPTION_NO_MDEBUG:
10671 mips_flag_mdebug = FALSE;
10673 #endif /* OBJ_ELF */
10682 /* Set up globals to generate code for the ISA or processor
10683 described by INFO. */
10686 mips_set_architecture (const struct mips_cpu_info *info)
10690 file_mips_arch = info->cpu;
10691 mips_opts.arch = info->cpu;
10692 mips_opts.isa = info->isa;
10697 /* Likewise for tuning. */
10700 mips_set_tune (const struct mips_cpu_info *info)
10703 mips_tune = info->cpu;
10708 mips_after_parse_args (void)
10710 const struct mips_cpu_info *arch_info = 0;
10711 const struct mips_cpu_info *tune_info = 0;
10713 /* GP relative stuff not working for PE */
10714 if (strncmp (TARGET_OS, "pe", 2) == 0
10715 && g_switch_value != 0)
10718 as_bad (_("-G not supported in this configuration."));
10719 g_switch_value = 0;
10722 if (mips_abi == NO_ABI)
10723 mips_abi = MIPS_DEFAULT_ABI;
10725 /* The following code determines the architecture and register size.
10726 Similar code was added to GCC 3.3 (see override_options() in
10727 config/mips/mips.c). The GAS and GCC code should be kept in sync
10728 as much as possible. */
10730 if (mips_arch_string != 0)
10731 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10733 if (file_mips_isa != ISA_UNKNOWN)
10735 /* Handle -mipsN. At this point, file_mips_isa contains the
10736 ISA level specified by -mipsN, while arch_info->isa contains
10737 the -march selection (if any). */
10738 if (arch_info != 0)
10740 /* -march takes precedence over -mipsN, since it is more descriptive.
10741 There's no harm in specifying both as long as the ISA levels
10743 if (file_mips_isa != arch_info->isa)
10744 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10745 mips_cpu_info_from_isa (file_mips_isa)->name,
10746 mips_cpu_info_from_isa (arch_info->isa)->name);
10749 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10752 if (arch_info == 0)
10753 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10755 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10756 as_bad ("-march=%s is not compatible with the selected ABI",
10759 mips_set_architecture (arch_info);
10761 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10762 if (mips_tune_string != 0)
10763 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10765 if (tune_info == 0)
10766 mips_set_tune (arch_info);
10768 mips_set_tune (tune_info);
10770 if (file_mips_gp32 >= 0)
10772 /* The user specified the size of the integer registers. Make sure
10773 it agrees with the ABI and ISA. */
10774 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10775 as_bad (_("-mgp64 used with a 32-bit processor"));
10776 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10777 as_bad (_("-mgp32 used with a 64-bit ABI"));
10778 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10779 as_bad (_("-mgp64 used with a 32-bit ABI"));
10783 /* Infer the integer register size from the ABI and processor.
10784 Restrict ourselves to 32-bit registers if that's all the
10785 processor has, or if the ABI cannot handle 64-bit registers. */
10786 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10787 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10790 /* ??? GAS treats single-float processors as though they had 64-bit
10791 float registers (although it complains when double-precision
10792 instructions are used). As things stand, saying they have 32-bit
10793 registers would lead to spurious "register must be even" messages.
10794 So here we assume float registers are always the same size as
10795 integer ones, unless the user says otherwise. */
10796 if (file_mips_fp32 < 0)
10797 file_mips_fp32 = file_mips_gp32;
10799 /* End of GCC-shared inference code. */
10801 /* This flag is set when we have a 64-bit capable CPU but use only
10802 32-bit wide registers. Note that EABI does not use it. */
10803 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10804 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10805 || mips_abi == O32_ABI))
10806 mips_32bitmode = 1;
10808 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10809 as_bad (_("trap exception not supported at ISA 1"));
10811 /* If the selected architecture includes support for ASEs, enable
10812 generation of code for them. */
10813 if (mips_opts.mips16 == -1)
10814 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10815 if (mips_opts.ase_mips3d == -1)
10816 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10817 if (mips_opts.ase_mdmx == -1)
10818 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10820 file_mips_isa = mips_opts.isa;
10821 file_ase_mips16 = mips_opts.mips16;
10822 file_ase_mips3d = mips_opts.ase_mips3d;
10823 file_ase_mdmx = mips_opts.ase_mdmx;
10824 mips_opts.gp32 = file_mips_gp32;
10825 mips_opts.fp32 = file_mips_fp32;
10827 if (mips_flag_mdebug < 0)
10829 #ifdef OBJ_MAYBE_ECOFF
10830 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10831 mips_flag_mdebug = 1;
10833 #endif /* OBJ_MAYBE_ECOFF */
10834 mips_flag_mdebug = 0;
10839 mips_init_after_args (void)
10841 /* initialize opcodes */
10842 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10843 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10847 md_pcrel_from (fixS *fixP)
10849 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10850 switch (fixP->fx_r_type)
10852 case BFD_RELOC_16_PCREL_S2:
10853 case BFD_RELOC_MIPS_JMP:
10854 /* Return the address of the delay slot. */
10861 /* This is called before the symbol table is processed. In order to
10862 work with gcc when using mips-tfile, we must keep all local labels.
10863 However, in other cases, we want to discard them. If we were
10864 called with -g, but we didn't see any debugging information, it may
10865 mean that gcc is smuggling debugging information through to
10866 mips-tfile, in which case we must generate all local labels. */
10869 mips_frob_file_before_adjust (void)
10871 #ifndef NO_ECOFF_DEBUGGING
10872 if (ECOFF_DEBUGGING
10874 && ! ecoff_debugging_seen)
10875 flag_keep_locals = 1;
10879 /* Sort any unmatched HI16_S relocs so that they immediately precede
10880 the corresponding LO reloc. This is called before md_apply_fix3 and
10881 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10882 explicit use of the %hi modifier. */
10885 mips_frob_file (void)
10887 struct mips_hi_fixup *l;
10889 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10891 segment_info_type *seginfo;
10894 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10896 /* If a GOT16 relocation turns out to be against a global symbol,
10897 there isn't supposed to be a matching LO. */
10898 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10899 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10902 /* Check quickly whether the next fixup happens to be a matching %lo. */
10903 if (fixup_has_matching_lo_p (l->fixp))
10906 /* Look through the fixups for this segment for a matching %lo.
10907 When we find one, move the %hi just in front of it. We do
10908 this in two passes. In the first pass, we try to find a
10909 unique %lo. In the second pass, we permit multiple %hi
10910 relocs for a single %lo (this is a GNU extension). */
10911 seginfo = seg_info (l->seg);
10912 for (pass = 0; pass < 2; pass++)
10917 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10919 /* Check whether this is a %lo fixup which matches l->fixp. */
10920 if (f->fx_r_type == BFD_RELOC_LO16
10921 && f->fx_addsy == l->fixp->fx_addsy
10922 && f->fx_offset == l->fixp->fx_offset
10925 || !reloc_needs_lo_p (prev->fx_r_type)
10926 || !fixup_has_matching_lo_p (prev)))
10930 /* Move l->fixp before f. */
10931 for (pf = &seginfo->fix_root;
10933 pf = &(*pf)->fx_next)
10934 assert (*pf != NULL);
10936 *pf = l->fixp->fx_next;
10938 l->fixp->fx_next = f;
10940 seginfo->fix_root = l->fixp;
10942 prev->fx_next = l->fixp;
10953 #if 0 /* GCC code motion plus incomplete dead code elimination
10954 can leave a %hi without a %lo. */
10956 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10957 _("Unmatched %%hi reloc"));
10963 /* When generating embedded PIC code we need to use a special
10964 relocation to represent the difference of two symbols in the .text
10965 section (switch tables use a difference of this sort). See
10966 include/coff/mips.h for details. This macro checks whether this
10967 fixup requires the special reloc. */
10968 #define SWITCH_TABLE(fixp) \
10969 ((fixp)->fx_r_type == BFD_RELOC_32 \
10970 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10971 && (fixp)->fx_addsy != NULL \
10972 && (fixp)->fx_subsy != NULL \
10973 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10974 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10976 /* When generating embedded PIC code we must keep all PC relative
10977 relocations, in case the linker has to relax a call. We also need
10978 to keep relocations for switch table entries.
10980 We may have combined relocations without symbols in the N32/N64 ABI.
10981 We have to prevent gas from dropping them. */
10984 mips_force_relocation (fixS *fixp)
10986 if (generic_force_reloc (fixp))
10990 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10991 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10992 || fixp->fx_r_type == BFD_RELOC_HI16_S
10993 || fixp->fx_r_type == BFD_RELOC_LO16))
10996 return (mips_pic == EMBEDDED_PIC
10998 || SWITCH_TABLE (fixp)
10999 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11000 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11003 /* This hook is called before a fix is simplified. We don't really
11004 decide whether to skip a fix here. Rather, we turn global symbols
11005 used as branch targets into local symbols, such that they undergo
11006 simplification. We can only do this if the symbol is defined and
11007 it is in the same section as the branch. If this doesn't hold, we
11008 emit a better error message than just saying the relocation is not
11009 valid for the selected object format.
11011 FIXP is the fix-up we're going to try to simplify, SEG is the
11012 segment in which the fix up occurs. The return value should be
11013 non-zero to indicate the fix-up is valid for further
11014 simplifications. */
11017 mips_validate_fix (struct fix *fixP, asection *seg)
11019 /* There's a lot of discussion on whether it should be possible to
11020 use R_MIPS_PC16 to represent branch relocations. The outcome
11021 seems to be that it can, but gas/bfd are very broken in creating
11022 RELA relocations for this, so for now we only accept branches to
11023 symbols in the same section. Anything else is of dubious value,
11024 since there's no guarantee that at link time the symbol would be
11025 in range. Even for branches to local symbols this is arguably
11026 wrong, since it we assume the symbol is not going to be
11027 overridden, which should be possible per ELF library semantics,
11028 but then, there isn't a dynamic relocation that could be used to
11029 this effect, and the target would likely be out of range as well.
11031 Unfortunately, it seems that there is too much code out there
11032 that relies on branches to symbols that are global to be resolved
11033 as if they were local, like the IRIX tools do, so we do it as
11034 well, but with a warning so that people are reminded to fix their
11035 code. If we ever get back to using R_MIPS_PC16 for branch
11036 targets, this entire block should go away (and probably the
11037 whole function). */
11039 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11040 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11041 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11042 && mips_pic != EMBEDDED_PIC)
11043 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11046 if (! S_IS_DEFINED (fixP->fx_addsy))
11048 as_bad_where (fixP->fx_file, fixP->fx_line,
11049 _("Cannot branch to undefined symbol."));
11050 /* Avoid any further errors about this fixup. */
11053 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11055 as_bad_where (fixP->fx_file, fixP->fx_line,
11056 _("Cannot branch to symbol in another section."));
11059 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11061 symbolS *sym = fixP->fx_addsy;
11063 if (mips_pic == SVR4_PIC)
11064 as_warn_where (fixP->fx_file, fixP->fx_line,
11065 _("Pretending global symbol used as branch target is local."));
11067 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11068 S_GET_SEGMENT (sym),
11070 symbol_get_frag (sym));
11071 copy_symbol_attributes (fixP->fx_addsy, sym);
11072 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11073 assert (symbol_resolved_p (sym));
11074 symbol_mark_resolved (fixP->fx_addsy);
11083 mips_need_elf_addend_fixup (fixS *fixP)
11085 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
11087 if (mips_pic == EMBEDDED_PIC
11088 && S_IS_WEAK (fixP->fx_addsy))
11090 if (mips_pic != EMBEDDED_PIC
11091 && (S_IS_WEAK (fixP->fx_addsy)
11092 || S_IS_EXTERNAL (fixP->fx_addsy))
11093 && !S_IS_COMMON (fixP->fx_addsy))
11095 if (((bfd_get_section_flags (stdoutput,
11096 S_GET_SEGMENT (fixP->fx_addsy))
11097 & (SEC_LINK_ONCE | SEC_MERGE)) != 0)
11098 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
11100 sizeof (".gnu.linkonce") - 1))
11106 /* Apply a fixup to the object file. */
11109 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11113 static int previous_fx_r_type = 0;
11114 reloc_howto_type *howto;
11116 /* We ignore generic BFD relocations we don't know about. */
11117 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11121 assert (fixP->fx_size == 4
11122 || fixP->fx_r_type == BFD_RELOC_16
11123 || fixP->fx_r_type == BFD_RELOC_64
11124 || fixP->fx_r_type == BFD_RELOC_CTOR
11125 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11126 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11127 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11129 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11131 /* If we aren't adjusting this fixup to be against the section
11132 symbol, we need to adjust the value. */
11134 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
11136 if (mips_need_elf_addend_fixup (fixP)
11137 && howto->partial_inplace
11138 && fixP->fx_r_type != BFD_RELOC_GPREL16
11139 && fixP->fx_r_type != BFD_RELOC_GPREL32
11140 && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL)
11142 /* In this case, the bfd_install_relocation routine will
11143 incorrectly add the symbol value back in. We just want
11144 the addend to appear in the object file.
11146 The condition above used to include
11147 "&& (! fixP->fx_pcrel || howto->pcrel_offset)".
11149 However, howto can't be trusted here, because we
11150 might change the reloc type in tc_gen_reloc. We can
11151 check howto->partial_inplace because that conversion
11152 happens to preserve howto->partial_inplace; but it
11153 does not preserve howto->pcrel_offset. I've just
11154 eliminated the check, because all MIPS PC-relative
11155 relocations are marked howto->pcrel_offset.
11157 howto->pcrel_offset was originally added for
11158 R_MIPS_PC16, which is generated for code like
11167 *valP -= S_GET_VALUE (fixP->fx_addsy);
11170 /* This code was generated using trial and error and so is
11171 fragile and not trustworthy. If you change it, you should
11172 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11173 they still pass. */
11174 if (fixP->fx_pcrel)
11176 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11178 /* BFD's REL handling, for MIPS, is _very_ weird.
11179 This gives the right results, but it can't possibly
11180 be the way things are supposed to work. */
11181 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11186 /* We are not done if this is a composite relocation to set up gp. */
11187 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11188 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11189 || (fixP->fx_r_type == BFD_RELOC_64
11190 && (previous_fx_r_type == BFD_RELOC_GPREL32
11191 || previous_fx_r_type == BFD_RELOC_GPREL16))
11192 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11193 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11194 || fixP->fx_r_type == BFD_RELOC_LO16))))
11196 previous_fx_r_type = fixP->fx_r_type;
11198 switch (fixP->fx_r_type)
11200 case BFD_RELOC_MIPS_JMP:
11201 case BFD_RELOC_MIPS_SHIFT5:
11202 case BFD_RELOC_MIPS_SHIFT6:
11203 case BFD_RELOC_MIPS_GOT_DISP:
11204 case BFD_RELOC_MIPS_GOT_PAGE:
11205 case BFD_RELOC_MIPS_GOT_OFST:
11206 case BFD_RELOC_MIPS_SUB:
11207 case BFD_RELOC_MIPS_INSERT_A:
11208 case BFD_RELOC_MIPS_INSERT_B:
11209 case BFD_RELOC_MIPS_DELETE:
11210 case BFD_RELOC_MIPS_HIGHEST:
11211 case BFD_RELOC_MIPS_HIGHER:
11212 case BFD_RELOC_MIPS_SCN_DISP:
11213 case BFD_RELOC_MIPS_REL16:
11214 case BFD_RELOC_MIPS_RELGOT:
11215 case BFD_RELOC_MIPS_JALR:
11216 case BFD_RELOC_HI16:
11217 case BFD_RELOC_HI16_S:
11218 case BFD_RELOC_GPREL16:
11219 case BFD_RELOC_MIPS_LITERAL:
11220 case BFD_RELOC_MIPS_CALL16:
11221 case BFD_RELOC_MIPS_GOT16:
11222 case BFD_RELOC_GPREL32:
11223 case BFD_RELOC_MIPS_GOT_HI16:
11224 case BFD_RELOC_MIPS_GOT_LO16:
11225 case BFD_RELOC_MIPS_CALL_HI16:
11226 case BFD_RELOC_MIPS_CALL_LO16:
11227 case BFD_RELOC_MIPS16_GPREL:
11228 if (fixP->fx_pcrel)
11229 as_bad_where (fixP->fx_file, fixP->fx_line,
11230 _("Invalid PC relative reloc"));
11231 /* Nothing needed to do. The value comes from the reloc entry */
11234 case BFD_RELOC_MIPS16_JMP:
11235 /* We currently always generate a reloc against a symbol, which
11236 means that we don't want an addend even if the symbol is
11241 case BFD_RELOC_PCREL_HI16_S:
11242 /* The addend for this is tricky if it is internal, so we just
11243 do everything here rather than in bfd_install_relocation. */
11244 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11247 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11249 /* For an external symbol adjust by the address to make it
11250 pcrel_offset. We use the address of the RELLO reloc
11251 which follows this one. */
11252 *valP += (fixP->fx_next->fx_frag->fr_address
11253 + fixP->fx_next->fx_where);
11255 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11256 if (target_big_endian)
11258 md_number_to_chars (buf, *valP, 2);
11261 case BFD_RELOC_PCREL_LO16:
11262 /* The addend for this is tricky if it is internal, so we just
11263 do everything here rather than in bfd_install_relocation. */
11264 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11267 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11268 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11269 if (target_big_endian)
11271 md_number_to_chars (buf, *valP, 2);
11275 /* This is handled like BFD_RELOC_32, but we output a sign
11276 extended value if we are only 32 bits. */
11278 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11280 if (8 <= sizeof (valueT))
11281 md_number_to_chars (buf, *valP, 8);
11286 if ((*valP & 0x80000000) != 0)
11290 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11292 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11298 case BFD_RELOC_RVA:
11300 /* If we are deleting this reloc entry, we must fill in the
11301 value now. This can happen if we have a .word which is not
11302 resolved when it appears but is later defined. We also need
11303 to fill in the value if this is an embedded PIC switch table
11306 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11307 md_number_to_chars (buf, *valP, 4);
11311 /* If we are deleting this reloc entry, we must fill in the
11313 assert (fixP->fx_size == 2);
11315 md_number_to_chars (buf, *valP, 2);
11318 case BFD_RELOC_LO16:
11319 /* When handling an embedded PIC switch statement, we can wind
11320 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11323 if (*valP + 0x8000 > 0xffff)
11324 as_bad_where (fixP->fx_file, fixP->fx_line,
11325 _("relocation overflow"));
11326 if (target_big_endian)
11328 md_number_to_chars (buf, *valP, 2);
11332 case BFD_RELOC_16_PCREL_S2:
11333 if ((*valP & 0x3) != 0)
11334 as_bad_where (fixP->fx_file, fixP->fx_line,
11335 _("Branch to odd address (%lx)"), (long) *valP);
11338 * We need to save the bits in the instruction since fixup_segment()
11339 * might be deleting the relocation entry (i.e., a branch within
11340 * the current segment).
11342 if (! fixP->fx_done)
11345 /* update old instruction data */
11346 if (target_big_endian)
11347 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11349 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11351 if (*valP + 0x20000 <= 0x3ffff)
11353 insn |= (*valP >> 2) & 0xffff;
11354 md_number_to_chars (buf, insn, 4);
11356 else if (mips_pic == NO_PIC
11358 && fixP->fx_frag->fr_address >= text_section->vma
11359 && (fixP->fx_frag->fr_address
11360 < text_section->vma + text_section->_raw_size)
11361 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11362 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11363 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11365 /* The branch offset is too large. If this is an
11366 unconditional branch, and we are not generating PIC code,
11367 we can convert it to an absolute jump instruction. */
11368 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11369 insn = 0x0c000000; /* jal */
11371 insn = 0x08000000; /* j */
11372 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11374 fixP->fx_addsy = section_symbol (text_section);
11375 *valP += md_pcrel_from (fixP);
11376 md_number_to_chars (buf, insn, 4);
11380 /* If we got here, we have branch-relaxation disabled,
11381 and there's nothing we can do to fix this instruction
11382 without turning it into a longer sequence. */
11383 as_bad_where (fixP->fx_file, fixP->fx_line,
11384 _("Branch out of range"));
11388 case BFD_RELOC_VTABLE_INHERIT:
11391 && !S_IS_DEFINED (fixP->fx_addsy)
11392 && !S_IS_WEAK (fixP->fx_addsy))
11393 S_SET_WEAK (fixP->fx_addsy);
11396 case BFD_RELOC_VTABLE_ENTRY:
11404 /* Remember value for tc_gen_reloc. */
11405 fixP->fx_addnumber = *valP;
11410 printInsn (unsigned long oc)
11412 const struct mips_opcode *p;
11413 int treg, sreg, dreg, shamt;
11418 for (i = 0; i < NUMOPCODES; ++i)
11420 p = &mips_opcodes[i];
11421 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11423 printf ("%08lx %s\t", oc, p->name);
11424 treg = (oc >> 16) & 0x1f;
11425 sreg = (oc >> 21) & 0x1f;
11426 dreg = (oc >> 11) & 0x1f;
11427 shamt = (oc >> 6) & 0x1f;
11429 for (args = p->args;; ++args)
11440 printf ("%c", *args);
11444 assert (treg == sreg);
11445 printf ("$%d,$%d", treg, sreg);
11450 printf ("$%d", dreg);
11455 printf ("$%d", treg);
11459 printf ("0x%x", treg);
11464 printf ("$%d", sreg);
11468 printf ("0x%08lx", oc & 0x1ffffff);
11475 printf ("%d", imm);
11480 printf ("$%d", shamt);
11491 printf (_("%08lx UNDEFINED\n"), oc);
11502 name = input_line_pointer;
11503 c = get_symbol_end ();
11504 p = (symbolS *) symbol_find_or_make (name);
11505 *input_line_pointer = c;
11509 /* Align the current frag to a given power of two. The MIPS assembler
11510 also automatically adjusts any preceding label. */
11513 mips_align (int to, int fill, symbolS *label)
11515 mips_emit_delays (FALSE);
11516 frag_align (to, fill, 0);
11517 record_alignment (now_seg, to);
11520 assert (S_GET_SEGMENT (label) == now_seg);
11521 symbol_set_frag (label, frag_now);
11522 S_SET_VALUE (label, (valueT) frag_now_fix ());
11526 /* Align to a given power of two. .align 0 turns off the automatic
11527 alignment used by the data creating pseudo-ops. */
11530 s_align (int x ATTRIBUTE_UNUSED)
11533 register long temp_fill;
11534 long max_alignment = 15;
11538 o Note that the assembler pulls down any immediately preceeding label
11539 to the aligned address.
11540 o It's not documented but auto alignment is reinstated by
11541 a .align pseudo instruction.
11542 o Note also that after auto alignment is turned off the mips assembler
11543 issues an error on attempt to assemble an improperly aligned data item.
11548 temp = get_absolute_expression ();
11549 if (temp > max_alignment)
11550 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11553 as_warn (_("Alignment negative: 0 assumed."));
11556 if (*input_line_pointer == ',')
11558 ++input_line_pointer;
11559 temp_fill = get_absolute_expression ();
11566 mips_align (temp, (int) temp_fill,
11567 insn_labels != NULL ? insn_labels->label : NULL);
11574 demand_empty_rest_of_line ();
11578 mips_flush_pending_output (void)
11580 mips_emit_delays (FALSE);
11581 mips_clear_insn_labels ();
11585 s_change_sec (int sec)
11589 /* When generating embedded PIC code, we only use the .text, .lit8,
11590 .sdata and .sbss sections. We change the .data and .rdata
11591 pseudo-ops to use .sdata. */
11592 if (mips_pic == EMBEDDED_PIC
11593 && (sec == 'd' || sec == 'r'))
11597 /* The ELF backend needs to know that we are changing sections, so
11598 that .previous works correctly. We could do something like check
11599 for an obj_section_change_hook macro, but that might be confusing
11600 as it would not be appropriate to use it in the section changing
11601 functions in read.c, since obj-elf.c intercepts those. FIXME:
11602 This should be cleaner, somehow. */
11603 obj_elf_section_change_hook ();
11606 mips_emit_delays (FALSE);
11616 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11617 demand_empty_rest_of_line ();
11621 if (USE_GLOBAL_POINTER_OPT)
11623 seg = subseg_new (RDATA_SECTION_NAME,
11624 (subsegT) get_absolute_expression ());
11625 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11627 bfd_set_section_flags (stdoutput, seg,
11633 if (strcmp (TARGET_OS, "elf") != 0)
11634 record_alignment (seg, 4);
11636 demand_empty_rest_of_line ();
11640 as_bad (_("No read only data section in this object file format"));
11641 demand_empty_rest_of_line ();
11647 if (USE_GLOBAL_POINTER_OPT)
11649 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11650 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11652 bfd_set_section_flags (stdoutput, seg,
11653 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11655 if (strcmp (TARGET_OS, "elf") != 0)
11656 record_alignment (seg, 4);
11658 demand_empty_rest_of_line ();
11663 as_bad (_("Global pointers not supported; recompile -G 0"));
11664 demand_empty_rest_of_line ();
11673 s_change_section (int ignore ATTRIBUTE_UNUSED)
11676 char *section_name;
11681 int section_entry_size;
11682 int section_alignment;
11684 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11687 section_name = input_line_pointer;
11688 c = get_symbol_end ();
11690 next_c = *(input_line_pointer + 1);
11692 /* Do we have .section Name<,"flags">? */
11693 if (c != ',' || (c == ',' && next_c == '"'))
11695 /* just after name is now '\0'. */
11696 *input_line_pointer = c;
11697 input_line_pointer = section_name;
11698 obj_elf_section (ignore);
11701 input_line_pointer++;
11703 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11705 section_type = get_absolute_expression ();
11708 if (*input_line_pointer++ == ',')
11709 section_flag = get_absolute_expression ();
11712 if (*input_line_pointer++ == ',')
11713 section_entry_size = get_absolute_expression ();
11715 section_entry_size = 0;
11716 if (*input_line_pointer++ == ',')
11717 section_alignment = get_absolute_expression ();
11719 section_alignment = 0;
11721 section_name = xstrdup (section_name);
11723 obj_elf_change_section (section_name, section_type, section_flag,
11724 section_entry_size, 0, 0, 0);
11726 if (now_seg->name != section_name)
11727 free (section_name);
11728 #endif /* OBJ_ELF */
11732 mips_enable_auto_align (void)
11738 s_cons (int log_size)
11742 label = insn_labels != NULL ? insn_labels->label : NULL;
11743 mips_emit_delays (FALSE);
11744 if (log_size > 0 && auto_align)
11745 mips_align (log_size, 0, label);
11746 mips_clear_insn_labels ();
11747 cons (1 << log_size);
11751 s_float_cons (int type)
11755 label = insn_labels != NULL ? insn_labels->label : NULL;
11757 mips_emit_delays (FALSE);
11762 mips_align (3, 0, label);
11764 mips_align (2, 0, label);
11767 mips_clear_insn_labels ();
11772 /* Handle .globl. We need to override it because on Irix 5 you are
11775 where foo is an undefined symbol, to mean that foo should be
11776 considered to be the address of a function. */
11779 s_mips_globl (int x ATTRIBUTE_UNUSED)
11786 name = input_line_pointer;
11787 c = get_symbol_end ();
11788 symbolP = symbol_find_or_make (name);
11789 *input_line_pointer = c;
11790 SKIP_WHITESPACE ();
11792 /* On Irix 5, every global symbol that is not explicitly labelled as
11793 being a function is apparently labelled as being an object. */
11796 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11801 secname = input_line_pointer;
11802 c = get_symbol_end ();
11803 sec = bfd_get_section_by_name (stdoutput, secname);
11805 as_bad (_("%s: no such section"), secname);
11806 *input_line_pointer = c;
11808 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11809 flag = BSF_FUNCTION;
11812 symbol_get_bfdsym (symbolP)->flags |= flag;
11814 S_SET_EXTERNAL (symbolP);
11815 demand_empty_rest_of_line ();
11819 s_option (int x ATTRIBUTE_UNUSED)
11824 opt = input_line_pointer;
11825 c = get_symbol_end ();
11829 /* FIXME: What does this mean? */
11831 else if (strncmp (opt, "pic", 3) == 0)
11835 i = atoi (opt + 3);
11840 mips_pic = SVR4_PIC;
11841 mips_abicalls = TRUE;
11844 as_bad (_(".option pic%d not supported"), i);
11846 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11848 if (g_switch_seen && g_switch_value != 0)
11849 as_warn (_("-G may not be used with SVR4 PIC code"));
11850 g_switch_value = 0;
11851 bfd_set_gp_size (stdoutput, 0);
11855 as_warn (_("Unrecognized option \"%s\""), opt);
11857 *input_line_pointer = c;
11858 demand_empty_rest_of_line ();
11861 /* This structure is used to hold a stack of .set values. */
11863 struct mips_option_stack
11865 struct mips_option_stack *next;
11866 struct mips_set_options options;
11869 static struct mips_option_stack *mips_opts_stack;
11871 /* Handle the .set pseudo-op. */
11874 s_mipsset (int x ATTRIBUTE_UNUSED)
11876 char *name = input_line_pointer, ch;
11878 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11879 ++input_line_pointer;
11880 ch = *input_line_pointer;
11881 *input_line_pointer = '\0';
11883 if (strcmp (name, "reorder") == 0)
11885 if (mips_opts.noreorder && prev_nop_frag != NULL)
11887 /* If we still have pending nops, we can discard them. The
11888 usual nop handling will insert any that are still
11890 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11891 * (mips_opts.mips16 ? 2 : 4));
11892 prev_nop_frag = NULL;
11894 mips_opts.noreorder = 0;
11896 else if (strcmp (name, "noreorder") == 0)
11898 mips_emit_delays (TRUE);
11899 mips_opts.noreorder = 1;
11900 mips_any_noreorder = 1;
11902 else if (strcmp (name, "at") == 0)
11904 mips_opts.noat = 0;
11906 else if (strcmp (name, "noat") == 0)
11908 mips_opts.noat = 1;
11910 else if (strcmp (name, "macro") == 0)
11912 mips_opts.warn_about_macros = 0;
11914 else if (strcmp (name, "nomacro") == 0)
11916 if (mips_opts.noreorder == 0)
11917 as_bad (_("`noreorder' must be set before `nomacro'"));
11918 mips_opts.warn_about_macros = 1;
11920 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11922 mips_opts.nomove = 0;
11924 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11926 mips_opts.nomove = 1;
11928 else if (strcmp (name, "bopt") == 0)
11930 mips_opts.nobopt = 0;
11932 else if (strcmp (name, "nobopt") == 0)
11934 mips_opts.nobopt = 1;
11936 else if (strcmp (name, "mips16") == 0
11937 || strcmp (name, "MIPS-16") == 0)
11938 mips_opts.mips16 = 1;
11939 else if (strcmp (name, "nomips16") == 0
11940 || strcmp (name, "noMIPS-16") == 0)
11941 mips_opts.mips16 = 0;
11942 else if (strcmp (name, "mips3d") == 0)
11943 mips_opts.ase_mips3d = 1;
11944 else if (strcmp (name, "nomips3d") == 0)
11945 mips_opts.ase_mips3d = 0;
11946 else if (strcmp (name, "mdmx") == 0)
11947 mips_opts.ase_mdmx = 1;
11948 else if (strcmp (name, "nomdmx") == 0)
11949 mips_opts.ase_mdmx = 0;
11950 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11954 /* Permit the user to change the ISA and architecture on the fly.
11955 Needless to say, misuse can cause serious problems. */
11956 if (strcmp (name, "mips0") == 0)
11959 mips_opts.isa = file_mips_isa;
11961 else if (strcmp (name, "mips1") == 0)
11962 mips_opts.isa = ISA_MIPS1;
11963 else if (strcmp (name, "mips2") == 0)
11964 mips_opts.isa = ISA_MIPS2;
11965 else if (strcmp (name, "mips3") == 0)
11966 mips_opts.isa = ISA_MIPS3;
11967 else if (strcmp (name, "mips4") == 0)
11968 mips_opts.isa = ISA_MIPS4;
11969 else if (strcmp (name, "mips5") == 0)
11970 mips_opts.isa = ISA_MIPS5;
11971 else if (strcmp (name, "mips32") == 0)
11972 mips_opts.isa = ISA_MIPS32;
11973 else if (strcmp (name, "mips32r2") == 0)
11974 mips_opts.isa = ISA_MIPS32R2;
11975 else if (strcmp (name, "mips64") == 0)
11976 mips_opts.isa = ISA_MIPS64;
11977 else if (strcmp (name, "arch=default") == 0)
11980 mips_opts.arch = file_mips_arch;
11981 mips_opts.isa = file_mips_isa;
11983 else if (strncmp (name, "arch=", 5) == 0)
11985 const struct mips_cpu_info *p;
11987 p = mips_parse_cpu("internal use", name + 5);
11989 as_bad (_("unknown architecture %s"), name + 5);
11992 mips_opts.arch = p->cpu;
11993 mips_opts.isa = p->isa;
11997 as_bad (_("unknown ISA level %s"), name + 4);
11999 switch (mips_opts.isa)
12007 mips_opts.gp32 = 1;
12008 mips_opts.fp32 = 1;
12014 mips_opts.gp32 = 0;
12015 mips_opts.fp32 = 0;
12018 as_bad (_("unknown ISA level %s"), name + 4);
12023 mips_opts.gp32 = file_mips_gp32;
12024 mips_opts.fp32 = file_mips_fp32;
12027 else if (strcmp (name, "autoextend") == 0)
12028 mips_opts.noautoextend = 0;
12029 else if (strcmp (name, "noautoextend") == 0)
12030 mips_opts.noautoextend = 1;
12031 else if (strcmp (name, "push") == 0)
12033 struct mips_option_stack *s;
12035 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12036 s->next = mips_opts_stack;
12037 s->options = mips_opts;
12038 mips_opts_stack = s;
12040 else if (strcmp (name, "pop") == 0)
12042 struct mips_option_stack *s;
12044 s = mips_opts_stack;
12046 as_bad (_(".set pop with no .set push"));
12049 /* If we're changing the reorder mode we need to handle
12050 delay slots correctly. */
12051 if (s->options.noreorder && ! mips_opts.noreorder)
12052 mips_emit_delays (TRUE);
12053 else if (! s->options.noreorder && mips_opts.noreorder)
12055 if (prev_nop_frag != NULL)
12057 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12058 * (mips_opts.mips16 ? 2 : 4));
12059 prev_nop_frag = NULL;
12063 mips_opts = s->options;
12064 mips_opts_stack = s->next;
12070 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12072 *input_line_pointer = ch;
12073 demand_empty_rest_of_line ();
12076 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12077 .option pic2. It means to generate SVR4 PIC calls. */
12080 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12082 mips_pic = SVR4_PIC;
12083 mips_abicalls = TRUE;
12084 if (USE_GLOBAL_POINTER_OPT)
12086 if (g_switch_seen && g_switch_value != 0)
12087 as_warn (_("-G may not be used with SVR4 PIC code"));
12088 g_switch_value = 0;
12090 bfd_set_gp_size (stdoutput, 0);
12091 demand_empty_rest_of_line ();
12094 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12095 PIC code. It sets the $gp register for the function based on the
12096 function address, which is in the register named in the argument.
12097 This uses a relocation against _gp_disp, which is handled specially
12098 by the linker. The result is:
12099 lui $gp,%hi(_gp_disp)
12100 addiu $gp,$gp,%lo(_gp_disp)
12101 addu $gp,$gp,.cpload argument
12102 The .cpload argument is normally $25 == $t9. */
12105 s_cpload (int ignore ATTRIBUTE_UNUSED)
12110 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12111 .cpload is ignored. */
12112 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12118 /* .cpload should be in a .set noreorder section. */
12119 if (mips_opts.noreorder == 0)
12120 as_warn (_(".cpload not in noreorder section"));
12122 ex.X_op = O_symbol;
12123 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12124 ex.X_op_symbol = NULL;
12125 ex.X_add_number = 0;
12127 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12128 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12130 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12131 macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
12132 mips_gp_register, BFD_RELOC_LO16);
12134 macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
12135 mips_gp_register, tc_get_register (0));
12137 demand_empty_rest_of_line ();
12140 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12141 .cpsetup $reg1, offset|$reg2, label
12143 If offset is given, this results in:
12144 sd $gp, offset($sp)
12145 lui $gp, %hi(%neg(%gp_rel(label)))
12146 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12147 daddu $gp, $gp, $reg1
12149 If $reg2 is given, this results in:
12150 daddu $reg2, $gp, $0
12151 lui $gp, %hi(%neg(%gp_rel(label)))
12152 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12153 daddu $gp, $gp, $reg1
12154 $reg1 is normally $25 == $t9. */
12156 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12158 expressionS ex_off;
12159 expressionS ex_sym;
12164 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12165 We also need NewABI support. */
12166 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12172 reg1 = tc_get_register (0);
12173 SKIP_WHITESPACE ();
12174 if (*input_line_pointer != ',')
12176 as_bad (_("missing argument separator ',' for .cpsetup"));
12180 ++input_line_pointer;
12181 SKIP_WHITESPACE ();
12182 if (*input_line_pointer == '$')
12184 mips_cpreturn_register = tc_get_register (0);
12185 mips_cpreturn_offset = -1;
12189 mips_cpreturn_offset = get_absolute_expression ();
12190 mips_cpreturn_register = -1;
12192 SKIP_WHITESPACE ();
12193 if (*input_line_pointer != ',')
12195 as_bad (_("missing argument separator ',' for .cpsetup"));
12199 ++input_line_pointer;
12200 SKIP_WHITESPACE ();
12201 expression (&ex_sym);
12203 if (mips_cpreturn_register == -1)
12205 ex_off.X_op = O_constant;
12206 ex_off.X_add_symbol = NULL;
12207 ex_off.X_op_symbol = NULL;
12208 ex_off.X_add_number = mips_cpreturn_offset;
12210 macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
12211 BFD_RELOC_LO16, SP);
12214 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
12215 mips_gp_register, 0);
12217 /* Ensure there's room for the next two instructions, so that `f'
12218 doesn't end up with an address in the wrong frag. */
12221 macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12222 BFD_RELOC_GPREL16);
12223 fix_new (frag_now, f - frag_now->fr_literal,
12224 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12225 fix_new (frag_now, f - frag_now->fr_literal,
12226 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12229 macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
12230 mips_gp_register, BFD_RELOC_GPREL16);
12231 fix_new (frag_now, f - frag_now->fr_literal,
12232 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12233 fix_new (frag_now, f - frag_now->fr_literal,
12234 4, NULL, 0, 0, BFD_RELOC_LO16);
12236 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12237 mips_gp_register, reg1);
12239 demand_empty_rest_of_line ();
12243 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12245 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12246 .cplocal is ignored. */
12247 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12253 mips_gp_register = tc_get_register (0);
12254 demand_empty_rest_of_line ();
12257 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12258 offset from $sp. The offset is remembered, and after making a PIC
12259 call $gp is restored from that location. */
12262 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12267 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12268 .cprestore is ignored. */
12269 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12275 mips_cprestore_offset = get_absolute_expression ();
12276 mips_cprestore_valid = 1;
12278 ex.X_op = O_constant;
12279 ex.X_add_symbol = NULL;
12280 ex.X_op_symbol = NULL;
12281 ex.X_add_number = mips_cprestore_offset;
12283 macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
12284 mips_gp_register, SP);
12286 demand_empty_rest_of_line ();
12289 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12290 was given in the preceeding .gpsetup, it results in:
12291 ld $gp, offset($sp)
12293 If a register $reg2 was given there, it results in:
12294 daddiu $gp, $gp, $reg2
12297 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12302 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12303 We also need NewABI support. */
12304 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12310 if (mips_cpreturn_register == -1)
12312 ex.X_op = O_constant;
12313 ex.X_add_symbol = NULL;
12314 ex.X_op_symbol = NULL;
12315 ex.X_add_number = mips_cpreturn_offset;
12317 macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
12318 BFD_RELOC_LO16, SP);
12321 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
12322 mips_cpreturn_register, 0);
12324 demand_empty_rest_of_line ();
12327 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12328 code. It sets the offset to use in gp_rel relocations. */
12331 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12333 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12334 We also need NewABI support. */
12335 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12341 mips_gprel_offset = get_absolute_expression ();
12343 demand_empty_rest_of_line ();
12346 /* Handle the .gpword pseudo-op. This is used when generating PIC
12347 code. It generates a 32 bit GP relative reloc. */
12350 s_gpword (int ignore ATTRIBUTE_UNUSED)
12356 /* When not generating PIC code, this is treated as .word. */
12357 if (mips_pic != SVR4_PIC)
12363 label = insn_labels != NULL ? insn_labels->label : NULL;
12364 mips_emit_delays (TRUE);
12366 mips_align (2, 0, label);
12367 mips_clear_insn_labels ();
12371 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12373 as_bad (_("Unsupported use of .gpword"));
12374 ignore_rest_of_line ();
12378 md_number_to_chars (p, 0, 4);
12379 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12380 BFD_RELOC_GPREL32);
12382 demand_empty_rest_of_line ();
12386 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12392 /* When not generating PIC code, this is treated as .dword. */
12393 if (mips_pic != SVR4_PIC)
12399 label = insn_labels != NULL ? insn_labels->label : NULL;
12400 mips_emit_delays (TRUE);
12402 mips_align (3, 0, label);
12403 mips_clear_insn_labels ();
12407 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12409 as_bad (_("Unsupported use of .gpdword"));
12410 ignore_rest_of_line ();
12414 md_number_to_chars (p, 0, 8);
12415 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12416 BFD_RELOC_GPREL32);
12418 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12419 ex.X_op = O_absent;
12420 ex.X_add_symbol = 0;
12421 ex.X_add_number = 0;
12422 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12425 demand_empty_rest_of_line ();
12428 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12429 tables in SVR4 PIC code. */
12432 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12437 /* This is ignored when not generating SVR4 PIC code. */
12438 if (mips_pic != SVR4_PIC)
12444 /* Add $gp to the register named as an argument. */
12445 reg = tc_get_register (0);
12446 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
12447 reg, reg, mips_gp_register);
12449 demand_empty_rest_of_line ();
12452 /* Handle the .insn pseudo-op. This marks instruction labels in
12453 mips16 mode. This permits the linker to handle them specially,
12454 such as generating jalx instructions when needed. We also make
12455 them odd for the duration of the assembly, in order to generate the
12456 right sort of code. We will make them even in the adjust_symtab
12457 routine, while leaving them marked. This is convenient for the
12458 debugger and the disassembler. The linker knows to make them odd
12462 s_insn (int ignore ATTRIBUTE_UNUSED)
12464 mips16_mark_labels ();
12466 demand_empty_rest_of_line ();
12469 /* Handle a .stabn directive. We need these in order to mark a label
12470 as being a mips16 text label correctly. Sometimes the compiler
12471 will emit a label, followed by a .stabn, and then switch sections.
12472 If the label and .stabn are in mips16 mode, then the label is
12473 really a mips16 text label. */
12476 s_mips_stab (int type)
12479 mips16_mark_labels ();
12484 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12488 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12495 name = input_line_pointer;
12496 c = get_symbol_end ();
12497 symbolP = symbol_find_or_make (name);
12498 S_SET_WEAK (symbolP);
12499 *input_line_pointer = c;
12501 SKIP_WHITESPACE ();
12503 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12505 if (S_IS_DEFINED (symbolP))
12507 as_bad ("ignoring attempt to redefine symbol %s",
12508 S_GET_NAME (symbolP));
12509 ignore_rest_of_line ();
12513 if (*input_line_pointer == ',')
12515 ++input_line_pointer;
12516 SKIP_WHITESPACE ();
12520 if (exp.X_op != O_symbol)
12522 as_bad ("bad .weakext directive");
12523 ignore_rest_of_line ();
12526 symbol_set_value_expression (symbolP, &exp);
12529 demand_empty_rest_of_line ();
12532 /* Parse a register string into a number. Called from the ECOFF code
12533 to parse .frame. The argument is non-zero if this is the frame
12534 register, so that we can record it in mips_frame_reg. */
12537 tc_get_register (int frame)
12541 SKIP_WHITESPACE ();
12542 if (*input_line_pointer++ != '$')
12544 as_warn (_("expected `$'"));
12547 else if (ISDIGIT (*input_line_pointer))
12549 reg = get_absolute_expression ();
12550 if (reg < 0 || reg >= 32)
12552 as_warn (_("Bad register number"));
12558 if (strncmp (input_line_pointer, "ra", 2) == 0)
12561 input_line_pointer += 2;
12563 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12566 input_line_pointer += 2;
12568 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12571 input_line_pointer += 2;
12573 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12576 input_line_pointer += 2;
12578 else if (strncmp (input_line_pointer, "at", 2) == 0)
12581 input_line_pointer += 2;
12583 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12586 input_line_pointer += 3;
12588 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12591 input_line_pointer += 3;
12593 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12596 input_line_pointer += 4;
12600 as_warn (_("Unrecognized register name"));
12602 while (ISALNUM(*input_line_pointer))
12603 input_line_pointer++;
12608 mips_frame_reg = reg != 0 ? reg : SP;
12609 mips_frame_reg_valid = 1;
12610 mips_cprestore_valid = 0;
12616 md_section_align (asection *seg, valueT addr)
12618 int align = bfd_get_section_alignment (stdoutput, seg);
12621 /* We don't need to align ELF sections to the full alignment.
12622 However, Irix 5 may prefer that we align them at least to a 16
12623 byte boundary. We don't bother to align the sections if we are
12624 targeted for an embedded system. */
12625 if (strcmp (TARGET_OS, "elf") == 0)
12631 return ((addr + (1 << align) - 1) & (-1 << align));
12634 /* Utility routine, called from above as well. If called while the
12635 input file is still being read, it's only an approximation. (For
12636 example, a symbol may later become defined which appeared to be
12637 undefined earlier.) */
12640 nopic_need_relax (symbolS *sym, int before_relaxing)
12645 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12647 const char *symname;
12650 /* Find out whether this symbol can be referenced off the $gp
12651 register. It can be if it is smaller than the -G size or if
12652 it is in the .sdata or .sbss section. Certain symbols can
12653 not be referenced off the $gp, although it appears as though
12655 symname = S_GET_NAME (sym);
12656 if (symname != (const char *) NULL
12657 && (strcmp (symname, "eprol") == 0
12658 || strcmp (symname, "etext") == 0
12659 || strcmp (symname, "_gp") == 0
12660 || strcmp (symname, "edata") == 0
12661 || strcmp (symname, "_fbss") == 0
12662 || strcmp (symname, "_fdata") == 0
12663 || strcmp (symname, "_ftext") == 0
12664 || strcmp (symname, "end") == 0
12665 || strcmp (symname, "_gp_disp") == 0))
12667 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12669 #ifndef NO_ECOFF_DEBUGGING
12670 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12671 && (symbol_get_obj (sym)->ecoff_extern_size
12672 <= g_switch_value))
12674 /* We must defer this decision until after the whole
12675 file has been read, since there might be a .extern
12676 after the first use of this symbol. */
12677 || (before_relaxing
12678 #ifndef NO_ECOFF_DEBUGGING
12679 && symbol_get_obj (sym)->ecoff_extern_size == 0
12681 && S_GET_VALUE (sym) == 0)
12682 || (S_GET_VALUE (sym) != 0
12683 && S_GET_VALUE (sym) <= g_switch_value)))
12687 const char *segname;
12689 segname = segment_name (S_GET_SEGMENT (sym));
12690 assert (strcmp (segname, ".lit8") != 0
12691 && strcmp (segname, ".lit4") != 0);
12692 change = (strcmp (segname, ".sdata") != 0
12693 && strcmp (segname, ".sbss") != 0
12694 && strncmp (segname, ".sdata.", 7) != 0
12695 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12700 /* We are not optimizing for the $gp register. */
12705 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12708 pic_need_relax (symbolS *sym, asection *segtype)
12711 bfd_boolean linkonce;
12713 /* Handle the case of a symbol equated to another symbol. */
12714 while (symbol_equated_reloc_p (sym))
12718 /* It's possible to get a loop here in a badly written
12720 n = symbol_get_value_expression (sym)->X_add_symbol;
12726 symsec = S_GET_SEGMENT (sym);
12728 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12730 if (symsec != segtype && ! S_IS_LOCAL (sym))
12732 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12736 /* The GNU toolchain uses an extension for ELF: a section
12737 beginning with the magic string .gnu.linkonce is a linkonce
12739 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12740 sizeof ".gnu.linkonce" - 1) == 0)
12744 /* This must duplicate the test in adjust_reloc_syms. */
12745 return (symsec != &bfd_und_section
12746 && symsec != &bfd_abs_section
12747 && ! bfd_is_com_section (symsec)
12750 /* A global or weak symbol is treated as external. */
12751 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12752 || (! S_IS_WEAK (sym)
12753 && (! S_IS_EXTERNAL (sym)
12754 || mips_pic == EMBEDDED_PIC)))
12760 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12761 extended opcode. SEC is the section the frag is in. */
12764 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12767 register const struct mips16_immed_operand *op;
12769 int mintiny, maxtiny;
12773 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12775 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12778 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12779 op = mips16_immed_operands;
12780 while (op->type != type)
12783 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12788 if (type == '<' || type == '>' || type == '[' || type == ']')
12791 maxtiny = 1 << op->nbits;
12796 maxtiny = (1 << op->nbits) - 1;
12801 mintiny = - (1 << (op->nbits - 1));
12802 maxtiny = (1 << (op->nbits - 1)) - 1;
12805 sym_frag = symbol_get_frag (fragp->fr_symbol);
12806 val = S_GET_VALUE (fragp->fr_symbol);
12807 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12813 /* We won't have the section when we are called from
12814 mips_relax_frag. However, we will always have been called
12815 from md_estimate_size_before_relax first. If this is a
12816 branch to a different section, we mark it as such. If SEC is
12817 NULL, and the frag is not marked, then it must be a branch to
12818 the same section. */
12821 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12826 /* Must have been called from md_estimate_size_before_relax. */
12829 fragp->fr_subtype =
12830 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12832 /* FIXME: We should support this, and let the linker
12833 catch branches and loads that are out of range. */
12834 as_bad_where (fragp->fr_file, fragp->fr_line,
12835 _("unsupported PC relative reference to different section"));
12839 if (fragp != sym_frag && sym_frag->fr_address == 0)
12840 /* Assume non-extended on the first relaxation pass.
12841 The address we have calculated will be bogus if this is
12842 a forward branch to another frag, as the forward frag
12843 will have fr_address == 0. */
12847 /* In this case, we know for sure that the symbol fragment is in
12848 the same section. If the relax_marker of the symbol fragment
12849 differs from the relax_marker of this fragment, we have not
12850 yet adjusted the symbol fragment fr_address. We want to add
12851 in STRETCH in order to get a better estimate of the address.
12852 This particularly matters because of the shift bits. */
12854 && sym_frag->relax_marker != fragp->relax_marker)
12858 /* Adjust stretch for any alignment frag. Note that if have
12859 been expanding the earlier code, the symbol may be
12860 defined in what appears to be an earlier frag. FIXME:
12861 This doesn't handle the fr_subtype field, which specifies
12862 a maximum number of bytes to skip when doing an
12864 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12866 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12869 stretch = - ((- stretch)
12870 & ~ ((1 << (int) f->fr_offset) - 1));
12872 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12881 addr = fragp->fr_address + fragp->fr_fix;
12883 /* The base address rules are complicated. The base address of
12884 a branch is the following instruction. The base address of a
12885 PC relative load or add is the instruction itself, but if it
12886 is in a delay slot (in which case it can not be extended) use
12887 the address of the instruction whose delay slot it is in. */
12888 if (type == 'p' || type == 'q')
12892 /* If we are currently assuming that this frag should be
12893 extended, then, the current address is two bytes
12895 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12898 /* Ignore the low bit in the target, since it will be set
12899 for a text label. */
12900 if ((val & 1) != 0)
12903 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12905 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12908 val -= addr & ~ ((1 << op->shift) - 1);
12910 /* Branch offsets have an implicit 0 in the lowest bit. */
12911 if (type == 'p' || type == 'q')
12914 /* If any of the shifted bits are set, we must use an extended
12915 opcode. If the address depends on the size of this
12916 instruction, this can lead to a loop, so we arrange to always
12917 use an extended opcode. We only check this when we are in
12918 the main relaxation loop, when SEC is NULL. */
12919 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12921 fragp->fr_subtype =
12922 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12926 /* If we are about to mark a frag as extended because the value
12927 is precisely maxtiny + 1, then there is a chance of an
12928 infinite loop as in the following code:
12933 In this case when the la is extended, foo is 0x3fc bytes
12934 away, so the la can be shrunk, but then foo is 0x400 away, so
12935 the la must be extended. To avoid this loop, we mark the
12936 frag as extended if it was small, and is about to become
12937 extended with a value of maxtiny + 1. */
12938 if (val == ((maxtiny + 1) << op->shift)
12939 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12942 fragp->fr_subtype =
12943 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12947 else if (symsec != absolute_section && sec != NULL)
12948 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12950 if ((val & ((1 << op->shift) - 1)) != 0
12951 || val < (mintiny << op->shift)
12952 || val > (maxtiny << op->shift))
12958 /* Compute the length of a branch sequence, and adjust the
12959 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12960 worst-case length is computed, with UPDATE being used to indicate
12961 whether an unconditional (-1), branch-likely (+1) or regular (0)
12962 branch is to be computed. */
12964 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12966 bfd_boolean toofar;
12970 && S_IS_DEFINED (fragp->fr_symbol)
12971 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12976 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12978 addr = fragp->fr_address + fragp->fr_fix + 4;
12982 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12985 /* If the symbol is not defined or it's in a different segment,
12986 assume the user knows what's going on and emit a short
12992 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12994 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12995 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12996 RELAX_BRANCH_LINK (fragp->fr_subtype),
13002 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13005 if (mips_pic != NO_PIC)
13007 /* Additional space for PIC loading of target address. */
13009 if (mips_opts.isa == ISA_MIPS1)
13010 /* Additional space for $at-stabilizing nop. */
13014 /* If branch is conditional. */
13015 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13022 /* Estimate the size of a frag before relaxing. Unless this is the
13023 mips16, we are not really relaxing here, and the final size is
13024 encoded in the subtype information. For the mips16, we have to
13025 decide whether we are using an extended opcode or not. */
13028 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13032 if (RELAX_BRANCH_P (fragp->fr_subtype))
13035 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13037 return fragp->fr_var;
13040 if (RELAX_MIPS16_P (fragp->fr_subtype))
13041 /* We don't want to modify the EXTENDED bit here; it might get us
13042 into infinite loops. We change it only in mips_relax_frag(). */
13043 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13045 if (mips_pic == NO_PIC)
13046 change = nopic_need_relax (fragp->fr_symbol, 0);
13047 else if (mips_pic == SVR4_PIC)
13048 change = pic_need_relax (fragp->fr_symbol, segtype);
13054 /* Record the offset to the first reloc in the fr_opcode field.
13055 This lets md_convert_frag and tc_gen_reloc know that the code
13056 must be expanded. */
13057 fragp->fr_opcode = (fragp->fr_literal
13059 - RELAX_OLD (fragp->fr_subtype)
13060 + RELAX_RELOC1 (fragp->fr_subtype));
13061 /* FIXME: This really needs as_warn_where. */
13062 if (RELAX_WARN (fragp->fr_subtype))
13063 as_warn (_("AT used after \".set noat\" or macro used after "
13064 "\".set nomacro\""));
13066 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
13072 /* This is called to see whether a reloc against a defined symbol
13073 should be converted into a reloc against a section. Don't adjust
13074 MIPS16 jump relocations, so we don't have to worry about the format
13075 of the offset in the .o file. Don't adjust relocations against
13076 mips16 symbols, so that the linker can find them if it needs to set
13080 mips_fix_adjustable (fixS *fixp)
13082 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13085 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13086 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13089 if (fixp->fx_addsy == NULL)
13093 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13094 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13095 && fixp->fx_subsy == NULL)
13102 /* Translate internal representation of relocation info to BFD target
13106 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13108 static arelent *retval[4];
13110 bfd_reloc_code_real_type code;
13112 memset (retval, 0, sizeof(retval));
13113 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13114 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13115 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13116 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13118 if (mips_pic == EMBEDDED_PIC
13119 && SWITCH_TABLE (fixp))
13121 /* For a switch table entry we use a special reloc. The addend
13122 is actually the difference between the reloc address and the
13124 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13125 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13126 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13127 fixp->fx_r_type = BFD_RELOC_GPREL32;
13129 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
13131 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13132 reloc->addend = fixp->fx_addnumber;
13135 /* We use a special addend for an internal RELLO reloc. */
13136 if (symbol_section_p (fixp->fx_addsy))
13137 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13139 reloc->addend = fixp->fx_addnumber + reloc->address;
13142 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13144 assert (fixp->fx_next != NULL
13145 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13147 /* The reloc is relative to the RELLO; adjust the addend
13149 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13150 reloc->addend = fixp->fx_next->fx_addnumber;
13153 /* We use a special addend for an internal RELHI reloc. */
13154 if (symbol_section_p (fixp->fx_addsy))
13155 reloc->addend = (fixp->fx_next->fx_frag->fr_address
13156 + fixp->fx_next->fx_where
13157 - S_GET_VALUE (fixp->fx_subsy));
13159 reloc->addend = (fixp->fx_addnumber
13160 + fixp->fx_next->fx_frag->fr_address
13161 + fixp->fx_next->fx_where);
13164 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13165 reloc->addend = fixp->fx_addnumber;
13168 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13169 /* A gruesome hack which is a result of the gruesome gas reloc
13171 reloc->addend = reloc->address;
13173 reloc->addend = -reloc->address;
13176 /* If this is a variant frag, we may need to adjust the existing
13177 reloc and generate a new one. */
13178 if (fixp->fx_frag->fr_opcode != NULL
13179 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13181 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP
13183 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13184 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13185 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13186 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13187 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13188 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13193 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13195 /* If this is not the last reloc in this frag, then we have two
13196 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13197 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13198 the second one handle all of them. */
13199 if (fixp->fx_next != NULL
13200 && fixp->fx_frag == fixp->fx_next->fx_frag)
13202 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13203 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13204 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13205 && (fixp->fx_next->fx_r_type
13206 == BFD_RELOC_MIPS_GOT_LO16))
13207 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13208 && (fixp->fx_next->fx_r_type
13209 == BFD_RELOC_MIPS_CALL_LO16)));
13214 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13215 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13216 reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset;
13217 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13218 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13219 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13220 reloc2->address = (reloc->address
13221 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13222 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13223 reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy)
13224 + fixp->fx_frag->tc_frag_data.tc_fr_offset;
13225 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13226 assert (reloc2->howto != NULL);
13228 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13232 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13234 reloc3->address += 4;
13237 if (mips_pic == NO_PIC)
13239 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13240 fixp->fx_r_type = BFD_RELOC_HI16_S;
13242 else if (mips_pic == SVR4_PIC)
13244 switch (fixp->fx_r_type)
13248 case BFD_RELOC_MIPS_GOT16:
13250 case BFD_RELOC_MIPS_GOT_LO16:
13251 case BFD_RELOC_MIPS_CALL_LO16:
13254 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13255 reloc2->howto = bfd_reloc_type_lookup
13256 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13259 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13261 case BFD_RELOC_MIPS_CALL16:
13262 case BFD_RELOC_MIPS_GOT_OFST:
13263 case BFD_RELOC_MIPS_GOT_DISP:
13266 /* It may seem nonsensical to relax GOT_DISP to
13267 GOT_DISP, but we're actually turning a GOT_DISP
13268 without offset into a GOT_DISP with an offset,
13269 getting rid of the separate addition, which we can
13270 do when the symbol is found to be local. */
13271 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13275 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13283 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13284 entry to be used in the relocation's section offset. */
13285 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13287 reloc->address = reloc->addend;
13291 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13292 fixup_segment converted a non-PC relative reloc into a PC
13293 relative reloc. In such a case, we need to convert the reloc
13295 code = fixp->fx_r_type;
13296 if (fixp->fx_pcrel)
13301 code = BFD_RELOC_8_PCREL;
13304 code = BFD_RELOC_16_PCREL;
13307 code = BFD_RELOC_32_PCREL;
13310 code = BFD_RELOC_64_PCREL;
13312 case BFD_RELOC_8_PCREL:
13313 case BFD_RELOC_16_PCREL:
13314 case BFD_RELOC_32_PCREL:
13315 case BFD_RELOC_64_PCREL:
13316 case BFD_RELOC_16_PCREL_S2:
13317 case BFD_RELOC_PCREL_HI16_S:
13318 case BFD_RELOC_PCREL_LO16:
13321 as_bad_where (fixp->fx_file, fixp->fx_line,
13322 _("Cannot make %s relocation PC relative"),
13323 bfd_get_reloc_code_name (code));
13327 /* To support a PC relative reloc when generating embedded PIC code
13328 for ECOFF, we use a Cygnus extension. We check for that here to
13329 make sure that we don't let such a reloc escape normally. */
13330 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13331 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13332 && code == BFD_RELOC_16_PCREL_S2
13333 && mips_pic != EMBEDDED_PIC)
13334 reloc->howto = NULL;
13336 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13338 if (reloc->howto == NULL)
13340 as_bad_where (fixp->fx_file, fixp->fx_line,
13341 _("Can not represent %s relocation in this object file format"),
13342 bfd_get_reloc_code_name (code));
13349 /* Relax a machine dependent frag. This returns the amount by which
13350 the current size of the frag should change. */
13353 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13355 if (RELAX_BRANCH_P (fragp->fr_subtype))
13357 offsetT old_var = fragp->fr_var;
13359 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13361 return fragp->fr_var - old_var;
13364 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13367 if (mips16_extended_frag (fragp, NULL, stretch))
13369 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13371 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13376 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13378 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13385 /* Convert a machine dependent frag. */
13388 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13393 if (RELAX_BRANCH_P (fragp->fr_subtype))
13396 unsigned long insn;
13400 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13402 if (target_big_endian)
13403 insn = bfd_getb32 (buf);
13405 insn = bfd_getl32 (buf);
13407 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13409 /* We generate a fixup instead of applying it right now
13410 because, if there are linker relaxations, we're going to
13411 need the relocations. */
13412 exp.X_op = O_symbol;
13413 exp.X_add_symbol = fragp->fr_symbol;
13414 exp.X_add_number = fragp->fr_offset;
13416 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13418 BFD_RELOC_16_PCREL_S2);
13419 fixp->fx_file = fragp->fr_file;
13420 fixp->fx_line = fragp->fr_line;
13422 md_number_to_chars (buf, insn, 4);
13429 as_warn_where (fragp->fr_file, fragp->fr_line,
13430 _("relaxed out-of-range branch into a jump"));
13432 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13435 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13437 /* Reverse the branch. */
13438 switch ((insn >> 28) & 0xf)
13441 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13442 have the condition reversed by tweaking a single
13443 bit, and their opcodes all have 0x4???????. */
13444 assert ((insn & 0xf1000000) == 0x41000000);
13445 insn ^= 0x00010000;
13449 /* bltz 0x04000000 bgez 0x04010000
13450 bltzal 0x04100000 bgezal 0x04110000 */
13451 assert ((insn & 0xfc0e0000) == 0x04000000);
13452 insn ^= 0x00010000;
13456 /* beq 0x10000000 bne 0x14000000
13457 blez 0x18000000 bgtz 0x1c000000 */
13458 insn ^= 0x04000000;
13466 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13468 /* Clear the and-link bit. */
13469 assert ((insn & 0xfc1c0000) == 0x04100000);
13471 /* bltzal 0x04100000 bgezal 0x04110000
13472 bltzall 0x04120000 bgezall 0x04130000 */
13473 insn &= ~0x00100000;
13476 /* Branch over the branch (if the branch was likely) or the
13477 full jump (not likely case). Compute the offset from the
13478 current instruction to branch to. */
13479 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13483 /* How many bytes in instructions we've already emitted? */
13484 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13485 /* How many bytes in instructions from here to the end? */
13486 i = fragp->fr_var - i;
13488 /* Convert to instruction count. */
13490 /* Branch counts from the next instruction. */
13493 /* Branch over the jump. */
13494 md_number_to_chars (buf, insn, 4);
13498 md_number_to_chars (buf, 0, 4);
13501 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13503 /* beql $0, $0, 2f */
13505 /* Compute the PC offset from the current instruction to
13506 the end of the variable frag. */
13507 /* How many bytes in instructions we've already emitted? */
13508 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13509 /* How many bytes in instructions from here to the end? */
13510 i = fragp->fr_var - i;
13511 /* Convert to instruction count. */
13513 /* Don't decrement i, because we want to branch over the
13517 md_number_to_chars (buf, insn, 4);
13520 md_number_to_chars (buf, 0, 4);
13525 if (mips_pic == NO_PIC)
13528 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13529 ? 0x0c000000 : 0x08000000);
13530 exp.X_op = O_symbol;
13531 exp.X_add_symbol = fragp->fr_symbol;
13532 exp.X_add_number = fragp->fr_offset;
13534 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13535 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13536 fixp->fx_file = fragp->fr_file;
13537 fixp->fx_line = fragp->fr_line;
13539 md_number_to_chars (buf, insn, 4);
13544 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13545 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13546 exp.X_op = O_symbol;
13547 exp.X_add_symbol = fragp->fr_symbol;
13548 exp.X_add_number = fragp->fr_offset;
13550 if (fragp->fr_offset)
13552 exp.X_add_symbol = make_expr_symbol (&exp);
13553 exp.X_add_number = 0;
13556 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13557 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13558 fixp->fx_file = fragp->fr_file;
13559 fixp->fx_line = fragp->fr_line;
13561 md_number_to_chars (buf, insn, 4);
13564 if (mips_opts.isa == ISA_MIPS1)
13567 md_number_to_chars (buf, 0, 4);
13571 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13572 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13574 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13575 4, &exp, 0, BFD_RELOC_LO16);
13576 fixp->fx_file = fragp->fr_file;
13577 fixp->fx_line = fragp->fr_line;
13579 md_number_to_chars (buf, insn, 4);
13583 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13588 md_number_to_chars (buf, insn, 4);
13593 assert (buf == (bfd_byte *)fragp->fr_literal
13594 + fragp->fr_fix + fragp->fr_var);
13596 fragp->fr_fix += fragp->fr_var;
13601 if (RELAX_MIPS16_P (fragp->fr_subtype))
13604 register const struct mips16_immed_operand *op;
13605 bfd_boolean small, ext;
13608 unsigned long insn;
13609 bfd_boolean use_extend;
13610 unsigned short extend;
13612 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13613 op = mips16_immed_operands;
13614 while (op->type != type)
13617 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13628 resolve_symbol_value (fragp->fr_symbol);
13629 val = S_GET_VALUE (fragp->fr_symbol);
13634 addr = fragp->fr_address + fragp->fr_fix;
13636 /* The rules for the base address of a PC relative reloc are
13637 complicated; see mips16_extended_frag. */
13638 if (type == 'p' || type == 'q')
13643 /* Ignore the low bit in the target, since it will be
13644 set for a text label. */
13645 if ((val & 1) != 0)
13648 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13650 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13653 addr &= ~ (addressT) ((1 << op->shift) - 1);
13656 /* Make sure the section winds up with the alignment we have
13659 record_alignment (asec, op->shift);
13663 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13664 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13665 as_warn_where (fragp->fr_file, fragp->fr_line,
13666 _("extended instruction in delay slot"));
13668 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13670 if (target_big_endian)
13671 insn = bfd_getb16 (buf);
13673 insn = bfd_getl16 (buf);
13675 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13676 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13677 small, ext, &insn, &use_extend, &extend);
13681 md_number_to_chars (buf, 0xf000 | extend, 2);
13682 fragp->fr_fix += 2;
13686 md_number_to_chars (buf, insn, 2);
13687 fragp->fr_fix += 2;
13692 if (fragp->fr_opcode == NULL)
13695 old = RELAX_OLD (fragp->fr_subtype);
13696 new = RELAX_NEW (fragp->fr_subtype);
13697 fixptr = fragp->fr_literal + fragp->fr_fix;
13700 memmove (fixptr - old, fixptr, new);
13702 fragp->fr_fix += new - old;
13708 /* This function is called after the relocs have been generated.
13709 We've been storing mips16 text labels as odd. Here we convert them
13710 back to even for the convenience of the debugger. */
13713 mips_frob_file_after_relocs (void)
13716 unsigned int count, i;
13718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13721 syms = bfd_get_outsymbols (stdoutput);
13722 count = bfd_get_symcount (stdoutput);
13723 for (i = 0; i < count; i++, syms++)
13725 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13726 && ((*syms)->value & 1) != 0)
13728 (*syms)->value &= ~1;
13729 /* If the symbol has an odd size, it was probably computed
13730 incorrectly, so adjust that as well. */
13731 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13732 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13739 /* This function is called whenever a label is defined. It is used
13740 when handling branch delays; if a branch has a label, we assume we
13741 can not move it. */
13744 mips_define_label (symbolS *sym)
13746 struct insn_label_list *l;
13748 if (free_insn_labels == NULL)
13749 l = (struct insn_label_list *) xmalloc (sizeof *l);
13752 l = free_insn_labels;
13753 free_insn_labels = l->next;
13757 l->next = insn_labels;
13761 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13763 /* Some special processing for a MIPS ELF file. */
13766 mips_elf_final_processing (void)
13768 /* Write out the register information. */
13769 if (mips_abi != N64_ABI)
13773 s.ri_gprmask = mips_gprmask;
13774 s.ri_cprmask[0] = mips_cprmask[0];
13775 s.ri_cprmask[1] = mips_cprmask[1];
13776 s.ri_cprmask[2] = mips_cprmask[2];
13777 s.ri_cprmask[3] = mips_cprmask[3];
13778 /* The gp_value field is set by the MIPS ELF backend. */
13780 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13781 ((Elf32_External_RegInfo *)
13782 mips_regmask_frag));
13786 Elf64_Internal_RegInfo s;
13788 s.ri_gprmask = mips_gprmask;
13790 s.ri_cprmask[0] = mips_cprmask[0];
13791 s.ri_cprmask[1] = mips_cprmask[1];
13792 s.ri_cprmask[2] = mips_cprmask[2];
13793 s.ri_cprmask[3] = mips_cprmask[3];
13794 /* The gp_value field is set by the MIPS ELF backend. */
13796 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13797 ((Elf64_External_RegInfo *)
13798 mips_regmask_frag));
13801 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13802 sort of BFD interface for this. */
13803 if (mips_any_noreorder)
13804 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13805 if (mips_pic != NO_PIC)
13807 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13808 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13811 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13813 /* Set MIPS ELF flags for ASEs. */
13814 if (file_ase_mips16)
13815 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13816 #if 0 /* XXX FIXME */
13817 if (file_ase_mips3d)
13818 elf_elfheader (stdoutput)->e_flags |= ???;
13821 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13823 /* Set the MIPS ELF ABI flags. */
13824 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13825 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13826 else if (mips_abi == O64_ABI)
13827 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13828 else if (mips_abi == EABI_ABI)
13830 if (!file_mips_gp32)
13831 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13833 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13835 else if (mips_abi == N32_ABI)
13836 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13838 /* Nothing to do for N64_ABI. */
13840 if (mips_32bitmode)
13841 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13844 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13846 typedef struct proc {
13848 unsigned long reg_mask;
13849 unsigned long reg_offset;
13850 unsigned long fpreg_mask;
13851 unsigned long fpreg_offset;
13852 unsigned long frame_offset;
13853 unsigned long frame_reg;
13854 unsigned long pc_reg;
13857 static procS cur_proc;
13858 static procS *cur_proc_ptr;
13859 static int numprocs;
13861 /* Fill in an rs_align_code fragment. */
13864 mips_handle_align (fragS *fragp)
13866 if (fragp->fr_type != rs_align_code)
13869 if (mips_opts.mips16)
13871 static const unsigned char be_nop[] = { 0x65, 0x00 };
13872 static const unsigned char le_nop[] = { 0x00, 0x65 };
13877 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13878 p = fragp->fr_literal + fragp->fr_fix;
13886 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13890 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13894 md_obj_begin (void)
13901 /* check for premature end, nesting errors, etc */
13903 as_warn (_("missing .end at end of assembly"));
13912 if (*input_line_pointer == '-')
13914 ++input_line_pointer;
13917 if (!ISDIGIT (*input_line_pointer))
13918 as_bad (_("expected simple number"));
13919 if (input_line_pointer[0] == '0')
13921 if (input_line_pointer[1] == 'x')
13923 input_line_pointer += 2;
13924 while (ISXDIGIT (*input_line_pointer))
13927 val |= hex_value (*input_line_pointer++);
13929 return negative ? -val : val;
13933 ++input_line_pointer;
13934 while (ISDIGIT (*input_line_pointer))
13937 val |= *input_line_pointer++ - '0';
13939 return negative ? -val : val;
13942 if (!ISDIGIT (*input_line_pointer))
13944 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13945 *input_line_pointer, *input_line_pointer);
13946 as_warn (_("invalid number"));
13949 while (ISDIGIT (*input_line_pointer))
13952 val += *input_line_pointer++ - '0';
13954 return negative ? -val : val;
13957 /* The .file directive; just like the usual .file directive, but there
13958 is an initial number which is the ECOFF file index. In the non-ECOFF
13959 case .file implies DWARF-2. */
13962 s_mips_file (int x ATTRIBUTE_UNUSED)
13964 static int first_file_directive = 0;
13966 if (ECOFF_DEBUGGING)
13975 filename = dwarf2_directive_file (0);
13977 /* Versions of GCC up to 3.1 start files with a ".file"
13978 directive even for stabs output. Make sure that this
13979 ".file" is handled. Note that you need a version of GCC
13980 after 3.1 in order to support DWARF-2 on MIPS. */
13981 if (filename != NULL && ! first_file_directive)
13983 (void) new_logical_line (filename, -1);
13984 s_app_file_string (filename);
13986 first_file_directive = 1;
13990 /* The .loc directive, implying DWARF-2. */
13993 s_mips_loc (int x ATTRIBUTE_UNUSED)
13995 if (!ECOFF_DEBUGGING)
13996 dwarf2_directive_loc (0);
13999 /* The .end directive. */
14002 s_mips_end (int x ATTRIBUTE_UNUSED)
14006 /* Following functions need their own .frame and .cprestore directives. */
14007 mips_frame_reg_valid = 0;
14008 mips_cprestore_valid = 0;
14010 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14013 demand_empty_rest_of_line ();
14018 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14019 as_warn (_(".end not in text section"));
14023 as_warn (_(".end directive without a preceding .ent directive."));
14024 demand_empty_rest_of_line ();
14030 assert (S_GET_NAME (p));
14031 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14032 as_warn (_(".end symbol does not match .ent symbol."));
14034 if (debug_type == DEBUG_STABS)
14035 stabs_generate_asm_endfunc (S_GET_NAME (p),
14039 as_warn (_(".end directive missing or unknown symbol"));
14042 /* Generate a .pdr section. */
14043 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14045 segT saved_seg = now_seg;
14046 subsegT saved_subseg = now_subseg;
14051 dot = frag_now_fix ();
14053 #ifdef md_flush_pending_output
14054 md_flush_pending_output ();
14058 subseg_set (pdr_seg, 0);
14060 /* Write the symbol. */
14061 exp.X_op = O_symbol;
14062 exp.X_add_symbol = p;
14063 exp.X_add_number = 0;
14064 emit_expr (&exp, 4);
14066 fragp = frag_more (7 * 4);
14068 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14069 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14070 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14071 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14072 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14073 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14074 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14076 subseg_set (saved_seg, saved_subseg);
14078 #endif /* OBJ_ELF */
14080 cur_proc_ptr = NULL;
14083 /* The .aent and .ent directives. */
14086 s_mips_ent (int aent)
14090 symbolP = get_symbol ();
14091 if (*input_line_pointer == ',')
14092 ++input_line_pointer;
14093 SKIP_WHITESPACE ();
14094 if (ISDIGIT (*input_line_pointer)
14095 || *input_line_pointer == '-')
14098 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14099 as_warn (_(".ent or .aent not in text section."));
14101 if (!aent && cur_proc_ptr)
14102 as_warn (_("missing .end"));
14106 /* This function needs its own .frame and .cprestore directives. */
14107 mips_frame_reg_valid = 0;
14108 mips_cprestore_valid = 0;
14110 cur_proc_ptr = &cur_proc;
14111 memset (cur_proc_ptr, '\0', sizeof (procS));
14113 cur_proc_ptr->isym = symbolP;
14115 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14119 if (debug_type == DEBUG_STABS)
14120 stabs_generate_asm_func (S_GET_NAME (symbolP),
14121 S_GET_NAME (symbolP));
14124 demand_empty_rest_of_line ();
14127 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14128 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14129 s_mips_frame is used so that we can set the PDR information correctly.
14130 We can't use the ecoff routines because they make reference to the ecoff
14131 symbol table (in the mdebug section). */
14134 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14137 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14141 if (cur_proc_ptr == (procS *) NULL)
14143 as_warn (_(".frame outside of .ent"));
14144 demand_empty_rest_of_line ();
14148 cur_proc_ptr->frame_reg = tc_get_register (1);
14150 SKIP_WHITESPACE ();
14151 if (*input_line_pointer++ != ','
14152 || get_absolute_expression_and_terminator (&val) != ',')
14154 as_warn (_("Bad .frame directive"));
14155 --input_line_pointer;
14156 demand_empty_rest_of_line ();
14160 cur_proc_ptr->frame_offset = val;
14161 cur_proc_ptr->pc_reg = tc_get_register (0);
14163 demand_empty_rest_of_line ();
14166 #endif /* OBJ_ELF */
14170 /* The .fmask and .mask directives. If the mdebug section is present
14171 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14172 embedded targets, s_mips_mask is used so that we can set the PDR
14173 information correctly. We can't use the ecoff routines because they
14174 make reference to the ecoff symbol table (in the mdebug section). */
14177 s_mips_mask (int reg_type)
14180 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14184 if (cur_proc_ptr == (procS *) NULL)
14186 as_warn (_(".mask/.fmask outside of .ent"));
14187 demand_empty_rest_of_line ();
14191 if (get_absolute_expression_and_terminator (&mask) != ',')
14193 as_warn (_("Bad .mask/.fmask directive"));
14194 --input_line_pointer;
14195 demand_empty_rest_of_line ();
14199 off = get_absolute_expression ();
14201 if (reg_type == 'F')
14203 cur_proc_ptr->fpreg_mask = mask;
14204 cur_proc_ptr->fpreg_offset = off;
14208 cur_proc_ptr->reg_mask = mask;
14209 cur_proc_ptr->reg_offset = off;
14212 demand_empty_rest_of_line ();
14215 #endif /* OBJ_ELF */
14216 s_ignore (reg_type);
14219 /* The .loc directive. */
14229 assert (now_seg == text_section);
14231 lineno = get_number ();
14232 addroff = frag_now_fix ();
14234 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14235 S_SET_TYPE (symbolP, N_SLINE);
14236 S_SET_OTHER (symbolP, 0);
14237 S_SET_DESC (symbolP, lineno);
14238 symbolP->sy_segment = now_seg;
14242 /* A table describing all the processors gas knows about. Names are
14243 matched in the order listed.
14245 To ease comparison, please keep this table in the same order as
14246 gcc's mips_cpu_info_table[]. */
14247 static const struct mips_cpu_info mips_cpu_info_table[] =
14249 /* Entries for generic ISAs */
14250 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14251 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14252 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14253 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14254 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14255 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14256 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14257 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14260 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14261 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14262 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14265 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14268 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14269 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14270 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14271 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14272 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14273 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14274 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14275 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14276 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14277 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14278 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14279 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14282 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14283 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14284 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14285 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14286 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14287 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14288 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14289 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14290 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14291 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14292 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14293 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14294 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14297 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14298 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14299 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14302 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14303 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14305 /* Broadcom SB-1 CPU core */
14306 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14313 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14314 with a final "000" replaced by "k". Ignore case.
14316 Note: this function is shared between GCC and GAS. */
14319 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14321 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14322 given++, canonical++;
14324 return ((*given == 0 && *canonical == 0)
14325 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14329 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14330 CPU name. We've traditionally allowed a lot of variation here.
14332 Note: this function is shared between GCC and GAS. */
14335 mips_matching_cpu_name_p (const char *canonical, const char *given)
14337 /* First see if the name matches exactly, or with a final "000"
14338 turned into "k". */
14339 if (mips_strict_matching_cpu_name_p (canonical, given))
14342 /* If not, try comparing based on numerical designation alone.
14343 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14344 if (TOLOWER (*given) == 'r')
14346 if (!ISDIGIT (*given))
14349 /* Skip over some well-known prefixes in the canonical name,
14350 hoping to find a number there too. */
14351 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14353 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14355 else if (TOLOWER (canonical[0]) == 'r')
14358 return mips_strict_matching_cpu_name_p (canonical, given);
14362 /* Parse an option that takes the name of a processor as its argument.
14363 OPTION is the name of the option and CPU_STRING is the argument.
14364 Return the corresponding processor enumeration if the CPU_STRING is
14365 recognized, otherwise report an error and return null.
14367 A similar function exists in GCC. */
14369 static const struct mips_cpu_info *
14370 mips_parse_cpu (const char *option, const char *cpu_string)
14372 const struct mips_cpu_info *p;
14374 /* 'from-abi' selects the most compatible architecture for the given
14375 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14376 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14377 version. Look first at the -mgp options, if given, otherwise base
14378 the choice on MIPS_DEFAULT_64BIT.
14380 Treat NO_ABI like the EABIs. One reason to do this is that the
14381 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14382 architecture. This code picks MIPS I for 'mips' and MIPS III for
14383 'mips64', just as we did in the days before 'from-abi'. */
14384 if (strcasecmp (cpu_string, "from-abi") == 0)
14386 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14387 return mips_cpu_info_from_isa (ISA_MIPS1);
14389 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14390 return mips_cpu_info_from_isa (ISA_MIPS3);
14392 if (file_mips_gp32 >= 0)
14393 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14395 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14400 /* 'default' has traditionally been a no-op. Probably not very useful. */
14401 if (strcasecmp (cpu_string, "default") == 0)
14404 for (p = mips_cpu_info_table; p->name != 0; p++)
14405 if (mips_matching_cpu_name_p (p->name, cpu_string))
14408 as_bad ("Bad value (%s) for %s", cpu_string, option);
14412 /* Return the canonical processor information for ISA (a member of the
14413 ISA_MIPS* enumeration). */
14415 static const struct mips_cpu_info *
14416 mips_cpu_info_from_isa (int isa)
14420 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14421 if (mips_cpu_info_table[i].is_isa
14422 && isa == mips_cpu_info_table[i].isa)
14423 return (&mips_cpu_info_table[i]);
14428 static const struct mips_cpu_info *
14429 mips_cpu_info_from_arch (int arch)
14433 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14434 if (arch == mips_cpu_info_table[i].cpu)
14435 return (&mips_cpu_info_table[i]);
14441 show (FILE *stream, const char *string, int *col_p, int *first_p)
14445 fprintf (stream, "%24s", "");
14450 fprintf (stream, ", ");
14454 if (*col_p + strlen (string) > 72)
14456 fprintf (stream, "\n%24s", "");
14460 fprintf (stream, "%s", string);
14461 *col_p += strlen (string);
14467 md_show_usage (FILE *stream)
14472 fprintf (stream, _("\
14474 -membedded-pic generate embedded position independent code\n\
14475 -EB generate big endian output\n\
14476 -EL generate little endian output\n\
14477 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14478 -G NUM allow referencing objects up to NUM bytes\n\
14479 implicitly with the gp register [default 8]\n"));
14480 fprintf (stream, _("\
14481 -mips1 generate MIPS ISA I instructions\n\
14482 -mips2 generate MIPS ISA II instructions\n\
14483 -mips3 generate MIPS ISA III instructions\n\
14484 -mips4 generate MIPS ISA IV instructions\n\
14485 -mips5 generate MIPS ISA V instructions\n\
14486 -mips32 generate MIPS32 ISA instructions\n\
14487 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14488 -mips64 generate MIPS64 ISA instructions\n\
14489 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14493 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14494 show (stream, mips_cpu_info_table[i].name, &column, &first);
14495 show (stream, "from-abi", &column, &first);
14496 fputc ('\n', stream);
14498 fprintf (stream, _("\
14499 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14500 -no-mCPU don't generate code specific to CPU.\n\
14501 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14505 show (stream, "3900", &column, &first);
14506 show (stream, "4010", &column, &first);
14507 show (stream, "4100", &column, &first);
14508 show (stream, "4650", &column, &first);
14509 fputc ('\n', stream);
14511 fprintf (stream, _("\
14512 -mips16 generate mips16 instructions\n\
14513 -no-mips16 do not generate mips16 instructions\n"));
14514 fprintf (stream, _("\
14515 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14516 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14517 -O0 remove unneeded NOPs, do not swap branches\n\
14518 -O remove unneeded NOPs and swap branches\n\
14519 -n warn about NOPs generated from macros\n\
14520 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14521 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14522 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14524 fprintf (stream, _("\
14525 -KPIC, -call_shared generate SVR4 position independent code\n\
14526 -non_shared do not generate position independent code\n\
14527 -xgot assume a 32 bit GOT\n\
14528 -mabi=ABI create ABI conformant object file for:\n"));
14532 show (stream, "32", &column, &first);
14533 show (stream, "o64", &column, &first);
14534 show (stream, "n32", &column, &first);
14535 show (stream, "64", &column, &first);
14536 show (stream, "eabi", &column, &first);
14538 fputc ('\n', stream);
14540 fprintf (stream, _("\
14541 -32 create o32 ABI object file (default)\n\
14542 -n32 create n32 ABI object file\n\
14543 -64 create 64 ABI object file\n"));
14548 mips_dwarf2_format (void)
14550 if (mips_abi == N64_ABI)
14553 return dwarf2_format_64bit_irix;
14555 return dwarf2_format_64bit;
14559 return dwarf2_format_32bit;