1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag;
89 #define PIC_CALL_REG 25
97 #define ILLEGAL_REG (32)
99 /* Allow override of standard little-endian ECOFF format. */
101 #ifndef ECOFF_LITTLE_FORMAT
102 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
105 extern int target_big_endian;
107 /* The name of the readonly data section. */
108 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
110 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
118 /* The ABI to use. */
129 /* MIPS ABI we are using for this output file. */
130 static enum mips_abi_level file_mips_abi = NO_ABI;
132 /* This is the set of options which may be modified by the .set
133 pseudo-op. We use a struct so that .set push and .set pop are more
136 struct mips_set_options
138 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
139 if it has not been initialized. Changed by `.set mipsN', and the
140 -mipsN command line option, and the default CPU. */
142 /* Enabled Application Specific Extensions (ASEs). These are set to -1
143 if they have not been initialized. Changed by `.set <asename>', by
144 command line options, and based on the default architecture. */
147 /* Whether we are assembling for the mips16 processor. 0 if we are
148 not, 1 if we are, and -1 if the value has not been initialized.
149 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
150 -nomips16 command line options, and the default CPU. */
152 /* Non-zero if we should not reorder instructions. Changed by `.set
153 reorder' and `.set noreorder'. */
155 /* Non-zero if we should not permit the $at ($1) register to be used
156 in instructions. Changed by `.set at' and `.set noat'. */
158 /* Non-zero if we should warn when a macro instruction expands into
159 more than one machine instruction. Changed by `.set nomacro' and
161 int warn_about_macros;
162 /* Non-zero if we should not move instructions. Changed by `.set
163 move', `.set volatile', `.set nomove', and `.set novolatile'. */
165 /* Non-zero if we should not optimize branches by moving the target
166 of the branch into the delay slot. Actually, we don't perform
167 this optimization anyhow. Changed by `.set bopt' and `.set
170 /* Non-zero if we should not autoextend mips16 instructions.
171 Changed by `.set autoextend' and `.set noautoextend'. */
173 /* Restrict general purpose registers and floating point registers
174 to 32 bit. This is initially determined when -mgp32 or -mfp32
175 is passed but can changed if the assembler code uses .set mipsN. */
178 /* The ABI currently in use. This is changed by .set mipsN to loosen
179 restrictions and doesn't affect the whole file. */
180 enum mips_abi_level abi;
183 /* True if -mgp32 was passed. */
184 static int file_mips_gp32 = -1;
186 /* True if -mfp32 was passed. */
187 static int file_mips_fp32 = -1;
189 /* This is the struct we use to hold the current set of options. Note
190 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
191 -1 to indicate that they have not been initialized. */
193 static struct mips_set_options mips_opts =
195 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
198 /* These variables are filled in with the masks of registers used.
199 The object format code reads them and puts them in the appropriate
201 unsigned long mips_gprmask;
202 unsigned long mips_cprmask[4];
204 /* MIPS ISA we are using for this output file. */
205 static int file_mips_isa = ISA_UNKNOWN;
207 /* True if -mips16 was passed or implied by arguments passed on the
208 command line (e.g., by -march). */
209 static int file_ase_mips16;
211 /* True if -mips3d was passed or implied by arguments passed on the
212 command line (e.g., by -march). */
213 static int file_ase_mips3d;
215 /* True if -mdmx was passed or implied by arguments passed on the
216 command line (e.g., by -march). */
217 static int file_ase_mdmx;
219 /* The argument of the -mcpu= flag. Historical for code generation. */
220 static int mips_cpu = CPU_UNKNOWN;
222 /* The argument of the -march= flag. The architecture we are assembling. */
223 static int mips_arch = CPU_UNKNOWN;
225 /* The argument of the -mtune= flag. The architecture for which we
227 static int mips_tune = CPU_UNKNOWN;
229 /* If they asked for mips1 or mips2 and a cpu that is
230 mips3 or greater, then mark the object file 32BITMODE. */
231 static int mips_32bitmode = 0;
233 /* Some ISA's have delay slots for instructions which read or write
234 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
235 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
236 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
237 delay slot in this ISA. The uses of this macro assume that any
238 ISA that has delay slots for one of these, has them for all. They
239 also assume that ISAs which don't have delays for these insns, don't
240 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
241 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
243 || (ISA) == ISA_MIPS2 \
244 || (ISA) == ISA_MIPS3 \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
255 #define HAVE_32BIT_GPRS \
257 || mips_opts.abi == O32_ABI \
258 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
260 #define HAVE_32BIT_FPRS \
262 || mips_opts.abi == O32_ABI \
263 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
265 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
266 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
268 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
270 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
272 /* We can only have 64bit addresses if the object file format
274 #define HAVE_32BIT_ADDRESSES \
276 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
277 || ! HAVE_64BIT_OBJECTS) \
278 && mips_pic != EMBEDDED_PIC))
280 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
282 /* Return true if the given CPU supports the MIPS16 ASE. */
283 #define CPU_HAS_MIPS16(cpu) \
284 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0)
286 /* Return true if the given CPU supports the MIPS3D ASE. */
287 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
290 /* Return true if the given CPU supports the MDMX ASE. */
291 #define CPU_HAS_MDMX(cpu) (false \
294 /* Whether the processor uses hardware interlocks to protect
295 reads from the HI and LO registers, and thus does not
296 require nops to be inserted. */
298 #define hilo_interlocks (mips_arch == CPU_R4010 \
299 || mips_arch == CPU_SB1 \
302 /* Whether the processor uses hardware interlocks to protect reads
303 from the GPRs, and thus does not require nops to be inserted. */
304 #define gpr_interlocks \
305 (mips_opts.isa != ISA_MIPS1 \
306 || mips_arch == CPU_R3900)
308 /* As with other "interlocks" this is used by hardware that has FP
309 (co-processor) interlocks. */
310 /* Itbl support may require additional care here. */
311 #define cop_interlocks (mips_arch == CPU_R4300 \
312 || mips_arch == CPU_SB1 \
315 /* Is this a mfhi or mflo instruction? */
316 #define MF_HILO_INSN(PINFO) \
317 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
319 /* MIPS PIC level. */
323 /* Do not generate PIC code. */
326 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
327 not sure what it is supposed to do. */
330 /* Generate PIC code as in the SVR4 MIPS ABI. */
333 /* Generate PIC code without using a global offset table: the data
334 segment has a maximum size of 64K, all data references are off
335 the $gp register, and all text references are PC relative. This
336 is used on some embedded systems. */
340 static enum mips_pic_level mips_pic;
342 /* Warn about all NOPS that the assembler generates. */
343 static int warn_nops = 0;
345 /* 1 if we should generate 32 bit offsets from the $gp register in
346 SVR4_PIC mode. Currently has no meaning in other modes. */
347 static int mips_big_got = 0;
349 /* 1 if trap instructions should used for overflow rather than break
351 static int mips_trap = 0;
353 /* 1 if double width floating point constants should not be constructed
354 by assembling two single width halves into two single width floating
355 point registers which just happen to alias the double width destination
356 register. On some architectures this aliasing can be disabled by a bit
357 in the status register, and the setting of this bit cannot be determined
358 automatically at assemble time. */
359 static int mips_disable_float_construction;
361 /* Non-zero if any .set noreorder directives were used. */
363 static int mips_any_noreorder;
365 /* Non-zero if nops should be inserted when the register referenced in
366 an mfhi/mflo instruction is read in the next two instructions. */
367 static int mips_7000_hilo_fix;
369 /* The size of the small data section. */
370 static unsigned int g_switch_value = 8;
371 /* Whether the -G option was used. */
372 static int g_switch_seen = 0;
377 /* If we can determine in advance that GP optimization won't be
378 possible, we can skip the relaxation stuff that tries to produce
379 GP-relative references. This makes delay slot optimization work
382 This function can only provide a guess, but it seems to work for
383 gcc output. It needs to guess right for gcc, otherwise gcc
384 will put what it thinks is a GP-relative instruction in a branch
387 I don't know if a fix is needed for the SVR4_PIC mode. I've only
388 fixed it for the non-PIC mode. KR 95/04/07 */
389 static int nopic_need_relax PARAMS ((symbolS *, int));
391 /* handle of the OPCODE hash table */
392 static struct hash_control *op_hash = NULL;
394 /* The opcode hash table we use for the mips16. */
395 static struct hash_control *mips16_op_hash = NULL;
397 /* This array holds the chars that always start a comment. If the
398 pre-processor is disabled, these aren't very useful */
399 const char comment_chars[] = "#";
401 /* This array holds the chars that only start a comment at the beginning of
402 a line. If the line seems to have the form '# 123 filename'
403 .line and .file directives will appear in the pre-processed output */
404 /* Note that input_file.c hand checks for '#' at the beginning of the
405 first line of the input file. This is because the compiler outputs
406 #NO_APP at the beginning of its output. */
407 /* Also note that C style comments are always supported. */
408 const char line_comment_chars[] = "#";
410 /* This array holds machine specific line separator characters. */
411 const char line_separator_chars[] = ";";
413 /* Chars that can be used to separate mant from exp in floating point nums */
414 const char EXP_CHARS[] = "eE";
416 /* Chars that mean this number is a floating point constant */
419 const char FLT_CHARS[] = "rRsSfFdDxXpP";
421 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
422 changed in read.c . Ideally it shouldn't have to know about it at all,
423 but nothing is ideal around here.
426 static char *insn_error;
428 static int auto_align = 1;
430 /* When outputting SVR4 PIC code, the assembler needs to know the
431 offset in the stack frame from which to restore the $gp register.
432 This is set by the .cprestore pseudo-op, and saved in this
434 static offsetT mips_cprestore_offset = -1;
436 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
437 more optimizations, it can use a register value instead of a memory-saved
438 offset and even an other register than $gp as global pointer. */
439 static offsetT mips_cpreturn_offset = -1;
440 static int mips_cpreturn_register = -1;
441 static int mips_gp_register = GP;
442 static int mips_gprel_offset = 0;
444 /* Whether mips_cprestore_offset has been set in the current function
445 (or whether it has already been warned about, if not). */
446 static int mips_cprestore_valid = 0;
448 /* This is the register which holds the stack frame, as set by the
449 .frame pseudo-op. This is needed to implement .cprestore. */
450 static int mips_frame_reg = SP;
452 /* Whether mips_frame_reg has been set in the current function
453 (or whether it has already been warned about, if not). */
454 static int mips_frame_reg_valid = 0;
456 /* To output NOP instructions correctly, we need to keep information
457 about the previous two instructions. */
459 /* Whether we are optimizing. The default value of 2 means to remove
460 unneeded NOPs and swap branch instructions when possible. A value
461 of 1 means to not swap branches. A value of 0 means to always
463 static int mips_optimize = 2;
465 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
466 equivalent to seeing no -g option at all. */
467 static int mips_debug = 0;
469 /* The previous instruction. */
470 static struct mips_cl_insn prev_insn;
472 /* The instruction before prev_insn. */
473 static struct mips_cl_insn prev_prev_insn;
475 /* If we don't want information for prev_insn or prev_prev_insn, we
476 point the insn_mo field at this dummy integer. */
477 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
479 /* Non-zero if prev_insn is valid. */
480 static int prev_insn_valid;
482 /* The frag for the previous instruction. */
483 static struct frag *prev_insn_frag;
485 /* The offset into prev_insn_frag for the previous instruction. */
486 static long prev_insn_where;
488 /* The reloc type for the previous instruction, if any. */
489 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
491 /* The reloc for the previous instruction, if any. */
492 static fixS *prev_insn_fixp[3];
494 /* Non-zero if the previous instruction was in a delay slot. */
495 static int prev_insn_is_delay_slot;
497 /* Non-zero if the previous instruction was in a .set noreorder. */
498 static int prev_insn_unreordered;
500 /* Non-zero if the previous instruction uses an extend opcode (if
502 static int prev_insn_extended;
504 /* Non-zero if the previous previous instruction was in a .set
506 static int prev_prev_insn_unreordered;
508 /* If this is set, it points to a frag holding nop instructions which
509 were inserted before the start of a noreorder section. If those
510 nops turn out to be unnecessary, the size of the frag can be
512 static fragS *prev_nop_frag;
514 /* The number of nop instructions we created in prev_nop_frag. */
515 static int prev_nop_frag_holds;
517 /* The number of nop instructions that we know we need in
519 static int prev_nop_frag_required;
521 /* The number of instructions we've seen since prev_nop_frag. */
522 static int prev_nop_frag_since;
524 /* For ECOFF and ELF, relocations against symbols are done in two
525 parts, with a HI relocation and a LO relocation. Each relocation
526 has only 16 bits of space to store an addend. This means that in
527 order for the linker to handle carries correctly, it must be able
528 to locate both the HI and the LO relocation. This means that the
529 relocations must appear in order in the relocation table.
531 In order to implement this, we keep track of each unmatched HI
532 relocation. We then sort them so that they immediately precede the
533 corresponding LO relocation. */
538 struct mips_hi_fixup *next;
541 /* The section this fixup is in. */
545 /* The list of unmatched HI relocs. */
547 static struct mips_hi_fixup *mips_hi_fixup_list;
549 /* Map normal MIPS register numbers to mips16 register numbers. */
551 #define X ILLEGAL_REG
552 static const int mips32_to_16_reg_map[] =
554 X, X, 2, 3, 4, 5, 6, 7,
555 X, X, X, X, X, X, X, X,
556 0, 1, X, X, X, X, X, X,
557 X, X, X, X, X, X, X, X
561 /* Map mips16 register numbers to normal MIPS register numbers. */
563 static const unsigned int mips16_to_32_reg_map[] =
565 16, 17, 2, 3, 4, 5, 6, 7
568 /* Since the MIPS does not have multiple forms of PC relative
569 instructions, we do not have to do relaxing as is done on other
570 platforms. However, we do have to handle GP relative addressing
571 correctly, which turns out to be a similar problem.
573 Every macro that refers to a symbol can occur in (at least) two
574 forms, one with GP relative addressing and one without. For
575 example, loading a global variable into a register generally uses
576 a macro instruction like this:
578 If i can be addressed off the GP register (this is true if it is in
579 the .sbss or .sdata section, or if it is known to be smaller than
580 the -G argument) this will generate the following instruction:
582 This instruction will use a GPREL reloc. If i can not be addressed
583 off the GP register, the following instruction sequence will be used:
586 In this case the first instruction will have a HI16 reloc, and the
587 second reloc will have a LO16 reloc. Both relocs will be against
590 The issue here is that we may not know whether i is GP addressable
591 until after we see the instruction that uses it. Therefore, we
592 want to be able to choose the final instruction sequence only at
593 the end of the assembly. This is similar to the way other
594 platforms choose the size of a PC relative instruction only at the
597 When generating position independent code we do not use GP
598 addressing in quite the same way, but the issue still arises as
599 external symbols and local symbols must be handled differently.
601 We handle these issues by actually generating both possible
602 instruction sequences. The longer one is put in a frag_var with
603 type rs_machine_dependent. We encode what to do with the frag in
604 the subtype field. We encode (1) the number of existing bytes to
605 replace, (2) the number of new bytes to use, (3) the offset from
606 the start of the existing bytes to the first reloc we must generate
607 (that is, the offset is applied from the start of the existing
608 bytes after they are replaced by the new bytes, if any), (4) the
609 offset from the start of the existing bytes to the second reloc,
610 (5) whether a third reloc is needed (the third reloc is always four
611 bytes after the second reloc), and (6) whether to warn if this
612 variant is used (this is sometimes needed if .set nomacro or .set
613 noat is in effect). All these numbers are reasonably small.
615 Generating two instruction sequences must be handled carefully to
616 ensure that delay slots are handled correctly. Fortunately, there
617 are a limited number of cases. When the second instruction
618 sequence is generated, append_insn is directed to maintain the
619 existing delay slot information, so it continues to apply to any
620 code after the second instruction sequence. This means that the
621 second instruction sequence must not impose any requirements not
622 required by the first instruction sequence.
624 These variant frags are then handled in functions called by the
625 machine independent code. md_estimate_size_before_relax returns
626 the final size of the frag. md_convert_frag sets up the final form
627 of the frag. tc_gen_reloc adjust the first reloc and adds a second
629 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
633 | (((reloc1) + 64) << 9) \
634 | (((reloc2) + 64) << 2) \
635 | ((reloc3) ? (1 << 1) : 0) \
637 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
638 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
639 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
640 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
641 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
642 #define RELAX_WARN(i) ((i) & 1)
644 /* For mips16 code, we use an entirely different form of relaxation.
645 mips16 supports two versions of most instructions which take
646 immediate values: a small one which takes some small value, and a
647 larger one which takes a 16 bit value. Since branches also follow
648 this pattern, relaxing these values is required.
650 We can assemble both mips16 and normal MIPS code in a single
651 object. Therefore, we need to support this type of relaxation at
652 the same time that we support the relaxation described above. We
653 use the high bit of the subtype field to distinguish these cases.
655 The information we store for this type of relaxation is the
656 argument code found in the opcode file for this relocation, whether
657 the user explicitly requested a small or extended form, and whether
658 the relocation is in a jump or jal delay slot. That tells us the
659 size of the value, and how it should be stored. We also store
660 whether the fragment is considered to be extended or not. We also
661 store whether this is known to be a branch to a different section,
662 whether we have tried to relax this frag yet, and whether we have
663 ever extended a PC relative fragment because of a shift count. */
664 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
667 | ((small) ? 0x100 : 0) \
668 | ((ext) ? 0x200 : 0) \
669 | ((dslot) ? 0x400 : 0) \
670 | ((jal_dslot) ? 0x800 : 0))
671 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
672 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
673 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
674 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
675 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
676 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
677 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
678 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
679 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
680 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
681 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
682 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
684 /* Prototypes for static functions. */
687 #define internalError() \
688 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
690 #define internalError() as_fatal (_("MIPS internal Error"));
693 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
695 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
696 unsigned int reg, enum mips_regclass class));
697 static int reg_needs_delay PARAMS ((unsigned int));
698 static void mips16_mark_labels PARAMS ((void));
699 static void append_insn PARAMS ((char *place,
700 struct mips_cl_insn * ip,
702 bfd_reloc_code_real_type *r,
704 static void mips_no_prev_insn PARAMS ((int));
705 static void mips_emit_delays PARAMS ((boolean));
707 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
708 const char *name, const char *fmt,
711 static void macro_build ();
713 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
714 const char *, const char *,
716 static void macro_build_jalr PARAMS ((int, expressionS *));
717 static void macro_build_lui PARAMS ((char *place, int *counter,
718 expressionS * ep, int regnum));
719 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
720 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
722 static void load_register PARAMS ((int *, int, expressionS *, int));
723 static void load_address PARAMS ((int *, int, expressionS *, int *));
724 static void move_register PARAMS ((int *, int, int));
725 static void macro PARAMS ((struct mips_cl_insn * ip));
726 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
727 #ifdef LOSING_COMPILER
728 static void macro2 PARAMS ((struct mips_cl_insn * ip));
730 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
731 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
732 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
733 boolean, boolean, unsigned long *,
734 boolean *, unsigned short *));
735 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
736 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
737 static int my_getSmallExpression PARAMS ((expressionS *, char *));
738 static void my_getExpression PARAMS ((expressionS *, char *));
740 static int support_64bit_objects PARAMS((void));
742 static symbolS *get_symbol PARAMS ((void));
743 static void mips_align PARAMS ((int to, int fill, symbolS *label));
744 static void s_align PARAMS ((int));
745 static void s_change_sec PARAMS ((int));
746 static void s_cons PARAMS ((int));
747 static void s_float_cons PARAMS ((int));
748 static void s_mips_globl PARAMS ((int));
749 static void s_option PARAMS ((int));
750 static void s_mipsset PARAMS ((int));
751 static void s_abicalls PARAMS ((int));
752 static void s_cpload PARAMS ((int));
753 static void s_cpsetup PARAMS ((int));
754 static void s_cplocal PARAMS ((int));
755 static void s_cprestore PARAMS ((int));
756 static void s_cpreturn PARAMS ((int));
757 static void s_gpvalue PARAMS ((int));
758 static void s_gpword PARAMS ((int));
759 static void s_cpadd PARAMS ((int));
760 static void s_insn PARAMS ((int));
761 static void md_obj_begin PARAMS ((void));
762 static void md_obj_end PARAMS ((void));
763 static long get_number PARAMS ((void));
764 static void s_mips_ent PARAMS ((int));
765 static void s_mips_end PARAMS ((int));
766 static void s_mips_frame PARAMS ((int));
767 static void s_mips_mask PARAMS ((int));
768 static void s_mips_stab PARAMS ((int));
769 static void s_mips_weakext PARAMS ((int));
770 static void s_mips_file PARAMS ((int));
771 static void s_mips_loc PARAMS ((int));
772 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
773 static const char *mips_isa_to_str PARAMS ((int));
774 static const char *mips_cpu_to_str PARAMS ((int));
775 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
776 static void show PARAMS ((FILE *, char *, int *, int *));
778 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
781 /* Return values of my_getSmallExpression(). */
788 /* Direct relocation creation by %percent_op(). */
807 /* Table and functions used to map between CPU/ISA names, and
808 ISA levels, and CPU numbers. */
812 const char *name; /* CPU or ISA name. */
813 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
814 int isa; /* ISA level. */
815 int cpu; /* CPU number (default CPU if ISA). */
818 static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *));
819 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
820 static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
824 The following pseudo-ops from the Kane and Heinrich MIPS book
825 should be defined here, but are currently unsupported: .alias,
826 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
828 The following pseudo-ops from the Kane and Heinrich MIPS book are
829 specific to the type of debugging information being generated, and
830 should be defined by the object format: .aent, .begin, .bend,
831 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
834 The following pseudo-ops from the Kane and Heinrich MIPS book are
835 not MIPS CPU specific, but are also not specific to the object file
836 format. This file is probably the best place to define them, but
837 they are not currently supported: .asm0, .endr, .lab, .repeat,
840 static const pseudo_typeS mips_pseudo_table[] =
842 /* MIPS specific pseudo-ops. */
843 {"option", s_option, 0},
844 {"set", s_mipsset, 0},
845 {"rdata", s_change_sec, 'r'},
846 {"sdata", s_change_sec, 's'},
847 {"livereg", s_ignore, 0},
848 {"abicalls", s_abicalls, 0},
849 {"cpload", s_cpload, 0},
850 {"cpsetup", s_cpsetup, 0},
851 {"cplocal", s_cplocal, 0},
852 {"cprestore", s_cprestore, 0},
853 {"cpreturn", s_cpreturn, 0},
854 {"gpvalue", s_gpvalue, 0},
855 {"gpword", s_gpword, 0},
856 {"cpadd", s_cpadd, 0},
859 /* Relatively generic pseudo-ops that happen to be used on MIPS
861 {"asciiz", stringer, 1},
862 {"bss", s_change_sec, 'b'},
865 {"dword", s_cons, 3},
866 {"weakext", s_mips_weakext, 0},
868 /* These pseudo-ops are defined in read.c, but must be overridden
869 here for one reason or another. */
870 {"align", s_align, 0},
872 {"data", s_change_sec, 'd'},
873 {"double", s_float_cons, 'd'},
874 {"float", s_float_cons, 'f'},
875 {"globl", s_mips_globl, 0},
876 {"global", s_mips_globl, 0},
877 {"hword", s_cons, 1},
882 {"short", s_cons, 1},
883 {"single", s_float_cons, 'f'},
884 {"stabn", s_mips_stab, 'n'},
885 {"text", s_change_sec, 't'},
888 #ifdef MIPS_STABS_ELF
889 { "extern", ecoff_directive_extern, 0},
895 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
897 /* These pseudo-ops should be defined by the object file format.
898 However, a.out doesn't support them, so we have versions here. */
899 {"aent", s_mips_ent, 1},
900 {"bgnb", s_ignore, 0},
901 {"end", s_mips_end, 0},
902 {"endb", s_ignore, 0},
903 {"ent", s_mips_ent, 0},
904 {"file", s_mips_file, 0},
905 {"fmask", s_mips_mask, 'F'},
906 {"frame", s_mips_frame, 0},
907 {"loc", s_mips_loc, 0},
908 {"mask", s_mips_mask, 'R'},
909 {"verstamp", s_ignore, 0},
913 extern void pop_insert PARAMS ((const pseudo_typeS *));
918 pop_insert (mips_pseudo_table);
919 if (! ECOFF_DEBUGGING)
920 pop_insert (mips_nonecoff_pseudo_table);
923 /* Symbols labelling the current insn. */
925 struct insn_label_list
927 struct insn_label_list *next;
931 static struct insn_label_list *insn_labels;
932 static struct insn_label_list *free_insn_labels;
934 static void mips_clear_insn_labels PARAMS ((void));
937 mips_clear_insn_labels ()
939 register struct insn_label_list **pl;
941 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
947 static char *expr_end;
949 /* Expressions which appear in instructions. These are set by
952 static expressionS imm_expr;
953 static expressionS offset_expr;
955 /* Relocs associated with imm_expr and offset_expr. */
957 static bfd_reloc_code_real_type imm_reloc[3]
958 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
959 static bfd_reloc_code_real_type offset_reloc[3]
960 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
962 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
964 static boolean imm_unmatched_hi;
966 /* These are set by mips16_ip if an explicit extension is used. */
968 static boolean mips16_small, mips16_ext;
970 #ifdef MIPS_STABS_ELF
971 /* The pdr segment for per procedure frame/regmask info */
977 mips_isa_to_str (isa)
980 const struct mips_cpu_info *ci;
983 ci = mips_cpu_info_from_isa (isa);
987 sprintf (s, "ISA#%d", isa);
992 mips_cpu_to_str (cpu)
995 const struct mips_cpu_info *ci;
998 ci = mips_cpu_info_from_cpu (cpu);
1002 sprintf (s, "CPU#%d", cpu);
1006 /* The default target format to use. */
1009 mips_target_format ()
1011 switch (OUTPUT_FLAVOR)
1013 case bfd_target_aout_flavour:
1014 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1015 case bfd_target_ecoff_flavour:
1016 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1017 case bfd_target_coff_flavour:
1019 case bfd_target_elf_flavour:
1021 /* This is traditional mips */
1022 return (target_big_endian
1023 ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips"
1024 : "elf32-tradbigmips")
1025 : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips"
1026 : "elf32-tradlittlemips"));
1028 return (target_big_endian
1029 ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips")
1030 : (HAVE_64BIT_OBJECTS ? "elf64-littlemips"
1031 : "elf32-littlemips"));
1039 /* This function is called once, at assembler startup time. It should
1040 set up all the tables, etc. that the MD part of the assembler will need. */
1045 register const char *retval = NULL;
1049 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1050 as_warn (_("Could not set architecture and machine"));
1052 op_hash = hash_new ();
1054 for (i = 0; i < NUMOPCODES;)
1056 const char *name = mips_opcodes[i].name;
1058 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1061 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1062 mips_opcodes[i].name, retval);
1063 /* Probably a memory allocation problem? Give up now. */
1064 as_fatal (_("Broken assembler. No assembly attempted."));
1068 if (mips_opcodes[i].pinfo != INSN_MACRO)
1070 if (!validate_mips_insn (&mips_opcodes[i]))
1075 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1078 mips16_op_hash = hash_new ();
1081 while (i < bfd_mips16_num_opcodes)
1083 const char *name = mips16_opcodes[i].name;
1085 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1087 as_fatal (_("internal: can't hash `%s': %s"),
1088 mips16_opcodes[i].name, retval);
1091 if (mips16_opcodes[i].pinfo != INSN_MACRO
1092 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1093 != mips16_opcodes[i].match))
1095 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1096 mips16_opcodes[i].name, mips16_opcodes[i].args);
1101 while (i < bfd_mips16_num_opcodes
1102 && strcmp (mips16_opcodes[i].name, name) == 0);
1106 as_fatal (_("Broken assembler. No assembly attempted."));
1108 /* We add all the general register names to the symbol table. This
1109 helps us detect invalid uses of them. */
1110 for (i = 0; i < 32; i++)
1114 sprintf (buf, "$%d", i);
1115 symbol_table_insert (symbol_new (buf, reg_section, i,
1116 &zero_address_frag));
1118 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1119 &zero_address_frag));
1120 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1121 &zero_address_frag));
1122 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1123 &zero_address_frag));
1124 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1125 &zero_address_frag));
1126 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1127 &zero_address_frag));
1128 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1129 &zero_address_frag));
1130 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1131 &zero_address_frag));
1132 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1133 &zero_address_frag));
1134 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1135 &zero_address_frag));
1137 mips_no_prev_insn (false);
1140 mips_cprmask[0] = 0;
1141 mips_cprmask[1] = 0;
1142 mips_cprmask[2] = 0;
1143 mips_cprmask[3] = 0;
1145 /* set the default alignment for the text section (2**2) */
1146 record_alignment (text_section, 2);
1148 if (USE_GLOBAL_POINTER_OPT)
1149 bfd_set_gp_size (stdoutput, g_switch_value);
1151 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1153 /* On a native system, sections must be aligned to 16 byte
1154 boundaries. When configured for an embedded ELF target, we
1156 if (strcmp (TARGET_OS, "elf") != 0)
1158 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1159 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1160 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1163 /* Create a .reginfo section for register masks and a .mdebug
1164 section for debugging information. */
1172 subseg = now_subseg;
1174 /* The ABI says this section should be loaded so that the
1175 running program can access it. However, we don't load it
1176 if we are configured for an embedded target */
1177 flags = SEC_READONLY | SEC_DATA;
1178 if (strcmp (TARGET_OS, "elf") != 0)
1179 flags |= SEC_ALLOC | SEC_LOAD;
1181 if (file_mips_abi != N64_ABI)
1183 sec = subseg_new (".reginfo", (subsegT) 0);
1185 bfd_set_section_flags (stdoutput, sec, flags);
1186 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1189 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1194 /* The 64-bit ABI uses a .MIPS.options section rather than
1195 .reginfo section. */
1196 sec = subseg_new (".MIPS.options", (subsegT) 0);
1197 bfd_set_section_flags (stdoutput, sec, flags);
1198 bfd_set_section_alignment (stdoutput, sec, 3);
1201 /* Set up the option header. */
1203 Elf_Internal_Options opthdr;
1206 opthdr.kind = ODK_REGINFO;
1207 opthdr.size = (sizeof (Elf_External_Options)
1208 + sizeof (Elf64_External_RegInfo));
1211 f = frag_more (sizeof (Elf_External_Options));
1212 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1213 (Elf_External_Options *) f);
1215 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1220 if (ECOFF_DEBUGGING)
1222 sec = subseg_new (".mdebug", (subsegT) 0);
1223 (void) bfd_set_section_flags (stdoutput, sec,
1224 SEC_HAS_CONTENTS | SEC_READONLY);
1225 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1228 #ifdef MIPS_STABS_ELF
1229 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1230 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1231 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
1232 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1235 subseg_set (seg, subseg);
1239 if (! ECOFF_DEBUGGING)
1246 if (! ECOFF_DEBUGGING)
1254 struct mips_cl_insn insn;
1255 bfd_reloc_code_real_type unused_reloc[3]
1256 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1258 imm_expr.X_op = O_absent;
1259 imm_unmatched_hi = false;
1260 offset_expr.X_op = O_absent;
1261 imm_reloc[0] = BFD_RELOC_UNUSED;
1262 imm_reloc[1] = BFD_RELOC_UNUSED;
1263 imm_reloc[2] = BFD_RELOC_UNUSED;
1264 offset_reloc[0] = BFD_RELOC_UNUSED;
1265 offset_reloc[1] = BFD_RELOC_UNUSED;
1266 offset_reloc[2] = BFD_RELOC_UNUSED;
1268 if (mips_opts.mips16)
1269 mips16_ip (str, &insn);
1272 mips_ip (str, &insn);
1273 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1274 str, insn.insn_opcode));
1279 as_bad ("%s `%s'", insn_error, str);
1283 if (insn.insn_mo->pinfo == INSN_MACRO)
1285 if (mips_opts.mips16)
1286 mips16_macro (&insn);
1292 if (imm_expr.X_op != O_absent)
1293 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1294 else if (offset_expr.X_op != O_absent)
1295 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1297 append_insn (NULL, &insn, NULL, unused_reloc, false);
1301 /* See whether instruction IP reads register REG. CLASS is the type
1305 insn_uses_reg (ip, reg, class)
1306 struct mips_cl_insn *ip;
1308 enum mips_regclass class;
1310 if (class == MIPS16_REG)
1312 assert (mips_opts.mips16);
1313 reg = mips16_to_32_reg_map[reg];
1314 class = MIPS_GR_REG;
1317 /* Don't report on general register ZERO, since it never changes. */
1318 if (class == MIPS_GR_REG && reg == ZERO)
1321 if (class == MIPS_FP_REG)
1323 assert (! mips_opts.mips16);
1324 /* If we are called with either $f0 or $f1, we must check $f0.
1325 This is not optimal, because it will introduce an unnecessary
1326 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1327 need to distinguish reading both $f0 and $f1 or just one of
1328 them. Note that we don't have to check the other way,
1329 because there is no instruction that sets both $f0 and $f1
1330 and requires a delay. */
1331 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1332 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1333 == (reg &~ (unsigned) 1)))
1335 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1336 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1337 == (reg &~ (unsigned) 1)))
1340 else if (! mips_opts.mips16)
1342 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1343 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1345 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1346 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1351 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1352 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1353 & MIPS16OP_MASK_RX)]
1356 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1357 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1358 & MIPS16OP_MASK_RY)]
1361 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1362 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1363 & MIPS16OP_MASK_MOVE32Z)]
1366 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1368 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1370 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1372 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1373 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1374 & MIPS16OP_MASK_REGR32) == reg)
1381 /* This function returns true if modifying a register requires a
1385 reg_needs_delay (reg)
1388 unsigned long prev_pinfo;
1390 prev_pinfo = prev_insn.insn_mo->pinfo;
1391 if (! mips_opts.noreorder
1392 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1393 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1394 || (! gpr_interlocks
1395 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1397 /* A load from a coprocessor or from memory. All load
1398 delays delay the use of general register rt for one
1399 instruction on the r3000. The r6000 and r4000 use
1401 /* Itbl support may require additional care here. */
1402 know (prev_pinfo & INSN_WRITE_GPR_T);
1403 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1410 /* Mark instruction labels in mips16 mode. This permits the linker to
1411 handle them specially, such as generating jalx instructions when
1412 needed. We also make them odd for the duration of the assembly, in
1413 order to generate the right sort of code. We will make them even
1414 in the adjust_symtab routine, while leaving them marked. This is
1415 convenient for the debugger and the disassembler. The linker knows
1416 to make them odd again. */
1419 mips16_mark_labels ()
1421 if (mips_opts.mips16)
1423 struct insn_label_list *l;
1426 for (l = insn_labels; l != NULL; l = l->next)
1429 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1430 S_SET_OTHER (l->label, STO_MIPS16);
1432 val = S_GET_VALUE (l->label);
1434 S_SET_VALUE (l->label, val + 1);
1439 /* Output an instruction. PLACE is where to put the instruction; if
1440 it is NULL, this uses frag_more to get room. IP is the instruction
1441 information. ADDRESS_EXPR is an operand of the instruction to be
1442 used with RELOC_TYPE. */
1445 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1447 struct mips_cl_insn *ip;
1448 expressionS *address_expr;
1449 bfd_reloc_code_real_type *reloc_type;
1450 boolean unmatched_hi;
1452 register unsigned long prev_pinfo, pinfo;
1457 /* Mark instruction labels in mips16 mode. */
1458 mips16_mark_labels ();
1460 prev_pinfo = prev_insn.insn_mo->pinfo;
1461 pinfo = ip->insn_mo->pinfo;
1463 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1467 /* If the previous insn required any delay slots, see if we need
1468 to insert a NOP or two. There are eight kinds of possible
1469 hazards, of which an instruction can have at most one type.
1470 (1) a load from memory delay
1471 (2) a load from a coprocessor delay
1472 (3) an unconditional branch delay
1473 (4) a conditional branch delay
1474 (5) a move to coprocessor register delay
1475 (6) a load coprocessor register from memory delay
1476 (7) a coprocessor condition code delay
1477 (8) a HI/LO special register delay
1479 There are a lot of optimizations we could do that we don't.
1480 In particular, we do not, in general, reorder instructions.
1481 If you use gcc with optimization, it will reorder
1482 instructions and generally do much more optimization then we
1483 do here; repeating all that work in the assembler would only
1484 benefit hand written assembly code, and does not seem worth
1487 /* This is how a NOP is emitted. */
1488 #define emit_nop() \
1490 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1491 : md_number_to_chars (frag_more (4), 0, 4))
1493 /* The previous insn might require a delay slot, depending upon
1494 the contents of the current insn. */
1495 if (! mips_opts.mips16
1496 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1497 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1498 && ! cop_interlocks)
1499 || (! gpr_interlocks
1500 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1502 /* A load from a coprocessor or from memory. All load
1503 delays delay the use of general register rt for one
1504 instruction on the r3000. The r6000 and r4000 use
1506 /* Itbl support may require additional care here. */
1507 know (prev_pinfo & INSN_WRITE_GPR_T);
1508 if (mips_optimize == 0
1509 || insn_uses_reg (ip,
1510 ((prev_insn.insn_opcode >> OP_SH_RT)
1515 else if (! mips_opts.mips16
1516 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1517 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1518 && ! cop_interlocks)
1519 || (mips_opts.isa == ISA_MIPS1
1520 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1522 /* A generic coprocessor delay. The previous instruction
1523 modified a coprocessor general or control register. If
1524 it modified a control register, we need to avoid any
1525 coprocessor instruction (this is probably not always
1526 required, but it sometimes is). If it modified a general
1527 register, we avoid using that register.
1529 On the r6000 and r4000 loading a coprocessor register
1530 from memory is interlocked, and does not require a delay.
1532 This case is not handled very well. There is no special
1533 knowledge of CP0 handling, and the coprocessors other
1534 than the floating point unit are not distinguished at
1536 /* Itbl support may require additional care here. FIXME!
1537 Need to modify this to include knowledge about
1538 user specified delays! */
1539 if (prev_pinfo & INSN_WRITE_FPR_T)
1541 if (mips_optimize == 0
1542 || insn_uses_reg (ip,
1543 ((prev_insn.insn_opcode >> OP_SH_FT)
1548 else if (prev_pinfo & INSN_WRITE_FPR_S)
1550 if (mips_optimize == 0
1551 || insn_uses_reg (ip,
1552 ((prev_insn.insn_opcode >> OP_SH_FS)
1559 /* We don't know exactly what the previous instruction
1560 does. If the current instruction uses a coprocessor
1561 register, we must insert a NOP. If previous
1562 instruction may set the condition codes, and the
1563 current instruction uses them, we must insert two
1565 /* Itbl support may require additional care here. */
1566 if (mips_optimize == 0
1567 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1568 && (pinfo & INSN_READ_COND_CODE)))
1570 else if (pinfo & INSN_COP)
1574 else if (! mips_opts.mips16
1575 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1576 && (prev_pinfo & INSN_WRITE_COND_CODE)
1577 && ! cop_interlocks)
1579 /* The previous instruction sets the coprocessor condition
1580 codes, but does not require a general coprocessor delay
1581 (this means it is a floating point comparison
1582 instruction). If this instruction uses the condition
1583 codes, we need to insert a single NOP. */
1584 /* Itbl support may require additional care here. */
1585 if (mips_optimize == 0
1586 || (pinfo & INSN_READ_COND_CODE))
1590 /* If we're fixing up mfhi/mflo for the r7000 and the
1591 previous insn was an mfhi/mflo and the current insn
1592 reads the register that the mfhi/mflo wrote to, then
1595 else if (mips_7000_hilo_fix
1596 && MF_HILO_INSN (prev_pinfo)
1597 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1604 /* If we're fixing up mfhi/mflo for the r7000 and the
1605 2nd previous insn was an mfhi/mflo and the current insn
1606 reads the register that the mfhi/mflo wrote to, then
1609 else if (mips_7000_hilo_fix
1610 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1611 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1619 else if (prev_pinfo & INSN_READ_LO)
1621 /* The previous instruction reads the LO register; if the
1622 current instruction writes to the LO register, we must
1623 insert two NOPS. Some newer processors have interlocks.
1624 Also the tx39's multiply instructions can be exectuted
1625 immediatly after a read from HI/LO (without the delay),
1626 though the tx39's divide insns still do require the
1628 if (! (hilo_interlocks
1629 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1630 && (mips_optimize == 0
1631 || (pinfo & INSN_WRITE_LO)))
1633 /* Most mips16 branch insns don't have a delay slot.
1634 If a read from LO is immediately followed by a branch
1635 to a write to LO we have a read followed by a write
1636 less than 2 insns away. We assume the target of
1637 a branch might be a write to LO, and insert a nop
1638 between a read and an immediately following branch. */
1639 else if (mips_opts.mips16
1640 && (mips_optimize == 0
1641 || (pinfo & MIPS16_INSN_BRANCH)))
1644 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1646 /* The previous instruction reads the HI register; if the
1647 current instruction writes to the HI register, we must
1648 insert a NOP. Some newer processors have interlocks.
1649 Also the note tx39's multiply above. */
1650 if (! (hilo_interlocks
1651 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1652 && (mips_optimize == 0
1653 || (pinfo & INSN_WRITE_HI)))
1655 /* Most mips16 branch insns don't have a delay slot.
1656 If a read from HI is immediately followed by a branch
1657 to a write to HI we have a read followed by a write
1658 less than 2 insns away. We assume the target of
1659 a branch might be a write to HI, and insert a nop
1660 between a read and an immediately following branch. */
1661 else if (mips_opts.mips16
1662 && (mips_optimize == 0
1663 || (pinfo & MIPS16_INSN_BRANCH)))
1667 /* If the previous instruction was in a noreorder section, then
1668 we don't want to insert the nop after all. */
1669 /* Itbl support may require additional care here. */
1670 if (prev_insn_unreordered)
1673 /* There are two cases which require two intervening
1674 instructions: 1) setting the condition codes using a move to
1675 coprocessor instruction which requires a general coprocessor
1676 delay and then reading the condition codes 2) reading the HI
1677 or LO register and then writing to it (except on processors
1678 which have interlocks). If we are not already emitting a NOP
1679 instruction, we must check for these cases compared to the
1680 instruction previous to the previous instruction. */
1681 if ((! mips_opts.mips16
1682 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1683 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1684 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1685 && (pinfo & INSN_READ_COND_CODE)
1686 && ! cop_interlocks)
1687 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1688 && (pinfo & INSN_WRITE_LO)
1689 && ! (hilo_interlocks
1690 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1691 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1692 && (pinfo & INSN_WRITE_HI)
1693 && ! (hilo_interlocks
1694 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1699 if (prev_prev_insn_unreordered)
1702 if (prev_prev_nop && nops == 0)
1705 /* If we are being given a nop instruction, don't bother with
1706 one of the nops we would otherwise output. This will only
1707 happen when a nop instruction is used with mips_optimize set
1710 && ! mips_opts.noreorder
1711 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1714 /* Now emit the right number of NOP instructions. */
1715 if (nops > 0 && ! mips_opts.noreorder)
1718 unsigned long old_frag_offset;
1720 struct insn_label_list *l;
1722 old_frag = frag_now;
1723 old_frag_offset = frag_now_fix ();
1725 for (i = 0; i < nops; i++)
1730 listing_prev_line ();
1731 /* We may be at the start of a variant frag. In case we
1732 are, make sure there is enough space for the frag
1733 after the frags created by listing_prev_line. The
1734 argument to frag_grow here must be at least as large
1735 as the argument to all other calls to frag_grow in
1736 this file. We don't have to worry about being in the
1737 middle of a variant frag, because the variants insert
1738 all needed nop instructions themselves. */
1742 for (l = insn_labels; l != NULL; l = l->next)
1746 assert (S_GET_SEGMENT (l->label) == now_seg);
1747 symbol_set_frag (l->label, frag_now);
1748 val = (valueT) frag_now_fix ();
1749 /* mips16 text labels are stored as odd. */
1750 if (mips_opts.mips16)
1752 S_SET_VALUE (l->label, val);
1755 #ifndef NO_ECOFF_DEBUGGING
1756 if (ECOFF_DEBUGGING)
1757 ecoff_fix_loc (old_frag, old_frag_offset);
1760 else if (prev_nop_frag != NULL)
1762 /* We have a frag holding nops we may be able to remove. If
1763 we don't need any nops, we can decrease the size of
1764 prev_nop_frag by the size of one instruction. If we do
1765 need some nops, we count them in prev_nops_required. */
1766 if (prev_nop_frag_since == 0)
1770 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1771 --prev_nop_frag_holds;
1774 prev_nop_frag_required += nops;
1778 if (prev_prev_nop == 0)
1780 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1781 --prev_nop_frag_holds;
1784 ++prev_nop_frag_required;
1787 if (prev_nop_frag_holds <= prev_nop_frag_required)
1788 prev_nop_frag = NULL;
1790 ++prev_nop_frag_since;
1792 /* Sanity check: by the time we reach the second instruction
1793 after prev_nop_frag, we should have used up all the nops
1794 one way or another. */
1795 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1799 if (*reloc_type > BFD_RELOC_UNUSED)
1801 /* We need to set up a variant frag. */
1802 assert (mips_opts.mips16 && address_expr != NULL);
1803 f = frag_var (rs_machine_dependent, 4, 0,
1804 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1805 mips16_small, mips16_ext,
1807 & INSN_UNCOND_BRANCH_DELAY),
1808 (*prev_insn_reloc_type
1809 == BFD_RELOC_MIPS16_JMP)),
1810 make_expr_symbol (address_expr), 0, NULL);
1812 else if (place != NULL)
1814 else if (mips_opts.mips16
1816 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1818 /* Make sure there is enough room to swap this instruction with
1819 a following jump instruction. */
1825 if (mips_opts.mips16
1826 && mips_opts.noreorder
1827 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1828 as_warn (_("extended instruction in delay slot"));
1833 fixp[0] = fixp[1] = fixp[2] = NULL;
1834 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1836 if (address_expr->X_op == O_constant)
1840 switch (*reloc_type)
1843 ip->insn_opcode |= address_expr->X_add_number;
1846 case BFD_RELOC_MIPS_HIGHEST:
1847 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
1849 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1852 case BFD_RELOC_MIPS_HIGHER:
1853 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
1854 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1857 case BFD_RELOC_HI16_S:
1858 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
1862 case BFD_RELOC_HI16:
1863 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
1866 case BFD_RELOC_LO16:
1867 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1870 case BFD_RELOC_MIPS_JMP:
1871 if ((address_expr->X_add_number & 3) != 0)
1872 as_bad (_("jump to misaligned address (0x%lx)"),
1873 (unsigned long) address_expr->X_add_number);
1874 if (address_expr->X_add_number & ~0xfffffff
1875 || address_expr->X_add_number > 0x7fffffc)
1876 as_bad (_("jump address range overflow (0x%lx)"),
1877 (unsigned long) address_expr->X_add_number);
1878 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
1881 case BFD_RELOC_MIPS16_JMP:
1882 if ((address_expr->X_add_number & 3) != 0)
1883 as_bad (_("jump to misaligned address (0x%lx)"),
1884 (unsigned long) address_expr->X_add_number);
1885 if (address_expr->X_add_number & ~0xfffffff
1886 || address_expr->X_add_number > 0x7fffffc)
1887 as_bad (_("jump address range overflow (0x%lx)"),
1888 (unsigned long) address_expr->X_add_number);
1890 (((address_expr->X_add_number & 0x7c0000) << 3)
1891 | ((address_expr->X_add_number & 0xf800000) >> 7)
1892 | ((address_expr->X_add_number & 0x3fffc) >> 2));
1895 case BFD_RELOC_16_PCREL:
1896 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1899 case BFD_RELOC_16_PCREL_S2:
1909 /* Don't generate a reloc if we are writing into a variant frag. */
1912 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1914 (*reloc_type == BFD_RELOC_16_PCREL
1915 || *reloc_type == BFD_RELOC_16_PCREL_S2),
1918 /* These relocations can have an addend that won't fit in
1919 4 octets for 64bit assembly. */
1920 if (HAVE_64BIT_GPRS &&
1921 (*reloc_type == BFD_RELOC_16
1922 || *reloc_type == BFD_RELOC_32
1923 || *reloc_type == BFD_RELOC_MIPS_JMP
1924 || *reloc_type == BFD_RELOC_HI16_S
1925 || *reloc_type == BFD_RELOC_LO16
1926 || *reloc_type == BFD_RELOC_GPREL16
1927 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1928 || *reloc_type == BFD_RELOC_GPREL32
1929 || *reloc_type == BFD_RELOC_64
1930 || *reloc_type == BFD_RELOC_CTOR
1931 || *reloc_type == BFD_RELOC_MIPS_SUB
1932 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1933 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1934 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1935 || *reloc_type == BFD_RELOC_MIPS_REL16
1936 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1937 fixp[0]->fx_no_overflow = 1;
1941 struct mips_hi_fixup *hi_fixup;
1943 assert (*reloc_type == BFD_RELOC_HI16_S);
1944 hi_fixup = ((struct mips_hi_fixup *)
1945 xmalloc (sizeof (struct mips_hi_fixup)));
1946 hi_fixup->fixp = fixp[0];
1947 hi_fixup->seg = now_seg;
1948 hi_fixup->next = mips_hi_fixup_list;
1949 mips_hi_fixup_list = hi_fixup;
1952 if (reloc_type[1] != BFD_RELOC_UNUSED)
1954 /* FIXME: This symbol can be one of
1955 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1956 address_expr->X_op = O_absent;
1957 address_expr->X_add_symbol = 0;
1958 address_expr->X_add_number = 0;
1960 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
1961 4, address_expr, false,
1964 /* These relocations can have an addend that won't fit in
1965 4 octets for 64bit assembly. */
1966 if (HAVE_64BIT_GPRS &&
1967 (*reloc_type == BFD_RELOC_16
1968 || *reloc_type == BFD_RELOC_32
1969 || *reloc_type == BFD_RELOC_MIPS_JMP
1970 || *reloc_type == BFD_RELOC_HI16_S
1971 || *reloc_type == BFD_RELOC_LO16
1972 || *reloc_type == BFD_RELOC_GPREL16
1973 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1974 || *reloc_type == BFD_RELOC_GPREL32
1975 || *reloc_type == BFD_RELOC_64
1976 || *reloc_type == BFD_RELOC_CTOR
1977 || *reloc_type == BFD_RELOC_MIPS_SUB
1978 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1979 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1980 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1981 || *reloc_type == BFD_RELOC_MIPS_REL16
1982 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1983 fixp[1]->fx_no_overflow = 1;
1985 if (reloc_type[2] != BFD_RELOC_UNUSED)
1987 address_expr->X_op = O_absent;
1988 address_expr->X_add_symbol = 0;
1989 address_expr->X_add_number = 0;
1991 fixp[2] = fix_new_exp (frag_now,
1992 f - frag_now->fr_literal, 4,
1993 address_expr, false,
1996 /* These relocations can have an addend that won't fit in
1997 4 octets for 64bit assembly. */
1998 if (HAVE_64BIT_GPRS &&
1999 (*reloc_type == BFD_RELOC_16
2000 || *reloc_type == BFD_RELOC_32
2001 || *reloc_type == BFD_RELOC_MIPS_JMP
2002 || *reloc_type == BFD_RELOC_HI16_S
2003 || *reloc_type == BFD_RELOC_LO16
2004 || *reloc_type == BFD_RELOC_GPREL16
2005 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2006 || *reloc_type == BFD_RELOC_GPREL32
2007 || *reloc_type == BFD_RELOC_64
2008 || *reloc_type == BFD_RELOC_CTOR
2009 || *reloc_type == BFD_RELOC_MIPS_SUB
2010 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2011 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2012 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2013 || *reloc_type == BFD_RELOC_MIPS_REL16
2014 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2015 fixp[2]->fx_no_overflow = 1;
2022 if (! mips_opts.mips16)
2024 md_number_to_chars (f, ip->insn_opcode, 4);
2026 dwarf2_emit_insn (4);
2029 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2031 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2032 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2034 dwarf2_emit_insn (4);
2041 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2044 md_number_to_chars (f, ip->insn_opcode, 2);
2046 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2050 /* Update the register mask information. */
2051 if (! mips_opts.mips16)
2053 if (pinfo & INSN_WRITE_GPR_D)
2054 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2055 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2056 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2057 if (pinfo & INSN_READ_GPR_S)
2058 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2059 if (pinfo & INSN_WRITE_GPR_31)
2060 mips_gprmask |= 1 << RA;
2061 if (pinfo & INSN_WRITE_FPR_D)
2062 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2063 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2064 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2065 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2066 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2067 if ((pinfo & INSN_READ_FPR_R) != 0)
2068 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2069 if (pinfo & INSN_COP)
2071 /* We don't keep enough information to sort these cases out.
2072 The itbl support does keep this information however, although
2073 we currently don't support itbl fprmats as part of the cop
2074 instruction. May want to add this support in the future. */
2076 /* Never set the bit for $0, which is always zero. */
2077 mips_gprmask &= ~1 << 0;
2081 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2082 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2083 & MIPS16OP_MASK_RX);
2084 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2085 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2086 & MIPS16OP_MASK_RY);
2087 if (pinfo & MIPS16_INSN_WRITE_Z)
2088 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2089 & MIPS16OP_MASK_RZ);
2090 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2091 mips_gprmask |= 1 << TREG;
2092 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2093 mips_gprmask |= 1 << SP;
2094 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2095 mips_gprmask |= 1 << RA;
2096 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2097 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2098 if (pinfo & MIPS16_INSN_READ_Z)
2099 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2100 & MIPS16OP_MASK_MOVE32Z);
2101 if (pinfo & MIPS16_INSN_READ_GPR_X)
2102 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2103 & MIPS16OP_MASK_REGR32);
2106 if (place == NULL && ! mips_opts.noreorder)
2108 /* Filling the branch delay slot is more complex. We try to
2109 switch the branch with the previous instruction, which we can
2110 do if the previous instruction does not set up a condition
2111 that the branch tests and if the branch is not itself the
2112 target of any branch. */
2113 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2114 || (pinfo & INSN_COND_BRANCH_DELAY))
2116 if (mips_optimize < 2
2117 /* If we have seen .set volatile or .set nomove, don't
2119 || mips_opts.nomove != 0
2120 /* If we had to emit any NOP instructions, then we
2121 already know we can not swap. */
2123 /* If we don't even know the previous insn, we can not
2125 || ! prev_insn_valid
2126 /* If the previous insn is already in a branch delay
2127 slot, then we can not swap. */
2128 || prev_insn_is_delay_slot
2129 /* If the previous previous insn was in a .set
2130 noreorder, we can't swap. Actually, the MIPS
2131 assembler will swap in this situation. However, gcc
2132 configured -with-gnu-as will generate code like
2138 in which we can not swap the bne and INSN. If gcc is
2139 not configured -with-gnu-as, it does not output the
2140 .set pseudo-ops. We don't have to check
2141 prev_insn_unreordered, because prev_insn_valid will
2142 be 0 in that case. We don't want to use
2143 prev_prev_insn_valid, because we do want to be able
2144 to swap at the start of a function. */
2145 || prev_prev_insn_unreordered
2146 /* If the branch is itself the target of a branch, we
2147 can not swap. We cheat on this; all we check for is
2148 whether there is a label on this instruction. If
2149 there are any branches to anything other than a
2150 label, users must use .set noreorder. */
2151 || insn_labels != NULL
2152 /* If the previous instruction is in a variant frag, we
2153 can not do the swap. This does not apply to the
2154 mips16, which uses variant frags for different
2156 || (! mips_opts.mips16
2157 && prev_insn_frag->fr_type == rs_machine_dependent)
2158 /* If the branch reads the condition codes, we don't
2159 even try to swap, because in the sequence
2164 we can not swap, and I don't feel like handling that
2166 || (! mips_opts.mips16
2167 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2168 && (pinfo & INSN_READ_COND_CODE))
2169 /* We can not swap with an instruction that requires a
2170 delay slot, becase the target of the branch might
2171 interfere with that instruction. */
2172 || (! mips_opts.mips16
2173 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2175 /* Itbl support may require additional care here. */
2176 & (INSN_LOAD_COPROC_DELAY
2177 | INSN_COPROC_MOVE_DELAY
2178 | INSN_WRITE_COND_CODE)))
2179 || (! (hilo_interlocks
2180 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2184 || (! mips_opts.mips16
2186 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2187 || (! mips_opts.mips16
2188 && mips_opts.isa == ISA_MIPS1
2189 /* Itbl support may require additional care here. */
2190 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2191 /* We can not swap with a branch instruction. */
2193 & (INSN_UNCOND_BRANCH_DELAY
2194 | INSN_COND_BRANCH_DELAY
2195 | INSN_COND_BRANCH_LIKELY))
2196 /* We do not swap with a trap instruction, since it
2197 complicates trap handlers to have the trap
2198 instruction be in a delay slot. */
2199 || (prev_pinfo & INSN_TRAP)
2200 /* If the branch reads a register that the previous
2201 instruction sets, we can not swap. */
2202 || (! mips_opts.mips16
2203 && (prev_pinfo & INSN_WRITE_GPR_T)
2204 && insn_uses_reg (ip,
2205 ((prev_insn.insn_opcode >> OP_SH_RT)
2208 || (! mips_opts.mips16
2209 && (prev_pinfo & INSN_WRITE_GPR_D)
2210 && insn_uses_reg (ip,
2211 ((prev_insn.insn_opcode >> OP_SH_RD)
2214 || (mips_opts.mips16
2215 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2216 && insn_uses_reg (ip,
2217 ((prev_insn.insn_opcode
2219 & MIPS16OP_MASK_RX),
2221 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2222 && insn_uses_reg (ip,
2223 ((prev_insn.insn_opcode
2225 & MIPS16OP_MASK_RY),
2227 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2228 && insn_uses_reg (ip,
2229 ((prev_insn.insn_opcode
2231 & MIPS16OP_MASK_RZ),
2233 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2234 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2235 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2236 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2237 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2238 && insn_uses_reg (ip,
2239 MIPS16OP_EXTRACT_REG32R (prev_insn.
2242 /* If the branch writes a register that the previous
2243 instruction sets, we can not swap (we know that
2244 branches write only to RD or to $31). */
2245 || (! mips_opts.mips16
2246 && (prev_pinfo & INSN_WRITE_GPR_T)
2247 && (((pinfo & INSN_WRITE_GPR_D)
2248 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2249 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2250 || ((pinfo & INSN_WRITE_GPR_31)
2251 && (((prev_insn.insn_opcode >> OP_SH_RT)
2254 || (! mips_opts.mips16
2255 && (prev_pinfo & INSN_WRITE_GPR_D)
2256 && (((pinfo & INSN_WRITE_GPR_D)
2257 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2258 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2259 || ((pinfo & INSN_WRITE_GPR_31)
2260 && (((prev_insn.insn_opcode >> OP_SH_RD)
2263 || (mips_opts.mips16
2264 && (pinfo & MIPS16_INSN_WRITE_31)
2265 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2266 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2267 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2269 /* If the branch writes a register that the previous
2270 instruction reads, we can not swap (we know that
2271 branches only write to RD or to $31). */
2272 || (! mips_opts.mips16
2273 && (pinfo & INSN_WRITE_GPR_D)
2274 && insn_uses_reg (&prev_insn,
2275 ((ip->insn_opcode >> OP_SH_RD)
2278 || (! mips_opts.mips16
2279 && (pinfo & INSN_WRITE_GPR_31)
2280 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2281 || (mips_opts.mips16
2282 && (pinfo & MIPS16_INSN_WRITE_31)
2283 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2284 /* If we are generating embedded PIC code, the branch
2285 might be expanded into a sequence which uses $at, so
2286 we can't swap with an instruction which reads it. */
2287 || (mips_pic == EMBEDDED_PIC
2288 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2289 /* If the previous previous instruction has a load
2290 delay, and sets a register that the branch reads, we
2292 || (! mips_opts.mips16
2293 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2294 /* Itbl support may require additional care here. */
2295 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2296 || (! gpr_interlocks
2297 && (prev_prev_insn.insn_mo->pinfo
2298 & INSN_LOAD_MEMORY_DELAY)))
2299 && insn_uses_reg (ip,
2300 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2303 /* If one instruction sets a condition code and the
2304 other one uses a condition code, we can not swap. */
2305 || ((pinfo & INSN_READ_COND_CODE)
2306 && (prev_pinfo & INSN_WRITE_COND_CODE))
2307 || ((pinfo & INSN_WRITE_COND_CODE)
2308 && (prev_pinfo & INSN_READ_COND_CODE))
2309 /* If the previous instruction uses the PC, we can not
2311 || (mips_opts.mips16
2312 && (prev_pinfo & MIPS16_INSN_READ_PC))
2313 /* If the previous instruction was extended, we can not
2315 || (mips_opts.mips16 && prev_insn_extended)
2316 /* If the previous instruction had a fixup in mips16
2317 mode, we can not swap. This normally means that the
2318 previous instruction was a 4 byte branch anyhow. */
2319 || (mips_opts.mips16 && prev_insn_fixp[0])
2320 /* If the previous instruction is a sync, sync.l, or
2321 sync.p, we can not swap. */
2322 || (prev_pinfo & INSN_SYNC))
2324 /* We could do even better for unconditional branches to
2325 portions of this object file; we could pick up the
2326 instruction at the destination, put it in the delay
2327 slot, and bump the destination address. */
2329 /* Update the previous insn information. */
2330 prev_prev_insn = *ip;
2331 prev_insn.insn_mo = &dummy_opcode;
2335 /* It looks like we can actually do the swap. */
2336 if (! mips_opts.mips16)
2341 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2342 memcpy (temp, prev_f, 4);
2343 memcpy (prev_f, f, 4);
2344 memcpy (f, temp, 4);
2345 if (prev_insn_fixp[0])
2347 prev_insn_fixp[0]->fx_frag = frag_now;
2348 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2350 if (prev_insn_fixp[1])
2352 prev_insn_fixp[1]->fx_frag = frag_now;
2353 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2355 if (prev_insn_fixp[2])
2357 prev_insn_fixp[2]->fx_frag = frag_now;
2358 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2362 fixp[0]->fx_frag = prev_insn_frag;
2363 fixp[0]->fx_where = prev_insn_where;
2367 fixp[1]->fx_frag = prev_insn_frag;
2368 fixp[1]->fx_where = prev_insn_where;
2372 fixp[2]->fx_frag = prev_insn_frag;
2373 fixp[2]->fx_where = prev_insn_where;
2381 assert (prev_insn_fixp[0] == NULL);
2382 assert (prev_insn_fixp[1] == NULL);
2383 assert (prev_insn_fixp[2] == NULL);
2384 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2385 memcpy (temp, prev_f, 2);
2386 memcpy (prev_f, f, 2);
2387 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2389 assert (*reloc_type == BFD_RELOC_UNUSED);
2390 memcpy (f, temp, 2);
2394 memcpy (f, f + 2, 2);
2395 memcpy (f + 2, temp, 2);
2399 fixp[0]->fx_frag = prev_insn_frag;
2400 fixp[0]->fx_where = prev_insn_where;
2404 fixp[1]->fx_frag = prev_insn_frag;
2405 fixp[1]->fx_where = prev_insn_where;
2409 fixp[2]->fx_frag = prev_insn_frag;
2410 fixp[2]->fx_where = prev_insn_where;
2414 /* Update the previous insn information; leave prev_insn
2416 prev_prev_insn = *ip;
2418 prev_insn_is_delay_slot = 1;
2420 /* If that was an unconditional branch, forget the previous
2421 insn information. */
2422 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2424 prev_prev_insn.insn_mo = &dummy_opcode;
2425 prev_insn.insn_mo = &dummy_opcode;
2428 prev_insn_fixp[0] = NULL;
2429 prev_insn_fixp[1] = NULL;
2430 prev_insn_fixp[2] = NULL;
2431 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2432 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2433 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2434 prev_insn_extended = 0;
2436 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2438 /* We don't yet optimize a branch likely. What we should do
2439 is look at the target, copy the instruction found there
2440 into the delay slot, and increment the branch to jump to
2441 the next instruction. */
2443 /* Update the previous insn information. */
2444 prev_prev_insn = *ip;
2445 prev_insn.insn_mo = &dummy_opcode;
2446 prev_insn_fixp[0] = NULL;
2447 prev_insn_fixp[1] = NULL;
2448 prev_insn_fixp[2] = NULL;
2449 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2450 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2451 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2452 prev_insn_extended = 0;
2456 /* Update the previous insn information. */
2458 prev_prev_insn.insn_mo = &dummy_opcode;
2460 prev_prev_insn = prev_insn;
2463 /* Any time we see a branch, we always fill the delay slot
2464 immediately; since this insn is not a branch, we know it
2465 is not in a delay slot. */
2466 prev_insn_is_delay_slot = 0;
2468 prev_insn_fixp[0] = fixp[0];
2469 prev_insn_fixp[1] = fixp[1];
2470 prev_insn_fixp[2] = fixp[2];
2471 prev_insn_reloc_type[0] = reloc_type[0];
2472 prev_insn_reloc_type[1] = reloc_type[1];
2473 prev_insn_reloc_type[2] = reloc_type[2];
2474 if (mips_opts.mips16)
2475 prev_insn_extended = (ip->use_extend
2476 || *reloc_type > BFD_RELOC_UNUSED);
2479 prev_prev_insn_unreordered = prev_insn_unreordered;
2480 prev_insn_unreordered = 0;
2481 prev_insn_frag = frag_now;
2482 prev_insn_where = f - frag_now->fr_literal;
2483 prev_insn_valid = 1;
2485 else if (place == NULL)
2487 /* We need to record a bit of information even when we are not
2488 reordering, in order to determine the base address for mips16
2489 PC relative relocs. */
2490 prev_prev_insn = prev_insn;
2492 prev_insn_reloc_type[0] = reloc_type[0];
2493 prev_insn_reloc_type[1] = reloc_type[1];
2494 prev_insn_reloc_type[2] = reloc_type[2];
2495 prev_prev_insn_unreordered = prev_insn_unreordered;
2496 prev_insn_unreordered = 1;
2499 /* We just output an insn, so the next one doesn't have a label. */
2500 mips_clear_insn_labels ();
2502 /* We must ensure that a fixup associated with an unmatched %hi
2503 reloc does not become a variant frag. Otherwise, the
2504 rearrangement of %hi relocs in frob_file may confuse
2508 frag_wane (frag_now);
2513 /* This function forgets that there was any previous instruction or
2514 label. If PRESERVE is non-zero, it remembers enough information to
2515 know whether nops are needed before a noreorder section. */
2518 mips_no_prev_insn (preserve)
2523 prev_insn.insn_mo = &dummy_opcode;
2524 prev_prev_insn.insn_mo = &dummy_opcode;
2525 prev_nop_frag = NULL;
2526 prev_nop_frag_holds = 0;
2527 prev_nop_frag_required = 0;
2528 prev_nop_frag_since = 0;
2530 prev_insn_valid = 0;
2531 prev_insn_is_delay_slot = 0;
2532 prev_insn_unreordered = 0;
2533 prev_insn_extended = 0;
2534 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2535 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2536 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2537 prev_prev_insn_unreordered = 0;
2538 mips_clear_insn_labels ();
2541 /* This function must be called whenever we turn on noreorder or emit
2542 something other than instructions. It inserts any NOPS which might
2543 be needed by the previous instruction, and clears the information
2544 kept for the previous instructions. The INSNS parameter is true if
2545 instructions are to follow. */
2548 mips_emit_delays (insns)
2551 if (! mips_opts.noreorder)
2556 if ((! mips_opts.mips16
2557 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2558 && (! cop_interlocks
2559 && (prev_insn.insn_mo->pinfo
2560 & (INSN_LOAD_COPROC_DELAY
2561 | INSN_COPROC_MOVE_DELAY
2562 | INSN_WRITE_COND_CODE))))
2563 || (! hilo_interlocks
2564 && (prev_insn.insn_mo->pinfo
2567 || (! mips_opts.mips16
2569 && (prev_insn.insn_mo->pinfo
2570 & INSN_LOAD_MEMORY_DELAY))
2571 || (! mips_opts.mips16
2572 && mips_opts.isa == ISA_MIPS1
2573 && (prev_insn.insn_mo->pinfo
2574 & INSN_COPROC_MEMORY_DELAY)))
2576 /* Itbl support may require additional care here. */
2578 if ((! mips_opts.mips16
2579 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2580 && (! cop_interlocks
2581 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2582 || (! hilo_interlocks
2583 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2584 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2587 if (prev_insn_unreordered)
2590 else if ((! mips_opts.mips16
2591 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2592 && (! cop_interlocks
2593 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2594 || (! hilo_interlocks
2595 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2596 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2598 /* Itbl support may require additional care here. */
2599 if (! prev_prev_insn_unreordered)
2605 struct insn_label_list *l;
2609 /* Record the frag which holds the nop instructions, so
2610 that we can remove them if we don't need them. */
2611 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2612 prev_nop_frag = frag_now;
2613 prev_nop_frag_holds = nops;
2614 prev_nop_frag_required = 0;
2615 prev_nop_frag_since = 0;
2618 for (; nops > 0; --nops)
2623 /* Move on to a new frag, so that it is safe to simply
2624 decrease the size of prev_nop_frag. */
2625 frag_wane (frag_now);
2629 for (l = insn_labels; l != NULL; l = l->next)
2633 assert (S_GET_SEGMENT (l->label) == now_seg);
2634 symbol_set_frag (l->label, frag_now);
2635 val = (valueT) frag_now_fix ();
2636 /* mips16 text labels are stored as odd. */
2637 if (mips_opts.mips16)
2639 S_SET_VALUE (l->label, val);
2644 /* Mark instruction labels in mips16 mode. */
2646 mips16_mark_labels ();
2648 mips_no_prev_insn (insns);
2651 /* Build an instruction created by a macro expansion. This is passed
2652 a pointer to the count of instructions created so far, an
2653 expression, the name of the instruction to build, an operand format
2654 string, and corresponding arguments. */
2658 macro_build (char *place,
2666 macro_build (place, counter, ep, name, fmt, va_alist)
2675 struct mips_cl_insn insn;
2676 bfd_reloc_code_real_type r[3];
2680 va_start (args, fmt);
2686 * If the macro is about to expand into a second instruction,
2687 * print a warning if needed. We need to pass ip as a parameter
2688 * to generate a better warning message here...
2690 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2691 as_warn (_("Macro instruction expanded into multiple instructions"));
2694 * If the macro is about to expand into a second instruction,
2695 * and it is in a delay slot, print a warning.
2699 && mips_opts.noreorder
2700 && (prev_prev_insn.insn_mo->pinfo
2701 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2702 | INSN_COND_BRANCH_LIKELY)) != 0)
2703 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2706 ++*counter; /* bump instruction counter */
2708 if (mips_opts.mips16)
2710 mips16_macro_build (place, counter, ep, name, fmt, args);
2715 r[0] = BFD_RELOC_UNUSED;
2716 r[1] = BFD_RELOC_UNUSED;
2717 r[2] = BFD_RELOC_UNUSED;
2718 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2719 assert (insn.insn_mo);
2720 assert (strcmp (name, insn.insn_mo->name) == 0);
2722 /* Search until we get a match for NAME. */
2725 /* It is assumed here that macros will never generate
2726 MDMX or MIPS-3D instructions. */
2727 if (strcmp (fmt, insn.insn_mo->args) == 0
2728 && insn.insn_mo->pinfo != INSN_MACRO
2729 && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
2730 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2734 assert (insn.insn_mo->name);
2735 assert (strcmp (name, insn.insn_mo->name) == 0);
2738 insn.insn_opcode = insn.insn_mo->match;
2754 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2758 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2763 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2768 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2773 int tmp = va_arg (args, int);
2775 insn.insn_opcode |= tmp << OP_SH_RT;
2776 insn.insn_opcode |= tmp << OP_SH_RD;
2782 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2789 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2793 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2797 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2801 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2805 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2812 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2818 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2819 assert (*r == BFD_RELOC_GPREL16
2820 || *r == BFD_RELOC_MIPS_LITERAL
2821 || *r == BFD_RELOC_MIPS_HIGHER
2822 || *r == BFD_RELOC_HI16_S
2823 || *r == BFD_RELOC_LO16
2824 || *r == BFD_RELOC_MIPS_GOT16
2825 || *r == BFD_RELOC_MIPS_CALL16
2826 || *r == BFD_RELOC_MIPS_GOT_DISP
2827 || *r == BFD_RELOC_MIPS_GOT_PAGE
2828 || *r == BFD_RELOC_MIPS_GOT_OFST
2829 || *r == BFD_RELOC_MIPS_GOT_LO16
2830 || *r == BFD_RELOC_MIPS_CALL_LO16
2831 || (ep->X_op == O_subtract
2832 && *r == BFD_RELOC_PCREL_LO16));
2836 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2838 && (ep->X_op == O_constant
2839 || (ep->X_op == O_symbol
2840 && (*r == BFD_RELOC_MIPS_HIGHEST
2841 || *r == BFD_RELOC_HI16_S
2842 || *r == BFD_RELOC_HI16
2843 || *r == BFD_RELOC_GPREL16
2844 || *r == BFD_RELOC_MIPS_GOT_HI16
2845 || *r == BFD_RELOC_MIPS_CALL_HI16))
2846 || (ep->X_op == O_subtract
2847 && *r == BFD_RELOC_PCREL_HI16_S)));
2851 assert (ep != NULL);
2853 * This allows macro() to pass an immediate expression for
2854 * creating short branches without creating a symbol.
2855 * Note that the expression still might come from the assembly
2856 * input, in which case the value is not checked for range nor
2857 * is a relocation entry generated (yuck).
2859 if (ep->X_op == O_constant)
2861 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2865 if (mips_pic == EMBEDDED_PIC)
2866 *r = BFD_RELOC_16_PCREL_S2;
2868 *r = BFD_RELOC_16_PCREL;
2872 assert (ep != NULL);
2873 *r = BFD_RELOC_MIPS_JMP;
2877 insn.insn_opcode |= va_arg (args, unsigned long);
2886 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2888 append_insn (place, &insn, ep, r, false);
2892 mips16_macro_build (place, counter, ep, name, fmt, args)
2894 int *counter ATTRIBUTE_UNUSED;
2900 struct mips_cl_insn insn;
2901 bfd_reloc_code_real_type r[3]
2902 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2904 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
2905 assert (insn.insn_mo);
2906 assert (strcmp (name, insn.insn_mo->name) == 0);
2908 while (strcmp (fmt, insn.insn_mo->args) != 0
2909 || insn.insn_mo->pinfo == INSN_MACRO)
2912 assert (insn.insn_mo->name);
2913 assert (strcmp (name, insn.insn_mo->name) == 0);
2916 insn.insn_opcode = insn.insn_mo->match;
2917 insn.use_extend = false;
2936 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
2941 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
2945 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
2949 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
2959 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
2966 regno = va_arg (args, int);
2967 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
2968 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
2989 assert (ep != NULL);
2991 if (ep->X_op != O_constant)
2992 *r = (int) BFD_RELOC_UNUSED + c;
2995 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
2996 false, &insn.insn_opcode, &insn.use_extend,
2999 *r = BFD_RELOC_UNUSED;
3005 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3012 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3014 append_insn (place, &insn, ep, r, false);
3018 * Generate a "jalr" instruction with a relocation hint to the called
3019 * function. This occurs in NewABI PIC code.
3022 macro_build_jalr (icnt, ep)
3028 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3031 fix_new_exp (frag_now, 0, 0, ep, false, BFD_RELOC_MIPS_JALR);
3035 * Generate a "lui" instruction.
3038 macro_build_lui (place, counter, ep, regnum)
3044 expressionS high_expr;
3045 struct mips_cl_insn insn;
3046 bfd_reloc_code_real_type r[3]
3047 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3048 const char *name = "lui";
3049 const char *fmt = "t,u";
3051 assert (! mips_opts.mips16);
3057 high_expr.X_op = O_constant;
3058 high_expr.X_add_number = ep->X_add_number;
3061 if (high_expr.X_op == O_constant)
3063 /* we can compute the instruction now without a relocation entry */
3064 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3066 *r = BFD_RELOC_UNUSED;
3068 else if (! HAVE_NEWABI)
3070 assert (ep->X_op == O_symbol);
3071 /* _gp_disp is a special case, used from s_cpload. */
3072 assert (mips_pic == NO_PIC
3073 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3074 *r = BFD_RELOC_HI16_S;
3078 * If the macro is about to expand into a second instruction,
3079 * print a warning if needed. We need to pass ip as a parameter
3080 * to generate a better warning message here...
3082 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3083 as_warn (_("Macro instruction expanded into multiple instructions"));
3086 ++*counter; /* bump instruction counter */
3088 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3089 assert (insn.insn_mo);
3090 assert (strcmp (name, insn.insn_mo->name) == 0);
3091 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3093 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3094 if (*r == BFD_RELOC_UNUSED)
3096 insn.insn_opcode |= high_expr.X_add_number;
3097 append_insn (place, &insn, NULL, r, false);
3100 append_insn (place, &insn, &high_expr, r, false);
3104 * Generates code to set the $at register to true (one)
3105 * if reg is less than the immediate expression.
3108 set_at (counter, reg, unsignedp)
3113 if (imm_expr.X_op == O_constant
3114 && imm_expr.X_add_number >= -0x8000
3115 && imm_expr.X_add_number < 0x8000)
3116 macro_build ((char *) NULL, counter, &imm_expr,
3117 unsignedp ? "sltiu" : "slti",
3118 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3121 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3122 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3123 unsignedp ? "sltu" : "slt",
3124 "d,v,t", AT, reg, AT);
3128 /* Warn if an expression is not a constant. */
3131 check_absolute_expr (ip, ex)
3132 struct mips_cl_insn *ip;
3135 if (ex->X_op == O_big)
3136 as_bad (_("unsupported large constant"));
3137 else if (ex->X_op != O_constant)
3138 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3141 /* Count the leading zeroes by performing a binary chop. This is a
3142 bulky bit of source, but performance is a LOT better for the
3143 majority of values than a simple loop to count the bits:
3144 for (lcnt = 0; (lcnt < 32); lcnt++)
3145 if ((v) & (1 << (31 - lcnt)))
3147 However it is not code size friendly, and the gain will drop a bit
3148 on certain cached systems.
3150 #define COUNT_TOP_ZEROES(v) \
3151 (((v) & ~0xffff) == 0 \
3152 ? ((v) & ~0xff) == 0 \
3153 ? ((v) & ~0xf) == 0 \
3154 ? ((v) & ~0x3) == 0 \
3155 ? ((v) & ~0x1) == 0 \
3160 : ((v) & ~0x7) == 0 \
3163 : ((v) & ~0x3f) == 0 \
3164 ? ((v) & ~0x1f) == 0 \
3167 : ((v) & ~0x7f) == 0 \
3170 : ((v) & ~0xfff) == 0 \
3171 ? ((v) & ~0x3ff) == 0 \
3172 ? ((v) & ~0x1ff) == 0 \
3175 : ((v) & ~0x7ff) == 0 \
3178 : ((v) & ~0x3fff) == 0 \
3179 ? ((v) & ~0x1fff) == 0 \
3182 : ((v) & ~0x7fff) == 0 \
3185 : ((v) & ~0xffffff) == 0 \
3186 ? ((v) & ~0xfffff) == 0 \
3187 ? ((v) & ~0x3ffff) == 0 \
3188 ? ((v) & ~0x1ffff) == 0 \
3191 : ((v) & ~0x7ffff) == 0 \
3194 : ((v) & ~0x3fffff) == 0 \
3195 ? ((v) & ~0x1fffff) == 0 \
3198 : ((v) & ~0x7fffff) == 0 \
3201 : ((v) & ~0xfffffff) == 0 \
3202 ? ((v) & ~0x3ffffff) == 0 \
3203 ? ((v) & ~0x1ffffff) == 0 \
3206 : ((v) & ~0x7ffffff) == 0 \
3209 : ((v) & ~0x3fffffff) == 0 \
3210 ? ((v) & ~0x1fffffff) == 0 \
3213 : ((v) & ~0x7fffffff) == 0 \
3217 /* Is the given value a sign-extended 32-bit value? */
3218 #define IS_SEXT_32BIT_NUM(x) \
3219 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3220 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3223 * This routine generates the least number of instructions neccessary to load
3224 * an absolute expression value into a register.
3227 load_register (counter, reg, ep, dbl)
3234 expressionS hi32, lo32;
3236 if (ep->X_op != O_big)
3238 assert (ep->X_op == O_constant);
3239 if (ep->X_add_number < 0x8000
3240 && (ep->X_add_number >= 0
3241 || (ep->X_add_number >= -0x8000
3244 || sizeof (ep->X_add_number) > 4))))
3246 /* We can handle 16 bit signed values with an addiu to
3247 $zero. No need to ever use daddiu here, since $zero and
3248 the result are always correct in 32 bit mode. */
3249 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3250 (int) BFD_RELOC_LO16);
3253 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3255 /* We can handle 16 bit unsigned values with an ori to
3257 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3258 (int) BFD_RELOC_LO16);
3261 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3264 || sizeof (ep->X_add_number) > 4
3265 || (ep->X_add_number & 0x80000000) == 0))
3266 || ((HAVE_32BIT_GPRS || ! dbl)
3267 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3270 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3271 == ~ (offsetT) 0xffffffff)))
3273 /* 32 bit values require an lui. */
3274 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3275 (int) BFD_RELOC_HI16);
3276 if ((ep->X_add_number & 0xffff) != 0)
3277 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3278 (int) BFD_RELOC_LO16);
3283 /* The value is larger than 32 bits. */
3285 if (HAVE_32BIT_GPRS)
3287 as_bad (_("Number (0x%lx) larger than 32 bits"),
3288 (unsigned long) ep->X_add_number);
3289 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3290 (int) BFD_RELOC_LO16);
3294 if (ep->X_op != O_big)
3297 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3298 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3299 hi32.X_add_number &= 0xffffffff;
3301 lo32.X_add_number &= 0xffffffff;
3305 assert (ep->X_add_number > 2);
3306 if (ep->X_add_number == 3)
3307 generic_bignum[3] = 0;
3308 else if (ep->X_add_number > 4)
3309 as_bad (_("Number larger than 64 bits"));
3310 lo32.X_op = O_constant;
3311 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3312 hi32.X_op = O_constant;
3313 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3316 if (hi32.X_add_number == 0)
3321 unsigned long hi, lo;
3323 if (hi32.X_add_number == (offsetT) 0xffffffff)
3325 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3327 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3328 reg, 0, (int) BFD_RELOC_LO16);
3331 if (lo32.X_add_number & 0x80000000)
3333 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3334 (int) BFD_RELOC_HI16);
3335 if (lo32.X_add_number & 0xffff)
3336 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3337 reg, reg, (int) BFD_RELOC_LO16);
3342 /* Check for 16bit shifted constant. We know that hi32 is
3343 non-zero, so start the mask on the first bit of the hi32
3348 unsigned long himask, lomask;
3352 himask = 0xffff >> (32 - shift);
3353 lomask = (0xffff << shift) & 0xffffffff;
3357 himask = 0xffff << (shift - 32);
3360 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3361 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3365 tmp.X_op = O_constant;
3367 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3368 | (lo32.X_add_number >> shift));
3370 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3371 macro_build ((char *) NULL, counter, &tmp,
3372 "ori", "t,r,i", reg, 0,
3373 (int) BFD_RELOC_LO16);
3374 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3375 (shift >= 32) ? "dsll32" : "dsll",
3377 (shift >= 32) ? shift - 32 : shift);
3382 while (shift <= (64 - 16));
3384 /* Find the bit number of the lowest one bit, and store the
3385 shifted value in hi/lo. */
3386 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3387 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3391 while ((lo & 1) == 0)
3396 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3402 while ((hi & 1) == 0)
3411 /* Optimize if the shifted value is a (power of 2) - 1. */
3412 if ((hi == 0 && ((lo + 1) & lo) == 0)
3413 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3415 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3420 /* This instruction will set the register to be all
3422 tmp.X_op = O_constant;
3423 tmp.X_add_number = (offsetT) -1;
3424 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3425 reg, 0, (int) BFD_RELOC_LO16);
3429 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3430 (bit >= 32) ? "dsll32" : "dsll",
3432 (bit >= 32) ? bit - 32 : bit);
3434 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3435 (shift >= 32) ? "dsrl32" : "dsrl",
3437 (shift >= 32) ? shift - 32 : shift);
3442 /* Sign extend hi32 before calling load_register, because we can
3443 generally get better code when we load a sign extended value. */
3444 if ((hi32.X_add_number & 0x80000000) != 0)
3445 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3446 load_register (counter, reg, &hi32, 0);
3449 if ((lo32.X_add_number & 0xffff0000) == 0)
3453 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3454 "dsll32", "d,w,<", reg, freg, 0);
3462 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3464 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3465 (int) BFD_RELOC_HI16);
3466 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3467 "dsrl32", "d,w,<", reg, reg, 0);
3473 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3474 "d,w,<", reg, freg, 16);
3478 mid16.X_add_number >>= 16;
3479 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3480 freg, (int) BFD_RELOC_LO16);
3481 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3482 "d,w,<", reg, reg, 16);
3485 if ((lo32.X_add_number & 0xffff) != 0)
3486 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3487 (int) BFD_RELOC_LO16);
3490 /* Load an address into a register. */
3493 load_address (counter, reg, ep, used_at)
3501 if (ep->X_op != O_constant
3502 && ep->X_op != O_symbol)
3504 as_bad (_("expression too complex"));
3505 ep->X_op = O_constant;
3508 if (ep->X_op == O_constant)
3510 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3514 if (mips_pic == NO_PIC)
3516 /* If this is a reference to a GP relative symbol, we want
3517 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3519 lui $reg,<sym> (BFD_RELOC_HI16_S)
3520 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3521 If we have an addend, we always use the latter form.
3523 With 64bit address space and a usable $at we want
3524 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3525 lui $at,<sym> (BFD_RELOC_HI16_S)
3526 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3527 daddiu $at,<sym> (BFD_RELOC_LO16)
3531 If $at is already in use, we use an path which is suboptimal
3532 on superscalar processors.
3533 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3534 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3536 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3538 daddiu $reg,<sym> (BFD_RELOC_LO16)
3540 if (HAVE_64BIT_ADDRESSES)
3542 /* We don't do GP optimization for now because RELAX_ENCODE can't
3543 hold the data for such large chunks. */
3547 macro_build (p, counter, ep, "lui", "t,u",
3548 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3549 macro_build (p, counter, ep, "lui", "t,u",
3550 AT, (int) BFD_RELOC_HI16_S);
3551 macro_build (p, counter, ep, "daddiu", "t,r,j",
3552 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3553 macro_build (p, counter, ep, "daddiu", "t,r,j",
3554 AT, AT, (int) BFD_RELOC_LO16);
3555 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3556 "d,w,<", reg, reg, 0);
3557 macro_build (p, counter, (expressionS *) NULL, "dadd",
3558 "d,v,t", reg, reg, AT);
3563 macro_build (p, counter, ep, "lui", "t,u",
3564 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3565 macro_build (p, counter, ep, "daddiu", "t,r,j",
3566 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3567 macro_build (p, counter, (expressionS *) NULL, "dsll",
3568 "d,w,<", reg, reg, 16);
3569 macro_build (p, counter, ep, "daddiu", "t,r,j",
3570 reg, reg, (int) BFD_RELOC_HI16_S);
3571 macro_build (p, counter, (expressionS *) NULL, "dsll",
3572 "d,w,<", reg, reg, 16);
3573 macro_build (p, counter, ep, "daddiu", "t,r,j",
3574 reg, reg, (int) BFD_RELOC_LO16);
3579 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3580 && ! nopic_need_relax (ep->X_add_symbol, 1))
3583 macro_build ((char *) NULL, counter, ep,
3584 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3585 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3586 p = frag_var (rs_machine_dependent, 8, 0,
3587 RELAX_ENCODE (4, 8, 0, 4, 0,
3588 mips_opts.warn_about_macros),
3589 ep->X_add_symbol, 0, NULL);
3591 macro_build_lui (p, counter, ep, reg);
3594 macro_build (p, counter, ep,
3595 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3596 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3599 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3603 /* If this is a reference to an external symbol, we want
3604 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3606 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3608 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3609 If there is a constant, it must be added in after. */
3610 ex.X_add_number = ep->X_add_number;
3611 ep->X_add_number = 0;
3613 macro_build ((char *) NULL, counter, ep,
3614 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3615 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3616 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3617 p = frag_var (rs_machine_dependent, 4, 0,
3618 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3619 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3620 macro_build (p, counter, ep,
3621 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3622 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3623 if (ex.X_add_number != 0)
3625 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3626 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3627 ex.X_op = O_constant;
3628 macro_build ((char *) NULL, counter, &ex,
3629 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3630 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3633 else if (mips_pic == SVR4_PIC)
3638 /* This is the large GOT case. If this is a reference to an
3639 external symbol, we want
3640 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3642 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3643 Otherwise, for a reference to a local symbol, we want
3644 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3646 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3647 If we have NewABI, we want
3648 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3649 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3650 If there is a constant, it must be added in after. */
3651 ex.X_add_number = ep->X_add_number;
3652 ep->X_add_number = 0;
3655 macro_build ((char *) NULL, counter, ep,
3656 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3657 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3658 macro_build (p, counter, ep,
3659 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3660 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3664 if (reg_needs_delay (mips_gp_register))
3669 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3670 (int) BFD_RELOC_MIPS_GOT_HI16);
3671 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3672 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3673 reg, mips_gp_register);
3674 macro_build ((char *) NULL, counter, ep,
3675 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3676 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3677 p = frag_var (rs_machine_dependent, 12 + off, 0,
3678 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3679 mips_opts.warn_about_macros),
3680 ep->X_add_symbol, 0, NULL);
3683 /* We need a nop before loading from $gp. This special
3684 check is required because the lui which starts the main
3685 instruction stream does not refer to $gp, and so will not
3686 insert the nop which may be required. */
3687 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3690 macro_build (p, counter, ep,
3691 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3692 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3694 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3696 macro_build (p, counter, ep,
3697 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3698 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3701 if (ex.X_add_number != 0)
3703 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3704 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3705 ex.X_op = O_constant;
3706 macro_build ((char *) NULL, counter, &ex,
3707 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3708 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3711 else if (mips_pic == EMBEDDED_PIC)
3714 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3716 macro_build ((char *) NULL, counter, ep,
3717 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3718 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3724 /* Move the contents of register SOURCE into register DEST. */
3727 move_register (counter, dest, source)
3732 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3733 HAVE_32BIT_GPRS ? "addu" : "daddu",
3734 "d,v,t", dest, source, 0);
3739 * This routine implements the seemingly endless macro or synthesized
3740 * instructions and addressing modes in the mips assembly language. Many
3741 * of these macros are simple and are similar to each other. These could
3742 * probably be handled by some kind of table or grammer aproach instead of
3743 * this verbose method. Others are not simple macros but are more like
3744 * optimizing code generation.
3745 * One interesting optimization is when several store macros appear
3746 * consecutivly that would load AT with the upper half of the same address.
3747 * The ensuing load upper instructions are ommited. This implies some kind
3748 * of global optimization. We currently only optimize within a single macro.
3749 * For many of the load and store macros if the address is specified as a
3750 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3751 * first load register 'at' with zero and use it as the base register. The
3752 * mips assembler simply uses register $zero. Just one tiny optimization
3757 struct mips_cl_insn *ip;
3759 register int treg, sreg, dreg, breg;
3775 bfd_reloc_code_real_type r;
3776 int hold_mips_optimize;
3778 assert (! mips_opts.mips16);
3780 treg = (ip->insn_opcode >> 16) & 0x1f;
3781 dreg = (ip->insn_opcode >> 11) & 0x1f;
3782 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3783 mask = ip->insn_mo->mask;
3785 expr1.X_op = O_constant;
3786 expr1.X_op_symbol = NULL;
3787 expr1.X_add_symbol = NULL;
3788 expr1.X_add_number = 1;
3800 mips_emit_delays (true);
3801 ++mips_opts.noreorder;
3802 mips_any_noreorder = 1;
3804 expr1.X_add_number = 8;
3805 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3807 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3810 move_register (&icnt, dreg, sreg);
3811 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3812 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3814 --mips_opts.noreorder;
3835 if (imm_expr.X_op == O_constant
3836 && imm_expr.X_add_number >= -0x8000
3837 && imm_expr.X_add_number < 0x8000)
3839 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3840 (int) BFD_RELOC_LO16);
3843 load_register (&icnt, AT, &imm_expr, dbl);
3844 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3864 if (imm_expr.X_op == O_constant
3865 && imm_expr.X_add_number >= 0
3866 && imm_expr.X_add_number < 0x10000)
3868 if (mask != M_NOR_I)
3869 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3870 sreg, (int) BFD_RELOC_LO16);
3873 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3874 treg, sreg, (int) BFD_RELOC_LO16);
3875 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
3876 "d,v,t", treg, treg, 0);
3881 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3882 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3900 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3902 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
3906 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3907 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
3915 macro_build ((char *) NULL, &icnt, &offset_expr,
3916 likely ? "bgezl" : "bgez", "s,p", sreg);
3921 macro_build ((char *) NULL, &icnt, &offset_expr,
3922 likely ? "blezl" : "blez", "s,p", treg);
3925 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
3927 macro_build ((char *) NULL, &icnt, &offset_expr,
3928 likely ? "beql" : "beq", "s,t,p", AT, 0);
3934 /* check for > max integer */
3935 maxnum = 0x7fffffff;
3936 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3943 if (imm_expr.X_op == O_constant
3944 && imm_expr.X_add_number >= maxnum
3945 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3948 /* result is always false */
3952 as_warn (_("Branch %s is always false (nop)"),
3954 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
3960 as_warn (_("Branch likely %s is always false"),
3962 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
3967 if (imm_expr.X_op != O_constant)
3968 as_bad (_("Unsupported large constant"));
3969 ++imm_expr.X_add_number;
3973 if (mask == M_BGEL_I)
3975 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3977 macro_build ((char *) NULL, &icnt, &offset_expr,
3978 likely ? "bgezl" : "bgez", "s,p", sreg);
3981 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3983 macro_build ((char *) NULL, &icnt, &offset_expr,
3984 likely ? "bgtzl" : "bgtz", "s,p", sreg);
3987 maxnum = 0x7fffffff;
3988 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3995 maxnum = - maxnum - 1;
3996 if (imm_expr.X_op == O_constant
3997 && imm_expr.X_add_number <= maxnum
3998 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4001 /* result is always true */
4002 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4003 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4006 set_at (&icnt, sreg, 0);
4007 macro_build ((char *) NULL, &icnt, &offset_expr,
4008 likely ? "beql" : "beq", "s,t,p", AT, 0);
4018 macro_build ((char *) NULL, &icnt, &offset_expr,
4019 likely ? "beql" : "beq", "s,t,p", 0, treg);
4022 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4023 "d,v,t", AT, sreg, treg);
4024 macro_build ((char *) NULL, &icnt, &offset_expr,
4025 likely ? "beql" : "beq", "s,t,p", AT, 0);
4033 && imm_expr.X_op == O_constant
4034 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4036 if (imm_expr.X_op != O_constant)
4037 as_bad (_("Unsupported large constant"));
4038 ++imm_expr.X_add_number;
4042 if (mask == M_BGEUL_I)
4044 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4046 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4048 macro_build ((char *) NULL, &icnt, &offset_expr,
4049 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4052 set_at (&icnt, sreg, 1);
4053 macro_build ((char *) NULL, &icnt, &offset_expr,
4054 likely ? "beql" : "beq", "s,t,p", AT, 0);
4062 macro_build ((char *) NULL, &icnt, &offset_expr,
4063 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4068 macro_build ((char *) NULL, &icnt, &offset_expr,
4069 likely ? "bltzl" : "bltz", "s,p", treg);
4072 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4074 macro_build ((char *) NULL, &icnt, &offset_expr,
4075 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4083 macro_build ((char *) NULL, &icnt, &offset_expr,
4084 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4089 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4090 "d,v,t", AT, treg, sreg);
4091 macro_build ((char *) NULL, &icnt, &offset_expr,
4092 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4100 macro_build ((char *) NULL, &icnt, &offset_expr,
4101 likely ? "blezl" : "blez", "s,p", sreg);
4106 macro_build ((char *) NULL, &icnt, &offset_expr,
4107 likely ? "bgezl" : "bgez", "s,p", treg);
4110 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4112 macro_build ((char *) NULL, &icnt, &offset_expr,
4113 likely ? "beql" : "beq", "s,t,p", AT, 0);
4119 maxnum = 0x7fffffff;
4120 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4127 if (imm_expr.X_op == O_constant
4128 && imm_expr.X_add_number >= maxnum
4129 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4131 if (imm_expr.X_op != O_constant)
4132 as_bad (_("Unsupported large constant"));
4133 ++imm_expr.X_add_number;
4137 if (mask == M_BLTL_I)
4139 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4141 macro_build ((char *) NULL, &icnt, &offset_expr,
4142 likely ? "bltzl" : "bltz", "s,p", sreg);
4145 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4147 macro_build ((char *) NULL, &icnt, &offset_expr,
4148 likely ? "blezl" : "blez", "s,p", sreg);
4151 set_at (&icnt, sreg, 0);
4152 macro_build ((char *) NULL, &icnt, &offset_expr,
4153 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4161 macro_build ((char *) NULL, &icnt, &offset_expr,
4162 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4167 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4168 "d,v,t", AT, treg, sreg);
4169 macro_build ((char *) NULL, &icnt, &offset_expr,
4170 likely ? "beql" : "beq", "s,t,p", AT, 0);
4178 && imm_expr.X_op == O_constant
4179 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4181 if (imm_expr.X_op != O_constant)
4182 as_bad (_("Unsupported large constant"));
4183 ++imm_expr.X_add_number;
4187 if (mask == M_BLTUL_I)
4189 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4191 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4193 macro_build ((char *) NULL, &icnt, &offset_expr,
4194 likely ? "beql" : "beq",
4198 set_at (&icnt, sreg, 1);
4199 macro_build ((char *) NULL, &icnt, &offset_expr,
4200 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4208 macro_build ((char *) NULL, &icnt, &offset_expr,
4209 likely ? "bltzl" : "bltz", "s,p", sreg);
4214 macro_build ((char *) NULL, &icnt, &offset_expr,
4215 likely ? "bgtzl" : "bgtz", "s,p", treg);
4218 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4220 macro_build ((char *) NULL, &icnt, &offset_expr,
4221 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4231 macro_build ((char *) NULL, &icnt, &offset_expr,
4232 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4235 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4238 macro_build ((char *) NULL, &icnt, &offset_expr,
4239 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4254 as_warn (_("Divide by zero."));
4256 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4259 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4264 mips_emit_delays (true);
4265 ++mips_opts.noreorder;
4266 mips_any_noreorder = 1;
4269 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4271 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4272 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4276 expr1.X_add_number = 8;
4277 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4278 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4279 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4280 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4283 expr1.X_add_number = -1;
4284 macro_build ((char *) NULL, &icnt, &expr1,
4285 dbl ? "daddiu" : "addiu",
4286 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4287 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4288 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4291 expr1.X_add_number = 1;
4292 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4293 (int) BFD_RELOC_LO16);
4294 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4295 "d,w,<", AT, AT, 31);
4299 expr1.X_add_number = 0x80000000;
4300 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4301 (int) BFD_RELOC_HI16);
4305 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4307 /* We want to close the noreorder block as soon as possible, so
4308 that later insns are available for delay slot filling. */
4309 --mips_opts.noreorder;
4313 expr1.X_add_number = 8;
4314 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4315 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4318 /* We want to close the noreorder block as soon as possible, so
4319 that later insns are available for delay slot filling. */
4320 --mips_opts.noreorder;
4322 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4325 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4364 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4366 as_warn (_("Divide by zero."));
4368 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4371 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4375 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4377 if (strcmp (s2, "mflo") == 0)
4378 move_register (&icnt, dreg, sreg);
4380 move_register (&icnt, dreg, 0);
4383 if (imm_expr.X_op == O_constant
4384 && imm_expr.X_add_number == -1
4385 && s[strlen (s) - 1] != 'u')
4387 if (strcmp (s2, "mflo") == 0)
4389 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4390 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4393 move_register (&icnt, dreg, 0);
4397 load_register (&icnt, AT, &imm_expr, dbl);
4398 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4400 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4419 mips_emit_delays (true);
4420 ++mips_opts.noreorder;
4421 mips_any_noreorder = 1;
4424 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4426 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4428 /* We want to close the noreorder block as soon as possible, so
4429 that later insns are available for delay slot filling. */
4430 --mips_opts.noreorder;
4434 expr1.X_add_number = 8;
4435 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4436 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4439 /* We want to close the noreorder block as soon as possible, so
4440 that later insns are available for delay slot filling. */
4441 --mips_opts.noreorder;
4442 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4445 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4451 /* Load the address of a symbol into a register. If breg is not
4452 zero, we then add a base register to it. */
4454 if (dbl && HAVE_32BIT_GPRS)
4455 as_warn (_("dla used to load 32-bit register"));
4457 if (! dbl && HAVE_64BIT_OBJECTS)
4458 as_warn (_("la used to load 64-bit address"));
4471 /* When generating embedded PIC code, we permit expressions of
4474 la $treg,foo-bar($breg)
4475 where bar is an address in the current section. These are used
4476 when getting the addresses of functions. We don't permit
4477 X_add_number to be non-zero, because if the symbol is
4478 external the relaxing code needs to know that any addend is
4479 purely the offset to X_op_symbol. */
4480 if (mips_pic == EMBEDDED_PIC
4481 && offset_expr.X_op == O_subtract
4482 && (symbol_constant_p (offset_expr.X_op_symbol)
4483 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4484 : (symbol_equated_p (offset_expr.X_op_symbol)
4486 (symbol_get_value_expression (offset_expr.X_op_symbol)
4489 && (offset_expr.X_add_number == 0
4490 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4496 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4497 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4501 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4502 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4503 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4504 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4505 "d,v,t", tempreg, tempreg, breg);
4507 macro_build ((char *) NULL, &icnt, &offset_expr,
4508 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4509 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4515 if (offset_expr.X_op != O_symbol
4516 && offset_expr.X_op != O_constant)
4518 as_bad (_("expression too complex"));
4519 offset_expr.X_op = O_constant;
4522 if (offset_expr.X_op == O_constant)
4523 load_register (&icnt, tempreg, &offset_expr,
4524 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4525 ? (dbl || HAVE_64BIT_ADDRESSES)
4526 : HAVE_64BIT_ADDRESSES));
4527 else if (mips_pic == NO_PIC)
4529 /* If this is a reference to a GP relative symbol, we want
4530 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4532 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4533 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4534 If we have a constant, we need two instructions anyhow,
4535 so we may as well always use the latter form.
4537 With 64bit address space and a usable $at we want
4538 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4539 lui $at,<sym> (BFD_RELOC_HI16_S)
4540 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4541 daddiu $at,<sym> (BFD_RELOC_LO16)
4543 dadd $tempreg,$tempreg,$at
4545 If $at is already in use, we use an path which is suboptimal
4546 on superscalar processors.
4547 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4548 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4550 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4552 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4555 if (HAVE_64BIT_ADDRESSES)
4557 /* We don't do GP optimization for now because RELAX_ENCODE can't
4558 hold the data for such large chunks. */
4562 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4563 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4564 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4565 AT, (int) BFD_RELOC_HI16_S);
4566 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4567 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4568 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4569 AT, AT, (int) BFD_RELOC_LO16);
4570 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4571 "d,w,<", tempreg, tempreg, 0);
4572 macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t",
4573 tempreg, tempreg, AT);
4578 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4579 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4580 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4581 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4582 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4583 tempreg, tempreg, 16);
4584 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4585 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4586 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4587 tempreg, tempreg, 16);
4588 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4589 tempreg, tempreg, (int) BFD_RELOC_LO16);
4594 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4595 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4598 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4599 "t,r,j", tempreg, mips_gp_register,
4600 (int) BFD_RELOC_GPREL16);
4601 p = frag_var (rs_machine_dependent, 8, 0,
4602 RELAX_ENCODE (4, 8, 0, 4, 0,
4603 mips_opts.warn_about_macros),
4604 offset_expr.X_add_symbol, 0, NULL);
4606 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4609 macro_build (p, &icnt, &offset_expr, "addiu",
4610 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4613 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4615 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4617 /* If this is a reference to an external symbol, and there
4618 is no constant, we want
4619 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4620 or if tempreg is PIC_CALL_REG
4621 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4622 For a local symbol, we want
4623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4625 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4627 If we have a small constant, and this is a reference to
4628 an external symbol, we want
4629 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4631 addiu $tempreg,$tempreg,<constant>
4632 For a local symbol, we want the same instruction
4633 sequence, but we output a BFD_RELOC_LO16 reloc on the
4636 If we have a large constant, and this is a reference to
4637 an external symbol, we want
4638 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4639 lui $at,<hiconstant>
4640 addiu $at,$at,<loconstant>
4641 addu $tempreg,$tempreg,$at
4642 For a local symbol, we want the same instruction
4643 sequence, but we output a BFD_RELOC_LO16 reloc on the
4644 addiu instruction. */
4645 expr1.X_add_number = offset_expr.X_add_number;
4646 offset_expr.X_add_number = 0;
4648 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4649 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4650 macro_build ((char *) NULL, &icnt, &offset_expr,
4651 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4652 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4653 if (expr1.X_add_number == 0)
4662 /* We're going to put in an addu instruction using
4663 tempreg, so we may as well insert the nop right
4665 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4669 p = frag_var (rs_machine_dependent, 8 - off, 0,
4670 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4672 ? mips_opts.warn_about_macros
4674 offset_expr.X_add_symbol, 0, NULL);
4677 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4680 macro_build (p, &icnt, &expr1,
4681 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4682 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4683 /* FIXME: If breg == 0, and the next instruction uses
4684 $tempreg, then if this variant case is used an extra
4685 nop will be generated. */
4687 else if (expr1.X_add_number >= -0x8000
4688 && expr1.X_add_number < 0x8000)
4690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4692 macro_build ((char *) NULL, &icnt, &expr1,
4693 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4694 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4695 frag_var (rs_machine_dependent, 0, 0,
4696 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4697 offset_expr.X_add_symbol, 0, NULL);
4703 /* If we are going to add in a base register, and the
4704 target register and the base register are the same,
4705 then we are using AT as a temporary register. Since
4706 we want to load the constant into AT, we add our
4707 current AT (from the global offset table) and the
4708 register into the register now, and pretend we were
4709 not using a base register. */
4714 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4716 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4717 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4718 "d,v,t", treg, AT, breg);
4724 /* Set mips_optimize around the lui instruction to avoid
4725 inserting an unnecessary nop after the lw. */
4726 hold_mips_optimize = mips_optimize;
4728 macro_build_lui (NULL, &icnt, &expr1, AT);
4729 mips_optimize = hold_mips_optimize;
4731 macro_build ((char *) NULL, &icnt, &expr1,
4732 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4733 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4734 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4735 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4736 "d,v,t", tempreg, tempreg, AT);
4737 frag_var (rs_machine_dependent, 0, 0,
4738 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4739 offset_expr.X_add_symbol, 0, NULL);
4743 else if (mips_pic == SVR4_PIC)
4747 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4748 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4750 /* This is the large GOT case. If this is a reference to an
4751 external symbol, and there is no constant, we want
4752 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4753 addu $tempreg,$tempreg,$gp
4754 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4755 or if tempreg is PIC_CALL_REG
4756 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4757 addu $tempreg,$tempreg,$gp
4758 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4759 For a local symbol, we want
4760 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4762 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4764 If we have a small constant, and this is a reference to
4765 an external symbol, we want
4766 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4767 addu $tempreg,$tempreg,$gp
4768 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4770 addiu $tempreg,$tempreg,<constant>
4771 For a local symbol, we want
4772 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4774 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4776 If we have a large constant, and this is a reference to
4777 an external symbol, we want
4778 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4779 addu $tempreg,$tempreg,$gp
4780 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4781 lui $at,<hiconstant>
4782 addiu $at,$at,<loconstant>
4783 addu $tempreg,$tempreg,$at
4784 For a local symbol, we want
4785 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4786 lui $at,<hiconstant>
4787 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4788 addu $tempreg,$tempreg,$at
4790 For NewABI, we want for data addresses
4791 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4792 If tempreg is PIC_CALL_REG pointing to a external symbol, we want
4793 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4797 int reloc_type = (tempreg == PIC_CALL_REG
4798 ? BFD_RELOC_MIPS_CALL16
4799 : BFD_RELOC_MIPS_GOT_DISP);
4801 macro_build ((char *) NULL, &icnt, &offset_expr,
4802 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4803 "t,o(b)", tempreg, reloc_type, mips_gp_register);
4806 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4807 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4808 "d,v,t", treg, tempreg, breg);
4815 expr1.X_add_number = offset_expr.X_add_number;
4816 offset_expr.X_add_number = 0;
4818 if (reg_needs_delay (mips_gp_register))
4822 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4824 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4825 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4827 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4828 tempreg, lui_reloc_type);
4829 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4830 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4831 "d,v,t", tempreg, tempreg, mips_gp_register);
4832 macro_build ((char *) NULL, &icnt, &offset_expr,
4833 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4834 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4835 if (expr1.X_add_number == 0)
4843 /* We're going to put in an addu instruction using
4844 tempreg, so we may as well insert the nop right
4846 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4851 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4852 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4855 ? mips_opts.warn_about_macros
4857 offset_expr.X_add_symbol, 0, NULL);
4859 else if (expr1.X_add_number >= -0x8000
4860 && expr1.X_add_number < 0x8000)
4862 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4864 macro_build ((char *) NULL, &icnt, &expr1,
4865 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4866 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4868 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4869 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4871 ? mips_opts.warn_about_macros
4873 offset_expr.X_add_symbol, 0, NULL);
4879 /* If we are going to add in a base register, and the
4880 target register and the base register are the same,
4881 then we are using AT as a temporary register. Since
4882 we want to load the constant into AT, we add our
4883 current AT (from the global offset table) and the
4884 register into the register now, and pretend we were
4885 not using a base register. */
4893 assert (tempreg == AT);
4894 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4896 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4897 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4898 "d,v,t", treg, AT, breg);
4903 /* Set mips_optimize around the lui instruction to avoid
4904 inserting an unnecessary nop after the lw. */
4905 hold_mips_optimize = mips_optimize;
4907 macro_build_lui (NULL, &icnt, &expr1, AT);
4908 mips_optimize = hold_mips_optimize;
4910 macro_build ((char *) NULL, &icnt, &expr1,
4911 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4912 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4913 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4914 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4915 "d,v,t", dreg, dreg, AT);
4917 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
4918 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
4921 ? mips_opts.warn_about_macros
4923 offset_expr.X_add_symbol, 0, NULL);
4930 /* This is needed because this instruction uses $gp, but
4931 the first instruction on the main stream does not. */
4932 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4935 macro_build (p, &icnt, &offset_expr,
4936 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4937 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
4940 if (expr1.X_add_number >= -0x8000
4941 && expr1.X_add_number < 0x8000)
4943 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4945 macro_build (p, &icnt, &expr1,
4946 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4947 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4948 /* FIXME: If add_number is 0, and there was no base
4949 register, the external symbol case ended with a load,
4950 so if the symbol turns out to not be external, and
4951 the next instruction uses tempreg, an unnecessary nop
4952 will be inserted. */
4958 /* We must add in the base register now, as in the
4959 external symbol case. */
4960 assert (tempreg == AT);
4961 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4963 macro_build (p, &icnt, (expressionS *) NULL,
4964 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4965 "d,v,t", treg, AT, breg);
4968 /* We set breg to 0 because we have arranged to add
4969 it in in both cases. */
4973 macro_build_lui (p, &icnt, &expr1, AT);
4975 macro_build (p, &icnt, &expr1,
4976 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4977 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4979 macro_build (p, &icnt, (expressionS *) NULL,
4980 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4981 "d,v,t", tempreg, tempreg, AT);
4985 else if (mips_pic == EMBEDDED_PIC)
4988 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4990 macro_build ((char *) NULL, &icnt, &offset_expr,
4991 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
4992 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
5001 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5002 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5004 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5006 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5007 "d,v,t", treg, tempreg, breg);
5016 /* The j instruction may not be used in PIC code, since it
5017 requires an absolute address. We convert it to a b
5019 if (mips_pic == NO_PIC)
5020 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5022 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5025 /* The jal instructions must be handled as macros because when
5026 generating PIC code they expand to multi-instruction
5027 sequences. Normally they are simple instructions. */
5032 if (mips_pic == NO_PIC
5033 || mips_pic == EMBEDDED_PIC)
5034 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5036 else if (mips_pic == SVR4_PIC)
5038 if (sreg != PIC_CALL_REG)
5039 as_warn (_("MIPS PIC call to register other than $25"));
5041 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5045 if (mips_cprestore_offset < 0)
5046 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5049 if (! mips_frame_reg_valid)
5051 as_warn (_("No .frame pseudo-op used in PIC code"));
5052 /* Quiet this warning. */
5053 mips_frame_reg_valid = 1;
5055 if (! mips_cprestore_valid)
5057 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5058 /* Quiet this warning. */
5059 mips_cprestore_valid = 1;
5061 expr1.X_add_number = mips_cprestore_offset;
5062 macro_build ((char *) NULL, &icnt, &expr1,
5063 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5064 mips_gp_register, (int) BFD_RELOC_LO16,
5075 if (mips_pic == NO_PIC)
5076 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5077 else if (mips_pic == SVR4_PIC)
5081 /* If this is a reference to an external symbol, and we are
5082 using a small GOT, we want
5083 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5087 lw $gp,cprestore($sp)
5088 The cprestore value is set using the .cprestore
5089 pseudo-op. If we are using a big GOT, we want
5090 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5092 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5096 lw $gp,cprestore($sp)
5097 If the symbol is not external, we want
5098 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5100 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5103 lw $gp,cprestore($sp)
5105 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5106 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5110 macro_build ((char *) NULL, &icnt, &offset_expr,
5111 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5112 "t,o(b)", PIC_CALL_REG,
5113 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5114 macro_build_jalr (icnt, &offset_expr);
5121 macro_build ((char *) NULL, &icnt, &offset_expr,
5122 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5123 "t,o(b)", PIC_CALL_REG,
5124 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5125 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5127 p = frag_var (rs_machine_dependent, 4, 0,
5128 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5129 offset_expr.X_add_symbol, 0, NULL);
5135 if (reg_needs_delay (mips_gp_register))
5139 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5140 "t,u", PIC_CALL_REG,
5141 (int) BFD_RELOC_MIPS_CALL_HI16);
5142 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5143 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5144 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5146 macro_build ((char *) NULL, &icnt, &offset_expr,
5147 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5148 "t,o(b)", PIC_CALL_REG,
5149 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5150 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5152 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5153 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5155 offset_expr.X_add_symbol, 0, NULL);
5158 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5161 macro_build (p, &icnt, &offset_expr,
5162 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5163 "t,o(b)", PIC_CALL_REG,
5164 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5166 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5169 macro_build (p, &icnt, &offset_expr,
5170 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5171 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5172 (int) BFD_RELOC_LO16);
5173 macro_build_jalr (icnt, &offset_expr);
5175 if (mips_cprestore_offset < 0)
5176 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5179 if (! mips_frame_reg_valid)
5181 as_warn (_("No .frame pseudo-op used in PIC code"));
5182 /* Quiet this warning. */
5183 mips_frame_reg_valid = 1;
5185 if (! mips_cprestore_valid)
5187 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5188 /* Quiet this warning. */
5189 mips_cprestore_valid = 1;
5191 if (mips_opts.noreorder)
5192 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5194 expr1.X_add_number = mips_cprestore_offset;
5195 macro_build ((char *) NULL, &icnt, &expr1,
5196 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5197 mips_gp_register, (int) BFD_RELOC_LO16,
5202 else if (mips_pic == EMBEDDED_PIC)
5204 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5205 /* The linker may expand the call to a longer sequence which
5206 uses $at, so we must break rather than return. */
5231 /* Itbl support may require additional care here. */
5236 /* Itbl support may require additional care here. */
5241 /* Itbl support may require additional care here. */
5246 /* Itbl support may require additional care here. */
5258 if (mips_arch == CPU_R4650)
5260 as_bad (_("opcode not supported on this processor"));
5264 /* Itbl support may require additional care here. */
5269 /* Itbl support may require additional care here. */
5274 /* Itbl support may require additional care here. */
5294 if (breg == treg || coproc || lr)
5316 /* Itbl support may require additional care here. */
5321 /* Itbl support may require additional care here. */
5326 /* Itbl support may require additional care here. */
5331 /* Itbl support may require additional care here. */
5347 if (mips_arch == CPU_R4650)
5349 as_bad (_("opcode not supported on this processor"));
5354 /* Itbl support may require additional care here. */
5358 /* Itbl support may require additional care here. */
5363 /* Itbl support may require additional care here. */
5375 /* Itbl support may require additional care here. */
5376 if (mask == M_LWC1_AB
5377 || mask == M_SWC1_AB
5378 || mask == M_LDC1_AB
5379 || mask == M_SDC1_AB
5388 /* For embedded PIC, we allow loads where the offset is calculated
5389 by subtracting a symbol in the current segment from an unknown
5390 symbol, relative to a base register, e.g.:
5391 <op> $treg, <sym>-<localsym>($breg)
5392 This is used by the compiler for switch statements. */
5393 if (mips_pic == EMBEDDED_PIC
5394 && offset_expr.X_op == O_subtract
5395 && (symbol_constant_p (offset_expr.X_op_symbol)
5396 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5397 : (symbol_equated_p (offset_expr.X_op_symbol)
5399 (symbol_get_value_expression (offset_expr.X_op_symbol)
5403 && (offset_expr.X_add_number == 0
5404 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5406 /* For this case, we output the instructions:
5407 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5408 addiu $tempreg,$tempreg,$breg
5409 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5410 If the relocation would fit entirely in 16 bits, it would be
5412 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5413 instead, but that seems quite difficult. */
5414 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5415 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5416 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5417 ((bfd_arch_bits_per_address (stdoutput) == 32
5418 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5419 ? "addu" : "daddu"),
5420 "d,v,t", tempreg, tempreg, breg);
5421 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5422 (int) BFD_RELOC_PCREL_LO16, tempreg);
5428 if (offset_expr.X_op != O_constant
5429 && offset_expr.X_op != O_symbol)
5431 as_bad (_("expression too complex"));
5432 offset_expr.X_op = O_constant;
5435 /* A constant expression in PIC code can be handled just as it
5436 is in non PIC code. */
5437 if (mips_pic == NO_PIC
5438 || offset_expr.X_op == O_constant)
5442 /* If this is a reference to a GP relative symbol, and there
5443 is no base register, we want
5444 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5445 Otherwise, if there is no base register, we want
5446 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5447 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5448 If we have a constant, we need two instructions anyhow,
5449 so we always use the latter form.
5451 If we have a base register, and this is a reference to a
5452 GP relative symbol, we want
5453 addu $tempreg,$breg,$gp
5454 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5456 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5457 addu $tempreg,$tempreg,$breg
5458 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5459 With a constant we always use the latter case.
5461 With 64bit address space and no base register and $at usable,
5463 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5464 lui $at,<sym> (BFD_RELOC_HI16_S)
5465 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5468 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5469 If we have a base register, we want
5470 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5471 lui $at,<sym> (BFD_RELOC_HI16_S)
5472 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5476 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5478 Without $at we can't generate the optimal path for superscalar
5479 processors here since this would require two temporary registers.
5480 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5481 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5483 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5485 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5486 If we have a base register, we want
5487 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5488 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5490 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5492 daddu $tempreg,$tempreg,$breg
5493 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5495 If we have 64-bit addresses, as an optimization, for
5496 addresses which are 32-bit constants (e.g. kseg0/kseg1
5497 addresses) we fall back to the 32-bit address generation
5498 mechanism since it is more efficient. This code should
5499 probably attempt to generate 64-bit constants more
5500 efficiently in general.
5502 if (HAVE_64BIT_ADDRESSES
5503 && !(offset_expr.X_op == O_constant
5504 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number)))
5508 /* We don't do GP optimization for now because RELAX_ENCODE can't
5509 hold the data for such large chunks. */
5513 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5514 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5515 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5516 AT, (int) BFD_RELOC_HI16_S);
5517 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5518 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5520 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5521 "d,v,t", AT, AT, breg);
5522 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5523 "d,w,<", tempreg, tempreg, 0);
5524 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5525 "d,v,t", tempreg, tempreg, AT);
5526 macro_build (p, &icnt, &offset_expr, s,
5527 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5532 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5533 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5534 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5535 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5536 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5537 "d,w,<", tempreg, tempreg, 16);
5538 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5539 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5540 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5541 "d,w,<", tempreg, tempreg, 16);
5543 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5544 "d,v,t", tempreg, tempreg, breg);
5545 macro_build (p, &icnt, &offset_expr, s,
5546 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5554 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5555 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5560 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5561 treg, (int) BFD_RELOC_GPREL16,
5563 p = frag_var (rs_machine_dependent, 8, 0,
5564 RELAX_ENCODE (4, 8, 0, 4, 0,
5565 (mips_opts.warn_about_macros
5567 && mips_opts.noat))),
5568 offset_expr.X_add_symbol, 0, NULL);
5571 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5574 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5575 (int) BFD_RELOC_LO16, tempreg);
5579 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5580 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5585 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5586 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5587 "d,v,t", tempreg, breg, mips_gp_register);
5588 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5589 treg, (int) BFD_RELOC_GPREL16, tempreg);
5590 p = frag_var (rs_machine_dependent, 12, 0,
5591 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5592 offset_expr.X_add_symbol, 0, NULL);
5594 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5597 macro_build (p, &icnt, (expressionS *) NULL,
5598 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5599 "d,v,t", tempreg, tempreg, breg);
5602 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5603 (int) BFD_RELOC_LO16, tempreg);
5606 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5610 /* If this is a reference to an external symbol, we want
5611 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5613 <op> $treg,0($tempreg)
5615 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5617 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5618 <op> $treg,0($tempreg)
5619 If there is a base register, we add it to $tempreg before
5620 the <op>. If there is a constant, we stick it in the
5621 <op> instruction. We don't handle constants larger than
5622 16 bits, because we have no way to load the upper 16 bits
5623 (actually, we could handle them for the subset of cases
5624 in which we are not using $at). */
5625 assert (offset_expr.X_op == O_symbol);
5626 expr1.X_add_number = offset_expr.X_add_number;
5627 offset_expr.X_add_number = 0;
5628 if (expr1.X_add_number < -0x8000
5629 || expr1.X_add_number >= 0x8000)
5630 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5632 macro_build ((char *) NULL, &icnt, &offset_expr,
5633 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5634 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5635 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5636 p = frag_var (rs_machine_dependent, 4, 0,
5637 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5638 offset_expr.X_add_symbol, 0, NULL);
5639 macro_build (p, &icnt, &offset_expr,
5640 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5641 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5643 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5644 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5645 "d,v,t", tempreg, tempreg, breg);
5646 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5647 (int) BFD_RELOC_LO16, tempreg);
5649 else if (mips_pic == SVR4_PIC)
5654 /* If this is a reference to an external symbol, we want
5655 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5656 addu $tempreg,$tempreg,$gp
5657 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5658 <op> $treg,0($tempreg)
5660 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5662 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5663 <op> $treg,0($tempreg)
5664 If there is a base register, we add it to $tempreg before
5665 the <op>. If there is a constant, we stick it in the
5666 <op> instruction. We don't handle constants larger than
5667 16 bits, because we have no way to load the upper 16 bits
5668 (actually, we could handle them for the subset of cases
5669 in which we are not using $at).
5672 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5673 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5674 <op> $treg,0($tempreg)
5676 assert (offset_expr.X_op == O_symbol);
5677 expr1.X_add_number = offset_expr.X_add_number;
5678 offset_expr.X_add_number = 0;
5679 if (expr1.X_add_number < -0x8000
5680 || expr1.X_add_number >= 0x8000)
5681 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5684 macro_build ((char *) NULL, &icnt, &offset_expr,
5685 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5686 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5688 macro_build ((char *) NULL, &icnt, &offset_expr,
5689 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5690 "t,r,j", tempreg, tempreg,
5691 BFD_RELOC_MIPS_GOT_OFST);
5693 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5694 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5695 "d,v,t", tempreg, tempreg, breg);
5696 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5697 (int) BFD_RELOC_LO16, tempreg);
5704 if (reg_needs_delay (mips_gp_register))
5709 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5710 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5711 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5712 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5713 "d,v,t", tempreg, tempreg, mips_gp_register);
5714 macro_build ((char *) NULL, &icnt, &offset_expr,
5715 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5716 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5718 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5719 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5720 offset_expr.X_add_symbol, 0, NULL);
5723 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5726 macro_build (p, &icnt, &offset_expr,
5727 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5728 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5731 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5733 macro_build (p, &icnt, &offset_expr,
5734 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5735 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5737 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5738 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5739 "d,v,t", tempreg, tempreg, breg);
5740 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5741 (int) BFD_RELOC_LO16, tempreg);
5743 else if (mips_pic == EMBEDDED_PIC)
5745 /* If there is no base register, we want
5746 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5747 If there is a base register, we want
5748 addu $tempreg,$breg,$gp
5749 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5751 assert (offset_expr.X_op == O_symbol);
5754 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5755 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
5760 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5761 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5762 "d,v,t", tempreg, breg, mips_gp_register);
5763 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5764 treg, (int) BFD_RELOC_GPREL16, tempreg);
5777 load_register (&icnt, treg, &imm_expr, 0);
5781 load_register (&icnt, treg, &imm_expr, 1);
5785 if (imm_expr.X_op == O_constant)
5787 load_register (&icnt, AT, &imm_expr, 0);
5788 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5789 "mtc1", "t,G", AT, treg);
5794 assert (offset_expr.X_op == O_symbol
5795 && strcmp (segment_name (S_GET_SEGMENT
5796 (offset_expr.X_add_symbol)),
5798 && offset_expr.X_add_number == 0);
5799 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5800 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
5805 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5806 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5807 order 32 bits of the value and the low order 32 bits are either
5808 zero or in OFFSET_EXPR. */
5809 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5811 if (HAVE_64BIT_GPRS)
5812 load_register (&icnt, treg, &imm_expr, 1);
5817 if (target_big_endian)
5829 load_register (&icnt, hreg, &imm_expr, 0);
5832 if (offset_expr.X_op == O_absent)
5833 move_register (&icnt, lreg, 0);
5836 assert (offset_expr.X_op == O_constant);
5837 load_register (&icnt, lreg, &offset_expr, 0);
5844 /* We know that sym is in the .rdata section. First we get the
5845 upper 16 bits of the address. */
5846 if (mips_pic == NO_PIC)
5848 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5850 else if (mips_pic == SVR4_PIC)
5852 macro_build ((char *) NULL, &icnt, &offset_expr,
5853 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5854 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5857 else if (mips_pic == EMBEDDED_PIC)
5859 /* For embedded PIC we pick up the entire address off $gp in
5860 a single instruction. */
5861 macro_build ((char *) NULL, &icnt, &offset_expr,
5862 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
5863 mips_gp_register, (int) BFD_RELOC_GPREL16);
5864 offset_expr.X_op = O_constant;
5865 offset_expr.X_add_number = 0;
5870 /* Now we load the register(s). */
5871 if (HAVE_64BIT_GPRS)
5872 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5873 treg, (int) BFD_RELOC_LO16, AT);
5876 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5877 treg, (int) BFD_RELOC_LO16, AT);
5880 /* FIXME: How in the world do we deal with the possible
5882 offset_expr.X_add_number += 4;
5883 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5884 treg + 1, (int) BFD_RELOC_LO16, AT);
5888 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5889 does not become a variant frag. */
5890 frag_wane (frag_now);
5896 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5897 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5898 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5899 the value and the low order 32 bits are either zero or in
5901 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5903 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5904 if (HAVE_64BIT_FPRS)
5906 assert (HAVE_64BIT_GPRS);
5907 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5908 "dmtc1", "t,S", AT, treg);
5912 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5913 "mtc1", "t,G", AT, treg + 1);
5914 if (offset_expr.X_op == O_absent)
5915 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5916 "mtc1", "t,G", 0, treg);
5919 assert (offset_expr.X_op == O_constant);
5920 load_register (&icnt, AT, &offset_expr, 0);
5921 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5922 "mtc1", "t,G", AT, treg);
5928 assert (offset_expr.X_op == O_symbol
5929 && offset_expr.X_add_number == 0);
5930 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5931 if (strcmp (s, ".lit8") == 0)
5933 if (mips_opts.isa != ISA_MIPS1)
5935 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5936 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
5940 breg = mips_gp_register;
5941 r = BFD_RELOC_MIPS_LITERAL;
5946 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
5947 if (mips_pic == SVR4_PIC)
5948 macro_build ((char *) NULL, &icnt, &offset_expr,
5949 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5950 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5954 /* FIXME: This won't work for a 64 bit address. */
5955 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5958 if (mips_opts.isa != ISA_MIPS1)
5960 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5961 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
5963 /* To avoid confusion in tc_gen_reloc, we must ensure
5964 that this does not become a variant frag. */
5965 frag_wane (frag_now);
5976 if (mips_arch == CPU_R4650)
5978 as_bad (_("opcode not supported on this processor"));
5981 /* Even on a big endian machine $fn comes before $fn+1. We have
5982 to adjust when loading from memory. */
5985 assert (mips_opts.isa == ISA_MIPS1);
5986 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5987 target_big_endian ? treg + 1 : treg,
5989 /* FIXME: A possible overflow which I don't know how to deal
5991 offset_expr.X_add_number += 4;
5992 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5993 target_big_endian ? treg : treg + 1,
5996 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5997 does not become a variant frag. */
5998 frag_wane (frag_now);
6007 * The MIPS assembler seems to check for X_add_number not
6008 * being double aligned and generating:
6011 * addiu at,at,%lo(foo+1)
6014 * But, the resulting address is the same after relocation so why
6015 * generate the extra instruction?
6017 if (mips_arch == CPU_R4650)
6019 as_bad (_("opcode not supported on this processor"));
6022 /* Itbl support may require additional care here. */
6024 if (mips_opts.isa != ISA_MIPS1)
6035 if (mips_arch == CPU_R4650)
6037 as_bad (_("opcode not supported on this processor"));
6041 if (mips_opts.isa != ISA_MIPS1)
6049 /* Itbl support may require additional care here. */
6054 if (HAVE_64BIT_GPRS)
6065 if (HAVE_64BIT_GPRS)
6075 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6076 loads for the case of doing a pair of loads to simulate an 'ld'.
6077 This is not currently done by the compiler, and assembly coders
6078 writing embedded-pic code can cope. */
6080 if (offset_expr.X_op != O_symbol
6081 && offset_expr.X_op != O_constant)
6083 as_bad (_("expression too complex"));
6084 offset_expr.X_op = O_constant;
6087 /* Even on a big endian machine $fn comes before $fn+1. We have
6088 to adjust when loading from memory. We set coproc if we must
6089 load $fn+1 first. */
6090 /* Itbl support may require additional care here. */
6091 if (! target_big_endian)
6094 if (mips_pic == NO_PIC
6095 || offset_expr.X_op == O_constant)
6099 /* If this is a reference to a GP relative symbol, we want
6100 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6101 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6102 If we have a base register, we use this
6104 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6105 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6106 If this is not a GP relative symbol, we want
6107 lui $at,<sym> (BFD_RELOC_HI16_S)
6108 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6109 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6110 If there is a base register, we add it to $at after the
6111 lui instruction. If there is a constant, we always use
6113 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6114 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6126 tempreg = mips_gp_register;
6133 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6134 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6135 "d,v,t", AT, breg, mips_gp_register);
6141 /* Itbl support may require additional care here. */
6142 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6143 coproc ? treg + 1 : treg,
6144 (int) BFD_RELOC_GPREL16, tempreg);
6145 offset_expr.X_add_number += 4;
6147 /* Set mips_optimize to 2 to avoid inserting an
6149 hold_mips_optimize = mips_optimize;
6151 /* Itbl support may require additional care here. */
6152 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6153 coproc ? treg : treg + 1,
6154 (int) BFD_RELOC_GPREL16, tempreg);
6155 mips_optimize = hold_mips_optimize;
6157 p = frag_var (rs_machine_dependent, 12 + off, 0,
6158 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6159 used_at && mips_opts.noat),
6160 offset_expr.X_add_symbol, 0, NULL);
6162 /* We just generated two relocs. When tc_gen_reloc
6163 handles this case, it will skip the first reloc and
6164 handle the second. The second reloc already has an
6165 extra addend of 4, which we added above. We must
6166 subtract it out, and then subtract another 4 to make
6167 the first reloc come out right. The second reloc
6168 will come out right because we are going to add 4 to
6169 offset_expr when we build its instruction below.
6171 If we have a symbol, then we don't want to include
6172 the offset, because it will wind up being included
6173 when we generate the reloc. */
6175 if (offset_expr.X_op == O_constant)
6176 offset_expr.X_add_number -= 8;
6179 offset_expr.X_add_number = -4;
6180 offset_expr.X_op = O_constant;
6183 macro_build_lui (p, &icnt, &offset_expr, AT);
6188 macro_build (p, &icnt, (expressionS *) NULL,
6189 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6190 "d,v,t", AT, breg, AT);
6194 /* Itbl support may require additional care here. */
6195 macro_build (p, &icnt, &offset_expr, s, fmt,
6196 coproc ? treg + 1 : treg,
6197 (int) BFD_RELOC_LO16, AT);
6200 /* FIXME: How do we handle overflow here? */
6201 offset_expr.X_add_number += 4;
6202 /* Itbl support may require additional care here. */
6203 macro_build (p, &icnt, &offset_expr, s, fmt,
6204 coproc ? treg : treg + 1,
6205 (int) BFD_RELOC_LO16, AT);
6207 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6211 /* If this is a reference to an external symbol, we want
6212 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6217 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6219 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6220 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6221 If there is a base register we add it to $at before the
6222 lwc1 instructions. If there is a constant we include it
6223 in the lwc1 instructions. */
6225 expr1.X_add_number = offset_expr.X_add_number;
6226 offset_expr.X_add_number = 0;
6227 if (expr1.X_add_number < -0x8000
6228 || expr1.X_add_number >= 0x8000 - 4)
6229 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6234 frag_grow (24 + off);
6235 macro_build ((char *) NULL, &icnt, &offset_expr,
6236 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6237 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6238 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6240 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6241 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6242 "d,v,t", AT, breg, AT);
6243 /* Itbl support may require additional care here. */
6244 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6245 coproc ? treg + 1 : treg,
6246 (int) BFD_RELOC_LO16, AT);
6247 expr1.X_add_number += 4;
6249 /* Set mips_optimize to 2 to avoid inserting an undesired
6251 hold_mips_optimize = mips_optimize;
6253 /* Itbl support may require additional care here. */
6254 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6255 coproc ? treg : treg + 1,
6256 (int) BFD_RELOC_LO16, AT);
6257 mips_optimize = hold_mips_optimize;
6259 (void) frag_var (rs_machine_dependent, 0, 0,
6260 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6261 offset_expr.X_add_symbol, 0, NULL);
6263 else if (mips_pic == SVR4_PIC)
6268 /* If this is a reference to an external symbol, we want
6269 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6271 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6276 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6278 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6279 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6280 If there is a base register we add it to $at before the
6281 lwc1 instructions. If there is a constant we include it
6282 in the lwc1 instructions. */
6284 expr1.X_add_number = offset_expr.X_add_number;
6285 offset_expr.X_add_number = 0;
6286 if (expr1.X_add_number < -0x8000
6287 || expr1.X_add_number >= 0x8000 - 4)
6288 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6289 if (reg_needs_delay (mips_gp_register))
6298 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6299 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6300 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6301 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6302 "d,v,t", AT, AT, mips_gp_register);
6303 macro_build ((char *) NULL, &icnt, &offset_expr,
6304 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6305 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6306 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6308 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6309 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6310 "d,v,t", AT, breg, AT);
6311 /* Itbl support may require additional care here. */
6312 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6313 coproc ? treg + 1 : treg,
6314 (int) BFD_RELOC_LO16, AT);
6315 expr1.X_add_number += 4;
6317 /* Set mips_optimize to 2 to avoid inserting an undesired
6319 hold_mips_optimize = mips_optimize;
6321 /* Itbl support may require additional care here. */
6322 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6323 coproc ? treg : treg + 1,
6324 (int) BFD_RELOC_LO16, AT);
6325 mips_optimize = hold_mips_optimize;
6326 expr1.X_add_number -= 4;
6328 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6329 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6330 8 + gpdel + off, 1, 0),
6331 offset_expr.X_add_symbol, 0, NULL);
6334 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6337 macro_build (p, &icnt, &offset_expr,
6338 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6339 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6342 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6346 macro_build (p, &icnt, (expressionS *) NULL,
6347 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6348 "d,v,t", AT, breg, AT);
6351 /* Itbl support may require additional care here. */
6352 macro_build (p, &icnt, &expr1, s, fmt,
6353 coproc ? treg + 1 : treg,
6354 (int) BFD_RELOC_LO16, AT);
6356 expr1.X_add_number += 4;
6358 /* Set mips_optimize to 2 to avoid inserting an undesired
6360 hold_mips_optimize = mips_optimize;
6362 /* Itbl support may require additional care here. */
6363 macro_build (p, &icnt, &expr1, s, fmt,
6364 coproc ? treg : treg + 1,
6365 (int) BFD_RELOC_LO16, AT);
6366 mips_optimize = hold_mips_optimize;
6368 else if (mips_pic == EMBEDDED_PIC)
6370 /* If there is no base register, we use
6371 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6372 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6373 If we have a base register, we use
6375 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6376 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6380 tempreg = mips_gp_register;
6385 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6386 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6387 "d,v,t", AT, breg, mips_gp_register);
6392 /* Itbl support may require additional care here. */
6393 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6394 coproc ? treg + 1 : treg,
6395 (int) BFD_RELOC_GPREL16, tempreg);
6396 offset_expr.X_add_number += 4;
6397 /* Itbl support may require additional care here. */
6398 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6399 coproc ? treg : treg + 1,
6400 (int) BFD_RELOC_GPREL16, tempreg);
6416 assert (HAVE_32BIT_ADDRESSES);
6417 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6418 (int) BFD_RELOC_LO16, breg);
6419 offset_expr.X_add_number += 4;
6420 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6421 (int) BFD_RELOC_LO16, breg);
6424 /* New code added to support COPZ instructions.
6425 This code builds table entries out of the macros in mip_opcodes.
6426 R4000 uses interlocks to handle coproc delays.
6427 Other chips (like the R3000) require nops to be inserted for delays.
6429 FIXME: Currently, we require that the user handle delays.
6430 In order to fill delay slots for non-interlocked chips,
6431 we must have a way to specify delays based on the coprocessor.
6432 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6433 What are the side-effects of the cop instruction?
6434 What cache support might we have and what are its effects?
6435 Both coprocessor & memory require delays. how long???
6436 What registers are read/set/modified?
6438 If an itbl is provided to interpret cop instructions,
6439 this knowledge can be encoded in the itbl spec. */
6453 /* For now we just do C (same as Cz). The parameter will be
6454 stored in insn_opcode by mips_ip. */
6455 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6460 move_register (&icnt, dreg, sreg);
6463 #ifdef LOSING_COMPILER
6465 /* Try and see if this is a new itbl instruction.
6466 This code builds table entries out of the macros in mip_opcodes.
6467 FIXME: For now we just assemble the expression and pass it's
6468 value along as a 32-bit immediate.
6469 We may want to have the assembler assemble this value,
6470 so that we gain the assembler's knowledge of delay slots,
6472 Would it be more efficient to use mask (id) here? */
6473 if (itbl_have_entries
6474 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6476 s = ip->insn_mo->name;
6478 coproc = ITBL_DECODE_PNUM (immed_expr);;
6479 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6486 as_warn (_("Macro used $at after \".set noat\""));
6491 struct mips_cl_insn *ip;
6493 register int treg, sreg, dreg, breg;
6509 bfd_reloc_code_real_type r;
6512 treg = (ip->insn_opcode >> 16) & 0x1f;
6513 dreg = (ip->insn_opcode >> 11) & 0x1f;
6514 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6515 mask = ip->insn_mo->mask;
6517 expr1.X_op = O_constant;
6518 expr1.X_op_symbol = NULL;
6519 expr1.X_add_symbol = NULL;
6520 expr1.X_add_number = 1;
6524 #endif /* LOSING_COMPILER */
6529 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6530 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6531 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6538 /* The MIPS assembler some times generates shifts and adds. I'm
6539 not trying to be that fancy. GCC should do this for us
6541 load_register (&icnt, AT, &imm_expr, dbl);
6542 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6543 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6544 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6558 mips_emit_delays (true);
6559 ++mips_opts.noreorder;
6560 mips_any_noreorder = 1;
6562 load_register (&icnt, AT, &imm_expr, dbl);
6563 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6564 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6565 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6567 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6568 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6569 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6572 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6576 expr1.X_add_number = 8;
6577 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6579 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6581 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6584 --mips_opts.noreorder;
6585 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6598 mips_emit_delays (true);
6599 ++mips_opts.noreorder;
6600 mips_any_noreorder = 1;
6602 load_register (&icnt, AT, &imm_expr, dbl);
6603 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6604 dbl ? "dmultu" : "multu",
6605 "s,t", sreg, imm ? AT : treg);
6606 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6608 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6611 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6615 expr1.X_add_number = 8;
6616 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6617 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6619 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6622 --mips_opts.noreorder;
6626 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6627 "d,v,t", AT, 0, treg);
6628 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6629 "d,t,s", AT, sreg, AT);
6630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6631 "d,t,s", dreg, sreg, treg);
6632 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6633 "d,v,t", dreg, dreg, AT);
6637 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6638 "d,v,t", AT, 0, treg);
6639 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6640 "d,t,s", AT, sreg, AT);
6641 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6642 "d,t,s", dreg, sreg, treg);
6643 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6644 "d,v,t", dreg, dreg, AT);
6652 if (imm_expr.X_op != O_constant)
6653 as_bad (_("rotate count too large"));
6654 rot = imm_expr.X_add_number & 0x3f;
6657 l = (rot < 0x20) ? "dsll" : "dsll32";
6658 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6660 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6661 "d,w,<", AT, sreg, rot);
6662 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6663 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6664 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6665 "d,v,t", dreg, dreg, AT);
6673 if (imm_expr.X_op != O_constant)
6674 as_bad (_("rotate count too large"));
6675 rot = imm_expr.X_add_number & 0x1f;
6678 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6679 "d,w,<", AT, sreg, rot);
6680 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6681 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6682 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6683 "d,v,t", dreg, dreg, AT);
6688 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6689 "d,v,t", AT, 0, treg);
6690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6691 "d,t,s", AT, sreg, AT);
6692 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6693 "d,t,s", dreg, sreg, treg);
6694 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6695 "d,v,t", dreg, dreg, AT);
6699 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6700 "d,v,t", AT, 0, treg);
6701 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6702 "d,t,s", AT, sreg, AT);
6703 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6704 "d,t,s", dreg, sreg, treg);
6705 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6706 "d,v,t", dreg, dreg, AT);
6714 if (imm_expr.X_op != O_constant)
6715 as_bad (_("rotate count too large"));
6716 rot = imm_expr.X_add_number & 0x3f;
6719 r = (rot < 0x20) ? "dsrl" : "dsrl32";
6720 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
6722 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6723 "d,w,<", AT, sreg, rot);
6724 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6725 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6726 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6727 "d,v,t", dreg, dreg, AT);
6735 if (imm_expr.X_op != O_constant)
6736 as_bad (_("rotate count too large"));
6737 rot = imm_expr.X_add_number & 0x1f;
6740 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6741 "d,w,<", AT, sreg, rot);
6742 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6743 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6744 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6745 "d,v,t", dreg, dreg, AT);
6750 if (mips_arch == CPU_R4650)
6752 as_bad (_("opcode not supported on this processor"));
6755 assert (mips_opts.isa == ISA_MIPS1);
6756 /* Even on a big endian machine $fn comes before $fn+1. We have
6757 to adjust when storing to memory. */
6758 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6759 target_big_endian ? treg + 1 : treg,
6760 (int) BFD_RELOC_LO16, breg);
6761 offset_expr.X_add_number += 4;
6762 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6763 target_big_endian ? treg : treg + 1,
6764 (int) BFD_RELOC_LO16, breg);
6769 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6770 treg, (int) BFD_RELOC_LO16);
6772 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6773 sreg, (int) BFD_RELOC_LO16);
6776 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6777 "d,v,t", dreg, sreg, treg);
6778 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6779 dreg, (int) BFD_RELOC_LO16);
6784 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6786 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6787 sreg, (int) BFD_RELOC_LO16);
6792 as_warn (_("Instruction %s: result is always false"),
6794 move_register (&icnt, dreg, 0);
6797 if (imm_expr.X_op == O_constant
6798 && imm_expr.X_add_number >= 0
6799 && imm_expr.X_add_number < 0x10000)
6801 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6802 sreg, (int) BFD_RELOC_LO16);
6805 else if (imm_expr.X_op == O_constant
6806 && imm_expr.X_add_number > -0x8000
6807 && imm_expr.X_add_number < 0)
6809 imm_expr.X_add_number = -imm_expr.X_add_number;
6810 macro_build ((char *) NULL, &icnt, &imm_expr,
6811 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6812 "t,r,j", dreg, sreg,
6813 (int) BFD_RELOC_LO16);
6818 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6819 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6820 "d,v,t", dreg, sreg, AT);
6823 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6824 (int) BFD_RELOC_LO16);
6829 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6835 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6837 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6838 (int) BFD_RELOC_LO16);
6841 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6843 if (imm_expr.X_op == O_constant
6844 && imm_expr.X_add_number >= -0x8000
6845 && imm_expr.X_add_number < 0x8000)
6847 macro_build ((char *) NULL, &icnt, &imm_expr,
6848 mask == M_SGE_I ? "slti" : "sltiu",
6849 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6854 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6855 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6856 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6860 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6861 (int) BFD_RELOC_LO16);
6866 case M_SGT: /* sreg > treg <==> treg < sreg */
6872 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6876 case M_SGT_I: /* sreg > I <==> I < sreg */
6882 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6883 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6887 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6893 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6895 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6896 (int) BFD_RELOC_LO16);
6899 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6905 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6906 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6908 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6909 (int) BFD_RELOC_LO16);
6913 if (imm_expr.X_op == O_constant
6914 && imm_expr.X_add_number >= -0x8000
6915 && imm_expr.X_add_number < 0x8000)
6917 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6918 dreg, sreg, (int) BFD_RELOC_LO16);
6921 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6922 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
6927 if (imm_expr.X_op == O_constant
6928 && imm_expr.X_add_number >= -0x8000
6929 && imm_expr.X_add_number < 0x8000)
6931 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6932 dreg, sreg, (int) BFD_RELOC_LO16);
6935 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6936 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6937 "d,v,t", dreg, sreg, AT);
6942 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6943 "d,v,t", dreg, 0, treg);
6945 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6946 "d,v,t", dreg, 0, sreg);
6949 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6950 "d,v,t", dreg, sreg, treg);
6951 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6952 "d,v,t", dreg, 0, dreg);
6957 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6959 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6960 "d,v,t", dreg, 0, sreg);
6965 as_warn (_("Instruction %s: result is always true"),
6967 macro_build ((char *) NULL, &icnt, &expr1,
6968 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6969 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
6972 if (imm_expr.X_op == O_constant
6973 && imm_expr.X_add_number >= 0
6974 && imm_expr.X_add_number < 0x10000)
6976 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
6977 dreg, sreg, (int) BFD_RELOC_LO16);
6980 else if (imm_expr.X_op == O_constant
6981 && imm_expr.X_add_number > -0x8000
6982 && imm_expr.X_add_number < 0)
6984 imm_expr.X_add_number = -imm_expr.X_add_number;
6985 macro_build ((char *) NULL, &icnt, &imm_expr,
6986 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6987 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6992 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6993 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6994 "d,v,t", dreg, sreg, AT);
6997 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6998 "d,v,t", dreg, 0, dreg);
7006 if (imm_expr.X_op == O_constant
7007 && imm_expr.X_add_number > -0x8000
7008 && imm_expr.X_add_number <= 0x8000)
7010 imm_expr.X_add_number = -imm_expr.X_add_number;
7011 macro_build ((char *) NULL, &icnt, &imm_expr,
7012 dbl ? "daddi" : "addi",
7013 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7016 load_register (&icnt, AT, &imm_expr, dbl);
7017 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7018 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7024 if (imm_expr.X_op == O_constant
7025 && imm_expr.X_add_number > -0x8000
7026 && imm_expr.X_add_number <= 0x8000)
7028 imm_expr.X_add_number = -imm_expr.X_add_number;
7029 macro_build ((char *) NULL, &icnt, &imm_expr,
7030 dbl ? "daddiu" : "addiu",
7031 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7034 load_register (&icnt, AT, &imm_expr, dbl);
7035 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7036 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7057 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7058 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7064 assert (mips_opts.isa == ISA_MIPS1);
7065 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7066 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7069 * Is the double cfc1 instruction a bug in the mips assembler;
7070 * or is there a reason for it?
7072 mips_emit_delays (true);
7073 ++mips_opts.noreorder;
7074 mips_any_noreorder = 1;
7075 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7077 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7079 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7080 expr1.X_add_number = 3;
7081 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7082 (int) BFD_RELOC_LO16);
7083 expr1.X_add_number = 2;
7084 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7085 (int) BFD_RELOC_LO16);
7086 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7088 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7089 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7090 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7091 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7093 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7094 --mips_opts.noreorder;
7103 if (offset_expr.X_add_number >= 0x7fff)
7104 as_bad (_("operand overflow"));
7105 /* avoid load delay */
7106 if (! target_big_endian)
7107 ++offset_expr.X_add_number;
7108 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7109 (int) BFD_RELOC_LO16, breg);
7110 if (! target_big_endian)
7111 --offset_expr.X_add_number;
7113 ++offset_expr.X_add_number;
7114 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7115 (int) BFD_RELOC_LO16, breg);
7116 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7118 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7132 if (offset_expr.X_add_number >= 0x8000 - off)
7133 as_bad (_("operand overflow"));
7134 if (! target_big_endian)
7135 offset_expr.X_add_number += off;
7136 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7137 (int) BFD_RELOC_LO16, breg);
7138 if (! target_big_endian)
7139 offset_expr.X_add_number -= off;
7141 offset_expr.X_add_number += off;
7142 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7143 (int) BFD_RELOC_LO16, breg);
7157 load_address (&icnt, AT, &offset_expr, &used_at);
7159 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7160 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7161 "d,v,t", AT, AT, breg);
7162 if (! target_big_endian)
7163 expr1.X_add_number = off;
7165 expr1.X_add_number = 0;
7166 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7167 (int) BFD_RELOC_LO16, AT);
7168 if (! target_big_endian)
7169 expr1.X_add_number = 0;
7171 expr1.X_add_number = off;
7172 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7173 (int) BFD_RELOC_LO16, AT);
7179 load_address (&icnt, AT, &offset_expr, &used_at);
7181 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7182 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7183 "d,v,t", AT, AT, breg);
7184 if (target_big_endian)
7185 expr1.X_add_number = 0;
7186 macro_build ((char *) NULL, &icnt, &expr1,
7187 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7188 (int) BFD_RELOC_LO16, AT);
7189 if (target_big_endian)
7190 expr1.X_add_number = 1;
7192 expr1.X_add_number = 0;
7193 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7194 (int) BFD_RELOC_LO16, AT);
7195 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7197 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7202 if (offset_expr.X_add_number >= 0x7fff)
7203 as_bad (_("operand overflow"));
7204 if (target_big_endian)
7205 ++offset_expr.X_add_number;
7206 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7207 (int) BFD_RELOC_LO16, breg);
7208 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7210 if (target_big_endian)
7211 --offset_expr.X_add_number;
7213 ++offset_expr.X_add_number;
7214 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7215 (int) BFD_RELOC_LO16, breg);
7228 if (offset_expr.X_add_number >= 0x8000 - off)
7229 as_bad (_("operand overflow"));
7230 if (! target_big_endian)
7231 offset_expr.X_add_number += off;
7232 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7233 (int) BFD_RELOC_LO16, breg);
7234 if (! target_big_endian)
7235 offset_expr.X_add_number -= off;
7237 offset_expr.X_add_number += off;
7238 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7239 (int) BFD_RELOC_LO16, breg);
7253 load_address (&icnt, AT, &offset_expr, &used_at);
7255 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7256 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7257 "d,v,t", AT, AT, breg);
7258 if (! target_big_endian)
7259 expr1.X_add_number = off;
7261 expr1.X_add_number = 0;
7262 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7263 (int) BFD_RELOC_LO16, AT);
7264 if (! target_big_endian)
7265 expr1.X_add_number = 0;
7267 expr1.X_add_number = off;
7268 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7269 (int) BFD_RELOC_LO16, AT);
7274 load_address (&icnt, AT, &offset_expr, &used_at);
7276 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7277 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7278 "d,v,t", AT, AT, breg);
7279 if (! target_big_endian)
7280 expr1.X_add_number = 0;
7281 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7282 (int) BFD_RELOC_LO16, AT);
7283 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7285 if (! target_big_endian)
7286 expr1.X_add_number = 1;
7288 expr1.X_add_number = 0;
7289 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7290 (int) BFD_RELOC_LO16, AT);
7291 if (! target_big_endian)
7292 expr1.X_add_number = 0;
7294 expr1.X_add_number = 1;
7295 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7296 (int) BFD_RELOC_LO16, AT);
7297 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7299 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7304 /* FIXME: Check if this is one of the itbl macros, since they
7305 are added dynamically. */
7306 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7310 as_warn (_("Macro used $at after \".set noat\""));
7313 /* Implement macros in mips16 mode. */
7317 struct mips_cl_insn *ip;
7320 int xreg, yreg, zreg, tmp;
7324 const char *s, *s2, *s3;
7326 mask = ip->insn_mo->mask;
7328 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7329 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7330 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7334 expr1.X_op = O_constant;
7335 expr1.X_op_symbol = NULL;
7336 expr1.X_add_symbol = NULL;
7337 expr1.X_add_number = 1;
7356 mips_emit_delays (true);
7357 ++mips_opts.noreorder;
7358 mips_any_noreorder = 1;
7359 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7360 dbl ? "ddiv" : "div",
7361 "0,x,y", xreg, yreg);
7362 expr1.X_add_number = 2;
7363 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7364 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7367 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7368 since that causes an overflow. We should do that as well,
7369 but I don't see how to do the comparisons without a temporary
7371 --mips_opts.noreorder;
7372 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7391 mips_emit_delays (true);
7392 ++mips_opts.noreorder;
7393 mips_any_noreorder = 1;
7394 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7396 expr1.X_add_number = 2;
7397 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7398 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7400 --mips_opts.noreorder;
7401 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7407 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7408 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7409 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7418 if (imm_expr.X_op != O_constant)
7419 as_bad (_("Unsupported large constant"));
7420 imm_expr.X_add_number = -imm_expr.X_add_number;
7421 macro_build ((char *) NULL, &icnt, &imm_expr,
7422 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7426 if (imm_expr.X_op != O_constant)
7427 as_bad (_("Unsupported large constant"));
7428 imm_expr.X_add_number = -imm_expr.X_add_number;
7429 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7434 if (imm_expr.X_op != O_constant)
7435 as_bad (_("Unsupported large constant"));
7436 imm_expr.X_add_number = -imm_expr.X_add_number;
7437 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7460 goto do_reverse_branch;
7464 goto do_reverse_branch;
7476 goto do_reverse_branch;
7487 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7489 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7516 goto do_addone_branch_i;
7521 goto do_addone_branch_i;
7536 goto do_addone_branch_i;
7543 if (imm_expr.X_op != O_constant)
7544 as_bad (_("Unsupported large constant"));
7545 ++imm_expr.X_add_number;
7548 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7549 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7553 expr1.X_add_number = 0;
7554 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7556 move_register (&icnt, xreg, yreg);
7557 expr1.X_add_number = 2;
7558 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7559 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7560 "neg", "x,w", xreg, xreg);
7564 /* For consistency checking, verify that all bits are specified either
7565 by the match/mask part of the instruction definition, or by the
7568 validate_mips_insn (opc)
7569 const struct mips_opcode *opc;
7571 const char *p = opc->args;
7573 unsigned long used_bits = opc->mask;
7575 if ((used_bits & opc->match) != opc->match)
7577 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7578 opc->name, opc->args);
7581 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7588 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7589 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7591 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7592 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7593 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7594 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7596 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7597 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7599 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7601 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7602 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7603 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7604 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7605 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7606 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7607 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7608 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7609 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7610 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7611 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7612 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7613 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7614 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7615 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7616 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7617 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7619 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7620 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7621 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7622 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7624 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7625 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7626 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7627 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7628 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7629 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7630 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7631 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7632 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7635 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7636 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7637 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7639 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7640 c, opc->name, opc->args);
7644 if (used_bits != 0xffffffff)
7646 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7647 ~used_bits & 0xffffffff, opc->name, opc->args);
7653 /* This routine assembles an instruction into its binary format. As a
7654 side effect, it sets one of the global variables imm_reloc or
7655 offset_reloc to the type of relocation to do if one of the operands
7656 is an address expression. */
7661 struct mips_cl_insn *ip;
7666 struct mips_opcode *insn;
7669 unsigned int lastregno = 0;
7675 /* If the instruction contains a '.', we first try to match an instruction
7676 including the '.'. Then we try again without the '.'. */
7678 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7681 /* If we stopped on whitespace, then replace the whitespace with null for
7682 the call to hash_find. Save the character we replaced just in case we
7683 have to re-parse the instruction. */
7690 insn = (struct mips_opcode *) hash_find (op_hash, str);
7692 /* If we didn't find the instruction in the opcode table, try again, but
7693 this time with just the instruction up to, but not including the
7697 /* Restore the character we overwrite above (if any). */
7701 /* Scan up to the first '.' or whitespace. */
7703 *s != '\0' && *s != '.' && !ISSPACE (*s);
7707 /* If we did not find a '.', then we can quit now. */
7710 insn_error = "unrecognized opcode";
7714 /* Lookup the instruction in the hash table. */
7716 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7718 insn_error = "unrecognized opcode";
7728 assert (strcmp (insn->name, str) == 0);
7730 if (OPCODE_IS_MEMBER (insn,
7732 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7733 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7739 if (insn->pinfo != INSN_MACRO)
7741 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7747 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7748 && strcmp (insn->name, insn[1].name) == 0)
7757 static char buf[100];
7759 _("opcode not supported on this processor: %s (%s)"),
7760 mips_cpu_to_str (mips_arch),
7761 mips_isa_to_str (mips_opts.isa));
7772 ip->insn_opcode = insn->match;
7774 for (args = insn->args;; ++args)
7778 s += strspn (s, " \t");
7782 case '\0': /* end of args */
7795 ip->insn_opcode |= lastregno << OP_SH_RS;
7799 ip->insn_opcode |= lastregno << OP_SH_RT;
7803 ip->insn_opcode |= lastregno << OP_SH_FT;
7807 ip->insn_opcode |= lastregno << OP_SH_FS;
7813 /* Handle optional base register.
7814 Either the base register is omitted or
7815 we must have a left paren. */
7816 /* This is dependent on the next operand specifier
7817 is a base register specification. */
7818 assert (args[1] == 'b' || args[1] == '5'
7819 || args[1] == '-' || args[1] == '4');
7823 case ')': /* these must match exactly */
7828 case '<': /* must be at least one digit */
7830 * According to the manual, if the shift amount is greater
7831 * than 31 or less than 0, then the shift amount should be
7832 * mod 32. In reality the mips assembler issues an error.
7833 * We issue a warning and mask out all but the low 5 bits.
7835 my_getExpression (&imm_expr, s);
7836 check_absolute_expr (ip, &imm_expr);
7837 if ((unsigned long) imm_expr.X_add_number > 31)
7839 as_warn (_("Improper shift amount (%lu)"),
7840 (unsigned long) imm_expr.X_add_number);
7841 imm_expr.X_add_number &= OP_MASK_SHAMT;
7843 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7844 imm_expr.X_op = O_absent;
7848 case '>': /* shift amount minus 32 */
7849 my_getExpression (&imm_expr, s);
7850 check_absolute_expr (ip, &imm_expr);
7851 if ((unsigned long) imm_expr.X_add_number < 32
7852 || (unsigned long) imm_expr.X_add_number > 63)
7854 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7855 imm_expr.X_op = O_absent;
7859 case 'k': /* cache code */
7860 case 'h': /* prefx code */
7861 my_getExpression (&imm_expr, s);
7862 check_absolute_expr (ip, &imm_expr);
7863 if ((unsigned long) imm_expr.X_add_number > 31)
7865 as_warn (_("Invalid value for `%s' (%lu)"),
7867 (unsigned long) imm_expr.X_add_number);
7868 imm_expr.X_add_number &= 0x1f;
7871 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7873 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7874 imm_expr.X_op = O_absent;
7878 case 'c': /* break code */
7879 my_getExpression (&imm_expr, s);
7880 check_absolute_expr (ip, &imm_expr);
7881 if ((unsigned long) imm_expr.X_add_number > 1023)
7883 as_warn (_("Illegal break code (%lu)"),
7884 (unsigned long) imm_expr.X_add_number);
7885 imm_expr.X_add_number &= OP_MASK_CODE;
7887 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7888 imm_expr.X_op = O_absent;
7892 case 'q': /* lower break code */
7893 my_getExpression (&imm_expr, s);
7894 check_absolute_expr (ip, &imm_expr);
7895 if ((unsigned long) imm_expr.X_add_number > 1023)
7897 as_warn (_("Illegal lower break code (%lu)"),
7898 (unsigned long) imm_expr.X_add_number);
7899 imm_expr.X_add_number &= OP_MASK_CODE2;
7901 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7902 imm_expr.X_op = O_absent;
7906 case 'B': /* 20-bit syscall/break code. */
7907 my_getExpression (&imm_expr, s);
7908 check_absolute_expr (ip, &imm_expr);
7909 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
7910 as_warn (_("Illegal 20-bit code (%lu)"),
7911 (unsigned long) imm_expr.X_add_number);
7912 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7913 imm_expr.X_op = O_absent;
7917 case 'C': /* Coprocessor code */
7918 my_getExpression (&imm_expr, s);
7919 check_absolute_expr (ip, &imm_expr);
7920 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
7922 as_warn (_("Coproccesor code > 25 bits (%lu)"),
7923 (unsigned long) imm_expr.X_add_number);
7924 imm_expr.X_add_number &= ((1 << 25) - 1);
7926 ip->insn_opcode |= imm_expr.X_add_number;
7927 imm_expr.X_op = O_absent;
7931 case 'J': /* 19-bit wait code. */
7932 my_getExpression (&imm_expr, s);
7933 check_absolute_expr (ip, &imm_expr);
7934 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
7935 as_warn (_("Illegal 19-bit code (%lu)"),
7936 (unsigned long) imm_expr.X_add_number);
7937 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7938 imm_expr.X_op = O_absent;
7942 case 'P': /* Performance register */
7943 my_getExpression (&imm_expr, s);
7944 check_absolute_expr (ip, &imm_expr);
7945 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7947 as_warn (_("Invalid performance register (%lu)"),
7948 (unsigned long) imm_expr.X_add_number);
7949 imm_expr.X_add_number &= OP_MASK_PERFREG;
7951 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7952 imm_expr.X_op = O_absent;
7956 case 'b': /* base register */
7957 case 'd': /* destination register */
7958 case 's': /* source register */
7959 case 't': /* target register */
7960 case 'r': /* both target and source */
7961 case 'v': /* both dest and source */
7962 case 'w': /* both dest and target */
7963 case 'E': /* coprocessor target register */
7964 case 'G': /* coprocessor destination register */
7965 case 'x': /* ignore register name */
7966 case 'z': /* must be zero register */
7967 case 'U': /* destination register (clo/clz). */
7982 while (ISDIGIT (*s));
7984 as_bad (_("Invalid register number (%d)"), regno);
7986 else if (*args == 'E' || *args == 'G')
7990 if (s[1] == 'r' && s[2] == 'a')
7995 else if (s[1] == 'f' && s[2] == 'p')
8000 else if (s[1] == 's' && s[2] == 'p')
8005 else if (s[1] == 'g' && s[2] == 'p')
8010 else if (s[1] == 'a' && s[2] == 't')
8015 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8020 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8025 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8030 else if (itbl_have_entries)
8035 p = s + 1; /* advance past '$' */
8036 n = itbl_get_field (&p); /* n is name */
8038 /* See if this is a register defined in an
8040 if (itbl_get_reg_val (n, &r))
8042 /* Get_field advances to the start of
8043 the next field, so we need to back
8044 rack to the end of the last field. */
8048 s = strchr (s, '\0');
8061 as_warn (_("Used $at without \".set noat\""));
8067 if (c == 'r' || c == 'v' || c == 'w')
8074 /* 'z' only matches $0. */
8075 if (c == 'z' && regno != 0)
8078 /* Now that we have assembled one operand, we use the args string
8079 * to figure out where it goes in the instruction. */
8086 ip->insn_opcode |= regno << OP_SH_RS;
8090 ip->insn_opcode |= regno << OP_SH_RD;
8093 ip->insn_opcode |= regno << OP_SH_RD;
8094 ip->insn_opcode |= regno << OP_SH_RT;
8099 ip->insn_opcode |= regno << OP_SH_RT;
8102 /* This case exists because on the r3000 trunc
8103 expands into a macro which requires a gp
8104 register. On the r6000 or r4000 it is
8105 assembled into a single instruction which
8106 ignores the register. Thus the insn version
8107 is MIPS_ISA2 and uses 'x', and the macro
8108 version is MIPS_ISA1 and uses 't'. */
8111 /* This case is for the div instruction, which
8112 acts differently if the destination argument
8113 is $0. This only matches $0, and is checked
8114 outside the switch. */
8117 /* Itbl operand; not yet implemented. FIXME ?? */
8119 /* What about all other operands like 'i', which
8120 can be specified in the opcode table? */
8130 ip->insn_opcode |= lastregno << OP_SH_RS;
8133 ip->insn_opcode |= lastregno << OP_SH_RT;
8138 case 'O': /* MDMX alignment immediate constant. */
8139 my_getExpression (&imm_expr, s);
8140 check_absolute_expr (ip, &imm_expr);
8141 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8143 as_warn ("Improper align amount (%ld), using low bits",
8144 (long) imm_expr.X_add_number);
8145 imm_expr.X_add_number &= OP_MASK_ALN;
8147 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8148 imm_expr.X_op = O_absent;
8152 case 'Q': /* MDMX vector, element sel, or const. */
8155 /* MDMX Immediate. */
8156 my_getExpression (&imm_expr, s);
8157 check_absolute_expr (ip, &imm_expr);
8158 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8160 as_warn (_("Invalid MDMX Immediate (%ld)"),
8161 (long) imm_expr.X_add_number);
8162 imm_expr.X_add_number &= OP_MASK_FT;
8164 imm_expr.X_add_number &= OP_MASK_FT;
8165 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8166 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8168 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8169 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8170 imm_expr.X_op = O_absent;
8174 /* Not MDMX Immediate. Fall through. */
8175 case 'X': /* MDMX destination register. */
8176 case 'Y': /* MDMX source register. */
8177 case 'Z': /* MDMX target register. */
8179 case 'D': /* floating point destination register */
8180 case 'S': /* floating point source register */
8181 case 'T': /* floating point target register */
8182 case 'R': /* floating point source register */
8186 /* Accept $fN for FP and MDMX register numbers, and in
8187 addition accept $vN for MDMX register numbers. */
8188 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8189 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8200 while (ISDIGIT (*s));
8203 as_bad (_("Invalid float register number (%d)"), regno);
8205 if ((regno & 1) != 0
8207 && ! (strcmp (str, "mtc1") == 0
8208 || strcmp (str, "mfc1") == 0
8209 || strcmp (str, "lwc1") == 0
8210 || strcmp (str, "swc1") == 0
8211 || strcmp (str, "l.s") == 0
8212 || strcmp (str, "s.s") == 0))
8213 as_warn (_("Float register should be even, was %d"),
8221 if (c == 'V' || c == 'W')
8232 ip->insn_opcode |= regno << OP_SH_FD;
8237 ip->insn_opcode |= regno << OP_SH_FS;
8240 /* This is like 'Z', but also needs to fix the MDMX
8241 vector/scalar select bits. Note that the
8242 scalar immediate case is handled above. */
8245 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8246 int max_el = (is_qh ? 3 : 7);
8248 my_getExpression(&imm_expr, s);
8249 check_absolute_expr (ip, &imm_expr);
8251 if (imm_expr.X_add_number > max_el)
8252 as_bad(_("Bad element selector %ld"),
8253 (long) imm_expr.X_add_number);
8254 imm_expr.X_add_number &= max_el;
8255 ip->insn_opcode |= (imm_expr.X_add_number
8259 as_warn(_("Expecting ']' found '%s'"), s);
8265 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8266 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8269 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8276 ip->insn_opcode |= regno << OP_SH_FT;
8279 ip->insn_opcode |= regno << OP_SH_FR;
8289 ip->insn_opcode |= lastregno << OP_SH_FS;
8292 ip->insn_opcode |= lastregno << OP_SH_FT;
8298 my_getExpression (&imm_expr, s);
8299 if (imm_expr.X_op != O_big
8300 && imm_expr.X_op != O_constant)
8301 insn_error = _("absolute expression required");
8306 my_getExpression (&offset_expr, s);
8307 *imm_reloc = BFD_RELOC_32;
8320 unsigned char temp[8];
8322 unsigned int length;
8327 /* These only appear as the last operand in an
8328 instruction, and every instruction that accepts
8329 them in any variant accepts them in all variants.
8330 This means we don't have to worry about backing out
8331 any changes if the instruction does not match.
8333 The difference between them is the size of the
8334 floating point constant and where it goes. For 'F'
8335 and 'L' the constant is 64 bits; for 'f' and 'l' it
8336 is 32 bits. Where the constant is placed is based
8337 on how the MIPS assembler does things:
8340 f -- immediate value
8343 The .lit4 and .lit8 sections are only used if
8344 permitted by the -G argument.
8346 When generating embedded PIC code, we use the
8347 .lit8 section but not the .lit4 section (we can do
8348 .lit4 inline easily; we need to put .lit8
8349 somewhere in the data segment, and using .lit8
8350 permits the linker to eventually combine identical
8353 The code below needs to know whether the target register
8354 is 32 or 64 bits wide. It relies on the fact 'f' and
8355 'F' are used with GPR-based instructions and 'l' and
8356 'L' are used with FPR-based instructions. */
8358 f64 = *args == 'F' || *args == 'L';
8359 using_gprs = *args == 'F' || *args == 'f';
8361 save_in = input_line_pointer;
8362 input_line_pointer = s;
8363 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8365 s = input_line_pointer;
8366 input_line_pointer = save_in;
8367 if (err != NULL && *err != '\0')
8369 as_bad (_("Bad floating point constant: %s"), err);
8370 memset (temp, '\0', sizeof temp);
8371 length = f64 ? 8 : 4;
8374 assert (length == (unsigned) (f64 ? 8 : 4));
8378 && (! USE_GLOBAL_POINTER_OPT
8379 || mips_pic == EMBEDDED_PIC
8380 || g_switch_value < 4
8381 || (temp[0] == 0 && temp[1] == 0)
8382 || (temp[2] == 0 && temp[3] == 0))))
8384 imm_expr.X_op = O_constant;
8385 if (! target_big_endian)
8386 imm_expr.X_add_number = bfd_getl32 (temp);
8388 imm_expr.X_add_number = bfd_getb32 (temp);
8391 && ! mips_disable_float_construction
8392 /* Constants can only be constructed in GPRs and
8393 copied to FPRs if the GPRs are at least as wide
8394 as the FPRs. Force the constant into memory if
8395 we are using 64-bit FPRs but the GPRs are only
8398 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8399 && ((temp[0] == 0 && temp[1] == 0)
8400 || (temp[2] == 0 && temp[3] == 0))
8401 && ((temp[4] == 0 && temp[5] == 0)
8402 || (temp[6] == 0 && temp[7] == 0)))
8404 /* The value is simple enough to load with a couple of
8405 instructions. If using 32-bit registers, set
8406 imm_expr to the high order 32 bits and offset_expr to
8407 the low order 32 bits. Otherwise, set imm_expr to
8408 the entire 64 bit constant. */
8409 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8411 imm_expr.X_op = O_constant;
8412 offset_expr.X_op = O_constant;
8413 if (! target_big_endian)
8415 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8416 offset_expr.X_add_number = bfd_getl32 (temp);
8420 imm_expr.X_add_number = bfd_getb32 (temp);
8421 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8423 if (offset_expr.X_add_number == 0)
8424 offset_expr.X_op = O_absent;
8426 else if (sizeof (imm_expr.X_add_number) > 4)
8428 imm_expr.X_op = O_constant;
8429 if (! target_big_endian)
8430 imm_expr.X_add_number = bfd_getl64 (temp);
8432 imm_expr.X_add_number = bfd_getb64 (temp);
8436 imm_expr.X_op = O_big;
8437 imm_expr.X_add_number = 4;
8438 if (! target_big_endian)
8440 generic_bignum[0] = bfd_getl16 (temp);
8441 generic_bignum[1] = bfd_getl16 (temp + 2);
8442 generic_bignum[2] = bfd_getl16 (temp + 4);
8443 generic_bignum[3] = bfd_getl16 (temp + 6);
8447 generic_bignum[0] = bfd_getb16 (temp + 6);
8448 generic_bignum[1] = bfd_getb16 (temp + 4);
8449 generic_bignum[2] = bfd_getb16 (temp + 2);
8450 generic_bignum[3] = bfd_getb16 (temp);
8456 const char *newname;
8459 /* Switch to the right section. */
8461 subseg = now_subseg;
8464 default: /* unused default case avoids warnings. */
8466 newname = RDATA_SECTION_NAME;
8467 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8468 || mips_pic == EMBEDDED_PIC)
8472 if (mips_pic == EMBEDDED_PIC)
8475 newname = RDATA_SECTION_NAME;
8478 assert (!USE_GLOBAL_POINTER_OPT
8479 || g_switch_value >= 4);
8483 new_seg = subseg_new (newname, (subsegT) 0);
8484 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8485 bfd_set_section_flags (stdoutput, new_seg,
8490 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8491 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8492 && strcmp (TARGET_OS, "elf") != 0)
8493 record_alignment (new_seg, 4);
8495 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8497 as_bad (_("Can't use floating point insn in this section"));
8499 /* Set the argument to the current address in the
8501 offset_expr.X_op = O_symbol;
8502 offset_expr.X_add_symbol =
8503 symbol_new ("L0\001", now_seg,
8504 (valueT) frag_now_fix (), frag_now);
8505 offset_expr.X_add_number = 0;
8507 /* Put the floating point number into the section. */
8508 p = frag_more ((int) length);
8509 memcpy (p, temp, length);
8511 /* Switch back to the original section. */
8512 subseg_set (seg, subseg);
8517 case 'i': /* 16 bit unsigned immediate */
8518 case 'j': /* 16 bit signed immediate */
8519 *imm_reloc = BFD_RELOC_LO16;
8520 c = my_getSmallExpression (&imm_expr, s);
8525 if (imm_expr.X_op == O_constant)
8526 imm_expr.X_add_number =
8527 (imm_expr.X_add_number >> 16) & 0xffff;
8529 else if (c == S_EX_HIGHEST)
8530 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8531 else if (c == S_EX_HIGHER)
8532 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8533 else if (c == S_EX_GP_REL)
8535 /* This occurs in NewABI only. */
8536 c = my_getSmallExpression (&imm_expr, s);
8538 as_bad (_("bad composition of relocations"));
8541 c = my_getSmallExpression (&imm_expr, s);
8543 as_bad (_("bad composition of relocations"));
8546 imm_reloc[0] = BFD_RELOC_GPREL16;
8547 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8548 imm_reloc[2] = BFD_RELOC_LO16;
8553 else if (c == S_EX_HI)
8555 *imm_reloc = BFD_RELOC_HI16_S;
8556 imm_unmatched_hi = true;
8559 *imm_reloc = BFD_RELOC_HI16;
8561 else if (imm_expr.X_op == O_constant)
8562 imm_expr.X_add_number &= 0xffff;
8566 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8567 || ((imm_expr.X_add_number < 0
8568 || imm_expr.X_add_number >= 0x10000)
8569 && imm_expr.X_op == O_constant))
8571 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8572 !strcmp (insn->name, insn[1].name))
8574 if (imm_expr.X_op == O_constant
8575 || imm_expr.X_op == O_big)
8576 as_bad (_("16 bit expression not in range 0..65535"));
8584 /* The upper bound should be 0x8000, but
8585 unfortunately the MIPS assembler accepts numbers
8586 from 0x8000 to 0xffff and sign extends them, and
8587 we want to be compatible. We only permit this
8588 extended range for an instruction which does not
8589 provide any further alternates, since those
8590 alternates may handle other cases. People should
8591 use the numbers they mean, rather than relying on
8592 a mysterious sign extension. */
8593 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8594 strcmp (insn->name, insn[1].name) == 0);
8599 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8600 || ((imm_expr.X_add_number < -0x8000
8601 || imm_expr.X_add_number >= max)
8602 && imm_expr.X_op == O_constant)
8604 && imm_expr.X_add_number < 0
8606 && imm_expr.X_unsigned
8607 && sizeof (imm_expr.X_add_number) <= 4))
8611 if (imm_expr.X_op == O_constant
8612 || imm_expr.X_op == O_big)
8613 as_bad (_("16 bit expression not in range -32768..32767"));
8619 case 'o': /* 16 bit offset */
8620 c = my_getSmallExpression (&offset_expr, s);
8622 /* If this value won't fit into a 16 bit offset, then go
8623 find a macro that will generate the 32 bit offset
8626 && (offset_expr.X_op != O_constant
8627 || offset_expr.X_add_number >= 0x8000
8628 || offset_expr.X_add_number < -0x8000))
8633 if (offset_expr.X_op != O_constant)
8635 offset_expr.X_add_number =
8636 (offset_expr.X_add_number >> 16) & 0xffff;
8638 *offset_reloc = BFD_RELOC_LO16;
8642 case 'p': /* pc relative offset */
8643 if (mips_pic == EMBEDDED_PIC)
8644 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8646 *offset_reloc = BFD_RELOC_16_PCREL;
8647 my_getExpression (&offset_expr, s);
8651 case 'u': /* upper 16 bits */
8652 c = my_getSmallExpression (&imm_expr, s);
8653 *imm_reloc = BFD_RELOC_LO16;
8658 if (imm_expr.X_op == O_constant)
8659 imm_expr.X_add_number =
8660 (imm_expr.X_add_number >> 16) & 0xffff;
8661 else if (c == S_EX_HI)
8663 *imm_reloc = BFD_RELOC_HI16_S;
8664 imm_unmatched_hi = true;
8667 else if (c == S_EX_HIGHEST)
8668 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8669 else if (c == S_EX_GP_REL)
8671 /* This occurs in NewABI only. */
8672 c = my_getSmallExpression (&imm_expr, s);
8674 as_bad (_("bad composition of relocations"));
8677 c = my_getSmallExpression (&imm_expr, s);
8679 as_bad (_("bad composition of relocations"));
8682 imm_reloc[0] = BFD_RELOC_GPREL16;
8683 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8684 imm_reloc[2] = BFD_RELOC_HI16_S;
8690 *imm_reloc = BFD_RELOC_HI16;
8692 else if (imm_expr.X_op == O_constant)
8693 imm_expr.X_add_number &= 0xffff;
8695 if (imm_expr.X_op == O_constant
8696 && (imm_expr.X_add_number < 0
8697 || imm_expr.X_add_number >= 0x10000))
8698 as_bad (_("lui expression not in range 0..65535"));
8702 case 'a': /* 26 bit address */
8703 my_getExpression (&offset_expr, s);
8705 *offset_reloc = BFD_RELOC_MIPS_JMP;
8708 case 'N': /* 3 bit branch condition code */
8709 case 'M': /* 3 bit compare condition code */
8710 if (strncmp (s, "$fcc", 4) != 0)
8720 while (ISDIGIT (*s));
8722 as_bad (_("invalid condition code register $fcc%d"), regno);
8724 ip->insn_opcode |= regno << OP_SH_BCC;
8726 ip->insn_opcode |= regno << OP_SH_CCC;
8730 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8741 while (ISDIGIT (*s));
8744 c = 8; /* Invalid sel value. */
8747 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8748 ip->insn_opcode |= c;
8752 as_bad (_("bad char = '%c'\n"), *args);
8757 /* Args don't match. */
8758 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8759 !strcmp (insn->name, insn[1].name))
8763 insn_error = _("illegal operands");
8768 insn_error = _("illegal operands");
8773 /* This routine assembles an instruction into its binary format when
8774 assembling for the mips16. As a side effect, it sets one of the
8775 global variables imm_reloc or offset_reloc to the type of
8776 relocation to do if one of the operands is an address expression.
8777 It also sets mips16_small and mips16_ext if the user explicitly
8778 requested a small or extended instruction. */
8783 struct mips_cl_insn *ip;
8787 struct mips_opcode *insn;
8790 unsigned int lastregno = 0;
8795 mips16_small = false;
8798 for (s = str; ISLOWER (*s); ++s)
8810 if (s[1] == 't' && s[2] == ' ')
8813 mips16_small = true;
8817 else if (s[1] == 'e' && s[2] == ' ')
8826 insn_error = _("unknown opcode");
8830 if (mips_opts.noautoextend && ! mips16_ext)
8831 mips16_small = true;
8833 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8835 insn_error = _("unrecognized opcode");
8842 assert (strcmp (insn->name, str) == 0);
8845 ip->insn_opcode = insn->match;
8846 ip->use_extend = false;
8847 imm_expr.X_op = O_absent;
8848 imm_reloc[0] = BFD_RELOC_UNUSED;
8849 imm_reloc[1] = BFD_RELOC_UNUSED;
8850 imm_reloc[2] = BFD_RELOC_UNUSED;
8851 offset_expr.X_op = O_absent;
8852 offset_reloc[0] = BFD_RELOC_UNUSED;
8853 offset_reloc[1] = BFD_RELOC_UNUSED;
8854 offset_reloc[2] = BFD_RELOC_UNUSED;
8855 for (args = insn->args; 1; ++args)
8862 /* In this switch statement we call break if we did not find
8863 a match, continue if we did find a match, or return if we
8872 /* Stuff the immediate value in now, if we can. */
8873 if (imm_expr.X_op == O_constant
8874 && *imm_reloc > BFD_RELOC_UNUSED
8875 && insn->pinfo != INSN_MACRO)
8877 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8878 imm_expr.X_add_number, true, mips16_small,
8879 mips16_ext, &ip->insn_opcode,
8880 &ip->use_extend, &ip->extend);
8881 imm_expr.X_op = O_absent;
8882 *imm_reloc = BFD_RELOC_UNUSED;
8896 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8899 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8915 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8917 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8944 while (ISDIGIT (*s));
8947 as_bad (_("invalid register number (%d)"), regno);
8953 if (s[1] == 'r' && s[2] == 'a')
8958 else if (s[1] == 'f' && s[2] == 'p')
8963 else if (s[1] == 's' && s[2] == 'p')
8968 else if (s[1] == 'g' && s[2] == 'p')
8973 else if (s[1] == 'a' && s[2] == 't')
8978 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8983 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8988 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9001 if (c == 'v' || c == 'w')
9003 regno = mips16_to_32_reg_map[lastregno];
9017 regno = mips32_to_16_reg_map[regno];
9022 regno = ILLEGAL_REG;
9027 regno = ILLEGAL_REG;
9032 regno = ILLEGAL_REG;
9037 if (regno == AT && ! mips_opts.noat)
9038 as_warn (_("used $at without \".set noat\""));
9045 if (regno == ILLEGAL_REG)
9052 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9056 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9059 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9062 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9068 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9071 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9072 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9082 if (strncmp (s, "$pc", 3) == 0)
9106 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9108 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9109 and generate the appropriate reloc. If the text
9110 inside %gprel is not a symbol name with an
9111 optional offset, then we generate a normal reloc
9112 and will probably fail later. */
9113 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9114 if (imm_expr.X_op == O_symbol)
9117 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9119 ip->use_extend = true;
9126 /* Just pick up a normal expression. */
9127 my_getExpression (&imm_expr, s);
9130 if (imm_expr.X_op == O_register)
9132 /* What we thought was an expression turned out to
9135 if (s[0] == '(' && args[1] == '(')
9137 /* It looks like the expression was omitted
9138 before a register indirection, which means
9139 that the expression is implicitly zero. We
9140 still set up imm_expr, so that we handle
9141 explicit extensions correctly. */
9142 imm_expr.X_op = O_constant;
9143 imm_expr.X_add_number = 0;
9144 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9151 /* We need to relax this instruction. */
9152 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9161 /* We use offset_reloc rather than imm_reloc for the PC
9162 relative operands. This lets macros with both
9163 immediate and address operands work correctly. */
9164 my_getExpression (&offset_expr, s);
9166 if (offset_expr.X_op == O_register)
9169 /* We need to relax this instruction. */
9170 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9174 case '6': /* break code */
9175 my_getExpression (&imm_expr, s);
9176 check_absolute_expr (ip, &imm_expr);
9177 if ((unsigned long) imm_expr.X_add_number > 63)
9179 as_warn (_("Invalid value for `%s' (%lu)"),
9181 (unsigned long) imm_expr.X_add_number);
9182 imm_expr.X_add_number &= 0x3f;
9184 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9185 imm_expr.X_op = O_absent;
9189 case 'a': /* 26 bit address */
9190 my_getExpression (&offset_expr, s);
9192 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9193 ip->insn_opcode <<= 16;
9196 case 'l': /* register list for entry macro */
9197 case 'L': /* register list for exit macro */
9207 int freg, reg1, reg2;
9209 while (*s == ' ' || *s == ',')
9213 as_bad (_("can't parse register list"));
9225 while (ISDIGIT (*s))
9247 as_bad (_("invalid register list"));
9252 while (ISDIGIT (*s))
9259 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9264 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9269 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9270 mask |= (reg2 - 3) << 3;
9271 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9272 mask |= (reg2 - 15) << 1;
9273 else if (reg1 == RA && reg2 == RA)
9277 as_bad (_("invalid register list"));
9281 /* The mask is filled in in the opcode table for the
9282 benefit of the disassembler. We remove it before
9283 applying the actual mask. */
9284 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9285 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9289 case 'e': /* extend code */
9290 my_getExpression (&imm_expr, s);
9291 check_absolute_expr (ip, &imm_expr);
9292 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9294 as_warn (_("Invalid value for `%s' (%lu)"),
9296 (unsigned long) imm_expr.X_add_number);
9297 imm_expr.X_add_number &= 0x7ff;
9299 ip->insn_opcode |= imm_expr.X_add_number;
9300 imm_expr.X_op = O_absent;
9310 /* Args don't match. */
9311 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9312 strcmp (insn->name, insn[1].name) == 0)
9319 insn_error = _("illegal operands");
9325 /* This structure holds information we know about a mips16 immediate
9328 struct mips16_immed_operand
9330 /* The type code used in the argument string in the opcode table. */
9332 /* The number of bits in the short form of the opcode. */
9334 /* The number of bits in the extended form of the opcode. */
9336 /* The amount by which the short form is shifted when it is used;
9337 for example, the sw instruction has a shift count of 2. */
9339 /* The amount by which the short form is shifted when it is stored
9340 into the instruction code. */
9342 /* Non-zero if the short form is unsigned. */
9344 /* Non-zero if the extended form is unsigned. */
9346 /* Non-zero if the value is PC relative. */
9350 /* The mips16 immediate operand types. */
9352 static const struct mips16_immed_operand mips16_immed_operands[] =
9354 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9355 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9356 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9357 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9358 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9359 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9360 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9361 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9362 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9363 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9364 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9365 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9366 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9367 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9368 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9369 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9370 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9371 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9372 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9373 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9374 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9377 #define MIPS16_NUM_IMMED \
9378 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9380 /* Handle a mips16 instruction with an immediate value. This or's the
9381 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9382 whether an extended value is needed; if one is needed, it sets
9383 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9384 If SMALL is true, an unextended opcode was explicitly requested.
9385 If EXT is true, an extended opcode was explicitly requested. If
9386 WARN is true, warn if EXT does not match reality. */
9389 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9398 unsigned long *insn;
9399 boolean *use_extend;
9400 unsigned short *extend;
9402 register const struct mips16_immed_operand *op;
9403 int mintiny, maxtiny;
9406 op = mips16_immed_operands;
9407 while (op->type != type)
9410 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9415 if (type == '<' || type == '>' || type == '[' || type == ']')
9418 maxtiny = 1 << op->nbits;
9423 maxtiny = (1 << op->nbits) - 1;
9428 mintiny = - (1 << (op->nbits - 1));
9429 maxtiny = (1 << (op->nbits - 1)) - 1;
9432 /* Branch offsets have an implicit 0 in the lowest bit. */
9433 if (type == 'p' || type == 'q')
9436 if ((val & ((1 << op->shift) - 1)) != 0
9437 || val < (mintiny << op->shift)
9438 || val > (maxtiny << op->shift))
9443 if (warn && ext && ! needext)
9444 as_warn_where (file, line,
9445 _("extended operand requested but not required"));
9446 if (small && needext)
9447 as_bad_where (file, line, _("invalid unextended operand value"));
9449 if (small || (! ext && ! needext))
9453 *use_extend = false;
9454 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9455 insnval <<= op->op_shift;
9460 long minext, maxext;
9466 maxext = (1 << op->extbits) - 1;
9470 minext = - (1 << (op->extbits - 1));
9471 maxext = (1 << (op->extbits - 1)) - 1;
9473 if (val < minext || val > maxext)
9474 as_bad_where (file, line,
9475 _("operand value out of range for instruction"));
9478 if (op->extbits == 16)
9480 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9483 else if (op->extbits == 15)
9485 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9490 extval = ((val & 0x1f) << 6) | (val & 0x20);
9494 *extend = (unsigned short) extval;
9499 static struct percent_op_match
9502 const enum small_ex_type type;
9507 {"%call_hi", S_EX_CALL_HI},
9508 {"%call_lo", S_EX_CALL_LO},
9509 {"%call16", S_EX_CALL16},
9510 {"%got_disp", S_EX_GOT_DISP},
9511 {"%got_page", S_EX_GOT_PAGE},
9512 {"%got_ofst", S_EX_GOT_OFST},
9513 {"%got_hi", S_EX_GOT_HI},
9514 {"%got_lo", S_EX_GOT_LO},
9516 {"%gp_rel", S_EX_GP_REL},
9517 {"%half", S_EX_HALF},
9518 {"%highest", S_EX_HIGHEST},
9519 {"%higher", S_EX_HIGHER},
9525 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9526 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9527 can be nested, this is handled by blanking the innermost, parsing the
9528 rest by subsequent calls. */
9531 my_getSmallParser (str, len, nestlevel)
9537 *str += strspn (*str, " \t");
9538 /* Check for expression in parentheses. */
9541 char *b = *str + 1 + strspn (*str + 1, " \t");
9544 /* Check for base register. */
9548 && (e = b + strcspn (b, ") \t"))
9549 && e - b > 1 && e - b < 4)
9552 && ((b[1] == 'f' && b[2] == 'p')
9553 || (b[1] == 's' && b[2] == 'p')
9554 || (b[1] == 'g' && b[2] == 'p')
9555 || (b[1] == 'a' && b[2] == 't')
9557 && ISDIGIT (b[2]))))
9558 || (ISDIGIT (b[1])))
9560 *len = strcspn (*str, ")") + 1;
9561 return S_EX_REGISTER;
9565 /* Check for percent_op (in parentheses). */
9566 else if (b[0] == '%')
9569 return my_getPercentOp (str, len, nestlevel);
9572 /* Some other expression in the parentheses, which can contain
9573 parentheses itself. Attempt to find the matching one. */
9579 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9588 /* Check for percent_op (outside of parentheses). */
9589 else if (*str[0] == '%')
9590 return my_getPercentOp (str, len, nestlevel);
9592 /* Any other expression. */
9597 my_getPercentOp (str, len, nestlevel)
9602 char *tmp = *str + 1;
9605 while (ISALPHA (*tmp) || *tmp == '_')
9607 *tmp = TOLOWER (*tmp);
9610 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9612 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9616 int type = percent_op[i].type;
9618 /* Only %hi and %lo are allowed for OldABI. */
9619 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9622 *len = strlen (percent_op[i].str);
9631 my_getSmallExpression (ep, str)
9635 static char *oldstr = NULL;
9641 /* Don't update oldstr if the last call had nested percent_op's. We need
9642 it to parse the outer ones later. */
9649 c = my_getSmallParser (&str, &len, &nestlevel);
9650 if (c != S_EX_NONE && c != S_EX_REGISTER)
9653 while (c != S_EX_NONE && c != S_EX_REGISTER);
9657 /* A percent_op was encountered. Don't try to get an expression if
9658 it is already blanked out. */
9659 if (*(str + strspn (str + 1, " )")) != ')')
9663 /* Let my_getExpression() stop at the closing parenthesis. */
9664 save = *(str + len);
9665 *(str + len) = '\0';
9666 my_getExpression (ep, str);
9667 *(str + len) = save;
9671 /* Blank out including the % sign and the proper matching
9674 char *s = strrchr (oldstr, '%');
9677 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9681 else if (*end == ')')
9685 memset (s, ' ', end - s);
9689 expr_end = str + len;
9693 else if (c == S_EX_NONE)
9695 my_getExpression (ep, str);
9697 else if (c == S_EX_REGISTER)
9699 ep->X_op = O_constant;
9701 ep->X_add_symbol = NULL;
9702 ep->X_op_symbol = NULL;
9703 ep->X_add_number = 0;
9707 as_fatal (_("internal error"));
9711 /* All percent_op's have been handled. */
9718 my_getExpression (ep, str)
9725 save_in = input_line_pointer;
9726 input_line_pointer = str;
9728 expr_end = input_line_pointer;
9729 input_line_pointer = save_in;
9731 /* If we are in mips16 mode, and this is an expression based on `.',
9732 then we bump the value of the symbol by 1 since that is how other
9733 text symbols are handled. We don't bother to handle complex
9734 expressions, just `.' plus or minus a constant. */
9735 if (mips_opts.mips16
9736 && ep->X_op == O_symbol
9737 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9738 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9739 && symbol_get_frag (ep->X_add_symbol) == frag_now
9740 && symbol_constant_p (ep->X_add_symbol)
9741 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9742 S_SET_VALUE (ep->X_add_symbol, val + 1);
9745 /* Turn a string in input_line_pointer into a floating point constant
9746 of type TYPE, and store the appropriate bytes in *LITP. The number
9747 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9748 returned, or NULL on OK. */
9751 md_atof (type, litP, sizeP)
9757 LITTLENUM_TYPE words[4];
9773 return _("bad call to md_atof");
9776 t = atof_ieee (input_line_pointer, type, words);
9778 input_line_pointer = t;
9782 if (! target_big_endian)
9784 for (i = prec - 1; i >= 0; i--)
9786 md_number_to_chars (litP, (valueT) words[i], 2);
9792 for (i = 0; i < prec; i++)
9794 md_number_to_chars (litP, (valueT) words[i], 2);
9803 md_number_to_chars (buf, val, n)
9808 if (target_big_endian)
9809 number_to_chars_bigendian (buf, val, n);
9811 number_to_chars_littleendian (buf, val, n);
9815 static int support_64bit_objects(void)
9817 const char **list, **l;
9819 list = bfd_target_list ();
9820 for (l = list; *l != NULL; l++)
9822 /* This is traditional mips */
9823 if (strcmp (*l, "elf64-tradbigmips") == 0
9824 || strcmp (*l, "elf64-tradlittlemips") == 0)
9826 if (strcmp (*l, "elf64-bigmips") == 0
9827 || strcmp (*l, "elf64-littlemips") == 0)
9831 return (*l != NULL);
9833 #endif /* OBJ_ELF */
9835 const char *md_shortopts = "nO::g::G:";
9837 struct option md_longopts[] =
9839 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9840 {"mips0", no_argument, NULL, OPTION_MIPS1},
9841 {"mips1", no_argument, NULL, OPTION_MIPS1},
9842 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9843 {"mips2", no_argument, NULL, OPTION_MIPS2},
9844 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9845 {"mips3", no_argument, NULL, OPTION_MIPS3},
9846 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9847 {"mips4", no_argument, NULL, OPTION_MIPS4},
9848 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9849 {"mips5", no_argument, NULL, OPTION_MIPS5},
9850 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9851 {"mips32", no_argument, NULL, OPTION_MIPS32},
9852 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9853 {"mips64", no_argument, NULL, OPTION_MIPS64},
9854 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9855 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9856 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9857 {"trap", no_argument, NULL, OPTION_TRAP},
9858 {"no-break", no_argument, NULL, OPTION_TRAP},
9859 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9860 {"break", no_argument, NULL, OPTION_BREAK},
9861 {"no-trap", no_argument, NULL, OPTION_BREAK},
9862 #define OPTION_EB (OPTION_MD_BASE + 11)
9863 {"EB", no_argument, NULL, OPTION_EB},
9864 #define OPTION_EL (OPTION_MD_BASE + 12)
9865 {"EL", no_argument, NULL, OPTION_EL},
9866 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9867 {"mips16", no_argument, NULL, OPTION_MIPS16},
9868 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9869 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9870 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9871 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9872 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9873 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9874 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9875 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9876 {"mfp32", no_argument, NULL, OPTION_FP32},
9877 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9878 {"mgp32", no_argument, NULL, OPTION_GP32},
9879 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9880 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9881 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9882 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9883 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9884 {"march", required_argument, NULL, OPTION_MARCH},
9885 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9886 {"mtune", required_argument, NULL, OPTION_MTUNE},
9887 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9888 {"mcpu", required_argument, NULL, OPTION_MCPU},
9889 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9890 {"m4650", no_argument, NULL, OPTION_M4650},
9891 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9892 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9893 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9894 {"m4010", no_argument, NULL, OPTION_M4010},
9895 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9896 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9897 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9898 {"m4100", no_argument, NULL, OPTION_M4100},
9899 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9900 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9901 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9902 {"m3900", no_argument, NULL, OPTION_M3900},
9903 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9904 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9905 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9906 {"mgp64", no_argument, NULL, OPTION_GP64},
9907 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9908 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
9909 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9910 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
9911 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9912 {"mdmx", no_argument, NULL, OPTION_MDMX},
9913 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9914 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
9916 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9917 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9918 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9919 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9920 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9921 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
9922 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9923 {"xgot", no_argument, NULL, OPTION_XGOT},
9924 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9925 {"mabi", required_argument, NULL, OPTION_MABI},
9926 #define OPTION_32 (OPTION_ELF_BASE + 4)
9927 {"32", no_argument, NULL, OPTION_32},
9928 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9929 {"n32", no_argument, NULL, OPTION_N32},
9930 #define OPTION_64 (OPTION_ELF_BASE + 6)
9931 {"64", no_argument, NULL, OPTION_64},
9932 #endif /* OBJ_ELF */
9933 {NULL, no_argument, NULL, 0}
9935 size_t md_longopts_size = sizeof (md_longopts);
9938 md_parse_option (c, arg)
9944 case OPTION_CONSTRUCT_FLOATS:
9945 mips_disable_float_construction = 0;
9948 case OPTION_NO_CONSTRUCT_FLOATS:
9949 mips_disable_float_construction = 1;
9961 target_big_endian = 1;
9965 target_big_endian = 0;
9973 if (arg && arg[1] == '0')
9983 mips_debug = atoi (arg);
9984 /* When the MIPS assembler sees -g or -g2, it does not do
9985 optimizations which limit full symbolic debugging. We take
9986 that to be equivalent to -O0. */
9987 if (mips_debug == 2)
9992 mips_opts.isa = ISA_MIPS1;
9996 mips_opts.isa = ISA_MIPS2;
10000 mips_opts.isa = ISA_MIPS3;
10004 mips_opts.isa = ISA_MIPS4;
10008 mips_opts.isa = ISA_MIPS5;
10011 case OPTION_MIPS32:
10012 mips_opts.isa = ISA_MIPS32;
10015 case OPTION_MIPS64:
10016 mips_opts.isa = ISA_MIPS64;
10023 int cpu = CPU_UNKNOWN;
10025 /* Identify the processor type. */
10026 if (strcasecmp (arg, "default") != 0)
10028 const struct mips_cpu_info *ci;
10030 ci = mips_cpu_info_from_name (arg);
10031 if (ci == NULL || ci->is_isa)
10036 as_fatal (_("invalid architecture -mtune=%s"), arg);
10039 as_fatal (_("invalid architecture -march=%s"), arg);
10042 as_fatal (_("invalid architecture -mcpu=%s"), arg);
10053 if (mips_tune != CPU_UNKNOWN && mips_tune != cpu)
10054 as_warn (_("A different -mtune= was already specified, is now "
10055 "-mtune=%s"), arg);
10059 if (mips_arch != CPU_UNKNOWN && mips_arch != cpu)
10060 as_warn (_("A different -march= was already specified, is now "
10061 "-march=%s"), arg);
10065 if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu)
10066 as_warn (_("A different -mcpu= was already specified, is now "
10074 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650)
10075 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650))
10076 as_warn (_("A different -march= or -mtune= was already specified, "
10078 mips_arch = CPU_R4650;
10079 mips_tune = CPU_R4650;
10082 case OPTION_NO_M4650:
10086 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010)
10087 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010))
10088 as_warn (_("A different -march= or -mtune= was already specified, "
10090 mips_arch = CPU_R4010;
10091 mips_tune = CPU_R4010;
10094 case OPTION_NO_M4010:
10098 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100)
10099 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100))
10100 as_warn (_("A different -march= or -mtune= was already specified, "
10102 mips_arch = CPU_VR4100;
10103 mips_tune = CPU_VR4100;
10106 case OPTION_NO_M4100:
10110 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900)
10111 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900))
10112 as_warn (_("A different -march= or -mtune= was already specified, "
10114 mips_arch = CPU_R3900;
10115 mips_tune = CPU_R3900;
10118 case OPTION_NO_M3900:
10122 mips_opts.ase_mdmx = 1;
10125 case OPTION_NO_MDMX:
10126 mips_opts.ase_mdmx = 0;
10129 case OPTION_MIPS16:
10130 mips_opts.mips16 = 1;
10131 mips_no_prev_insn (false);
10134 case OPTION_NO_MIPS16:
10135 mips_opts.mips16 = 0;
10136 mips_no_prev_insn (false);
10139 case OPTION_MIPS3D:
10140 mips_opts.ase_mips3d = 1;
10143 case OPTION_NO_MIPS3D:
10144 mips_opts.ase_mips3d = 0;
10147 case OPTION_MEMBEDDED_PIC:
10148 mips_pic = EMBEDDED_PIC;
10149 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10151 as_bad (_("-G may not be used with embedded PIC code"));
10154 g_switch_value = 0x7fffffff;
10158 /* When generating ELF code, we permit -KPIC and -call_shared to
10159 select SVR4_PIC, and -non_shared to select no PIC. This is
10160 intended to be compatible with Irix 5. */
10161 case OPTION_CALL_SHARED:
10162 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10164 as_bad (_("-call_shared is supported only for ELF format"));
10167 mips_pic = SVR4_PIC;
10168 if (g_switch_seen && g_switch_value != 0)
10170 as_bad (_("-G may not be used with SVR4 PIC code"));
10173 g_switch_value = 0;
10176 case OPTION_NON_SHARED:
10177 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10179 as_bad (_("-non_shared is supported only for ELF format"));
10185 /* The -xgot option tells the assembler to use 32 offsets when
10186 accessing the got in SVR4_PIC mode. It is for Irix
10191 #endif /* OBJ_ELF */
10194 if (! USE_GLOBAL_POINTER_OPT)
10196 as_bad (_("-G is not supported for this configuration"));
10199 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10201 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10205 g_switch_value = atoi (arg);
10210 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10213 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10215 as_bad (_("-32 is supported for ELF format only"));
10218 mips_opts.abi = O32_ABI;
10222 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10224 as_bad (_("-n32 is supported for ELF format only"));
10227 mips_opts.abi = N32_ABI;
10231 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10233 as_bad (_("-64 is supported for ELF format only"));
10236 mips_opts.abi = N64_ABI;
10237 if (! support_64bit_objects())
10238 as_fatal (_("No compiled in support for 64 bit object file format"));
10240 #endif /* OBJ_ELF */
10243 file_mips_gp32 = 1;
10244 if (mips_opts.abi != O32_ABI)
10245 mips_opts.abi = NO_ABI;
10249 file_mips_gp32 = 0;
10250 if (mips_opts.abi == O32_ABI)
10251 mips_opts.abi = NO_ABI;
10255 file_mips_fp32 = 1;
10256 if (mips_opts.abi != O32_ABI)
10257 mips_opts.abi = NO_ABI;
10262 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10264 as_bad (_("-mabi is supported for ELF format only"));
10267 if (strcmp (arg, "32") == 0)
10268 mips_opts.abi = O32_ABI;
10269 else if (strcmp (arg, "o64") == 0)
10270 mips_opts.abi = O64_ABI;
10271 else if (strcmp (arg, "n32") == 0)
10272 mips_opts.abi = N32_ABI;
10273 else if (strcmp (arg, "64") == 0)
10275 mips_opts.abi = N64_ABI;
10276 if (! support_64bit_objects())
10277 as_fatal (_("No compiled in support for 64 bit object file "
10280 else if (strcmp (arg, "eabi") == 0)
10281 mips_opts.abi = EABI_ABI;
10284 as_fatal (_("invalid abi -mabi=%s"), arg);
10288 #endif /* OBJ_ELF */
10290 case OPTION_M7000_HILO_FIX:
10291 mips_7000_hilo_fix = true;
10294 case OPTION_MNO_7000_HILO_FIX:
10295 mips_7000_hilo_fix = false;
10306 show (stream, string, col_p, first_p)
10314 fprintf (stream, "%24s", "");
10319 fprintf (stream, ", ");
10323 if (*col_p + strlen (string) > 72)
10325 fprintf (stream, "\n%24s", "");
10329 fprintf (stream, "%s", string);
10330 *col_p += strlen (string);
10336 md_show_usage (stream)
10341 fprintf (stream, _("\
10343 -membedded-pic generate embedded position independent code\n\
10344 -EB generate big endian output\n\
10345 -EL generate little endian output\n\
10346 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10347 -G NUM allow referencing objects up to NUM bytes\n\
10348 implicitly with the gp register [default 8]\n"));
10349 fprintf (stream, _("\
10350 -mips1 generate MIPS ISA I instructions\n\
10351 -mips2 generate MIPS ISA II instructions\n\
10352 -mips3 generate MIPS ISA III instructions\n\
10353 -mips4 generate MIPS ISA IV instructions\n\
10354 -mips5 generate MIPS ISA V instructions\n\
10355 -mips32 generate MIPS32 ISA instructions\n\
10356 -mips64 generate MIPS64 ISA instructions\n\
10357 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10361 show (stream, "2000", &column, &first);
10362 show (stream, "3000", &column, &first);
10363 show (stream, "3900", &column, &first);
10364 show (stream, "4000", &column, &first);
10365 show (stream, "4010", &column, &first);
10366 show (stream, "4100", &column, &first);
10367 show (stream, "4111", &column, &first);
10368 show (stream, "4300", &column, &first);
10369 show (stream, "4400", &column, &first);
10370 show (stream, "4600", &column, &first);
10371 show (stream, "4650", &column, &first);
10372 show (stream, "5000", &column, &first);
10373 show (stream, "5200", &column, &first);
10374 show (stream, "5230", &column, &first);
10375 show (stream, "5231", &column, &first);
10376 show (stream, "5261", &column, &first);
10377 show (stream, "5721", &column, &first);
10378 show (stream, "6000", &column, &first);
10379 show (stream, "8000", &column, &first);
10380 show (stream, "10000", &column, &first);
10381 show (stream, "12000", &column, &first);
10382 show (stream, "sb1", &column, &first);
10383 fputc ('\n', stream);
10385 fprintf (stream, _("\
10386 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10387 -no-mCPU don't generate code specific to CPU.\n\
10388 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10392 show (stream, "3900", &column, &first);
10393 show (stream, "4010", &column, &first);
10394 show (stream, "4100", &column, &first);
10395 show (stream, "4650", &column, &first);
10396 fputc ('\n', stream);
10398 fprintf (stream, _("\
10399 -mips16 generate mips16 instructions\n\
10400 -no-mips16 do not generate mips16 instructions\n"));
10401 fprintf (stream, _("\
10402 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10403 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10404 -O0 remove unneeded NOPs, do not swap branches\n\
10405 -O remove unneeded NOPs and swap branches\n\
10406 -n warn about NOPs generated from macros\n\
10407 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10408 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10409 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10411 fprintf (stream, _("\
10412 -KPIC, -call_shared generate SVR4 position independent code\n\
10413 -non_shared do not generate position independent code\n\
10414 -xgot assume a 32 bit GOT\n\
10415 -mabi=ABI create ABI conformant object file for:\n"));
10419 show (stream, "32", &column, &first);
10420 show (stream, "o64", &column, &first);
10421 show (stream, "n32", &column, &first);
10422 show (stream, "64", &column, &first);
10423 show (stream, "eabi", &column, &first);
10425 fputc ('\n', stream);
10427 fprintf (stream, _("\
10428 -32 create o32 ABI object file (default)\n\
10429 -n32 create n32 ABI object file\n\
10430 -64 create 64 ABI object file\n"));
10435 mips_after_parse_args ()
10439 int mips_isa_from_cpu;
10440 const struct mips_cpu_info *ci;
10442 /* GP relative stuff not working for PE */
10443 if (strncmp (TARGET_OS, "pe", 2) == 0
10444 && g_switch_value != 0)
10447 as_bad (_("-G not supported in this configuration."));
10448 g_switch_value = 0;
10452 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
10454 a = xmalloc (sizeof TARGET_CPU);
10455 strcpy (a, TARGET_CPU);
10456 a[(sizeof TARGET_CPU) - 3] = '\0';
10460 /* Backward compatibility for historic -mcpu= option. Check for
10461 incompatible options, warn if -mcpu is used. */
10462 if (mips_cpu != CPU_UNKNOWN
10463 && mips_arch != CPU_UNKNOWN
10464 && mips_cpu != mips_arch)
10466 as_fatal (_("The -mcpu option can't be used together with -march. "
10467 "Use -mtune instead of -mcpu."));
10470 if (mips_cpu != CPU_UNKNOWN
10471 && mips_tune != CPU_UNKNOWN
10472 && mips_cpu != mips_tune)
10474 as_fatal (_("The -mcpu option can't be used together with -mtune. "
10475 "Use -march instead of -mcpu."));
10479 /* For backward compatibility, let -mipsN set various defaults. */
10480 /* This code should go away, to be replaced with something rather more
10481 draconian. Until GCC 3.1 has been released for some reasonable
10482 amount of time, however, we need to support this. */
10483 if (mips_opts.isa != ISA_UNKNOWN)
10485 /* Translate -mipsN to the appropriate settings of file_mips_gp32
10486 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
10487 if (file_mips_gp32 < 0)
10489 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
10490 file_mips_gp32 = 0;
10492 file_mips_gp32 = 1;
10494 if (file_mips_fp32 < 0)
10496 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
10497 file_mips_fp32 = 0;
10499 file_mips_fp32 = 1;
10502 ci = mips_cpu_info_from_isa (mips_opts.isa);
10503 assert (ci != NULL);
10504 /* -mipsN has higher priority than -mcpu but lower than -march. */
10505 if (mips_arch == CPU_UNKNOWN)
10506 mips_arch = ci->cpu;
10508 /* Default mips_abi. */
10509 if (mips_opts.abi == NO_ABI)
10511 if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2)
10512 mips_opts.abi = O32_ABI;
10513 else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4)
10514 mips_opts.abi = O64_ABI;
10518 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10520 ci = mips_cpu_info_from_cpu (mips_cpu);
10521 assert (ci != NULL);
10522 mips_arch = ci->cpu;
10523 as_warn (_("The -mcpu option is deprecated. Please use -march and "
10524 "-mtune instead."));
10527 /* Set tune from -mcpu, not from -mipsN. */
10528 if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10530 ci = mips_cpu_info_from_cpu (mips_cpu);
10531 assert (ci != NULL);
10532 mips_tune = ci->cpu;
10535 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
10536 specified on the command line, or some other value if one was.
10537 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
10538 the command line, or will be set otherwise if one was. */
10540 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10541 /* Handled above. */;
10543 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10545 ci = mips_cpu_info_from_cpu (mips_cpu);
10546 assert (ci != NULL);
10547 mips_arch = ci->cpu;
10548 as_warn (_("The -mcpu option is deprecated. Please use -march and "
10549 "-mtune instead."));
10552 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
10553 specified on the command line, or some other value if one was.
10554 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
10555 the command line, or will be set otherwise if one was. */
10557 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10559 /* We have to check if the isa is the default isa of arch. Otherwise
10560 we'll get invalid object file headers. */
10561 ci = mips_cpu_info_from_cpu (mips_arch);
10562 assert (ci != NULL);
10563 if (mips_opts.isa != ci->isa)
10565 /* This really should be an error instead of a warning, but old
10566 compilers only have -mcpu which sets both arch and tune. For
10567 now, we discard arch and preserve tune. */
10568 as_warn (_("The -march option is incompatible to -mipsN and "
10569 "therefore ignored."));
10570 if (mips_tune == CPU_UNKNOWN)
10571 mips_tune = mips_arch;
10572 ci = mips_cpu_info_from_isa (mips_opts.isa);
10573 assert (ci != NULL);
10574 mips_arch = ci->cpu;
10578 else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
10580 /* We have ARCH, we need ISA. */
10581 ci = mips_cpu_info_from_cpu (mips_arch);
10582 assert (ci != NULL);
10583 mips_opts.isa = ci->isa;
10585 else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10587 /* We have ISA, we need default ARCH. */
10588 ci = mips_cpu_info_from_isa (mips_opts.isa);
10589 assert (ci != NULL);
10590 mips_arch = ci->cpu;
10594 /* We need to set both ISA and ARCH from target cpu. */
10595 ci = mips_cpu_info_from_name (cpu);
10597 ci = mips_cpu_info_from_cpu (CPU_R3000);
10598 assert (ci != NULL);
10599 mips_opts.isa = ci->isa;
10600 mips_arch = ci->cpu;
10603 if (mips_tune == CPU_UNKNOWN)
10604 mips_tune = mips_arch;
10606 ci = mips_cpu_info_from_cpu (mips_arch);
10607 assert (ci != NULL);
10608 mips_isa_from_cpu = ci->isa;
10610 /* End of TARGET_CPU processing, get rid of malloced memory
10619 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10620 as_bad (_("trap exception not supported at ISA 1"));
10622 /* If they asked for mips1 or mips2 and a cpu that is
10623 mips3 or greater, then mark the object file 32BITMODE. */
10624 if (mips_isa_from_cpu != ISA_UNKNOWN
10625 && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
10626 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
10627 mips_32bitmode = 1;
10629 /* If the selected architecture includes support for ASEs, enable
10630 generation of code for them. */
10631 if (mips_opts.mips16 == -1)
10632 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10633 if (mips_opts.ase_mips3d == -1)
10634 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10635 if (mips_opts.ase_mdmx == -1)
10636 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10638 if (file_mips_gp32 < 0)
10639 file_mips_gp32 = 0;
10640 if (file_mips_fp32 < 0)
10641 file_mips_fp32 = 0;
10643 file_mips_isa = mips_opts.isa;
10644 file_mips_abi = mips_opts.abi;
10645 file_ase_mips16 = mips_opts.mips16;
10646 file_ase_mips3d = mips_opts.ase_mips3d;
10647 file_ase_mdmx = mips_opts.ase_mdmx;
10648 mips_opts.gp32 = file_mips_gp32;
10649 mips_opts.fp32 = file_mips_fp32;
10656 mips_init_after_args ()
10658 /* initialize opcodes */
10659 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10660 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10664 md_pcrel_from (fixP)
10667 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10668 && fixP->fx_addsy != (symbolS *) NULL
10669 && ! S_IS_DEFINED (fixP->fx_addsy))
10671 /* This makes a branch to an undefined symbol be a branch to the
10672 current location. */
10673 if (mips_pic == EMBEDDED_PIC)
10679 /* Return the address of the delay slot. */
10680 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10683 /* This is called before the symbol table is processed. In order to
10684 work with gcc when using mips-tfile, we must keep all local labels.
10685 However, in other cases, we want to discard them. If we were
10686 called with -g, but we didn't see any debugging information, it may
10687 mean that gcc is smuggling debugging information through to
10688 mips-tfile, in which case we must generate all local labels. */
10691 mips_frob_file_before_adjust ()
10693 #ifndef NO_ECOFF_DEBUGGING
10694 if (ECOFF_DEBUGGING
10696 && ! ecoff_debugging_seen)
10697 flag_keep_locals = 1;
10701 /* Sort any unmatched HI16_S relocs so that they immediately precede
10702 the corresponding LO reloc. This is called before md_apply_fix3 and
10703 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10704 explicit use of the %hi modifier. */
10709 struct mips_hi_fixup *l;
10711 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10713 segment_info_type *seginfo;
10716 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10718 /* Check quickly whether the next fixup happens to be a matching
10720 if (l->fixp->fx_next != NULL
10721 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10722 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10723 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10726 /* Look through the fixups for this segment for a matching %lo.
10727 When we find one, move the %hi just in front of it. We do
10728 this in two passes. In the first pass, we try to find a
10729 unique %lo. In the second pass, we permit multiple %hi
10730 relocs for a single %lo (this is a GNU extension). */
10731 seginfo = seg_info (l->seg);
10732 for (pass = 0; pass < 2; pass++)
10737 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10739 /* Check whether this is a %lo fixup which matches l->fixp. */
10740 if (f->fx_r_type == BFD_RELOC_LO16
10741 && f->fx_addsy == l->fixp->fx_addsy
10742 && f->fx_offset == l->fixp->fx_offset
10745 || prev->fx_r_type != BFD_RELOC_HI16_S
10746 || prev->fx_addsy != f->fx_addsy
10747 || prev->fx_offset != f->fx_offset))
10751 /* Move l->fixp before f. */
10752 for (pf = &seginfo->fix_root;
10754 pf = &(*pf)->fx_next)
10755 assert (*pf != NULL);
10757 *pf = l->fixp->fx_next;
10759 l->fixp->fx_next = f;
10761 seginfo->fix_root = l->fixp;
10763 prev->fx_next = l->fixp;
10774 #if 0 /* GCC code motion plus incomplete dead code elimination
10775 can leave a %hi without a %lo. */
10777 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10778 _("Unmatched %%hi reloc"));
10784 /* When generating embedded PIC code we need to use a special
10785 relocation to represent the difference of two symbols in the .text
10786 section (switch tables use a difference of this sort). See
10787 include/coff/mips.h for details. This macro checks whether this
10788 fixup requires the special reloc. */
10789 #define SWITCH_TABLE(fixp) \
10790 ((fixp)->fx_r_type == BFD_RELOC_32 \
10791 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10792 && (fixp)->fx_addsy != NULL \
10793 && (fixp)->fx_subsy != NULL \
10794 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10795 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10797 /* When generating embedded PIC code we must keep all PC relative
10798 relocations, in case the linker has to relax a call. We also need
10799 to keep relocations for switch table entries.
10801 We may have combined relocations without symbols in the N32/N64 ABI.
10802 We have to prevent gas from dropping them. */
10805 mips_force_relocation (fixp)
10808 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10809 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10813 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10814 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10815 || fixp->fx_r_type == BFD_RELOC_HI16_S
10816 || fixp->fx_r_type == BFD_RELOC_LO16))
10819 return (mips_pic == EMBEDDED_PIC
10821 || SWITCH_TABLE (fixp)
10822 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10823 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10828 mips_need_elf_addend_fixup (fixP)
10831 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10833 if (mips_pic == EMBEDDED_PIC
10834 && S_IS_WEAK (fixP->fx_addsy))
10836 if (mips_pic != EMBEDDED_PIC
10837 && (S_IS_WEAK (fixP->fx_addsy)
10838 || S_IS_EXTERN (fixP->fx_addsy))
10839 && !S_IS_COMMON (fixP->fx_addsy))
10841 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10842 && (((bfd_get_section_flags (stdoutput,
10843 S_GET_SEGMENT (fixP->fx_addsy))
10844 & SEC_LINK_ONCE) != 0)
10845 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10847 sizeof (".gnu.linkonce") - 1)))
10853 /* Apply a fixup to the object file. */
10856 md_apply_fix3 (fixP, valP, seg)
10859 segT seg ATTRIBUTE_UNUSED;
10865 assert (fixP->fx_size == 4
10866 || fixP->fx_r_type == BFD_RELOC_16
10867 || fixP->fx_r_type == BFD_RELOC_32
10868 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10869 || fixP->fx_r_type == BFD_RELOC_HI16_S
10870 || fixP->fx_r_type == BFD_RELOC_LO16
10871 || fixP->fx_r_type == BFD_RELOC_GPREL16
10872 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10873 || fixP->fx_r_type == BFD_RELOC_GPREL32
10874 || fixP->fx_r_type == BFD_RELOC_64
10875 || fixP->fx_r_type == BFD_RELOC_CTOR
10876 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10877 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10878 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10879 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10880 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10881 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10882 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10883 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10884 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
10888 /* If we aren't adjusting this fixup to be against the section
10889 symbol, we need to adjust the value. */
10891 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10893 if (mips_need_elf_addend_fixup (fixP))
10895 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10898 if (value != 0 && ! fixP->fx_pcrel)
10900 /* In this case, the bfd_install_relocation routine will
10901 incorrectly add the symbol value back in. We just want
10902 the addend to appear in the object file. */
10905 /* Make sure the addend is still non-zero. If it became zero
10906 after the last operation, set it to a spurious value and
10907 subtract the same value from the object file's contents. */
10912 /* The in-place addends for LO16 relocations are signed;
10913 leave the matching HI16 in-place addends as zero. */
10914 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10916 reloc_howto_type *howto;
10917 bfd_vma contents, mask, field;
10919 howto = bfd_reloc_type_lookup (stdoutput,
10922 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10925 target_big_endian);
10927 /* MASK has bits set where the relocation should go.
10928 FIELD is -value, shifted into the appropriate place
10929 for this relocation. */
10930 mask = 1 << (howto->bitsize - 1);
10931 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10932 field = (-value >> howto->rightshift) << howto->bitpos;
10934 bfd_put_bits ((field & mask) | (contents & ~mask),
10935 fixP->fx_frag->fr_literal + fixP->fx_where,
10937 target_big_endian);
10943 /* This code was generated using trial and error and so is
10944 fragile and not trustworthy. If you change it, you should
10945 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10946 they still pass. */
10947 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10949 value += fixP->fx_frag->fr_address + fixP->fx_where;
10951 /* BFD's REL handling, for MIPS, is _very_ weird.
10952 This gives the right results, but it can't possibly
10953 be the way things are supposed to work. */
10954 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10955 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10956 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10957 value += fixP->fx_frag->fr_address + fixP->fx_where;
10962 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10964 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
10967 switch (fixP->fx_r_type)
10969 case BFD_RELOC_MIPS_JMP:
10970 case BFD_RELOC_MIPS_SHIFT5:
10971 case BFD_RELOC_MIPS_SHIFT6:
10972 case BFD_RELOC_MIPS_GOT_DISP:
10973 case BFD_RELOC_MIPS_GOT_PAGE:
10974 case BFD_RELOC_MIPS_GOT_OFST:
10975 case BFD_RELOC_MIPS_SUB:
10976 case BFD_RELOC_MIPS_INSERT_A:
10977 case BFD_RELOC_MIPS_INSERT_B:
10978 case BFD_RELOC_MIPS_DELETE:
10979 case BFD_RELOC_MIPS_HIGHEST:
10980 case BFD_RELOC_MIPS_HIGHER:
10981 case BFD_RELOC_MIPS_SCN_DISP:
10982 case BFD_RELOC_MIPS_REL16:
10983 case BFD_RELOC_MIPS_RELGOT:
10984 case BFD_RELOC_MIPS_JALR:
10985 case BFD_RELOC_HI16:
10986 case BFD_RELOC_HI16_S:
10987 case BFD_RELOC_GPREL16:
10988 case BFD_RELOC_MIPS_LITERAL:
10989 case BFD_RELOC_MIPS_CALL16:
10990 case BFD_RELOC_MIPS_GOT16:
10991 case BFD_RELOC_GPREL32:
10992 case BFD_RELOC_MIPS_GOT_HI16:
10993 case BFD_RELOC_MIPS_GOT_LO16:
10994 case BFD_RELOC_MIPS_CALL_HI16:
10995 case BFD_RELOC_MIPS_CALL_LO16:
10996 case BFD_RELOC_MIPS16_GPREL:
10997 if (fixP->fx_pcrel)
10998 as_bad_where (fixP->fx_file, fixP->fx_line,
10999 _("Invalid PC relative reloc"));
11000 /* Nothing needed to do. The value comes from the reloc entry */
11003 case BFD_RELOC_MIPS16_JMP:
11004 /* We currently always generate a reloc against a symbol, which
11005 means that we don't want an addend even if the symbol is
11007 fixP->fx_addnumber = 0;
11010 case BFD_RELOC_PCREL_HI16_S:
11011 /* The addend for this is tricky if it is internal, so we just
11012 do everything here rather than in bfd_install_relocation. */
11013 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11018 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11020 /* For an external symbol adjust by the address to make it
11021 pcrel_offset. We use the address of the RELLO reloc
11022 which follows this one. */
11023 value += (fixP->fx_next->fx_frag->fr_address
11024 + fixP->fx_next->fx_where);
11026 value = ((value + 0x8000) >> 16) & 0xffff;
11027 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11028 if (target_big_endian)
11030 md_number_to_chars ((char *) buf, value, 2);
11033 case BFD_RELOC_PCREL_LO16:
11034 /* The addend for this is tricky if it is internal, so we just
11035 do everything here rather than in bfd_install_relocation. */
11036 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11041 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11042 value += fixP->fx_frag->fr_address + fixP->fx_where;
11043 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11044 if (target_big_endian)
11046 md_number_to_chars ((char *) buf, value, 2);
11050 /* This is handled like BFD_RELOC_32, but we output a sign
11051 extended value if we are only 32 bits. */
11053 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11055 if (8 <= sizeof (valueT))
11056 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11063 w1 = w2 = fixP->fx_where;
11064 if (target_big_endian)
11068 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
11069 if ((value & 0x80000000) != 0)
11073 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
11078 case BFD_RELOC_RVA:
11080 /* If we are deleting this reloc entry, we must fill in the
11081 value now. This can happen if we have a .word which is not
11082 resolved when it appears but is later defined. We also need
11083 to fill in the value if this is an embedded PIC switch table
11086 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11087 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11092 /* If we are deleting this reloc entry, we must fill in the
11094 assert (fixP->fx_size == 2);
11096 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11100 case BFD_RELOC_LO16:
11101 /* When handling an embedded PIC switch statement, we can wind
11102 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11105 if (value + 0x8000 > 0xffff)
11106 as_bad_where (fixP->fx_file, fixP->fx_line,
11107 _("relocation overflow"));
11108 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11109 if (target_big_endian)
11111 md_number_to_chars ((char *) buf, value, 2);
11115 case BFD_RELOC_16_PCREL_S2:
11116 if ((value & 0x3) != 0)
11117 as_bad_where (fixP->fx_file, fixP->fx_line,
11118 _("Branch to odd address (%lx)"), (long) value);
11120 /* Fall through. */
11122 case BFD_RELOC_16_PCREL:
11124 * We need to save the bits in the instruction since fixup_segment()
11125 * might be deleting the relocation entry (i.e., a branch within
11126 * the current segment).
11128 if (!fixP->fx_done && value != 0)
11130 /* If 'value' is zero, the remaining reloc code won't actually
11131 do the store, so it must be done here. This is probably
11132 a bug somewhere. */
11134 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
11135 || fixP->fx_addsy == NULL /* ??? */
11136 || ! S_IS_DEFINED (fixP->fx_addsy)))
11137 value -= fixP->fx_frag->fr_address + fixP->fx_where;
11139 value = (offsetT) value >> 2;
11141 /* update old instruction data */
11142 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
11143 if (target_big_endian)
11144 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11146 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11148 if (value + 0x8000 <= 0xffff)
11149 insn |= value & 0xffff;
11152 /* The branch offset is too large. If this is an
11153 unconditional branch, and we are not generating PIC code,
11154 we can convert it to an absolute jump instruction. */
11155 if (mips_pic == NO_PIC
11157 && fixP->fx_frag->fr_address >= text_section->vma
11158 && (fixP->fx_frag->fr_address
11159 < text_section->vma + text_section->_raw_size)
11160 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11161 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11162 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11164 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11165 insn = 0x0c000000; /* jal */
11167 insn = 0x08000000; /* j */
11168 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11170 fixP->fx_addsy = section_symbol (text_section);
11171 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
11175 /* FIXME. It would be possible in principle to handle
11176 conditional branches which overflow. They could be
11177 transformed into a branch around a jump. This would
11178 require setting up variant frags for each different
11179 branch type. The native MIPS assembler attempts to
11180 handle these cases, but it appears to do it
11182 as_bad_where (fixP->fx_file, fixP->fx_line,
11183 _("Branch out of range"));
11187 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11190 case BFD_RELOC_VTABLE_INHERIT:
11193 && !S_IS_DEFINED (fixP->fx_addsy)
11194 && !S_IS_WEAK (fixP->fx_addsy))
11195 S_SET_WEAK (fixP->fx_addsy);
11198 case BFD_RELOC_VTABLE_ENTRY:
11212 const struct mips_opcode *p;
11213 int treg, sreg, dreg, shamt;
11218 for (i = 0; i < NUMOPCODES; ++i)
11220 p = &mips_opcodes[i];
11221 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11223 printf ("%08lx %s\t", oc, p->name);
11224 treg = (oc >> 16) & 0x1f;
11225 sreg = (oc >> 21) & 0x1f;
11226 dreg = (oc >> 11) & 0x1f;
11227 shamt = (oc >> 6) & 0x1f;
11229 for (args = p->args;; ++args)
11240 printf ("%c", *args);
11244 assert (treg == sreg);
11245 printf ("$%d,$%d", treg, sreg);
11250 printf ("$%d", dreg);
11255 printf ("$%d", treg);
11259 printf ("0x%x", treg);
11264 printf ("$%d", sreg);
11268 printf ("0x%08lx", oc & 0x1ffffff);
11275 printf ("%d", imm);
11280 printf ("$%d", shamt);
11291 printf (_("%08lx UNDEFINED\n"), oc);
11302 name = input_line_pointer;
11303 c = get_symbol_end ();
11304 p = (symbolS *) symbol_find_or_make (name);
11305 *input_line_pointer = c;
11309 /* Align the current frag to a given power of two. The MIPS assembler
11310 also automatically adjusts any preceding label. */
11313 mips_align (to, fill, label)
11318 mips_emit_delays (false);
11319 frag_align (to, fill, 0);
11320 record_alignment (now_seg, to);
11323 assert (S_GET_SEGMENT (label) == now_seg);
11324 symbol_set_frag (label, frag_now);
11325 S_SET_VALUE (label, (valueT) frag_now_fix ());
11329 /* Align to a given power of two. .align 0 turns off the automatic
11330 alignment used by the data creating pseudo-ops. */
11334 int x ATTRIBUTE_UNUSED;
11337 register long temp_fill;
11338 long max_alignment = 15;
11342 o Note that the assembler pulls down any immediately preceeding label
11343 to the aligned address.
11344 o It's not documented but auto alignment is reinstated by
11345 a .align pseudo instruction.
11346 o Note also that after auto alignment is turned off the mips assembler
11347 issues an error on attempt to assemble an improperly aligned data item.
11352 temp = get_absolute_expression ();
11353 if (temp > max_alignment)
11354 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11357 as_warn (_("Alignment negative: 0 assumed."));
11360 if (*input_line_pointer == ',')
11362 ++input_line_pointer;
11363 temp_fill = get_absolute_expression ();
11370 mips_align (temp, (int) temp_fill,
11371 insn_labels != NULL ? insn_labels->label : NULL);
11378 demand_empty_rest_of_line ();
11382 mips_flush_pending_output ()
11384 mips_emit_delays (false);
11385 mips_clear_insn_labels ();
11394 /* When generating embedded PIC code, we only use the .text, .lit8,
11395 .sdata and .sbss sections. We change the .data and .rdata
11396 pseudo-ops to use .sdata. */
11397 if (mips_pic == EMBEDDED_PIC
11398 && (sec == 'd' || sec == 'r'))
11402 /* The ELF backend needs to know that we are changing sections, so
11403 that .previous works correctly. We could do something like check
11404 for an obj_section_change_hook macro, but that might be confusing
11405 as it would not be appropriate to use it in the section changing
11406 functions in read.c, since obj-elf.c intercepts those. FIXME:
11407 This should be cleaner, somehow. */
11408 obj_elf_section_change_hook ();
11411 mips_emit_delays (false);
11421 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11422 demand_empty_rest_of_line ();
11426 if (USE_GLOBAL_POINTER_OPT)
11428 seg = subseg_new (RDATA_SECTION_NAME,
11429 (subsegT) get_absolute_expression ());
11430 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11432 bfd_set_section_flags (stdoutput, seg,
11438 if (strcmp (TARGET_OS, "elf") != 0)
11439 record_alignment (seg, 4);
11441 demand_empty_rest_of_line ();
11445 as_bad (_("No read only data section in this object file format"));
11446 demand_empty_rest_of_line ();
11452 if (USE_GLOBAL_POINTER_OPT)
11454 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11455 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11457 bfd_set_section_flags (stdoutput, seg,
11458 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11460 if (strcmp (TARGET_OS, "elf") != 0)
11461 record_alignment (seg, 4);
11463 demand_empty_rest_of_line ();
11468 as_bad (_("Global pointers not supported; recompile -G 0"));
11469 demand_empty_rest_of_line ();
11478 mips_enable_auto_align ()
11489 label = insn_labels != NULL ? insn_labels->label : NULL;
11490 mips_emit_delays (false);
11491 if (log_size > 0 && auto_align)
11492 mips_align (log_size, 0, label);
11493 mips_clear_insn_labels ();
11494 cons (1 << log_size);
11498 s_float_cons (type)
11503 label = insn_labels != NULL ? insn_labels->label : NULL;
11505 mips_emit_delays (false);
11510 mips_align (3, 0, label);
11512 mips_align (2, 0, label);
11515 mips_clear_insn_labels ();
11520 /* Handle .globl. We need to override it because on Irix 5 you are
11523 where foo is an undefined symbol, to mean that foo should be
11524 considered to be the address of a function. */
11528 int x ATTRIBUTE_UNUSED;
11535 name = input_line_pointer;
11536 c = get_symbol_end ();
11537 symbolP = symbol_find_or_make (name);
11538 *input_line_pointer = c;
11539 SKIP_WHITESPACE ();
11541 /* On Irix 5, every global symbol that is not explicitly labelled as
11542 being a function is apparently labelled as being an object. */
11545 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11550 secname = input_line_pointer;
11551 c = get_symbol_end ();
11552 sec = bfd_get_section_by_name (stdoutput, secname);
11554 as_bad (_("%s: no such section"), secname);
11555 *input_line_pointer = c;
11557 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11558 flag = BSF_FUNCTION;
11561 symbol_get_bfdsym (symbolP)->flags |= flag;
11563 S_SET_EXTERNAL (symbolP);
11564 demand_empty_rest_of_line ();
11569 int x ATTRIBUTE_UNUSED;
11574 opt = input_line_pointer;
11575 c = get_symbol_end ();
11579 /* FIXME: What does this mean? */
11581 else if (strncmp (opt, "pic", 3) == 0)
11585 i = atoi (opt + 3);
11589 mips_pic = SVR4_PIC;
11591 as_bad (_(".option pic%d not supported"), i);
11593 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11595 if (g_switch_seen && g_switch_value != 0)
11596 as_warn (_("-G may not be used with SVR4 PIC code"));
11597 g_switch_value = 0;
11598 bfd_set_gp_size (stdoutput, 0);
11602 as_warn (_("Unrecognized option \"%s\""), opt);
11604 *input_line_pointer = c;
11605 demand_empty_rest_of_line ();
11608 /* This structure is used to hold a stack of .set values. */
11610 struct mips_option_stack
11612 struct mips_option_stack *next;
11613 struct mips_set_options options;
11616 static struct mips_option_stack *mips_opts_stack;
11618 /* Handle the .set pseudo-op. */
11622 int x ATTRIBUTE_UNUSED;
11624 char *name = input_line_pointer, ch;
11626 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11627 ++input_line_pointer;
11628 ch = *input_line_pointer;
11629 *input_line_pointer = '\0';
11631 if (strcmp (name, "reorder") == 0)
11633 if (mips_opts.noreorder && prev_nop_frag != NULL)
11635 /* If we still have pending nops, we can discard them. The
11636 usual nop handling will insert any that are still
11638 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11639 * (mips_opts.mips16 ? 2 : 4));
11640 prev_nop_frag = NULL;
11642 mips_opts.noreorder = 0;
11644 else if (strcmp (name, "noreorder") == 0)
11646 mips_emit_delays (true);
11647 mips_opts.noreorder = 1;
11648 mips_any_noreorder = 1;
11650 else if (strcmp (name, "at") == 0)
11652 mips_opts.noat = 0;
11654 else if (strcmp (name, "noat") == 0)
11656 mips_opts.noat = 1;
11658 else if (strcmp (name, "macro") == 0)
11660 mips_opts.warn_about_macros = 0;
11662 else if (strcmp (name, "nomacro") == 0)
11664 if (mips_opts.noreorder == 0)
11665 as_bad (_("`noreorder' must be set before `nomacro'"));
11666 mips_opts.warn_about_macros = 1;
11668 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11670 mips_opts.nomove = 0;
11672 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11674 mips_opts.nomove = 1;
11676 else if (strcmp (name, "bopt") == 0)
11678 mips_opts.nobopt = 0;
11680 else if (strcmp (name, "nobopt") == 0)
11682 mips_opts.nobopt = 1;
11684 else if (strcmp (name, "mips16") == 0
11685 || strcmp (name, "MIPS-16") == 0)
11686 mips_opts.mips16 = 1;
11687 else if (strcmp (name, "nomips16") == 0
11688 || strcmp (name, "noMIPS-16") == 0)
11689 mips_opts.mips16 = 0;
11690 else if (strcmp (name, "mips3d") == 0)
11691 mips_opts.ase_mips3d = 1;
11692 else if (strcmp (name, "nomips3d") == 0)
11693 mips_opts.ase_mips3d = 0;
11694 else if (strcmp (name, "mdmx") == 0)
11695 mips_opts.ase_mdmx = 1;
11696 else if (strcmp (name, "nomdmx") == 0)
11697 mips_opts.ase_mdmx = 0;
11698 else if (strncmp (name, "mips", 4) == 0)
11702 /* Permit the user to change the ISA on the fly. Needless to
11703 say, misuse can cause serious problems. */
11704 isa = atoi (name + 4);
11708 mips_opts.gp32 = file_mips_gp32;
11709 mips_opts.fp32 = file_mips_fp32;
11710 mips_opts.abi = file_mips_abi;
11715 mips_opts.gp32 = 1;
11716 mips_opts.fp32 = 1;
11722 /* Loosen ABI register width restriction. */
11723 if (mips_opts.abi == O32_ABI)
11724 mips_opts.abi = NO_ABI;
11725 mips_opts.gp32 = 0;
11726 mips_opts.fp32 = 0;
11729 as_bad (_("unknown ISA level %s"), name + 4);
11735 case 0: mips_opts.isa = file_mips_isa; break;
11736 case 1: mips_opts.isa = ISA_MIPS1; break;
11737 case 2: mips_opts.isa = ISA_MIPS2; break;
11738 case 3: mips_opts.isa = ISA_MIPS3; break;
11739 case 4: mips_opts.isa = ISA_MIPS4; break;
11740 case 5: mips_opts.isa = ISA_MIPS5; break;
11741 case 32: mips_opts.isa = ISA_MIPS32; break;
11742 case 64: mips_opts.isa = ISA_MIPS64; break;
11743 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11746 else if (strcmp (name, "autoextend") == 0)
11747 mips_opts.noautoextend = 0;
11748 else if (strcmp (name, "noautoextend") == 0)
11749 mips_opts.noautoextend = 1;
11750 else if (strcmp (name, "push") == 0)
11752 struct mips_option_stack *s;
11754 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11755 s->next = mips_opts_stack;
11756 s->options = mips_opts;
11757 mips_opts_stack = s;
11759 else if (strcmp (name, "pop") == 0)
11761 struct mips_option_stack *s;
11763 s = mips_opts_stack;
11765 as_bad (_(".set pop with no .set push"));
11768 /* If we're changing the reorder mode we need to handle
11769 delay slots correctly. */
11770 if (s->options.noreorder && ! mips_opts.noreorder)
11771 mips_emit_delays (true);
11772 else if (! s->options.noreorder && mips_opts.noreorder)
11774 if (prev_nop_frag != NULL)
11776 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11777 * (mips_opts.mips16 ? 2 : 4));
11778 prev_nop_frag = NULL;
11782 mips_opts = s->options;
11783 mips_opts_stack = s->next;
11789 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11791 *input_line_pointer = ch;
11792 demand_empty_rest_of_line ();
11795 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11796 .option pic2. It means to generate SVR4 PIC calls. */
11799 s_abicalls (ignore)
11800 int ignore ATTRIBUTE_UNUSED;
11802 mips_pic = SVR4_PIC;
11803 if (USE_GLOBAL_POINTER_OPT)
11805 if (g_switch_seen && g_switch_value != 0)
11806 as_warn (_("-G may not be used with SVR4 PIC code"));
11807 g_switch_value = 0;
11809 bfd_set_gp_size (stdoutput, 0);
11810 demand_empty_rest_of_line ();
11813 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11814 PIC code. It sets the $gp register for the function based on the
11815 function address, which is in the register named in the argument.
11816 This uses a relocation against _gp_disp, which is handled specially
11817 by the linker. The result is:
11818 lui $gp,%hi(_gp_disp)
11819 addiu $gp,$gp,%lo(_gp_disp)
11820 addu $gp,$gp,.cpload argument
11821 The .cpload argument is normally $25 == $t9. */
11825 int ignore ATTRIBUTE_UNUSED;
11830 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11831 .cpload is ignored. */
11832 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11838 /* .cpload should be in a .set noreorder section. */
11839 if (mips_opts.noreorder == 0)
11840 as_warn (_(".cpload not in noreorder section"));
11842 ex.X_op = O_symbol;
11843 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11844 ex.X_op_symbol = NULL;
11845 ex.X_add_number = 0;
11847 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11848 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11850 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
11851 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
11852 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
11854 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11855 mips_gp_register, mips_gp_register, tc_get_register (0));
11857 demand_empty_rest_of_line ();
11860 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11861 .cpsetup $reg1, offset|$reg2, label
11863 If offset is given, this results in:
11864 sd $gp, offset($sp)
11865 lui $gp, %hi(%neg(%gp_rel(label)))
11866 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11867 daddu $gp, $gp, $reg1
11869 If $reg2 is given, this results in:
11870 daddu $reg2, $gp, $0
11871 lui $gp, %hi(%neg(%gp_rel(label)))
11872 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11873 daddu $gp, $gp, $reg1
11874 $reg1 is normally $25 == $t9. */
11877 int ignore ATTRIBUTE_UNUSED;
11879 expressionS ex_off;
11880 expressionS ex_sym;
11885 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11886 We also need NewABI support. */
11887 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11893 reg1 = tc_get_register (0);
11894 SKIP_WHITESPACE ();
11895 if (*input_line_pointer != ',')
11897 as_bad (_("missing argument separator ',' for .cpsetup"));
11901 ++input_line_pointer;
11902 SKIP_WHITESPACE ();
11903 if (*input_line_pointer == '$')
11905 mips_cpreturn_register = tc_get_register (0);
11906 mips_cpreturn_offset = -1;
11910 mips_cpreturn_offset = get_absolute_expression ();
11911 mips_cpreturn_register = -1;
11913 SKIP_WHITESPACE ();
11914 if (*input_line_pointer != ',')
11916 as_bad (_("missing argument separator ',' for .cpsetup"));
11920 ++input_line_pointer;
11921 SKIP_WHITESPACE ();
11922 sym = input_line_pointer;
11923 while (ISALNUM (*input_line_pointer))
11924 ++input_line_pointer;
11925 *input_line_pointer = 0;
11927 ex_sym.X_op = O_symbol;
11928 ex_sym.X_add_symbol = symbol_find_or_make (sym);
11929 ex_sym.X_op_symbol = NULL;
11930 ex_sym.X_add_number = 0;
11932 if (mips_cpreturn_register == -1)
11934 ex_off.X_op = O_constant;
11935 ex_off.X_add_symbol = NULL;
11936 ex_off.X_op_symbol = NULL;
11937 ex_off.X_add_number = mips_cpreturn_offset;
11939 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11940 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11943 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11944 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11946 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11947 (int) BFD_RELOC_GPREL16);
11948 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11949 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S);
11950 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11951 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11952 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11953 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16);
11954 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11955 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
11956 mips_gp_register, mips_gp_register, reg1);
11958 demand_empty_rest_of_line ();
11963 int ignore ATTRIBUTE_UNUSED;
11965 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11966 .cplocal is ignored. */
11967 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11973 mips_gp_register = tc_get_register (0);
11974 demand_empty_rest_of_line ();
11977 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11978 offset from $sp. The offset is remembered, and after making a PIC
11979 call $gp is restored from that location. */
11982 s_cprestore (ignore)
11983 int ignore ATTRIBUTE_UNUSED;
11988 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11989 .cprestore is ignored. */
11990 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11996 mips_cprestore_offset = get_absolute_expression ();
11997 mips_cprestore_valid = 1;
11999 ex.X_op = O_constant;
12000 ex.X_add_symbol = NULL;
12001 ex.X_op_symbol = NULL;
12002 ex.X_add_number = mips_cprestore_offset;
12004 macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd",
12005 "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP);
12007 demand_empty_rest_of_line ();
12010 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12011 was given in the preceeding .gpsetup, it results in:
12012 ld $gp, offset($sp)
12014 If a register $reg2 was given there, it results in:
12015 daddiu $gp, $gp, $reg2
12018 s_cpreturn (ignore)
12019 int ignore ATTRIBUTE_UNUSED;
12024 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12025 We also need NewABI support. */
12026 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12032 if (mips_cpreturn_register == -1)
12034 ex.X_op = O_constant;
12035 ex.X_add_symbol = NULL;
12036 ex.X_op_symbol = NULL;
12037 ex.X_add_number = mips_cpreturn_offset;
12039 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
12040 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12043 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12044 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
12046 demand_empty_rest_of_line ();
12049 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12050 code. It sets the offset to use in gp_rel relocations. */
12054 int ignore ATTRIBUTE_UNUSED;
12056 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12057 We also need NewABI support. */
12058 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12064 mips_gprel_offset = get_absolute_expression ();
12066 demand_empty_rest_of_line ();
12069 /* Handle the .gpword pseudo-op. This is used when generating PIC
12070 code. It generates a 32 bit GP relative reloc. */
12074 int ignore ATTRIBUTE_UNUSED;
12080 /* When not generating PIC code, this is treated as .word. */
12081 if (mips_pic != SVR4_PIC)
12087 label = insn_labels != NULL ? insn_labels->label : NULL;
12088 mips_emit_delays (true);
12090 mips_align (2, 0, label);
12091 mips_clear_insn_labels ();
12095 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12097 as_bad (_("Unsupported use of .gpword"));
12098 ignore_rest_of_line ();
12102 md_number_to_chars (p, (valueT) 0, 4);
12103 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
12104 BFD_RELOC_GPREL32);
12106 demand_empty_rest_of_line ();
12109 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12110 tables in SVR4 PIC code. */
12114 int ignore ATTRIBUTE_UNUSED;
12119 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12121 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12127 /* Add $gp to the register named as an argument. */
12128 reg = tc_get_register (0);
12129 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12130 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
12131 "d,v,t", reg, reg, mips_gp_register);
12133 demand_empty_rest_of_line ();
12136 /* Handle the .insn pseudo-op. This marks instruction labels in
12137 mips16 mode. This permits the linker to handle them specially,
12138 such as generating jalx instructions when needed. We also make
12139 them odd for the duration of the assembly, in order to generate the
12140 right sort of code. We will make them even in the adjust_symtab
12141 routine, while leaving them marked. This is convenient for the
12142 debugger and the disassembler. The linker knows to make them odd
12147 int ignore ATTRIBUTE_UNUSED;
12149 mips16_mark_labels ();
12151 demand_empty_rest_of_line ();
12154 /* Handle a .stabn directive. We need these in order to mark a label
12155 as being a mips16 text label correctly. Sometimes the compiler
12156 will emit a label, followed by a .stabn, and then switch sections.
12157 If the label and .stabn are in mips16 mode, then the label is
12158 really a mips16 text label. */
12165 mips16_mark_labels ();
12170 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12174 s_mips_weakext (ignore)
12175 int ignore ATTRIBUTE_UNUSED;
12182 name = input_line_pointer;
12183 c = get_symbol_end ();
12184 symbolP = symbol_find_or_make (name);
12185 S_SET_WEAK (symbolP);
12186 *input_line_pointer = c;
12188 SKIP_WHITESPACE ();
12190 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12192 if (S_IS_DEFINED (symbolP))
12194 as_bad ("ignoring attempt to redefine symbol %s",
12195 S_GET_NAME (symbolP));
12196 ignore_rest_of_line ();
12200 if (*input_line_pointer == ',')
12202 ++input_line_pointer;
12203 SKIP_WHITESPACE ();
12207 if (exp.X_op != O_symbol)
12209 as_bad ("bad .weakext directive");
12210 ignore_rest_of_line ();
12213 symbol_set_value_expression (symbolP, &exp);
12216 demand_empty_rest_of_line ();
12219 /* Parse a register string into a number. Called from the ECOFF code
12220 to parse .frame. The argument is non-zero if this is the frame
12221 register, so that we can record it in mips_frame_reg. */
12224 tc_get_register (frame)
12229 SKIP_WHITESPACE ();
12230 if (*input_line_pointer++ != '$')
12232 as_warn (_("expected `$'"));
12235 else if (ISDIGIT (*input_line_pointer))
12237 reg = get_absolute_expression ();
12238 if (reg < 0 || reg >= 32)
12240 as_warn (_("Bad register number"));
12246 if (strncmp (input_line_pointer, "ra", 2) == 0)
12249 input_line_pointer += 2;
12251 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12254 input_line_pointer += 2;
12256 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12259 input_line_pointer += 2;
12261 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12264 input_line_pointer += 2;
12266 else if (strncmp (input_line_pointer, "at", 2) == 0)
12269 input_line_pointer += 2;
12271 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12274 input_line_pointer += 3;
12276 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12279 input_line_pointer += 3;
12281 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12284 input_line_pointer += 4;
12288 as_warn (_("Unrecognized register name"));
12290 while (ISALNUM(*input_line_pointer))
12291 input_line_pointer++;
12296 mips_frame_reg = reg != 0 ? reg : SP;
12297 mips_frame_reg_valid = 1;
12298 mips_cprestore_valid = 0;
12304 md_section_align (seg, addr)
12308 int align = bfd_get_section_alignment (stdoutput, seg);
12311 /* We don't need to align ELF sections to the full alignment.
12312 However, Irix 5 may prefer that we align them at least to a 16
12313 byte boundary. We don't bother to align the sections if we are
12314 targeted for an embedded system. */
12315 if (strcmp (TARGET_OS, "elf") == 0)
12321 return ((addr + (1 << align) - 1) & (-1 << align));
12324 /* Utility routine, called from above as well. If called while the
12325 input file is still being read, it's only an approximation. (For
12326 example, a symbol may later become defined which appeared to be
12327 undefined earlier.) */
12330 nopic_need_relax (sym, before_relaxing)
12332 int before_relaxing;
12337 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12339 const char *symname;
12342 /* Find out whether this symbol can be referenced off the $gp
12343 register. It can be if it is smaller than the -G size or if
12344 it is in the .sdata or .sbss section. Certain symbols can
12345 not be referenced off the $gp, although it appears as though
12347 symname = S_GET_NAME (sym);
12348 if (symname != (const char *) NULL
12349 && (strcmp (symname, "eprol") == 0
12350 || strcmp (symname, "etext") == 0
12351 || strcmp (symname, "_gp") == 0
12352 || strcmp (symname, "edata") == 0
12353 || strcmp (symname, "_fbss") == 0
12354 || strcmp (symname, "_fdata") == 0
12355 || strcmp (symname, "_ftext") == 0
12356 || strcmp (symname, "end") == 0
12357 || strcmp (symname, "_gp_disp") == 0))
12359 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12361 #ifndef NO_ECOFF_DEBUGGING
12362 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12363 && (symbol_get_obj (sym)->ecoff_extern_size
12364 <= g_switch_value))
12366 /* We must defer this decision until after the whole
12367 file has been read, since there might be a .extern
12368 after the first use of this symbol. */
12369 || (before_relaxing
12370 #ifndef NO_ECOFF_DEBUGGING
12371 && symbol_get_obj (sym)->ecoff_extern_size == 0
12373 && S_GET_VALUE (sym) == 0)
12374 || (S_GET_VALUE (sym) != 0
12375 && S_GET_VALUE (sym) <= g_switch_value)))
12379 const char *segname;
12381 segname = segment_name (S_GET_SEGMENT (sym));
12382 assert (strcmp (segname, ".lit8") != 0
12383 && strcmp (segname, ".lit4") != 0);
12384 change = (strcmp (segname, ".sdata") != 0
12385 && strcmp (segname, ".sbss") != 0
12386 && strncmp (segname, ".sdata.", 7) != 0
12387 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12392 /* We are not optimizing for the $gp register. */
12396 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12397 extended opcode. SEC is the section the frag is in. */
12400 mips16_extended_frag (fragp, sec, stretch)
12406 register const struct mips16_immed_operand *op;
12408 int mintiny, maxtiny;
12412 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12414 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12417 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12418 op = mips16_immed_operands;
12419 while (op->type != type)
12422 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12427 if (type == '<' || type == '>' || type == '[' || type == ']')
12430 maxtiny = 1 << op->nbits;
12435 maxtiny = (1 << op->nbits) - 1;
12440 mintiny = - (1 << (op->nbits - 1));
12441 maxtiny = (1 << (op->nbits - 1)) - 1;
12444 sym_frag = symbol_get_frag (fragp->fr_symbol);
12445 val = S_GET_VALUE (fragp->fr_symbol);
12446 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12452 /* We won't have the section when we are called from
12453 mips_relax_frag. However, we will always have been called
12454 from md_estimate_size_before_relax first. If this is a
12455 branch to a different section, we mark it as such. If SEC is
12456 NULL, and the frag is not marked, then it must be a branch to
12457 the same section. */
12460 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12465 /* Must have been called from md_estimate_size_before_relax. */
12468 fragp->fr_subtype =
12469 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12471 /* FIXME: We should support this, and let the linker
12472 catch branches and loads that are out of range. */
12473 as_bad_where (fragp->fr_file, fragp->fr_line,
12474 _("unsupported PC relative reference to different section"));
12478 if (fragp != sym_frag && sym_frag->fr_address == 0)
12479 /* Assume non-extended on the first relaxation pass.
12480 The address we have calculated will be bogus if this is
12481 a forward branch to another frag, as the forward frag
12482 will have fr_address == 0. */
12486 /* In this case, we know for sure that the symbol fragment is in
12487 the same section. If the relax_marker of the symbol fragment
12488 differs from the relax_marker of this fragment, we have not
12489 yet adjusted the symbol fragment fr_address. We want to add
12490 in STRETCH in order to get a better estimate of the address.
12491 This particularly matters because of the shift bits. */
12493 && sym_frag->relax_marker != fragp->relax_marker)
12497 /* Adjust stretch for any alignment frag. Note that if have
12498 been expanding the earlier code, the symbol may be
12499 defined in what appears to be an earlier frag. FIXME:
12500 This doesn't handle the fr_subtype field, which specifies
12501 a maximum number of bytes to skip when doing an
12503 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12505 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12508 stretch = - ((- stretch)
12509 & ~ ((1 << (int) f->fr_offset) - 1));
12511 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12520 addr = fragp->fr_address + fragp->fr_fix;
12522 /* The base address rules are complicated. The base address of
12523 a branch is the following instruction. The base address of a
12524 PC relative load or add is the instruction itself, but if it
12525 is in a delay slot (in which case it can not be extended) use
12526 the address of the instruction whose delay slot it is in. */
12527 if (type == 'p' || type == 'q')
12531 /* If we are currently assuming that this frag should be
12532 extended, then, the current address is two bytes
12534 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12537 /* Ignore the low bit in the target, since it will be set
12538 for a text label. */
12539 if ((val & 1) != 0)
12542 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12544 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12547 val -= addr & ~ ((1 << op->shift) - 1);
12549 /* Branch offsets have an implicit 0 in the lowest bit. */
12550 if (type == 'p' || type == 'q')
12553 /* If any of the shifted bits are set, we must use an extended
12554 opcode. If the address depends on the size of this
12555 instruction, this can lead to a loop, so we arrange to always
12556 use an extended opcode. We only check this when we are in
12557 the main relaxation loop, when SEC is NULL. */
12558 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12560 fragp->fr_subtype =
12561 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12565 /* If we are about to mark a frag as extended because the value
12566 is precisely maxtiny + 1, then there is a chance of an
12567 infinite loop as in the following code:
12572 In this case when the la is extended, foo is 0x3fc bytes
12573 away, so the la can be shrunk, but then foo is 0x400 away, so
12574 the la must be extended. To avoid this loop, we mark the
12575 frag as extended if it was small, and is about to become
12576 extended with a value of maxtiny + 1. */
12577 if (val == ((maxtiny + 1) << op->shift)
12578 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12581 fragp->fr_subtype =
12582 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12586 else if (symsec != absolute_section && sec != NULL)
12587 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12589 if ((val & ((1 << op->shift) - 1)) != 0
12590 || val < (mintiny << op->shift)
12591 || val > (maxtiny << op->shift))
12597 /* Estimate the size of a frag before relaxing. Unless this is the
12598 mips16, we are not really relaxing here, and the final size is
12599 encoded in the subtype information. For the mips16, we have to
12600 decide whether we are using an extended opcode or not. */
12603 md_estimate_size_before_relax (fragp, segtype)
12608 boolean linkonce = false;
12610 if (RELAX_MIPS16_P (fragp->fr_subtype))
12611 /* We don't want to modify the EXTENDED bit here; it might get us
12612 into infinite loops. We change it only in mips_relax_frag(). */
12613 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12615 if (mips_pic == NO_PIC)
12617 change = nopic_need_relax (fragp->fr_symbol, 0);
12619 else if (mips_pic == SVR4_PIC)
12624 sym = fragp->fr_symbol;
12626 /* Handle the case of a symbol equated to another symbol. */
12627 while (symbol_equated_reloc_p (sym))
12631 /* It's possible to get a loop here in a badly written
12633 n = symbol_get_value_expression (sym)->X_add_symbol;
12639 symsec = S_GET_SEGMENT (sym);
12641 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12642 if (symsec != segtype && ! S_IS_LOCAL (sym))
12644 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12648 /* The GNU toolchain uses an extension for ELF: a section
12649 beginning with the magic string .gnu.linkonce is a linkonce
12651 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12652 sizeof ".gnu.linkonce" - 1) == 0)
12656 /* This must duplicate the test in adjust_reloc_syms. */
12657 change = (symsec != &bfd_und_section
12658 && symsec != &bfd_abs_section
12659 && ! bfd_is_com_section (symsec)
12662 /* A global or weak symbol is treated as external. */
12663 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12664 || (! S_IS_WEAK (sym)
12665 && (! S_IS_EXTERN (sym) || mips_pic == EMBEDDED_PIC)))
12674 /* Record the offset to the first reloc in the fr_opcode field.
12675 This lets md_convert_frag and tc_gen_reloc know that the code
12676 must be expanded. */
12677 fragp->fr_opcode = (fragp->fr_literal
12679 - RELAX_OLD (fragp->fr_subtype)
12680 + RELAX_RELOC1 (fragp->fr_subtype));
12681 /* FIXME: This really needs as_warn_where. */
12682 if (RELAX_WARN (fragp->fr_subtype))
12683 as_warn (_("AT used after \".set noat\" or macro used after "
12684 "\".set nomacro\""));
12686 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12692 /* This is called to see whether a reloc against a defined symbol
12693 should be converted into a reloc against a section. Don't adjust
12694 MIPS16 jump relocations, so we don't have to worry about the format
12695 of the offset in the .o file. Don't adjust relocations against
12696 mips16 symbols, so that the linker can find them if it needs to set
12700 mips_fix_adjustable (fixp)
12704 /* Prevent all adjustments to global symbols. */
12705 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12706 && mips_pic != EMBEDDED_PIC
12707 && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)))
12710 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12712 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12713 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12715 if (fixp->fx_addsy == NULL)
12718 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12719 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12720 && fixp->fx_subsy == NULL)
12726 /* Translate internal representation of relocation info to BFD target
12730 tc_gen_reloc (section, fixp)
12731 asection *section ATTRIBUTE_UNUSED;
12734 static arelent *retval[4];
12736 bfd_reloc_code_real_type code;
12738 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12741 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12742 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12743 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12745 if (mips_pic == EMBEDDED_PIC
12746 && SWITCH_TABLE (fixp))
12748 /* For a switch table entry we use a special reloc. The addend
12749 is actually the difference between the reloc address and the
12751 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12752 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12753 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12754 fixp->fx_r_type = BFD_RELOC_GPREL32;
12756 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12758 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12759 reloc->addend = fixp->fx_addnumber;
12762 /* We use a special addend for an internal RELLO reloc. */
12763 if (symbol_section_p (fixp->fx_addsy))
12764 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12766 reloc->addend = fixp->fx_addnumber + reloc->address;
12769 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12771 assert (fixp->fx_next != NULL
12772 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12774 /* The reloc is relative to the RELLO; adjust the addend
12776 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12777 reloc->addend = fixp->fx_next->fx_addnumber;
12780 /* We use a special addend for an internal RELHI reloc. */
12781 if (symbol_section_p (fixp->fx_addsy))
12782 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12783 + fixp->fx_next->fx_where
12784 - S_GET_VALUE (fixp->fx_subsy));
12786 reloc->addend = (fixp->fx_addnumber
12787 + fixp->fx_next->fx_frag->fr_address
12788 + fixp->fx_next->fx_where);
12791 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12792 reloc->addend = fixp->fx_addnumber;
12795 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12796 /* A gruesome hack which is a result of the gruesome gas reloc
12798 reloc->addend = reloc->address;
12800 reloc->addend = -reloc->address;
12803 /* If this is a variant frag, we may need to adjust the existing
12804 reloc and generate a new one. */
12805 if (fixp->fx_frag->fr_opcode != NULL
12806 && (fixp->fx_r_type == BFD_RELOC_GPREL16
12807 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12808 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12809 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12810 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12811 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12812 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12817 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12819 /* If this is not the last reloc in this frag, then we have two
12820 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12821 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12822 the second one handle all of them. */
12823 if (fixp->fx_next != NULL
12824 && fixp->fx_frag == fixp->fx_next->fx_frag)
12826 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12827 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12828 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12829 && (fixp->fx_next->fx_r_type
12830 == BFD_RELOC_MIPS_GOT_LO16))
12831 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12832 && (fixp->fx_next->fx_r_type
12833 == BFD_RELOC_MIPS_CALL_LO16)));
12838 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12839 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12840 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12842 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12843 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12844 reloc2->address = (reloc->address
12845 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12846 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12847 reloc2->addend = fixp->fx_addnumber;
12848 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12849 assert (reloc2->howto != NULL);
12851 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12855 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12858 reloc3->address += 4;
12861 if (mips_pic == NO_PIC)
12863 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12864 fixp->fx_r_type = BFD_RELOC_HI16_S;
12866 else if (mips_pic == SVR4_PIC)
12868 switch (fixp->fx_r_type)
12872 case BFD_RELOC_MIPS_GOT16:
12874 case BFD_RELOC_MIPS_CALL16:
12875 case BFD_RELOC_MIPS_GOT_LO16:
12876 case BFD_RELOC_MIPS_CALL_LO16:
12877 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12885 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12886 entry to be used in the relocation's section offset. */
12887 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12889 reloc->address = reloc->addend;
12893 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12894 fixup_segment converted a non-PC relative reloc into a PC
12895 relative reloc. In such a case, we need to convert the reloc
12897 code = fixp->fx_r_type;
12898 if (fixp->fx_pcrel)
12903 code = BFD_RELOC_8_PCREL;
12906 code = BFD_RELOC_16_PCREL;
12909 code = BFD_RELOC_32_PCREL;
12912 code = BFD_RELOC_64_PCREL;
12914 case BFD_RELOC_8_PCREL:
12915 case BFD_RELOC_16_PCREL:
12916 case BFD_RELOC_32_PCREL:
12917 case BFD_RELOC_64_PCREL:
12918 case BFD_RELOC_16_PCREL_S2:
12919 case BFD_RELOC_PCREL_HI16_S:
12920 case BFD_RELOC_PCREL_LO16:
12923 as_bad_where (fixp->fx_file, fixp->fx_line,
12924 _("Cannot make %s relocation PC relative"),
12925 bfd_get_reloc_code_name (code));
12930 /* md_apply_fix3 has a double-subtraction hack to get
12931 bfd_install_relocation to behave nicely. GPREL relocations are
12932 handled correctly without this hack, so undo it here. We can't
12933 stop md_apply_fix3 from subtracting twice in the first place since
12934 the fake addend is required for variant frags above. */
12935 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12936 && code == BFD_RELOC_GPREL16
12937 && reloc->addend != 0
12938 && mips_need_elf_addend_fixup (fixp))
12939 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12942 /* To support a PC relative reloc when generating embedded PIC code
12943 for ECOFF, we use a Cygnus extension. We check for that here to
12944 make sure that we don't let such a reloc escape normally. */
12945 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12946 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12947 && code == BFD_RELOC_16_PCREL_S2
12948 && mips_pic != EMBEDDED_PIC)
12949 reloc->howto = NULL;
12951 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12953 if (reloc->howto == NULL)
12955 as_bad_where (fixp->fx_file, fixp->fx_line,
12956 _("Can not represent %s relocation in this object file format"),
12957 bfd_get_reloc_code_name (code));
12964 /* Relax a machine dependent frag. This returns the amount by which
12965 the current size of the frag should change. */
12968 mips_relax_frag (fragp, stretch)
12972 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12975 if (mips16_extended_frag (fragp, NULL, stretch))
12977 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12979 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12984 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12986 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12993 /* Convert a machine dependent frag. */
12996 md_convert_frag (abfd, asec, fragp)
12997 bfd *abfd ATTRIBUTE_UNUSED;
13004 if (RELAX_MIPS16_P (fragp->fr_subtype))
13007 register const struct mips16_immed_operand *op;
13008 boolean small, ext;
13011 unsigned long insn;
13012 boolean use_extend;
13013 unsigned short extend;
13015 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13016 op = mips16_immed_operands;
13017 while (op->type != type)
13020 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13031 resolve_symbol_value (fragp->fr_symbol);
13032 val = S_GET_VALUE (fragp->fr_symbol);
13037 addr = fragp->fr_address + fragp->fr_fix;
13039 /* The rules for the base address of a PC relative reloc are
13040 complicated; see mips16_extended_frag. */
13041 if (type == 'p' || type == 'q')
13046 /* Ignore the low bit in the target, since it will be
13047 set for a text label. */
13048 if ((val & 1) != 0)
13051 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13053 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13056 addr &= ~ (addressT) ((1 << op->shift) - 1);
13059 /* Make sure the section winds up with the alignment we have
13062 record_alignment (asec, op->shift);
13066 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13067 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13068 as_warn_where (fragp->fr_file, fragp->fr_line,
13069 _("extended instruction in delay slot"));
13071 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13073 if (target_big_endian)
13074 insn = bfd_getb16 (buf);
13076 insn = bfd_getl16 (buf);
13078 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13079 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13080 small, ext, &insn, &use_extend, &extend);
13084 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13085 fragp->fr_fix += 2;
13089 md_number_to_chars ((char *) buf, insn, 2);
13090 fragp->fr_fix += 2;
13095 if (fragp->fr_opcode == NULL)
13098 old = RELAX_OLD (fragp->fr_subtype);
13099 new = RELAX_NEW (fragp->fr_subtype);
13100 fixptr = fragp->fr_literal + fragp->fr_fix;
13103 memcpy (fixptr - old, fixptr, new);
13105 fragp->fr_fix += new - old;
13111 /* This function is called after the relocs have been generated.
13112 We've been storing mips16 text labels as odd. Here we convert them
13113 back to even for the convenience of the debugger. */
13116 mips_frob_file_after_relocs ()
13119 unsigned int count, i;
13121 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13124 syms = bfd_get_outsymbols (stdoutput);
13125 count = bfd_get_symcount (stdoutput);
13126 for (i = 0; i < count; i++, syms++)
13128 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13129 && ((*syms)->value & 1) != 0)
13131 (*syms)->value &= ~1;
13132 /* If the symbol has an odd size, it was probably computed
13133 incorrectly, so adjust that as well. */
13134 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13135 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13142 /* This function is called whenever a label is defined. It is used
13143 when handling branch delays; if a branch has a label, we assume we
13144 can not move it. */
13147 mips_define_label (sym)
13150 struct insn_label_list *l;
13152 if (free_insn_labels == NULL)
13153 l = (struct insn_label_list *) xmalloc (sizeof *l);
13156 l = free_insn_labels;
13157 free_insn_labels = l->next;
13161 l->next = insn_labels;
13165 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13167 /* Some special processing for a MIPS ELF file. */
13170 mips_elf_final_processing ()
13172 /* Write out the register information. */
13173 if (file_mips_abi != N64_ABI)
13177 s.ri_gprmask = mips_gprmask;
13178 s.ri_cprmask[0] = mips_cprmask[0];
13179 s.ri_cprmask[1] = mips_cprmask[1];
13180 s.ri_cprmask[2] = mips_cprmask[2];
13181 s.ri_cprmask[3] = mips_cprmask[3];
13182 /* The gp_value field is set by the MIPS ELF backend. */
13184 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13185 ((Elf32_External_RegInfo *)
13186 mips_regmask_frag));
13190 Elf64_Internal_RegInfo s;
13192 s.ri_gprmask = mips_gprmask;
13194 s.ri_cprmask[0] = mips_cprmask[0];
13195 s.ri_cprmask[1] = mips_cprmask[1];
13196 s.ri_cprmask[2] = mips_cprmask[2];
13197 s.ri_cprmask[3] = mips_cprmask[3];
13198 /* The gp_value field is set by the MIPS ELF backend. */
13200 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13201 ((Elf64_External_RegInfo *)
13202 mips_regmask_frag));
13205 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13206 sort of BFD interface for this. */
13207 if (mips_any_noreorder)
13208 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13209 if (mips_pic != NO_PIC)
13210 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13212 /* Set MIPS ELF flags for ASEs. */
13213 if (file_ase_mips16)
13214 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13215 #if 0 /* XXX FIXME */
13216 if (file_ase_mips3d)
13217 elf_elfheader (stdoutput)->e_flags |= ???;
13220 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13222 /* Set the MIPS ELF ABI flags. */
13223 if (file_mips_abi == NO_ABI)
13225 else if (file_mips_abi == O32_ABI)
13226 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13227 else if (file_mips_abi == O64_ABI)
13228 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13229 else if (file_mips_abi == EABI_ABI)
13231 /* Set the EABI kind based on the ISA. This isn't really
13232 the best, but then neither is basing the abi on the isa. */
13233 if (ISA_HAS_64BIT_REGS (file_mips_isa))
13234 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13236 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13238 else if (file_mips_abi == N32_ABI)
13239 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13241 /* Nothing to do for N64_ABI. */
13243 if (mips_32bitmode)
13244 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13247 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13249 typedef struct proc {
13251 unsigned long reg_mask;
13252 unsigned long reg_offset;
13253 unsigned long fpreg_mask;
13254 unsigned long fpreg_offset;
13255 unsigned long frame_offset;
13256 unsigned long frame_reg;
13257 unsigned long pc_reg;
13260 static procS cur_proc;
13261 static procS *cur_proc_ptr;
13262 static int numprocs;
13264 /* Fill in an rs_align_code fragment. */
13267 mips_handle_align (fragp)
13270 if (fragp->fr_type != rs_align_code)
13273 if (mips_opts.mips16)
13275 static const unsigned char be_nop[] = { 0x65, 0x00 };
13276 static const unsigned char le_nop[] = { 0x00, 0x65 };
13281 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13282 p = fragp->fr_literal + fragp->fr_fix;
13290 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13294 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13305 /* check for premature end, nesting errors, etc */
13307 as_warn (_("missing .end at end of assembly"));
13316 if (*input_line_pointer == '-')
13318 ++input_line_pointer;
13321 if (!ISDIGIT (*input_line_pointer))
13322 as_bad (_("expected simple number"));
13323 if (input_line_pointer[0] == '0')
13325 if (input_line_pointer[1] == 'x')
13327 input_line_pointer += 2;
13328 while (ISXDIGIT (*input_line_pointer))
13331 val |= hex_value (*input_line_pointer++);
13333 return negative ? -val : val;
13337 ++input_line_pointer;
13338 while (ISDIGIT (*input_line_pointer))
13341 val |= *input_line_pointer++ - '0';
13343 return negative ? -val : val;
13346 if (!ISDIGIT (*input_line_pointer))
13348 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13349 *input_line_pointer, *input_line_pointer);
13350 as_warn (_("invalid number"));
13353 while (ISDIGIT (*input_line_pointer))
13356 val += *input_line_pointer++ - '0';
13358 return negative ? -val : val;
13361 /* The .file directive; just like the usual .file directive, but there
13362 is an initial number which is the ECOFF file index. In the non-ECOFF
13363 case .file implies DWARF-2. */
13367 int x ATTRIBUTE_UNUSED;
13369 if (ECOFF_DEBUGGING)
13375 dwarf2_directive_file (0);
13378 /* The .loc directive, implying DWARF-2. */
13382 int x ATTRIBUTE_UNUSED;
13384 if (!ECOFF_DEBUGGING)
13385 dwarf2_directive_loc (0);
13388 /* The .end directive. */
13392 int x ATTRIBUTE_UNUSED;
13397 /* Following functions need their own .frame and .cprestore directives. */
13398 mips_frame_reg_valid = 0;
13399 mips_cprestore_valid = 0;
13401 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13404 demand_empty_rest_of_line ();
13409 #ifdef BFD_ASSEMBLER
13410 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13415 if (now_seg != data_section && now_seg != bss_section)
13422 as_warn (_(".end not in text section"));
13426 as_warn (_(".end directive without a preceding .ent directive."));
13427 demand_empty_rest_of_line ();
13433 assert (S_GET_NAME (p));
13434 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13435 as_warn (_(".end symbol does not match .ent symbol."));
13438 as_warn (_(".end directive missing or unknown symbol"));
13440 #ifdef MIPS_STABS_ELF
13442 segT saved_seg = now_seg;
13443 subsegT saved_subseg = now_subseg;
13448 dot = frag_now_fix ();
13450 #ifdef md_flush_pending_output
13451 md_flush_pending_output ();
13455 subseg_set (pdr_seg, 0);
13457 /* Write the symbol. */
13458 exp.X_op = O_symbol;
13459 exp.X_add_symbol = p;
13460 exp.X_add_number = 0;
13461 emit_expr (&exp, 4);
13463 fragp = frag_more (7 * 4);
13465 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13466 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13467 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13468 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13469 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13470 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13471 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13473 subseg_set (saved_seg, saved_subseg);
13475 #endif /* MIPS_STABS_ELF */
13477 cur_proc_ptr = NULL;
13480 /* The .aent and .ent directives. */
13489 symbolP = get_symbol ();
13490 if (*input_line_pointer == ',')
13491 ++input_line_pointer;
13492 SKIP_WHITESPACE ();
13493 if (ISDIGIT (*input_line_pointer)
13494 || *input_line_pointer == '-')
13497 #ifdef BFD_ASSEMBLER
13498 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13503 if (now_seg != data_section && now_seg != bss_section)
13510 as_warn (_(".ent or .aent not in text section."));
13512 if (!aent && cur_proc_ptr)
13513 as_warn (_("missing .end"));
13517 /* This function needs its own .frame and .cprestore directives. */
13518 mips_frame_reg_valid = 0;
13519 mips_cprestore_valid = 0;
13521 cur_proc_ptr = &cur_proc;
13522 memset (cur_proc_ptr, '\0', sizeof (procS));
13524 cur_proc_ptr->isym = symbolP;
13526 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13531 demand_empty_rest_of_line ();
13534 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13535 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13536 s_mips_frame is used so that we can set the PDR information correctly.
13537 We can't use the ecoff routines because they make reference to the ecoff
13538 symbol table (in the mdebug section). */
13541 s_mips_frame (ignore)
13542 int ignore ATTRIBUTE_UNUSED;
13544 #ifdef MIPS_STABS_ELF
13548 if (cur_proc_ptr == (procS *) NULL)
13550 as_warn (_(".frame outside of .ent"));
13551 demand_empty_rest_of_line ();
13555 cur_proc_ptr->frame_reg = tc_get_register (1);
13557 SKIP_WHITESPACE ();
13558 if (*input_line_pointer++ != ','
13559 || get_absolute_expression_and_terminator (&val) != ',')
13561 as_warn (_("Bad .frame directive"));
13562 --input_line_pointer;
13563 demand_empty_rest_of_line ();
13567 cur_proc_ptr->frame_offset = val;
13568 cur_proc_ptr->pc_reg = tc_get_register (0);
13570 demand_empty_rest_of_line ();
13573 #endif /* MIPS_STABS_ELF */
13576 /* The .fmask and .mask directives. If the mdebug section is present
13577 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13578 embedded targets, s_mips_mask is used so that we can set the PDR
13579 information correctly. We can't use the ecoff routines because they
13580 make reference to the ecoff symbol table (in the mdebug section). */
13583 s_mips_mask (reg_type)
13586 #ifdef MIPS_STABS_ELF
13589 if (cur_proc_ptr == (procS *) NULL)
13591 as_warn (_(".mask/.fmask outside of .ent"));
13592 demand_empty_rest_of_line ();
13596 if (get_absolute_expression_and_terminator (&mask) != ',')
13598 as_warn (_("Bad .mask/.fmask directive"));
13599 --input_line_pointer;
13600 demand_empty_rest_of_line ();
13604 off = get_absolute_expression ();
13606 if (reg_type == 'F')
13608 cur_proc_ptr->fpreg_mask = mask;
13609 cur_proc_ptr->fpreg_offset = off;
13613 cur_proc_ptr->reg_mask = mask;
13614 cur_proc_ptr->reg_offset = off;
13617 demand_empty_rest_of_line ();
13619 s_ignore (reg_type);
13620 #endif /* MIPS_STABS_ELF */
13623 /* The .loc directive. */
13634 assert (now_seg == text_section);
13636 lineno = get_number ();
13637 addroff = frag_now_fix ();
13639 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13640 S_SET_TYPE (symbolP, N_SLINE);
13641 S_SET_OTHER (symbolP, 0);
13642 S_SET_DESC (symbolP, lineno);
13643 symbolP->sy_segment = now_seg;
13647 /* CPU name/ISA/number mapping table.
13649 Entries are grouped by type. The first matching CPU or ISA entry
13650 gets chosen by CPU or ISA, so it should be the 'canonical' name
13651 for that type. Entries after that within the type are sorted
13654 Case is ignored in comparison, so put the canonical entry in the
13655 appropriate case but everything else in lower case to ease eye pain. */
13656 static const struct mips_cpu_info mips_cpu_info_table[] =
13659 { "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
13660 { "mips", 1, ISA_MIPS1, CPU_R3000, },
13663 { "MIPS2", 1, ISA_MIPS2, CPU_R6000, },
13666 { "MIPS3", 1, ISA_MIPS3, CPU_R4000, },
13669 { "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
13672 { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
13673 { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
13676 { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
13677 { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, },
13678 { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
13679 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13680 { "4km", 0, ISA_MIPS32, CPU_MIPS32, },
13681 { "4kp", 0, ISA_MIPS32, CPU_MIPS32, },
13683 /* For historical reasons. */
13684 { "MIPS64", 1, ISA_MIPS3, CPU_R4000, },
13687 { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, },
13688 { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
13689 { "5kc", 0, ISA_MIPS64, CPU_MIPS64, },
13690 { "20kc", 0, ISA_MIPS64, CPU_MIPS64, },
13693 { "R2000", 0, ISA_MIPS1, CPU_R2000, },
13694 { "2000", 0, ISA_MIPS1, CPU_R2000, },
13695 { "2k", 0, ISA_MIPS1, CPU_R2000, },
13696 { "r2k", 0, ISA_MIPS1, CPU_R2000, },
13699 { "R3000", 0, ISA_MIPS1, CPU_R3000, },
13700 { "3000", 0, ISA_MIPS1, CPU_R3000, },
13701 { "3k", 0, ISA_MIPS1, CPU_R3000, },
13702 { "r3k", 0, ISA_MIPS1, CPU_R3000, },
13705 { "R3900", 0, ISA_MIPS1, CPU_R3900, },
13706 { "3900", 0, ISA_MIPS1, CPU_R3900, },
13707 { "mipstx39", 0, ISA_MIPS1, CPU_R3900, },
13710 { "R4000", 0, ISA_MIPS3, CPU_R4000, },
13711 { "4000", 0, ISA_MIPS3, CPU_R4000, },
13712 { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */
13713 { "r4k", 0, ISA_MIPS3, CPU_R4000, },
13716 { "R4010", 0, ISA_MIPS2, CPU_R4010, },
13717 { "4010", 0, ISA_MIPS2, CPU_R4010, },
13720 { "R4400", 0, ISA_MIPS3, CPU_R4400, },
13721 { "4400", 0, ISA_MIPS3, CPU_R4400, },
13724 { "R4600", 0, ISA_MIPS3, CPU_R4600, },
13725 { "4600", 0, ISA_MIPS3, CPU_R4600, },
13726 { "mips64orion", 0, ISA_MIPS3, CPU_R4600, },
13727 { "orion", 0, ISA_MIPS3, CPU_R4600, },
13730 { "R4650", 0, ISA_MIPS3, CPU_R4650, },
13731 { "4650", 0, ISA_MIPS3, CPU_R4650, },
13734 { "R6000", 0, ISA_MIPS2, CPU_R6000, },
13735 { "6000", 0, ISA_MIPS2, CPU_R6000, },
13736 { "6k", 0, ISA_MIPS2, CPU_R6000, },
13737 { "r6k", 0, ISA_MIPS2, CPU_R6000, },
13740 { "R8000", 0, ISA_MIPS4, CPU_R8000, },
13741 { "8000", 0, ISA_MIPS4, CPU_R8000, },
13742 { "8k", 0, ISA_MIPS4, CPU_R8000, },
13743 { "r8k", 0, ISA_MIPS4, CPU_R8000, },
13746 { "R10000", 0, ISA_MIPS4, CPU_R10000, },
13747 { "10000", 0, ISA_MIPS4, CPU_R10000, },
13748 { "10k", 0, ISA_MIPS4, CPU_R10000, },
13749 { "r10k", 0, ISA_MIPS4, CPU_R10000, },
13752 { "R12000", 0, ISA_MIPS4, CPU_R12000, },
13753 { "12000", 0, ISA_MIPS4, CPU_R12000, },
13754 { "12k", 0, ISA_MIPS4, CPU_R12000, },
13755 { "r12k", 0, ISA_MIPS4, CPU_R12000, },
13758 { "VR4100", 0, ISA_MIPS3, CPU_VR4100, },
13759 { "4100", 0, ISA_MIPS3, CPU_VR4100, },
13760 { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, },
13761 { "r4100", 0, ISA_MIPS3, CPU_VR4100, },
13764 { "VR4111", 0, ISA_MIPS3, CPU_R4111, },
13765 { "4111", 0, ISA_MIPS3, CPU_R4111, },
13766 { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, },
13767 { "r4111", 0, ISA_MIPS3, CPU_R4111, },
13770 { "VR4300", 0, ISA_MIPS3, CPU_R4300, },
13771 { "4300", 0, ISA_MIPS3, CPU_R4300, },
13772 { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, },
13773 { "r4300", 0, ISA_MIPS3, CPU_R4300, },
13776 { "VR5000", 0, ISA_MIPS4, CPU_R5000, },
13777 { "5000", 0, ISA_MIPS4, CPU_R5000, },
13778 { "5k", 0, ISA_MIPS4, CPU_R5000, },
13779 { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, },
13780 { "r5000", 0, ISA_MIPS4, CPU_R5000, },
13781 { "r5200", 0, ISA_MIPS4, CPU_R5000, },
13782 { "rm5200", 0, ISA_MIPS4, CPU_R5000, },
13783 { "r5230", 0, ISA_MIPS4, CPU_R5000, },
13784 { "rm5230", 0, ISA_MIPS4, CPU_R5000, },
13785 { "r5231", 0, ISA_MIPS4, CPU_R5000, },
13786 { "rm5231", 0, ISA_MIPS4, CPU_R5000, },
13787 { "r5261", 0, ISA_MIPS4, CPU_R5000, },
13788 { "rm5261", 0, ISA_MIPS4, CPU_R5000, },
13789 { "r5721", 0, ISA_MIPS4, CPU_R5000, },
13790 { "rm5721", 0, ISA_MIPS4, CPU_R5000, },
13791 { "r5k", 0, ISA_MIPS4, CPU_R5000, },
13792 { "r7000", 0, ISA_MIPS4, CPU_R5000, },
13794 /* Broadcom SB-1 CPU */
13795 { "SB-1", 0, ISA_MIPS64, CPU_SB1, },
13796 { "sb-1250", 0, ISA_MIPS64, CPU_SB1, },
13797 { "sb1", 0, ISA_MIPS64, CPU_SB1, },
13798 { "sb1250", 0, ISA_MIPS64, CPU_SB1, },
13801 { NULL, 0, 0, 0, },
13804 static const struct mips_cpu_info *
13805 mips_cpu_info_from_name (name)
13810 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13811 if (strcasecmp (name, mips_cpu_info_table[i].name) == 0)
13812 return (&mips_cpu_info_table[i]);
13817 static const struct mips_cpu_info *
13818 mips_cpu_info_from_isa (isa)
13823 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13824 if (mips_cpu_info_table[i].is_isa
13825 && isa == mips_cpu_info_table[i].isa)
13826 return (&mips_cpu_info_table[i]);
13831 static const struct mips_cpu_info *
13832 mips_cpu_info_from_cpu (cpu)
13837 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13838 if (!mips_cpu_info_table[i].is_isa
13839 && cpu == mips_cpu_info_table[i].cpu)
13840 return (&mips_cpu_info_table[i]);