1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* True if the given ABI requires 32-bit registers. */
241 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
243 /* Likewise 64-bit registers. */
244 #define ABI_NEEDS_64BIT_REGS(ABI) \
246 || (ABI) == N64_ABI \
249 /* Return true if ISA supports 64 bit gp register instructions. */
250 #define ISA_HAS_64BIT_REGS(ISA) ( \
252 || (ISA) == ISA_MIPS4 \
253 || (ISA) == ISA_MIPS5 \
254 || (ISA) == ISA_MIPS64 \
255 || (ISA) == ISA_MIPS64R2 \
258 /* Return true if ISA supports 64-bit right rotate (dror et al.)
260 #define ISA_HAS_DROR(ISA) ( \
261 (ISA) == ISA_MIPS64R2 \
264 /* Return true if ISA supports 32-bit right rotate (ror et al.)
266 #define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
271 #define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
274 #define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
280 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
282 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
284 /* We can only have 64bit addresses if the object file format
286 #define HAVE_32BIT_ADDRESSES \
288 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS) \
290 && mips_pic != EMBEDDED_PIC))
292 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
294 /* Addresses are loaded in different ways, depending on the address size
295 in use. The n32 ABI Documentation also mandates the use of additions
296 with overflow checking, but existing implementations don't follow it. */
297 #define ADDRESS_ADD_INSN \
298 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
300 #define ADDRESS_ADDI_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
303 #define ADDRESS_LOAD_INSN \
304 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
306 #define ADDRESS_STORE_INSN \
307 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
309 /* Return true if the given CPU supports the MIPS16 ASE. */
310 #define CPU_HAS_MIPS16(cpu) \
311 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
312 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
314 /* Return true if the given CPU supports the MIPS3D ASE. */
315 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
318 /* Return true if the given CPU supports the MDMX ASE. */
319 #define CPU_HAS_MDMX(cpu) (FALSE \
322 /* True if CPU has a dror instruction. */
323 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
325 /* True if CPU has a ror instruction. */
326 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
328 /* Whether the processor uses hardware interlocks to protect
329 reads from the HI and LO registers, and thus does not
330 require nops to be inserted. */
332 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
333 || mips_opts.arch == CPU_VR5500 \
334 || mips_opts.arch == CPU_RM7000 \
335 || mips_opts.arch == CPU_SB1 \
338 /* Whether the processor uses hardware interlocks to protect reads
339 from the GPRs after they are loaded from memory, and thus does not
340 require nops to be inserted. This applies to instructions marked
341 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
343 #define gpr_interlocks \
344 (mips_opts.isa != ISA_MIPS1 \
345 || mips_opts.arch == CPU_VR5400 \
346 || mips_opts.arch == CPU_VR5500 \
347 || mips_opts.arch == CPU_R3900)
349 /* Whether the processor uses hardware interlocks to avoid delays
350 required by coprocessor instructions, and thus does not require
351 nops to be inserted. This applies to instructions marked
352 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
353 between instructions marked INSN_WRITE_COND_CODE and ones marked
354 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
355 levels I, II, and III. */
356 /* Itbl support may require additional care here. */
357 #define cop_interlocks \
358 ((mips_opts.isa != ISA_MIPS1 \
359 && mips_opts.isa != ISA_MIPS2 \
360 && mips_opts.isa != ISA_MIPS3) \
361 || mips_opts.arch == CPU_R4300 \
362 || mips_opts.arch == CPU_VR5400 \
363 || mips_opts.arch == CPU_VR5500 \
364 || mips_opts.arch == CPU_SB1 \
367 /* Whether the processor uses hardware interlocks to protect reads
368 from coprocessor registers after they are loaded from memory, and
369 thus does not require nops to be inserted. This applies to
370 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
371 requires at MIPS ISA level I. */
372 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
374 /* Is this a mfhi or mflo instruction? */
375 #define MF_HILO_INSN(PINFO) \
376 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
378 /* MIPS PIC level. */
380 enum mips_pic_level mips_pic;
382 /* 1 if we should generate 32 bit offsets from the $gp register in
383 SVR4_PIC mode. Currently has no meaning in other modes. */
384 static int mips_big_got = 0;
386 /* 1 if trap instructions should used for overflow rather than break
388 static int mips_trap = 0;
390 /* 1 if double width floating point constants should not be constructed
391 by assembling two single width halves into two single width floating
392 point registers which just happen to alias the double width destination
393 register. On some architectures this aliasing can be disabled by a bit
394 in the status register, and the setting of this bit cannot be determined
395 automatically at assemble time. */
396 static int mips_disable_float_construction;
398 /* Non-zero if any .set noreorder directives were used. */
400 static int mips_any_noreorder;
402 /* Non-zero if nops should be inserted when the register referenced in
403 an mfhi/mflo instruction is read in the next two instructions. */
404 static int mips_7000_hilo_fix;
406 /* The size of the small data section. */
407 static unsigned int g_switch_value = 8;
408 /* Whether the -G option was used. */
409 static int g_switch_seen = 0;
414 /* If we can determine in advance that GP optimization won't be
415 possible, we can skip the relaxation stuff that tries to produce
416 GP-relative references. This makes delay slot optimization work
419 This function can only provide a guess, but it seems to work for
420 gcc output. It needs to guess right for gcc, otherwise gcc
421 will put what it thinks is a GP-relative instruction in a branch
424 I don't know if a fix is needed for the SVR4_PIC mode. I've only
425 fixed it for the non-PIC mode. KR 95/04/07 */
426 static int nopic_need_relax (symbolS *, int);
428 /* handle of the OPCODE hash table */
429 static struct hash_control *op_hash = NULL;
431 /* The opcode hash table we use for the mips16. */
432 static struct hash_control *mips16_op_hash = NULL;
434 /* This array holds the chars that always start a comment. If the
435 pre-processor is disabled, these aren't very useful */
436 const char comment_chars[] = "#";
438 /* This array holds the chars that only start a comment at the beginning of
439 a line. If the line seems to have the form '# 123 filename'
440 .line and .file directives will appear in the pre-processed output */
441 /* Note that input_file.c hand checks for '#' at the beginning of the
442 first line of the input file. This is because the compiler outputs
443 #NO_APP at the beginning of its output. */
444 /* Also note that C style comments are always supported. */
445 const char line_comment_chars[] = "#";
447 /* This array holds machine specific line separator characters. */
448 const char line_separator_chars[] = ";";
450 /* Chars that can be used to separate mant from exp in floating point nums */
451 const char EXP_CHARS[] = "eE";
453 /* Chars that mean this number is a floating point constant */
456 const char FLT_CHARS[] = "rRsSfFdDxXpP";
458 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
459 changed in read.c . Ideally it shouldn't have to know about it at all,
460 but nothing is ideal around here.
463 static char *insn_error;
465 static int auto_align = 1;
467 /* When outputting SVR4 PIC code, the assembler needs to know the
468 offset in the stack frame from which to restore the $gp register.
469 This is set by the .cprestore pseudo-op, and saved in this
471 static offsetT mips_cprestore_offset = -1;
473 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
474 more optimizations, it can use a register value instead of a memory-saved
475 offset and even an other register than $gp as global pointer. */
476 static offsetT mips_cpreturn_offset = -1;
477 static int mips_cpreturn_register = -1;
478 static int mips_gp_register = GP;
479 static int mips_gprel_offset = 0;
481 /* Whether mips_cprestore_offset has been set in the current function
482 (or whether it has already been warned about, if not). */
483 static int mips_cprestore_valid = 0;
485 /* This is the register which holds the stack frame, as set by the
486 .frame pseudo-op. This is needed to implement .cprestore. */
487 static int mips_frame_reg = SP;
489 /* Whether mips_frame_reg has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_frame_reg_valid = 0;
493 /* To output NOP instructions correctly, we need to keep information
494 about the previous two instructions. */
496 /* Whether we are optimizing. The default value of 2 means to remove
497 unneeded NOPs and swap branch instructions when possible. A value
498 of 1 means to not swap branches. A value of 0 means to always
500 static int mips_optimize = 2;
502 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
503 equivalent to seeing no -g option at all. */
504 static int mips_debug = 0;
506 /* The previous instruction. */
507 static struct mips_cl_insn prev_insn;
509 /* The instruction before prev_insn. */
510 static struct mips_cl_insn prev_prev_insn;
512 /* If we don't want information for prev_insn or prev_prev_insn, we
513 point the insn_mo field at this dummy integer. */
514 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
516 /* Non-zero if prev_insn is valid. */
517 static int prev_insn_valid;
519 /* The frag for the previous instruction. */
520 static struct frag *prev_insn_frag;
522 /* The offset into prev_insn_frag for the previous instruction. */
523 static long prev_insn_where;
525 /* The reloc type for the previous instruction, if any. */
526 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
528 /* The reloc for the previous instruction, if any. */
529 static fixS *prev_insn_fixp[3];
531 /* Non-zero if the previous instruction was in a delay slot. */
532 static int prev_insn_is_delay_slot;
534 /* Non-zero if the previous instruction was in a .set noreorder. */
535 static int prev_insn_unreordered;
537 /* Non-zero if the previous instruction uses an extend opcode (if
539 static int prev_insn_extended;
541 /* Non-zero if the previous previous instruction was in a .set
543 static int prev_prev_insn_unreordered;
545 /* If this is set, it points to a frag holding nop instructions which
546 were inserted before the start of a noreorder section. If those
547 nops turn out to be unnecessary, the size of the frag can be
549 static fragS *prev_nop_frag;
551 /* The number of nop instructions we created in prev_nop_frag. */
552 static int prev_nop_frag_holds;
554 /* The number of nop instructions that we know we need in
556 static int prev_nop_frag_required;
558 /* The number of instructions we've seen since prev_nop_frag. */
559 static int prev_nop_frag_since;
561 /* For ECOFF and ELF, relocations against symbols are done in two
562 parts, with a HI relocation and a LO relocation. Each relocation
563 has only 16 bits of space to store an addend. This means that in
564 order for the linker to handle carries correctly, it must be able
565 to locate both the HI and the LO relocation. This means that the
566 relocations must appear in order in the relocation table.
568 In order to implement this, we keep track of each unmatched HI
569 relocation. We then sort them so that they immediately precede the
570 corresponding LO relocation. */
575 struct mips_hi_fixup *next;
578 /* The section this fixup is in. */
582 /* The list of unmatched HI relocs. */
584 static struct mips_hi_fixup *mips_hi_fixup_list;
586 /* The frag containing the last explicit relocation operator.
587 Null if explicit relocations have not been used. */
589 static fragS *prev_reloc_op_frag;
591 /* Map normal MIPS register numbers to mips16 register numbers. */
593 #define X ILLEGAL_REG
594 static const int mips32_to_16_reg_map[] =
596 X, X, 2, 3, 4, 5, 6, 7,
597 X, X, X, X, X, X, X, X,
598 0, 1, X, X, X, X, X, X,
599 X, X, X, X, X, X, X, X
603 /* Map mips16 register numbers to normal MIPS register numbers. */
605 static const unsigned int mips16_to_32_reg_map[] =
607 16, 17, 2, 3, 4, 5, 6, 7
610 static int mips_fix_4122_bugs;
612 /* We don't relax branches by default, since this causes us to expand
613 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
614 fail to compute the offset before expanding the macro to the most
615 efficient expansion. */
617 static int mips_relax_branch;
619 /* The expansion of many macros depends on the type of symbol that
620 they refer to. For example, when generating position-dependent code,
621 a macro that refers to a symbol may have two different expansions,
622 one which uses GP-relative addresses and one which uses absolute
623 addresses. When generating SVR4-style PIC, a macro may have
624 different expansions for local and global symbols.
626 We handle these situations by generating both sequences and putting
627 them in variant frags. In position-dependent code, the first sequence
628 will be the GP-relative one and the second sequence will be the
629 absolute one. In SVR4 PIC, the first sequence will be for global
630 symbols and the second will be for local symbols.
632 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
633 SECOND are the lengths of the two sequences in bytes. These fields
634 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
635 the subtype has the following flags:
638 Set if it has been decided that we should use the second
639 sequence instead of the first.
642 Set in the first variant frag if the macro's second implementation
643 is longer than its first. This refers to the macro as a whole,
644 not an individual relaxation.
647 Set in the first variant frag if the macro appeared in a .set nomacro
648 block and if one alternative requires a warning but the other does not.
651 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
654 The frag's "opcode" points to the first fixup for relaxable code.
656 Relaxable macros are generated using a sequence such as:
658 relax_start (SYMBOL);
659 ... generate first expansion ...
661 ... generate second expansion ...
664 The code and fixups for the unwanted alternative are discarded
665 by md_convert_frag. */
666 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
668 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
669 #define RELAX_SECOND(X) ((X) & 0xff)
670 #define RELAX_USE_SECOND 0x10000
671 #define RELAX_SECOND_LONGER 0x20000
672 #define RELAX_NOMACRO 0x40000
673 #define RELAX_DELAY_SLOT 0x80000
675 /* Branch without likely bit. If label is out of range, we turn:
677 beq reg1, reg2, label
687 with the following opcode replacements:
694 bltzal <-> bgezal (with jal label instead of j label)
696 Even though keeping the delay slot instruction in the delay slot of
697 the branch would be more efficient, it would be very tricky to do
698 correctly, because we'd have to introduce a variable frag *after*
699 the delay slot instruction, and expand that instead. Let's do it
700 the easy way for now, even if the branch-not-taken case now costs
701 one additional instruction. Out-of-range branches are not supposed
702 to be common, anyway.
704 Branch likely. If label is out of range, we turn:
706 beql reg1, reg2, label
707 delay slot (annulled if branch not taken)
716 delay slot (executed only if branch taken)
719 It would be possible to generate a shorter sequence by losing the
720 likely bit, generating something like:
725 delay slot (executed only if branch taken)
737 bltzall -> bgezal (with jal label instead of j label)
738 bgezall -> bltzal (ditto)
741 but it's not clear that it would actually improve performance. */
742 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
745 | ((toofar) ? 1 : 0) \
747 | ((likely) ? 4 : 0) \
748 | ((uncond) ? 8 : 0)))
749 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
750 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
751 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
752 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
753 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
755 /* For mips16 code, we use an entirely different form of relaxation.
756 mips16 supports two versions of most instructions which take
757 immediate values: a small one which takes some small value, and a
758 larger one which takes a 16 bit value. Since branches also follow
759 this pattern, relaxing these values is required.
761 We can assemble both mips16 and normal MIPS code in a single
762 object. Therefore, we need to support this type of relaxation at
763 the same time that we support the relaxation described above. We
764 use the high bit of the subtype field to distinguish these cases.
766 The information we store for this type of relaxation is the
767 argument code found in the opcode file for this relocation, whether
768 the user explicitly requested a small or extended form, and whether
769 the relocation is in a jump or jal delay slot. That tells us the
770 size of the value, and how it should be stored. We also store
771 whether the fragment is considered to be extended or not. We also
772 store whether this is known to be a branch to a different section,
773 whether we have tried to relax this frag yet, and whether we have
774 ever extended a PC relative fragment because of a shift count. */
775 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
778 | ((small) ? 0x100 : 0) \
779 | ((ext) ? 0x200 : 0) \
780 | ((dslot) ? 0x400 : 0) \
781 | ((jal_dslot) ? 0x800 : 0))
782 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
783 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
784 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
785 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
786 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
787 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
788 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
789 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
790 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
791 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
792 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
793 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
795 /* Is the given value a sign-extended 32-bit value? */
796 #define IS_SEXT_32BIT_NUM(x) \
797 (((x) &~ (offsetT) 0x7fffffff) == 0 \
798 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
800 /* Is the given value a sign-extended 16-bit value? */
801 #define IS_SEXT_16BIT_NUM(x) \
802 (((x) &~ (offsetT) 0x7fff) == 0 \
803 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
806 /* Global variables used when generating relaxable macros. See the
807 comment above RELAX_ENCODE for more details about how relaxation
810 /* 0 if we're not emitting a relaxable macro.
811 1 if we're emitting the first of the two relaxation alternatives.
812 2 if we're emitting the second alternative. */
815 /* The first relaxable fixup in the current frag. (In other words,
816 the first fixup that refers to relaxable code.) */
819 /* sizes[0] says how many bytes of the first alternative are stored in
820 the current frag. Likewise sizes[1] for the second alternative. */
821 unsigned int sizes[2];
823 /* The symbol on which the choice of sequence depends. */
827 /* Global variables used to decide whether a macro needs a warning. */
829 /* True if the macro is in a branch delay slot. */
830 bfd_boolean delay_slot_p;
832 /* For relaxable macros, sizes[0] is the length of the first alternative
833 in bytes and sizes[1] is the length of the second alternative.
834 For non-relaxable macros, both elements give the length of the
836 unsigned int sizes[2];
838 /* The first variant frag for this macro. */
840 } mips_macro_warning;
842 /* Prototypes for static functions. */
844 #define internalError() \
845 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
847 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
849 static void append_insn
850 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
851 static void mips_no_prev_insn (int);
852 static void mips16_macro_build
853 (int *, expressionS *, const char *, const char *, va_list);
854 static void load_register (int *, int, expressionS *, int);
855 static void macro_start (void);
856 static void macro_end (void);
857 static void macro (struct mips_cl_insn * ip);
858 static void mips16_macro (struct mips_cl_insn * ip);
859 #ifdef LOSING_COMPILER
860 static void macro2 (struct mips_cl_insn * ip);
862 static void mips_ip (char *str, struct mips_cl_insn * ip);
863 static void mips16_ip (char *str, struct mips_cl_insn * ip);
864 static void mips16_immed
865 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
866 unsigned long *, bfd_boolean *, unsigned short *);
867 static size_t my_getSmallExpression
868 (expressionS *, bfd_reloc_code_real_type *, char *);
869 static void my_getExpression (expressionS *, char *);
870 static void s_align (int);
871 static void s_change_sec (int);
872 static void s_change_section (int);
873 static void s_cons (int);
874 static void s_float_cons (int);
875 static void s_mips_globl (int);
876 static void s_option (int);
877 static void s_mipsset (int);
878 static void s_abicalls (int);
879 static void s_cpload (int);
880 static void s_cpsetup (int);
881 static void s_cplocal (int);
882 static void s_cprestore (int);
883 static void s_cpreturn (int);
884 static void s_gpvalue (int);
885 static void s_gpword (int);
886 static void s_gpdword (int);
887 static void s_cpadd (int);
888 static void s_insn (int);
889 static void md_obj_begin (void);
890 static void md_obj_end (void);
891 static void s_mips_ent (int);
892 static void s_mips_end (int);
893 static void s_mips_frame (int);
894 static void s_mips_mask (int reg_type);
895 static void s_mips_stab (int);
896 static void s_mips_weakext (int);
897 static void s_mips_file (int);
898 static void s_mips_loc (int);
899 static bfd_boolean pic_need_relax (symbolS *, asection *);
900 static int relaxed_branch_length (fragS *, asection *, int);
901 static int validate_mips_insn (const struct mips_opcode *);
903 /* Table and functions used to map between CPU/ISA names, and
904 ISA levels, and CPU numbers. */
908 const char *name; /* CPU or ISA name. */
909 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
910 int isa; /* ISA level. */
911 int cpu; /* CPU number (default CPU if ISA). */
914 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
915 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
916 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
920 The following pseudo-ops from the Kane and Heinrich MIPS book
921 should be defined here, but are currently unsupported: .alias,
922 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
924 The following pseudo-ops from the Kane and Heinrich MIPS book are
925 specific to the type of debugging information being generated, and
926 should be defined by the object format: .aent, .begin, .bend,
927 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
930 The following pseudo-ops from the Kane and Heinrich MIPS book are
931 not MIPS CPU specific, but are also not specific to the object file
932 format. This file is probably the best place to define them, but
933 they are not currently supported: .asm0, .endr, .lab, .repeat,
936 static const pseudo_typeS mips_pseudo_table[] =
938 /* MIPS specific pseudo-ops. */
939 {"option", s_option, 0},
940 {"set", s_mipsset, 0},
941 {"rdata", s_change_sec, 'r'},
942 {"sdata", s_change_sec, 's'},
943 {"livereg", s_ignore, 0},
944 {"abicalls", s_abicalls, 0},
945 {"cpload", s_cpload, 0},
946 {"cpsetup", s_cpsetup, 0},
947 {"cplocal", s_cplocal, 0},
948 {"cprestore", s_cprestore, 0},
949 {"cpreturn", s_cpreturn, 0},
950 {"gpvalue", s_gpvalue, 0},
951 {"gpword", s_gpword, 0},
952 {"gpdword", s_gpdword, 0},
953 {"cpadd", s_cpadd, 0},
956 /* Relatively generic pseudo-ops that happen to be used on MIPS
958 {"asciiz", stringer, 1},
959 {"bss", s_change_sec, 'b'},
962 {"dword", s_cons, 3},
963 {"weakext", s_mips_weakext, 0},
965 /* These pseudo-ops are defined in read.c, but must be overridden
966 here for one reason or another. */
967 {"align", s_align, 0},
969 {"data", s_change_sec, 'd'},
970 {"double", s_float_cons, 'd'},
971 {"float", s_float_cons, 'f'},
972 {"globl", s_mips_globl, 0},
973 {"global", s_mips_globl, 0},
974 {"hword", s_cons, 1},
979 {"section", s_change_section, 0},
980 {"short", s_cons, 1},
981 {"single", s_float_cons, 'f'},
982 {"stabn", s_mips_stab, 'n'},
983 {"text", s_change_sec, 't'},
986 { "extern", ecoff_directive_extern, 0},
991 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
993 /* These pseudo-ops should be defined by the object file format.
994 However, a.out doesn't support them, so we have versions here. */
995 {"aent", s_mips_ent, 1},
996 {"bgnb", s_ignore, 0},
997 {"end", s_mips_end, 0},
998 {"endb", s_ignore, 0},
999 {"ent", s_mips_ent, 0},
1000 {"file", s_mips_file, 0},
1001 {"fmask", s_mips_mask, 'F'},
1002 {"frame", s_mips_frame, 0},
1003 {"loc", s_mips_loc, 0},
1004 {"mask", s_mips_mask, 'R'},
1005 {"verstamp", s_ignore, 0},
1009 extern void pop_insert (const pseudo_typeS *);
1012 mips_pop_insert (void)
1014 pop_insert (mips_pseudo_table);
1015 if (! ECOFF_DEBUGGING)
1016 pop_insert (mips_nonecoff_pseudo_table);
1019 /* Symbols labelling the current insn. */
1021 struct insn_label_list
1023 struct insn_label_list *next;
1027 static struct insn_label_list *insn_labels;
1028 static struct insn_label_list *free_insn_labels;
1030 static void mips_clear_insn_labels (void);
1033 mips_clear_insn_labels (void)
1035 register struct insn_label_list **pl;
1037 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1043 static char *expr_end;
1045 /* Expressions which appear in instructions. These are set by
1048 static expressionS imm_expr;
1049 static expressionS imm2_expr;
1050 static expressionS offset_expr;
1052 /* Relocs associated with imm_expr and offset_expr. */
1054 static bfd_reloc_code_real_type imm_reloc[3]
1055 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1056 static bfd_reloc_code_real_type offset_reloc[3]
1057 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1059 /* These are set by mips16_ip if an explicit extension is used. */
1061 static bfd_boolean mips16_small, mips16_ext;
1064 /* The pdr segment for per procedure frame/regmask info. Not used for
1067 static segT pdr_seg;
1070 /* The default target format to use. */
1073 mips_target_format (void)
1075 switch (OUTPUT_FLAVOR)
1077 case bfd_target_aout_flavour:
1078 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1079 case bfd_target_ecoff_flavour:
1080 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1081 case bfd_target_coff_flavour:
1083 case bfd_target_elf_flavour:
1085 /* This is traditional mips. */
1086 return (target_big_endian
1087 ? (HAVE_64BIT_OBJECTS
1088 ? "elf64-tradbigmips"
1090 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1091 : (HAVE_64BIT_OBJECTS
1092 ? "elf64-tradlittlemips"
1094 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1096 return (target_big_endian
1097 ? (HAVE_64BIT_OBJECTS
1100 ? "elf32-nbigmips" : "elf32-bigmips"))
1101 : (HAVE_64BIT_OBJECTS
1102 ? "elf64-littlemips"
1104 ? "elf32-nlittlemips" : "elf32-littlemips")));
1112 /* This function is called once, at assembler startup time. It should
1113 set up all the tables, etc. that the MD part of the assembler will need. */
1118 register const char *retval = NULL;
1122 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1123 as_warn (_("Could not set architecture and machine"));
1125 op_hash = hash_new ();
1127 for (i = 0; i < NUMOPCODES;)
1129 const char *name = mips_opcodes[i].name;
1131 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1134 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1135 mips_opcodes[i].name, retval);
1136 /* Probably a memory allocation problem? Give up now. */
1137 as_fatal (_("Broken assembler. No assembly attempted."));
1141 if (mips_opcodes[i].pinfo != INSN_MACRO)
1143 if (!validate_mips_insn (&mips_opcodes[i]))
1148 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1151 mips16_op_hash = hash_new ();
1154 while (i < bfd_mips16_num_opcodes)
1156 const char *name = mips16_opcodes[i].name;
1158 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1160 as_fatal (_("internal: can't hash `%s': %s"),
1161 mips16_opcodes[i].name, retval);
1164 if (mips16_opcodes[i].pinfo != INSN_MACRO
1165 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1166 != mips16_opcodes[i].match))
1168 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1169 mips16_opcodes[i].name, mips16_opcodes[i].args);
1174 while (i < bfd_mips16_num_opcodes
1175 && strcmp (mips16_opcodes[i].name, name) == 0);
1179 as_fatal (_("Broken assembler. No assembly attempted."));
1181 /* We add all the general register names to the symbol table. This
1182 helps us detect invalid uses of them. */
1183 for (i = 0; i < 32; i++)
1187 sprintf (buf, "$%d", i);
1188 symbol_table_insert (symbol_new (buf, reg_section, i,
1189 &zero_address_frag));
1191 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1192 &zero_address_frag));
1193 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1194 &zero_address_frag));
1195 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1196 &zero_address_frag));
1197 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1198 &zero_address_frag));
1199 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1200 &zero_address_frag));
1201 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1202 &zero_address_frag));
1203 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1204 &zero_address_frag));
1205 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1206 &zero_address_frag));
1207 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1208 &zero_address_frag));
1210 /* If we don't add these register names to the symbol table, they
1211 may end up being added as regular symbols by operand(), and then
1212 make it to the object file as undefined in case they're not
1213 regarded as local symbols. They're local in o32, since `$' is a
1214 local symbol prefix, but not in n32 or n64. */
1215 for (i = 0; i < 8; i++)
1219 sprintf (buf, "$fcc%i", i);
1220 symbol_table_insert (symbol_new (buf, reg_section, -1,
1221 &zero_address_frag));
1224 mips_no_prev_insn (FALSE);
1227 mips_cprmask[0] = 0;
1228 mips_cprmask[1] = 0;
1229 mips_cprmask[2] = 0;
1230 mips_cprmask[3] = 0;
1232 /* set the default alignment for the text section (2**2) */
1233 record_alignment (text_section, 2);
1235 if (USE_GLOBAL_POINTER_OPT)
1236 bfd_set_gp_size (stdoutput, g_switch_value);
1238 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1240 /* On a native system, sections must be aligned to 16 byte
1241 boundaries. When configured for an embedded ELF target, we
1243 if (strcmp (TARGET_OS, "elf") != 0)
1245 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1246 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1247 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1250 /* Create a .reginfo section for register masks and a .mdebug
1251 section for debugging information. */
1259 subseg = now_subseg;
1261 /* The ABI says this section should be loaded so that the
1262 running program can access it. However, we don't load it
1263 if we are configured for an embedded target */
1264 flags = SEC_READONLY | SEC_DATA;
1265 if (strcmp (TARGET_OS, "elf") != 0)
1266 flags |= SEC_ALLOC | SEC_LOAD;
1268 if (mips_abi != N64_ABI)
1270 sec = subseg_new (".reginfo", (subsegT) 0);
1272 bfd_set_section_flags (stdoutput, sec, flags);
1273 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1276 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1281 /* The 64-bit ABI uses a .MIPS.options section rather than
1282 .reginfo section. */
1283 sec = subseg_new (".MIPS.options", (subsegT) 0);
1284 bfd_set_section_flags (stdoutput, sec, flags);
1285 bfd_set_section_alignment (stdoutput, sec, 3);
1288 /* Set up the option header. */
1290 Elf_Internal_Options opthdr;
1293 opthdr.kind = ODK_REGINFO;
1294 opthdr.size = (sizeof (Elf_External_Options)
1295 + sizeof (Elf64_External_RegInfo));
1298 f = frag_more (sizeof (Elf_External_Options));
1299 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1300 (Elf_External_Options *) f);
1302 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1307 if (ECOFF_DEBUGGING)
1309 sec = subseg_new (".mdebug", (subsegT) 0);
1310 (void) bfd_set_section_flags (stdoutput, sec,
1311 SEC_HAS_CONTENTS | SEC_READONLY);
1312 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1315 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1317 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1318 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1319 SEC_READONLY | SEC_RELOC
1321 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1325 subseg_set (seg, subseg);
1329 if (! ECOFF_DEBUGGING)
1336 if (! ECOFF_DEBUGGING)
1341 md_assemble (char *str)
1343 struct mips_cl_insn insn;
1344 bfd_reloc_code_real_type unused_reloc[3]
1345 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1347 imm_expr.X_op = O_absent;
1348 imm2_expr.X_op = O_absent;
1349 offset_expr.X_op = O_absent;
1350 imm_reloc[0] = BFD_RELOC_UNUSED;
1351 imm_reloc[1] = BFD_RELOC_UNUSED;
1352 imm_reloc[2] = BFD_RELOC_UNUSED;
1353 offset_reloc[0] = BFD_RELOC_UNUSED;
1354 offset_reloc[1] = BFD_RELOC_UNUSED;
1355 offset_reloc[2] = BFD_RELOC_UNUSED;
1357 if (mips_opts.mips16)
1358 mips16_ip (str, &insn);
1361 mips_ip (str, &insn);
1362 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1363 str, insn.insn_opcode));
1368 as_bad ("%s `%s'", insn_error, str);
1372 if (insn.insn_mo->pinfo == INSN_MACRO)
1375 if (mips_opts.mips16)
1376 mips16_macro (&insn);
1383 if (imm_expr.X_op != O_absent)
1384 append_insn (&insn, &imm_expr, imm_reloc);
1385 else if (offset_expr.X_op != O_absent)
1386 append_insn (&insn, &offset_expr, offset_reloc);
1388 append_insn (&insn, NULL, unused_reloc);
1392 /* Return true if the given relocation might need a matching %lo().
1393 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1394 applied to local symbols. */
1396 static inline bfd_boolean
1397 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1399 return (reloc == BFD_RELOC_HI16_S
1400 || reloc == BFD_RELOC_MIPS_GOT16);
1403 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1406 static inline bfd_boolean
1407 fixup_has_matching_lo_p (fixS *fixp)
1409 return (fixp->fx_next != NULL
1410 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1411 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1412 && fixp->fx_offset == fixp->fx_next->fx_offset);
1415 /* See whether instruction IP reads register REG. CLASS is the type
1419 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1420 enum mips_regclass class)
1422 if (class == MIPS16_REG)
1424 assert (mips_opts.mips16);
1425 reg = mips16_to_32_reg_map[reg];
1426 class = MIPS_GR_REG;
1429 /* Don't report on general register ZERO, since it never changes. */
1430 if (class == MIPS_GR_REG && reg == ZERO)
1433 if (class == MIPS_FP_REG)
1435 assert (! mips_opts.mips16);
1436 /* If we are called with either $f0 or $f1, we must check $f0.
1437 This is not optimal, because it will introduce an unnecessary
1438 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1439 need to distinguish reading both $f0 and $f1 or just one of
1440 them. Note that we don't have to check the other way,
1441 because there is no instruction that sets both $f0 and $f1
1442 and requires a delay. */
1443 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1444 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1445 == (reg &~ (unsigned) 1)))
1447 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1448 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1449 == (reg &~ (unsigned) 1)))
1452 else if (! mips_opts.mips16)
1454 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1455 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1457 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1458 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1463 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1464 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1465 & MIPS16OP_MASK_RX)]
1468 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1469 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1470 & MIPS16OP_MASK_RY)]
1473 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1474 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1475 & MIPS16OP_MASK_MOVE32Z)]
1478 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1480 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1482 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1484 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1485 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1486 & MIPS16OP_MASK_REGR32) == reg)
1493 /* This function returns true if modifying a register requires a
1497 reg_needs_delay (unsigned int reg)
1499 unsigned long prev_pinfo;
1501 prev_pinfo = prev_insn.insn_mo->pinfo;
1502 if (! mips_opts.noreorder
1503 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1504 && ! gpr_interlocks)
1505 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1506 && ! cop_interlocks)))
1508 /* A load from a coprocessor or from memory. All load delays
1509 delay the use of general register rt for one instruction. */
1510 /* Itbl support may require additional care here. */
1511 know (prev_pinfo & INSN_WRITE_GPR_T);
1512 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1519 /* Mark instruction labels in mips16 mode. This permits the linker to
1520 handle them specially, such as generating jalx instructions when
1521 needed. We also make them odd for the duration of the assembly, in
1522 order to generate the right sort of code. We will make them even
1523 in the adjust_symtab routine, while leaving them marked. This is
1524 convenient for the debugger and the disassembler. The linker knows
1525 to make them odd again. */
1528 mips16_mark_labels (void)
1530 if (mips_opts.mips16)
1532 struct insn_label_list *l;
1535 for (l = insn_labels; l != NULL; l = l->next)
1538 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1539 S_SET_OTHER (l->label, STO_MIPS16);
1541 val = S_GET_VALUE (l->label);
1543 S_SET_VALUE (l->label, val + 1);
1548 /* End the current frag. Make it a variant frag and record the
1552 relax_close_frag (void)
1554 mips_macro_warning.first_frag = frag_now;
1555 frag_var (rs_machine_dependent, 0, 0,
1556 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1557 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1559 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1560 mips_relax.first_fixup = 0;
1563 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1564 See the comment above RELAX_ENCODE for more details. */
1567 relax_start (symbolS *symbol)
1569 assert (mips_relax.sequence == 0);
1570 mips_relax.sequence = 1;
1571 mips_relax.symbol = symbol;
1574 /* Start generating the second version of a relaxable sequence.
1575 See the comment above RELAX_ENCODE for more details. */
1580 assert (mips_relax.sequence == 1);
1581 mips_relax.sequence = 2;
1584 /* End the current relaxable sequence. */
1589 assert (mips_relax.sequence == 2);
1590 relax_close_frag ();
1591 mips_relax.sequence = 0;
1594 /* Output an instruction. IP is the instruction information.
1595 ADDRESS_EXPR is an operand of the instruction to be used with
1599 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1600 bfd_reloc_code_real_type *reloc_type)
1602 register unsigned long prev_pinfo, pinfo;
1606 relax_stateT prev_insn_frag_type = 0;
1607 bfd_boolean relaxed_branch = FALSE;
1608 bfd_boolean force_new_frag = FALSE;
1610 /* Mark instruction labels in mips16 mode. */
1611 mips16_mark_labels ();
1613 prev_pinfo = prev_insn.insn_mo->pinfo;
1614 pinfo = ip->insn_mo->pinfo;
1616 if (mips_relax.sequence != 2
1617 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1621 /* If the previous insn required any delay slots, see if we need
1622 to insert a NOP or two. There are eight kinds of possible
1623 hazards, of which an instruction can have at most one type.
1624 (1) a load from memory delay
1625 (2) a load from a coprocessor delay
1626 (3) an unconditional branch delay
1627 (4) a conditional branch delay
1628 (5) a move to coprocessor register delay
1629 (6) a load coprocessor register from memory delay
1630 (7) a coprocessor condition code delay
1631 (8) a HI/LO special register delay
1633 There are a lot of optimizations we could do that we don't.
1634 In particular, we do not, in general, reorder instructions.
1635 If you use gcc with optimization, it will reorder
1636 instructions and generally do much more optimization then we
1637 do here; repeating all that work in the assembler would only
1638 benefit hand written assembly code, and does not seem worth
1641 /* This is how a NOP is emitted. */
1642 #define emit_nop() \
1644 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1645 : md_number_to_chars (frag_more (4), 0, 4))
1647 /* The previous insn might require a delay slot, depending upon
1648 the contents of the current insn. */
1649 if (! mips_opts.mips16
1650 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1651 && ! gpr_interlocks)
1652 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1653 && ! cop_interlocks)))
1655 /* A load from a coprocessor or from memory. All load
1656 delays delay the use of general register rt for one
1658 /* Itbl support may require additional care here. */
1659 know (prev_pinfo & INSN_WRITE_GPR_T);
1660 if (mips_optimize == 0
1661 || insn_uses_reg (ip,
1662 ((prev_insn.insn_opcode >> OP_SH_RT)
1667 else if (! mips_opts.mips16
1668 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1669 && ! cop_interlocks)
1670 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1671 && ! cop_mem_interlocks)))
1673 /* A generic coprocessor delay. The previous instruction
1674 modified a coprocessor general or control register. If
1675 it modified a control register, we need to avoid any
1676 coprocessor instruction (this is probably not always
1677 required, but it sometimes is). If it modified a general
1678 register, we avoid using that register.
1680 This case is not handled very well. There is no special
1681 knowledge of CP0 handling, and the coprocessors other
1682 than the floating point unit are not distinguished at
1684 /* Itbl support may require additional care here. FIXME!
1685 Need to modify this to include knowledge about
1686 user specified delays! */
1687 if (prev_pinfo & INSN_WRITE_FPR_T)
1689 if (mips_optimize == 0
1690 || insn_uses_reg (ip,
1691 ((prev_insn.insn_opcode >> OP_SH_FT)
1696 else if (prev_pinfo & INSN_WRITE_FPR_S)
1698 if (mips_optimize == 0
1699 || insn_uses_reg (ip,
1700 ((prev_insn.insn_opcode >> OP_SH_FS)
1707 /* We don't know exactly what the previous instruction
1708 does. If the current instruction uses a coprocessor
1709 register, we must insert a NOP. If previous
1710 instruction may set the condition codes, and the
1711 current instruction uses them, we must insert two
1713 /* Itbl support may require additional care here. */
1714 if (mips_optimize == 0
1715 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1716 && (pinfo & INSN_READ_COND_CODE)))
1718 else if (pinfo & INSN_COP)
1722 else if (! mips_opts.mips16
1723 && (prev_pinfo & INSN_WRITE_COND_CODE)
1724 && ! cop_interlocks)
1726 /* The previous instruction sets the coprocessor condition
1727 codes, but does not require a general coprocessor delay
1728 (this means it is a floating point comparison
1729 instruction). If this instruction uses the condition
1730 codes, we need to insert a single NOP. */
1731 /* Itbl support may require additional care here. */
1732 if (mips_optimize == 0
1733 || (pinfo & INSN_READ_COND_CODE))
1737 /* If we're fixing up mfhi/mflo for the r7000 and the
1738 previous insn was an mfhi/mflo and the current insn
1739 reads the register that the mfhi/mflo wrote to, then
1742 else if (mips_7000_hilo_fix
1743 && MF_HILO_INSN (prev_pinfo)
1744 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1751 /* If we're fixing up mfhi/mflo for the r7000 and the
1752 2nd previous insn was an mfhi/mflo and the current insn
1753 reads the register that the mfhi/mflo wrote to, then
1756 else if (mips_7000_hilo_fix
1757 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1758 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1766 else if (prev_pinfo & INSN_READ_LO)
1768 /* The previous instruction reads the LO register; if the
1769 current instruction writes to the LO register, we must
1770 insert two NOPS. Some newer processors have interlocks.
1771 Also the tx39's multiply instructions can be executed
1772 immediately after a read from HI/LO (without the delay),
1773 though the tx39's divide insns still do require the
1775 if (! (hilo_interlocks
1776 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1777 && (mips_optimize == 0
1778 || (pinfo & INSN_WRITE_LO)))
1780 /* Most mips16 branch insns don't have a delay slot.
1781 If a read from LO is immediately followed by a branch
1782 to a write to LO we have a read followed by a write
1783 less than 2 insns away. We assume the target of
1784 a branch might be a write to LO, and insert a nop
1785 between a read and an immediately following branch. */
1786 else if (mips_opts.mips16
1787 && (mips_optimize == 0
1788 || (pinfo & MIPS16_INSN_BRANCH)))
1791 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1793 /* The previous instruction reads the HI register; if the
1794 current instruction writes to the HI register, we must
1795 insert a NOP. Some newer processors have interlocks.
1796 Also the note tx39's multiply above. */
1797 if (! (hilo_interlocks
1798 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1799 && (mips_optimize == 0
1800 || (pinfo & INSN_WRITE_HI)))
1802 /* Most mips16 branch insns don't have a delay slot.
1803 If a read from HI is immediately followed by a branch
1804 to a write to HI we have a read followed by a write
1805 less than 2 insns away. We assume the target of
1806 a branch might be a write to HI, and insert a nop
1807 between a read and an immediately following branch. */
1808 else if (mips_opts.mips16
1809 && (mips_optimize == 0
1810 || (pinfo & MIPS16_INSN_BRANCH)))
1814 /* If the previous instruction was in a noreorder section, then
1815 we don't want to insert the nop after all. */
1816 /* Itbl support may require additional care here. */
1817 if (prev_insn_unreordered)
1820 /* There are two cases which require two intervening
1821 instructions: 1) setting the condition codes using a move to
1822 coprocessor instruction which requires a general coprocessor
1823 delay and then reading the condition codes 2) reading the HI
1824 or LO register and then writing to it (except on processors
1825 which have interlocks). If we are not already emitting a NOP
1826 instruction, we must check for these cases compared to the
1827 instruction previous to the previous instruction. */
1828 if ((! mips_opts.mips16
1829 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1830 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1831 && (pinfo & INSN_READ_COND_CODE)
1832 && ! cop_interlocks)
1833 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1834 && (pinfo & INSN_WRITE_LO)
1835 && ! (hilo_interlocks
1836 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1837 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1838 && (pinfo & INSN_WRITE_HI)
1839 && ! (hilo_interlocks
1840 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1845 if (prev_prev_insn_unreordered)
1848 if (prev_prev_nop && nops == 0)
1851 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1853 /* We're out of bits in pinfo, so we must resort to string
1854 ops here. Shortcuts are selected based on opcodes being
1855 limited to the VR4122 instruction set. */
1857 const char *pn = prev_insn.insn_mo->name;
1858 const char *tn = ip->insn_mo->name;
1859 if (strncmp(pn, "macc", 4) == 0
1860 || strncmp(pn, "dmacc", 5) == 0)
1862 /* Errata 21 - [D]DIV[U] after [D]MACC */
1863 if (strstr (tn, "div"))
1868 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1869 if (pn[0] == 'd' /* dmacc */
1870 && (strncmp(tn, "dmult", 5) == 0
1871 || strncmp(tn, "dmacc", 5) == 0))
1876 /* Errata 24 - MT{LO,HI} after [D]MACC */
1877 if (strcmp (tn, "mtlo") == 0
1878 || strcmp (tn, "mthi") == 0)
1884 else if (strncmp(pn, "dmult", 5) == 0
1885 && (strncmp(tn, "dmult", 5) == 0
1886 || strncmp(tn, "dmacc", 5) == 0))
1888 /* Here is the rest of errata 23. */
1891 if (nops < min_nops)
1895 /* If we are being given a nop instruction, don't bother with
1896 one of the nops we would otherwise output. This will only
1897 happen when a nop instruction is used with mips_optimize set
1900 && ! mips_opts.noreorder
1901 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1904 /* Now emit the right number of NOP instructions. */
1905 if (nops > 0 && ! mips_opts.noreorder)
1908 unsigned long old_frag_offset;
1910 struct insn_label_list *l;
1912 old_frag = frag_now;
1913 old_frag_offset = frag_now_fix ();
1915 for (i = 0; i < nops; i++)
1920 listing_prev_line ();
1921 /* We may be at the start of a variant frag. In case we
1922 are, make sure there is enough space for the frag
1923 after the frags created by listing_prev_line. The
1924 argument to frag_grow here must be at least as large
1925 as the argument to all other calls to frag_grow in
1926 this file. We don't have to worry about being in the
1927 middle of a variant frag, because the variants insert
1928 all needed nop instructions themselves. */
1932 for (l = insn_labels; l != NULL; l = l->next)
1936 assert (S_GET_SEGMENT (l->label) == now_seg);
1937 symbol_set_frag (l->label, frag_now);
1938 val = (valueT) frag_now_fix ();
1939 /* mips16 text labels are stored as odd. */
1940 if (mips_opts.mips16)
1942 S_SET_VALUE (l->label, val);
1945 #ifndef NO_ECOFF_DEBUGGING
1946 if (ECOFF_DEBUGGING)
1947 ecoff_fix_loc (old_frag, old_frag_offset);
1950 else if (prev_nop_frag != NULL)
1952 /* We have a frag holding nops we may be able to remove. If
1953 we don't need any nops, we can decrease the size of
1954 prev_nop_frag by the size of one instruction. If we do
1955 need some nops, we count them in prev_nops_required. */
1956 if (prev_nop_frag_since == 0)
1960 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1961 --prev_nop_frag_holds;
1964 prev_nop_frag_required += nops;
1968 if (prev_prev_nop == 0)
1970 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1971 --prev_nop_frag_holds;
1974 ++prev_nop_frag_required;
1977 if (prev_nop_frag_holds <= prev_nop_frag_required)
1978 prev_nop_frag = NULL;
1980 ++prev_nop_frag_since;
1982 /* Sanity check: by the time we reach the second instruction
1983 after prev_nop_frag, we should have used up all the nops
1984 one way or another. */
1985 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1989 /* Record the frag type before frag_var. */
1991 prev_insn_frag_type = prev_insn_frag->fr_type;
1994 && *reloc_type == BFD_RELOC_16_PCREL_S2
1995 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1996 || pinfo & INSN_COND_BRANCH_LIKELY)
1997 && mips_relax_branch
1998 /* Don't try branch relaxation within .set nomacro, or within
1999 .set noat if we use $at for PIC computations. If it turns
2000 out that the branch was out-of-range, we'll get an error. */
2001 && !mips_opts.warn_about_macros
2002 && !(mips_opts.noat && mips_pic != NO_PIC)
2003 && !mips_opts.mips16)
2005 relaxed_branch = TRUE;
2006 f = frag_var (rs_machine_dependent,
2007 relaxed_branch_length
2009 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2010 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2012 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2013 pinfo & INSN_COND_BRANCH_LIKELY,
2014 pinfo & INSN_WRITE_GPR_31,
2016 address_expr->X_add_symbol,
2017 address_expr->X_add_number,
2019 *reloc_type = BFD_RELOC_UNUSED;
2021 else if (*reloc_type > BFD_RELOC_UNUSED)
2023 /* We need to set up a variant frag. */
2024 assert (mips_opts.mips16 && address_expr != NULL);
2025 f = frag_var (rs_machine_dependent, 4, 0,
2026 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2027 mips16_small, mips16_ext,
2029 & INSN_UNCOND_BRANCH_DELAY),
2030 (*prev_insn_reloc_type
2031 == BFD_RELOC_MIPS16_JMP)),
2032 make_expr_symbol (address_expr), 0, NULL);
2034 else if (mips_opts.mips16
2036 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2038 /* Make sure there is enough room to swap this instruction with
2039 a following jump instruction. */
2045 if (mips_opts.mips16
2046 && mips_opts.noreorder
2047 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2048 as_warn (_("extended instruction in delay slot"));
2050 if (mips_relax.sequence)
2052 /* If we've reached the end of this frag, turn it into a variant
2053 frag and record the information for the instructions we've
2055 if (frag_room () < 4)
2056 relax_close_frag ();
2057 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2060 if (mips_relax.sequence != 2)
2061 mips_macro_warning.sizes[0] += 4;
2062 if (mips_relax.sequence != 1)
2063 mips_macro_warning.sizes[1] += 4;
2068 fixp[0] = fixp[1] = fixp[2] = NULL;
2069 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2071 if (address_expr->X_op == O_constant)
2075 switch (*reloc_type)
2078 ip->insn_opcode |= address_expr->X_add_number;
2081 case BFD_RELOC_MIPS_HIGHEST:
2082 tmp = (address_expr->X_add_number
2083 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2085 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2088 case BFD_RELOC_MIPS_HIGHER:
2089 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2090 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2093 case BFD_RELOC_HI16_S:
2094 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2098 case BFD_RELOC_HI16:
2099 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2102 case BFD_RELOC_LO16:
2103 case BFD_RELOC_MIPS_GOT_DISP:
2104 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2107 case BFD_RELOC_MIPS_JMP:
2108 if ((address_expr->X_add_number & 3) != 0)
2109 as_bad (_("jump to misaligned address (0x%lx)"),
2110 (unsigned long) address_expr->X_add_number);
2111 if (address_expr->X_add_number & ~0xfffffff)
2112 as_bad (_("jump address range overflow (0x%lx)"),
2113 (unsigned long) address_expr->X_add_number);
2114 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2117 case BFD_RELOC_MIPS16_JMP:
2118 if ((address_expr->X_add_number & 3) != 0)
2119 as_bad (_("jump to misaligned address (0x%lx)"),
2120 (unsigned long) address_expr->X_add_number);
2121 if (address_expr->X_add_number & ~0xfffffff)
2122 as_bad (_("jump address range overflow (0x%lx)"),
2123 (unsigned long) address_expr->X_add_number);
2125 (((address_expr->X_add_number & 0x7c0000) << 3)
2126 | ((address_expr->X_add_number & 0xf800000) >> 7)
2127 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2130 case BFD_RELOC_16_PCREL_S2:
2140 reloc_howto_type *howto;
2143 /* In a compound relocation, it is the final (outermost)
2144 operator that determines the relocated field. */
2145 for (i = 1; i < 3; i++)
2146 if (reloc_type[i] == BFD_RELOC_UNUSED)
2149 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2150 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2151 bfd_get_reloc_size(howto),
2153 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2156 /* These relocations can have an addend that won't fit in
2157 4 octets for 64bit assembly. */
2159 && ! howto->partial_inplace
2160 && (reloc_type[0] == BFD_RELOC_16
2161 || reloc_type[0] == BFD_RELOC_32
2162 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2163 || reloc_type[0] == BFD_RELOC_HI16_S
2164 || reloc_type[0] == BFD_RELOC_LO16
2165 || reloc_type[0] == BFD_RELOC_GPREL16
2166 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2167 || reloc_type[0] == BFD_RELOC_GPREL32
2168 || reloc_type[0] == BFD_RELOC_64
2169 || reloc_type[0] == BFD_RELOC_CTOR
2170 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2171 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2172 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2173 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2174 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2175 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2176 fixp[0]->fx_no_overflow = 1;
2178 if (mips_relax.sequence)
2180 if (mips_relax.first_fixup == 0)
2181 mips_relax.first_fixup = fixp[0];
2183 else if (reloc_needs_lo_p (*reloc_type))
2185 struct mips_hi_fixup *hi_fixup;
2187 /* Reuse the last entry if it already has a matching %lo. */
2188 hi_fixup = mips_hi_fixup_list;
2190 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2192 hi_fixup = ((struct mips_hi_fixup *)
2193 xmalloc (sizeof (struct mips_hi_fixup)));
2194 hi_fixup->next = mips_hi_fixup_list;
2195 mips_hi_fixup_list = hi_fixup;
2197 hi_fixup->fixp = fixp[0];
2198 hi_fixup->seg = now_seg;
2201 /* Add fixups for the second and third relocations, if given.
2202 Note that the ABI allows the second relocation to be
2203 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2204 moment we only use RSS_UNDEF, but we could add support
2205 for the others if it ever becomes necessary. */
2206 for (i = 1; i < 3; i++)
2207 if (reloc_type[i] != BFD_RELOC_UNUSED)
2209 address_expr->X_op = O_absent;
2210 address_expr->X_add_symbol = 0;
2211 address_expr->X_add_number = 0;
2213 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2214 fixp[0]->fx_size, address_expr,
2215 FALSE, reloc_type[i]);
2220 if (! mips_opts.mips16)
2222 md_number_to_chars (f, ip->insn_opcode, 4);
2224 dwarf2_emit_insn (4);
2227 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2229 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2230 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2232 dwarf2_emit_insn (4);
2239 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2242 md_number_to_chars (f, ip->insn_opcode, 2);
2244 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2248 /* Update the register mask information. */
2249 if (! mips_opts.mips16)
2251 if (pinfo & INSN_WRITE_GPR_D)
2252 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2253 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2254 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2255 if (pinfo & INSN_READ_GPR_S)
2256 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2257 if (pinfo & INSN_WRITE_GPR_31)
2258 mips_gprmask |= 1 << RA;
2259 if (pinfo & INSN_WRITE_FPR_D)
2260 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2261 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2262 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2263 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2264 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2265 if ((pinfo & INSN_READ_FPR_R) != 0)
2266 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2267 if (pinfo & INSN_COP)
2269 /* We don't keep enough information to sort these cases out.
2270 The itbl support does keep this information however, although
2271 we currently don't support itbl fprmats as part of the cop
2272 instruction. May want to add this support in the future. */
2274 /* Never set the bit for $0, which is always zero. */
2275 mips_gprmask &= ~1 << 0;
2279 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2280 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2281 & MIPS16OP_MASK_RX);
2282 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2283 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2284 & MIPS16OP_MASK_RY);
2285 if (pinfo & MIPS16_INSN_WRITE_Z)
2286 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2287 & MIPS16OP_MASK_RZ);
2288 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2289 mips_gprmask |= 1 << TREG;
2290 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2291 mips_gprmask |= 1 << SP;
2292 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2293 mips_gprmask |= 1 << RA;
2294 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2295 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2296 if (pinfo & MIPS16_INSN_READ_Z)
2297 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2298 & MIPS16OP_MASK_MOVE32Z);
2299 if (pinfo & MIPS16_INSN_READ_GPR_X)
2300 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2301 & MIPS16OP_MASK_REGR32);
2304 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2306 /* Filling the branch delay slot is more complex. We try to
2307 switch the branch with the previous instruction, which we can
2308 do if the previous instruction does not set up a condition
2309 that the branch tests and if the branch is not itself the
2310 target of any branch. */
2311 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2312 || (pinfo & INSN_COND_BRANCH_DELAY))
2314 if (mips_optimize < 2
2315 /* If we have seen .set volatile or .set nomove, don't
2317 || mips_opts.nomove != 0
2318 /* If we had to emit any NOP instructions, then we
2319 already know we can not swap. */
2321 /* If we don't even know the previous insn, we can not
2323 || ! prev_insn_valid
2324 /* If the previous insn is already in a branch delay
2325 slot, then we can not swap. */
2326 || prev_insn_is_delay_slot
2327 /* If the previous previous insn was in a .set
2328 noreorder, we can't swap. Actually, the MIPS
2329 assembler will swap in this situation. However, gcc
2330 configured -with-gnu-as will generate code like
2336 in which we can not swap the bne and INSN. If gcc is
2337 not configured -with-gnu-as, it does not output the
2338 .set pseudo-ops. We don't have to check
2339 prev_insn_unreordered, because prev_insn_valid will
2340 be 0 in that case. We don't want to use
2341 prev_prev_insn_valid, because we do want to be able
2342 to swap at the start of a function. */
2343 || prev_prev_insn_unreordered
2344 /* If the branch is itself the target of a branch, we
2345 can not swap. We cheat on this; all we check for is
2346 whether there is a label on this instruction. If
2347 there are any branches to anything other than a
2348 label, users must use .set noreorder. */
2349 || insn_labels != NULL
2350 /* If the previous instruction is in a variant frag
2351 other than this branch's one, we cannot do the swap.
2352 This does not apply to the mips16, which uses variant
2353 frags for different purposes. */
2354 || (! mips_opts.mips16
2355 && prev_insn_frag_type == rs_machine_dependent)
2356 /* If the branch reads the condition codes, we don't
2357 even try to swap, because in the sequence
2362 we can not swap, and I don't feel like handling that
2364 || (! mips_opts.mips16
2365 && (pinfo & INSN_READ_COND_CODE)
2366 && ! cop_interlocks)
2367 /* We can not swap with an instruction that requires a
2368 delay slot, because the target of the branch might
2369 interfere with that instruction. */
2370 || (! mips_opts.mips16
2372 /* Itbl support may require additional care here. */
2373 & (INSN_LOAD_COPROC_DELAY
2374 | INSN_COPROC_MOVE_DELAY
2375 | INSN_WRITE_COND_CODE))
2376 && ! cop_interlocks)
2377 || (! (hilo_interlocks
2378 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2382 || (! mips_opts.mips16
2383 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2384 && ! gpr_interlocks)
2385 || (! mips_opts.mips16
2386 /* Itbl support may require additional care here. */
2387 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2388 && ! cop_mem_interlocks)
2389 /* We can not swap with a branch instruction. */
2391 & (INSN_UNCOND_BRANCH_DELAY
2392 | INSN_COND_BRANCH_DELAY
2393 | INSN_COND_BRANCH_LIKELY))
2394 /* We do not swap with a trap instruction, since it
2395 complicates trap handlers to have the trap
2396 instruction be in a delay slot. */
2397 || (prev_pinfo & INSN_TRAP)
2398 /* If the branch reads a register that the previous
2399 instruction sets, we can not swap. */
2400 || (! mips_opts.mips16
2401 && (prev_pinfo & INSN_WRITE_GPR_T)
2402 && insn_uses_reg (ip,
2403 ((prev_insn.insn_opcode >> OP_SH_RT)
2406 || (! mips_opts.mips16
2407 && (prev_pinfo & INSN_WRITE_GPR_D)
2408 && insn_uses_reg (ip,
2409 ((prev_insn.insn_opcode >> OP_SH_RD)
2412 || (mips_opts.mips16
2413 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2414 && insn_uses_reg (ip,
2415 ((prev_insn.insn_opcode
2417 & MIPS16OP_MASK_RX),
2419 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2420 && insn_uses_reg (ip,
2421 ((prev_insn.insn_opcode
2423 & MIPS16OP_MASK_RY),
2425 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2426 && insn_uses_reg (ip,
2427 ((prev_insn.insn_opcode
2429 & MIPS16OP_MASK_RZ),
2431 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2432 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2433 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2434 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2435 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2436 && insn_uses_reg (ip,
2437 MIPS16OP_EXTRACT_REG32R (prev_insn.
2440 /* If the branch writes a register that the previous
2441 instruction sets, we can not swap (we know that
2442 branches write only to RD or to $31). */
2443 || (! mips_opts.mips16
2444 && (prev_pinfo & INSN_WRITE_GPR_T)
2445 && (((pinfo & INSN_WRITE_GPR_D)
2446 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2447 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2448 || ((pinfo & INSN_WRITE_GPR_31)
2449 && (((prev_insn.insn_opcode >> OP_SH_RT)
2452 || (! mips_opts.mips16
2453 && (prev_pinfo & INSN_WRITE_GPR_D)
2454 && (((pinfo & INSN_WRITE_GPR_D)
2455 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2456 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2457 || ((pinfo & INSN_WRITE_GPR_31)
2458 && (((prev_insn.insn_opcode >> OP_SH_RD)
2461 || (mips_opts.mips16
2462 && (pinfo & MIPS16_INSN_WRITE_31)
2463 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2464 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2465 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2467 /* If the branch writes a register that the previous
2468 instruction reads, we can not swap (we know that
2469 branches only write to RD or to $31). */
2470 || (! mips_opts.mips16
2471 && (pinfo & INSN_WRITE_GPR_D)
2472 && insn_uses_reg (&prev_insn,
2473 ((ip->insn_opcode >> OP_SH_RD)
2476 || (! mips_opts.mips16
2477 && (pinfo & INSN_WRITE_GPR_31)
2478 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2479 || (mips_opts.mips16
2480 && (pinfo & MIPS16_INSN_WRITE_31)
2481 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2482 /* If we are generating embedded PIC code, the branch
2483 might be expanded into a sequence which uses $at, so
2484 we can't swap with an instruction which reads it. */
2485 || (mips_pic == EMBEDDED_PIC
2486 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2487 /* If the previous previous instruction has a load
2488 delay, and sets a register that the branch reads, we
2490 || (! mips_opts.mips16
2491 /* Itbl support may require additional care here. */
2492 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2493 && ! cop_interlocks)
2494 || ((prev_prev_insn.insn_mo->pinfo
2495 & INSN_LOAD_MEMORY_DELAY)
2496 && ! gpr_interlocks))
2497 && insn_uses_reg (ip,
2498 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2501 /* If one instruction sets a condition code and the
2502 other one uses a condition code, we can not swap. */
2503 || ((pinfo & INSN_READ_COND_CODE)
2504 && (prev_pinfo & INSN_WRITE_COND_CODE))
2505 || ((pinfo & INSN_WRITE_COND_CODE)
2506 && (prev_pinfo & INSN_READ_COND_CODE))
2507 /* If the previous instruction uses the PC, we can not
2509 || (mips_opts.mips16
2510 && (prev_pinfo & MIPS16_INSN_READ_PC))
2511 /* If the previous instruction was extended, we can not
2513 || (mips_opts.mips16 && prev_insn_extended)
2514 /* If the previous instruction had a fixup in mips16
2515 mode, we can not swap. This normally means that the
2516 previous instruction was a 4 byte branch anyhow. */
2517 || (mips_opts.mips16 && prev_insn_fixp[0])
2518 /* If the previous instruction is a sync, sync.l, or
2519 sync.p, we can not swap. */
2520 || (prev_pinfo & INSN_SYNC))
2522 /* We could do even better for unconditional branches to
2523 portions of this object file; we could pick up the
2524 instruction at the destination, put it in the delay
2525 slot, and bump the destination address. */
2527 /* Update the previous insn information. */
2528 prev_prev_insn = *ip;
2529 prev_insn.insn_mo = &dummy_opcode;
2533 /* It looks like we can actually do the swap. */
2534 if (! mips_opts.mips16)
2539 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2540 if (!relaxed_branch)
2542 /* If this is not a relaxed branch, then just
2543 swap the instructions. */
2544 memcpy (temp, prev_f, 4);
2545 memcpy (prev_f, f, 4);
2546 memcpy (f, temp, 4);
2550 /* If this is a relaxed branch, then we move the
2551 instruction to be placed in the delay slot to
2552 the current frag, shrinking the fixed part of
2553 the originating frag. If the branch occupies
2554 the tail of the latter, we move it backwards,
2555 into the space freed by the moved instruction. */
2557 memcpy (f, prev_f, 4);
2558 prev_insn_frag->fr_fix -= 4;
2559 if (prev_insn_frag->fr_type == rs_machine_dependent)
2560 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2563 if (prev_insn_fixp[0])
2565 prev_insn_fixp[0]->fx_frag = frag_now;
2566 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2568 if (prev_insn_fixp[1])
2570 prev_insn_fixp[1]->fx_frag = frag_now;
2571 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2573 if (prev_insn_fixp[2])
2575 prev_insn_fixp[2]->fx_frag = frag_now;
2576 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2578 if (prev_insn_fixp[0] && HAVE_NEWABI
2579 && prev_insn_frag != frag_now
2580 && (prev_insn_fixp[0]->fx_r_type
2581 == BFD_RELOC_MIPS_GOT_DISP
2582 || (prev_insn_fixp[0]->fx_r_type
2583 == BFD_RELOC_MIPS_CALL16)))
2585 /* To avoid confusion in tc_gen_reloc, we must
2586 ensure that this does not become a variant
2588 force_new_frag = TRUE;
2591 if (!relaxed_branch)
2595 fixp[0]->fx_frag = prev_insn_frag;
2596 fixp[0]->fx_where = prev_insn_where;
2600 fixp[1]->fx_frag = prev_insn_frag;
2601 fixp[1]->fx_where = prev_insn_where;
2605 fixp[2]->fx_frag = prev_insn_frag;
2606 fixp[2]->fx_where = prev_insn_where;
2609 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2612 fixp[0]->fx_where -= 4;
2614 fixp[1]->fx_where -= 4;
2616 fixp[2]->fx_where -= 4;
2624 assert (prev_insn_fixp[0] == NULL);
2625 assert (prev_insn_fixp[1] == NULL);
2626 assert (prev_insn_fixp[2] == NULL);
2627 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2628 memcpy (temp, prev_f, 2);
2629 memcpy (prev_f, f, 2);
2630 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2632 assert (*reloc_type == BFD_RELOC_UNUSED);
2633 memcpy (f, temp, 2);
2637 memcpy (f, f + 2, 2);
2638 memcpy (f + 2, temp, 2);
2642 fixp[0]->fx_frag = prev_insn_frag;
2643 fixp[0]->fx_where = prev_insn_where;
2647 fixp[1]->fx_frag = prev_insn_frag;
2648 fixp[1]->fx_where = prev_insn_where;
2652 fixp[2]->fx_frag = prev_insn_frag;
2653 fixp[2]->fx_where = prev_insn_where;
2657 /* Update the previous insn information; leave prev_insn
2659 prev_prev_insn = *ip;
2661 prev_insn_is_delay_slot = 1;
2663 /* If that was an unconditional branch, forget the previous
2664 insn information. */
2665 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2667 prev_prev_insn.insn_mo = &dummy_opcode;
2668 prev_insn.insn_mo = &dummy_opcode;
2671 prev_insn_fixp[0] = NULL;
2672 prev_insn_fixp[1] = NULL;
2673 prev_insn_fixp[2] = NULL;
2674 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2675 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2676 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2677 prev_insn_extended = 0;
2679 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2681 /* We don't yet optimize a branch likely. What we should do
2682 is look at the target, copy the instruction found there
2683 into the delay slot, and increment the branch to jump to
2684 the next instruction. */
2686 /* Update the previous insn information. */
2687 prev_prev_insn = *ip;
2688 prev_insn.insn_mo = &dummy_opcode;
2689 prev_insn_fixp[0] = NULL;
2690 prev_insn_fixp[1] = NULL;
2691 prev_insn_fixp[2] = NULL;
2692 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2693 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2694 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2695 prev_insn_extended = 0;
2699 /* Update the previous insn information. */
2701 prev_prev_insn.insn_mo = &dummy_opcode;
2703 prev_prev_insn = prev_insn;
2706 /* Any time we see a branch, we always fill the delay slot
2707 immediately; since this insn is not a branch, we know it
2708 is not in a delay slot. */
2709 prev_insn_is_delay_slot = 0;
2711 prev_insn_fixp[0] = fixp[0];
2712 prev_insn_fixp[1] = fixp[1];
2713 prev_insn_fixp[2] = fixp[2];
2714 prev_insn_reloc_type[0] = reloc_type[0];
2715 prev_insn_reloc_type[1] = reloc_type[1];
2716 prev_insn_reloc_type[2] = reloc_type[2];
2717 if (mips_opts.mips16)
2718 prev_insn_extended = (ip->use_extend
2719 || *reloc_type > BFD_RELOC_UNUSED);
2722 prev_prev_insn_unreordered = prev_insn_unreordered;
2723 prev_insn_unreordered = 0;
2724 prev_insn_frag = frag_now;
2725 prev_insn_where = f - frag_now->fr_literal;
2726 prev_insn_valid = 1;
2728 else if (mips_relax.sequence != 2)
2730 /* We need to record a bit of information even when we are not
2731 reordering, in order to determine the base address for mips16
2732 PC relative relocs. */
2733 prev_prev_insn = prev_insn;
2735 prev_insn_reloc_type[0] = reloc_type[0];
2736 prev_insn_reloc_type[1] = reloc_type[1];
2737 prev_insn_reloc_type[2] = reloc_type[2];
2738 prev_prev_insn_unreordered = prev_insn_unreordered;
2739 prev_insn_unreordered = 1;
2742 /* We just output an insn, so the next one doesn't have a label. */
2743 mips_clear_insn_labels ();
2746 /* This function forgets that there was any previous instruction or
2747 label. If PRESERVE is non-zero, it remembers enough information to
2748 know whether nops are needed before a noreorder section. */
2751 mips_no_prev_insn (int preserve)
2755 prev_insn.insn_mo = &dummy_opcode;
2756 prev_prev_insn.insn_mo = &dummy_opcode;
2757 prev_nop_frag = NULL;
2758 prev_nop_frag_holds = 0;
2759 prev_nop_frag_required = 0;
2760 prev_nop_frag_since = 0;
2762 prev_insn_valid = 0;
2763 prev_insn_is_delay_slot = 0;
2764 prev_insn_unreordered = 0;
2765 prev_insn_extended = 0;
2766 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2767 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2768 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2769 prev_prev_insn_unreordered = 0;
2770 mips_clear_insn_labels ();
2773 /* This function must be called whenever we turn on noreorder or emit
2774 something other than instructions. It inserts any NOPS which might
2775 be needed by the previous instruction, and clears the information
2776 kept for the previous instructions. The INSNS parameter is true if
2777 instructions are to follow. */
2780 mips_emit_delays (bfd_boolean insns)
2782 if (! mips_opts.noreorder)
2787 if ((! mips_opts.mips16
2788 && ((prev_insn.insn_mo->pinfo
2789 & (INSN_LOAD_COPROC_DELAY
2790 | INSN_COPROC_MOVE_DELAY
2791 | INSN_WRITE_COND_CODE))
2792 && ! cop_interlocks))
2793 || (! hilo_interlocks
2794 && (prev_insn.insn_mo->pinfo
2797 || (! mips_opts.mips16
2798 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2799 && ! gpr_interlocks)
2800 || (! mips_opts.mips16
2801 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2802 && ! cop_mem_interlocks))
2804 /* Itbl support may require additional care here. */
2806 if ((! mips_opts.mips16
2807 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2808 && ! cop_interlocks))
2809 || (! hilo_interlocks
2810 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2811 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2814 if (prev_insn_unreordered)
2817 else if ((! mips_opts.mips16
2818 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2819 && ! cop_interlocks))
2820 || (! hilo_interlocks
2821 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2822 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2824 /* Itbl support may require additional care here. */
2825 if (! prev_prev_insn_unreordered)
2829 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2832 const char *pn = prev_insn.insn_mo->name;
2833 if (strncmp(pn, "macc", 4) == 0
2834 || strncmp(pn, "dmacc", 5) == 0
2835 || strncmp(pn, "dmult", 5) == 0)
2839 if (nops < min_nops)
2845 struct insn_label_list *l;
2849 /* Record the frag which holds the nop instructions, so
2850 that we can remove them if we don't need them. */
2851 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2852 prev_nop_frag = frag_now;
2853 prev_nop_frag_holds = nops;
2854 prev_nop_frag_required = 0;
2855 prev_nop_frag_since = 0;
2858 for (; nops > 0; --nops)
2863 /* Move on to a new frag, so that it is safe to simply
2864 decrease the size of prev_nop_frag. */
2865 frag_wane (frag_now);
2869 for (l = insn_labels; l != NULL; l = l->next)
2873 assert (S_GET_SEGMENT (l->label) == now_seg);
2874 symbol_set_frag (l->label, frag_now);
2875 val = (valueT) frag_now_fix ();
2876 /* mips16 text labels are stored as odd. */
2877 if (mips_opts.mips16)
2879 S_SET_VALUE (l->label, val);
2884 /* Mark instruction labels in mips16 mode. */
2886 mips16_mark_labels ();
2888 mips_no_prev_insn (insns);
2891 /* Set up global variables for the start of a new macro. */
2896 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2897 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2898 && (prev_insn.insn_mo->pinfo
2899 & (INSN_UNCOND_BRANCH_DELAY
2900 | INSN_COND_BRANCH_DELAY
2901 | INSN_COND_BRANCH_LIKELY)) != 0);
2904 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2905 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2906 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2909 macro_warning (relax_substateT subtype)
2911 if (subtype & RELAX_DELAY_SLOT)
2912 return _("Macro instruction expanded into multiple instructions"
2913 " in a branch delay slot");
2914 else if (subtype & RELAX_NOMACRO)
2915 return _("Macro instruction expanded into multiple instructions");
2920 /* Finish up a macro. Emit warnings as appropriate. */
2925 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2927 relax_substateT subtype;
2929 /* Set up the relaxation warning flags. */
2931 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2932 subtype |= RELAX_SECOND_LONGER;
2933 if (mips_opts.warn_about_macros)
2934 subtype |= RELAX_NOMACRO;
2935 if (mips_macro_warning.delay_slot_p)
2936 subtype |= RELAX_DELAY_SLOT;
2938 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2940 /* Either the macro has a single implementation or both
2941 implementations are longer than 4 bytes. Emit the
2943 const char *msg = macro_warning (subtype);
2949 /* One implementation might need a warning but the other
2950 definitely doesn't. */
2951 mips_macro_warning.first_frag->fr_subtype |= subtype;
2956 /* Build an instruction created by a macro expansion. This is passed
2957 a pointer to the count of instructions created so far, an
2958 expression, the name of the instruction to build, an operand format
2959 string, and corresponding arguments. */
2962 macro_build (char *place ATTRIBUTE_UNUSED, int *counter,
2963 expressionS *ep, const char *name, const char *fmt, ...)
2965 struct mips_cl_insn insn;
2966 bfd_reloc_code_real_type r[3];
2969 va_start (args, fmt);
2971 if (mips_opts.mips16)
2973 mips16_macro_build (counter, ep, name, fmt, args);
2978 r[0] = BFD_RELOC_UNUSED;
2979 r[1] = BFD_RELOC_UNUSED;
2980 r[2] = BFD_RELOC_UNUSED;
2981 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2982 assert (insn.insn_mo);
2983 assert (strcmp (name, insn.insn_mo->name) == 0);
2985 /* Search until we get a match for NAME. */
2988 /* It is assumed here that macros will never generate
2989 MDMX or MIPS-3D instructions. */
2990 if (strcmp (fmt, insn.insn_mo->args) == 0
2991 && insn.insn_mo->pinfo != INSN_MACRO
2992 && OPCODE_IS_MEMBER (insn.insn_mo,
2994 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2996 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3000 assert (insn.insn_mo->name);
3001 assert (strcmp (name, insn.insn_mo->name) == 0);
3004 insn.insn_opcode = insn.insn_mo->match;
3022 insn.insn_opcode |= (va_arg (args, int)
3023 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3028 /* Note that in the macro case, these arguments are already
3029 in MSB form. (When handling the instruction in the
3030 non-macro case, these arguments are sizes from which
3031 MSB values must be calculated.) */
3032 insn.insn_opcode |= (va_arg (args, int)
3033 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3039 /* Note that in the macro case, these arguments are already
3040 in MSBD form. (When handling the instruction in the
3041 non-macro case, these arguments are sizes from which
3042 MSBD values must be calculated.) */
3043 insn.insn_opcode |= (va_arg (args, int)
3044 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3055 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3059 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3064 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3070 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3075 int tmp = va_arg (args, int);
3077 insn.insn_opcode |= tmp << OP_SH_RT;
3078 insn.insn_opcode |= tmp << OP_SH_RD;
3084 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3091 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3095 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3099 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3103 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3107 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3114 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3120 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3121 assert (*r == BFD_RELOC_GPREL16
3122 || *r == BFD_RELOC_MIPS_LITERAL
3123 || *r == BFD_RELOC_MIPS_HIGHER
3124 || *r == BFD_RELOC_HI16_S
3125 || *r == BFD_RELOC_LO16
3126 || *r == BFD_RELOC_MIPS_GOT16
3127 || *r == BFD_RELOC_MIPS_CALL16
3128 || *r == BFD_RELOC_MIPS_GOT_DISP
3129 || *r == BFD_RELOC_MIPS_GOT_PAGE
3130 || *r == BFD_RELOC_MIPS_GOT_OFST
3131 || *r == BFD_RELOC_MIPS_GOT_LO16
3132 || *r == BFD_RELOC_MIPS_CALL_LO16
3133 || (ep->X_op == O_subtract
3134 && *r == BFD_RELOC_PCREL_LO16));
3138 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3140 && (ep->X_op == O_constant
3141 || (ep->X_op == O_symbol
3142 && (*r == BFD_RELOC_MIPS_HIGHEST
3143 || *r == BFD_RELOC_HI16_S
3144 || *r == BFD_RELOC_HI16
3145 || *r == BFD_RELOC_GPREL16
3146 || *r == BFD_RELOC_MIPS_GOT_HI16
3147 || *r == BFD_RELOC_MIPS_CALL_HI16))
3148 || (ep->X_op == O_subtract
3149 && *r == BFD_RELOC_PCREL_HI16_S)));
3153 assert (ep != NULL);
3155 * This allows macro() to pass an immediate expression for
3156 * creating short branches without creating a symbol.
3157 * Note that the expression still might come from the assembly
3158 * input, in which case the value is not checked for range nor
3159 * is a relocation entry generated (yuck).
3161 if (ep->X_op == O_constant)
3163 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3167 *r = BFD_RELOC_16_PCREL_S2;
3171 assert (ep != NULL);
3172 *r = BFD_RELOC_MIPS_JMP;
3176 insn.insn_opcode |= va_arg (args, unsigned long);
3185 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3187 append_insn (&insn, ep, r);
3191 mips16_macro_build (int *counter ATTRIBUTE_UNUSED,
3192 expressionS *ep, const char *name, const char *fmt,
3195 struct mips_cl_insn insn;
3196 bfd_reloc_code_real_type r[3]
3197 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3199 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3200 assert (insn.insn_mo);
3201 assert (strcmp (name, insn.insn_mo->name) == 0);
3203 while (strcmp (fmt, insn.insn_mo->args) != 0
3204 || insn.insn_mo->pinfo == INSN_MACRO)
3207 assert (insn.insn_mo->name);
3208 assert (strcmp (name, insn.insn_mo->name) == 0);
3211 insn.insn_opcode = insn.insn_mo->match;
3212 insn.use_extend = FALSE;
3231 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3236 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3240 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3244 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3254 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3261 regno = va_arg (args, int);
3262 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3263 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3284 assert (ep != NULL);
3286 if (ep->X_op != O_constant)
3287 *r = (int) BFD_RELOC_UNUSED + c;
3290 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3291 FALSE, &insn.insn_opcode, &insn.use_extend,
3294 *r = BFD_RELOC_UNUSED;
3300 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3307 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3309 append_insn (&insn, ep, r);
3313 * Generate a "jalr" instruction with a relocation hint to the called
3314 * function. This occurs in NewABI PIC code.
3317 macro_build_jalr (int icnt, expressionS *ep)
3326 macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3328 fix_new_exp (frag_now, f - frag_now->fr_literal,
3329 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3333 * Generate a "lui" instruction.
3336 macro_build_lui (char *place ATTRIBUTE_UNUSED, int *counter ATTRIBUTE_UNUSED,
3337 expressionS *ep, int regnum)
3339 expressionS high_expr;
3340 struct mips_cl_insn insn;
3341 bfd_reloc_code_real_type r[3]
3342 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3343 const char *name = "lui";
3344 const char *fmt = "t,u";
3346 assert (! mips_opts.mips16);
3350 if (high_expr.X_op == O_constant)
3352 /* we can compute the instruction now without a relocation entry */
3353 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3355 *r = BFD_RELOC_UNUSED;
3359 assert (ep->X_op == O_symbol);
3360 /* _gp_disp is a special case, used from s_cpload. */
3361 assert (mips_pic == NO_PIC
3363 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3364 *r = BFD_RELOC_HI16_S;
3367 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3368 assert (insn.insn_mo);
3369 assert (strcmp (name, insn.insn_mo->name) == 0);
3370 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3372 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3373 if (*r == BFD_RELOC_UNUSED)
3375 insn.insn_opcode |= high_expr.X_add_number;
3376 append_insn (&insn, NULL, r);
3379 append_insn (&insn, &high_expr, r);
3382 /* Generate a sequence of instructions to do a load or store from a constant
3383 offset off of a base register (breg) into/from a target register (treg),
3384 using AT if necessary. */
3386 macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
3387 const char *op, int treg, int breg, int dbl)
3389 assert (ep->X_op == O_constant);
3391 /* Sign-extending 32-bit constants makes their handling easier. */
3392 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3393 == ~((bfd_vma) 0x7fffffff)))
3395 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3396 as_bad (_("constant too large"));
3398 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3402 /* Right now, this routine can only handle signed 32-bit constants. */
3403 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3404 as_warn (_("operand overflow"));
3406 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3408 /* Signed 16-bit offset will fit in the op. Easy! */
3409 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3414 /* 32-bit offset, need multiple instructions and AT, like:
3415 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3416 addu $tempreg,$tempreg,$breg
3417 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3418 to handle the complete offset. */
3419 macro_build_lui (place, counter, ep, AT);
3422 macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
3426 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3430 as_warn (_("Macro used $at after \".set noat\""));
3435 * Generates code to set the $at register to true (one)
3436 * if reg is less than the immediate expression.
3439 set_at (int *counter, int reg, int unsignedp)
3441 if (imm_expr.X_op == O_constant
3442 && imm_expr.X_add_number >= -0x8000
3443 && imm_expr.X_add_number < 0x8000)
3444 macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
3445 "t,r,j", AT, reg, BFD_RELOC_LO16);
3448 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3449 macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
3450 "d,v,t", AT, reg, AT);
3455 normalize_constant_expr (expressionS *ex)
3457 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3458 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3462 /* Warn if an expression is not a constant. */
3465 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3467 if (ex->X_op == O_big)
3468 as_bad (_("unsupported large constant"));
3469 else if (ex->X_op != O_constant)
3470 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3472 normalize_constant_expr (ex);
3475 /* Count the leading zeroes by performing a binary chop. This is a
3476 bulky bit of source, but performance is a LOT better for the
3477 majority of values than a simple loop to count the bits:
3478 for (lcnt = 0; (lcnt < 32); lcnt++)
3479 if ((v) & (1 << (31 - lcnt)))
3481 However it is not code size friendly, and the gain will drop a bit
3482 on certain cached systems.
3484 #define COUNT_TOP_ZEROES(v) \
3485 (((v) & ~0xffff) == 0 \
3486 ? ((v) & ~0xff) == 0 \
3487 ? ((v) & ~0xf) == 0 \
3488 ? ((v) & ~0x3) == 0 \
3489 ? ((v) & ~0x1) == 0 \
3494 : ((v) & ~0x7) == 0 \
3497 : ((v) & ~0x3f) == 0 \
3498 ? ((v) & ~0x1f) == 0 \
3501 : ((v) & ~0x7f) == 0 \
3504 : ((v) & ~0xfff) == 0 \
3505 ? ((v) & ~0x3ff) == 0 \
3506 ? ((v) & ~0x1ff) == 0 \
3509 : ((v) & ~0x7ff) == 0 \
3512 : ((v) & ~0x3fff) == 0 \
3513 ? ((v) & ~0x1fff) == 0 \
3516 : ((v) & ~0x7fff) == 0 \
3519 : ((v) & ~0xffffff) == 0 \
3520 ? ((v) & ~0xfffff) == 0 \
3521 ? ((v) & ~0x3ffff) == 0 \
3522 ? ((v) & ~0x1ffff) == 0 \
3525 : ((v) & ~0x7ffff) == 0 \
3528 : ((v) & ~0x3fffff) == 0 \
3529 ? ((v) & ~0x1fffff) == 0 \
3532 : ((v) & ~0x7fffff) == 0 \
3535 : ((v) & ~0xfffffff) == 0 \
3536 ? ((v) & ~0x3ffffff) == 0 \
3537 ? ((v) & ~0x1ffffff) == 0 \
3540 : ((v) & ~0x7ffffff) == 0 \
3543 : ((v) & ~0x3fffffff) == 0 \
3544 ? ((v) & ~0x1fffffff) == 0 \
3547 : ((v) & ~0x7fffffff) == 0 \
3552 * This routine generates the least number of instructions necessary to load
3553 * an absolute expression value into a register.
3556 load_register (int *counter, int reg, expressionS *ep, int dbl)
3559 expressionS hi32, lo32;
3561 if (ep->X_op != O_big)
3563 assert (ep->X_op == O_constant);
3565 /* Sign-extending 32-bit constants makes their handling easier. */
3566 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3567 == ~((bfd_vma) 0x7fffffff)))
3569 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3570 as_bad (_("constant too large"));
3572 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3576 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3578 /* We can handle 16 bit signed values with an addiu to
3579 $zero. No need to ever use daddiu here, since $zero and
3580 the result are always correct in 32 bit mode. */
3581 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3585 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3587 /* We can handle 16 bit unsigned values with an ori to
3589 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
3593 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3595 /* 32 bit values require an lui. */
3596 macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3597 if ((ep->X_add_number & 0xffff) != 0)
3598 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
3604 /* The value is larger than 32 bits. */
3606 if (HAVE_32BIT_GPRS)
3608 as_bad (_("Number (0x%lx) larger than 32 bits"),
3609 (unsigned long) ep->X_add_number);
3610 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3615 if (ep->X_op != O_big)
3618 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3619 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3620 hi32.X_add_number &= 0xffffffff;
3622 lo32.X_add_number &= 0xffffffff;
3626 assert (ep->X_add_number > 2);
3627 if (ep->X_add_number == 3)
3628 generic_bignum[3] = 0;
3629 else if (ep->X_add_number > 4)
3630 as_bad (_("Number larger than 64 bits"));
3631 lo32.X_op = O_constant;
3632 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3633 hi32.X_op = O_constant;
3634 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3637 if (hi32.X_add_number == 0)
3642 unsigned long hi, lo;
3644 if (hi32.X_add_number == (offsetT) 0xffffffff)
3646 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3648 macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
3652 if (lo32.X_add_number & 0x80000000)
3654 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3656 if (lo32.X_add_number & 0xffff)
3657 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
3663 /* Check for 16bit shifted constant. We know that hi32 is
3664 non-zero, so start the mask on the first bit of the hi32
3669 unsigned long himask, lomask;
3673 himask = 0xffff >> (32 - shift);
3674 lomask = (0xffff << shift) & 0xffffffff;
3678 himask = 0xffff << (shift - 32);
3681 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3682 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3686 tmp.X_op = O_constant;
3688 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3689 | (lo32.X_add_number >> shift));
3691 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3692 macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
3694 macro_build (NULL, counter, NULL,
3695 (shift >= 32) ? "dsll32" : "dsll",
3697 (shift >= 32) ? shift - 32 : shift);
3702 while (shift <= (64 - 16));
3704 /* Find the bit number of the lowest one bit, and store the
3705 shifted value in hi/lo. */
3706 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3707 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3711 while ((lo & 1) == 0)
3716 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3722 while ((hi & 1) == 0)
3731 /* Optimize if the shifted value is a (power of 2) - 1. */
3732 if ((hi == 0 && ((lo + 1) & lo) == 0)
3733 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3735 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3740 /* This instruction will set the register to be all
3742 tmp.X_op = O_constant;
3743 tmp.X_add_number = (offsetT) -1;
3744 macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
3749 macro_build (NULL, counter, NULL,
3750 (bit >= 32) ? "dsll32" : "dsll",
3752 (bit >= 32) ? bit - 32 : bit);
3754 macro_build (NULL, counter, NULL,
3755 (shift >= 32) ? "dsrl32" : "dsrl",
3757 (shift >= 32) ? shift - 32 : shift);
3762 /* Sign extend hi32 before calling load_register, because we can
3763 generally get better code when we load a sign extended value. */
3764 if ((hi32.X_add_number & 0x80000000) != 0)
3765 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3766 load_register (counter, reg, &hi32, 0);
3769 if ((lo32.X_add_number & 0xffff0000) == 0)
3773 macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
3781 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3783 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3785 macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
3791 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
3795 mid16.X_add_number >>= 16;
3796 macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
3798 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3801 if ((lo32.X_add_number & 0xffff) != 0)
3802 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3806 /* Load an address into a register. */
3809 load_address (int *counter, int reg, expressionS *ep, int *used_at)
3813 if (ep->X_op != O_constant
3814 && ep->X_op != O_symbol)
3816 as_bad (_("expression too complex"));
3817 ep->X_op = O_constant;
3820 if (ep->X_op == O_constant)
3822 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3826 if (mips_pic == NO_PIC)
3828 /* If this is a reference to a GP relative symbol, we want
3829 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3831 lui $reg,<sym> (BFD_RELOC_HI16_S)
3832 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3833 If we have an addend, we always use the latter form.
3835 With 64bit address space and a usable $at we want
3836 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3837 lui $at,<sym> (BFD_RELOC_HI16_S)
3838 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3839 daddiu $at,<sym> (BFD_RELOC_LO16)
3843 If $at is already in use, we use a path which is suboptimal
3844 on superscalar processors.
3845 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3846 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3848 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3850 daddiu $reg,<sym> (BFD_RELOC_LO16)
3852 if (HAVE_64BIT_ADDRESSES)
3854 /* We don't do GP optimization for now because RELAX_ENCODE can't
3855 hold the data for such large chunks. */
3857 if (*used_at == 0 && ! mips_opts.noat)
3859 macro_build (p, counter, ep, "lui", "t,u",
3860 reg, BFD_RELOC_MIPS_HIGHEST);
3861 macro_build (p, counter, ep, "lui", "t,u",
3862 AT, BFD_RELOC_HI16_S);
3863 macro_build (p, counter, ep, "daddiu", "t,r,j",
3864 reg, reg, BFD_RELOC_MIPS_HIGHER);
3865 macro_build (p, counter, ep, "daddiu", "t,r,j",
3866 AT, AT, BFD_RELOC_LO16);
3867 macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
3868 macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
3873 macro_build (p, counter, ep, "lui", "t,u",
3874 reg, BFD_RELOC_MIPS_HIGHEST);
3875 macro_build (p, counter, ep, "daddiu", "t,r,j",
3876 reg, reg, BFD_RELOC_MIPS_HIGHER);
3877 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3878 macro_build (p, counter, ep, "daddiu", "t,r,j",
3879 reg, reg, BFD_RELOC_HI16_S);
3880 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3881 macro_build (p, counter, ep, "daddiu", "t,r,j",
3882 reg, reg, BFD_RELOC_LO16);
3887 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3888 && ! nopic_need_relax (ep->X_add_symbol, 1))
3890 relax_start (ep->X_add_symbol);
3891 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3892 mips_gp_register, BFD_RELOC_GPREL16);
3895 macro_build_lui (p, counter, ep, reg);
3896 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3898 if (mips_relax.sequence)
3902 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3906 /* If this is a reference to an external symbol, we want
3907 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3909 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3911 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3912 If there is a constant, it must be added in after.
3914 If we have NewABI, we want
3915 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3916 unless we're referencing a global symbol with a non-zero
3917 offset, in which case cst must be added separately. */
3920 if (ep->X_add_number)
3922 ex.X_add_number = ep->X_add_number;
3923 ep->X_add_number = 0;
3924 relax_start (ep->X_add_symbol);
3925 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
3926 reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3927 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3928 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3929 ex.X_op = O_constant;
3930 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3931 reg, reg, BFD_RELOC_LO16);
3932 ep->X_add_number = ex.X_add_number;
3935 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3936 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3937 if (mips_relax.sequence)
3942 ex.X_add_number = ep->X_add_number;
3943 ep->X_add_number = 0;
3944 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3945 BFD_RELOC_MIPS_GOT16,
3947 macro_build (NULL, counter, NULL, "nop", "");
3948 relax_start (ep->X_add_symbol);
3950 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3954 if (ex.X_add_number != 0)
3956 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3957 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3958 ex.X_op = O_constant;
3959 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3960 reg, reg, BFD_RELOC_LO16);
3964 else if (mips_pic == SVR4_PIC)
3968 /* This is the large GOT case. If this is a reference to an
3969 external symbol, we want
3970 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3972 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3974 Otherwise, for a reference to a local symbol in old ABI, we want
3975 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3977 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3978 If there is a constant, it must be added in after.
3980 In the NewABI, for local symbols, with or without offsets, we want:
3981 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3982 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3986 ex.X_add_number = ep->X_add_number;
3987 ep->X_add_number = 0;
3988 relax_start (ep->X_add_symbol);
3989 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3990 BFD_RELOC_MIPS_GOT_HI16);
3991 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3992 reg, mips_gp_register);
3993 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3994 BFD_RELOC_MIPS_GOT_LO16, reg);
3995 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3996 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3997 else if (ex.X_add_number)
3999 ex.X_op = O_constant;
4000 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
4001 reg, reg, BFD_RELOC_LO16);
4004 ep->X_add_number = ex.X_add_number;
4006 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4007 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4008 macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4009 reg, BFD_RELOC_MIPS_GOT_OFST);
4014 ex.X_add_number = ep->X_add_number;
4015 ep->X_add_number = 0;
4016 relax_start (ep->X_add_symbol);
4017 macro_build (NULL, counter, ep, "lui", "t,u", reg,
4018 BFD_RELOC_MIPS_GOT_HI16);
4019 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
4020 reg, mips_gp_register);
4021 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4022 BFD_RELOC_MIPS_GOT_LO16, reg);
4024 if (reg_needs_delay (mips_gp_register))
4026 /* We need a nop before loading from $gp. This special
4027 check is required because the lui which starts the main
4028 instruction stream does not refer to $gp, and so will not
4029 insert the nop which may be required. */
4030 macro_build (p, counter, NULL, "nop", "");
4032 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4033 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4034 macro_build (p, counter, NULL, "nop", "");
4035 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4039 if (ex.X_add_number != 0)
4041 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4042 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4043 ex.X_op = O_constant;
4044 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
4045 reg, reg, BFD_RELOC_LO16);
4049 else if (mips_pic == EMBEDDED_PIC)
4052 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4054 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4055 mips_gp_register, BFD_RELOC_GPREL16);
4061 /* Move the contents of register SOURCE into register DEST. */
4064 move_register (int *counter, int dest, int source)
4066 macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
4067 "d,v,t", dest, source, 0);
4070 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4071 LOCAL is the sum of a symbol and a 16-bit displacement. The two
4074 Global symbol Local sybmol
4075 ------------- ------------
4076 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4078 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4080 load_got_offset emits the first instruction and add_got_offset
4081 emits the second. */
4084 load_got_offset (int *counter, int dest, expressionS *local)
4089 global.X_add_number = 0;
4091 relax_start (local->X_add_symbol);
4092 macro_build (NULL, counter, &global, ADDRESS_LOAD_INSN, "t,o(b)",
4093 dest, BFD_RELOC_MIPS_GOT16, mips_gp_register);
4095 macro_build (NULL, counter, local, ADDRESS_LOAD_INSN, "t,o(b)",
4096 dest, BFD_RELOC_MIPS_GOT16, mips_gp_register);
4101 add_got_offset (int *counter, int dest, expressionS *local)
4105 global.X_op = O_constant;
4106 global.X_op_symbol = NULL;
4107 global.X_add_symbol = NULL;
4108 global.X_add_number = local->X_add_number;
4110 relax_start (local->X_add_symbol);
4111 macro_build (NULL, counter, &global, ADDRESS_ADDI_INSN, "t,r,j",
4112 dest, dest, BFD_RELOC_LO16);
4114 macro_build (NULL, counter, local, ADDRESS_ADDI_INSN, "t,r,j",
4115 dest, dest, BFD_RELOC_LO16);
4121 * This routine implements the seemingly endless macro or synthesized
4122 * instructions and addressing modes in the mips assembly language. Many
4123 * of these macros are simple and are similar to each other. These could
4124 * probably be handled by some kind of table or grammar approach instead of
4125 * this verbose method. Others are not simple macros but are more like
4126 * optimizing code generation.
4127 * One interesting optimization is when several store macros appear
4128 * consecutively that would load AT with the upper half of the same address.
4129 * The ensuing load upper instructions are ommited. This implies some kind
4130 * of global optimization. We currently only optimize within a single macro.
4131 * For many of the load and store macros if the address is specified as a
4132 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4133 * first load register 'at' with zero and use it as the base register. The
4134 * mips assembler simply uses register $zero. Just one tiny optimization
4138 macro (struct mips_cl_insn *ip)
4140 register int treg, sreg, dreg, breg;
4157 bfd_reloc_code_real_type r;
4158 int hold_mips_optimize;
4160 assert (! mips_opts.mips16);
4162 treg = (ip->insn_opcode >> 16) & 0x1f;
4163 dreg = (ip->insn_opcode >> 11) & 0x1f;
4164 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4165 mask = ip->insn_mo->mask;
4167 expr1.X_op = O_constant;
4168 expr1.X_op_symbol = NULL;
4169 expr1.X_add_symbol = NULL;
4170 expr1.X_add_number = 1;
4182 mips_emit_delays (TRUE);
4183 ++mips_opts.noreorder;
4184 mips_any_noreorder = 1;
4186 expr1.X_add_number = 8;
4187 macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4189 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4191 move_register (&icnt, dreg, sreg);
4192 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
4195 --mips_opts.noreorder;
4216 if (imm_expr.X_op == O_constant
4217 && imm_expr.X_add_number >= -0x8000
4218 && imm_expr.X_add_number < 0x8000)
4220 macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4224 load_register (&icnt, AT, &imm_expr, dbl);
4225 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4244 if (imm_expr.X_op == O_constant
4245 && imm_expr.X_add_number >= 0
4246 && imm_expr.X_add_number < 0x10000)
4248 if (mask != M_NOR_I)
4249 macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
4253 macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
4255 macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
4260 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4261 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4278 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4280 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
4283 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4284 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4292 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4298 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4302 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4303 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4310 /* check for > max integer */
4311 maxnum = 0x7fffffff;
4312 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4319 if (imm_expr.X_op == O_constant
4320 && imm_expr.X_add_number >= maxnum
4321 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4324 /* result is always false */
4326 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4328 macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
4331 if (imm_expr.X_op != O_constant)
4332 as_bad (_("Unsupported large constant"));
4333 ++imm_expr.X_add_number;
4337 if (mask == M_BGEL_I)
4339 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4341 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4345 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4347 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4351 maxnum = 0x7fffffff;
4352 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4359 maxnum = - maxnum - 1;
4360 if (imm_expr.X_op == O_constant
4361 && imm_expr.X_add_number <= maxnum
4362 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4365 /* result is always true */
4366 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4367 macro_build (NULL, &icnt, &offset_expr, "b", "p");
4370 set_at (&icnt, sreg, 0);
4371 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4382 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4386 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4387 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4396 && imm_expr.X_op == O_constant
4397 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4399 if (imm_expr.X_op != O_constant)
4400 as_bad (_("Unsupported large constant"));
4401 ++imm_expr.X_add_number;
4405 if (mask == M_BGEUL_I)
4407 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4409 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4411 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4415 set_at (&icnt, sreg, 1);
4416 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4425 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4431 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4435 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4436 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4445 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4451 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4452 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4461 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4467 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4471 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4472 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4479 maxnum = 0x7fffffff;
4480 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4487 if (imm_expr.X_op == O_constant
4488 && imm_expr.X_add_number >= maxnum
4489 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4491 if (imm_expr.X_op != O_constant)
4492 as_bad (_("Unsupported large constant"));
4493 ++imm_expr.X_add_number;
4497 if (mask == M_BLTL_I)
4499 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4501 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4505 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4507 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4511 set_at (&icnt, sreg, 0);
4512 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4521 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4527 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4528 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4537 && imm_expr.X_op == O_constant
4538 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4540 if (imm_expr.X_op != O_constant)
4541 as_bad (_("Unsupported large constant"));
4542 ++imm_expr.X_add_number;
4546 if (mask == M_BLTUL_I)
4548 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4550 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4552 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4556 set_at (&icnt, sreg, 1);
4557 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4566 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4572 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4576 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4577 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4588 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4592 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4593 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4602 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4604 as_bad (_("Unsupported large constant"));
4609 pos = (unsigned long) imm_expr.X_add_number;
4610 size = (unsigned long) imm2_expr.X_add_number;
4615 as_bad (_("Improper position (%lu)"), pos);
4618 if (size == 0 || size > 64
4619 || (pos + size - 1) > 63)
4621 as_bad (_("Improper extract size (%lu, position %lu)"),
4626 if (size <= 32 && pos < 32)
4631 else if (size <= 32)
4641 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4642 fmt, treg, sreg, pos, size - 1);
4651 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4653 as_bad (_("Unsupported large constant"));
4658 pos = (unsigned long) imm_expr.X_add_number;
4659 size = (unsigned long) imm2_expr.X_add_number;
4664 as_bad (_("Improper position (%lu)"), pos);
4667 if (size == 0 || size > 64
4668 || (pos + size - 1) > 63)
4670 as_bad (_("Improper insert size (%lu, position %lu)"),
4675 if (pos < 32 && (pos + size - 1) < 32)
4690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4691 fmt, treg, sreg, pos, pos + size - 1);
4707 as_warn (_("Divide by zero."));
4709 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4711 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4715 mips_emit_delays (TRUE);
4716 ++mips_opts.noreorder;
4717 mips_any_noreorder = 1;
4720 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4721 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4726 expr1.X_add_number = 8;
4727 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4728 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4730 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4732 expr1.X_add_number = -1;
4733 macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
4734 AT, 0, BFD_RELOC_LO16);
4735 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4736 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4739 expr1.X_add_number = 1;
4740 macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4742 macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
4746 expr1.X_add_number = 0x80000000;
4747 macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
4752 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
4753 /* We want to close the noreorder block as soon as possible, so
4754 that later insns are available for delay slot filling. */
4755 --mips_opts.noreorder;
4759 expr1.X_add_number = 8;
4760 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4761 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4763 /* We want to close the noreorder block as soon as possible, so
4764 that later insns are available for delay slot filling. */
4765 --mips_opts.noreorder;
4767 macro_build (NULL, &icnt, NULL, "break", "c", 6);
4769 macro_build (NULL, &icnt, NULL, s, "d", dreg);
4808 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4810 as_warn (_("Divide by zero."));
4812 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4814 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4817 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4819 if (strcmp (s2, "mflo") == 0)
4820 move_register (&icnt, dreg, sreg);
4822 move_register (&icnt, dreg, 0);
4825 if (imm_expr.X_op == O_constant
4826 && imm_expr.X_add_number == -1
4827 && s[strlen (s) - 1] != 'u')
4829 if (strcmp (s2, "mflo") == 0)
4831 macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
4835 move_register (&icnt, dreg, 0);
4839 load_register (&icnt, AT, &imm_expr, dbl);
4840 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
4841 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4860 mips_emit_delays (TRUE);
4861 ++mips_opts.noreorder;
4862 mips_any_noreorder = 1;
4865 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4866 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4867 /* We want to close the noreorder block as soon as possible, so
4868 that later insns are available for delay slot filling. */
4869 --mips_opts.noreorder;
4873 expr1.X_add_number = 8;
4874 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4875 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4877 /* We want to close the noreorder block as soon as possible, so
4878 that later insns are available for delay slot filling. */
4879 --mips_opts.noreorder;
4880 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4882 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4894 /* Load the address of a symbol into a register. If breg is not
4895 zero, we then add a base register to it. */
4897 if (dbl && HAVE_32BIT_GPRS)
4898 as_warn (_("dla used to load 32-bit register"));
4900 if (! dbl && HAVE_64BIT_OBJECTS)
4901 as_warn (_("la used to load 64-bit address"));
4903 if (offset_expr.X_op == O_constant
4904 && offset_expr.X_add_number >= -0x8000
4905 && offset_expr.X_add_number < 0x8000)
4907 macro_build (NULL, &icnt, &offset_expr,
4908 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4909 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4924 /* When generating embedded PIC code, we permit expressions of
4927 la $treg,foo-bar($breg)
4928 where bar is an address in the current section. These are used
4929 when getting the addresses of functions. We don't permit
4930 X_add_number to be non-zero, because if the symbol is
4931 external the relaxing code needs to know that any addend is
4932 purely the offset to X_op_symbol. */
4933 if (mips_pic == EMBEDDED_PIC
4934 && offset_expr.X_op == O_subtract
4935 && (symbol_constant_p (offset_expr.X_op_symbol)
4936 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4937 : (symbol_equated_p (offset_expr.X_op_symbol)
4939 (symbol_get_value_expression (offset_expr.X_op_symbol)
4942 && (offset_expr.X_add_number == 0
4943 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4949 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4950 BFD_RELOC_PCREL_HI16_S);
4954 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4955 BFD_RELOC_PCREL_HI16_S);
4956 macro_build (NULL, &icnt, NULL,
4957 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4958 "d,v,t", tempreg, tempreg, breg);
4960 macro_build (NULL, &icnt, &offset_expr,
4961 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4962 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4968 if (offset_expr.X_op != O_symbol
4969 && offset_expr.X_op != O_constant)
4971 as_bad (_("expression too complex"));
4972 offset_expr.X_op = O_constant;
4975 if (offset_expr.X_op == O_constant)
4976 load_register (&icnt, tempreg, &offset_expr,
4977 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4978 ? (dbl || HAVE_64BIT_ADDRESSES)
4979 : HAVE_64BIT_ADDRESSES));
4980 else if (mips_pic == NO_PIC)
4982 /* If this is a reference to a GP relative symbol, we want
4983 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4985 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4986 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4987 If we have a constant, we need two instructions anyhow,
4988 so we may as well always use the latter form.
4990 With 64bit address space and a usable $at we want
4991 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4992 lui $at,<sym> (BFD_RELOC_HI16_S)
4993 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4994 daddiu $at,<sym> (BFD_RELOC_LO16)
4996 daddu $tempreg,$tempreg,$at
4998 If $at is already in use, we use a path which is suboptimal
4999 on superscalar processors.
5000 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5001 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5003 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5005 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5008 if (HAVE_64BIT_ADDRESSES)
5010 /* We don't do GP optimization for now because RELAX_ENCODE can't
5011 hold the data for such large chunks. */
5013 if (used_at == 0 && ! mips_opts.noat)
5015 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5016 tempreg, BFD_RELOC_MIPS_HIGHEST);
5017 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5018 AT, BFD_RELOC_HI16_S);
5019 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5020 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5021 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5022 AT, AT, BFD_RELOC_LO16);
5023 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
5024 tempreg, tempreg, 0);
5025 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5026 tempreg, tempreg, AT);
5031 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5032 tempreg, BFD_RELOC_MIPS_HIGHEST);
5033 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5034 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5035 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
5036 tempreg, tempreg, 16);
5037 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5038 tempreg, tempreg, BFD_RELOC_HI16_S);
5039 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
5040 tempreg, tempreg, 16);
5041 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5042 tempreg, tempreg, BFD_RELOC_LO16);
5047 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5048 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
5050 relax_start (offset_expr.X_add_symbol);
5051 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5052 "t,r,j", tempreg, mips_gp_register,
5056 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5057 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5058 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5059 if (mips_relax.sequence)
5063 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
5065 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5067 /* If this is a reference to an external symbol, and there
5068 is no constant, we want
5069 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5070 or for lca or if tempreg is PIC_CALL_REG
5071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5072 For a local symbol, we want
5073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5075 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5077 If we have a small constant, and this is a reference to
5078 an external symbol, we want
5079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5081 addiu $tempreg,$tempreg,<constant>
5082 For a local symbol, we want the same instruction
5083 sequence, but we output a BFD_RELOC_LO16 reloc on the
5086 If we have a large constant, and this is a reference to
5087 an external symbol, we want
5088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5089 lui $at,<hiconstant>
5090 addiu $at,$at,<loconstant>
5091 addu $tempreg,$tempreg,$at
5092 For a local symbol, we want the same instruction
5093 sequence, but we output a BFD_RELOC_LO16 reloc on the
5097 if (offset_expr.X_add_number == 0)
5101 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5102 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5104 relax_start (offset_expr.X_add_symbol);
5105 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5106 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
5109 /* We're going to put in an addu instruction using
5110 tempreg, so we may as well insert the nop right
5112 macro_build (NULL, &icnt, NULL, "nop", "");
5115 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5116 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT16,
5118 macro_build (p, &icnt, NULL, "nop", "");
5119 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5120 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5122 /* FIXME: If breg == 0, and the next instruction uses
5123 $tempreg, then if this variant case is used an extra
5124 nop will be generated. */
5126 else if (offset_expr.X_add_number >= -0x8000
5127 && offset_expr.X_add_number < 0x8000)
5129 load_got_offset (&icnt, tempreg, &offset_expr);
5130 macro_build (NULL, &icnt, NULL, "nop", "");
5131 add_got_offset (&icnt, tempreg, &offset_expr);
5137 expr1.X_add_number = offset_expr.X_add_number;
5138 offset_expr.X_add_number =
5139 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5140 load_got_offset (&icnt, tempreg, &offset_expr);
5141 /* If we are going to add in a base register, and the
5142 target register and the base register are the same,
5143 then we are using AT as a temporary register. Since
5144 we want to load the constant into AT, we add our
5145 current AT (from the global offset table) and the
5146 register into the register now, and pretend we were
5147 not using a base register. */
5152 macro_build (NULL, &icnt, NULL, "nop", "");
5153 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5160 /* Set mips_optimize around the lui instruction to avoid
5161 inserting an unnecessary nop after the lw. */
5162 hold_mips_optimize = mips_optimize;
5164 macro_build_lui (NULL, &icnt, &expr1, AT);
5165 mips_optimize = hold_mips_optimize;
5167 add_got_offset (&icnt, AT, &offset_expr);
5168 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5169 tempreg, tempreg, AT);
5173 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5178 /* If this is a reference to an external, and there is no
5179 constant, or local symbol (*), with or without a
5181 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5182 or for lca or if tempreg is PIC_CALL_REG
5183 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5185 If we have a small constant, and this is a reference to
5186 an external symbol, we want
5187 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5188 addiu $tempreg,$tempreg,<constant>
5190 If we have a large constant, and this is a reference to
5191 an external symbol, we want
5192 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5193 lui $at,<hiconstant>
5194 addiu $at,$at,<loconstant>
5195 addu $tempreg,$tempreg,$at
5197 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5198 local symbols, even though it introduces an additional
5201 if (offset_expr.X_add_number)
5203 expr1.X_add_number = offset_expr.X_add_number;
5204 offset_expr.X_add_number = 0;
5206 relax_start (offset_expr.X_add_symbol);
5207 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5208 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5211 if (expr1.X_add_number >= -0x8000
5212 && expr1.X_add_number < 0x8000)
5214 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5215 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5217 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5221 /* If we are going to add in a base register, and the
5222 target register and the base register are the same,
5223 then we are using AT as a temporary register. Since
5224 we want to load the constant into AT, we add our
5225 current AT (from the global offset table) and the
5226 register into the register now, and pretend we were
5227 not using a base register. */
5232 assert (tempreg == AT);
5233 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN,
5234 "d,v,t", treg, AT, breg);
5239 macro_build_lui (NULL, &icnt, &expr1, AT);
5240 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5241 "t,r,j", AT, AT, BFD_RELOC_LO16);
5242 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5248 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5251 offset_expr.X_add_number = expr1.X_add_number;
5253 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5254 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5258 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5259 treg, tempreg, breg);
5265 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5267 relax_start (offset_expr.X_add_symbol);
5268 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5269 "t,o(b)", tempreg, BFD_RELOC_MIPS_CALL16,
5272 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5273 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5279 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5280 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5284 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5288 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5289 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5290 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5292 /* This is the large GOT case. If this is a reference to an
5293 external symbol, and there is no constant, we want
5294 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5295 addu $tempreg,$tempreg,$gp
5296 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5297 or for lca or if tempreg is PIC_CALL_REG
5298 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5299 addu $tempreg,$tempreg,$gp
5300 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5301 For a local symbol, we want
5302 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5304 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5306 If we have a small constant, and this is a reference to
5307 an external symbol, we want
5308 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5309 addu $tempreg,$tempreg,$gp
5310 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5312 addiu $tempreg,$tempreg,<constant>
5313 For a local symbol, we want
5314 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5316 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5318 If we have a large constant, and this is a reference to
5319 an external symbol, we want
5320 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5321 addu $tempreg,$tempreg,$gp
5322 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5323 lui $at,<hiconstant>
5324 addiu $at,$at,<loconstant>
5325 addu $tempreg,$tempreg,$at
5326 For a local symbol, we want
5327 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5328 lui $at,<hiconstant>
5329 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5330 addu $tempreg,$tempreg,$at
5333 expr1.X_add_number = offset_expr.X_add_number;
5334 offset_expr.X_add_number = 0;
5335 relax_start (offset_expr.X_add_symbol);
5336 if (reg_needs_delay (mips_gp_register))
5340 if (expr1.X_add_number == 0 && breg == 0
5341 && (call || tempreg == PIC_CALL_REG))
5343 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5344 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5346 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5347 tempreg, lui_reloc_type);
5348 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5349 tempreg, tempreg, mips_gp_register);
5350 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5351 tempreg, lw_reloc_type, tempreg);
5352 if (expr1.X_add_number == 0)
5360 /* We're going to put in an addu instruction using
5361 tempreg, so we may as well insert the nop right
5363 macro_build (NULL, &icnt, NULL, "nop", "");
5367 else if (expr1.X_add_number >= -0x8000
5368 && expr1.X_add_number < 0x8000)
5370 macro_build (NULL, &icnt, NULL, "nop", "");
5371 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5372 tempreg, tempreg, BFD_RELOC_LO16);
5378 /* If we are going to add in a base register, and the
5379 target register and the base register are the same,
5380 then we are using AT as a temporary register. Since
5381 we want to load the constant into AT, we add our
5382 current AT (from the global offset table) and the
5383 register into the register now, and pretend we were
5384 not using a base register. */
5392 assert (tempreg == AT);
5393 macro_build (NULL, &icnt, NULL, "nop", "");
5394 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5400 /* Set mips_optimize around the lui instruction to avoid
5401 inserting an unnecessary nop after the lw. */
5402 hold_mips_optimize = mips_optimize;
5404 macro_build_lui (NULL, &icnt, &expr1, AT);
5405 mips_optimize = hold_mips_optimize;
5407 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5408 AT, AT, BFD_RELOC_LO16);
5409 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5414 offset_expr.X_add_number =
5415 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5420 /* This is needed because this instruction uses $gp, but
5421 the first instruction on the main stream does not. */
5422 macro_build (p, &icnt, NULL, "nop", "");
5425 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5426 tempreg, local_reloc_type, mips_gp_register);
5427 if (expr1.X_add_number >= -0x8000
5428 && expr1.X_add_number < 0x8000)
5430 macro_build (p, &icnt, NULL, "nop", "");
5431 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5432 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5433 /* FIXME: If add_number is 0, and there was no base
5434 register, the external symbol case ended with a load,
5435 so if the symbol turns out to not be external, and
5436 the next instruction uses tempreg, an unnecessary nop
5437 will be inserted. */
5443 /* We must add in the base register now, as in the
5444 external symbol case. */
5445 assert (tempreg == AT);
5446 macro_build (p, &icnt, NULL, "nop", "");
5447 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5450 /* We set breg to 0 because we have arranged to add
5451 it in in both cases. */
5455 macro_build_lui (p, &icnt, &expr1, AT);
5456 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5457 AT, AT, BFD_RELOC_LO16);
5458 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5459 tempreg, tempreg, AT);
5463 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5466 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5467 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5470 /* This is the large GOT case. If this is a reference to an
5471 external symbol, and there is no constant, we want
5472 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5473 add $tempreg,$tempreg,$gp
5474 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5475 or for lca or if tempreg is PIC_CALL_REG
5476 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5477 add $tempreg,$tempreg,$gp
5478 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5480 If we have a small constant, and this is a reference to
5481 an external symbol, we want
5482 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5483 add $tempreg,$tempreg,$gp
5484 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5485 addi $tempreg,$tempreg,<constant>
5487 If we have a large constant, and this is a reference to
5488 an external symbol, we want
5489 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5490 addu $tempreg,$tempreg,$gp
5491 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5492 lui $at,<hiconstant>
5493 addi $at,$at,<loconstant>
5494 add $tempreg,$tempreg,$at
5496 If we have NewABI, and we know it's a local symbol, we want
5497 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5498 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5499 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5501 relax_start (offset_expr.X_add_symbol);
5503 expr1.X_add_number = offset_expr.X_add_number;
5504 offset_expr.X_add_number = 0;
5506 if (expr1.X_add_number == 0 && breg == 0
5507 && (call || tempreg == PIC_CALL_REG))
5509 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5510 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5512 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5513 tempreg, lui_reloc_type);
5514 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5515 tempreg, tempreg, mips_gp_register);
5516 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5517 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5519 if (expr1.X_add_number == 0)
5521 else if (expr1.X_add_number >= -0x8000
5522 && expr1.X_add_number < 0x8000)
5524 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5525 tempreg, tempreg, BFD_RELOC_LO16);
5527 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5531 /* If we are going to add in a base register, and the
5532 target register and the base register are the same,
5533 then we are using AT as a temporary register. Since
5534 we want to load the constant into AT, we add our
5535 current AT (from the global offset table) and the
5536 register into the register now, and pretend we were
5537 not using a base register. */
5542 assert (tempreg == AT);
5543 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5549 /* Set mips_optimize around the lui instruction to avoid
5550 inserting an unnecessary nop after the lw. */
5551 macro_build_lui (NULL, &icnt, &expr1, AT);
5552 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5553 "t,r,j", AT, AT, BFD_RELOC_LO16);
5554 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5560 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5563 offset_expr.X_add_number = expr1.X_add_number;
5564 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5565 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5566 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5567 tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
5570 macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5571 treg, tempreg, breg);
5577 else if (mips_pic == EMBEDDED_PIC)
5580 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5582 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5583 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5592 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5593 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5595 s = ADDRESS_ADD_INSN;
5597 macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
5606 /* The j instruction may not be used in PIC code, since it
5607 requires an absolute address. We convert it to a b
5609 if (mips_pic == NO_PIC)
5610 macro_build (NULL, &icnt, &offset_expr, "j", "a");
5612 macro_build (NULL, &icnt, &offset_expr, "b", "p");
5615 /* The jal instructions must be handled as macros because when
5616 generating PIC code they expand to multi-instruction
5617 sequences. Normally they are simple instructions. */
5622 if (mips_pic == NO_PIC
5623 || mips_pic == EMBEDDED_PIC)
5624 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5625 else if (mips_pic == SVR4_PIC)
5627 if (sreg != PIC_CALL_REG)
5628 as_warn (_("MIPS PIC call to register other than $25"));
5630 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5633 if (mips_cprestore_offset < 0)
5634 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5637 if (! mips_frame_reg_valid)
5639 as_warn (_("No .frame pseudo-op used in PIC code"));
5640 /* Quiet this warning. */
5641 mips_frame_reg_valid = 1;
5643 if (! mips_cprestore_valid)
5645 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5646 /* Quiet this warning. */
5647 mips_cprestore_valid = 1;
5649 expr1.X_add_number = mips_cprestore_offset;
5650 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5654 HAVE_64BIT_ADDRESSES);
5664 if (mips_pic == NO_PIC)
5665 macro_build (NULL, &icnt, &offset_expr, "jal", "a");
5666 else if (mips_pic == SVR4_PIC)
5670 /* If this is a reference to an external symbol, and we are
5671 using a small GOT, we want
5672 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5676 lw $gp,cprestore($sp)
5677 The cprestore value is set using the .cprestore
5678 pseudo-op. If we are using a big GOT, we want
5679 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5681 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5685 lw $gp,cprestore($sp)
5686 If the symbol is not external, we want
5687 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5689 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5692 lw $gp,cprestore($sp)
5694 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5695 sequences above, minus nops, unless the symbol is local,
5696 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5702 relax_start (offset_expr.X_add_symbol);
5703 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5704 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5707 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5708 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5714 relax_start (offset_expr.X_add_symbol);
5715 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5716 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5717 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5718 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5719 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5720 "t,o(b)", PIC_CALL_REG,
5721 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5723 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5724 "t,o(b)", PIC_CALL_REG,
5725 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5726 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5727 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5728 BFD_RELOC_MIPS_GOT_OFST);
5732 macro_build_jalr (icnt, &offset_expr);
5736 relax_start (offset_expr.X_add_symbol);
5739 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5740 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5742 macro_build (NULL, &icnt, NULL, "nop", "");
5749 if (reg_needs_delay (mips_gp_register))
5753 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5754 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5755 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5756 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5757 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5758 "t,o(b)", PIC_CALL_REG,
5759 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5760 macro_build (NULL, &icnt, NULL, "nop", "");
5764 macro_build (p, &icnt, NULL, "nop", "");
5768 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5769 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5771 macro_build (p, &icnt, NULL, "nop", "");
5772 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5773 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5776 macro_build_jalr (icnt, &offset_expr);
5778 if (mips_cprestore_offset < 0)
5779 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5782 if (! mips_frame_reg_valid)
5784 as_warn (_("No .frame pseudo-op used in PIC code"));
5785 /* Quiet this warning. */
5786 mips_frame_reg_valid = 1;
5788 if (! mips_cprestore_valid)
5790 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5791 /* Quiet this warning. */
5792 mips_cprestore_valid = 1;
5794 if (mips_opts.noreorder)
5795 macro_build (NULL, &icnt, NULL, "nop", "");
5796 expr1.X_add_number = mips_cprestore_offset;
5797 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5801 HAVE_64BIT_ADDRESSES);
5805 else if (mips_pic == EMBEDDED_PIC)
5807 macro_build (NULL, &icnt, &offset_expr, "bal", "p");
5808 /* The linker may expand the call to a longer sequence which
5809 uses $at, so we must break rather than return. */
5834 /* Itbl support may require additional care here. */
5839 /* Itbl support may require additional care here. */
5844 /* Itbl support may require additional care here. */
5849 /* Itbl support may require additional care here. */
5861 if (mips_opts.arch == CPU_R4650)
5863 as_bad (_("opcode not supported on this processor"));
5867 /* Itbl support may require additional care here. */
5872 /* Itbl support may require additional care here. */
5877 /* Itbl support may require additional care here. */
5897 if (breg == treg || coproc || lr)
5919 /* Itbl support may require additional care here. */
5924 /* Itbl support may require additional care here. */
5929 /* Itbl support may require additional care here. */
5934 /* Itbl support may require additional care here. */
5950 if (mips_opts.arch == CPU_R4650)
5952 as_bad (_("opcode not supported on this processor"));
5957 /* Itbl support may require additional care here. */
5961 /* Itbl support may require additional care here. */
5966 /* Itbl support may require additional care here. */
5978 /* Itbl support may require additional care here. */
5979 if (mask == M_LWC1_AB
5980 || mask == M_SWC1_AB
5981 || mask == M_LDC1_AB
5982 || mask == M_SDC1_AB
5991 /* Sign-extending 32-bit constants makes their handling easier.
5992 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5994 if ((! HAVE_64BIT_ADDRESSES
5995 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5996 && (offset_expr.X_op == O_constant)
5997 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5998 == ~((bfd_vma) 0x7fffffff)))
6000 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
6001 as_bad (_("constant too large"));
6003 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
6004 ^ 0x80000000) - 0x80000000);
6007 /* For embedded PIC, we allow loads where the offset is calculated
6008 by subtracting a symbol in the current segment from an unknown
6009 symbol, relative to a base register, e.g.:
6010 <op> $treg, <sym>-<localsym>($breg)
6011 This is used by the compiler for switch statements. */
6012 if (mips_pic == EMBEDDED_PIC
6013 && offset_expr.X_op == O_subtract
6014 && (symbol_constant_p (offset_expr.X_op_symbol)
6015 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
6016 : (symbol_equated_p (offset_expr.X_op_symbol)
6018 (symbol_get_value_expression (offset_expr.X_op_symbol)
6022 && (offset_expr.X_add_number == 0
6023 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
6025 /* For this case, we output the instructions:
6026 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
6027 addiu $tempreg,$tempreg,$breg
6028 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
6029 If the relocation would fit entirely in 16 bits, it would be
6031 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
6032 instead, but that seems quite difficult. */
6033 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6034 BFD_RELOC_PCREL_HI16_S);
6035 macro_build (NULL, &icnt, NULL,
6036 ((bfd_arch_bits_per_address (stdoutput) == 32
6037 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
6038 ? "addu" : "daddu"),
6039 "d,v,t", tempreg, tempreg, breg);
6040 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6041 BFD_RELOC_PCREL_LO16, tempreg);
6047 if (offset_expr.X_op != O_constant
6048 && offset_expr.X_op != O_symbol)
6050 as_bad (_("expression too complex"));
6051 offset_expr.X_op = O_constant;
6054 /* A constant expression in PIC code can be handled just as it
6055 is in non PIC code. */
6056 if (mips_pic == NO_PIC
6057 || offset_expr.X_op == O_constant)
6061 /* If this is a reference to a GP relative symbol, and there
6062 is no base register, we want
6063 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6064 Otherwise, if there is no base register, we want
6065 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6066 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6067 If we have a constant, we need two instructions anyhow,
6068 so we always use the latter form.
6070 If we have a base register, and this is a reference to a
6071 GP relative symbol, we want
6072 addu $tempreg,$breg,$gp
6073 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6075 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6076 addu $tempreg,$tempreg,$breg
6077 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6078 With a constant we always use the latter case.
6080 With 64bit address space and no base register and $at usable,
6082 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6083 lui $at,<sym> (BFD_RELOC_HI16_S)
6084 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6087 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6088 If we have a base register, we want
6089 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6090 lui $at,<sym> (BFD_RELOC_HI16_S)
6091 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6095 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6097 Without $at we can't generate the optimal path for superscalar
6098 processors here since this would require two temporary registers.
6099 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6100 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6102 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6104 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6105 If we have a base register, we want
6106 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6107 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6109 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6111 daddu $tempreg,$tempreg,$breg
6112 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6114 If we have 64-bit addresses, as an optimization, for
6115 addresses which are 32-bit constants (e.g. kseg0/kseg1
6116 addresses) we fall back to the 32-bit address generation
6117 mechanism since it is more efficient. Note that due to
6118 the signed offset used by memory operations, the 32-bit
6119 range is shifted down by 32768 here. This code should
6120 probably attempt to generate 64-bit constants more
6121 efficiently in general.
6123 As an extension for architectures with 64-bit registers,
6124 we don't truncate 64-bit addresses given as literal
6125 constants down to 32 bits, to support existing practice
6126 in the mips64 Linux (the kernel), that compiles source
6127 files with -mabi=64, assembling them as o32 or n32 (with
6128 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6129 the whole kernel is loaded into a memory region that is
6130 addressable with sign-extended 32-bit addresses, it is
6131 wasteful to compute the upper 32 bits of every
6132 non-literal address, that takes more space and time.
6133 Some day this should probably be implemented as an
6134 assembler option, such that the kernel doesn't have to
6135 use such ugly hacks, even though it will still have to
6136 end up converting the binary to ELF32 for a number of
6137 platforms whose boot loaders don't support ELF64
6139 if ((HAVE_64BIT_ADDRESSES
6140 && ! (offset_expr.X_op == O_constant
6141 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6143 && offset_expr.X_op == O_constant
6144 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6148 /* We don't do GP optimization for now because RELAX_ENCODE can't
6149 hold the data for such large chunks. */
6151 if (used_at == 0 && ! mips_opts.noat)
6153 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6154 tempreg, BFD_RELOC_MIPS_HIGHEST);
6155 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6156 AT, BFD_RELOC_HI16_S);
6157 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6158 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
6160 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6162 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
6163 tempreg, tempreg, 0);
6164 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6165 tempreg, tempreg, AT);
6166 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6167 BFD_RELOC_LO16, tempreg);
6172 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6173 tempreg, BFD_RELOC_MIPS_HIGHEST);
6174 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6175 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
6176 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
6177 tempreg, tempreg, 16);
6178 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6179 tempreg, tempreg, BFD_RELOC_HI16_S);
6180 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
6181 tempreg, tempreg, 16);
6183 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6184 tempreg, tempreg, breg);
6185 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6186 BFD_RELOC_LO16, tempreg);
6192 if (offset_expr.X_op == O_constant
6193 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6194 as_bad (_("load/store address overflow (max 32 bits)"));
6198 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6199 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6203 relax_start (offset_expr.X_add_symbol);
6204 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6205 BFD_RELOC_GPREL16, mips_gp_register);
6209 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6210 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6211 BFD_RELOC_LO16, tempreg);
6212 if (mips_relax.sequence)
6217 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6218 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6222 relax_start (offset_expr.X_add_symbol);
6223 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6224 tempreg, breg, mips_gp_register);
6225 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6226 BFD_RELOC_GPREL16, tempreg);
6229 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6230 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6231 tempreg, tempreg, breg);
6232 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6233 BFD_RELOC_LO16, tempreg);
6234 if (mips_relax.sequence)
6238 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6241 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6243 /* If this is a reference to an external symbol, we want
6244 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6246 <op> $treg,0($tempreg)
6248 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6250 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6251 <op> $treg,0($tempreg)
6254 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6255 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6257 If there is a base register, we add it to $tempreg before
6258 the <op>. If there is a constant, we stick it in the
6259 <op> instruction. We don't handle constants larger than
6260 16 bits, because we have no way to load the upper 16 bits
6261 (actually, we could handle them for the subset of cases
6262 in which we are not using $at). */
6263 assert (offset_expr.X_op == O_symbol);
6266 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6267 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6270 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6271 tempreg, tempreg, breg);
6272 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6273 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6280 expr1.X_add_number = offset_expr.X_add_number;
6281 offset_expr.X_add_number = 0;
6282 if (expr1.X_add_number < -0x8000
6283 || expr1.X_add_number >= 0x8000)
6284 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6285 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6286 tempreg, lw_reloc_type, mips_gp_register);
6287 macro_build (NULL, &icnt, NULL, "nop", "");
6288 relax_start (offset_expr.X_add_symbol);
6290 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6291 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
6294 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6295 tempreg, tempreg, breg);
6296 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6299 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6304 /* If this is a reference to an external symbol, we want
6305 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6306 addu $tempreg,$tempreg,$gp
6307 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6308 <op> $treg,0($tempreg)
6310 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6312 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6313 <op> $treg,0($tempreg)
6314 If there is a base register, we add it to $tempreg before
6315 the <op>. If there is a constant, we stick it in the
6316 <op> instruction. We don't handle constants larger than
6317 16 bits, because we have no way to load the upper 16 bits
6318 (actually, we could handle them for the subset of cases
6319 in which we are not using $at). */
6320 assert (offset_expr.X_op == O_symbol);
6321 expr1.X_add_number = offset_expr.X_add_number;
6322 offset_expr.X_add_number = 0;
6323 if (expr1.X_add_number < -0x8000
6324 || expr1.X_add_number >= 0x8000)
6325 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6326 if (reg_needs_delay (mips_gp_register))
6330 relax_start (offset_expr.X_add_symbol);
6331 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6332 BFD_RELOC_MIPS_GOT_HI16);
6333 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6334 tempreg, tempreg, mips_gp_register);
6335 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6336 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6339 macro_build (p, &icnt, NULL, "nop", "");
6340 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6341 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6342 macro_build (p, &icnt, NULL, "nop", "");
6343 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6344 tempreg, tempreg, BFD_RELOC_LO16);
6348 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6349 tempreg, tempreg, breg);
6350 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6353 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6356 int bregsz = breg != 0 ? 4 : 0;
6358 /* If this is a reference to an external symbol, we want
6359 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6360 add $tempreg,$tempreg,$gp
6361 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6362 <op> $treg,<ofst>($tempreg)
6363 Otherwise, for local symbols, we want:
6364 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6365 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6366 assert (offset_expr.X_op == O_symbol);
6367 expr1.X_add_number = offset_expr.X_add_number;
6368 offset_expr.X_add_number = 0;
6369 if (expr1.X_add_number < -0x8000
6370 || expr1.X_add_number >= 0x8000)
6371 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6372 relax_start (offset_expr.X_add_symbol);
6373 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6374 BFD_RELOC_MIPS_GOT_HI16);
6375 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6376 tempreg, tempreg, mips_gp_register);
6377 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6378 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6380 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6381 tempreg, tempreg, breg);
6382 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6386 offset_expr.X_add_number = expr1.X_add_number;
6387 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6388 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6390 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6391 tempreg, tempreg, breg);
6392 macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
6393 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6396 else if (mips_pic == EMBEDDED_PIC)
6398 /* If there is no base register, we want
6399 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6400 If there is a base register, we want
6401 addu $tempreg,$breg,$gp
6402 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6404 assert (offset_expr.X_op == O_symbol);
6407 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6408 BFD_RELOC_GPREL16, mips_gp_register);
6413 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6414 tempreg, breg, mips_gp_register);
6415 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6416 BFD_RELOC_GPREL16, tempreg);
6429 load_register (&icnt, treg, &imm_expr, 0);
6433 load_register (&icnt, treg, &imm_expr, 1);
6437 if (imm_expr.X_op == O_constant)
6439 load_register (&icnt, AT, &imm_expr, 0);
6440 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6445 assert (offset_expr.X_op == O_symbol
6446 && strcmp (segment_name (S_GET_SEGMENT
6447 (offset_expr.X_add_symbol)),
6449 && offset_expr.X_add_number == 0);
6450 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
6451 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6456 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6457 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6458 order 32 bits of the value and the low order 32 bits are either
6459 zero or in OFFSET_EXPR. */
6460 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6462 if (HAVE_64BIT_GPRS)
6463 load_register (&icnt, treg, &imm_expr, 1);
6468 if (target_big_endian)
6480 load_register (&icnt, hreg, &imm_expr, 0);
6483 if (offset_expr.X_op == O_absent)
6484 move_register (&icnt, lreg, 0);
6487 assert (offset_expr.X_op == O_constant);
6488 load_register (&icnt, lreg, &offset_expr, 0);
6495 /* We know that sym is in the .rdata section. First we get the
6496 upper 16 bits of the address. */
6497 if (mips_pic == NO_PIC)
6499 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6501 else if (mips_pic == SVR4_PIC)
6503 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6504 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6506 else if (mips_pic == EMBEDDED_PIC)
6508 /* For embedded PIC we pick up the entire address off $gp in
6509 a single instruction. */
6510 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6511 AT, mips_gp_register, BFD_RELOC_GPREL16);
6512 offset_expr.X_op = O_constant;
6513 offset_expr.X_add_number = 0;
6518 /* Now we load the register(s). */
6519 if (HAVE_64BIT_GPRS)
6520 macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
6521 BFD_RELOC_LO16, AT);
6524 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
6525 BFD_RELOC_LO16, AT);
6528 /* FIXME: How in the world do we deal with the possible
6530 offset_expr.X_add_number += 4;
6531 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6532 treg + 1, BFD_RELOC_LO16, AT);
6538 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6539 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6540 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6541 the value and the low order 32 bits are either zero or in
6543 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6545 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6546 if (HAVE_64BIT_FPRS)
6548 assert (HAVE_64BIT_GPRS);
6549 macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
6553 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
6554 if (offset_expr.X_op == O_absent)
6555 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
6558 assert (offset_expr.X_op == O_constant);
6559 load_register (&icnt, AT, &offset_expr, 0);
6560 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6566 assert (offset_expr.X_op == O_symbol
6567 && offset_expr.X_add_number == 0);
6568 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6569 if (strcmp (s, ".lit8") == 0)
6571 if (mips_opts.isa != ISA_MIPS1)
6573 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6574 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6577 breg = mips_gp_register;
6578 r = BFD_RELOC_MIPS_LITERAL;
6583 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6584 if (mips_pic == SVR4_PIC)
6585 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6586 "t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
6590 /* FIXME: This won't work for a 64 bit address. */
6591 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6594 if (mips_opts.isa != ISA_MIPS1)
6596 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6597 BFD_RELOC_LO16, AT);
6606 if (mips_opts.arch == CPU_R4650)
6608 as_bad (_("opcode not supported on this processor"));
6611 /* Even on a big endian machine $fn comes before $fn+1. We have
6612 to adjust when loading from memory. */
6615 assert (mips_opts.isa == ISA_MIPS1);
6616 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6617 target_big_endian ? treg + 1 : treg, r, breg);
6618 /* FIXME: A possible overflow which I don't know how to deal
6620 offset_expr.X_add_number += 4;
6621 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6622 target_big_endian ? treg : treg + 1, r, breg);
6630 * The MIPS assembler seems to check for X_add_number not
6631 * being double aligned and generating:
6634 * addiu at,at,%lo(foo+1)
6637 * But, the resulting address is the same after relocation so why
6638 * generate the extra instruction?
6640 if (mips_opts.arch == CPU_R4650)
6642 as_bad (_("opcode not supported on this processor"));
6645 /* Itbl support may require additional care here. */
6647 if (mips_opts.isa != ISA_MIPS1)
6658 if (mips_opts.arch == CPU_R4650)
6660 as_bad (_("opcode not supported on this processor"));
6664 if (mips_opts.isa != ISA_MIPS1)
6672 /* Itbl support may require additional care here. */
6677 if (HAVE_64BIT_GPRS)
6688 if (HAVE_64BIT_GPRS)
6698 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6699 loads for the case of doing a pair of loads to simulate an 'ld'.
6700 This is not currently done by the compiler, and assembly coders
6701 writing embedded-pic code can cope. */
6703 if (offset_expr.X_op != O_symbol
6704 && offset_expr.X_op != O_constant)
6706 as_bad (_("expression too complex"));
6707 offset_expr.X_op = O_constant;
6710 /* Even on a big endian machine $fn comes before $fn+1. We have
6711 to adjust when loading from memory. We set coproc if we must
6712 load $fn+1 first. */
6713 /* Itbl support may require additional care here. */
6714 if (! target_big_endian)
6717 if (mips_pic == NO_PIC
6718 || offset_expr.X_op == O_constant)
6722 /* If this is a reference to a GP relative symbol, we want
6723 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6724 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6725 If we have a base register, we use this
6727 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6728 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6729 If this is not a GP relative symbol, we want
6730 lui $at,<sym> (BFD_RELOC_HI16_S)
6731 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6732 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6733 If there is a base register, we add it to $at after the
6734 lui instruction. If there is a constant, we always use
6736 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6737 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6746 relax_start (offset_expr.X_add_symbol);
6749 tempreg = mips_gp_register;
6755 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6756 AT, breg, mips_gp_register);
6762 /* Itbl support may require additional care here. */
6763 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6764 coproc ? treg + 1 : treg,
6765 BFD_RELOC_GPREL16, tempreg);
6766 offset_expr.X_add_number += 4;
6768 /* Set mips_optimize to 2 to avoid inserting an
6770 hold_mips_optimize = mips_optimize;
6772 /* Itbl support may require additional care here. */
6773 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6774 coproc ? treg : treg + 1,
6775 BFD_RELOC_GPREL16, tempreg);
6776 mips_optimize = hold_mips_optimize;
6780 /* We just generated two relocs. When tc_gen_reloc
6781 handles this case, it will skip the first reloc and
6782 handle the second. The second reloc already has an
6783 extra addend of 4, which we added above. We must
6784 subtract it out, and then subtract another 4 to make
6785 the first reloc come out right. The second reloc
6786 will come out right because we are going to add 4 to
6787 offset_expr when we build its instruction below.
6789 If we have a symbol, then we don't want to include
6790 the offset, because it will wind up being included
6791 when we generate the reloc. */
6793 if (offset_expr.X_op == O_constant)
6794 offset_expr.X_add_number -= 8;
6797 offset_expr.X_add_number = -4;
6798 offset_expr.X_op = O_constant;
6801 macro_build_lui (p, &icnt, &offset_expr, AT);
6803 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6805 /* Itbl support may require additional care here. */
6806 macro_build (p, &icnt, &offset_expr, s, fmt,
6807 coproc ? treg + 1 : treg,
6808 BFD_RELOC_LO16, AT);
6809 /* FIXME: How do we handle overflow here? */
6810 offset_expr.X_add_number += 4;
6811 /* Itbl support may require additional care here. */
6812 macro_build (p, &icnt, &offset_expr, s, fmt,
6813 coproc ? treg : treg + 1,
6814 BFD_RELOC_LO16, AT);
6815 if (mips_relax.sequence)
6818 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6822 /* If this is a reference to an external symbol, we want
6823 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6828 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6830 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6831 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6832 If there is a base register we add it to $at before the
6833 lwc1 instructions. If there is a constant we include it
6834 in the lwc1 instructions. */
6836 expr1.X_add_number = offset_expr.X_add_number;
6837 if (expr1.X_add_number < -0x8000
6838 || expr1.X_add_number >= 0x8000 - 4)
6839 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6844 load_got_offset (&icnt, AT, &offset_expr);
6845 macro_build (NULL, &icnt, NULL, "nop", "");
6847 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6850 /* Set mips_optimize to 2 to avoid inserting an undesired
6852 hold_mips_optimize = mips_optimize;
6855 /* Itbl support may require additional care here. */
6856 relax_start (offset_expr.X_add_symbol);
6857 macro_build (NULL, &icnt, &expr1, s, fmt,
6858 coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
6859 expr1.X_add_number += 4;
6860 macro_build (NULL, &icnt, &expr1, s, fmt,
6861 coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
6863 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6864 coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
6865 offset_expr.X_add_number += 4;
6866 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6867 coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
6870 mips_optimize = hold_mips_optimize;
6872 else if (mips_pic == SVR4_PIC)
6877 /* If this is a reference to an external symbol, we want
6878 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6880 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6885 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6887 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6888 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6889 If there is a base register we add it to $at before the
6890 lwc1 instructions. If there is a constant we include it
6891 in the lwc1 instructions. */
6893 expr1.X_add_number = offset_expr.X_add_number;
6894 offset_expr.X_add_number = 0;
6895 if (expr1.X_add_number < -0x8000
6896 || expr1.X_add_number >= 0x8000 - 4)
6897 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6898 if (reg_needs_delay (mips_gp_register))
6906 relax_start (offset_expr.X_add_symbol);
6907 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
6908 BFD_RELOC_MIPS_GOT_HI16);
6909 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6910 AT, AT, mips_gp_register);
6911 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6912 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6913 macro_build (NULL, &icnt, NULL, "nop", "");
6915 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6917 /* Itbl support may require additional care here. */
6918 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6919 BFD_RELOC_LO16, AT);
6920 expr1.X_add_number += 4;
6922 /* Set mips_optimize to 2 to avoid inserting an undesired
6924 hold_mips_optimize = mips_optimize;
6926 /* Itbl support may require additional care here. */
6927 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6928 BFD_RELOC_LO16, AT);
6929 mips_optimize = hold_mips_optimize;
6930 expr1.X_add_number -= 4;
6933 offset_expr.X_add_number = expr1.X_add_number;
6935 macro_build (p, &icnt, NULL, "nop", "");
6936 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6937 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6938 macro_build (p, &icnt, NULL, "nop", "");
6940 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6942 /* Itbl support may require additional care here. */
6943 macro_build (p, &icnt, &offset_expr, s, fmt,
6944 coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
6945 offset_expr.X_add_number += 4;
6947 /* Set mips_optimize to 2 to avoid inserting an undesired
6949 hold_mips_optimize = mips_optimize;
6951 /* Itbl support may require additional care here. */
6952 macro_build (p, &icnt, &offset_expr, s, fmt,
6953 coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
6954 mips_optimize = hold_mips_optimize;
6957 else if (mips_pic == EMBEDDED_PIC)
6959 /* If there is no base register, we use
6960 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6961 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6962 If we have a base register, we use
6964 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6965 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6969 tempreg = mips_gp_register;
6974 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6975 AT, breg, mips_gp_register);
6980 /* Itbl support may require additional care here. */
6981 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6982 coproc ? treg + 1 : treg,
6983 BFD_RELOC_GPREL16, tempreg);
6984 offset_expr.X_add_number += 4;
6985 /* Itbl support may require additional care here. */
6986 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6987 coproc ? treg : treg + 1,
6988 BFD_RELOC_GPREL16, tempreg);
7004 assert (HAVE_32BIT_ADDRESSES);
7005 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7006 BFD_RELOC_LO16, breg);
7007 offset_expr.X_add_number += 4;
7008 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
7009 BFD_RELOC_LO16, breg);
7012 /* New code added to support COPZ instructions.
7013 This code builds table entries out of the macros in mip_opcodes.
7014 R4000 uses interlocks to handle coproc delays.
7015 Other chips (like the R3000) require nops to be inserted for delays.
7017 FIXME: Currently, we require that the user handle delays.
7018 In order to fill delay slots for non-interlocked chips,
7019 we must have a way to specify delays based on the coprocessor.
7020 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7021 What are the side-effects of the cop instruction?
7022 What cache support might we have and what are its effects?
7023 Both coprocessor & memory require delays. how long???
7024 What registers are read/set/modified?
7026 If an itbl is provided to interpret cop instructions,
7027 this knowledge can be encoded in the itbl spec. */
7041 /* For now we just do C (same as Cz). The parameter will be
7042 stored in insn_opcode by mips_ip. */
7043 macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
7047 move_register (&icnt, dreg, sreg);
7050 #ifdef LOSING_COMPILER
7052 /* Try and see if this is a new itbl instruction.
7053 This code builds table entries out of the macros in mip_opcodes.
7054 FIXME: For now we just assemble the expression and pass it's
7055 value along as a 32-bit immediate.
7056 We may want to have the assembler assemble this value,
7057 so that we gain the assembler's knowledge of delay slots,
7059 Would it be more efficient to use mask (id) here? */
7060 if (itbl_have_entries
7061 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7063 s = ip->insn_mo->name;
7065 coproc = ITBL_DECODE_PNUM (immed_expr);;
7066 macro_build (NULL, &icnt, &immed_expr, s, "C");
7073 as_warn (_("Macro used $at after \".set noat\""));
7077 macro2 (struct mips_cl_insn *ip)
7079 register int treg, sreg, dreg, breg;
7095 bfd_reloc_code_real_type r;
7098 treg = (ip->insn_opcode >> 16) & 0x1f;
7099 dreg = (ip->insn_opcode >> 11) & 0x1f;
7100 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7101 mask = ip->insn_mo->mask;
7103 expr1.X_op = O_constant;
7104 expr1.X_op_symbol = NULL;
7105 expr1.X_add_symbol = NULL;
7106 expr1.X_add_number = 1;
7110 #endif /* LOSING_COMPILER */
7115 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7117 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7123 /* The MIPS assembler some times generates shifts and adds. I'm
7124 not trying to be that fancy. GCC should do this for us
7126 load_register (&icnt, AT, &imm_expr, dbl);
7127 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7129 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7142 mips_emit_delays (TRUE);
7143 ++mips_opts.noreorder;
7144 mips_any_noreorder = 1;
7146 load_register (&icnt, AT, &imm_expr, dbl);
7147 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7148 sreg, imm ? AT : treg);
7149 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7150 macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
7152 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7154 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
7157 expr1.X_add_number = 8;
7158 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
7159 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7160 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7162 --mips_opts.noreorder;
7163 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7176 mips_emit_delays (TRUE);
7177 ++mips_opts.noreorder;
7178 mips_any_noreorder = 1;
7180 load_register (&icnt, AT, &imm_expr, dbl);
7181 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7182 sreg, imm ? AT : treg);
7183 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7184 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7186 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
7189 expr1.X_add_number = 8;
7190 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
7191 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7192 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7194 --mips_opts.noreorder;
7198 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7210 macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
7211 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
7217 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7218 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7219 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7220 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7224 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7236 macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
7237 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
7243 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7244 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
7245 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
7246 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7254 if (imm_expr.X_op != O_constant)
7255 as_bad (_("Improper rotate count"));
7256 rot = imm_expr.X_add_number & 0x3f;
7257 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7259 rot = (64 - rot) & 0x3f;
7261 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7262 dreg, sreg, rot - 32);
7264 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7270 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7273 l = (rot < 0x20) ? "dsll" : "dsll32";
7274 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7276 macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
7277 macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
7278 (0x20 - rot) & 0x1f);
7279 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7287 if (imm_expr.X_op != O_constant)
7288 as_bad (_("Improper rotate count"));
7289 rot = imm_expr.X_add_number & 0x1f;
7290 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7292 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
7298 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7301 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
7302 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
7303 (0x20 - rot) & 0x1f);
7304 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7309 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7311 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
7314 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7315 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
7316 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7317 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7321 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7323 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
7326 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7327 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
7328 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
7329 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7337 if (imm_expr.X_op != O_constant)
7338 as_bad (_("Improper rotate count"));
7339 rot = imm_expr.X_add_number & 0x3f;
7340 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7343 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7344 dreg, sreg, rot - 32);
7346 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7352 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7355 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7356 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7358 macro_build (NULL, &icnt, NULL, r, "d,w,<", AT, sreg, rot);
7359 macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
7360 (0x20 - rot) & 0x1f);
7361 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7369 if (imm_expr.X_op != O_constant)
7370 as_bad (_("Improper rotate count"));
7371 rot = imm_expr.X_add_number & 0x1f;
7372 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7374 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
7379 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7382 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
7383 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
7384 (0x20 - rot) & 0x1f);
7385 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7390 if (mips_opts.arch == CPU_R4650)
7392 as_bad (_("opcode not supported on this processor"));
7395 assert (mips_opts.isa == ISA_MIPS1);
7396 /* Even on a big endian machine $fn comes before $fn+1. We have
7397 to adjust when storing to memory. */
7398 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7399 target_big_endian ? treg + 1 : treg,
7400 BFD_RELOC_LO16, breg);
7401 offset_expr.X_add_number += 4;
7402 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7403 target_big_endian ? treg : treg + 1,
7404 BFD_RELOC_LO16, breg);
7409 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
7412 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7416 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7417 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7423 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7425 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7431 as_warn (_("Instruction %s: result is always false"),
7433 move_register (&icnt, dreg, 0);
7436 if (imm_expr.X_op == O_constant
7437 && imm_expr.X_add_number >= 0
7438 && imm_expr.X_add_number < 0x10000)
7440 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7444 else if (imm_expr.X_op == O_constant
7445 && imm_expr.X_add_number > -0x8000
7446 && imm_expr.X_add_number < 0)
7448 imm_expr.X_add_number = -imm_expr.X_add_number;
7449 macro_build (NULL, &icnt, &imm_expr,
7450 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7451 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7456 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7457 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7460 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7466 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7472 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
7473 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7477 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7479 if (imm_expr.X_op == O_constant
7480 && imm_expr.X_add_number >= -0x8000
7481 && imm_expr.X_add_number < 0x8000)
7483 macro_build (NULL, &icnt, &imm_expr,
7484 mask == M_SGE_I ? "slti" : "sltiu",
7485 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7490 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7491 macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
7492 "d,v,t", dreg, sreg, AT);
7495 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7501 case M_SGT: /* sreg > treg <==> treg < sreg */
7507 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7510 case M_SGT_I: /* sreg > I <==> I < sreg */
7516 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7517 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7520 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7526 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7527 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7531 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7537 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7538 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7539 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7544 if (imm_expr.X_op == O_constant
7545 && imm_expr.X_add_number >= -0x8000
7546 && imm_expr.X_add_number < 0x8000)
7548 macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
7552 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7553 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
7557 if (imm_expr.X_op == O_constant
7558 && imm_expr.X_add_number >= -0x8000
7559 && imm_expr.X_add_number < 0x8000)
7561 macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
7565 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7566 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
7571 macro_build (NULL, &icnt, NULL, "sltu","d,v,t", dreg, 0, treg);
7573 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7576 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7577 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7582 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7584 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7589 as_warn (_("Instruction %s: result is always true"),
7591 macro_build (NULL, &icnt, &expr1,
7592 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7593 "t,r,j", dreg, 0, BFD_RELOC_LO16);
7596 if (imm_expr.X_op == O_constant
7597 && imm_expr.X_add_number >= 0
7598 && imm_expr.X_add_number < 0x10000)
7600 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7604 else if (imm_expr.X_op == O_constant
7605 && imm_expr.X_add_number > -0x8000
7606 && imm_expr.X_add_number < 0)
7608 imm_expr.X_add_number = -imm_expr.X_add_number;
7609 macro_build (NULL, &icnt, &imm_expr,
7610 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7611 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7616 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7617 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7620 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7628 if (imm_expr.X_op == O_constant
7629 && imm_expr.X_add_number > -0x8000
7630 && imm_expr.X_add_number <= 0x8000)
7632 imm_expr.X_add_number = -imm_expr.X_add_number;
7633 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
7634 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7637 load_register (&icnt, AT, &imm_expr, dbl);
7638 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
7645 if (imm_expr.X_op == O_constant
7646 && imm_expr.X_add_number > -0x8000
7647 && imm_expr.X_add_number <= 0x8000)
7649 imm_expr.X_add_number = -imm_expr.X_add_number;
7650 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
7651 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7654 load_register (&icnt, AT, &imm_expr, dbl);
7655 macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
7677 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7678 macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
7683 assert (mips_opts.isa == ISA_MIPS1);
7684 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7685 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7688 * Is the double cfc1 instruction a bug in the mips assembler;
7689 * or is there a reason for it?
7691 mips_emit_delays (TRUE);
7692 ++mips_opts.noreorder;
7693 mips_any_noreorder = 1;
7694 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7695 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7696 macro_build (NULL, &icnt, NULL, "nop", "");
7697 expr1.X_add_number = 3;
7698 macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7700 expr1.X_add_number = 2;
7701 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7703 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
7704 macro_build (NULL, &icnt, NULL, "nop", "");
7705 macro_build (NULL, &icnt, NULL,
7706 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
7708 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
7709 macro_build (NULL, &icnt, NULL, "nop", "");
7710 --mips_opts.noreorder;
7719 if (offset_expr.X_add_number >= 0x7fff)
7720 as_bad (_("operand overflow"));
7721 if (! target_big_endian)
7722 ++offset_expr.X_add_number;
7723 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7724 BFD_RELOC_LO16, breg);
7725 if (! target_big_endian)
7726 --offset_expr.X_add_number;
7728 ++offset_expr.X_add_number;
7729 macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7730 BFD_RELOC_LO16, breg);
7731 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
7732 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7745 if (offset_expr.X_add_number >= 0x8000 - off)
7746 as_bad (_("operand overflow"));
7751 if (! target_big_endian)
7752 offset_expr.X_add_number += off;
7753 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7754 BFD_RELOC_LO16, breg);
7755 if (! target_big_endian)
7756 offset_expr.X_add_number -= off;
7758 offset_expr.X_add_number += off;
7759 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7760 BFD_RELOC_LO16, breg);
7762 /* If necessary, move the result in tempreg the final destination. */
7763 if (treg == tempreg)
7765 /* Protect second load's delay slot. */
7766 if (!gpr_interlocks)
7767 macro_build (NULL, &icnt, NULL, "nop", "");
7768 move_register (&icnt, treg, tempreg);
7782 load_address (&icnt, AT, &offset_expr, &used_at);
7784 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7786 if (! target_big_endian)
7787 expr1.X_add_number = off;
7789 expr1.X_add_number = 0;
7790 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7791 BFD_RELOC_LO16, AT);
7792 if (! target_big_endian)
7793 expr1.X_add_number = 0;
7795 expr1.X_add_number = off;
7796 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7797 BFD_RELOC_LO16, AT);
7803 load_address (&icnt, AT, &offset_expr, &used_at);
7805 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7807 if (target_big_endian)
7808 expr1.X_add_number = 0;
7809 macro_build (NULL, &icnt, &expr1,
7810 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7811 treg, BFD_RELOC_LO16, AT);
7812 if (target_big_endian)
7813 expr1.X_add_number = 1;
7815 expr1.X_add_number = 0;
7816 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
7817 AT, BFD_RELOC_LO16, AT);
7818 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7819 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7823 if (offset_expr.X_add_number >= 0x7fff)
7824 as_bad (_("operand overflow"));
7825 if (target_big_endian)
7826 ++offset_expr.X_add_number;
7827 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7828 BFD_RELOC_LO16, breg);
7829 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
7830 if (target_big_endian)
7831 --offset_expr.X_add_number;
7833 ++offset_expr.X_add_number;
7834 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7835 BFD_RELOC_LO16, breg);
7848 if (offset_expr.X_add_number >= 0x8000 - off)
7849 as_bad (_("operand overflow"));
7850 if (! target_big_endian)
7851 offset_expr.X_add_number += off;
7852 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7853 BFD_RELOC_LO16, breg);
7854 if (! target_big_endian)
7855 offset_expr.X_add_number -= off;
7857 offset_expr.X_add_number += off;
7858 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7859 BFD_RELOC_LO16, breg);
7873 load_address (&icnt, AT, &offset_expr, &used_at);
7875 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7877 if (! target_big_endian)
7878 expr1.X_add_number = off;
7880 expr1.X_add_number = 0;
7881 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7882 BFD_RELOC_LO16, AT);
7883 if (! target_big_endian)
7884 expr1.X_add_number = 0;
7886 expr1.X_add_number = off;
7887 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7888 BFD_RELOC_LO16, AT);
7893 load_address (&icnt, AT, &offset_expr, &used_at);
7895 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7897 if (! target_big_endian)
7898 expr1.X_add_number = 0;
7899 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7900 BFD_RELOC_LO16, AT);
7901 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
7902 if (! target_big_endian)
7903 expr1.X_add_number = 1;
7905 expr1.X_add_number = 0;
7906 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7907 BFD_RELOC_LO16, AT);
7908 if (! target_big_endian)
7909 expr1.X_add_number = 0;
7911 expr1.X_add_number = 1;
7912 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7913 BFD_RELOC_LO16, AT);
7914 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7915 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7919 /* FIXME: Check if this is one of the itbl macros, since they
7920 are added dynamically. */
7921 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7925 as_warn (_("Macro used $at after \".set noat\""));
7928 /* Implement macros in mips16 mode. */
7931 mips16_macro (struct mips_cl_insn *ip)
7934 int xreg, yreg, zreg, tmp;
7938 const char *s, *s2, *s3;
7940 mask = ip->insn_mo->mask;
7942 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7943 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7944 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7948 expr1.X_op = O_constant;
7949 expr1.X_op_symbol = NULL;
7950 expr1.X_add_symbol = NULL;
7951 expr1.X_add_number = 1;
7970 mips_emit_delays (TRUE);
7971 ++mips_opts.noreorder;
7972 mips_any_noreorder = 1;
7973 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
7975 expr1.X_add_number = 2;
7976 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7977 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7979 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7980 since that causes an overflow. We should do that as well,
7981 but I don't see how to do the comparisons without a temporary
7983 --mips_opts.noreorder;
7984 macro_build (NULL, &icnt, NULL, s, "x", zreg);
8003 mips_emit_delays (TRUE);
8004 ++mips_opts.noreorder;
8005 mips_any_noreorder = 1;
8006 macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
8007 expr1.X_add_number = 2;
8008 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
8009 macro_build (NULL, &icnt, NULL, "break", "6", 7);
8010 --mips_opts.noreorder;
8011 macro_build (NULL, &icnt, NULL, s2, "x", zreg);
8017 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
8019 macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
8027 if (imm_expr.X_op != O_constant)
8028 as_bad (_("Unsupported large constant"));
8029 imm_expr.X_add_number = -imm_expr.X_add_number;
8030 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
8035 if (imm_expr.X_op != O_constant)
8036 as_bad (_("Unsupported large constant"));
8037 imm_expr.X_add_number = -imm_expr.X_add_number;
8038 macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
8042 if (imm_expr.X_op != O_constant)
8043 as_bad (_("Unsupported large constant"));
8044 imm_expr.X_add_number = -imm_expr.X_add_number;
8045 macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
8067 goto do_reverse_branch;
8071 goto do_reverse_branch;
8083 goto do_reverse_branch;
8094 macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
8095 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8122 goto do_addone_branch_i;
8127 goto do_addone_branch_i;
8142 goto do_addone_branch_i;
8149 if (imm_expr.X_op != O_constant)
8150 as_bad (_("Unsupported large constant"));
8151 ++imm_expr.X_add_number;
8154 macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
8155 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8159 expr1.X_add_number = 0;
8160 macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
8162 move_register (&icnt, xreg, yreg);
8163 expr1.X_add_number = 2;
8164 macro_build (NULL, &icnt, &expr1, "bteqz", "p");
8165 macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
8169 /* For consistency checking, verify that all bits are specified either
8170 by the match/mask part of the instruction definition, or by the
8173 validate_mips_insn (const struct mips_opcode *opc)
8175 const char *p = opc->args;
8177 unsigned long used_bits = opc->mask;
8179 if ((used_bits & opc->match) != opc->match)
8181 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8182 opc->name, opc->args);
8185 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8195 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8196 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8197 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8198 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8199 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8200 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8201 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8202 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8203 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8206 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8207 c, opc->name, opc->args);
8211 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8212 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8214 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8215 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8216 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8217 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8219 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8220 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8222 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8223 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8225 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8226 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8227 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8228 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8229 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8230 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8231 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8232 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8233 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8234 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8235 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8236 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8237 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8238 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8239 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8240 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8241 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8243 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8244 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8245 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8246 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8248 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8249 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8250 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8251 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8252 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8253 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8254 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8255 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8256 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8259 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8260 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8261 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8262 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8263 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8267 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8268 c, opc->name, opc->args);
8272 if (used_bits != 0xffffffff)
8274 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8275 ~used_bits & 0xffffffff, opc->name, opc->args);
8281 /* This routine assembles an instruction into its binary format. As a
8282 side effect, it sets one of the global variables imm_reloc or
8283 offset_reloc to the type of relocation to do if one of the operands
8284 is an address expression. */
8287 mips_ip (char *str, struct mips_cl_insn *ip)
8292 struct mips_opcode *insn;
8295 unsigned int lastregno = 0;
8296 unsigned int lastpos = 0;
8297 unsigned int limlo, limhi;
8303 /* If the instruction contains a '.', we first try to match an instruction
8304 including the '.'. Then we try again without the '.'. */
8306 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8309 /* If we stopped on whitespace, then replace the whitespace with null for
8310 the call to hash_find. Save the character we replaced just in case we
8311 have to re-parse the instruction. */
8318 insn = (struct mips_opcode *) hash_find (op_hash, str);
8320 /* If we didn't find the instruction in the opcode table, try again, but
8321 this time with just the instruction up to, but not including the
8325 /* Restore the character we overwrite above (if any). */
8329 /* Scan up to the first '.' or whitespace. */
8331 *s != '\0' && *s != '.' && !ISSPACE (*s);
8335 /* If we did not find a '.', then we can quit now. */
8338 insn_error = "unrecognized opcode";
8342 /* Lookup the instruction in the hash table. */
8344 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8346 insn_error = "unrecognized opcode";
8356 assert (strcmp (insn->name, str) == 0);
8358 if (OPCODE_IS_MEMBER (insn,
8360 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8361 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8362 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8368 if (insn->pinfo != INSN_MACRO)
8370 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8376 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8377 && strcmp (insn->name, insn[1].name) == 0)
8386 static char buf[100];
8388 _("opcode not supported on this processor: %s (%s)"),
8389 mips_cpu_info_from_arch (mips_opts.arch)->name,
8390 mips_cpu_info_from_isa (mips_opts.isa)->name);
8400 ip->insn_opcode = insn->match;
8402 for (args = insn->args;; ++args)
8406 s += strspn (s, " \t");
8410 case '\0': /* end of args */
8423 ip->insn_opcode |= lastregno << OP_SH_RS;
8427 ip->insn_opcode |= lastregno << OP_SH_RT;
8431 ip->insn_opcode |= lastregno << OP_SH_FT;
8435 ip->insn_opcode |= lastregno << OP_SH_FS;
8441 /* Handle optional base register.
8442 Either the base register is omitted or
8443 we must have a left paren. */
8444 /* This is dependent on the next operand specifier
8445 is a base register specification. */
8446 assert (args[1] == 'b' || args[1] == '5'
8447 || args[1] == '-' || args[1] == '4');
8451 case ')': /* these must match exactly */
8458 case '+': /* Opcode extension character. */
8461 case 'A': /* ins/ext position, becomes LSB. */
8470 my_getExpression (&imm_expr, s);
8471 check_absolute_expr (ip, &imm_expr);
8472 if ((unsigned long) imm_expr.X_add_number < limlo
8473 || (unsigned long) imm_expr.X_add_number > limhi)
8475 as_bad (_("Improper position (%lu)"),
8476 (unsigned long) imm_expr.X_add_number);
8477 imm_expr.X_add_number = limlo;
8479 lastpos = imm_expr.X_add_number;
8480 ip->insn_opcode |= (imm_expr.X_add_number
8481 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8482 imm_expr.X_op = O_absent;
8486 case 'B': /* ins size, becomes MSB. */
8495 my_getExpression (&imm_expr, s);
8496 check_absolute_expr (ip, &imm_expr);
8497 /* Check for negative input so that small negative numbers
8498 will not succeed incorrectly. The checks against
8499 (pos+size) transitively check "size" itself,
8500 assuming that "pos" is reasonable. */
8501 if ((long) imm_expr.X_add_number < 0
8502 || ((unsigned long) imm_expr.X_add_number
8504 || ((unsigned long) imm_expr.X_add_number
8507 as_bad (_("Improper insert size (%lu, position %lu)"),
8508 (unsigned long) imm_expr.X_add_number,
8509 (unsigned long) lastpos);
8510 imm_expr.X_add_number = limlo - lastpos;
8512 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8513 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8514 imm_expr.X_op = O_absent;
8518 case 'C': /* ext size, becomes MSBD. */
8531 my_getExpression (&imm_expr, s);
8532 check_absolute_expr (ip, &imm_expr);
8533 /* Check for negative input so that small negative numbers
8534 will not succeed incorrectly. The checks against
8535 (pos+size) transitively check "size" itself,
8536 assuming that "pos" is reasonable. */
8537 if ((long) imm_expr.X_add_number < 0
8538 || ((unsigned long) imm_expr.X_add_number
8540 || ((unsigned long) imm_expr.X_add_number
8543 as_bad (_("Improper extract size (%lu, position %lu)"),
8544 (unsigned long) imm_expr.X_add_number,
8545 (unsigned long) lastpos);
8546 imm_expr.X_add_number = limlo - lastpos;
8548 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8549 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8550 imm_expr.X_op = O_absent;
8555 /* +D is for disassembly only; never match. */
8559 /* "+I" is like "I", except that imm2_expr is used. */
8560 my_getExpression (&imm2_expr, s);
8561 if (imm2_expr.X_op != O_big
8562 && imm2_expr.X_op != O_constant)
8563 insn_error = _("absolute expression required");
8564 normalize_constant_expr (&imm2_expr);
8569 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8570 *args, insn->name, insn->args);
8571 /* Further processing is fruitless. */
8576 case '<': /* must be at least one digit */
8578 * According to the manual, if the shift amount is greater
8579 * than 31 or less than 0, then the shift amount should be
8580 * mod 32. In reality the mips assembler issues an error.
8581 * We issue a warning and mask out all but the low 5 bits.
8583 my_getExpression (&imm_expr, s);
8584 check_absolute_expr (ip, &imm_expr);
8585 if ((unsigned long) imm_expr.X_add_number > 31)
8587 as_warn (_("Improper shift amount (%lu)"),
8588 (unsigned long) imm_expr.X_add_number);
8589 imm_expr.X_add_number &= OP_MASK_SHAMT;
8591 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8592 imm_expr.X_op = O_absent;
8596 case '>': /* shift amount minus 32 */
8597 my_getExpression (&imm_expr, s);
8598 check_absolute_expr (ip, &imm_expr);
8599 if ((unsigned long) imm_expr.X_add_number < 32
8600 || (unsigned long) imm_expr.X_add_number > 63)
8602 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8603 imm_expr.X_op = O_absent;
8607 case 'k': /* cache code */
8608 case 'h': /* prefx code */
8609 my_getExpression (&imm_expr, s);
8610 check_absolute_expr (ip, &imm_expr);
8611 if ((unsigned long) imm_expr.X_add_number > 31)
8613 as_warn (_("Invalid value for `%s' (%lu)"),
8615 (unsigned long) imm_expr.X_add_number);
8616 imm_expr.X_add_number &= 0x1f;
8619 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8621 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8622 imm_expr.X_op = O_absent;
8626 case 'c': /* break code */
8627 my_getExpression (&imm_expr, s);
8628 check_absolute_expr (ip, &imm_expr);
8629 if ((unsigned long) imm_expr.X_add_number > 1023)
8631 as_warn (_("Illegal break code (%lu)"),
8632 (unsigned long) imm_expr.X_add_number);
8633 imm_expr.X_add_number &= OP_MASK_CODE;
8635 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8636 imm_expr.X_op = O_absent;
8640 case 'q': /* lower break code */
8641 my_getExpression (&imm_expr, s);
8642 check_absolute_expr (ip, &imm_expr);
8643 if ((unsigned long) imm_expr.X_add_number > 1023)
8645 as_warn (_("Illegal lower break code (%lu)"),
8646 (unsigned long) imm_expr.X_add_number);
8647 imm_expr.X_add_number &= OP_MASK_CODE2;
8649 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8650 imm_expr.X_op = O_absent;
8654 case 'B': /* 20-bit syscall/break code. */
8655 my_getExpression (&imm_expr, s);
8656 check_absolute_expr (ip, &imm_expr);
8657 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8658 as_warn (_("Illegal 20-bit code (%lu)"),
8659 (unsigned long) imm_expr.X_add_number);
8660 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8661 imm_expr.X_op = O_absent;
8665 case 'C': /* Coprocessor code */
8666 my_getExpression (&imm_expr, s);
8667 check_absolute_expr (ip, &imm_expr);
8668 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8670 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8671 (unsigned long) imm_expr.X_add_number);
8672 imm_expr.X_add_number &= ((1 << 25) - 1);
8674 ip->insn_opcode |= imm_expr.X_add_number;
8675 imm_expr.X_op = O_absent;
8679 case 'J': /* 19-bit wait code. */
8680 my_getExpression (&imm_expr, s);
8681 check_absolute_expr (ip, &imm_expr);
8682 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8683 as_warn (_("Illegal 19-bit code (%lu)"),
8684 (unsigned long) imm_expr.X_add_number);
8685 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8686 imm_expr.X_op = O_absent;
8690 case 'P': /* Performance register */
8691 my_getExpression (&imm_expr, s);
8692 check_absolute_expr (ip, &imm_expr);
8693 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8695 as_warn (_("Invalid performance register (%lu)"),
8696 (unsigned long) imm_expr.X_add_number);
8697 imm_expr.X_add_number &= OP_MASK_PERFREG;
8699 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8700 imm_expr.X_op = O_absent;
8704 case 'b': /* base register */
8705 case 'd': /* destination register */
8706 case 's': /* source register */
8707 case 't': /* target register */
8708 case 'r': /* both target and source */
8709 case 'v': /* both dest and source */
8710 case 'w': /* both dest and target */
8711 case 'E': /* coprocessor target register */
8712 case 'G': /* coprocessor destination register */
8713 case 'K': /* 'rdhwr' destination register */
8714 case 'x': /* ignore register name */
8715 case 'z': /* must be zero register */
8716 case 'U': /* destination register (clo/clz). */
8731 while (ISDIGIT (*s));
8733 as_bad (_("Invalid register number (%d)"), regno);
8735 else if (*args == 'E' || *args == 'G' || *args == 'K')
8739 if (s[1] == 'r' && s[2] == 'a')
8744 else if (s[1] == 'f' && s[2] == 'p')
8749 else if (s[1] == 's' && s[2] == 'p')
8754 else if (s[1] == 'g' && s[2] == 'p')
8759 else if (s[1] == 'a' && s[2] == 't')
8764 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8769 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8774 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8779 else if (itbl_have_entries)
8784 p = s + 1; /* advance past '$' */
8785 n = itbl_get_field (&p); /* n is name */
8787 /* See if this is a register defined in an
8789 if (itbl_get_reg_val (n, &r))
8791 /* Get_field advances to the start of
8792 the next field, so we need to back
8793 rack to the end of the last field. */
8797 s = strchr (s, '\0');
8811 as_warn (_("Used $at without \".set noat\""));
8817 if (c == 'r' || c == 'v' || c == 'w')
8824 /* 'z' only matches $0. */
8825 if (c == 'z' && regno != 0)
8828 /* Now that we have assembled one operand, we use the args string
8829 * to figure out where it goes in the instruction. */
8836 ip->insn_opcode |= regno << OP_SH_RS;
8841 ip->insn_opcode |= regno << OP_SH_RD;
8844 ip->insn_opcode |= regno << OP_SH_RD;
8845 ip->insn_opcode |= regno << OP_SH_RT;
8850 ip->insn_opcode |= regno << OP_SH_RT;
8853 /* This case exists because on the r3000 trunc
8854 expands into a macro which requires a gp
8855 register. On the r6000 or r4000 it is
8856 assembled into a single instruction which
8857 ignores the register. Thus the insn version
8858 is MIPS_ISA2 and uses 'x', and the macro
8859 version is MIPS_ISA1 and uses 't'. */
8862 /* This case is for the div instruction, which
8863 acts differently if the destination argument
8864 is $0. This only matches $0, and is checked
8865 outside the switch. */
8868 /* Itbl operand; not yet implemented. FIXME ?? */
8870 /* What about all other operands like 'i', which
8871 can be specified in the opcode table? */
8881 ip->insn_opcode |= lastregno << OP_SH_RS;
8884 ip->insn_opcode |= lastregno << OP_SH_RT;
8889 case 'O': /* MDMX alignment immediate constant. */
8890 my_getExpression (&imm_expr, s);
8891 check_absolute_expr (ip, &imm_expr);
8892 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8894 as_warn ("Improper align amount (%ld), using low bits",
8895 (long) imm_expr.X_add_number);
8896 imm_expr.X_add_number &= OP_MASK_ALN;
8898 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8899 imm_expr.X_op = O_absent;
8903 case 'Q': /* MDMX vector, element sel, or const. */
8906 /* MDMX Immediate. */
8907 my_getExpression (&imm_expr, s);
8908 check_absolute_expr (ip, &imm_expr);
8909 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8911 as_warn (_("Invalid MDMX Immediate (%ld)"),
8912 (long) imm_expr.X_add_number);
8913 imm_expr.X_add_number &= OP_MASK_FT;
8915 imm_expr.X_add_number &= OP_MASK_FT;
8916 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8917 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8919 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8920 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8921 imm_expr.X_op = O_absent;
8925 /* Not MDMX Immediate. Fall through. */
8926 case 'X': /* MDMX destination register. */
8927 case 'Y': /* MDMX source register. */
8928 case 'Z': /* MDMX target register. */
8930 case 'D': /* floating point destination register */
8931 case 'S': /* floating point source register */
8932 case 'T': /* floating point target register */
8933 case 'R': /* floating point source register */
8937 /* Accept $fN for FP and MDMX register numbers, and in
8938 addition accept $vN for MDMX register numbers. */
8939 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8940 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8951 while (ISDIGIT (*s));
8954 as_bad (_("Invalid float register number (%d)"), regno);
8956 if ((regno & 1) != 0
8958 && ! (strcmp (str, "mtc1") == 0
8959 || strcmp (str, "mfc1") == 0
8960 || strcmp (str, "lwc1") == 0
8961 || strcmp (str, "swc1") == 0
8962 || strcmp (str, "l.s") == 0
8963 || strcmp (str, "s.s") == 0))
8964 as_warn (_("Float register should be even, was %d"),
8972 if (c == 'V' || c == 'W')
8983 ip->insn_opcode |= regno << OP_SH_FD;
8988 ip->insn_opcode |= regno << OP_SH_FS;
8991 /* This is like 'Z', but also needs to fix the MDMX
8992 vector/scalar select bits. Note that the
8993 scalar immediate case is handled above. */
8996 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8997 int max_el = (is_qh ? 3 : 7);
8999 my_getExpression(&imm_expr, s);
9000 check_absolute_expr (ip, &imm_expr);
9002 if (imm_expr.X_add_number > max_el)
9003 as_bad(_("Bad element selector %ld"),
9004 (long) imm_expr.X_add_number);
9005 imm_expr.X_add_number &= max_el;
9006 ip->insn_opcode |= (imm_expr.X_add_number
9010 as_warn(_("Expecting ']' found '%s'"), s);
9016 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9017 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9020 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9027 ip->insn_opcode |= regno << OP_SH_FT;
9030 ip->insn_opcode |= regno << OP_SH_FR;
9040 ip->insn_opcode |= lastregno << OP_SH_FS;
9043 ip->insn_opcode |= lastregno << OP_SH_FT;
9049 my_getExpression (&imm_expr, s);
9050 if (imm_expr.X_op != O_big
9051 && imm_expr.X_op != O_constant)
9052 insn_error = _("absolute expression required");
9053 normalize_constant_expr (&imm_expr);
9058 my_getExpression (&offset_expr, s);
9059 *imm_reloc = BFD_RELOC_32;
9072 unsigned char temp[8];
9074 unsigned int length;
9079 /* These only appear as the last operand in an
9080 instruction, and every instruction that accepts
9081 them in any variant accepts them in all variants.
9082 This means we don't have to worry about backing out
9083 any changes if the instruction does not match.
9085 The difference between them is the size of the
9086 floating point constant and where it goes. For 'F'
9087 and 'L' the constant is 64 bits; for 'f' and 'l' it
9088 is 32 bits. Where the constant is placed is based
9089 on how the MIPS assembler does things:
9092 f -- immediate value
9095 The .lit4 and .lit8 sections are only used if
9096 permitted by the -G argument.
9098 When generating embedded PIC code, we use the
9099 .lit8 section but not the .lit4 section (we can do
9100 .lit4 inline easily; we need to put .lit8
9101 somewhere in the data segment, and using .lit8
9102 permits the linker to eventually combine identical
9105 The code below needs to know whether the target register
9106 is 32 or 64 bits wide. It relies on the fact 'f' and
9107 'F' are used with GPR-based instructions and 'l' and
9108 'L' are used with FPR-based instructions. */
9110 f64 = *args == 'F' || *args == 'L';
9111 using_gprs = *args == 'F' || *args == 'f';
9113 save_in = input_line_pointer;
9114 input_line_pointer = s;
9115 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9117 s = input_line_pointer;
9118 input_line_pointer = save_in;
9119 if (err != NULL && *err != '\0')
9121 as_bad (_("Bad floating point constant: %s"), err);
9122 memset (temp, '\0', sizeof temp);
9123 length = f64 ? 8 : 4;
9126 assert (length == (unsigned) (f64 ? 8 : 4));
9130 && (! USE_GLOBAL_POINTER_OPT
9131 || mips_pic == EMBEDDED_PIC
9132 || g_switch_value < 4
9133 || (temp[0] == 0 && temp[1] == 0)
9134 || (temp[2] == 0 && temp[3] == 0))))
9136 imm_expr.X_op = O_constant;
9137 if (! target_big_endian)
9138 imm_expr.X_add_number = bfd_getl32 (temp);
9140 imm_expr.X_add_number = bfd_getb32 (temp);
9143 && ! mips_disable_float_construction
9144 /* Constants can only be constructed in GPRs and
9145 copied to FPRs if the GPRs are at least as wide
9146 as the FPRs. Force the constant into memory if
9147 we are using 64-bit FPRs but the GPRs are only
9150 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9151 && ((temp[0] == 0 && temp[1] == 0)
9152 || (temp[2] == 0 && temp[3] == 0))
9153 && ((temp[4] == 0 && temp[5] == 0)
9154 || (temp[6] == 0 && temp[7] == 0)))
9156 /* The value is simple enough to load with a couple of
9157 instructions. If using 32-bit registers, set
9158 imm_expr to the high order 32 bits and offset_expr to
9159 the low order 32 bits. Otherwise, set imm_expr to
9160 the entire 64 bit constant. */
9161 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9163 imm_expr.X_op = O_constant;
9164 offset_expr.X_op = O_constant;
9165 if (! target_big_endian)
9167 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9168 offset_expr.X_add_number = bfd_getl32 (temp);
9172 imm_expr.X_add_number = bfd_getb32 (temp);
9173 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9175 if (offset_expr.X_add_number == 0)
9176 offset_expr.X_op = O_absent;
9178 else if (sizeof (imm_expr.X_add_number) > 4)
9180 imm_expr.X_op = O_constant;
9181 if (! target_big_endian)
9182 imm_expr.X_add_number = bfd_getl64 (temp);
9184 imm_expr.X_add_number = bfd_getb64 (temp);
9188 imm_expr.X_op = O_big;
9189 imm_expr.X_add_number = 4;
9190 if (! target_big_endian)
9192 generic_bignum[0] = bfd_getl16 (temp);
9193 generic_bignum[1] = bfd_getl16 (temp + 2);
9194 generic_bignum[2] = bfd_getl16 (temp + 4);
9195 generic_bignum[3] = bfd_getl16 (temp + 6);
9199 generic_bignum[0] = bfd_getb16 (temp + 6);
9200 generic_bignum[1] = bfd_getb16 (temp + 4);
9201 generic_bignum[2] = bfd_getb16 (temp + 2);
9202 generic_bignum[3] = bfd_getb16 (temp);
9208 const char *newname;
9211 /* Switch to the right section. */
9213 subseg = now_subseg;
9216 default: /* unused default case avoids warnings. */
9218 newname = RDATA_SECTION_NAME;
9219 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9220 || mips_pic == EMBEDDED_PIC)
9224 if (mips_pic == EMBEDDED_PIC)
9227 newname = RDATA_SECTION_NAME;
9230 assert (!USE_GLOBAL_POINTER_OPT
9231 || g_switch_value >= 4);
9235 new_seg = subseg_new (newname, (subsegT) 0);
9236 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9237 bfd_set_section_flags (stdoutput, new_seg,
9242 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9243 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9244 && strcmp (TARGET_OS, "elf") != 0)
9245 record_alignment (new_seg, 4);
9247 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9249 as_bad (_("Can't use floating point insn in this section"));
9251 /* Set the argument to the current address in the
9253 offset_expr.X_op = O_symbol;
9254 offset_expr.X_add_symbol =
9255 symbol_new ("L0\001", now_seg,
9256 (valueT) frag_now_fix (), frag_now);
9257 offset_expr.X_add_number = 0;
9259 /* Put the floating point number into the section. */
9260 p = frag_more ((int) length);
9261 memcpy (p, temp, length);
9263 /* Switch back to the original section. */
9264 subseg_set (seg, subseg);
9269 case 'i': /* 16 bit unsigned immediate */
9270 case 'j': /* 16 bit signed immediate */
9271 *imm_reloc = BFD_RELOC_LO16;
9272 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9275 offsetT minval, maxval;
9277 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9278 && strcmp (insn->name, insn[1].name) == 0);
9280 /* If the expression was written as an unsigned number,
9281 only treat it as signed if there are no more
9285 && sizeof (imm_expr.X_add_number) <= 4
9286 && imm_expr.X_op == O_constant
9287 && imm_expr.X_add_number < 0
9288 && imm_expr.X_unsigned
9292 /* For compatibility with older assemblers, we accept
9293 0x8000-0xffff as signed 16-bit numbers when only
9294 signed numbers are allowed. */
9296 minval = 0, maxval = 0xffff;
9298 minval = -0x8000, maxval = 0x7fff;
9300 minval = -0x8000, maxval = 0xffff;
9302 if (imm_expr.X_op != O_constant
9303 || imm_expr.X_add_number < minval
9304 || imm_expr.X_add_number > maxval)
9308 if (imm_expr.X_op == O_constant
9309 || imm_expr.X_op == O_big)
9310 as_bad (_("expression out of range"));
9316 case 'o': /* 16 bit offset */
9317 /* Check whether there is only a single bracketed expression
9318 left. If so, it must be the base register and the
9319 constant must be zero. */
9320 if (*s == '(' && strchr (s + 1, '(') == 0)
9322 offset_expr.X_op = O_constant;
9323 offset_expr.X_add_number = 0;
9327 /* If this value won't fit into a 16 bit offset, then go
9328 find a macro that will generate the 32 bit offset
9330 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9331 && (offset_expr.X_op != O_constant
9332 || offset_expr.X_add_number >= 0x8000
9333 || offset_expr.X_add_number < -0x8000))
9339 case 'p': /* pc relative offset */
9340 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9341 my_getExpression (&offset_expr, s);
9345 case 'u': /* upper 16 bits */
9346 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9347 && imm_expr.X_op == O_constant
9348 && (imm_expr.X_add_number < 0
9349 || imm_expr.X_add_number >= 0x10000))
9350 as_bad (_("lui expression not in range 0..65535"));
9354 case 'a': /* 26 bit address */
9355 my_getExpression (&offset_expr, s);
9357 *offset_reloc = BFD_RELOC_MIPS_JMP;
9360 case 'N': /* 3 bit branch condition code */
9361 case 'M': /* 3 bit compare condition code */
9362 if (strncmp (s, "$fcc", 4) != 0)
9372 while (ISDIGIT (*s));
9374 as_bad (_("Invalid condition code register $fcc%d"), regno);
9375 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9376 || strcmp(str + strlen(str) - 5, "any2f") == 0
9377 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9378 && (regno & 1) != 0)
9379 as_warn(_("Condition code register should be even for %s, was %d"),
9381 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9382 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9383 && (regno & 3) != 0)
9384 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9387 ip->insn_opcode |= regno << OP_SH_BCC;
9389 ip->insn_opcode |= regno << OP_SH_CCC;
9393 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9404 while (ISDIGIT (*s));
9407 c = 8; /* Invalid sel value. */
9410 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9411 ip->insn_opcode |= c;
9415 /* Must be at least one digit. */
9416 my_getExpression (&imm_expr, s);
9417 check_absolute_expr (ip, &imm_expr);
9419 if ((unsigned long) imm_expr.X_add_number
9420 > (unsigned long) OP_MASK_VECBYTE)
9422 as_bad (_("bad byte vector index (%ld)"),
9423 (long) imm_expr.X_add_number);
9424 imm_expr.X_add_number = 0;
9427 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9428 imm_expr.X_op = O_absent;
9433 my_getExpression (&imm_expr, s);
9434 check_absolute_expr (ip, &imm_expr);
9436 if ((unsigned long) imm_expr.X_add_number
9437 > (unsigned long) OP_MASK_VECALIGN)
9439 as_bad (_("bad byte vector index (%ld)"),
9440 (long) imm_expr.X_add_number);
9441 imm_expr.X_add_number = 0;
9444 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9445 imm_expr.X_op = O_absent;
9450 as_bad (_("bad char = '%c'\n"), *args);
9455 /* Args don't match. */
9456 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9457 !strcmp (insn->name, insn[1].name))
9461 insn_error = _("illegal operands");
9466 insn_error = _("illegal operands");
9471 /* This routine assembles an instruction into its binary format when
9472 assembling for the mips16. As a side effect, it sets one of the
9473 global variables imm_reloc or offset_reloc to the type of
9474 relocation to do if one of the operands is an address expression.
9475 It also sets mips16_small and mips16_ext if the user explicitly
9476 requested a small or extended instruction. */
9479 mips16_ip (char *str, struct mips_cl_insn *ip)
9483 struct mips_opcode *insn;
9486 unsigned int lastregno = 0;
9491 mips16_small = FALSE;
9494 for (s = str; ISLOWER (*s); ++s)
9506 if (s[1] == 't' && s[2] == ' ')
9509 mips16_small = TRUE;
9513 else if (s[1] == 'e' && s[2] == ' ')
9522 insn_error = _("unknown opcode");
9526 if (mips_opts.noautoextend && ! mips16_ext)
9527 mips16_small = TRUE;
9529 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9531 insn_error = _("unrecognized opcode");
9538 assert (strcmp (insn->name, str) == 0);
9541 ip->insn_opcode = insn->match;
9542 ip->use_extend = FALSE;
9543 imm_expr.X_op = O_absent;
9544 imm_reloc[0] = BFD_RELOC_UNUSED;
9545 imm_reloc[1] = BFD_RELOC_UNUSED;
9546 imm_reloc[2] = BFD_RELOC_UNUSED;
9547 imm2_expr.X_op = O_absent;
9548 offset_expr.X_op = O_absent;
9549 offset_reloc[0] = BFD_RELOC_UNUSED;
9550 offset_reloc[1] = BFD_RELOC_UNUSED;
9551 offset_reloc[2] = BFD_RELOC_UNUSED;
9552 for (args = insn->args; 1; ++args)
9559 /* In this switch statement we call break if we did not find
9560 a match, continue if we did find a match, or return if we
9569 /* Stuff the immediate value in now, if we can. */
9570 if (imm_expr.X_op == O_constant
9571 && *imm_reloc > BFD_RELOC_UNUSED
9572 && insn->pinfo != INSN_MACRO)
9574 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9575 imm_expr.X_add_number, TRUE, mips16_small,
9576 mips16_ext, &ip->insn_opcode,
9577 &ip->use_extend, &ip->extend);
9578 imm_expr.X_op = O_absent;
9579 *imm_reloc = BFD_RELOC_UNUSED;
9593 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9596 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9612 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9614 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9641 while (ISDIGIT (*s));
9644 as_bad (_("invalid register number (%d)"), regno);
9650 if (s[1] == 'r' && s[2] == 'a')
9655 else if (s[1] == 'f' && s[2] == 'p')
9660 else if (s[1] == 's' && s[2] == 'p')
9665 else if (s[1] == 'g' && s[2] == 'p')
9670 else if (s[1] == 'a' && s[2] == 't')
9675 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9680 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9685 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9698 if (c == 'v' || c == 'w')
9700 regno = mips16_to_32_reg_map[lastregno];
9714 regno = mips32_to_16_reg_map[regno];
9719 regno = ILLEGAL_REG;
9724 regno = ILLEGAL_REG;
9729 regno = ILLEGAL_REG;
9734 if (regno == AT && ! mips_opts.noat)
9735 as_warn (_("used $at without \".set noat\""));
9742 if (regno == ILLEGAL_REG)
9749 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9753 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9756 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9759 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9765 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9768 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9769 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9779 if (strncmp (s, "$pc", 3) == 0)
9803 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9805 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9806 and generate the appropriate reloc. If the text
9807 inside %gprel is not a symbol name with an
9808 optional offset, then we generate a normal reloc
9809 and will probably fail later. */
9810 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9811 if (imm_expr.X_op == O_symbol)
9814 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9816 ip->use_extend = TRUE;
9823 /* Just pick up a normal expression. */
9824 my_getExpression (&imm_expr, s);
9827 if (imm_expr.X_op == O_register)
9829 /* What we thought was an expression turned out to
9832 if (s[0] == '(' && args[1] == '(')
9834 /* It looks like the expression was omitted
9835 before a register indirection, which means
9836 that the expression is implicitly zero. We
9837 still set up imm_expr, so that we handle
9838 explicit extensions correctly. */
9839 imm_expr.X_op = O_constant;
9840 imm_expr.X_add_number = 0;
9841 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9848 /* We need to relax this instruction. */
9849 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9858 /* We use offset_reloc rather than imm_reloc for the PC
9859 relative operands. This lets macros with both
9860 immediate and address operands work correctly. */
9861 my_getExpression (&offset_expr, s);
9863 if (offset_expr.X_op == O_register)
9866 /* We need to relax this instruction. */
9867 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9871 case '6': /* break code */
9872 my_getExpression (&imm_expr, s);
9873 check_absolute_expr (ip, &imm_expr);
9874 if ((unsigned long) imm_expr.X_add_number > 63)
9876 as_warn (_("Invalid value for `%s' (%lu)"),
9878 (unsigned long) imm_expr.X_add_number);
9879 imm_expr.X_add_number &= 0x3f;
9881 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9882 imm_expr.X_op = O_absent;
9886 case 'a': /* 26 bit address */
9887 my_getExpression (&offset_expr, s);
9889 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9890 ip->insn_opcode <<= 16;
9893 case 'l': /* register list for entry macro */
9894 case 'L': /* register list for exit macro */
9904 int freg, reg1, reg2;
9906 while (*s == ' ' || *s == ',')
9910 as_bad (_("can't parse register list"));
9922 while (ISDIGIT (*s))
9944 as_bad (_("invalid register list"));
9949 while (ISDIGIT (*s))
9956 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9961 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9966 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9967 mask |= (reg2 - 3) << 3;
9968 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9969 mask |= (reg2 - 15) << 1;
9970 else if (reg1 == RA && reg2 == RA)
9974 as_bad (_("invalid register list"));
9978 /* The mask is filled in in the opcode table for the
9979 benefit of the disassembler. We remove it before
9980 applying the actual mask. */
9981 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9982 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9986 case 'e': /* extend code */
9987 my_getExpression (&imm_expr, s);
9988 check_absolute_expr (ip, &imm_expr);
9989 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9991 as_warn (_("Invalid value for `%s' (%lu)"),
9993 (unsigned long) imm_expr.X_add_number);
9994 imm_expr.X_add_number &= 0x7ff;
9996 ip->insn_opcode |= imm_expr.X_add_number;
9997 imm_expr.X_op = O_absent;
10007 /* Args don't match. */
10008 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10009 strcmp (insn->name, insn[1].name) == 0)
10016 insn_error = _("illegal operands");
10022 /* This structure holds information we know about a mips16 immediate
10025 struct mips16_immed_operand
10027 /* The type code used in the argument string in the opcode table. */
10029 /* The number of bits in the short form of the opcode. */
10031 /* The number of bits in the extended form of the opcode. */
10033 /* The amount by which the short form is shifted when it is used;
10034 for example, the sw instruction has a shift count of 2. */
10036 /* The amount by which the short form is shifted when it is stored
10037 into the instruction code. */
10039 /* Non-zero if the short form is unsigned. */
10041 /* Non-zero if the extended form is unsigned. */
10043 /* Non-zero if the value is PC relative. */
10047 /* The mips16 immediate operand types. */
10049 static const struct mips16_immed_operand mips16_immed_operands[] =
10051 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10052 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10053 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10054 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10055 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10056 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10057 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10058 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10059 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10060 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10061 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10062 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10063 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10064 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10065 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10066 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10067 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10068 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10069 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10070 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10071 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10074 #define MIPS16_NUM_IMMED \
10075 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10077 /* Handle a mips16 instruction with an immediate value. This or's the
10078 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10079 whether an extended value is needed; if one is needed, it sets
10080 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10081 If SMALL is true, an unextended opcode was explicitly requested.
10082 If EXT is true, an extended opcode was explicitly requested. If
10083 WARN is true, warn if EXT does not match reality. */
10086 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10087 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10088 unsigned long *insn, bfd_boolean *use_extend,
10089 unsigned short *extend)
10091 register const struct mips16_immed_operand *op;
10092 int mintiny, maxtiny;
10093 bfd_boolean needext;
10095 op = mips16_immed_operands;
10096 while (op->type != type)
10099 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10104 if (type == '<' || type == '>' || type == '[' || type == ']')
10107 maxtiny = 1 << op->nbits;
10112 maxtiny = (1 << op->nbits) - 1;
10117 mintiny = - (1 << (op->nbits - 1));
10118 maxtiny = (1 << (op->nbits - 1)) - 1;
10121 /* Branch offsets have an implicit 0 in the lowest bit. */
10122 if (type == 'p' || type == 'q')
10125 if ((val & ((1 << op->shift) - 1)) != 0
10126 || val < (mintiny << op->shift)
10127 || val > (maxtiny << op->shift))
10132 if (warn && ext && ! needext)
10133 as_warn_where (file, line,
10134 _("extended operand requested but not required"));
10135 if (small && needext)
10136 as_bad_where (file, line, _("invalid unextended operand value"));
10138 if (small || (! ext && ! needext))
10142 *use_extend = FALSE;
10143 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10144 insnval <<= op->op_shift;
10149 long minext, maxext;
10155 maxext = (1 << op->extbits) - 1;
10159 minext = - (1 << (op->extbits - 1));
10160 maxext = (1 << (op->extbits - 1)) - 1;
10162 if (val < minext || val > maxext)
10163 as_bad_where (file, line,
10164 _("operand value out of range for instruction"));
10166 *use_extend = TRUE;
10167 if (op->extbits == 16)
10169 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10172 else if (op->extbits == 15)
10174 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10179 extval = ((val & 0x1f) << 6) | (val & 0x20);
10183 *extend = (unsigned short) extval;
10188 static const struct percent_op_match
10191 bfd_reloc_code_real_type reloc;
10194 {"%lo", BFD_RELOC_LO16},
10196 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10197 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10198 {"%call16", BFD_RELOC_MIPS_CALL16},
10199 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10200 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10201 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10202 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10203 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10204 {"%got", BFD_RELOC_MIPS_GOT16},
10205 {"%gp_rel", BFD_RELOC_GPREL16},
10206 {"%half", BFD_RELOC_16},
10207 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10208 {"%higher", BFD_RELOC_MIPS_HIGHER},
10209 {"%neg", BFD_RELOC_MIPS_SUB},
10211 {"%hi", BFD_RELOC_HI16_S}
10215 /* Return true if *STR points to a relocation operator. When returning true,
10216 move *STR over the operator and store its relocation code in *RELOC.
10217 Leave both *STR and *RELOC alone when returning false. */
10220 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10224 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10225 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10227 *str += strlen (percent_op[i].str);
10228 *reloc = percent_op[i].reloc;
10230 /* Check whether the output BFD supports this relocation.
10231 If not, issue an error and fall back on something safe. */
10232 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10234 as_bad ("relocation %s isn't supported by the current ABI",
10235 percent_op[i].str);
10236 *reloc = BFD_RELOC_LO16;
10244 /* Parse string STR as a 16-bit relocatable operand. Store the
10245 expression in *EP and the relocations in the array starting
10246 at RELOC. Return the number of relocation operators used.
10248 On exit, EXPR_END points to the first character after the expression.
10249 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10252 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10255 bfd_reloc_code_real_type reversed_reloc[3];
10256 size_t reloc_index, i;
10257 int crux_depth, str_depth;
10260 /* Search for the start of the main expression, recoding relocations
10261 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10262 of the main expression and with CRUX_DEPTH containing the number
10263 of open brackets at that point. */
10270 crux_depth = str_depth;
10272 /* Skip over whitespace and brackets, keeping count of the number
10274 while (*str == ' ' || *str == '\t' || *str == '(')
10279 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10280 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10282 my_getExpression (ep, crux);
10285 /* Match every open bracket. */
10286 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10290 if (crux_depth > 0)
10291 as_bad ("unclosed '('");
10295 if (reloc_index == 0)
10296 reloc[0] = BFD_RELOC_LO16;
10299 prev_reloc_op_frag = frag_now;
10300 for (i = 0; i < reloc_index; i++)
10301 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10304 return reloc_index;
10308 my_getExpression (expressionS *ep, char *str)
10313 save_in = input_line_pointer;
10314 input_line_pointer = str;
10316 expr_end = input_line_pointer;
10317 input_line_pointer = save_in;
10319 /* If we are in mips16 mode, and this is an expression based on `.',
10320 then we bump the value of the symbol by 1 since that is how other
10321 text symbols are handled. We don't bother to handle complex
10322 expressions, just `.' plus or minus a constant. */
10323 if (mips_opts.mips16
10324 && ep->X_op == O_symbol
10325 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10326 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10327 && symbol_get_frag (ep->X_add_symbol) == frag_now
10328 && symbol_constant_p (ep->X_add_symbol)
10329 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10330 S_SET_VALUE (ep->X_add_symbol, val + 1);
10333 /* Turn a string in input_line_pointer into a floating point constant
10334 of type TYPE, and store the appropriate bytes in *LITP. The number
10335 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10336 returned, or NULL on OK. */
10339 md_atof (int type, char *litP, int *sizeP)
10342 LITTLENUM_TYPE words[4];
10358 return _("bad call to md_atof");
10361 t = atof_ieee (input_line_pointer, type, words);
10363 input_line_pointer = t;
10367 if (! target_big_endian)
10369 for (i = prec - 1; i >= 0; i--)
10371 md_number_to_chars (litP, words[i], 2);
10377 for (i = 0; i < prec; i++)
10379 md_number_to_chars (litP, words[i], 2);
10388 md_number_to_chars (char *buf, valueT val, int n)
10390 if (target_big_endian)
10391 number_to_chars_bigendian (buf, val, n);
10393 number_to_chars_littleendian (buf, val, n);
10397 static int support_64bit_objects(void)
10399 const char **list, **l;
10402 list = bfd_target_list ();
10403 for (l = list; *l != NULL; l++)
10405 /* This is traditional mips */
10406 if (strcmp (*l, "elf64-tradbigmips") == 0
10407 || strcmp (*l, "elf64-tradlittlemips") == 0)
10409 if (strcmp (*l, "elf64-bigmips") == 0
10410 || strcmp (*l, "elf64-littlemips") == 0)
10413 yes = (*l != NULL);
10417 #endif /* OBJ_ELF */
10419 const char *md_shortopts = "O::g::G:";
10421 struct option md_longopts[] =
10423 /* Options which specify architecture. */
10424 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10425 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10426 {"march", required_argument, NULL, OPTION_MARCH},
10427 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10428 {"mtune", required_argument, NULL, OPTION_MTUNE},
10429 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10430 {"mips0", no_argument, NULL, OPTION_MIPS1},
10431 {"mips1", no_argument, NULL, OPTION_MIPS1},
10432 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10433 {"mips2", no_argument, NULL, OPTION_MIPS2},
10434 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10435 {"mips3", no_argument, NULL, OPTION_MIPS3},
10436 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10437 {"mips4", no_argument, NULL, OPTION_MIPS4},
10438 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10439 {"mips5", no_argument, NULL, OPTION_MIPS5},
10440 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10441 {"mips32", no_argument, NULL, OPTION_MIPS32},
10442 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10443 {"mips64", no_argument, NULL, OPTION_MIPS64},
10444 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10445 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10446 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10447 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10449 /* Options which specify Application Specific Extensions (ASEs). */
10450 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10451 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10452 {"mips16", no_argument, NULL, OPTION_MIPS16},
10453 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10454 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10455 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10456 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10457 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10458 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10459 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10460 {"mdmx", no_argument, NULL, OPTION_MDMX},
10461 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10462 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10464 /* Old-style architecture options. Don't add more of these. */
10465 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10466 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10467 {"m4650", no_argument, NULL, OPTION_M4650},
10468 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10469 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10470 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10471 {"m4010", no_argument, NULL, OPTION_M4010},
10472 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10473 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10474 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10475 {"m4100", no_argument, NULL, OPTION_M4100},
10476 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10477 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10478 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10479 {"m3900", no_argument, NULL, OPTION_M3900},
10480 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10481 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10483 /* Options which enable bug fixes. */
10484 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10485 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10486 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10487 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10488 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10489 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10490 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10491 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10492 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10493 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10495 /* Miscellaneous options. */
10496 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10497 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10498 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10499 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10500 {"trap", no_argument, NULL, OPTION_TRAP},
10501 {"no-break", no_argument, NULL, OPTION_TRAP},
10502 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10503 {"break", no_argument, NULL, OPTION_BREAK},
10504 {"no-trap", no_argument, NULL, OPTION_BREAK},
10505 #define OPTION_EB (OPTION_MISC_BASE + 3)
10506 {"EB", no_argument, NULL, OPTION_EB},
10507 #define OPTION_EL (OPTION_MISC_BASE + 4)
10508 {"EL", no_argument, NULL, OPTION_EL},
10509 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10510 {"mfp32", no_argument, NULL, OPTION_FP32},
10511 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10512 {"mgp32", no_argument, NULL, OPTION_GP32},
10513 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10514 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10515 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10516 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10517 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10518 {"mfp64", no_argument, NULL, OPTION_FP64},
10519 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10520 {"mgp64", no_argument, NULL, OPTION_GP64},
10521 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10522 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10523 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10524 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10526 /* ELF-specific options. */
10528 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10529 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10530 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10531 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10532 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10533 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10534 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10535 {"xgot", no_argument, NULL, OPTION_XGOT},
10536 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10537 {"mabi", required_argument, NULL, OPTION_MABI},
10538 #define OPTION_32 (OPTION_ELF_BASE + 4)
10539 {"32", no_argument, NULL, OPTION_32},
10540 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10541 {"n32", no_argument, NULL, OPTION_N32},
10542 #define OPTION_64 (OPTION_ELF_BASE + 6)
10543 {"64", no_argument, NULL, OPTION_64},
10544 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10545 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10546 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10547 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10548 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10549 {"mpdr", no_argument, NULL, OPTION_PDR},
10550 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10551 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10552 #endif /* OBJ_ELF */
10554 {NULL, no_argument, NULL, 0}
10556 size_t md_longopts_size = sizeof (md_longopts);
10558 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10559 NEW_VALUE. Warn if another value was already specified. Note:
10560 we have to defer parsing the -march and -mtune arguments in order
10561 to handle 'from-abi' correctly, since the ABI might be specified
10562 in a later argument. */
10565 mips_set_option_string (const char **string_ptr, const char *new_value)
10567 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10568 as_warn (_("A different %s was already specified, is now %s"),
10569 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10572 *string_ptr = new_value;
10576 md_parse_option (int c, char *arg)
10580 case OPTION_CONSTRUCT_FLOATS:
10581 mips_disable_float_construction = 0;
10584 case OPTION_NO_CONSTRUCT_FLOATS:
10585 mips_disable_float_construction = 1;
10597 target_big_endian = 1;
10601 target_big_endian = 0;
10605 if (arg && arg[1] == '0')
10615 mips_debug = atoi (arg);
10616 /* When the MIPS assembler sees -g or -g2, it does not do
10617 optimizations which limit full symbolic debugging. We take
10618 that to be equivalent to -O0. */
10619 if (mips_debug == 2)
10624 file_mips_isa = ISA_MIPS1;
10628 file_mips_isa = ISA_MIPS2;
10632 file_mips_isa = ISA_MIPS3;
10636 file_mips_isa = ISA_MIPS4;
10640 file_mips_isa = ISA_MIPS5;
10643 case OPTION_MIPS32:
10644 file_mips_isa = ISA_MIPS32;
10647 case OPTION_MIPS32R2:
10648 file_mips_isa = ISA_MIPS32R2;
10651 case OPTION_MIPS64R2:
10652 file_mips_isa = ISA_MIPS64R2;
10655 case OPTION_MIPS64:
10656 file_mips_isa = ISA_MIPS64;
10660 mips_set_option_string (&mips_tune_string, arg);
10664 mips_set_option_string (&mips_arch_string, arg);
10668 mips_set_option_string (&mips_arch_string, "4650");
10669 mips_set_option_string (&mips_tune_string, "4650");
10672 case OPTION_NO_M4650:
10676 mips_set_option_string (&mips_arch_string, "4010");
10677 mips_set_option_string (&mips_tune_string, "4010");
10680 case OPTION_NO_M4010:
10684 mips_set_option_string (&mips_arch_string, "4100");
10685 mips_set_option_string (&mips_tune_string, "4100");
10688 case OPTION_NO_M4100:
10692 mips_set_option_string (&mips_arch_string, "3900");
10693 mips_set_option_string (&mips_tune_string, "3900");
10696 case OPTION_NO_M3900:
10700 mips_opts.ase_mdmx = 1;
10703 case OPTION_NO_MDMX:
10704 mips_opts.ase_mdmx = 0;
10707 case OPTION_MIPS16:
10708 mips_opts.mips16 = 1;
10709 mips_no_prev_insn (FALSE);
10712 case OPTION_NO_MIPS16:
10713 mips_opts.mips16 = 0;
10714 mips_no_prev_insn (FALSE);
10717 case OPTION_MIPS3D:
10718 mips_opts.ase_mips3d = 1;
10721 case OPTION_NO_MIPS3D:
10722 mips_opts.ase_mips3d = 0;
10725 case OPTION_MEMBEDDED_PIC:
10726 mips_pic = EMBEDDED_PIC;
10727 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10729 as_bad (_("-G may not be used with embedded PIC code"));
10732 g_switch_value = 0x7fffffff;
10735 case OPTION_FIX_VR4122:
10736 mips_fix_4122_bugs = 1;
10739 case OPTION_NO_FIX_VR4122:
10740 mips_fix_4122_bugs = 0;
10743 case OPTION_RELAX_BRANCH:
10744 mips_relax_branch = 1;
10747 case OPTION_NO_RELAX_BRANCH:
10748 mips_relax_branch = 0;
10752 /* When generating ELF code, we permit -KPIC and -call_shared to
10753 select SVR4_PIC, and -non_shared to select no PIC. This is
10754 intended to be compatible with Irix 5. */
10755 case OPTION_CALL_SHARED:
10756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10758 as_bad (_("-call_shared is supported only for ELF format"));
10761 mips_pic = SVR4_PIC;
10762 mips_abicalls = TRUE;
10763 if (g_switch_seen && g_switch_value != 0)
10765 as_bad (_("-G may not be used with SVR4 PIC code"));
10768 g_switch_value = 0;
10771 case OPTION_NON_SHARED:
10772 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10774 as_bad (_("-non_shared is supported only for ELF format"));
10778 mips_abicalls = FALSE;
10781 /* The -xgot option tells the assembler to use 32 offsets when
10782 accessing the got in SVR4_PIC mode. It is for Irix
10787 #endif /* OBJ_ELF */
10790 if (! USE_GLOBAL_POINTER_OPT)
10792 as_bad (_("-G is not supported for this configuration"));
10795 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10797 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10801 g_switch_value = atoi (arg);
10806 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10809 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10811 as_bad (_("-32 is supported for ELF format only"));
10814 mips_abi = O32_ABI;
10818 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10820 as_bad (_("-n32 is supported for ELF format only"));
10823 mips_abi = N32_ABI;
10827 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10829 as_bad (_("-64 is supported for ELF format only"));
10832 mips_abi = N64_ABI;
10833 if (! support_64bit_objects())
10834 as_fatal (_("No compiled in support for 64 bit object file format"));
10836 #endif /* OBJ_ELF */
10839 file_mips_gp32 = 1;
10843 file_mips_gp32 = 0;
10847 file_mips_fp32 = 1;
10851 file_mips_fp32 = 0;
10856 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10858 as_bad (_("-mabi is supported for ELF format only"));
10861 if (strcmp (arg, "32") == 0)
10862 mips_abi = O32_ABI;
10863 else if (strcmp (arg, "o64") == 0)
10864 mips_abi = O64_ABI;
10865 else if (strcmp (arg, "n32") == 0)
10866 mips_abi = N32_ABI;
10867 else if (strcmp (arg, "64") == 0)
10869 mips_abi = N64_ABI;
10870 if (! support_64bit_objects())
10871 as_fatal (_("No compiled in support for 64 bit object file "
10874 else if (strcmp (arg, "eabi") == 0)
10875 mips_abi = EABI_ABI;
10878 as_fatal (_("invalid abi -mabi=%s"), arg);
10882 #endif /* OBJ_ELF */
10884 case OPTION_M7000_HILO_FIX:
10885 mips_7000_hilo_fix = TRUE;
10888 case OPTION_MNO_7000_HILO_FIX:
10889 mips_7000_hilo_fix = FALSE;
10893 case OPTION_MDEBUG:
10894 mips_flag_mdebug = TRUE;
10897 case OPTION_NO_MDEBUG:
10898 mips_flag_mdebug = FALSE;
10902 mips_flag_pdr = TRUE;
10905 case OPTION_NO_PDR:
10906 mips_flag_pdr = FALSE;
10908 #endif /* OBJ_ELF */
10917 /* Set up globals to generate code for the ISA or processor
10918 described by INFO. */
10921 mips_set_architecture (const struct mips_cpu_info *info)
10925 file_mips_arch = info->cpu;
10926 mips_opts.arch = info->cpu;
10927 mips_opts.isa = info->isa;
10932 /* Likewise for tuning. */
10935 mips_set_tune (const struct mips_cpu_info *info)
10938 mips_tune = info->cpu;
10943 mips_after_parse_args (void)
10945 const struct mips_cpu_info *arch_info = 0;
10946 const struct mips_cpu_info *tune_info = 0;
10948 /* GP relative stuff not working for PE */
10949 if (strncmp (TARGET_OS, "pe", 2) == 0
10950 && g_switch_value != 0)
10953 as_bad (_("-G not supported in this configuration."));
10954 g_switch_value = 0;
10957 if (mips_abi == NO_ABI)
10958 mips_abi = MIPS_DEFAULT_ABI;
10960 /* The following code determines the architecture and register size.
10961 Similar code was added to GCC 3.3 (see override_options() in
10962 config/mips/mips.c). The GAS and GCC code should be kept in sync
10963 as much as possible. */
10965 if (mips_arch_string != 0)
10966 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10968 if (file_mips_isa != ISA_UNKNOWN)
10970 /* Handle -mipsN. At this point, file_mips_isa contains the
10971 ISA level specified by -mipsN, while arch_info->isa contains
10972 the -march selection (if any). */
10973 if (arch_info != 0)
10975 /* -march takes precedence over -mipsN, since it is more descriptive.
10976 There's no harm in specifying both as long as the ISA levels
10978 if (file_mips_isa != arch_info->isa)
10979 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10980 mips_cpu_info_from_isa (file_mips_isa)->name,
10981 mips_cpu_info_from_isa (arch_info->isa)->name);
10984 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10987 if (arch_info == 0)
10988 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10990 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10991 as_bad ("-march=%s is not compatible with the selected ABI",
10994 mips_set_architecture (arch_info);
10996 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10997 if (mips_tune_string != 0)
10998 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11000 if (tune_info == 0)
11001 mips_set_tune (arch_info);
11003 mips_set_tune (tune_info);
11005 if (file_mips_gp32 >= 0)
11007 /* The user specified the size of the integer registers. Make sure
11008 it agrees with the ABI and ISA. */
11009 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11010 as_bad (_("-mgp64 used with a 32-bit processor"));
11011 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11012 as_bad (_("-mgp32 used with a 64-bit ABI"));
11013 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11014 as_bad (_("-mgp64 used with a 32-bit ABI"));
11018 /* Infer the integer register size from the ABI and processor.
11019 Restrict ourselves to 32-bit registers if that's all the
11020 processor has, or if the ABI cannot handle 64-bit registers. */
11021 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11022 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11025 /* ??? GAS treats single-float processors as though they had 64-bit
11026 float registers (although it complains when double-precision
11027 instructions are used). As things stand, saying they have 32-bit
11028 registers would lead to spurious "register must be even" messages.
11029 So here we assume float registers are always the same size as
11030 integer ones, unless the user says otherwise. */
11031 if (file_mips_fp32 < 0)
11032 file_mips_fp32 = file_mips_gp32;
11034 /* End of GCC-shared inference code. */
11036 /* This flag is set when we have a 64-bit capable CPU but use only
11037 32-bit wide registers. Note that EABI does not use it. */
11038 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11039 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11040 || mips_abi == O32_ABI))
11041 mips_32bitmode = 1;
11043 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11044 as_bad (_("trap exception not supported at ISA 1"));
11046 /* If the selected architecture includes support for ASEs, enable
11047 generation of code for them. */
11048 if (mips_opts.mips16 == -1)
11049 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11050 if (mips_opts.ase_mips3d == -1)
11051 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
11052 if (mips_opts.ase_mdmx == -1)
11053 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
11055 file_mips_isa = mips_opts.isa;
11056 file_ase_mips16 = mips_opts.mips16;
11057 file_ase_mips3d = mips_opts.ase_mips3d;
11058 file_ase_mdmx = mips_opts.ase_mdmx;
11059 mips_opts.gp32 = file_mips_gp32;
11060 mips_opts.fp32 = file_mips_fp32;
11062 if (mips_flag_mdebug < 0)
11064 #ifdef OBJ_MAYBE_ECOFF
11065 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
11066 mips_flag_mdebug = 1;
11068 #endif /* OBJ_MAYBE_ECOFF */
11069 mips_flag_mdebug = 0;
11074 mips_init_after_args (void)
11076 /* initialize opcodes */
11077 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
11078 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
11082 md_pcrel_from (fixS *fixP)
11084 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11085 switch (fixP->fx_r_type)
11087 case BFD_RELOC_16_PCREL_S2:
11088 case BFD_RELOC_MIPS_JMP:
11089 /* Return the address of the delay slot. */
11096 /* This is called before the symbol table is processed. In order to
11097 work with gcc when using mips-tfile, we must keep all local labels.
11098 However, in other cases, we want to discard them. If we were
11099 called with -g, but we didn't see any debugging information, it may
11100 mean that gcc is smuggling debugging information through to
11101 mips-tfile, in which case we must generate all local labels. */
11104 mips_frob_file_before_adjust (void)
11106 #ifndef NO_ECOFF_DEBUGGING
11107 if (ECOFF_DEBUGGING
11109 && ! ecoff_debugging_seen)
11110 flag_keep_locals = 1;
11114 /* Sort any unmatched HI16_S relocs so that they immediately precede
11115 the corresponding LO reloc. This is called before md_apply_fix3 and
11116 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11117 explicit use of the %hi modifier. */
11120 mips_frob_file (void)
11122 struct mips_hi_fixup *l;
11124 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
11126 segment_info_type *seginfo;
11129 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
11131 /* If a GOT16 relocation turns out to be against a global symbol,
11132 there isn't supposed to be a matching LO. */
11133 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11134 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
11137 /* Check quickly whether the next fixup happens to be a matching %lo. */
11138 if (fixup_has_matching_lo_p (l->fixp))
11141 /* Look through the fixups for this segment for a matching %lo.
11142 When we find one, move the %hi just in front of it. We do
11143 this in two passes. In the first pass, we try to find a
11144 unique %lo. In the second pass, we permit multiple %hi
11145 relocs for a single %lo (this is a GNU extension). */
11146 seginfo = seg_info (l->seg);
11147 for (pass = 0; pass < 2; pass++)
11152 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
11154 /* Check whether this is a %lo fixup which matches l->fixp. */
11155 if (f->fx_r_type == BFD_RELOC_LO16
11156 && f->fx_addsy == l->fixp->fx_addsy
11157 && f->fx_offset == l->fixp->fx_offset
11160 || !reloc_needs_lo_p (prev->fx_r_type)
11161 || !fixup_has_matching_lo_p (prev)))
11165 /* Move l->fixp before f. */
11166 for (pf = &seginfo->fix_root;
11168 pf = &(*pf)->fx_next)
11169 assert (*pf != NULL);
11171 *pf = l->fixp->fx_next;
11173 l->fixp->fx_next = f;
11175 seginfo->fix_root = l->fixp;
11177 prev->fx_next = l->fixp;
11188 #if 0 /* GCC code motion plus incomplete dead code elimination
11189 can leave a %hi without a %lo. */
11191 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
11192 _("Unmatched %%hi reloc"));
11198 /* When generating embedded PIC code we need to use a special
11199 relocation to represent the difference of two symbols in the .text
11200 section (switch tables use a difference of this sort). See
11201 include/coff/mips.h for details. This macro checks whether this
11202 fixup requires the special reloc. */
11203 #define SWITCH_TABLE(fixp) \
11204 ((fixp)->fx_r_type == BFD_RELOC_32 \
11205 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11206 && (fixp)->fx_addsy != NULL \
11207 && (fixp)->fx_subsy != NULL \
11208 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11209 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11211 /* When generating embedded PIC code we must keep all PC relative
11212 relocations, in case the linker has to relax a call. We also need
11213 to keep relocations for switch table entries.
11215 We may have combined relocations without symbols in the N32/N64 ABI.
11216 We have to prevent gas from dropping them. */
11219 mips_force_relocation (fixS *fixp)
11221 if (generic_force_reloc (fixp))
11225 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11226 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11227 || fixp->fx_r_type == BFD_RELOC_HI16_S
11228 || fixp->fx_r_type == BFD_RELOC_LO16))
11231 return (mips_pic == EMBEDDED_PIC
11233 || SWITCH_TABLE (fixp)
11234 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11235 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11238 /* This hook is called before a fix is simplified. We don't really
11239 decide whether to skip a fix here. Rather, we turn global symbols
11240 used as branch targets into local symbols, such that they undergo
11241 simplification. We can only do this if the symbol is defined and
11242 it is in the same section as the branch. If this doesn't hold, we
11243 emit a better error message than just saying the relocation is not
11244 valid for the selected object format.
11246 FIXP is the fix-up we're going to try to simplify, SEG is the
11247 segment in which the fix up occurs. The return value should be
11248 non-zero to indicate the fix-up is valid for further
11249 simplifications. */
11252 mips_validate_fix (struct fix *fixP, asection *seg)
11254 /* There's a lot of discussion on whether it should be possible to
11255 use R_MIPS_PC16 to represent branch relocations. The outcome
11256 seems to be that it can, but gas/bfd are very broken in creating
11257 RELA relocations for this, so for now we only accept branches to
11258 symbols in the same section. Anything else is of dubious value,
11259 since there's no guarantee that at link time the symbol would be
11260 in range. Even for branches to local symbols this is arguably
11261 wrong, since it we assume the symbol is not going to be
11262 overridden, which should be possible per ELF library semantics,
11263 but then, there isn't a dynamic relocation that could be used to
11264 this effect, and the target would likely be out of range as well.
11266 Unfortunately, it seems that there is too much code out there
11267 that relies on branches to symbols that are global to be resolved
11268 as if they were local, like the IRIX tools do, so we do it as
11269 well, but with a warning so that people are reminded to fix their
11270 code. If we ever get back to using R_MIPS_PC16 for branch
11271 targets, this entire block should go away (and probably the
11272 whole function). */
11274 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11275 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11276 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11277 && mips_pic != EMBEDDED_PIC)
11278 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11281 if (! S_IS_DEFINED (fixP->fx_addsy))
11283 as_bad_where (fixP->fx_file, fixP->fx_line,
11284 _("Cannot branch to undefined symbol."));
11285 /* Avoid any further errors about this fixup. */
11288 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11290 as_bad_where (fixP->fx_file, fixP->fx_line,
11291 _("Cannot branch to symbol in another section."));
11294 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11296 symbolS *sym = fixP->fx_addsy;
11298 if (mips_pic == SVR4_PIC)
11299 as_warn_where (fixP->fx_file, fixP->fx_line,
11300 _("Pretending global symbol used as branch target is local."));
11302 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11303 S_GET_SEGMENT (sym),
11305 symbol_get_frag (sym));
11306 copy_symbol_attributes (fixP->fx_addsy, sym);
11307 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11308 assert (symbol_resolved_p (sym));
11309 symbol_mark_resolved (fixP->fx_addsy);
11316 /* Apply a fixup to the object file. */
11319 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11323 static int previous_fx_r_type = 0;
11324 reloc_howto_type *howto;
11326 /* We ignore generic BFD relocations we don't know about. */
11327 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11331 assert (fixP->fx_size == 4
11332 || fixP->fx_r_type == BFD_RELOC_16
11333 || fixP->fx_r_type == BFD_RELOC_64
11334 || fixP->fx_r_type == BFD_RELOC_CTOR
11335 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11336 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11337 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11339 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11341 /* We are not done if this is a composite relocation to set up gp. */
11342 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11343 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11344 || (fixP->fx_r_type == BFD_RELOC_64
11345 && (previous_fx_r_type == BFD_RELOC_GPREL32
11346 || previous_fx_r_type == BFD_RELOC_GPREL16))
11347 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11348 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11349 || fixP->fx_r_type == BFD_RELOC_LO16))))
11351 previous_fx_r_type = fixP->fx_r_type;
11353 switch (fixP->fx_r_type)
11355 case BFD_RELOC_MIPS_JMP:
11356 case BFD_RELOC_MIPS_SHIFT5:
11357 case BFD_RELOC_MIPS_SHIFT6:
11358 case BFD_RELOC_MIPS_GOT_DISP:
11359 case BFD_RELOC_MIPS_GOT_PAGE:
11360 case BFD_RELOC_MIPS_GOT_OFST:
11361 case BFD_RELOC_MIPS_SUB:
11362 case BFD_RELOC_MIPS_INSERT_A:
11363 case BFD_RELOC_MIPS_INSERT_B:
11364 case BFD_RELOC_MIPS_DELETE:
11365 case BFD_RELOC_MIPS_HIGHEST:
11366 case BFD_RELOC_MIPS_HIGHER:
11367 case BFD_RELOC_MIPS_SCN_DISP:
11368 case BFD_RELOC_MIPS_REL16:
11369 case BFD_RELOC_MIPS_RELGOT:
11370 case BFD_RELOC_MIPS_JALR:
11371 case BFD_RELOC_HI16:
11372 case BFD_RELOC_HI16_S:
11373 case BFD_RELOC_GPREL16:
11374 case BFD_RELOC_MIPS_LITERAL:
11375 case BFD_RELOC_MIPS_CALL16:
11376 case BFD_RELOC_MIPS_GOT16:
11377 case BFD_RELOC_GPREL32:
11378 case BFD_RELOC_MIPS_GOT_HI16:
11379 case BFD_RELOC_MIPS_GOT_LO16:
11380 case BFD_RELOC_MIPS_CALL_HI16:
11381 case BFD_RELOC_MIPS_CALL_LO16:
11382 case BFD_RELOC_MIPS16_GPREL:
11383 if (fixP->fx_pcrel)
11384 as_bad_where (fixP->fx_file, fixP->fx_line,
11385 _("Invalid PC relative reloc"));
11386 /* Nothing needed to do. The value comes from the reloc entry */
11389 case BFD_RELOC_MIPS16_JMP:
11390 /* We currently always generate a reloc against a symbol, which
11391 means that we don't want an addend even if the symbol is
11396 case BFD_RELOC_PCREL_HI16_S:
11397 /* The addend for this is tricky if it is internal, so we just
11398 do everything here rather than in bfd_install_relocation. */
11399 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11402 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11404 /* For an external symbol adjust by the address to make it
11405 pcrel_offset. We use the address of the RELLO reloc
11406 which follows this one. */
11407 *valP += (fixP->fx_next->fx_frag->fr_address
11408 + fixP->fx_next->fx_where);
11410 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11411 if (target_big_endian)
11413 md_number_to_chars (buf, *valP, 2);
11416 case BFD_RELOC_PCREL_LO16:
11417 /* The addend for this is tricky if it is internal, so we just
11418 do everything here rather than in bfd_install_relocation. */
11419 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11422 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11423 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11424 if (target_big_endian)
11426 md_number_to_chars (buf, *valP, 2);
11430 /* This is handled like BFD_RELOC_32, but we output a sign
11431 extended value if we are only 32 bits. */
11433 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11435 if (8 <= sizeof (valueT))
11436 md_number_to_chars (buf, *valP, 8);
11441 if ((*valP & 0x80000000) != 0)
11445 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11447 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11453 case BFD_RELOC_RVA:
11455 /* If we are deleting this reloc entry, we must fill in the
11456 value now. This can happen if we have a .word which is not
11457 resolved when it appears but is later defined. We also need
11458 to fill in the value if this is an embedded PIC switch table
11461 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11462 md_number_to_chars (buf, *valP, 4);
11466 /* If we are deleting this reloc entry, we must fill in the
11468 assert (fixP->fx_size == 2);
11470 md_number_to_chars (buf, *valP, 2);
11473 case BFD_RELOC_LO16:
11474 /* When handling an embedded PIC switch statement, we can wind
11475 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11478 if (*valP + 0x8000 > 0xffff)
11479 as_bad_where (fixP->fx_file, fixP->fx_line,
11480 _("relocation overflow"));
11481 if (target_big_endian)
11483 md_number_to_chars (buf, *valP, 2);
11487 case BFD_RELOC_16_PCREL_S2:
11488 if ((*valP & 0x3) != 0)
11489 as_bad_where (fixP->fx_file, fixP->fx_line,
11490 _("Branch to odd address (%lx)"), (long) *valP);
11493 * We need to save the bits in the instruction since fixup_segment()
11494 * might be deleting the relocation entry (i.e., a branch within
11495 * the current segment).
11497 if (! fixP->fx_done)
11500 /* update old instruction data */
11501 if (target_big_endian)
11502 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11504 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11506 if (*valP + 0x20000 <= 0x3ffff)
11508 insn |= (*valP >> 2) & 0xffff;
11509 md_number_to_chars (buf, insn, 4);
11511 else if (mips_pic == NO_PIC
11513 && fixP->fx_frag->fr_address >= text_section->vma
11514 && (fixP->fx_frag->fr_address
11515 < text_section->vma + text_section->_raw_size)
11516 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11517 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11518 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11520 /* The branch offset is too large. If this is an
11521 unconditional branch, and we are not generating PIC code,
11522 we can convert it to an absolute jump instruction. */
11523 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11524 insn = 0x0c000000; /* jal */
11526 insn = 0x08000000; /* j */
11527 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11529 fixP->fx_addsy = section_symbol (text_section);
11530 *valP += md_pcrel_from (fixP);
11531 md_number_to_chars (buf, insn, 4);
11535 /* If we got here, we have branch-relaxation disabled,
11536 and there's nothing we can do to fix this instruction
11537 without turning it into a longer sequence. */
11538 as_bad_where (fixP->fx_file, fixP->fx_line,
11539 _("Branch out of range"));
11543 case BFD_RELOC_VTABLE_INHERIT:
11546 && !S_IS_DEFINED (fixP->fx_addsy)
11547 && !S_IS_WEAK (fixP->fx_addsy))
11548 S_SET_WEAK (fixP->fx_addsy);
11551 case BFD_RELOC_VTABLE_ENTRY:
11559 /* Remember value for tc_gen_reloc. */
11560 fixP->fx_addnumber = *valP;
11565 printInsn (unsigned long oc)
11567 const struct mips_opcode *p;
11568 int treg, sreg, dreg, shamt;
11573 for (i = 0; i < NUMOPCODES; ++i)
11575 p = &mips_opcodes[i];
11576 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11578 printf ("%08lx %s\t", oc, p->name);
11579 treg = (oc >> 16) & 0x1f;
11580 sreg = (oc >> 21) & 0x1f;
11581 dreg = (oc >> 11) & 0x1f;
11582 shamt = (oc >> 6) & 0x1f;
11584 for (args = p->args;; ++args)
11595 printf ("%c", *args);
11599 assert (treg == sreg);
11600 printf ("$%d,$%d", treg, sreg);
11605 printf ("$%d", dreg);
11610 printf ("$%d", treg);
11614 printf ("0x%x", treg);
11619 printf ("$%d", sreg);
11623 printf ("0x%08lx", oc & 0x1ffffff);
11630 printf ("%d", imm);
11635 printf ("$%d", shamt);
11646 printf (_("%08lx UNDEFINED\n"), oc);
11657 name = input_line_pointer;
11658 c = get_symbol_end ();
11659 p = (symbolS *) symbol_find_or_make (name);
11660 *input_line_pointer = c;
11664 /* Align the current frag to a given power of two. The MIPS assembler
11665 also automatically adjusts any preceding label. */
11668 mips_align (int to, int fill, symbolS *label)
11670 mips_emit_delays (FALSE);
11671 frag_align (to, fill, 0);
11672 record_alignment (now_seg, to);
11675 assert (S_GET_SEGMENT (label) == now_seg);
11676 symbol_set_frag (label, frag_now);
11677 S_SET_VALUE (label, (valueT) frag_now_fix ());
11681 /* Align to a given power of two. .align 0 turns off the automatic
11682 alignment used by the data creating pseudo-ops. */
11685 s_align (int x ATTRIBUTE_UNUSED)
11688 register long temp_fill;
11689 long max_alignment = 15;
11693 o Note that the assembler pulls down any immediately preceding label
11694 to the aligned address.
11695 o It's not documented but auto alignment is reinstated by
11696 a .align pseudo instruction.
11697 o Note also that after auto alignment is turned off the mips assembler
11698 issues an error on attempt to assemble an improperly aligned data item.
11703 temp = get_absolute_expression ();
11704 if (temp > max_alignment)
11705 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11708 as_warn (_("Alignment negative: 0 assumed."));
11711 if (*input_line_pointer == ',')
11713 ++input_line_pointer;
11714 temp_fill = get_absolute_expression ();
11721 mips_align (temp, (int) temp_fill,
11722 insn_labels != NULL ? insn_labels->label : NULL);
11729 demand_empty_rest_of_line ();
11733 mips_flush_pending_output (void)
11735 mips_emit_delays (FALSE);
11736 mips_clear_insn_labels ();
11740 s_change_sec (int sec)
11744 /* When generating embedded PIC code, we only use the .text, .lit8,
11745 .sdata and .sbss sections. We change the .data and .rdata
11746 pseudo-ops to use .sdata. */
11747 if (mips_pic == EMBEDDED_PIC
11748 && (sec == 'd' || sec == 'r'))
11752 /* The ELF backend needs to know that we are changing sections, so
11753 that .previous works correctly. We could do something like check
11754 for an obj_section_change_hook macro, but that might be confusing
11755 as it would not be appropriate to use it in the section changing
11756 functions in read.c, since obj-elf.c intercepts those. FIXME:
11757 This should be cleaner, somehow. */
11758 obj_elf_section_change_hook ();
11761 mips_emit_delays (FALSE);
11771 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11772 demand_empty_rest_of_line ();
11776 if (USE_GLOBAL_POINTER_OPT)
11778 seg = subseg_new (RDATA_SECTION_NAME,
11779 (subsegT) get_absolute_expression ());
11780 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11782 bfd_set_section_flags (stdoutput, seg,
11788 if (strcmp (TARGET_OS, "elf") != 0)
11789 record_alignment (seg, 4);
11791 demand_empty_rest_of_line ();
11795 as_bad (_("No read only data section in this object file format"));
11796 demand_empty_rest_of_line ();
11802 if (USE_GLOBAL_POINTER_OPT)
11804 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11805 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11807 bfd_set_section_flags (stdoutput, seg,
11808 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11810 if (strcmp (TARGET_OS, "elf") != 0)
11811 record_alignment (seg, 4);
11813 demand_empty_rest_of_line ();
11818 as_bad (_("Global pointers not supported; recompile -G 0"));
11819 demand_empty_rest_of_line ();
11828 s_change_section (int ignore ATTRIBUTE_UNUSED)
11831 char *section_name;
11836 int section_entry_size;
11837 int section_alignment;
11839 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11842 section_name = input_line_pointer;
11843 c = get_symbol_end ();
11845 next_c = *(input_line_pointer + 1);
11847 /* Do we have .section Name<,"flags">? */
11848 if (c != ',' || (c == ',' && next_c == '"'))
11850 /* just after name is now '\0'. */
11851 *input_line_pointer = c;
11852 input_line_pointer = section_name;
11853 obj_elf_section (ignore);
11856 input_line_pointer++;
11858 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11860 section_type = get_absolute_expression ();
11863 if (*input_line_pointer++ == ',')
11864 section_flag = get_absolute_expression ();
11867 if (*input_line_pointer++ == ',')
11868 section_entry_size = get_absolute_expression ();
11870 section_entry_size = 0;
11871 if (*input_line_pointer++ == ',')
11872 section_alignment = get_absolute_expression ();
11874 section_alignment = 0;
11876 section_name = xstrdup (section_name);
11878 /* When using the generic form of .section (as implemented by obj-elf.c),
11879 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11880 traditionally had to fall back on the more common @progbits instead.
11882 There's nothing really harmful in this, since bfd will correct
11883 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11884 means that, for backwards compatibiltiy, the special_section entries
11885 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11887 Even so, we shouldn't force users of the MIPS .section syntax to
11888 incorrectly label the sections as SHT_PROGBITS. The best compromise
11889 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11890 generic type-checking code. */
11891 if (section_type == SHT_MIPS_DWARF)
11892 section_type = SHT_PROGBITS;
11894 obj_elf_change_section (section_name, section_type, section_flag,
11895 section_entry_size, 0, 0, 0);
11897 if (now_seg->name != section_name)
11898 free (section_name);
11899 #endif /* OBJ_ELF */
11903 mips_enable_auto_align (void)
11909 s_cons (int log_size)
11913 label = insn_labels != NULL ? insn_labels->label : NULL;
11914 mips_emit_delays (FALSE);
11915 if (log_size > 0 && auto_align)
11916 mips_align (log_size, 0, label);
11917 mips_clear_insn_labels ();
11918 cons (1 << log_size);
11922 s_float_cons (int type)
11926 label = insn_labels != NULL ? insn_labels->label : NULL;
11928 mips_emit_delays (FALSE);
11933 mips_align (3, 0, label);
11935 mips_align (2, 0, label);
11938 mips_clear_insn_labels ();
11943 /* Handle .globl. We need to override it because on Irix 5 you are
11946 where foo is an undefined symbol, to mean that foo should be
11947 considered to be the address of a function. */
11950 s_mips_globl (int x ATTRIBUTE_UNUSED)
11957 name = input_line_pointer;
11958 c = get_symbol_end ();
11959 symbolP = symbol_find_or_make (name);
11960 *input_line_pointer = c;
11961 SKIP_WHITESPACE ();
11963 /* On Irix 5, every global symbol that is not explicitly labelled as
11964 being a function is apparently labelled as being an object. */
11967 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11972 secname = input_line_pointer;
11973 c = get_symbol_end ();
11974 sec = bfd_get_section_by_name (stdoutput, secname);
11976 as_bad (_("%s: no such section"), secname);
11977 *input_line_pointer = c;
11979 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11980 flag = BSF_FUNCTION;
11983 symbol_get_bfdsym (symbolP)->flags |= flag;
11985 S_SET_EXTERNAL (symbolP);
11986 demand_empty_rest_of_line ();
11990 s_option (int x ATTRIBUTE_UNUSED)
11995 opt = input_line_pointer;
11996 c = get_symbol_end ();
12000 /* FIXME: What does this mean? */
12002 else if (strncmp (opt, "pic", 3) == 0)
12006 i = atoi (opt + 3);
12011 mips_pic = SVR4_PIC;
12012 mips_abicalls = TRUE;
12015 as_bad (_(".option pic%d not supported"), i);
12017 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
12019 if (g_switch_seen && g_switch_value != 0)
12020 as_warn (_("-G may not be used with SVR4 PIC code"));
12021 g_switch_value = 0;
12022 bfd_set_gp_size (stdoutput, 0);
12026 as_warn (_("Unrecognized option \"%s\""), opt);
12028 *input_line_pointer = c;
12029 demand_empty_rest_of_line ();
12032 /* This structure is used to hold a stack of .set values. */
12034 struct mips_option_stack
12036 struct mips_option_stack *next;
12037 struct mips_set_options options;
12040 static struct mips_option_stack *mips_opts_stack;
12042 /* Handle the .set pseudo-op. */
12045 s_mipsset (int x ATTRIBUTE_UNUSED)
12047 char *name = input_line_pointer, ch;
12049 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12050 ++input_line_pointer;
12051 ch = *input_line_pointer;
12052 *input_line_pointer = '\0';
12054 if (strcmp (name, "reorder") == 0)
12056 if (mips_opts.noreorder && prev_nop_frag != NULL)
12058 /* If we still have pending nops, we can discard them. The
12059 usual nop handling will insert any that are still
12061 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12062 * (mips_opts.mips16 ? 2 : 4));
12063 prev_nop_frag = NULL;
12065 mips_opts.noreorder = 0;
12067 else if (strcmp (name, "noreorder") == 0)
12069 mips_emit_delays (TRUE);
12070 mips_opts.noreorder = 1;
12071 mips_any_noreorder = 1;
12073 else if (strcmp (name, "at") == 0)
12075 mips_opts.noat = 0;
12077 else if (strcmp (name, "noat") == 0)
12079 mips_opts.noat = 1;
12081 else if (strcmp (name, "macro") == 0)
12083 mips_opts.warn_about_macros = 0;
12085 else if (strcmp (name, "nomacro") == 0)
12087 if (mips_opts.noreorder == 0)
12088 as_bad (_("`noreorder' must be set before `nomacro'"));
12089 mips_opts.warn_about_macros = 1;
12091 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12093 mips_opts.nomove = 0;
12095 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12097 mips_opts.nomove = 1;
12099 else if (strcmp (name, "bopt") == 0)
12101 mips_opts.nobopt = 0;
12103 else if (strcmp (name, "nobopt") == 0)
12105 mips_opts.nobopt = 1;
12107 else if (strcmp (name, "mips16") == 0
12108 || strcmp (name, "MIPS-16") == 0)
12109 mips_opts.mips16 = 1;
12110 else if (strcmp (name, "nomips16") == 0
12111 || strcmp (name, "noMIPS-16") == 0)
12112 mips_opts.mips16 = 0;
12113 else if (strcmp (name, "mips3d") == 0)
12114 mips_opts.ase_mips3d = 1;
12115 else if (strcmp (name, "nomips3d") == 0)
12116 mips_opts.ase_mips3d = 0;
12117 else if (strcmp (name, "mdmx") == 0)
12118 mips_opts.ase_mdmx = 1;
12119 else if (strcmp (name, "nomdmx") == 0)
12120 mips_opts.ase_mdmx = 0;
12121 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12125 /* Permit the user to change the ISA and architecture on the fly.
12126 Needless to say, misuse can cause serious problems. */
12127 if (strcmp (name, "mips0") == 0)
12130 mips_opts.isa = file_mips_isa;
12132 else if (strcmp (name, "mips1") == 0)
12133 mips_opts.isa = ISA_MIPS1;
12134 else if (strcmp (name, "mips2") == 0)
12135 mips_opts.isa = ISA_MIPS2;
12136 else if (strcmp (name, "mips3") == 0)
12137 mips_opts.isa = ISA_MIPS3;
12138 else if (strcmp (name, "mips4") == 0)
12139 mips_opts.isa = ISA_MIPS4;
12140 else if (strcmp (name, "mips5") == 0)
12141 mips_opts.isa = ISA_MIPS5;
12142 else if (strcmp (name, "mips32") == 0)
12143 mips_opts.isa = ISA_MIPS32;
12144 else if (strcmp (name, "mips32r2") == 0)
12145 mips_opts.isa = ISA_MIPS32R2;
12146 else if (strcmp (name, "mips64") == 0)
12147 mips_opts.isa = ISA_MIPS64;
12148 else if (strcmp (name, "mips64r2") == 0)
12149 mips_opts.isa = ISA_MIPS64R2;
12150 else if (strcmp (name, "arch=default") == 0)
12153 mips_opts.arch = file_mips_arch;
12154 mips_opts.isa = file_mips_isa;
12156 else if (strncmp (name, "arch=", 5) == 0)
12158 const struct mips_cpu_info *p;
12160 p = mips_parse_cpu("internal use", name + 5);
12162 as_bad (_("unknown architecture %s"), name + 5);
12165 mips_opts.arch = p->cpu;
12166 mips_opts.isa = p->isa;
12170 as_bad (_("unknown ISA level %s"), name + 4);
12172 switch (mips_opts.isa)
12180 mips_opts.gp32 = 1;
12181 mips_opts.fp32 = 1;
12188 mips_opts.gp32 = 0;
12189 mips_opts.fp32 = 0;
12192 as_bad (_("unknown ISA level %s"), name + 4);
12197 mips_opts.gp32 = file_mips_gp32;
12198 mips_opts.fp32 = file_mips_fp32;
12201 else if (strcmp (name, "autoextend") == 0)
12202 mips_opts.noautoextend = 0;
12203 else if (strcmp (name, "noautoextend") == 0)
12204 mips_opts.noautoextend = 1;
12205 else if (strcmp (name, "push") == 0)
12207 struct mips_option_stack *s;
12209 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12210 s->next = mips_opts_stack;
12211 s->options = mips_opts;
12212 mips_opts_stack = s;
12214 else if (strcmp (name, "pop") == 0)
12216 struct mips_option_stack *s;
12218 s = mips_opts_stack;
12220 as_bad (_(".set pop with no .set push"));
12223 /* If we're changing the reorder mode we need to handle
12224 delay slots correctly. */
12225 if (s->options.noreorder && ! mips_opts.noreorder)
12226 mips_emit_delays (TRUE);
12227 else if (! s->options.noreorder && mips_opts.noreorder)
12229 if (prev_nop_frag != NULL)
12231 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12232 * (mips_opts.mips16 ? 2 : 4));
12233 prev_nop_frag = NULL;
12237 mips_opts = s->options;
12238 mips_opts_stack = s->next;
12244 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12246 *input_line_pointer = ch;
12247 demand_empty_rest_of_line ();
12250 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12251 .option pic2. It means to generate SVR4 PIC calls. */
12254 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12256 mips_pic = SVR4_PIC;
12257 mips_abicalls = TRUE;
12258 if (USE_GLOBAL_POINTER_OPT)
12260 if (g_switch_seen && g_switch_value != 0)
12261 as_warn (_("-G may not be used with SVR4 PIC code"));
12262 g_switch_value = 0;
12264 bfd_set_gp_size (stdoutput, 0);
12265 demand_empty_rest_of_line ();
12268 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12269 PIC code. It sets the $gp register for the function based on the
12270 function address, which is in the register named in the argument.
12271 This uses a relocation against _gp_disp, which is handled specially
12272 by the linker. The result is:
12273 lui $gp,%hi(_gp_disp)
12274 addiu $gp,$gp,%lo(_gp_disp)
12275 addu $gp,$gp,.cpload argument
12276 The .cpload argument is normally $25 == $t9. */
12279 s_cpload (int ignore ATTRIBUTE_UNUSED)
12284 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12285 .cpload is ignored. */
12286 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12292 /* .cpload should be in a .set noreorder section. */
12293 if (mips_opts.noreorder == 0)
12294 as_warn (_(".cpload not in noreorder section"));
12296 ex.X_op = O_symbol;
12297 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12298 ex.X_op_symbol = NULL;
12299 ex.X_add_number = 0;
12301 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12302 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12305 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12306 macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
12307 mips_gp_register, BFD_RELOC_LO16);
12309 macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
12310 mips_gp_register, tc_get_register (0));
12313 demand_empty_rest_of_line ();
12316 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12317 .cpsetup $reg1, offset|$reg2, label
12319 If offset is given, this results in:
12320 sd $gp, offset($sp)
12321 lui $gp, %hi(%neg(%gp_rel(label)))
12322 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12323 daddu $gp, $gp, $reg1
12325 If $reg2 is given, this results in:
12326 daddu $reg2, $gp, $0
12327 lui $gp, %hi(%neg(%gp_rel(label)))
12328 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12329 daddu $gp, $gp, $reg1
12330 $reg1 is normally $25 == $t9. */
12332 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12334 expressionS ex_off;
12335 expressionS ex_sym;
12340 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12341 We also need NewABI support. */
12342 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12348 reg1 = tc_get_register (0);
12349 SKIP_WHITESPACE ();
12350 if (*input_line_pointer != ',')
12352 as_bad (_("missing argument separator ',' for .cpsetup"));
12356 ++input_line_pointer;
12357 SKIP_WHITESPACE ();
12358 if (*input_line_pointer == '$')
12360 mips_cpreturn_register = tc_get_register (0);
12361 mips_cpreturn_offset = -1;
12365 mips_cpreturn_offset = get_absolute_expression ();
12366 mips_cpreturn_register = -1;
12368 SKIP_WHITESPACE ();
12369 if (*input_line_pointer != ',')
12371 as_bad (_("missing argument separator ',' for .cpsetup"));
12375 ++input_line_pointer;
12376 SKIP_WHITESPACE ();
12377 expression (&ex_sym);
12380 if (mips_cpreturn_register == -1)
12382 ex_off.X_op = O_constant;
12383 ex_off.X_add_symbol = NULL;
12384 ex_off.X_op_symbol = NULL;
12385 ex_off.X_add_number = mips_cpreturn_offset;
12387 macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
12388 BFD_RELOC_LO16, SP);
12391 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
12392 mips_gp_register, 0);
12394 /* Ensure there's room for the next two instructions, so that `f'
12395 doesn't end up with an address in the wrong frag. */
12398 macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12399 BFD_RELOC_GPREL16);
12400 fix_new (frag_now, f - frag_now->fr_literal,
12401 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12402 fix_new (frag_now, f - frag_now->fr_literal,
12403 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12406 macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
12407 mips_gp_register, BFD_RELOC_GPREL16);
12408 fix_new (frag_now, f - frag_now->fr_literal,
12409 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12410 fix_new (frag_now, f - frag_now->fr_literal,
12411 4, NULL, 0, 0, BFD_RELOC_LO16);
12413 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12414 mips_gp_register, reg1);
12417 demand_empty_rest_of_line ();
12421 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12423 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12424 .cplocal is ignored. */
12425 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12431 mips_gp_register = tc_get_register (0);
12432 demand_empty_rest_of_line ();
12435 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12436 offset from $sp. The offset is remembered, and after making a PIC
12437 call $gp is restored from that location. */
12440 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12445 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12446 .cprestore is ignored. */
12447 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12453 mips_cprestore_offset = get_absolute_expression ();
12454 mips_cprestore_valid = 1;
12456 ex.X_op = O_constant;
12457 ex.X_add_symbol = NULL;
12458 ex.X_op_symbol = NULL;
12459 ex.X_add_number = mips_cprestore_offset;
12462 macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
12463 mips_gp_register, SP, HAVE_64BIT_ADDRESSES);
12466 demand_empty_rest_of_line ();
12469 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12470 was given in the preceding .cpsetup, it results in:
12471 ld $gp, offset($sp)
12473 If a register $reg2 was given there, it results in:
12474 daddu $gp, $reg2, $0
12477 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12482 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12483 We also need NewABI support. */
12484 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12491 if (mips_cpreturn_register == -1)
12493 ex.X_op = O_constant;
12494 ex.X_add_symbol = NULL;
12495 ex.X_op_symbol = NULL;
12496 ex.X_add_number = mips_cpreturn_offset;
12498 macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
12499 BFD_RELOC_LO16, SP);
12502 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
12503 mips_cpreturn_register, 0);
12506 demand_empty_rest_of_line ();
12509 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12510 code. It sets the offset to use in gp_rel relocations. */
12513 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12515 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12516 We also need NewABI support. */
12517 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12523 mips_gprel_offset = get_absolute_expression ();
12525 demand_empty_rest_of_line ();
12528 /* Handle the .gpword pseudo-op. This is used when generating PIC
12529 code. It generates a 32 bit GP relative reloc. */
12532 s_gpword (int ignore ATTRIBUTE_UNUSED)
12538 /* When not generating PIC code, this is treated as .word. */
12539 if (mips_pic != SVR4_PIC)
12545 label = insn_labels != NULL ? insn_labels->label : NULL;
12546 mips_emit_delays (TRUE);
12548 mips_align (2, 0, label);
12549 mips_clear_insn_labels ();
12553 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12555 as_bad (_("Unsupported use of .gpword"));
12556 ignore_rest_of_line ();
12560 md_number_to_chars (p, 0, 4);
12561 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12562 BFD_RELOC_GPREL32);
12564 demand_empty_rest_of_line ();
12568 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12574 /* When not generating PIC code, this is treated as .dword. */
12575 if (mips_pic != SVR4_PIC)
12581 label = insn_labels != NULL ? insn_labels->label : NULL;
12582 mips_emit_delays (TRUE);
12584 mips_align (3, 0, label);
12585 mips_clear_insn_labels ();
12589 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12591 as_bad (_("Unsupported use of .gpdword"));
12592 ignore_rest_of_line ();
12596 md_number_to_chars (p, 0, 8);
12597 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12598 BFD_RELOC_GPREL32);
12600 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12601 ex.X_op = O_absent;
12602 ex.X_add_symbol = 0;
12603 ex.X_add_number = 0;
12604 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12607 demand_empty_rest_of_line ();
12610 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12611 tables in SVR4 PIC code. */
12614 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12619 /* This is ignored when not generating SVR4 PIC code. */
12620 if (mips_pic != SVR4_PIC)
12626 /* Add $gp to the register named as an argument. */
12628 reg = tc_get_register (0);
12629 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
12630 reg, reg, mips_gp_register);
12633 demand_empty_rest_of_line ();
12636 /* Handle the .insn pseudo-op. This marks instruction labels in
12637 mips16 mode. This permits the linker to handle them specially,
12638 such as generating jalx instructions when needed. We also make
12639 them odd for the duration of the assembly, in order to generate the
12640 right sort of code. We will make them even in the adjust_symtab
12641 routine, while leaving them marked. This is convenient for the
12642 debugger and the disassembler. The linker knows to make them odd
12646 s_insn (int ignore ATTRIBUTE_UNUSED)
12648 mips16_mark_labels ();
12650 demand_empty_rest_of_line ();
12653 /* Handle a .stabn directive. We need these in order to mark a label
12654 as being a mips16 text label correctly. Sometimes the compiler
12655 will emit a label, followed by a .stabn, and then switch sections.
12656 If the label and .stabn are in mips16 mode, then the label is
12657 really a mips16 text label. */
12660 s_mips_stab (int type)
12663 mips16_mark_labels ();
12668 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12672 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12679 name = input_line_pointer;
12680 c = get_symbol_end ();
12681 symbolP = symbol_find_or_make (name);
12682 S_SET_WEAK (symbolP);
12683 *input_line_pointer = c;
12685 SKIP_WHITESPACE ();
12687 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12689 if (S_IS_DEFINED (symbolP))
12691 as_bad ("ignoring attempt to redefine symbol %s",
12692 S_GET_NAME (symbolP));
12693 ignore_rest_of_line ();
12697 if (*input_line_pointer == ',')
12699 ++input_line_pointer;
12700 SKIP_WHITESPACE ();
12704 if (exp.X_op != O_symbol)
12706 as_bad ("bad .weakext directive");
12707 ignore_rest_of_line ();
12710 symbol_set_value_expression (symbolP, &exp);
12713 demand_empty_rest_of_line ();
12716 /* Parse a register string into a number. Called from the ECOFF code
12717 to parse .frame. The argument is non-zero if this is the frame
12718 register, so that we can record it in mips_frame_reg. */
12721 tc_get_register (int frame)
12725 SKIP_WHITESPACE ();
12726 if (*input_line_pointer++ != '$')
12728 as_warn (_("expected `$'"));
12731 else if (ISDIGIT (*input_line_pointer))
12733 reg = get_absolute_expression ();
12734 if (reg < 0 || reg >= 32)
12736 as_warn (_("Bad register number"));
12742 if (strncmp (input_line_pointer, "ra", 2) == 0)
12745 input_line_pointer += 2;
12747 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12750 input_line_pointer += 2;
12752 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12755 input_line_pointer += 2;
12757 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12760 input_line_pointer += 2;
12762 else if (strncmp (input_line_pointer, "at", 2) == 0)
12765 input_line_pointer += 2;
12767 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12770 input_line_pointer += 3;
12772 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12775 input_line_pointer += 3;
12777 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12780 input_line_pointer += 4;
12784 as_warn (_("Unrecognized register name"));
12786 while (ISALNUM(*input_line_pointer))
12787 input_line_pointer++;
12792 mips_frame_reg = reg != 0 ? reg : SP;
12793 mips_frame_reg_valid = 1;
12794 mips_cprestore_valid = 0;
12800 md_section_align (asection *seg, valueT addr)
12802 int align = bfd_get_section_alignment (stdoutput, seg);
12805 /* We don't need to align ELF sections to the full alignment.
12806 However, Irix 5 may prefer that we align them at least to a 16
12807 byte boundary. We don't bother to align the sections if we are
12808 targeted for an embedded system. */
12809 if (strcmp (TARGET_OS, "elf") == 0)
12815 return ((addr + (1 << align) - 1) & (-1 << align));
12818 /* Utility routine, called from above as well. If called while the
12819 input file is still being read, it's only an approximation. (For
12820 example, a symbol may later become defined which appeared to be
12821 undefined earlier.) */
12824 nopic_need_relax (symbolS *sym, int before_relaxing)
12829 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12831 const char *symname;
12834 /* Find out whether this symbol can be referenced off the $gp
12835 register. It can be if it is smaller than the -G size or if
12836 it is in the .sdata or .sbss section. Certain symbols can
12837 not be referenced off the $gp, although it appears as though
12839 symname = S_GET_NAME (sym);
12840 if (symname != (const char *) NULL
12841 && (strcmp (symname, "eprol") == 0
12842 || strcmp (symname, "etext") == 0
12843 || strcmp (symname, "_gp") == 0
12844 || strcmp (symname, "edata") == 0
12845 || strcmp (symname, "_fbss") == 0
12846 || strcmp (symname, "_fdata") == 0
12847 || strcmp (symname, "_ftext") == 0
12848 || strcmp (symname, "end") == 0
12849 || strcmp (symname, "_gp_disp") == 0))
12851 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12853 #ifndef NO_ECOFF_DEBUGGING
12854 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12855 && (symbol_get_obj (sym)->ecoff_extern_size
12856 <= g_switch_value))
12858 /* We must defer this decision until after the whole
12859 file has been read, since there might be a .extern
12860 after the first use of this symbol. */
12861 || (before_relaxing
12862 #ifndef NO_ECOFF_DEBUGGING
12863 && symbol_get_obj (sym)->ecoff_extern_size == 0
12865 && S_GET_VALUE (sym) == 0)
12866 || (S_GET_VALUE (sym) != 0
12867 && S_GET_VALUE (sym) <= g_switch_value)))
12871 const char *segname;
12873 segname = segment_name (S_GET_SEGMENT (sym));
12874 assert (strcmp (segname, ".lit8") != 0
12875 && strcmp (segname, ".lit4") != 0);
12876 change = (strcmp (segname, ".sdata") != 0
12877 && strcmp (segname, ".sbss") != 0
12878 && strncmp (segname, ".sdata.", 7) != 0
12879 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12884 /* We are not optimizing for the $gp register. */
12889 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12892 pic_need_relax (symbolS *sym, asection *segtype)
12895 bfd_boolean linkonce;
12897 /* Handle the case of a symbol equated to another symbol. */
12898 while (symbol_equated_reloc_p (sym))
12902 /* It's possible to get a loop here in a badly written
12904 n = symbol_get_value_expression (sym)->X_add_symbol;
12910 symsec = S_GET_SEGMENT (sym);
12912 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12914 if (symsec != segtype && ! S_IS_LOCAL (sym))
12916 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12920 /* The GNU toolchain uses an extension for ELF: a section
12921 beginning with the magic string .gnu.linkonce is a linkonce
12923 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12924 sizeof ".gnu.linkonce" - 1) == 0)
12928 /* This must duplicate the test in adjust_reloc_syms. */
12929 return (symsec != &bfd_und_section
12930 && symsec != &bfd_abs_section
12931 && ! bfd_is_com_section (symsec)
12934 /* A global or weak symbol is treated as external. */
12935 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12936 || (! S_IS_WEAK (sym)
12937 && (! S_IS_EXTERNAL (sym)
12938 || mips_pic == EMBEDDED_PIC)))
12944 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12945 extended opcode. SEC is the section the frag is in. */
12948 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12951 register const struct mips16_immed_operand *op;
12953 int mintiny, maxtiny;
12957 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12959 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12962 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12963 op = mips16_immed_operands;
12964 while (op->type != type)
12967 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12972 if (type == '<' || type == '>' || type == '[' || type == ']')
12975 maxtiny = 1 << op->nbits;
12980 maxtiny = (1 << op->nbits) - 1;
12985 mintiny = - (1 << (op->nbits - 1));
12986 maxtiny = (1 << (op->nbits - 1)) - 1;
12989 sym_frag = symbol_get_frag (fragp->fr_symbol);
12990 val = S_GET_VALUE (fragp->fr_symbol);
12991 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12997 /* We won't have the section when we are called from
12998 mips_relax_frag. However, we will always have been called
12999 from md_estimate_size_before_relax first. If this is a
13000 branch to a different section, we mark it as such. If SEC is
13001 NULL, and the frag is not marked, then it must be a branch to
13002 the same section. */
13005 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13010 /* Must have been called from md_estimate_size_before_relax. */
13013 fragp->fr_subtype =
13014 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13016 /* FIXME: We should support this, and let the linker
13017 catch branches and loads that are out of range. */
13018 as_bad_where (fragp->fr_file, fragp->fr_line,
13019 _("unsupported PC relative reference to different section"));
13023 if (fragp != sym_frag && sym_frag->fr_address == 0)
13024 /* Assume non-extended on the first relaxation pass.
13025 The address we have calculated will be bogus if this is
13026 a forward branch to another frag, as the forward frag
13027 will have fr_address == 0. */
13031 /* In this case, we know for sure that the symbol fragment is in
13032 the same section. If the relax_marker of the symbol fragment
13033 differs from the relax_marker of this fragment, we have not
13034 yet adjusted the symbol fragment fr_address. We want to add
13035 in STRETCH in order to get a better estimate of the address.
13036 This particularly matters because of the shift bits. */
13038 && sym_frag->relax_marker != fragp->relax_marker)
13042 /* Adjust stretch for any alignment frag. Note that if have
13043 been expanding the earlier code, the symbol may be
13044 defined in what appears to be an earlier frag. FIXME:
13045 This doesn't handle the fr_subtype field, which specifies
13046 a maximum number of bytes to skip when doing an
13048 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13050 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13053 stretch = - ((- stretch)
13054 & ~ ((1 << (int) f->fr_offset) - 1));
13056 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13065 addr = fragp->fr_address + fragp->fr_fix;
13067 /* The base address rules are complicated. The base address of
13068 a branch is the following instruction. The base address of a
13069 PC relative load or add is the instruction itself, but if it
13070 is in a delay slot (in which case it can not be extended) use
13071 the address of the instruction whose delay slot it is in. */
13072 if (type == 'p' || type == 'q')
13076 /* If we are currently assuming that this frag should be
13077 extended, then, the current address is two bytes
13079 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13082 /* Ignore the low bit in the target, since it will be set
13083 for a text label. */
13084 if ((val & 1) != 0)
13087 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13089 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13092 val -= addr & ~ ((1 << op->shift) - 1);
13094 /* Branch offsets have an implicit 0 in the lowest bit. */
13095 if (type == 'p' || type == 'q')
13098 /* If any of the shifted bits are set, we must use an extended
13099 opcode. If the address depends on the size of this
13100 instruction, this can lead to a loop, so we arrange to always
13101 use an extended opcode. We only check this when we are in
13102 the main relaxation loop, when SEC is NULL. */
13103 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13105 fragp->fr_subtype =
13106 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13110 /* If we are about to mark a frag as extended because the value
13111 is precisely maxtiny + 1, then there is a chance of an
13112 infinite loop as in the following code:
13117 In this case when the la is extended, foo is 0x3fc bytes
13118 away, so the la can be shrunk, but then foo is 0x400 away, so
13119 the la must be extended. To avoid this loop, we mark the
13120 frag as extended if it was small, and is about to become
13121 extended with a value of maxtiny + 1. */
13122 if (val == ((maxtiny + 1) << op->shift)
13123 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13126 fragp->fr_subtype =
13127 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13131 else if (symsec != absolute_section && sec != NULL)
13132 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13134 if ((val & ((1 << op->shift) - 1)) != 0
13135 || val < (mintiny << op->shift)
13136 || val > (maxtiny << op->shift))
13142 /* Compute the length of a branch sequence, and adjust the
13143 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13144 worst-case length is computed, with UPDATE being used to indicate
13145 whether an unconditional (-1), branch-likely (+1) or regular (0)
13146 branch is to be computed. */
13148 relaxed_branch_length (fragS *fragp, asection *sec, int update)
13150 bfd_boolean toofar;
13154 && S_IS_DEFINED (fragp->fr_symbol)
13155 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13160 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13162 addr = fragp->fr_address + fragp->fr_fix + 4;
13166 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13169 /* If the symbol is not defined or it's in a different segment,
13170 assume the user knows what's going on and emit a short
13176 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13178 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13179 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13180 RELAX_BRANCH_LINK (fragp->fr_subtype),
13186 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13189 if (mips_pic != NO_PIC)
13191 /* Additional space for PIC loading of target address. */
13193 if (mips_opts.isa == ISA_MIPS1)
13194 /* Additional space for $at-stabilizing nop. */
13198 /* If branch is conditional. */
13199 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13206 /* Estimate the size of a frag before relaxing. Unless this is the
13207 mips16, we are not really relaxing here, and the final size is
13208 encoded in the subtype information. For the mips16, we have to
13209 decide whether we are using an extended opcode or not. */
13212 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13216 if (RELAX_BRANCH_P (fragp->fr_subtype))
13219 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13221 return fragp->fr_var;
13224 if (RELAX_MIPS16_P (fragp->fr_subtype))
13225 /* We don't want to modify the EXTENDED bit here; it might get us
13226 into infinite loops. We change it only in mips_relax_frag(). */
13227 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13229 if (mips_pic == NO_PIC)
13230 change = nopic_need_relax (fragp->fr_symbol, 0);
13231 else if (mips_pic == SVR4_PIC)
13232 change = pic_need_relax (fragp->fr_symbol, segtype);
13238 fragp->fr_subtype |= RELAX_USE_SECOND;
13239 return -RELAX_FIRST (fragp->fr_subtype);
13242 return -RELAX_SECOND (fragp->fr_subtype);
13245 /* This is called to see whether a reloc against a defined symbol
13246 should be converted into a reloc against a section. Don't adjust
13247 MIPS16 jump relocations, so we don't have to worry about the format
13248 of the offset in the .o file. Don't adjust relocations against
13249 mips16 symbols, so that the linker can find them if it needs to set
13253 mips_fix_adjustable (fixS *fixp)
13255 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13258 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13259 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13262 if (fixp->fx_addsy == NULL)
13266 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13267 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13268 && fixp->fx_subsy == NULL)
13275 /* Translate internal representation of relocation info to BFD target
13279 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13281 static arelent *retval[4];
13283 bfd_reloc_code_real_type code;
13285 memset (retval, 0, sizeof(retval));
13286 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13287 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13288 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13289 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13291 if (mips_pic == EMBEDDED_PIC
13292 && SWITCH_TABLE (fixp))
13294 /* For a switch table entry we use a special reloc. The addend
13295 is actually the difference between the reloc address and the
13297 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13298 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13299 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13300 fixp->fx_r_type = BFD_RELOC_GPREL32;
13302 else if (fixp->fx_pcrel)
13304 bfd_vma pcrel_address;
13306 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13307 high-part relocs is the address of the low-part reloc. */
13308 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13310 assert (fixp->fx_next != NULL
13311 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13312 pcrel_address = (fixp->fx_next->fx_where
13313 + fixp->fx_next->fx_frag->fr_address);
13316 pcrel_address = reloc->address;
13318 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13320 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13321 Relocations want only the symbol offset. */
13322 reloc->addend = fixp->fx_addnumber + pcrel_address;
13324 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
13325 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13327 /* We use a special addend for an internal RELLO or RELHI reloc. */
13328 if (symbol_section_p (fixp->fx_addsy))
13329 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
13331 reloc->addend = fixp->fx_addnumber + pcrel_address;
13335 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13336 /* A gruesome hack which is a result of the gruesome gas reloc
13338 reloc->addend = pcrel_address;
13340 reloc->addend = -pcrel_address;
13344 reloc->addend = fixp->fx_addnumber;
13346 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13347 entry to be used in the relocation's section offset. */
13348 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13350 reloc->address = reloc->addend;
13354 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13355 fixup_segment converted a non-PC relative reloc into a PC
13356 relative reloc. In such a case, we need to convert the reloc
13358 code = fixp->fx_r_type;
13359 if (fixp->fx_pcrel)
13364 code = BFD_RELOC_8_PCREL;
13367 code = BFD_RELOC_16_PCREL;
13370 code = BFD_RELOC_32_PCREL;
13373 code = BFD_RELOC_64_PCREL;
13375 case BFD_RELOC_8_PCREL:
13376 case BFD_RELOC_16_PCREL:
13377 case BFD_RELOC_32_PCREL:
13378 case BFD_RELOC_64_PCREL:
13379 case BFD_RELOC_16_PCREL_S2:
13380 case BFD_RELOC_PCREL_HI16_S:
13381 case BFD_RELOC_PCREL_LO16:
13384 as_bad_where (fixp->fx_file, fixp->fx_line,
13385 _("Cannot make %s relocation PC relative"),
13386 bfd_get_reloc_code_name (code));
13390 /* To support a PC relative reloc when generating embedded PIC code
13391 for ECOFF, we use a Cygnus extension. We check for that here to
13392 make sure that we don't let such a reloc escape normally. */
13393 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13394 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13395 && code == BFD_RELOC_16_PCREL_S2
13396 && mips_pic != EMBEDDED_PIC)
13397 reloc->howto = NULL;
13399 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13401 if (reloc->howto == NULL)
13403 as_bad_where (fixp->fx_file, fixp->fx_line,
13404 _("Can not represent %s relocation in this object file format"),
13405 bfd_get_reloc_code_name (code));
13412 /* Relax a machine dependent frag. This returns the amount by which
13413 the current size of the frag should change. */
13416 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13418 if (RELAX_BRANCH_P (fragp->fr_subtype))
13420 offsetT old_var = fragp->fr_var;
13422 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13424 return fragp->fr_var - old_var;
13427 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13430 if (mips16_extended_frag (fragp, NULL, stretch))
13432 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13434 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13439 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13441 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13448 /* Convert a machine dependent frag. */
13451 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13453 if (RELAX_BRANCH_P (fragp->fr_subtype))
13456 unsigned long insn;
13460 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13462 if (target_big_endian)
13463 insn = bfd_getb32 (buf);
13465 insn = bfd_getl32 (buf);
13467 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13469 /* We generate a fixup instead of applying it right now
13470 because, if there are linker relaxations, we're going to
13471 need the relocations. */
13472 exp.X_op = O_symbol;
13473 exp.X_add_symbol = fragp->fr_symbol;
13474 exp.X_add_number = fragp->fr_offset;
13476 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13478 BFD_RELOC_16_PCREL_S2);
13479 fixp->fx_file = fragp->fr_file;
13480 fixp->fx_line = fragp->fr_line;
13482 md_number_to_chars (buf, insn, 4);
13489 as_warn_where (fragp->fr_file, fragp->fr_line,
13490 _("relaxed out-of-range branch into a jump"));
13492 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13495 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13497 /* Reverse the branch. */
13498 switch ((insn >> 28) & 0xf)
13501 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13502 have the condition reversed by tweaking a single
13503 bit, and their opcodes all have 0x4???????. */
13504 assert ((insn & 0xf1000000) == 0x41000000);
13505 insn ^= 0x00010000;
13509 /* bltz 0x04000000 bgez 0x04010000
13510 bltzal 0x04100000 bgezal 0x04110000 */
13511 assert ((insn & 0xfc0e0000) == 0x04000000);
13512 insn ^= 0x00010000;
13516 /* beq 0x10000000 bne 0x14000000
13517 blez 0x18000000 bgtz 0x1c000000 */
13518 insn ^= 0x04000000;
13526 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13528 /* Clear the and-link bit. */
13529 assert ((insn & 0xfc1c0000) == 0x04100000);
13531 /* bltzal 0x04100000 bgezal 0x04110000
13532 bltzall 0x04120000 bgezall 0x04130000 */
13533 insn &= ~0x00100000;
13536 /* Branch over the branch (if the branch was likely) or the
13537 full jump (not likely case). Compute the offset from the
13538 current instruction to branch to. */
13539 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13543 /* How many bytes in instructions we've already emitted? */
13544 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13545 /* How many bytes in instructions from here to the end? */
13546 i = fragp->fr_var - i;
13548 /* Convert to instruction count. */
13550 /* Branch counts from the next instruction. */
13553 /* Branch over the jump. */
13554 md_number_to_chars (buf, insn, 4);
13558 md_number_to_chars (buf, 0, 4);
13561 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13563 /* beql $0, $0, 2f */
13565 /* Compute the PC offset from the current instruction to
13566 the end of the variable frag. */
13567 /* How many bytes in instructions we've already emitted? */
13568 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13569 /* How many bytes in instructions from here to the end? */
13570 i = fragp->fr_var - i;
13571 /* Convert to instruction count. */
13573 /* Don't decrement i, because we want to branch over the
13577 md_number_to_chars (buf, insn, 4);
13580 md_number_to_chars (buf, 0, 4);
13585 if (mips_pic == NO_PIC)
13588 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13589 ? 0x0c000000 : 0x08000000);
13590 exp.X_op = O_symbol;
13591 exp.X_add_symbol = fragp->fr_symbol;
13592 exp.X_add_number = fragp->fr_offset;
13594 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13595 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13596 fixp->fx_file = fragp->fr_file;
13597 fixp->fx_line = fragp->fr_line;
13599 md_number_to_chars (buf, insn, 4);
13604 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13605 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13606 exp.X_op = O_symbol;
13607 exp.X_add_symbol = fragp->fr_symbol;
13608 exp.X_add_number = fragp->fr_offset;
13610 if (fragp->fr_offset)
13612 exp.X_add_symbol = make_expr_symbol (&exp);
13613 exp.X_add_number = 0;
13616 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13617 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13618 fixp->fx_file = fragp->fr_file;
13619 fixp->fx_line = fragp->fr_line;
13621 md_number_to_chars (buf, insn, 4);
13624 if (mips_opts.isa == ISA_MIPS1)
13627 md_number_to_chars (buf, 0, 4);
13631 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13632 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13634 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13635 4, &exp, 0, BFD_RELOC_LO16);
13636 fixp->fx_file = fragp->fr_file;
13637 fixp->fx_line = fragp->fr_line;
13639 md_number_to_chars (buf, insn, 4);
13643 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13648 md_number_to_chars (buf, insn, 4);
13653 assert (buf == (bfd_byte *)fragp->fr_literal
13654 + fragp->fr_fix + fragp->fr_var);
13656 fragp->fr_fix += fragp->fr_var;
13661 if (RELAX_MIPS16_P (fragp->fr_subtype))
13664 register const struct mips16_immed_operand *op;
13665 bfd_boolean small, ext;
13668 unsigned long insn;
13669 bfd_boolean use_extend;
13670 unsigned short extend;
13672 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13673 op = mips16_immed_operands;
13674 while (op->type != type)
13677 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13688 resolve_symbol_value (fragp->fr_symbol);
13689 val = S_GET_VALUE (fragp->fr_symbol);
13694 addr = fragp->fr_address + fragp->fr_fix;
13696 /* The rules for the base address of a PC relative reloc are
13697 complicated; see mips16_extended_frag. */
13698 if (type == 'p' || type == 'q')
13703 /* Ignore the low bit in the target, since it will be
13704 set for a text label. */
13705 if ((val & 1) != 0)
13708 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13710 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13713 addr &= ~ (addressT) ((1 << op->shift) - 1);
13716 /* Make sure the section winds up with the alignment we have
13719 record_alignment (asec, op->shift);
13723 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13724 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13725 as_warn_where (fragp->fr_file, fragp->fr_line,
13726 _("extended instruction in delay slot"));
13728 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13730 if (target_big_endian)
13731 insn = bfd_getb16 (buf);
13733 insn = bfd_getl16 (buf);
13735 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13736 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13737 small, ext, &insn, &use_extend, &extend);
13741 md_number_to_chars (buf, 0xf000 | extend, 2);
13742 fragp->fr_fix += 2;
13746 md_number_to_chars (buf, insn, 2);
13747 fragp->fr_fix += 2;
13755 first = RELAX_FIRST (fragp->fr_subtype);
13756 second = RELAX_SECOND (fragp->fr_subtype);
13757 fixp = (fixS *) fragp->fr_opcode;
13759 /* Possibly emit a warning if we've chosen the longer option. */
13760 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13761 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13763 const char *msg = macro_warning (fragp->fr_subtype);
13765 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13768 /* Go through all the fixups for the first sequence. Disable them
13769 (by marking them as done) if we're going to use the second
13770 sequence instead. */
13772 && fixp->fx_frag == fragp
13773 && fixp->fx_where < fragp->fr_fix - second)
13775 if (fragp->fr_subtype & RELAX_USE_SECOND)
13777 fixp = fixp->fx_next;
13780 /* Go through the fixups for the second sequence. Disable them if
13781 we're going to use the first sequence, otherwise adjust their
13782 addresses to account for the relaxation. */
13783 while (fixp && fixp->fx_frag == fragp)
13785 if (fragp->fr_subtype & RELAX_USE_SECOND)
13786 fixp->fx_where -= first;
13789 fixp = fixp->fx_next;
13792 /* Now modify the frag contents. */
13793 if (fragp->fr_subtype & RELAX_USE_SECOND)
13797 start = fragp->fr_literal + fragp->fr_fix - first - second;
13798 memmove (start, start + first, second);
13799 fragp->fr_fix -= first;
13802 fragp->fr_fix -= second;
13808 /* This function is called after the relocs have been generated.
13809 We've been storing mips16 text labels as odd. Here we convert them
13810 back to even for the convenience of the debugger. */
13813 mips_frob_file_after_relocs (void)
13816 unsigned int count, i;
13818 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13821 syms = bfd_get_outsymbols (stdoutput);
13822 count = bfd_get_symcount (stdoutput);
13823 for (i = 0; i < count; i++, syms++)
13825 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13826 && ((*syms)->value & 1) != 0)
13828 (*syms)->value &= ~1;
13829 /* If the symbol has an odd size, it was probably computed
13830 incorrectly, so adjust that as well. */
13831 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13832 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13839 /* This function is called whenever a label is defined. It is used
13840 when handling branch delays; if a branch has a label, we assume we
13841 can not move it. */
13844 mips_define_label (symbolS *sym)
13846 struct insn_label_list *l;
13848 if (free_insn_labels == NULL)
13849 l = (struct insn_label_list *) xmalloc (sizeof *l);
13852 l = free_insn_labels;
13853 free_insn_labels = l->next;
13857 l->next = insn_labels;
13861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13863 /* Some special processing for a MIPS ELF file. */
13866 mips_elf_final_processing (void)
13868 /* Write out the register information. */
13869 if (mips_abi != N64_ABI)
13873 s.ri_gprmask = mips_gprmask;
13874 s.ri_cprmask[0] = mips_cprmask[0];
13875 s.ri_cprmask[1] = mips_cprmask[1];
13876 s.ri_cprmask[2] = mips_cprmask[2];
13877 s.ri_cprmask[3] = mips_cprmask[3];
13878 /* The gp_value field is set by the MIPS ELF backend. */
13880 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13881 ((Elf32_External_RegInfo *)
13882 mips_regmask_frag));
13886 Elf64_Internal_RegInfo s;
13888 s.ri_gprmask = mips_gprmask;
13890 s.ri_cprmask[0] = mips_cprmask[0];
13891 s.ri_cprmask[1] = mips_cprmask[1];
13892 s.ri_cprmask[2] = mips_cprmask[2];
13893 s.ri_cprmask[3] = mips_cprmask[3];
13894 /* The gp_value field is set by the MIPS ELF backend. */
13896 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13897 ((Elf64_External_RegInfo *)
13898 mips_regmask_frag));
13901 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13902 sort of BFD interface for this. */
13903 if (mips_any_noreorder)
13904 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13905 if (mips_pic != NO_PIC)
13907 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13908 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13911 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13913 /* Set MIPS ELF flags for ASEs. */
13914 if (file_ase_mips16)
13915 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13916 #if 0 /* XXX FIXME */
13917 if (file_ase_mips3d)
13918 elf_elfheader (stdoutput)->e_flags |= ???;
13921 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13923 /* Set the MIPS ELF ABI flags. */
13924 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13925 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13926 else if (mips_abi == O64_ABI)
13927 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13928 else if (mips_abi == EABI_ABI)
13930 if (!file_mips_gp32)
13931 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13933 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13935 else if (mips_abi == N32_ABI)
13936 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13938 /* Nothing to do for N64_ABI. */
13940 if (mips_32bitmode)
13941 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13944 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13946 typedef struct proc {
13948 unsigned long reg_mask;
13949 unsigned long reg_offset;
13950 unsigned long fpreg_mask;
13951 unsigned long fpreg_offset;
13952 unsigned long frame_offset;
13953 unsigned long frame_reg;
13954 unsigned long pc_reg;
13957 static procS cur_proc;
13958 static procS *cur_proc_ptr;
13959 static int numprocs;
13961 /* Fill in an rs_align_code fragment. */
13964 mips_handle_align (fragS *fragp)
13966 if (fragp->fr_type != rs_align_code)
13969 if (mips_opts.mips16)
13971 static const unsigned char be_nop[] = { 0x65, 0x00 };
13972 static const unsigned char le_nop[] = { 0x00, 0x65 };
13977 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13978 p = fragp->fr_literal + fragp->fr_fix;
13986 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13990 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13994 md_obj_begin (void)
14001 /* check for premature end, nesting errors, etc */
14003 as_warn (_("missing .end at end of assembly"));
14012 if (*input_line_pointer == '-')
14014 ++input_line_pointer;
14017 if (!ISDIGIT (*input_line_pointer))
14018 as_bad (_("expected simple number"));
14019 if (input_line_pointer[0] == '0')
14021 if (input_line_pointer[1] == 'x')
14023 input_line_pointer += 2;
14024 while (ISXDIGIT (*input_line_pointer))
14027 val |= hex_value (*input_line_pointer++);
14029 return negative ? -val : val;
14033 ++input_line_pointer;
14034 while (ISDIGIT (*input_line_pointer))
14037 val |= *input_line_pointer++ - '0';
14039 return negative ? -val : val;
14042 if (!ISDIGIT (*input_line_pointer))
14044 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14045 *input_line_pointer, *input_line_pointer);
14046 as_warn (_("invalid number"));
14049 while (ISDIGIT (*input_line_pointer))
14052 val += *input_line_pointer++ - '0';
14054 return negative ? -val : val;
14057 /* The .file directive; just like the usual .file directive, but there
14058 is an initial number which is the ECOFF file index. In the non-ECOFF
14059 case .file implies DWARF-2. */
14062 s_mips_file (int x ATTRIBUTE_UNUSED)
14064 static int first_file_directive = 0;
14066 if (ECOFF_DEBUGGING)
14075 filename = dwarf2_directive_file (0);
14077 /* Versions of GCC up to 3.1 start files with a ".file"
14078 directive even for stabs output. Make sure that this
14079 ".file" is handled. Note that you need a version of GCC
14080 after 3.1 in order to support DWARF-2 on MIPS. */
14081 if (filename != NULL && ! first_file_directive)
14083 (void) new_logical_line (filename, -1);
14084 s_app_file_string (filename);
14086 first_file_directive = 1;
14090 /* The .loc directive, implying DWARF-2. */
14093 s_mips_loc (int x ATTRIBUTE_UNUSED)
14095 if (!ECOFF_DEBUGGING)
14096 dwarf2_directive_loc (0);
14099 /* The .end directive. */
14102 s_mips_end (int x ATTRIBUTE_UNUSED)
14106 /* Following functions need their own .frame and .cprestore directives. */
14107 mips_frame_reg_valid = 0;
14108 mips_cprestore_valid = 0;
14110 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14113 demand_empty_rest_of_line ();
14118 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14119 as_warn (_(".end not in text section"));
14123 as_warn (_(".end directive without a preceding .ent directive."));
14124 demand_empty_rest_of_line ();
14130 assert (S_GET_NAME (p));
14131 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14132 as_warn (_(".end symbol does not match .ent symbol."));
14134 if (debug_type == DEBUG_STABS)
14135 stabs_generate_asm_endfunc (S_GET_NAME (p),
14139 as_warn (_(".end directive missing or unknown symbol"));
14142 /* Generate a .pdr section. */
14143 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14146 segT saved_seg = now_seg;
14147 subsegT saved_subseg = now_subseg;
14152 dot = frag_now_fix ();
14154 #ifdef md_flush_pending_output
14155 md_flush_pending_output ();
14159 subseg_set (pdr_seg, 0);
14161 /* Write the symbol. */
14162 exp.X_op = O_symbol;
14163 exp.X_add_symbol = p;
14164 exp.X_add_number = 0;
14165 emit_expr (&exp, 4);
14167 fragp = frag_more (7 * 4);
14169 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14170 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14171 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14172 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14173 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14174 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14175 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14177 subseg_set (saved_seg, saved_subseg);
14179 #endif /* OBJ_ELF */
14181 cur_proc_ptr = NULL;
14184 /* The .aent and .ent directives. */
14187 s_mips_ent (int aent)
14191 symbolP = get_symbol ();
14192 if (*input_line_pointer == ',')
14193 ++input_line_pointer;
14194 SKIP_WHITESPACE ();
14195 if (ISDIGIT (*input_line_pointer)
14196 || *input_line_pointer == '-')
14199 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14200 as_warn (_(".ent or .aent not in text section."));
14202 if (!aent && cur_proc_ptr)
14203 as_warn (_("missing .end"));
14207 /* This function needs its own .frame and .cprestore directives. */
14208 mips_frame_reg_valid = 0;
14209 mips_cprestore_valid = 0;
14211 cur_proc_ptr = &cur_proc;
14212 memset (cur_proc_ptr, '\0', sizeof (procS));
14214 cur_proc_ptr->isym = symbolP;
14216 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14220 if (debug_type == DEBUG_STABS)
14221 stabs_generate_asm_func (S_GET_NAME (symbolP),
14222 S_GET_NAME (symbolP));
14225 demand_empty_rest_of_line ();
14228 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14229 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14230 s_mips_frame is used so that we can set the PDR information correctly.
14231 We can't use the ecoff routines because they make reference to the ecoff
14232 symbol table (in the mdebug section). */
14235 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14238 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14242 if (cur_proc_ptr == (procS *) NULL)
14244 as_warn (_(".frame outside of .ent"));
14245 demand_empty_rest_of_line ();
14249 cur_proc_ptr->frame_reg = tc_get_register (1);
14251 SKIP_WHITESPACE ();
14252 if (*input_line_pointer++ != ','
14253 || get_absolute_expression_and_terminator (&val) != ',')
14255 as_warn (_("Bad .frame directive"));
14256 --input_line_pointer;
14257 demand_empty_rest_of_line ();
14261 cur_proc_ptr->frame_offset = val;
14262 cur_proc_ptr->pc_reg = tc_get_register (0);
14264 demand_empty_rest_of_line ();
14267 #endif /* OBJ_ELF */
14271 /* The .fmask and .mask directives. If the mdebug section is present
14272 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14273 embedded targets, s_mips_mask is used so that we can set the PDR
14274 information correctly. We can't use the ecoff routines because they
14275 make reference to the ecoff symbol table (in the mdebug section). */
14278 s_mips_mask (int reg_type)
14281 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14285 if (cur_proc_ptr == (procS *) NULL)
14287 as_warn (_(".mask/.fmask outside of .ent"));
14288 demand_empty_rest_of_line ();
14292 if (get_absolute_expression_and_terminator (&mask) != ',')
14294 as_warn (_("Bad .mask/.fmask directive"));
14295 --input_line_pointer;
14296 demand_empty_rest_of_line ();
14300 off = get_absolute_expression ();
14302 if (reg_type == 'F')
14304 cur_proc_ptr->fpreg_mask = mask;
14305 cur_proc_ptr->fpreg_offset = off;
14309 cur_proc_ptr->reg_mask = mask;
14310 cur_proc_ptr->reg_offset = off;
14313 demand_empty_rest_of_line ();
14316 #endif /* OBJ_ELF */
14317 s_ignore (reg_type);
14320 /* The .loc directive. */
14330 assert (now_seg == text_section);
14332 lineno = get_number ();
14333 addroff = frag_now_fix ();
14335 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14336 S_SET_TYPE (symbolP, N_SLINE);
14337 S_SET_OTHER (symbolP, 0);
14338 S_SET_DESC (symbolP, lineno);
14339 symbolP->sy_segment = now_seg;
14343 /* A table describing all the processors gas knows about. Names are
14344 matched in the order listed.
14346 To ease comparison, please keep this table in the same order as
14347 gcc's mips_cpu_info_table[]. */
14348 static const struct mips_cpu_info mips_cpu_info_table[] =
14350 /* Entries for generic ISAs */
14351 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14352 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14353 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14354 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14355 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14356 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14357 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14358 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14359 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
14362 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14363 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14364 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14367 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14370 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14371 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14372 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14373 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14374 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14375 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14376 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14377 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14378 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14379 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14380 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14381 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14384 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14385 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14386 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14387 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14388 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14389 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14390 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14391 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14392 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14393 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14394 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14395 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14396 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14399 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14400 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14401 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14404 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14405 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14407 /* Broadcom SB-1 CPU core */
14408 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14415 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14416 with a final "000" replaced by "k". Ignore case.
14418 Note: this function is shared between GCC and GAS. */
14421 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14423 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14424 given++, canonical++;
14426 return ((*given == 0 && *canonical == 0)
14427 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14431 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14432 CPU name. We've traditionally allowed a lot of variation here.
14434 Note: this function is shared between GCC and GAS. */
14437 mips_matching_cpu_name_p (const char *canonical, const char *given)
14439 /* First see if the name matches exactly, or with a final "000"
14440 turned into "k". */
14441 if (mips_strict_matching_cpu_name_p (canonical, given))
14444 /* If not, try comparing based on numerical designation alone.
14445 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14446 if (TOLOWER (*given) == 'r')
14448 if (!ISDIGIT (*given))
14451 /* Skip over some well-known prefixes in the canonical name,
14452 hoping to find a number there too. */
14453 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14455 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14457 else if (TOLOWER (canonical[0]) == 'r')
14460 return mips_strict_matching_cpu_name_p (canonical, given);
14464 /* Parse an option that takes the name of a processor as its argument.
14465 OPTION is the name of the option and CPU_STRING is the argument.
14466 Return the corresponding processor enumeration if the CPU_STRING is
14467 recognized, otherwise report an error and return null.
14469 A similar function exists in GCC. */
14471 static const struct mips_cpu_info *
14472 mips_parse_cpu (const char *option, const char *cpu_string)
14474 const struct mips_cpu_info *p;
14476 /* 'from-abi' selects the most compatible architecture for the given
14477 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14478 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14479 version. Look first at the -mgp options, if given, otherwise base
14480 the choice on MIPS_DEFAULT_64BIT.
14482 Treat NO_ABI like the EABIs. One reason to do this is that the
14483 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14484 architecture. This code picks MIPS I for 'mips' and MIPS III for
14485 'mips64', just as we did in the days before 'from-abi'. */
14486 if (strcasecmp (cpu_string, "from-abi") == 0)
14488 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14489 return mips_cpu_info_from_isa (ISA_MIPS1);
14491 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14492 return mips_cpu_info_from_isa (ISA_MIPS3);
14494 if (file_mips_gp32 >= 0)
14495 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14497 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14502 /* 'default' has traditionally been a no-op. Probably not very useful. */
14503 if (strcasecmp (cpu_string, "default") == 0)
14506 for (p = mips_cpu_info_table; p->name != 0; p++)
14507 if (mips_matching_cpu_name_p (p->name, cpu_string))
14510 as_bad ("Bad value (%s) for %s", cpu_string, option);
14514 /* Return the canonical processor information for ISA (a member of the
14515 ISA_MIPS* enumeration). */
14517 static const struct mips_cpu_info *
14518 mips_cpu_info_from_isa (int isa)
14522 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14523 if (mips_cpu_info_table[i].is_isa
14524 && isa == mips_cpu_info_table[i].isa)
14525 return (&mips_cpu_info_table[i]);
14530 static const struct mips_cpu_info *
14531 mips_cpu_info_from_arch (int arch)
14535 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14536 if (arch == mips_cpu_info_table[i].cpu)
14537 return (&mips_cpu_info_table[i]);
14543 show (FILE *stream, const char *string, int *col_p, int *first_p)
14547 fprintf (stream, "%24s", "");
14552 fprintf (stream, ", ");
14556 if (*col_p + strlen (string) > 72)
14558 fprintf (stream, "\n%24s", "");
14562 fprintf (stream, "%s", string);
14563 *col_p += strlen (string);
14569 md_show_usage (FILE *stream)
14574 fprintf (stream, _("\
14576 -membedded-pic generate embedded position independent code\n\
14577 -EB generate big endian output\n\
14578 -EL generate little endian output\n\
14579 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14580 -G NUM allow referencing objects up to NUM bytes\n\
14581 implicitly with the gp register [default 8]\n"));
14582 fprintf (stream, _("\
14583 -mips1 generate MIPS ISA I instructions\n\
14584 -mips2 generate MIPS ISA II instructions\n\
14585 -mips3 generate MIPS ISA III instructions\n\
14586 -mips4 generate MIPS ISA IV instructions\n\
14587 -mips5 generate MIPS ISA V instructions\n\
14588 -mips32 generate MIPS32 ISA instructions\n\
14589 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14590 -mips64 generate MIPS64 ISA instructions\n\
14591 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14592 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14596 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14597 show (stream, mips_cpu_info_table[i].name, &column, &first);
14598 show (stream, "from-abi", &column, &first);
14599 fputc ('\n', stream);
14601 fprintf (stream, _("\
14602 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14603 -no-mCPU don't generate code specific to CPU.\n\
14604 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14608 show (stream, "3900", &column, &first);
14609 show (stream, "4010", &column, &first);
14610 show (stream, "4100", &column, &first);
14611 show (stream, "4650", &column, &first);
14612 fputc ('\n', stream);
14614 fprintf (stream, _("\
14615 -mips16 generate mips16 instructions\n\
14616 -no-mips16 do not generate mips16 instructions\n"));
14617 fprintf (stream, _("\
14618 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14619 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14620 -O0 remove unneeded NOPs, do not swap branches\n\
14621 -O remove unneeded NOPs and swap branches\n\
14622 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14623 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14624 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14626 fprintf (stream, _("\
14627 -KPIC, -call_shared generate SVR4 position independent code\n\
14628 -non_shared do not generate position independent code\n\
14629 -xgot assume a 32 bit GOT\n\
14630 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14631 -mabi=ABI create ABI conformant object file for:\n"));
14635 show (stream, "32", &column, &first);
14636 show (stream, "o64", &column, &first);
14637 show (stream, "n32", &column, &first);
14638 show (stream, "64", &column, &first);
14639 show (stream, "eabi", &column, &first);
14641 fputc ('\n', stream);
14643 fprintf (stream, _("\
14644 -32 create o32 ABI object file (default)\n\
14645 -n32 create n32 ABI object file\n\
14646 -64 create 64 ABI object file\n"));
14651 mips_dwarf2_format (void)
14653 if (mips_abi == N64_ABI)
14656 return dwarf2_format_64bit_irix;
14658 return dwarf2_format_64bit;
14662 return dwarf2_format_32bit;