1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p : 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p : 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi = NO_ABI;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls = FALSE;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared = TRUE;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32 = -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32 = -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float = 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float = 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008 = FALSE;
281 static struct mips_set_options mips_opts =
283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
287 /* soft_float */ FALSE, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch = CPU_UNKNOWN;
331 static const char *mips_arch_string;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune = CPU_UNKNOWN;
336 static const char *mips_tune_string;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode = 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got = 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap = 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value = 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen = 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS *, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control *op_hash = NULL;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control *mips16_op_hash = NULL;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control *micromips_op_hash = NULL;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 /* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635 enum mips_insn_error_format {
641 /* Information about an error that was found while assembling the current
643 struct mips_insn_error {
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format;
668 /* The error that should be reported for the current instruction. */
669 static struct mips_insn_error insn_error;
671 static int auto_align = 1;
673 /* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
677 static offsetT mips_cprestore_offset = -1;
679 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
680 more optimizations, it can use a register value instead of a memory-saved
681 offset and even an other register than $gp as global pointer. */
682 static offsetT mips_cpreturn_offset = -1;
683 static int mips_cpreturn_register = -1;
684 static int mips_gp_register = GP;
685 static int mips_gprel_offset = 0;
687 /* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689 static int mips_cprestore_valid = 0;
691 /* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693 static int mips_frame_reg = SP;
695 /* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_frame_reg_valid = 0;
699 /* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
702 /* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
706 static int mips_optimize = 2;
708 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710 static int mips_debug = 0;
712 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713 #define MAX_VR4130_NOPS 4
715 /* The maximum number of NOPs needed to fill delay slots. */
716 #define MAX_DELAY_NOPS 2
718 /* The maximum number of NOPs needed for any purpose. */
721 /* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726 static struct mips_cl_insn history[1 + MAX_NOPS];
728 /* Arrays of operands for each instruction. */
729 #define MAX_OPERANDS 6
730 struct mips_operand_array {
731 const struct mips_operand *operand[MAX_OPERANDS];
733 static struct mips_operand_array *mips_operands;
734 static struct mips_operand_array *mips16_operands;
735 static struct mips_operand_array *micromips_operands;
737 /* Nop instructions used by emit_nop. */
738 static struct mips_cl_insn nop_insn;
739 static struct mips_cl_insn mips16_nop_insn;
740 static struct mips_cl_insn micromips_nop16_insn;
741 static struct mips_cl_insn micromips_nop32_insn;
743 /* The appropriate nop for the current mode. */
744 #define NOP_INSN (mips_opts.mips16 \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? µmips_nop32_insn \
749 : µmips_nop16_insn) \
752 /* The size of NOP_INSN in bytes. */
753 #define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
757 /* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
761 static fragS *prev_nop_frag;
763 /* The number of nop instructions we created in prev_nop_frag. */
764 static int prev_nop_frag_holds;
766 /* The number of nop instructions that we know we need in
768 static int prev_nop_frag_required;
770 /* The number of instructions we've seen since prev_nop_frag. */
771 static int prev_nop_frag_since;
773 /* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
782 corresponding LO relocation. */
787 struct mips_hi_fixup *next;
790 /* The section this fixup is in. */
794 /* The list of unmatched HI relocs. */
796 static struct mips_hi_fixup *mips_hi_fixup_list;
798 /* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
801 static fragS *prev_reloc_op_frag;
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map microMIPS register numbers to normal MIPS register numbers. */
812 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
814 /* The microMIPS registers with type h. */
815 static const unsigned int micromips_to_32_reg_h_map1[] =
817 5, 5, 6, 4, 4, 4, 4, 4
819 static const unsigned int micromips_to_32_reg_h_map2[] =
821 6, 7, 7, 21, 22, 5, 6, 7
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
834 enum fix_vr4120_class
842 NUM_FIX_VR4120_CLASSES
845 /* ...likewise -mfix-loongson2f-jump. */
846 static bfd_boolean mips_fix_loongson2f_jump;
848 /* ...likewise -mfix-loongson2f-nop. */
849 static bfd_boolean mips_fix_loongson2f_nop;
851 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852 static bfd_boolean mips_fix_loongson2f;
854 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
859 /* True if -mfix-vr4120 is in force. */
860 static int mips_fix_vr4120;
862 /* ...likewise -mfix-vr4130. */
863 static int mips_fix_vr4130;
865 /* ...likewise -mfix-24k. */
866 static int mips_fix_24k;
868 /* ...likewise -mfix-cn63xxp1 */
869 static bfd_boolean mips_fix_cn63xxp1;
871 /* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
876 static int mips_relax_branch;
878 /* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
925 The frag's "opcode" points to the first fixup for relaxable code.
927 Relaxable macros are generated using a sequence such as:
929 relax_start (SYMBOL);
930 ... generate first expansion ...
932 ... generate second expansion ...
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
937 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
939 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940 #define RELAX_SECOND(X) ((X) & 0xff)
941 #define RELAX_USE_SECOND 0x10000
942 #define RELAX_SECOND_LONGER 0x20000
943 #define RELAX_NOMACRO 0x40000
944 #define RELAX_DELAY_SLOT 0x80000
945 #define RELAX_DELAY_SLOT_16BIT 0x100000
946 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
949 /* Branch without likely bit. If label is out of range, we turn:
951 beq reg1, reg2, label
961 with the following opcode replacements:
968 bltzal <-> bgezal (with jal label instead of j label)
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
978 Branch likely. If label is out of range, we turn:
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
990 delay slot (executed only if branch taken)
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
999 delay slot (executed only if branch taken)
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1015 but it's not clear that it would actually improve performance. */
1016 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
1024 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1025 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1031 /* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
1058 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1059 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1071 /* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
1102 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1105 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1110 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1117 /* Sign-extend 16-bit value X. */
1118 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1120 /* Is the given value a sign-extended 32-bit value? */
1121 #define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1125 /* Is the given value a sign-extended 16-bit value? */
1126 #define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1130 /* Is the given value a sign-extended 12-bit value? */
1131 #define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1134 /* Is the given value a sign-extended 9-bit value? */
1135 #define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1138 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139 #define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1143 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1145 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1148 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1149 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1154 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
1159 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160 #define MIPS16_EXTEND (0xf000U << 16)
1162 /* Whether or not we are emitting a branch-likely macro. */
1163 static bfd_boolean emit_branch_likely_macro = FALSE;
1165 /* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes[2];
1182 /* The symbol on which the choice of sequence depends. */
1186 /* Global variables used to decide whether a macro needs a warning. */
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p;
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length;
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1199 unsigned int sizes[2];
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes[2];
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns[2];
1218 /* The first variant frag for this macro. */
1220 } mips_macro_warning;
1222 /* Prototypes for static functions. */
1224 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1226 static void append_insn
1227 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1228 bfd_boolean expansionp);
1229 static void mips_no_prev_insn (void);
1230 static void macro_build (expressionS *, const char *, const char *, ...);
1231 static void mips16_macro_build
1232 (expressionS *, const char *, const char *, va_list *);
1233 static void load_register (int, expressionS *, int);
1234 static void macro_start (void);
1235 static void macro_end (void);
1236 static void macro (struct mips_cl_insn *ip, char *str);
1237 static void mips16_macro (struct mips_cl_insn * ip);
1238 static void mips_ip (char *str, struct mips_cl_insn * ip);
1239 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1240 static void mips16_immed
1241 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1242 unsigned int, unsigned long *);
1243 static size_t my_getSmallExpression
1244 (expressionS *, bfd_reloc_code_real_type *, char *);
1245 static void my_getExpression (expressionS *, char *);
1246 static void s_align (int);
1247 static void s_change_sec (int);
1248 static void s_change_section (int);
1249 static void s_cons (int);
1250 static void s_float_cons (int);
1251 static void s_mips_globl (int);
1252 static void s_option (int);
1253 static void s_mipsset (int);
1254 static void s_abicalls (int);
1255 static void s_cpload (int);
1256 static void s_cpsetup (int);
1257 static void s_cplocal (int);
1258 static void s_cprestore (int);
1259 static void s_cpreturn (int);
1260 static void s_dtprelword (int);
1261 static void s_dtpreldword (int);
1262 static void s_tprelword (int);
1263 static void s_tpreldword (int);
1264 static void s_gpvalue (int);
1265 static void s_gpword (int);
1266 static void s_gpdword (int);
1267 static void s_ehword (int);
1268 static void s_cpadd (int);
1269 static void s_insn (int);
1270 static void s_nan (int);
1271 static void md_obj_begin (void);
1272 static void md_obj_end (void);
1273 static void s_mips_ent (int);
1274 static void s_mips_end (int);
1275 static void s_mips_frame (int);
1276 static void s_mips_mask (int reg_type);
1277 static void s_mips_stab (int);
1278 static void s_mips_weakext (int);
1279 static void s_mips_file (int);
1280 static void s_mips_loc (int);
1281 static bfd_boolean pic_need_relax (symbolS *, asection *);
1282 static int relaxed_branch_length (fragS *, asection *, int);
1283 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1284 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1286 /* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1289 struct mips_cpu_info
1291 const char *name; /* CPU or ISA name. */
1292 int flags; /* MIPS_CPU_* flags. */
1293 int ase; /* Set of ASEs implemented by the CPU. */
1294 int isa; /* ISA level. */
1295 int cpu; /* CPU number (default CPU if ISA). */
1298 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1300 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1301 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1302 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1304 /* Command-line options. */
1305 const char *md_shortopts = "O::g::G:";
1309 OPTION_MARCH = OPTION_MD_BASE,
1335 OPTION_NO_SMARTMIPS,
1341 OPTION_NO_MICROMIPS,
1344 OPTION_COMPAT_ARCH_BASE,
1353 OPTION_M7000_HILO_FIX,
1354 OPTION_MNO_7000_HILO_FIX,
1357 OPTION_FIX_LOONGSON2F_JUMP,
1358 OPTION_NO_FIX_LOONGSON2F_JUMP,
1359 OPTION_FIX_LOONGSON2F_NOP,
1360 OPTION_NO_FIX_LOONGSON2F_NOP,
1362 OPTION_NO_FIX_VR4120,
1364 OPTION_NO_FIX_VR4130,
1365 OPTION_FIX_CN63XXP1,
1366 OPTION_NO_FIX_CN63XXP1,
1373 OPTION_CONSTRUCT_FLOATS,
1374 OPTION_NO_CONSTRUCT_FLOATS,
1377 OPTION_RELAX_BRANCH,
1378 OPTION_NO_RELAX_BRANCH,
1387 OPTION_SINGLE_FLOAT,
1388 OPTION_DOUBLE_FLOAT,
1401 OPTION_MVXWORKS_PIC,
1406 struct option md_longopts[] =
1408 /* Options which specify architecture. */
1409 {"march", required_argument, NULL, OPTION_MARCH},
1410 {"mtune", required_argument, NULL, OPTION_MTUNE},
1411 {"mips0", no_argument, NULL, OPTION_MIPS1},
1412 {"mips1", no_argument, NULL, OPTION_MIPS1},
1413 {"mips2", no_argument, NULL, OPTION_MIPS2},
1414 {"mips3", no_argument, NULL, OPTION_MIPS3},
1415 {"mips4", no_argument, NULL, OPTION_MIPS4},
1416 {"mips5", no_argument, NULL, OPTION_MIPS5},
1417 {"mips32", no_argument, NULL, OPTION_MIPS32},
1418 {"mips64", no_argument, NULL, OPTION_MIPS64},
1419 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1420 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1422 /* Options which specify Application Specific Extensions (ASEs). */
1423 {"mips16", no_argument, NULL, OPTION_MIPS16},
1424 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1425 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1426 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1427 {"mdmx", no_argument, NULL, OPTION_MDMX},
1428 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1429 {"mdsp", no_argument, NULL, OPTION_DSP},
1430 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1431 {"mmt", no_argument, NULL, OPTION_MT},
1432 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1433 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1434 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1435 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1436 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1437 {"meva", no_argument, NULL, OPTION_EVA},
1438 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1439 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1440 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1441 {"mmcu", no_argument, NULL, OPTION_MCU},
1442 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1443 {"mvirt", no_argument, NULL, OPTION_VIRT},
1444 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1445 {"mmsa", no_argument, NULL, OPTION_MSA},
1446 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1448 /* Old-style architecture options. Don't add more of these. */
1449 {"m4650", no_argument, NULL, OPTION_M4650},
1450 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1451 {"m4010", no_argument, NULL, OPTION_M4010},
1452 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1453 {"m4100", no_argument, NULL, OPTION_M4100},
1454 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1455 {"m3900", no_argument, NULL, OPTION_M3900},
1456 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1458 /* Options which enable bug fixes. */
1459 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1460 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1461 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1462 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1463 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1464 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1465 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1466 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1467 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1468 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1469 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1470 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1471 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1472 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1473 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1475 /* Miscellaneous options. */
1476 {"trap", no_argument, NULL, OPTION_TRAP},
1477 {"no-break", no_argument, NULL, OPTION_TRAP},
1478 {"break", no_argument, NULL, OPTION_BREAK},
1479 {"no-trap", no_argument, NULL, OPTION_BREAK},
1480 {"EB", no_argument, NULL, OPTION_EB},
1481 {"EL", no_argument, NULL, OPTION_EL},
1482 {"mfp32", no_argument, NULL, OPTION_FP32},
1483 {"mgp32", no_argument, NULL, OPTION_GP32},
1484 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1485 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1486 {"mfp64", no_argument, NULL, OPTION_FP64},
1487 {"mgp64", no_argument, NULL, OPTION_GP64},
1488 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1489 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1490 {"minsn32", no_argument, NULL, OPTION_INSN32},
1491 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1492 {"mshared", no_argument, NULL, OPTION_MSHARED},
1493 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1494 {"msym32", no_argument, NULL, OPTION_MSYM32},
1495 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1496 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1497 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1498 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1499 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1501 /* Strictly speaking this next option is ELF specific,
1502 but we allow it for other ports as well in order to
1503 make testing easier. */
1504 {"32", no_argument, NULL, OPTION_32},
1506 /* ELF-specific options. */
1507 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1508 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1509 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1510 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1511 {"xgot", no_argument, NULL, OPTION_XGOT},
1512 {"mabi", required_argument, NULL, OPTION_MABI},
1513 {"n32", no_argument, NULL, OPTION_N32},
1514 {"64", no_argument, NULL, OPTION_64},
1515 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1516 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1517 {"mpdr", no_argument, NULL, OPTION_PDR},
1518 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1519 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1520 {"mnan", required_argument, NULL, OPTION_NAN},
1522 {NULL, no_argument, NULL, 0}
1524 size_t md_longopts_size = sizeof (md_longopts);
1526 /* Information about either an Application Specific Extension or an
1527 optional architecture feature that, for simplicity, we treat in the
1528 same way as an ASE. */
1531 /* The name of the ASE, used in both the command-line and .set options. */
1534 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1535 and 64-bit architectures, the flags here refer to the subset that
1536 is available on both. */
1539 /* The ASE_* flag used for instructions that are available on 64-bit
1540 architectures but that are not included in FLAGS. */
1541 unsigned int flags64;
1543 /* The command-line options that turn the ASE on and off. */
1547 /* The minimum required architecture revisions for MIPS32, MIPS64,
1548 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1551 int micromips32_rev;
1552 int micromips64_rev;
1555 /* A table of all supported ASEs. */
1556 static const struct mips_ase mips_ases[] = {
1557 { "dsp", ASE_DSP, ASE_DSP64,
1558 OPTION_DSP, OPTION_NO_DSP,
1561 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1562 OPTION_DSPR2, OPTION_NO_DSPR2,
1565 { "eva", ASE_EVA, 0,
1566 OPTION_EVA, OPTION_NO_EVA,
1569 { "mcu", ASE_MCU, 0,
1570 OPTION_MCU, OPTION_NO_MCU,
1573 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1574 { "mdmx", ASE_MDMX, 0,
1575 OPTION_MDMX, OPTION_NO_MDMX,
1578 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1579 { "mips3d", ASE_MIPS3D, 0,
1580 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1584 OPTION_MT, OPTION_NO_MT,
1587 { "smartmips", ASE_SMARTMIPS, 0,
1588 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1591 { "virt", ASE_VIRT, ASE_VIRT64,
1592 OPTION_VIRT, OPTION_NO_VIRT,
1595 { "msa", ASE_MSA, ASE_MSA64,
1596 OPTION_MSA, OPTION_NO_MSA,
1600 /* The set of ASEs that require -mfp64. */
1601 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1603 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1604 static const unsigned int mips_ase_groups[] = {
1610 The following pseudo-ops from the Kane and Heinrich MIPS book
1611 should be defined here, but are currently unsupported: .alias,
1612 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1614 The following pseudo-ops from the Kane and Heinrich MIPS book are
1615 specific to the type of debugging information being generated, and
1616 should be defined by the object format: .aent, .begin, .bend,
1617 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1620 The following pseudo-ops from the Kane and Heinrich MIPS book are
1621 not MIPS CPU specific, but are also not specific to the object file
1622 format. This file is probably the best place to define them, but
1623 they are not currently supported: .asm0, .endr, .lab, .struct. */
1625 static const pseudo_typeS mips_pseudo_table[] =
1627 /* MIPS specific pseudo-ops. */
1628 {"option", s_option, 0},
1629 {"set", s_mipsset, 0},
1630 {"rdata", s_change_sec, 'r'},
1631 {"sdata", s_change_sec, 's'},
1632 {"livereg", s_ignore, 0},
1633 {"abicalls", s_abicalls, 0},
1634 {"cpload", s_cpload, 0},
1635 {"cpsetup", s_cpsetup, 0},
1636 {"cplocal", s_cplocal, 0},
1637 {"cprestore", s_cprestore, 0},
1638 {"cpreturn", s_cpreturn, 0},
1639 {"dtprelword", s_dtprelword, 0},
1640 {"dtpreldword", s_dtpreldword, 0},
1641 {"tprelword", s_tprelword, 0},
1642 {"tpreldword", s_tpreldword, 0},
1643 {"gpvalue", s_gpvalue, 0},
1644 {"gpword", s_gpword, 0},
1645 {"gpdword", s_gpdword, 0},
1646 {"ehword", s_ehword, 0},
1647 {"cpadd", s_cpadd, 0},
1648 {"insn", s_insn, 0},
1651 /* Relatively generic pseudo-ops that happen to be used on MIPS
1653 {"asciiz", stringer, 8 + 1},
1654 {"bss", s_change_sec, 'b'},
1656 {"half", s_cons, 1},
1657 {"dword", s_cons, 3},
1658 {"weakext", s_mips_weakext, 0},
1659 {"origin", s_org, 0},
1660 {"repeat", s_rept, 0},
1662 /* For MIPS this is non-standard, but we define it for consistency. */
1663 {"sbss", s_change_sec, 'B'},
1665 /* These pseudo-ops are defined in read.c, but must be overridden
1666 here for one reason or another. */
1667 {"align", s_align, 0},
1668 {"byte", s_cons, 0},
1669 {"data", s_change_sec, 'd'},
1670 {"double", s_float_cons, 'd'},
1671 {"float", s_float_cons, 'f'},
1672 {"globl", s_mips_globl, 0},
1673 {"global", s_mips_globl, 0},
1674 {"hword", s_cons, 1},
1676 {"long", s_cons, 2},
1677 {"octa", s_cons, 4},
1678 {"quad", s_cons, 3},
1679 {"section", s_change_section, 0},
1680 {"short", s_cons, 1},
1681 {"single", s_float_cons, 'f'},
1682 {"stabd", s_mips_stab, 'd'},
1683 {"stabn", s_mips_stab, 'n'},
1684 {"stabs", s_mips_stab, 's'},
1685 {"text", s_change_sec, 't'},
1686 {"word", s_cons, 2},
1688 { "extern", ecoff_directive_extern, 0},
1693 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1695 /* These pseudo-ops should be defined by the object file format.
1696 However, a.out doesn't support them, so we have versions here. */
1697 {"aent", s_mips_ent, 1},
1698 {"bgnb", s_ignore, 0},
1699 {"end", s_mips_end, 0},
1700 {"endb", s_ignore, 0},
1701 {"ent", s_mips_ent, 0},
1702 {"file", s_mips_file, 0},
1703 {"fmask", s_mips_mask, 'F'},
1704 {"frame", s_mips_frame, 0},
1705 {"loc", s_mips_loc, 0},
1706 {"mask", s_mips_mask, 'R'},
1707 {"verstamp", s_ignore, 0},
1711 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1712 purpose of the `.dc.a' internal pseudo-op. */
1715 mips_address_bytes (void)
1717 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1720 extern void pop_insert (const pseudo_typeS *);
1723 mips_pop_insert (void)
1725 pop_insert (mips_pseudo_table);
1726 if (! ECOFF_DEBUGGING)
1727 pop_insert (mips_nonecoff_pseudo_table);
1730 /* Symbols labelling the current insn. */
1732 struct insn_label_list
1734 struct insn_label_list *next;
1738 static struct insn_label_list *free_insn_labels;
1739 #define label_list tc_segment_info_data.labels
1741 static void mips_clear_insn_labels (void);
1742 static void mips_mark_labels (void);
1743 static void mips_compressed_mark_labels (void);
1746 mips_clear_insn_labels (void)
1748 register struct insn_label_list **pl;
1749 segment_info_type *si;
1753 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1756 si = seg_info (now_seg);
1757 *pl = si->label_list;
1758 si->label_list = NULL;
1762 /* Mark instruction labels in MIPS16/microMIPS mode. */
1765 mips_mark_labels (void)
1767 if (HAVE_CODE_COMPRESSION)
1768 mips_compressed_mark_labels ();
1771 static char *expr_end;
1773 /* An expression in a macro instruction. This is set by mips_ip and
1774 mips16_ip and when populated is always an O_constant. */
1776 static expressionS imm_expr;
1778 /* The relocatable field in an instruction and the relocs associated
1779 with it. These variables are used for instructions like LUI and
1780 JAL as well as true offsets. They are also used for address
1781 operands in macros. */
1783 static expressionS offset_expr;
1784 static bfd_reloc_code_real_type offset_reloc[3]
1785 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1787 /* This is set to the resulting size of the instruction to be produced
1788 by mips16_ip if an explicit extension is used or by mips_ip if an
1789 explicit size is supplied. */
1791 static unsigned int forced_insn_length;
1793 /* True if we are assembling an instruction. All dot symbols defined during
1794 this time should be treated as code labels. */
1796 static bfd_boolean mips_assembling_insn;
1798 /* The pdr segment for per procedure frame/regmask info. Not used for
1801 static segT pdr_seg;
1803 /* The default target format to use. */
1805 #if defined (TE_FreeBSD)
1806 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1807 #elif defined (TE_TMIPS)
1808 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1810 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1814 mips_target_format (void)
1816 switch (OUTPUT_FLAVOR)
1818 case bfd_target_elf_flavour:
1820 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1821 return (target_big_endian
1822 ? "elf32-bigmips-vxworks"
1823 : "elf32-littlemips-vxworks");
1825 return (target_big_endian
1826 ? (HAVE_64BIT_OBJECTS
1827 ? ELF_TARGET ("elf64-", "big")
1829 ? ELF_TARGET ("elf32-n", "big")
1830 : ELF_TARGET ("elf32-", "big")))
1831 : (HAVE_64BIT_OBJECTS
1832 ? ELF_TARGET ("elf64-", "little")
1834 ? ELF_TARGET ("elf32-n", "little")
1835 : ELF_TARGET ("elf32-", "little"))));
1842 /* Return the ISA revision that is currently in use, or 0 if we are
1843 generating code for MIPS V or below. */
1848 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1851 /* microMIPS implies revision 2 or above. */
1852 if (mips_opts.micromips)
1855 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1861 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1864 mips_ase_mask (unsigned int flags)
1868 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1869 if (flags & mips_ase_groups[i])
1870 flags |= mips_ase_groups[i];
1874 /* Check whether the current ISA supports ASE. Issue a warning if
1878 mips_check_isa_supports_ase (const struct mips_ase *ase)
1882 static unsigned int warned_isa;
1883 static unsigned int warned_fp32;
1885 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1886 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1888 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1889 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1890 && (warned_isa & ase->flags) != ase->flags)
1892 warned_isa |= ase->flags;
1893 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1894 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1896 as_warn (_("the %d-bit %s architecture does not support the"
1897 " `%s' extension"), size, base, ase->name);
1899 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
1900 ase->name, base, size, min_rev);
1902 if ((ase->flags & FP64_ASES)
1904 && (warned_fp32 & ase->flags) != ase->flags)
1906 warned_fp32 |= ase->flags;
1907 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
1911 /* Check all enabled ASEs to see whether they are supported by the
1912 chosen architecture. */
1915 mips_check_isa_supports_ases (void)
1917 unsigned int i, mask;
1919 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1921 mask = mips_ase_mask (mips_ases[i].flags);
1922 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1923 mips_check_isa_supports_ase (&mips_ases[i]);
1927 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1928 that were affected. */
1931 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1935 mask = mips_ase_mask (ase->flags);
1936 mips_opts.ase &= ~mask;
1938 mips_opts.ase |= ase->flags;
1942 /* Return the ASE called NAME, or null if none. */
1944 static const struct mips_ase *
1945 mips_lookup_ase (const char *name)
1949 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1950 if (strcmp (name, mips_ases[i].name) == 0)
1951 return &mips_ases[i];
1955 /* Return the length of a microMIPS instruction in bytes. If bits of
1956 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1957 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1958 major opcode) will require further modifications to the opcode
1961 static inline unsigned int
1962 micromips_insn_length (const struct mips_opcode *mo)
1964 return (mo->mask >> 16) == 0 ? 2 : 4;
1967 /* Return the length of MIPS16 instruction OPCODE. */
1969 static inline unsigned int
1970 mips16_opcode_length (unsigned long opcode)
1972 return (opcode >> 16) == 0 ? 2 : 4;
1975 /* Return the length of instruction INSN. */
1977 static inline unsigned int
1978 insn_length (const struct mips_cl_insn *insn)
1980 if (mips_opts.micromips)
1981 return micromips_insn_length (insn->insn_mo);
1982 else if (mips_opts.mips16)
1983 return mips16_opcode_length (insn->insn_opcode);
1988 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1991 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1996 insn->insn_opcode = mo->match;
1999 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2000 insn->fixp[i] = NULL;
2001 insn->fixed_p = (mips_opts.noreorder > 0);
2002 insn->noreorder_p = (mips_opts.noreorder > 0);
2003 insn->mips16_absolute_jump_p = 0;
2004 insn->complete_p = 0;
2005 insn->cleared_p = 0;
2008 /* Get a list of all the operands in INSN. */
2010 static const struct mips_operand_array *
2011 insn_operands (const struct mips_cl_insn *insn)
2013 if (insn->insn_mo >= &mips_opcodes[0]
2014 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2015 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2017 if (insn->insn_mo >= &mips16_opcodes[0]
2018 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2019 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2021 if (insn->insn_mo >= µmips_opcodes[0]
2022 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2023 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2028 /* Get a description of operand OPNO of INSN. */
2030 static const struct mips_operand *
2031 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2033 const struct mips_operand_array *operands;
2035 operands = insn_operands (insn);
2036 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2038 return operands->operand[opno];
2041 /* Install UVAL as the value of OPERAND in INSN. */
2044 insn_insert_operand (struct mips_cl_insn *insn,
2045 const struct mips_operand *operand, unsigned int uval)
2047 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2050 /* Extract the value of OPERAND from INSN. */
2052 static inline unsigned
2053 insn_extract_operand (const struct mips_cl_insn *insn,
2054 const struct mips_operand *operand)
2056 return mips_extract_operand (operand, insn->insn_opcode);
2059 /* Record the current MIPS16/microMIPS mode in now_seg. */
2062 mips_record_compressed_mode (void)
2064 segment_info_type *si;
2066 si = seg_info (now_seg);
2067 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2068 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2069 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2070 si->tc_segment_info_data.micromips = mips_opts.micromips;
2073 /* Read a standard MIPS instruction from BUF. */
2075 static unsigned long
2076 read_insn (char *buf)
2078 if (target_big_endian)
2079 return bfd_getb32 ((bfd_byte *) buf);
2081 return bfd_getl32 ((bfd_byte *) buf);
2084 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2088 write_insn (char *buf, unsigned int insn)
2090 md_number_to_chars (buf, insn, 4);
2094 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2095 has length LENGTH. */
2097 static unsigned long
2098 read_compressed_insn (char *buf, unsigned int length)
2104 for (i = 0; i < length; i += 2)
2107 if (target_big_endian)
2108 insn |= bfd_getb16 ((char *) buf);
2110 insn |= bfd_getl16 ((char *) buf);
2116 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2117 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2120 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2124 for (i = 0; i < length; i += 2)
2125 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2126 return buf + length;
2129 /* Install INSN at the location specified by its "frag" and "where" fields. */
2132 install_insn (const struct mips_cl_insn *insn)
2134 char *f = insn->frag->fr_literal + insn->where;
2135 if (HAVE_CODE_COMPRESSION)
2136 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2138 write_insn (f, insn->insn_opcode);
2139 mips_record_compressed_mode ();
2142 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2143 and install the opcode in the new location. */
2146 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2151 insn->where = where;
2152 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2153 if (insn->fixp[i] != NULL)
2155 insn->fixp[i]->fx_frag = frag;
2156 insn->fixp[i]->fx_where = where;
2158 install_insn (insn);
2161 /* Add INSN to the end of the output. */
2164 add_fixed_insn (struct mips_cl_insn *insn)
2166 char *f = frag_more (insn_length (insn));
2167 move_insn (insn, frag_now, f - frag_now->fr_literal);
2170 /* Start a variant frag and move INSN to the start of the variant part,
2171 marking it as fixed. The other arguments are as for frag_var. */
2174 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2175 relax_substateT subtype, symbolS *symbol, offsetT offset)
2177 frag_grow (max_chars);
2178 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2180 frag_var (rs_machine_dependent, max_chars, var,
2181 subtype, symbol, offset, NULL);
2184 /* Insert N copies of INSN into the history buffer, starting at
2185 position FIRST. Neither FIRST nor N need to be clipped. */
2188 insert_into_history (unsigned int first, unsigned int n,
2189 const struct mips_cl_insn *insn)
2191 if (mips_relax.sequence != 2)
2195 for (i = ARRAY_SIZE (history); i-- > first;)
2197 history[i] = history[i - n];
2203 /* Clear the error in insn_error. */
2206 clear_insn_error (void)
2208 memset (&insn_error, 0, sizeof (insn_error));
2211 /* Possibly record error message MSG for the current instruction.
2212 If the error is about a particular argument, ARGNUM is the 1-based
2213 number of that argument, otherwise it is 0. FORMAT is the format
2214 of MSG. Return true if MSG was used, false if the current message
2218 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2223 /* Give priority to errors against specific arguments, and to
2224 the first whole-instruction message. */
2230 /* Keep insn_error if it is against a later argument. */
2231 if (argnum < insn_error.min_argnum)
2234 /* If both errors are against the same argument but are different,
2235 give up on reporting a specific error for this argument.
2236 See the comment about mips_insn_error for details. */
2237 if (argnum == insn_error.min_argnum
2239 && strcmp (insn_error.msg, msg) != 0)
2242 insn_error.min_argnum += 1;
2246 insn_error.min_argnum = argnum;
2247 insn_error.format = format;
2248 insn_error.msg = msg;
2252 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2253 as for set_insn_error_format. */
2256 set_insn_error (int argnum, const char *msg)
2258 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2261 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2262 as for set_insn_error_format. */
2265 set_insn_error_i (int argnum, const char *msg, int i)
2267 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2271 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2272 are as for set_insn_error_format. */
2275 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2277 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2279 insn_error.u.ss[0] = s1;
2280 insn_error.u.ss[1] = s2;
2284 /* Report the error in insn_error, which is against assembly code STR. */
2287 report_insn_error (const char *str)
2291 msg = ACONCAT ((insn_error.msg, " `%s'", NULL));
2292 switch (insn_error.format)
2299 as_bad (msg, insn_error.u.i, str);
2303 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2308 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2309 the idea is to make it obvious at a glance that each errata is
2313 init_vr4120_conflicts (void)
2315 #define CONFLICT(FIRST, SECOND) \
2316 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2318 /* Errata 21 - [D]DIV[U] after [D]MACC */
2319 CONFLICT (MACC, DIV);
2320 CONFLICT (DMACC, DIV);
2322 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2323 CONFLICT (DMULT, DMULT);
2324 CONFLICT (DMULT, DMACC);
2325 CONFLICT (DMACC, DMULT);
2326 CONFLICT (DMACC, DMACC);
2328 /* Errata 24 - MT{LO,HI} after [D]MACC */
2329 CONFLICT (MACC, MTHILO);
2330 CONFLICT (DMACC, MTHILO);
2332 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2333 instruction is executed immediately after a MACC or DMACC
2334 instruction, the result of [either instruction] is incorrect." */
2335 CONFLICT (MACC, MULT);
2336 CONFLICT (MACC, DMULT);
2337 CONFLICT (DMACC, MULT);
2338 CONFLICT (DMACC, DMULT);
2340 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2341 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2342 DDIV or DDIVU instruction, the result of the MACC or
2343 DMACC instruction is incorrect.". */
2344 CONFLICT (DMULT, MACC);
2345 CONFLICT (DMULT, DMACC);
2346 CONFLICT (DIV, MACC);
2347 CONFLICT (DIV, DMACC);
2357 #define RNUM_MASK 0x00000ff
2358 #define RTYPE_MASK 0x0ffff00
2359 #define RTYPE_NUM 0x0000100
2360 #define RTYPE_FPU 0x0000200
2361 #define RTYPE_FCC 0x0000400
2362 #define RTYPE_VEC 0x0000800
2363 #define RTYPE_GP 0x0001000
2364 #define RTYPE_CP0 0x0002000
2365 #define RTYPE_PC 0x0004000
2366 #define RTYPE_ACC 0x0008000
2367 #define RTYPE_CCC 0x0010000
2368 #define RTYPE_VI 0x0020000
2369 #define RTYPE_VF 0x0040000
2370 #define RTYPE_R5900_I 0x0080000
2371 #define RTYPE_R5900_Q 0x0100000
2372 #define RTYPE_R5900_R 0x0200000
2373 #define RTYPE_R5900_ACC 0x0400000
2374 #define RTYPE_MSA 0x0800000
2375 #define RWARN 0x8000000
2377 #define GENERIC_REGISTER_NUMBERS \
2378 {"$0", RTYPE_NUM | 0}, \
2379 {"$1", RTYPE_NUM | 1}, \
2380 {"$2", RTYPE_NUM | 2}, \
2381 {"$3", RTYPE_NUM | 3}, \
2382 {"$4", RTYPE_NUM | 4}, \
2383 {"$5", RTYPE_NUM | 5}, \
2384 {"$6", RTYPE_NUM | 6}, \
2385 {"$7", RTYPE_NUM | 7}, \
2386 {"$8", RTYPE_NUM | 8}, \
2387 {"$9", RTYPE_NUM | 9}, \
2388 {"$10", RTYPE_NUM | 10}, \
2389 {"$11", RTYPE_NUM | 11}, \
2390 {"$12", RTYPE_NUM | 12}, \
2391 {"$13", RTYPE_NUM | 13}, \
2392 {"$14", RTYPE_NUM | 14}, \
2393 {"$15", RTYPE_NUM | 15}, \
2394 {"$16", RTYPE_NUM | 16}, \
2395 {"$17", RTYPE_NUM | 17}, \
2396 {"$18", RTYPE_NUM | 18}, \
2397 {"$19", RTYPE_NUM | 19}, \
2398 {"$20", RTYPE_NUM | 20}, \
2399 {"$21", RTYPE_NUM | 21}, \
2400 {"$22", RTYPE_NUM | 22}, \
2401 {"$23", RTYPE_NUM | 23}, \
2402 {"$24", RTYPE_NUM | 24}, \
2403 {"$25", RTYPE_NUM | 25}, \
2404 {"$26", RTYPE_NUM | 26}, \
2405 {"$27", RTYPE_NUM | 27}, \
2406 {"$28", RTYPE_NUM | 28}, \
2407 {"$29", RTYPE_NUM | 29}, \
2408 {"$30", RTYPE_NUM | 30}, \
2409 {"$31", RTYPE_NUM | 31}
2411 #define FPU_REGISTER_NAMES \
2412 {"$f0", RTYPE_FPU | 0}, \
2413 {"$f1", RTYPE_FPU | 1}, \
2414 {"$f2", RTYPE_FPU | 2}, \
2415 {"$f3", RTYPE_FPU | 3}, \
2416 {"$f4", RTYPE_FPU | 4}, \
2417 {"$f5", RTYPE_FPU | 5}, \
2418 {"$f6", RTYPE_FPU | 6}, \
2419 {"$f7", RTYPE_FPU | 7}, \
2420 {"$f8", RTYPE_FPU | 8}, \
2421 {"$f9", RTYPE_FPU | 9}, \
2422 {"$f10", RTYPE_FPU | 10}, \
2423 {"$f11", RTYPE_FPU | 11}, \
2424 {"$f12", RTYPE_FPU | 12}, \
2425 {"$f13", RTYPE_FPU | 13}, \
2426 {"$f14", RTYPE_FPU | 14}, \
2427 {"$f15", RTYPE_FPU | 15}, \
2428 {"$f16", RTYPE_FPU | 16}, \
2429 {"$f17", RTYPE_FPU | 17}, \
2430 {"$f18", RTYPE_FPU | 18}, \
2431 {"$f19", RTYPE_FPU | 19}, \
2432 {"$f20", RTYPE_FPU | 20}, \
2433 {"$f21", RTYPE_FPU | 21}, \
2434 {"$f22", RTYPE_FPU | 22}, \
2435 {"$f23", RTYPE_FPU | 23}, \
2436 {"$f24", RTYPE_FPU | 24}, \
2437 {"$f25", RTYPE_FPU | 25}, \
2438 {"$f26", RTYPE_FPU | 26}, \
2439 {"$f27", RTYPE_FPU | 27}, \
2440 {"$f28", RTYPE_FPU | 28}, \
2441 {"$f29", RTYPE_FPU | 29}, \
2442 {"$f30", RTYPE_FPU | 30}, \
2443 {"$f31", RTYPE_FPU | 31}
2445 #define FPU_CONDITION_CODE_NAMES \
2446 {"$fcc0", RTYPE_FCC | 0}, \
2447 {"$fcc1", RTYPE_FCC | 1}, \
2448 {"$fcc2", RTYPE_FCC | 2}, \
2449 {"$fcc3", RTYPE_FCC | 3}, \
2450 {"$fcc4", RTYPE_FCC | 4}, \
2451 {"$fcc5", RTYPE_FCC | 5}, \
2452 {"$fcc6", RTYPE_FCC | 6}, \
2453 {"$fcc7", RTYPE_FCC | 7}
2455 #define COPROC_CONDITION_CODE_NAMES \
2456 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2457 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2458 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2459 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2460 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2461 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2462 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2463 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2465 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2466 {"$a4", RTYPE_GP | 8}, \
2467 {"$a5", RTYPE_GP | 9}, \
2468 {"$a6", RTYPE_GP | 10}, \
2469 {"$a7", RTYPE_GP | 11}, \
2470 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2471 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2472 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2473 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2474 {"$t0", RTYPE_GP | 12}, \
2475 {"$t1", RTYPE_GP | 13}, \
2476 {"$t2", RTYPE_GP | 14}, \
2477 {"$t3", RTYPE_GP | 15}
2479 #define O32_SYMBOLIC_REGISTER_NAMES \
2480 {"$t0", RTYPE_GP | 8}, \
2481 {"$t1", RTYPE_GP | 9}, \
2482 {"$t2", RTYPE_GP | 10}, \
2483 {"$t3", RTYPE_GP | 11}, \
2484 {"$t4", RTYPE_GP | 12}, \
2485 {"$t5", RTYPE_GP | 13}, \
2486 {"$t6", RTYPE_GP | 14}, \
2487 {"$t7", RTYPE_GP | 15}, \
2488 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2489 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2490 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2491 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2493 /* Remaining symbolic register names */
2494 #define SYMBOLIC_REGISTER_NAMES \
2495 {"$zero", RTYPE_GP | 0}, \
2496 {"$at", RTYPE_GP | 1}, \
2497 {"$AT", RTYPE_GP | 1}, \
2498 {"$v0", RTYPE_GP | 2}, \
2499 {"$v1", RTYPE_GP | 3}, \
2500 {"$a0", RTYPE_GP | 4}, \
2501 {"$a1", RTYPE_GP | 5}, \
2502 {"$a2", RTYPE_GP | 6}, \
2503 {"$a3", RTYPE_GP | 7}, \
2504 {"$s0", RTYPE_GP | 16}, \
2505 {"$s1", RTYPE_GP | 17}, \
2506 {"$s2", RTYPE_GP | 18}, \
2507 {"$s3", RTYPE_GP | 19}, \
2508 {"$s4", RTYPE_GP | 20}, \
2509 {"$s5", RTYPE_GP | 21}, \
2510 {"$s6", RTYPE_GP | 22}, \
2511 {"$s7", RTYPE_GP | 23}, \
2512 {"$t8", RTYPE_GP | 24}, \
2513 {"$t9", RTYPE_GP | 25}, \
2514 {"$k0", RTYPE_GP | 26}, \
2515 {"$kt0", RTYPE_GP | 26}, \
2516 {"$k1", RTYPE_GP | 27}, \
2517 {"$kt1", RTYPE_GP | 27}, \
2518 {"$gp", RTYPE_GP | 28}, \
2519 {"$sp", RTYPE_GP | 29}, \
2520 {"$s8", RTYPE_GP | 30}, \
2521 {"$fp", RTYPE_GP | 30}, \
2522 {"$ra", RTYPE_GP | 31}
2524 #define MIPS16_SPECIAL_REGISTER_NAMES \
2525 {"$pc", RTYPE_PC | 0}
2527 #define MDMX_VECTOR_REGISTER_NAMES \
2528 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2529 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2530 {"$v2", RTYPE_VEC | 2}, \
2531 {"$v3", RTYPE_VEC | 3}, \
2532 {"$v4", RTYPE_VEC | 4}, \
2533 {"$v5", RTYPE_VEC | 5}, \
2534 {"$v6", RTYPE_VEC | 6}, \
2535 {"$v7", RTYPE_VEC | 7}, \
2536 {"$v8", RTYPE_VEC | 8}, \
2537 {"$v9", RTYPE_VEC | 9}, \
2538 {"$v10", RTYPE_VEC | 10}, \
2539 {"$v11", RTYPE_VEC | 11}, \
2540 {"$v12", RTYPE_VEC | 12}, \
2541 {"$v13", RTYPE_VEC | 13}, \
2542 {"$v14", RTYPE_VEC | 14}, \
2543 {"$v15", RTYPE_VEC | 15}, \
2544 {"$v16", RTYPE_VEC | 16}, \
2545 {"$v17", RTYPE_VEC | 17}, \
2546 {"$v18", RTYPE_VEC | 18}, \
2547 {"$v19", RTYPE_VEC | 19}, \
2548 {"$v20", RTYPE_VEC | 20}, \
2549 {"$v21", RTYPE_VEC | 21}, \
2550 {"$v22", RTYPE_VEC | 22}, \
2551 {"$v23", RTYPE_VEC | 23}, \
2552 {"$v24", RTYPE_VEC | 24}, \
2553 {"$v25", RTYPE_VEC | 25}, \
2554 {"$v26", RTYPE_VEC | 26}, \
2555 {"$v27", RTYPE_VEC | 27}, \
2556 {"$v28", RTYPE_VEC | 28}, \
2557 {"$v29", RTYPE_VEC | 29}, \
2558 {"$v30", RTYPE_VEC | 30}, \
2559 {"$v31", RTYPE_VEC | 31}
2561 #define R5900_I_NAMES \
2562 {"$I", RTYPE_R5900_I | 0}
2564 #define R5900_Q_NAMES \
2565 {"$Q", RTYPE_R5900_Q | 0}
2567 #define R5900_R_NAMES \
2568 {"$R", RTYPE_R5900_R | 0}
2570 #define R5900_ACC_NAMES \
2571 {"$ACC", RTYPE_R5900_ACC | 0 }
2573 #define MIPS_DSP_ACCUMULATOR_NAMES \
2574 {"$ac0", RTYPE_ACC | 0}, \
2575 {"$ac1", RTYPE_ACC | 1}, \
2576 {"$ac2", RTYPE_ACC | 2}, \
2577 {"$ac3", RTYPE_ACC | 3}
2579 static const struct regname reg_names[] = {
2580 GENERIC_REGISTER_NUMBERS,
2582 FPU_CONDITION_CODE_NAMES,
2583 COPROC_CONDITION_CODE_NAMES,
2585 /* The $txx registers depends on the abi,
2586 these will be added later into the symbol table from
2587 one of the tables below once mips_abi is set after
2588 parsing of arguments from the command line. */
2589 SYMBOLIC_REGISTER_NAMES,
2591 MIPS16_SPECIAL_REGISTER_NAMES,
2592 MDMX_VECTOR_REGISTER_NAMES,
2597 MIPS_DSP_ACCUMULATOR_NAMES,
2601 static const struct regname reg_names_o32[] = {
2602 O32_SYMBOLIC_REGISTER_NAMES,
2606 static const struct regname reg_names_n32n64[] = {
2607 N32N64_SYMBOLIC_REGISTER_NAMES,
2611 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2612 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2613 of these register symbols, return the associated vector register,
2614 otherwise return SYMVAL itself. */
2617 mips_prefer_vec_regno (unsigned int symval)
2619 if ((symval & -2) == (RTYPE_GP | 2))
2620 return RTYPE_VEC | (symval & 1);
2624 /* Return true if string [S, E) is a valid register name, storing its
2625 symbol value in *SYMVAL_PTR if so. */
2628 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2633 /* Terminate name. */
2637 /* Look up the name. */
2638 symbol = symbol_find (s);
2641 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2644 *symval_ptr = S_GET_VALUE (symbol);
2648 /* Return true if the string at *SPTR is a valid register name. Allow it
2649 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2652 When returning true, move *SPTR past the register, store the
2653 register's symbol value in *SYMVAL_PTR and the channel mask in
2654 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2655 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2656 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2659 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2660 unsigned int *channels_ptr)
2664 unsigned int channels, symval, bit;
2666 /* Find end of name. */
2668 if (is_name_beginner (*e))
2670 while (is_part_of_name (*e))
2674 if (!mips_parse_register_1 (s, e, &symval))
2679 /* Eat characters from the end of the string that are valid
2680 channel suffixes. The preceding register must be $ACC or
2681 end with a digit, so there is no ambiguity. */
2684 for (q = "wzyx"; *q; q++, bit <<= 1)
2685 if (m > s && m[-1] == *q)
2692 || !mips_parse_register_1 (s, m, &symval)
2693 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2698 *symval_ptr = symval;
2700 *channels_ptr = channels;
2704 /* Check if SPTR points at a valid register specifier according to TYPES.
2705 If so, then return 1, advance S to consume the specifier and store
2706 the register's number in REGNOP, otherwise return 0. */
2709 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2713 if (mips_parse_register (s, ®no, NULL))
2715 if (types & RTYPE_VEC)
2716 regno = mips_prefer_vec_regno (regno);
2725 as_warn (_("unrecognized register name `%s'"), *s);
2730 return regno <= RNUM_MASK;
2733 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2734 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2737 mips_parse_vu0_channels (char *s, unsigned int *channels)
2742 for (i = 0; i < 4; i++)
2743 if (*s == "xyzw"[i])
2745 *channels |= 1 << (3 - i);
2751 /* Token types for parsed operand lists. */
2752 enum mips_operand_token_type {
2753 /* A plain register, e.g. $f2. */
2756 /* A 4-bit XYZW channel mask. */
2759 /* A constant vector index, e.g. [1]. */
2762 /* A register vector index, e.g. [$2]. */
2765 /* A continuous range of registers, e.g. $s0-$s4. */
2768 /* A (possibly relocated) expression. */
2771 /* A floating-point value. */
2774 /* A single character. This can be '(', ')' or ',', but '(' only appears
2778 /* A doubled character, either "--" or "++". */
2781 /* The end of the operand list. */
2785 /* A parsed operand token. */
2786 struct mips_operand_token
2788 /* The type of token. */
2789 enum mips_operand_token_type type;
2792 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2795 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2796 unsigned int channels;
2798 /* The integer value of an OT_INTEGER_INDEX. */
2801 /* The two register symbol values involved in an OT_REG_RANGE. */
2803 unsigned int regno1;
2804 unsigned int regno2;
2807 /* The value of an OT_INTEGER. The value is represented as an
2808 expression and the relocation operators that were applied to
2809 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2810 relocation operators were used. */
2813 bfd_reloc_code_real_type relocs[3];
2816 /* The binary data for an OT_FLOAT constant, and the number of bytes
2819 unsigned char data[8];
2823 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2828 /* An obstack used to construct lists of mips_operand_tokens. */
2829 static struct obstack mips_operand_tokens;
2831 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2834 mips_add_token (struct mips_operand_token *token,
2835 enum mips_operand_token_type type)
2838 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2841 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2842 and OT_REG tokens for them if so, and return a pointer to the first
2843 unconsumed character. Return null otherwise. */
2846 mips_parse_base_start (char *s)
2848 struct mips_operand_token token;
2849 unsigned int regno, channels;
2850 bfd_boolean decrement_p;
2856 SKIP_SPACE_TABS (s);
2858 /* Only match "--" as part of a base expression. In other contexts "--X"
2859 is a double negative. */
2860 decrement_p = (s[0] == '-' && s[1] == '-');
2864 SKIP_SPACE_TABS (s);
2867 /* Allow a channel specifier because that leads to better error messages
2868 than treating something like "$vf0x++" as an expression. */
2869 if (!mips_parse_register (&s, ®no, &channels))
2873 mips_add_token (&token, OT_CHAR);
2878 mips_add_token (&token, OT_DOUBLE_CHAR);
2881 token.u.regno = regno;
2882 mips_add_token (&token, OT_REG);
2886 token.u.channels = channels;
2887 mips_add_token (&token, OT_CHANNELS);
2890 /* For consistency, only match "++" as part of base expressions too. */
2891 SKIP_SPACE_TABS (s);
2892 if (s[0] == '+' && s[1] == '+')
2896 mips_add_token (&token, OT_DOUBLE_CHAR);
2902 /* Parse one or more tokens from S. Return a pointer to the first
2903 unconsumed character on success. Return null if an error was found
2904 and store the error text in insn_error. FLOAT_FORMAT is as for
2905 mips_parse_arguments. */
2908 mips_parse_argument_token (char *s, char float_format)
2910 char *end, *save_in, *err;
2911 unsigned int regno1, regno2, channels;
2912 struct mips_operand_token token;
2914 /* First look for "($reg", since we want to treat that as an
2915 OT_CHAR and OT_REG rather than an expression. */
2916 end = mips_parse_base_start (s);
2920 /* Handle other characters that end up as OT_CHARs. */
2921 if (*s == ')' || *s == ',')
2924 mips_add_token (&token, OT_CHAR);
2929 /* Handle tokens that start with a register. */
2930 if (mips_parse_register (&s, ®no1, &channels))
2934 /* A register and a VU0 channel suffix. */
2935 token.u.regno = regno1;
2936 mips_add_token (&token, OT_REG);
2938 token.u.channels = channels;
2939 mips_add_token (&token, OT_CHANNELS);
2943 SKIP_SPACE_TABS (s);
2946 /* A register range. */
2948 SKIP_SPACE_TABS (s);
2949 if (!mips_parse_register (&s, ®no2, NULL))
2951 set_insn_error (0, _("invalid register range"));
2955 token.u.reg_range.regno1 = regno1;
2956 token.u.reg_range.regno2 = regno2;
2957 mips_add_token (&token, OT_REG_RANGE);
2961 /* Add the register itself. */
2962 token.u.regno = regno1;
2963 mips_add_token (&token, OT_REG);
2965 /* Check for a vector index. */
2969 SKIP_SPACE_TABS (s);
2970 if (mips_parse_register (&s, &token.u.regno, NULL))
2971 mips_add_token (&token, OT_REG_INDEX);
2974 expressionS element;
2976 my_getExpression (&element, s);
2977 if (element.X_op != O_constant)
2979 set_insn_error (0, _("vector element must be constant"));
2983 token.u.index = element.X_add_number;
2984 mips_add_token (&token, OT_INTEGER_INDEX);
2986 SKIP_SPACE_TABS (s);
2989 set_insn_error (0, _("missing `]'"));
2999 /* First try to treat expressions as floats. */
3000 save_in = input_line_pointer;
3001 input_line_pointer = s;
3002 err = md_atof (float_format, (char *) token.u.flt.data,
3003 &token.u.flt.length);
3004 end = input_line_pointer;
3005 input_line_pointer = save_in;
3008 set_insn_error (0, err);
3013 mips_add_token (&token, OT_FLOAT);
3018 /* Treat everything else as an integer expression. */
3019 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3020 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3021 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3022 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3024 mips_add_token (&token, OT_INTEGER);
3028 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3029 if expressions should be treated as 32-bit floating-point constants,
3030 'd' if they should be treated as 64-bit floating-point constants,
3031 or 0 if they should be treated as integer expressions (the usual case).
3033 Return a list of tokens on success, otherwise return 0. The caller
3034 must obstack_free the list after use. */
3036 static struct mips_operand_token *
3037 mips_parse_arguments (char *s, char float_format)
3039 struct mips_operand_token token;
3041 SKIP_SPACE_TABS (s);
3044 s = mips_parse_argument_token (s, float_format);
3047 obstack_free (&mips_operand_tokens,
3048 obstack_finish (&mips_operand_tokens));
3051 SKIP_SPACE_TABS (s);
3053 mips_add_token (&token, OT_END);
3054 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3057 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3058 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3061 is_opcode_valid (const struct mips_opcode *mo)
3063 int isa = mips_opts.isa;
3064 int ase = mips_opts.ase;
3068 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3069 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3070 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3071 ase |= mips_ases[i].flags64;
3073 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3076 /* Check whether the instruction or macro requires single-precision or
3077 double-precision floating-point support. Note that this information is
3078 stored differently in the opcode table for insns and macros. */
3079 if (mo->pinfo == INSN_MACRO)
3081 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3082 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3086 fp_s = mo->pinfo & FP_S;
3087 fp_d = mo->pinfo & FP_D;
3090 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3093 if (fp_s && mips_opts.soft_float)
3099 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3100 selected ISA and architecture. */
3103 is_opcode_valid_16 (const struct mips_opcode *mo)
3105 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3108 /* Return TRUE if the size of the microMIPS opcode MO matches one
3109 explicitly requested. Always TRUE in the standard MIPS mode. */
3112 is_size_valid (const struct mips_opcode *mo)
3114 if (!mips_opts.micromips)
3117 if (mips_opts.insn32)
3119 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3121 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3124 if (!forced_insn_length)
3126 if (mo->pinfo == INSN_MACRO)
3128 return forced_insn_length == micromips_insn_length (mo);
3131 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3132 of the preceding instruction. Always TRUE in the standard MIPS mode.
3134 We don't accept macros in 16-bit delay slots to avoid a case where
3135 a macro expansion fails because it relies on a preceding 32-bit real
3136 instruction to have matched and does not handle the operands correctly.
3137 The only macros that may expand to 16-bit instructions are JAL that
3138 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3139 and BGT (that likewise cannot be placed in a delay slot) that decay to
3140 a NOP. In all these cases the macros precede any corresponding real
3141 instruction definitions in the opcode table, so they will match in the
3142 second pass where the size of the delay slot is ignored and therefore
3143 produce correct code. */
3146 is_delay_slot_valid (const struct mips_opcode *mo)
3148 if (!mips_opts.micromips)
3151 if (mo->pinfo == INSN_MACRO)
3152 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3153 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3154 && micromips_insn_length (mo) != 4)
3156 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3157 && micromips_insn_length (mo) != 2)
3163 /* For consistency checking, verify that all bits of OPCODE are specified
3164 either by the match/mask part of the instruction definition, or by the
3165 operand list. Also build up a list of operands in OPERANDS.
3167 INSN_BITS says which bits of the instruction are significant.
3168 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3169 provides the mips_operand description of each operand. DECODE_OPERAND
3170 is null for MIPS16 instructions. */
3173 validate_mips_insn (const struct mips_opcode *opcode,
3174 unsigned long insn_bits,
3175 const struct mips_operand *(*decode_operand) (const char *),
3176 struct mips_operand_array *operands)
3179 unsigned long used_bits, doubled, undefined, opno, mask;
3180 const struct mips_operand *operand;
3182 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3183 if ((mask & opcode->match) != opcode->match)
3185 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3186 opcode->name, opcode->args);
3191 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3192 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3193 for (s = opcode->args; *s; ++s)
3206 if (!decode_operand)
3207 operand = decode_mips16_operand (*s, FALSE);
3209 operand = decode_operand (s);
3210 if (!operand && opcode->pinfo != INSN_MACRO)
3212 as_bad (_("internal: unknown operand type: %s %s"),
3213 opcode->name, opcode->args);
3216 gas_assert (opno < MAX_OPERANDS);
3217 operands->operand[opno] = operand;
3218 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3220 used_bits = mips_insert_operand (operand, used_bits, -1);
3221 if (operand->type == OP_MDMX_IMM_REG)
3222 /* Bit 5 is the format selector (OB vs QH). The opcode table
3223 has separate entries for each format. */
3224 used_bits &= ~(1 << (operand->lsb + 5));
3225 if (operand->type == OP_ENTRY_EXIT_LIST)
3226 used_bits &= ~(mask & 0x700);
3228 /* Skip prefix characters. */
3229 if (decode_operand && (*s == '+' || *s == 'm'))
3234 doubled = used_bits & mask & insn_bits;
3237 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3238 " %s %s"), doubled, opcode->name, opcode->args);
3242 undefined = ~used_bits & insn_bits;
3243 if (opcode->pinfo != INSN_MACRO && undefined)
3245 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3246 undefined, opcode->name, opcode->args);
3249 used_bits &= ~insn_bits;
3252 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3253 used_bits, opcode->name, opcode->args);
3259 /* The MIPS16 version of validate_mips_insn. */
3262 validate_mips16_insn (const struct mips_opcode *opcode,
3263 struct mips_operand_array *operands)
3265 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3267 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3268 instruction. Use TMP to describe the full instruction. */
3269 struct mips_opcode tmp;
3274 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3276 return validate_mips_insn (opcode, 0xffff, 0, operands);
3279 /* The microMIPS version of validate_mips_insn. */
3282 validate_micromips_insn (const struct mips_opcode *opc,
3283 struct mips_operand_array *operands)
3285 unsigned long insn_bits;
3286 unsigned long major;
3287 unsigned int length;
3289 if (opc->pinfo == INSN_MACRO)
3290 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3293 length = micromips_insn_length (opc);
3294 if (length != 2 && length != 4)
3296 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3297 "%s %s"), length, opc->name, opc->args);
3300 major = opc->match >> (10 + 8 * (length - 2));
3301 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3302 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3304 as_bad (_("internal error: bad microMIPS opcode "
3305 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3309 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3310 insn_bits = 1 << 4 * length;
3311 insn_bits <<= 4 * length;
3313 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3317 /* This function is called once, at assembler startup time. It should set up
3318 all the tables, etc. that the MD part of the assembler will need. */
3323 const char *retval = NULL;
3327 if (mips_pic != NO_PIC)
3329 if (g_switch_seen && g_switch_value != 0)
3330 as_bad (_("-G may not be used in position-independent code"));
3334 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
3335 as_warn (_("could not set architecture and machine"));
3337 op_hash = hash_new ();
3339 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3340 for (i = 0; i < NUMOPCODES;)
3342 const char *name = mips_opcodes[i].name;
3344 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3347 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3348 mips_opcodes[i].name, retval);
3349 /* Probably a memory allocation problem? Give up now. */
3350 as_fatal (_("broken assembler, no assembly attempted"));
3354 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3355 decode_mips_operand, &mips_operands[i]))
3357 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3359 create_insn (&nop_insn, mips_opcodes + i);
3360 if (mips_fix_loongson2f_nop)
3361 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3362 nop_insn.fixed_p = 1;
3366 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3369 mips16_op_hash = hash_new ();
3370 mips16_operands = XCNEWVEC (struct mips_operand_array,
3371 bfd_mips16_num_opcodes);
3374 while (i < bfd_mips16_num_opcodes)
3376 const char *name = mips16_opcodes[i].name;
3378 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3380 as_fatal (_("internal: can't hash `%s': %s"),
3381 mips16_opcodes[i].name, retval);
3384 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3386 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3388 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3389 mips16_nop_insn.fixed_p = 1;
3393 while (i < bfd_mips16_num_opcodes
3394 && strcmp (mips16_opcodes[i].name, name) == 0);
3397 micromips_op_hash = hash_new ();
3398 micromips_operands = XCNEWVEC (struct mips_operand_array,
3399 bfd_micromips_num_opcodes);
3402 while (i < bfd_micromips_num_opcodes)
3404 const char *name = micromips_opcodes[i].name;
3406 retval = hash_insert (micromips_op_hash, name,
3407 (void *) µmips_opcodes[i]);
3409 as_fatal (_("internal: can't hash `%s': %s"),
3410 micromips_opcodes[i].name, retval);
3413 struct mips_cl_insn *micromips_nop_insn;
3415 if (!validate_micromips_insn (µmips_opcodes[i],
3416 µmips_operands[i]))
3419 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3421 if (micromips_insn_length (micromips_opcodes + i) == 2)
3422 micromips_nop_insn = µmips_nop16_insn;
3423 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3424 micromips_nop_insn = µmips_nop32_insn;
3428 if (micromips_nop_insn->insn_mo == NULL
3429 && strcmp (name, "nop") == 0)
3431 create_insn (micromips_nop_insn, micromips_opcodes + i);
3432 micromips_nop_insn->fixed_p = 1;
3436 while (++i < bfd_micromips_num_opcodes
3437 && strcmp (micromips_opcodes[i].name, name) == 0);
3441 as_fatal (_("broken assembler, no assembly attempted"));
3443 /* We add all the general register names to the symbol table. This
3444 helps us detect invalid uses of them. */
3445 for (i = 0; reg_names[i].name; i++)
3446 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3447 reg_names[i].num, /* & RNUM_MASK, */
3448 &zero_address_frag));
3450 for (i = 0; reg_names_n32n64[i].name; i++)
3451 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3452 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3453 &zero_address_frag));
3455 for (i = 0; reg_names_o32[i].name; i++)
3456 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3457 reg_names_o32[i].num, /* & RNUM_MASK, */
3458 &zero_address_frag));
3460 for (i = 0; i < 32; i++)
3464 /* R5900 VU0 floating-point register. */
3465 regname[sizeof (rename) - 1] = 0;
3466 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3467 symbol_table_insert (symbol_new (regname, reg_section,
3468 RTYPE_VF | i, &zero_address_frag));
3470 /* R5900 VU0 integer register. */
3471 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3472 symbol_table_insert (symbol_new (regname, reg_section,
3473 RTYPE_VI | i, &zero_address_frag));
3476 snprintf (regname, sizeof (regname) - 1, "$w%d", i);
3477 symbol_table_insert (symbol_new (regname, reg_section,
3478 RTYPE_MSA | i, &zero_address_frag));
3481 obstack_init (&mips_operand_tokens);
3483 mips_no_prev_insn ();
3486 mips_cprmask[0] = 0;
3487 mips_cprmask[1] = 0;
3488 mips_cprmask[2] = 0;
3489 mips_cprmask[3] = 0;
3491 /* set the default alignment for the text section (2**2) */
3492 record_alignment (text_section, 2);
3494 bfd_set_gp_size (stdoutput, g_switch_value);
3496 /* On a native system other than VxWorks, sections must be aligned
3497 to 16 byte boundaries. When configured for an embedded ELF
3498 target, we don't bother. */
3499 if (strncmp (TARGET_OS, "elf", 3) != 0
3500 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3502 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3503 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3504 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3507 /* Create a .reginfo section for register masks and a .mdebug
3508 section for debugging information. */
3516 subseg = now_subseg;
3518 /* The ABI says this section should be loaded so that the
3519 running program can access it. However, we don't load it
3520 if we are configured for an embedded target */
3521 flags = SEC_READONLY | SEC_DATA;
3522 if (strncmp (TARGET_OS, "elf", 3) != 0)
3523 flags |= SEC_ALLOC | SEC_LOAD;
3525 if (mips_abi != N64_ABI)
3527 sec = subseg_new (".reginfo", (subsegT) 0);
3529 bfd_set_section_flags (stdoutput, sec, flags);
3530 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3532 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3536 /* The 64-bit ABI uses a .MIPS.options section rather than
3537 .reginfo section. */
3538 sec = subseg_new (".MIPS.options", (subsegT) 0);
3539 bfd_set_section_flags (stdoutput, sec, flags);
3540 bfd_set_section_alignment (stdoutput, sec, 3);
3542 /* Set up the option header. */
3544 Elf_Internal_Options opthdr;
3547 opthdr.kind = ODK_REGINFO;
3548 opthdr.size = (sizeof (Elf_External_Options)
3549 + sizeof (Elf64_External_RegInfo));
3552 f = frag_more (sizeof (Elf_External_Options));
3553 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3554 (Elf_External_Options *) f);
3556 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3560 if (ECOFF_DEBUGGING)
3562 sec = subseg_new (".mdebug", (subsegT) 0);
3563 (void) bfd_set_section_flags (stdoutput, sec,
3564 SEC_HAS_CONTENTS | SEC_READONLY);
3565 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3567 else if (mips_flag_pdr)
3569 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3570 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3571 SEC_READONLY | SEC_RELOC
3573 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3576 subseg_set (seg, subseg);
3579 if (! ECOFF_DEBUGGING)
3582 if (mips_fix_vr4120)
3583 init_vr4120_conflicts ();
3589 mips_emit_delays ();
3590 if (! ECOFF_DEBUGGING)
3595 md_assemble (char *str)
3597 struct mips_cl_insn insn;
3598 bfd_reloc_code_real_type unused_reloc[3]
3599 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3601 imm_expr.X_op = O_absent;
3602 offset_expr.X_op = O_absent;
3603 offset_reloc[0] = BFD_RELOC_UNUSED;
3604 offset_reloc[1] = BFD_RELOC_UNUSED;
3605 offset_reloc[2] = BFD_RELOC_UNUSED;
3607 mips_mark_labels ();
3608 mips_assembling_insn = TRUE;
3609 clear_insn_error ();
3611 if (mips_opts.mips16)
3612 mips16_ip (str, &insn);
3615 mips_ip (str, &insn);
3616 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3617 str, insn.insn_opcode));
3621 report_insn_error (str);
3622 else if (insn.insn_mo->pinfo == INSN_MACRO)
3625 if (mips_opts.mips16)
3626 mips16_macro (&insn);
3633 if (offset_expr.X_op != O_absent)
3634 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3636 append_insn (&insn, NULL, unused_reloc, FALSE);
3639 mips_assembling_insn = FALSE;
3642 /* Convenience functions for abstracting away the differences between
3643 MIPS16 and non-MIPS16 relocations. */
3645 static inline bfd_boolean
3646 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3650 case BFD_RELOC_MIPS16_JMP:
3651 case BFD_RELOC_MIPS16_GPREL:
3652 case BFD_RELOC_MIPS16_GOT16:
3653 case BFD_RELOC_MIPS16_CALL16:
3654 case BFD_RELOC_MIPS16_HI16_S:
3655 case BFD_RELOC_MIPS16_HI16:
3656 case BFD_RELOC_MIPS16_LO16:
3664 static inline bfd_boolean
3665 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3669 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3670 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3671 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3672 case BFD_RELOC_MICROMIPS_GPREL16:
3673 case BFD_RELOC_MICROMIPS_JMP:
3674 case BFD_RELOC_MICROMIPS_HI16:
3675 case BFD_RELOC_MICROMIPS_HI16_S:
3676 case BFD_RELOC_MICROMIPS_LO16:
3677 case BFD_RELOC_MICROMIPS_LITERAL:
3678 case BFD_RELOC_MICROMIPS_GOT16:
3679 case BFD_RELOC_MICROMIPS_CALL16:
3680 case BFD_RELOC_MICROMIPS_GOT_HI16:
3681 case BFD_RELOC_MICROMIPS_GOT_LO16:
3682 case BFD_RELOC_MICROMIPS_CALL_HI16:
3683 case BFD_RELOC_MICROMIPS_CALL_LO16:
3684 case BFD_RELOC_MICROMIPS_SUB:
3685 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3686 case BFD_RELOC_MICROMIPS_GOT_OFST:
3687 case BFD_RELOC_MICROMIPS_GOT_DISP:
3688 case BFD_RELOC_MICROMIPS_HIGHEST:
3689 case BFD_RELOC_MICROMIPS_HIGHER:
3690 case BFD_RELOC_MICROMIPS_SCN_DISP:
3691 case BFD_RELOC_MICROMIPS_JALR:
3699 static inline bfd_boolean
3700 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3702 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3705 static inline bfd_boolean
3706 got16_reloc_p (bfd_reloc_code_real_type reloc)
3708 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3709 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3712 static inline bfd_boolean
3713 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3715 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3716 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3719 static inline bfd_boolean
3720 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3722 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3723 || reloc == BFD_RELOC_MICROMIPS_LO16);
3726 static inline bfd_boolean
3727 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3729 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3732 static inline bfd_boolean
3733 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3735 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3736 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3739 /* Return true if RELOC is a PC-relative relocation that does not have
3740 full address range. */
3742 static inline bfd_boolean
3743 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3747 case BFD_RELOC_16_PCREL_S2:
3748 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3749 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3750 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3753 case BFD_RELOC_32_PCREL:
3754 return HAVE_64BIT_ADDRESSES;
3761 /* Return true if the given relocation might need a matching %lo().
3762 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3763 need a matching %lo() when applied to local symbols. */
3765 static inline bfd_boolean
3766 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3768 return (HAVE_IN_PLACE_ADDENDS
3769 && (hi16_reloc_p (reloc)
3770 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3771 all GOT16 relocations evaluate to "G". */
3772 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3775 /* Return the type of %lo() reloc needed by RELOC, given that
3776 reloc_needs_lo_p. */
3778 static inline bfd_reloc_code_real_type
3779 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3781 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3782 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3786 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3789 static inline bfd_boolean
3790 fixup_has_matching_lo_p (fixS *fixp)
3792 return (fixp->fx_next != NULL
3793 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3794 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3795 && fixp->fx_offset == fixp->fx_next->fx_offset);
3798 /* Move all labels in LABELS to the current insertion point. TEXT_P
3799 says whether the labels refer to text or data. */
3802 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3804 struct insn_label_list *l;
3807 for (l = labels; l != NULL; l = l->next)
3809 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3810 symbol_set_frag (l->label, frag_now);
3811 val = (valueT) frag_now_fix ();
3812 /* MIPS16/microMIPS text labels are stored as odd. */
3813 if (text_p && HAVE_CODE_COMPRESSION)
3815 S_SET_VALUE (l->label, val);
3819 /* Move all labels in insn_labels to the current insertion point
3820 and treat them as text labels. */
3823 mips_move_text_labels (void)
3825 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3829 s_is_linkonce (symbolS *sym, segT from_seg)
3831 bfd_boolean linkonce = FALSE;
3832 segT symseg = S_GET_SEGMENT (sym);
3834 if (symseg != from_seg && !S_IS_LOCAL (sym))
3836 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3838 /* The GNU toolchain uses an extension for ELF: a section
3839 beginning with the magic string .gnu.linkonce is a
3840 linkonce section. */
3841 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3842 sizeof ".gnu.linkonce" - 1) == 0)
3848 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3849 linker to handle them specially, such as generating jalx instructions
3850 when needed. We also make them odd for the duration of the assembly,
3851 in order to generate the right sort of code. We will make them even
3852 in the adjust_symtab routine, while leaving them marked. This is
3853 convenient for the debugger and the disassembler. The linker knows
3854 to make them odd again. */
3857 mips_compressed_mark_label (symbolS *label)
3859 gas_assert (HAVE_CODE_COMPRESSION);
3861 if (mips_opts.mips16)
3862 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3864 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3865 if ((S_GET_VALUE (label) & 1) == 0
3866 /* Don't adjust the address if the label is global or weak, or
3867 in a link-once section, since we'll be emitting symbol reloc
3868 references to it which will be patched up by the linker, and
3869 the final value of the symbol may or may not be MIPS16/microMIPS. */
3870 && !S_IS_WEAK (label)
3871 && !S_IS_EXTERNAL (label)
3872 && !s_is_linkonce (label, now_seg))
3873 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3876 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3879 mips_compressed_mark_labels (void)
3881 struct insn_label_list *l;
3883 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3884 mips_compressed_mark_label (l->label);
3887 /* End the current frag. Make it a variant frag and record the
3891 relax_close_frag (void)
3893 mips_macro_warning.first_frag = frag_now;
3894 frag_var (rs_machine_dependent, 0, 0,
3895 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3896 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3898 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3899 mips_relax.first_fixup = 0;
3902 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3903 See the comment above RELAX_ENCODE for more details. */
3906 relax_start (symbolS *symbol)
3908 gas_assert (mips_relax.sequence == 0);
3909 mips_relax.sequence = 1;
3910 mips_relax.symbol = symbol;
3913 /* Start generating the second version of a relaxable sequence.
3914 See the comment above RELAX_ENCODE for more details. */
3919 gas_assert (mips_relax.sequence == 1);
3920 mips_relax.sequence = 2;
3923 /* End the current relaxable sequence. */
3928 gas_assert (mips_relax.sequence == 2);
3929 relax_close_frag ();
3930 mips_relax.sequence = 0;
3933 /* Return true if IP is a delayed branch or jump. */
3935 static inline bfd_boolean
3936 delayed_branch_p (const struct mips_cl_insn *ip)
3938 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3939 | INSN_COND_BRANCH_DELAY
3940 | INSN_COND_BRANCH_LIKELY)) != 0;
3943 /* Return true if IP is a compact branch or jump. */
3945 static inline bfd_boolean
3946 compact_branch_p (const struct mips_cl_insn *ip)
3948 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3949 | INSN2_COND_BRANCH)) != 0;
3952 /* Return true if IP is an unconditional branch or jump. */
3954 static inline bfd_boolean
3955 uncond_branch_p (const struct mips_cl_insn *ip)
3957 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3958 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
3961 /* Return true if IP is a branch-likely instruction. */
3963 static inline bfd_boolean
3964 branch_likely_p (const struct mips_cl_insn *ip)
3966 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3969 /* Return the type of nop that should be used to fill the delay slot
3970 of delayed branch IP. */
3972 static struct mips_cl_insn *
3973 get_delay_slot_nop (const struct mips_cl_insn *ip)
3975 if (mips_opts.micromips
3976 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3977 return µmips_nop32_insn;
3981 /* Return a mask that has bit N set if OPCODE reads the register(s)
3985 insn_read_mask (const struct mips_opcode *opcode)
3987 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
3990 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3994 insn_write_mask (const struct mips_opcode *opcode)
3996 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
3999 /* Return a mask of the registers specified by operand OPERAND of INSN.
4000 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4004 operand_reg_mask (const struct mips_cl_insn *insn,
4005 const struct mips_operand *operand,
4006 unsigned int type_mask)
4008 unsigned int uval, vsel;
4010 switch (operand->type)
4017 case OP_ADDIUSP_INT:
4018 case OP_ENTRY_EXIT_LIST:
4019 case OP_REPEAT_DEST_REG:
4020 case OP_REPEAT_PREV_REG:
4023 case OP_VU0_MATCH_SUFFIX:
4028 case OP_OPTIONAL_REG:
4030 const struct mips_reg_operand *reg_op;
4032 reg_op = (const struct mips_reg_operand *) operand;
4033 if (!(type_mask & (1 << reg_op->reg_type)))
4035 uval = insn_extract_operand (insn, operand);
4036 return 1 << mips_decode_reg_operand (reg_op, uval);
4041 const struct mips_reg_pair_operand *pair_op;
4043 pair_op = (const struct mips_reg_pair_operand *) operand;
4044 if (!(type_mask & (1 << pair_op->reg_type)))
4046 uval = insn_extract_operand (insn, operand);
4047 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4050 case OP_CLO_CLZ_DEST:
4051 if (!(type_mask & (1 << OP_REG_GP)))
4053 uval = insn_extract_operand (insn, operand);
4054 return (1 << (uval & 31)) | (1 << (uval >> 5));
4056 case OP_LWM_SWM_LIST:
4059 case OP_SAVE_RESTORE_LIST:
4062 case OP_MDMX_IMM_REG:
4063 if (!(type_mask & (1 << OP_REG_VEC)))
4065 uval = insn_extract_operand (insn, operand);
4067 if ((vsel & 0x18) == 0x18)
4069 return 1 << (uval & 31);
4072 if (!(type_mask & (1 << OP_REG_GP)))
4074 return 1 << insn_extract_operand (insn, operand);
4079 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4080 where bit N of OPNO_MASK is set if operand N should be included.
4081 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4085 insn_reg_mask (const struct mips_cl_insn *insn,
4086 unsigned int type_mask, unsigned int opno_mask)
4088 unsigned int opno, reg_mask;
4092 while (opno_mask != 0)
4095 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4102 /* Return the mask of core registers that IP reads. */
4105 gpr_read_mask (const struct mips_cl_insn *ip)
4107 unsigned long pinfo, pinfo2;
4110 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4111 pinfo = ip->insn_mo->pinfo;
4112 pinfo2 = ip->insn_mo->pinfo2;
4113 if (pinfo & INSN_UDI)
4115 /* UDI instructions have traditionally been assumed to read RS
4117 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4118 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4120 if (pinfo & INSN_READ_GPR_24)
4122 if (pinfo2 & INSN2_READ_GPR_16)
4124 if (pinfo2 & INSN2_READ_SP)
4126 if (pinfo2 & INSN2_READ_GPR_31)
4128 /* Don't include register 0. */
4132 /* Return the mask of core registers that IP writes. */
4135 gpr_write_mask (const struct mips_cl_insn *ip)
4137 unsigned long pinfo, pinfo2;
4140 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4141 pinfo = ip->insn_mo->pinfo;
4142 pinfo2 = ip->insn_mo->pinfo2;
4143 if (pinfo & INSN_WRITE_GPR_24)
4145 if (pinfo & INSN_WRITE_GPR_31)
4147 if (pinfo & INSN_UDI)
4148 /* UDI instructions have traditionally been assumed to write to RD. */
4149 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4150 if (pinfo2 & INSN2_WRITE_SP)
4152 /* Don't include register 0. */
4156 /* Return the mask of floating-point registers that IP reads. */
4159 fpr_read_mask (const struct mips_cl_insn *ip)
4161 unsigned long pinfo;
4164 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4165 insn_read_mask (ip->insn_mo));
4166 pinfo = ip->insn_mo->pinfo;
4167 /* Conservatively treat all operands to an FP_D instruction are doubles.
4168 (This is overly pessimistic for things like cvt.d.s.) */
4169 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4174 /* Return the mask of floating-point registers that IP writes. */
4177 fpr_write_mask (const struct mips_cl_insn *ip)
4179 unsigned long pinfo;
4182 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4183 insn_write_mask (ip->insn_mo));
4184 pinfo = ip->insn_mo->pinfo;
4185 /* Conservatively treat all operands to an FP_D instruction are doubles.
4186 (This is overly pessimistic for things like cvt.s.d.) */
4187 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4192 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4193 Check whether that is allowed. */
4196 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4198 const char *s = insn->name;
4200 if (insn->pinfo == INSN_MACRO)
4201 /* Let a macro pass, we'll catch it later when it is expanded. */
4204 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
4206 /* Allow odd registers for single-precision ops. */
4207 switch (insn->pinfo & (FP_S | FP_D))
4218 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4219 s = strchr (insn->name, '.');
4220 if (s != NULL && opnum == 2)
4221 s = strchr (s + 1, '.');
4222 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
4225 /* Single-precision coprocessor loads and moves are OK too. */
4226 if ((insn->pinfo & FP_S)
4227 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
4228 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
4234 /* Information about an instruction argument that we're trying to match. */
4235 struct mips_arg_info
4237 /* The instruction so far. */
4238 struct mips_cl_insn *insn;
4240 /* The first unconsumed operand token. */
4241 struct mips_operand_token *token;
4243 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4246 /* The 1-based argument number, for error reporting. This does not
4247 count elided optional registers, etc.. */
4250 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4251 unsigned int last_regno;
4253 /* If the first operand was an OP_REG, this is the register that it
4254 specified, otherwise it is ILLEGAL_REG. */
4255 unsigned int dest_regno;
4257 /* The value of the last OP_INT operand. Only used for OP_MSB,
4258 where it gives the lsb position. */
4259 unsigned int last_op_int;
4261 /* If true, match routines should assume that no later instruction
4262 alternative matches and should therefore be as accomodating as
4263 possible. Match routines should not report errors if something
4264 is only invalid for !LAX_MATCH. */
4265 bfd_boolean lax_match;
4267 /* True if a reference to the current AT register was seen. */
4268 bfd_boolean seen_at;
4271 /* Record that the argument is out of range. */
4274 match_out_of_range (struct mips_arg_info *arg)
4276 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4279 /* Record that the argument isn't constant but needs to be. */
4282 match_not_constant (struct mips_arg_info *arg)
4284 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4288 /* Try to match an OT_CHAR token for character CH. Consume the token
4289 and return true on success, otherwise return false. */
4292 match_char (struct mips_arg_info *arg, char ch)
4294 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4304 /* Try to get an expression from the next tokens in ARG. Consume the
4305 tokens and return true on success, storing the expression value in
4306 VALUE and relocation types in R. */
4309 match_expression (struct mips_arg_info *arg, expressionS *value,
4310 bfd_reloc_code_real_type *r)
4312 /* If the next token is a '(' that was parsed as being part of a base
4313 expression, assume we have an elided offset. The later match will fail
4314 if this turns out to be wrong. */
4315 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4317 value->X_op = O_constant;
4318 value->X_add_number = 0;
4319 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4323 /* Reject register-based expressions such as "0+$2" and "(($2))".
4324 For plain registers the default error seems more appropriate. */
4325 if (arg->token->type == OT_INTEGER
4326 && arg->token->u.integer.value.X_op == O_register)
4328 set_insn_error (arg->argnum, _("register value used as expression"));
4332 if (arg->token->type == OT_INTEGER)
4334 *value = arg->token->u.integer.value;
4335 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4341 (arg->argnum, _("operand %d must be an immediate expression"),
4346 /* Try to get a constant expression from the next tokens in ARG. Consume
4347 the tokens and return return true on success, storing the constant value
4348 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4352 match_const_int (struct mips_arg_info *arg, offsetT *value)
4355 bfd_reloc_code_real_type r[3];
4357 if (!match_expression (arg, &ex, r))
4360 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4361 *value = ex.X_add_number;
4364 match_not_constant (arg);
4370 /* Return the RTYPE_* flags for a register operand of type TYPE that
4371 appears in instruction OPCODE. */
4374 convert_reg_type (const struct mips_opcode *opcode,
4375 enum mips_reg_operand_type type)
4380 return RTYPE_NUM | RTYPE_GP;
4383 /* Allow vector register names for MDMX if the instruction is a 64-bit
4384 FPR load, store or move (including moves to and from GPRs). */
4385 if ((mips_opts.ase & ASE_MDMX)
4386 && (opcode->pinfo & FP_D)
4387 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4388 | INSN_COPROC_MEMORY_DELAY
4389 | INSN_LOAD_COPROC_DELAY
4390 | INSN_LOAD_MEMORY_DELAY
4391 | INSN_STORE_MEMORY)))
4392 return RTYPE_FPU | RTYPE_VEC;
4396 if (opcode->pinfo & (FP_D | FP_S))
4397 return RTYPE_CCC | RTYPE_FCC;
4401 if (opcode->membership & INSN_5400)
4403 return RTYPE_FPU | RTYPE_VEC;
4409 if (opcode->name[strlen (opcode->name) - 1] == '0')
4410 return RTYPE_NUM | RTYPE_CP0;
4417 return RTYPE_NUM | RTYPE_VI;
4420 return RTYPE_NUM | RTYPE_VF;
4422 case OP_REG_R5900_I:
4423 return RTYPE_R5900_I;
4425 case OP_REG_R5900_Q:
4426 return RTYPE_R5900_Q;
4428 case OP_REG_R5900_R:
4429 return RTYPE_R5900_R;
4431 case OP_REG_R5900_ACC:
4432 return RTYPE_R5900_ACC;
4437 case OP_REG_MSA_CTRL:
4443 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4446 check_regno (struct mips_arg_info *arg,
4447 enum mips_reg_operand_type type, unsigned int regno)
4449 if (AT && type == OP_REG_GP && regno == AT)
4450 arg->seen_at = TRUE;
4452 if (type == OP_REG_FP
4455 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4456 as_warn (_("float register should be even, was %d"), regno);
4458 if (type == OP_REG_CCC)
4463 name = arg->insn->insn_mo->name;
4464 length = strlen (name);
4465 if ((regno & 1) != 0
4466 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4467 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4468 as_warn (_("condition code register should be even for %s, was %d"),
4471 if ((regno & 3) != 0
4472 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4473 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4478 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4479 a register of type TYPE. Return true on success, storing the register
4480 number in *REGNO and warning about any dubious uses. */
4483 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4484 unsigned int symval, unsigned int *regno)
4486 if (type == OP_REG_VEC)
4487 symval = mips_prefer_vec_regno (symval);
4488 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4491 *regno = symval & RNUM_MASK;
4492 check_regno (arg, type, *regno);
4496 /* Try to interpret the next token in ARG as a register of type TYPE.
4497 Consume the token and return true on success, storing the register
4498 number in *REGNO. Return false on failure. */
4501 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4502 unsigned int *regno)
4504 if (arg->token->type == OT_REG
4505 && match_regno (arg, type, arg->token->u.regno, regno))
4513 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4514 Consume the token and return true on success, storing the register numbers
4515 in *REGNO1 and *REGNO2. Return false on failure. */
4518 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4519 unsigned int *regno1, unsigned int *regno2)
4521 if (match_reg (arg, type, regno1))
4526 if (arg->token->type == OT_REG_RANGE
4527 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4528 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4529 && *regno1 <= *regno2)
4537 /* OP_INT matcher. */
4540 match_int_operand (struct mips_arg_info *arg,
4541 const struct mips_operand *operand_base)
4543 const struct mips_int_operand *operand;
4545 int min_val, max_val, factor;
4548 operand = (const struct mips_int_operand *) operand_base;
4549 factor = 1 << operand->shift;
4550 min_val = mips_int_operand_min (operand);
4551 max_val = mips_int_operand_max (operand);
4553 if (operand_base->lsb == 0
4554 && operand_base->size == 16
4555 && operand->shift == 0
4556 && operand->bias == 0
4557 && (operand->max_val == 32767 || operand->max_val == 65535))
4559 /* The operand can be relocated. */
4560 if (!match_expression (arg, &offset_expr, offset_reloc))
4563 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4564 /* Relocation operators were used. Accept the arguent and
4565 leave the relocation value in offset_expr and offset_relocs
4566 for the caller to process. */
4569 if (offset_expr.X_op != O_constant)
4571 /* Accept non-constant operands if no later alternative matches,
4572 leaving it for the caller to process. */
4573 if (!arg->lax_match)
4575 offset_reloc[0] = BFD_RELOC_LO16;
4579 /* Clear the global state; we're going to install the operand
4581 sval = offset_expr.X_add_number;
4582 offset_expr.X_op = O_absent;
4584 /* For compatibility with older assemblers, we accept
4585 0x8000-0xffff as signed 16-bit numbers when only
4586 signed numbers are allowed. */
4589 max_val = ((1 << operand_base->size) - 1) << operand->shift;
4590 if (!arg->lax_match && sval <= max_val)
4596 if (!match_const_int (arg, &sval))
4600 arg->last_op_int = sval;
4602 if (sval < min_val || sval > max_val || sval % factor)
4604 match_out_of_range (arg);
4608 uval = (unsigned int) sval >> operand->shift;
4609 uval -= operand->bias;
4611 /* Handle -mfix-cn63xxp1. */
4613 && mips_fix_cn63xxp1
4614 && !mips_opts.micromips
4615 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4630 /* The rest must be changed to 28. */
4635 insn_insert_operand (arg->insn, operand_base, uval);
4639 /* OP_MAPPED_INT matcher. */
4642 match_mapped_int_operand (struct mips_arg_info *arg,
4643 const struct mips_operand *operand_base)
4645 const struct mips_mapped_int_operand *operand;
4646 unsigned int uval, num_vals;
4649 operand = (const struct mips_mapped_int_operand *) operand_base;
4650 if (!match_const_int (arg, &sval))
4653 num_vals = 1 << operand_base->size;
4654 for (uval = 0; uval < num_vals; uval++)
4655 if (operand->int_map[uval] == sval)
4657 if (uval == num_vals)
4659 match_out_of_range (arg);
4663 insn_insert_operand (arg->insn, operand_base, uval);
4667 /* OP_MSB matcher. */
4670 match_msb_operand (struct mips_arg_info *arg,
4671 const struct mips_operand *operand_base)
4673 const struct mips_msb_operand *operand;
4674 int min_val, max_val, max_high;
4675 offsetT size, sval, high;
4677 operand = (const struct mips_msb_operand *) operand_base;
4678 min_val = operand->bias;
4679 max_val = min_val + (1 << operand_base->size) - 1;
4680 max_high = operand->opsize;
4682 if (!match_const_int (arg, &size))
4685 high = size + arg->last_op_int;
4686 sval = operand->add_lsb ? high : size;
4688 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4690 match_out_of_range (arg);
4693 insn_insert_operand (arg->insn, operand_base, sval - min_val);
4697 /* OP_REG matcher. */
4700 match_reg_operand (struct mips_arg_info *arg,
4701 const struct mips_operand *operand_base)
4703 const struct mips_reg_operand *operand;
4704 unsigned int regno, uval, num_vals;
4706 operand = (const struct mips_reg_operand *) operand_base;
4707 if (!match_reg (arg, operand->reg_type, ®no))
4710 if (operand->reg_map)
4712 num_vals = 1 << operand->root.size;
4713 for (uval = 0; uval < num_vals; uval++)
4714 if (operand->reg_map[uval] == regno)
4716 if (num_vals == uval)
4722 arg->last_regno = regno;
4723 if (arg->opnum == 1)
4724 arg->dest_regno = regno;
4725 insn_insert_operand (arg->insn, operand_base, uval);
4729 /* OP_REG_PAIR matcher. */
4732 match_reg_pair_operand (struct mips_arg_info *arg,
4733 const struct mips_operand *operand_base)
4735 const struct mips_reg_pair_operand *operand;
4736 unsigned int regno1, regno2, uval, num_vals;
4738 operand = (const struct mips_reg_pair_operand *) operand_base;
4739 if (!match_reg (arg, operand->reg_type, ®no1)
4740 || !match_char (arg, ',')
4741 || !match_reg (arg, operand->reg_type, ®no2))
4744 num_vals = 1 << operand_base->size;
4745 for (uval = 0; uval < num_vals; uval++)
4746 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4748 if (uval == num_vals)
4751 insn_insert_operand (arg->insn, operand_base, uval);
4755 /* OP_PCREL matcher. The caller chooses the relocation type. */
4758 match_pcrel_operand (struct mips_arg_info *arg)
4760 bfd_reloc_code_real_type r[3];
4762 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
4765 /* OP_PERF_REG matcher. */
4768 match_perf_reg_operand (struct mips_arg_info *arg,
4769 const struct mips_operand *operand)
4773 if (!match_const_int (arg, &sval))
4778 || (mips_opts.arch == CPU_R5900
4779 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4780 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4782 set_insn_error (arg->argnum, _("invalid performance register"));
4786 insn_insert_operand (arg->insn, operand, sval);
4790 /* OP_ADDIUSP matcher. */
4793 match_addiusp_operand (struct mips_arg_info *arg,
4794 const struct mips_operand *operand)
4799 if (!match_const_int (arg, &sval))
4804 match_out_of_range (arg);
4809 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
4811 match_out_of_range (arg);
4815 uval = (unsigned int) sval;
4816 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4817 insn_insert_operand (arg->insn, operand, uval);
4821 /* OP_CLO_CLZ_DEST matcher. */
4824 match_clo_clz_dest_operand (struct mips_arg_info *arg,
4825 const struct mips_operand *operand)
4829 if (!match_reg (arg, OP_REG_GP, ®no))
4832 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
4836 /* OP_LWM_SWM_LIST matcher. */
4839 match_lwm_swm_list_operand (struct mips_arg_info *arg,
4840 const struct mips_operand *operand)
4842 unsigned int reglist, sregs, ra, regno1, regno2;
4843 struct mips_arg_info reset;
4846 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4850 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4855 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4858 while (match_char (arg, ',')
4859 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
4862 if (operand->size == 2)
4864 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4870 and any permutations of these. */
4871 if ((reglist & 0xfff1ffff) != 0x80010000)
4874 sregs = (reglist >> 17) & 7;
4879 /* The list must include at least one of ra and s0-sN,
4880 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4881 which are $23 and $30 respectively.) E.g.:
4889 and any permutations of these. */
4890 if ((reglist & 0x3f00ffff) != 0)
4893 ra = (reglist >> 27) & 0x10;
4894 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4897 if ((sregs & -sregs) != sregs)
4900 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
4904 /* OP_ENTRY_EXIT_LIST matcher. */
4907 match_entry_exit_operand (struct mips_arg_info *arg,
4908 const struct mips_operand *operand)
4911 bfd_boolean is_exit;
4913 /* The format is the same for both ENTRY and EXIT, but the constraints
4915 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4916 mask = (is_exit ? 7 << 3 : 0);
4919 unsigned int regno1, regno2;
4920 bfd_boolean is_freg;
4922 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4924 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
4929 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4932 mask |= (5 + regno2) << 3;
4934 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4935 mask |= (regno2 - 3) << 3;
4936 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4937 mask |= (regno2 - 15) << 1;
4938 else if (regno1 == RA && regno2 == RA)
4943 while (match_char (arg, ','));
4945 insn_insert_operand (arg->insn, operand, mask);
4949 /* OP_SAVE_RESTORE_LIST matcher. */
4952 match_save_restore_list_operand (struct mips_arg_info *arg)
4954 unsigned int opcode, args, statics, sregs;
4955 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
4958 opcode = arg->insn->insn_opcode;
4960 num_frame_sizes = 0;
4966 unsigned int regno1, regno2;
4968 if (arg->token->type == OT_INTEGER)
4970 /* Handle the frame size. */
4971 if (!match_const_int (arg, &frame_size))
4973 num_frame_sizes += 1;
4977 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4980 while (regno1 <= regno2)
4982 if (regno1 >= 4 && regno1 <= 7)
4984 if (num_frame_sizes == 0)
4986 args |= 1 << (regno1 - 4);
4988 /* statics $a0-$a3 */
4989 statics |= 1 << (regno1 - 4);
4991 else if (regno1 >= 16 && regno1 <= 23)
4993 sregs |= 1 << (regno1 - 16);
4994 else if (regno1 == 30)
4997 else if (regno1 == 31)
4998 /* Add $ra to insn. */
5008 while (match_char (arg, ','));
5010 /* Encode args/statics combination. */
5013 else if (args == 0xf)
5014 /* All $a0-$a3 are args. */
5015 opcode |= MIPS16_ALL_ARGS << 16;
5016 else if (statics == 0xf)
5017 /* All $a0-$a3 are statics. */
5018 opcode |= MIPS16_ALL_STATICS << 16;
5021 /* Count arg registers. */
5031 /* Count static registers. */
5033 while (statics & 0x8)
5035 statics = (statics << 1) & 0xf;
5041 /* Encode args/statics. */
5042 opcode |= ((num_args << 2) | num_statics) << 16;
5045 /* Encode $s0/$s1. */
5046 if (sregs & (1 << 0)) /* $s0 */
5048 if (sregs & (1 << 1)) /* $s1 */
5052 /* Encode $s2-$s8. */
5061 opcode |= num_sregs << 24;
5063 /* Encode frame size. */
5064 if (num_frame_sizes == 0)
5066 set_insn_error (arg->argnum, _("missing frame size"));
5069 if (num_frame_sizes > 1)
5071 set_insn_error (arg->argnum, _("frame size specified twice"));
5074 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5076 set_insn_error (arg->argnum, _("invalid frame size"));
5079 if (frame_size != 128 || (opcode >> 16) != 0)
5082 opcode |= (((frame_size & 0xf0) << 16)
5083 | (frame_size & 0x0f));
5086 /* Finally build the instruction. */
5087 if ((opcode >> 16) != 0 || frame_size == 0)
5088 opcode |= MIPS16_EXTEND;
5089 arg->insn->insn_opcode = opcode;
5093 /* OP_MDMX_IMM_REG matcher. */
5096 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5097 const struct mips_operand *operand)
5099 unsigned int regno, uval;
5101 const struct mips_opcode *opcode;
5103 /* The mips_opcode records whether this is an octobyte or quadhalf
5104 instruction. Start out with that bit in place. */
5105 opcode = arg->insn->insn_mo;
5106 uval = mips_extract_operand (operand, opcode->match);
5107 is_qh = (uval != 0);
5109 if (arg->token->type == OT_REG)
5111 if ((opcode->membership & INSN_5400)
5112 && strcmp (opcode->name, "rzu.ob") == 0)
5114 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5119 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5123 /* Check whether this is a vector register or a broadcast of
5124 a single element. */
5125 if (arg->token->type == OT_INTEGER_INDEX)
5127 if (arg->token->u.index > (is_qh ? 3 : 7))
5129 set_insn_error (arg->argnum, _("invalid element selector"));
5132 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5137 /* A full vector. */
5138 if ((opcode->membership & INSN_5400)
5139 && (strcmp (opcode->name, "sll.ob") == 0
5140 || strcmp (opcode->name, "srl.ob") == 0))
5142 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5148 uval |= MDMX_FMTSEL_VEC_QH << 5;
5150 uval |= MDMX_FMTSEL_VEC_OB << 5;
5158 if (!match_const_int (arg, &sval))
5160 if (sval < 0 || sval > 31)
5162 match_out_of_range (arg);
5165 uval |= (sval & 31);
5167 uval |= MDMX_FMTSEL_IMM_QH << 5;
5169 uval |= MDMX_FMTSEL_IMM_OB << 5;
5171 insn_insert_operand (arg->insn, operand, uval);
5175 /* OP_IMM_INDEX matcher. */
5178 match_imm_index_operand (struct mips_arg_info *arg,
5179 const struct mips_operand *operand)
5181 unsigned int max_val;
5183 if (arg->token->type != OT_INTEGER_INDEX)
5186 max_val = (1 << operand->size) - 1;
5187 if (arg->token->u.index > max_val)
5189 match_out_of_range (arg);
5192 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5197 /* OP_REG_INDEX matcher. */
5200 match_reg_index_operand (struct mips_arg_info *arg,
5201 const struct mips_operand *operand)
5205 if (arg->token->type != OT_REG_INDEX)
5208 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5211 insn_insert_operand (arg->insn, operand, regno);
5216 /* OP_PC matcher. */
5219 match_pc_operand (struct mips_arg_info *arg)
5221 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5229 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5230 register that we need to match. */
5233 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5237 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5240 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5241 the length of the value in bytes (4 for float, 8 for double) and
5242 USING_GPRS says whether the destination is a GPR rather than an FPR.
5244 Return the constant in IMM and OFFSET as follows:
5246 - If the constant should be loaded via memory, set IMM to O_absent and
5247 OFFSET to the memory address.
5249 - Otherwise, if the constant should be loaded into two 32-bit registers,
5250 set IMM to the O_constant to load into the high register and OFFSET
5251 to the corresponding value for the low register.
5253 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5255 These constants only appear as the last operand in an instruction,
5256 and every instruction that accepts them in any variant accepts them
5257 in all variants. This means we don't have to worry about backing out
5258 any changes if the instruction does not match. We just match
5259 unconditionally and report an error if the constant is invalid. */
5262 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5263 expressionS *offset, int length, bfd_boolean using_gprs)
5268 const char *newname;
5269 unsigned char *data;
5271 /* Where the constant is placed is based on how the MIPS assembler
5274 length == 4 && using_gprs -- immediate value only
5275 length == 8 && using_gprs -- .rdata or immediate value
5276 length == 4 && !using_gprs -- .lit4 or immediate value
5277 length == 8 && !using_gprs -- .lit8 or immediate value
5279 The .lit4 and .lit8 sections are only used if permitted by the
5281 if (arg->token->type != OT_FLOAT)
5283 set_insn_error (arg->argnum, _("floating-point expression required"));
5287 gas_assert (arg->token->u.flt.length == length);
5288 data = arg->token->u.flt.data;
5291 /* Handle 32-bit constants for which an immediate value is best. */
5294 || g_switch_value < 4
5295 || (data[0] == 0 && data[1] == 0)
5296 || (data[2] == 0 && data[3] == 0)))
5298 imm->X_op = O_constant;
5299 if (!target_big_endian)
5300 imm->X_add_number = bfd_getl32 (data);
5302 imm->X_add_number = bfd_getb32 (data);
5303 offset->X_op = O_absent;
5307 /* Handle 64-bit constants for which an immediate value is best. */
5309 && !mips_disable_float_construction
5310 /* Constants can only be constructed in GPRs and copied
5311 to FPRs if the GPRs are at least as wide as the FPRs.
5312 Force the constant into memory if we are using 64-bit FPRs
5313 but the GPRs are only 32 bits wide. */
5314 /* ??? No longer true with the addition of MTHC1, but this
5315 is legacy code... */
5316 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
5317 && ((data[0] == 0 && data[1] == 0)
5318 || (data[2] == 0 && data[3] == 0))
5319 && ((data[4] == 0 && data[5] == 0)
5320 || (data[6] == 0 && data[7] == 0)))
5322 /* The value is simple enough to load with a couple of instructions.
5323 If using 32-bit registers, set IMM to the high order 32 bits and
5324 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5326 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
5328 imm->X_op = O_constant;
5329 offset->X_op = O_constant;
5330 if (!target_big_endian)
5332 imm->X_add_number = bfd_getl32 (data + 4);
5333 offset->X_add_number = bfd_getl32 (data);
5337 imm->X_add_number = bfd_getb32 (data);
5338 offset->X_add_number = bfd_getb32 (data + 4);
5340 if (offset->X_add_number == 0)
5341 offset->X_op = O_absent;
5345 imm->X_op = O_constant;
5346 if (!target_big_endian)
5347 imm->X_add_number = bfd_getl64 (data);
5349 imm->X_add_number = bfd_getb64 (data);
5350 offset->X_op = O_absent;
5355 /* Switch to the right section. */
5357 subseg = now_subseg;
5360 gas_assert (!using_gprs && g_switch_value >= 4);
5365 if (using_gprs || g_switch_value < 8)
5366 newname = RDATA_SECTION_NAME;
5371 new_seg = subseg_new (newname, (subsegT) 0);
5372 bfd_set_section_flags (stdoutput, new_seg,
5373 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5374 frag_align (length == 4 ? 2 : 3, 0, 0);
5375 if (strncmp (TARGET_OS, "elf", 3) != 0)
5376 record_alignment (new_seg, 4);
5378 record_alignment (new_seg, length == 4 ? 2 : 3);
5380 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
5382 /* Set the argument to the current address in the section. */
5383 imm->X_op = O_absent;
5384 offset->X_op = O_symbol;
5385 offset->X_add_symbol = symbol_temp_new_now ();
5386 offset->X_add_number = 0;
5388 /* Put the floating point number into the section. */
5389 p = frag_more (length);
5390 memcpy (p, data, length);
5392 /* Switch back to the original section. */
5393 subseg_set (seg, subseg);
5397 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5401 match_vu0_suffix_operand (struct mips_arg_info *arg,
5402 const struct mips_operand *operand,
5403 bfd_boolean match_p)
5407 /* The operand can be an XYZW mask or a single 2-bit channel index
5408 (with X being 0). */
5409 gas_assert (operand->size == 2 || operand->size == 4);
5411 /* The suffix can be omitted when it is already part of the opcode. */
5412 if (arg->token->type != OT_CHANNELS)
5415 uval = arg->token->u.channels;
5416 if (operand->size == 2)
5418 /* Check that a single bit is set and convert it into a 2-bit index. */
5419 if ((uval & -uval) != uval)
5421 uval = 4 - ffs (uval);
5424 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5429 insn_insert_operand (arg->insn, operand, uval);
5433 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5434 of the argument text if the match is successful, otherwise return null. */
5437 match_operand (struct mips_arg_info *arg,
5438 const struct mips_operand *operand)
5440 switch (operand->type)
5443 return match_int_operand (arg, operand);
5446 return match_mapped_int_operand (arg, operand);
5449 return match_msb_operand (arg, operand);
5452 case OP_OPTIONAL_REG:
5453 return match_reg_operand (arg, operand);
5456 return match_reg_pair_operand (arg, operand);
5459 return match_pcrel_operand (arg);
5462 return match_perf_reg_operand (arg, operand);
5464 case OP_ADDIUSP_INT:
5465 return match_addiusp_operand (arg, operand);
5467 case OP_CLO_CLZ_DEST:
5468 return match_clo_clz_dest_operand (arg, operand);
5470 case OP_LWM_SWM_LIST:
5471 return match_lwm_swm_list_operand (arg, operand);
5473 case OP_ENTRY_EXIT_LIST:
5474 return match_entry_exit_operand (arg, operand);
5476 case OP_SAVE_RESTORE_LIST:
5477 return match_save_restore_list_operand (arg);
5479 case OP_MDMX_IMM_REG:
5480 return match_mdmx_imm_reg_operand (arg, operand);
5482 case OP_REPEAT_DEST_REG:
5483 return match_tied_reg_operand (arg, arg->dest_regno);
5485 case OP_REPEAT_PREV_REG:
5486 return match_tied_reg_operand (arg, arg->last_regno);
5489 return match_pc_operand (arg);
5492 return match_vu0_suffix_operand (arg, operand, FALSE);
5494 case OP_VU0_MATCH_SUFFIX:
5495 return match_vu0_suffix_operand (arg, operand, TRUE);
5498 return match_imm_index_operand (arg, operand);
5501 return match_reg_index_operand (arg, operand);
5506 /* ARG is the state after successfully matching an instruction.
5507 Issue any queued-up warnings. */
5510 check_completed_insn (struct mips_arg_info *arg)
5515 as_warn (_("used $at without \".set noat\""));
5517 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
5521 /* Return true if modifying general-purpose register REG needs a delay. */
5524 reg_needs_delay (unsigned int reg)
5526 unsigned long prev_pinfo;
5528 prev_pinfo = history[0].insn_mo->pinfo;
5529 if (!mips_opts.noreorder
5530 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5531 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5532 && (gpr_write_mask (&history[0]) & (1 << reg)))
5538 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5539 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5540 by VR4120 errata. */
5543 classify_vr4120_insn (const char *name)
5545 if (strncmp (name, "macc", 4) == 0)
5546 return FIX_VR4120_MACC;
5547 if (strncmp (name, "dmacc", 5) == 0)
5548 return FIX_VR4120_DMACC;
5549 if (strncmp (name, "mult", 4) == 0)
5550 return FIX_VR4120_MULT;
5551 if (strncmp (name, "dmult", 5) == 0)
5552 return FIX_VR4120_DMULT;
5553 if (strstr (name, "div"))
5554 return FIX_VR4120_DIV;
5555 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5556 return FIX_VR4120_MTHILO;
5557 return NUM_FIX_VR4120_CLASSES;
5560 #define INSN_ERET 0x42000018
5561 #define INSN_DERET 0x4200001f
5563 /* Return the number of instructions that must separate INSN1 and INSN2,
5564 where INSN1 is the earlier instruction. Return the worst-case value
5565 for any INSN2 if INSN2 is null. */
5568 insns_between (const struct mips_cl_insn *insn1,
5569 const struct mips_cl_insn *insn2)
5571 unsigned long pinfo1, pinfo2;
5574 /* If INFO2 is null, pessimistically assume that all flags are set for
5575 the second instruction. */
5576 pinfo1 = insn1->insn_mo->pinfo;
5577 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
5579 /* For most targets, write-after-read dependencies on the HI and LO
5580 registers must be separated by at least two instructions. */
5581 if (!hilo_interlocks)
5583 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5585 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5589 /* If we're working around r7000 errata, there must be two instructions
5590 between an mfhi or mflo and any instruction that uses the result. */
5591 if (mips_7000_hilo_fix
5592 && !mips_opts.micromips
5593 && MF_HILO_INSN (pinfo1)
5594 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
5597 /* If we're working around 24K errata, one instruction is required
5598 if an ERET or DERET is followed by a branch instruction. */
5599 if (mips_fix_24k && !mips_opts.micromips)
5601 if (insn1->insn_opcode == INSN_ERET
5602 || insn1->insn_opcode == INSN_DERET)
5605 || insn2->insn_opcode == INSN_ERET
5606 || insn2->insn_opcode == INSN_DERET
5607 || delayed_branch_p (insn2))
5612 /* If working around VR4120 errata, check for combinations that need
5613 a single intervening instruction. */
5614 if (mips_fix_vr4120 && !mips_opts.micromips)
5616 unsigned int class1, class2;
5618 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5619 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
5623 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5624 if (vr4120_conflicts[class1] & (1 << class2))
5629 if (!HAVE_CODE_COMPRESSION)
5631 /* Check for GPR or coprocessor load delays. All such delays
5632 are on the RT register. */
5633 /* Itbl support may require additional care here. */
5634 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5635 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
5637 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
5641 /* Check for generic coprocessor hazards.
5643 This case is not handled very well. There is no special
5644 knowledge of CP0 handling, and the coprocessors other than
5645 the floating point unit are not distinguished at all. */
5646 /* Itbl support may require additional care here. FIXME!
5647 Need to modify this to include knowledge about
5648 user specified delays! */
5649 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5650 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5652 /* Handle cases where INSN1 writes to a known general coprocessor
5653 register. There must be a one instruction delay before INSN2
5654 if INSN2 reads that register, otherwise no delay is needed. */
5655 mask = fpr_write_mask (insn1);
5658 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
5663 /* Read-after-write dependencies on the control registers
5664 require a two-instruction gap. */
5665 if ((pinfo1 & INSN_WRITE_COND_CODE)
5666 && (pinfo2 & INSN_READ_COND_CODE))
5669 /* We don't know exactly what INSN1 does. If INSN2 is
5670 also a coprocessor instruction, assume there must be
5671 a one instruction gap. */
5672 if (pinfo2 & INSN_COP)
5677 /* Check for read-after-write dependencies on the coprocessor
5678 control registers in cases where INSN1 does not need a general
5679 coprocessor delay. This means that INSN1 is a floating point
5680 comparison instruction. */
5681 /* Itbl support may require additional care here. */
5682 else if (!cop_interlocks
5683 && (pinfo1 & INSN_WRITE_COND_CODE)
5684 && (pinfo2 & INSN_READ_COND_CODE))
5691 /* Return the number of nops that would be needed to work around the
5692 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5693 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5694 that are contained within the first IGNORE instructions of HIST. */
5697 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
5698 const struct mips_cl_insn *insn)
5703 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5704 are not affected by the errata. */
5706 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5707 || strcmp (insn->insn_mo->name, "mtlo") == 0
5708 || strcmp (insn->insn_mo->name, "mthi") == 0))
5711 /* Search for the first MFLO or MFHI. */
5712 for (i = 0; i < MAX_VR4130_NOPS; i++)
5713 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
5715 /* Extract the destination register. */
5716 mask = gpr_write_mask (&hist[i]);
5718 /* No nops are needed if INSN reads that register. */
5719 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
5722 /* ...or if any of the intervening instructions do. */
5723 for (j = 0; j < i; j++)
5724 if (gpr_read_mask (&hist[j]) & mask)
5728 return MAX_VR4130_NOPS - i;
5733 #define BASE_REG_EQ(INSN1, INSN2) \
5734 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5735 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5737 /* Return the minimum alignment for this store instruction. */
5740 fix_24k_align_to (const struct mips_opcode *mo)
5742 if (strcmp (mo->name, "sh") == 0)
5745 if (strcmp (mo->name, "swc1") == 0
5746 || strcmp (mo->name, "swc2") == 0
5747 || strcmp (mo->name, "sw") == 0
5748 || strcmp (mo->name, "sc") == 0
5749 || strcmp (mo->name, "s.s") == 0)
5752 if (strcmp (mo->name, "sdc1") == 0
5753 || strcmp (mo->name, "sdc2") == 0
5754 || strcmp (mo->name, "s.d") == 0)
5761 struct fix_24k_store_info
5763 /* Immediate offset, if any, for this store instruction. */
5765 /* Alignment required by this store instruction. */
5767 /* True for register offsets. */
5768 int register_offset;
5771 /* Comparison function used by qsort. */
5774 fix_24k_sort (const void *a, const void *b)
5776 const struct fix_24k_store_info *pos1 = a;
5777 const struct fix_24k_store_info *pos2 = b;
5779 return (pos1->off - pos2->off);
5782 /* INSN is a store instruction. Try to record the store information
5783 in STINFO. Return false if the information isn't known. */
5786 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
5787 const struct mips_cl_insn *insn)
5789 /* The instruction must have a known offset. */
5790 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5793 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5794 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5798 /* Return the number of nops that would be needed to work around the 24k
5799 "lost data on stores during refill" errata if instruction INSN
5800 immediately followed the 2 instructions described by HIST.
5801 Ignore hazards that are contained within the first IGNORE
5802 instructions of HIST.
5804 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5805 for the data cache refills and store data. The following describes
5806 the scenario where the store data could be lost.
5808 * A data cache miss, due to either a load or a store, causing fill
5809 data to be supplied by the memory subsystem
5810 * The first three doublewords of fill data are returned and written
5812 * A sequence of four stores occurs in consecutive cycles around the
5813 final doubleword of the fill:
5817 * Zero, One or more instructions
5820 The four stores A-D must be to different doublewords of the line that
5821 is being filled. The fourth instruction in the sequence above permits
5822 the fill of the final doubleword to be transferred from the FSB into
5823 the cache. In the sequence above, the stores may be either integer
5824 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5825 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5826 different doublewords on the line. If the floating point unit is
5827 running in 1:2 mode, it is not possible to create the sequence above
5828 using only floating point store instructions.
5830 In this case, the cache line being filled is incorrectly marked
5831 invalid, thereby losing the data from any store to the line that
5832 occurs between the original miss and the completion of the five
5833 cycle sequence shown above.
5835 The workarounds are:
5837 * Run the data cache in write-through mode.
5838 * Insert a non-store instruction between
5839 Store A and Store B or Store B and Store C. */
5842 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
5843 const struct mips_cl_insn *insn)
5845 struct fix_24k_store_info pos[3];
5846 int align, i, base_offset;
5851 /* If the previous instruction wasn't a store, there's nothing to
5853 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5856 /* If the instructions after the previous one are unknown, we have
5857 to assume the worst. */
5861 /* Check whether we are dealing with three consecutive stores. */
5862 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5863 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5866 /* If we don't know the relationship between the store addresses,
5867 assume the worst. */
5868 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
5869 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5872 if (!fix_24k_record_store_info (&pos[0], insn)
5873 || !fix_24k_record_store_info (&pos[1], &hist[0])
5874 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5877 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5879 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5880 X bytes and such that the base register + X is known to be aligned
5883 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5887 align = pos[0].align_to;
5888 base_offset = pos[0].off;
5889 for (i = 1; i < 3; i++)
5890 if (align < pos[i].align_to)
5892 align = pos[i].align_to;
5893 base_offset = pos[i].off;
5895 for (i = 0; i < 3; i++)
5896 pos[i].off -= base_offset;
5899 pos[0].off &= ~align + 1;
5900 pos[1].off &= ~align + 1;
5901 pos[2].off &= ~align + 1;
5903 /* If any two stores write to the same chunk, they also write to the
5904 same doubleword. The offsets are still sorted at this point. */
5905 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5908 /* A range of at least 9 bytes is needed for the stores to be in
5909 non-overlapping doublewords. */
5910 if (pos[2].off - pos[0].off <= 8)
5913 if (pos[2].off - pos[1].off >= 24
5914 || pos[1].off - pos[0].off >= 24
5915 || pos[2].off - pos[0].off >= 32)
5921 /* Return the number of nops that would be needed if instruction INSN
5922 immediately followed the MAX_NOPS instructions given by HIST,
5923 where HIST[0] is the most recent instruction. Ignore hazards
5924 between INSN and the first IGNORE instructions in HIST.
5926 If INSN is null, return the worse-case number of nops for any
5930 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
5931 const struct mips_cl_insn *insn)
5933 int i, nops, tmp_nops;
5936 for (i = ignore; i < MAX_DELAY_NOPS; i++)
5938 tmp_nops = insns_between (hist + i, insn) - i;
5939 if (tmp_nops > nops)
5943 if (mips_fix_vr4130 && !mips_opts.micromips)
5945 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
5946 if (tmp_nops > nops)
5950 if (mips_fix_24k && !mips_opts.micromips)
5952 tmp_nops = nops_for_24k (ignore, hist, insn);
5953 if (tmp_nops > nops)
5960 /* The variable arguments provide NUM_INSNS extra instructions that
5961 might be added to HIST. Return the largest number of nops that
5962 would be needed after the extended sequence, ignoring hazards
5963 in the first IGNORE instructions. */
5966 nops_for_sequence (int num_insns, int ignore,
5967 const struct mips_cl_insn *hist, ...)
5970 struct mips_cl_insn buffer[MAX_NOPS];
5971 struct mips_cl_insn *cursor;
5974 va_start (args, hist);
5975 cursor = buffer + num_insns;
5976 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
5977 while (cursor > buffer)
5978 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5980 nops = nops_for_insn (ignore, buffer, NULL);
5985 /* Like nops_for_insn, but if INSN is a branch, take into account the
5986 worst-case delay for the branch target. */
5989 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
5990 const struct mips_cl_insn *insn)
5994 nops = nops_for_insn (ignore, hist, insn);
5995 if (delayed_branch_p (insn))
5997 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
5998 hist, insn, get_delay_slot_nop (insn));
5999 if (tmp_nops > nops)
6002 else if (compact_branch_p (insn))
6004 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6005 if (tmp_nops > nops)
6011 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6014 fix_loongson2f_nop (struct mips_cl_insn * ip)
6016 gas_assert (!HAVE_CODE_COMPRESSION);
6017 if (strcmp (ip->insn_mo->name, "nop") == 0)
6018 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6021 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6022 jr target pc &= 'hffff_ffff_cfff_ffff. */
6025 fix_loongson2f_jump (struct mips_cl_insn * ip)
6027 gas_assert (!HAVE_CODE_COMPRESSION);
6028 if (strcmp (ip->insn_mo->name, "j") == 0
6029 || strcmp (ip->insn_mo->name, "jr") == 0
6030 || strcmp (ip->insn_mo->name, "jalr") == 0)
6038 sreg = EXTRACT_OPERAND (0, RS, *ip);
6039 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6042 ep.X_op = O_constant;
6043 ep.X_add_number = 0xcfff0000;
6044 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6045 ep.X_add_number = 0xffff;
6046 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6047 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6052 fix_loongson2f (struct mips_cl_insn * ip)
6054 if (mips_fix_loongson2f_nop)
6055 fix_loongson2f_nop (ip);
6057 if (mips_fix_loongson2f_jump)
6058 fix_loongson2f_jump (ip);
6061 /* IP is a branch that has a delay slot, and we need to fill it
6062 automatically. Return true if we can do that by swapping IP
6063 with the previous instruction.
6064 ADDRESS_EXPR is an operand of the instruction to be used with
6068 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6069 bfd_reloc_code_real_type *reloc_type)
6071 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6072 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6074 /* -O2 and above is required for this optimization. */
6075 if (mips_optimize < 2)
6078 /* If we have seen .set volatile or .set nomove, don't optimize. */
6079 if (mips_opts.nomove)
6082 /* We can't swap if the previous instruction's position is fixed. */
6083 if (history[0].fixed_p)
6086 /* If the previous previous insn was in a .set noreorder, we can't
6087 swap. Actually, the MIPS assembler will swap in this situation.
6088 However, gcc configured -with-gnu-as will generate code like
6096 in which we can not swap the bne and INSN. If gcc is not configured
6097 -with-gnu-as, it does not output the .set pseudo-ops. */
6098 if (history[1].noreorder_p)
6101 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6102 This means that the previous instruction was a 4-byte one anyhow. */
6103 if (mips_opts.mips16 && history[0].fixp[0])
6106 /* If the branch is itself the target of a branch, we can not swap.
6107 We cheat on this; all we check for is whether there is a label on
6108 this instruction. If there are any branches to anything other than
6109 a label, users must use .set noreorder. */
6110 if (seg_info (now_seg)->label_list)
6113 /* If the previous instruction is in a variant frag other than this
6114 branch's one, we cannot do the swap. This does not apply to
6115 MIPS16 code, which uses variant frags for different purposes. */
6116 if (!mips_opts.mips16
6118 && history[0].frag->fr_type == rs_machine_dependent)
6121 /* We do not swap with instructions that cannot architecturally
6122 be placed in a branch delay slot, such as SYNC or ERET. We
6123 also refrain from swapping with a trap instruction, since it
6124 complicates trap handlers to have the trap instruction be in
6126 prev_pinfo = history[0].insn_mo->pinfo;
6127 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6130 /* Check for conflicts between the branch and the instructions
6131 before the candidate delay slot. */
6132 if (nops_for_insn (0, history + 1, ip) > 0)
6135 /* Check for conflicts between the swapped sequence and the
6136 target of the branch. */
6137 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6140 /* If the branch reads a register that the previous
6141 instruction sets, we can not swap. */
6142 gpr_read = gpr_read_mask (ip);
6143 prev_gpr_write = gpr_write_mask (&history[0]);
6144 if (gpr_read & prev_gpr_write)
6147 /* If the branch writes a register that the previous
6148 instruction sets, we can not swap. */
6149 gpr_write = gpr_write_mask (ip);
6150 if (gpr_write & prev_gpr_write)
6153 /* If the branch writes a register that the previous
6154 instruction reads, we can not swap. */
6155 prev_gpr_read = gpr_read_mask (&history[0]);
6156 if (gpr_write & prev_gpr_read)
6159 /* If one instruction sets a condition code and the
6160 other one uses a condition code, we can not swap. */
6161 pinfo = ip->insn_mo->pinfo;
6162 if ((pinfo & INSN_READ_COND_CODE)
6163 && (prev_pinfo & INSN_WRITE_COND_CODE))
6165 if ((pinfo & INSN_WRITE_COND_CODE)
6166 && (prev_pinfo & INSN_READ_COND_CODE))
6169 /* If the previous instruction uses the PC, we can not swap. */
6170 prev_pinfo2 = history[0].insn_mo->pinfo2;
6171 if (prev_pinfo2 & INSN2_READ_PC)
6174 /* If the previous instruction has an incorrect size for a fixed
6175 branch delay slot in microMIPS mode, we cannot swap. */
6176 pinfo2 = ip->insn_mo->pinfo2;
6177 if (mips_opts.micromips
6178 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6179 && insn_length (history) != 2)
6181 if (mips_opts.micromips
6182 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6183 && insn_length (history) != 4)
6186 /* On R5900 short loops need to be fixed by inserting a nop in
6187 the branch delay slots.
6188 A short loop can be terminated too early. */
6189 if (mips_opts.arch == CPU_R5900
6190 /* Check if instruction has a parameter, ignore "j $31". */
6191 && (address_expr != NULL)
6192 /* Parameter must be 16 bit. */
6193 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6194 /* Branch to same segment. */
6195 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6196 /* Branch to same code fragment. */
6197 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6198 /* Can only calculate branch offset if value is known. */
6199 && symbol_constant_p(address_expr->X_add_symbol)
6200 /* Check if branch is really conditional. */
6201 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6202 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6203 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6206 /* Check if loop is shorter than 6 instructions including
6207 branch and delay slot. */
6208 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6215 /* When the loop includes branches or jumps,
6216 it is not a short loop. */
6217 for (i = 0; i < (distance / 4); i++)
6219 if ((history[i].cleared_p)
6220 || delayed_branch_p(&history[i]))
6228 /* Insert nop after branch to fix short loop. */
6237 /* Decide how we should add IP to the instruction stream.
6238 ADDRESS_EXPR is an operand of the instruction to be used with
6241 static enum append_method
6242 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6243 bfd_reloc_code_real_type *reloc_type)
6245 /* The relaxed version of a macro sequence must be inherently
6247 if (mips_relax.sequence == 2)
6250 /* We must not dabble with instructions in a ".set norerorder" block. */
6251 if (mips_opts.noreorder)
6254 /* Otherwise, it's our responsibility to fill branch delay slots. */
6255 if (delayed_branch_p (ip))
6257 if (!branch_likely_p (ip)
6258 && can_swap_branch_p (ip, address_expr, reloc_type))
6261 if (mips_opts.mips16
6262 && ISA_SUPPORTS_MIPS16E
6263 && gpr_read_mask (ip) != 0)
6264 return APPEND_ADD_COMPACT;
6266 return APPEND_ADD_WITH_NOP;
6272 /* IP is a MIPS16 instruction whose opcode we have just changed.
6273 Point IP->insn_mo to the new opcode's definition. */
6276 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6278 const struct mips_opcode *mo, *end;
6280 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6281 for (mo = ip->insn_mo; mo < end; mo++)
6282 if ((ip->insn_opcode & mo->mask) == mo->match)
6290 /* For microMIPS macros, we need to generate a local number label
6291 as the target of branches. */
6292 #define MICROMIPS_LABEL_CHAR '\037'
6293 static unsigned long micromips_target_label;
6294 static char micromips_target_name[32];
6297 micromips_label_name (void)
6299 char *p = micromips_target_name;
6300 char symbol_name_temporary[24];
6308 l = micromips_target_label;
6309 #ifdef LOCAL_LABEL_PREFIX
6310 *p++ = LOCAL_LABEL_PREFIX;
6313 *p++ = MICROMIPS_LABEL_CHAR;
6316 symbol_name_temporary[i++] = l % 10 + '0';
6321 *p++ = symbol_name_temporary[--i];
6324 return micromips_target_name;
6328 micromips_label_expr (expressionS *label_expr)
6330 label_expr->X_op = O_symbol;
6331 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6332 label_expr->X_add_number = 0;
6336 micromips_label_inc (void)
6338 micromips_target_label++;
6339 *micromips_target_name = '\0';
6343 micromips_add_label (void)
6347 s = colon (micromips_label_name ());
6348 micromips_label_inc ();
6349 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6352 /* If assembling microMIPS code, then return the microMIPS reloc
6353 corresponding to the requested one if any. Otherwise return
6354 the reloc unchanged. */
6356 static bfd_reloc_code_real_type
6357 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6359 static const bfd_reloc_code_real_type relocs[][2] =
6361 /* Keep sorted incrementally by the left-hand key. */
6362 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6363 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6364 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6365 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6366 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6367 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6368 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6369 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6370 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6371 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6372 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6373 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6374 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6375 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6376 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6377 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6378 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6379 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6380 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6381 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6382 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6383 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6384 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6385 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6386 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6387 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6388 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6390 bfd_reloc_code_real_type r;
6393 if (!mips_opts.micromips)
6395 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6401 return relocs[i][1];
6406 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6407 Return true on success, storing the resolved value in RESULT. */
6410 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6415 case BFD_RELOC_MIPS_HIGHEST:
6416 case BFD_RELOC_MICROMIPS_HIGHEST:
6417 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6420 case BFD_RELOC_MIPS_HIGHER:
6421 case BFD_RELOC_MICROMIPS_HIGHER:
6422 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6425 case BFD_RELOC_HI16_S:
6426 case BFD_RELOC_MICROMIPS_HI16_S:
6427 case BFD_RELOC_MIPS16_HI16_S:
6428 *result = ((operand + 0x8000) >> 16) & 0xffff;
6431 case BFD_RELOC_HI16:
6432 case BFD_RELOC_MICROMIPS_HI16:
6433 case BFD_RELOC_MIPS16_HI16:
6434 *result = (operand >> 16) & 0xffff;
6437 case BFD_RELOC_LO16:
6438 case BFD_RELOC_MICROMIPS_LO16:
6439 case BFD_RELOC_MIPS16_LO16:
6440 *result = operand & 0xffff;
6443 case BFD_RELOC_UNUSED:
6452 /* Output an instruction. IP is the instruction information.
6453 ADDRESS_EXPR is an operand of the instruction to be used with
6454 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6455 a macro expansion. */
6458 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
6459 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
6461 unsigned long prev_pinfo2, pinfo;
6462 bfd_boolean relaxed_branch = FALSE;
6463 enum append_method method;
6464 bfd_boolean relax32;
6467 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
6468 fix_loongson2f (ip);
6470 file_ase_mips16 |= mips_opts.mips16;
6471 file_ase_micromips |= mips_opts.micromips;
6473 prev_pinfo2 = history[0].insn_mo->pinfo2;
6474 pinfo = ip->insn_mo->pinfo;
6476 if (mips_opts.micromips
6478 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6479 && micromips_insn_length (ip->insn_mo) != 2)
6480 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6481 && micromips_insn_length (ip->insn_mo) != 4)))
6482 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
6483 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
6485 if (address_expr == NULL)
6487 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6488 && reloc_type[1] == BFD_RELOC_UNUSED
6489 && reloc_type[2] == BFD_RELOC_UNUSED
6490 && address_expr->X_op == O_constant)
6492 switch (*reloc_type)
6494 case BFD_RELOC_MIPS_JMP:
6498 shift = mips_opts.micromips ? 1 : 2;
6499 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6500 as_bad (_("jump to misaligned address (0x%lx)"),
6501 (unsigned long) address_expr->X_add_number);
6502 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6508 case BFD_RELOC_MIPS16_JMP:
6509 if ((address_expr->X_add_number & 3) != 0)
6510 as_bad (_("jump to misaligned address (0x%lx)"),
6511 (unsigned long) address_expr->X_add_number);
6513 (((address_expr->X_add_number & 0x7c0000) << 3)
6514 | ((address_expr->X_add_number & 0xf800000) >> 7)
6515 | ((address_expr->X_add_number & 0x3fffc) >> 2));
6519 case BFD_RELOC_16_PCREL_S2:
6523 shift = mips_opts.micromips ? 1 : 2;
6524 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6525 as_bad (_("branch to misaligned address (0x%lx)"),
6526 (unsigned long) address_expr->X_add_number);
6527 if (!mips_relax_branch)
6529 if ((address_expr->X_add_number + (1 << (shift + 15)))
6530 & ~((1 << (shift + 16)) - 1))
6531 as_bad (_("branch address range overflow (0x%lx)"),
6532 (unsigned long) address_expr->X_add_number);
6533 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6543 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6546 ip->insn_opcode |= value & 0xffff;
6554 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6556 /* There are a lot of optimizations we could do that we don't.
6557 In particular, we do not, in general, reorder instructions.
6558 If you use gcc with optimization, it will reorder
6559 instructions and generally do much more optimization then we
6560 do here; repeating all that work in the assembler would only
6561 benefit hand written assembly code, and does not seem worth
6563 int nops = (mips_optimize == 0
6564 ? nops_for_insn (0, history, NULL)
6565 : nops_for_insn_or_target (0, history, ip));
6569 unsigned long old_frag_offset;
6572 old_frag = frag_now;
6573 old_frag_offset = frag_now_fix ();
6575 for (i = 0; i < nops; i++)
6576 add_fixed_insn (NOP_INSN);
6577 insert_into_history (0, nops, NOP_INSN);
6581 listing_prev_line ();
6582 /* We may be at the start of a variant frag. In case we
6583 are, make sure there is enough space for the frag
6584 after the frags created by listing_prev_line. The
6585 argument to frag_grow here must be at least as large
6586 as the argument to all other calls to frag_grow in
6587 this file. We don't have to worry about being in the
6588 middle of a variant frag, because the variants insert
6589 all needed nop instructions themselves. */
6593 mips_move_text_labels ();
6595 #ifndef NO_ECOFF_DEBUGGING
6596 if (ECOFF_DEBUGGING)
6597 ecoff_fix_loc (old_frag, old_frag_offset);
6601 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6605 /* Work out how many nops in prev_nop_frag are needed by IP,
6606 ignoring hazards generated by the first prev_nop_frag_since
6608 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
6609 gas_assert (nops <= prev_nop_frag_holds);
6611 /* Enforce NOPS as a minimum. */
6612 if (nops > prev_nop_frag_required)
6613 prev_nop_frag_required = nops;
6615 if (prev_nop_frag_holds == prev_nop_frag_required)
6617 /* Settle for the current number of nops. Update the history
6618 accordingly (for the benefit of any future .set reorder code). */
6619 prev_nop_frag = NULL;
6620 insert_into_history (prev_nop_frag_since,
6621 prev_nop_frag_holds, NOP_INSN);
6625 /* Allow this instruction to replace one of the nops that was
6626 tentatively added to prev_nop_frag. */
6627 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
6628 prev_nop_frag_holds--;
6629 prev_nop_frag_since++;
6633 method = get_append_method (ip, address_expr, reloc_type);
6634 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
6636 dwarf2_emit_insn (0);
6637 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6638 so "move" the instruction address accordingly.
6640 Also, it doesn't seem appropriate for the assembler to reorder .loc
6641 entries. If this instruction is a branch that we are going to swap
6642 with the previous instruction, the two instructions should be
6643 treated as a unit, and the debug information for both instructions
6644 should refer to the start of the branch sequence. Using the
6645 current position is certainly wrong when swapping a 32-bit branch
6646 and a 16-bit delay slot, since the current position would then be
6647 in the middle of a branch. */
6648 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
6650 relax32 = (mips_relax_branch
6651 /* Don't try branch relaxation within .set nomacro, or within
6652 .set noat if we use $at for PIC computations. If it turns
6653 out that the branch was out-of-range, we'll get an error. */
6654 && !mips_opts.warn_about_macros
6655 && (mips_opts.at || mips_pic == NO_PIC)
6656 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6657 as they have no complementing branches. */
6658 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
6660 if (!HAVE_CODE_COMPRESSION
6663 && *reloc_type == BFD_RELOC_16_PCREL_S2
6664 && delayed_branch_p (ip))
6666 relaxed_branch = TRUE;
6667 add_relaxed_insn (ip, (relaxed_branch_length
6669 uncond_branch_p (ip) ? -1
6670 : branch_likely_p (ip) ? 1
6674 uncond_branch_p (ip),
6675 branch_likely_p (ip),
6676 pinfo & INSN_WRITE_GPR_31,
6678 address_expr->X_add_symbol,
6679 address_expr->X_add_number);
6680 *reloc_type = BFD_RELOC_UNUSED;
6682 else if (mips_opts.micromips
6684 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6685 || *reloc_type > BFD_RELOC_UNUSED)
6686 && (delayed_branch_p (ip) || compact_branch_p (ip))
6687 /* Don't try branch relaxation when users specify
6688 16-bit/32-bit instructions. */
6689 && !forced_insn_length)
6691 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6692 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
6693 int uncond = uncond_branch_p (ip) ? -1 : 0;
6694 int compact = compact_branch_p (ip);
6695 int al = pinfo & INSN_WRITE_GPR_31;
6698 gas_assert (address_expr != NULL);
6699 gas_assert (!mips_relax.sequence);
6701 relaxed_branch = TRUE;
6702 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6703 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
6704 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6706 address_expr->X_add_symbol,
6707 address_expr->X_add_number);
6708 *reloc_type = BFD_RELOC_UNUSED;
6710 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
6712 /* We need to set up a variant frag. */
6713 gas_assert (address_expr != NULL);
6714 add_relaxed_insn (ip, 4, 0,
6716 (*reloc_type - BFD_RELOC_UNUSED,
6717 forced_insn_length == 2, forced_insn_length == 4,
6718 delayed_branch_p (&history[0]),
6719 history[0].mips16_absolute_jump_p),
6720 make_expr_symbol (address_expr), 0);
6722 else if (mips_opts.mips16 && insn_length (ip) == 2)
6724 if (!delayed_branch_p (ip))
6725 /* Make sure there is enough room to swap this instruction with
6726 a following jump instruction. */
6728 add_fixed_insn (ip);
6732 if (mips_opts.mips16
6733 && mips_opts.noreorder
6734 && delayed_branch_p (&history[0]))
6735 as_warn (_("extended instruction in delay slot"));
6737 if (mips_relax.sequence)
6739 /* If we've reached the end of this frag, turn it into a variant
6740 frag and record the information for the instructions we've
6742 if (frag_room () < 4)
6743 relax_close_frag ();
6744 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
6747 if (mips_relax.sequence != 2)
6749 if (mips_macro_warning.first_insn_sizes[0] == 0)
6750 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6751 mips_macro_warning.sizes[0] += insn_length (ip);
6752 mips_macro_warning.insns[0]++;
6754 if (mips_relax.sequence != 1)
6756 if (mips_macro_warning.first_insn_sizes[1] == 0)
6757 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6758 mips_macro_warning.sizes[1] += insn_length (ip);
6759 mips_macro_warning.insns[1]++;
6762 if (mips_opts.mips16)
6765 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6767 add_fixed_insn (ip);
6770 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
6772 bfd_reloc_code_real_type final_type[3];
6773 reloc_howto_type *howto0;
6774 reloc_howto_type *howto;
6777 /* Perform any necessary conversion to microMIPS relocations
6778 and find out how many relocations there actually are. */
6779 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6780 final_type[i] = micromips_map_reloc (reloc_type[i]);
6782 /* In a compound relocation, it is the final (outermost)
6783 operator that determines the relocated field. */
6784 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
6789 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
6790 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6791 bfd_get_reloc_size (howto),
6793 howto0 && howto0->pc_relative,
6796 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6797 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
6798 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6800 /* These relocations can have an addend that won't fit in
6801 4 octets for 64bit assembly. */
6803 && ! howto->partial_inplace
6804 && (reloc_type[0] == BFD_RELOC_16
6805 || reloc_type[0] == BFD_RELOC_32
6806 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6807 || reloc_type[0] == BFD_RELOC_GPREL16
6808 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6809 || reloc_type[0] == BFD_RELOC_GPREL32
6810 || reloc_type[0] == BFD_RELOC_64
6811 || reloc_type[0] == BFD_RELOC_CTOR
6812 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6813 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6814 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6815 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6816 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6817 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6818 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6819 || hi16_reloc_p (reloc_type[0])
6820 || lo16_reloc_p (reloc_type[0])))
6821 ip->fixp[0]->fx_no_overflow = 1;
6823 /* These relocations can have an addend that won't fit in 2 octets. */
6824 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6825 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6826 ip->fixp[0]->fx_no_overflow = 1;
6828 if (mips_relax.sequence)
6830 if (mips_relax.first_fixup == 0)
6831 mips_relax.first_fixup = ip->fixp[0];
6833 else if (reloc_needs_lo_p (*reloc_type))
6835 struct mips_hi_fixup *hi_fixup;
6837 /* Reuse the last entry if it already has a matching %lo. */
6838 hi_fixup = mips_hi_fixup_list;
6840 || !fixup_has_matching_lo_p (hi_fixup->fixp))
6842 hi_fixup = ((struct mips_hi_fixup *)
6843 xmalloc (sizeof (struct mips_hi_fixup)));
6844 hi_fixup->next = mips_hi_fixup_list;
6845 mips_hi_fixup_list = hi_fixup;
6847 hi_fixup->fixp = ip->fixp[0];
6848 hi_fixup->seg = now_seg;
6851 /* Add fixups for the second and third relocations, if given.
6852 Note that the ABI allows the second relocation to be
6853 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6854 moment we only use RSS_UNDEF, but we could add support
6855 for the others if it ever becomes necessary. */
6856 for (i = 1; i < 3; i++)
6857 if (reloc_type[i] != BFD_RELOC_UNUSED)
6859 ip->fixp[i] = fix_new (ip->frag, ip->where,
6860 ip->fixp[0]->fx_size, NULL, 0,
6861 FALSE, final_type[i]);
6863 /* Use fx_tcbit to mark compound relocs. */
6864 ip->fixp[0]->fx_tcbit = 1;
6865 ip->fixp[i]->fx_tcbit = 1;
6870 /* Update the register mask information. */
6871 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6872 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
6877 insert_into_history (0, 1, ip);
6880 case APPEND_ADD_WITH_NOP:
6882 struct mips_cl_insn *nop;
6884 insert_into_history (0, 1, ip);
6885 nop = get_delay_slot_nop (ip);
6886 add_fixed_insn (nop);
6887 insert_into_history (0, 1, nop);
6888 if (mips_relax.sequence)
6889 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6893 case APPEND_ADD_COMPACT:
6894 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6895 gas_assert (mips_opts.mips16);
6896 ip->insn_opcode |= 0x0080;
6897 find_altered_mips16_opcode (ip);
6899 insert_into_history (0, 1, ip);
6904 struct mips_cl_insn delay = history[0];
6905 if (mips_opts.mips16)
6907 know (delay.frag == ip->frag);
6908 move_insn (ip, delay.frag, delay.where);
6909 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6911 else if (relaxed_branch || delay.frag != ip->frag)
6913 /* Add the delay slot instruction to the end of the
6914 current frag and shrink the fixed part of the
6915 original frag. If the branch occupies the tail of
6916 the latter, move it backwards to cover the gap. */
6917 delay.frag->fr_fix -= branch_disp;
6918 if (delay.frag == ip->frag)
6919 move_insn (ip, ip->frag, ip->where - branch_disp);
6920 add_fixed_insn (&delay);
6924 move_insn (&delay, ip->frag,
6925 ip->where - branch_disp + insn_length (ip));
6926 move_insn (ip, history[0].frag, history[0].where);
6930 insert_into_history (0, 1, &delay);
6935 /* If we have just completed an unconditional branch, clear the history. */
6936 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6937 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
6941 mips_no_prev_insn ();
6943 for (i = 0; i < ARRAY_SIZE (history); i++)
6944 history[i].cleared_p = 1;
6947 /* We need to emit a label at the end of branch-likely macros. */
6948 if (emit_branch_likely_macro)
6950 emit_branch_likely_macro = FALSE;
6951 micromips_add_label ();
6954 /* We just output an insn, so the next one doesn't have a label. */
6955 mips_clear_insn_labels ();
6958 /* Forget that there was any previous instruction or label.
6959 When BRANCH is true, the branch history is also flushed. */
6962 mips_no_prev_insn (void)
6964 prev_nop_frag = NULL;
6965 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
6966 mips_clear_insn_labels ();
6969 /* This function must be called before we emit something other than
6970 instructions. It is like mips_no_prev_insn except that it inserts
6971 any NOPS that might be needed by previous instructions. */
6974 mips_emit_delays (void)
6976 if (! mips_opts.noreorder)
6978 int nops = nops_for_insn (0, history, NULL);
6982 add_fixed_insn (NOP_INSN);
6983 mips_move_text_labels ();
6986 mips_no_prev_insn ();
6989 /* Start a (possibly nested) noreorder block. */
6992 start_noreorder (void)
6994 if (mips_opts.noreorder == 0)
6999 /* None of the instructions before the .set noreorder can be moved. */
7000 for (i = 0; i < ARRAY_SIZE (history); i++)
7001 history[i].fixed_p = 1;
7003 /* Insert any nops that might be needed between the .set noreorder
7004 block and the previous instructions. We will later remove any
7005 nops that turn out not to be needed. */
7006 nops = nops_for_insn (0, history, NULL);
7009 if (mips_optimize != 0)
7011 /* Record the frag which holds the nop instructions, so
7012 that we can remove them if we don't need them. */
7013 frag_grow (nops * NOP_INSN_SIZE);
7014 prev_nop_frag = frag_now;
7015 prev_nop_frag_holds = nops;
7016 prev_nop_frag_required = 0;
7017 prev_nop_frag_since = 0;
7020 for (; nops > 0; --nops)
7021 add_fixed_insn (NOP_INSN);
7023 /* Move on to a new frag, so that it is safe to simply
7024 decrease the size of prev_nop_frag. */
7025 frag_wane (frag_now);
7027 mips_move_text_labels ();
7029 mips_mark_labels ();
7030 mips_clear_insn_labels ();
7032 mips_opts.noreorder++;
7033 mips_any_noreorder = 1;
7036 /* End a nested noreorder block. */
7039 end_noreorder (void)
7041 mips_opts.noreorder--;
7042 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7044 /* Commit to inserting prev_nop_frag_required nops and go back to
7045 handling nop insertion the .set reorder way. */
7046 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7048 insert_into_history (prev_nop_frag_since,
7049 prev_nop_frag_required, NOP_INSN);
7050 prev_nop_frag = NULL;
7054 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7055 higher bits unset. */
7058 normalize_constant_expr (expressionS *ex)
7060 if (ex->X_op == O_constant
7061 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7062 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7066 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7067 all higher bits unset. */
7070 normalize_address_expr (expressionS *ex)
7072 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7073 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7074 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7075 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7079 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7080 Return true if the match was successful.
7082 OPCODE_EXTRA is a value that should be ORed into the opcode
7083 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7084 there are more alternatives after OPCODE and SOFT_MATCH is
7085 as for mips_arg_info. */
7088 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7089 struct mips_operand_token *tokens, unsigned int opcode_extra,
7090 bfd_boolean lax_match, bfd_boolean complete_p)
7093 struct mips_arg_info arg;
7094 const struct mips_operand *operand;
7097 imm_expr.X_op = O_absent;
7098 offset_expr.X_op = O_absent;
7099 offset_reloc[0] = BFD_RELOC_UNUSED;
7100 offset_reloc[1] = BFD_RELOC_UNUSED;
7101 offset_reloc[2] = BFD_RELOC_UNUSED;
7103 create_insn (insn, opcode);
7104 /* When no opcode suffix is specified, assume ".xyzw". */
7105 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7106 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7108 insn->insn_opcode |= opcode_extra;
7109 memset (&arg, 0, sizeof (arg));
7113 arg.last_regno = ILLEGAL_REG;
7114 arg.dest_regno = ILLEGAL_REG;
7115 arg.lax_match = lax_match;
7116 for (args = opcode->args;; ++args)
7118 if (arg.token->type == OT_END)
7120 /* Handle unary instructions in which only one operand is given.
7121 The source is then the same as the destination. */
7122 if (arg.opnum == 1 && *args == ',')
7124 operand = (mips_opts.micromips
7125 ? decode_micromips_operand (args + 1)
7126 : decode_mips_operand (args + 1));
7127 if (operand && mips_optional_operand_p (operand))
7135 /* Treat elided base registers as $0. */
7136 if (strcmp (args, "(b)") == 0)
7144 /* The register suffix is optional. */
7149 /* Fail the match if there were too few operands. */
7153 /* Successful match. */
7156 clear_insn_error ();
7157 if (arg.dest_regno == arg.last_regno
7158 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7162 (0, _("source and destination must be different"));
7163 else if (arg.last_regno == 31)
7165 (0, _("a destination register must be supplied"));
7167 else if (arg.last_regno == 31
7168 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7169 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7170 set_insn_error (0, _("the source register must not be $31"));
7171 check_completed_insn (&arg);
7175 /* Fail the match if the line has too many operands. */
7179 /* Handle characters that need to match exactly. */
7180 if (*args == '(' || *args == ')' || *args == ',')
7182 if (match_char (&arg, *args))
7189 if (arg.token->type == OT_DOUBLE_CHAR
7190 && arg.token->u.ch == *args)
7198 /* Handle special macro operands. Work out the properties of
7207 *offset_reloc = BFD_RELOC_MIPS_JMP;
7213 if (!match_const_int (&arg, &imm_expr.X_add_number))
7215 imm_expr.X_op = O_constant;
7216 if (HAVE_32BIT_GPRS)
7217 normalize_constant_expr (&imm_expr);
7221 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7223 /* Assume that the offset has been elided and that what
7224 we saw was a base register. The match will fail later
7225 if that assumption turns out to be wrong. */
7226 offset_expr.X_op = O_constant;
7227 offset_expr.X_add_number = 0;
7231 if (!match_expression (&arg, &offset_expr, offset_reloc))
7233 normalize_address_expr (&offset_expr);
7238 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7244 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7250 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7256 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7262 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7266 *offset_reloc = BFD_RELOC_MIPS_JMP;
7270 gas_assert (mips_opts.micromips);
7276 if (!forced_insn_length)
7277 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7279 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7281 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7287 operand = (mips_opts.micromips
7288 ? decode_micromips_operand (args)
7289 : decode_mips_operand (args));
7293 /* Skip prefixes. */
7294 if (*args == '+' || *args == 'm')
7297 if (mips_optional_operand_p (operand)
7299 && (arg.token[0].type != OT_REG
7300 || arg.token[1].type == OT_END))
7302 /* Assume that the register has been elided and is the
7303 same as the first operand. */
7308 if (!match_operand (&arg, operand))
7313 /* Like match_insn, but for MIPS16. */
7316 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7317 struct mips_operand_token *tokens)
7320 const struct mips_operand *operand;
7321 const struct mips_operand *ext_operand;
7322 struct mips_arg_info arg;
7325 create_insn (insn, opcode);
7326 imm_expr.X_op = O_absent;
7327 offset_expr.X_op = O_absent;
7328 offset_reloc[0] = BFD_RELOC_UNUSED;
7329 offset_reloc[1] = BFD_RELOC_UNUSED;
7330 offset_reloc[2] = BFD_RELOC_UNUSED;
7333 memset (&arg, 0, sizeof (arg));
7337 arg.last_regno = ILLEGAL_REG;
7338 arg.dest_regno = ILLEGAL_REG;
7340 for (args = opcode->args;; ++args)
7344 if (arg.token->type == OT_END)
7348 /* Handle unary instructions in which only one operand is given.
7349 The source is then the same as the destination. */
7350 if (arg.opnum == 1 && *args == ',')
7352 operand = decode_mips16_operand (args[1], FALSE);
7353 if (operand && mips_optional_operand_p (operand))
7361 /* Fail the match if there were too few operands. */
7365 /* Successful match. Stuff the immediate value in now, if
7367 clear_insn_error ();
7368 if (opcode->pinfo == INSN_MACRO)
7370 gas_assert (relax_char == 0 || relax_char == 'p');
7371 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7374 && offset_expr.X_op == O_constant
7375 && calculate_reloc (*offset_reloc,
7376 offset_expr.X_add_number,
7379 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7380 forced_insn_length, &insn->insn_opcode);
7381 offset_expr.X_op = O_absent;
7382 *offset_reloc = BFD_RELOC_UNUSED;
7384 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7386 if (forced_insn_length == 2)
7387 set_insn_error (0, _("invalid unextended operand value"));
7388 forced_insn_length = 4;
7389 insn->insn_opcode |= MIPS16_EXTEND;
7391 else if (relax_char)
7392 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7394 check_completed_insn (&arg);
7398 /* Fail the match if the line has too many operands. */
7402 /* Handle characters that need to match exactly. */
7403 if (*args == '(' || *args == ')' || *args == ',')
7405 if (match_char (&arg, *args))
7423 if (!match_const_int (&arg, &imm_expr.X_add_number))
7425 imm_expr.X_op = O_constant;
7426 if (HAVE_32BIT_GPRS)
7427 normalize_constant_expr (&imm_expr);
7432 *offset_reloc = BFD_RELOC_MIPS16_JMP;
7433 insn->insn_opcode <<= 16;
7437 operand = decode_mips16_operand (c, FALSE);
7441 /* '6' is a special case. It is used for BREAK and SDBBP,
7442 whose operands are only meaningful to the software that decodes
7443 them. This means that there is no architectural reason why
7444 they cannot be prefixed by EXTEND, but in practice,
7445 exception handlers will only look at the instruction
7446 itself. We therefore allow '6' to be extended when
7447 disassembling but not when assembling. */
7448 if (operand->type != OP_PCREL && c != '6')
7450 ext_operand = decode_mips16_operand (c, TRUE);
7451 if (operand != ext_operand)
7453 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7455 offset_expr.X_op = O_constant;
7456 offset_expr.X_add_number = 0;
7461 /* We need the OT_INTEGER check because some MIPS16
7462 immediate variants are listed before the register ones. */
7463 if (arg.token->type != OT_INTEGER
7464 || !match_expression (&arg, &offset_expr, offset_reloc))
7467 /* '8' is used for SLTI(U) and has traditionally not
7468 been allowed to take relocation operators. */
7469 if (offset_reloc[0] != BFD_RELOC_UNUSED
7470 && (ext_operand->size != 16 || c == '8'))
7478 if (mips_optional_operand_p (operand)
7480 && (arg.token[0].type != OT_REG
7481 || arg.token[1].type == OT_END))
7483 /* Assume that the register has been elided and is the
7484 same as the first operand. */
7489 if (!match_operand (&arg, operand))
7494 /* Record that the current instruction is invalid for the current ISA. */
7497 match_invalid_for_isa (void)
7500 (0, _("opcode not supported on this processor: %s (%s)"),
7501 mips_cpu_info_from_arch (mips_opts.arch)->name,
7502 mips_cpu_info_from_isa (mips_opts.isa)->name);
7505 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
7506 Return true if a definite match or failure was found, storing any match
7507 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
7508 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
7509 tried and failed to match under normal conditions and now want to try a
7510 more relaxed match. */
7513 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
7514 const struct mips_opcode *past, struct mips_operand_token *tokens,
7515 int opcode_extra, bfd_boolean lax_match)
7517 const struct mips_opcode *opcode;
7518 const struct mips_opcode *invalid_delay_slot;
7519 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
7521 /* Search for a match, ignoring alternatives that don't satisfy the
7522 current ISA or forced_length. */
7523 invalid_delay_slot = 0;
7524 seen_valid_for_isa = FALSE;
7525 seen_valid_for_size = FALSE;
7529 gas_assert (strcmp (opcode->name, first->name) == 0);
7530 if (is_opcode_valid (opcode))
7532 seen_valid_for_isa = TRUE;
7533 if (is_size_valid (opcode))
7535 bfd_boolean delay_slot_ok;
7537 seen_valid_for_size = TRUE;
7538 delay_slot_ok = is_delay_slot_valid (opcode);
7539 if (match_insn (insn, opcode, tokens, opcode_extra,
7540 lax_match, delay_slot_ok))
7544 if (!invalid_delay_slot)
7545 invalid_delay_slot = opcode;
7554 while (opcode < past && strcmp (opcode->name, first->name) == 0);
7556 /* If the only matches we found had the wrong length for the delay slot,
7557 pick the first such match. We'll issue an appropriate warning later. */
7558 if (invalid_delay_slot)
7560 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
7566 /* Handle the case where we didn't try to match an instruction because
7567 all the alternatives were incompatible with the current ISA. */
7568 if (!seen_valid_for_isa)
7570 match_invalid_for_isa ();
7574 /* Handle the case where we didn't try to match an instruction because
7575 all the alternatives were of the wrong size. */
7576 if (!seen_valid_for_size)
7578 if (mips_opts.insn32)
7579 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
7582 (0, _("unrecognized %d-bit version of microMIPS opcode"),
7583 8 * forced_insn_length);
7590 /* Like match_insns, but for MIPS16. */
7593 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
7594 struct mips_operand_token *tokens)
7596 const struct mips_opcode *opcode;
7597 bfd_boolean seen_valid_for_isa;
7599 /* Search for a match, ignoring alternatives that don't satisfy the
7600 current ISA. There are no separate entries for extended forms so
7601 we deal with forced_length later. */
7602 seen_valid_for_isa = FALSE;
7606 gas_assert (strcmp (opcode->name, first->name) == 0);
7607 if (is_opcode_valid_16 (opcode))
7609 seen_valid_for_isa = TRUE;
7610 if (match_mips16_insn (insn, opcode, tokens))
7615 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
7616 && strcmp (opcode->name, first->name) == 0);
7618 /* Handle the case where we didn't try to match an instruction because
7619 all the alternatives were incompatible with the current ISA. */
7620 if (!seen_valid_for_isa)
7622 match_invalid_for_isa ();
7629 /* Set up global variables for the start of a new macro. */
7634 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
7635 memset (&mips_macro_warning.first_insn_sizes, 0,
7636 sizeof (mips_macro_warning.first_insn_sizes));
7637 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
7638 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
7639 && delayed_branch_p (&history[0]));
7640 switch (history[0].insn_mo->pinfo2
7641 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
7643 case INSN2_BRANCH_DELAY_32BIT:
7644 mips_macro_warning.delay_slot_length = 4;
7646 case INSN2_BRANCH_DELAY_16BIT:
7647 mips_macro_warning.delay_slot_length = 2;
7650 mips_macro_warning.delay_slot_length = 0;
7653 mips_macro_warning.first_frag = NULL;
7656 /* Given that a macro is longer than one instruction or of the wrong size,
7657 return the appropriate warning for it. Return null if no warning is
7658 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7659 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7660 and RELAX_NOMACRO. */
7663 macro_warning (relax_substateT subtype)
7665 if (subtype & RELAX_DELAY_SLOT)
7666 return _("macro instruction expanded into multiple instructions"
7667 " in a branch delay slot");
7668 else if (subtype & RELAX_NOMACRO)
7669 return _("macro instruction expanded into multiple instructions");
7670 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
7671 | RELAX_DELAY_SLOT_SIZE_SECOND))
7672 return ((subtype & RELAX_DELAY_SLOT_16BIT)
7673 ? _("macro instruction expanded into a wrong size instruction"
7674 " in a 16-bit branch delay slot")
7675 : _("macro instruction expanded into a wrong size instruction"
7676 " in a 32-bit branch delay slot"));
7681 /* Finish up a macro. Emit warnings as appropriate. */
7686 /* Relaxation warning flags. */
7687 relax_substateT subtype = 0;
7689 /* Check delay slot size requirements. */
7690 if (mips_macro_warning.delay_slot_length == 2)
7691 subtype |= RELAX_DELAY_SLOT_16BIT;
7692 if (mips_macro_warning.delay_slot_length != 0)
7694 if (mips_macro_warning.delay_slot_length
7695 != mips_macro_warning.first_insn_sizes[0])
7696 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
7697 if (mips_macro_warning.delay_slot_length
7698 != mips_macro_warning.first_insn_sizes[1])
7699 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
7702 /* Check instruction count requirements. */
7703 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
7705 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
7706 subtype |= RELAX_SECOND_LONGER;
7707 if (mips_opts.warn_about_macros)
7708 subtype |= RELAX_NOMACRO;
7709 if (mips_macro_warning.delay_slot_p)
7710 subtype |= RELAX_DELAY_SLOT;
7713 /* If both alternatives fail to fill a delay slot correctly,
7714 emit the warning now. */
7715 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
7716 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
7721 s = subtype & (RELAX_DELAY_SLOT_16BIT
7722 | RELAX_DELAY_SLOT_SIZE_FIRST
7723 | RELAX_DELAY_SLOT_SIZE_SECOND);
7724 msg = macro_warning (s);
7726 as_warn ("%s", msg);
7730 /* If both implementations are longer than 1 instruction, then emit the
7732 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
7737 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
7738 msg = macro_warning (s);
7740 as_warn ("%s", msg);
7744 /* If any flags still set, then one implementation might need a warning
7745 and the other either will need one of a different kind or none at all.
7746 Pass any remaining flags over to relaxation. */
7747 if (mips_macro_warning.first_frag != NULL)
7748 mips_macro_warning.first_frag->fr_subtype |= subtype;
7751 /* Instruction operand formats used in macros that vary between
7752 standard MIPS and microMIPS code. */
7754 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
7755 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
7756 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
7757 static const char * const lui_fmt[2] = { "t,u", "s,u" };
7758 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
7759 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
7760 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
7761 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
7763 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7764 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7765 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7766 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7767 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7768 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7769 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7770 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7772 /* Read a macro's relocation codes from *ARGS and store them in *R.
7773 The first argument in *ARGS will be either the code for a single
7774 relocation or -1 followed by the three codes that make up a
7775 composite relocation. */
7778 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
7782 next = va_arg (*args, int);
7784 r[0] = (bfd_reloc_code_real_type) next;
7787 for (i = 0; i < 3; i++)
7788 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
7789 /* This function is only used for 16-bit relocation fields.
7790 To make the macro code simpler, treat an unrelocated value
7791 in the same way as BFD_RELOC_LO16. */
7792 if (r[0] == BFD_RELOC_UNUSED)
7793 r[0] = BFD_RELOC_LO16;
7797 /* Build an instruction created by a macro expansion. This is passed
7798 a pointer to the count of instructions created so far, an
7799 expression, the name of the instruction to build, an operand format
7800 string, and corresponding arguments. */
7803 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
7805 const struct mips_opcode *mo = NULL;
7806 bfd_reloc_code_real_type r[3];
7807 const struct mips_opcode *amo;
7808 const struct mips_operand *operand;
7809 struct hash_control *hash;
7810 struct mips_cl_insn insn;
7814 va_start (args, fmt);
7816 if (mips_opts.mips16)
7818 mips16_macro_build (ep, name, fmt, &args);
7823 r[0] = BFD_RELOC_UNUSED;
7824 r[1] = BFD_RELOC_UNUSED;
7825 r[2] = BFD_RELOC_UNUSED;
7826 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
7827 amo = (struct mips_opcode *) hash_find (hash, name);
7829 gas_assert (strcmp (name, amo->name) == 0);
7833 /* Search until we get a match for NAME. It is assumed here that
7834 macros will never generate MDMX, MIPS-3D, or MT instructions.
7835 We try to match an instruction that fulfils the branch delay
7836 slot instruction length requirement (if any) of the previous
7837 instruction. While doing this we record the first instruction
7838 seen that matches all the other conditions and use it anyway
7839 if the requirement cannot be met; we will issue an appropriate
7840 warning later on. */
7841 if (strcmp (fmt, amo->args) == 0
7842 && amo->pinfo != INSN_MACRO
7843 && is_opcode_valid (amo)
7844 && is_size_valid (amo))
7846 if (is_delay_slot_valid (amo))
7856 gas_assert (amo->name);
7858 while (strcmp (name, amo->name) == 0);
7861 create_insn (&insn, mo);
7874 macro_read_relocs (&args, r);
7875 gas_assert (*r == BFD_RELOC_GPREL16
7876 || *r == BFD_RELOC_MIPS_HIGHER
7877 || *r == BFD_RELOC_HI16_S
7878 || *r == BFD_RELOC_LO16
7879 || *r == BFD_RELOC_MIPS_GOT_OFST);
7883 macro_read_relocs (&args, r);
7887 macro_read_relocs (&args, r);
7888 gas_assert (ep != NULL
7889 && (ep->X_op == O_constant
7890 || (ep->X_op == O_symbol
7891 && (*r == BFD_RELOC_MIPS_HIGHEST
7892 || *r == BFD_RELOC_HI16_S
7893 || *r == BFD_RELOC_HI16
7894 || *r == BFD_RELOC_GPREL16
7895 || *r == BFD_RELOC_MIPS_GOT_HI16
7896 || *r == BFD_RELOC_MIPS_CALL_HI16))));
7900 gas_assert (ep != NULL);
7903 * This allows macro() to pass an immediate expression for
7904 * creating short branches without creating a symbol.
7906 * We don't allow branch relaxation for these branches, as
7907 * they should only appear in ".set nomacro" anyway.
7909 if (ep->X_op == O_constant)
7911 /* For microMIPS we always use relocations for branches.
7912 So we should not resolve immediate values. */
7913 gas_assert (!mips_opts.micromips);
7915 if ((ep->X_add_number & 3) != 0)
7916 as_bad (_("branch to misaligned address (0x%lx)"),
7917 (unsigned long) ep->X_add_number);
7918 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
7919 as_bad (_("branch address range overflow (0x%lx)"),
7920 (unsigned long) ep->X_add_number);
7921 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
7925 *r = BFD_RELOC_16_PCREL_S2;
7929 gas_assert (ep != NULL);
7930 *r = BFD_RELOC_MIPS_JMP;
7934 operand = (mips_opts.micromips
7935 ? decode_micromips_operand (fmt)
7936 : decode_mips_operand (fmt));
7940 uval = va_arg (args, int);
7941 if (operand->type == OP_CLO_CLZ_DEST)
7942 uval |= (uval << 5);
7943 insn_insert_operand (&insn, operand, uval);
7945 if (*fmt == '+' || *fmt == 'm')
7951 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7953 append_insn (&insn, ep, r, TRUE);
7957 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
7960 struct mips_opcode *mo;
7961 struct mips_cl_insn insn;
7962 const struct mips_operand *operand;
7963 bfd_reloc_code_real_type r[3]
7964 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
7966 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
7968 gas_assert (strcmp (name, mo->name) == 0);
7970 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
7973 gas_assert (mo->name);
7974 gas_assert (strcmp (name, mo->name) == 0);
7977 create_insn (&insn, mo);
8015 gas_assert (ep != NULL);
8017 if (ep->X_op != O_constant)
8018 *r = (int) BFD_RELOC_UNUSED + c;
8019 else if (calculate_reloc (*r, ep->X_add_number, &value))
8021 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8023 *r = BFD_RELOC_UNUSED;
8029 operand = decode_mips16_operand (c, FALSE);
8033 insn_insert_operand (&insn, operand, va_arg (*args, int));
8038 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8040 append_insn (&insn, ep, r, TRUE);
8044 * Generate a "jalr" instruction with a relocation hint to the called
8045 * function. This occurs in NewABI PIC code.
8048 macro_build_jalr (expressionS *ep, int cprestore)
8050 static const bfd_reloc_code_real_type jalr_relocs[2]
8051 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8052 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8056 if (MIPS_JALR_HINT_P (ep))
8061 if (mips_opts.micromips)
8063 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8064 ? "jalr" : "jalrs");
8065 if (MIPS_JALR_HINT_P (ep)
8067 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8068 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8070 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8073 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
8074 if (MIPS_JALR_HINT_P (ep))
8075 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
8079 * Generate a "lui" instruction.
8082 macro_build_lui (expressionS *ep, int regnum)
8084 gas_assert (! mips_opts.mips16);
8086 if (ep->X_op != O_constant)
8088 gas_assert (ep->X_op == O_symbol);
8089 /* _gp_disp is a special case, used from s_cpload.
8090 __gnu_local_gp is used if mips_no_shared. */
8091 gas_assert (mips_pic == NO_PIC
8093 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8094 || (! mips_in_shared
8095 && strcmp (S_GET_NAME (ep->X_add_symbol),
8096 "__gnu_local_gp") == 0));
8099 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
8102 /* Generate a sequence of instructions to do a load or store from a constant
8103 offset off of a base register (breg) into/from a target register (treg),
8104 using AT if necessary. */
8106 macro_build_ldst_constoffset (expressionS *ep, const char *op,
8107 int treg, int breg, int dbl)
8109 gas_assert (ep->X_op == O_constant);
8111 /* Sign-extending 32-bit constants makes their handling easier. */
8113 normalize_constant_expr (ep);
8115 /* Right now, this routine can only handle signed 32-bit constants. */
8116 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
8117 as_warn (_("operand overflow"));
8119 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8121 /* Signed 16-bit offset will fit in the op. Easy! */
8122 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8126 /* 32-bit offset, need multiple instructions and AT, like:
8127 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8128 addu $tempreg,$tempreg,$breg
8129 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8130 to handle the complete offset. */
8131 macro_build_lui (ep, AT);
8132 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8133 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8136 as_bad (_("macro used $at after \".set noat\""));
8141 * Generates code to set the $at register to true (one)
8142 * if reg is less than the immediate expression.
8145 set_at (int reg, int unsignedp)
8147 if (imm_expr.X_add_number >= -0x8000
8148 && imm_expr.X_add_number < 0x8000)
8149 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8150 AT, reg, BFD_RELOC_LO16);
8153 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8154 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8158 /* Count the leading zeroes by performing a binary chop. This is a
8159 bulky bit of source, but performance is a LOT better for the
8160 majority of values than a simple loop to count the bits:
8161 for (lcnt = 0; (lcnt < 32); lcnt++)
8162 if ((v) & (1 << (31 - lcnt)))
8164 However it is not code size friendly, and the gain will drop a bit
8165 on certain cached systems.
8167 #define COUNT_TOP_ZEROES(v) \
8168 (((v) & ~0xffff) == 0 \
8169 ? ((v) & ~0xff) == 0 \
8170 ? ((v) & ~0xf) == 0 \
8171 ? ((v) & ~0x3) == 0 \
8172 ? ((v) & ~0x1) == 0 \
8177 : ((v) & ~0x7) == 0 \
8180 : ((v) & ~0x3f) == 0 \
8181 ? ((v) & ~0x1f) == 0 \
8184 : ((v) & ~0x7f) == 0 \
8187 : ((v) & ~0xfff) == 0 \
8188 ? ((v) & ~0x3ff) == 0 \
8189 ? ((v) & ~0x1ff) == 0 \
8192 : ((v) & ~0x7ff) == 0 \
8195 : ((v) & ~0x3fff) == 0 \
8196 ? ((v) & ~0x1fff) == 0 \
8199 : ((v) & ~0x7fff) == 0 \
8202 : ((v) & ~0xffffff) == 0 \
8203 ? ((v) & ~0xfffff) == 0 \
8204 ? ((v) & ~0x3ffff) == 0 \
8205 ? ((v) & ~0x1ffff) == 0 \
8208 : ((v) & ~0x7ffff) == 0 \
8211 : ((v) & ~0x3fffff) == 0 \
8212 ? ((v) & ~0x1fffff) == 0 \
8215 : ((v) & ~0x7fffff) == 0 \
8218 : ((v) & ~0xfffffff) == 0 \
8219 ? ((v) & ~0x3ffffff) == 0 \
8220 ? ((v) & ~0x1ffffff) == 0 \
8223 : ((v) & ~0x7ffffff) == 0 \
8226 : ((v) & ~0x3fffffff) == 0 \
8227 ? ((v) & ~0x1fffffff) == 0 \
8230 : ((v) & ~0x7fffffff) == 0 \
8235 * This routine generates the least number of instructions necessary to load
8236 * an absolute expression value into a register.
8239 load_register (int reg, expressionS *ep, int dbl)
8242 expressionS hi32, lo32;
8244 if (ep->X_op != O_big)
8246 gas_assert (ep->X_op == O_constant);
8248 /* Sign-extending 32-bit constants makes their handling easier. */
8250 normalize_constant_expr (ep);
8252 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8254 /* We can handle 16 bit signed values with an addiu to
8255 $zero. No need to ever use daddiu here, since $zero and
8256 the result are always correct in 32 bit mode. */
8257 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8260 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8262 /* We can handle 16 bit unsigned values with an ori to
8264 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8267 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8269 /* 32 bit values require an lui. */
8270 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8271 if ((ep->X_add_number & 0xffff) != 0)
8272 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8277 /* The value is larger than 32 bits. */
8279 if (!dbl || HAVE_32BIT_GPRS)
8283 sprintf_vma (value, ep->X_add_number);
8284 as_bad (_("number (0x%s) larger than 32 bits"), value);
8285 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8289 if (ep->X_op != O_big)
8292 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8293 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8294 hi32.X_add_number &= 0xffffffff;
8296 lo32.X_add_number &= 0xffffffff;
8300 gas_assert (ep->X_add_number > 2);
8301 if (ep->X_add_number == 3)
8302 generic_bignum[3] = 0;
8303 else if (ep->X_add_number > 4)
8304 as_bad (_("number larger than 64 bits"));
8305 lo32.X_op = O_constant;
8306 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8307 hi32.X_op = O_constant;
8308 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8311 if (hi32.X_add_number == 0)
8316 unsigned long hi, lo;
8318 if (hi32.X_add_number == (offsetT) 0xffffffff)
8320 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8322 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8325 if (lo32.X_add_number & 0x80000000)
8327 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8328 if (lo32.X_add_number & 0xffff)
8329 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8334 /* Check for 16bit shifted constant. We know that hi32 is
8335 non-zero, so start the mask on the first bit of the hi32
8340 unsigned long himask, lomask;
8344 himask = 0xffff >> (32 - shift);
8345 lomask = (0xffff << shift) & 0xffffffff;
8349 himask = 0xffff << (shift - 32);
8352 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8353 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8357 tmp.X_op = O_constant;
8359 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8360 | (lo32.X_add_number >> shift));
8362 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
8363 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8364 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8365 reg, reg, (shift >= 32) ? shift - 32 : shift);
8370 while (shift <= (64 - 16));
8372 /* Find the bit number of the lowest one bit, and store the
8373 shifted value in hi/lo. */
8374 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8375 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8379 while ((lo & 1) == 0)
8384 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8390 while ((hi & 1) == 0)
8399 /* Optimize if the shifted value is a (power of 2) - 1. */
8400 if ((hi == 0 && ((lo + 1) & lo) == 0)
8401 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
8403 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
8408 /* This instruction will set the register to be all
8410 tmp.X_op = O_constant;
8411 tmp.X_add_number = (offsetT) -1;
8412 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8416 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8417 reg, reg, (bit >= 32) ? bit - 32 : bit);
8419 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
8420 reg, reg, (shift >= 32) ? shift - 32 : shift);
8425 /* Sign extend hi32 before calling load_register, because we can
8426 generally get better code when we load a sign extended value. */
8427 if ((hi32.X_add_number & 0x80000000) != 0)
8428 hi32.X_add_number |= ~(offsetT) 0xffffffff;
8429 load_register (reg, &hi32, 0);
8432 if ((lo32.X_add_number & 0xffff0000) == 0)
8436 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
8444 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
8446 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8447 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
8453 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
8457 mid16.X_add_number >>= 16;
8458 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
8459 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8462 if ((lo32.X_add_number & 0xffff) != 0)
8463 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
8467 load_delay_nop (void)
8469 if (!gpr_interlocks)
8470 macro_build (NULL, "nop", "");
8473 /* Load an address into a register. */
8476 load_address (int reg, expressionS *ep, int *used_at)
8478 if (ep->X_op != O_constant
8479 && ep->X_op != O_symbol)
8481 as_bad (_("expression too complex"));
8482 ep->X_op = O_constant;
8485 if (ep->X_op == O_constant)
8487 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
8491 if (mips_pic == NO_PIC)
8493 /* If this is a reference to a GP relative symbol, we want
8494 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8496 lui $reg,<sym> (BFD_RELOC_HI16_S)
8497 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8498 If we have an addend, we always use the latter form.
8500 With 64bit address space and a usable $at we want
8501 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8502 lui $at,<sym> (BFD_RELOC_HI16_S)
8503 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8504 daddiu $at,<sym> (BFD_RELOC_LO16)
8508 If $at is already in use, we use a path which is suboptimal
8509 on superscalar processors.
8510 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8511 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8513 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8515 daddiu $reg,<sym> (BFD_RELOC_LO16)
8517 For GP relative symbols in 64bit address space we can use
8518 the same sequence as in 32bit address space. */
8519 if (HAVE_64BIT_SYMBOLS)
8521 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8522 && !nopic_need_relax (ep->X_add_symbol, 1))
8524 relax_start (ep->X_add_symbol);
8525 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8526 mips_gp_register, BFD_RELOC_GPREL16);
8530 if (*used_at == 0 && mips_opts.at)
8532 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8533 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
8534 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8535 BFD_RELOC_MIPS_HIGHER);
8536 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
8537 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
8538 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
8543 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8544 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8545 BFD_RELOC_MIPS_HIGHER);
8546 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8547 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
8548 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8549 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
8552 if (mips_relax.sequence)
8557 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8558 && !nopic_need_relax (ep->X_add_symbol, 1))
8560 relax_start (ep->X_add_symbol);
8561 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8562 mips_gp_register, BFD_RELOC_GPREL16);
8565 macro_build_lui (ep, reg);
8566 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
8567 reg, reg, BFD_RELOC_LO16);
8568 if (mips_relax.sequence)
8572 else if (!mips_big_got)
8576 /* If this is a reference to an external symbol, we want
8577 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8579 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8581 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8582 If there is a constant, it must be added in after.
8584 If we have NewABI, we want
8585 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8586 unless we're referencing a global symbol with a non-zero
8587 offset, in which case cst must be added separately. */
8590 if (ep->X_add_number)
8592 ex.X_add_number = ep->X_add_number;
8593 ep->X_add_number = 0;
8594 relax_start (ep->X_add_symbol);
8595 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8596 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8597 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8598 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8599 ex.X_op = O_constant;
8600 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
8601 reg, reg, BFD_RELOC_LO16);
8602 ep->X_add_number = ex.X_add_number;
8605 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8606 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8607 if (mips_relax.sequence)
8612 ex.X_add_number = ep->X_add_number;
8613 ep->X_add_number = 0;
8614 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8615 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8617 relax_start (ep->X_add_symbol);
8619 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8623 if (ex.X_add_number != 0)
8625 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8626 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8627 ex.X_op = O_constant;
8628 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
8629 reg, reg, BFD_RELOC_LO16);
8633 else if (mips_big_got)
8637 /* This is the large GOT case. If this is a reference to an
8638 external symbol, we want
8639 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8641 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8643 Otherwise, for a reference to a local symbol in old ABI, we want
8644 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8646 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8647 If there is a constant, it must be added in after.
8649 In the NewABI, for local symbols, with or without offsets, we want:
8650 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8651 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8655 ex.X_add_number = ep->X_add_number;
8656 ep->X_add_number = 0;
8657 relax_start (ep->X_add_symbol);
8658 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
8659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8660 reg, reg, mips_gp_register);
8661 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8662 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
8663 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8664 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8665 else if (ex.X_add_number)
8667 ex.X_op = O_constant;
8668 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8672 ep->X_add_number = ex.X_add_number;
8674 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8675 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8676 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8677 BFD_RELOC_MIPS_GOT_OFST);
8682 ex.X_add_number = ep->X_add_number;
8683 ep->X_add_number = 0;
8684 relax_start (ep->X_add_symbol);
8685 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
8686 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8687 reg, reg, mips_gp_register);
8688 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8689 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
8691 if (reg_needs_delay (mips_gp_register))
8693 /* We need a nop before loading from $gp. This special
8694 check is required because the lui which starts the main
8695 instruction stream does not refer to $gp, and so will not
8696 insert the nop which may be required. */
8697 macro_build (NULL, "nop", "");
8699 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8700 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8702 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8706 if (ex.X_add_number != 0)
8708 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8709 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8710 ex.X_op = O_constant;
8711 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8719 if (!mips_opts.at && *used_at == 1)
8720 as_bad (_("macro used $at after \".set noat\""));
8723 /* Move the contents of register SOURCE into register DEST. */
8726 move_register (int dest, int source)
8728 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8729 instruction specifically requires a 32-bit one. */
8730 if (mips_opts.micromips
8731 && !mips_opts.insn32
8732 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8733 macro_build (NULL, "move", "mp,mj", dest, source);
8735 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
8739 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8740 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8741 The two alternatives are:
8743 Global symbol Local sybmol
8744 ------------- ------------
8745 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8747 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8749 load_got_offset emits the first instruction and add_got_offset
8750 emits the second for a 16-bit offset or add_got_offset_hilo emits
8751 a sequence to add a 32-bit offset using a scratch register. */
8754 load_got_offset (int dest, expressionS *local)
8759 global.X_add_number = 0;
8761 relax_start (local->X_add_symbol);
8762 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8763 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8765 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8766 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8771 add_got_offset (int dest, expressionS *local)
8775 global.X_op = O_constant;
8776 global.X_op_symbol = NULL;
8777 global.X_add_symbol = NULL;
8778 global.X_add_number = local->X_add_number;
8780 relax_start (local->X_add_symbol);
8781 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
8782 dest, dest, BFD_RELOC_LO16);
8784 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
8789 add_got_offset_hilo (int dest, expressionS *local, int tmp)
8792 int hold_mips_optimize;
8794 global.X_op = O_constant;
8795 global.X_op_symbol = NULL;
8796 global.X_add_symbol = NULL;
8797 global.X_add_number = local->X_add_number;
8799 relax_start (local->X_add_symbol);
8800 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
8802 /* Set mips_optimize around the lui instruction to avoid
8803 inserting an unnecessary nop after the lw. */
8804 hold_mips_optimize = mips_optimize;
8806 macro_build_lui (&global, tmp);
8807 mips_optimize = hold_mips_optimize;
8808 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
8811 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
8814 /* Emit a sequence of instructions to emulate a branch likely operation.
8815 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8816 is its complementing branch with the original condition negated.
8817 CALL is set if the original branch specified the link operation.
8818 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8820 Code like this is produced in the noreorder mode:
8825 delay slot (executed only if branch taken)
8833 delay slot (executed only if branch taken)
8836 In the reorder mode the delay slot would be filled with a nop anyway,
8837 so code produced is simply:
8842 This function is used when producing code for the microMIPS ASE that
8843 does not implement branch likely instructions in hardware. */
8846 macro_build_branch_likely (const char *br, const char *brneg,
8847 int call, expressionS *ep, const char *fmt,
8848 unsigned int sreg, unsigned int treg)
8850 int noreorder = mips_opts.noreorder;
8853 gas_assert (mips_opts.micromips);
8857 micromips_label_expr (&expr1);
8858 macro_build (&expr1, brneg, fmt, sreg, treg);
8859 macro_build (NULL, "nop", "");
8860 macro_build (ep, call ? "bal" : "b", "p");
8862 /* Set to true so that append_insn adds a label. */
8863 emit_branch_likely_macro = TRUE;
8867 macro_build (ep, br, fmt, sreg, treg);
8868 macro_build (NULL, "nop", "");
8873 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8874 the condition code tested. EP specifies the branch target. */
8877 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
8904 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
8907 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8908 the register tested. EP specifies the branch target. */
8911 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
8913 const char *brneg = NULL;
8923 br = mips_opts.micromips ? "bgez" : "bgezl";
8927 gas_assert (mips_opts.micromips);
8928 br = mips_opts.insn32 ? "bgezal" : "bgezals";
8936 br = mips_opts.micromips ? "bgtz" : "bgtzl";
8943 br = mips_opts.micromips ? "blez" : "blezl";
8950 br = mips_opts.micromips ? "bltz" : "bltzl";
8954 gas_assert (mips_opts.micromips);
8955 br = mips_opts.insn32 ? "bltzal" : "bltzals";
8962 if (mips_opts.micromips && brneg)
8963 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
8965 macro_build (ep, br, "s,p", sreg);
8968 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8969 TREG as the registers tested. EP specifies the branch target. */
8972 macro_build_branch_rsrt (int type, expressionS *ep,
8973 unsigned int sreg, unsigned int treg)
8975 const char *brneg = NULL;
8987 br = mips_opts.micromips ? "beq" : "beql";
8996 br = mips_opts.micromips ? "bne" : "bnel";
9002 if (mips_opts.micromips && brneg)
9003 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9005 macro_build (ep, br, "s,t,p", sreg, treg);
9008 /* Return the high part that should be loaded in order to make the low
9009 part of VALUE accessible using an offset of OFFBITS bits. */
9012 offset_high_part (offsetT value, unsigned int offbits)
9019 bias = 1 << (offbits - 1);
9020 low_mask = bias * 2 - 1;
9021 return (value + bias) & ~low_mask;
9024 /* Return true if the value stored in offset_expr and offset_reloc
9025 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9026 amount that the caller wants to add without inducing overflow
9027 and ALIGN is the known alignment of the value in bytes. */
9030 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9034 /* Accept any relocation operator if overflow isn't a concern. */
9035 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9038 /* These relocations are guaranteed not to overflow in correct links. */
9039 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9040 || gprel16_reloc_p (*offset_reloc))
9043 if (offset_expr.X_op == O_constant
9044 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9045 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9052 * This routine implements the seemingly endless macro or synthesized
9053 * instructions and addressing modes in the mips assembly language. Many
9054 * of these macros are simple and are similar to each other. These could
9055 * probably be handled by some kind of table or grammar approach instead of
9056 * this verbose method. Others are not simple macros but are more like
9057 * optimizing code generation.
9058 * One interesting optimization is when several store macros appear
9059 * consecutively that would load AT with the upper half of the same address.
9060 * The ensuing load upper instructions are ommited. This implies some kind
9061 * of global optimization. We currently only optimize within a single macro.
9062 * For many of the load and store macros if the address is specified as a
9063 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9064 * first load register 'at' with zero and use it as the base register. The
9065 * mips assembler simply uses register $zero. Just one tiny optimization
9069 macro (struct mips_cl_insn *ip, char *str)
9071 const struct mips_operand_array *operands;
9072 unsigned int breg, i;
9073 unsigned int tempreg;
9076 expressionS label_expr;
9091 bfd_boolean large_offset;
9093 int hold_mips_optimize;
9095 unsigned int op[MAX_OPERANDS];
9097 gas_assert (! mips_opts.mips16);
9099 operands = insn_operands (ip);
9100 for (i = 0; i < MAX_OPERANDS; i++)
9101 if (operands->operand[i])
9102 op[i] = insn_extract_operand (ip, operands->operand[i]);
9106 mask = ip->insn_mo->mask;
9108 label_expr.X_op = O_constant;
9109 label_expr.X_op_symbol = NULL;
9110 label_expr.X_add_symbol = NULL;
9111 label_expr.X_add_number = 0;
9113 expr1.X_op = O_constant;
9114 expr1.X_op_symbol = NULL;
9115 expr1.X_add_symbol = NULL;
9116 expr1.X_add_number = 1;
9132 if (mips_opts.micromips)
9133 micromips_label_expr (&label_expr);
9135 label_expr.X_add_number = 8;
9136 macro_build (&label_expr, "bgez", "s,p", op[1]);
9138 macro_build (NULL, "nop", "");
9140 move_register (op[0], op[1]);
9141 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
9142 if (mips_opts.micromips)
9143 micromips_add_label ();
9160 if (!mips_opts.micromips)
9162 if (imm_expr.X_add_number >= -0x200
9163 && imm_expr.X_add_number < 0x200)
9165 macro_build (NULL, s, "t,r,.", op[0], op[1],
9166 (int) imm_expr.X_add_number);
9175 if (imm_expr.X_add_number >= -0x8000
9176 && imm_expr.X_add_number < 0x8000)
9178 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9183 load_register (AT, &imm_expr, dbl);
9184 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9203 if (imm_expr.X_add_number >= 0
9204 && imm_expr.X_add_number < 0x10000)
9206 if (mask != M_NOR_I)
9207 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9210 macro_build (&imm_expr, "ori", "t,r,i",
9211 op[0], op[1], BFD_RELOC_LO16);
9212 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9218 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9219 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9223 switch (imm_expr.X_add_number)
9226 macro_build (NULL, "nop", "");
9229 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9233 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9234 (int) imm_expr.X_add_number);
9237 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9238 (unsigned long) imm_expr.X_add_number);
9247 gas_assert (mips_opts.micromips);
9248 macro_build_branch_ccl (mask, &offset_expr,
9249 EXTRACT_OPERAND (1, BCC, *ip));
9256 if (imm_expr.X_add_number == 0)
9262 load_register (op[1], &imm_expr, HAVE_64BIT_GPRS);
9267 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9274 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9275 else if (op[0] == 0)
9276 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9280 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9281 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9282 &offset_expr, AT, ZERO);
9292 macro_build_branch_rs (mask, &offset_expr, op[0]);
9298 /* Check for > max integer. */
9299 if (imm_expr.X_add_number >= GPR_SMAX)
9302 /* Result is always false. */
9304 macro_build (NULL, "nop", "");
9306 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9309 ++imm_expr.X_add_number;
9313 if (mask == M_BGEL_I)
9315 if (imm_expr.X_add_number == 0)
9317 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9318 &offset_expr, op[0]);
9321 if (imm_expr.X_add_number == 1)
9323 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9324 &offset_expr, op[0]);
9327 if (imm_expr.X_add_number <= GPR_SMIN)
9330 /* result is always true */
9331 as_warn (_("branch %s is always true"), ip->insn_mo->name);
9332 macro_build (&offset_expr, "b", "p");
9337 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9338 &offset_expr, AT, ZERO);
9346 else if (op[0] == 0)
9347 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9348 &offset_expr, ZERO, op[1]);
9352 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9353 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9354 &offset_expr, AT, ZERO);
9363 && imm_expr.X_add_number == -1))
9365 ++imm_expr.X_add_number;
9369 if (mask == M_BGEUL_I)
9371 if (imm_expr.X_add_number == 0)
9373 else if (imm_expr.X_add_number == 1)
9374 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9375 &offset_expr, op[0], ZERO);
9380 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9381 &offset_expr, AT, ZERO);
9389 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9390 else if (op[0] == 0)
9391 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
9395 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9396 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9397 &offset_expr, AT, ZERO);
9405 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9406 &offset_expr, op[0], ZERO);
9407 else if (op[0] == 0)
9412 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
9413 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9414 &offset_expr, AT, ZERO);
9422 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9423 else if (op[0] == 0)
9424 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
9428 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9429 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9430 &offset_expr, AT, ZERO);
9437 if (imm_expr.X_add_number >= GPR_SMAX)
9439 ++imm_expr.X_add_number;
9443 if (mask == M_BLTL_I)
9445 if (imm_expr.X_add_number == 0)
9446 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9447 else if (imm_expr.X_add_number == 1)
9448 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9453 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9454 &offset_expr, AT, ZERO);
9462 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9463 &offset_expr, op[0], ZERO);
9464 else if (op[0] == 0)
9469 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
9470 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9471 &offset_expr, AT, ZERO);
9480 && imm_expr.X_add_number == -1))
9482 ++imm_expr.X_add_number;
9486 if (mask == M_BLTUL_I)
9488 if (imm_expr.X_add_number == 0)
9490 else if (imm_expr.X_add_number == 1)
9491 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9492 &offset_expr, op[0], ZERO);
9497 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9498 &offset_expr, AT, ZERO);
9506 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9507 else if (op[0] == 0)
9508 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
9512 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9513 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9514 &offset_expr, AT, ZERO);
9523 else if (op[0] == 0)
9524 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9525 &offset_expr, ZERO, op[1]);
9529 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9530 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9531 &offset_expr, AT, ZERO);
9547 as_warn (_("divide by zero"));
9549 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
9551 macro_build (NULL, "break", BRK_FMT, 7);
9558 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9559 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
9563 if (mips_opts.micromips)
9564 micromips_label_expr (&label_expr);
9566 label_expr.X_add_number = 8;
9567 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9568 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
9569 macro_build (NULL, "break", BRK_FMT, 7);
9570 if (mips_opts.micromips)
9571 micromips_add_label ();
9573 expr1.X_add_number = -1;
9575 load_register (AT, &expr1, dbl);
9576 if (mips_opts.micromips)
9577 micromips_label_expr (&label_expr);
9579 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
9580 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
9583 expr1.X_add_number = 1;
9584 load_register (AT, &expr1, dbl);
9585 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
9589 expr1.X_add_number = 0x80000000;
9590 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
9594 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
9595 /* We want to close the noreorder block as soon as possible, so
9596 that later insns are available for delay slot filling. */
9601 if (mips_opts.micromips)
9602 micromips_label_expr (&label_expr);
9604 label_expr.X_add_number = 8;
9605 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
9606 macro_build (NULL, "nop", "");
9608 /* We want to close the noreorder block as soon as possible, so
9609 that later insns are available for delay slot filling. */
9612 macro_build (NULL, "break", BRK_FMT, 6);
9614 if (mips_opts.micromips)
9615 micromips_add_label ();
9616 macro_build (NULL, s, MFHL_FMT, op[0]);
9655 if (imm_expr.X_add_number == 0)
9657 as_warn (_("divide by zero"));
9659 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
9661 macro_build (NULL, "break", BRK_FMT, 7);
9664 if (imm_expr.X_add_number == 1)
9666 if (strcmp (s2, "mflo") == 0)
9667 move_register (op[0], op[1]);
9669 move_register (op[0], ZERO);
9672 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
9674 if (strcmp (s2, "mflo") == 0)
9675 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
9677 move_register (op[0], ZERO);
9682 load_register (AT, &imm_expr, dbl);
9683 macro_build (NULL, s, "z,s,t", op[1], AT);
9684 macro_build (NULL, s2, MFHL_FMT, op[0]);
9706 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9707 macro_build (NULL, s, "z,s,t", op[1], op[2]);
9708 /* We want to close the noreorder block as soon as possible, so
9709 that later insns are available for delay slot filling. */
9714 if (mips_opts.micromips)
9715 micromips_label_expr (&label_expr);
9717 label_expr.X_add_number = 8;
9718 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9719 macro_build (NULL, s, "z,s,t", op[1], op[2]);
9721 /* We want to close the noreorder block as soon as possible, so
9722 that later insns are available for delay slot filling. */
9724 macro_build (NULL, "break", BRK_FMT, 7);
9725 if (mips_opts.micromips)
9726 micromips_add_label ();
9728 macro_build (NULL, s2, MFHL_FMT, op[0]);
9740 /* Load the address of a symbol into a register. If breg is not
9741 zero, we then add a base register to it. */
9744 if (dbl && HAVE_32BIT_GPRS)
9745 as_warn (_("dla used to load 32-bit register"));
9747 if (!dbl && HAVE_64BIT_OBJECTS)
9748 as_warn (_("la used to load 64-bit address"));
9750 if (small_offset_p (0, align, 16))
9752 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
9753 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9757 if (mips_opts.at && (op[0] == breg))
9765 if (offset_expr.X_op != O_symbol
9766 && offset_expr.X_op != O_constant)
9768 as_bad (_("expression too complex"));
9769 offset_expr.X_op = O_constant;
9772 if (offset_expr.X_op == O_constant)
9773 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
9774 else if (mips_pic == NO_PIC)
9776 /* If this is a reference to a GP relative symbol, we want
9777 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9779 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9780 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9781 If we have a constant, we need two instructions anyhow,
9782 so we may as well always use the latter form.
9784 With 64bit address space and a usable $at we want
9785 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9786 lui $at,<sym> (BFD_RELOC_HI16_S)
9787 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9788 daddiu $at,<sym> (BFD_RELOC_LO16)
9790 daddu $tempreg,$tempreg,$at
9792 If $at is already in use, we use a path which is suboptimal
9793 on superscalar processors.
9794 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9795 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9797 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9799 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9801 For GP relative symbols in 64bit address space we can use
9802 the same sequence as in 32bit address space. */
9803 if (HAVE_64BIT_SYMBOLS)
9805 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9806 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9808 relax_start (offset_expr.X_add_symbol);
9809 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9810 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9814 if (used_at == 0 && mips_opts.at)
9816 macro_build (&offset_expr, "lui", LUI_FMT,
9817 tempreg, BFD_RELOC_MIPS_HIGHEST);
9818 macro_build (&offset_expr, "lui", LUI_FMT,
9819 AT, BFD_RELOC_HI16_S);
9820 macro_build (&offset_expr, "daddiu", "t,r,j",
9821 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9822 macro_build (&offset_expr, "daddiu", "t,r,j",
9823 AT, AT, BFD_RELOC_LO16);
9824 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
9825 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
9830 macro_build (&offset_expr, "lui", LUI_FMT,
9831 tempreg, BFD_RELOC_MIPS_HIGHEST);
9832 macro_build (&offset_expr, "daddiu", "t,r,j",
9833 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9834 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9835 macro_build (&offset_expr, "daddiu", "t,r,j",
9836 tempreg, tempreg, BFD_RELOC_HI16_S);
9837 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9838 macro_build (&offset_expr, "daddiu", "t,r,j",
9839 tempreg, tempreg, BFD_RELOC_LO16);
9842 if (mips_relax.sequence)
9847 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9848 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9850 relax_start (offset_expr.X_add_symbol);
9851 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9852 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9855 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9856 as_bad (_("offset too large"));
9857 macro_build_lui (&offset_expr, tempreg);
9858 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9859 tempreg, tempreg, BFD_RELOC_LO16);
9860 if (mips_relax.sequence)
9864 else if (!mips_big_got && !HAVE_NEWABI)
9866 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9868 /* If this is a reference to an external symbol, and there
9869 is no constant, we want
9870 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9871 or for lca or if tempreg is PIC_CALL_REG
9872 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9873 For a local symbol, we want
9874 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9876 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9878 If we have a small constant, and this is a reference to
9879 an external symbol, we want
9880 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9882 addiu $tempreg,$tempreg,<constant>
9883 For a local symbol, we want the same instruction
9884 sequence, but we output a BFD_RELOC_LO16 reloc on the
9887 If we have a large constant, and this is a reference to
9888 an external symbol, we want
9889 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9890 lui $at,<hiconstant>
9891 addiu $at,$at,<loconstant>
9892 addu $tempreg,$tempreg,$at
9893 For a local symbol, we want the same instruction
9894 sequence, but we output a BFD_RELOC_LO16 reloc on the
9898 if (offset_expr.X_add_number == 0)
9900 if (mips_pic == SVR4_PIC
9902 && (call || tempreg == PIC_CALL_REG))
9903 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9905 relax_start (offset_expr.X_add_symbol);
9906 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9907 lw_reloc_type, mips_gp_register);
9910 /* We're going to put in an addu instruction using
9911 tempreg, so we may as well insert the nop right
9916 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9917 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
9919 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9920 tempreg, tempreg, BFD_RELOC_LO16);
9922 /* FIXME: If breg == 0, and the next instruction uses
9923 $tempreg, then if this variant case is used an extra
9924 nop will be generated. */
9926 else if (offset_expr.X_add_number >= -0x8000
9927 && offset_expr.X_add_number < 0x8000)
9929 load_got_offset (tempreg, &offset_expr);
9931 add_got_offset (tempreg, &offset_expr);
9935 expr1.X_add_number = offset_expr.X_add_number;
9936 offset_expr.X_add_number =
9937 SEXT_16BIT (offset_expr.X_add_number);
9938 load_got_offset (tempreg, &offset_expr);
9939 offset_expr.X_add_number = expr1.X_add_number;
9940 /* If we are going to add in a base register, and the
9941 target register and the base register are the same,
9942 then we are using AT as a temporary register. Since
9943 we want to load the constant into AT, we add our
9944 current AT (from the global offset table) and the
9945 register into the register now, and pretend we were
9946 not using a base register. */
9950 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9955 add_got_offset_hilo (tempreg, &offset_expr, AT);
9959 else if (!mips_big_got && HAVE_NEWABI)
9961 int add_breg_early = 0;
9963 /* If this is a reference to an external, and there is no
9964 constant, or local symbol (*), with or without a
9966 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9967 or for lca or if tempreg is PIC_CALL_REG
9968 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9970 If we have a small constant, and this is a reference to
9971 an external symbol, we want
9972 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9973 addiu $tempreg,$tempreg,<constant>
9975 If we have a large constant, and this is a reference to
9976 an external symbol, we want
9977 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9978 lui $at,<hiconstant>
9979 addiu $at,$at,<loconstant>
9980 addu $tempreg,$tempreg,$at
9982 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9983 local symbols, even though it introduces an additional
9986 if (offset_expr.X_add_number)
9988 expr1.X_add_number = offset_expr.X_add_number;
9989 offset_expr.X_add_number = 0;
9991 relax_start (offset_expr.X_add_symbol);
9992 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9993 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9995 if (expr1.X_add_number >= -0x8000
9996 && expr1.X_add_number < 0x8000)
9998 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9999 tempreg, tempreg, BFD_RELOC_LO16);
10001 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10005 /* If we are going to add in a base register, and the
10006 target register and the base register are the same,
10007 then we are using AT as a temporary register. Since
10008 we want to load the constant into AT, we add our
10009 current AT (from the global offset table) and the
10010 register into the register now, and pretend we were
10011 not using a base register. */
10016 gas_assert (tempreg == AT);
10017 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10020 add_breg_early = 1;
10023 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10024 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10030 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10033 offset_expr.X_add_number = expr1.X_add_number;
10035 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10036 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10037 if (add_breg_early)
10039 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10040 op[0], tempreg, breg);
10046 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10048 relax_start (offset_expr.X_add_symbol);
10049 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10050 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10052 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10053 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10058 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10059 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10062 else if (mips_big_got && !HAVE_NEWABI)
10065 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10066 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10067 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10069 /* This is the large GOT case. If this is a reference to an
10070 external symbol, and there is no constant, we want
10071 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10072 addu $tempreg,$tempreg,$gp
10073 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10074 or for lca or if tempreg is PIC_CALL_REG
10075 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10076 addu $tempreg,$tempreg,$gp
10077 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10078 For a local symbol, we want
10079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10081 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10083 If we have a small constant, and this is a reference to
10084 an external symbol, we want
10085 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10086 addu $tempreg,$tempreg,$gp
10087 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10089 addiu $tempreg,$tempreg,<constant>
10090 For a local symbol, we want
10091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10093 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10095 If we have a large constant, and this is a reference to
10096 an external symbol, we want
10097 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10098 addu $tempreg,$tempreg,$gp
10099 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10100 lui $at,<hiconstant>
10101 addiu $at,$at,<loconstant>
10102 addu $tempreg,$tempreg,$at
10103 For a local symbol, we want
10104 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10105 lui $at,<hiconstant>
10106 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10107 addu $tempreg,$tempreg,$at
10110 expr1.X_add_number = offset_expr.X_add_number;
10111 offset_expr.X_add_number = 0;
10112 relax_start (offset_expr.X_add_symbol);
10113 gpdelay = reg_needs_delay (mips_gp_register);
10114 if (expr1.X_add_number == 0 && breg == 0
10115 && (call || tempreg == PIC_CALL_REG))
10117 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10118 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10120 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10122 tempreg, tempreg, mips_gp_register);
10123 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10124 tempreg, lw_reloc_type, tempreg);
10125 if (expr1.X_add_number == 0)
10129 /* We're going to put in an addu instruction using
10130 tempreg, so we may as well insert the nop right
10135 else if (expr1.X_add_number >= -0x8000
10136 && expr1.X_add_number < 0x8000)
10139 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10140 tempreg, tempreg, BFD_RELOC_LO16);
10146 /* If we are going to add in a base register, and the
10147 target register and the base register are the same,
10148 then we are using AT as a temporary register. Since
10149 we want to load the constant into AT, we add our
10150 current AT (from the global offset table) and the
10151 register into the register now, and pretend we were
10152 not using a base register. */
10157 gas_assert (tempreg == AT);
10159 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10164 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10165 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10169 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10174 /* This is needed because this instruction uses $gp, but
10175 the first instruction on the main stream does not. */
10176 macro_build (NULL, "nop", "");
10179 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10180 local_reloc_type, mips_gp_register);
10181 if (expr1.X_add_number >= -0x8000
10182 && expr1.X_add_number < 0x8000)
10185 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10186 tempreg, tempreg, BFD_RELOC_LO16);
10187 /* FIXME: If add_number is 0, and there was no base
10188 register, the external symbol case ended with a load,
10189 so if the symbol turns out to not be external, and
10190 the next instruction uses tempreg, an unnecessary nop
10191 will be inserted. */
10197 /* We must add in the base register now, as in the
10198 external symbol case. */
10199 gas_assert (tempreg == AT);
10201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10204 /* We set breg to 0 because we have arranged to add
10205 it in in both cases. */
10209 macro_build_lui (&expr1, AT);
10210 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10211 AT, AT, BFD_RELOC_LO16);
10212 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10213 tempreg, tempreg, AT);
10218 else if (mips_big_got && HAVE_NEWABI)
10220 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10221 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10222 int add_breg_early = 0;
10224 /* This is the large GOT case. If this is a reference to an
10225 external symbol, and there is no constant, we want
10226 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10227 add $tempreg,$tempreg,$gp
10228 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10229 or for lca or if tempreg is PIC_CALL_REG
10230 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10231 add $tempreg,$tempreg,$gp
10232 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10234 If we have a small constant, and this is a reference to
10235 an external symbol, we want
10236 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10237 add $tempreg,$tempreg,$gp
10238 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10239 addi $tempreg,$tempreg,<constant>
10241 If we have a large constant, and this is a reference to
10242 an external symbol, we want
10243 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10244 addu $tempreg,$tempreg,$gp
10245 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10246 lui $at,<hiconstant>
10247 addi $at,$at,<loconstant>
10248 add $tempreg,$tempreg,$at
10250 If we have NewABI, and we know it's a local symbol, we want
10251 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10252 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10253 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10255 relax_start (offset_expr.X_add_symbol);
10257 expr1.X_add_number = offset_expr.X_add_number;
10258 offset_expr.X_add_number = 0;
10260 if (expr1.X_add_number == 0 && breg == 0
10261 && (call || tempreg == PIC_CALL_REG))
10263 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10264 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10266 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10267 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10268 tempreg, tempreg, mips_gp_register);
10269 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10270 tempreg, lw_reloc_type, tempreg);
10272 if (expr1.X_add_number == 0)
10274 else if (expr1.X_add_number >= -0x8000
10275 && expr1.X_add_number < 0x8000)
10277 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10278 tempreg, tempreg, BFD_RELOC_LO16);
10280 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10284 /* If we are going to add in a base register, and the
10285 target register and the base register are the same,
10286 then we are using AT as a temporary register. Since
10287 we want to load the constant into AT, we add our
10288 current AT (from the global offset table) and the
10289 register into the register now, and pretend we were
10290 not using a base register. */
10295 gas_assert (tempreg == AT);
10296 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10299 add_breg_early = 1;
10302 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10303 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10308 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10311 offset_expr.X_add_number = expr1.X_add_number;
10312 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10313 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10314 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10315 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10316 if (add_breg_early)
10318 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10319 op[0], tempreg, breg);
10329 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10333 gas_assert (!mips_opts.micromips);
10334 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10338 gas_assert (!mips_opts.micromips);
10339 macro_build (NULL, "c2", "C", 0x02);
10343 gas_assert (!mips_opts.micromips);
10344 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10348 gas_assert (!mips_opts.micromips);
10349 macro_build (NULL, "c2", "C", 3);
10353 gas_assert (!mips_opts.micromips);
10354 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
10358 /* The j instruction may not be used in PIC code, since it
10359 requires an absolute address. We convert it to a b
10361 if (mips_pic == NO_PIC)
10362 macro_build (&offset_expr, "j", "a");
10364 macro_build (&offset_expr, "b", "p");
10367 /* The jal instructions must be handled as macros because when
10368 generating PIC code they expand to multi-instruction
10369 sequences. Normally they are simple instructions. */
10373 /* Fall through. */
10375 gas_assert (mips_opts.micromips);
10376 if (mips_opts.insn32)
10378 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
10386 /* Fall through. */
10389 if (mips_pic == NO_PIC)
10391 s = jals ? "jalrs" : "jalr";
10392 if (mips_opts.micromips
10393 && !mips_opts.insn32
10395 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10396 macro_build (NULL, s, "mj", op[1]);
10398 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
10402 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
10403 && mips_cprestore_offset >= 0);
10405 if (op[1] != PIC_CALL_REG)
10406 as_warn (_("MIPS PIC call to register other than $25"));
10408 s = ((mips_opts.micromips
10409 && !mips_opts.insn32
10410 && (!mips_opts.noreorder || cprestore))
10411 ? "jalrs" : "jalr");
10412 if (mips_opts.micromips
10413 && !mips_opts.insn32
10415 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10416 macro_build (NULL, s, "mj", op[1]);
10418 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
10419 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
10421 if (mips_cprestore_offset < 0)
10422 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10425 if (!mips_frame_reg_valid)
10427 as_warn (_("no .frame pseudo-op used in PIC code"));
10428 /* Quiet this warning. */
10429 mips_frame_reg_valid = 1;
10431 if (!mips_cprestore_valid)
10433 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10434 /* Quiet this warning. */
10435 mips_cprestore_valid = 1;
10437 if (mips_opts.noreorder)
10438 macro_build (NULL, "nop", "");
10439 expr1.X_add_number = mips_cprestore_offset;
10440 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
10443 HAVE_64BIT_ADDRESSES);
10451 gas_assert (mips_opts.micromips);
10452 if (mips_opts.insn32)
10454 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
10458 /* Fall through. */
10460 if (mips_pic == NO_PIC)
10461 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
10462 else if (mips_pic == SVR4_PIC)
10464 /* If this is a reference to an external symbol, and we are
10465 using a small GOT, we want
10466 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10470 lw $gp,cprestore($sp)
10471 The cprestore value is set using the .cprestore
10472 pseudo-op. If we are using a big GOT, we want
10473 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10475 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10479 lw $gp,cprestore($sp)
10480 If the symbol is not external, we want
10481 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10483 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10486 lw $gp,cprestore($sp)
10488 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10489 sequences above, minus nops, unless the symbol is local,
10490 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10496 relax_start (offset_expr.X_add_symbol);
10497 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10498 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
10501 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10502 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
10508 relax_start (offset_expr.X_add_symbol);
10509 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
10510 BFD_RELOC_MIPS_CALL_HI16);
10511 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10512 PIC_CALL_REG, mips_gp_register);
10513 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10514 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10517 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10518 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
10520 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10521 PIC_CALL_REG, PIC_CALL_REG,
10522 BFD_RELOC_MIPS_GOT_OFST);
10526 macro_build_jalr (&offset_expr, 0);
10530 relax_start (offset_expr.X_add_symbol);
10533 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10534 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
10543 gpdelay = reg_needs_delay (mips_gp_register);
10544 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
10545 BFD_RELOC_MIPS_CALL_HI16);
10546 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10547 PIC_CALL_REG, mips_gp_register);
10548 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10549 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10554 macro_build (NULL, "nop", "");
10556 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10557 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
10560 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10561 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
10563 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
10565 if (mips_cprestore_offset < 0)
10566 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10569 if (!mips_frame_reg_valid)
10571 as_warn (_("no .frame pseudo-op used in PIC code"));
10572 /* Quiet this warning. */
10573 mips_frame_reg_valid = 1;
10575 if (!mips_cprestore_valid)
10577 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10578 /* Quiet this warning. */
10579 mips_cprestore_valid = 1;
10581 if (mips_opts.noreorder)
10582 macro_build (NULL, "nop", "");
10583 expr1.X_add_number = mips_cprestore_offset;
10584 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
10587 HAVE_64BIT_ADDRESSES);
10591 else if (mips_pic == VXWORKS_PIC)
10592 as_bad (_("non-PIC jump used in PIC library"));
10699 gas_assert (!mips_opts.micromips);
10702 /* Itbl support may require additional care here. */
10708 /* Itbl support may require additional care here. */
10714 offbits = (mips_opts.micromips ? 12 : 16);
10715 /* Itbl support may require additional care here. */
10719 gas_assert (!mips_opts.micromips);
10722 /* Itbl support may require additional care here. */
10728 offbits = (mips_opts.micromips ? 12 : 16);
10733 offbits = (mips_opts.micromips ? 12 : 16);
10738 /* Itbl support may require additional care here. */
10744 offbits = (mips_opts.micromips ? 12 : 16);
10745 /* Itbl support may require additional care here. */
10751 /* Itbl support may require additional care here. */
10757 /* Itbl support may require additional care here. */
10763 offbits = (mips_opts.micromips ? 12 : 16);
10768 offbits = (mips_opts.micromips ? 12 : 16);
10773 offbits = (mips_opts.micromips ? 12 : 16);
10778 offbits = (mips_opts.micromips ? 12 : 16);
10783 offbits = (mips_opts.micromips ? 12 : 16);
10786 gas_assert (mips_opts.micromips);
10793 gas_assert (mips_opts.micromips);
10800 gas_assert (mips_opts.micromips);
10806 gas_assert (mips_opts.micromips);
10813 /* We don't want to use $0 as tempreg. */
10814 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
10817 tempreg = op[0] + lp;
10833 gas_assert (!mips_opts.micromips);
10836 /* Itbl support may require additional care here. */
10842 /* Itbl support may require additional care here. */
10848 offbits = (mips_opts.micromips ? 12 : 16);
10849 /* Itbl support may require additional care here. */
10853 gas_assert (!mips_opts.micromips);
10856 /* Itbl support may require additional care here. */
10862 offbits = (mips_opts.micromips ? 12 : 16);
10867 offbits = (mips_opts.micromips ? 12 : 16);
10872 offbits = (mips_opts.micromips ? 12 : 16);
10877 offbits = (mips_opts.micromips ? 12 : 16);
10881 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
10882 offbits = (mips_opts.micromips ? 12 : 16);
10891 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
10892 offbits = (mips_opts.micromips ? 12 : 16);
10903 /* Itbl support may require additional care here. */
10908 offbits = (mips_opts.micromips ? 12 : 16);
10909 /* Itbl support may require additional care here. */
10915 /* Itbl support may require additional care here. */
10919 gas_assert (!mips_opts.micromips);
10922 /* Itbl support may require additional care here. */
10928 offbits = (mips_opts.micromips ? 12 : 16);
10933 offbits = (mips_opts.micromips ? 12 : 16);
10936 gas_assert (mips_opts.micromips);
10942 gas_assert (mips_opts.micromips);
10948 gas_assert (mips_opts.micromips);
10954 gas_assert (mips_opts.micromips);
10963 if (small_offset_p (0, align, 16))
10965 /* The first case exists for M_LD_AB and M_SD_AB, which are
10966 macros for o32 but which should act like normal instructions
10969 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
10970 offset_reloc[1], offset_reloc[2], breg);
10971 else if (small_offset_p (0, align, offbits))
10974 macro_build (NULL, s, fmt, op[0], breg);
10976 macro_build (NULL, s, fmt, op[0],
10977 (int) offset_expr.X_add_number, breg);
10983 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10984 tempreg, breg, -1, offset_reloc[0],
10985 offset_reloc[1], offset_reloc[2]);
10987 macro_build (NULL, s, fmt, op[0], tempreg);
10989 macro_build (NULL, s, fmt, op[0], 0, tempreg);
10997 if (offset_expr.X_op != O_constant
10998 && offset_expr.X_op != O_symbol)
11000 as_bad (_("expression too complex"));
11001 offset_expr.X_op = O_constant;
11004 if (HAVE_32BIT_ADDRESSES
11005 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11009 sprintf_vma (value, offset_expr.X_add_number);
11010 as_bad (_("number (0x%s) larger than 32 bits"), value);
11013 /* A constant expression in PIC code can be handled just as it
11014 is in non PIC code. */
11015 if (offset_expr.X_op == O_constant)
11017 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11018 offbits == 0 ? 16 : offbits);
11019 offset_expr.X_add_number -= expr1.X_add_number;
11021 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11023 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11024 tempreg, tempreg, breg);
11027 if (offset_expr.X_add_number != 0)
11028 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
11029 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
11030 macro_build (NULL, s, fmt, op[0], tempreg);
11032 else if (offbits == 16)
11033 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11035 macro_build (NULL, s, fmt, op[0],
11036 (int) offset_expr.X_add_number, tempreg);
11038 else if (offbits != 16)
11040 /* The offset field is too narrow to be used for a low-part
11041 relocation, so load the whole address into the auxillary
11043 load_address (tempreg, &offset_expr, &used_at);
11045 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11046 tempreg, tempreg, breg);
11048 macro_build (NULL, s, fmt, op[0], tempreg);
11050 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11052 else if (mips_pic == NO_PIC)
11054 /* If this is a reference to a GP relative symbol, and there
11055 is no base register, we want
11056 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11057 Otherwise, if there is no base register, we want
11058 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11059 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11060 If we have a constant, we need two instructions anyhow,
11061 so we always use the latter form.
11063 If we have a base register, and this is a reference to a
11064 GP relative symbol, we want
11065 addu $tempreg,$breg,$gp
11066 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11068 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11069 addu $tempreg,$tempreg,$breg
11070 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11071 With a constant we always use the latter case.
11073 With 64bit address space and no base register and $at usable,
11075 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11076 lui $at,<sym> (BFD_RELOC_HI16_S)
11077 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11080 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11081 If we have a base register, we want
11082 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11083 lui $at,<sym> (BFD_RELOC_HI16_S)
11084 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11088 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11090 Without $at we can't generate the optimal path for superscalar
11091 processors here since this would require two temporary registers.
11092 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11093 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11095 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11097 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11098 If we have a base register, we want
11099 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11100 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11102 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11104 daddu $tempreg,$tempreg,$breg
11105 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11107 For GP relative symbols in 64bit address space we can use
11108 the same sequence as in 32bit address space. */
11109 if (HAVE_64BIT_SYMBOLS)
11111 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11112 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11114 relax_start (offset_expr.X_add_symbol);
11117 macro_build (&offset_expr, s, fmt, op[0],
11118 BFD_RELOC_GPREL16, mips_gp_register);
11122 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11123 tempreg, breg, mips_gp_register);
11124 macro_build (&offset_expr, s, fmt, op[0],
11125 BFD_RELOC_GPREL16, tempreg);
11130 if (used_at == 0 && mips_opts.at)
11132 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11133 BFD_RELOC_MIPS_HIGHEST);
11134 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11136 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11137 tempreg, BFD_RELOC_MIPS_HIGHER);
11139 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11140 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11141 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11142 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11148 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11149 BFD_RELOC_MIPS_HIGHEST);
11150 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11151 tempreg, BFD_RELOC_MIPS_HIGHER);
11152 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11153 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11154 tempreg, BFD_RELOC_HI16_S);
11155 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11157 macro_build (NULL, "daddu", "d,v,t",
11158 tempreg, tempreg, breg);
11159 macro_build (&offset_expr, s, fmt, op[0],
11160 BFD_RELOC_LO16, tempreg);
11163 if (mips_relax.sequence)
11170 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11171 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11173 relax_start (offset_expr.X_add_symbol);
11174 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11178 macro_build_lui (&offset_expr, tempreg);
11179 macro_build (&offset_expr, s, fmt, op[0],
11180 BFD_RELOC_LO16, tempreg);
11181 if (mips_relax.sequence)
11186 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11187 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11189 relax_start (offset_expr.X_add_symbol);
11190 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11191 tempreg, breg, mips_gp_register);
11192 macro_build (&offset_expr, s, fmt, op[0],
11193 BFD_RELOC_GPREL16, tempreg);
11196 macro_build_lui (&offset_expr, tempreg);
11197 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11198 tempreg, tempreg, breg);
11199 macro_build (&offset_expr, s, fmt, op[0],
11200 BFD_RELOC_LO16, tempreg);
11201 if (mips_relax.sequence)
11205 else if (!mips_big_got)
11207 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11209 /* If this is a reference to an external symbol, we want
11210 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11212 <op> op[0],0($tempreg)
11214 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11216 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11217 <op> op[0],0($tempreg)
11219 For NewABI, we want
11220 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11221 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11223 If there is a base register, we add it to $tempreg before
11224 the <op>. If there is a constant, we stick it in the
11225 <op> instruction. We don't handle constants larger than
11226 16 bits, because we have no way to load the upper 16 bits
11227 (actually, we could handle them for the subset of cases
11228 in which we are not using $at). */
11229 gas_assert (offset_expr.X_op == O_symbol);
11232 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11233 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11235 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11236 tempreg, tempreg, breg);
11237 macro_build (&offset_expr, s, fmt, op[0],
11238 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11241 expr1.X_add_number = offset_expr.X_add_number;
11242 offset_expr.X_add_number = 0;
11243 if (expr1.X_add_number < -0x8000
11244 || expr1.X_add_number >= 0x8000)
11245 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11246 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11247 lw_reloc_type, mips_gp_register);
11249 relax_start (offset_expr.X_add_symbol);
11251 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11252 tempreg, BFD_RELOC_LO16);
11255 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11256 tempreg, tempreg, breg);
11257 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11259 else if (mips_big_got && !HAVE_NEWABI)
11263 /* If this is a reference to an external symbol, we want
11264 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11265 addu $tempreg,$tempreg,$gp
11266 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11267 <op> op[0],0($tempreg)
11269 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11271 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11272 <op> op[0],0($tempreg)
11273 If there is a base register, we add it to $tempreg before
11274 the <op>. If there is a constant, we stick it in the
11275 <op> instruction. We don't handle constants larger than
11276 16 bits, because we have no way to load the upper 16 bits
11277 (actually, we could handle them for the subset of cases
11278 in which we are not using $at). */
11279 gas_assert (offset_expr.X_op == O_symbol);
11280 expr1.X_add_number = offset_expr.X_add_number;
11281 offset_expr.X_add_number = 0;
11282 if (expr1.X_add_number < -0x8000
11283 || expr1.X_add_number >= 0x8000)
11284 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11285 gpdelay = reg_needs_delay (mips_gp_register);
11286 relax_start (offset_expr.X_add_symbol);
11287 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11288 BFD_RELOC_MIPS_GOT_HI16);
11289 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11291 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11292 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11295 macro_build (NULL, "nop", "");
11296 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11297 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11299 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11300 tempreg, BFD_RELOC_LO16);
11304 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11305 tempreg, tempreg, breg);
11306 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11308 else if (mips_big_got && HAVE_NEWABI)
11310 /* If this is a reference to an external symbol, we want
11311 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11312 add $tempreg,$tempreg,$gp
11313 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11314 <op> op[0],<ofst>($tempreg)
11315 Otherwise, for local symbols, we want:
11316 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11317 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11318 gas_assert (offset_expr.X_op == O_symbol);
11319 expr1.X_add_number = offset_expr.X_add_number;
11320 offset_expr.X_add_number = 0;
11321 if (expr1.X_add_number < -0x8000
11322 || expr1.X_add_number >= 0x8000)
11323 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11324 relax_start (offset_expr.X_add_symbol);
11325 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11326 BFD_RELOC_MIPS_GOT_HI16);
11327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11329 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11330 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11332 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11333 tempreg, tempreg, breg);
11334 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11337 offset_expr.X_add_number = expr1.X_add_number;
11338 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11339 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11341 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11342 tempreg, tempreg, breg);
11343 macro_build (&offset_expr, s, fmt, op[0],
11344 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11353 gas_assert (mips_opts.micromips);
11354 gas_assert (mips_opts.insn32);
11355 start_noreorder ();
11356 macro_build (NULL, "jr", "s", RA);
11357 expr1.X_add_number = op[0] << 2;
11358 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11363 gas_assert (mips_opts.micromips);
11364 gas_assert (mips_opts.insn32);
11365 macro_build (NULL, "jr", "s", op[0]);
11366 if (mips_opts.noreorder)
11367 macro_build (NULL, "nop", "");
11372 load_register (op[0], &imm_expr, 0);
11376 load_register (op[0], &imm_expr, 1);
11380 if (imm_expr.X_op == O_constant)
11383 load_register (AT, &imm_expr, 0);
11384 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
11389 gas_assert (imm_expr.X_op == O_absent
11390 && offset_expr.X_op == O_symbol
11391 && strcmp (segment_name (S_GET_SEGMENT
11392 (offset_expr.X_add_symbol)),
11394 && offset_expr.X_add_number == 0);
11395 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
11396 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
11401 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11402 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11403 order 32 bits of the value and the low order 32 bits are either
11404 zero or in OFFSET_EXPR. */
11405 if (imm_expr.X_op == O_constant)
11407 if (HAVE_64BIT_GPRS)
11408 load_register (op[0], &imm_expr, 1);
11413 if (target_big_endian)
11425 load_register (hreg, &imm_expr, 0);
11428 if (offset_expr.X_op == O_absent)
11429 move_register (lreg, 0);
11432 gas_assert (offset_expr.X_op == O_constant);
11433 load_register (lreg, &offset_expr, 0);
11439 gas_assert (imm_expr.X_op == O_absent);
11441 /* We know that sym is in the .rdata section. First we get the
11442 upper 16 bits of the address. */
11443 if (mips_pic == NO_PIC)
11445 macro_build_lui (&offset_expr, AT);
11450 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11451 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11455 /* Now we load the register(s). */
11456 if (HAVE_64BIT_GPRS)
11459 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
11460 BFD_RELOC_LO16, AT);
11465 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
11466 BFD_RELOC_LO16, AT);
11469 /* FIXME: How in the world do we deal with the possible
11471 offset_expr.X_add_number += 4;
11472 macro_build (&offset_expr, "lw", "t,o(b)",
11473 op[0] + 1, BFD_RELOC_LO16, AT);
11479 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11480 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11481 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11482 the value and the low order 32 bits are either zero or in
11484 if (imm_expr.X_op == O_constant)
11487 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
11488 if (HAVE_64BIT_FPRS)
11490 gas_assert (HAVE_64BIT_GPRS);
11491 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
11495 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
11496 if (offset_expr.X_op == O_absent)
11497 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
11500 gas_assert (offset_expr.X_op == O_constant);
11501 load_register (AT, &offset_expr, 0);
11502 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
11508 gas_assert (imm_expr.X_op == O_absent
11509 && offset_expr.X_op == O_symbol
11510 && offset_expr.X_add_number == 0);
11511 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
11512 if (strcmp (s, ".lit8") == 0)
11514 op[2] = mips_gp_register;
11515 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
11516 offset_reloc[1] = BFD_RELOC_UNUSED;
11517 offset_reloc[2] = BFD_RELOC_UNUSED;
11521 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
11523 if (mips_pic != NO_PIC)
11524 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11525 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11528 /* FIXME: This won't work for a 64 bit address. */
11529 macro_build_lui (&offset_expr, AT);
11533 offset_reloc[0] = BFD_RELOC_LO16;
11534 offset_reloc[1] = BFD_RELOC_UNUSED;
11535 offset_reloc[2] = BFD_RELOC_UNUSED;
11542 * The MIPS assembler seems to check for X_add_number not
11543 * being double aligned and generating:
11544 * lui at,%hi(foo+1)
11546 * addiu at,at,%lo(foo+1)
11549 * But, the resulting address is the same after relocation so why
11550 * generate the extra instruction?
11552 /* Itbl support may require additional care here. */
11555 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
11564 gas_assert (!mips_opts.micromips);
11565 /* Itbl support may require additional care here. */
11568 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
11588 if (HAVE_64BIT_GPRS)
11598 if (HAVE_64BIT_GPRS)
11606 /* Even on a big endian machine $fn comes before $fn+1. We have
11607 to adjust when loading from memory. We set coproc if we must
11608 load $fn+1 first. */
11609 /* Itbl support may require additional care here. */
11610 if (!target_big_endian)
11614 if (small_offset_p (0, align, 16))
11617 if (!small_offset_p (4, align, 16))
11619 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
11620 -1, offset_reloc[0], offset_reloc[1],
11622 expr1.X_add_number = 0;
11626 offset_reloc[0] = BFD_RELOC_LO16;
11627 offset_reloc[1] = BFD_RELOC_UNUSED;
11628 offset_reloc[2] = BFD_RELOC_UNUSED;
11630 if (strcmp (s, "lw") == 0 && op[0] == breg)
11632 ep->X_add_number += 4;
11633 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
11634 offset_reloc[1], offset_reloc[2], breg);
11635 ep->X_add_number -= 4;
11636 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
11637 offset_reloc[1], offset_reloc[2], breg);
11641 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
11642 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11644 ep->X_add_number += 4;
11645 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
11646 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11652 if (offset_expr.X_op != O_symbol
11653 && offset_expr.X_op != O_constant)
11655 as_bad (_("expression too complex"));
11656 offset_expr.X_op = O_constant;
11659 if (HAVE_32BIT_ADDRESSES
11660 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11664 sprintf_vma (value, offset_expr.X_add_number);
11665 as_bad (_("number (0x%s) larger than 32 bits"), value);
11668 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
11670 /* If this is a reference to a GP relative symbol, we want
11671 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11672 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11673 If we have a base register, we use this
11675 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11676 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11677 If this is not a GP relative symbol, we want
11678 lui $at,<sym> (BFD_RELOC_HI16_S)
11679 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11680 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11681 If there is a base register, we add it to $at after the
11682 lui instruction. If there is a constant, we always use
11684 if (offset_expr.X_op == O_symbol
11685 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11686 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11688 relax_start (offset_expr.X_add_symbol);
11691 tempreg = mips_gp_register;
11695 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11696 AT, breg, mips_gp_register);
11701 /* Itbl support may require additional care here. */
11702 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11703 BFD_RELOC_GPREL16, tempreg);
11704 offset_expr.X_add_number += 4;
11706 /* Set mips_optimize to 2 to avoid inserting an
11708 hold_mips_optimize = mips_optimize;
11710 /* Itbl support may require additional care here. */
11711 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11712 BFD_RELOC_GPREL16, tempreg);
11713 mips_optimize = hold_mips_optimize;
11717 offset_expr.X_add_number -= 4;
11720 if (offset_high_part (offset_expr.X_add_number, 16)
11721 != offset_high_part (offset_expr.X_add_number + 4, 16))
11723 load_address (AT, &offset_expr, &used_at);
11724 offset_expr.X_op = O_constant;
11725 offset_expr.X_add_number = 0;
11728 macro_build_lui (&offset_expr, AT);
11730 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11731 /* Itbl support may require additional care here. */
11732 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11733 BFD_RELOC_LO16, AT);
11734 /* FIXME: How do we handle overflow here? */
11735 offset_expr.X_add_number += 4;
11736 /* Itbl support may require additional care here. */
11737 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11738 BFD_RELOC_LO16, AT);
11739 if (mips_relax.sequence)
11742 else if (!mips_big_got)
11744 /* If this is a reference to an external symbol, we want
11745 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11748 <op> op[0]+1,4($at)
11750 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11752 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11753 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11754 If there is a base register we add it to $at before the
11755 lwc1 instructions. If there is a constant we include it
11756 in the lwc1 instructions. */
11758 expr1.X_add_number = offset_expr.X_add_number;
11759 if (expr1.X_add_number < -0x8000
11760 || expr1.X_add_number >= 0x8000 - 4)
11761 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11762 load_got_offset (AT, &offset_expr);
11765 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11767 /* Set mips_optimize to 2 to avoid inserting an undesired
11769 hold_mips_optimize = mips_optimize;
11772 /* Itbl support may require additional care here. */
11773 relax_start (offset_expr.X_add_symbol);
11774 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
11775 BFD_RELOC_LO16, AT);
11776 expr1.X_add_number += 4;
11777 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
11778 BFD_RELOC_LO16, AT);
11780 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11781 BFD_RELOC_LO16, AT);
11782 offset_expr.X_add_number += 4;
11783 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11784 BFD_RELOC_LO16, AT);
11787 mips_optimize = hold_mips_optimize;
11789 else if (mips_big_got)
11793 /* If this is a reference to an external symbol, we want
11794 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11796 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11799 <op> op[0]+1,4($at)
11801 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11803 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11804 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11805 If there is a base register we add it to $at before the
11806 lwc1 instructions. If there is a constant we include it
11807 in the lwc1 instructions. */
11809 expr1.X_add_number = offset_expr.X_add_number;
11810 offset_expr.X_add_number = 0;
11811 if (expr1.X_add_number < -0x8000
11812 || expr1.X_add_number >= 0x8000 - 4)
11813 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11814 gpdelay = reg_needs_delay (mips_gp_register);
11815 relax_start (offset_expr.X_add_symbol);
11816 macro_build (&offset_expr, "lui", LUI_FMT,
11817 AT, BFD_RELOC_MIPS_GOT_HI16);
11818 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11819 AT, AT, mips_gp_register);
11820 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11821 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
11824 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11825 /* Itbl support may require additional care here. */
11826 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
11827 BFD_RELOC_LO16, AT);
11828 expr1.X_add_number += 4;
11830 /* Set mips_optimize to 2 to avoid inserting an undesired
11832 hold_mips_optimize = mips_optimize;
11834 /* Itbl support may require additional care here. */
11835 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
11836 BFD_RELOC_LO16, AT);
11837 mips_optimize = hold_mips_optimize;
11838 expr1.X_add_number -= 4;
11841 offset_expr.X_add_number = expr1.X_add_number;
11843 macro_build (NULL, "nop", "");
11844 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11845 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11848 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11849 /* Itbl support may require additional care here. */
11850 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11851 BFD_RELOC_LO16, AT);
11852 offset_expr.X_add_number += 4;
11854 /* Set mips_optimize to 2 to avoid inserting an undesired
11856 hold_mips_optimize = mips_optimize;
11858 /* Itbl support may require additional care here. */
11859 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11860 BFD_RELOC_LO16, AT);
11861 mips_optimize = hold_mips_optimize;
11880 /* New code added to support COPZ instructions.
11881 This code builds table entries out of the macros in mip_opcodes.
11882 R4000 uses interlocks to handle coproc delays.
11883 Other chips (like the R3000) require nops to be inserted for delays.
11885 FIXME: Currently, we require that the user handle delays.
11886 In order to fill delay slots for non-interlocked chips,
11887 we must have a way to specify delays based on the coprocessor.
11888 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11889 What are the side-effects of the cop instruction?
11890 What cache support might we have and what are its effects?
11891 Both coprocessor & memory require delays. how long???
11892 What registers are read/set/modified?
11894 If an itbl is provided to interpret cop instructions,
11895 this knowledge can be encoded in the itbl spec. */
11909 gas_assert (!mips_opts.micromips);
11910 /* For now we just do C (same as Cz). The parameter will be
11911 stored in insn_opcode by mips_ip. */
11912 macro_build (NULL, s, "C", (int) ip->insn_opcode);
11916 move_register (op[0], op[1]);
11920 gas_assert (mips_opts.micromips);
11921 gas_assert (mips_opts.insn32);
11922 move_register (micromips_to_32_reg_h_map1[op[0]],
11923 micromips_to_32_reg_m_map[op[1]]);
11924 move_register (micromips_to_32_reg_h_map2[op[0]],
11925 micromips_to_32_reg_n_map[op[2]]);
11931 if (mips_opts.arch == CPU_R5900)
11932 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
11936 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
11937 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11944 /* The MIPS assembler some times generates shifts and adds. I'm
11945 not trying to be that fancy. GCC should do this for us
11948 load_register (AT, &imm_expr, dbl);
11949 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
11950 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11963 start_noreorder ();
11966 load_register (AT, &imm_expr, dbl);
11967 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
11968 op[1], imm ? AT : op[2]);
11969 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11970 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
11971 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11973 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
11976 if (mips_opts.micromips)
11977 micromips_label_expr (&label_expr);
11979 label_expr.X_add_number = 8;
11980 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
11981 macro_build (NULL, "nop", "");
11982 macro_build (NULL, "break", BRK_FMT, 6);
11983 if (mips_opts.micromips)
11984 micromips_add_label ();
11987 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12000 start_noreorder ();
12003 load_register (AT, &imm_expr, dbl);
12004 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
12005 op[1], imm ? AT : op[2]);
12006 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12007 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12009 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
12012 if (mips_opts.micromips)
12013 micromips_label_expr (&label_expr);
12015 label_expr.X_add_number = 8;
12016 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
12017 macro_build (NULL, "nop", "");
12018 macro_build (NULL, "break", BRK_FMT, 6);
12019 if (mips_opts.micromips)
12020 micromips_add_label ();
12026 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12028 if (op[0] == op[1])
12035 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12036 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12040 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12041 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12042 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12043 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12047 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12049 if (op[0] == op[1])
12056 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12057 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12061 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12062 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12063 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12064 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12073 rot = imm_expr.X_add_number & 0x3f;
12074 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12076 rot = (64 - rot) & 0x3f;
12078 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12080 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12085 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12088 l = (rot < 0x20) ? "dsll" : "dsll32";
12089 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12092 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12093 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12094 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12102 rot = imm_expr.X_add_number & 0x1f;
12103 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12105 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12106 (32 - rot) & 0x1f);
12111 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12115 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12116 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12117 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12122 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12124 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12128 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12129 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12130 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12131 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12135 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12137 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12141 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12142 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12143 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12144 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12153 rot = imm_expr.X_add_number & 0x3f;
12154 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12157 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12159 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12164 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12167 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12168 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12171 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12172 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12173 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12181 rot = imm_expr.X_add_number & 0x1f;
12182 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12184 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12189 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12193 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12194 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12195 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12201 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12202 else if (op[2] == 0)
12203 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12206 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12207 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12212 if (imm_expr.X_add_number == 0)
12214 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12219 as_warn (_("instruction %s: result is always false"),
12220 ip->insn_mo->name);
12221 move_register (op[0], 0);
12224 if (CPU_HAS_SEQ (mips_opts.arch)
12225 && -512 <= imm_expr.X_add_number
12226 && imm_expr.X_add_number < 512)
12228 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12229 (int) imm_expr.X_add_number);
12232 if (imm_expr.X_add_number >= 0
12233 && imm_expr.X_add_number < 0x10000)
12234 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12235 else if (imm_expr.X_add_number > -0x8000
12236 && imm_expr.X_add_number < 0)
12238 imm_expr.X_add_number = -imm_expr.X_add_number;
12239 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
12240 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12242 else if (CPU_HAS_SEQ (mips_opts.arch))
12245 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12246 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12251 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12252 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12255 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12258 case M_SGE: /* X >= Y <==> not (X < Y) */
12264 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12265 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12268 case M_SGE_I: /* X >= I <==> not (X < I) */
12270 if (imm_expr.X_add_number >= -0x8000
12271 && imm_expr.X_add_number < 0x8000)
12272 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12273 op[0], op[1], BFD_RELOC_LO16);
12276 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12277 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12281 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12284 case M_SGT: /* X > Y <==> Y < X */
12290 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12293 case M_SGT_I: /* X > I <==> I < X */
12300 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12301 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12304 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12310 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12311 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12314 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12321 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12322 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12323 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12327 if (imm_expr.X_add_number >= -0x8000
12328 && imm_expr.X_add_number < 0x8000)
12330 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12335 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12336 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
12340 if (imm_expr.X_add_number >= -0x8000
12341 && imm_expr.X_add_number < 0x8000)
12343 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
12348 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12349 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
12354 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12355 else if (op[2] == 0)
12356 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12359 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12360 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12365 if (imm_expr.X_add_number == 0)
12367 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12372 as_warn (_("instruction %s: result is always true"),
12373 ip->insn_mo->name);
12374 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
12375 op[0], 0, BFD_RELOC_LO16);
12378 if (CPU_HAS_SEQ (mips_opts.arch)
12379 && -512 <= imm_expr.X_add_number
12380 && imm_expr.X_add_number < 512)
12382 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
12383 (int) imm_expr.X_add_number);
12386 if (imm_expr.X_add_number >= 0
12387 && imm_expr.X_add_number < 0x10000)
12389 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
12392 else if (imm_expr.X_add_number > -0x8000
12393 && imm_expr.X_add_number < 0)
12395 imm_expr.X_add_number = -imm_expr.X_add_number;
12396 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
12397 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12399 else if (CPU_HAS_SEQ (mips_opts.arch))
12402 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12403 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
12408 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12409 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12412 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12427 if (!mips_opts.micromips)
12429 if (imm_expr.X_add_number > -0x200
12430 && imm_expr.X_add_number <= 0x200)
12432 macro_build (NULL, s, "t,r,.", op[0], op[1],
12433 (int) -imm_expr.X_add_number);
12442 if (imm_expr.X_add_number > -0x8000
12443 && imm_expr.X_add_number <= 0x8000)
12445 imm_expr.X_add_number = -imm_expr.X_add_number;
12446 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12451 load_register (AT, &imm_expr, dbl);
12452 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
12474 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12475 macro_build (NULL, s, "s,t", op[0], AT);
12480 gas_assert (!mips_opts.micromips);
12481 gas_assert (mips_opts.isa == ISA_MIPS1);
12485 * Is the double cfc1 instruction a bug in the mips assembler;
12486 * or is there a reason for it?
12488 start_noreorder ();
12489 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12490 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12491 macro_build (NULL, "nop", "");
12492 expr1.X_add_number = 3;
12493 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
12494 expr1.X_add_number = 2;
12495 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
12496 macro_build (NULL, "ctc1", "t,G", AT, RA);
12497 macro_build (NULL, "nop", "");
12498 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
12500 macro_build (NULL, "ctc1", "t,G", op[2], RA);
12501 macro_build (NULL, "nop", "");
12518 offbits = (mips_opts.micromips ? 12 : 16);
12524 offbits = (mips_opts.micromips ? 12 : 16);
12536 offbits = (mips_opts.micromips ? 12 : 16);
12543 offbits = (mips_opts.micromips ? 12 : 16);
12549 large_offset = !small_offset_p (off, align, offbits);
12551 expr1.X_add_number = 0;
12556 if (small_offset_p (0, align, 16))
12557 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
12558 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
12561 load_address (tempreg, ep, &used_at);
12563 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12564 tempreg, tempreg, breg);
12566 offset_reloc[0] = BFD_RELOC_LO16;
12567 offset_reloc[1] = BFD_RELOC_UNUSED;
12568 offset_reloc[2] = BFD_RELOC_UNUSED;
12573 else if (!ust && op[0] == breg)
12584 if (!target_big_endian)
12585 ep->X_add_number += off;
12587 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
12589 macro_build (ep, s, "t,o(b)", tempreg, -1,
12590 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12592 if (!target_big_endian)
12593 ep->X_add_number -= off;
12595 ep->X_add_number += off;
12597 macro_build (NULL, s2, "t,~(b)",
12598 tempreg, (int) ep->X_add_number, breg);
12600 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12601 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12603 /* If necessary, move the result in tempreg to the final destination. */
12604 if (!ust && op[0] != tempreg)
12606 /* Protect second load's delay slot. */
12608 move_register (op[0], tempreg);
12614 if (target_big_endian == ust)
12615 ep->X_add_number += off;
12616 tempreg = ust || large_offset ? op[0] : AT;
12617 macro_build (ep, s, "t,o(b)", tempreg, -1,
12618 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12620 /* For halfword transfers we need a temporary register to shuffle
12621 bytes. Unfortunately for M_USH_A we have none available before
12622 the next store as AT holds the base address. We deal with this
12623 case by clobbering TREG and then restoring it as with ULH. */
12624 tempreg = ust == large_offset ? op[0] : AT;
12626 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
12628 if (target_big_endian == ust)
12629 ep->X_add_number -= off;
12631 ep->X_add_number += off;
12632 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12633 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12635 /* For M_USH_A re-retrieve the LSB. */
12636 if (ust && large_offset)
12638 if (target_big_endian)
12639 ep->X_add_number += off;
12641 ep->X_add_number -= off;
12642 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
12643 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
12645 /* For ULH and M_USH_A OR the LSB in. */
12646 if (!ust || large_offset)
12648 tempreg = !large_offset ? AT : op[0];
12649 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
12650 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12655 /* FIXME: Check if this is one of the itbl macros, since they
12656 are added dynamically. */
12657 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
12660 if (!mips_opts.at && used_at)
12661 as_bad (_("macro used $at after \".set noat\""));
12664 /* Implement macros in mips16 mode. */
12667 mips16_macro (struct mips_cl_insn *ip)
12669 const struct mips_operand_array *operands;
12674 const char *s, *s2, *s3;
12675 unsigned int op[MAX_OPERANDS];
12678 mask = ip->insn_mo->mask;
12680 operands = insn_operands (ip);
12681 for (i = 0; i < MAX_OPERANDS; i++)
12682 if (operands->operand[i])
12683 op[i] = insn_extract_operand (ip, operands->operand[i]);
12687 expr1.X_op = O_constant;
12688 expr1.X_op_symbol = NULL;
12689 expr1.X_add_symbol = NULL;
12690 expr1.X_add_number = 1;
12709 start_noreorder ();
12710 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
12711 expr1.X_add_number = 2;
12712 macro_build (&expr1, "bnez", "x,p", op[2]);
12713 macro_build (NULL, "break", "6", 7);
12715 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12716 since that causes an overflow. We should do that as well,
12717 but I don't see how to do the comparisons without a temporary
12720 macro_build (NULL, s, "x", op[0]);
12739 start_noreorder ();
12740 macro_build (NULL, s, "0,x,y", op[1], op[2]);
12741 expr1.X_add_number = 2;
12742 macro_build (&expr1, "bnez", "x,p", op[2]);
12743 macro_build (NULL, "break", "6", 7);
12745 macro_build (NULL, s2, "x", op[0]);
12751 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
12752 macro_build (NULL, "mflo", "x", op[0]);
12760 imm_expr.X_add_number = -imm_expr.X_add_number;
12761 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
12765 imm_expr.X_add_number = -imm_expr.X_add_number;
12766 macro_build (&imm_expr, "addiu", "x,k", op[0]);
12770 imm_expr.X_add_number = -imm_expr.X_add_number;
12771 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
12793 goto do_reverse_branch;
12797 goto do_reverse_branch;
12809 goto do_reverse_branch;
12820 macro_build (NULL, s, "x,y", op[0], op[1]);
12821 macro_build (&offset_expr, s2, "p");
12848 goto do_addone_branch_i;
12853 goto do_addone_branch_i;
12868 goto do_addone_branch_i;
12874 do_addone_branch_i:
12875 ++imm_expr.X_add_number;
12878 macro_build (&imm_expr, s, s3, op[0]);
12879 macro_build (&offset_expr, s2, "p");
12883 expr1.X_add_number = 0;
12884 macro_build (&expr1, "slti", "x,8", op[1]);
12885 if (op[0] != op[1])
12886 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
12887 expr1.X_add_number = 2;
12888 macro_build (&expr1, "bteqz", "p");
12889 macro_build (NULL, "neg", "x,w", op[0], op[0]);
12894 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12895 opcode bits in *OPCODE_EXTRA. */
12897 static struct mips_opcode *
12898 mips_lookup_insn (struct hash_control *hash, const char *start,
12899 ssize_t length, unsigned int *opcode_extra)
12901 char *name, *dot, *p;
12902 unsigned int mask, suffix;
12904 struct mips_opcode *insn;
12906 /* Make a copy of the instruction so that we can fiddle with it. */
12907 name = alloca (length + 1);
12908 memcpy (name, start, length);
12909 name[length] = '\0';
12911 /* Look up the instruction as-is. */
12912 insn = (struct mips_opcode *) hash_find (hash, name);
12916 dot = strchr (name, '.');
12919 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12920 p = mips_parse_vu0_channels (dot + 1, &mask);
12921 if (*p == 0 && mask != 0)
12924 insn = (struct mips_opcode *) hash_find (hash, name);
12926 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
12928 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
12934 if (mips_opts.micromips)
12936 /* See if there's an instruction size override suffix,
12937 either `16' or `32', at the end of the mnemonic proper,
12938 that defines the operation, i.e. before the first `.'
12939 character if any. Strip it and retry. */
12940 opend = dot != NULL ? dot - name : length;
12941 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
12943 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12949 memcpy (name + opend - 2, name + opend, length - opend + 1);
12950 insn = (struct mips_opcode *) hash_find (hash, name);
12953 forced_insn_length = suffix;
12962 /* Assemble an instruction into its binary format. If the instruction
12963 is a macro, set imm_expr and offset_expr to the values associated
12964 with "I" and "A" operands respectively. Otherwise store the value
12965 of the relocatable field (if any) in offset_expr. In both cases
12966 set offset_reloc to the relocation operators applied to offset_expr. */
12969 mips_ip (char *str, struct mips_cl_insn *insn)
12971 const struct mips_opcode *first, *past;
12972 struct hash_control *hash;
12975 struct mips_operand_token *tokens;
12976 unsigned int opcode_extra;
12978 if (mips_opts.micromips)
12980 hash = micromips_op_hash;
12981 past = µmips_opcodes[bfd_micromips_num_opcodes];
12986 past = &mips_opcodes[NUMOPCODES];
12988 forced_insn_length = 0;
12991 /* We first try to match an instruction up to a space or to the end. */
12992 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12995 first = mips_lookup_insn (hash, str, end, &opcode_extra);
12998 set_insn_error (0, _("unrecognized opcode"));
13002 if (strcmp (first->name, "li.s") == 0)
13004 else if (strcmp (first->name, "li.d") == 0)
13008 tokens = mips_parse_arguments (str + end, format);
13012 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13013 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
13014 set_insn_error (0, _("invalid operands"));
13016 obstack_free (&mips_operand_tokens, tokens);
13019 /* As for mips_ip, but used when assembling MIPS16 code.
13020 Also set forced_insn_length to the resulting instruction size in
13021 bytes if the user explicitly requested a small or extended instruction. */
13024 mips16_ip (char *str, struct mips_cl_insn *insn)
13027 struct mips_opcode *first;
13028 struct mips_operand_token *tokens;
13030 forced_insn_length = 0;
13032 for (s = str; ISLOWER (*s); ++s)
13046 if (s[1] == 't' && s[2] == ' ')
13048 forced_insn_length = 2;
13052 else if (s[1] == 'e' && s[2] == ' ')
13054 forced_insn_length = 4;
13058 /* Fall through. */
13060 set_insn_error (0, _("unrecognized opcode"));
13064 if (mips_opts.noautoextend && !forced_insn_length)
13065 forced_insn_length = 2;
13068 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13073 set_insn_error (0, _("unrecognized opcode"));
13077 tokens = mips_parse_arguments (s, 0);
13081 if (!match_mips16_insns (insn, first, tokens))
13082 set_insn_error (0, _("invalid operands"));
13084 obstack_free (&mips_operand_tokens, tokens);
13087 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13088 NBITS is the number of significant bits in VAL. */
13090 static unsigned long
13091 mips16_immed_extend (offsetT val, unsigned int nbits)
13096 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13099 else if (nbits == 15)
13101 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13106 extval = ((val & 0x1f) << 6) | (val & 0x20);
13109 return (extval << 16) | val;
13112 /* Like decode_mips16_operand, but require the operand to be defined and
13113 require it to be an integer. */
13115 static const struct mips_int_operand *
13116 mips16_immed_operand (int type, bfd_boolean extended_p)
13118 const struct mips_operand *operand;
13120 operand = decode_mips16_operand (type, extended_p);
13121 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13123 return (const struct mips_int_operand *) operand;
13126 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13129 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13130 bfd_reloc_code_real_type reloc, offsetT sval)
13132 int min_val, max_val;
13134 min_val = mips_int_operand_min (operand);
13135 max_val = mips_int_operand_max (operand);
13136 if (reloc != BFD_RELOC_UNUSED)
13139 sval = SEXT_16BIT (sval);
13144 return (sval >= min_val
13146 && (sval & ((1 << operand->shift) - 1)) == 0);
13149 /* Install immediate value VAL into MIPS16 instruction *INSN,
13150 extending it if necessary. The instruction in *INSN may
13151 already be extended.
13153 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13154 if none. In the former case, VAL is a 16-bit number with no
13155 defined signedness.
13157 TYPE is the type of the immediate field. USER_INSN_LENGTH
13158 is the length that the user requested, or 0 if none. */
13161 mips16_immed (char *file, unsigned int line, int type,
13162 bfd_reloc_code_real_type reloc, offsetT val,
13163 unsigned int user_insn_length, unsigned long *insn)
13165 const struct mips_int_operand *operand;
13166 unsigned int uval, length;
13168 operand = mips16_immed_operand (type, FALSE);
13169 if (!mips16_immed_in_range_p (operand, reloc, val))
13171 /* We need an extended instruction. */
13172 if (user_insn_length == 2)
13173 as_bad_where (file, line, _("invalid unextended operand value"));
13175 *insn |= MIPS16_EXTEND;
13177 else if (user_insn_length == 4)
13179 /* The operand doesn't force an unextended instruction to be extended.
13180 Warn if the user wanted an extended instruction anyway. */
13181 *insn |= MIPS16_EXTEND;
13182 as_warn_where (file, line,
13183 _("extended operand requested but not required"));
13186 length = mips16_opcode_length (*insn);
13189 operand = mips16_immed_operand (type, TRUE);
13190 if (!mips16_immed_in_range_p (operand, reloc, val))
13191 as_bad_where (file, line,
13192 _("operand value out of range for instruction"));
13194 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13196 *insn = mips_insert_operand (&operand->root, *insn, uval);
13198 *insn |= mips16_immed_extend (uval, operand->root.size);
13201 struct percent_op_match
13204 bfd_reloc_code_real_type reloc;
13207 static const struct percent_op_match mips_percent_op[] =
13209 {"%lo", BFD_RELOC_LO16},
13210 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13211 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13212 {"%call16", BFD_RELOC_MIPS_CALL16},
13213 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13214 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13215 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13216 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13217 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13218 {"%got", BFD_RELOC_MIPS_GOT16},
13219 {"%gp_rel", BFD_RELOC_GPREL16},
13220 {"%half", BFD_RELOC_16},
13221 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13222 {"%higher", BFD_RELOC_MIPS_HIGHER},
13223 {"%neg", BFD_RELOC_MIPS_SUB},
13224 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13225 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13226 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13227 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13228 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13229 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13230 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13231 {"%hi", BFD_RELOC_HI16_S}
13234 static const struct percent_op_match mips16_percent_op[] =
13236 {"%lo", BFD_RELOC_MIPS16_LO16},
13237 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13238 {"%got", BFD_RELOC_MIPS16_GOT16},
13239 {"%call16", BFD_RELOC_MIPS16_CALL16},
13240 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13241 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13242 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13243 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13244 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13245 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13246 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13247 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13251 /* Return true if *STR points to a relocation operator. When returning true,
13252 move *STR over the operator and store its relocation code in *RELOC.
13253 Leave both *STR and *RELOC alone when returning false. */
13256 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13258 const struct percent_op_match *percent_op;
13261 if (mips_opts.mips16)
13263 percent_op = mips16_percent_op;
13264 limit = ARRAY_SIZE (mips16_percent_op);
13268 percent_op = mips_percent_op;
13269 limit = ARRAY_SIZE (mips_percent_op);
13272 for (i = 0; i < limit; i++)
13273 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13275 int len = strlen (percent_op[i].str);
13277 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13280 *str += strlen (percent_op[i].str);
13281 *reloc = percent_op[i].reloc;
13283 /* Check whether the output BFD supports this relocation.
13284 If not, issue an error and fall back on something safe. */
13285 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13287 as_bad (_("relocation %s isn't supported by the current ABI"),
13288 percent_op[i].str);
13289 *reloc = BFD_RELOC_UNUSED;
13297 /* Parse string STR as a 16-bit relocatable operand. Store the
13298 expression in *EP and the relocations in the array starting
13299 at RELOC. Return the number of relocation operators used.
13301 On exit, EXPR_END points to the first character after the expression. */
13304 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13307 bfd_reloc_code_real_type reversed_reloc[3];
13308 size_t reloc_index, i;
13309 int crux_depth, str_depth;
13312 /* Search for the start of the main expression, recoding relocations
13313 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13314 of the main expression and with CRUX_DEPTH containing the number
13315 of open brackets at that point. */
13322 crux_depth = str_depth;
13324 /* Skip over whitespace and brackets, keeping count of the number
13326 while (*str == ' ' || *str == '\t' || *str == '(')
13331 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13332 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13334 my_getExpression (ep, crux);
13337 /* Match every open bracket. */
13338 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13342 if (crux_depth > 0)
13343 as_bad (_("unclosed '('"));
13347 if (reloc_index != 0)
13349 prev_reloc_op_frag = frag_now;
13350 for (i = 0; i < reloc_index; i++)
13351 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13354 return reloc_index;
13358 my_getExpression (expressionS *ep, char *str)
13362 save_in = input_line_pointer;
13363 input_line_pointer = str;
13365 expr_end = input_line_pointer;
13366 input_line_pointer = save_in;
13370 md_atof (int type, char *litP, int *sizeP)
13372 return ieee_md_atof (type, litP, sizeP, target_big_endian);
13376 md_number_to_chars (char *buf, valueT val, int n)
13378 if (target_big_endian)
13379 number_to_chars_bigendian (buf, val, n);
13381 number_to_chars_littleendian (buf, val, n);
13384 static int support_64bit_objects(void)
13386 const char **list, **l;
13389 list = bfd_target_list ();
13390 for (l = list; *l != NULL; l++)
13391 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13392 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
13394 yes = (*l != NULL);
13399 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13400 NEW_VALUE. Warn if another value was already specified. Note:
13401 we have to defer parsing the -march and -mtune arguments in order
13402 to handle 'from-abi' correctly, since the ABI might be specified
13403 in a later argument. */
13406 mips_set_option_string (const char **string_ptr, const char *new_value)
13408 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13409 as_warn (_("a different %s was already specified, is now %s"),
13410 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13413 *string_ptr = new_value;
13417 md_parse_option (int c, char *arg)
13421 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13422 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13424 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13425 c == mips_ases[i].option_on);
13431 case OPTION_CONSTRUCT_FLOATS:
13432 mips_disable_float_construction = 0;
13435 case OPTION_NO_CONSTRUCT_FLOATS:
13436 mips_disable_float_construction = 1;
13448 target_big_endian = 1;
13452 target_big_endian = 0;
13458 else if (arg[0] == '0')
13460 else if (arg[0] == '1')
13470 mips_debug = atoi (arg);
13474 file_mips_isa = ISA_MIPS1;
13478 file_mips_isa = ISA_MIPS2;
13482 file_mips_isa = ISA_MIPS3;
13486 file_mips_isa = ISA_MIPS4;
13490 file_mips_isa = ISA_MIPS5;
13493 case OPTION_MIPS32:
13494 file_mips_isa = ISA_MIPS32;
13497 case OPTION_MIPS32R2:
13498 file_mips_isa = ISA_MIPS32R2;
13501 case OPTION_MIPS64R2:
13502 file_mips_isa = ISA_MIPS64R2;
13505 case OPTION_MIPS64:
13506 file_mips_isa = ISA_MIPS64;
13510 mips_set_option_string (&mips_tune_string, arg);
13514 mips_set_option_string (&mips_arch_string, arg);
13518 mips_set_option_string (&mips_arch_string, "4650");
13519 mips_set_option_string (&mips_tune_string, "4650");
13522 case OPTION_NO_M4650:
13526 mips_set_option_string (&mips_arch_string, "4010");
13527 mips_set_option_string (&mips_tune_string, "4010");
13530 case OPTION_NO_M4010:
13534 mips_set_option_string (&mips_arch_string, "4100");
13535 mips_set_option_string (&mips_tune_string, "4100");
13538 case OPTION_NO_M4100:
13542 mips_set_option_string (&mips_arch_string, "3900");
13543 mips_set_option_string (&mips_tune_string, "3900");
13546 case OPTION_NO_M3900:
13549 case OPTION_MICROMIPS:
13550 if (mips_opts.mips16 == 1)
13552 as_bad (_("-mmicromips cannot be used with -mips16"));
13555 mips_opts.micromips = 1;
13556 mips_no_prev_insn ();
13559 case OPTION_NO_MICROMIPS:
13560 mips_opts.micromips = 0;
13561 mips_no_prev_insn ();
13564 case OPTION_MIPS16:
13565 if (mips_opts.micromips == 1)
13567 as_bad (_("-mips16 cannot be used with -micromips"));
13570 mips_opts.mips16 = 1;
13571 mips_no_prev_insn ();
13574 case OPTION_NO_MIPS16:
13575 mips_opts.mips16 = 0;
13576 mips_no_prev_insn ();
13579 case OPTION_FIX_24K:
13583 case OPTION_NO_FIX_24K:
13587 case OPTION_FIX_LOONGSON2F_JUMP:
13588 mips_fix_loongson2f_jump = TRUE;
13591 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13592 mips_fix_loongson2f_jump = FALSE;
13595 case OPTION_FIX_LOONGSON2F_NOP:
13596 mips_fix_loongson2f_nop = TRUE;
13599 case OPTION_NO_FIX_LOONGSON2F_NOP:
13600 mips_fix_loongson2f_nop = FALSE;
13603 case OPTION_FIX_VR4120:
13604 mips_fix_vr4120 = 1;
13607 case OPTION_NO_FIX_VR4120:
13608 mips_fix_vr4120 = 0;
13611 case OPTION_FIX_VR4130:
13612 mips_fix_vr4130 = 1;
13615 case OPTION_NO_FIX_VR4130:
13616 mips_fix_vr4130 = 0;
13619 case OPTION_FIX_CN63XXP1:
13620 mips_fix_cn63xxp1 = TRUE;
13623 case OPTION_NO_FIX_CN63XXP1:
13624 mips_fix_cn63xxp1 = FALSE;
13627 case OPTION_RELAX_BRANCH:
13628 mips_relax_branch = 1;
13631 case OPTION_NO_RELAX_BRANCH:
13632 mips_relax_branch = 0;
13635 case OPTION_INSN32:
13636 mips_opts.insn32 = TRUE;
13639 case OPTION_NO_INSN32:
13640 mips_opts.insn32 = FALSE;
13643 case OPTION_MSHARED:
13644 mips_in_shared = TRUE;
13647 case OPTION_MNO_SHARED:
13648 mips_in_shared = FALSE;
13651 case OPTION_MSYM32:
13652 mips_opts.sym32 = TRUE;
13655 case OPTION_MNO_SYM32:
13656 mips_opts.sym32 = FALSE;
13659 /* When generating ELF code, we permit -KPIC and -call_shared to
13660 select SVR4_PIC, and -non_shared to select no PIC. This is
13661 intended to be compatible with Irix 5. */
13662 case OPTION_CALL_SHARED:
13663 mips_pic = SVR4_PIC;
13664 mips_abicalls = TRUE;
13667 case OPTION_CALL_NONPIC:
13669 mips_abicalls = TRUE;
13672 case OPTION_NON_SHARED:
13674 mips_abicalls = FALSE;
13677 /* The -xgot option tells the assembler to use 32 bit offsets
13678 when accessing the got in SVR4_PIC mode. It is for Irix
13685 g_switch_value = atoi (arg);
13689 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13692 mips_abi = O32_ABI;
13696 mips_abi = N32_ABI;
13700 mips_abi = N64_ABI;
13701 if (!support_64bit_objects())
13702 as_fatal (_("no compiled in support for 64 bit object file format"));
13706 file_mips_gp32 = 1;
13710 file_mips_gp32 = 0;
13714 file_mips_fp32 = 1;
13718 file_mips_fp32 = 0;
13721 case OPTION_SINGLE_FLOAT:
13722 file_mips_single_float = 1;
13725 case OPTION_DOUBLE_FLOAT:
13726 file_mips_single_float = 0;
13729 case OPTION_SOFT_FLOAT:
13730 file_mips_soft_float = 1;
13733 case OPTION_HARD_FLOAT:
13734 file_mips_soft_float = 0;
13738 if (strcmp (arg, "32") == 0)
13739 mips_abi = O32_ABI;
13740 else if (strcmp (arg, "o64") == 0)
13741 mips_abi = O64_ABI;
13742 else if (strcmp (arg, "n32") == 0)
13743 mips_abi = N32_ABI;
13744 else if (strcmp (arg, "64") == 0)
13746 mips_abi = N64_ABI;
13747 if (! support_64bit_objects())
13748 as_fatal (_("no compiled in support for 64 bit object file "
13751 else if (strcmp (arg, "eabi") == 0)
13752 mips_abi = EABI_ABI;
13755 as_fatal (_("invalid abi -mabi=%s"), arg);
13760 case OPTION_M7000_HILO_FIX:
13761 mips_7000_hilo_fix = TRUE;
13764 case OPTION_MNO_7000_HILO_FIX:
13765 mips_7000_hilo_fix = FALSE;
13768 case OPTION_MDEBUG:
13769 mips_flag_mdebug = TRUE;
13772 case OPTION_NO_MDEBUG:
13773 mips_flag_mdebug = FALSE;
13777 mips_flag_pdr = TRUE;
13780 case OPTION_NO_PDR:
13781 mips_flag_pdr = FALSE;
13784 case OPTION_MVXWORKS_PIC:
13785 mips_pic = VXWORKS_PIC;
13789 if (strcmp (arg, "2008") == 0)
13790 mips_flag_nan2008 = TRUE;
13791 else if (strcmp (arg, "legacy") == 0)
13792 mips_flag_nan2008 = FALSE;
13795 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
13804 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13809 /* Set up globals to generate code for the ISA or processor
13810 described by INFO. */
13813 mips_set_architecture (const struct mips_cpu_info *info)
13817 file_mips_arch = info->cpu;
13818 mips_opts.arch = info->cpu;
13819 mips_opts.isa = info->isa;
13824 /* Likewise for tuning. */
13827 mips_set_tune (const struct mips_cpu_info *info)
13830 mips_tune = info->cpu;
13835 mips_after_parse_args (void)
13837 const struct mips_cpu_info *arch_info = 0;
13838 const struct mips_cpu_info *tune_info = 0;
13840 /* GP relative stuff not working for PE */
13841 if (strncmp (TARGET_OS, "pe", 2) == 0)
13843 if (g_switch_seen && g_switch_value != 0)
13844 as_bad (_("-G not supported in this configuration"));
13845 g_switch_value = 0;
13848 if (mips_abi == NO_ABI)
13849 mips_abi = MIPS_DEFAULT_ABI;
13851 /* The following code determines the architecture and register size.
13852 Similar code was added to GCC 3.3 (see override_options() in
13853 config/mips/mips.c). The GAS and GCC code should be kept in sync
13854 as much as possible. */
13856 if (mips_arch_string != 0)
13857 arch_info = mips_parse_cpu ("-march", mips_arch_string);
13859 if (file_mips_isa != ISA_UNKNOWN)
13861 /* Handle -mipsN. At this point, file_mips_isa contains the
13862 ISA level specified by -mipsN, while arch_info->isa contains
13863 the -march selection (if any). */
13864 if (arch_info != 0)
13866 /* -march takes precedence over -mipsN, since it is more descriptive.
13867 There's no harm in specifying both as long as the ISA levels
13869 if (file_mips_isa != arch_info->isa)
13870 as_bad (_("-%s conflicts with the other architecture options,"
13871 " which imply -%s"),
13872 mips_cpu_info_from_isa (file_mips_isa)->name,
13873 mips_cpu_info_from_isa (arch_info->isa)->name);
13876 arch_info = mips_cpu_info_from_isa (file_mips_isa);
13879 if (arch_info == 0)
13881 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13882 gas_assert (arch_info);
13885 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
13886 as_bad (_("-march=%s is not compatible with the selected ABI"),
13889 mips_set_architecture (arch_info);
13891 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13892 if (mips_tune_string != 0)
13893 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
13895 if (tune_info == 0)
13896 mips_set_tune (arch_info);
13898 mips_set_tune (tune_info);
13900 if (file_mips_gp32 >= 0)
13902 /* The user specified the size of the integer registers. Make sure
13903 it agrees with the ABI and ISA. */
13904 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
13905 as_bad (_("-mgp64 used with a 32-bit processor"));
13906 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
13907 as_bad (_("-mgp32 used with a 64-bit ABI"));
13908 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
13909 as_bad (_("-mgp64 used with a 32-bit ABI"));
13913 /* Infer the integer register size from the ABI and processor.
13914 Restrict ourselves to 32-bit registers if that's all the
13915 processor has, or if the ABI cannot handle 64-bit registers. */
13916 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
13917 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
13920 switch (file_mips_fp32)
13924 /* No user specified float register size.
13925 ??? GAS treats single-float processors as though they had 64-bit
13926 float registers (although it complains when double-precision
13927 instructions are used). As things stand, saying they have 32-bit
13928 registers would lead to spurious "register must be even" messages.
13929 So here we assume float registers are never smaller than the
13931 if (file_mips_gp32 == 0)
13932 /* 64-bit integer registers implies 64-bit float registers. */
13933 file_mips_fp32 = 0;
13934 else if ((mips_opts.ase & FP64_ASES)
13935 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
13936 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13937 file_mips_fp32 = 0;
13939 /* 32-bit float registers. */
13940 file_mips_fp32 = 1;
13943 /* The user specified the size of the float registers. Check if it
13944 agrees with the ABI and ISA. */
13946 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13947 as_bad (_("-mfp64 used with a 32-bit fpu"));
13948 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
13949 && !ISA_HAS_MXHC1 (mips_opts.isa))
13950 as_warn (_("-mfp64 used with a 32-bit ABI"));
13953 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13954 as_warn (_("-mfp32 used with a 64-bit ABI"));
13958 /* End of GCC-shared inference code. */
13960 /* This flag is set when we have a 64-bit capable CPU but use only
13961 32-bit wide registers. Note that EABI does not use it. */
13962 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
13963 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
13964 || mips_abi == O32_ABI))
13965 mips_32bitmode = 1;
13967 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
13968 as_bad (_("trap exception not supported at ISA 1"));
13970 /* If the selected architecture includes support for ASEs, enable
13971 generation of code for them. */
13972 if (mips_opts.mips16 == -1)
13973 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
13974 if (mips_opts.micromips == -1)
13975 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
13977 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13978 ASEs from being selected implicitly. */
13979 if (file_mips_fp32 == 1)
13980 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
13982 /* If the user didn't explicitly select or deselect a particular ASE,
13983 use the default setting for the CPU. */
13984 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
13986 file_mips_isa = mips_opts.isa;
13987 file_ase = mips_opts.ase;
13988 mips_opts.gp32 = file_mips_gp32;
13989 mips_opts.fp32 = file_mips_fp32;
13990 mips_opts.soft_float = file_mips_soft_float;
13991 mips_opts.single_float = file_mips_single_float;
13993 mips_check_isa_supports_ases ();
13995 if (mips_flag_mdebug < 0)
13996 mips_flag_mdebug = 0;
14000 mips_init_after_args (void)
14002 /* initialize opcodes */
14003 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14004 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14008 md_pcrel_from (fixS *fixP)
14010 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14011 switch (fixP->fx_r_type)
14013 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14014 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14015 /* Return the address of the delay slot. */
14018 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14019 case BFD_RELOC_MICROMIPS_JMP:
14020 case BFD_RELOC_16_PCREL_S2:
14021 case BFD_RELOC_MIPS_JMP:
14022 /* Return the address of the delay slot. */
14025 case BFD_RELOC_32_PCREL:
14029 /* We have no relocation type for PC relative MIPS16 instructions. */
14030 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
14031 as_bad_where (fixP->fx_file, fixP->fx_line,
14032 _("PC relative MIPS16 instruction references"
14033 " a different section"));
14038 /* This is called before the symbol table is processed. In order to
14039 work with gcc when using mips-tfile, we must keep all local labels.
14040 However, in other cases, we want to discard them. If we were
14041 called with -g, but we didn't see any debugging information, it may
14042 mean that gcc is smuggling debugging information through to
14043 mips-tfile, in which case we must generate all local labels. */
14046 mips_frob_file_before_adjust (void)
14048 #ifndef NO_ECOFF_DEBUGGING
14049 if (ECOFF_DEBUGGING
14051 && ! ecoff_debugging_seen)
14052 flag_keep_locals = 1;
14056 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14057 the corresponding LO16 reloc. This is called before md_apply_fix and
14058 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14059 relocation operators.
14061 For our purposes, a %lo() expression matches a %got() or %hi()
14064 (a) it refers to the same symbol; and
14065 (b) the offset applied in the %lo() expression is no lower than
14066 the offset applied in the %got() or %hi().
14068 (b) allows us to cope with code like:
14071 lh $4,%lo(foo+2)($4)
14073 ...which is legal on RELA targets, and has a well-defined behaviour
14074 if the user knows that adding 2 to "foo" will not induce a carry to
14077 When several %lo()s match a particular %got() or %hi(), we use the
14078 following rules to distinguish them:
14080 (1) %lo()s with smaller offsets are a better match than %lo()s with
14083 (2) %lo()s with no matching %got() or %hi() are better than those
14084 that already have a matching %got() or %hi().
14086 (3) later %lo()s are better than earlier %lo()s.
14088 These rules are applied in order.
14090 (1) means, among other things, that %lo()s with identical offsets are
14091 chosen if they exist.
14093 (2) means that we won't associate several high-part relocations with
14094 the same low-part relocation unless there's no alternative. Having
14095 several high parts for the same low part is a GNU extension; this rule
14096 allows careful users to avoid it.
14098 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14099 with the last high-part relocation being at the front of the list.
14100 It therefore makes sense to choose the last matching low-part
14101 relocation, all other things being equal. It's also easier
14102 to code that way. */
14105 mips_frob_file (void)
14107 struct mips_hi_fixup *l;
14108 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14110 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14112 segment_info_type *seginfo;
14113 bfd_boolean matched_lo_p;
14114 fixS **hi_pos, **lo_pos, **pos;
14116 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14118 /* If a GOT16 relocation turns out to be against a global symbol,
14119 there isn't supposed to be a matching LO. Ignore %gots against
14120 constants; we'll report an error for those later. */
14121 if (got16_reloc_p (l->fixp->fx_r_type)
14122 && !(l->fixp->fx_addsy
14123 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14126 /* Check quickly whether the next fixup happens to be a matching %lo. */
14127 if (fixup_has_matching_lo_p (l->fixp))
14130 seginfo = seg_info (l->seg);
14132 /* Set HI_POS to the position of this relocation in the chain.
14133 Set LO_POS to the position of the chosen low-part relocation.
14134 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14135 relocation that matches an immediately-preceding high-part
14139 matched_lo_p = FALSE;
14140 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14142 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14144 if (*pos == l->fixp)
14147 if ((*pos)->fx_r_type == looking_for_rtype
14148 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14149 && (*pos)->fx_offset >= l->fixp->fx_offset
14151 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14153 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14156 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14157 && fixup_has_matching_lo_p (*pos));
14160 /* If we found a match, remove the high-part relocation from its
14161 current position and insert it before the low-part relocation.
14162 Make the offsets match so that fixup_has_matching_lo_p()
14165 We don't warn about unmatched high-part relocations since some
14166 versions of gcc have been known to emit dead "lui ...%hi(...)"
14168 if (lo_pos != NULL)
14170 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14171 if (l->fixp->fx_next != *lo_pos)
14173 *hi_pos = l->fixp->fx_next;
14174 l->fixp->fx_next = *lo_pos;
14182 mips_force_relocation (fixS *fixp)
14184 if (generic_force_reloc (fixp))
14187 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14188 so that the linker relaxation can update targets. */
14189 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14190 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14191 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14197 /* Read the instruction associated with RELOC from BUF. */
14199 static unsigned int
14200 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14202 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14203 return read_compressed_insn (buf, 4);
14205 return read_insn (buf);
14208 /* Write instruction INSN to BUF, given that it has been relocated
14212 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14213 unsigned long insn)
14215 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14216 write_compressed_insn (buf, insn, 4);
14218 write_insn (buf, insn);
14221 /* Apply a fixup to the object file. */
14224 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14227 unsigned long insn;
14228 reloc_howto_type *howto;
14230 /* We ignore generic BFD relocations we don't know about. */
14231 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14235 gas_assert (fixP->fx_size == 2
14236 || fixP->fx_size == 4
14237 || fixP->fx_r_type == BFD_RELOC_16
14238 || fixP->fx_r_type == BFD_RELOC_64
14239 || fixP->fx_r_type == BFD_RELOC_CTOR
14240 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14241 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14242 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14243 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14244 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
14246 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14248 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
14249 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14250 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14251 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
14252 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
14254 /* Don't treat parts of a composite relocation as done. There are two
14257 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14258 should nevertheless be emitted if the first part is.
14260 (2) In normal usage, composite relocations are never assembly-time
14261 constants. The easiest way of dealing with the pathological
14262 exceptions is to generate a relocation against STN_UNDEF and
14263 leave everything up to the linker. */
14264 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14267 switch (fixP->fx_r_type)
14269 case BFD_RELOC_MIPS_TLS_GD:
14270 case BFD_RELOC_MIPS_TLS_LDM:
14271 case BFD_RELOC_MIPS_TLS_DTPREL32:
14272 case BFD_RELOC_MIPS_TLS_DTPREL64:
14273 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14274 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14275 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14276 case BFD_RELOC_MIPS_TLS_TPREL32:
14277 case BFD_RELOC_MIPS_TLS_TPREL64:
14278 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14279 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14280 case BFD_RELOC_MICROMIPS_TLS_GD:
14281 case BFD_RELOC_MICROMIPS_TLS_LDM:
14282 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14283 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14284 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14285 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14286 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14287 case BFD_RELOC_MIPS16_TLS_GD:
14288 case BFD_RELOC_MIPS16_TLS_LDM:
14289 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14290 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14291 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14292 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14293 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14294 if (!fixP->fx_addsy)
14296 as_bad_where (fixP->fx_file, fixP->fx_line,
14297 _("TLS relocation against a constant"));
14300 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14303 case BFD_RELOC_MIPS_JMP:
14304 case BFD_RELOC_MIPS_SHIFT5:
14305 case BFD_RELOC_MIPS_SHIFT6:
14306 case BFD_RELOC_MIPS_GOT_DISP:
14307 case BFD_RELOC_MIPS_GOT_PAGE:
14308 case BFD_RELOC_MIPS_GOT_OFST:
14309 case BFD_RELOC_MIPS_SUB:
14310 case BFD_RELOC_MIPS_INSERT_A:
14311 case BFD_RELOC_MIPS_INSERT_B:
14312 case BFD_RELOC_MIPS_DELETE:
14313 case BFD_RELOC_MIPS_HIGHEST:
14314 case BFD_RELOC_MIPS_HIGHER:
14315 case BFD_RELOC_MIPS_SCN_DISP:
14316 case BFD_RELOC_MIPS_REL16:
14317 case BFD_RELOC_MIPS_RELGOT:
14318 case BFD_RELOC_MIPS_JALR:
14319 case BFD_RELOC_HI16:
14320 case BFD_RELOC_HI16_S:
14321 case BFD_RELOC_LO16:
14322 case BFD_RELOC_GPREL16:
14323 case BFD_RELOC_MIPS_LITERAL:
14324 case BFD_RELOC_MIPS_CALL16:
14325 case BFD_RELOC_MIPS_GOT16:
14326 case BFD_RELOC_GPREL32:
14327 case BFD_RELOC_MIPS_GOT_HI16:
14328 case BFD_RELOC_MIPS_GOT_LO16:
14329 case BFD_RELOC_MIPS_CALL_HI16:
14330 case BFD_RELOC_MIPS_CALL_LO16:
14331 case BFD_RELOC_MIPS16_GPREL:
14332 case BFD_RELOC_MIPS16_GOT16:
14333 case BFD_RELOC_MIPS16_CALL16:
14334 case BFD_RELOC_MIPS16_HI16:
14335 case BFD_RELOC_MIPS16_HI16_S:
14336 case BFD_RELOC_MIPS16_LO16:
14337 case BFD_RELOC_MIPS16_JMP:
14338 case BFD_RELOC_MICROMIPS_JMP:
14339 case BFD_RELOC_MICROMIPS_GOT_DISP:
14340 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14341 case BFD_RELOC_MICROMIPS_GOT_OFST:
14342 case BFD_RELOC_MICROMIPS_SUB:
14343 case BFD_RELOC_MICROMIPS_HIGHEST:
14344 case BFD_RELOC_MICROMIPS_HIGHER:
14345 case BFD_RELOC_MICROMIPS_SCN_DISP:
14346 case BFD_RELOC_MICROMIPS_JALR:
14347 case BFD_RELOC_MICROMIPS_HI16:
14348 case BFD_RELOC_MICROMIPS_HI16_S:
14349 case BFD_RELOC_MICROMIPS_LO16:
14350 case BFD_RELOC_MICROMIPS_GPREL16:
14351 case BFD_RELOC_MICROMIPS_LITERAL:
14352 case BFD_RELOC_MICROMIPS_CALL16:
14353 case BFD_RELOC_MICROMIPS_GOT16:
14354 case BFD_RELOC_MICROMIPS_GOT_HI16:
14355 case BFD_RELOC_MICROMIPS_GOT_LO16:
14356 case BFD_RELOC_MICROMIPS_CALL_HI16:
14357 case BFD_RELOC_MICROMIPS_CALL_LO16:
14358 case BFD_RELOC_MIPS_EH:
14363 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14365 insn = read_reloc_insn (buf, fixP->fx_r_type);
14366 if (mips16_reloc_p (fixP->fx_r_type))
14367 insn |= mips16_immed_extend (value, 16);
14369 insn |= (value & 0xffff);
14370 write_reloc_insn (buf, fixP->fx_r_type, insn);
14373 as_bad_where (fixP->fx_file, fixP->fx_line,
14374 _("unsupported constant in relocation"));
14379 /* This is handled like BFD_RELOC_32, but we output a sign
14380 extended value if we are only 32 bits. */
14383 if (8 <= sizeof (valueT))
14384 md_number_to_chars (buf, *valP, 8);
14389 if ((*valP & 0x80000000) != 0)
14393 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14394 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
14399 case BFD_RELOC_RVA:
14401 case BFD_RELOC_32_PCREL:
14403 /* If we are deleting this reloc entry, we must fill in the
14404 value now. This can happen if we have a .word which is not
14405 resolved when it appears but is later defined. */
14407 md_number_to_chars (buf, *valP, fixP->fx_size);
14410 case BFD_RELOC_16_PCREL_S2:
14411 if ((*valP & 0x3) != 0)
14412 as_bad_where (fixP->fx_file, fixP->fx_line,
14413 _("branch to misaligned address (%lx)"), (long) *valP);
14415 /* We need to save the bits in the instruction since fixup_segment()
14416 might be deleting the relocation entry (i.e., a branch within
14417 the current segment). */
14418 if (! fixP->fx_done)
14421 /* Update old instruction data. */
14422 insn = read_insn (buf);
14424 if (*valP + 0x20000 <= 0x3ffff)
14426 insn |= (*valP >> 2) & 0xffff;
14427 write_insn (buf, insn);
14429 else if (mips_pic == NO_PIC
14431 && fixP->fx_frag->fr_address >= text_section->vma
14432 && (fixP->fx_frag->fr_address
14433 < text_section->vma + bfd_get_section_size (text_section))
14434 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14435 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14436 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
14438 /* The branch offset is too large. If this is an
14439 unconditional branch, and we are not generating PIC code,
14440 we can convert it to an absolute jump instruction. */
14441 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14442 insn = 0x0c000000; /* jal */
14444 insn = 0x08000000; /* j */
14445 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14447 fixP->fx_addsy = section_symbol (text_section);
14448 *valP += md_pcrel_from (fixP);
14449 write_insn (buf, insn);
14453 /* If we got here, we have branch-relaxation disabled,
14454 and there's nothing we can do to fix this instruction
14455 without turning it into a longer sequence. */
14456 as_bad_where (fixP->fx_file, fixP->fx_line,
14457 _("branch out of range"));
14461 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14462 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14463 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14464 /* We adjust the offset back to even. */
14465 if ((*valP & 0x1) != 0)
14468 if (! fixP->fx_done)
14471 /* Should never visit here, because we keep the relocation. */
14475 case BFD_RELOC_VTABLE_INHERIT:
14478 && !S_IS_DEFINED (fixP->fx_addsy)
14479 && !S_IS_WEAK (fixP->fx_addsy))
14480 S_SET_WEAK (fixP->fx_addsy);
14483 case BFD_RELOC_VTABLE_ENTRY:
14491 /* Remember value for tc_gen_reloc. */
14492 fixP->fx_addnumber = *valP;
14502 name = input_line_pointer;
14503 c = get_symbol_end ();
14504 p = (symbolS *) symbol_find_or_make (name);
14505 *input_line_pointer = c;
14509 /* Align the current frag to a given power of two. If a particular
14510 fill byte should be used, FILL points to an integer that contains
14511 that byte, otherwise FILL is null.
14513 This function used to have the comment:
14515 The MIPS assembler also automatically adjusts any preceding label.
14517 The implementation therefore applied the adjustment to a maximum of
14518 one label. However, other label adjustments are applied to batches
14519 of labels, and adjusting just one caused problems when new labels
14520 were added for the sake of debugging or unwind information.
14521 We therefore adjust all preceding labels (given as LABELS) instead. */
14524 mips_align (int to, int *fill, struct insn_label_list *labels)
14526 mips_emit_delays ();
14527 mips_record_compressed_mode ();
14528 if (fill == NULL && subseg_text_p (now_seg))
14529 frag_align_code (to, 0);
14531 frag_align (to, fill ? *fill : 0, 0);
14532 record_alignment (now_seg, to);
14533 mips_move_labels (labels, FALSE);
14536 /* Align to a given power of two. .align 0 turns off the automatic
14537 alignment used by the data creating pseudo-ops. */
14540 s_align (int x ATTRIBUTE_UNUSED)
14542 int temp, fill_value, *fill_ptr;
14543 long max_alignment = 28;
14545 /* o Note that the assembler pulls down any immediately preceding label
14546 to the aligned address.
14547 o It's not documented but auto alignment is reinstated by
14548 a .align pseudo instruction.
14549 o Note also that after auto alignment is turned off the mips assembler
14550 issues an error on attempt to assemble an improperly aligned data item.
14553 temp = get_absolute_expression ();
14554 if (temp > max_alignment)
14555 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
14558 as_warn (_("alignment negative, 0 assumed"));
14561 if (*input_line_pointer == ',')
14563 ++input_line_pointer;
14564 fill_value = get_absolute_expression ();
14565 fill_ptr = &fill_value;
14571 segment_info_type *si = seg_info (now_seg);
14572 struct insn_label_list *l = si->label_list;
14573 /* Auto alignment should be switched on by next section change. */
14575 mips_align (temp, fill_ptr, l);
14582 demand_empty_rest_of_line ();
14586 s_change_sec (int sec)
14590 /* The ELF backend needs to know that we are changing sections, so
14591 that .previous works correctly. We could do something like check
14592 for an obj_section_change_hook macro, but that might be confusing
14593 as it would not be appropriate to use it in the section changing
14594 functions in read.c, since obj-elf.c intercepts those. FIXME:
14595 This should be cleaner, somehow. */
14596 obj_elf_section_change_hook ();
14598 mips_emit_delays ();
14609 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14610 demand_empty_rest_of_line ();
14614 seg = subseg_new (RDATA_SECTION_NAME,
14615 (subsegT) get_absolute_expression ());
14616 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14617 | SEC_READONLY | SEC_RELOC
14619 if (strncmp (TARGET_OS, "elf", 3) != 0)
14620 record_alignment (seg, 4);
14621 demand_empty_rest_of_line ();
14625 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
14626 bfd_set_section_flags (stdoutput, seg,
14627 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14628 if (strncmp (TARGET_OS, "elf", 3) != 0)
14629 record_alignment (seg, 4);
14630 demand_empty_rest_of_line ();
14634 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
14635 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14636 if (strncmp (TARGET_OS, "elf", 3) != 0)
14637 record_alignment (seg, 4);
14638 demand_empty_rest_of_line ();
14646 s_change_section (int ignore ATTRIBUTE_UNUSED)
14648 char *section_name;
14653 int section_entry_size;
14654 int section_alignment;
14656 section_name = input_line_pointer;
14657 c = get_symbol_end ();
14659 next_c = *(input_line_pointer + 1);
14661 /* Do we have .section Name<,"flags">? */
14662 if (c != ',' || (c == ',' && next_c == '"'))
14664 /* just after name is now '\0'. */
14665 *input_line_pointer = c;
14666 input_line_pointer = section_name;
14667 obj_elf_section (ignore);
14670 input_line_pointer++;
14672 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14674 section_type = get_absolute_expression ();
14677 if (*input_line_pointer++ == ',')
14678 section_flag = get_absolute_expression ();
14681 if (*input_line_pointer++ == ',')
14682 section_entry_size = get_absolute_expression ();
14684 section_entry_size = 0;
14685 if (*input_line_pointer++ == ',')
14686 section_alignment = get_absolute_expression ();
14688 section_alignment = 0;
14689 /* FIXME: really ignore? */
14690 (void) section_alignment;
14692 section_name = xstrdup (section_name);
14694 /* When using the generic form of .section (as implemented by obj-elf.c),
14695 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14696 traditionally had to fall back on the more common @progbits instead.
14698 There's nothing really harmful in this, since bfd will correct
14699 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14700 means that, for backwards compatibility, the special_section entries
14701 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14703 Even so, we shouldn't force users of the MIPS .section syntax to
14704 incorrectly label the sections as SHT_PROGBITS. The best compromise
14705 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14706 generic type-checking code. */
14707 if (section_type == SHT_MIPS_DWARF)
14708 section_type = SHT_PROGBITS;
14710 obj_elf_change_section (section_name, section_type, section_flag,
14711 section_entry_size, 0, 0, 0);
14713 if (now_seg->name != section_name)
14714 free (section_name);
14718 mips_enable_auto_align (void)
14724 s_cons (int log_size)
14726 segment_info_type *si = seg_info (now_seg);
14727 struct insn_label_list *l = si->label_list;
14729 mips_emit_delays ();
14730 if (log_size > 0 && auto_align)
14731 mips_align (log_size, 0, l);
14732 cons (1 << log_size);
14733 mips_clear_insn_labels ();
14737 s_float_cons (int type)
14739 segment_info_type *si = seg_info (now_seg);
14740 struct insn_label_list *l = si->label_list;
14742 mips_emit_delays ();
14747 mips_align (3, 0, l);
14749 mips_align (2, 0, l);
14753 mips_clear_insn_labels ();
14756 /* Handle .globl. We need to override it because on Irix 5 you are
14759 where foo is an undefined symbol, to mean that foo should be
14760 considered to be the address of a function. */
14763 s_mips_globl (int x ATTRIBUTE_UNUSED)
14772 name = input_line_pointer;
14773 c = get_symbol_end ();
14774 symbolP = symbol_find_or_make (name);
14775 S_SET_EXTERNAL (symbolP);
14777 *input_line_pointer = c;
14778 SKIP_WHITESPACE ();
14780 /* On Irix 5, every global symbol that is not explicitly labelled as
14781 being a function is apparently labelled as being an object. */
14784 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14785 && (*input_line_pointer != ','))
14790 secname = input_line_pointer;
14791 c = get_symbol_end ();
14792 sec = bfd_get_section_by_name (stdoutput, secname);
14794 as_bad (_("%s: no such section"), secname);
14795 *input_line_pointer = c;
14797 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14798 flag = BSF_FUNCTION;
14801 symbol_get_bfdsym (symbolP)->flags |= flag;
14803 c = *input_line_pointer;
14806 input_line_pointer++;
14807 SKIP_WHITESPACE ();
14808 if (is_end_of_line[(unsigned char) *input_line_pointer])
14814 demand_empty_rest_of_line ();
14818 s_option (int x ATTRIBUTE_UNUSED)
14823 opt = input_line_pointer;
14824 c = get_symbol_end ();
14828 /* FIXME: What does this mean? */
14830 else if (strncmp (opt, "pic", 3) == 0)
14834 i = atoi (opt + 3);
14839 mips_pic = SVR4_PIC;
14840 mips_abicalls = TRUE;
14843 as_bad (_(".option pic%d not supported"), i);
14845 if (mips_pic == SVR4_PIC)
14847 if (g_switch_seen && g_switch_value != 0)
14848 as_warn (_("-G may not be used with SVR4 PIC code"));
14849 g_switch_value = 0;
14850 bfd_set_gp_size (stdoutput, 0);
14854 as_warn (_("unrecognized option \"%s\""), opt);
14856 *input_line_pointer = c;
14857 demand_empty_rest_of_line ();
14860 /* This structure is used to hold a stack of .set values. */
14862 struct mips_option_stack
14864 struct mips_option_stack *next;
14865 struct mips_set_options options;
14868 static struct mips_option_stack *mips_opts_stack;
14870 /* Handle the .set pseudo-op. */
14873 s_mipsset (int x ATTRIBUTE_UNUSED)
14875 char *name = input_line_pointer, ch;
14876 const struct mips_ase *ase;
14878 while (!is_end_of_line[(unsigned char) *input_line_pointer])
14879 ++input_line_pointer;
14880 ch = *input_line_pointer;
14881 *input_line_pointer = '\0';
14883 if (strcmp (name, "reorder") == 0)
14885 if (mips_opts.noreorder)
14888 else if (strcmp (name, "noreorder") == 0)
14890 if (!mips_opts.noreorder)
14891 start_noreorder ();
14893 else if (strncmp (name, "at=", 3) == 0)
14895 char *s = name + 3;
14897 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
14898 as_bad (_("unrecognized register name `%s'"), s);
14900 else if (strcmp (name, "at") == 0)
14902 mips_opts.at = ATREG;
14904 else if (strcmp (name, "noat") == 0)
14906 mips_opts.at = ZERO;
14908 else if (strcmp (name, "macro") == 0)
14910 mips_opts.warn_about_macros = 0;
14912 else if (strcmp (name, "nomacro") == 0)
14914 if (mips_opts.noreorder == 0)
14915 as_bad (_("`noreorder' must be set before `nomacro'"));
14916 mips_opts.warn_about_macros = 1;
14918 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
14920 mips_opts.nomove = 0;
14922 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
14924 mips_opts.nomove = 1;
14926 else if (strcmp (name, "bopt") == 0)
14928 mips_opts.nobopt = 0;
14930 else if (strcmp (name, "nobopt") == 0)
14932 mips_opts.nobopt = 1;
14934 else if (strcmp (name, "gp=default") == 0)
14935 mips_opts.gp32 = file_mips_gp32;
14936 else if (strcmp (name, "gp=32") == 0)
14937 mips_opts.gp32 = 1;
14938 else if (strcmp (name, "gp=64") == 0)
14940 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
14941 as_warn (_("%s isa does not support 64-bit registers"),
14942 mips_cpu_info_from_isa (mips_opts.isa)->name);
14943 mips_opts.gp32 = 0;
14945 else if (strcmp (name, "fp=default") == 0)
14946 mips_opts.fp32 = file_mips_fp32;
14947 else if (strcmp (name, "fp=32") == 0)
14948 mips_opts.fp32 = 1;
14949 else if (strcmp (name, "fp=64") == 0)
14951 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14952 as_warn (_("%s isa does not support 64-bit floating point registers"),
14953 mips_cpu_info_from_isa (mips_opts.isa)->name);
14954 mips_opts.fp32 = 0;
14956 else if (strcmp (name, "softfloat") == 0)
14957 mips_opts.soft_float = 1;
14958 else if (strcmp (name, "hardfloat") == 0)
14959 mips_opts.soft_float = 0;
14960 else if (strcmp (name, "singlefloat") == 0)
14961 mips_opts.single_float = 1;
14962 else if (strcmp (name, "doublefloat") == 0)
14963 mips_opts.single_float = 0;
14964 else if (strcmp (name, "mips16") == 0
14965 || strcmp (name, "MIPS-16") == 0)
14967 if (mips_opts.micromips == 1)
14968 as_fatal (_("`mips16' cannot be used with `micromips'"));
14969 mips_opts.mips16 = 1;
14971 else if (strcmp (name, "nomips16") == 0
14972 || strcmp (name, "noMIPS-16") == 0)
14973 mips_opts.mips16 = 0;
14974 else if (strcmp (name, "micromips") == 0)
14976 if (mips_opts.mips16 == 1)
14977 as_fatal (_("`micromips' cannot be used with `mips16'"));
14978 mips_opts.micromips = 1;
14980 else if (strcmp (name, "nomicromips") == 0)
14981 mips_opts.micromips = 0;
14982 else if (name[0] == 'n'
14984 && (ase = mips_lookup_ase (name + 2)))
14985 mips_set_ase (ase, FALSE);
14986 else if ((ase = mips_lookup_ase (name)))
14987 mips_set_ase (ase, TRUE);
14988 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
14992 /* Permit the user to change the ISA and architecture on the fly.
14993 Needless to say, misuse can cause serious problems. */
14994 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
14997 mips_opts.isa = file_mips_isa;
14998 mips_opts.arch = file_mips_arch;
15000 else if (strncmp (name, "arch=", 5) == 0)
15002 const struct mips_cpu_info *p;
15004 p = mips_parse_cpu("internal use", name + 5);
15006 as_bad (_("unknown architecture %s"), name + 5);
15009 mips_opts.arch = p->cpu;
15010 mips_opts.isa = p->isa;
15013 else if (strncmp (name, "mips", 4) == 0)
15015 const struct mips_cpu_info *p;
15017 p = mips_parse_cpu("internal use", name);
15019 as_bad (_("unknown ISA level %s"), name + 4);
15022 mips_opts.arch = p->cpu;
15023 mips_opts.isa = p->isa;
15027 as_bad (_("unknown ISA or architecture %s"), name);
15029 switch (mips_opts.isa)
15037 mips_opts.gp32 = 1;
15038 mips_opts.fp32 = 1;
15045 mips_opts.gp32 = 0;
15046 if (mips_opts.arch == CPU_R5900)
15048 mips_opts.fp32 = 1;
15052 mips_opts.fp32 = 0;
15056 as_bad (_("unknown ISA level %s"), name + 4);
15061 mips_opts.gp32 = file_mips_gp32;
15062 mips_opts.fp32 = file_mips_fp32;
15065 else if (strcmp (name, "autoextend") == 0)
15066 mips_opts.noautoextend = 0;
15067 else if (strcmp (name, "noautoextend") == 0)
15068 mips_opts.noautoextend = 1;
15069 else if (strcmp (name, "insn32") == 0)
15070 mips_opts.insn32 = TRUE;
15071 else if (strcmp (name, "noinsn32") == 0)
15072 mips_opts.insn32 = FALSE;
15073 else if (strcmp (name, "push") == 0)
15075 struct mips_option_stack *s;
15077 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15078 s->next = mips_opts_stack;
15079 s->options = mips_opts;
15080 mips_opts_stack = s;
15082 else if (strcmp (name, "pop") == 0)
15084 struct mips_option_stack *s;
15086 s = mips_opts_stack;
15088 as_bad (_(".set pop with no .set push"));
15091 /* If we're changing the reorder mode we need to handle
15092 delay slots correctly. */
15093 if (s->options.noreorder && ! mips_opts.noreorder)
15094 start_noreorder ();
15095 else if (! s->options.noreorder && mips_opts.noreorder)
15098 mips_opts = s->options;
15099 mips_opts_stack = s->next;
15103 else if (strcmp (name, "sym32") == 0)
15104 mips_opts.sym32 = TRUE;
15105 else if (strcmp (name, "nosym32") == 0)
15106 mips_opts.sym32 = FALSE;
15107 else if (strchr (name, ','))
15109 /* Generic ".set" directive; use the generic handler. */
15110 *input_line_pointer = ch;
15111 input_line_pointer = name;
15117 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
15119 mips_check_isa_supports_ases ();
15120 *input_line_pointer = ch;
15121 demand_empty_rest_of_line ();
15124 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15125 .option pic2. It means to generate SVR4 PIC calls. */
15128 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15130 mips_pic = SVR4_PIC;
15131 mips_abicalls = TRUE;
15133 if (g_switch_seen && g_switch_value != 0)
15134 as_warn (_("-G may not be used with SVR4 PIC code"));
15135 g_switch_value = 0;
15137 bfd_set_gp_size (stdoutput, 0);
15138 demand_empty_rest_of_line ();
15141 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15142 PIC code. It sets the $gp register for the function based on the
15143 function address, which is in the register named in the argument.
15144 This uses a relocation against _gp_disp, which is handled specially
15145 by the linker. The result is:
15146 lui $gp,%hi(_gp_disp)
15147 addiu $gp,$gp,%lo(_gp_disp)
15148 addu $gp,$gp,.cpload argument
15149 The .cpload argument is normally $25 == $t9.
15151 The -mno-shared option changes this to:
15152 lui $gp,%hi(__gnu_local_gp)
15153 addiu $gp,$gp,%lo(__gnu_local_gp)
15154 and the argument is ignored. This saves an instruction, but the
15155 resulting code is not position independent; it uses an absolute
15156 address for __gnu_local_gp. Thus code assembled with -mno-shared
15157 can go into an ordinary executable, but not into a shared library. */
15160 s_cpload (int ignore ATTRIBUTE_UNUSED)
15166 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15167 .cpload is ignored. */
15168 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15174 if (mips_opts.mips16)
15176 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15177 ignore_rest_of_line ();
15181 /* .cpload should be in a .set noreorder section. */
15182 if (mips_opts.noreorder == 0)
15183 as_warn (_(".cpload not in noreorder section"));
15185 reg = tc_get_register (0);
15187 /* If we need to produce a 64-bit address, we are better off using
15188 the default instruction sequence. */
15189 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15191 ex.X_op = O_symbol;
15192 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15194 ex.X_op_symbol = NULL;
15195 ex.X_add_number = 0;
15197 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15198 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15200 mips_mark_labels ();
15201 mips_assembling_insn = TRUE;
15204 macro_build_lui (&ex, mips_gp_register);
15205 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15206 mips_gp_register, BFD_RELOC_LO16);
15208 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15209 mips_gp_register, reg);
15212 mips_assembling_insn = FALSE;
15213 demand_empty_rest_of_line ();
15216 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15217 .cpsetup $reg1, offset|$reg2, label
15219 If offset is given, this results in:
15220 sd $gp, offset($sp)
15221 lui $gp, %hi(%neg(%gp_rel(label)))
15222 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15223 daddu $gp, $gp, $reg1
15225 If $reg2 is given, this results in:
15226 daddu $reg2, $gp, $0
15227 lui $gp, %hi(%neg(%gp_rel(label)))
15228 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15229 daddu $gp, $gp, $reg1
15230 $reg1 is normally $25 == $t9.
15232 The -mno-shared option replaces the last three instructions with
15234 addiu $gp,$gp,%lo(_gp) */
15237 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
15239 expressionS ex_off;
15240 expressionS ex_sym;
15243 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15244 We also need NewABI support. */
15245 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15251 if (mips_opts.mips16)
15253 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15254 ignore_rest_of_line ();
15258 reg1 = tc_get_register (0);
15259 SKIP_WHITESPACE ();
15260 if (*input_line_pointer != ',')
15262 as_bad (_("missing argument separator ',' for .cpsetup"));
15266 ++input_line_pointer;
15267 SKIP_WHITESPACE ();
15268 if (*input_line_pointer == '$')
15270 mips_cpreturn_register = tc_get_register (0);
15271 mips_cpreturn_offset = -1;
15275 mips_cpreturn_offset = get_absolute_expression ();
15276 mips_cpreturn_register = -1;
15278 SKIP_WHITESPACE ();
15279 if (*input_line_pointer != ',')
15281 as_bad (_("missing argument separator ',' for .cpsetup"));
15285 ++input_line_pointer;
15286 SKIP_WHITESPACE ();
15287 expression (&ex_sym);
15289 mips_mark_labels ();
15290 mips_assembling_insn = TRUE;
15293 if (mips_cpreturn_register == -1)
15295 ex_off.X_op = O_constant;
15296 ex_off.X_add_symbol = NULL;
15297 ex_off.X_op_symbol = NULL;
15298 ex_off.X_add_number = mips_cpreturn_offset;
15300 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15301 BFD_RELOC_LO16, SP);
15304 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
15305 mips_gp_register, 0);
15307 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15309 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15310 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15313 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15314 mips_gp_register, -1, BFD_RELOC_GPREL16,
15315 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15317 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15318 mips_gp_register, reg1);
15324 ex.X_op = O_symbol;
15325 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15326 ex.X_op_symbol = NULL;
15327 ex.X_add_number = 0;
15329 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15330 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15332 macro_build_lui (&ex, mips_gp_register);
15333 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15334 mips_gp_register, BFD_RELOC_LO16);
15339 mips_assembling_insn = FALSE;
15340 demand_empty_rest_of_line ();
15344 s_cplocal (int ignore ATTRIBUTE_UNUSED)
15346 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15347 .cplocal is ignored. */
15348 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15354 if (mips_opts.mips16)
15356 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15357 ignore_rest_of_line ();
15361 mips_gp_register = tc_get_register (0);
15362 demand_empty_rest_of_line ();
15365 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15366 offset from $sp. The offset is remembered, and after making a PIC
15367 call $gp is restored from that location. */
15370 s_cprestore (int ignore ATTRIBUTE_UNUSED)
15374 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15375 .cprestore is ignored. */
15376 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15382 if (mips_opts.mips16)
15384 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15385 ignore_rest_of_line ();
15389 mips_cprestore_offset = get_absolute_expression ();
15390 mips_cprestore_valid = 1;
15392 ex.X_op = O_constant;
15393 ex.X_add_symbol = NULL;
15394 ex.X_op_symbol = NULL;
15395 ex.X_add_number = mips_cprestore_offset;
15397 mips_mark_labels ();
15398 mips_assembling_insn = TRUE;
15401 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15402 SP, HAVE_64BIT_ADDRESSES);
15405 mips_assembling_insn = FALSE;
15406 demand_empty_rest_of_line ();
15409 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15410 was given in the preceding .cpsetup, it results in:
15411 ld $gp, offset($sp)
15413 If a register $reg2 was given there, it results in:
15414 daddu $gp, $reg2, $0 */
15417 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
15421 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15422 We also need NewABI support. */
15423 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15429 if (mips_opts.mips16)
15431 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15432 ignore_rest_of_line ();
15436 mips_mark_labels ();
15437 mips_assembling_insn = TRUE;
15440 if (mips_cpreturn_register == -1)
15442 ex.X_op = O_constant;
15443 ex.X_add_symbol = NULL;
15444 ex.X_op_symbol = NULL;
15445 ex.X_add_number = mips_cpreturn_offset;
15447 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
15450 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
15451 mips_cpreturn_register, 0);
15454 mips_assembling_insn = FALSE;
15455 demand_empty_rest_of_line ();
15458 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15459 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15460 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15461 debug information or MIPS16 TLS. */
15464 s_tls_rel_directive (const size_t bytes, const char *dirstr,
15465 bfd_reloc_code_real_type rtype)
15472 if (ex.X_op != O_symbol)
15474 as_bad (_("unsupported use of %s"), dirstr);
15475 ignore_rest_of_line ();
15478 p = frag_more (bytes);
15479 md_number_to_chars (p, 0, bytes);
15480 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
15481 demand_empty_rest_of_line ();
15482 mips_clear_insn_labels ();
15485 /* Handle .dtprelword. */
15488 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15490 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
15493 /* Handle .dtpreldword. */
15496 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15498 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15501 /* Handle .tprelword. */
15504 s_tprelword (int ignore ATTRIBUTE_UNUSED)
15506 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15509 /* Handle .tpreldword. */
15512 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15514 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
15517 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15518 code. It sets the offset to use in gp_rel relocations. */
15521 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
15523 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15524 We also need NewABI support. */
15525 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15531 mips_gprel_offset = get_absolute_expression ();
15533 demand_empty_rest_of_line ();
15536 /* Handle the .gpword pseudo-op. This is used when generating PIC
15537 code. It generates a 32 bit GP relative reloc. */
15540 s_gpword (int ignore ATTRIBUTE_UNUSED)
15542 segment_info_type *si;
15543 struct insn_label_list *l;
15547 /* When not generating PIC code, this is treated as .word. */
15548 if (mips_pic != SVR4_PIC)
15554 si = seg_info (now_seg);
15555 l = si->label_list;
15556 mips_emit_delays ();
15558 mips_align (2, 0, l);
15561 mips_clear_insn_labels ();
15563 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15565 as_bad (_("unsupported use of .gpword"));
15566 ignore_rest_of_line ();
15570 md_number_to_chars (p, 0, 4);
15571 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15572 BFD_RELOC_GPREL32);
15574 demand_empty_rest_of_line ();
15578 s_gpdword (int ignore ATTRIBUTE_UNUSED)
15580 segment_info_type *si;
15581 struct insn_label_list *l;
15585 /* When not generating PIC code, this is treated as .dword. */
15586 if (mips_pic != SVR4_PIC)
15592 si = seg_info (now_seg);
15593 l = si->label_list;
15594 mips_emit_delays ();
15596 mips_align (3, 0, l);
15599 mips_clear_insn_labels ();
15601 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15603 as_bad (_("unsupported use of .gpdword"));
15604 ignore_rest_of_line ();
15608 md_number_to_chars (p, 0, 8);
15609 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15610 BFD_RELOC_GPREL32)->fx_tcbit = 1;
15612 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15613 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15614 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
15616 demand_empty_rest_of_line ();
15619 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15620 tables. It generates a R_MIPS_EH reloc. */
15623 s_ehword (int ignore ATTRIBUTE_UNUSED)
15628 mips_emit_delays ();
15631 mips_clear_insn_labels ();
15633 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15635 as_bad (_("unsupported use of .ehword"));
15636 ignore_rest_of_line ();
15640 md_number_to_chars (p, 0, 4);
15641 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15642 BFD_RELOC_MIPS_EH);
15644 demand_empty_rest_of_line ();
15647 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15648 tables in SVR4 PIC code. */
15651 s_cpadd (int ignore ATTRIBUTE_UNUSED)
15655 /* This is ignored when not generating SVR4 PIC code. */
15656 if (mips_pic != SVR4_PIC)
15662 mips_mark_labels ();
15663 mips_assembling_insn = TRUE;
15665 /* Add $gp to the register named as an argument. */
15667 reg = tc_get_register (0);
15668 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
15671 mips_assembling_insn = FALSE;
15672 demand_empty_rest_of_line ();
15675 /* Handle the .insn pseudo-op. This marks instruction labels in
15676 mips16/micromips mode. This permits the linker to handle them specially,
15677 such as generating jalx instructions when needed. We also make
15678 them odd for the duration of the assembly, in order to generate the
15679 right sort of code. We will make them even in the adjust_symtab
15680 routine, while leaving them marked. This is convenient for the
15681 debugger and the disassembler. The linker knows to make them odd
15685 s_insn (int ignore ATTRIBUTE_UNUSED)
15687 mips_mark_labels ();
15689 demand_empty_rest_of_line ();
15692 /* Handle the .nan pseudo-op. */
15695 s_nan (int ignore ATTRIBUTE_UNUSED)
15697 static const char str_legacy[] = "legacy";
15698 static const char str_2008[] = "2008";
15701 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15703 if (i == sizeof (str_2008) - 1
15704 && memcmp (input_line_pointer, str_2008, i) == 0)
15705 mips_flag_nan2008 = TRUE;
15706 else if (i == sizeof (str_legacy) - 1
15707 && memcmp (input_line_pointer, str_legacy, i) == 0)
15708 mips_flag_nan2008 = FALSE;
15710 as_bad (_("bad .nan directive"));
15712 input_line_pointer += i;
15713 demand_empty_rest_of_line ();
15716 /* Handle a .stab[snd] directive. Ideally these directives would be
15717 implemented in a transparent way, so that removing them would not
15718 have any effect on the generated instructions. However, s_stab
15719 internally changes the section, so in practice we need to decide
15720 now whether the preceding label marks compressed code. We do not
15721 support changing the compression mode of a label after a .stab*
15722 directive, such as in:
15728 so the current mode wins. */
15731 s_mips_stab (int type)
15733 mips_mark_labels ();
15737 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15740 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
15747 name = input_line_pointer;
15748 c = get_symbol_end ();
15749 symbolP = symbol_find_or_make (name);
15750 S_SET_WEAK (symbolP);
15751 *input_line_pointer = c;
15753 SKIP_WHITESPACE ();
15755 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15757 if (S_IS_DEFINED (symbolP))
15759 as_bad (_("ignoring attempt to redefine symbol %s"),
15760 S_GET_NAME (symbolP));
15761 ignore_rest_of_line ();
15765 if (*input_line_pointer == ',')
15767 ++input_line_pointer;
15768 SKIP_WHITESPACE ();
15772 if (exp.X_op != O_symbol)
15774 as_bad (_("bad .weakext directive"));
15775 ignore_rest_of_line ();
15778 symbol_set_value_expression (symbolP, &exp);
15781 demand_empty_rest_of_line ();
15784 /* Parse a register string into a number. Called from the ECOFF code
15785 to parse .frame. The argument is non-zero if this is the frame
15786 register, so that we can record it in mips_frame_reg. */
15789 tc_get_register (int frame)
15793 SKIP_WHITESPACE ();
15794 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
15798 mips_frame_reg = reg != 0 ? reg : SP;
15799 mips_frame_reg_valid = 1;
15800 mips_cprestore_valid = 0;
15806 md_section_align (asection *seg, valueT addr)
15808 int align = bfd_get_section_alignment (stdoutput, seg);
15810 /* We don't need to align ELF sections to the full alignment.
15811 However, Irix 5 may prefer that we align them at least to a 16
15812 byte boundary. We don't bother to align the sections if we
15813 are targeted for an embedded system. */
15814 if (strncmp (TARGET_OS, "elf", 3) == 0)
15819 return ((addr + (1 << align) - 1) & (-1 << align));
15822 /* Utility routine, called from above as well. If called while the
15823 input file is still being read, it's only an approximation. (For
15824 example, a symbol may later become defined which appeared to be
15825 undefined earlier.) */
15828 nopic_need_relax (symbolS *sym, int before_relaxing)
15833 if (g_switch_value > 0)
15835 const char *symname;
15838 /* Find out whether this symbol can be referenced off the $gp
15839 register. It can be if it is smaller than the -G size or if
15840 it is in the .sdata or .sbss section. Certain symbols can
15841 not be referenced off the $gp, although it appears as though
15843 symname = S_GET_NAME (sym);
15844 if (symname != (const char *) NULL
15845 && (strcmp (symname, "eprol") == 0
15846 || strcmp (symname, "etext") == 0
15847 || strcmp (symname, "_gp") == 0
15848 || strcmp (symname, "edata") == 0
15849 || strcmp (symname, "_fbss") == 0
15850 || strcmp (symname, "_fdata") == 0
15851 || strcmp (symname, "_ftext") == 0
15852 || strcmp (symname, "end") == 0
15853 || strcmp (symname, "_gp_disp") == 0))
15855 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15857 #ifndef NO_ECOFF_DEBUGGING
15858 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15859 && (symbol_get_obj (sym)->ecoff_extern_size
15860 <= g_switch_value))
15862 /* We must defer this decision until after the whole
15863 file has been read, since there might be a .extern
15864 after the first use of this symbol. */
15865 || (before_relaxing
15866 #ifndef NO_ECOFF_DEBUGGING
15867 && symbol_get_obj (sym)->ecoff_extern_size == 0
15869 && S_GET_VALUE (sym) == 0)
15870 || (S_GET_VALUE (sym) != 0
15871 && S_GET_VALUE (sym) <= g_switch_value)))
15875 const char *segname;
15877 segname = segment_name (S_GET_SEGMENT (sym));
15878 gas_assert (strcmp (segname, ".lit8") != 0
15879 && strcmp (segname, ".lit4") != 0);
15880 change = (strcmp (segname, ".sdata") != 0
15881 && strcmp (segname, ".sbss") != 0
15882 && strncmp (segname, ".sdata.", 7) != 0
15883 && strncmp (segname, ".sbss.", 6) != 0
15884 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
15885 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
15890 /* We are not optimizing for the $gp register. */
15895 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15898 pic_need_relax (symbolS *sym, asection *segtype)
15902 /* Handle the case of a symbol equated to another symbol. */
15903 while (symbol_equated_reloc_p (sym))
15907 /* It's possible to get a loop here in a badly written program. */
15908 n = symbol_get_value_expression (sym)->X_add_symbol;
15914 if (symbol_section_p (sym))
15917 symsec = S_GET_SEGMENT (sym);
15919 /* This must duplicate the test in adjust_reloc_syms. */
15920 return (!bfd_is_und_section (symsec)
15921 && !bfd_is_abs_section (symsec)
15922 && !bfd_is_com_section (symsec)
15923 && !s_is_linkonce (sym, segtype)
15924 /* A global or weak symbol is treated as external. */
15925 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
15929 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15930 extended opcode. SEC is the section the frag is in. */
15933 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
15936 const struct mips_int_operand *operand;
15941 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
15943 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
15946 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
15947 operand = mips16_immed_operand (type, FALSE);
15949 sym_frag = symbol_get_frag (fragp->fr_symbol);
15950 val = S_GET_VALUE (fragp->fr_symbol);
15951 symsec = S_GET_SEGMENT (fragp->fr_symbol);
15953 if (operand->root.type == OP_PCREL)
15955 const struct mips_pcrel_operand *pcrel_op;
15959 /* We won't have the section when we are called from
15960 mips_relax_frag. However, we will always have been called
15961 from md_estimate_size_before_relax first. If this is a
15962 branch to a different section, we mark it as such. If SEC is
15963 NULL, and the frag is not marked, then it must be a branch to
15964 the same section. */
15965 pcrel_op = (const struct mips_pcrel_operand *) operand;
15968 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
15973 /* Must have been called from md_estimate_size_before_relax. */
15976 fragp->fr_subtype =
15977 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15979 /* FIXME: We should support this, and let the linker
15980 catch branches and loads that are out of range. */
15981 as_bad_where (fragp->fr_file, fragp->fr_line,
15982 _("unsupported PC relative reference to different section"));
15986 if (fragp != sym_frag && sym_frag->fr_address == 0)
15987 /* Assume non-extended on the first relaxation pass.
15988 The address we have calculated will be bogus if this is
15989 a forward branch to another frag, as the forward frag
15990 will have fr_address == 0. */
15994 /* In this case, we know for sure that the symbol fragment is in
15995 the same section. If the relax_marker of the symbol fragment
15996 differs from the relax_marker of this fragment, we have not
15997 yet adjusted the symbol fragment fr_address. We want to add
15998 in STRETCH in order to get a better estimate of the address.
15999 This particularly matters because of the shift bits. */
16001 && sym_frag->relax_marker != fragp->relax_marker)
16005 /* Adjust stretch for any alignment frag. Note that if have
16006 been expanding the earlier code, the symbol may be
16007 defined in what appears to be an earlier frag. FIXME:
16008 This doesn't handle the fr_subtype field, which specifies
16009 a maximum number of bytes to skip when doing an
16011 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16013 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16016 stretch = - ((- stretch)
16017 & ~ ((1 << (int) f->fr_offset) - 1));
16019 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16028 addr = fragp->fr_address + fragp->fr_fix;
16030 /* The base address rules are complicated. The base address of
16031 a branch is the following instruction. The base address of a
16032 PC relative load or add is the instruction itself, but if it
16033 is in a delay slot (in which case it can not be extended) use
16034 the address of the instruction whose delay slot it is in. */
16035 if (pcrel_op->include_isa_bit)
16039 /* If we are currently assuming that this frag should be
16040 extended, then, the current address is two bytes
16042 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16045 /* Ignore the low bit in the target, since it will be set
16046 for a text label. */
16049 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16051 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16054 val -= addr & -(1 << pcrel_op->align_log2);
16056 /* If any of the shifted bits are set, we must use an extended
16057 opcode. If the address depends on the size of this
16058 instruction, this can lead to a loop, so we arrange to always
16059 use an extended opcode. We only check this when we are in
16060 the main relaxation loop, when SEC is NULL. */
16061 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
16063 fragp->fr_subtype =
16064 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16068 /* If we are about to mark a frag as extended because the value
16069 is precisely the next value above maxtiny, then there is a
16070 chance of an infinite loop as in the following code:
16075 In this case when the la is extended, foo is 0x3fc bytes
16076 away, so the la can be shrunk, but then foo is 0x400 away, so
16077 the la must be extended. To avoid this loop, we mark the
16078 frag as extended if it was small, and is about to become
16079 extended with the next value above maxtiny. */
16080 maxtiny = mips_int_operand_max (operand);
16081 if (val == maxtiny + (1 << operand->shift)
16082 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16085 fragp->fr_subtype =
16086 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16090 else if (symsec != absolute_section && sec != NULL)
16091 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16093 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16096 /* Compute the length of a branch sequence, and adjust the
16097 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16098 worst-case length is computed, with UPDATE being used to indicate
16099 whether an unconditional (-1), branch-likely (+1) or regular (0)
16100 branch is to be computed. */
16102 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16104 bfd_boolean toofar;
16108 && S_IS_DEFINED (fragp->fr_symbol)
16109 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16114 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16116 addr = fragp->fr_address + fragp->fr_fix + 4;
16120 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16123 /* If the symbol is not defined or it's in a different segment,
16124 assume the user knows what's going on and emit a short
16130 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16132 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16133 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16134 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16135 RELAX_BRANCH_LINK (fragp->fr_subtype),
16141 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16144 if (mips_pic != NO_PIC)
16146 /* Additional space for PIC loading of target address. */
16148 if (mips_opts.isa == ISA_MIPS1)
16149 /* Additional space for $at-stabilizing nop. */
16153 /* If branch is conditional. */
16154 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16161 /* Compute the length of a branch sequence, and adjust the
16162 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16163 worst-case length is computed, with UPDATE being used to indicate
16164 whether an unconditional (-1), or regular (0) branch is to be
16168 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16170 bfd_boolean toofar;
16174 && S_IS_DEFINED (fragp->fr_symbol)
16175 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16180 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16181 /* Ignore the low bit in the target, since it will be set
16182 for a text label. */
16183 if ((val & 1) != 0)
16186 addr = fragp->fr_address + fragp->fr_fix + 4;
16190 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16193 /* If the symbol is not defined or it's in a different segment,
16194 assume the user knows what's going on and emit a short
16200 if (fragp && update
16201 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16202 fragp->fr_subtype = (toofar
16203 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16204 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16209 bfd_boolean compact_known = fragp != NULL;
16210 bfd_boolean compact = FALSE;
16211 bfd_boolean uncond;
16214 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16216 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16218 uncond = update < 0;
16220 /* If label is out of range, we turn branch <br>:
16222 <br> label # 4 bytes
16228 nop # 2 bytes if compact && !PIC
16231 if (mips_pic == NO_PIC && (!compact_known || compact))
16234 /* If assembling PIC code, we further turn:
16240 lw/ld at, %got(label)(gp) # 4 bytes
16241 d/addiu at, %lo(label) # 4 bytes
16244 if (mips_pic != NO_PIC)
16247 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16249 <brneg> 0f # 4 bytes
16250 nop # 2 bytes if !compact
16253 length += (compact_known && compact) ? 4 : 6;
16259 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16260 bit accordingly. */
16263 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16265 bfd_boolean toofar;
16268 && S_IS_DEFINED (fragp->fr_symbol)
16269 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16275 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16276 /* Ignore the low bit in the target, since it will be set
16277 for a text label. */
16278 if ((val & 1) != 0)
16281 /* Assume this is a 2-byte branch. */
16282 addr = fragp->fr_address + fragp->fr_fix + 2;
16284 /* We try to avoid the infinite loop by not adding 2 more bytes for
16289 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16291 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16292 else if (type == 'E')
16293 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16298 /* If the symbol is not defined or it's in a different segment,
16299 we emit a normal 32-bit branch. */
16302 if (fragp && update
16303 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16305 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16306 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16314 /* Estimate the size of a frag before relaxing. Unless this is the
16315 mips16, we are not really relaxing here, and the final size is
16316 encoded in the subtype information. For the mips16, we have to
16317 decide whether we are using an extended opcode or not. */
16320 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
16324 if (RELAX_BRANCH_P (fragp->fr_subtype))
16327 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16329 return fragp->fr_var;
16332 if (RELAX_MIPS16_P (fragp->fr_subtype))
16333 /* We don't want to modify the EXTENDED bit here; it might get us
16334 into infinite loops. We change it only in mips_relax_frag(). */
16335 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
16337 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16341 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16342 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16343 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16344 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16345 fragp->fr_var = length;
16350 if (mips_pic == NO_PIC)
16351 change = nopic_need_relax (fragp->fr_symbol, 0);
16352 else if (mips_pic == SVR4_PIC)
16353 change = pic_need_relax (fragp->fr_symbol, segtype);
16354 else if (mips_pic == VXWORKS_PIC)
16355 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16362 fragp->fr_subtype |= RELAX_USE_SECOND;
16363 return -RELAX_FIRST (fragp->fr_subtype);
16366 return -RELAX_SECOND (fragp->fr_subtype);
16369 /* This is called to see whether a reloc against a defined symbol
16370 should be converted into a reloc against a section. */
16373 mips_fix_adjustable (fixS *fixp)
16375 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16376 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16379 if (fixp->fx_addsy == NULL)
16382 /* If symbol SYM is in a mergeable section, relocations of the form
16383 SYM + 0 can usually be made section-relative. The mergeable data
16384 is then identified by the section offset rather than by the symbol.
16386 However, if we're generating REL LO16 relocations, the offset is split
16387 between the LO16 and parterning high part relocation. The linker will
16388 need to recalculate the complete offset in order to correctly identify
16391 The linker has traditionally not looked for the parterning high part
16392 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16393 placed anywhere. Rather than break backwards compatibility by changing
16394 this, it seems better not to force the issue, and instead keep the
16395 original symbol. This will work with either linker behavior. */
16396 if ((lo16_reloc_p (fixp->fx_r_type)
16397 || reloc_needs_lo_p (fixp->fx_r_type))
16398 && HAVE_IN_PLACE_ADDENDS
16399 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16402 /* There is no place to store an in-place offset for JALR relocations.
16403 Likewise an in-range offset of limited PC-relative relocations may
16404 overflow the in-place relocatable field if recalculated against the
16405 start address of the symbol's containing section. */
16406 if (HAVE_IN_PLACE_ADDENDS
16407 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16408 || jalr_reloc_p (fixp->fx_r_type)))
16411 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16412 to a floating-point stub. The same is true for non-R_MIPS16_26
16413 relocations against MIPS16 functions; in this case, the stub becomes
16414 the function's canonical address.
16416 Floating-point stubs are stored in unique .mips16.call.* or
16417 .mips16.fn.* sections. If a stub T for function F is in section S,
16418 the first relocation in section S must be against F; this is how the
16419 linker determines the target function. All relocations that might
16420 resolve to T must also be against F. We therefore have the following
16421 restrictions, which are given in an intentionally-redundant way:
16423 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16426 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16427 if that stub might be used.
16429 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16432 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16433 that stub might be used.
16435 There is a further restriction:
16437 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16438 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16439 targets with in-place addends; the relocation field cannot
16440 encode the low bit.
16442 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16443 against a MIPS16 symbol. We deal with (5) by by not reducing any
16444 such relocations on REL targets.
16446 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16447 relocation against some symbol R, no relocation against R may be
16448 reduced. (Note that this deals with (2) as well as (1) because
16449 relocations against global symbols will never be reduced on ELF
16450 targets.) This approach is a little simpler than trying to detect
16451 stub sections, and gives the "all or nothing" per-symbol consistency
16452 that we have for MIPS16 symbols. */
16453 if (fixp->fx_subsy == NULL
16454 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
16455 || *symbol_get_tc (fixp->fx_addsy)
16456 || (HAVE_IN_PLACE_ADDENDS
16457 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16458 && jmp_reloc_p (fixp->fx_r_type))))
16464 /* Translate internal representation of relocation info to BFD target
16468 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
16470 static arelent *retval[4];
16472 bfd_reloc_code_real_type code;
16474 memset (retval, 0, sizeof(retval));
16475 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
16476 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16477 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
16478 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16480 if (fixp->fx_pcrel)
16482 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16483 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16484 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
16485 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16486 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
16488 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16489 Relocations want only the symbol offset. */
16490 reloc->addend = fixp->fx_addnumber + reloc->address;
16493 reloc->addend = fixp->fx_addnumber;
16495 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16496 entry to be used in the relocation's section offset. */
16497 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16499 reloc->address = reloc->addend;
16503 code = fixp->fx_r_type;
16505 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
16506 if (reloc->howto == NULL)
16508 as_bad_where (fixp->fx_file, fixp->fx_line,
16509 _("cannot represent %s relocation in this object file"
16511 bfd_get_reloc_code_name (code));
16518 /* Relax a machine dependent frag. This returns the amount by which
16519 the current size of the frag should change. */
16522 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
16524 if (RELAX_BRANCH_P (fragp->fr_subtype))
16526 offsetT old_var = fragp->fr_var;
16528 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
16530 return fragp->fr_var - old_var;
16533 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16535 offsetT old_var = fragp->fr_var;
16536 offsetT new_var = 4;
16538 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16539 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16540 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16541 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16542 fragp->fr_var = new_var;
16544 return new_var - old_var;
16547 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16550 if (mips16_extended_frag (fragp, NULL, stretch))
16552 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16554 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16559 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16561 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16568 /* Convert a machine dependent frag. */
16571 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
16573 if (RELAX_BRANCH_P (fragp->fr_subtype))
16576 unsigned long insn;
16580 buf = fragp->fr_literal + fragp->fr_fix;
16581 insn = read_insn (buf);
16583 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16585 /* We generate a fixup instead of applying it right now
16586 because, if there are linker relaxations, we're going to
16587 need the relocations. */
16588 exp.X_op = O_symbol;
16589 exp.X_add_symbol = fragp->fr_symbol;
16590 exp.X_add_number = fragp->fr_offset;
16592 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16593 BFD_RELOC_16_PCREL_S2);
16594 fixp->fx_file = fragp->fr_file;
16595 fixp->fx_line = fragp->fr_line;
16597 buf = write_insn (buf, insn);
16603 as_warn_where (fragp->fr_file, fragp->fr_line,
16604 _("relaxed out-of-range branch into a jump"));
16606 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16609 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16611 /* Reverse the branch. */
16612 switch ((insn >> 28) & 0xf)
16615 if ((insn & 0xff000000) == 0x47000000
16616 || (insn & 0xff600000) == 0x45600000)
16618 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
16619 reversed by tweaking bit 23. */
16620 insn ^= 0x00800000;
16624 /* bc[0-3][tf]l? instructions can have the condition
16625 reversed by tweaking a single TF bit, and their
16626 opcodes all have 0x4???????. */
16627 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16628 insn ^= 0x00010000;
16633 /* bltz 0x04000000 bgez 0x04010000
16634 bltzal 0x04100000 bgezal 0x04110000 */
16635 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
16636 insn ^= 0x00010000;
16640 /* beq 0x10000000 bne 0x14000000
16641 blez 0x18000000 bgtz 0x1c000000 */
16642 insn ^= 0x04000000;
16650 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16652 /* Clear the and-link bit. */
16653 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
16655 /* bltzal 0x04100000 bgezal 0x04110000
16656 bltzall 0x04120000 bgezall 0x04130000 */
16657 insn &= ~0x00100000;
16660 /* Branch over the branch (if the branch was likely) or the
16661 full jump (not likely case). Compute the offset from the
16662 current instruction to branch to. */
16663 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16667 /* How many bytes in instructions we've already emitted? */
16668 i = buf - fragp->fr_literal - fragp->fr_fix;
16669 /* How many bytes in instructions from here to the end? */
16670 i = fragp->fr_var - i;
16672 /* Convert to instruction count. */
16674 /* Branch counts from the next instruction. */
16677 /* Branch over the jump. */
16678 buf = write_insn (buf, insn);
16681 buf = write_insn (buf, 0);
16683 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16685 /* beql $0, $0, 2f */
16687 /* Compute the PC offset from the current instruction to
16688 the end of the variable frag. */
16689 /* How many bytes in instructions we've already emitted? */
16690 i = buf - fragp->fr_literal - fragp->fr_fix;
16691 /* How many bytes in instructions from here to the end? */
16692 i = fragp->fr_var - i;
16693 /* Convert to instruction count. */
16695 /* Don't decrement i, because we want to branch over the
16699 buf = write_insn (buf, insn);
16700 buf = write_insn (buf, 0);
16704 if (mips_pic == NO_PIC)
16707 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16708 ? 0x0c000000 : 0x08000000);
16709 exp.X_op = O_symbol;
16710 exp.X_add_symbol = fragp->fr_symbol;
16711 exp.X_add_number = fragp->fr_offset;
16713 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16714 FALSE, BFD_RELOC_MIPS_JMP);
16715 fixp->fx_file = fragp->fr_file;
16716 fixp->fx_line = fragp->fr_line;
16718 buf = write_insn (buf, insn);
16722 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16724 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16725 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16726 insn |= at << OP_SH_RT;
16727 exp.X_op = O_symbol;
16728 exp.X_add_symbol = fragp->fr_symbol;
16729 exp.X_add_number = fragp->fr_offset;
16731 if (fragp->fr_offset)
16733 exp.X_add_symbol = make_expr_symbol (&exp);
16734 exp.X_add_number = 0;
16737 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16738 FALSE, BFD_RELOC_MIPS_GOT16);
16739 fixp->fx_file = fragp->fr_file;
16740 fixp->fx_line = fragp->fr_line;
16742 buf = write_insn (buf, insn);
16744 if (mips_opts.isa == ISA_MIPS1)
16746 buf = write_insn (buf, 0);
16748 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16749 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16750 insn |= at << OP_SH_RS | at << OP_SH_RT;
16752 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16753 FALSE, BFD_RELOC_LO16);
16754 fixp->fx_file = fragp->fr_file;
16755 fixp->fx_line = fragp->fr_line;
16757 buf = write_insn (buf, insn);
16760 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16764 insn |= at << OP_SH_RS;
16766 buf = write_insn (buf, insn);
16770 fragp->fr_fix += fragp->fr_var;
16771 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16775 /* Relax microMIPS branches. */
16776 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16778 char *buf = fragp->fr_literal + fragp->fr_fix;
16779 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16780 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16781 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16782 bfd_boolean short_ds;
16783 unsigned long insn;
16787 exp.X_op = O_symbol;
16788 exp.X_add_symbol = fragp->fr_symbol;
16789 exp.X_add_number = fragp->fr_offset;
16791 fragp->fr_fix += fragp->fr_var;
16793 /* Handle 16-bit branches that fit or are forced to fit. */
16794 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16796 /* We generate a fixup instead of applying it right now,
16797 because if there is linker relaxation, we're going to
16798 need the relocations. */
16800 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16801 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16802 else if (type == 'E')
16803 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16804 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16808 fixp->fx_file = fragp->fr_file;
16809 fixp->fx_line = fragp->fr_line;
16811 /* These relocations can have an addend that won't fit in
16813 fixp->fx_no_overflow = 1;
16818 /* Handle 32-bit branches that fit or are forced to fit. */
16819 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16820 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16822 /* We generate a fixup instead of applying it right now,
16823 because if there is linker relaxation, we're going to
16824 need the relocations. */
16825 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16826 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16827 fixp->fx_file = fragp->fr_file;
16828 fixp->fx_line = fragp->fr_line;
16834 /* Relax 16-bit branches to 32-bit branches. */
16837 insn = read_compressed_insn (buf, 2);
16839 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16840 insn = 0x94000000; /* beq */
16841 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16843 unsigned long regno;
16845 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16846 regno = micromips_to_32_reg_d_map [regno];
16847 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16848 insn |= regno << MICROMIPSOP_SH_RS;
16853 /* Nothing else to do, just write it out. */
16854 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16855 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16857 buf = write_compressed_insn (buf, insn, 4);
16858 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16863 insn = read_compressed_insn (buf, 4);
16865 /* Relax 32-bit branches to a sequence of instructions. */
16866 as_warn_where (fragp->fr_file, fragp->fr_line,
16867 _("relaxed out-of-range branch into a jump"));
16869 /* Set the short-delay-slot bit. */
16870 short_ds = al && (insn & 0x02000000) != 0;
16872 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16876 /* Reverse the branch. */
16877 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16878 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16879 insn ^= 0x20000000;
16880 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16881 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16882 || (insn & 0xffe00000) == 0x40800000 /* blez */
16883 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16884 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16885 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16886 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16887 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16888 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16889 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16890 insn ^= 0x00400000;
16891 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16892 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16893 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16894 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16895 insn ^= 0x00200000;
16896 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
16898 || (insn & 0xff600000) == 0x81600000) /* BZ.V
16900 insn ^= 0x00800000;
16906 /* Clear the and-link and short-delay-slot bits. */
16907 gas_assert ((insn & 0xfda00000) == 0x40200000);
16909 /* bltzal 0x40200000 bgezal 0x40600000 */
16910 /* bltzals 0x42200000 bgezals 0x42600000 */
16911 insn &= ~0x02200000;
16914 /* Make a label at the end for use with the branch. */
16915 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
16916 micromips_label_inc ();
16917 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
16920 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
16921 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16922 fixp->fx_file = fragp->fr_file;
16923 fixp->fx_line = fragp->fr_line;
16925 /* Branch over the jump. */
16926 buf = write_compressed_insn (buf, insn, 4);
16929 buf = write_compressed_insn (buf, 0x0c00, 2);
16932 if (mips_pic == NO_PIC)
16934 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
16936 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16937 insn = al ? jal : 0xd4000000;
16939 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16940 BFD_RELOC_MICROMIPS_JMP);
16941 fixp->fx_file = fragp->fr_file;
16942 fixp->fx_line = fragp->fr_line;
16944 buf = write_compressed_insn (buf, insn, 4);
16947 buf = write_compressed_insn (buf, 0x0c00, 2);
16951 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
16952 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
16953 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
16955 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16956 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
16957 insn |= at << MICROMIPSOP_SH_RT;
16959 if (exp.X_add_number)
16961 exp.X_add_symbol = make_expr_symbol (&exp);
16962 exp.X_add_number = 0;
16965 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16966 BFD_RELOC_MICROMIPS_GOT16);
16967 fixp->fx_file = fragp->fr_file;
16968 fixp->fx_line = fragp->fr_line;
16970 buf = write_compressed_insn (buf, insn, 4);
16972 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16973 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
16974 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
16976 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16977 BFD_RELOC_MICROMIPS_LO16);
16978 fixp->fx_file = fragp->fr_file;
16979 fixp->fx_line = fragp->fr_line;
16981 buf = write_compressed_insn (buf, insn, 4);
16983 /* jr/jrc/jalr/jalrs $at */
16984 insn = al ? jalr : jr;
16985 insn |= at << MICROMIPSOP_SH_MJ;
16987 buf = write_compressed_insn (buf, insn, 2);
16990 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16994 if (RELAX_MIPS16_P (fragp->fr_subtype))
16997 const struct mips_int_operand *operand;
17000 unsigned int user_length, length;
17001 unsigned long insn;
17004 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17005 operand = mips16_immed_operand (type, FALSE);
17007 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17008 val = resolve_symbol_value (fragp->fr_symbol);
17009 if (operand->root.type == OP_PCREL)
17011 const struct mips_pcrel_operand *pcrel_op;
17014 pcrel_op = (const struct mips_pcrel_operand *) operand;
17015 addr = fragp->fr_address + fragp->fr_fix;
17017 /* The rules for the base address of a PC relative reloc are
17018 complicated; see mips16_extended_frag. */
17019 if (pcrel_op->include_isa_bit)
17024 /* Ignore the low bit in the target, since it will be
17025 set for a text label. */
17028 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17030 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17033 addr &= -(1 << pcrel_op->align_log2);
17036 /* Make sure the section winds up with the alignment we have
17038 if (operand->shift > 0)
17039 record_alignment (asec, operand->shift);
17043 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17044 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17045 as_warn_where (fragp->fr_file, fragp->fr_line,
17046 _("extended instruction in delay slot"));
17048 buf = fragp->fr_literal + fragp->fr_fix;
17050 insn = read_compressed_insn (buf, 2);
17052 insn |= MIPS16_EXTEND;
17054 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17056 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17061 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17062 BFD_RELOC_UNUSED, val, user_length, &insn);
17064 length = (ext ? 4 : 2);
17065 gas_assert (mips16_opcode_length (insn) == length);
17066 write_compressed_insn (buf, insn, length);
17067 fragp->fr_fix += length;
17071 relax_substateT subtype = fragp->fr_subtype;
17072 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17073 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17077 first = RELAX_FIRST (subtype);
17078 second = RELAX_SECOND (subtype);
17079 fixp = (fixS *) fragp->fr_opcode;
17081 /* If the delay slot chosen does not match the size of the instruction,
17082 then emit a warning. */
17083 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17084 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17089 s = subtype & (RELAX_DELAY_SLOT_16BIT
17090 | RELAX_DELAY_SLOT_SIZE_FIRST
17091 | RELAX_DELAY_SLOT_SIZE_SECOND);
17092 msg = macro_warning (s);
17094 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17098 /* Possibly emit a warning if we've chosen the longer option. */
17099 if (use_second == second_longer)
17105 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17106 msg = macro_warning (s);
17108 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17112 /* Go through all the fixups for the first sequence. Disable them
17113 (by marking them as done) if we're going to use the second
17114 sequence instead. */
17116 && fixp->fx_frag == fragp
17117 && fixp->fx_where < fragp->fr_fix - second)
17119 if (subtype & RELAX_USE_SECOND)
17121 fixp = fixp->fx_next;
17124 /* Go through the fixups for the second sequence. Disable them if
17125 we're going to use the first sequence, otherwise adjust their
17126 addresses to account for the relaxation. */
17127 while (fixp && fixp->fx_frag == fragp)
17129 if (subtype & RELAX_USE_SECOND)
17130 fixp->fx_where -= first;
17133 fixp = fixp->fx_next;
17136 /* Now modify the frag contents. */
17137 if (subtype & RELAX_USE_SECOND)
17141 start = fragp->fr_literal + fragp->fr_fix - first - second;
17142 memmove (start, start + first, second);
17143 fragp->fr_fix -= first;
17146 fragp->fr_fix -= second;
17150 /* This function is called after the relocs have been generated.
17151 We've been storing mips16 text labels as odd. Here we convert them
17152 back to even for the convenience of the debugger. */
17155 mips_frob_file_after_relocs (void)
17158 unsigned int count, i;
17160 syms = bfd_get_outsymbols (stdoutput);
17161 count = bfd_get_symcount (stdoutput);
17162 for (i = 0; i < count; i++, syms++)
17163 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17164 && ((*syms)->value & 1) != 0)
17166 (*syms)->value &= ~1;
17167 /* If the symbol has an odd size, it was probably computed
17168 incorrectly, so adjust that as well. */
17169 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17170 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17174 /* This function is called whenever a label is defined, including fake
17175 labels instantiated off the dot special symbol. It is used when
17176 handling branch delays; if a branch has a label, we assume we cannot
17177 move it. This also bumps the value of the symbol by 1 in compressed
17181 mips_record_label (symbolS *sym)
17183 segment_info_type *si = seg_info (now_seg);
17184 struct insn_label_list *l;
17186 if (free_insn_labels == NULL)
17187 l = (struct insn_label_list *) xmalloc (sizeof *l);
17190 l = free_insn_labels;
17191 free_insn_labels = l->next;
17195 l->next = si->label_list;
17196 si->label_list = l;
17199 /* This function is called as tc_frob_label() whenever a label is defined
17200 and adds a DWARF-2 record we only want for true labels. */
17203 mips_define_label (symbolS *sym)
17205 mips_record_label (sym);
17206 dwarf2_emit_label (sym);
17209 /* This function is called by tc_new_dot_label whenever a new dot symbol
17213 mips_add_dot_label (symbolS *sym)
17215 mips_record_label (sym);
17216 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17217 mips_compressed_mark_label (sym);
17220 /* Some special processing for a MIPS ELF file. */
17223 mips_elf_final_processing (void)
17225 /* Write out the register information. */
17226 if (mips_abi != N64_ABI)
17230 s.ri_gprmask = mips_gprmask;
17231 s.ri_cprmask[0] = mips_cprmask[0];
17232 s.ri_cprmask[1] = mips_cprmask[1];
17233 s.ri_cprmask[2] = mips_cprmask[2];
17234 s.ri_cprmask[3] = mips_cprmask[3];
17235 /* The gp_value field is set by the MIPS ELF backend. */
17237 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
17238 ((Elf32_External_RegInfo *)
17239 mips_regmask_frag));
17243 Elf64_Internal_RegInfo s;
17245 s.ri_gprmask = mips_gprmask;
17247 s.ri_cprmask[0] = mips_cprmask[0];
17248 s.ri_cprmask[1] = mips_cprmask[1];
17249 s.ri_cprmask[2] = mips_cprmask[2];
17250 s.ri_cprmask[3] = mips_cprmask[3];
17251 /* The gp_value field is set by the MIPS ELF backend. */
17253 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
17254 ((Elf64_External_RegInfo *)
17255 mips_regmask_frag));
17258 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17259 sort of BFD interface for this. */
17260 if (mips_any_noreorder)
17261 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
17262 if (mips_pic != NO_PIC)
17264 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
17265 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17268 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17270 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17271 defined at present; this might need to change in future. */
17272 if (file_ase_mips16)
17273 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
17274 if (file_ase_micromips)
17275 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
17276 if (file_ase & ASE_MDMX)
17277 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
17279 /* Set the MIPS ELF ABI flags. */
17280 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
17281 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
17282 else if (mips_abi == O64_ABI)
17283 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
17284 else if (mips_abi == EABI_ABI)
17286 if (!file_mips_gp32)
17287 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17289 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17291 else if (mips_abi == N32_ABI)
17292 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17294 /* Nothing to do for N64_ABI. */
17296 if (mips_32bitmode)
17297 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
17299 if (mips_flag_nan2008)
17300 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17302 /* 32 bit code with 64 bit FP registers. */
17303 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17304 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
17307 typedef struct proc {
17309 symbolS *func_end_sym;
17310 unsigned long reg_mask;
17311 unsigned long reg_offset;
17312 unsigned long fpreg_mask;
17313 unsigned long fpreg_offset;
17314 unsigned long frame_offset;
17315 unsigned long frame_reg;
17316 unsigned long pc_reg;
17319 static procS cur_proc;
17320 static procS *cur_proc_ptr;
17321 static int numprocs;
17323 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17324 as "2", and a normal nop as "0". */
17326 #define NOP_OPCODE_MIPS 0
17327 #define NOP_OPCODE_MIPS16 1
17328 #define NOP_OPCODE_MICROMIPS 2
17331 mips_nop_opcode (void)
17333 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17334 return NOP_OPCODE_MICROMIPS;
17335 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17336 return NOP_OPCODE_MIPS16;
17338 return NOP_OPCODE_MIPS;
17341 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17342 32-bit microMIPS NOPs here (if applicable). */
17345 mips_handle_align (fragS *fragp)
17349 int bytes, size, excess;
17352 if (fragp->fr_type != rs_align_code)
17355 p = fragp->fr_literal + fragp->fr_fix;
17357 switch (nop_opcode)
17359 case NOP_OPCODE_MICROMIPS:
17360 opcode = micromips_nop32_insn.insn_opcode;
17363 case NOP_OPCODE_MIPS16:
17364 opcode = mips16_nop_insn.insn_opcode;
17367 case NOP_OPCODE_MIPS:
17369 opcode = nop_insn.insn_opcode;
17374 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17375 excess = bytes % size;
17377 /* Handle the leading part if we're not inserting a whole number of
17378 instructions, and make it the end of the fixed part of the frag.
17379 Try to fit in a short microMIPS NOP if applicable and possible,
17380 and use zeroes otherwise. */
17381 gas_assert (excess < 4);
17382 fragp->fr_fix += excess;
17387 /* Fall through. */
17389 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
17391 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
17395 /* Fall through. */
17398 /* Fall through. */
17403 md_number_to_chars (p, opcode, size);
17404 fragp->fr_var = size;
17408 md_obj_begin (void)
17415 /* Check for premature end, nesting errors, etc. */
17417 as_warn (_("missing .end at end of assembly"));
17426 if (*input_line_pointer == '-')
17428 ++input_line_pointer;
17431 if (!ISDIGIT (*input_line_pointer))
17432 as_bad (_("expected simple number"));
17433 if (input_line_pointer[0] == '0')
17435 if (input_line_pointer[1] == 'x')
17437 input_line_pointer += 2;
17438 while (ISXDIGIT (*input_line_pointer))
17441 val |= hex_value (*input_line_pointer++);
17443 return negative ? -val : val;
17447 ++input_line_pointer;
17448 while (ISDIGIT (*input_line_pointer))
17451 val |= *input_line_pointer++ - '0';
17453 return negative ? -val : val;
17456 if (!ISDIGIT (*input_line_pointer))
17458 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17459 *input_line_pointer, *input_line_pointer);
17460 as_warn (_("invalid number"));
17463 while (ISDIGIT (*input_line_pointer))
17466 val += *input_line_pointer++ - '0';
17468 return negative ? -val : val;
17471 /* The .file directive; just like the usual .file directive, but there
17472 is an initial number which is the ECOFF file index. In the non-ECOFF
17473 case .file implies DWARF-2. */
17476 s_mips_file (int x ATTRIBUTE_UNUSED)
17478 static int first_file_directive = 0;
17480 if (ECOFF_DEBUGGING)
17489 filename = dwarf2_directive_file (0);
17491 /* Versions of GCC up to 3.1 start files with a ".file"
17492 directive even for stabs output. Make sure that this
17493 ".file" is handled. Note that you need a version of GCC
17494 after 3.1 in order to support DWARF-2 on MIPS. */
17495 if (filename != NULL && ! first_file_directive)
17497 (void) new_logical_line (filename, -1);
17498 s_app_file_string (filename, 0);
17500 first_file_directive = 1;
17504 /* The .loc directive, implying DWARF-2. */
17507 s_mips_loc (int x ATTRIBUTE_UNUSED)
17509 if (!ECOFF_DEBUGGING)
17510 dwarf2_directive_loc (0);
17513 /* The .end directive. */
17516 s_mips_end (int x ATTRIBUTE_UNUSED)
17520 /* Following functions need their own .frame and .cprestore directives. */
17521 mips_frame_reg_valid = 0;
17522 mips_cprestore_valid = 0;
17524 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17527 demand_empty_rest_of_line ();
17532 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17533 as_warn (_(".end not in text section"));
17537 as_warn (_(".end directive without a preceding .ent directive"));
17538 demand_empty_rest_of_line ();
17544 gas_assert (S_GET_NAME (p));
17545 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
17546 as_warn (_(".end symbol does not match .ent symbol"));
17548 if (debug_type == DEBUG_STABS)
17549 stabs_generate_asm_endfunc (S_GET_NAME (p),
17553 as_warn (_(".end directive missing or unknown symbol"));
17555 /* Create an expression to calculate the size of the function. */
17556 if (p && cur_proc_ptr)
17558 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17559 expressionS *exp = xmalloc (sizeof (expressionS));
17562 exp->X_op = O_subtract;
17563 exp->X_add_symbol = symbol_temp_new_now ();
17564 exp->X_op_symbol = p;
17565 exp->X_add_number = 0;
17567 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17570 /* Generate a .pdr section. */
17571 if (!ECOFF_DEBUGGING && mips_flag_pdr)
17573 segT saved_seg = now_seg;
17574 subsegT saved_subseg = now_subseg;
17578 #ifdef md_flush_pending_output
17579 md_flush_pending_output ();
17582 gas_assert (pdr_seg);
17583 subseg_set (pdr_seg, 0);
17585 /* Write the symbol. */
17586 exp.X_op = O_symbol;
17587 exp.X_add_symbol = p;
17588 exp.X_add_number = 0;
17589 emit_expr (&exp, 4);
17591 fragp = frag_more (7 * 4);
17593 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17594 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17595 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17596 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17597 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17598 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17599 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
17601 subseg_set (saved_seg, saved_subseg);
17604 cur_proc_ptr = NULL;
17607 /* The .aent and .ent directives. */
17610 s_mips_ent (int aent)
17614 symbolP = get_symbol ();
17615 if (*input_line_pointer == ',')
17616 ++input_line_pointer;
17617 SKIP_WHITESPACE ();
17618 if (ISDIGIT (*input_line_pointer)
17619 || *input_line_pointer == '-')
17622 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17623 as_warn (_(".ent or .aent not in text section"));
17625 if (!aent && cur_proc_ptr)
17626 as_warn (_("missing .end"));
17630 /* This function needs its own .frame and .cprestore directives. */
17631 mips_frame_reg_valid = 0;
17632 mips_cprestore_valid = 0;
17634 cur_proc_ptr = &cur_proc;
17635 memset (cur_proc_ptr, '\0', sizeof (procS));
17637 cur_proc_ptr->func_sym = symbolP;
17641 if (debug_type == DEBUG_STABS)
17642 stabs_generate_asm_func (S_GET_NAME (symbolP),
17643 S_GET_NAME (symbolP));
17646 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17648 demand_empty_rest_of_line ();
17651 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17652 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17653 s_mips_frame is used so that we can set the PDR information correctly.
17654 We can't use the ecoff routines because they make reference to the ecoff
17655 symbol table (in the mdebug section). */
17658 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
17660 if (ECOFF_DEBUGGING)
17666 if (cur_proc_ptr == (procS *) NULL)
17668 as_warn (_(".frame outside of .ent"));
17669 demand_empty_rest_of_line ();
17673 cur_proc_ptr->frame_reg = tc_get_register (1);
17675 SKIP_WHITESPACE ();
17676 if (*input_line_pointer++ != ','
17677 || get_absolute_expression_and_terminator (&val) != ',')
17679 as_warn (_("bad .frame directive"));
17680 --input_line_pointer;
17681 demand_empty_rest_of_line ();
17685 cur_proc_ptr->frame_offset = val;
17686 cur_proc_ptr->pc_reg = tc_get_register (0);
17688 demand_empty_rest_of_line ();
17692 /* The .fmask and .mask directives. If the mdebug section is present
17693 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17694 embedded targets, s_mips_mask is used so that we can set the PDR
17695 information correctly. We can't use the ecoff routines because they
17696 make reference to the ecoff symbol table (in the mdebug section). */
17699 s_mips_mask (int reg_type)
17701 if (ECOFF_DEBUGGING)
17702 s_ignore (reg_type);
17707 if (cur_proc_ptr == (procS *) NULL)
17709 as_warn (_(".mask/.fmask outside of .ent"));
17710 demand_empty_rest_of_line ();
17714 if (get_absolute_expression_and_terminator (&mask) != ',')
17716 as_warn (_("bad .mask/.fmask directive"));
17717 --input_line_pointer;
17718 demand_empty_rest_of_line ();
17722 off = get_absolute_expression ();
17724 if (reg_type == 'F')
17726 cur_proc_ptr->fpreg_mask = mask;
17727 cur_proc_ptr->fpreg_offset = off;
17731 cur_proc_ptr->reg_mask = mask;
17732 cur_proc_ptr->reg_offset = off;
17735 demand_empty_rest_of_line ();
17739 /* A table describing all the processors gas knows about. Names are
17740 matched in the order listed.
17742 To ease comparison, please keep this table in the same order as
17743 gcc's mips_cpu_info_table[]. */
17744 static const struct mips_cpu_info mips_cpu_info_table[] =
17746 /* Entries for generic ISAs */
17747 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17748 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17749 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17750 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17751 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17752 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17753 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17754 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17755 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
17758 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17759 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17760 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
17763 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
17766 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17767 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17768 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17769 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17770 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17771 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17772 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17773 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17774 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17775 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17776 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17777 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17778 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
17779 /* ST Microelectronics Loongson 2E and 2F cores */
17780 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17781 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
17784 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17785 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17786 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17787 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17788 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17789 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17790 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17791 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17792 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17793 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17794 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17795 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17796 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17797 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17798 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
17801 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17802 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17803 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17804 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
17806 /* MIPS 32 Release 2 */
17807 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17808 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17809 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17810 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17811 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17812 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17813 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17814 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17815 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17816 ISA_MIPS32R2, CPU_MIPS32R2 },
17817 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17818 ISA_MIPS32R2, CPU_MIPS32R2 },
17819 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17820 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17821 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17822 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17823 /* Deprecated forms of the above. */
17824 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17825 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17826 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17827 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17828 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17829 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17830 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17831 /* Deprecated forms of the above. */
17832 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17833 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17834 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17835 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17836 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17837 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17838 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17839 /* Deprecated forms of the above. */
17840 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17841 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17842 /* 34Kn is a 34kc without DSP. */
17843 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17844 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17845 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17846 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17847 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17848 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17849 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17850 /* Deprecated forms of the above. */
17851 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17852 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17853 /* 1004K cores are multiprocessor versions of the 34K. */
17854 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17855 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17856 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17857 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17860 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17861 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17862 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17863 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17865 /* Broadcom SB-1 CPU core */
17866 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17867 /* Broadcom SB-1A CPU core */
17868 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17870 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
17872 /* MIPS 64 Release 2 */
17874 /* Cavium Networks Octeon CPU core */
17875 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17876 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17877 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
17880 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
17883 XLP is mostly like XLR, with the prominent exception that it is
17884 MIPS64R2 rather than MIPS64. */
17885 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
17888 { NULL, 0, 0, 0, 0 }
17892 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17893 with a final "000" replaced by "k". Ignore case.
17895 Note: this function is shared between GCC and GAS. */
17898 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
17900 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17901 given++, canonical++;
17903 return ((*given == 0 && *canonical == 0)
17904 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17908 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17909 CPU name. We've traditionally allowed a lot of variation here.
17911 Note: this function is shared between GCC and GAS. */
17914 mips_matching_cpu_name_p (const char *canonical, const char *given)
17916 /* First see if the name matches exactly, or with a final "000"
17917 turned into "k". */
17918 if (mips_strict_matching_cpu_name_p (canonical, given))
17921 /* If not, try comparing based on numerical designation alone.
17922 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17923 if (TOLOWER (*given) == 'r')
17925 if (!ISDIGIT (*given))
17928 /* Skip over some well-known prefixes in the canonical name,
17929 hoping to find a number there too. */
17930 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
17932 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
17934 else if (TOLOWER (canonical[0]) == 'r')
17937 return mips_strict_matching_cpu_name_p (canonical, given);
17941 /* Parse an option that takes the name of a processor as its argument.
17942 OPTION is the name of the option and CPU_STRING is the argument.
17943 Return the corresponding processor enumeration if the CPU_STRING is
17944 recognized, otherwise report an error and return null.
17946 A similar function exists in GCC. */
17948 static const struct mips_cpu_info *
17949 mips_parse_cpu (const char *option, const char *cpu_string)
17951 const struct mips_cpu_info *p;
17953 /* 'from-abi' selects the most compatible architecture for the given
17954 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17955 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17956 version. Look first at the -mgp options, if given, otherwise base
17957 the choice on MIPS_DEFAULT_64BIT.
17959 Treat NO_ABI like the EABIs. One reason to do this is that the
17960 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17961 architecture. This code picks MIPS I for 'mips' and MIPS III for
17962 'mips64', just as we did in the days before 'from-abi'. */
17963 if (strcasecmp (cpu_string, "from-abi") == 0)
17965 if (ABI_NEEDS_32BIT_REGS (mips_abi))
17966 return mips_cpu_info_from_isa (ISA_MIPS1);
17968 if (ABI_NEEDS_64BIT_REGS (mips_abi))
17969 return mips_cpu_info_from_isa (ISA_MIPS3);
17971 if (file_mips_gp32 >= 0)
17972 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
17974 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17979 /* 'default' has traditionally been a no-op. Probably not very useful. */
17980 if (strcasecmp (cpu_string, "default") == 0)
17983 for (p = mips_cpu_info_table; p->name != 0; p++)
17984 if (mips_matching_cpu_name_p (p->name, cpu_string))
17987 as_bad (_("bad value (%s) for %s"), cpu_string, option);
17991 /* Return the canonical processor information for ISA (a member of the
17992 ISA_MIPS* enumeration). */
17994 static const struct mips_cpu_info *
17995 mips_cpu_info_from_isa (int isa)
17999 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18000 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18001 && isa == mips_cpu_info_table[i].isa)
18002 return (&mips_cpu_info_table[i]);
18007 static const struct mips_cpu_info *
18008 mips_cpu_info_from_arch (int arch)
18012 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18013 if (arch == mips_cpu_info_table[i].cpu)
18014 return (&mips_cpu_info_table[i]);
18020 show (FILE *stream, const char *string, int *col_p, int *first_p)
18024 fprintf (stream, "%24s", "");
18029 fprintf (stream, ", ");
18033 if (*col_p + strlen (string) > 72)
18035 fprintf (stream, "\n%24s", "");
18039 fprintf (stream, "%s", string);
18040 *col_p += strlen (string);
18046 md_show_usage (FILE *stream)
18051 fprintf (stream, _("\
18053 -EB generate big endian output\n\
18054 -EL generate little endian output\n\
18055 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18056 -G NUM allow referencing objects up to NUM bytes\n\
18057 implicitly with the gp register [default 8]\n"));
18058 fprintf (stream, _("\
18059 -mips1 generate MIPS ISA I instructions\n\
18060 -mips2 generate MIPS ISA II instructions\n\
18061 -mips3 generate MIPS ISA III instructions\n\
18062 -mips4 generate MIPS ISA IV instructions\n\
18063 -mips5 generate MIPS ISA V instructions\n\
18064 -mips32 generate MIPS32 ISA instructions\n\
18065 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18066 -mips64 generate MIPS64 ISA instructions\n\
18067 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18068 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18072 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18073 show (stream, mips_cpu_info_table[i].name, &column, &first);
18074 show (stream, "from-abi", &column, &first);
18075 fputc ('\n', stream);
18077 fprintf (stream, _("\
18078 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18079 -no-mCPU don't generate code specific to CPU.\n\
18080 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18084 show (stream, "3900", &column, &first);
18085 show (stream, "4010", &column, &first);
18086 show (stream, "4100", &column, &first);
18087 show (stream, "4650", &column, &first);
18088 fputc ('\n', stream);
18090 fprintf (stream, _("\
18091 -mips16 generate mips16 instructions\n\
18092 -no-mips16 do not generate mips16 instructions\n"));
18093 fprintf (stream, _("\
18094 -mmicromips generate microMIPS instructions\n\
18095 -mno-micromips do not generate microMIPS instructions\n"));
18096 fprintf (stream, _("\
18097 -msmartmips generate smartmips instructions\n\
18098 -mno-smartmips do not generate smartmips instructions\n"));
18099 fprintf (stream, _("\
18100 -mdsp generate DSP instructions\n\
18101 -mno-dsp do not generate DSP instructions\n"));
18102 fprintf (stream, _("\
18103 -mdspr2 generate DSP R2 instructions\n\
18104 -mno-dspr2 do not generate DSP R2 instructions\n"));
18105 fprintf (stream, _("\
18106 -mmt generate MT instructions\n\
18107 -mno-mt do not generate MT instructions\n"));
18108 fprintf (stream, _("\
18109 -mmcu generate MCU instructions\n\
18110 -mno-mcu do not generate MCU instructions\n"));
18111 fprintf (stream, _("\
18112 -mmsa generate MSA instructions\n\
18113 -mno-msa do not generate MSA instructions\n"));
18114 fprintf (stream, _("\
18115 -mvirt generate Virtualization instructions\n\
18116 -mno-virt do not generate Virtualization instructions\n"));
18117 fprintf (stream, _("\
18118 -minsn32 only generate 32-bit microMIPS instructions\n\
18119 -mno-insn32 generate all microMIPS instructions\n"));
18120 fprintf (stream, _("\
18121 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18122 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18123 -mfix-vr4120 work around certain VR4120 errata\n\
18124 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18125 -mfix-24k insert a nop after ERET and DERET instructions\n\
18126 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18127 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18128 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18129 -msym32 assume all symbols have 32-bit values\n\
18130 -O0 remove unneeded NOPs, do not swap branches\n\
18131 -O remove unneeded NOPs and swap branches\n\
18132 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18133 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18134 fprintf (stream, _("\
18135 -mhard-float allow floating-point instructions\n\
18136 -msoft-float do not allow floating-point instructions\n\
18137 -msingle-float only allow 32-bit floating-point operations\n\
18138 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18139 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18140 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18141 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18145 show (stream, "legacy", &column, &first);
18146 show (stream, "2008", &column, &first);
18148 fputc ('\n', stream);
18150 fprintf (stream, _("\
18151 -KPIC, -call_shared generate SVR4 position independent code\n\
18152 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18153 -mvxworks-pic generate VxWorks position independent code\n\
18154 -non_shared do not generate code that can operate with DSOs\n\
18155 -xgot assume a 32 bit GOT\n\
18156 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18157 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18158 position dependent (non shared) code\n\
18159 -mabi=ABI create ABI conformant object file for:\n"));
18163 show (stream, "32", &column, &first);
18164 show (stream, "o64", &column, &first);
18165 show (stream, "n32", &column, &first);
18166 show (stream, "64", &column, &first);
18167 show (stream, "eabi", &column, &first);
18169 fputc ('\n', stream);
18171 fprintf (stream, _("\
18172 -32 create o32 ABI object file (default)\n\
18173 -n32 create n32 ABI object file\n\
18174 -64 create 64 ABI object file\n"));
18179 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
18181 if (HAVE_64BIT_SYMBOLS)
18182 return dwarf2_format_64bit_irix;
18184 return dwarf2_format_32bit;
18189 mips_dwarf2_addr_size (void)
18191 if (HAVE_64BIT_OBJECTS)
18197 /* Standard calling conventions leave the CFA at SP on entry. */
18199 mips_cfi_frame_initial_instructions (void)
18201 cfi_add_CFA_def_cfa_register (SP);
18205 tc_mips_regname_to_dw2regnum (char *regname)
18207 unsigned int regnum = -1;
18210 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))