1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug = -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr = FALSE;
82 int mips_flag_pdr = TRUE;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode *insn_mo;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p : 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p : 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p : 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi = NO_ABI;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls = FALSE;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared = TRUE;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32 = -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32 = -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float = 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float = 0;
265 static struct mips_set_options mips_opts =
267 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
272 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask;
279 unsigned long mips_cprmask[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa = ISA_UNKNOWN;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch = CPU_UNKNOWN;
333 static const char *mips_arch_string;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune = CPU_UNKNOWN;
338 static const char *mips_tune_string;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode = 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if CPU does not implement the all the coprocessor insns. For these
451 CPUs only those COP insns are accepted that are explicitly marked to be
452 available on the CPU. ISA membership for COP insns is ignored. */
453 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R10000 \
474 || mips_opts.arch == CPU_R12000 \
475 || mips_opts.arch == CPU_R14000 \
476 || mips_opts.arch == CPU_R16000 \
477 || mips_opts.arch == CPU_RM7000 \
478 || mips_opts.arch == CPU_VR5500 \
481 /* Whether the processor uses hardware interlocks to protect reads
482 from the GPRs after they are loaded from memory, and thus does not
483 require nops to be inserted. This applies to instructions marked
484 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
486 #define gpr_interlocks \
487 (mips_opts.isa != ISA_MIPS1 \
488 || mips_opts.arch == CPU_R3900)
490 /* Whether the processor uses hardware interlocks to avoid delays
491 required by coprocessor instructions, and thus does not require
492 nops to be inserted. This applies to instructions marked
493 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
494 between instructions marked INSN_WRITE_COND_CODE and ones marked
495 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
496 levels I, II, and III. */
497 /* Itbl support may require additional care here. */
498 #define cop_interlocks \
499 ((mips_opts.isa != ISA_MIPS1 \
500 && mips_opts.isa != ISA_MIPS2 \
501 && mips_opts.isa != ISA_MIPS3) \
502 || mips_opts.arch == CPU_R4300 \
505 /* Whether the processor uses hardware interlocks to protect reads
506 from coprocessor registers after they are loaded from memory, and
507 thus does not require nops to be inserted. This applies to
508 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
509 requires at MIPS ISA level I. */
510 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
512 /* Is this a mfhi or mflo instruction? */
513 #define MF_HILO_INSN(PINFO) \
514 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
516 /* Returns true for a (non floating-point) coprocessor instruction. Reading
517 or writing the condition code is only possible on the coprocessors and
518 these insns are not marked with INSN_COP. Thus for these insns use the
519 condition-code flags. */
520 #define COP_INSN(PINFO) \
521 (PINFO != INSN_MACRO \
522 && ((PINFO) & (FP_S | FP_D)) == 0 \
523 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
525 /* MIPS PIC level. */
527 enum mips_pic_level mips_pic;
529 /* 1 if we should generate 32 bit offsets from the $gp register in
530 SVR4_PIC mode. Currently has no meaning in other modes. */
531 static int mips_big_got = 0;
533 /* 1 if trap instructions should used for overflow rather than break
535 static int mips_trap = 0;
537 /* 1 if double width floating point constants should not be constructed
538 by assembling two single width halves into two single width floating
539 point registers which just happen to alias the double width destination
540 register. On some architectures this aliasing can be disabled by a bit
541 in the status register, and the setting of this bit cannot be determined
542 automatically at assemble time. */
543 static int mips_disable_float_construction;
545 /* Non-zero if any .set noreorder directives were used. */
547 static int mips_any_noreorder;
549 /* Non-zero if nops should be inserted when the register referenced in
550 an mfhi/mflo instruction is read in the next two instructions. */
551 static int mips_7000_hilo_fix;
553 /* The size of objects in the small data section. */
554 static unsigned int g_switch_value = 8;
555 /* Whether the -G option was used. */
556 static int g_switch_seen = 0;
561 /* If we can determine in advance that GP optimization won't be
562 possible, we can skip the relaxation stuff that tries to produce
563 GP-relative references. This makes delay slot optimization work
566 This function can only provide a guess, but it seems to work for
567 gcc output. It needs to guess right for gcc, otherwise gcc
568 will put what it thinks is a GP-relative instruction in a branch
571 I don't know if a fix is needed for the SVR4_PIC mode. I've only
572 fixed it for the non-PIC mode. KR 95/04/07 */
573 static int nopic_need_relax (symbolS *, int);
575 /* handle of the OPCODE hash table */
576 static struct hash_control *op_hash = NULL;
578 /* The opcode hash table we use for the mips16. */
579 static struct hash_control *mips16_op_hash = NULL;
581 /* This array holds the chars that always start a comment. If the
582 pre-processor is disabled, these aren't very useful */
583 const char comment_chars[] = "#";
585 /* This array holds the chars that only start a comment at the beginning of
586 a line. If the line seems to have the form '# 123 filename'
587 .line and .file directives will appear in the pre-processed output */
588 /* Note that input_file.c hand checks for '#' at the beginning of the
589 first line of the input file. This is because the compiler outputs
590 #NO_APP at the beginning of its output. */
591 /* Also note that C style comments are always supported. */
592 const char line_comment_chars[] = "#";
594 /* This array holds machine specific line separator characters. */
595 const char line_separator_chars[] = ";";
597 /* Chars that can be used to separate mant from exp in floating point nums */
598 const char EXP_CHARS[] = "eE";
600 /* Chars that mean this number is a floating point constant */
603 const char FLT_CHARS[] = "rRsSfFdDxXpP";
605 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
606 changed in read.c . Ideally it shouldn't have to know about it at all,
607 but nothing is ideal around here.
610 static char *insn_error;
612 static int auto_align = 1;
614 /* When outputting SVR4 PIC code, the assembler needs to know the
615 offset in the stack frame from which to restore the $gp register.
616 This is set by the .cprestore pseudo-op, and saved in this
618 static offsetT mips_cprestore_offset = -1;
620 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
621 more optimizations, it can use a register value instead of a memory-saved
622 offset and even an other register than $gp as global pointer. */
623 static offsetT mips_cpreturn_offset = -1;
624 static int mips_cpreturn_register = -1;
625 static int mips_gp_register = GP;
626 static int mips_gprel_offset = 0;
628 /* Whether mips_cprestore_offset has been set in the current function
629 (or whether it has already been warned about, if not). */
630 static int mips_cprestore_valid = 0;
632 /* This is the register which holds the stack frame, as set by the
633 .frame pseudo-op. This is needed to implement .cprestore. */
634 static int mips_frame_reg = SP;
636 /* Whether mips_frame_reg has been set in the current function
637 (or whether it has already been warned about, if not). */
638 static int mips_frame_reg_valid = 0;
640 /* To output NOP instructions correctly, we need to keep information
641 about the previous two instructions. */
643 /* Whether we are optimizing. The default value of 2 means to remove
644 unneeded NOPs and swap branch instructions when possible. A value
645 of 1 means to not swap branches. A value of 0 means to always
647 static int mips_optimize = 2;
649 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
650 equivalent to seeing no -g option at all. */
651 static int mips_debug = 0;
653 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
654 #define MAX_VR4130_NOPS 4
656 /* The maximum number of NOPs needed to fill delay slots. */
657 #define MAX_DELAY_NOPS 2
659 /* The maximum number of NOPs needed for any purpose. */
662 /* A list of previous instructions, with index 0 being the most recent.
663 We need to look back MAX_NOPS instructions when filling delay slots
664 or working around processor errata. We need to look back one
665 instruction further if we're thinking about using history[0] to
666 fill a branch delay slot. */
667 static struct mips_cl_insn history[1 + MAX_NOPS];
669 /* Nop instructions used by emit_nop. */
670 static struct mips_cl_insn nop_insn, mips16_nop_insn;
672 /* The appropriate nop for the current mode. */
673 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
675 /* If this is set, it points to a frag holding nop instructions which
676 were inserted before the start of a noreorder section. If those
677 nops turn out to be unnecessary, the size of the frag can be
679 static fragS *prev_nop_frag;
681 /* The number of nop instructions we created in prev_nop_frag. */
682 static int prev_nop_frag_holds;
684 /* The number of nop instructions that we know we need in
686 static int prev_nop_frag_required;
688 /* The number of instructions we've seen since prev_nop_frag. */
689 static int prev_nop_frag_since;
691 /* For ECOFF and ELF, relocations against symbols are done in two
692 parts, with a HI relocation and a LO relocation. Each relocation
693 has only 16 bits of space to store an addend. This means that in
694 order for the linker to handle carries correctly, it must be able
695 to locate both the HI and the LO relocation. This means that the
696 relocations must appear in order in the relocation table.
698 In order to implement this, we keep track of each unmatched HI
699 relocation. We then sort them so that they immediately precede the
700 corresponding LO relocation. */
705 struct mips_hi_fixup *next;
708 /* The section this fixup is in. */
712 /* The list of unmatched HI relocs. */
714 static struct mips_hi_fixup *mips_hi_fixup_list;
716 /* The frag containing the last explicit relocation operator.
717 Null if explicit relocations have not been used. */
719 static fragS *prev_reloc_op_frag;
721 /* Map normal MIPS register numbers to mips16 register numbers. */
723 #define X ILLEGAL_REG
724 static const int mips32_to_16_reg_map[] =
726 X, X, 2, 3, 4, 5, 6, 7,
727 X, X, X, X, X, X, X, X,
728 0, 1, X, X, X, X, X, X,
729 X, X, X, X, X, X, X, X
733 /* Map mips16 register numbers to normal MIPS register numbers. */
735 static const unsigned int mips16_to_32_reg_map[] =
737 16, 17, 2, 3, 4, 5, 6, 7
740 /* Classifies the kind of instructions we're interested in when
741 implementing -mfix-vr4120. */
742 enum fix_vr4120_class {
749 NUM_FIX_VR4120_CLASSES
752 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
753 there must be at least one other instruction between an instruction
754 of type X and an instruction of type Y. */
755 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
757 /* True if -mfix-vr4120 is in force. */
758 static int mips_fix_vr4120;
760 /* ...likewise -mfix-vr4130. */
761 static int mips_fix_vr4130;
763 /* ...likewise -mfix-24k. */
764 static int mips_fix_24k;
766 /* We don't relax branches by default, since this causes us to expand
767 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
768 fail to compute the offset before expanding the macro to the most
769 efficient expansion. */
771 static int mips_relax_branch;
773 /* The expansion of many macros depends on the type of symbol that
774 they refer to. For example, when generating position-dependent code,
775 a macro that refers to a symbol may have two different expansions,
776 one which uses GP-relative addresses and one which uses absolute
777 addresses. When generating SVR4-style PIC, a macro may have
778 different expansions for local and global symbols.
780 We handle these situations by generating both sequences and putting
781 them in variant frags. In position-dependent code, the first sequence
782 will be the GP-relative one and the second sequence will be the
783 absolute one. In SVR4 PIC, the first sequence will be for global
784 symbols and the second will be for local symbols.
786 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
787 SECOND are the lengths of the two sequences in bytes. These fields
788 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
789 the subtype has the following flags:
792 Set if it has been decided that we should use the second
793 sequence instead of the first.
796 Set in the first variant frag if the macro's second implementation
797 is longer than its first. This refers to the macro as a whole,
798 not an individual relaxation.
801 Set in the first variant frag if the macro appeared in a .set nomacro
802 block and if one alternative requires a warning but the other does not.
805 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
808 The frag's "opcode" points to the first fixup for relaxable code.
810 Relaxable macros are generated using a sequence such as:
812 relax_start (SYMBOL);
813 ... generate first expansion ...
815 ... generate second expansion ...
818 The code and fixups for the unwanted alternative are discarded
819 by md_convert_frag. */
820 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
822 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
823 #define RELAX_SECOND(X) ((X) & 0xff)
824 #define RELAX_USE_SECOND 0x10000
825 #define RELAX_SECOND_LONGER 0x20000
826 #define RELAX_NOMACRO 0x40000
827 #define RELAX_DELAY_SLOT 0x80000
829 /* Branch without likely bit. If label is out of range, we turn:
831 beq reg1, reg2, label
841 with the following opcode replacements:
848 bltzal <-> bgezal (with jal label instead of j label)
850 Even though keeping the delay slot instruction in the delay slot of
851 the branch would be more efficient, it would be very tricky to do
852 correctly, because we'd have to introduce a variable frag *after*
853 the delay slot instruction, and expand that instead. Let's do it
854 the easy way for now, even if the branch-not-taken case now costs
855 one additional instruction. Out-of-range branches are not supposed
856 to be common, anyway.
858 Branch likely. If label is out of range, we turn:
860 beql reg1, reg2, label
861 delay slot (annulled if branch not taken)
870 delay slot (executed only if branch taken)
873 It would be possible to generate a shorter sequence by losing the
874 likely bit, generating something like:
879 delay slot (executed only if branch taken)
891 bltzall -> bgezal (with jal label instead of j label)
892 bgezall -> bltzal (ditto)
895 but it's not clear that it would actually improve performance. */
896 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
899 | ((toofar) ? 1 : 0) \
901 | ((likely) ? 4 : 0) \
902 | ((uncond) ? 8 : 0)))
903 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
904 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
905 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
906 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
907 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
909 /* For mips16 code, we use an entirely different form of relaxation.
910 mips16 supports two versions of most instructions which take
911 immediate values: a small one which takes some small value, and a
912 larger one which takes a 16 bit value. Since branches also follow
913 this pattern, relaxing these values is required.
915 We can assemble both mips16 and normal MIPS code in a single
916 object. Therefore, we need to support this type of relaxation at
917 the same time that we support the relaxation described above. We
918 use the high bit of the subtype field to distinguish these cases.
920 The information we store for this type of relaxation is the
921 argument code found in the opcode file for this relocation, whether
922 the user explicitly requested a small or extended form, and whether
923 the relocation is in a jump or jal delay slot. That tells us the
924 size of the value, and how it should be stored. We also store
925 whether the fragment is considered to be extended or not. We also
926 store whether this is known to be a branch to a different section,
927 whether we have tried to relax this frag yet, and whether we have
928 ever extended a PC relative fragment because of a shift count. */
929 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
932 | ((small) ? 0x100 : 0) \
933 | ((ext) ? 0x200 : 0) \
934 | ((dslot) ? 0x400 : 0) \
935 | ((jal_dslot) ? 0x800 : 0))
936 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
937 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
938 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
939 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
940 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
941 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
942 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
943 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
944 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
945 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
946 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
947 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
949 /* Is the given value a sign-extended 32-bit value? */
950 #define IS_SEXT_32BIT_NUM(x) \
951 (((x) &~ (offsetT) 0x7fffffff) == 0 \
952 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
954 /* Is the given value a sign-extended 16-bit value? */
955 #define IS_SEXT_16BIT_NUM(x) \
956 (((x) &~ (offsetT) 0x7fff) == 0 \
957 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
959 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
960 #define IS_ZEXT_32BIT_NUM(x) \
961 (((x) &~ (offsetT) 0xffffffff) == 0 \
962 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
964 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
965 VALUE << SHIFT. VALUE is evaluated exactly once. */
966 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
967 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
968 | (((VALUE) & (MASK)) << (SHIFT)))
970 /* Extract bits MASK << SHIFT from STRUCT and shift them right
972 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
973 (((STRUCT) >> (SHIFT)) & (MASK))
975 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
976 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
978 include/opcode/mips.h specifies operand fields using the macros
979 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
980 with "MIPS16OP" instead of "OP". */
981 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
982 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
983 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
984 INSERT_BITS ((INSN).insn_opcode, VALUE, \
985 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
987 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
988 #define EXTRACT_OPERAND(FIELD, INSN) \
989 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
990 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
991 EXTRACT_BITS ((INSN).insn_opcode, \
992 MIPS16OP_MASK_##FIELD, \
995 /* Global variables used when generating relaxable macros. See the
996 comment above RELAX_ENCODE for more details about how relaxation
999 /* 0 if we're not emitting a relaxable macro.
1000 1 if we're emitting the first of the two relaxation alternatives.
1001 2 if we're emitting the second alternative. */
1004 /* The first relaxable fixup in the current frag. (In other words,
1005 the first fixup that refers to relaxable code.) */
1008 /* sizes[0] says how many bytes of the first alternative are stored in
1009 the current frag. Likewise sizes[1] for the second alternative. */
1010 unsigned int sizes[2];
1012 /* The symbol on which the choice of sequence depends. */
1016 /* Global variables used to decide whether a macro needs a warning. */
1018 /* True if the macro is in a branch delay slot. */
1019 bfd_boolean delay_slot_p;
1021 /* For relaxable macros, sizes[0] is the length of the first alternative
1022 in bytes and sizes[1] is the length of the second alternative.
1023 For non-relaxable macros, both elements give the length of the
1025 unsigned int sizes[2];
1027 /* The first variant frag for this macro. */
1029 } mips_macro_warning;
1031 /* Prototypes for static functions. */
1033 #define internalError() \
1034 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1036 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1038 static void append_insn
1039 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
1040 static void mips_no_prev_insn (void);
1041 static void mips16_macro_build
1042 (expressionS *, const char *, const char *, va_list);
1043 static void load_register (int, expressionS *, int);
1044 static void macro_start (void);
1045 static void macro_end (void);
1046 static void macro (struct mips_cl_insn * ip);
1047 static void mips16_macro (struct mips_cl_insn * ip);
1048 #ifdef LOSING_COMPILER
1049 static void macro2 (struct mips_cl_insn * ip);
1051 static void mips_ip (char *str, struct mips_cl_insn * ip);
1052 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1053 static void mips16_immed
1054 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1055 unsigned long *, bfd_boolean *, unsigned short *);
1056 static size_t my_getSmallExpression
1057 (expressionS *, bfd_reloc_code_real_type *, char *);
1058 static void my_getExpression (expressionS *, char *);
1059 static void s_align (int);
1060 static void s_change_sec (int);
1061 static void s_change_section (int);
1062 static void s_cons (int);
1063 static void s_float_cons (int);
1064 static void s_mips_globl (int);
1065 static void s_option (int);
1066 static void s_mipsset (int);
1067 static void s_abicalls (int);
1068 static void s_cpload (int);
1069 static void s_cpsetup (int);
1070 static void s_cplocal (int);
1071 static void s_cprestore (int);
1072 static void s_cpreturn (int);
1073 static void s_dtprelword (int);
1074 static void s_dtpreldword (int);
1075 static void s_gpvalue (int);
1076 static void s_gpword (int);
1077 static void s_gpdword (int);
1078 static void s_cpadd (int);
1079 static void s_insn (int);
1080 static void md_obj_begin (void);
1081 static void md_obj_end (void);
1082 static void s_mips_ent (int);
1083 static void s_mips_end (int);
1084 static void s_mips_frame (int);
1085 static void s_mips_mask (int reg_type);
1086 static void s_mips_stab (int);
1087 static void s_mips_weakext (int);
1088 static void s_mips_file (int);
1089 static void s_mips_loc (int);
1090 static bfd_boolean pic_need_relax (symbolS *, asection *);
1091 static int relaxed_branch_length (fragS *, asection *, int);
1092 static int validate_mips_insn (const struct mips_opcode *);
1094 /* Table and functions used to map between CPU/ISA names, and
1095 ISA levels, and CPU numbers. */
1097 struct mips_cpu_info
1099 const char *name; /* CPU or ISA name. */
1100 int flags; /* ASEs available, or ISA flag. */
1101 int isa; /* ISA level. */
1102 int cpu; /* CPU number (default CPU if ISA). */
1105 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1106 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1107 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1108 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1109 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1110 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1111 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1113 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1114 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1115 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1119 The following pseudo-ops from the Kane and Heinrich MIPS book
1120 should be defined here, but are currently unsupported: .alias,
1121 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1123 The following pseudo-ops from the Kane and Heinrich MIPS book are
1124 specific to the type of debugging information being generated, and
1125 should be defined by the object format: .aent, .begin, .bend,
1126 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1129 The following pseudo-ops from the Kane and Heinrich MIPS book are
1130 not MIPS CPU specific, but are also not specific to the object file
1131 format. This file is probably the best place to define them, but
1132 they are not currently supported: .asm0, .endr, .lab, .struct. */
1134 static const pseudo_typeS mips_pseudo_table[] =
1136 /* MIPS specific pseudo-ops. */
1137 {"option", s_option, 0},
1138 {"set", s_mipsset, 0},
1139 {"rdata", s_change_sec, 'r'},
1140 {"sdata", s_change_sec, 's'},
1141 {"livereg", s_ignore, 0},
1142 {"abicalls", s_abicalls, 0},
1143 {"cpload", s_cpload, 0},
1144 {"cpsetup", s_cpsetup, 0},
1145 {"cplocal", s_cplocal, 0},
1146 {"cprestore", s_cprestore, 0},
1147 {"cpreturn", s_cpreturn, 0},
1148 {"dtprelword", s_dtprelword, 0},
1149 {"dtpreldword", s_dtpreldword, 0},
1150 {"gpvalue", s_gpvalue, 0},
1151 {"gpword", s_gpword, 0},
1152 {"gpdword", s_gpdword, 0},
1153 {"cpadd", s_cpadd, 0},
1154 {"insn", s_insn, 0},
1156 /* Relatively generic pseudo-ops that happen to be used on MIPS
1158 {"asciiz", stringer, 8 + 1},
1159 {"bss", s_change_sec, 'b'},
1161 {"half", s_cons, 1},
1162 {"dword", s_cons, 3},
1163 {"weakext", s_mips_weakext, 0},
1164 {"origin", s_org, 0},
1165 {"repeat", s_rept, 0},
1167 /* These pseudo-ops are defined in read.c, but must be overridden
1168 here for one reason or another. */
1169 {"align", s_align, 0},
1170 {"byte", s_cons, 0},
1171 {"data", s_change_sec, 'd'},
1172 {"double", s_float_cons, 'd'},
1173 {"float", s_float_cons, 'f'},
1174 {"globl", s_mips_globl, 0},
1175 {"global", s_mips_globl, 0},
1176 {"hword", s_cons, 1},
1178 {"long", s_cons, 2},
1179 {"octa", s_cons, 4},
1180 {"quad", s_cons, 3},
1181 {"section", s_change_section, 0},
1182 {"short", s_cons, 1},
1183 {"single", s_float_cons, 'f'},
1184 {"stabn", s_mips_stab, 'n'},
1185 {"text", s_change_sec, 't'},
1186 {"word", s_cons, 2},
1188 { "extern", ecoff_directive_extern, 0},
1193 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1195 /* These pseudo-ops should be defined by the object file format.
1196 However, a.out doesn't support them, so we have versions here. */
1197 {"aent", s_mips_ent, 1},
1198 {"bgnb", s_ignore, 0},
1199 {"end", s_mips_end, 0},
1200 {"endb", s_ignore, 0},
1201 {"ent", s_mips_ent, 0},
1202 {"file", s_mips_file, 0},
1203 {"fmask", s_mips_mask, 'F'},
1204 {"frame", s_mips_frame, 0},
1205 {"loc", s_mips_loc, 0},
1206 {"mask", s_mips_mask, 'R'},
1207 {"verstamp", s_ignore, 0},
1211 extern void pop_insert (const pseudo_typeS *);
1214 mips_pop_insert (void)
1216 pop_insert (mips_pseudo_table);
1217 if (! ECOFF_DEBUGGING)
1218 pop_insert (mips_nonecoff_pseudo_table);
1221 /* Symbols labelling the current insn. */
1223 struct insn_label_list
1225 struct insn_label_list *next;
1229 static struct insn_label_list *free_insn_labels;
1230 #define label_list tc_segment_info_data.labels
1232 static void mips_clear_insn_labels (void);
1235 mips_clear_insn_labels (void)
1237 register struct insn_label_list **pl;
1238 segment_info_type *si;
1242 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1245 si = seg_info (now_seg);
1246 *pl = si->label_list;
1247 si->label_list = NULL;
1252 static char *expr_end;
1254 /* Expressions which appear in instructions. These are set by
1257 static expressionS imm_expr;
1258 static expressionS imm2_expr;
1259 static expressionS offset_expr;
1261 /* Relocs associated with imm_expr and offset_expr. */
1263 static bfd_reloc_code_real_type imm_reloc[3]
1264 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1265 static bfd_reloc_code_real_type offset_reloc[3]
1266 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1268 /* These are set by mips16_ip if an explicit extension is used. */
1270 static bfd_boolean mips16_small, mips16_ext;
1273 /* The pdr segment for per procedure frame/regmask info. Not used for
1276 static segT pdr_seg;
1279 /* The default target format to use. */
1282 mips_target_format (void)
1284 switch (OUTPUT_FLAVOR)
1286 case bfd_target_ecoff_flavour:
1287 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1288 case bfd_target_coff_flavour:
1290 case bfd_target_elf_flavour:
1292 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1293 return (target_big_endian
1294 ? "elf32-bigmips-vxworks"
1295 : "elf32-littlemips-vxworks");
1298 /* This is traditional mips. */
1299 return (target_big_endian
1300 ? (HAVE_64BIT_OBJECTS
1301 ? "elf64-tradbigmips"
1303 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1304 : (HAVE_64BIT_OBJECTS
1305 ? "elf64-tradlittlemips"
1307 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1309 return (target_big_endian
1310 ? (HAVE_64BIT_OBJECTS
1313 ? "elf32-nbigmips" : "elf32-bigmips"))
1314 : (HAVE_64BIT_OBJECTS
1315 ? "elf64-littlemips"
1317 ? "elf32-nlittlemips" : "elf32-littlemips")));
1325 /* Return the length of instruction INSN. */
1327 static inline unsigned int
1328 insn_length (const struct mips_cl_insn *insn)
1330 if (!mips_opts.mips16)
1332 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1335 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1338 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1343 insn->use_extend = FALSE;
1345 insn->insn_opcode = mo->match;
1348 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1349 insn->fixp[i] = NULL;
1350 insn->fixed_p = (mips_opts.noreorder > 0);
1351 insn->noreorder_p = (mips_opts.noreorder > 0);
1352 insn->mips16_absolute_jump_p = 0;
1355 /* Record the current MIPS16 mode in now_seg. */
1358 mips_record_mips16_mode (void)
1360 segment_info_type *si;
1362 si = seg_info (now_seg);
1363 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1364 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1367 /* Install INSN at the location specified by its "frag" and "where" fields. */
1370 install_insn (const struct mips_cl_insn *insn)
1372 char *f = insn->frag->fr_literal + insn->where;
1373 if (!mips_opts.mips16)
1374 md_number_to_chars (f, insn->insn_opcode, 4);
1375 else if (insn->mips16_absolute_jump_p)
1377 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1378 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1382 if (insn->use_extend)
1384 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1387 md_number_to_chars (f, insn->insn_opcode, 2);
1389 mips_record_mips16_mode ();
1392 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1393 and install the opcode in the new location. */
1396 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1401 insn->where = where;
1402 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1403 if (insn->fixp[i] != NULL)
1405 insn->fixp[i]->fx_frag = frag;
1406 insn->fixp[i]->fx_where = where;
1408 install_insn (insn);
1411 /* Add INSN to the end of the output. */
1414 add_fixed_insn (struct mips_cl_insn *insn)
1416 char *f = frag_more (insn_length (insn));
1417 move_insn (insn, frag_now, f - frag_now->fr_literal);
1420 /* Start a variant frag and move INSN to the start of the variant part,
1421 marking it as fixed. The other arguments are as for frag_var. */
1424 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1425 relax_substateT subtype, symbolS *symbol, offsetT offset)
1427 frag_grow (max_chars);
1428 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1430 frag_var (rs_machine_dependent, max_chars, var,
1431 subtype, symbol, offset, NULL);
1434 /* Insert N copies of INSN into the history buffer, starting at
1435 position FIRST. Neither FIRST nor N need to be clipped. */
1438 insert_into_history (unsigned int first, unsigned int n,
1439 const struct mips_cl_insn *insn)
1441 if (mips_relax.sequence != 2)
1445 for (i = ARRAY_SIZE (history); i-- > first;)
1447 history[i] = history[i - n];
1453 /* Emit a nop instruction, recording it in the history buffer. */
1458 add_fixed_insn (NOP_INSN);
1459 insert_into_history (0, 1, NOP_INSN);
1462 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1463 the idea is to make it obvious at a glance that each errata is
1467 init_vr4120_conflicts (void)
1469 #define CONFLICT(FIRST, SECOND) \
1470 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1472 /* Errata 21 - [D]DIV[U] after [D]MACC */
1473 CONFLICT (MACC, DIV);
1474 CONFLICT (DMACC, DIV);
1476 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1477 CONFLICT (DMULT, DMULT);
1478 CONFLICT (DMULT, DMACC);
1479 CONFLICT (DMACC, DMULT);
1480 CONFLICT (DMACC, DMACC);
1482 /* Errata 24 - MT{LO,HI} after [D]MACC */
1483 CONFLICT (MACC, MTHILO);
1484 CONFLICT (DMACC, MTHILO);
1486 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1487 instruction is executed immediately after a MACC or DMACC
1488 instruction, the result of [either instruction] is incorrect." */
1489 CONFLICT (MACC, MULT);
1490 CONFLICT (MACC, DMULT);
1491 CONFLICT (DMACC, MULT);
1492 CONFLICT (DMACC, DMULT);
1494 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1495 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1496 DDIV or DDIVU instruction, the result of the MACC or
1497 DMACC instruction is incorrect.". */
1498 CONFLICT (DMULT, MACC);
1499 CONFLICT (DMULT, DMACC);
1500 CONFLICT (DIV, MACC);
1501 CONFLICT (DIV, DMACC);
1511 #define RTYPE_MASK 0x1ff00
1512 #define RTYPE_NUM 0x00100
1513 #define RTYPE_FPU 0x00200
1514 #define RTYPE_FCC 0x00400
1515 #define RTYPE_VEC 0x00800
1516 #define RTYPE_GP 0x01000
1517 #define RTYPE_CP0 0x02000
1518 #define RTYPE_PC 0x04000
1519 #define RTYPE_ACC 0x08000
1520 #define RTYPE_CCC 0x10000
1521 #define RNUM_MASK 0x000ff
1522 #define RWARN 0x80000
1524 #define GENERIC_REGISTER_NUMBERS \
1525 {"$0", RTYPE_NUM | 0}, \
1526 {"$1", RTYPE_NUM | 1}, \
1527 {"$2", RTYPE_NUM | 2}, \
1528 {"$3", RTYPE_NUM | 3}, \
1529 {"$4", RTYPE_NUM | 4}, \
1530 {"$5", RTYPE_NUM | 5}, \
1531 {"$6", RTYPE_NUM | 6}, \
1532 {"$7", RTYPE_NUM | 7}, \
1533 {"$8", RTYPE_NUM | 8}, \
1534 {"$9", RTYPE_NUM | 9}, \
1535 {"$10", RTYPE_NUM | 10}, \
1536 {"$11", RTYPE_NUM | 11}, \
1537 {"$12", RTYPE_NUM | 12}, \
1538 {"$13", RTYPE_NUM | 13}, \
1539 {"$14", RTYPE_NUM | 14}, \
1540 {"$15", RTYPE_NUM | 15}, \
1541 {"$16", RTYPE_NUM | 16}, \
1542 {"$17", RTYPE_NUM | 17}, \
1543 {"$18", RTYPE_NUM | 18}, \
1544 {"$19", RTYPE_NUM | 19}, \
1545 {"$20", RTYPE_NUM | 20}, \
1546 {"$21", RTYPE_NUM | 21}, \
1547 {"$22", RTYPE_NUM | 22}, \
1548 {"$23", RTYPE_NUM | 23}, \
1549 {"$24", RTYPE_NUM | 24}, \
1550 {"$25", RTYPE_NUM | 25}, \
1551 {"$26", RTYPE_NUM | 26}, \
1552 {"$27", RTYPE_NUM | 27}, \
1553 {"$28", RTYPE_NUM | 28}, \
1554 {"$29", RTYPE_NUM | 29}, \
1555 {"$30", RTYPE_NUM | 30}, \
1556 {"$31", RTYPE_NUM | 31}
1558 #define FPU_REGISTER_NAMES \
1559 {"$f0", RTYPE_FPU | 0}, \
1560 {"$f1", RTYPE_FPU | 1}, \
1561 {"$f2", RTYPE_FPU | 2}, \
1562 {"$f3", RTYPE_FPU | 3}, \
1563 {"$f4", RTYPE_FPU | 4}, \
1564 {"$f5", RTYPE_FPU | 5}, \
1565 {"$f6", RTYPE_FPU | 6}, \
1566 {"$f7", RTYPE_FPU | 7}, \
1567 {"$f8", RTYPE_FPU | 8}, \
1568 {"$f9", RTYPE_FPU | 9}, \
1569 {"$f10", RTYPE_FPU | 10}, \
1570 {"$f11", RTYPE_FPU | 11}, \
1571 {"$f12", RTYPE_FPU | 12}, \
1572 {"$f13", RTYPE_FPU | 13}, \
1573 {"$f14", RTYPE_FPU | 14}, \
1574 {"$f15", RTYPE_FPU | 15}, \
1575 {"$f16", RTYPE_FPU | 16}, \
1576 {"$f17", RTYPE_FPU | 17}, \
1577 {"$f18", RTYPE_FPU | 18}, \
1578 {"$f19", RTYPE_FPU | 19}, \
1579 {"$f20", RTYPE_FPU | 20}, \
1580 {"$f21", RTYPE_FPU | 21}, \
1581 {"$f22", RTYPE_FPU | 22}, \
1582 {"$f23", RTYPE_FPU | 23}, \
1583 {"$f24", RTYPE_FPU | 24}, \
1584 {"$f25", RTYPE_FPU | 25}, \
1585 {"$f26", RTYPE_FPU | 26}, \
1586 {"$f27", RTYPE_FPU | 27}, \
1587 {"$f28", RTYPE_FPU | 28}, \
1588 {"$f29", RTYPE_FPU | 29}, \
1589 {"$f30", RTYPE_FPU | 30}, \
1590 {"$f31", RTYPE_FPU | 31}
1592 #define FPU_CONDITION_CODE_NAMES \
1593 {"$fcc0", RTYPE_FCC | 0}, \
1594 {"$fcc1", RTYPE_FCC | 1}, \
1595 {"$fcc2", RTYPE_FCC | 2}, \
1596 {"$fcc3", RTYPE_FCC | 3}, \
1597 {"$fcc4", RTYPE_FCC | 4}, \
1598 {"$fcc5", RTYPE_FCC | 5}, \
1599 {"$fcc6", RTYPE_FCC | 6}, \
1600 {"$fcc7", RTYPE_FCC | 7}
1602 #define COPROC_CONDITION_CODE_NAMES \
1603 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1604 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1605 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1606 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1607 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1608 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1609 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1610 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1612 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1613 {"$a4", RTYPE_GP | 8}, \
1614 {"$a5", RTYPE_GP | 9}, \
1615 {"$a6", RTYPE_GP | 10}, \
1616 {"$a7", RTYPE_GP | 11}, \
1617 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1618 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1619 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1620 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1621 {"$t0", RTYPE_GP | 12}, \
1622 {"$t1", RTYPE_GP | 13}, \
1623 {"$t2", RTYPE_GP | 14}, \
1624 {"$t3", RTYPE_GP | 15}
1626 #define O32_SYMBOLIC_REGISTER_NAMES \
1627 {"$t0", RTYPE_GP | 8}, \
1628 {"$t1", RTYPE_GP | 9}, \
1629 {"$t2", RTYPE_GP | 10}, \
1630 {"$t3", RTYPE_GP | 11}, \
1631 {"$t4", RTYPE_GP | 12}, \
1632 {"$t5", RTYPE_GP | 13}, \
1633 {"$t6", RTYPE_GP | 14}, \
1634 {"$t7", RTYPE_GP | 15}, \
1635 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1636 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1637 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1638 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1640 /* Remaining symbolic register names */
1641 #define SYMBOLIC_REGISTER_NAMES \
1642 {"$zero", RTYPE_GP | 0}, \
1643 {"$at", RTYPE_GP | 1}, \
1644 {"$AT", RTYPE_GP | 1}, \
1645 {"$v0", RTYPE_GP | 2}, \
1646 {"$v1", RTYPE_GP | 3}, \
1647 {"$a0", RTYPE_GP | 4}, \
1648 {"$a1", RTYPE_GP | 5}, \
1649 {"$a2", RTYPE_GP | 6}, \
1650 {"$a3", RTYPE_GP | 7}, \
1651 {"$s0", RTYPE_GP | 16}, \
1652 {"$s1", RTYPE_GP | 17}, \
1653 {"$s2", RTYPE_GP | 18}, \
1654 {"$s3", RTYPE_GP | 19}, \
1655 {"$s4", RTYPE_GP | 20}, \
1656 {"$s5", RTYPE_GP | 21}, \
1657 {"$s6", RTYPE_GP | 22}, \
1658 {"$s7", RTYPE_GP | 23}, \
1659 {"$t8", RTYPE_GP | 24}, \
1660 {"$t9", RTYPE_GP | 25}, \
1661 {"$k0", RTYPE_GP | 26}, \
1662 {"$kt0", RTYPE_GP | 26}, \
1663 {"$k1", RTYPE_GP | 27}, \
1664 {"$kt1", RTYPE_GP | 27}, \
1665 {"$gp", RTYPE_GP | 28}, \
1666 {"$sp", RTYPE_GP | 29}, \
1667 {"$s8", RTYPE_GP | 30}, \
1668 {"$fp", RTYPE_GP | 30}, \
1669 {"$ra", RTYPE_GP | 31}
1671 #define MIPS16_SPECIAL_REGISTER_NAMES \
1672 {"$pc", RTYPE_PC | 0}
1674 #define MDMX_VECTOR_REGISTER_NAMES \
1675 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1676 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1677 {"$v2", RTYPE_VEC | 2}, \
1678 {"$v3", RTYPE_VEC | 3}, \
1679 {"$v4", RTYPE_VEC | 4}, \
1680 {"$v5", RTYPE_VEC | 5}, \
1681 {"$v6", RTYPE_VEC | 6}, \
1682 {"$v7", RTYPE_VEC | 7}, \
1683 {"$v8", RTYPE_VEC | 8}, \
1684 {"$v9", RTYPE_VEC | 9}, \
1685 {"$v10", RTYPE_VEC | 10}, \
1686 {"$v11", RTYPE_VEC | 11}, \
1687 {"$v12", RTYPE_VEC | 12}, \
1688 {"$v13", RTYPE_VEC | 13}, \
1689 {"$v14", RTYPE_VEC | 14}, \
1690 {"$v15", RTYPE_VEC | 15}, \
1691 {"$v16", RTYPE_VEC | 16}, \
1692 {"$v17", RTYPE_VEC | 17}, \
1693 {"$v18", RTYPE_VEC | 18}, \
1694 {"$v19", RTYPE_VEC | 19}, \
1695 {"$v20", RTYPE_VEC | 20}, \
1696 {"$v21", RTYPE_VEC | 21}, \
1697 {"$v22", RTYPE_VEC | 22}, \
1698 {"$v23", RTYPE_VEC | 23}, \
1699 {"$v24", RTYPE_VEC | 24}, \
1700 {"$v25", RTYPE_VEC | 25}, \
1701 {"$v26", RTYPE_VEC | 26}, \
1702 {"$v27", RTYPE_VEC | 27}, \
1703 {"$v28", RTYPE_VEC | 28}, \
1704 {"$v29", RTYPE_VEC | 29}, \
1705 {"$v30", RTYPE_VEC | 30}, \
1706 {"$v31", RTYPE_VEC | 31}
1708 #define MIPS_DSP_ACCUMULATOR_NAMES \
1709 {"$ac0", RTYPE_ACC | 0}, \
1710 {"$ac1", RTYPE_ACC | 1}, \
1711 {"$ac2", RTYPE_ACC | 2}, \
1712 {"$ac3", RTYPE_ACC | 3}
1714 static const struct regname reg_names[] = {
1715 GENERIC_REGISTER_NUMBERS,
1717 FPU_CONDITION_CODE_NAMES,
1718 COPROC_CONDITION_CODE_NAMES,
1720 /* The $txx registers depends on the abi,
1721 these will be added later into the symbol table from
1722 one of the tables below once mips_abi is set after
1723 parsing of arguments from the command line. */
1724 SYMBOLIC_REGISTER_NAMES,
1726 MIPS16_SPECIAL_REGISTER_NAMES,
1727 MDMX_VECTOR_REGISTER_NAMES,
1728 MIPS_DSP_ACCUMULATOR_NAMES,
1732 static const struct regname reg_names_o32[] = {
1733 O32_SYMBOLIC_REGISTER_NAMES,
1737 static const struct regname reg_names_n32n64[] = {
1738 N32N64_SYMBOLIC_REGISTER_NAMES,
1743 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1750 /* Find end of name. */
1752 if (is_name_beginner (*e))
1754 while (is_part_of_name (*e))
1757 /* Terminate name. */
1761 /* Look for a register symbol. */
1762 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1764 int r = S_GET_VALUE (symbolP);
1766 reg = r & RNUM_MASK;
1767 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1768 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1769 reg = (r & RNUM_MASK) - 2;
1771 /* Else see if this is a register defined in an itbl entry. */
1772 else if ((types & RTYPE_GP) && itbl_have_entries)
1779 if (itbl_get_reg_val (n, &r))
1780 reg = r & RNUM_MASK;
1783 /* Advance to next token if a register was recognised. */
1786 else if (types & RWARN)
1787 as_warn ("Unrecognized register name `%s'", *s);
1795 #define INSN_ERET 0x42000018
1796 #define INSN_DERET 0x4200001f
1798 /* Implement the ERET/DERET Errata for MIPS 24k.
1800 If an ERET/DERET is encountered in a noreorder block,
1801 warn if the ERET/DERET is followed by a branch instruction.
1802 Also warn if the ERET/DERET is the last instruction in the
1805 IF an ERET/DERET is in a reorder block and is followed by a
1806 branch instruction, insert a nop. */
1809 check_for_24k_errata (struct mips_cl_insn *insn, int eret_ndx)
1811 bfd_boolean next_insn_is_branch = FALSE;
1813 /* eret_ndx will be -1 for the last instruction in a section
1814 and the ERET/DERET will be in insn, not history. */
1817 && (insn->insn_opcode == INSN_ERET
1818 || insn->insn_opcode == INSN_DERET)
1819 && insn->noreorder_p)
1821 as_warn (_("ERET and DERET must be followed by a NOP on the 24K."));
1825 if (history[eret_ndx].insn_opcode != INSN_ERET
1826 && history[eret_ndx].insn_opcode != INSN_DERET)
1831 if (history[eret_ndx].noreorder_p)
1832 as_warn (_("ERET and DERET must be followed by a NOP on the 24K."));
1836 next_insn_is_branch = ((insn->insn_opcode == INSN_ERET)
1837 || (insn->insn_opcode == INSN_DERET)
1838 || (insn->insn_mo->pinfo
1839 & (INSN_UNCOND_BRANCH_DELAY
1840 | INSN_COND_BRANCH_DELAY
1841 | INSN_COND_BRANCH_LIKELY)));
1843 if (next_insn_is_branch && history[eret_ndx].noreorder_p)
1845 as_warn (_("ERET and DERET must be followed by a NOP on the 24K."));
1849 /* Emit nop if the next instruction is a branch. */
1850 if (next_insn_is_branch)
1852 long nop_where, br_where;
1853 struct frag *nop_frag, *br_frag;
1854 struct mips_cl_insn br_insn, nop_insn;
1858 nop_insn = history[eret_ndx - 1];
1859 nop_frag = history[eret_ndx - 1].frag;
1860 nop_where = history[eret_ndx - 1].where;
1862 br_insn = history[eret_ndx];
1863 br_frag = history[eret_ndx].frag;
1864 br_where = history[eret_ndx].where;
1866 move_insn (&nop_insn, br_frag, br_where);
1867 move_insn (&br_insn, nop_frag, nop_where);
1869 history[eret_ndx-1] = br_insn;
1870 history[eret_ndx] = nop_insn;
1874 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1875 architecture. If EXPANSIONP is TRUE then this check is done while
1876 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1879 is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
1881 int isa = mips_opts.isa;
1884 if (mips_opts.ase_mdmx)
1886 if (mips_opts.ase_dsp)
1888 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1890 if (mips_opts.ase_dspr2)
1892 if (mips_opts.ase_mt)
1894 if (mips_opts.ase_mips3d)
1896 if (mips_opts.ase_smartmips)
1897 isa |= INSN_SMARTMIPS;
1899 /* For user code we don't check for mips_opts.mips16 since we want
1900 to allow jalx if -mips16 was specified on the command line. */
1901 if (expansionp ? mips_opts.mips16 : file_ase_mips16)
1904 /* Don't accept instructions based on the ISA if the CPU does not implement
1905 all the coprocessor insns. */
1906 if (NO_ISA_COP (mips_opts.arch)
1907 && COP_INSN (mo->pinfo))
1910 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1913 /* Check whether the instruction or macro requires single-precision or
1914 double-precision floating-point support. Note that this information is
1915 stored differently in the opcode table for insns and macros. */
1916 if (mo->pinfo == INSN_MACRO)
1918 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1919 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1923 fp_s = mo->pinfo & FP_S;
1924 fp_d = mo->pinfo & FP_D;
1927 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1930 if (fp_s && mips_opts.soft_float)
1936 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1937 selected ISA and architecture. */
1940 is_opcode_valid_16 (const struct mips_opcode *mo)
1942 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1945 /* This function is called once, at assembler startup time. It should set up
1946 all the tables, etc. that the MD part of the assembler will need. */
1951 const char *retval = NULL;
1955 if (mips_pic != NO_PIC)
1957 if (g_switch_seen && g_switch_value != 0)
1958 as_bad (_("-G may not be used in position-independent code"));
1962 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1963 as_warn (_("Could not set architecture and machine"));
1965 op_hash = hash_new ();
1967 for (i = 0; i < NUMOPCODES;)
1969 const char *name = mips_opcodes[i].name;
1971 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1974 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1975 mips_opcodes[i].name, retval);
1976 /* Probably a memory allocation problem? Give up now. */
1977 as_fatal (_("Broken assembler. No assembly attempted."));
1981 if (mips_opcodes[i].pinfo != INSN_MACRO)
1983 if (!validate_mips_insn (&mips_opcodes[i]))
1985 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1987 create_insn (&nop_insn, mips_opcodes + i);
1988 nop_insn.fixed_p = 1;
1993 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1996 mips16_op_hash = hash_new ();
1999 while (i < bfd_mips16_num_opcodes)
2001 const char *name = mips16_opcodes[i].name;
2003 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2005 as_fatal (_("internal: can't hash `%s': %s"),
2006 mips16_opcodes[i].name, retval);
2009 if (mips16_opcodes[i].pinfo != INSN_MACRO
2010 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2011 != mips16_opcodes[i].match))
2013 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2014 mips16_opcodes[i].name, mips16_opcodes[i].args);
2017 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2019 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2020 mips16_nop_insn.fixed_p = 1;
2024 while (i < bfd_mips16_num_opcodes
2025 && strcmp (mips16_opcodes[i].name, name) == 0);
2029 as_fatal (_("Broken assembler. No assembly attempted."));
2031 /* We add all the general register names to the symbol table. This
2032 helps us detect invalid uses of them. */
2033 for (i = 0; reg_names[i].name; i++)
2034 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2035 reg_names[i].num, /* & RNUM_MASK, */
2036 &zero_address_frag));
2038 for (i = 0; reg_names_n32n64[i].name; i++)
2039 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2040 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2041 &zero_address_frag));
2043 for (i = 0; reg_names_o32[i].name; i++)
2044 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2045 reg_names_o32[i].num, /* & RNUM_MASK, */
2046 &zero_address_frag));
2048 mips_no_prev_insn ();
2051 mips_cprmask[0] = 0;
2052 mips_cprmask[1] = 0;
2053 mips_cprmask[2] = 0;
2054 mips_cprmask[3] = 0;
2056 /* set the default alignment for the text section (2**2) */
2057 record_alignment (text_section, 2);
2059 bfd_set_gp_size (stdoutput, g_switch_value);
2064 /* On a native system other than VxWorks, sections must be aligned
2065 to 16 byte boundaries. When configured for an embedded ELF
2066 target, we don't bother. */
2067 if (strncmp (TARGET_OS, "elf", 3) != 0
2068 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2070 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2071 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2072 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2075 /* Create a .reginfo section for register masks and a .mdebug
2076 section for debugging information. */
2084 subseg = now_subseg;
2086 /* The ABI says this section should be loaded so that the
2087 running program can access it. However, we don't load it
2088 if we are configured for an embedded target */
2089 flags = SEC_READONLY | SEC_DATA;
2090 if (strncmp (TARGET_OS, "elf", 3) != 0)
2091 flags |= SEC_ALLOC | SEC_LOAD;
2093 if (mips_abi != N64_ABI)
2095 sec = subseg_new (".reginfo", (subsegT) 0);
2097 bfd_set_section_flags (stdoutput, sec, flags);
2098 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2100 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2104 /* The 64-bit ABI uses a .MIPS.options section rather than
2105 .reginfo section. */
2106 sec = subseg_new (".MIPS.options", (subsegT) 0);
2107 bfd_set_section_flags (stdoutput, sec, flags);
2108 bfd_set_section_alignment (stdoutput, sec, 3);
2110 /* Set up the option header. */
2112 Elf_Internal_Options opthdr;
2115 opthdr.kind = ODK_REGINFO;
2116 opthdr.size = (sizeof (Elf_External_Options)
2117 + sizeof (Elf64_External_RegInfo));
2120 f = frag_more (sizeof (Elf_External_Options));
2121 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2122 (Elf_External_Options *) f);
2124 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2128 if (ECOFF_DEBUGGING)
2130 sec = subseg_new (".mdebug", (subsegT) 0);
2131 (void) bfd_set_section_flags (stdoutput, sec,
2132 SEC_HAS_CONTENTS | SEC_READONLY);
2133 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2135 else if (mips_flag_pdr)
2137 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2138 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2139 SEC_READONLY | SEC_RELOC
2141 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2144 subseg_set (seg, subseg);
2147 #endif /* OBJ_ELF */
2149 if (! ECOFF_DEBUGGING)
2152 if (mips_fix_vr4120)
2153 init_vr4120_conflicts ();
2160 check_for_24k_errata ((struct mips_cl_insn *) &history[0], -1);
2162 if (! ECOFF_DEBUGGING)
2167 md_assemble (char *str)
2169 struct mips_cl_insn insn;
2170 bfd_reloc_code_real_type unused_reloc[3]
2171 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2173 imm_expr.X_op = O_absent;
2174 imm2_expr.X_op = O_absent;
2175 offset_expr.X_op = O_absent;
2176 imm_reloc[0] = BFD_RELOC_UNUSED;
2177 imm_reloc[1] = BFD_RELOC_UNUSED;
2178 imm_reloc[2] = BFD_RELOC_UNUSED;
2179 offset_reloc[0] = BFD_RELOC_UNUSED;
2180 offset_reloc[1] = BFD_RELOC_UNUSED;
2181 offset_reloc[2] = BFD_RELOC_UNUSED;
2183 if (mips_opts.mips16)
2184 mips16_ip (str, &insn);
2187 mips_ip (str, &insn);
2188 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2189 str, insn.insn_opcode));
2194 as_bad ("%s `%s'", insn_error, str);
2198 if (insn.insn_mo->pinfo == INSN_MACRO)
2201 if (mips_opts.mips16)
2202 mips16_macro (&insn);
2209 if (imm_expr.X_op != O_absent)
2210 append_insn (&insn, &imm_expr, imm_reloc);
2211 else if (offset_expr.X_op != O_absent)
2212 append_insn (&insn, &offset_expr, offset_reloc);
2214 append_insn (&insn, NULL, unused_reloc);
2218 /* Convenience functions for abstracting away the differences between
2219 MIPS16 and non-MIPS16 relocations. */
2221 static inline bfd_boolean
2222 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2226 case BFD_RELOC_MIPS16_JMP:
2227 case BFD_RELOC_MIPS16_GPREL:
2228 case BFD_RELOC_MIPS16_GOT16:
2229 case BFD_RELOC_MIPS16_CALL16:
2230 case BFD_RELOC_MIPS16_HI16_S:
2231 case BFD_RELOC_MIPS16_HI16:
2232 case BFD_RELOC_MIPS16_LO16:
2240 static inline bfd_boolean
2241 got16_reloc_p (bfd_reloc_code_real_type reloc)
2243 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2246 static inline bfd_boolean
2247 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2249 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2252 static inline bfd_boolean
2253 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2255 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2258 /* Return true if the given relocation might need a matching %lo().
2259 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2260 need a matching %lo() when applied to local symbols. */
2262 static inline bfd_boolean
2263 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2265 return (HAVE_IN_PLACE_ADDENDS
2266 && (hi16_reloc_p (reloc)
2267 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2268 all GOT16 relocations evaluate to "G". */
2269 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2272 /* Return the type of %lo() reloc needed by RELOC, given that
2273 reloc_needs_lo_p. */
2275 static inline bfd_reloc_code_real_type
2276 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2278 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2281 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2284 static inline bfd_boolean
2285 fixup_has_matching_lo_p (fixS *fixp)
2287 return (fixp->fx_next != NULL
2288 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2289 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2290 && fixp->fx_offset == fixp->fx_next->fx_offset);
2293 /* See whether instruction IP reads register REG. CLASS is the type
2297 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2298 enum mips_regclass class)
2300 if (class == MIPS16_REG)
2302 assert (mips_opts.mips16);
2303 reg = mips16_to_32_reg_map[reg];
2304 class = MIPS_GR_REG;
2307 /* Don't report on general register ZERO, since it never changes. */
2308 if (class == MIPS_GR_REG && reg == ZERO)
2311 if (class == MIPS_FP_REG)
2313 assert (! mips_opts.mips16);
2314 /* If we are called with either $f0 or $f1, we must check $f0.
2315 This is not optimal, because it will introduce an unnecessary
2316 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2317 need to distinguish reading both $f0 and $f1 or just one of
2318 them. Note that we don't have to check the other way,
2319 because there is no instruction that sets both $f0 and $f1
2320 and requires a delay. */
2321 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2322 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2323 == (reg &~ (unsigned) 1)))
2325 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2326 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2327 == (reg &~ (unsigned) 1)))
2330 else if (! mips_opts.mips16)
2332 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2333 && EXTRACT_OPERAND (RS, *ip) == reg)
2335 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2336 && EXTRACT_OPERAND (RT, *ip) == reg)
2341 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2342 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2344 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2345 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2347 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2348 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2351 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2353 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2355 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2357 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2358 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2365 /* This function returns true if modifying a register requires a
2369 reg_needs_delay (unsigned int reg)
2371 unsigned long prev_pinfo;
2373 prev_pinfo = history[0].insn_mo->pinfo;
2374 if (! mips_opts.noreorder
2375 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2376 && ! gpr_interlocks)
2377 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2378 && ! cop_interlocks)))
2380 /* A load from a coprocessor or from memory. All load delays
2381 delay the use of general register rt for one instruction. */
2382 /* Itbl support may require additional care here. */
2383 know (prev_pinfo & INSN_WRITE_GPR_T);
2384 if (reg == EXTRACT_OPERAND (RT, history[0]))
2391 /* Move all labels in insn_labels to the current insertion point. */
2394 mips_move_labels (void)
2396 segment_info_type *si = seg_info (now_seg);
2397 struct insn_label_list *l;
2400 for (l = si->label_list; l != NULL; l = l->next)
2402 assert (S_GET_SEGMENT (l->label) == now_seg);
2403 symbol_set_frag (l->label, frag_now);
2404 val = (valueT) frag_now_fix ();
2405 /* mips16 text labels are stored as odd. */
2406 if (mips_opts.mips16)
2408 S_SET_VALUE (l->label, val);
2413 s_is_linkonce (symbolS *sym, segT from_seg)
2415 bfd_boolean linkonce = FALSE;
2416 segT symseg = S_GET_SEGMENT (sym);
2418 if (symseg != from_seg && !S_IS_LOCAL (sym))
2420 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2423 /* The GNU toolchain uses an extension for ELF: a section
2424 beginning with the magic string .gnu.linkonce is a
2425 linkonce section. */
2426 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2427 sizeof ".gnu.linkonce" - 1) == 0)
2434 /* Mark instruction labels in mips16 mode. This permits the linker to
2435 handle them specially, such as generating jalx instructions when
2436 needed. We also make them odd for the duration of the assembly, in
2437 order to generate the right sort of code. We will make them even
2438 in the adjust_symtab routine, while leaving them marked. This is
2439 convenient for the debugger and the disassembler. The linker knows
2440 to make them odd again. */
2443 mips16_mark_labels (void)
2445 segment_info_type *si = seg_info (now_seg);
2446 struct insn_label_list *l;
2448 if (!mips_opts.mips16)
2451 for (l = si->label_list; l != NULL; l = l->next)
2453 symbolS *label = l->label;
2455 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2457 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2459 if ((S_GET_VALUE (label) & 1) == 0
2460 /* Don't adjust the address if the label is global or weak, or
2461 in a link-once section, since we'll be emitting symbol reloc
2462 references to it which will be patched up by the linker, and
2463 the final value of the symbol may or may not be MIPS16. */
2464 && ! S_IS_WEAK (label)
2465 && ! S_IS_EXTERNAL (label)
2466 && ! s_is_linkonce (label, now_seg))
2467 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2471 /* End the current frag. Make it a variant frag and record the
2475 relax_close_frag (void)
2477 mips_macro_warning.first_frag = frag_now;
2478 frag_var (rs_machine_dependent, 0, 0,
2479 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2480 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2482 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2483 mips_relax.first_fixup = 0;
2486 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2487 See the comment above RELAX_ENCODE for more details. */
2490 relax_start (symbolS *symbol)
2492 assert (mips_relax.sequence == 0);
2493 mips_relax.sequence = 1;
2494 mips_relax.symbol = symbol;
2497 /* Start generating the second version of a relaxable sequence.
2498 See the comment above RELAX_ENCODE for more details. */
2503 assert (mips_relax.sequence == 1);
2504 mips_relax.sequence = 2;
2507 /* End the current relaxable sequence. */
2512 assert (mips_relax.sequence == 2);
2513 relax_close_frag ();
2514 mips_relax.sequence = 0;
2517 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2518 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2519 by VR4120 errata. */
2522 classify_vr4120_insn (const char *name)
2524 if (strncmp (name, "macc", 4) == 0)
2525 return FIX_VR4120_MACC;
2526 if (strncmp (name, "dmacc", 5) == 0)
2527 return FIX_VR4120_DMACC;
2528 if (strncmp (name, "mult", 4) == 0)
2529 return FIX_VR4120_MULT;
2530 if (strncmp (name, "dmult", 5) == 0)
2531 return FIX_VR4120_DMULT;
2532 if (strstr (name, "div"))
2533 return FIX_VR4120_DIV;
2534 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2535 return FIX_VR4120_MTHILO;
2536 return NUM_FIX_VR4120_CLASSES;
2539 /* Return the number of instructions that must separate INSN1 and INSN2,
2540 where INSN1 is the earlier instruction. Return the worst-case value
2541 for any INSN2 if INSN2 is null. */
2544 insns_between (const struct mips_cl_insn *insn1,
2545 const struct mips_cl_insn *insn2)
2547 unsigned long pinfo1, pinfo2;
2549 /* This function needs to know which pinfo flags are set for INSN2
2550 and which registers INSN2 uses. The former is stored in PINFO2 and
2551 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2552 will have every flag set and INSN2_USES_REG will always return true. */
2553 pinfo1 = insn1->insn_mo->pinfo;
2554 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2556 #define INSN2_USES_REG(REG, CLASS) \
2557 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2559 /* For most targets, write-after-read dependencies on the HI and LO
2560 registers must be separated by at least two instructions. */
2561 if (!hilo_interlocks)
2563 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2565 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2569 /* If we're working around r7000 errata, there must be two instructions
2570 between an mfhi or mflo and any instruction that uses the result. */
2571 if (mips_7000_hilo_fix
2572 && MF_HILO_INSN (pinfo1)
2573 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2576 /* If working around VR4120 errata, check for combinations that need
2577 a single intervening instruction. */
2578 if (mips_fix_vr4120)
2580 unsigned int class1, class2;
2582 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2583 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2587 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2588 if (vr4120_conflicts[class1] & (1 << class2))
2593 if (!mips_opts.mips16)
2595 /* Check for GPR or coprocessor load delays. All such delays
2596 are on the RT register. */
2597 /* Itbl support may require additional care here. */
2598 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2599 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2601 know (pinfo1 & INSN_WRITE_GPR_T);
2602 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2606 /* Check for generic coprocessor hazards.
2608 This case is not handled very well. There is no special
2609 knowledge of CP0 handling, and the coprocessors other than
2610 the floating point unit are not distinguished at all. */
2611 /* Itbl support may require additional care here. FIXME!
2612 Need to modify this to include knowledge about
2613 user specified delays! */
2614 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2615 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2617 /* Handle cases where INSN1 writes to a known general coprocessor
2618 register. There must be a one instruction delay before INSN2
2619 if INSN2 reads that register, otherwise no delay is needed. */
2620 if (pinfo1 & INSN_WRITE_FPR_T)
2622 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2625 else if (pinfo1 & INSN_WRITE_FPR_S)
2627 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2632 /* Read-after-write dependencies on the control registers
2633 require a two-instruction gap. */
2634 if ((pinfo1 & INSN_WRITE_COND_CODE)
2635 && (pinfo2 & INSN_READ_COND_CODE))
2638 /* We don't know exactly what INSN1 does. If INSN2 is
2639 also a coprocessor instruction, assume there must be
2640 a one instruction gap. */
2641 if (pinfo2 & INSN_COP)
2646 /* Check for read-after-write dependencies on the coprocessor
2647 control registers in cases where INSN1 does not need a general
2648 coprocessor delay. This means that INSN1 is a floating point
2649 comparison instruction. */
2650 /* Itbl support may require additional care here. */
2651 else if (!cop_interlocks
2652 && (pinfo1 & INSN_WRITE_COND_CODE)
2653 && (pinfo2 & INSN_READ_COND_CODE))
2657 #undef INSN2_USES_REG
2662 /* Return the number of nops that would be needed to work around the
2663 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2664 the MAX_VR4130_NOPS instructions described by HISTORY. */
2667 nops_for_vr4130 (const struct mips_cl_insn *history,
2668 const struct mips_cl_insn *insn)
2672 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2673 are not affected by the errata. */
2675 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2676 || strcmp (insn->insn_mo->name, "mtlo") == 0
2677 || strcmp (insn->insn_mo->name, "mthi") == 0))
2680 /* Search for the first MFLO or MFHI. */
2681 for (i = 0; i < MAX_VR4130_NOPS; i++)
2682 if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo))
2684 /* Extract the destination register. */
2685 if (mips_opts.mips16)
2686 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
2688 reg = EXTRACT_OPERAND (RD, history[i]);
2690 /* No nops are needed if INSN reads that register. */
2691 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2694 /* ...or if any of the intervening instructions do. */
2695 for (j = 0; j < i; j++)
2696 if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
2699 return MAX_VR4130_NOPS - i;
2704 /* Return the number of nops that would be needed if instruction INSN
2705 immediately followed the MAX_NOPS instructions given by HISTORY,
2706 where HISTORY[0] is the most recent instruction. If INSN is null,
2707 return the worse-case number of nops for any instruction. */
2710 nops_for_insn (const struct mips_cl_insn *history,
2711 const struct mips_cl_insn *insn)
2713 int i, nops, tmp_nops;
2716 for (i = 0; i < MAX_DELAY_NOPS; i++)
2717 if (!history[i].noreorder_p)
2719 tmp_nops = insns_between (history + i, insn) - i;
2720 if (tmp_nops > nops)
2724 if (mips_fix_vr4130)
2726 tmp_nops = nops_for_vr4130 (history, insn);
2727 if (tmp_nops > nops)
2734 /* The variable arguments provide NUM_INSNS extra instructions that
2735 might be added to HISTORY. Return the largest number of nops that
2736 would be needed after the extended sequence. */
2739 nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
2742 struct mips_cl_insn buffer[MAX_NOPS];
2743 struct mips_cl_insn *cursor;
2746 va_start (args, history);
2747 cursor = buffer + num_insns;
2748 memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
2749 while (cursor > buffer)
2750 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2752 nops = nops_for_insn (buffer, NULL);
2757 /* Like nops_for_insn, but if INSN is a branch, take into account the
2758 worst-case delay for the branch target. */
2761 nops_for_insn_or_target (const struct mips_cl_insn *history,
2762 const struct mips_cl_insn *insn)
2766 nops = nops_for_insn (history, insn);
2767 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2768 | INSN_COND_BRANCH_DELAY
2769 | INSN_COND_BRANCH_LIKELY))
2771 tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
2772 if (tmp_nops > nops)
2775 else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
2777 tmp_nops = nops_for_sequence (1, history, insn);
2778 if (tmp_nops > nops)
2784 /* Output an instruction. IP is the instruction information.
2785 ADDRESS_EXPR is an operand of the instruction to be used with
2789 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2790 bfd_reloc_code_real_type *reloc_type)
2792 unsigned long prev_pinfo, pinfo;
2794 relax_stateT prev_insn_frag_type = 0;
2795 bfd_boolean relaxed_branch = FALSE;
2796 segment_info_type *si = seg_info (now_seg);
2798 /* Mark instruction labels in mips16 mode. */
2799 mips16_mark_labels ();
2801 prev_pinfo = history[0].insn_mo->pinfo;
2802 pinfo = ip->insn_mo->pinfo;
2804 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2806 /* There are a lot of optimizations we could do that we don't.
2807 In particular, we do not, in general, reorder instructions.
2808 If you use gcc with optimization, it will reorder
2809 instructions and generally do much more optimization then we
2810 do here; repeating all that work in the assembler would only
2811 benefit hand written assembly code, and does not seem worth
2813 int nops = (mips_optimize == 0
2814 ? nops_for_insn (history, NULL)
2815 : nops_for_insn_or_target (history, ip));
2819 unsigned long old_frag_offset;
2822 old_frag = frag_now;
2823 old_frag_offset = frag_now_fix ();
2825 for (i = 0; i < nops; i++)
2830 listing_prev_line ();
2831 /* We may be at the start of a variant frag. In case we
2832 are, make sure there is enough space for the frag
2833 after the frags created by listing_prev_line. The
2834 argument to frag_grow here must be at least as large
2835 as the argument to all other calls to frag_grow in
2836 this file. We don't have to worry about being in the
2837 middle of a variant frag, because the variants insert
2838 all needed nop instructions themselves. */
2842 mips_move_labels ();
2844 #ifndef NO_ECOFF_DEBUGGING
2845 if (ECOFF_DEBUGGING)
2846 ecoff_fix_loc (old_frag, old_frag_offset);
2850 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2852 /* Work out how many nops in prev_nop_frag are needed by IP. */
2853 int nops = nops_for_insn_or_target (history, ip);
2854 assert (nops <= prev_nop_frag_holds);
2856 /* Enforce NOPS as a minimum. */
2857 if (nops > prev_nop_frag_required)
2858 prev_nop_frag_required = nops;
2860 if (prev_nop_frag_holds == prev_nop_frag_required)
2862 /* Settle for the current number of nops. Update the history
2863 accordingly (for the benefit of any future .set reorder code). */
2864 prev_nop_frag = NULL;
2865 insert_into_history (prev_nop_frag_since,
2866 prev_nop_frag_holds, NOP_INSN);
2870 /* Allow this instruction to replace one of the nops that was
2871 tentatively added to prev_nop_frag. */
2872 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2873 prev_nop_frag_holds--;
2874 prev_nop_frag_since++;
2879 /* The value passed to dwarf2_emit_insn is the distance between
2880 the beginning of the current instruction and the address that
2881 should be recorded in the debug tables. For MIPS16 debug info
2882 we want to use ISA-encoded addresses, so we pass -1 for an
2883 address higher by one than the current. */
2884 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2887 /* Record the frag type before frag_var. */
2888 if (history[0].frag)
2889 prev_insn_frag_type = history[0].frag->fr_type;
2892 && *reloc_type == BFD_RELOC_16_PCREL_S2
2893 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2894 || pinfo & INSN_COND_BRANCH_LIKELY)
2895 && mips_relax_branch
2896 /* Don't try branch relaxation within .set nomacro, or within
2897 .set noat if we use $at for PIC computations. If it turns
2898 out that the branch was out-of-range, we'll get an error. */
2899 && !mips_opts.warn_about_macros
2900 && (mips_opts.at || mips_pic == NO_PIC)
2901 && !mips_opts.mips16)
2903 relaxed_branch = TRUE;
2904 add_relaxed_insn (ip, (relaxed_branch_length
2906 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2907 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2910 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2911 pinfo & INSN_COND_BRANCH_LIKELY,
2912 pinfo & INSN_WRITE_GPR_31,
2914 address_expr->X_add_symbol,
2915 address_expr->X_add_number);
2916 *reloc_type = BFD_RELOC_UNUSED;
2918 else if (*reloc_type > BFD_RELOC_UNUSED)
2920 /* We need to set up a variant frag. */
2921 assert (mips_opts.mips16 && address_expr != NULL);
2922 add_relaxed_insn (ip, 4, 0,
2924 (*reloc_type - BFD_RELOC_UNUSED,
2925 mips16_small, mips16_ext,
2926 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2927 history[0].mips16_absolute_jump_p),
2928 make_expr_symbol (address_expr), 0);
2930 else if (mips_opts.mips16
2932 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2934 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2935 /* Make sure there is enough room to swap this instruction with
2936 a following jump instruction. */
2938 add_fixed_insn (ip);
2942 if (mips_opts.mips16
2943 && mips_opts.noreorder
2944 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2945 as_warn (_("extended instruction in delay slot"));
2947 if (mips_relax.sequence)
2949 /* If we've reached the end of this frag, turn it into a variant
2950 frag and record the information for the instructions we've
2952 if (frag_room () < 4)
2953 relax_close_frag ();
2954 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2957 if (mips_relax.sequence != 2)
2958 mips_macro_warning.sizes[0] += 4;
2959 if (mips_relax.sequence != 1)
2960 mips_macro_warning.sizes[1] += 4;
2962 if (mips_opts.mips16)
2965 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2967 add_fixed_insn (ip);
2970 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2972 if (address_expr->X_op == O_constant)
2976 switch (*reloc_type)
2979 ip->insn_opcode |= address_expr->X_add_number;
2982 case BFD_RELOC_MIPS_HIGHEST:
2983 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2984 ip->insn_opcode |= tmp & 0xffff;
2987 case BFD_RELOC_MIPS_HIGHER:
2988 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2989 ip->insn_opcode |= tmp & 0xffff;
2992 case BFD_RELOC_HI16_S:
2993 tmp = (address_expr->X_add_number + 0x8000) >> 16;
2994 ip->insn_opcode |= tmp & 0xffff;
2997 case BFD_RELOC_HI16:
2998 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3001 case BFD_RELOC_UNUSED:
3002 case BFD_RELOC_LO16:
3003 case BFD_RELOC_MIPS_GOT_DISP:
3004 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3007 case BFD_RELOC_MIPS_JMP:
3008 if ((address_expr->X_add_number & 3) != 0)
3009 as_bad (_("jump to misaligned address (0x%lx)"),
3010 (unsigned long) address_expr->X_add_number);
3011 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3014 case BFD_RELOC_MIPS16_JMP:
3015 if ((address_expr->X_add_number & 3) != 0)
3016 as_bad (_("jump to misaligned address (0x%lx)"),
3017 (unsigned long) address_expr->X_add_number);
3019 (((address_expr->X_add_number & 0x7c0000) << 3)
3020 | ((address_expr->X_add_number & 0xf800000) >> 7)
3021 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3024 case BFD_RELOC_16_PCREL_S2:
3025 if ((address_expr->X_add_number & 3) != 0)
3026 as_bad (_("branch to misaligned address (0x%lx)"),
3027 (unsigned long) address_expr->X_add_number);
3028 if (mips_relax_branch)
3030 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3031 as_bad (_("branch address range overflow (0x%lx)"),
3032 (unsigned long) address_expr->X_add_number);
3033 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3040 else if (*reloc_type < BFD_RELOC_UNUSED)
3043 reloc_howto_type *howto;
3046 /* In a compound relocation, it is the final (outermost)
3047 operator that determines the relocated field. */
3048 for (i = 1; i < 3; i++)
3049 if (reloc_type[i] == BFD_RELOC_UNUSED)
3052 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3055 /* To reproduce this failure try assembling gas/testsuites/
3056 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3058 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3059 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3062 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3063 bfd_get_reloc_size (howto),
3065 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3068 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3069 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3070 && ip->fixp[0]->fx_addsy)
3071 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3073 /* These relocations can have an addend that won't fit in
3074 4 octets for 64bit assembly. */
3076 && ! howto->partial_inplace
3077 && (reloc_type[0] == BFD_RELOC_16
3078 || reloc_type[0] == BFD_RELOC_32
3079 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3080 || reloc_type[0] == BFD_RELOC_GPREL16
3081 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3082 || reloc_type[0] == BFD_RELOC_GPREL32
3083 || reloc_type[0] == BFD_RELOC_64
3084 || reloc_type[0] == BFD_RELOC_CTOR
3085 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3086 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3087 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3088 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3089 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3090 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3091 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3092 || hi16_reloc_p (reloc_type[0])
3093 || lo16_reloc_p (reloc_type[0])))
3094 ip->fixp[0]->fx_no_overflow = 1;
3096 if (mips_relax.sequence)
3098 if (mips_relax.first_fixup == 0)
3099 mips_relax.first_fixup = ip->fixp[0];
3101 else if (reloc_needs_lo_p (*reloc_type))
3103 struct mips_hi_fixup *hi_fixup;
3105 /* Reuse the last entry if it already has a matching %lo. */
3106 hi_fixup = mips_hi_fixup_list;
3108 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3110 hi_fixup = ((struct mips_hi_fixup *)
3111 xmalloc (sizeof (struct mips_hi_fixup)));
3112 hi_fixup->next = mips_hi_fixup_list;
3113 mips_hi_fixup_list = hi_fixup;
3115 hi_fixup->fixp = ip->fixp[0];
3116 hi_fixup->seg = now_seg;
3119 /* Add fixups for the second and third relocations, if given.
3120 Note that the ABI allows the second relocation to be
3121 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3122 moment we only use RSS_UNDEF, but we could add support
3123 for the others if it ever becomes necessary. */
3124 for (i = 1; i < 3; i++)
3125 if (reloc_type[i] != BFD_RELOC_UNUSED)
3127 ip->fixp[i] = fix_new (ip->frag, ip->where,
3128 ip->fixp[0]->fx_size, NULL, 0,
3129 FALSE, reloc_type[i]);
3131 /* Use fx_tcbit to mark compound relocs. */
3132 ip->fixp[0]->fx_tcbit = 1;
3133 ip->fixp[i]->fx_tcbit = 1;
3139 /* Update the register mask information. */
3140 if (! mips_opts.mips16)
3142 if (pinfo & INSN_WRITE_GPR_D)
3143 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3144 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3145 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3146 if (pinfo & INSN_READ_GPR_S)
3147 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3148 if (pinfo & INSN_WRITE_GPR_31)
3149 mips_gprmask |= 1 << RA;
3150 if (pinfo & INSN_WRITE_FPR_D)
3151 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3152 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3153 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3154 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3155 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3156 if ((pinfo & INSN_READ_FPR_R) != 0)
3157 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3158 if (pinfo & INSN_COP)
3160 /* We don't keep enough information to sort these cases out.
3161 The itbl support does keep this information however, although
3162 we currently don't support itbl fprmats as part of the cop
3163 instruction. May want to add this support in the future. */
3165 /* Never set the bit for $0, which is always zero. */
3166 mips_gprmask &= ~1 << 0;
3170 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3171 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3172 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3173 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3174 if (pinfo & MIPS16_INSN_WRITE_Z)
3175 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3176 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3177 mips_gprmask |= 1 << TREG;
3178 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3179 mips_gprmask |= 1 << SP;
3180 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3181 mips_gprmask |= 1 << RA;
3182 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3183 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3184 if (pinfo & MIPS16_INSN_READ_Z)
3185 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3186 if (pinfo & MIPS16_INSN_READ_GPR_X)
3187 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3190 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3192 /* Filling the branch delay slot is more complex. We try to
3193 switch the branch with the previous instruction, which we can
3194 do if the previous instruction does not set up a condition
3195 that the branch tests and if the branch is not itself the
3196 target of any branch. */
3197 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3198 || (pinfo & INSN_COND_BRANCH_DELAY))
3200 if (mips_optimize < 2
3201 /* If we have seen .set volatile or .set nomove, don't
3203 || mips_opts.nomove != 0
3204 /* We can't swap if the previous instruction's position
3206 || history[0].fixed_p
3207 /* If the previous previous insn was in a .set
3208 noreorder, we can't swap. Actually, the MIPS
3209 assembler will swap in this situation. However, gcc
3210 configured -with-gnu-as will generate code like
3216 in which we can not swap the bne and INSN. If gcc is
3217 not configured -with-gnu-as, it does not output the
3219 || history[1].noreorder_p
3220 /* If the branch is itself the target of a branch, we
3221 can not swap. We cheat on this; all we check for is
3222 whether there is a label on this instruction. If
3223 there are any branches to anything other than a
3224 label, users must use .set noreorder. */
3225 || si->label_list != NULL
3226 /* If the previous instruction is in a variant frag
3227 other than this branch's one, we cannot do the swap.
3228 This does not apply to the mips16, which uses variant
3229 frags for different purposes. */
3230 || (! mips_opts.mips16
3231 && prev_insn_frag_type == rs_machine_dependent)
3232 /* Check for conflicts between the branch and the instructions
3233 before the candidate delay slot. */
3234 || nops_for_insn (history + 1, ip) > 0
3235 /* Check for conflicts between the swapped sequence and the
3236 target of the branch. */
3237 || nops_for_sequence (2, history + 1, ip, history) > 0
3238 /* We do not swap with a trap instruction, since it
3239 complicates trap handlers to have the trap
3240 instruction be in a delay slot. */
3241 || (prev_pinfo & INSN_TRAP)
3242 /* If the branch reads a register that the previous
3243 instruction sets, we can not swap. */
3244 || (! mips_opts.mips16
3245 && (prev_pinfo & INSN_WRITE_GPR_T)
3246 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3248 || (! mips_opts.mips16
3249 && (prev_pinfo & INSN_WRITE_GPR_D)
3250 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3252 || (mips_opts.mips16
3253 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3255 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3257 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3259 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3261 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3263 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3265 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3266 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3267 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3268 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3269 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3270 && insn_uses_reg (ip,
3271 MIPS16OP_EXTRACT_REG32R
3272 (history[0].insn_opcode),
3274 /* If the branch writes a register that the previous
3275 instruction sets, we can not swap (we know that
3276 branches write only to RD or to $31). */
3277 || (! mips_opts.mips16
3278 && (prev_pinfo & INSN_WRITE_GPR_T)
3279 && (((pinfo & INSN_WRITE_GPR_D)
3280 && (EXTRACT_OPERAND (RT, history[0])
3281 == EXTRACT_OPERAND (RD, *ip)))
3282 || ((pinfo & INSN_WRITE_GPR_31)
3283 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3284 || (! mips_opts.mips16
3285 && (prev_pinfo & INSN_WRITE_GPR_D)
3286 && (((pinfo & INSN_WRITE_GPR_D)
3287 && (EXTRACT_OPERAND (RD, history[0])
3288 == EXTRACT_OPERAND (RD, *ip)))
3289 || ((pinfo & INSN_WRITE_GPR_31)
3290 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3291 || (mips_opts.mips16
3292 && (pinfo & MIPS16_INSN_WRITE_31)
3293 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3294 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3295 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3297 /* If the branch writes a register that the previous
3298 instruction reads, we can not swap (we know that
3299 branches only write to RD or to $31). */
3300 || (! mips_opts.mips16
3301 && (pinfo & INSN_WRITE_GPR_D)
3302 && insn_uses_reg (&history[0],
3303 EXTRACT_OPERAND (RD, *ip),
3305 || (! mips_opts.mips16
3306 && (pinfo & INSN_WRITE_GPR_31)
3307 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3308 || (mips_opts.mips16
3309 && (pinfo & MIPS16_INSN_WRITE_31)
3310 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3311 /* If one instruction sets a condition code and the
3312 other one uses a condition code, we can not swap. */
3313 || ((pinfo & INSN_READ_COND_CODE)
3314 && (prev_pinfo & INSN_WRITE_COND_CODE))
3315 || ((pinfo & INSN_WRITE_COND_CODE)
3316 && (prev_pinfo & INSN_READ_COND_CODE))
3317 /* If the previous instruction uses the PC, we can not
3319 || (mips_opts.mips16
3320 && (prev_pinfo & MIPS16_INSN_READ_PC))
3321 /* If the previous instruction had a fixup in mips16
3322 mode, we can not swap. This normally means that the
3323 previous instruction was a 4 byte branch anyhow. */
3324 || (mips_opts.mips16 && history[0].fixp[0])
3325 /* If the previous instruction is a sync, sync.l, or
3326 sync.p, we can not swap. */
3327 || (prev_pinfo & INSN_SYNC)
3328 /* If the previous instruction is an ERET or
3329 DERET, avoid the swap. */
3330 || (history[0].insn_opcode == INSN_ERET)
3331 || (history[0].insn_opcode == INSN_DERET))
3333 if (mips_opts.mips16
3334 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3335 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3336 && ISA_SUPPORTS_MIPS16E)
3338 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3339 ip->insn_opcode |= 0x0080;
3341 insert_into_history (0, 1, ip);
3345 /* We could do even better for unconditional branches to
3346 portions of this object file; we could pick up the
3347 instruction at the destination, put it in the delay
3348 slot, and bump the destination address. */
3349 insert_into_history (0, 1, ip);
3355 if (mips_relax.sequence)
3356 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3360 /* It looks like we can actually do the swap. */
3361 struct mips_cl_insn delay = history[0];
3362 if (mips_opts.mips16)
3364 know (delay.frag == ip->frag);
3365 move_insn (ip, delay.frag, delay.where);
3366 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3368 else if (relaxed_branch)
3370 /* Add the delay slot instruction to the end of the
3371 current frag and shrink the fixed part of the
3372 original frag. If the branch occupies the tail of
3373 the latter, move it backwards to cover the gap. */
3374 delay.frag->fr_fix -= 4;
3375 if (delay.frag == ip->frag)
3376 move_insn (ip, ip->frag, ip->where - 4);
3377 add_fixed_insn (&delay);
3381 move_insn (&delay, ip->frag, ip->where);
3382 move_insn (ip, history[0].frag, history[0].where);
3386 insert_into_history (0, 1, &delay);
3389 /* If that was an unconditional branch, forget the previous
3390 insn information. */
3391 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3393 /* Check for eret/deret before clearing history. */
3395 check_for_24k_errata (
3396 (struct mips_cl_insn *) &history[hndx_24k],
3398 mips_no_prev_insn ();
3401 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3403 /* We don't yet optimize a branch likely. What we should do
3404 is look at the target, copy the instruction found there
3405 into the delay slot, and increment the branch to jump to
3406 the next instruction. */
3407 insert_into_history (0, 1, ip);
3413 insert_into_history (0, 1, ip);
3416 insert_into_history (0, 1, ip);
3419 check_for_24k_errata ((struct mips_cl_insn *) &history[hndx_24k],
3422 /* We just output an insn, so the next one doesn't have a label. */
3423 mips_clear_insn_labels ();
3426 /* Forget that there was any previous instruction or label. */
3429 mips_no_prev_insn (void)
3431 prev_nop_frag = NULL;
3432 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3433 mips_clear_insn_labels ();
3436 /* This function must be called before we emit something other than
3437 instructions. It is like mips_no_prev_insn except that it inserts
3438 any NOPS that might be needed by previous instructions. */
3441 mips_emit_delays (void)
3443 if (! mips_opts.noreorder)
3445 int nops = nops_for_insn (history, NULL);
3449 add_fixed_insn (NOP_INSN);
3450 mips_move_labels ();
3453 mips_no_prev_insn ();
3456 /* Start a (possibly nested) noreorder block. */
3459 start_noreorder (void)
3461 if (mips_opts.noreorder == 0)
3466 /* None of the instructions before the .set noreorder can be moved. */
3467 for (i = 0; i < ARRAY_SIZE (history); i++)
3468 history[i].fixed_p = 1;
3470 /* Insert any nops that might be needed between the .set noreorder
3471 block and the previous instructions. We will later remove any
3472 nops that turn out not to be needed. */
3473 nops = nops_for_insn (history, NULL);
3476 if (mips_optimize != 0)
3478 /* Record the frag which holds the nop instructions, so
3479 that we can remove them if we don't need them. */
3480 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3481 prev_nop_frag = frag_now;
3482 prev_nop_frag_holds = nops;
3483 prev_nop_frag_required = 0;
3484 prev_nop_frag_since = 0;
3487 for (; nops > 0; --nops)
3488 add_fixed_insn (NOP_INSN);
3490 /* Move on to a new frag, so that it is safe to simply
3491 decrease the size of prev_nop_frag. */
3492 frag_wane (frag_now);
3494 mips_move_labels ();
3496 mips16_mark_labels ();
3497 mips_clear_insn_labels ();
3499 mips_opts.noreorder++;
3500 mips_any_noreorder = 1;
3503 /* End a nested noreorder block. */
3506 end_noreorder (void)
3509 check_for_24k_errata (NULL, 0);
3511 mips_opts.noreorder--;
3512 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3514 /* Commit to inserting prev_nop_frag_required nops and go back to
3515 handling nop insertion the .set reorder way. */
3516 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3517 * (mips_opts.mips16 ? 2 : 4));
3518 insert_into_history (prev_nop_frag_since,
3519 prev_nop_frag_required, NOP_INSN);
3520 prev_nop_frag = NULL;
3524 /* Set up global variables for the start of a new macro. */
3529 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3530 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3531 && (history[0].insn_mo->pinfo
3532 & (INSN_UNCOND_BRANCH_DELAY
3533 | INSN_COND_BRANCH_DELAY
3534 | INSN_COND_BRANCH_LIKELY)) != 0);
3537 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3538 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3539 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3542 macro_warning (relax_substateT subtype)
3544 if (subtype & RELAX_DELAY_SLOT)
3545 return _("Macro instruction expanded into multiple instructions"
3546 " in a branch delay slot");
3547 else if (subtype & RELAX_NOMACRO)
3548 return _("Macro instruction expanded into multiple instructions");
3553 /* Finish up a macro. Emit warnings as appropriate. */
3558 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3560 relax_substateT subtype;
3562 /* Set up the relaxation warning flags. */
3564 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3565 subtype |= RELAX_SECOND_LONGER;
3566 if (mips_opts.warn_about_macros)
3567 subtype |= RELAX_NOMACRO;
3568 if (mips_macro_warning.delay_slot_p)
3569 subtype |= RELAX_DELAY_SLOT;
3571 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3573 /* Either the macro has a single implementation or both
3574 implementations are longer than 4 bytes. Emit the
3576 const char *msg = macro_warning (subtype);
3578 as_warn ("%s", msg);
3582 /* One implementation might need a warning but the other
3583 definitely doesn't. */
3584 mips_macro_warning.first_frag->fr_subtype |= subtype;
3589 /* Read a macro's relocation codes from *ARGS and store them in *R.
3590 The first argument in *ARGS will be either the code for a single
3591 relocation or -1 followed by the three codes that make up a
3592 composite relocation. */
3595 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3599 next = va_arg (*args, int);
3601 r[0] = (bfd_reloc_code_real_type) next;
3603 for (i = 0; i < 3; i++)
3604 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3607 /* Build an instruction created by a macro expansion. This is passed
3608 a pointer to the count of instructions created so far, an
3609 expression, the name of the instruction to build, an operand format
3610 string, and corresponding arguments. */
3613 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3615 const struct mips_opcode *mo;
3616 struct mips_cl_insn insn;
3617 bfd_reloc_code_real_type r[3];
3620 va_start (args, fmt);
3622 if (mips_opts.mips16)
3624 mips16_macro_build (ep, name, fmt, args);
3629 r[0] = BFD_RELOC_UNUSED;
3630 r[1] = BFD_RELOC_UNUSED;
3631 r[2] = BFD_RELOC_UNUSED;
3632 mo = (struct mips_opcode *) hash_find (op_hash, name);
3634 assert (strcmp (name, mo->name) == 0);
3638 /* Search until we get a match for NAME. It is assumed here that
3639 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3640 if (strcmp (fmt, mo->args) == 0
3641 && mo->pinfo != INSN_MACRO
3642 && is_opcode_valid (mo, TRUE))
3647 assert (strcmp (name, mo->name) == 0);
3650 create_insn (&insn, mo);
3668 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3673 /* Note that in the macro case, these arguments are already
3674 in MSB form. (When handling the instruction in the
3675 non-macro case, these arguments are sizes from which
3676 MSB values must be calculated.) */
3677 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3683 /* Note that in the macro case, these arguments are already
3684 in MSBD form. (When handling the instruction in the
3685 non-macro case, these arguments are sizes from which
3686 MSBD values must be calculated.) */
3687 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3691 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3700 INSERT_OPERAND (BP, insn, va_arg (args, int));
3706 INSERT_OPERAND (RT, insn, va_arg (args, int));
3710 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3715 INSERT_OPERAND (FT, insn, va_arg (args, int));
3721 INSERT_OPERAND (RD, insn, va_arg (args, int));
3726 int tmp = va_arg (args, int);
3728 INSERT_OPERAND (RT, insn, tmp);
3729 INSERT_OPERAND (RD, insn, tmp);
3735 INSERT_OPERAND (FS, insn, va_arg (args, int));
3742 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3746 INSERT_OPERAND (FD, insn, va_arg (args, int));
3750 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3754 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3758 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3765 INSERT_OPERAND (RS, insn, va_arg (args, int));
3771 macro_read_relocs (&args, r);
3772 assert (*r == BFD_RELOC_GPREL16
3773 || *r == BFD_RELOC_MIPS_LITERAL
3774 || *r == BFD_RELOC_MIPS_HIGHER
3775 || *r == BFD_RELOC_HI16_S
3776 || *r == BFD_RELOC_LO16
3777 || *r == BFD_RELOC_MIPS_GOT16
3778 || *r == BFD_RELOC_MIPS_CALL16
3779 || *r == BFD_RELOC_MIPS_GOT_DISP
3780 || *r == BFD_RELOC_MIPS_GOT_PAGE
3781 || *r == BFD_RELOC_MIPS_GOT_OFST
3782 || *r == BFD_RELOC_MIPS_GOT_LO16
3783 || *r == BFD_RELOC_MIPS_CALL_LO16);
3787 macro_read_relocs (&args, r);
3789 && (ep->X_op == O_constant
3790 || (ep->X_op == O_symbol
3791 && (*r == BFD_RELOC_MIPS_HIGHEST
3792 || *r == BFD_RELOC_HI16_S
3793 || *r == BFD_RELOC_HI16
3794 || *r == BFD_RELOC_GPREL16
3795 || *r == BFD_RELOC_MIPS_GOT_HI16
3796 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3800 assert (ep != NULL);
3803 * This allows macro() to pass an immediate expression for
3804 * creating short branches without creating a symbol.
3806 * We don't allow branch relaxation for these branches, as
3807 * they should only appear in ".set nomacro" anyway.
3809 if (ep->X_op == O_constant)
3811 if ((ep->X_add_number & 3) != 0)
3812 as_bad (_("branch to misaligned address (0x%lx)"),
3813 (unsigned long) ep->X_add_number);
3814 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3815 as_bad (_("branch address range overflow (0x%lx)"),
3816 (unsigned long) ep->X_add_number);
3817 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3821 *r = BFD_RELOC_16_PCREL_S2;
3825 assert (ep != NULL);
3826 *r = BFD_RELOC_MIPS_JMP;
3830 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3834 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3843 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3845 append_insn (&insn, ep, r);
3849 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3852 struct mips_opcode *mo;
3853 struct mips_cl_insn insn;
3854 bfd_reloc_code_real_type r[3]
3855 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3857 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3859 assert (strcmp (name, mo->name) == 0);
3861 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3865 assert (strcmp (name, mo->name) == 0);
3868 create_insn (&insn, mo);
3886 MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
3891 MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
3895 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
3899 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
3909 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
3916 regno = va_arg (args, int);
3917 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3918 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3939 assert (ep != NULL);
3941 if (ep->X_op != O_constant)
3942 *r = (int) BFD_RELOC_UNUSED + c;
3945 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3946 FALSE, &insn.insn_opcode, &insn.use_extend,
3949 *r = BFD_RELOC_UNUSED;
3955 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
3962 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3964 append_insn (&insn, ep, r);
3968 * Sign-extend 32-bit mode constants that have bit 31 set and all
3969 * higher bits unset.
3972 normalize_constant_expr (expressionS *ex)
3974 if (ex->X_op == O_constant
3975 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3976 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3981 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3982 * all higher bits unset.
3985 normalize_address_expr (expressionS *ex)
3987 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3988 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3989 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3990 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3995 * Generate a "jalr" instruction with a relocation hint to the called
3996 * function. This occurs in NewABI PIC code.
3999 macro_build_jalr (expressionS *ep)
4008 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4010 fix_new_exp (frag_now, f - frag_now->fr_literal,
4011 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4015 * Generate a "lui" instruction.
4018 macro_build_lui (expressionS *ep, int regnum)
4020 expressionS high_expr;
4021 const struct mips_opcode *mo;
4022 struct mips_cl_insn insn;
4023 bfd_reloc_code_real_type r[3]
4024 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4025 const char *name = "lui";
4026 const char *fmt = "t,u";
4028 assert (! mips_opts.mips16);
4032 if (high_expr.X_op == O_constant)
4034 /* We can compute the instruction now without a relocation entry. */
4035 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4037 *r = BFD_RELOC_UNUSED;
4041 assert (ep->X_op == O_symbol);
4042 /* _gp_disp is a special case, used from s_cpload.
4043 __gnu_local_gp is used if mips_no_shared. */
4044 assert (mips_pic == NO_PIC
4046 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4047 || (! mips_in_shared
4048 && strcmp (S_GET_NAME (ep->X_add_symbol),
4049 "__gnu_local_gp") == 0));
4050 *r = BFD_RELOC_HI16_S;
4053 mo = hash_find (op_hash, name);
4054 assert (strcmp (name, mo->name) == 0);
4055 assert (strcmp (fmt, mo->args) == 0);
4056 create_insn (&insn, mo);
4058 insn.insn_opcode = insn.insn_mo->match;
4059 INSERT_OPERAND (RT, insn, regnum);
4060 if (*r == BFD_RELOC_UNUSED)
4062 insn.insn_opcode |= high_expr.X_add_number;
4063 append_insn (&insn, NULL, r);
4066 append_insn (&insn, &high_expr, r);
4069 /* Generate a sequence of instructions to do a load or store from a constant
4070 offset off of a base register (breg) into/from a target register (treg),
4071 using AT if necessary. */
4073 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4074 int treg, int breg, int dbl)
4076 assert (ep->X_op == O_constant);
4078 /* Sign-extending 32-bit constants makes their handling easier. */
4080 normalize_constant_expr (ep);
4082 /* Right now, this routine can only handle signed 32-bit constants. */
4083 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4084 as_warn (_("operand overflow"));
4086 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4088 /* Signed 16-bit offset will fit in the op. Easy! */
4089 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4093 /* 32-bit offset, need multiple instructions and AT, like:
4094 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4095 addu $tempreg,$tempreg,$breg
4096 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4097 to handle the complete offset. */
4098 macro_build_lui (ep, AT);
4099 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4100 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4103 as_bad (_("Macro used $at after \".set noat\""));
4108 * Generates code to set the $at register to true (one)
4109 * if reg is less than the immediate expression.
4112 set_at (int reg, int unsignedp)
4114 if (imm_expr.X_op == O_constant
4115 && imm_expr.X_add_number >= -0x8000
4116 && imm_expr.X_add_number < 0x8000)
4117 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4118 AT, reg, BFD_RELOC_LO16);
4121 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4122 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4126 /* Warn if an expression is not a constant. */
4129 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4131 if (ex->X_op == O_big)
4132 as_bad (_("unsupported large constant"));
4133 else if (ex->X_op != O_constant)
4134 as_bad (_("Instruction %s requires absolute expression"),
4137 if (HAVE_32BIT_GPRS)
4138 normalize_constant_expr (ex);
4141 /* Count the leading zeroes by performing a binary chop. This is a
4142 bulky bit of source, but performance is a LOT better for the
4143 majority of values than a simple loop to count the bits:
4144 for (lcnt = 0; (lcnt < 32); lcnt++)
4145 if ((v) & (1 << (31 - lcnt)))
4147 However it is not code size friendly, and the gain will drop a bit
4148 on certain cached systems.
4150 #define COUNT_TOP_ZEROES(v) \
4151 (((v) & ~0xffff) == 0 \
4152 ? ((v) & ~0xff) == 0 \
4153 ? ((v) & ~0xf) == 0 \
4154 ? ((v) & ~0x3) == 0 \
4155 ? ((v) & ~0x1) == 0 \
4160 : ((v) & ~0x7) == 0 \
4163 : ((v) & ~0x3f) == 0 \
4164 ? ((v) & ~0x1f) == 0 \
4167 : ((v) & ~0x7f) == 0 \
4170 : ((v) & ~0xfff) == 0 \
4171 ? ((v) & ~0x3ff) == 0 \
4172 ? ((v) & ~0x1ff) == 0 \
4175 : ((v) & ~0x7ff) == 0 \
4178 : ((v) & ~0x3fff) == 0 \
4179 ? ((v) & ~0x1fff) == 0 \
4182 : ((v) & ~0x7fff) == 0 \
4185 : ((v) & ~0xffffff) == 0 \
4186 ? ((v) & ~0xfffff) == 0 \
4187 ? ((v) & ~0x3ffff) == 0 \
4188 ? ((v) & ~0x1ffff) == 0 \
4191 : ((v) & ~0x7ffff) == 0 \
4194 : ((v) & ~0x3fffff) == 0 \
4195 ? ((v) & ~0x1fffff) == 0 \
4198 : ((v) & ~0x7fffff) == 0 \
4201 : ((v) & ~0xfffffff) == 0 \
4202 ? ((v) & ~0x3ffffff) == 0 \
4203 ? ((v) & ~0x1ffffff) == 0 \
4206 : ((v) & ~0x7ffffff) == 0 \
4209 : ((v) & ~0x3fffffff) == 0 \
4210 ? ((v) & ~0x1fffffff) == 0 \
4213 : ((v) & ~0x7fffffff) == 0 \
4218 * This routine generates the least number of instructions necessary to load
4219 * an absolute expression value into a register.
4222 load_register (int reg, expressionS *ep, int dbl)
4225 expressionS hi32, lo32;
4227 if (ep->X_op != O_big)
4229 assert (ep->X_op == O_constant);
4231 /* Sign-extending 32-bit constants makes their handling easier. */
4233 normalize_constant_expr (ep);
4235 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4237 /* We can handle 16 bit signed values with an addiu to
4238 $zero. No need to ever use daddiu here, since $zero and
4239 the result are always correct in 32 bit mode. */
4240 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4243 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4245 /* We can handle 16 bit unsigned values with an ori to
4247 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4250 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4252 /* 32 bit values require an lui. */
4253 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4254 if ((ep->X_add_number & 0xffff) != 0)
4255 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4260 /* The value is larger than 32 bits. */
4262 if (!dbl || HAVE_32BIT_GPRS)
4266 sprintf_vma (value, ep->X_add_number);
4267 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4268 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4272 if (ep->X_op != O_big)
4275 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4276 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4277 hi32.X_add_number &= 0xffffffff;
4279 lo32.X_add_number &= 0xffffffff;
4283 assert (ep->X_add_number > 2);
4284 if (ep->X_add_number == 3)
4285 generic_bignum[3] = 0;
4286 else if (ep->X_add_number > 4)
4287 as_bad (_("Number larger than 64 bits"));
4288 lo32.X_op = O_constant;
4289 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4290 hi32.X_op = O_constant;
4291 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4294 if (hi32.X_add_number == 0)
4299 unsigned long hi, lo;
4301 if (hi32.X_add_number == (offsetT) 0xffffffff)
4303 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4305 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4308 if (lo32.X_add_number & 0x80000000)
4310 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4311 if (lo32.X_add_number & 0xffff)
4312 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4317 /* Check for 16bit shifted constant. We know that hi32 is
4318 non-zero, so start the mask on the first bit of the hi32
4323 unsigned long himask, lomask;
4327 himask = 0xffff >> (32 - shift);
4328 lomask = (0xffff << shift) & 0xffffffff;
4332 himask = 0xffff << (shift - 32);
4335 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4336 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4340 tmp.X_op = O_constant;
4342 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4343 | (lo32.X_add_number >> shift));
4345 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4346 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4347 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4348 reg, reg, (shift >= 32) ? shift - 32 : shift);
4353 while (shift <= (64 - 16));
4355 /* Find the bit number of the lowest one bit, and store the
4356 shifted value in hi/lo. */
4357 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4358 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4362 while ((lo & 1) == 0)
4367 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4373 while ((hi & 1) == 0)
4382 /* Optimize if the shifted value is a (power of 2) - 1. */
4383 if ((hi == 0 && ((lo + 1) & lo) == 0)
4384 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4386 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4391 /* This instruction will set the register to be all
4393 tmp.X_op = O_constant;
4394 tmp.X_add_number = (offsetT) -1;
4395 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4399 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4400 reg, reg, (bit >= 32) ? bit - 32 : bit);
4402 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4403 reg, reg, (shift >= 32) ? shift - 32 : shift);
4408 /* Sign extend hi32 before calling load_register, because we can
4409 generally get better code when we load a sign extended value. */
4410 if ((hi32.X_add_number & 0x80000000) != 0)
4411 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4412 load_register (reg, &hi32, 0);
4415 if ((lo32.X_add_number & 0xffff0000) == 0)
4419 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4427 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4429 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4430 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4436 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4440 mid16.X_add_number >>= 16;
4441 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4442 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4445 if ((lo32.X_add_number & 0xffff) != 0)
4446 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4450 load_delay_nop (void)
4452 if (!gpr_interlocks)
4453 macro_build (NULL, "nop", "");
4456 /* Load an address into a register. */
4459 load_address (int reg, expressionS *ep, int *used_at)
4461 if (ep->X_op != O_constant
4462 && ep->X_op != O_symbol)
4464 as_bad (_("expression too complex"));
4465 ep->X_op = O_constant;
4468 if (ep->X_op == O_constant)
4470 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4474 if (mips_pic == NO_PIC)
4476 /* If this is a reference to a GP relative symbol, we want
4477 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4479 lui $reg,<sym> (BFD_RELOC_HI16_S)
4480 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4481 If we have an addend, we always use the latter form.
4483 With 64bit address space and a usable $at we want
4484 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4485 lui $at,<sym> (BFD_RELOC_HI16_S)
4486 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4487 daddiu $at,<sym> (BFD_RELOC_LO16)
4491 If $at is already in use, we use a path which is suboptimal
4492 on superscalar processors.
4493 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4494 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4496 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4498 daddiu $reg,<sym> (BFD_RELOC_LO16)
4500 For GP relative symbols in 64bit address space we can use
4501 the same sequence as in 32bit address space. */
4502 if (HAVE_64BIT_SYMBOLS)
4504 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4505 && !nopic_need_relax (ep->X_add_symbol, 1))
4507 relax_start (ep->X_add_symbol);
4508 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4509 mips_gp_register, BFD_RELOC_GPREL16);
4513 if (*used_at == 0 && mips_opts.at)
4515 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4516 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4517 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4518 BFD_RELOC_MIPS_HIGHER);
4519 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4520 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4521 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4526 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4527 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4528 BFD_RELOC_MIPS_HIGHER);
4529 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4530 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4531 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4532 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4535 if (mips_relax.sequence)
4540 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4541 && !nopic_need_relax (ep->X_add_symbol, 1))
4543 relax_start (ep->X_add_symbol);
4544 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4545 mips_gp_register, BFD_RELOC_GPREL16);
4548 macro_build_lui (ep, reg);
4549 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4550 reg, reg, BFD_RELOC_LO16);
4551 if (mips_relax.sequence)
4555 else if (!mips_big_got)
4559 /* If this is a reference to an external symbol, we want
4560 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4562 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4564 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4565 If there is a constant, it must be added in after.
4567 If we have NewABI, we want
4568 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4569 unless we're referencing a global symbol with a non-zero
4570 offset, in which case cst must be added separately. */
4573 if (ep->X_add_number)
4575 ex.X_add_number = ep->X_add_number;
4576 ep->X_add_number = 0;
4577 relax_start (ep->X_add_symbol);
4578 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4579 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4580 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4581 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4582 ex.X_op = O_constant;
4583 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4584 reg, reg, BFD_RELOC_LO16);
4585 ep->X_add_number = ex.X_add_number;
4588 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4589 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4590 if (mips_relax.sequence)
4595 ex.X_add_number = ep->X_add_number;
4596 ep->X_add_number = 0;
4597 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4598 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4600 relax_start (ep->X_add_symbol);
4602 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4606 if (ex.X_add_number != 0)
4608 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4609 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4610 ex.X_op = O_constant;
4611 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4612 reg, reg, BFD_RELOC_LO16);
4616 else if (mips_big_got)
4620 /* This is the large GOT case. If this is a reference to an
4621 external symbol, we want
4622 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4624 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4626 Otherwise, for a reference to a local symbol in old ABI, we want
4627 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4629 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4630 If there is a constant, it must be added in after.
4632 In the NewABI, for local symbols, with or without offsets, we want:
4633 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4634 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4638 ex.X_add_number = ep->X_add_number;
4639 ep->X_add_number = 0;
4640 relax_start (ep->X_add_symbol);
4641 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4642 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4643 reg, reg, mips_gp_register);
4644 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4645 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4646 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4647 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4648 else if (ex.X_add_number)
4650 ex.X_op = O_constant;
4651 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4655 ep->X_add_number = ex.X_add_number;
4657 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4658 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4659 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4660 BFD_RELOC_MIPS_GOT_OFST);
4665 ex.X_add_number = ep->X_add_number;
4666 ep->X_add_number = 0;
4667 relax_start (ep->X_add_symbol);
4668 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4669 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4670 reg, reg, mips_gp_register);
4671 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4672 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4674 if (reg_needs_delay (mips_gp_register))
4676 /* We need a nop before loading from $gp. This special
4677 check is required because the lui which starts the main
4678 instruction stream does not refer to $gp, and so will not
4679 insert the nop which may be required. */
4680 macro_build (NULL, "nop", "");
4682 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4683 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4685 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4689 if (ex.X_add_number != 0)
4691 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4692 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4693 ex.X_op = O_constant;
4694 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4702 if (!mips_opts.at && *used_at == 1)
4703 as_bad (_("Macro used $at after \".set noat\""));
4706 /* Move the contents of register SOURCE into register DEST. */
4709 move_register (int dest, int source)
4711 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4715 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4716 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4717 The two alternatives are:
4719 Global symbol Local sybmol
4720 ------------- ------------
4721 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4723 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4725 load_got_offset emits the first instruction and add_got_offset
4726 emits the second for a 16-bit offset or add_got_offset_hilo emits
4727 a sequence to add a 32-bit offset using a scratch register. */
4730 load_got_offset (int dest, expressionS *local)
4735 global.X_add_number = 0;
4737 relax_start (local->X_add_symbol);
4738 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4739 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4741 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4742 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4747 add_got_offset (int dest, expressionS *local)
4751 global.X_op = O_constant;
4752 global.X_op_symbol = NULL;
4753 global.X_add_symbol = NULL;
4754 global.X_add_number = local->X_add_number;
4756 relax_start (local->X_add_symbol);
4757 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4758 dest, dest, BFD_RELOC_LO16);
4760 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4765 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4768 int hold_mips_optimize;
4770 global.X_op = O_constant;
4771 global.X_op_symbol = NULL;
4772 global.X_add_symbol = NULL;
4773 global.X_add_number = local->X_add_number;
4775 relax_start (local->X_add_symbol);
4776 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4778 /* Set mips_optimize around the lui instruction to avoid
4779 inserting an unnecessary nop after the lw. */
4780 hold_mips_optimize = mips_optimize;
4782 macro_build_lui (&global, tmp);
4783 mips_optimize = hold_mips_optimize;
4784 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4787 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4792 * This routine implements the seemingly endless macro or synthesized
4793 * instructions and addressing modes in the mips assembly language. Many
4794 * of these macros are simple and are similar to each other. These could
4795 * probably be handled by some kind of table or grammar approach instead of
4796 * this verbose method. Others are not simple macros but are more like
4797 * optimizing code generation.
4798 * One interesting optimization is when several store macros appear
4799 * consecutively that would load AT with the upper half of the same address.
4800 * The ensuing load upper instructions are ommited. This implies some kind
4801 * of global optimization. We currently only optimize within a single macro.
4802 * For many of the load and store macros if the address is specified as a
4803 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4804 * first load register 'at' with zero and use it as the base register. The
4805 * mips assembler simply uses register $zero. Just one tiny optimization
4809 macro (struct mips_cl_insn *ip)
4811 unsigned int treg, sreg, dreg, breg;
4812 unsigned int tempreg;
4827 bfd_reloc_code_real_type r;
4828 int hold_mips_optimize;
4830 assert (! mips_opts.mips16);
4832 treg = (ip->insn_opcode >> 16) & 0x1f;
4833 dreg = (ip->insn_opcode >> 11) & 0x1f;
4834 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4835 mask = ip->insn_mo->mask;
4837 expr1.X_op = O_constant;
4838 expr1.X_op_symbol = NULL;
4839 expr1.X_add_symbol = NULL;
4840 expr1.X_add_number = 1;
4854 expr1.X_add_number = 8;
4855 macro_build (&expr1, "bgez", "s,p", sreg);
4857 macro_build (NULL, "nop", "", 0);
4859 move_register (dreg, sreg);
4860 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4883 if (imm_expr.X_op == O_constant
4884 && imm_expr.X_add_number >= -0x8000
4885 && imm_expr.X_add_number < 0x8000)
4887 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4891 load_register (AT, &imm_expr, dbl);
4892 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4911 if (imm_expr.X_op == O_constant
4912 && imm_expr.X_add_number >= 0
4913 && imm_expr.X_add_number < 0x10000)
4915 if (mask != M_NOR_I)
4916 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4919 macro_build (&imm_expr, "ori", "t,r,i",
4920 treg, sreg, BFD_RELOC_LO16);
4921 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4927 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4928 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4932 switch (imm_expr.X_add_number)
4935 macro_build (NULL, "nop", "");
4938 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4941 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4942 (int)imm_expr.X_add_number);
4961 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4963 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4967 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4968 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4976 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4981 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4985 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4986 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4992 /* check for > max integer */
4993 maxnum = 0x7fffffff;
4994 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5001 if (imm_expr.X_op == O_constant
5002 && imm_expr.X_add_number >= maxnum
5003 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5006 /* result is always false */
5008 macro_build (NULL, "nop", "", 0);
5010 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
5013 if (imm_expr.X_op != O_constant)
5014 as_bad (_("Unsupported large constant"));
5015 ++imm_expr.X_add_number;
5019 if (mask == M_BGEL_I)
5021 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5023 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5026 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5028 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5031 maxnum = 0x7fffffff;
5032 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5039 maxnum = - maxnum - 1;
5040 if (imm_expr.X_op == O_constant
5041 && imm_expr.X_add_number <= maxnum
5042 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5045 /* result is always true */
5046 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5047 macro_build (&offset_expr, "b", "p");
5052 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5062 macro_build (&offset_expr, likely ? "beql" : "beq",
5067 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5068 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5076 && imm_expr.X_op == O_constant
5077 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5079 if (imm_expr.X_op != O_constant)
5080 as_bad (_("Unsupported large constant"));
5081 ++imm_expr.X_add_number;
5085 if (mask == M_BGEUL_I)
5087 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5089 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5091 macro_build (&offset_expr, likely ? "bnel" : "bne",
5097 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5105 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5110 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5114 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5115 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5123 macro_build (&offset_expr, likely ? "bnel" : "bne",
5130 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5131 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5139 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5144 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5148 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5149 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5155 maxnum = 0x7fffffff;
5156 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5163 if (imm_expr.X_op == O_constant
5164 && imm_expr.X_add_number >= maxnum
5165 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5167 if (imm_expr.X_op != O_constant)
5168 as_bad (_("Unsupported large constant"));
5169 ++imm_expr.X_add_number;
5173 if (mask == M_BLTL_I)
5175 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5177 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5180 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5182 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5187 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5195 macro_build (&offset_expr, likely ? "beql" : "beq",
5202 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5203 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5211 && imm_expr.X_op == O_constant
5212 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5214 if (imm_expr.X_op != O_constant)
5215 as_bad (_("Unsupported large constant"));
5216 ++imm_expr.X_add_number;
5220 if (mask == M_BLTUL_I)
5222 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5224 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5226 macro_build (&offset_expr, likely ? "beql" : "beq",
5232 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5240 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5245 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5249 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5250 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5260 macro_build (&offset_expr, likely ? "bnel" : "bne",
5265 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5266 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5274 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5276 as_bad (_("Unsupported large constant"));
5281 pos = (unsigned long) imm_expr.X_add_number;
5282 size = (unsigned long) imm2_expr.X_add_number;
5287 as_bad (_("Improper position (%lu)"), pos);
5290 if (size == 0 || size > 64
5291 || (pos + size - 1) > 63)
5293 as_bad (_("Improper extract size (%lu, position %lu)"),
5298 if (size <= 32 && pos < 32)
5303 else if (size <= 32)
5313 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
5322 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5324 as_bad (_("Unsupported large constant"));
5329 pos = (unsigned long) imm_expr.X_add_number;
5330 size = (unsigned long) imm2_expr.X_add_number;
5335 as_bad (_("Improper position (%lu)"), pos);
5338 if (size == 0 || size > 64
5339 || (pos + size - 1) > 63)
5341 as_bad (_("Improper insert size (%lu, position %lu)"),
5346 if (pos < 32 && (pos + size - 1) < 32)
5361 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5362 (int) (pos + size - 1));
5378 as_warn (_("Divide by zero."));
5380 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5382 macro_build (NULL, "break", "c", 7);
5389 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5390 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5394 expr1.X_add_number = 8;
5395 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5396 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5397 macro_build (NULL, "break", "c", 7);
5399 expr1.X_add_number = -1;
5401 load_register (AT, &expr1, dbl);
5402 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5403 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5406 expr1.X_add_number = 1;
5407 load_register (AT, &expr1, dbl);
5408 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5412 expr1.X_add_number = 0x80000000;
5413 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5417 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5418 /* We want to close the noreorder block as soon as possible, so
5419 that later insns are available for delay slot filling. */
5424 expr1.X_add_number = 8;
5425 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5426 macro_build (NULL, "nop", "", 0);
5428 /* We want to close the noreorder block as soon as possible, so
5429 that later insns are available for delay slot filling. */
5432 macro_build (NULL, "break", "c", 6);
5434 macro_build (NULL, s, "d", dreg);
5473 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5475 as_warn (_("Divide by zero."));
5477 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5479 macro_build (NULL, "break", "c", 7);
5482 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5484 if (strcmp (s2, "mflo") == 0)
5485 move_register (dreg, sreg);
5487 move_register (dreg, 0);
5490 if (imm_expr.X_op == O_constant
5491 && imm_expr.X_add_number == -1
5492 && s[strlen (s) - 1] != 'u')
5494 if (strcmp (s2, "mflo") == 0)
5496 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5499 move_register (dreg, 0);
5504 load_register (AT, &imm_expr, dbl);
5505 macro_build (NULL, s, "z,s,t", sreg, AT);
5506 macro_build (NULL, s2, "d", dreg);
5528 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5529 macro_build (NULL, s, "z,s,t", sreg, treg);
5530 /* We want to close the noreorder block as soon as possible, so
5531 that later insns are available for delay slot filling. */
5536 expr1.X_add_number = 8;
5537 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5538 macro_build (NULL, s, "z,s,t", sreg, treg);
5540 /* We want to close the noreorder block as soon as possible, so
5541 that later insns are available for delay slot filling. */
5543 macro_build (NULL, "break", "c", 7);
5545 macro_build (NULL, s2, "d", dreg);
5557 /* Load the address of a symbol into a register. If breg is not
5558 zero, we then add a base register to it. */
5560 if (dbl && HAVE_32BIT_GPRS)
5561 as_warn (_("dla used to load 32-bit register"));
5563 if (! dbl && HAVE_64BIT_OBJECTS)
5564 as_warn (_("la used to load 64-bit address"));
5566 if (offset_expr.X_op == O_constant
5567 && offset_expr.X_add_number >= -0x8000
5568 && offset_expr.X_add_number < 0x8000)
5570 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5571 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5575 if (mips_opts.at && (treg == breg))
5585 if (offset_expr.X_op != O_symbol
5586 && offset_expr.X_op != O_constant)
5588 as_bad (_("expression too complex"));
5589 offset_expr.X_op = O_constant;
5592 if (offset_expr.X_op == O_constant)
5593 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5594 else if (mips_pic == NO_PIC)
5596 /* If this is a reference to a GP relative symbol, we want
5597 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5599 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5600 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5601 If we have a constant, we need two instructions anyhow,
5602 so we may as well always use the latter form.
5604 With 64bit address space and a usable $at we want
5605 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5606 lui $at,<sym> (BFD_RELOC_HI16_S)
5607 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5608 daddiu $at,<sym> (BFD_RELOC_LO16)
5610 daddu $tempreg,$tempreg,$at
5612 If $at is already in use, we use a path which is suboptimal
5613 on superscalar processors.
5614 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5615 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5617 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5619 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5621 For GP relative symbols in 64bit address space we can use
5622 the same sequence as in 32bit address space. */
5623 if (HAVE_64BIT_SYMBOLS)
5625 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5626 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5628 relax_start (offset_expr.X_add_symbol);
5629 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5630 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5634 if (used_at == 0 && mips_opts.at)
5636 macro_build (&offset_expr, "lui", "t,u",
5637 tempreg, BFD_RELOC_MIPS_HIGHEST);
5638 macro_build (&offset_expr, "lui", "t,u",
5639 AT, BFD_RELOC_HI16_S);
5640 macro_build (&offset_expr, "daddiu", "t,r,j",
5641 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5642 macro_build (&offset_expr, "daddiu", "t,r,j",
5643 AT, AT, BFD_RELOC_LO16);
5644 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5645 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5650 macro_build (&offset_expr, "lui", "t,u",
5651 tempreg, BFD_RELOC_MIPS_HIGHEST);
5652 macro_build (&offset_expr, "daddiu", "t,r,j",
5653 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5654 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5655 macro_build (&offset_expr, "daddiu", "t,r,j",
5656 tempreg, tempreg, BFD_RELOC_HI16_S);
5657 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5658 macro_build (&offset_expr, "daddiu", "t,r,j",
5659 tempreg, tempreg, BFD_RELOC_LO16);
5662 if (mips_relax.sequence)
5667 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5668 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5670 relax_start (offset_expr.X_add_symbol);
5671 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5672 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5675 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5676 as_bad (_("offset too large"));
5677 macro_build_lui (&offset_expr, tempreg);
5678 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5679 tempreg, tempreg, BFD_RELOC_LO16);
5680 if (mips_relax.sequence)
5684 else if (!mips_big_got && !HAVE_NEWABI)
5686 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5688 /* If this is a reference to an external symbol, and there
5689 is no constant, we want
5690 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5691 or for lca or if tempreg is PIC_CALL_REG
5692 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5693 For a local symbol, we want
5694 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5696 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5698 If we have a small constant, and this is a reference to
5699 an external symbol, we want
5700 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5702 addiu $tempreg,$tempreg,<constant>
5703 For a local symbol, we want the same instruction
5704 sequence, but we output a BFD_RELOC_LO16 reloc on the
5707 If we have a large constant, and this is a reference to
5708 an external symbol, we want
5709 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5710 lui $at,<hiconstant>
5711 addiu $at,$at,<loconstant>
5712 addu $tempreg,$tempreg,$at
5713 For a local symbol, we want the same instruction
5714 sequence, but we output a BFD_RELOC_LO16 reloc on the
5718 if (offset_expr.X_add_number == 0)
5720 if (mips_pic == SVR4_PIC
5722 && (call || tempreg == PIC_CALL_REG))
5723 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5725 relax_start (offset_expr.X_add_symbol);
5726 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5727 lw_reloc_type, mips_gp_register);
5730 /* We're going to put in an addu instruction using
5731 tempreg, so we may as well insert the nop right
5736 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5737 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5739 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5740 tempreg, tempreg, BFD_RELOC_LO16);
5742 /* FIXME: If breg == 0, and the next instruction uses
5743 $tempreg, then if this variant case is used an extra
5744 nop will be generated. */
5746 else if (offset_expr.X_add_number >= -0x8000
5747 && offset_expr.X_add_number < 0x8000)
5749 load_got_offset (tempreg, &offset_expr);
5751 add_got_offset (tempreg, &offset_expr);
5755 expr1.X_add_number = offset_expr.X_add_number;
5756 offset_expr.X_add_number =
5757 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5758 load_got_offset (tempreg, &offset_expr);
5759 offset_expr.X_add_number = expr1.X_add_number;
5760 /* If we are going to add in a base register, and the
5761 target register and the base register are the same,
5762 then we are using AT as a temporary register. Since
5763 we want to load the constant into AT, we add our
5764 current AT (from the global offset table) and the
5765 register into the register now, and pretend we were
5766 not using a base register. */
5770 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5775 add_got_offset_hilo (tempreg, &offset_expr, AT);
5779 else if (!mips_big_got && HAVE_NEWABI)
5781 int add_breg_early = 0;
5783 /* If this is a reference to an external, and there is no
5784 constant, or local symbol (*), with or without a
5786 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5787 or for lca or if tempreg is PIC_CALL_REG
5788 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5790 If we have a small constant, and this is a reference to
5791 an external symbol, we want
5792 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5793 addiu $tempreg,$tempreg,<constant>
5795 If we have a large constant, and this is a reference to
5796 an external symbol, we want
5797 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5798 lui $at,<hiconstant>
5799 addiu $at,$at,<loconstant>
5800 addu $tempreg,$tempreg,$at
5802 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5803 local symbols, even though it introduces an additional
5806 if (offset_expr.X_add_number)
5808 expr1.X_add_number = offset_expr.X_add_number;
5809 offset_expr.X_add_number = 0;
5811 relax_start (offset_expr.X_add_symbol);
5812 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5813 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5815 if (expr1.X_add_number >= -0x8000
5816 && expr1.X_add_number < 0x8000)
5818 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5819 tempreg, tempreg, BFD_RELOC_LO16);
5821 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5825 /* If we are going to add in a base register, and the
5826 target register and the base register are the same,
5827 then we are using AT as a temporary register. Since
5828 we want to load the constant into AT, we add our
5829 current AT (from the global offset table) and the
5830 register into the register now, and pretend we were
5831 not using a base register. */
5836 assert (tempreg == AT);
5837 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5843 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5844 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5850 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5853 offset_expr.X_add_number = expr1.X_add_number;
5855 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5856 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5859 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5860 treg, tempreg, breg);
5866 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5868 relax_start (offset_expr.X_add_symbol);
5869 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5870 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5872 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5873 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5878 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5879 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5882 else if (mips_big_got && !HAVE_NEWABI)
5885 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5886 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5887 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5889 /* This is the large GOT case. If this is a reference to an
5890 external symbol, and there is no constant, we want
5891 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5892 addu $tempreg,$tempreg,$gp
5893 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5894 or for lca or if tempreg is PIC_CALL_REG
5895 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5896 addu $tempreg,$tempreg,$gp
5897 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5898 For a local symbol, we want
5899 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5901 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5903 If we have a small constant, and this is a reference to
5904 an external symbol, we want
5905 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5906 addu $tempreg,$tempreg,$gp
5907 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5909 addiu $tempreg,$tempreg,<constant>
5910 For a local symbol, we want
5911 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5913 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5915 If we have a large constant, and this is a reference to
5916 an external symbol, we want
5917 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5918 addu $tempreg,$tempreg,$gp
5919 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5920 lui $at,<hiconstant>
5921 addiu $at,$at,<loconstant>
5922 addu $tempreg,$tempreg,$at
5923 For a local symbol, we want
5924 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5925 lui $at,<hiconstant>
5926 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5927 addu $tempreg,$tempreg,$at
5930 expr1.X_add_number = offset_expr.X_add_number;
5931 offset_expr.X_add_number = 0;
5932 relax_start (offset_expr.X_add_symbol);
5933 gpdelay = reg_needs_delay (mips_gp_register);
5934 if (expr1.X_add_number == 0 && breg == 0
5935 && (call || tempreg == PIC_CALL_REG))
5937 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5938 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5940 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5941 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5942 tempreg, tempreg, mips_gp_register);
5943 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5944 tempreg, lw_reloc_type, tempreg);
5945 if (expr1.X_add_number == 0)
5949 /* We're going to put in an addu instruction using
5950 tempreg, so we may as well insert the nop right
5955 else if (expr1.X_add_number >= -0x8000
5956 && expr1.X_add_number < 0x8000)
5959 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5960 tempreg, tempreg, BFD_RELOC_LO16);
5966 /* If we are going to add in a base register, and the
5967 target register and the base register are the same,
5968 then we are using AT as a temporary register. Since
5969 we want to load the constant into AT, we add our
5970 current AT (from the global offset table) and the
5971 register into the register now, and pretend we were
5972 not using a base register. */
5977 assert (tempreg == AT);
5979 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5984 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5985 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5989 offset_expr.X_add_number =
5990 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5995 /* This is needed because this instruction uses $gp, but
5996 the first instruction on the main stream does not. */
5997 macro_build (NULL, "nop", "");
6000 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6001 local_reloc_type, mips_gp_register);
6002 if (expr1.X_add_number >= -0x8000
6003 && expr1.X_add_number < 0x8000)
6006 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6007 tempreg, tempreg, BFD_RELOC_LO16);
6008 /* FIXME: If add_number is 0, and there was no base
6009 register, the external symbol case ended with a load,
6010 so if the symbol turns out to not be external, and
6011 the next instruction uses tempreg, an unnecessary nop
6012 will be inserted. */
6018 /* We must add in the base register now, as in the
6019 external symbol case. */
6020 assert (tempreg == AT);
6022 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6025 /* We set breg to 0 because we have arranged to add
6026 it in in both cases. */
6030 macro_build_lui (&expr1, AT);
6031 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6032 AT, AT, BFD_RELOC_LO16);
6033 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6034 tempreg, tempreg, AT);
6039 else if (mips_big_got && HAVE_NEWABI)
6041 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6042 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6043 int add_breg_early = 0;
6045 /* This is the large GOT case. If this is a reference to an
6046 external symbol, and there is no constant, we want
6047 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6048 add $tempreg,$tempreg,$gp
6049 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6050 or for lca or if tempreg is PIC_CALL_REG
6051 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6052 add $tempreg,$tempreg,$gp
6053 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6055 If we have a small constant, and this is a reference to
6056 an external symbol, we want
6057 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6058 add $tempreg,$tempreg,$gp
6059 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6060 addi $tempreg,$tempreg,<constant>
6062 If we have a large constant, and this is a reference to
6063 an external symbol, we want
6064 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6065 addu $tempreg,$tempreg,$gp
6066 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6067 lui $at,<hiconstant>
6068 addi $at,$at,<loconstant>
6069 add $tempreg,$tempreg,$at
6071 If we have NewABI, and we know it's a local symbol, we want
6072 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6073 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6074 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6076 relax_start (offset_expr.X_add_symbol);
6078 expr1.X_add_number = offset_expr.X_add_number;
6079 offset_expr.X_add_number = 0;
6081 if (expr1.X_add_number == 0 && breg == 0
6082 && (call || tempreg == PIC_CALL_REG))
6084 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6085 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6087 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6088 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6089 tempreg, tempreg, mips_gp_register);
6090 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6091 tempreg, lw_reloc_type, tempreg);
6093 if (expr1.X_add_number == 0)
6095 else if (expr1.X_add_number >= -0x8000
6096 && expr1.X_add_number < 0x8000)
6098 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6099 tempreg, tempreg, BFD_RELOC_LO16);
6101 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6105 /* If we are going to add in a base register, and the
6106 target register and the base register are the same,
6107 then we are using AT as a temporary register. Since
6108 we want to load the constant into AT, we add our
6109 current AT (from the global offset table) and the
6110 register into the register now, and pretend we were
6111 not using a base register. */
6116 assert (tempreg == AT);
6117 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6123 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6124 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6129 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6132 offset_expr.X_add_number = expr1.X_add_number;
6133 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6134 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6135 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6136 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6139 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6140 treg, tempreg, breg);
6150 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6155 unsigned long temp = (treg << 16) | (0x01);
6156 macro_build (NULL, "c2", "C", temp);
6158 /* AT is not used, just return */
6163 unsigned long temp = (0x02);
6164 macro_build (NULL, "c2", "C", temp);
6166 /* AT is not used, just return */
6171 unsigned long temp = (treg << 16) | (0x02);
6172 macro_build (NULL, "c2", "C", temp);
6174 /* AT is not used, just return */
6178 macro_build (NULL, "c2", "C", 3);
6179 /* AT is not used, just return */
6184 unsigned long temp = (treg << 16) | 0x03;
6185 macro_build (NULL, "c2", "C", temp);
6187 /* AT is not used, just return */
6191 /* The j instruction may not be used in PIC code, since it
6192 requires an absolute address. We convert it to a b
6194 if (mips_pic == NO_PIC)
6195 macro_build (&offset_expr, "j", "a");
6197 macro_build (&offset_expr, "b", "p");
6200 /* The jal instructions must be handled as macros because when
6201 generating PIC code they expand to multi-instruction
6202 sequences. Normally they are simple instructions. */
6207 if (mips_pic == NO_PIC)
6208 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6211 if (sreg != PIC_CALL_REG)
6212 as_warn (_("MIPS PIC call to register other than $25"));
6214 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6215 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6217 if (mips_cprestore_offset < 0)
6218 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6221 if (! mips_frame_reg_valid)
6223 as_warn (_("No .frame pseudo-op used in PIC code"));
6224 /* Quiet this warning. */
6225 mips_frame_reg_valid = 1;
6227 if (! mips_cprestore_valid)
6229 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6230 /* Quiet this warning. */
6231 mips_cprestore_valid = 1;
6233 expr1.X_add_number = mips_cprestore_offset;
6234 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6237 HAVE_64BIT_ADDRESSES);
6245 if (mips_pic == NO_PIC)
6246 macro_build (&offset_expr, "jal", "a");
6247 else if (mips_pic == SVR4_PIC)
6249 /* If this is a reference to an external symbol, and we are
6250 using a small GOT, we want
6251 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6255 lw $gp,cprestore($sp)
6256 The cprestore value is set using the .cprestore
6257 pseudo-op. If we are using a big GOT, we want
6258 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6260 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6264 lw $gp,cprestore($sp)
6265 If the symbol is not external, we want
6266 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6268 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6271 lw $gp,cprestore($sp)
6273 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6274 sequences above, minus nops, unless the symbol is local,
6275 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6281 relax_start (offset_expr.X_add_symbol);
6282 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6283 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6286 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6287 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6293 relax_start (offset_expr.X_add_symbol);
6294 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6295 BFD_RELOC_MIPS_CALL_HI16);
6296 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6297 PIC_CALL_REG, mips_gp_register);
6298 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6299 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6302 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6303 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6305 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6306 PIC_CALL_REG, PIC_CALL_REG,
6307 BFD_RELOC_MIPS_GOT_OFST);
6311 macro_build_jalr (&offset_expr);
6315 relax_start (offset_expr.X_add_symbol);
6318 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6319 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6328 gpdelay = reg_needs_delay (mips_gp_register);
6329 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6330 BFD_RELOC_MIPS_CALL_HI16);
6331 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6332 PIC_CALL_REG, mips_gp_register);
6333 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6334 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6339 macro_build (NULL, "nop", "");
6341 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6342 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6345 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6346 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6348 macro_build_jalr (&offset_expr);
6350 if (mips_cprestore_offset < 0)
6351 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6354 if (! mips_frame_reg_valid)
6356 as_warn (_("No .frame pseudo-op used in PIC code"));
6357 /* Quiet this warning. */
6358 mips_frame_reg_valid = 1;
6360 if (! mips_cprestore_valid)
6362 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6363 /* Quiet this warning. */
6364 mips_cprestore_valid = 1;
6366 if (mips_opts.noreorder)
6367 macro_build (NULL, "nop", "");
6368 expr1.X_add_number = mips_cprestore_offset;
6369 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6372 HAVE_64BIT_ADDRESSES);
6376 else if (mips_pic == VXWORKS_PIC)
6377 as_bad (_("Non-PIC jump used in PIC library"));
6400 /* Itbl support may require additional care here. */
6405 /* Itbl support may require additional care here. */
6410 /* Itbl support may require additional care here. */
6415 /* Itbl support may require additional care here. */
6428 /* Itbl support may require additional care here. */
6433 /* Itbl support may require additional care here. */
6438 /* Itbl support may require additional care here. */
6458 if (breg == treg || coproc || lr)
6479 /* Itbl support may require additional care here. */
6484 /* Itbl support may require additional care here. */
6489 /* Itbl support may require additional care here. */
6494 /* Itbl support may require additional care here. */
6515 /* Itbl support may require additional care here. */
6519 /* Itbl support may require additional care here. */
6524 /* Itbl support may require additional care here. */
6537 && NO_ISA_COP (mips_opts.arch)
6538 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6540 as_bad (_("opcode not supported on this processor: %s"),
6541 mips_cpu_info_from_arch (mips_opts.arch)->name);
6545 /* Itbl support may require additional care here. */
6546 if (mask == M_LWC1_AB
6547 || mask == M_SWC1_AB
6548 || mask == M_LDC1_AB
6549 || mask == M_SDC1_AB
6553 else if (mask == M_CACHE_AB)
6560 if (offset_expr.X_op != O_constant
6561 && offset_expr.X_op != O_symbol)
6563 as_bad (_("expression too complex"));
6564 offset_expr.X_op = O_constant;
6567 if (HAVE_32BIT_ADDRESSES
6568 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6572 sprintf_vma (value, offset_expr.X_add_number);
6573 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6576 /* A constant expression in PIC code can be handled just as it
6577 is in non PIC code. */
6578 if (offset_expr.X_op == O_constant)
6580 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
6581 & ~(bfd_vma) 0xffff);
6582 normalize_address_expr (&expr1);
6583 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6585 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6586 tempreg, tempreg, breg);
6587 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6589 else if (mips_pic == NO_PIC)
6591 /* If this is a reference to a GP relative symbol, and there
6592 is no base register, we want
6593 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6594 Otherwise, if there is no base register, we want
6595 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6596 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6597 If we have a constant, we need two instructions anyhow,
6598 so we always use the latter form.
6600 If we have a base register, and this is a reference to a
6601 GP relative symbol, we want
6602 addu $tempreg,$breg,$gp
6603 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6605 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6606 addu $tempreg,$tempreg,$breg
6607 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6608 With a constant we always use the latter case.
6610 With 64bit address space and no base register and $at usable,
6612 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6613 lui $at,<sym> (BFD_RELOC_HI16_S)
6614 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6617 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6618 If we have a base register, we want
6619 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6620 lui $at,<sym> (BFD_RELOC_HI16_S)
6621 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6625 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6627 Without $at we can't generate the optimal path for superscalar
6628 processors here since this would require two temporary registers.
6629 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6630 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6632 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6634 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6635 If we have a base register, we want
6636 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6637 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6639 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6641 daddu $tempreg,$tempreg,$breg
6642 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6644 For GP relative symbols in 64bit address space we can use
6645 the same sequence as in 32bit address space. */
6646 if (HAVE_64BIT_SYMBOLS)
6648 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6649 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6651 relax_start (offset_expr.X_add_symbol);
6654 macro_build (&offset_expr, s, fmt, treg,
6655 BFD_RELOC_GPREL16, mips_gp_register);
6659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6660 tempreg, breg, mips_gp_register);
6661 macro_build (&offset_expr, s, fmt, treg,
6662 BFD_RELOC_GPREL16, tempreg);
6667 if (used_at == 0 && mips_opts.at)
6669 macro_build (&offset_expr, "lui", "t,u", tempreg,
6670 BFD_RELOC_MIPS_HIGHEST);
6671 macro_build (&offset_expr, "lui", "t,u", AT,
6673 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6674 tempreg, BFD_RELOC_MIPS_HIGHER);
6676 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6677 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6678 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6679 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6685 macro_build (&offset_expr, "lui", "t,u", tempreg,
6686 BFD_RELOC_MIPS_HIGHEST);
6687 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6688 tempreg, BFD_RELOC_MIPS_HIGHER);
6689 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6690 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6691 tempreg, BFD_RELOC_HI16_S);
6692 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6694 macro_build (NULL, "daddu", "d,v,t",
6695 tempreg, tempreg, breg);
6696 macro_build (&offset_expr, s, fmt, treg,
6697 BFD_RELOC_LO16, tempreg);
6700 if (mips_relax.sequence)
6707 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6708 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6710 relax_start (offset_expr.X_add_symbol);
6711 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6715 macro_build_lui (&offset_expr, tempreg);
6716 macro_build (&offset_expr, s, fmt, treg,
6717 BFD_RELOC_LO16, tempreg);
6718 if (mips_relax.sequence)
6723 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6724 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6726 relax_start (offset_expr.X_add_symbol);
6727 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6728 tempreg, breg, mips_gp_register);
6729 macro_build (&offset_expr, s, fmt, treg,
6730 BFD_RELOC_GPREL16, tempreg);
6733 macro_build_lui (&offset_expr, tempreg);
6734 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6735 tempreg, tempreg, breg);
6736 macro_build (&offset_expr, s, fmt, treg,
6737 BFD_RELOC_LO16, tempreg);
6738 if (mips_relax.sequence)
6742 else if (!mips_big_got)
6744 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6746 /* If this is a reference to an external symbol, we want
6747 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6749 <op> $treg,0($tempreg)
6751 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6753 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6754 <op> $treg,0($tempreg)
6757 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6758 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6760 If there is a base register, we add it to $tempreg before
6761 the <op>. If there is a constant, we stick it in the
6762 <op> instruction. We don't handle constants larger than
6763 16 bits, because we have no way to load the upper 16 bits
6764 (actually, we could handle them for the subset of cases
6765 in which we are not using $at). */
6766 assert (offset_expr.X_op == O_symbol);
6769 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6770 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6772 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6773 tempreg, tempreg, breg);
6774 macro_build (&offset_expr, s, fmt, treg,
6775 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6778 expr1.X_add_number = offset_expr.X_add_number;
6779 offset_expr.X_add_number = 0;
6780 if (expr1.X_add_number < -0x8000
6781 || expr1.X_add_number >= 0x8000)
6782 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6783 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6784 lw_reloc_type, mips_gp_register);
6786 relax_start (offset_expr.X_add_symbol);
6788 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6789 tempreg, BFD_RELOC_LO16);
6792 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6793 tempreg, tempreg, breg);
6794 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6796 else if (mips_big_got && !HAVE_NEWABI)
6800 /* If this is a reference to an external symbol, we want
6801 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6802 addu $tempreg,$tempreg,$gp
6803 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6804 <op> $treg,0($tempreg)
6806 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6808 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6809 <op> $treg,0($tempreg)
6810 If there is a base register, we add it to $tempreg before
6811 the <op>. If there is a constant, we stick it in the
6812 <op> instruction. We don't handle constants larger than
6813 16 bits, because we have no way to load the upper 16 bits
6814 (actually, we could handle them for the subset of cases
6815 in which we are not using $at). */
6816 assert (offset_expr.X_op == O_symbol);
6817 expr1.X_add_number = offset_expr.X_add_number;
6818 offset_expr.X_add_number = 0;
6819 if (expr1.X_add_number < -0x8000
6820 || expr1.X_add_number >= 0x8000)
6821 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6822 gpdelay = reg_needs_delay (mips_gp_register);
6823 relax_start (offset_expr.X_add_symbol);
6824 macro_build (&offset_expr, "lui", "t,u", tempreg,
6825 BFD_RELOC_MIPS_GOT_HI16);
6826 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6828 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6829 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6832 macro_build (NULL, "nop", "");
6833 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6834 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6836 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6837 tempreg, BFD_RELOC_LO16);
6841 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6842 tempreg, tempreg, breg);
6843 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6845 else if (mips_big_got && HAVE_NEWABI)
6847 /* If this is a reference to an external symbol, we want
6848 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6849 add $tempreg,$tempreg,$gp
6850 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6851 <op> $treg,<ofst>($tempreg)
6852 Otherwise, for local symbols, we want:
6853 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6854 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6855 assert (offset_expr.X_op == O_symbol);
6856 expr1.X_add_number = offset_expr.X_add_number;
6857 offset_expr.X_add_number = 0;
6858 if (expr1.X_add_number < -0x8000
6859 || expr1.X_add_number >= 0x8000)
6860 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6861 relax_start (offset_expr.X_add_symbol);
6862 macro_build (&offset_expr, "lui", "t,u", tempreg,
6863 BFD_RELOC_MIPS_GOT_HI16);
6864 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6866 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6867 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6869 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6870 tempreg, tempreg, breg);
6871 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6874 offset_expr.X_add_number = expr1.X_add_number;
6875 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6876 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6878 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6879 tempreg, tempreg, breg);
6880 macro_build (&offset_expr, s, fmt, treg,
6881 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6891 load_register (treg, &imm_expr, 0);
6895 load_register (treg, &imm_expr, 1);
6899 if (imm_expr.X_op == O_constant)
6902 load_register (AT, &imm_expr, 0);
6903 macro_build (NULL, "mtc1", "t,G", AT, treg);
6908 assert (offset_expr.X_op == O_symbol
6909 && strcmp (segment_name (S_GET_SEGMENT
6910 (offset_expr.X_add_symbol)),
6912 && offset_expr.X_add_number == 0);
6913 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6914 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6919 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6920 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6921 order 32 bits of the value and the low order 32 bits are either
6922 zero or in OFFSET_EXPR. */
6923 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6925 if (HAVE_64BIT_GPRS)
6926 load_register (treg, &imm_expr, 1);
6931 if (target_big_endian)
6943 load_register (hreg, &imm_expr, 0);
6946 if (offset_expr.X_op == O_absent)
6947 move_register (lreg, 0);
6950 assert (offset_expr.X_op == O_constant);
6951 load_register (lreg, &offset_expr, 0);
6958 /* We know that sym is in the .rdata section. First we get the
6959 upper 16 bits of the address. */
6960 if (mips_pic == NO_PIC)
6962 macro_build_lui (&offset_expr, AT);
6967 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6968 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6972 /* Now we load the register(s). */
6973 if (HAVE_64BIT_GPRS)
6976 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6981 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6984 /* FIXME: How in the world do we deal with the possible
6986 offset_expr.X_add_number += 4;
6987 macro_build (&offset_expr, "lw", "t,o(b)",
6988 treg + 1, BFD_RELOC_LO16, AT);
6994 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6995 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6996 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6997 the value and the low order 32 bits are either zero or in
6999 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7002 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7003 if (HAVE_64BIT_FPRS)
7005 assert (HAVE_64BIT_GPRS);
7006 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7010 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7011 if (offset_expr.X_op == O_absent)
7012 macro_build (NULL, "mtc1", "t,G", 0, treg);
7015 assert (offset_expr.X_op == O_constant);
7016 load_register (AT, &offset_expr, 0);
7017 macro_build (NULL, "mtc1", "t,G", AT, treg);
7023 assert (offset_expr.X_op == O_symbol
7024 && offset_expr.X_add_number == 0);
7025 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7026 if (strcmp (s, ".lit8") == 0)
7028 if (mips_opts.isa != ISA_MIPS1)
7030 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7031 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7034 breg = mips_gp_register;
7035 r = BFD_RELOC_MIPS_LITERAL;
7040 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7042 if (mips_pic != NO_PIC)
7043 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7044 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7047 /* FIXME: This won't work for a 64 bit address. */
7048 macro_build_lui (&offset_expr, AT);
7051 if (mips_opts.isa != ISA_MIPS1)
7053 macro_build (&offset_expr, "ldc1", "T,o(b)",
7054 treg, BFD_RELOC_LO16, AT);
7063 /* Even on a big endian machine $fn comes before $fn+1. We have
7064 to adjust when loading from memory. */
7067 assert (mips_opts.isa == ISA_MIPS1);
7068 macro_build (&offset_expr, "lwc1", "T,o(b)",
7069 target_big_endian ? treg + 1 : treg, r, breg);
7070 /* FIXME: A possible overflow which I don't know how to deal
7072 offset_expr.X_add_number += 4;
7073 macro_build (&offset_expr, "lwc1", "T,o(b)",
7074 target_big_endian ? treg : treg + 1, r, breg);
7079 * The MIPS assembler seems to check for X_add_number not
7080 * being double aligned and generating:
7083 * addiu at,at,%lo(foo+1)
7086 * But, the resulting address is the same after relocation so why
7087 * generate the extra instruction?
7089 /* Itbl support may require additional care here. */
7091 if (mips_opts.isa != ISA_MIPS1)
7102 if (mips_opts.isa != ISA_MIPS1)
7110 /* Itbl support may require additional care here. */
7115 if (HAVE_64BIT_GPRS)
7126 if (HAVE_64BIT_GPRS)
7136 if (offset_expr.X_op != O_symbol
7137 && offset_expr.X_op != O_constant)
7139 as_bad (_("expression too complex"));
7140 offset_expr.X_op = O_constant;
7143 if (HAVE_32BIT_ADDRESSES
7144 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7148 sprintf_vma (value, offset_expr.X_add_number);
7149 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7152 /* Even on a big endian machine $fn comes before $fn+1. We have
7153 to adjust when loading from memory. We set coproc if we must
7154 load $fn+1 first. */
7155 /* Itbl support may require additional care here. */
7156 if (! target_big_endian)
7159 if (mips_pic == NO_PIC
7160 || offset_expr.X_op == O_constant)
7162 /* If this is a reference to a GP relative symbol, we want
7163 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7164 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7165 If we have a base register, we use this
7167 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7168 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7169 If this is not a GP relative symbol, we want
7170 lui $at,<sym> (BFD_RELOC_HI16_S)
7171 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7172 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7173 If there is a base register, we add it to $at after the
7174 lui instruction. If there is a constant, we always use
7176 if (offset_expr.X_op == O_symbol
7177 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7178 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7180 relax_start (offset_expr.X_add_symbol);
7183 tempreg = mips_gp_register;
7187 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7188 AT, breg, mips_gp_register);
7193 /* Itbl support may require additional care here. */
7194 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7195 BFD_RELOC_GPREL16, tempreg);
7196 offset_expr.X_add_number += 4;
7198 /* Set mips_optimize to 2 to avoid inserting an
7200 hold_mips_optimize = mips_optimize;
7202 /* Itbl support may require additional care here. */
7203 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7204 BFD_RELOC_GPREL16, tempreg);
7205 mips_optimize = hold_mips_optimize;
7209 /* We just generated two relocs. When tc_gen_reloc
7210 handles this case, it will skip the first reloc and
7211 handle the second. The second reloc already has an
7212 extra addend of 4, which we added above. We must
7213 subtract it out, and then subtract another 4 to make
7214 the first reloc come out right. The second reloc
7215 will come out right because we are going to add 4 to
7216 offset_expr when we build its instruction below.
7218 If we have a symbol, then we don't want to include
7219 the offset, because it will wind up being included
7220 when we generate the reloc. */
7222 if (offset_expr.X_op == O_constant)
7223 offset_expr.X_add_number -= 8;
7226 offset_expr.X_add_number = -4;
7227 offset_expr.X_op = O_constant;
7231 macro_build_lui (&offset_expr, AT);
7233 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7234 /* Itbl support may require additional care here. */
7235 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7236 BFD_RELOC_LO16, AT);
7237 /* FIXME: How do we handle overflow here? */
7238 offset_expr.X_add_number += 4;
7239 /* Itbl support may require additional care here. */
7240 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7241 BFD_RELOC_LO16, AT);
7242 if (mips_relax.sequence)
7245 else if (!mips_big_got)
7247 /* If this is a reference to an external symbol, we want
7248 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7253 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7255 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7256 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7257 If there is a base register we add it to $at before the
7258 lwc1 instructions. If there is a constant we include it
7259 in the lwc1 instructions. */
7261 expr1.X_add_number = offset_expr.X_add_number;
7262 if (expr1.X_add_number < -0x8000
7263 || expr1.X_add_number >= 0x8000 - 4)
7264 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7265 load_got_offset (AT, &offset_expr);
7268 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7270 /* Set mips_optimize to 2 to avoid inserting an undesired
7272 hold_mips_optimize = mips_optimize;
7275 /* Itbl support may require additional care here. */
7276 relax_start (offset_expr.X_add_symbol);
7277 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7278 BFD_RELOC_LO16, AT);
7279 expr1.X_add_number += 4;
7280 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7281 BFD_RELOC_LO16, AT);
7283 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7284 BFD_RELOC_LO16, AT);
7285 offset_expr.X_add_number += 4;
7286 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7287 BFD_RELOC_LO16, AT);
7290 mips_optimize = hold_mips_optimize;
7292 else if (mips_big_got)
7296 /* If this is a reference to an external symbol, we want
7297 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7299 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7304 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7306 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7307 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7308 If there is a base register we add it to $at before the
7309 lwc1 instructions. If there is a constant we include it
7310 in the lwc1 instructions. */
7312 expr1.X_add_number = offset_expr.X_add_number;
7313 offset_expr.X_add_number = 0;
7314 if (expr1.X_add_number < -0x8000
7315 || expr1.X_add_number >= 0x8000 - 4)
7316 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7317 gpdelay = reg_needs_delay (mips_gp_register);
7318 relax_start (offset_expr.X_add_symbol);
7319 macro_build (&offset_expr, "lui", "t,u",
7320 AT, BFD_RELOC_MIPS_GOT_HI16);
7321 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7322 AT, AT, mips_gp_register);
7323 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7324 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7328 /* Itbl support may require additional care here. */
7329 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7330 BFD_RELOC_LO16, AT);
7331 expr1.X_add_number += 4;
7333 /* Set mips_optimize to 2 to avoid inserting an undesired
7335 hold_mips_optimize = mips_optimize;
7337 /* Itbl support may require additional care here. */
7338 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7339 BFD_RELOC_LO16, AT);
7340 mips_optimize = hold_mips_optimize;
7341 expr1.X_add_number -= 4;
7344 offset_expr.X_add_number = expr1.X_add_number;
7346 macro_build (NULL, "nop", "");
7347 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7348 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7351 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7352 /* Itbl support may require additional care here. */
7353 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7354 BFD_RELOC_LO16, AT);
7355 offset_expr.X_add_number += 4;
7357 /* Set mips_optimize to 2 to avoid inserting an undesired
7359 hold_mips_optimize = mips_optimize;
7361 /* Itbl support may require additional care here. */
7362 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7363 BFD_RELOC_LO16, AT);
7364 mips_optimize = hold_mips_optimize;
7378 assert (HAVE_32BIT_ADDRESSES);
7379 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7380 offset_expr.X_add_number += 4;
7381 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
7384 /* New code added to support COPZ instructions.
7385 This code builds table entries out of the macros in mip_opcodes.
7386 R4000 uses interlocks to handle coproc delays.
7387 Other chips (like the R3000) require nops to be inserted for delays.
7389 FIXME: Currently, we require that the user handle delays.
7390 In order to fill delay slots for non-interlocked chips,
7391 we must have a way to specify delays based on the coprocessor.
7392 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7393 What are the side-effects of the cop instruction?
7394 What cache support might we have and what are its effects?
7395 Both coprocessor & memory require delays. how long???
7396 What registers are read/set/modified?
7398 If an itbl is provided to interpret cop instructions,
7399 this knowledge can be encoded in the itbl spec. */
7413 if (NO_ISA_COP (mips_opts.arch)
7414 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7416 as_bad (_("opcode not supported on this processor: %s"),
7417 mips_cpu_info_from_arch (mips_opts.arch)->name);
7421 /* For now we just do C (same as Cz). The parameter will be
7422 stored in insn_opcode by mips_ip. */
7423 macro_build (NULL, s, "C", ip->insn_opcode);
7427 move_register (dreg, sreg);
7430 #ifdef LOSING_COMPILER
7432 /* Try and see if this is a new itbl instruction.
7433 This code builds table entries out of the macros in mip_opcodes.
7434 FIXME: For now we just assemble the expression and pass it's
7435 value along as a 32-bit immediate.
7436 We may want to have the assembler assemble this value,
7437 so that we gain the assembler's knowledge of delay slots,
7439 Would it be more efficient to use mask (id) here? */
7440 if (itbl_have_entries
7441 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7443 s = ip->insn_mo->name;
7445 coproc = ITBL_DECODE_PNUM (immed_expr);;
7446 macro_build (&immed_expr, s, "C");
7452 if (!mips_opts.at && used_at)
7453 as_bad (_("Macro used $at after \".set noat\""));
7457 macro2 (struct mips_cl_insn *ip)
7459 unsigned int treg, sreg, dreg, breg;
7460 unsigned int tempreg;
7474 bfd_reloc_code_real_type r;
7476 treg = (ip->insn_opcode >> 16) & 0x1f;
7477 dreg = (ip->insn_opcode >> 11) & 0x1f;
7478 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7479 mask = ip->insn_mo->mask;
7481 expr1.X_op = O_constant;
7482 expr1.X_op_symbol = NULL;
7483 expr1.X_add_symbol = NULL;
7484 expr1.X_add_number = 1;
7488 #endif /* LOSING_COMPILER */
7493 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7494 macro_build (NULL, "mflo", "d", dreg);
7500 /* The MIPS assembler some times generates shifts and adds. I'm
7501 not trying to be that fancy. GCC should do this for us
7504 load_register (AT, &imm_expr, dbl);
7505 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7506 macro_build (NULL, "mflo", "d", dreg);
7522 load_register (AT, &imm_expr, dbl);
7523 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7524 macro_build (NULL, "mflo", "d", dreg);
7525 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7526 macro_build (NULL, "mfhi", "d", AT);
7528 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7531 expr1.X_add_number = 8;
7532 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7533 macro_build (NULL, "nop", "", 0);
7534 macro_build (NULL, "break", "c", 6);
7537 macro_build (NULL, "mflo", "d", dreg);
7553 load_register (AT, &imm_expr, dbl);
7554 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7555 sreg, imm ? AT : treg);
7556 macro_build (NULL, "mfhi", "d", AT);
7557 macro_build (NULL, "mflo", "d", dreg);
7559 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7562 expr1.X_add_number = 8;
7563 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7564 macro_build (NULL, "nop", "", 0);
7565 macro_build (NULL, "break", "c", 6);
7571 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7582 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7583 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7587 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7588 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7589 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7590 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7594 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7605 macro_build (NULL, "negu", "d,w", tempreg, treg);
7606 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7610 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7611 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7612 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7613 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7621 if (imm_expr.X_op != O_constant)
7622 as_bad (_("Improper rotate count"));
7623 rot = imm_expr.X_add_number & 0x3f;
7624 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7626 rot = (64 - rot) & 0x3f;
7628 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7630 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7635 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7638 l = (rot < 0x20) ? "dsll" : "dsll32";
7639 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7642 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7643 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7644 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7652 if (imm_expr.X_op != O_constant)
7653 as_bad (_("Improper rotate count"));
7654 rot = imm_expr.X_add_number & 0x1f;
7655 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7657 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7662 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7666 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7667 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7668 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7673 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7675 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7679 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7680 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7681 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7682 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7686 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7688 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7692 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7693 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7694 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7695 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7703 if (imm_expr.X_op != O_constant)
7704 as_bad (_("Improper rotate count"));
7705 rot = imm_expr.X_add_number & 0x3f;
7706 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7709 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7711 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7716 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7719 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7720 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7723 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7724 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7725 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7733 if (imm_expr.X_op != O_constant)
7734 as_bad (_("Improper rotate count"));
7735 rot = imm_expr.X_add_number & 0x1f;
7736 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7738 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7743 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7747 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7748 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7749 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7754 assert (mips_opts.isa == ISA_MIPS1);
7755 /* Even on a big endian machine $fn comes before $fn+1. We have
7756 to adjust when storing to memory. */
7757 macro_build (&offset_expr, "swc1", "T,o(b)",
7758 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7759 offset_expr.X_add_number += 4;
7760 macro_build (&offset_expr, "swc1", "T,o(b)",
7761 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7766 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7768 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7771 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7772 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7777 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7779 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7784 as_warn (_("Instruction %s: result is always false"),
7786 move_register (dreg, 0);
7789 if (CPU_HAS_SEQ (mips_opts.arch)
7790 && -512 <= imm_expr.X_add_number
7791 && imm_expr.X_add_number < 512)
7793 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7794 (int) imm_expr.X_add_number);
7797 if (imm_expr.X_op == O_constant
7798 && imm_expr.X_add_number >= 0
7799 && imm_expr.X_add_number < 0x10000)
7801 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7803 else if (imm_expr.X_op == O_constant
7804 && imm_expr.X_add_number > -0x8000
7805 && imm_expr.X_add_number < 0)
7807 imm_expr.X_add_number = -imm_expr.X_add_number;
7808 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7809 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7811 else if (CPU_HAS_SEQ (mips_opts.arch))
7814 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7815 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7820 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7821 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7824 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7827 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7833 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7834 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7837 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7839 if (imm_expr.X_op == O_constant
7840 && imm_expr.X_add_number >= -0x8000
7841 && imm_expr.X_add_number < 0x8000)
7843 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7844 dreg, sreg, BFD_RELOC_LO16);
7848 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7849 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7853 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7856 case M_SGT: /* sreg > treg <==> treg < sreg */
7862 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7865 case M_SGT_I: /* sreg > I <==> I < sreg */
7872 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7873 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7876 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7882 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7883 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7886 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7893 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7894 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7895 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7899 if (imm_expr.X_op == O_constant
7900 && imm_expr.X_add_number >= -0x8000
7901 && imm_expr.X_add_number < 0x8000)
7903 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7907 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7908 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7912 if (imm_expr.X_op == O_constant
7913 && imm_expr.X_add_number >= -0x8000
7914 && imm_expr.X_add_number < 0x8000)
7916 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7921 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7922 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7927 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7929 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7932 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7933 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7938 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7940 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7945 as_warn (_("Instruction %s: result is always true"),
7947 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7948 dreg, 0, BFD_RELOC_LO16);
7951 if (CPU_HAS_SEQ (mips_opts.arch)
7952 && -512 <= imm_expr.X_add_number
7953 && imm_expr.X_add_number < 512)
7955 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
7956 (int) imm_expr.X_add_number);
7959 if (imm_expr.X_op == O_constant
7960 && imm_expr.X_add_number >= 0
7961 && imm_expr.X_add_number < 0x10000)
7963 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7965 else if (imm_expr.X_op == O_constant
7966 && imm_expr.X_add_number > -0x8000
7967 && imm_expr.X_add_number < 0)
7969 imm_expr.X_add_number = -imm_expr.X_add_number;
7970 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7971 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7973 else if (CPU_HAS_SEQ (mips_opts.arch))
7976 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7977 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
7982 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7983 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7986 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7992 if (imm_expr.X_op == O_constant
7993 && imm_expr.X_add_number > -0x8000
7994 && imm_expr.X_add_number <= 0x8000)
7996 imm_expr.X_add_number = -imm_expr.X_add_number;
7997 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7998 dreg, sreg, BFD_RELOC_LO16);
8002 load_register (AT, &imm_expr, dbl);
8003 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8009 if (imm_expr.X_op == O_constant
8010 && imm_expr.X_add_number > -0x8000
8011 && imm_expr.X_add_number <= 0x8000)
8013 imm_expr.X_add_number = -imm_expr.X_add_number;
8014 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8015 dreg, sreg, BFD_RELOC_LO16);
8019 load_register (AT, &imm_expr, dbl);
8020 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8042 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8043 macro_build (NULL, s, "s,t", sreg, AT);
8048 assert (mips_opts.isa == ISA_MIPS1);
8050 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8051 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8054 * Is the double cfc1 instruction a bug in the mips assembler;
8055 * or is there a reason for it?
8058 macro_build (NULL, "cfc1", "t,G", treg, RA);
8059 macro_build (NULL, "cfc1", "t,G", treg, RA);
8060 macro_build (NULL, "nop", "");
8061 expr1.X_add_number = 3;
8062 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8063 expr1.X_add_number = 2;
8064 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8065 macro_build (NULL, "ctc1", "t,G", AT, RA);
8066 macro_build (NULL, "nop", "");
8067 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8069 macro_build (NULL, "ctc1", "t,G", treg, RA);
8070 macro_build (NULL, "nop", "");
8081 if (offset_expr.X_add_number >= 0x7fff)
8082 as_bad (_("operand overflow"));
8083 if (! target_big_endian)
8084 ++offset_expr.X_add_number;
8085 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8086 if (! target_big_endian)
8087 --offset_expr.X_add_number;
8089 ++offset_expr.X_add_number;
8090 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8091 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8092 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8105 if (offset_expr.X_add_number >= 0x8000 - off)
8106 as_bad (_("operand overflow"));
8114 if (! target_big_endian)
8115 offset_expr.X_add_number += off;
8116 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8117 if (! target_big_endian)
8118 offset_expr.X_add_number -= off;
8120 offset_expr.X_add_number += off;
8121 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8123 /* If necessary, move the result in tempreg the final destination. */
8124 if (treg == tempreg)
8126 /* Protect second load's delay slot. */
8128 move_register (treg, tempreg);
8142 load_address (AT, &offset_expr, &used_at);
8144 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8145 if (! target_big_endian)
8146 expr1.X_add_number = off;
8148 expr1.X_add_number = 0;
8149 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8150 if (! target_big_endian)
8151 expr1.X_add_number = 0;
8153 expr1.X_add_number = off;
8154 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8160 load_address (AT, &offset_expr, &used_at);
8162 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8163 if (target_big_endian)
8164 expr1.X_add_number = 0;
8165 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8166 treg, BFD_RELOC_LO16, AT);
8167 if (target_big_endian)
8168 expr1.X_add_number = 1;
8170 expr1.X_add_number = 0;
8171 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8172 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8173 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8178 if (offset_expr.X_add_number >= 0x7fff)
8179 as_bad (_("operand overflow"));
8180 if (target_big_endian)
8181 ++offset_expr.X_add_number;
8182 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8183 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8184 if (target_big_endian)
8185 --offset_expr.X_add_number;
8187 ++offset_expr.X_add_number;
8188 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8201 if (offset_expr.X_add_number >= 0x8000 - off)
8202 as_bad (_("operand overflow"));
8203 if (! target_big_endian)
8204 offset_expr.X_add_number += off;
8205 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8206 if (! target_big_endian)
8207 offset_expr.X_add_number -= off;
8209 offset_expr.X_add_number += off;
8210 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8224 load_address (AT, &offset_expr, &used_at);
8226 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8227 if (! target_big_endian)
8228 expr1.X_add_number = off;
8230 expr1.X_add_number = 0;
8231 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8232 if (! target_big_endian)
8233 expr1.X_add_number = 0;
8235 expr1.X_add_number = off;
8236 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8241 load_address (AT, &offset_expr, &used_at);
8243 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8244 if (! target_big_endian)
8245 expr1.X_add_number = 0;
8246 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8247 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8248 if (! target_big_endian)
8249 expr1.X_add_number = 1;
8251 expr1.X_add_number = 0;
8252 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8253 if (! target_big_endian)
8254 expr1.X_add_number = 0;
8256 expr1.X_add_number = 1;
8257 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8258 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8259 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8263 /* FIXME: Check if this is one of the itbl macros, since they
8264 are added dynamically. */
8265 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8268 if (!mips_opts.at && used_at)
8269 as_bad (_("Macro used $at after \".set noat\""));
8272 /* Implement macros in mips16 mode. */
8275 mips16_macro (struct mips_cl_insn *ip)
8278 int xreg, yreg, zreg, tmp;
8281 const char *s, *s2, *s3;
8283 mask = ip->insn_mo->mask;
8285 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8286 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8287 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8289 expr1.X_op = O_constant;
8290 expr1.X_op_symbol = NULL;
8291 expr1.X_add_symbol = NULL;
8292 expr1.X_add_number = 1;
8312 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8313 expr1.X_add_number = 2;
8314 macro_build (&expr1, "bnez", "x,p", yreg);
8315 macro_build (NULL, "break", "6", 7);
8317 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8318 since that causes an overflow. We should do that as well,
8319 but I don't see how to do the comparisons without a temporary
8322 macro_build (NULL, s, "x", zreg);
8342 macro_build (NULL, s, "0,x,y", xreg, yreg);
8343 expr1.X_add_number = 2;
8344 macro_build (&expr1, "bnez", "x,p", yreg);
8345 macro_build (NULL, "break", "6", 7);
8347 macro_build (NULL, s2, "x", zreg);
8353 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8354 macro_build (NULL, "mflo", "x", zreg);
8362 if (imm_expr.X_op != O_constant)
8363 as_bad (_("Unsupported large constant"));
8364 imm_expr.X_add_number = -imm_expr.X_add_number;
8365 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8369 if (imm_expr.X_op != O_constant)
8370 as_bad (_("Unsupported large constant"));
8371 imm_expr.X_add_number = -imm_expr.X_add_number;
8372 macro_build (&imm_expr, "addiu", "x,k", xreg);
8376 if (imm_expr.X_op != O_constant)
8377 as_bad (_("Unsupported large constant"));
8378 imm_expr.X_add_number = -imm_expr.X_add_number;
8379 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8401 goto do_reverse_branch;
8405 goto do_reverse_branch;
8417 goto do_reverse_branch;
8428 macro_build (NULL, s, "x,y", xreg, yreg);
8429 macro_build (&offset_expr, s2, "p");
8456 goto do_addone_branch_i;
8461 goto do_addone_branch_i;
8476 goto do_addone_branch_i;
8483 if (imm_expr.X_op != O_constant)
8484 as_bad (_("Unsupported large constant"));
8485 ++imm_expr.X_add_number;
8488 macro_build (&imm_expr, s, s3, xreg);
8489 macro_build (&offset_expr, s2, "p");
8493 expr1.X_add_number = 0;
8494 macro_build (&expr1, "slti", "x,8", yreg);
8496 move_register (xreg, yreg);
8497 expr1.X_add_number = 2;
8498 macro_build (&expr1, "bteqz", "p");
8499 macro_build (NULL, "neg", "x,w", xreg, xreg);
8503 /* For consistency checking, verify that all bits are specified either
8504 by the match/mask part of the instruction definition, or by the
8507 validate_mips_insn (const struct mips_opcode *opc)
8509 const char *p = opc->args;
8511 unsigned long used_bits = opc->mask;
8513 if ((used_bits & opc->match) != opc->match)
8515 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8516 opc->name, opc->args);
8519 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8529 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8530 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8531 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8532 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8533 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8534 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8535 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8536 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8537 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8538 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8539 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8540 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8541 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8543 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8544 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8545 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8546 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8547 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8548 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8549 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8550 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8551 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8552 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8555 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8556 c, opc->name, opc->args);
8560 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8561 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8563 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8564 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8565 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8566 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8568 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8569 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8571 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8572 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8574 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8575 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8576 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8577 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8578 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8579 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8580 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8581 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8582 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8583 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8584 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8585 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8586 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8587 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8588 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8589 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8590 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8592 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8593 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8594 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8595 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8597 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8598 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8599 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8600 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8601 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8602 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8603 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8604 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8605 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8608 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8609 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8610 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8611 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8612 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8615 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8616 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8617 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8618 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8619 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8620 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8621 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8622 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8623 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8624 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8625 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8626 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8627 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8628 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8629 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8630 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8631 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8632 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8634 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8635 c, opc->name, opc->args);
8639 if (used_bits != 0xffffffff)
8641 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8642 ~used_bits & 0xffffffff, opc->name, opc->args);
8648 /* UDI immediates. */
8656 static const struct mips_immed mips_immed[] = {
8657 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8658 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8659 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8660 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8664 /* Check whether an odd floating-point register is allowed. */
8666 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8668 const char *s = insn->name;
8670 if (insn->pinfo == INSN_MACRO)
8671 /* Let a macro pass, we'll catch it later when it is expanded. */
8674 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8676 /* Allow odd registers for single-precision ops. */
8677 switch (insn->pinfo & (FP_S | FP_D))
8681 return 1; /* both single precision - ok */
8683 return 0; /* both double precision - fail */
8688 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8689 s = strchr (insn->name, '.');
8691 s = s != NULL ? strchr (s + 1, '.') : NULL;
8692 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8695 /* Single-precision coprocessor loads and moves are OK too. */
8696 if ((insn->pinfo & FP_S)
8697 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8698 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8704 /* This routine assembles an instruction into its binary format. As a
8705 side effect, it sets one of the global variables imm_reloc or
8706 offset_reloc to the type of relocation to do if one of the operands
8707 is an address expression. */
8710 mips_ip (char *str, struct mips_cl_insn *ip)
8715 struct mips_opcode *insn;
8718 unsigned int lastregno = 0;
8719 unsigned int lastpos = 0;
8720 unsigned int limlo, limhi;
8723 offsetT min_range, max_range;
8729 /* If the instruction contains a '.', we first try to match an instruction
8730 including the '.'. Then we try again without the '.'. */
8732 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8735 /* If we stopped on whitespace, then replace the whitespace with null for
8736 the call to hash_find. Save the character we replaced just in case we
8737 have to re-parse the instruction. */
8744 insn = (struct mips_opcode *) hash_find (op_hash, str);
8746 /* If we didn't find the instruction in the opcode table, try again, but
8747 this time with just the instruction up to, but not including the
8751 /* Restore the character we overwrite above (if any). */
8755 /* Scan up to the first '.' or whitespace. */
8757 *s != '\0' && *s != '.' && !ISSPACE (*s);
8761 /* If we did not find a '.', then we can quit now. */
8764 insn_error = "unrecognized opcode";
8768 /* Lookup the instruction in the hash table. */
8770 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8772 insn_error = "unrecognized opcode";
8782 assert (strcmp (insn->name, str) == 0);
8784 ok = is_opcode_valid (insn, FALSE);
8787 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8788 && strcmp (insn->name, insn[1].name) == 0)
8797 static char buf[100];
8799 _("opcode not supported on this processor: %s (%s)"),
8800 mips_cpu_info_from_arch (mips_opts.arch)->name,
8801 mips_cpu_info_from_isa (mips_opts.isa)->name);
8810 create_insn (ip, insn);
8813 lastregno = 0xffffffff;
8814 for (args = insn->args;; ++args)
8818 s += strspn (s, " \t");
8822 case '\0': /* end of args */
8827 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8828 my_getExpression (&imm_expr, s);
8829 check_absolute_expr (ip, &imm_expr);
8830 if ((unsigned long) imm_expr.X_add_number != 1
8831 && (unsigned long) imm_expr.X_add_number != 3)
8833 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8834 (unsigned long) imm_expr.X_add_number);
8836 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8837 imm_expr.X_op = O_absent;
8841 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8842 my_getExpression (&imm_expr, s);
8843 check_absolute_expr (ip, &imm_expr);
8844 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8846 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8847 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8849 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8850 imm_expr.X_op = O_absent;
8854 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8855 my_getExpression (&imm_expr, s);
8856 check_absolute_expr (ip, &imm_expr);
8857 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8859 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8860 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8862 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8863 imm_expr.X_op = O_absent;
8867 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8868 my_getExpression (&imm_expr, s);
8869 check_absolute_expr (ip, &imm_expr);
8870 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8872 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8873 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8875 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8876 imm_expr.X_op = O_absent;
8880 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8881 my_getExpression (&imm_expr, s);
8882 check_absolute_expr (ip, &imm_expr);
8883 if (imm_expr.X_add_number & ~OP_MASK_RS)
8885 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8886 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8888 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8889 imm_expr.X_op = O_absent;
8893 case '7': /* four dsp accumulators in bits 11,12 */
8894 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8895 s[3] >= '0' && s[3] <= '3')
8899 INSERT_OPERAND (DSPACC, *ip, regno);
8903 as_bad (_("Invalid dsp acc register"));
8906 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8907 my_getExpression (&imm_expr, s);
8908 check_absolute_expr (ip, &imm_expr);
8909 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8911 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8913 (unsigned long) imm_expr.X_add_number);
8915 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8916 imm_expr.X_op = O_absent;
8920 case '9': /* four dsp accumulators in bits 21,22 */
8921 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8922 s[3] >= '0' && s[3] <= '3')
8926 INSERT_OPERAND (DSPACC_S, *ip, regno);
8930 as_bad (_("Invalid dsp acc register"));
8933 case '0': /* dsp 6-bit signed immediate in bit 20 */
8934 my_getExpression (&imm_expr, s);
8935 check_absolute_expr (ip, &imm_expr);
8936 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8937 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8938 if (imm_expr.X_add_number < min_range ||
8939 imm_expr.X_add_number > max_range)
8941 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8942 (long) min_range, (long) max_range,
8943 (long) imm_expr.X_add_number);
8945 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8946 imm_expr.X_op = O_absent;
8950 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8951 my_getExpression (&imm_expr, s);
8952 check_absolute_expr (ip, &imm_expr);
8953 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8955 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8957 (unsigned long) imm_expr.X_add_number);
8959 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8960 imm_expr.X_op = O_absent;
8964 case ':': /* dsp 7-bit signed immediate in bit 19 */
8965 my_getExpression (&imm_expr, s);
8966 check_absolute_expr (ip, &imm_expr);
8967 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8968 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8969 if (imm_expr.X_add_number < min_range ||
8970 imm_expr.X_add_number > max_range)
8972 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8973 (long) min_range, (long) max_range,
8974 (long) imm_expr.X_add_number);
8976 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8977 imm_expr.X_op = O_absent;
8981 case '@': /* dsp 10-bit signed immediate in bit 16 */
8982 my_getExpression (&imm_expr, s);
8983 check_absolute_expr (ip, &imm_expr);
8984 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8985 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8986 if (imm_expr.X_add_number < min_range ||
8987 imm_expr.X_add_number > max_range)
8989 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8990 (long) min_range, (long) max_range,
8991 (long) imm_expr.X_add_number);
8993 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8994 imm_expr.X_op = O_absent;
8998 case '!': /* MT usermode flag bit. */
8999 my_getExpression (&imm_expr, s);
9000 check_absolute_expr (ip, &imm_expr);
9001 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9002 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9003 (unsigned long) imm_expr.X_add_number);
9004 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9005 imm_expr.X_op = O_absent;
9009 case '$': /* MT load high flag bit. */
9010 my_getExpression (&imm_expr, s);
9011 check_absolute_expr (ip, &imm_expr);
9012 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9013 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9014 (unsigned long) imm_expr.X_add_number);
9015 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9016 imm_expr.X_op = O_absent;
9020 case '*': /* four dsp accumulators in bits 18,19 */
9021 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9022 s[3] >= '0' && s[3] <= '3')
9026 INSERT_OPERAND (MTACC_T, *ip, regno);
9030 as_bad (_("Invalid dsp/smartmips acc register"));
9033 case '&': /* four dsp accumulators in bits 13,14 */
9034 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9035 s[3] >= '0' && s[3] <= '3')
9039 INSERT_OPERAND (MTACC_D, *ip, regno);
9043 as_bad (_("Invalid dsp/smartmips acc register"));
9055 INSERT_OPERAND (RS, *ip, lastregno);
9059 INSERT_OPERAND (RT, *ip, lastregno);
9063 INSERT_OPERAND (FT, *ip, lastregno);
9067 INSERT_OPERAND (FS, *ip, lastregno);
9073 /* Handle optional base register.
9074 Either the base register is omitted or
9075 we must have a left paren. */
9076 /* This is dependent on the next operand specifier
9077 is a base register specification. */
9078 assert (args[1] == 'b' || args[1] == '5'
9079 || args[1] == '-' || args[1] == '4');
9083 case ')': /* these must match exactly */
9090 case '+': /* Opcode extension character. */
9093 case '1': /* UDI immediates. */
9098 const struct mips_immed *imm = mips_immed;
9100 while (imm->type && imm->type != *args)
9104 my_getExpression (&imm_expr, s);
9105 check_absolute_expr (ip, &imm_expr);
9106 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9108 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9109 imm->desc ? imm->desc : ip->insn_mo->name,
9110 (unsigned long) imm_expr.X_add_number,
9111 (unsigned long) imm_expr.X_add_number);
9112 imm_expr.X_add_number &= imm->mask;
9114 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9116 imm_expr.X_op = O_absent;
9121 case 'A': /* ins/ext position, becomes LSB. */
9130 my_getExpression (&imm_expr, s);
9131 check_absolute_expr (ip, &imm_expr);
9132 if ((unsigned long) imm_expr.X_add_number < limlo
9133 || (unsigned long) imm_expr.X_add_number > limhi)
9135 as_bad (_("Improper position (%lu)"),
9136 (unsigned long) imm_expr.X_add_number);
9137 imm_expr.X_add_number = limlo;
9139 lastpos = imm_expr.X_add_number;
9140 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9141 imm_expr.X_op = O_absent;
9145 case 'B': /* ins size, becomes MSB. */
9154 my_getExpression (&imm_expr, s);
9155 check_absolute_expr (ip, &imm_expr);
9156 /* Check for negative input so that small negative numbers
9157 will not succeed incorrectly. The checks against
9158 (pos+size) transitively check "size" itself,
9159 assuming that "pos" is reasonable. */
9160 if ((long) imm_expr.X_add_number < 0
9161 || ((unsigned long) imm_expr.X_add_number
9163 || ((unsigned long) imm_expr.X_add_number
9166 as_bad (_("Improper insert size (%lu, position %lu)"),
9167 (unsigned long) imm_expr.X_add_number,
9168 (unsigned long) lastpos);
9169 imm_expr.X_add_number = limlo - lastpos;
9171 INSERT_OPERAND (INSMSB, *ip,
9172 lastpos + imm_expr.X_add_number - 1);
9173 imm_expr.X_op = O_absent;
9177 case 'C': /* ext size, becomes MSBD. */
9190 my_getExpression (&imm_expr, s);
9191 check_absolute_expr (ip, &imm_expr);
9192 /* Check for negative input so that small negative numbers
9193 will not succeed incorrectly. The checks against
9194 (pos+size) transitively check "size" itself,
9195 assuming that "pos" is reasonable. */
9196 if ((long) imm_expr.X_add_number < 0
9197 || ((unsigned long) imm_expr.X_add_number
9199 || ((unsigned long) imm_expr.X_add_number
9202 as_bad (_("Improper extract size (%lu, position %lu)"),
9203 (unsigned long) imm_expr.X_add_number,
9204 (unsigned long) lastpos);
9205 imm_expr.X_add_number = limlo - lastpos;
9207 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9208 imm_expr.X_op = O_absent;
9213 /* +D is for disassembly only; never match. */
9217 /* "+I" is like "I", except that imm2_expr is used. */
9218 my_getExpression (&imm2_expr, s);
9219 if (imm2_expr.X_op != O_big
9220 && imm2_expr.X_op != O_constant)
9221 insn_error = _("absolute expression required");
9222 if (HAVE_32BIT_GPRS)
9223 normalize_constant_expr (&imm2_expr);
9227 case 'T': /* Coprocessor register. */
9228 /* +T is for disassembly only; never match. */
9231 case 't': /* Coprocessor register number. */
9232 if (s[0] == '$' && ISDIGIT (s[1]))
9242 while (ISDIGIT (*s));
9244 as_bad (_("Invalid register number (%d)"), regno);
9247 INSERT_OPERAND (RT, *ip, regno);
9252 as_bad (_("Invalid coprocessor 0 register number"));
9256 /* bbit[01] and bbit[01]32 bit index. Give error if index
9257 is not in the valid range. */
9258 my_getExpression (&imm_expr, s);
9259 check_absolute_expr (ip, &imm_expr);
9260 if ((unsigned) imm_expr.X_add_number > 31)
9262 as_bad (_("Improper bit index (%lu)"),
9263 (unsigned long) imm_expr.X_add_number);
9264 imm_expr.X_add_number = 0;
9266 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9267 imm_expr.X_op = O_absent;
9272 /* bbit[01] bit index when bbit is used but we generate
9273 bbit[01]32 because the index is over 32. Move to the
9274 next candidate if index is not in the valid range. */
9275 my_getExpression (&imm_expr, s);
9276 check_absolute_expr (ip, &imm_expr);
9277 if ((unsigned) imm_expr.X_add_number < 32
9278 || (unsigned) imm_expr.X_add_number > 63)
9280 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9281 imm_expr.X_op = O_absent;
9286 /* cins, cins32, exts and exts32 position field. Give error
9287 if it's not in the valid range. */
9288 my_getExpression (&imm_expr, s);
9289 check_absolute_expr (ip, &imm_expr);
9290 if ((unsigned) imm_expr.X_add_number > 31)
9292 as_bad (_("Improper position (%lu)"),
9293 (unsigned long) imm_expr.X_add_number);
9294 imm_expr.X_add_number = 0;
9296 /* Make the pos explicit to simplify +S. */
9297 lastpos = imm_expr.X_add_number + 32;
9298 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9299 imm_expr.X_op = O_absent;
9304 /* cins, cins32, exts and exts32 position field. Move to
9305 the next candidate if it's not in the valid range. */
9306 my_getExpression (&imm_expr, s);
9307 check_absolute_expr (ip, &imm_expr);
9308 if ((unsigned) imm_expr.X_add_number < 32
9309 || (unsigned) imm_expr.X_add_number > 63)
9311 lastpos = imm_expr.X_add_number;
9312 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9313 imm_expr.X_op = O_absent;
9318 /* cins and exts length-minus-one field. */
9319 my_getExpression (&imm_expr, s);
9320 check_absolute_expr (ip, &imm_expr);
9321 if ((unsigned long) imm_expr.X_add_number > 31)
9323 as_bad (_("Improper size (%lu)"),
9324 (unsigned long) imm_expr.X_add_number);
9325 imm_expr.X_add_number = 0;
9327 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9328 imm_expr.X_op = O_absent;
9333 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9334 length-minus-one field. */
9335 my_getExpression (&imm_expr, s);
9336 check_absolute_expr (ip, &imm_expr);
9337 if ((long) imm_expr.X_add_number < 0
9338 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9340 as_bad (_("Improper size (%lu)"),
9341 (unsigned long) imm_expr.X_add_number);
9342 imm_expr.X_add_number = 0;
9344 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9345 imm_expr.X_op = O_absent;
9350 /* seqi/snei immediate field. */
9351 my_getExpression (&imm_expr, s);
9352 check_absolute_expr (ip, &imm_expr);
9353 if ((long) imm_expr.X_add_number < -512
9354 || (long) imm_expr.X_add_number >= 512)
9356 as_bad (_("Improper immediate (%ld)"),
9357 (long) imm_expr.X_add_number);
9358 imm_expr.X_add_number = 0;
9360 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9361 imm_expr.X_op = O_absent;
9366 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9367 *args, insn->name, insn->args);
9368 /* Further processing is fruitless. */
9373 case '<': /* must be at least one digit */
9375 * According to the manual, if the shift amount is greater
9376 * than 31 or less than 0, then the shift amount should be
9377 * mod 32. In reality the mips assembler issues an error.
9378 * We issue a warning and mask out all but the low 5 bits.
9380 my_getExpression (&imm_expr, s);
9381 check_absolute_expr (ip, &imm_expr);
9382 if ((unsigned long) imm_expr.X_add_number > 31)
9383 as_warn (_("Improper shift amount (%lu)"),
9384 (unsigned long) imm_expr.X_add_number);
9385 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9386 imm_expr.X_op = O_absent;
9390 case '>': /* shift amount minus 32 */
9391 my_getExpression (&imm_expr, s);
9392 check_absolute_expr (ip, &imm_expr);
9393 if ((unsigned long) imm_expr.X_add_number < 32
9394 || (unsigned long) imm_expr.X_add_number > 63)
9396 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9397 imm_expr.X_op = O_absent;
9401 case 'k': /* cache code */
9402 case 'h': /* prefx code */
9403 case '1': /* sync type */
9404 my_getExpression (&imm_expr, s);
9405 check_absolute_expr (ip, &imm_expr);
9406 if ((unsigned long) imm_expr.X_add_number > 31)
9407 as_warn (_("Invalid value for `%s' (%lu)"),
9409 (unsigned long) imm_expr.X_add_number);
9411 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9412 else if (*args == 'h')
9413 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9415 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9416 imm_expr.X_op = O_absent;
9420 case 'c': /* break code */
9421 my_getExpression (&imm_expr, s);
9422 check_absolute_expr (ip, &imm_expr);
9423 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9424 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9426 (unsigned long) imm_expr.X_add_number);
9427 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9428 imm_expr.X_op = O_absent;
9432 case 'q': /* lower break code */
9433 my_getExpression (&imm_expr, s);
9434 check_absolute_expr (ip, &imm_expr);
9435 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9436 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9438 (unsigned long) imm_expr.X_add_number);
9439 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9440 imm_expr.X_op = O_absent;
9444 case 'B': /* 20-bit syscall/break code. */
9445 my_getExpression (&imm_expr, s);
9446 check_absolute_expr (ip, &imm_expr);
9447 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9448 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9450 (unsigned long) imm_expr.X_add_number);
9451 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9452 imm_expr.X_op = O_absent;
9456 case 'C': /* Coprocessor code */
9457 my_getExpression (&imm_expr, s);
9458 check_absolute_expr (ip, &imm_expr);
9459 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9461 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9462 (unsigned long) imm_expr.X_add_number);
9463 imm_expr.X_add_number &= OP_MASK_COPZ;
9465 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9466 imm_expr.X_op = O_absent;
9470 case 'J': /* 19-bit wait code. */
9471 my_getExpression (&imm_expr, s);
9472 check_absolute_expr (ip, &imm_expr);
9473 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9475 as_warn (_("Illegal 19-bit code (%lu)"),
9476 (unsigned long) imm_expr.X_add_number);
9477 imm_expr.X_add_number &= OP_MASK_CODE19;
9479 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9480 imm_expr.X_op = O_absent;
9484 case 'P': /* Performance register. */
9485 my_getExpression (&imm_expr, s);
9486 check_absolute_expr (ip, &imm_expr);
9487 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9488 as_warn (_("Invalid performance register (%lu)"),
9489 (unsigned long) imm_expr.X_add_number);
9490 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9491 imm_expr.X_op = O_absent;
9495 case 'G': /* Coprocessor destination register. */
9496 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9497 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9499 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9500 INSERT_OPERAND (RD, *ip, regno);
9509 case 'b': /* base register */
9510 case 'd': /* destination register */
9511 case 's': /* source register */
9512 case 't': /* target register */
9513 case 'r': /* both target and source */
9514 case 'v': /* both dest and source */
9515 case 'w': /* both dest and target */
9516 case 'E': /* coprocessor target register */
9517 case 'K': /* 'rdhwr' destination register */
9518 case 'x': /* ignore register name */
9519 case 'z': /* must be zero register */
9520 case 'U': /* destination register (clo/clz). */
9521 case 'g': /* coprocessor destination register */
9523 if (*args == 'E' || *args == 'K')
9524 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9527 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9528 if (regno == AT && mips_opts.at)
9530 if (mips_opts.at == ATREG)
9531 as_warn (_("used $at without \".set noat\""));
9533 as_warn (_("used $%u with \".set at=$%u\""),
9534 regno, mips_opts.at);
9544 if (c == 'r' || c == 'v' || c == 'w')
9551 /* 'z' only matches $0. */
9552 if (c == 'z' && regno != 0)
9555 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9557 if (regno == lastregno)
9559 insn_error = _("source and destination must be different");
9562 if (regno == 31 && lastregno == 0xffffffff)
9564 insn_error = _("a destination register must be supplied");
9568 /* Now that we have assembled one operand, we use the args string
9569 * to figure out where it goes in the instruction. */
9576 INSERT_OPERAND (RS, *ip, regno);
9582 INSERT_OPERAND (RD, *ip, regno);
9585 INSERT_OPERAND (RD, *ip, regno);
9586 INSERT_OPERAND (RT, *ip, regno);
9591 INSERT_OPERAND (RT, *ip, regno);
9594 /* This case exists because on the r3000 trunc
9595 expands into a macro which requires a gp
9596 register. On the r6000 or r4000 it is
9597 assembled into a single instruction which
9598 ignores the register. Thus the insn version
9599 is MIPS_ISA2 and uses 'x', and the macro
9600 version is MIPS_ISA1 and uses 't'. */
9603 /* This case is for the div instruction, which
9604 acts differently if the destination argument
9605 is $0. This only matches $0, and is checked
9606 outside the switch. */
9609 /* Itbl operand; not yet implemented. FIXME ?? */
9611 /* What about all other operands like 'i', which
9612 can be specified in the opcode table? */
9621 INSERT_OPERAND (RS, *ip, lastregno);
9624 INSERT_OPERAND (RT, *ip, lastregno);
9629 case 'O': /* MDMX alignment immediate constant. */
9630 my_getExpression (&imm_expr, s);
9631 check_absolute_expr (ip, &imm_expr);
9632 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9633 as_warn ("Improper align amount (%ld), using low bits",
9634 (long) imm_expr.X_add_number);
9635 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9636 imm_expr.X_op = O_absent;
9640 case 'Q': /* MDMX vector, element sel, or const. */
9643 /* MDMX Immediate. */
9644 my_getExpression (&imm_expr, s);
9645 check_absolute_expr (ip, &imm_expr);
9646 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9647 as_warn (_("Invalid MDMX Immediate (%ld)"),
9648 (long) imm_expr.X_add_number);
9649 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9650 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9651 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9653 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9654 imm_expr.X_op = O_absent;
9658 /* Not MDMX Immediate. Fall through. */
9659 case 'X': /* MDMX destination register. */
9660 case 'Y': /* MDMX source register. */
9661 case 'Z': /* MDMX target register. */
9663 case 'D': /* floating point destination register */
9664 case 'S': /* floating point source register */
9665 case 'T': /* floating point target register */
9666 case 'R': /* floating point source register */
9671 || (mips_opts.ase_mdmx
9672 && (ip->insn_mo->pinfo & FP_D)
9673 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9674 | INSN_COPROC_MEMORY_DELAY
9675 | INSN_LOAD_COPROC_DELAY
9676 | INSN_LOAD_MEMORY_DELAY
9677 | INSN_STORE_MEMORY))))
9680 if (reg_lookup (&s, rtype, ®no))
9682 if ((regno & 1) != 0
9684 && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
9685 as_warn (_("Float register should be even, was %d"),
9693 if (c == 'V' || c == 'W')
9704 INSERT_OPERAND (FD, *ip, regno);
9709 INSERT_OPERAND (FS, *ip, regno);
9712 /* This is like 'Z', but also needs to fix the MDMX
9713 vector/scalar select bits. Note that the
9714 scalar immediate case is handled above. */
9717 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9718 int max_el = (is_qh ? 3 : 7);
9720 my_getExpression(&imm_expr, s);
9721 check_absolute_expr (ip, &imm_expr);
9723 if (imm_expr.X_add_number > max_el)
9724 as_bad(_("Bad element selector %ld"),
9725 (long) imm_expr.X_add_number);
9726 imm_expr.X_add_number &= max_el;
9727 ip->insn_opcode |= (imm_expr.X_add_number
9730 imm_expr.X_op = O_absent;
9732 as_warn(_("Expecting ']' found '%s'"), s);
9738 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9739 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9742 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9749 INSERT_OPERAND (FT, *ip, regno);
9752 INSERT_OPERAND (FR, *ip, regno);
9762 INSERT_OPERAND (FS, *ip, lastregno);
9765 INSERT_OPERAND (FT, *ip, lastregno);
9771 my_getExpression (&imm_expr, s);
9772 if (imm_expr.X_op != O_big
9773 && imm_expr.X_op != O_constant)
9774 insn_error = _("absolute expression required");
9775 if (HAVE_32BIT_GPRS)
9776 normalize_constant_expr (&imm_expr);
9781 my_getExpression (&offset_expr, s);
9782 normalize_address_expr (&offset_expr);
9783 *imm_reloc = BFD_RELOC_32;
9796 unsigned char temp[8];
9798 unsigned int length;
9803 /* These only appear as the last operand in an
9804 instruction, and every instruction that accepts
9805 them in any variant accepts them in all variants.
9806 This means we don't have to worry about backing out
9807 any changes if the instruction does not match.
9809 The difference between them is the size of the
9810 floating point constant and where it goes. For 'F'
9811 and 'L' the constant is 64 bits; for 'f' and 'l' it
9812 is 32 bits. Where the constant is placed is based
9813 on how the MIPS assembler does things:
9816 f -- immediate value
9819 The .lit4 and .lit8 sections are only used if
9820 permitted by the -G argument.
9822 The code below needs to know whether the target register
9823 is 32 or 64 bits wide. It relies on the fact 'f' and
9824 'F' are used with GPR-based instructions and 'l' and
9825 'L' are used with FPR-based instructions. */
9827 f64 = *args == 'F' || *args == 'L';
9828 using_gprs = *args == 'F' || *args == 'f';
9830 save_in = input_line_pointer;
9831 input_line_pointer = s;
9832 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9834 s = input_line_pointer;
9835 input_line_pointer = save_in;
9836 if (err != NULL && *err != '\0')
9838 as_bad (_("Bad floating point constant: %s"), err);
9839 memset (temp, '\0', sizeof temp);
9840 length = f64 ? 8 : 4;
9843 assert (length == (unsigned) (f64 ? 8 : 4));
9847 && (g_switch_value < 4
9848 || (temp[0] == 0 && temp[1] == 0)
9849 || (temp[2] == 0 && temp[3] == 0))))
9851 imm_expr.X_op = O_constant;
9852 if (! target_big_endian)
9853 imm_expr.X_add_number = bfd_getl32 (temp);
9855 imm_expr.X_add_number = bfd_getb32 (temp);
9858 && ! mips_disable_float_construction
9859 /* Constants can only be constructed in GPRs and
9860 copied to FPRs if the GPRs are at least as wide
9861 as the FPRs. Force the constant into memory if
9862 we are using 64-bit FPRs but the GPRs are only
9865 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9866 && ((temp[0] == 0 && temp[1] == 0)
9867 || (temp[2] == 0 && temp[3] == 0))
9868 && ((temp[4] == 0 && temp[5] == 0)
9869 || (temp[6] == 0 && temp[7] == 0)))
9871 /* The value is simple enough to load with a couple of
9872 instructions. If using 32-bit registers, set
9873 imm_expr to the high order 32 bits and offset_expr to
9874 the low order 32 bits. Otherwise, set imm_expr to
9875 the entire 64 bit constant. */
9876 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9878 imm_expr.X_op = O_constant;
9879 offset_expr.X_op = O_constant;
9880 if (! target_big_endian)
9882 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9883 offset_expr.X_add_number = bfd_getl32 (temp);
9887 imm_expr.X_add_number = bfd_getb32 (temp);
9888 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9890 if (offset_expr.X_add_number == 0)
9891 offset_expr.X_op = O_absent;
9893 else if (sizeof (imm_expr.X_add_number) > 4)
9895 imm_expr.X_op = O_constant;
9896 if (! target_big_endian)
9897 imm_expr.X_add_number = bfd_getl64 (temp);
9899 imm_expr.X_add_number = bfd_getb64 (temp);
9903 imm_expr.X_op = O_big;
9904 imm_expr.X_add_number = 4;
9905 if (! target_big_endian)
9907 generic_bignum[0] = bfd_getl16 (temp);
9908 generic_bignum[1] = bfd_getl16 (temp + 2);
9909 generic_bignum[2] = bfd_getl16 (temp + 4);
9910 generic_bignum[3] = bfd_getl16 (temp + 6);
9914 generic_bignum[0] = bfd_getb16 (temp + 6);
9915 generic_bignum[1] = bfd_getb16 (temp + 4);
9916 generic_bignum[2] = bfd_getb16 (temp + 2);
9917 generic_bignum[3] = bfd_getb16 (temp);
9923 const char *newname;
9926 /* Switch to the right section. */
9928 subseg = now_subseg;
9931 default: /* unused default case avoids warnings. */
9933 newname = RDATA_SECTION_NAME;
9934 if (g_switch_value >= 8)
9938 newname = RDATA_SECTION_NAME;
9941 assert (g_switch_value >= 4);
9945 new_seg = subseg_new (newname, (subsegT) 0);
9947 bfd_set_section_flags (stdoutput, new_seg,
9952 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9953 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
9954 record_alignment (new_seg, 4);
9956 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9958 as_bad (_("Can't use floating point insn in this section"));
9960 /* Set the argument to the current address in the
9962 offset_expr.X_op = O_symbol;
9963 offset_expr.X_add_symbol =
9964 symbol_new ("L0\001", now_seg,
9965 (valueT) frag_now_fix (), frag_now);
9966 offset_expr.X_add_number = 0;
9968 /* Put the floating point number into the section. */
9969 p = frag_more ((int) length);
9970 memcpy (p, temp, length);
9972 /* Switch back to the original section. */
9973 subseg_set (seg, subseg);
9978 case 'i': /* 16 bit unsigned immediate */
9979 case 'j': /* 16 bit signed immediate */
9980 *imm_reloc = BFD_RELOC_LO16;
9981 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9984 offsetT minval, maxval;
9986 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9987 && strcmp (insn->name, insn[1].name) == 0);
9989 /* If the expression was written as an unsigned number,
9990 only treat it as signed if there are no more
9994 && sizeof (imm_expr.X_add_number) <= 4
9995 && imm_expr.X_op == O_constant
9996 && imm_expr.X_add_number < 0
9997 && imm_expr.X_unsigned
10001 /* For compatibility with older assemblers, we accept
10002 0x8000-0xffff as signed 16-bit numbers when only
10003 signed numbers are allowed. */
10005 minval = 0, maxval = 0xffff;
10007 minval = -0x8000, maxval = 0x7fff;
10009 minval = -0x8000, maxval = 0xffff;
10011 if (imm_expr.X_op != O_constant
10012 || imm_expr.X_add_number < minval
10013 || imm_expr.X_add_number > maxval)
10017 if (imm_expr.X_op == O_constant
10018 || imm_expr.X_op == O_big)
10019 as_bad (_("expression out of range"));
10025 case 'o': /* 16 bit offset */
10026 /* Check whether there is only a single bracketed expression
10027 left. If so, it must be the base register and the
10028 constant must be zero. */
10029 if (*s == '(' && strchr (s + 1, '(') == 0)
10031 offset_expr.X_op = O_constant;
10032 offset_expr.X_add_number = 0;
10036 /* If this value won't fit into a 16 bit offset, then go
10037 find a macro that will generate the 32 bit offset
10039 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10040 && (offset_expr.X_op != O_constant
10041 || offset_expr.X_add_number >= 0x8000
10042 || offset_expr.X_add_number < -0x8000))
10048 case 'p': /* pc relative offset */
10049 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10050 my_getExpression (&offset_expr, s);
10054 case 'u': /* upper 16 bits */
10055 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10056 && imm_expr.X_op == O_constant
10057 && (imm_expr.X_add_number < 0
10058 || imm_expr.X_add_number >= 0x10000))
10059 as_bad (_("lui expression not in range 0..65535"));
10063 case 'a': /* 26 bit address */
10064 my_getExpression (&offset_expr, s);
10066 *offset_reloc = BFD_RELOC_MIPS_JMP;
10069 case 'N': /* 3 bit branch condition code */
10070 case 'M': /* 3 bit compare condition code */
10072 if (ip->insn_mo->pinfo & (FP_D| FP_S))
10073 rtype |= RTYPE_FCC;
10074 if (!reg_lookup (&s, rtype, ®no))
10076 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
10077 || strcmp(str + strlen(str) - 5, "any2f") == 0
10078 || strcmp(str + strlen(str) - 5, "any2t") == 0)
10079 && (regno & 1) != 0)
10080 as_warn(_("Condition code register should be even for %s, was %d"),
10082 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
10083 || strcmp(str + strlen(str) - 5, "any4t") == 0)
10084 && (regno & 3) != 0)
10085 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
10088 INSERT_OPERAND (BCC, *ip, regno);
10090 INSERT_OPERAND (CCC, *ip, regno);
10094 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10105 while (ISDIGIT (*s));
10108 c = 8; /* Invalid sel value. */
10111 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
10112 ip->insn_opcode |= c;
10116 /* Must be at least one digit. */
10117 my_getExpression (&imm_expr, s);
10118 check_absolute_expr (ip, &imm_expr);
10120 if ((unsigned long) imm_expr.X_add_number
10121 > (unsigned long) OP_MASK_VECBYTE)
10123 as_bad (_("bad byte vector index (%ld)"),
10124 (long) imm_expr.X_add_number);
10125 imm_expr.X_add_number = 0;
10128 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10129 imm_expr.X_op = O_absent;
10134 my_getExpression (&imm_expr, s);
10135 check_absolute_expr (ip, &imm_expr);
10137 if ((unsigned long) imm_expr.X_add_number
10138 > (unsigned long) OP_MASK_VECALIGN)
10140 as_bad (_("bad byte vector index (%ld)"),
10141 (long) imm_expr.X_add_number);
10142 imm_expr.X_add_number = 0;
10145 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10146 imm_expr.X_op = O_absent;
10151 as_bad (_("bad char = '%c'\n"), *args);
10156 /* Args don't match. */
10157 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10158 !strcmp (insn->name, insn[1].name))
10162 insn_error = _("illegal operands");
10166 *(--argsStart) = save_c;
10167 insn_error = _("illegal operands");
10172 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10174 /* This routine assembles an instruction into its binary format when
10175 assembling for the mips16. As a side effect, it sets one of the
10176 global variables imm_reloc or offset_reloc to the type of
10177 relocation to do if one of the operands is an address expression.
10178 It also sets mips16_small and mips16_ext if the user explicitly
10179 requested a small or extended instruction. */
10182 mips16_ip (char *str, struct mips_cl_insn *ip)
10186 struct mips_opcode *insn;
10188 unsigned int regno;
10189 unsigned int lastregno = 0;
10195 mips16_small = FALSE;
10196 mips16_ext = FALSE;
10198 for (s = str; ISLOWER (*s); ++s)
10210 if (s[1] == 't' && s[2] == ' ')
10213 mips16_small = TRUE;
10217 else if (s[1] == 'e' && s[2] == ' ')
10224 /* Fall through. */
10226 insn_error = _("unknown opcode");
10230 if (mips_opts.noautoextend && ! mips16_ext)
10231 mips16_small = TRUE;
10233 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10235 insn_error = _("unrecognized opcode");
10244 assert (strcmp (insn->name, str) == 0);
10246 ok = is_opcode_valid_16 (insn);
10249 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10250 && strcmp (insn->name, insn[1].name) == 0)
10259 static char buf[100];
10261 _("opcode not supported on this processor: %s (%s)"),
10262 mips_cpu_info_from_arch (mips_opts.arch)->name,
10263 mips_cpu_info_from_isa (mips_opts.isa)->name);
10270 create_insn (ip, insn);
10271 imm_expr.X_op = O_absent;
10272 imm_reloc[0] = BFD_RELOC_UNUSED;
10273 imm_reloc[1] = BFD_RELOC_UNUSED;
10274 imm_reloc[2] = BFD_RELOC_UNUSED;
10275 imm2_expr.X_op = O_absent;
10276 offset_expr.X_op = O_absent;
10277 offset_reloc[0] = BFD_RELOC_UNUSED;
10278 offset_reloc[1] = BFD_RELOC_UNUSED;
10279 offset_reloc[2] = BFD_RELOC_UNUSED;
10280 for (args = insn->args; 1; ++args)
10287 /* In this switch statement we call break if we did not find
10288 a match, continue if we did find a match, or return if we
10297 /* Stuff the immediate value in now, if we can. */
10298 if (imm_expr.X_op == O_constant
10299 && *imm_reloc > BFD_RELOC_UNUSED
10300 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10301 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10302 && insn->pinfo != INSN_MACRO)
10306 switch (*offset_reloc)
10308 case BFD_RELOC_MIPS16_HI16_S:
10309 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10312 case BFD_RELOC_MIPS16_HI16:
10313 tmp = imm_expr.X_add_number >> 16;
10316 case BFD_RELOC_MIPS16_LO16:
10317 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10321 case BFD_RELOC_UNUSED:
10322 tmp = imm_expr.X_add_number;
10328 *offset_reloc = BFD_RELOC_UNUSED;
10330 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10331 tmp, TRUE, mips16_small,
10332 mips16_ext, &ip->insn_opcode,
10333 &ip->use_extend, &ip->extend);
10334 imm_expr.X_op = O_absent;
10335 *imm_reloc = BFD_RELOC_UNUSED;
10349 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10352 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10368 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10370 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10374 /* Fall through. */
10385 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10387 if (c == 'v' || c == 'w')
10390 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10392 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10403 if (c == 'v' || c == 'w')
10405 regno = mips16_to_32_reg_map[lastregno];
10419 regno = mips32_to_16_reg_map[regno];
10424 regno = ILLEGAL_REG;
10429 regno = ILLEGAL_REG;
10434 regno = ILLEGAL_REG;
10439 if (regno == AT && mips_opts.at)
10441 if (mips_opts.at == ATREG)
10442 as_warn (_("used $at without \".set noat\""));
10444 as_warn (_("used $%u with \".set at=$%u\""),
10445 regno, mips_opts.at);
10453 if (regno == ILLEGAL_REG)
10460 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10464 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10467 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10470 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10476 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10479 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10480 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10490 if (strncmp (s, "$pc", 3) == 0)
10507 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10510 if (imm_expr.X_op != O_constant)
10513 ip->use_extend = TRUE;
10518 /* We need to relax this instruction. */
10519 *offset_reloc = *imm_reloc;
10520 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10525 *imm_reloc = BFD_RELOC_UNUSED;
10526 /* Fall through. */
10533 my_getExpression (&imm_expr, s);
10534 if (imm_expr.X_op == O_register)
10536 /* What we thought was an expression turned out to
10539 if (s[0] == '(' && args[1] == '(')
10541 /* It looks like the expression was omitted
10542 before a register indirection, which means
10543 that the expression is implicitly zero. We
10544 still set up imm_expr, so that we handle
10545 explicit extensions correctly. */
10546 imm_expr.X_op = O_constant;
10547 imm_expr.X_add_number = 0;
10548 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10555 /* We need to relax this instruction. */
10556 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10565 /* We use offset_reloc rather than imm_reloc for the PC
10566 relative operands. This lets macros with both
10567 immediate and address operands work correctly. */
10568 my_getExpression (&offset_expr, s);
10570 if (offset_expr.X_op == O_register)
10573 /* We need to relax this instruction. */
10574 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10578 case '6': /* break code */
10579 my_getExpression (&imm_expr, s);
10580 check_absolute_expr (ip, &imm_expr);
10581 if ((unsigned long) imm_expr.X_add_number > 63)
10582 as_warn (_("Invalid value for `%s' (%lu)"),
10584 (unsigned long) imm_expr.X_add_number);
10585 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10586 imm_expr.X_op = O_absent;
10590 case 'a': /* 26 bit address */
10591 my_getExpression (&offset_expr, s);
10593 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10594 ip->insn_opcode <<= 16;
10597 case 'l': /* register list for entry macro */
10598 case 'L': /* register list for exit macro */
10608 unsigned int freg, reg1, reg2;
10610 while (*s == ' ' || *s == ',')
10612 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10614 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10618 as_bad (_("can't parse register list"));
10628 if (!reg_lookup (&s, freg ? RTYPE_FPU
10629 : (RTYPE_GP | RTYPE_NUM), ®2))
10631 as_bad (_("invalid register list"));
10635 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10637 mask &= ~ (7 << 3);
10640 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10642 mask &= ~ (7 << 3);
10645 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10646 mask |= (reg2 - 3) << 3;
10647 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10648 mask |= (reg2 - 15) << 1;
10649 else if (reg1 == RA && reg2 == RA)
10653 as_bad (_("invalid register list"));
10657 /* The mask is filled in in the opcode table for the
10658 benefit of the disassembler. We remove it before
10659 applying the actual mask. */
10660 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10661 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10665 case 'm': /* Register list for save insn. */
10666 case 'M': /* Register list for restore insn. */
10669 int framesz = 0, seen_framesz = 0;
10670 int args = 0, statics = 0, sregs = 0;
10674 unsigned int reg1, reg2;
10676 SKIP_SPACE_TABS (s);
10679 SKIP_SPACE_TABS (s);
10681 my_getExpression (&imm_expr, s);
10682 if (imm_expr.X_op == O_constant)
10684 /* Handle the frame size. */
10687 as_bad (_("more than one frame size in list"));
10691 framesz = imm_expr.X_add_number;
10692 imm_expr.X_op = O_absent;
10697 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10699 as_bad (_("can't parse register list"));
10711 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10714 as_bad (_("can't parse register list"));
10719 while (reg1 <= reg2)
10721 if (reg1 >= 4 && reg1 <= 7)
10725 args |= 1 << (reg1 - 4);
10727 /* statics $a0-$a3 */
10728 statics |= 1 << (reg1 - 4);
10730 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10733 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10735 else if (reg1 == 31)
10737 /* Add $ra to insn. */
10742 as_bad (_("unexpected register in list"));
10750 /* Encode args/statics combination. */
10751 if (args & statics)
10752 as_bad (_("arg/static registers overlap"));
10753 else if (args == 0xf)
10754 /* All $a0-$a3 are args. */
10755 opcode |= MIPS16_ALL_ARGS << 16;
10756 else if (statics == 0xf)
10757 /* All $a0-$a3 are statics. */
10758 opcode |= MIPS16_ALL_STATICS << 16;
10761 int narg = 0, nstat = 0;
10763 /* Count arg registers. */
10770 as_bad (_("invalid arg register list"));
10772 /* Count static registers. */
10773 while (statics & 0x8)
10775 statics = (statics << 1) & 0xf;
10779 as_bad (_("invalid static register list"));
10781 /* Encode args/statics. */
10782 opcode |= ((narg << 2) | nstat) << 16;
10785 /* Encode $s0/$s1. */
10786 if (sregs & (1 << 0)) /* $s0 */
10788 if (sregs & (1 << 1)) /* $s1 */
10794 /* Count regs $s2-$s8. */
10802 as_bad (_("invalid static register list"));
10803 /* Encode $s2-$s8. */
10804 opcode |= nsreg << 24;
10807 /* Encode frame size. */
10809 as_bad (_("missing frame size"));
10810 else if ((framesz & 7) != 0 || framesz < 0
10811 || framesz > 0xff * 8)
10812 as_bad (_("invalid frame size"));
10813 else if (framesz != 128 || (opcode >> 16) != 0)
10816 opcode |= (((framesz & 0xf0) << 16)
10817 | (framesz & 0x0f));
10820 /* Finally build the instruction. */
10821 if ((opcode >> 16) != 0 || framesz == 0)
10823 ip->use_extend = TRUE;
10824 ip->extend = opcode >> 16;
10826 ip->insn_opcode |= opcode & 0x7f;
10830 case 'e': /* extend code */
10831 my_getExpression (&imm_expr, s);
10832 check_absolute_expr (ip, &imm_expr);
10833 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10835 as_warn (_("Invalid value for `%s' (%lu)"),
10837 (unsigned long) imm_expr.X_add_number);
10838 imm_expr.X_add_number &= 0x7ff;
10840 ip->insn_opcode |= imm_expr.X_add_number;
10841 imm_expr.X_op = O_absent;
10851 /* Args don't match. */
10852 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10853 strcmp (insn->name, insn[1].name) == 0)
10860 insn_error = _("illegal operands");
10866 /* This structure holds information we know about a mips16 immediate
10869 struct mips16_immed_operand
10871 /* The type code used in the argument string in the opcode table. */
10873 /* The number of bits in the short form of the opcode. */
10875 /* The number of bits in the extended form of the opcode. */
10877 /* The amount by which the short form is shifted when it is used;
10878 for example, the sw instruction has a shift count of 2. */
10880 /* The amount by which the short form is shifted when it is stored
10881 into the instruction code. */
10883 /* Non-zero if the short form is unsigned. */
10885 /* Non-zero if the extended form is unsigned. */
10887 /* Non-zero if the value is PC relative. */
10891 /* The mips16 immediate operand types. */
10893 static const struct mips16_immed_operand mips16_immed_operands[] =
10895 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10896 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10897 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10898 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10899 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10900 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10901 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10902 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10903 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10904 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10905 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10906 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10907 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10908 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10909 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10910 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10911 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10912 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10913 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10914 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10915 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10918 #define MIPS16_NUM_IMMED \
10919 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10921 /* Handle a mips16 instruction with an immediate value. This or's the
10922 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10923 whether an extended value is needed; if one is needed, it sets
10924 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10925 If SMALL is true, an unextended opcode was explicitly requested.
10926 If EXT is true, an extended opcode was explicitly requested. If
10927 WARN is true, warn if EXT does not match reality. */
10930 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10931 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10932 unsigned long *insn, bfd_boolean *use_extend,
10933 unsigned short *extend)
10935 const struct mips16_immed_operand *op;
10936 int mintiny, maxtiny;
10937 bfd_boolean needext;
10939 op = mips16_immed_operands;
10940 while (op->type != type)
10943 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10948 if (type == '<' || type == '>' || type == '[' || type == ']')
10951 maxtiny = 1 << op->nbits;
10956 maxtiny = (1 << op->nbits) - 1;
10961 mintiny = - (1 << (op->nbits - 1));
10962 maxtiny = (1 << (op->nbits - 1)) - 1;
10965 /* Branch offsets have an implicit 0 in the lowest bit. */
10966 if (type == 'p' || type == 'q')
10969 if ((val & ((1 << op->shift) - 1)) != 0
10970 || val < (mintiny << op->shift)
10971 || val > (maxtiny << op->shift))
10976 if (warn && ext && ! needext)
10977 as_warn_where (file, line,
10978 _("extended operand requested but not required"));
10979 if (small && needext)
10980 as_bad_where (file, line, _("invalid unextended operand value"));
10982 if (small || (! ext && ! needext))
10986 *use_extend = FALSE;
10987 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10988 insnval <<= op->op_shift;
10993 long minext, maxext;
10999 maxext = (1 << op->extbits) - 1;
11003 minext = - (1 << (op->extbits - 1));
11004 maxext = (1 << (op->extbits - 1)) - 1;
11006 if (val < minext || val > maxext)
11007 as_bad_where (file, line,
11008 _("operand value out of range for instruction"));
11010 *use_extend = TRUE;
11011 if (op->extbits == 16)
11013 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11016 else if (op->extbits == 15)
11018 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11023 extval = ((val & 0x1f) << 6) | (val & 0x20);
11027 *extend = (unsigned short) extval;
11032 struct percent_op_match
11035 bfd_reloc_code_real_type reloc;
11038 static const struct percent_op_match mips_percent_op[] =
11040 {"%lo", BFD_RELOC_LO16},
11042 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11043 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11044 {"%call16", BFD_RELOC_MIPS_CALL16},
11045 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11046 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11047 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11048 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11049 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11050 {"%got", BFD_RELOC_MIPS_GOT16},
11051 {"%gp_rel", BFD_RELOC_GPREL16},
11052 {"%half", BFD_RELOC_16},
11053 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11054 {"%higher", BFD_RELOC_MIPS_HIGHER},
11055 {"%neg", BFD_RELOC_MIPS_SUB},
11056 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11057 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11058 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11059 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11060 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11061 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11062 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11064 {"%hi", BFD_RELOC_HI16_S}
11067 static const struct percent_op_match mips16_percent_op[] =
11069 {"%lo", BFD_RELOC_MIPS16_LO16},
11070 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11071 {"%got", BFD_RELOC_MIPS16_GOT16},
11072 {"%call16", BFD_RELOC_MIPS16_CALL16},
11073 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11077 /* Return true if *STR points to a relocation operator. When returning true,
11078 move *STR over the operator and store its relocation code in *RELOC.
11079 Leave both *STR and *RELOC alone when returning false. */
11082 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11084 const struct percent_op_match *percent_op;
11087 if (mips_opts.mips16)
11089 percent_op = mips16_percent_op;
11090 limit = ARRAY_SIZE (mips16_percent_op);
11094 percent_op = mips_percent_op;
11095 limit = ARRAY_SIZE (mips_percent_op);
11098 for (i = 0; i < limit; i++)
11099 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11101 int len = strlen (percent_op[i].str);
11103 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11106 *str += strlen (percent_op[i].str);
11107 *reloc = percent_op[i].reloc;
11109 /* Check whether the output BFD supports this relocation.
11110 If not, issue an error and fall back on something safe. */
11111 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11113 as_bad ("relocation %s isn't supported by the current ABI",
11114 percent_op[i].str);
11115 *reloc = BFD_RELOC_UNUSED;
11123 /* Parse string STR as a 16-bit relocatable operand. Store the
11124 expression in *EP and the relocations in the array starting
11125 at RELOC. Return the number of relocation operators used.
11127 On exit, EXPR_END points to the first character after the expression. */
11130 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11133 bfd_reloc_code_real_type reversed_reloc[3];
11134 size_t reloc_index, i;
11135 int crux_depth, str_depth;
11138 /* Search for the start of the main expression, recoding relocations
11139 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11140 of the main expression and with CRUX_DEPTH containing the number
11141 of open brackets at that point. */
11148 crux_depth = str_depth;
11150 /* Skip over whitespace and brackets, keeping count of the number
11152 while (*str == ' ' || *str == '\t' || *str == '(')
11157 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11158 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11160 my_getExpression (ep, crux);
11163 /* Match every open bracket. */
11164 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11168 if (crux_depth > 0)
11169 as_bad ("unclosed '('");
11173 if (reloc_index != 0)
11175 prev_reloc_op_frag = frag_now;
11176 for (i = 0; i < reloc_index; i++)
11177 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11180 return reloc_index;
11184 my_getExpression (expressionS *ep, char *str)
11189 save_in = input_line_pointer;
11190 input_line_pointer = str;
11192 expr_end = input_line_pointer;
11193 input_line_pointer = save_in;
11195 /* If we are in mips16 mode, and this is an expression based on `.',
11196 then we bump the value of the symbol by 1 since that is how other
11197 text symbols are handled. We don't bother to handle complex
11198 expressions, just `.' plus or minus a constant. */
11199 if (mips_opts.mips16
11200 && ep->X_op == O_symbol
11201 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
11202 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
11203 && symbol_get_frag (ep->X_add_symbol) == frag_now
11204 && symbol_constant_p (ep->X_add_symbol)
11205 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
11206 S_SET_VALUE (ep->X_add_symbol, val + 1);
11210 md_atof (int type, char *litP, int *sizeP)
11212 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11216 md_number_to_chars (char *buf, valueT val, int n)
11218 if (target_big_endian)
11219 number_to_chars_bigendian (buf, val, n);
11221 number_to_chars_littleendian (buf, val, n);
11225 static int support_64bit_objects(void)
11227 const char **list, **l;
11230 list = bfd_target_list ();
11231 for (l = list; *l != NULL; l++)
11233 /* This is traditional mips */
11234 if (strcmp (*l, "elf64-tradbigmips") == 0
11235 || strcmp (*l, "elf64-tradlittlemips") == 0)
11237 if (strcmp (*l, "elf64-bigmips") == 0
11238 || strcmp (*l, "elf64-littlemips") == 0)
11241 yes = (*l != NULL);
11245 #endif /* OBJ_ELF */
11247 const char *md_shortopts = "O::g::G:";
11251 OPTION_MARCH = OPTION_MD_BASE,
11273 OPTION_NO_SMARTMIPS,
11276 OPTION_COMPAT_ARCH_BASE,
11285 OPTION_M7000_HILO_FIX,
11286 OPTION_MNO_7000_HILO_FIX,
11290 OPTION_NO_FIX_VR4120,
11292 OPTION_NO_FIX_VR4130,
11299 OPTION_CONSTRUCT_FLOATS,
11300 OPTION_NO_CONSTRUCT_FLOATS,
11303 OPTION_RELAX_BRANCH,
11304 OPTION_NO_RELAX_BRANCH,
11311 OPTION_SINGLE_FLOAT,
11312 OPTION_DOUBLE_FLOAT,
11315 OPTION_CALL_SHARED,
11316 OPTION_CALL_NONPIC,
11326 OPTION_MVXWORKS_PIC,
11327 #endif /* OBJ_ELF */
11331 struct option md_longopts[] =
11333 /* Options which specify architecture. */
11334 {"march", required_argument, NULL, OPTION_MARCH},
11335 {"mtune", required_argument, NULL, OPTION_MTUNE},
11336 {"mips0", no_argument, NULL, OPTION_MIPS1},
11337 {"mips1", no_argument, NULL, OPTION_MIPS1},
11338 {"mips2", no_argument, NULL, OPTION_MIPS2},
11339 {"mips3", no_argument, NULL, OPTION_MIPS3},
11340 {"mips4", no_argument, NULL, OPTION_MIPS4},
11341 {"mips5", no_argument, NULL, OPTION_MIPS5},
11342 {"mips32", no_argument, NULL, OPTION_MIPS32},
11343 {"mips64", no_argument, NULL, OPTION_MIPS64},
11344 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11345 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11347 /* Options which specify Application Specific Extensions (ASEs). */
11348 {"mips16", no_argument, NULL, OPTION_MIPS16},
11349 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11350 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11351 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11352 {"mdmx", no_argument, NULL, OPTION_MDMX},
11353 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11354 {"mdsp", no_argument, NULL, OPTION_DSP},
11355 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11356 {"mmt", no_argument, NULL, OPTION_MT},
11357 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11358 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11359 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11360 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11361 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11363 /* Old-style architecture options. Don't add more of these. */
11364 {"m4650", no_argument, NULL, OPTION_M4650},
11365 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11366 {"m4010", no_argument, NULL, OPTION_M4010},
11367 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11368 {"m4100", no_argument, NULL, OPTION_M4100},
11369 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11370 {"m3900", no_argument, NULL, OPTION_M3900},
11371 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11373 /* Options which enable bug fixes. */
11374 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11375 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11376 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11377 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11378 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11379 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11380 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11381 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11382 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11384 /* Miscellaneous options. */
11385 {"trap", no_argument, NULL, OPTION_TRAP},
11386 {"no-break", no_argument, NULL, OPTION_TRAP},
11387 {"break", no_argument, NULL, OPTION_BREAK},
11388 {"no-trap", no_argument, NULL, OPTION_BREAK},
11389 {"EB", no_argument, NULL, OPTION_EB},
11390 {"EL", no_argument, NULL, OPTION_EL},
11391 {"mfp32", no_argument, NULL, OPTION_FP32},
11392 {"mgp32", no_argument, NULL, OPTION_GP32},
11393 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11394 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11395 {"mfp64", no_argument, NULL, OPTION_FP64},
11396 {"mgp64", no_argument, NULL, OPTION_GP64},
11397 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11398 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11399 {"mshared", no_argument, NULL, OPTION_MSHARED},
11400 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11401 {"msym32", no_argument, NULL, OPTION_MSYM32},
11402 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11403 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11404 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11405 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11406 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11408 /* Strictly speaking this next option is ELF specific,
11409 but we allow it for other ports as well in order to
11410 make testing easier. */
11411 {"32", no_argument, NULL, OPTION_32},
11413 /* ELF-specific options. */
11415 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11416 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11417 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11418 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11419 {"xgot", no_argument, NULL, OPTION_XGOT},
11420 {"mabi", required_argument, NULL, OPTION_MABI},
11421 {"n32", no_argument, NULL, OPTION_N32},
11422 {"64", no_argument, NULL, OPTION_64},
11423 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11424 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11425 {"mpdr", no_argument, NULL, OPTION_PDR},
11426 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11427 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11428 #endif /* OBJ_ELF */
11430 {NULL, no_argument, NULL, 0}
11432 size_t md_longopts_size = sizeof (md_longopts);
11434 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11435 NEW_VALUE. Warn if another value was already specified. Note:
11436 we have to defer parsing the -march and -mtune arguments in order
11437 to handle 'from-abi' correctly, since the ABI might be specified
11438 in a later argument. */
11441 mips_set_option_string (const char **string_ptr, const char *new_value)
11443 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11444 as_warn (_("A different %s was already specified, is now %s"),
11445 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11448 *string_ptr = new_value;
11452 md_parse_option (int c, char *arg)
11456 case OPTION_CONSTRUCT_FLOATS:
11457 mips_disable_float_construction = 0;
11460 case OPTION_NO_CONSTRUCT_FLOATS:
11461 mips_disable_float_construction = 1;
11473 target_big_endian = 1;
11477 target_big_endian = 0;
11483 else if (arg[0] == '0')
11485 else if (arg[0] == '1')
11495 mips_debug = atoi (arg);
11499 file_mips_isa = ISA_MIPS1;
11503 file_mips_isa = ISA_MIPS2;
11507 file_mips_isa = ISA_MIPS3;
11511 file_mips_isa = ISA_MIPS4;
11515 file_mips_isa = ISA_MIPS5;
11518 case OPTION_MIPS32:
11519 file_mips_isa = ISA_MIPS32;
11522 case OPTION_MIPS32R2:
11523 file_mips_isa = ISA_MIPS32R2;
11526 case OPTION_MIPS64R2:
11527 file_mips_isa = ISA_MIPS64R2;
11530 case OPTION_MIPS64:
11531 file_mips_isa = ISA_MIPS64;
11535 mips_set_option_string (&mips_tune_string, arg);
11539 mips_set_option_string (&mips_arch_string, arg);
11543 mips_set_option_string (&mips_arch_string, "4650");
11544 mips_set_option_string (&mips_tune_string, "4650");
11547 case OPTION_NO_M4650:
11551 mips_set_option_string (&mips_arch_string, "4010");
11552 mips_set_option_string (&mips_tune_string, "4010");
11555 case OPTION_NO_M4010:
11559 mips_set_option_string (&mips_arch_string, "4100");
11560 mips_set_option_string (&mips_tune_string, "4100");
11563 case OPTION_NO_M4100:
11567 mips_set_option_string (&mips_arch_string, "3900");
11568 mips_set_option_string (&mips_tune_string, "3900");
11571 case OPTION_NO_M3900:
11575 mips_opts.ase_mdmx = 1;
11578 case OPTION_NO_MDMX:
11579 mips_opts.ase_mdmx = 0;
11583 mips_opts.ase_dsp = 1;
11584 mips_opts.ase_dspr2 = 0;
11587 case OPTION_NO_DSP:
11588 mips_opts.ase_dsp = 0;
11589 mips_opts.ase_dspr2 = 0;
11593 mips_opts.ase_dspr2 = 1;
11594 mips_opts.ase_dsp = 1;
11597 case OPTION_NO_DSPR2:
11598 mips_opts.ase_dspr2 = 0;
11599 mips_opts.ase_dsp = 0;
11603 mips_opts.ase_mt = 1;
11607 mips_opts.ase_mt = 0;
11610 case OPTION_MIPS16:
11611 mips_opts.mips16 = 1;
11612 mips_no_prev_insn ();
11615 case OPTION_NO_MIPS16:
11616 mips_opts.mips16 = 0;
11617 mips_no_prev_insn ();
11620 case OPTION_MIPS3D:
11621 mips_opts.ase_mips3d = 1;
11624 case OPTION_NO_MIPS3D:
11625 mips_opts.ase_mips3d = 0;
11628 case OPTION_SMARTMIPS:
11629 mips_opts.ase_smartmips = 1;
11632 case OPTION_NO_SMARTMIPS:
11633 mips_opts.ase_smartmips = 0;
11636 case OPTION_FIX_24K:
11640 case OPTION_NO_FIX_24K:
11644 case OPTION_FIX_VR4120:
11645 mips_fix_vr4120 = 1;
11648 case OPTION_NO_FIX_VR4120:
11649 mips_fix_vr4120 = 0;
11652 case OPTION_FIX_VR4130:
11653 mips_fix_vr4130 = 1;
11656 case OPTION_NO_FIX_VR4130:
11657 mips_fix_vr4130 = 0;
11660 case OPTION_RELAX_BRANCH:
11661 mips_relax_branch = 1;
11664 case OPTION_NO_RELAX_BRANCH:
11665 mips_relax_branch = 0;
11668 case OPTION_MSHARED:
11669 mips_in_shared = TRUE;
11672 case OPTION_MNO_SHARED:
11673 mips_in_shared = FALSE;
11676 case OPTION_MSYM32:
11677 mips_opts.sym32 = TRUE;
11680 case OPTION_MNO_SYM32:
11681 mips_opts.sym32 = FALSE;
11685 /* When generating ELF code, we permit -KPIC and -call_shared to
11686 select SVR4_PIC, and -non_shared to select no PIC. This is
11687 intended to be compatible with Irix 5. */
11688 case OPTION_CALL_SHARED:
11691 as_bad (_("-call_shared is supported only for ELF format"));
11694 mips_pic = SVR4_PIC;
11695 mips_abicalls = TRUE;
11698 case OPTION_CALL_NONPIC:
11701 as_bad (_("-call_nonpic is supported only for ELF format"));
11705 mips_abicalls = TRUE;
11708 case OPTION_NON_SHARED:
11711 as_bad (_("-non_shared is supported only for ELF format"));
11715 mips_abicalls = FALSE;
11718 /* The -xgot option tells the assembler to use 32 bit offsets
11719 when accessing the got in SVR4_PIC mode. It is for Irix
11724 #endif /* OBJ_ELF */
11727 g_switch_value = atoi (arg);
11731 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11735 mips_abi = O32_ABI;
11736 /* We silently ignore -32 for non-ELF targets. This greatly
11737 simplifies the construction of the MIPS GAS test cases. */
11744 as_bad (_("-n32 is supported for ELF format only"));
11747 mips_abi = N32_ABI;
11753 as_bad (_("-64 is supported for ELF format only"));
11756 mips_abi = N64_ABI;
11757 if (!support_64bit_objects())
11758 as_fatal (_("No compiled in support for 64 bit object file format"));
11760 #endif /* OBJ_ELF */
11763 file_mips_gp32 = 1;
11767 file_mips_gp32 = 0;
11771 file_mips_fp32 = 1;
11775 file_mips_fp32 = 0;
11778 case OPTION_SINGLE_FLOAT:
11779 file_mips_single_float = 1;
11782 case OPTION_DOUBLE_FLOAT:
11783 file_mips_single_float = 0;
11786 case OPTION_SOFT_FLOAT:
11787 file_mips_soft_float = 1;
11790 case OPTION_HARD_FLOAT:
11791 file_mips_soft_float = 0;
11798 as_bad (_("-mabi is supported for ELF format only"));
11801 if (strcmp (arg, "32") == 0)
11802 mips_abi = O32_ABI;
11803 else if (strcmp (arg, "o64") == 0)
11804 mips_abi = O64_ABI;
11805 else if (strcmp (arg, "n32") == 0)
11806 mips_abi = N32_ABI;
11807 else if (strcmp (arg, "64") == 0)
11809 mips_abi = N64_ABI;
11810 if (! support_64bit_objects())
11811 as_fatal (_("No compiled in support for 64 bit object file "
11814 else if (strcmp (arg, "eabi") == 0)
11815 mips_abi = EABI_ABI;
11818 as_fatal (_("invalid abi -mabi=%s"), arg);
11822 #endif /* OBJ_ELF */
11824 case OPTION_M7000_HILO_FIX:
11825 mips_7000_hilo_fix = TRUE;
11828 case OPTION_MNO_7000_HILO_FIX:
11829 mips_7000_hilo_fix = FALSE;
11833 case OPTION_MDEBUG:
11834 mips_flag_mdebug = TRUE;
11837 case OPTION_NO_MDEBUG:
11838 mips_flag_mdebug = FALSE;
11842 mips_flag_pdr = TRUE;
11845 case OPTION_NO_PDR:
11846 mips_flag_pdr = FALSE;
11849 case OPTION_MVXWORKS_PIC:
11850 mips_pic = VXWORKS_PIC;
11852 #endif /* OBJ_ELF */
11861 /* Set up globals to generate code for the ISA or processor
11862 described by INFO. */
11865 mips_set_architecture (const struct mips_cpu_info *info)
11869 file_mips_arch = info->cpu;
11870 mips_opts.arch = info->cpu;
11871 mips_opts.isa = info->isa;
11876 /* Likewise for tuning. */
11879 mips_set_tune (const struct mips_cpu_info *info)
11882 mips_tune = info->cpu;
11887 mips_after_parse_args (void)
11889 const struct mips_cpu_info *arch_info = 0;
11890 const struct mips_cpu_info *tune_info = 0;
11892 /* GP relative stuff not working for PE */
11893 if (strncmp (TARGET_OS, "pe", 2) == 0)
11895 if (g_switch_seen && g_switch_value != 0)
11896 as_bad (_("-G not supported in this configuration."));
11897 g_switch_value = 0;
11900 if (mips_abi == NO_ABI)
11901 mips_abi = MIPS_DEFAULT_ABI;
11903 /* The following code determines the architecture and register size.
11904 Similar code was added to GCC 3.3 (see override_options() in
11905 config/mips/mips.c). The GAS and GCC code should be kept in sync
11906 as much as possible. */
11908 if (mips_arch_string != 0)
11909 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11911 if (file_mips_isa != ISA_UNKNOWN)
11913 /* Handle -mipsN. At this point, file_mips_isa contains the
11914 ISA level specified by -mipsN, while arch_info->isa contains
11915 the -march selection (if any). */
11916 if (arch_info != 0)
11918 /* -march takes precedence over -mipsN, since it is more descriptive.
11919 There's no harm in specifying both as long as the ISA levels
11921 if (file_mips_isa != arch_info->isa)
11922 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11923 mips_cpu_info_from_isa (file_mips_isa)->name,
11924 mips_cpu_info_from_isa (arch_info->isa)->name);
11927 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11930 if (arch_info == 0)
11931 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11933 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11934 as_bad ("-march=%s is not compatible with the selected ABI",
11937 mips_set_architecture (arch_info);
11939 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11940 if (mips_tune_string != 0)
11941 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11943 if (tune_info == 0)
11944 mips_set_tune (arch_info);
11946 mips_set_tune (tune_info);
11948 if (file_mips_gp32 >= 0)
11950 /* The user specified the size of the integer registers. Make sure
11951 it agrees with the ABI and ISA. */
11952 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11953 as_bad (_("-mgp64 used with a 32-bit processor"));
11954 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11955 as_bad (_("-mgp32 used with a 64-bit ABI"));
11956 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11957 as_bad (_("-mgp64 used with a 32-bit ABI"));
11961 /* Infer the integer register size from the ABI and processor.
11962 Restrict ourselves to 32-bit registers if that's all the
11963 processor has, or if the ABI cannot handle 64-bit registers. */
11964 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11965 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11968 switch (file_mips_fp32)
11972 /* No user specified float register size.
11973 ??? GAS treats single-float processors as though they had 64-bit
11974 float registers (although it complains when double-precision
11975 instructions are used). As things stand, saying they have 32-bit
11976 registers would lead to spurious "register must be even" messages.
11977 So here we assume float registers are never smaller than the
11979 if (file_mips_gp32 == 0)
11980 /* 64-bit integer registers implies 64-bit float registers. */
11981 file_mips_fp32 = 0;
11982 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11983 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11984 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11985 file_mips_fp32 = 0;
11987 /* 32-bit float registers. */
11988 file_mips_fp32 = 1;
11991 /* The user specified the size of the float registers. Check if it
11992 agrees with the ABI and ISA. */
11994 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
11995 as_bad (_("-mfp64 used with a 32-bit fpu"));
11996 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
11997 && !ISA_HAS_MXHC1 (mips_opts.isa))
11998 as_warn (_("-mfp64 used with a 32-bit ABI"));
12001 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12002 as_warn (_("-mfp32 used with a 64-bit ABI"));
12006 /* End of GCC-shared inference code. */
12008 /* This flag is set when we have a 64-bit capable CPU but use only
12009 32-bit wide registers. Note that EABI does not use it. */
12010 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12011 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12012 || mips_abi == O32_ABI))
12013 mips_32bitmode = 1;
12015 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12016 as_bad (_("trap exception not supported at ISA 1"));
12018 /* If the selected architecture includes support for ASEs, enable
12019 generation of code for them. */
12020 if (mips_opts.mips16 == -1)
12021 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12022 if (mips_opts.ase_mips3d == -1)
12023 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12024 && file_mips_fp32 == 0) ? 1 : 0;
12025 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12026 as_bad (_("-mfp32 used with -mips3d"));
12028 if (mips_opts.ase_mdmx == -1)
12029 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12030 && file_mips_fp32 == 0) ? 1 : 0;
12031 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12032 as_bad (_("-mfp32 used with -mdmx"));
12034 if (mips_opts.ase_smartmips == -1)
12035 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12036 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12037 as_warn ("%s ISA does not support SmartMIPS",
12038 mips_cpu_info_from_isa (mips_opts.isa)->name);
12040 if (mips_opts.ase_dsp == -1)
12041 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12042 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12043 as_warn ("%s ISA does not support DSP ASE",
12044 mips_cpu_info_from_isa (mips_opts.isa)->name);
12046 if (mips_opts.ase_dspr2 == -1)
12048 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12049 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12051 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12052 as_warn ("%s ISA does not support DSP R2 ASE",
12053 mips_cpu_info_from_isa (mips_opts.isa)->name);
12055 if (mips_opts.ase_mt == -1)
12056 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12057 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12058 as_warn ("%s ISA does not support MT ASE",
12059 mips_cpu_info_from_isa (mips_opts.isa)->name);
12061 file_mips_isa = mips_opts.isa;
12062 file_ase_mips16 = mips_opts.mips16;
12063 file_ase_mips3d = mips_opts.ase_mips3d;
12064 file_ase_mdmx = mips_opts.ase_mdmx;
12065 file_ase_smartmips = mips_opts.ase_smartmips;
12066 file_ase_dsp = mips_opts.ase_dsp;
12067 file_ase_dspr2 = mips_opts.ase_dspr2;
12068 file_ase_mt = mips_opts.ase_mt;
12069 mips_opts.gp32 = file_mips_gp32;
12070 mips_opts.fp32 = file_mips_fp32;
12071 mips_opts.soft_float = file_mips_soft_float;
12072 mips_opts.single_float = file_mips_single_float;
12074 if (mips_flag_mdebug < 0)
12076 #ifdef OBJ_MAYBE_ECOFF
12077 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12078 mips_flag_mdebug = 1;
12080 #endif /* OBJ_MAYBE_ECOFF */
12081 mips_flag_mdebug = 0;
12086 mips_init_after_args (void)
12088 /* initialize opcodes */
12089 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12090 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12094 md_pcrel_from (fixS *fixP)
12096 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12097 switch (fixP->fx_r_type)
12099 case BFD_RELOC_16_PCREL_S2:
12100 case BFD_RELOC_MIPS_JMP:
12101 /* Return the address of the delay slot. */
12104 /* We have no relocation type for PC relative MIPS16 instructions. */
12105 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12106 as_bad_where (fixP->fx_file, fixP->fx_line,
12107 _("PC relative MIPS16 instruction references a different section"));
12112 /* This is called before the symbol table is processed. In order to
12113 work with gcc when using mips-tfile, we must keep all local labels.
12114 However, in other cases, we want to discard them. If we were
12115 called with -g, but we didn't see any debugging information, it may
12116 mean that gcc is smuggling debugging information through to
12117 mips-tfile, in which case we must generate all local labels. */
12120 mips_frob_file_before_adjust (void)
12122 #ifndef NO_ECOFF_DEBUGGING
12123 if (ECOFF_DEBUGGING
12125 && ! ecoff_debugging_seen)
12126 flag_keep_locals = 1;
12130 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12131 the corresponding LO16 reloc. This is called before md_apply_fix and
12132 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12133 relocation operators.
12135 For our purposes, a %lo() expression matches a %got() or %hi()
12138 (a) it refers to the same symbol; and
12139 (b) the offset applied in the %lo() expression is no lower than
12140 the offset applied in the %got() or %hi().
12142 (b) allows us to cope with code like:
12145 lh $4,%lo(foo+2)($4)
12147 ...which is legal on RELA targets, and has a well-defined behaviour
12148 if the user knows that adding 2 to "foo" will not induce a carry to
12151 When several %lo()s match a particular %got() or %hi(), we use the
12152 following rules to distinguish them:
12154 (1) %lo()s with smaller offsets are a better match than %lo()s with
12157 (2) %lo()s with no matching %got() or %hi() are better than those
12158 that already have a matching %got() or %hi().
12160 (3) later %lo()s are better than earlier %lo()s.
12162 These rules are applied in order.
12164 (1) means, among other things, that %lo()s with identical offsets are
12165 chosen if they exist.
12167 (2) means that we won't associate several high-part relocations with
12168 the same low-part relocation unless there's no alternative. Having
12169 several high parts for the same low part is a GNU extension; this rule
12170 allows careful users to avoid it.
12172 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12173 with the last high-part relocation being at the front of the list.
12174 It therefore makes sense to choose the last matching low-part
12175 relocation, all other things being equal. It's also easier
12176 to code that way. */
12179 mips_frob_file (void)
12181 struct mips_hi_fixup *l;
12182 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12184 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12186 segment_info_type *seginfo;
12187 bfd_boolean matched_lo_p;
12188 fixS **hi_pos, **lo_pos, **pos;
12190 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12192 /* If a GOT16 relocation turns out to be against a global symbol,
12193 there isn't supposed to be a matching LO. */
12194 if (got16_reloc_p (l->fixp->fx_r_type)
12195 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12198 /* Check quickly whether the next fixup happens to be a matching %lo. */
12199 if (fixup_has_matching_lo_p (l->fixp))
12202 seginfo = seg_info (l->seg);
12204 /* Set HI_POS to the position of this relocation in the chain.
12205 Set LO_POS to the position of the chosen low-part relocation.
12206 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12207 relocation that matches an immediately-preceding high-part
12211 matched_lo_p = FALSE;
12212 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12214 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12216 if (*pos == l->fixp)
12219 if ((*pos)->fx_r_type == looking_for_rtype
12220 && (*pos)->fx_addsy == l->fixp->fx_addsy
12221 && (*pos)->fx_offset >= l->fixp->fx_offset
12223 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12225 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12228 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12229 && fixup_has_matching_lo_p (*pos));
12232 /* If we found a match, remove the high-part relocation from its
12233 current position and insert it before the low-part relocation.
12234 Make the offsets match so that fixup_has_matching_lo_p()
12237 We don't warn about unmatched high-part relocations since some
12238 versions of gcc have been known to emit dead "lui ...%hi(...)"
12240 if (lo_pos != NULL)
12242 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12243 if (l->fixp->fx_next != *lo_pos)
12245 *hi_pos = l->fixp->fx_next;
12246 l->fixp->fx_next = *lo_pos;
12253 /* We may have combined relocations without symbols in the N32/N64 ABI.
12254 We have to prevent gas from dropping them. */
12257 mips_force_relocation (fixS *fixp)
12259 if (generic_force_reloc (fixp))
12263 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12264 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12265 || hi16_reloc_p (fixp->fx_r_type)
12266 || lo16_reloc_p (fixp->fx_r_type)))
12272 /* Apply a fixup to the object file. */
12275 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12279 reloc_howto_type *howto;
12281 /* We ignore generic BFD relocations we don't know about. */
12282 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12286 assert (fixP->fx_size == 4
12287 || fixP->fx_r_type == BFD_RELOC_16
12288 || fixP->fx_r_type == BFD_RELOC_64
12289 || fixP->fx_r_type == BFD_RELOC_CTOR
12290 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12291 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12292 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12293 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12295 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12297 assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12299 /* Don't treat parts of a composite relocation as done. There are two
12302 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12303 should nevertheless be emitted if the first part is.
12305 (2) In normal usage, composite relocations are never assembly-time
12306 constants. The easiest way of dealing with the pathological
12307 exceptions is to generate a relocation against STN_UNDEF and
12308 leave everything up to the linker. */
12309 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12312 switch (fixP->fx_r_type)
12314 case BFD_RELOC_MIPS_TLS_GD:
12315 case BFD_RELOC_MIPS_TLS_LDM:
12316 case BFD_RELOC_MIPS_TLS_DTPREL32:
12317 case BFD_RELOC_MIPS_TLS_DTPREL64:
12318 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12319 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12320 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12321 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12322 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12323 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12326 case BFD_RELOC_MIPS_JMP:
12327 case BFD_RELOC_MIPS_SHIFT5:
12328 case BFD_RELOC_MIPS_SHIFT6:
12329 case BFD_RELOC_MIPS_GOT_DISP:
12330 case BFD_RELOC_MIPS_GOT_PAGE:
12331 case BFD_RELOC_MIPS_GOT_OFST:
12332 case BFD_RELOC_MIPS_SUB:
12333 case BFD_RELOC_MIPS_INSERT_A:
12334 case BFD_RELOC_MIPS_INSERT_B:
12335 case BFD_RELOC_MIPS_DELETE:
12336 case BFD_RELOC_MIPS_HIGHEST:
12337 case BFD_RELOC_MIPS_HIGHER:
12338 case BFD_RELOC_MIPS_SCN_DISP:
12339 case BFD_RELOC_MIPS_REL16:
12340 case BFD_RELOC_MIPS_RELGOT:
12341 case BFD_RELOC_MIPS_JALR:
12342 case BFD_RELOC_HI16:
12343 case BFD_RELOC_HI16_S:
12344 case BFD_RELOC_GPREL16:
12345 case BFD_RELOC_MIPS_LITERAL:
12346 case BFD_RELOC_MIPS_CALL16:
12347 case BFD_RELOC_MIPS_GOT16:
12348 case BFD_RELOC_GPREL32:
12349 case BFD_RELOC_MIPS_GOT_HI16:
12350 case BFD_RELOC_MIPS_GOT_LO16:
12351 case BFD_RELOC_MIPS_CALL_HI16:
12352 case BFD_RELOC_MIPS_CALL_LO16:
12353 case BFD_RELOC_MIPS16_GPREL:
12354 case BFD_RELOC_MIPS16_GOT16:
12355 case BFD_RELOC_MIPS16_CALL16:
12356 case BFD_RELOC_MIPS16_HI16:
12357 case BFD_RELOC_MIPS16_HI16_S:
12358 case BFD_RELOC_MIPS16_JMP:
12359 /* Nothing needed to do. The value comes from the reloc entry. */
12363 /* This is handled like BFD_RELOC_32, but we output a sign
12364 extended value if we are only 32 bits. */
12367 if (8 <= sizeof (valueT))
12368 md_number_to_chars ((char *) buf, *valP, 8);
12373 if ((*valP & 0x80000000) != 0)
12377 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12379 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12385 case BFD_RELOC_RVA:
12388 /* If we are deleting this reloc entry, we must fill in the
12389 value now. This can happen if we have a .word which is not
12390 resolved when it appears but is later defined. */
12392 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12395 case BFD_RELOC_LO16:
12396 case BFD_RELOC_MIPS16_LO16:
12397 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12398 may be safe to remove, but if so it's not obvious. */
12399 /* When handling an embedded PIC switch statement, we can wind
12400 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12403 if (*valP + 0x8000 > 0xffff)
12404 as_bad_where (fixP->fx_file, fixP->fx_line,
12405 _("relocation overflow"));
12406 if (target_big_endian)
12408 md_number_to_chars ((char *) buf, *valP, 2);
12412 case BFD_RELOC_16_PCREL_S2:
12413 if ((*valP & 0x3) != 0)
12414 as_bad_where (fixP->fx_file, fixP->fx_line,
12415 _("Branch to misaligned address (%lx)"), (long) *valP);
12417 /* We need to save the bits in the instruction since fixup_segment()
12418 might be deleting the relocation entry (i.e., a branch within
12419 the current segment). */
12420 if (! fixP->fx_done)
12423 /* Update old instruction data. */
12424 if (target_big_endian)
12425 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12427 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12429 if (*valP + 0x20000 <= 0x3ffff)
12431 insn |= (*valP >> 2) & 0xffff;
12432 md_number_to_chars ((char *) buf, insn, 4);
12434 else if (mips_pic == NO_PIC
12436 && fixP->fx_frag->fr_address >= text_section->vma
12437 && (fixP->fx_frag->fr_address
12438 < text_section->vma + bfd_get_section_size (text_section))
12439 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12440 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12441 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12443 /* The branch offset is too large. If this is an
12444 unconditional branch, and we are not generating PIC code,
12445 we can convert it to an absolute jump instruction. */
12446 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12447 insn = 0x0c000000; /* jal */
12449 insn = 0x08000000; /* j */
12450 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12452 fixP->fx_addsy = section_symbol (text_section);
12453 *valP += md_pcrel_from (fixP);
12454 md_number_to_chars ((char *) buf, insn, 4);
12458 /* If we got here, we have branch-relaxation disabled,
12459 and there's nothing we can do to fix this instruction
12460 without turning it into a longer sequence. */
12461 as_bad_where (fixP->fx_file, fixP->fx_line,
12462 _("Branch out of range"));
12466 case BFD_RELOC_VTABLE_INHERIT:
12469 && !S_IS_DEFINED (fixP->fx_addsy)
12470 && !S_IS_WEAK (fixP->fx_addsy))
12471 S_SET_WEAK (fixP->fx_addsy);
12474 case BFD_RELOC_VTABLE_ENTRY:
12482 /* Remember value for tc_gen_reloc. */
12483 fixP->fx_addnumber = *valP;
12493 name = input_line_pointer;
12494 c = get_symbol_end ();
12495 p = (symbolS *) symbol_find_or_make (name);
12496 *input_line_pointer = c;
12500 /* Align the current frag to a given power of two. If a particular
12501 fill byte should be used, FILL points to an integer that contains
12502 that byte, otherwise FILL is null.
12504 The MIPS assembler also automatically adjusts any preceding
12508 mips_align (int to, int *fill, symbolS *label)
12510 mips_emit_delays ();
12511 mips_record_mips16_mode ();
12512 if (fill == NULL && subseg_text_p (now_seg))
12513 frag_align_code (to, 0);
12515 frag_align (to, fill ? *fill : 0, 0);
12516 record_alignment (now_seg, to);
12519 assert (S_GET_SEGMENT (label) == now_seg);
12520 symbol_set_frag (label, frag_now);
12521 S_SET_VALUE (label, (valueT) frag_now_fix ());
12525 /* Align to a given power of two. .align 0 turns off the automatic
12526 alignment used by the data creating pseudo-ops. */
12529 s_align (int x ATTRIBUTE_UNUSED)
12531 int temp, fill_value, *fill_ptr;
12532 long max_alignment = 28;
12534 /* o Note that the assembler pulls down any immediately preceding label
12535 to the aligned address.
12536 o It's not documented but auto alignment is reinstated by
12537 a .align pseudo instruction.
12538 o Note also that after auto alignment is turned off the mips assembler
12539 issues an error on attempt to assemble an improperly aligned data item.
12542 temp = get_absolute_expression ();
12543 if (temp > max_alignment)
12544 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12547 as_warn (_("Alignment negative: 0 assumed."));
12550 if (*input_line_pointer == ',')
12552 ++input_line_pointer;
12553 fill_value = get_absolute_expression ();
12554 fill_ptr = &fill_value;
12560 segment_info_type *si = seg_info (now_seg);
12561 struct insn_label_list *l = si->label_list;
12562 /* Auto alignment should be switched on by next section change. */
12564 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12571 demand_empty_rest_of_line ();
12575 s_change_sec (int sec)
12580 /* The ELF backend needs to know that we are changing sections, so
12581 that .previous works correctly. We could do something like check
12582 for an obj_section_change_hook macro, but that might be confusing
12583 as it would not be appropriate to use it in the section changing
12584 functions in read.c, since obj-elf.c intercepts those. FIXME:
12585 This should be cleaner, somehow. */
12587 obj_elf_section_change_hook ();
12590 mips_emit_delays ();
12593 check_for_24k_errata ((struct mips_cl_insn *) &history[0], -1);
12604 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12605 demand_empty_rest_of_line ();
12609 seg = subseg_new (RDATA_SECTION_NAME,
12610 (subsegT) get_absolute_expression ());
12613 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12614 | SEC_READONLY | SEC_RELOC
12616 if (strncmp (TARGET_OS, "elf", 3) != 0)
12617 record_alignment (seg, 4);
12619 demand_empty_rest_of_line ();
12623 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12626 bfd_set_section_flags (stdoutput, seg,
12627 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12628 if (strncmp (TARGET_OS, "elf", 3) != 0)
12629 record_alignment (seg, 4);
12631 demand_empty_rest_of_line ();
12639 s_change_section (int ignore ATTRIBUTE_UNUSED)
12642 char *section_name;
12647 int section_entry_size;
12648 int section_alignment;
12654 check_for_24k_errata ((struct mips_cl_insn *) &history[0], -1);
12656 section_name = input_line_pointer;
12657 c = get_symbol_end ();
12659 next_c = *(input_line_pointer + 1);
12661 /* Do we have .section Name<,"flags">? */
12662 if (c != ',' || (c == ',' && next_c == '"'))
12664 /* just after name is now '\0'. */
12665 *input_line_pointer = c;
12666 input_line_pointer = section_name;
12667 obj_elf_section (ignore);
12670 input_line_pointer++;
12672 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12674 section_type = get_absolute_expression ();
12677 if (*input_line_pointer++ == ',')
12678 section_flag = get_absolute_expression ();
12681 if (*input_line_pointer++ == ',')
12682 section_entry_size = get_absolute_expression ();
12684 section_entry_size = 0;
12685 if (*input_line_pointer++ == ',')
12686 section_alignment = get_absolute_expression ();
12688 section_alignment = 0;
12690 section_name = xstrdup (section_name);
12692 /* When using the generic form of .section (as implemented by obj-elf.c),
12693 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12694 traditionally had to fall back on the more common @progbits instead.
12696 There's nothing really harmful in this, since bfd will correct
12697 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12698 means that, for backwards compatibility, the special_section entries
12699 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12701 Even so, we shouldn't force users of the MIPS .section syntax to
12702 incorrectly label the sections as SHT_PROGBITS. The best compromise
12703 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12704 generic type-checking code. */
12705 if (section_type == SHT_MIPS_DWARF)
12706 section_type = SHT_PROGBITS;
12708 obj_elf_change_section (section_name, section_type, section_flag,
12709 section_entry_size, 0, 0, 0);
12711 if (now_seg->name != section_name)
12712 free (section_name);
12713 #endif /* OBJ_ELF */
12717 mips_enable_auto_align (void)
12723 s_cons (int log_size)
12725 segment_info_type *si = seg_info (now_seg);
12726 struct insn_label_list *l = si->label_list;
12729 label = l != NULL ? l->label : NULL;
12730 mips_emit_delays ();
12731 if (log_size > 0 && auto_align)
12732 mips_align (log_size, 0, label);
12733 mips_clear_insn_labels ();
12734 cons (1 << log_size);
12738 s_float_cons (int type)
12740 segment_info_type *si = seg_info (now_seg);
12741 struct insn_label_list *l = si->label_list;
12744 label = l != NULL ? l->label : NULL;
12746 mips_emit_delays ();
12751 mips_align (3, 0, label);
12753 mips_align (2, 0, label);
12756 mips_clear_insn_labels ();
12761 /* Handle .globl. We need to override it because on Irix 5 you are
12764 where foo is an undefined symbol, to mean that foo should be
12765 considered to be the address of a function. */
12768 s_mips_globl (int x ATTRIBUTE_UNUSED)
12777 name = input_line_pointer;
12778 c = get_symbol_end ();
12779 symbolP = symbol_find_or_make (name);
12780 S_SET_EXTERNAL (symbolP);
12782 *input_line_pointer = c;
12783 SKIP_WHITESPACE ();
12785 /* On Irix 5, every global symbol that is not explicitly labelled as
12786 being a function is apparently labelled as being an object. */
12789 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12790 && (*input_line_pointer != ','))
12795 secname = input_line_pointer;
12796 c = get_symbol_end ();
12797 sec = bfd_get_section_by_name (stdoutput, secname);
12799 as_bad (_("%s: no such section"), secname);
12800 *input_line_pointer = c;
12802 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12803 flag = BSF_FUNCTION;
12806 symbol_get_bfdsym (symbolP)->flags |= flag;
12808 c = *input_line_pointer;
12811 input_line_pointer++;
12812 SKIP_WHITESPACE ();
12813 if (is_end_of_line[(unsigned char) *input_line_pointer])
12819 demand_empty_rest_of_line ();
12823 s_option (int x ATTRIBUTE_UNUSED)
12828 opt = input_line_pointer;
12829 c = get_symbol_end ();
12833 /* FIXME: What does this mean? */
12835 else if (strncmp (opt, "pic", 3) == 0)
12839 i = atoi (opt + 3);
12844 mips_pic = SVR4_PIC;
12845 mips_abicalls = TRUE;
12848 as_bad (_(".option pic%d not supported"), i);
12850 if (mips_pic == SVR4_PIC)
12852 if (g_switch_seen && g_switch_value != 0)
12853 as_warn (_("-G may not be used with SVR4 PIC code"));
12854 g_switch_value = 0;
12855 bfd_set_gp_size (stdoutput, 0);
12859 as_warn (_("Unrecognized option \"%s\""), opt);
12861 *input_line_pointer = c;
12862 demand_empty_rest_of_line ();
12865 /* This structure is used to hold a stack of .set values. */
12867 struct mips_option_stack
12869 struct mips_option_stack *next;
12870 struct mips_set_options options;
12873 static struct mips_option_stack *mips_opts_stack;
12875 /* Handle the .set pseudo-op. */
12878 s_mipsset (int x ATTRIBUTE_UNUSED)
12880 char *name = input_line_pointer, ch;
12882 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12883 ++input_line_pointer;
12884 ch = *input_line_pointer;
12885 *input_line_pointer = '\0';
12887 if (strcmp (name, "reorder") == 0)
12889 if (mips_opts.noreorder)
12892 else if (strcmp (name, "noreorder") == 0)
12894 if (!mips_opts.noreorder)
12895 start_noreorder ();
12897 else if (strncmp (name, "at=", 3) == 0)
12899 char *s = name + 3;
12901 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
12902 as_bad (_("Unrecognized register name `%s'"), s);
12904 else if (strcmp (name, "at") == 0)
12906 mips_opts.at = ATREG;
12908 else if (strcmp (name, "noat") == 0)
12910 mips_opts.at = ZERO;
12912 else if (strcmp (name, "macro") == 0)
12914 mips_opts.warn_about_macros = 0;
12916 else if (strcmp (name, "nomacro") == 0)
12918 if (mips_opts.noreorder == 0)
12919 as_bad (_("`noreorder' must be set before `nomacro'"));
12920 mips_opts.warn_about_macros = 1;
12922 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12924 mips_opts.nomove = 0;
12926 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12928 mips_opts.nomove = 1;
12930 else if (strcmp (name, "bopt") == 0)
12932 mips_opts.nobopt = 0;
12934 else if (strcmp (name, "nobopt") == 0)
12936 mips_opts.nobopt = 1;
12938 else if (strcmp (name, "gp=default") == 0)
12939 mips_opts.gp32 = file_mips_gp32;
12940 else if (strcmp (name, "gp=32") == 0)
12941 mips_opts.gp32 = 1;
12942 else if (strcmp (name, "gp=64") == 0)
12944 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12945 as_warn ("%s isa does not support 64-bit registers",
12946 mips_cpu_info_from_isa (mips_opts.isa)->name);
12947 mips_opts.gp32 = 0;
12949 else if (strcmp (name, "fp=default") == 0)
12950 mips_opts.fp32 = file_mips_fp32;
12951 else if (strcmp (name, "fp=32") == 0)
12952 mips_opts.fp32 = 1;
12953 else if (strcmp (name, "fp=64") == 0)
12955 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12956 as_warn ("%s isa does not support 64-bit floating point registers",
12957 mips_cpu_info_from_isa (mips_opts.isa)->name);
12958 mips_opts.fp32 = 0;
12960 else if (strcmp (name, "softfloat") == 0)
12961 mips_opts.soft_float = 1;
12962 else if (strcmp (name, "hardfloat") == 0)
12963 mips_opts.soft_float = 0;
12964 else if (strcmp (name, "singlefloat") == 0)
12965 mips_opts.single_float = 1;
12966 else if (strcmp (name, "doublefloat") == 0)
12967 mips_opts.single_float = 0;
12968 else if (strcmp (name, "mips16") == 0
12969 || strcmp (name, "MIPS-16") == 0)
12970 mips_opts.mips16 = 1;
12971 else if (strcmp (name, "nomips16") == 0
12972 || strcmp (name, "noMIPS-16") == 0)
12973 mips_opts.mips16 = 0;
12974 else if (strcmp (name, "smartmips") == 0)
12976 if (!ISA_SUPPORTS_SMARTMIPS)
12977 as_warn ("%s ISA does not support SmartMIPS ASE",
12978 mips_cpu_info_from_isa (mips_opts.isa)->name);
12979 mips_opts.ase_smartmips = 1;
12981 else if (strcmp (name, "nosmartmips") == 0)
12982 mips_opts.ase_smartmips = 0;
12983 else if (strcmp (name, "mips3d") == 0)
12984 mips_opts.ase_mips3d = 1;
12985 else if (strcmp (name, "nomips3d") == 0)
12986 mips_opts.ase_mips3d = 0;
12987 else if (strcmp (name, "mdmx") == 0)
12988 mips_opts.ase_mdmx = 1;
12989 else if (strcmp (name, "nomdmx") == 0)
12990 mips_opts.ase_mdmx = 0;
12991 else if (strcmp (name, "dsp") == 0)
12993 if (!ISA_SUPPORTS_DSP_ASE)
12994 as_warn ("%s ISA does not support DSP ASE",
12995 mips_cpu_info_from_isa (mips_opts.isa)->name);
12996 mips_opts.ase_dsp = 1;
12997 mips_opts.ase_dspr2 = 0;
12999 else if (strcmp (name, "nodsp") == 0)
13001 mips_opts.ase_dsp = 0;
13002 mips_opts.ase_dspr2 = 0;
13004 else if (strcmp (name, "dspr2") == 0)
13006 if (!ISA_SUPPORTS_DSPR2_ASE)
13007 as_warn ("%s ISA does not support DSP R2 ASE",
13008 mips_cpu_info_from_isa (mips_opts.isa)->name);
13009 mips_opts.ase_dspr2 = 1;
13010 mips_opts.ase_dsp = 1;
13012 else if (strcmp (name, "nodspr2") == 0)
13014 mips_opts.ase_dspr2 = 0;
13015 mips_opts.ase_dsp = 0;
13017 else if (strcmp (name, "mt") == 0)
13019 if (!ISA_SUPPORTS_MT_ASE)
13020 as_warn ("%s ISA does not support MT ASE",
13021 mips_cpu_info_from_isa (mips_opts.isa)->name);
13022 mips_opts.ase_mt = 1;
13024 else if (strcmp (name, "nomt") == 0)
13025 mips_opts.ase_mt = 0;
13026 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13030 /* Permit the user to change the ISA and architecture on the fly.
13031 Needless to say, misuse can cause serious problems. */
13032 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13035 mips_opts.isa = file_mips_isa;
13036 mips_opts.arch = file_mips_arch;
13038 else if (strncmp (name, "arch=", 5) == 0)
13040 const struct mips_cpu_info *p;
13042 p = mips_parse_cpu("internal use", name + 5);
13044 as_bad (_("unknown architecture %s"), name + 5);
13047 mips_opts.arch = p->cpu;
13048 mips_opts.isa = p->isa;
13051 else if (strncmp (name, "mips", 4) == 0)
13053 const struct mips_cpu_info *p;
13055 p = mips_parse_cpu("internal use", name);
13057 as_bad (_("unknown ISA level %s"), name + 4);
13060 mips_opts.arch = p->cpu;
13061 mips_opts.isa = p->isa;
13065 as_bad (_("unknown ISA or architecture %s"), name);
13067 switch (mips_opts.isa)
13075 mips_opts.gp32 = 1;
13076 mips_opts.fp32 = 1;
13083 mips_opts.gp32 = 0;
13084 mips_opts.fp32 = 0;
13087 as_bad (_("unknown ISA level %s"), name + 4);
13092 mips_opts.gp32 = file_mips_gp32;
13093 mips_opts.fp32 = file_mips_fp32;
13096 else if (strcmp (name, "autoextend") == 0)
13097 mips_opts.noautoextend = 0;
13098 else if (strcmp (name, "noautoextend") == 0)
13099 mips_opts.noautoextend = 1;
13100 else if (strcmp (name, "push") == 0)
13102 struct mips_option_stack *s;
13104 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13105 s->next = mips_opts_stack;
13106 s->options = mips_opts;
13107 mips_opts_stack = s;
13109 else if (strcmp (name, "pop") == 0)
13111 struct mips_option_stack *s;
13113 s = mips_opts_stack;
13115 as_bad (_(".set pop with no .set push"));
13118 /* If we're changing the reorder mode we need to handle
13119 delay slots correctly. */
13120 if (s->options.noreorder && ! mips_opts.noreorder)
13121 start_noreorder ();
13122 else if (! s->options.noreorder && mips_opts.noreorder)
13125 mips_opts = s->options;
13126 mips_opts_stack = s->next;
13130 else if (strcmp (name, "sym32") == 0)
13131 mips_opts.sym32 = TRUE;
13132 else if (strcmp (name, "nosym32") == 0)
13133 mips_opts.sym32 = FALSE;
13134 else if (strchr (name, ','))
13136 /* Generic ".set" directive; use the generic handler. */
13137 *input_line_pointer = ch;
13138 input_line_pointer = name;
13144 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13146 *input_line_pointer = ch;
13147 demand_empty_rest_of_line ();
13150 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13151 .option pic2. It means to generate SVR4 PIC calls. */
13154 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13156 mips_pic = SVR4_PIC;
13157 mips_abicalls = TRUE;
13159 if (g_switch_seen && g_switch_value != 0)
13160 as_warn (_("-G may not be used with SVR4 PIC code"));
13161 g_switch_value = 0;
13163 bfd_set_gp_size (stdoutput, 0);
13164 demand_empty_rest_of_line ();
13167 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13168 PIC code. It sets the $gp register for the function based on the
13169 function address, which is in the register named in the argument.
13170 This uses a relocation against _gp_disp, which is handled specially
13171 by the linker. The result is:
13172 lui $gp,%hi(_gp_disp)
13173 addiu $gp,$gp,%lo(_gp_disp)
13174 addu $gp,$gp,.cpload argument
13175 The .cpload argument is normally $25 == $t9.
13177 The -mno-shared option changes this to:
13178 lui $gp,%hi(__gnu_local_gp)
13179 addiu $gp,$gp,%lo(__gnu_local_gp)
13180 and the argument is ignored. This saves an instruction, but the
13181 resulting code is not position independent; it uses an absolute
13182 address for __gnu_local_gp. Thus code assembled with -mno-shared
13183 can go into an ordinary executable, but not into a shared library. */
13186 s_cpload (int ignore ATTRIBUTE_UNUSED)
13192 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13193 .cpload is ignored. */
13194 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13200 /* .cpload should be in a .set noreorder section. */
13201 if (mips_opts.noreorder == 0)
13202 as_warn (_(".cpload not in noreorder section"));
13204 reg = tc_get_register (0);
13206 /* If we need to produce a 64-bit address, we are better off using
13207 the default instruction sequence. */
13208 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13210 ex.X_op = O_symbol;
13211 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13213 ex.X_op_symbol = NULL;
13214 ex.X_add_number = 0;
13216 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13217 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13220 macro_build_lui (&ex, mips_gp_register);
13221 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13222 mips_gp_register, BFD_RELOC_LO16);
13224 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13225 mips_gp_register, reg);
13228 demand_empty_rest_of_line ();
13231 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13232 .cpsetup $reg1, offset|$reg2, label
13234 If offset is given, this results in:
13235 sd $gp, offset($sp)
13236 lui $gp, %hi(%neg(%gp_rel(label)))
13237 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13238 daddu $gp, $gp, $reg1
13240 If $reg2 is given, this results in:
13241 daddu $reg2, $gp, $0
13242 lui $gp, %hi(%neg(%gp_rel(label)))
13243 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13244 daddu $gp, $gp, $reg1
13245 $reg1 is normally $25 == $t9.
13247 The -mno-shared option replaces the last three instructions with
13249 addiu $gp,$gp,%lo(_gp) */
13252 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13254 expressionS ex_off;
13255 expressionS ex_sym;
13258 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13259 We also need NewABI support. */
13260 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13266 reg1 = tc_get_register (0);
13267 SKIP_WHITESPACE ();
13268 if (*input_line_pointer != ',')
13270 as_bad (_("missing argument separator ',' for .cpsetup"));
13274 ++input_line_pointer;
13275 SKIP_WHITESPACE ();
13276 if (*input_line_pointer == '$')
13278 mips_cpreturn_register = tc_get_register (0);
13279 mips_cpreturn_offset = -1;
13283 mips_cpreturn_offset = get_absolute_expression ();
13284 mips_cpreturn_register = -1;
13286 SKIP_WHITESPACE ();
13287 if (*input_line_pointer != ',')
13289 as_bad (_("missing argument separator ',' for .cpsetup"));
13293 ++input_line_pointer;
13294 SKIP_WHITESPACE ();
13295 expression (&ex_sym);
13298 if (mips_cpreturn_register == -1)
13300 ex_off.X_op = O_constant;
13301 ex_off.X_add_symbol = NULL;
13302 ex_off.X_op_symbol = NULL;
13303 ex_off.X_add_number = mips_cpreturn_offset;
13305 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13306 BFD_RELOC_LO16, SP);
13309 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13310 mips_gp_register, 0);
13312 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13314 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13315 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13318 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13319 mips_gp_register, -1, BFD_RELOC_GPREL16,
13320 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13322 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13323 mips_gp_register, reg1);
13329 ex.X_op = O_symbol;
13330 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13331 ex.X_op_symbol = NULL;
13332 ex.X_add_number = 0;
13334 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13335 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13337 macro_build_lui (&ex, mips_gp_register);
13338 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13339 mips_gp_register, BFD_RELOC_LO16);
13344 demand_empty_rest_of_line ();
13348 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13350 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13351 .cplocal is ignored. */
13352 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13358 mips_gp_register = tc_get_register (0);
13359 demand_empty_rest_of_line ();
13362 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13363 offset from $sp. The offset is remembered, and after making a PIC
13364 call $gp is restored from that location. */
13367 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13371 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13372 .cprestore is ignored. */
13373 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13379 mips_cprestore_offset = get_absolute_expression ();
13380 mips_cprestore_valid = 1;
13382 ex.X_op = O_constant;
13383 ex.X_add_symbol = NULL;
13384 ex.X_op_symbol = NULL;
13385 ex.X_add_number = mips_cprestore_offset;
13388 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13389 SP, HAVE_64BIT_ADDRESSES);
13392 demand_empty_rest_of_line ();
13395 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13396 was given in the preceding .cpsetup, it results in:
13397 ld $gp, offset($sp)
13399 If a register $reg2 was given there, it results in:
13400 daddu $gp, $reg2, $0 */
13403 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13407 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13408 We also need NewABI support. */
13409 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13416 if (mips_cpreturn_register == -1)
13418 ex.X_op = O_constant;
13419 ex.X_add_symbol = NULL;
13420 ex.X_op_symbol = NULL;
13421 ex.X_add_number = mips_cpreturn_offset;
13423 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13426 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13427 mips_cpreturn_register, 0);
13430 demand_empty_rest_of_line ();
13433 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13434 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13435 use in DWARF debug information. */
13438 s_dtprel_internal (size_t bytes)
13445 if (ex.X_op != O_symbol)
13447 as_bad (_("Unsupported use of %s"), (bytes == 8
13450 ignore_rest_of_line ();
13453 p = frag_more (bytes);
13454 md_number_to_chars (p, 0, bytes);
13455 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13457 ? BFD_RELOC_MIPS_TLS_DTPREL64
13458 : BFD_RELOC_MIPS_TLS_DTPREL32));
13460 demand_empty_rest_of_line ();
13463 /* Handle .dtprelword. */
13466 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13468 s_dtprel_internal (4);
13471 /* Handle .dtpreldword. */
13474 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13476 s_dtprel_internal (8);
13479 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13480 code. It sets the offset to use in gp_rel relocations. */
13483 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13485 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13486 We also need NewABI support. */
13487 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13493 mips_gprel_offset = get_absolute_expression ();
13495 demand_empty_rest_of_line ();
13498 /* Handle the .gpword pseudo-op. This is used when generating PIC
13499 code. It generates a 32 bit GP relative reloc. */
13502 s_gpword (int ignore ATTRIBUTE_UNUSED)
13504 segment_info_type *si;
13505 struct insn_label_list *l;
13510 /* When not generating PIC code, this is treated as .word. */
13511 if (mips_pic != SVR4_PIC)
13517 si = seg_info (now_seg);
13518 l = si->label_list;
13519 label = l != NULL ? l->label : NULL;
13520 mips_emit_delays ();
13522 mips_align (2, 0, label);
13523 mips_clear_insn_labels ();
13527 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13529 as_bad (_("Unsupported use of .gpword"));
13530 ignore_rest_of_line ();
13534 md_number_to_chars (p, 0, 4);
13535 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13536 BFD_RELOC_GPREL32);
13538 demand_empty_rest_of_line ();
13542 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13544 segment_info_type *si;
13545 struct insn_label_list *l;
13550 /* When not generating PIC code, this is treated as .dword. */
13551 if (mips_pic != SVR4_PIC)
13557 si = seg_info (now_seg);
13558 l = si->label_list;
13559 label = l != NULL ? l->label : NULL;
13560 mips_emit_delays ();
13562 mips_align (3, 0, label);
13563 mips_clear_insn_labels ();
13567 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13569 as_bad (_("Unsupported use of .gpdword"));
13570 ignore_rest_of_line ();
13574 md_number_to_chars (p, 0, 8);
13575 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13576 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13578 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13579 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13580 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13582 demand_empty_rest_of_line ();
13585 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13586 tables in SVR4 PIC code. */
13589 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13593 /* This is ignored when not generating SVR4 PIC code. */
13594 if (mips_pic != SVR4_PIC)
13600 /* Add $gp to the register named as an argument. */
13602 reg = tc_get_register (0);
13603 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13606 demand_empty_rest_of_line ();
13609 /* Handle the .insn pseudo-op. This marks instruction labels in
13610 mips16 mode. This permits the linker to handle them specially,
13611 such as generating jalx instructions when needed. We also make
13612 them odd for the duration of the assembly, in order to generate the
13613 right sort of code. We will make them even in the adjust_symtab
13614 routine, while leaving them marked. This is convenient for the
13615 debugger and the disassembler. The linker knows to make them odd
13619 s_insn (int ignore ATTRIBUTE_UNUSED)
13621 mips16_mark_labels ();
13623 demand_empty_rest_of_line ();
13626 /* Handle a .stabn directive. We need these in order to mark a label
13627 as being a mips16 text label correctly. Sometimes the compiler
13628 will emit a label, followed by a .stabn, and then switch sections.
13629 If the label and .stabn are in mips16 mode, then the label is
13630 really a mips16 text label. */
13633 s_mips_stab (int type)
13636 mips16_mark_labels ();
13641 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13644 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13651 name = input_line_pointer;
13652 c = get_symbol_end ();
13653 symbolP = symbol_find_or_make (name);
13654 S_SET_WEAK (symbolP);
13655 *input_line_pointer = c;
13657 SKIP_WHITESPACE ();
13659 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13661 if (S_IS_DEFINED (symbolP))
13663 as_bad ("ignoring attempt to redefine symbol %s",
13664 S_GET_NAME (symbolP));
13665 ignore_rest_of_line ();
13669 if (*input_line_pointer == ',')
13671 ++input_line_pointer;
13672 SKIP_WHITESPACE ();
13676 if (exp.X_op != O_symbol)
13678 as_bad ("bad .weakext directive");
13679 ignore_rest_of_line ();
13682 symbol_set_value_expression (symbolP, &exp);
13685 demand_empty_rest_of_line ();
13688 /* Parse a register string into a number. Called from the ECOFF code
13689 to parse .frame. The argument is non-zero if this is the frame
13690 register, so that we can record it in mips_frame_reg. */
13693 tc_get_register (int frame)
13697 SKIP_WHITESPACE ();
13698 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13702 mips_frame_reg = reg != 0 ? reg : SP;
13703 mips_frame_reg_valid = 1;
13704 mips_cprestore_valid = 0;
13710 md_section_align (asection *seg, valueT addr)
13712 int align = bfd_get_section_alignment (stdoutput, seg);
13716 /* We don't need to align ELF sections to the full alignment.
13717 However, Irix 5 may prefer that we align them at least to a 16
13718 byte boundary. We don't bother to align the sections if we
13719 are targeted for an embedded system. */
13720 if (strncmp (TARGET_OS, "elf", 3) == 0)
13726 return ((addr + (1 << align) - 1) & (-1 << align));
13729 /* Utility routine, called from above as well. If called while the
13730 input file is still being read, it's only an approximation. (For
13731 example, a symbol may later become defined which appeared to be
13732 undefined earlier.) */
13735 nopic_need_relax (symbolS *sym, int before_relaxing)
13740 if (g_switch_value > 0)
13742 const char *symname;
13745 /* Find out whether this symbol can be referenced off the $gp
13746 register. It can be if it is smaller than the -G size or if
13747 it is in the .sdata or .sbss section. Certain symbols can
13748 not be referenced off the $gp, although it appears as though
13750 symname = S_GET_NAME (sym);
13751 if (symname != (const char *) NULL
13752 && (strcmp (symname, "eprol") == 0
13753 || strcmp (symname, "etext") == 0
13754 || strcmp (symname, "_gp") == 0
13755 || strcmp (symname, "edata") == 0
13756 || strcmp (symname, "_fbss") == 0
13757 || strcmp (symname, "_fdata") == 0
13758 || strcmp (symname, "_ftext") == 0
13759 || strcmp (symname, "end") == 0
13760 || strcmp (symname, "_gp_disp") == 0))
13762 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13764 #ifndef NO_ECOFF_DEBUGGING
13765 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13766 && (symbol_get_obj (sym)->ecoff_extern_size
13767 <= g_switch_value))
13769 /* We must defer this decision until after the whole
13770 file has been read, since there might be a .extern
13771 after the first use of this symbol. */
13772 || (before_relaxing
13773 #ifndef NO_ECOFF_DEBUGGING
13774 && symbol_get_obj (sym)->ecoff_extern_size == 0
13776 && S_GET_VALUE (sym) == 0)
13777 || (S_GET_VALUE (sym) != 0
13778 && S_GET_VALUE (sym) <= g_switch_value)))
13782 const char *segname;
13784 segname = segment_name (S_GET_SEGMENT (sym));
13785 assert (strcmp (segname, ".lit8") != 0
13786 && strcmp (segname, ".lit4") != 0);
13787 change = (strcmp (segname, ".sdata") != 0
13788 && strcmp (segname, ".sbss") != 0
13789 && strncmp (segname, ".sdata.", 7) != 0
13790 && strncmp (segname, ".sbss.", 6) != 0
13791 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13792 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13797 /* We are not optimizing for the $gp register. */
13802 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13805 pic_need_relax (symbolS *sym, asection *segtype)
13809 /* Handle the case of a symbol equated to another symbol. */
13810 while (symbol_equated_reloc_p (sym))
13814 /* It's possible to get a loop here in a badly written program. */
13815 n = symbol_get_value_expression (sym)->X_add_symbol;
13821 if (symbol_section_p (sym))
13824 symsec = S_GET_SEGMENT (sym);
13826 /* This must duplicate the test in adjust_reloc_syms. */
13827 return (symsec != &bfd_und_section
13828 && symsec != &bfd_abs_section
13829 && !bfd_is_com_section (symsec)
13830 && !s_is_linkonce (sym, segtype)
13832 /* A global or weak symbol is treated as external. */
13833 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13839 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13840 extended opcode. SEC is the section the frag is in. */
13843 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13846 const struct mips16_immed_operand *op;
13848 int mintiny, maxtiny;
13852 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13854 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13857 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13858 op = mips16_immed_operands;
13859 while (op->type != type)
13862 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13867 if (type == '<' || type == '>' || type == '[' || type == ']')
13870 maxtiny = 1 << op->nbits;
13875 maxtiny = (1 << op->nbits) - 1;
13880 mintiny = - (1 << (op->nbits - 1));
13881 maxtiny = (1 << (op->nbits - 1)) - 1;
13884 sym_frag = symbol_get_frag (fragp->fr_symbol);
13885 val = S_GET_VALUE (fragp->fr_symbol);
13886 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13892 /* We won't have the section when we are called from
13893 mips_relax_frag. However, we will always have been called
13894 from md_estimate_size_before_relax first. If this is a
13895 branch to a different section, we mark it as such. If SEC is
13896 NULL, and the frag is not marked, then it must be a branch to
13897 the same section. */
13900 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13905 /* Must have been called from md_estimate_size_before_relax. */
13908 fragp->fr_subtype =
13909 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13911 /* FIXME: We should support this, and let the linker
13912 catch branches and loads that are out of range. */
13913 as_bad_where (fragp->fr_file, fragp->fr_line,
13914 _("unsupported PC relative reference to different section"));
13918 if (fragp != sym_frag && sym_frag->fr_address == 0)
13919 /* Assume non-extended on the first relaxation pass.
13920 The address we have calculated will be bogus if this is
13921 a forward branch to another frag, as the forward frag
13922 will have fr_address == 0. */
13926 /* In this case, we know for sure that the symbol fragment is in
13927 the same section. If the relax_marker of the symbol fragment
13928 differs from the relax_marker of this fragment, we have not
13929 yet adjusted the symbol fragment fr_address. We want to add
13930 in STRETCH in order to get a better estimate of the address.
13931 This particularly matters because of the shift bits. */
13933 && sym_frag->relax_marker != fragp->relax_marker)
13937 /* Adjust stretch for any alignment frag. Note that if have
13938 been expanding the earlier code, the symbol may be
13939 defined in what appears to be an earlier frag. FIXME:
13940 This doesn't handle the fr_subtype field, which specifies
13941 a maximum number of bytes to skip when doing an
13943 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13945 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13948 stretch = - ((- stretch)
13949 & ~ ((1 << (int) f->fr_offset) - 1));
13951 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13960 addr = fragp->fr_address + fragp->fr_fix;
13962 /* The base address rules are complicated. The base address of
13963 a branch is the following instruction. The base address of a
13964 PC relative load or add is the instruction itself, but if it
13965 is in a delay slot (in which case it can not be extended) use
13966 the address of the instruction whose delay slot it is in. */
13967 if (type == 'p' || type == 'q')
13971 /* If we are currently assuming that this frag should be
13972 extended, then, the current address is two bytes
13974 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13977 /* Ignore the low bit in the target, since it will be set
13978 for a text label. */
13979 if ((val & 1) != 0)
13982 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13984 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13987 val -= addr & ~ ((1 << op->shift) - 1);
13989 /* Branch offsets have an implicit 0 in the lowest bit. */
13990 if (type == 'p' || type == 'q')
13993 /* If any of the shifted bits are set, we must use an extended
13994 opcode. If the address depends on the size of this
13995 instruction, this can lead to a loop, so we arrange to always
13996 use an extended opcode. We only check this when we are in
13997 the main relaxation loop, when SEC is NULL. */
13998 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14000 fragp->fr_subtype =
14001 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14005 /* If we are about to mark a frag as extended because the value
14006 is precisely maxtiny + 1, then there is a chance of an
14007 infinite loop as in the following code:
14012 In this case when the la is extended, foo is 0x3fc bytes
14013 away, so the la can be shrunk, but then foo is 0x400 away, so
14014 the la must be extended. To avoid this loop, we mark the
14015 frag as extended if it was small, and is about to become
14016 extended with a value of maxtiny + 1. */
14017 if (val == ((maxtiny + 1) << op->shift)
14018 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14021 fragp->fr_subtype =
14022 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14026 else if (symsec != absolute_section && sec != NULL)
14027 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14029 if ((val & ((1 << op->shift) - 1)) != 0
14030 || val < (mintiny << op->shift)
14031 || val > (maxtiny << op->shift))
14037 /* Compute the length of a branch sequence, and adjust the
14038 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14039 worst-case length is computed, with UPDATE being used to indicate
14040 whether an unconditional (-1), branch-likely (+1) or regular (0)
14041 branch is to be computed. */
14043 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14045 bfd_boolean toofar;
14049 && S_IS_DEFINED (fragp->fr_symbol)
14050 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14055 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14057 addr = fragp->fr_address + fragp->fr_fix + 4;
14061 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14064 /* If the symbol is not defined or it's in a different segment,
14065 assume the user knows what's going on and emit a short
14071 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14073 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14074 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14075 RELAX_BRANCH_LINK (fragp->fr_subtype),
14081 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14084 if (mips_pic != NO_PIC)
14086 /* Additional space for PIC loading of target address. */
14088 if (mips_opts.isa == ISA_MIPS1)
14089 /* Additional space for $at-stabilizing nop. */
14093 /* If branch is conditional. */
14094 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14101 /* Estimate the size of a frag before relaxing. Unless this is the
14102 mips16, we are not really relaxing here, and the final size is
14103 encoded in the subtype information. For the mips16, we have to
14104 decide whether we are using an extended opcode or not. */
14107 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14111 if (RELAX_BRANCH_P (fragp->fr_subtype))
14114 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14116 return fragp->fr_var;
14119 if (RELAX_MIPS16_P (fragp->fr_subtype))
14120 /* We don't want to modify the EXTENDED bit here; it might get us
14121 into infinite loops. We change it only in mips_relax_frag(). */
14122 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14124 if (mips_pic == NO_PIC)
14125 change = nopic_need_relax (fragp->fr_symbol, 0);
14126 else if (mips_pic == SVR4_PIC)
14127 change = pic_need_relax (fragp->fr_symbol, segtype);
14128 else if (mips_pic == VXWORKS_PIC)
14129 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14136 fragp->fr_subtype |= RELAX_USE_SECOND;
14137 return -RELAX_FIRST (fragp->fr_subtype);
14140 return -RELAX_SECOND (fragp->fr_subtype);
14143 /* This is called to see whether a reloc against a defined symbol
14144 should be converted into a reloc against a section. */
14147 mips_fix_adjustable (fixS *fixp)
14149 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14150 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14153 if (fixp->fx_addsy == NULL)
14156 /* If symbol SYM is in a mergeable section, relocations of the form
14157 SYM + 0 can usually be made section-relative. The mergeable data
14158 is then identified by the section offset rather than by the symbol.
14160 However, if we're generating REL LO16 relocations, the offset is split
14161 between the LO16 and parterning high part relocation. The linker will
14162 need to recalculate the complete offset in order to correctly identify
14165 The linker has traditionally not looked for the parterning high part
14166 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14167 placed anywhere. Rather than break backwards compatibility by changing
14168 this, it seems better not to force the issue, and instead keep the
14169 original symbol. This will work with either linker behavior. */
14170 if ((lo16_reloc_p (fixp->fx_r_type)
14171 || reloc_needs_lo_p (fixp->fx_r_type))
14172 && HAVE_IN_PLACE_ADDENDS
14173 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14177 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14178 to a floating-point stub. The same is true for non-R_MIPS16_26
14179 relocations against MIPS16 functions; in this case, the stub becomes
14180 the function's canonical address.
14182 Floating-point stubs are stored in unique .mips16.call.* or
14183 .mips16.fn.* sections. If a stub T for function F is in section S,
14184 the first relocation in section S must be against F; this is how the
14185 linker determines the target function. All relocations that might
14186 resolve to T must also be against F. We therefore have the following
14187 restrictions, which are given in an intentionally-redundant way:
14189 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14192 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14193 if that stub might be used.
14195 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14198 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14199 that stub might be used.
14201 There is a further restriction:
14203 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14204 on targets with in-place addends; the relocation field cannot
14205 encode the low bit.
14207 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14208 against a MIPS16 symbol.
14210 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14211 relocation against some symbol R, no relocation against R may be
14212 reduced. (Note that this deals with (2) as well as (1) because
14213 relocations against global symbols will never be reduced on ELF
14214 targets.) This approach is a little simpler than trying to detect
14215 stub sections, and gives the "all or nothing" per-symbol consistency
14216 that we have for MIPS16 symbols. */
14218 && fixp->fx_subsy == NULL
14219 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14220 || *symbol_get_tc (fixp->fx_addsy)))
14227 /* Translate internal representation of relocation info to BFD target
14231 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14233 static arelent *retval[4];
14235 bfd_reloc_code_real_type code;
14237 memset (retval, 0, sizeof(retval));
14238 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14239 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14240 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14241 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14243 if (fixp->fx_pcrel)
14245 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14247 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14248 Relocations want only the symbol offset. */
14249 reloc->addend = fixp->fx_addnumber + reloc->address;
14252 /* A gruesome hack which is a result of the gruesome gas
14253 reloc handling. What's worse, for COFF (as opposed to
14254 ECOFF), we might need yet another copy of reloc->address.
14255 See bfd_install_relocation. */
14256 reloc->addend += reloc->address;
14260 reloc->addend = fixp->fx_addnumber;
14262 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14263 entry to be used in the relocation's section offset. */
14264 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14266 reloc->address = reloc->addend;
14270 code = fixp->fx_r_type;
14272 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14273 if (reloc->howto == NULL)
14275 as_bad_where (fixp->fx_file, fixp->fx_line,
14276 _("Can not represent %s relocation in this object file format"),
14277 bfd_get_reloc_code_name (code));
14284 /* Relax a machine dependent frag. This returns the amount by which
14285 the current size of the frag should change. */
14288 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14290 if (RELAX_BRANCH_P (fragp->fr_subtype))
14292 offsetT old_var = fragp->fr_var;
14294 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14296 return fragp->fr_var - old_var;
14299 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14302 if (mips16_extended_frag (fragp, NULL, stretch))
14304 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14306 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14311 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14313 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14320 /* Convert a machine dependent frag. */
14323 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14325 if (RELAX_BRANCH_P (fragp->fr_subtype))
14328 unsigned long insn;
14332 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14334 if (target_big_endian)
14335 insn = bfd_getb32 (buf);
14337 insn = bfd_getl32 (buf);
14339 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14341 /* We generate a fixup instead of applying it right now
14342 because, if there are linker relaxations, we're going to
14343 need the relocations. */
14344 exp.X_op = O_symbol;
14345 exp.X_add_symbol = fragp->fr_symbol;
14346 exp.X_add_number = fragp->fr_offset;
14348 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14349 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14350 fixp->fx_file = fragp->fr_file;
14351 fixp->fx_line = fragp->fr_line;
14353 md_number_to_chars ((char *) buf, insn, 4);
14360 as_warn_where (fragp->fr_file, fragp->fr_line,
14361 _("relaxed out-of-range branch into a jump"));
14363 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14366 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14368 /* Reverse the branch. */
14369 switch ((insn >> 28) & 0xf)
14372 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14373 have the condition reversed by tweaking a single
14374 bit, and their opcodes all have 0x4???????. */
14375 assert ((insn & 0xf1000000) == 0x41000000);
14376 insn ^= 0x00010000;
14380 /* bltz 0x04000000 bgez 0x04010000
14381 bltzal 0x04100000 bgezal 0x04110000 */
14382 assert ((insn & 0xfc0e0000) == 0x04000000);
14383 insn ^= 0x00010000;
14387 /* beq 0x10000000 bne 0x14000000
14388 blez 0x18000000 bgtz 0x1c000000 */
14389 insn ^= 0x04000000;
14397 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14399 /* Clear the and-link bit. */
14400 assert ((insn & 0xfc1c0000) == 0x04100000);
14402 /* bltzal 0x04100000 bgezal 0x04110000
14403 bltzall 0x04120000 bgezall 0x04130000 */
14404 insn &= ~0x00100000;
14407 /* Branch over the branch (if the branch was likely) or the
14408 full jump (not likely case). Compute the offset from the
14409 current instruction to branch to. */
14410 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14414 /* How many bytes in instructions we've already emitted? */
14415 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14416 /* How many bytes in instructions from here to the end? */
14417 i = fragp->fr_var - i;
14419 /* Convert to instruction count. */
14421 /* Branch counts from the next instruction. */
14424 /* Branch over the jump. */
14425 md_number_to_chars ((char *) buf, insn, 4);
14429 md_number_to_chars ((char *) buf, 0, 4);
14432 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14434 /* beql $0, $0, 2f */
14436 /* Compute the PC offset from the current instruction to
14437 the end of the variable frag. */
14438 /* How many bytes in instructions we've already emitted? */
14439 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14440 /* How many bytes in instructions from here to the end? */
14441 i = fragp->fr_var - i;
14442 /* Convert to instruction count. */
14444 /* Don't decrement i, because we want to branch over the
14448 md_number_to_chars ((char *) buf, insn, 4);
14451 md_number_to_chars ((char *) buf, 0, 4);
14456 if (mips_pic == NO_PIC)
14459 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14460 ? 0x0c000000 : 0x08000000);
14461 exp.X_op = O_symbol;
14462 exp.X_add_symbol = fragp->fr_symbol;
14463 exp.X_add_number = fragp->fr_offset;
14465 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14466 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14467 fixp->fx_file = fragp->fr_file;
14468 fixp->fx_line = fragp->fr_line;
14470 md_number_to_chars ((char *) buf, insn, 4);
14475 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14476 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
14477 exp.X_op = O_symbol;
14478 exp.X_add_symbol = fragp->fr_symbol;
14479 exp.X_add_number = fragp->fr_offset;
14481 if (fragp->fr_offset)
14483 exp.X_add_symbol = make_expr_symbol (&exp);
14484 exp.X_add_number = 0;
14487 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14488 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14489 fixp->fx_file = fragp->fr_file;
14490 fixp->fx_line = fragp->fr_line;
14492 md_number_to_chars ((char *) buf, insn, 4);
14495 if (mips_opts.isa == ISA_MIPS1)
14498 md_number_to_chars ((char *) buf, 0, 4);
14502 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14503 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14505 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14506 4, &exp, FALSE, BFD_RELOC_LO16);
14507 fixp->fx_file = fragp->fr_file;
14508 fixp->fx_line = fragp->fr_line;
14510 md_number_to_chars ((char *) buf, insn, 4);
14514 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14519 md_number_to_chars ((char *) buf, insn, 4);
14524 assert (buf == (bfd_byte *)fragp->fr_literal
14525 + fragp->fr_fix + fragp->fr_var);
14527 fragp->fr_fix += fragp->fr_var;
14532 if (RELAX_MIPS16_P (fragp->fr_subtype))
14535 const struct mips16_immed_operand *op;
14536 bfd_boolean small, ext;
14539 unsigned long insn;
14540 bfd_boolean use_extend;
14541 unsigned short extend;
14543 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14544 op = mips16_immed_operands;
14545 while (op->type != type)
14548 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14559 resolve_symbol_value (fragp->fr_symbol);
14560 val = S_GET_VALUE (fragp->fr_symbol);
14565 addr = fragp->fr_address + fragp->fr_fix;
14567 /* The rules for the base address of a PC relative reloc are
14568 complicated; see mips16_extended_frag. */
14569 if (type == 'p' || type == 'q')
14574 /* Ignore the low bit in the target, since it will be
14575 set for a text label. */
14576 if ((val & 1) != 0)
14579 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14581 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14584 addr &= ~ (addressT) ((1 << op->shift) - 1);
14587 /* Make sure the section winds up with the alignment we have
14590 record_alignment (asec, op->shift);
14594 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14595 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14596 as_warn_where (fragp->fr_file, fragp->fr_line,
14597 _("extended instruction in delay slot"));
14599 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14601 if (target_big_endian)
14602 insn = bfd_getb16 (buf);
14604 insn = bfd_getl16 (buf);
14606 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14607 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14608 small, ext, &insn, &use_extend, &extend);
14612 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14613 fragp->fr_fix += 2;
14617 md_number_to_chars ((char *) buf, insn, 2);
14618 fragp->fr_fix += 2;
14626 first = RELAX_FIRST (fragp->fr_subtype);
14627 second = RELAX_SECOND (fragp->fr_subtype);
14628 fixp = (fixS *) fragp->fr_opcode;
14630 /* Possibly emit a warning if we've chosen the longer option. */
14631 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14632 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14634 const char *msg = macro_warning (fragp->fr_subtype);
14636 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14639 /* Go through all the fixups for the first sequence. Disable them
14640 (by marking them as done) if we're going to use the second
14641 sequence instead. */
14643 && fixp->fx_frag == fragp
14644 && fixp->fx_where < fragp->fr_fix - second)
14646 if (fragp->fr_subtype & RELAX_USE_SECOND)
14648 fixp = fixp->fx_next;
14651 /* Go through the fixups for the second sequence. Disable them if
14652 we're going to use the first sequence, otherwise adjust their
14653 addresses to account for the relaxation. */
14654 while (fixp && fixp->fx_frag == fragp)
14656 if (fragp->fr_subtype & RELAX_USE_SECOND)
14657 fixp->fx_where -= first;
14660 fixp = fixp->fx_next;
14663 /* Now modify the frag contents. */
14664 if (fragp->fr_subtype & RELAX_USE_SECOND)
14668 start = fragp->fr_literal + fragp->fr_fix - first - second;
14669 memmove (start, start + first, second);
14670 fragp->fr_fix -= first;
14673 fragp->fr_fix -= second;
14679 /* This function is called after the relocs have been generated.
14680 We've been storing mips16 text labels as odd. Here we convert them
14681 back to even for the convenience of the debugger. */
14684 mips_frob_file_after_relocs (void)
14687 unsigned int count, i;
14692 syms = bfd_get_outsymbols (stdoutput);
14693 count = bfd_get_symcount (stdoutput);
14694 for (i = 0; i < count; i++, syms++)
14696 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14697 && ((*syms)->value & 1) != 0)
14699 (*syms)->value &= ~1;
14700 /* If the symbol has an odd size, it was probably computed
14701 incorrectly, so adjust that as well. */
14702 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14703 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14710 /* This function is called whenever a label is defined. It is used
14711 when handling branch delays; if a branch has a label, we assume we
14712 can not move it. */
14715 mips_define_label (symbolS *sym)
14717 segment_info_type *si = seg_info (now_seg);
14718 struct insn_label_list *l;
14720 if (free_insn_labels == NULL)
14721 l = (struct insn_label_list *) xmalloc (sizeof *l);
14724 l = free_insn_labels;
14725 free_insn_labels = l->next;
14729 l->next = si->label_list;
14730 si->label_list = l;
14733 dwarf2_emit_label (sym);
14737 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14739 /* Some special processing for a MIPS ELF file. */
14742 mips_elf_final_processing (void)
14744 /* Write out the register information. */
14745 if (mips_abi != N64_ABI)
14749 s.ri_gprmask = mips_gprmask;
14750 s.ri_cprmask[0] = mips_cprmask[0];
14751 s.ri_cprmask[1] = mips_cprmask[1];
14752 s.ri_cprmask[2] = mips_cprmask[2];
14753 s.ri_cprmask[3] = mips_cprmask[3];
14754 /* The gp_value field is set by the MIPS ELF backend. */
14756 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14757 ((Elf32_External_RegInfo *)
14758 mips_regmask_frag));
14762 Elf64_Internal_RegInfo s;
14764 s.ri_gprmask = mips_gprmask;
14766 s.ri_cprmask[0] = mips_cprmask[0];
14767 s.ri_cprmask[1] = mips_cprmask[1];
14768 s.ri_cprmask[2] = mips_cprmask[2];
14769 s.ri_cprmask[3] = mips_cprmask[3];
14770 /* The gp_value field is set by the MIPS ELF backend. */
14772 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14773 ((Elf64_External_RegInfo *)
14774 mips_regmask_frag));
14777 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14778 sort of BFD interface for this. */
14779 if (mips_any_noreorder)
14780 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14781 if (mips_pic != NO_PIC)
14783 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14784 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14787 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14789 /* Set MIPS ELF flags for ASEs. */
14790 /* We may need to define a new flag for DSP ASE, and set this flag when
14791 file_ase_dsp is true. */
14792 /* Same for DSP R2. */
14793 /* We may need to define a new flag for MT ASE, and set this flag when
14794 file_ase_mt is true. */
14795 if (file_ase_mips16)
14796 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14797 #if 0 /* XXX FIXME */
14798 if (file_ase_mips3d)
14799 elf_elfheader (stdoutput)->e_flags |= ???;
14802 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14804 /* Set the MIPS ELF ABI flags. */
14805 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14806 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14807 else if (mips_abi == O64_ABI)
14808 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14809 else if (mips_abi == EABI_ABI)
14811 if (!file_mips_gp32)
14812 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14814 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14816 else if (mips_abi == N32_ABI)
14817 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14819 /* Nothing to do for N64_ABI. */
14821 if (mips_32bitmode)
14822 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14824 #if 0 /* XXX FIXME */
14825 /* 32 bit code with 64 bit FP registers. */
14826 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14827 elf_elfheader (stdoutput)->e_flags |= ???;
14831 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14833 typedef struct proc {
14835 symbolS *func_end_sym;
14836 unsigned long reg_mask;
14837 unsigned long reg_offset;
14838 unsigned long fpreg_mask;
14839 unsigned long fpreg_offset;
14840 unsigned long frame_offset;
14841 unsigned long frame_reg;
14842 unsigned long pc_reg;
14845 static procS cur_proc;
14846 static procS *cur_proc_ptr;
14847 static int numprocs;
14849 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14853 mips_nop_opcode (void)
14855 return seg_info (now_seg)->tc_segment_info_data.mips16;
14858 /* Fill in an rs_align_code fragment. This only needs to do something
14859 for MIPS16 code, where 0 is not a nop. */
14862 mips_handle_align (fragS *fragp)
14866 if (fragp->fr_type != rs_align_code)
14869 p = fragp->fr_literal + fragp->fr_fix;
14874 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14880 md_number_to_chars (p, mips16_nop_insn.insn_opcode, 2);
14886 md_obj_begin (void)
14893 /* Check for premature end, nesting errors, etc. */
14895 as_warn (_("missing .end at end of assembly"));
14904 if (*input_line_pointer == '-')
14906 ++input_line_pointer;
14909 if (!ISDIGIT (*input_line_pointer))
14910 as_bad (_("expected simple number"));
14911 if (input_line_pointer[0] == '0')
14913 if (input_line_pointer[1] == 'x')
14915 input_line_pointer += 2;
14916 while (ISXDIGIT (*input_line_pointer))
14919 val |= hex_value (*input_line_pointer++);
14921 return negative ? -val : val;
14925 ++input_line_pointer;
14926 while (ISDIGIT (*input_line_pointer))
14929 val |= *input_line_pointer++ - '0';
14931 return negative ? -val : val;
14934 if (!ISDIGIT (*input_line_pointer))
14936 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14937 *input_line_pointer, *input_line_pointer);
14938 as_warn (_("invalid number"));
14941 while (ISDIGIT (*input_line_pointer))
14944 val += *input_line_pointer++ - '0';
14946 return negative ? -val : val;
14949 /* The .file directive; just like the usual .file directive, but there
14950 is an initial number which is the ECOFF file index. In the non-ECOFF
14951 case .file implies DWARF-2. */
14954 s_mips_file (int x ATTRIBUTE_UNUSED)
14956 static int first_file_directive = 0;
14958 if (ECOFF_DEBUGGING)
14967 filename = dwarf2_directive_file (0);
14969 /* Versions of GCC up to 3.1 start files with a ".file"
14970 directive even for stabs output. Make sure that this
14971 ".file" is handled. Note that you need a version of GCC
14972 after 3.1 in order to support DWARF-2 on MIPS. */
14973 if (filename != NULL && ! first_file_directive)
14975 (void) new_logical_line (filename, -1);
14976 s_app_file_string (filename, 0);
14978 first_file_directive = 1;
14982 /* The .loc directive, implying DWARF-2. */
14985 s_mips_loc (int x ATTRIBUTE_UNUSED)
14987 if (!ECOFF_DEBUGGING)
14988 dwarf2_directive_loc (0);
14991 /* The .end directive. */
14994 s_mips_end (int x ATTRIBUTE_UNUSED)
14998 /* Following functions need their own .frame and .cprestore directives. */
14999 mips_frame_reg_valid = 0;
15000 mips_cprestore_valid = 0;
15002 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15005 demand_empty_rest_of_line ();
15010 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15011 as_warn (_(".end not in text section"));
15015 as_warn (_(".end directive without a preceding .ent directive."));
15016 demand_empty_rest_of_line ();
15022 assert (S_GET_NAME (p));
15023 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15024 as_warn (_(".end symbol does not match .ent symbol."));
15026 if (debug_type == DEBUG_STABS)
15027 stabs_generate_asm_endfunc (S_GET_NAME (p),
15031 as_warn (_(".end directive missing or unknown symbol"));
15034 /* Create an expression to calculate the size of the function. */
15035 if (p && cur_proc_ptr)
15037 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15038 expressionS *exp = xmalloc (sizeof (expressionS));
15041 exp->X_op = O_subtract;
15042 exp->X_add_symbol = symbol_temp_new_now ();
15043 exp->X_op_symbol = p;
15044 exp->X_add_number = 0;
15046 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15049 /* Generate a .pdr section. */
15050 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15052 segT saved_seg = now_seg;
15053 subsegT saved_subseg = now_subseg;
15058 dot = frag_now_fix ();
15060 #ifdef md_flush_pending_output
15061 md_flush_pending_output ();
15065 subseg_set (pdr_seg, 0);
15067 /* Write the symbol. */
15068 exp.X_op = O_symbol;
15069 exp.X_add_symbol = p;
15070 exp.X_add_number = 0;
15071 emit_expr (&exp, 4);
15073 fragp = frag_more (7 * 4);
15075 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15076 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15077 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15078 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15079 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15080 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15081 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15083 subseg_set (saved_seg, saved_subseg);
15085 #endif /* OBJ_ELF */
15087 cur_proc_ptr = NULL;
15090 /* The .aent and .ent directives. */
15093 s_mips_ent (int aent)
15097 symbolP = get_symbol ();
15098 if (*input_line_pointer == ',')
15099 ++input_line_pointer;
15100 SKIP_WHITESPACE ();
15101 if (ISDIGIT (*input_line_pointer)
15102 || *input_line_pointer == '-')
15105 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15106 as_warn (_(".ent or .aent not in text section."));
15108 if (!aent && cur_proc_ptr)
15109 as_warn (_("missing .end"));
15113 /* This function needs its own .frame and .cprestore directives. */
15114 mips_frame_reg_valid = 0;
15115 mips_cprestore_valid = 0;
15117 cur_proc_ptr = &cur_proc;
15118 memset (cur_proc_ptr, '\0', sizeof (procS));
15120 cur_proc_ptr->func_sym = symbolP;
15122 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15126 if (debug_type == DEBUG_STABS)
15127 stabs_generate_asm_func (S_GET_NAME (symbolP),
15128 S_GET_NAME (symbolP));
15131 demand_empty_rest_of_line ();
15134 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15135 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15136 s_mips_frame is used so that we can set the PDR information correctly.
15137 We can't use the ecoff routines because they make reference to the ecoff
15138 symbol table (in the mdebug section). */
15141 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15144 if (IS_ELF && !ECOFF_DEBUGGING)
15148 if (cur_proc_ptr == (procS *) NULL)
15150 as_warn (_(".frame outside of .ent"));
15151 demand_empty_rest_of_line ();
15155 cur_proc_ptr->frame_reg = tc_get_register (1);
15157 SKIP_WHITESPACE ();
15158 if (*input_line_pointer++ != ','
15159 || get_absolute_expression_and_terminator (&val) != ',')
15161 as_warn (_("Bad .frame directive"));
15162 --input_line_pointer;
15163 demand_empty_rest_of_line ();
15167 cur_proc_ptr->frame_offset = val;
15168 cur_proc_ptr->pc_reg = tc_get_register (0);
15170 demand_empty_rest_of_line ();
15173 #endif /* OBJ_ELF */
15177 /* The .fmask and .mask directives. If the mdebug section is present
15178 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15179 embedded targets, s_mips_mask is used so that we can set the PDR
15180 information correctly. We can't use the ecoff routines because they
15181 make reference to the ecoff symbol table (in the mdebug section). */
15184 s_mips_mask (int reg_type)
15187 if (IS_ELF && !ECOFF_DEBUGGING)
15191 if (cur_proc_ptr == (procS *) NULL)
15193 as_warn (_(".mask/.fmask outside of .ent"));
15194 demand_empty_rest_of_line ();
15198 if (get_absolute_expression_and_terminator (&mask) != ',')
15200 as_warn (_("Bad .mask/.fmask directive"));
15201 --input_line_pointer;
15202 demand_empty_rest_of_line ();
15206 off = get_absolute_expression ();
15208 if (reg_type == 'F')
15210 cur_proc_ptr->fpreg_mask = mask;
15211 cur_proc_ptr->fpreg_offset = off;
15215 cur_proc_ptr->reg_mask = mask;
15216 cur_proc_ptr->reg_offset = off;
15219 demand_empty_rest_of_line ();
15222 #endif /* OBJ_ELF */
15223 s_ignore (reg_type);
15226 /* A table describing all the processors gas knows about. Names are
15227 matched in the order listed.
15229 To ease comparison, please keep this table in the same order as
15230 gcc's mips_cpu_info_table[]. */
15231 static const struct mips_cpu_info mips_cpu_info_table[] =
15233 /* Entries for generic ISAs */
15234 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15235 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15236 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15237 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15238 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15239 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15240 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15241 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15242 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15245 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15246 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15247 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15250 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15253 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15254 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15255 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15256 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15257 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15258 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15259 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15260 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15261 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15262 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15263 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15264 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15265 /* ST Microelectronics Loongson 2E and 2F cores */
15266 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15267 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15270 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15271 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15272 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15273 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15274 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15275 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15276 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15277 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15278 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15279 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15280 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15281 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15282 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15283 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15284 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15287 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15288 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15289 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15290 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15292 /* MIPS 32 Release 2 */
15293 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15294 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15295 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15296 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15297 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15298 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15299 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15300 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15301 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15302 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15303 /* Deprecated forms of the above. */
15304 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15305 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15306 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15307 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15308 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15309 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15310 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15311 /* Deprecated forms of the above. */
15312 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15313 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15314 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15315 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15316 ISA_MIPS32R2, CPU_MIPS32R2 },
15317 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15318 ISA_MIPS32R2, CPU_MIPS32R2 },
15319 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15320 ISA_MIPS32R2, CPU_MIPS32R2 },
15321 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15322 ISA_MIPS32R2, CPU_MIPS32R2 },
15323 /* Deprecated forms of the above. */
15324 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15325 ISA_MIPS32R2, CPU_MIPS32R2 },
15326 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15327 ISA_MIPS32R2, CPU_MIPS32R2 },
15328 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15329 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15330 ISA_MIPS32R2, CPU_MIPS32R2 },
15331 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15332 ISA_MIPS32R2, CPU_MIPS32R2 },
15333 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15334 ISA_MIPS32R2, CPU_MIPS32R2 },
15335 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15336 ISA_MIPS32R2, CPU_MIPS32R2 },
15337 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15338 ISA_MIPS32R2, CPU_MIPS32R2 },
15339 /* Deprecated forms of the above. */
15340 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15341 ISA_MIPS32R2, CPU_MIPS32R2 },
15342 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15343 ISA_MIPS32R2, CPU_MIPS32R2 },
15346 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15347 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15348 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15349 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15351 /* Broadcom SB-1 CPU core */
15352 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15353 ISA_MIPS64, CPU_SB1 },
15354 /* Broadcom SB-1A CPU core */
15355 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15356 ISA_MIPS64, CPU_SB1 },
15358 /* MIPS 64 Release 2 */
15360 /* Cavium Networks Octeon CPU core */
15361 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15364 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15371 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15372 with a final "000" replaced by "k". Ignore case.
15374 Note: this function is shared between GCC and GAS. */
15377 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15379 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15380 given++, canonical++;
15382 return ((*given == 0 && *canonical == 0)
15383 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15387 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15388 CPU name. We've traditionally allowed a lot of variation here.
15390 Note: this function is shared between GCC and GAS. */
15393 mips_matching_cpu_name_p (const char *canonical, const char *given)
15395 /* First see if the name matches exactly, or with a final "000"
15396 turned into "k". */
15397 if (mips_strict_matching_cpu_name_p (canonical, given))
15400 /* If not, try comparing based on numerical designation alone.
15401 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15402 if (TOLOWER (*given) == 'r')
15404 if (!ISDIGIT (*given))
15407 /* Skip over some well-known prefixes in the canonical name,
15408 hoping to find a number there too. */
15409 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15411 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15413 else if (TOLOWER (canonical[0]) == 'r')
15416 return mips_strict_matching_cpu_name_p (canonical, given);
15420 /* Parse an option that takes the name of a processor as its argument.
15421 OPTION is the name of the option and CPU_STRING is the argument.
15422 Return the corresponding processor enumeration if the CPU_STRING is
15423 recognized, otherwise report an error and return null.
15425 A similar function exists in GCC. */
15427 static const struct mips_cpu_info *
15428 mips_parse_cpu (const char *option, const char *cpu_string)
15430 const struct mips_cpu_info *p;
15432 /* 'from-abi' selects the most compatible architecture for the given
15433 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15434 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15435 version. Look first at the -mgp options, if given, otherwise base
15436 the choice on MIPS_DEFAULT_64BIT.
15438 Treat NO_ABI like the EABIs. One reason to do this is that the
15439 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15440 architecture. This code picks MIPS I for 'mips' and MIPS III for
15441 'mips64', just as we did in the days before 'from-abi'. */
15442 if (strcasecmp (cpu_string, "from-abi") == 0)
15444 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15445 return mips_cpu_info_from_isa (ISA_MIPS1);
15447 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15448 return mips_cpu_info_from_isa (ISA_MIPS3);
15450 if (file_mips_gp32 >= 0)
15451 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15453 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15458 /* 'default' has traditionally been a no-op. Probably not very useful. */
15459 if (strcasecmp (cpu_string, "default") == 0)
15462 for (p = mips_cpu_info_table; p->name != 0; p++)
15463 if (mips_matching_cpu_name_p (p->name, cpu_string))
15466 as_bad ("Bad value (%s) for %s", cpu_string, option);
15470 /* Return the canonical processor information for ISA (a member of the
15471 ISA_MIPS* enumeration). */
15473 static const struct mips_cpu_info *
15474 mips_cpu_info_from_isa (int isa)
15478 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15479 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15480 && isa == mips_cpu_info_table[i].isa)
15481 return (&mips_cpu_info_table[i]);
15486 static const struct mips_cpu_info *
15487 mips_cpu_info_from_arch (int arch)
15491 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15492 if (arch == mips_cpu_info_table[i].cpu)
15493 return (&mips_cpu_info_table[i]);
15499 show (FILE *stream, const char *string, int *col_p, int *first_p)
15503 fprintf (stream, "%24s", "");
15508 fprintf (stream, ", ");
15512 if (*col_p + strlen (string) > 72)
15514 fprintf (stream, "\n%24s", "");
15518 fprintf (stream, "%s", string);
15519 *col_p += strlen (string);
15525 md_show_usage (FILE *stream)
15530 fprintf (stream, _("\
15532 -EB generate big endian output\n\
15533 -EL generate little endian output\n\
15534 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15535 -G NUM allow referencing objects up to NUM bytes\n\
15536 implicitly with the gp register [default 8]\n"));
15537 fprintf (stream, _("\
15538 -mips1 generate MIPS ISA I instructions\n\
15539 -mips2 generate MIPS ISA II instructions\n\
15540 -mips3 generate MIPS ISA III instructions\n\
15541 -mips4 generate MIPS ISA IV instructions\n\
15542 -mips5 generate MIPS ISA V instructions\n\
15543 -mips32 generate MIPS32 ISA instructions\n\
15544 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15545 -mips64 generate MIPS64 ISA instructions\n\
15546 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15547 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15551 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15552 show (stream, mips_cpu_info_table[i].name, &column, &first);
15553 show (stream, "from-abi", &column, &first);
15554 fputc ('\n', stream);
15556 fprintf (stream, _("\
15557 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15558 -no-mCPU don't generate code specific to CPU.\n\
15559 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15563 show (stream, "3900", &column, &first);
15564 show (stream, "4010", &column, &first);
15565 show (stream, "4100", &column, &first);
15566 show (stream, "4650", &column, &first);
15567 fputc ('\n', stream);
15569 fprintf (stream, _("\
15570 -mips16 generate mips16 instructions\n\
15571 -no-mips16 do not generate mips16 instructions\n"));
15572 fprintf (stream, _("\
15573 -msmartmips generate smartmips instructions\n\
15574 -mno-smartmips do not generate smartmips instructions\n"));
15575 fprintf (stream, _("\
15576 -mdsp generate DSP instructions\n\
15577 -mno-dsp do not generate DSP instructions\n"));
15578 fprintf (stream, _("\
15579 -mdspr2 generate DSP R2 instructions\n\
15580 -mno-dspr2 do not generate DSP R2 instructions\n"));
15581 fprintf (stream, _("\
15582 -mmt generate MT instructions\n\
15583 -mno-mt do not generate MT instructions\n"));
15584 fprintf (stream, _("\
15585 -mfix-vr4120 work around certain VR4120 errata\n\
15586 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15587 -mfix-24k insert a nop after ERET and DERET instructions\n\
15588 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15589 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15590 -msym32 assume all symbols have 32-bit values\n\
15591 -O0 remove unneeded NOPs, do not swap branches\n\
15592 -O remove unneeded NOPs and swap branches\n\
15593 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15594 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15595 fprintf (stream, _("\
15596 -mhard-float allow floating-point instructions\n\
15597 -msoft-float do not allow floating-point instructions\n\
15598 -msingle-float only allow 32-bit floating-point operations\n\
15599 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15600 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15603 fprintf (stream, _("\
15604 -KPIC, -call_shared generate SVR4 position independent code\n\
15605 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15606 -mvxworks-pic generate VxWorks position independent code\n\
15607 -non_shared do not generate code that can operate with DSOs\n\
15608 -xgot assume a 32 bit GOT\n\
15609 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15610 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15611 position dependent (non shared) code\n\
15612 -mabi=ABI create ABI conformant object file for:\n"));
15616 show (stream, "32", &column, &first);
15617 show (stream, "o64", &column, &first);
15618 show (stream, "n32", &column, &first);
15619 show (stream, "64", &column, &first);
15620 show (stream, "eabi", &column, &first);
15622 fputc ('\n', stream);
15624 fprintf (stream, _("\
15625 -32 create o32 ABI object file (default)\n\
15626 -n32 create n32 ABI object file\n\
15627 -64 create 64 ABI object file\n"));
15632 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15634 if (HAVE_64BIT_SYMBOLS)
15637 return dwarf2_format_64bit_irix;
15639 return dwarf2_format_64bit;
15643 return dwarf2_format_32bit;
15647 mips_dwarf2_addr_size (void)
15649 if (HAVE_64BIT_OBJECTS)
15655 /* Standard calling conventions leave the CFA at SP on entry. */
15657 mips_cfi_frame_initial_instructions (void)
15659 cfi_add_CFA_def_cfa_register (SP);
15663 tc_mips_regname_to_dw2regnum (char *regname)
15665 unsigned int regnum = -1;
15668 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))