1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
1171 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1174 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1179 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1186 /* Sign-extend 16-bit value X. */
1187 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1189 /* Is the given value a sign-extended 32-bit value? */
1190 #define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1194 /* Is the given value a sign-extended 16-bit value? */
1195 #define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1199 /* Is the given value a sign-extended 12-bit value? */
1200 #define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1203 /* Is the given value a sign-extended 9-bit value? */
1204 #define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1207 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208 #define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1212 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1214 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1217 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1218 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1223 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
1228 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229 #define MIPS16_EXTEND (0xf000U << 16)
1231 /* Whether or not we are emitting a branch-likely macro. */
1232 static bfd_boolean emit_branch_likely_macro = FALSE;
1234 /* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes[2];
1251 /* The symbol on which the choice of sequence depends. */
1255 /* Global variables used to decide whether a macro needs a warning. */
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p;
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length;
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1268 unsigned int sizes[2];
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes[2];
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns[2];
1287 /* The first variant frag for this macro. */
1289 } mips_macro_warning;
1291 /* Prototypes for static functions. */
1293 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1295 static void append_insn
1296 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1297 bfd_boolean expansionp);
1298 static void mips_no_prev_insn (void);
1299 static void macro_build (expressionS *, const char *, const char *, ...);
1300 static void mips16_macro_build
1301 (expressionS *, const char *, const char *, va_list *);
1302 static void load_register (int, expressionS *, int);
1303 static void macro_start (void);
1304 static void macro_end (void);
1305 static void macro (struct mips_cl_insn *ip, char *str);
1306 static void mips16_macro (struct mips_cl_insn * ip);
1307 static void mips_ip (char *str, struct mips_cl_insn * ip);
1308 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1309 static void mips16_immed
1310 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1311 unsigned int, unsigned long *);
1312 static size_t my_getSmallExpression
1313 (expressionS *, bfd_reloc_code_real_type *, char *);
1314 static void my_getExpression (expressionS *, char *);
1315 static void s_align (int);
1316 static void s_change_sec (int);
1317 static void s_change_section (int);
1318 static void s_cons (int);
1319 static void s_float_cons (int);
1320 static void s_mips_globl (int);
1321 static void s_option (int);
1322 static void s_mipsset (int);
1323 static void s_abicalls (int);
1324 static void s_cpload (int);
1325 static void s_cpsetup (int);
1326 static void s_cplocal (int);
1327 static void s_cprestore (int);
1328 static void s_cpreturn (int);
1329 static void s_dtprelword (int);
1330 static void s_dtpreldword (int);
1331 static void s_tprelword (int);
1332 static void s_tpreldword (int);
1333 static void s_gpvalue (int);
1334 static void s_gpword (int);
1335 static void s_gpdword (int);
1336 static void s_ehword (int);
1337 static void s_cpadd (int);
1338 static void s_insn (int);
1339 static void s_nan (int);
1340 static void s_module (int);
1341 static void s_mips_ent (int);
1342 static void s_mips_end (int);
1343 static void s_mips_frame (int);
1344 static void s_mips_mask (int reg_type);
1345 static void s_mips_stab (int);
1346 static void s_mips_weakext (int);
1347 static void s_mips_file (int);
1348 static void s_mips_loc (int);
1349 static bfd_boolean pic_need_relax (symbolS *, asection *);
1350 static int relaxed_branch_length (fragS *, asection *, int);
1351 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1352 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1353 static void file_mips_check_options (void);
1355 /* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1358 struct mips_cpu_info
1360 const char *name; /* CPU or ISA name. */
1361 int flags; /* MIPS_CPU_* flags. */
1362 int ase; /* Set of ASEs implemented by the CPU. */
1363 int isa; /* ISA level. */
1364 int cpu; /* CPU number (default CPU if ISA). */
1367 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1369 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1371 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1373 /* Command-line options. */
1374 const char *md_shortopts = "O::g::G:";
1378 OPTION_MARCH = OPTION_MD_BASE,
1410 OPTION_NO_SMARTMIPS,
1418 OPTION_NO_MICROMIPS,
1421 OPTION_COMPAT_ARCH_BASE,
1430 OPTION_M7000_HILO_FIX,
1431 OPTION_MNO_7000_HILO_FIX,
1435 OPTION_NO_FIX_RM7000,
1436 OPTION_FIX_LOONGSON2F_JUMP,
1437 OPTION_NO_FIX_LOONGSON2F_JUMP,
1438 OPTION_FIX_LOONGSON2F_NOP,
1439 OPTION_NO_FIX_LOONGSON2F_NOP,
1441 OPTION_NO_FIX_VR4120,
1443 OPTION_NO_FIX_VR4130,
1444 OPTION_FIX_CN63XXP1,
1445 OPTION_NO_FIX_CN63XXP1,
1452 OPTION_CONSTRUCT_FLOATS,
1453 OPTION_NO_CONSTRUCT_FLOATS,
1457 OPTION_RELAX_BRANCH,
1458 OPTION_NO_RELAX_BRANCH,
1467 OPTION_SINGLE_FLOAT,
1468 OPTION_DOUBLE_FLOAT,
1481 OPTION_MVXWORKS_PIC,
1484 OPTION_NO_ODD_SPREG,
1488 struct option md_longopts[] =
1490 /* Options which specify architecture. */
1491 {"march", required_argument, NULL, OPTION_MARCH},
1492 {"mtune", required_argument, NULL, OPTION_MTUNE},
1493 {"mips0", no_argument, NULL, OPTION_MIPS1},
1494 {"mips1", no_argument, NULL, OPTION_MIPS1},
1495 {"mips2", no_argument, NULL, OPTION_MIPS2},
1496 {"mips3", no_argument, NULL, OPTION_MIPS3},
1497 {"mips4", no_argument, NULL, OPTION_MIPS4},
1498 {"mips5", no_argument, NULL, OPTION_MIPS5},
1499 {"mips32", no_argument, NULL, OPTION_MIPS32},
1500 {"mips64", no_argument, NULL, OPTION_MIPS64},
1501 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1502 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1503 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1504 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1505 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1506 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1507 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1508 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1510 /* Options which specify Application Specific Extensions (ASEs). */
1511 {"mips16", no_argument, NULL, OPTION_MIPS16},
1512 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1513 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1514 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1515 {"mdmx", no_argument, NULL, OPTION_MDMX},
1516 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1517 {"mdsp", no_argument, NULL, OPTION_DSP},
1518 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1519 {"mmt", no_argument, NULL, OPTION_MT},
1520 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1521 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1522 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1523 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1524 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1525 {"meva", no_argument, NULL, OPTION_EVA},
1526 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1527 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1528 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1529 {"mmcu", no_argument, NULL, OPTION_MCU},
1530 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1531 {"mvirt", no_argument, NULL, OPTION_VIRT},
1532 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1533 {"mmsa", no_argument, NULL, OPTION_MSA},
1534 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1535 {"mxpa", no_argument, NULL, OPTION_XPA},
1536 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1538 /* Old-style architecture options. Don't add more of these. */
1539 {"m4650", no_argument, NULL, OPTION_M4650},
1540 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1541 {"m4010", no_argument, NULL, OPTION_M4010},
1542 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1543 {"m4100", no_argument, NULL, OPTION_M4100},
1544 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1545 {"m3900", no_argument, NULL, OPTION_M3900},
1546 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1548 /* Options which enable bug fixes. */
1549 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1550 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1551 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1552 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1553 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1554 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1555 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1556 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1557 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1558 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1559 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1560 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1561 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1562 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1563 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1564 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1565 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1567 /* Miscellaneous options. */
1568 {"trap", no_argument, NULL, OPTION_TRAP},
1569 {"no-break", no_argument, NULL, OPTION_TRAP},
1570 {"break", no_argument, NULL, OPTION_BREAK},
1571 {"no-trap", no_argument, NULL, OPTION_BREAK},
1572 {"EB", no_argument, NULL, OPTION_EB},
1573 {"EL", no_argument, NULL, OPTION_EL},
1574 {"mfp32", no_argument, NULL, OPTION_FP32},
1575 {"mgp32", no_argument, NULL, OPTION_GP32},
1576 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1577 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1578 {"mfp64", no_argument, NULL, OPTION_FP64},
1579 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1580 {"mgp64", no_argument, NULL, OPTION_GP64},
1581 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1582 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1583 {"minsn32", no_argument, NULL, OPTION_INSN32},
1584 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1585 {"mshared", no_argument, NULL, OPTION_MSHARED},
1586 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1587 {"msym32", no_argument, NULL, OPTION_MSYM32},
1588 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1589 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1590 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1591 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1592 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1593 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1594 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1596 /* Strictly speaking this next option is ELF specific,
1597 but we allow it for other ports as well in order to
1598 make testing easier. */
1599 {"32", no_argument, NULL, OPTION_32},
1601 /* ELF-specific options. */
1602 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1603 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1604 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1605 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1606 {"xgot", no_argument, NULL, OPTION_XGOT},
1607 {"mabi", required_argument, NULL, OPTION_MABI},
1608 {"n32", no_argument, NULL, OPTION_N32},
1609 {"64", no_argument, NULL, OPTION_64},
1610 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1611 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1612 {"mpdr", no_argument, NULL, OPTION_PDR},
1613 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1614 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1615 {"mnan", required_argument, NULL, OPTION_NAN},
1617 {NULL, no_argument, NULL, 0}
1619 size_t md_longopts_size = sizeof (md_longopts);
1621 /* Information about either an Application Specific Extension or an
1622 optional architecture feature that, for simplicity, we treat in the
1623 same way as an ASE. */
1626 /* The name of the ASE, used in both the command-line and .set options. */
1629 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1630 and 64-bit architectures, the flags here refer to the subset that
1631 is available on both. */
1634 /* The ASE_* flag used for instructions that are available on 64-bit
1635 architectures but that are not included in FLAGS. */
1636 unsigned int flags64;
1638 /* The command-line options that turn the ASE on and off. */
1642 /* The minimum required architecture revisions for MIPS32, MIPS64,
1643 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1646 int micromips32_rev;
1647 int micromips64_rev;
1649 /* The architecture where the ASE was removed or -1 if the extension has not
1654 /* A table of all supported ASEs. */
1655 static const struct mips_ase mips_ases[] = {
1656 { "dsp", ASE_DSP, ASE_DSP64,
1657 OPTION_DSP, OPTION_NO_DSP,
1661 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1662 OPTION_DSPR2, OPTION_NO_DSPR2,
1666 { "eva", ASE_EVA, 0,
1667 OPTION_EVA, OPTION_NO_EVA,
1671 { "mcu", ASE_MCU, 0,
1672 OPTION_MCU, OPTION_NO_MCU,
1676 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1677 { "mdmx", ASE_MDMX, 0,
1678 OPTION_MDMX, OPTION_NO_MDMX,
1682 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1683 { "mips3d", ASE_MIPS3D, 0,
1684 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1689 OPTION_MT, OPTION_NO_MT,
1693 { "smartmips", ASE_SMARTMIPS, 0,
1694 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1698 { "virt", ASE_VIRT, ASE_VIRT64,
1699 OPTION_VIRT, OPTION_NO_VIRT,
1703 { "msa", ASE_MSA, ASE_MSA64,
1704 OPTION_MSA, OPTION_NO_MSA,
1708 { "xpa", ASE_XPA, 0,
1709 OPTION_XPA, OPTION_NO_XPA,
1714 /* The set of ASEs that require -mfp64. */
1715 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1717 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1718 static const unsigned int mips_ase_groups[] = {
1724 The following pseudo-ops from the Kane and Heinrich MIPS book
1725 should be defined here, but are currently unsupported: .alias,
1726 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1728 The following pseudo-ops from the Kane and Heinrich MIPS book are
1729 specific to the type of debugging information being generated, and
1730 should be defined by the object format: .aent, .begin, .bend,
1731 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1734 The following pseudo-ops from the Kane and Heinrich MIPS book are
1735 not MIPS CPU specific, but are also not specific to the object file
1736 format. This file is probably the best place to define them, but
1737 they are not currently supported: .asm0, .endr, .lab, .struct. */
1739 static const pseudo_typeS mips_pseudo_table[] =
1741 /* MIPS specific pseudo-ops. */
1742 {"option", s_option, 0},
1743 {"set", s_mipsset, 0},
1744 {"rdata", s_change_sec, 'r'},
1745 {"sdata", s_change_sec, 's'},
1746 {"livereg", s_ignore, 0},
1747 {"abicalls", s_abicalls, 0},
1748 {"cpload", s_cpload, 0},
1749 {"cpsetup", s_cpsetup, 0},
1750 {"cplocal", s_cplocal, 0},
1751 {"cprestore", s_cprestore, 0},
1752 {"cpreturn", s_cpreturn, 0},
1753 {"dtprelword", s_dtprelword, 0},
1754 {"dtpreldword", s_dtpreldword, 0},
1755 {"tprelword", s_tprelword, 0},
1756 {"tpreldword", s_tpreldword, 0},
1757 {"gpvalue", s_gpvalue, 0},
1758 {"gpword", s_gpword, 0},
1759 {"gpdword", s_gpdword, 0},
1760 {"ehword", s_ehword, 0},
1761 {"cpadd", s_cpadd, 0},
1762 {"insn", s_insn, 0},
1764 {"module", s_module, 0},
1766 /* Relatively generic pseudo-ops that happen to be used on MIPS
1768 {"asciiz", stringer, 8 + 1},
1769 {"bss", s_change_sec, 'b'},
1771 {"half", s_cons, 1},
1772 {"dword", s_cons, 3},
1773 {"weakext", s_mips_weakext, 0},
1774 {"origin", s_org, 0},
1775 {"repeat", s_rept, 0},
1777 /* For MIPS this is non-standard, but we define it for consistency. */
1778 {"sbss", s_change_sec, 'B'},
1780 /* These pseudo-ops are defined in read.c, but must be overridden
1781 here for one reason or another. */
1782 {"align", s_align, 0},
1783 {"byte", s_cons, 0},
1784 {"data", s_change_sec, 'd'},
1785 {"double", s_float_cons, 'd'},
1786 {"float", s_float_cons, 'f'},
1787 {"globl", s_mips_globl, 0},
1788 {"global", s_mips_globl, 0},
1789 {"hword", s_cons, 1},
1791 {"long", s_cons, 2},
1792 {"octa", s_cons, 4},
1793 {"quad", s_cons, 3},
1794 {"section", s_change_section, 0},
1795 {"short", s_cons, 1},
1796 {"single", s_float_cons, 'f'},
1797 {"stabd", s_mips_stab, 'd'},
1798 {"stabn", s_mips_stab, 'n'},
1799 {"stabs", s_mips_stab, 's'},
1800 {"text", s_change_sec, 't'},
1801 {"word", s_cons, 2},
1803 { "extern", ecoff_directive_extern, 0},
1808 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1810 /* These pseudo-ops should be defined by the object file format.
1811 However, a.out doesn't support them, so we have versions here. */
1812 {"aent", s_mips_ent, 1},
1813 {"bgnb", s_ignore, 0},
1814 {"end", s_mips_end, 0},
1815 {"endb", s_ignore, 0},
1816 {"ent", s_mips_ent, 0},
1817 {"file", s_mips_file, 0},
1818 {"fmask", s_mips_mask, 'F'},
1819 {"frame", s_mips_frame, 0},
1820 {"loc", s_mips_loc, 0},
1821 {"mask", s_mips_mask, 'R'},
1822 {"verstamp", s_ignore, 0},
1826 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1827 purpose of the `.dc.a' internal pseudo-op. */
1830 mips_address_bytes (void)
1832 file_mips_check_options ();
1833 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1836 extern void pop_insert (const pseudo_typeS *);
1839 mips_pop_insert (void)
1841 pop_insert (mips_pseudo_table);
1842 if (! ECOFF_DEBUGGING)
1843 pop_insert (mips_nonecoff_pseudo_table);
1846 /* Symbols labelling the current insn. */
1848 struct insn_label_list
1850 struct insn_label_list *next;
1854 static struct insn_label_list *free_insn_labels;
1855 #define label_list tc_segment_info_data.labels
1857 static void mips_clear_insn_labels (void);
1858 static void mips_mark_labels (void);
1859 static void mips_compressed_mark_labels (void);
1862 mips_clear_insn_labels (void)
1864 struct insn_label_list **pl;
1865 segment_info_type *si;
1869 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1872 si = seg_info (now_seg);
1873 *pl = si->label_list;
1874 si->label_list = NULL;
1878 /* Mark instruction labels in MIPS16/microMIPS mode. */
1881 mips_mark_labels (void)
1883 if (HAVE_CODE_COMPRESSION)
1884 mips_compressed_mark_labels ();
1887 static char *expr_end;
1889 /* An expression in a macro instruction. This is set by mips_ip and
1890 mips16_ip and when populated is always an O_constant. */
1892 static expressionS imm_expr;
1894 /* The relocatable field in an instruction and the relocs associated
1895 with it. These variables are used for instructions like LUI and
1896 JAL as well as true offsets. They are also used for address
1897 operands in macros. */
1899 static expressionS offset_expr;
1900 static bfd_reloc_code_real_type offset_reloc[3]
1901 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1903 /* This is set to the resulting size of the instruction to be produced
1904 by mips16_ip if an explicit extension is used or by mips_ip if an
1905 explicit size is supplied. */
1907 static unsigned int forced_insn_length;
1909 /* True if we are assembling an instruction. All dot symbols defined during
1910 this time should be treated as code labels. */
1912 static bfd_boolean mips_assembling_insn;
1914 /* The pdr segment for per procedure frame/regmask info. Not used for
1917 static segT pdr_seg;
1919 /* The default target format to use. */
1921 #if defined (TE_FreeBSD)
1922 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1923 #elif defined (TE_TMIPS)
1924 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1926 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1930 mips_target_format (void)
1932 switch (OUTPUT_FLAVOR)
1934 case bfd_target_elf_flavour:
1936 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1937 return (target_big_endian
1938 ? "elf32-bigmips-vxworks"
1939 : "elf32-littlemips-vxworks");
1941 return (target_big_endian
1942 ? (HAVE_64BIT_OBJECTS
1943 ? ELF_TARGET ("elf64-", "big")
1945 ? ELF_TARGET ("elf32-n", "big")
1946 : ELF_TARGET ("elf32-", "big")))
1947 : (HAVE_64BIT_OBJECTS
1948 ? ELF_TARGET ("elf64-", "little")
1950 ? ELF_TARGET ("elf32-n", "little")
1951 : ELF_TARGET ("elf32-", "little"))));
1958 /* Return the ISA revision that is currently in use, or 0 if we are
1959 generating code for MIPS V or below. */
1964 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1967 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1970 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1973 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1976 /* microMIPS implies revision 2 or above. */
1977 if (mips_opts.micromips)
1980 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1986 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1989 mips_ase_mask (unsigned int flags)
1993 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1994 if (flags & mips_ase_groups[i])
1995 flags |= mips_ase_groups[i];
1999 /* Check whether the current ISA supports ASE. Issue a warning if
2003 mips_check_isa_supports_ase (const struct mips_ase *ase)
2007 static unsigned int warned_isa;
2008 static unsigned int warned_fp32;
2010 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2011 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2013 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2014 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2015 && (warned_isa & ase->flags) != ase->flags)
2017 warned_isa |= ase->flags;
2018 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2019 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2021 as_warn (_("the %d-bit %s architecture does not support the"
2022 " `%s' extension"), size, base, ase->name);
2024 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2025 ase->name, base, size, min_rev);
2027 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2028 && (warned_isa & ase->flags) != ase->flags)
2030 warned_isa |= ase->flags;
2031 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2032 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2033 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2034 ase->name, base, size, ase->rem_rev);
2037 if ((ase->flags & FP64_ASES)
2038 && mips_opts.fp != 64
2039 && (warned_fp32 & ase->flags) != ase->flags)
2041 warned_fp32 |= ase->flags;
2042 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2046 /* Check all enabled ASEs to see whether they are supported by the
2047 chosen architecture. */
2050 mips_check_isa_supports_ases (void)
2052 unsigned int i, mask;
2054 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2056 mask = mips_ase_mask (mips_ases[i].flags);
2057 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2058 mips_check_isa_supports_ase (&mips_ases[i]);
2062 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2063 that were affected. */
2066 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2067 bfd_boolean enabled_p)
2071 mask = mips_ase_mask (ase->flags);
2074 opts->ase |= ase->flags;
2078 /* Return the ASE called NAME, or null if none. */
2080 static const struct mips_ase *
2081 mips_lookup_ase (const char *name)
2085 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2086 if (strcmp (name, mips_ases[i].name) == 0)
2087 return &mips_ases[i];
2091 /* Return the length of a microMIPS instruction in bytes. If bits of
2092 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2093 otherwise it is a 32-bit instruction. */
2095 static inline unsigned int
2096 micromips_insn_length (const struct mips_opcode *mo)
2098 return (mo->mask >> 16) == 0 ? 2 : 4;
2101 /* Return the length of MIPS16 instruction OPCODE. */
2103 static inline unsigned int
2104 mips16_opcode_length (unsigned long opcode)
2106 return (opcode >> 16) == 0 ? 2 : 4;
2109 /* Return the length of instruction INSN. */
2111 static inline unsigned int
2112 insn_length (const struct mips_cl_insn *insn)
2114 if (mips_opts.micromips)
2115 return micromips_insn_length (insn->insn_mo);
2116 else if (mips_opts.mips16)
2117 return mips16_opcode_length (insn->insn_opcode);
2122 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2125 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2130 insn->insn_opcode = mo->match;
2133 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2134 insn->fixp[i] = NULL;
2135 insn->fixed_p = (mips_opts.noreorder > 0);
2136 insn->noreorder_p = (mips_opts.noreorder > 0);
2137 insn->mips16_absolute_jump_p = 0;
2138 insn->complete_p = 0;
2139 insn->cleared_p = 0;
2142 /* Get a list of all the operands in INSN. */
2144 static const struct mips_operand_array *
2145 insn_operands (const struct mips_cl_insn *insn)
2147 if (insn->insn_mo >= &mips_opcodes[0]
2148 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2149 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2151 if (insn->insn_mo >= &mips16_opcodes[0]
2152 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2153 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2155 if (insn->insn_mo >= µmips_opcodes[0]
2156 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2157 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2162 /* Get a description of operand OPNO of INSN. */
2164 static const struct mips_operand *
2165 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2167 const struct mips_operand_array *operands;
2169 operands = insn_operands (insn);
2170 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2172 return operands->operand[opno];
2175 /* Install UVAL as the value of OPERAND in INSN. */
2178 insn_insert_operand (struct mips_cl_insn *insn,
2179 const struct mips_operand *operand, unsigned int uval)
2181 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2184 /* Extract the value of OPERAND from INSN. */
2186 static inline unsigned
2187 insn_extract_operand (const struct mips_cl_insn *insn,
2188 const struct mips_operand *operand)
2190 return mips_extract_operand (operand, insn->insn_opcode);
2193 /* Record the current MIPS16/microMIPS mode in now_seg. */
2196 mips_record_compressed_mode (void)
2198 segment_info_type *si;
2200 si = seg_info (now_seg);
2201 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2202 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2203 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2204 si->tc_segment_info_data.micromips = mips_opts.micromips;
2207 /* Read a standard MIPS instruction from BUF. */
2209 static unsigned long
2210 read_insn (char *buf)
2212 if (target_big_endian)
2213 return bfd_getb32 ((bfd_byte *) buf);
2215 return bfd_getl32 ((bfd_byte *) buf);
2218 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2222 write_insn (char *buf, unsigned int insn)
2224 md_number_to_chars (buf, insn, 4);
2228 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2229 has length LENGTH. */
2231 static unsigned long
2232 read_compressed_insn (char *buf, unsigned int length)
2238 for (i = 0; i < length; i += 2)
2241 if (target_big_endian)
2242 insn |= bfd_getb16 ((char *) buf);
2244 insn |= bfd_getl16 ((char *) buf);
2250 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2251 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2254 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2258 for (i = 0; i < length; i += 2)
2259 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2260 return buf + length;
2263 /* Install INSN at the location specified by its "frag" and "where" fields. */
2266 install_insn (const struct mips_cl_insn *insn)
2268 char *f = insn->frag->fr_literal + insn->where;
2269 if (HAVE_CODE_COMPRESSION)
2270 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2272 write_insn (f, insn->insn_opcode);
2273 mips_record_compressed_mode ();
2276 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2277 and install the opcode in the new location. */
2280 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2285 insn->where = where;
2286 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2287 if (insn->fixp[i] != NULL)
2289 insn->fixp[i]->fx_frag = frag;
2290 insn->fixp[i]->fx_where = where;
2292 install_insn (insn);
2295 /* Add INSN to the end of the output. */
2298 add_fixed_insn (struct mips_cl_insn *insn)
2300 char *f = frag_more (insn_length (insn));
2301 move_insn (insn, frag_now, f - frag_now->fr_literal);
2304 /* Start a variant frag and move INSN to the start of the variant part,
2305 marking it as fixed. The other arguments are as for frag_var. */
2308 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2309 relax_substateT subtype, symbolS *symbol, offsetT offset)
2311 frag_grow (max_chars);
2312 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2314 frag_var (rs_machine_dependent, max_chars, var,
2315 subtype, symbol, offset, NULL);
2318 /* Insert N copies of INSN into the history buffer, starting at
2319 position FIRST. Neither FIRST nor N need to be clipped. */
2322 insert_into_history (unsigned int first, unsigned int n,
2323 const struct mips_cl_insn *insn)
2325 if (mips_relax.sequence != 2)
2329 for (i = ARRAY_SIZE (history); i-- > first;)
2331 history[i] = history[i - n];
2337 /* Clear the error in insn_error. */
2340 clear_insn_error (void)
2342 memset (&insn_error, 0, sizeof (insn_error));
2345 /* Possibly record error message MSG for the current instruction.
2346 If the error is about a particular argument, ARGNUM is the 1-based
2347 number of that argument, otherwise it is 0. FORMAT is the format
2348 of MSG. Return true if MSG was used, false if the current message
2352 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2357 /* Give priority to errors against specific arguments, and to
2358 the first whole-instruction message. */
2364 /* Keep insn_error if it is against a later argument. */
2365 if (argnum < insn_error.min_argnum)
2368 /* If both errors are against the same argument but are different,
2369 give up on reporting a specific error for this argument.
2370 See the comment about mips_insn_error for details. */
2371 if (argnum == insn_error.min_argnum
2373 && strcmp (insn_error.msg, msg) != 0)
2376 insn_error.min_argnum += 1;
2380 insn_error.min_argnum = argnum;
2381 insn_error.format = format;
2382 insn_error.msg = msg;
2386 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2387 as for set_insn_error_format. */
2390 set_insn_error (int argnum, const char *msg)
2392 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2395 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2396 as for set_insn_error_format. */
2399 set_insn_error_i (int argnum, const char *msg, int i)
2401 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2405 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2406 are as for set_insn_error_format. */
2409 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2411 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2413 insn_error.u.ss[0] = s1;
2414 insn_error.u.ss[1] = s2;
2418 /* Report the error in insn_error, which is against assembly code STR. */
2421 report_insn_error (const char *str)
2423 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2425 switch (insn_error.format)
2432 as_bad (msg, insn_error.u.i, str);
2436 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2440 free ((char *) msg);
2443 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2444 the idea is to make it obvious at a glance that each errata is
2448 init_vr4120_conflicts (void)
2450 #define CONFLICT(FIRST, SECOND) \
2451 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2453 /* Errata 21 - [D]DIV[U] after [D]MACC */
2454 CONFLICT (MACC, DIV);
2455 CONFLICT (DMACC, DIV);
2457 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2458 CONFLICT (DMULT, DMULT);
2459 CONFLICT (DMULT, DMACC);
2460 CONFLICT (DMACC, DMULT);
2461 CONFLICT (DMACC, DMACC);
2463 /* Errata 24 - MT{LO,HI} after [D]MACC */
2464 CONFLICT (MACC, MTHILO);
2465 CONFLICT (DMACC, MTHILO);
2467 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2468 instruction is executed immediately after a MACC or DMACC
2469 instruction, the result of [either instruction] is incorrect." */
2470 CONFLICT (MACC, MULT);
2471 CONFLICT (MACC, DMULT);
2472 CONFLICT (DMACC, MULT);
2473 CONFLICT (DMACC, DMULT);
2475 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2476 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2477 DDIV or DDIVU instruction, the result of the MACC or
2478 DMACC instruction is incorrect.". */
2479 CONFLICT (DMULT, MACC);
2480 CONFLICT (DMULT, DMACC);
2481 CONFLICT (DIV, MACC);
2482 CONFLICT (DIV, DMACC);
2492 #define RNUM_MASK 0x00000ff
2493 #define RTYPE_MASK 0x0ffff00
2494 #define RTYPE_NUM 0x0000100
2495 #define RTYPE_FPU 0x0000200
2496 #define RTYPE_FCC 0x0000400
2497 #define RTYPE_VEC 0x0000800
2498 #define RTYPE_GP 0x0001000
2499 #define RTYPE_CP0 0x0002000
2500 #define RTYPE_PC 0x0004000
2501 #define RTYPE_ACC 0x0008000
2502 #define RTYPE_CCC 0x0010000
2503 #define RTYPE_VI 0x0020000
2504 #define RTYPE_VF 0x0040000
2505 #define RTYPE_R5900_I 0x0080000
2506 #define RTYPE_R5900_Q 0x0100000
2507 #define RTYPE_R5900_R 0x0200000
2508 #define RTYPE_R5900_ACC 0x0400000
2509 #define RTYPE_MSA 0x0800000
2510 #define RWARN 0x8000000
2512 #define GENERIC_REGISTER_NUMBERS \
2513 {"$0", RTYPE_NUM | 0}, \
2514 {"$1", RTYPE_NUM | 1}, \
2515 {"$2", RTYPE_NUM | 2}, \
2516 {"$3", RTYPE_NUM | 3}, \
2517 {"$4", RTYPE_NUM | 4}, \
2518 {"$5", RTYPE_NUM | 5}, \
2519 {"$6", RTYPE_NUM | 6}, \
2520 {"$7", RTYPE_NUM | 7}, \
2521 {"$8", RTYPE_NUM | 8}, \
2522 {"$9", RTYPE_NUM | 9}, \
2523 {"$10", RTYPE_NUM | 10}, \
2524 {"$11", RTYPE_NUM | 11}, \
2525 {"$12", RTYPE_NUM | 12}, \
2526 {"$13", RTYPE_NUM | 13}, \
2527 {"$14", RTYPE_NUM | 14}, \
2528 {"$15", RTYPE_NUM | 15}, \
2529 {"$16", RTYPE_NUM | 16}, \
2530 {"$17", RTYPE_NUM | 17}, \
2531 {"$18", RTYPE_NUM | 18}, \
2532 {"$19", RTYPE_NUM | 19}, \
2533 {"$20", RTYPE_NUM | 20}, \
2534 {"$21", RTYPE_NUM | 21}, \
2535 {"$22", RTYPE_NUM | 22}, \
2536 {"$23", RTYPE_NUM | 23}, \
2537 {"$24", RTYPE_NUM | 24}, \
2538 {"$25", RTYPE_NUM | 25}, \
2539 {"$26", RTYPE_NUM | 26}, \
2540 {"$27", RTYPE_NUM | 27}, \
2541 {"$28", RTYPE_NUM | 28}, \
2542 {"$29", RTYPE_NUM | 29}, \
2543 {"$30", RTYPE_NUM | 30}, \
2544 {"$31", RTYPE_NUM | 31}
2546 #define FPU_REGISTER_NAMES \
2547 {"$f0", RTYPE_FPU | 0}, \
2548 {"$f1", RTYPE_FPU | 1}, \
2549 {"$f2", RTYPE_FPU | 2}, \
2550 {"$f3", RTYPE_FPU | 3}, \
2551 {"$f4", RTYPE_FPU | 4}, \
2552 {"$f5", RTYPE_FPU | 5}, \
2553 {"$f6", RTYPE_FPU | 6}, \
2554 {"$f7", RTYPE_FPU | 7}, \
2555 {"$f8", RTYPE_FPU | 8}, \
2556 {"$f9", RTYPE_FPU | 9}, \
2557 {"$f10", RTYPE_FPU | 10}, \
2558 {"$f11", RTYPE_FPU | 11}, \
2559 {"$f12", RTYPE_FPU | 12}, \
2560 {"$f13", RTYPE_FPU | 13}, \
2561 {"$f14", RTYPE_FPU | 14}, \
2562 {"$f15", RTYPE_FPU | 15}, \
2563 {"$f16", RTYPE_FPU | 16}, \
2564 {"$f17", RTYPE_FPU | 17}, \
2565 {"$f18", RTYPE_FPU | 18}, \
2566 {"$f19", RTYPE_FPU | 19}, \
2567 {"$f20", RTYPE_FPU | 20}, \
2568 {"$f21", RTYPE_FPU | 21}, \
2569 {"$f22", RTYPE_FPU | 22}, \
2570 {"$f23", RTYPE_FPU | 23}, \
2571 {"$f24", RTYPE_FPU | 24}, \
2572 {"$f25", RTYPE_FPU | 25}, \
2573 {"$f26", RTYPE_FPU | 26}, \
2574 {"$f27", RTYPE_FPU | 27}, \
2575 {"$f28", RTYPE_FPU | 28}, \
2576 {"$f29", RTYPE_FPU | 29}, \
2577 {"$f30", RTYPE_FPU | 30}, \
2578 {"$f31", RTYPE_FPU | 31}
2580 #define FPU_CONDITION_CODE_NAMES \
2581 {"$fcc0", RTYPE_FCC | 0}, \
2582 {"$fcc1", RTYPE_FCC | 1}, \
2583 {"$fcc2", RTYPE_FCC | 2}, \
2584 {"$fcc3", RTYPE_FCC | 3}, \
2585 {"$fcc4", RTYPE_FCC | 4}, \
2586 {"$fcc5", RTYPE_FCC | 5}, \
2587 {"$fcc6", RTYPE_FCC | 6}, \
2588 {"$fcc7", RTYPE_FCC | 7}
2590 #define COPROC_CONDITION_CODE_NAMES \
2591 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2592 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2593 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2594 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2595 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2596 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2597 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2598 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2600 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2601 {"$a4", RTYPE_GP | 8}, \
2602 {"$a5", RTYPE_GP | 9}, \
2603 {"$a6", RTYPE_GP | 10}, \
2604 {"$a7", RTYPE_GP | 11}, \
2605 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2606 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2607 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2608 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2609 {"$t0", RTYPE_GP | 12}, \
2610 {"$t1", RTYPE_GP | 13}, \
2611 {"$t2", RTYPE_GP | 14}, \
2612 {"$t3", RTYPE_GP | 15}
2614 #define O32_SYMBOLIC_REGISTER_NAMES \
2615 {"$t0", RTYPE_GP | 8}, \
2616 {"$t1", RTYPE_GP | 9}, \
2617 {"$t2", RTYPE_GP | 10}, \
2618 {"$t3", RTYPE_GP | 11}, \
2619 {"$t4", RTYPE_GP | 12}, \
2620 {"$t5", RTYPE_GP | 13}, \
2621 {"$t6", RTYPE_GP | 14}, \
2622 {"$t7", RTYPE_GP | 15}, \
2623 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2624 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2625 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2626 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2628 /* Remaining symbolic register names */
2629 #define SYMBOLIC_REGISTER_NAMES \
2630 {"$zero", RTYPE_GP | 0}, \
2631 {"$at", RTYPE_GP | 1}, \
2632 {"$AT", RTYPE_GP | 1}, \
2633 {"$v0", RTYPE_GP | 2}, \
2634 {"$v1", RTYPE_GP | 3}, \
2635 {"$a0", RTYPE_GP | 4}, \
2636 {"$a1", RTYPE_GP | 5}, \
2637 {"$a2", RTYPE_GP | 6}, \
2638 {"$a3", RTYPE_GP | 7}, \
2639 {"$s0", RTYPE_GP | 16}, \
2640 {"$s1", RTYPE_GP | 17}, \
2641 {"$s2", RTYPE_GP | 18}, \
2642 {"$s3", RTYPE_GP | 19}, \
2643 {"$s4", RTYPE_GP | 20}, \
2644 {"$s5", RTYPE_GP | 21}, \
2645 {"$s6", RTYPE_GP | 22}, \
2646 {"$s7", RTYPE_GP | 23}, \
2647 {"$t8", RTYPE_GP | 24}, \
2648 {"$t9", RTYPE_GP | 25}, \
2649 {"$k0", RTYPE_GP | 26}, \
2650 {"$kt0", RTYPE_GP | 26}, \
2651 {"$k1", RTYPE_GP | 27}, \
2652 {"$kt1", RTYPE_GP | 27}, \
2653 {"$gp", RTYPE_GP | 28}, \
2654 {"$sp", RTYPE_GP | 29}, \
2655 {"$s8", RTYPE_GP | 30}, \
2656 {"$fp", RTYPE_GP | 30}, \
2657 {"$ra", RTYPE_GP | 31}
2659 #define MIPS16_SPECIAL_REGISTER_NAMES \
2660 {"$pc", RTYPE_PC | 0}
2662 #define MDMX_VECTOR_REGISTER_NAMES \
2663 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2664 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2665 {"$v2", RTYPE_VEC | 2}, \
2666 {"$v3", RTYPE_VEC | 3}, \
2667 {"$v4", RTYPE_VEC | 4}, \
2668 {"$v5", RTYPE_VEC | 5}, \
2669 {"$v6", RTYPE_VEC | 6}, \
2670 {"$v7", RTYPE_VEC | 7}, \
2671 {"$v8", RTYPE_VEC | 8}, \
2672 {"$v9", RTYPE_VEC | 9}, \
2673 {"$v10", RTYPE_VEC | 10}, \
2674 {"$v11", RTYPE_VEC | 11}, \
2675 {"$v12", RTYPE_VEC | 12}, \
2676 {"$v13", RTYPE_VEC | 13}, \
2677 {"$v14", RTYPE_VEC | 14}, \
2678 {"$v15", RTYPE_VEC | 15}, \
2679 {"$v16", RTYPE_VEC | 16}, \
2680 {"$v17", RTYPE_VEC | 17}, \
2681 {"$v18", RTYPE_VEC | 18}, \
2682 {"$v19", RTYPE_VEC | 19}, \
2683 {"$v20", RTYPE_VEC | 20}, \
2684 {"$v21", RTYPE_VEC | 21}, \
2685 {"$v22", RTYPE_VEC | 22}, \
2686 {"$v23", RTYPE_VEC | 23}, \
2687 {"$v24", RTYPE_VEC | 24}, \
2688 {"$v25", RTYPE_VEC | 25}, \
2689 {"$v26", RTYPE_VEC | 26}, \
2690 {"$v27", RTYPE_VEC | 27}, \
2691 {"$v28", RTYPE_VEC | 28}, \
2692 {"$v29", RTYPE_VEC | 29}, \
2693 {"$v30", RTYPE_VEC | 30}, \
2694 {"$v31", RTYPE_VEC | 31}
2696 #define R5900_I_NAMES \
2697 {"$I", RTYPE_R5900_I | 0}
2699 #define R5900_Q_NAMES \
2700 {"$Q", RTYPE_R5900_Q | 0}
2702 #define R5900_R_NAMES \
2703 {"$R", RTYPE_R5900_R | 0}
2705 #define R5900_ACC_NAMES \
2706 {"$ACC", RTYPE_R5900_ACC | 0 }
2708 #define MIPS_DSP_ACCUMULATOR_NAMES \
2709 {"$ac0", RTYPE_ACC | 0}, \
2710 {"$ac1", RTYPE_ACC | 1}, \
2711 {"$ac2", RTYPE_ACC | 2}, \
2712 {"$ac3", RTYPE_ACC | 3}
2714 static const struct regname reg_names[] = {
2715 GENERIC_REGISTER_NUMBERS,
2717 FPU_CONDITION_CODE_NAMES,
2718 COPROC_CONDITION_CODE_NAMES,
2720 /* The $txx registers depends on the abi,
2721 these will be added later into the symbol table from
2722 one of the tables below once mips_abi is set after
2723 parsing of arguments from the command line. */
2724 SYMBOLIC_REGISTER_NAMES,
2726 MIPS16_SPECIAL_REGISTER_NAMES,
2727 MDMX_VECTOR_REGISTER_NAMES,
2732 MIPS_DSP_ACCUMULATOR_NAMES,
2736 static const struct regname reg_names_o32[] = {
2737 O32_SYMBOLIC_REGISTER_NAMES,
2741 static const struct regname reg_names_n32n64[] = {
2742 N32N64_SYMBOLIC_REGISTER_NAMES,
2746 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2747 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2748 of these register symbols, return the associated vector register,
2749 otherwise return SYMVAL itself. */
2752 mips_prefer_vec_regno (unsigned int symval)
2754 if ((symval & -2) == (RTYPE_GP | 2))
2755 return RTYPE_VEC | (symval & 1);
2759 /* Return true if string [S, E) is a valid register name, storing its
2760 symbol value in *SYMVAL_PTR if so. */
2763 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2768 /* Terminate name. */
2772 /* Look up the name. */
2773 symbol = symbol_find (s);
2776 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2779 *symval_ptr = S_GET_VALUE (symbol);
2783 /* Return true if the string at *SPTR is a valid register name. Allow it
2784 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2787 When returning true, move *SPTR past the register, store the
2788 register's symbol value in *SYMVAL_PTR and the channel mask in
2789 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2790 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2791 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2794 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2795 unsigned int *channels_ptr)
2799 unsigned int channels, symval, bit;
2801 /* Find end of name. */
2803 if (is_name_beginner (*e))
2805 while (is_part_of_name (*e))
2809 if (!mips_parse_register_1 (s, e, &symval))
2814 /* Eat characters from the end of the string that are valid
2815 channel suffixes. The preceding register must be $ACC or
2816 end with a digit, so there is no ambiguity. */
2819 for (q = "wzyx"; *q; q++, bit <<= 1)
2820 if (m > s && m[-1] == *q)
2827 || !mips_parse_register_1 (s, m, &symval)
2828 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2833 *symval_ptr = symval;
2835 *channels_ptr = channels;
2839 /* Check if SPTR points at a valid register specifier according to TYPES.
2840 If so, then return 1, advance S to consume the specifier and store
2841 the register's number in REGNOP, otherwise return 0. */
2844 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2848 if (mips_parse_register (s, ®no, NULL))
2850 if (types & RTYPE_VEC)
2851 regno = mips_prefer_vec_regno (regno);
2860 as_warn (_("unrecognized register name `%s'"), *s);
2865 return regno <= RNUM_MASK;
2868 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2869 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2872 mips_parse_vu0_channels (char *s, unsigned int *channels)
2877 for (i = 0; i < 4; i++)
2878 if (*s == "xyzw"[i])
2880 *channels |= 1 << (3 - i);
2886 /* Token types for parsed operand lists. */
2887 enum mips_operand_token_type {
2888 /* A plain register, e.g. $f2. */
2891 /* A 4-bit XYZW channel mask. */
2894 /* A constant vector index, e.g. [1]. */
2897 /* A register vector index, e.g. [$2]. */
2900 /* A continuous range of registers, e.g. $s0-$s4. */
2903 /* A (possibly relocated) expression. */
2906 /* A floating-point value. */
2909 /* A single character. This can be '(', ')' or ',', but '(' only appears
2913 /* A doubled character, either "--" or "++". */
2916 /* The end of the operand list. */
2920 /* A parsed operand token. */
2921 struct mips_operand_token
2923 /* The type of token. */
2924 enum mips_operand_token_type type;
2927 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2930 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2931 unsigned int channels;
2933 /* The integer value of an OT_INTEGER_INDEX. */
2936 /* The two register symbol values involved in an OT_REG_RANGE. */
2938 unsigned int regno1;
2939 unsigned int regno2;
2942 /* The value of an OT_INTEGER. The value is represented as an
2943 expression and the relocation operators that were applied to
2944 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2945 relocation operators were used. */
2948 bfd_reloc_code_real_type relocs[3];
2951 /* The binary data for an OT_FLOAT constant, and the number of bytes
2954 unsigned char data[8];
2958 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2963 /* An obstack used to construct lists of mips_operand_tokens. */
2964 static struct obstack mips_operand_tokens;
2966 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2969 mips_add_token (struct mips_operand_token *token,
2970 enum mips_operand_token_type type)
2973 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2976 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2977 and OT_REG tokens for them if so, and return a pointer to the first
2978 unconsumed character. Return null otherwise. */
2981 mips_parse_base_start (char *s)
2983 struct mips_operand_token token;
2984 unsigned int regno, channels;
2985 bfd_boolean decrement_p;
2991 SKIP_SPACE_TABS (s);
2993 /* Only match "--" as part of a base expression. In other contexts "--X"
2994 is a double negative. */
2995 decrement_p = (s[0] == '-' && s[1] == '-');
2999 SKIP_SPACE_TABS (s);
3002 /* Allow a channel specifier because that leads to better error messages
3003 than treating something like "$vf0x++" as an expression. */
3004 if (!mips_parse_register (&s, ®no, &channels))
3008 mips_add_token (&token, OT_CHAR);
3013 mips_add_token (&token, OT_DOUBLE_CHAR);
3016 token.u.regno = regno;
3017 mips_add_token (&token, OT_REG);
3021 token.u.channels = channels;
3022 mips_add_token (&token, OT_CHANNELS);
3025 /* For consistency, only match "++" as part of base expressions too. */
3026 SKIP_SPACE_TABS (s);
3027 if (s[0] == '+' && s[1] == '+')
3031 mips_add_token (&token, OT_DOUBLE_CHAR);
3037 /* Parse one or more tokens from S. Return a pointer to the first
3038 unconsumed character on success. Return null if an error was found
3039 and store the error text in insn_error. FLOAT_FORMAT is as for
3040 mips_parse_arguments. */
3043 mips_parse_argument_token (char *s, char float_format)
3045 char *end, *save_in, *err;
3046 unsigned int regno1, regno2, channels;
3047 struct mips_operand_token token;
3049 /* First look for "($reg", since we want to treat that as an
3050 OT_CHAR and OT_REG rather than an expression. */
3051 end = mips_parse_base_start (s);
3055 /* Handle other characters that end up as OT_CHARs. */
3056 if (*s == ')' || *s == ',')
3059 mips_add_token (&token, OT_CHAR);
3064 /* Handle tokens that start with a register. */
3065 if (mips_parse_register (&s, ®no1, &channels))
3069 /* A register and a VU0 channel suffix. */
3070 token.u.regno = regno1;
3071 mips_add_token (&token, OT_REG);
3073 token.u.channels = channels;
3074 mips_add_token (&token, OT_CHANNELS);
3078 SKIP_SPACE_TABS (s);
3081 /* A register range. */
3083 SKIP_SPACE_TABS (s);
3084 if (!mips_parse_register (&s, ®no2, NULL))
3086 set_insn_error (0, _("invalid register range"));
3090 token.u.reg_range.regno1 = regno1;
3091 token.u.reg_range.regno2 = regno2;
3092 mips_add_token (&token, OT_REG_RANGE);
3096 /* Add the register itself. */
3097 token.u.regno = regno1;
3098 mips_add_token (&token, OT_REG);
3100 /* Check for a vector index. */
3104 SKIP_SPACE_TABS (s);
3105 if (mips_parse_register (&s, &token.u.regno, NULL))
3106 mips_add_token (&token, OT_REG_INDEX);
3109 expressionS element;
3111 my_getExpression (&element, s);
3112 if (element.X_op != O_constant)
3114 set_insn_error (0, _("vector element must be constant"));
3118 token.u.index = element.X_add_number;
3119 mips_add_token (&token, OT_INTEGER_INDEX);
3121 SKIP_SPACE_TABS (s);
3124 set_insn_error (0, _("missing `]'"));
3134 /* First try to treat expressions as floats. */
3135 save_in = input_line_pointer;
3136 input_line_pointer = s;
3137 err = md_atof (float_format, (char *) token.u.flt.data,
3138 &token.u.flt.length);
3139 end = input_line_pointer;
3140 input_line_pointer = save_in;
3143 set_insn_error (0, err);
3148 mips_add_token (&token, OT_FLOAT);
3153 /* Treat everything else as an integer expression. */
3154 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3155 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3156 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3157 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3159 mips_add_token (&token, OT_INTEGER);
3163 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3164 if expressions should be treated as 32-bit floating-point constants,
3165 'd' if they should be treated as 64-bit floating-point constants,
3166 or 0 if they should be treated as integer expressions (the usual case).
3168 Return a list of tokens on success, otherwise return 0. The caller
3169 must obstack_free the list after use. */
3171 static struct mips_operand_token *
3172 mips_parse_arguments (char *s, char float_format)
3174 struct mips_operand_token token;
3176 SKIP_SPACE_TABS (s);
3179 s = mips_parse_argument_token (s, float_format);
3182 obstack_free (&mips_operand_tokens,
3183 obstack_finish (&mips_operand_tokens));
3186 SKIP_SPACE_TABS (s);
3188 mips_add_token (&token, OT_END);
3189 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3192 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3193 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3196 is_opcode_valid (const struct mips_opcode *mo)
3198 int isa = mips_opts.isa;
3199 int ase = mips_opts.ase;
3203 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3204 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3205 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3206 ase |= mips_ases[i].flags64;
3208 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3211 /* Check whether the instruction or macro requires single-precision or
3212 double-precision floating-point support. Note that this information is
3213 stored differently in the opcode table for insns and macros. */
3214 if (mo->pinfo == INSN_MACRO)
3216 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3217 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3221 fp_s = mo->pinfo & FP_S;
3222 fp_d = mo->pinfo & FP_D;
3225 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3228 if (fp_s && mips_opts.soft_float)
3234 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3235 selected ISA and architecture. */
3238 is_opcode_valid_16 (const struct mips_opcode *mo)
3240 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3243 /* Return TRUE if the size of the microMIPS opcode MO matches one
3244 explicitly requested. Always TRUE in the standard MIPS mode. */
3247 is_size_valid (const struct mips_opcode *mo)
3249 if (!mips_opts.micromips)
3252 if (mips_opts.insn32)
3254 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3256 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3259 if (!forced_insn_length)
3261 if (mo->pinfo == INSN_MACRO)
3263 return forced_insn_length == micromips_insn_length (mo);
3266 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3267 of the preceding instruction. Always TRUE in the standard MIPS mode.
3269 We don't accept macros in 16-bit delay slots to avoid a case where
3270 a macro expansion fails because it relies on a preceding 32-bit real
3271 instruction to have matched and does not handle the operands correctly.
3272 The only macros that may expand to 16-bit instructions are JAL that
3273 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3274 and BGT (that likewise cannot be placed in a delay slot) that decay to
3275 a NOP. In all these cases the macros precede any corresponding real
3276 instruction definitions in the opcode table, so they will match in the
3277 second pass where the size of the delay slot is ignored and therefore
3278 produce correct code. */
3281 is_delay_slot_valid (const struct mips_opcode *mo)
3283 if (!mips_opts.micromips)
3286 if (mo->pinfo == INSN_MACRO)
3287 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3288 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3289 && micromips_insn_length (mo) != 4)
3291 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3292 && micromips_insn_length (mo) != 2)
3298 /* For consistency checking, verify that all bits of OPCODE are specified
3299 either by the match/mask part of the instruction definition, or by the
3300 operand list. Also build up a list of operands in OPERANDS.
3302 INSN_BITS says which bits of the instruction are significant.
3303 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3304 provides the mips_operand description of each operand. DECODE_OPERAND
3305 is null for MIPS16 instructions. */
3308 validate_mips_insn (const struct mips_opcode *opcode,
3309 unsigned long insn_bits,
3310 const struct mips_operand *(*decode_operand) (const char *),
3311 struct mips_operand_array *operands)
3314 unsigned long used_bits, doubled, undefined, opno, mask;
3315 const struct mips_operand *operand;
3317 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3318 if ((mask & opcode->match) != opcode->match)
3320 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3321 opcode->name, opcode->args);
3326 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3327 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3328 for (s = opcode->args; *s; ++s)
3341 if (!decode_operand)
3342 operand = decode_mips16_operand (*s, FALSE);
3344 operand = decode_operand (s);
3345 if (!operand && opcode->pinfo != INSN_MACRO)
3347 as_bad (_("internal: unknown operand type: %s %s"),
3348 opcode->name, opcode->args);
3351 gas_assert (opno < MAX_OPERANDS);
3352 operands->operand[opno] = operand;
3353 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3355 used_bits = mips_insert_operand (operand, used_bits, -1);
3356 if (operand->type == OP_MDMX_IMM_REG)
3357 /* Bit 5 is the format selector (OB vs QH). The opcode table
3358 has separate entries for each format. */
3359 used_bits &= ~(1 << (operand->lsb + 5));
3360 if (operand->type == OP_ENTRY_EXIT_LIST)
3361 used_bits &= ~(mask & 0x700);
3363 /* Skip prefix characters. */
3364 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3369 doubled = used_bits & mask & insn_bits;
3372 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3373 " %s %s"), doubled, opcode->name, opcode->args);
3377 undefined = ~used_bits & insn_bits;
3378 if (opcode->pinfo != INSN_MACRO && undefined)
3380 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3381 undefined, opcode->name, opcode->args);
3384 used_bits &= ~insn_bits;
3387 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3388 used_bits, opcode->name, opcode->args);
3394 /* The MIPS16 version of validate_mips_insn. */
3397 validate_mips16_insn (const struct mips_opcode *opcode,
3398 struct mips_operand_array *operands)
3400 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3402 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3403 instruction. Use TMP to describe the full instruction. */
3404 struct mips_opcode tmp;
3409 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3411 return validate_mips_insn (opcode, 0xffff, 0, operands);
3414 /* The microMIPS version of validate_mips_insn. */
3417 validate_micromips_insn (const struct mips_opcode *opc,
3418 struct mips_operand_array *operands)
3420 unsigned long insn_bits;
3421 unsigned long major;
3422 unsigned int length;
3424 if (opc->pinfo == INSN_MACRO)
3425 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3428 length = micromips_insn_length (opc);
3429 if (length != 2 && length != 4)
3431 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3432 "%s %s"), length, opc->name, opc->args);
3435 major = opc->match >> (10 + 8 * (length - 2));
3436 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3437 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3439 as_bad (_("internal error: bad microMIPS opcode "
3440 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3444 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3445 insn_bits = 1 << 4 * length;
3446 insn_bits <<= 4 * length;
3448 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3452 /* This function is called once, at assembler startup time. It should set up
3453 all the tables, etc. that the MD part of the assembler will need. */
3458 const char *retval = NULL;
3462 if (mips_pic != NO_PIC)
3464 if (g_switch_seen && g_switch_value != 0)
3465 as_bad (_("-G may not be used in position-independent code"));
3468 else if (mips_abicalls)
3470 if (g_switch_seen && g_switch_value != 0)
3471 as_bad (_("-G may not be used with abicalls"));
3475 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3476 as_warn (_("could not set architecture and machine"));
3478 op_hash = hash_new ();
3480 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3481 for (i = 0; i < NUMOPCODES;)
3483 const char *name = mips_opcodes[i].name;
3485 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3488 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3489 mips_opcodes[i].name, retval);
3490 /* Probably a memory allocation problem? Give up now. */
3491 as_fatal (_("broken assembler, no assembly attempted"));
3495 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3496 decode_mips_operand, &mips_operands[i]))
3498 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3500 create_insn (&nop_insn, mips_opcodes + i);
3501 if (mips_fix_loongson2f_nop)
3502 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3503 nop_insn.fixed_p = 1;
3507 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3510 mips16_op_hash = hash_new ();
3511 mips16_operands = XCNEWVEC (struct mips_operand_array,
3512 bfd_mips16_num_opcodes);
3515 while (i < bfd_mips16_num_opcodes)
3517 const char *name = mips16_opcodes[i].name;
3519 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3521 as_fatal (_("internal: can't hash `%s': %s"),
3522 mips16_opcodes[i].name, retval);
3525 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3527 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3529 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3530 mips16_nop_insn.fixed_p = 1;
3534 while (i < bfd_mips16_num_opcodes
3535 && strcmp (mips16_opcodes[i].name, name) == 0);
3538 micromips_op_hash = hash_new ();
3539 micromips_operands = XCNEWVEC (struct mips_operand_array,
3540 bfd_micromips_num_opcodes);
3543 while (i < bfd_micromips_num_opcodes)
3545 const char *name = micromips_opcodes[i].name;
3547 retval = hash_insert (micromips_op_hash, name,
3548 (void *) µmips_opcodes[i]);
3550 as_fatal (_("internal: can't hash `%s': %s"),
3551 micromips_opcodes[i].name, retval);
3554 struct mips_cl_insn *micromips_nop_insn;
3556 if (!validate_micromips_insn (µmips_opcodes[i],
3557 µmips_operands[i]))
3560 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3562 if (micromips_insn_length (micromips_opcodes + i) == 2)
3563 micromips_nop_insn = µmips_nop16_insn;
3564 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3565 micromips_nop_insn = µmips_nop32_insn;
3569 if (micromips_nop_insn->insn_mo == NULL
3570 && strcmp (name, "nop") == 0)
3572 create_insn (micromips_nop_insn, micromips_opcodes + i);
3573 micromips_nop_insn->fixed_p = 1;
3577 while (++i < bfd_micromips_num_opcodes
3578 && strcmp (micromips_opcodes[i].name, name) == 0);
3582 as_fatal (_("broken assembler, no assembly attempted"));
3584 /* We add all the general register names to the symbol table. This
3585 helps us detect invalid uses of them. */
3586 for (i = 0; reg_names[i].name; i++)
3587 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3588 reg_names[i].num, /* & RNUM_MASK, */
3589 &zero_address_frag));
3591 for (i = 0; reg_names_n32n64[i].name; i++)
3592 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3593 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3594 &zero_address_frag));
3596 for (i = 0; reg_names_o32[i].name; i++)
3597 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3598 reg_names_o32[i].num, /* & RNUM_MASK, */
3599 &zero_address_frag));
3601 for (i = 0; i < 32; i++)
3605 /* R5900 VU0 floating-point register. */
3606 regname[sizeof (rename) - 1] = 0;
3607 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3608 symbol_table_insert (symbol_new (regname, reg_section,
3609 RTYPE_VF | i, &zero_address_frag));
3611 /* R5900 VU0 integer register. */
3612 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3613 symbol_table_insert (symbol_new (regname, reg_section,
3614 RTYPE_VI | i, &zero_address_frag));
3617 snprintf (regname, sizeof (regname) - 1, "$w%d", i);
3618 symbol_table_insert (symbol_new (regname, reg_section,
3619 RTYPE_MSA | i, &zero_address_frag));
3622 obstack_init (&mips_operand_tokens);
3624 mips_no_prev_insn ();
3627 mips_cprmask[0] = 0;
3628 mips_cprmask[1] = 0;
3629 mips_cprmask[2] = 0;
3630 mips_cprmask[3] = 0;
3632 /* set the default alignment for the text section (2**2) */
3633 record_alignment (text_section, 2);
3635 bfd_set_gp_size (stdoutput, g_switch_value);
3637 /* On a native system other than VxWorks, sections must be aligned
3638 to 16 byte boundaries. When configured for an embedded ELF
3639 target, we don't bother. */
3640 if (strncmp (TARGET_OS, "elf", 3) != 0
3641 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3643 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3644 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3645 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3648 /* Create a .reginfo section for register masks and a .mdebug
3649 section for debugging information. */
3657 subseg = now_subseg;
3659 /* The ABI says this section should be loaded so that the
3660 running program can access it. However, we don't load it
3661 if we are configured for an embedded target */
3662 flags = SEC_READONLY | SEC_DATA;
3663 if (strncmp (TARGET_OS, "elf", 3) != 0)
3664 flags |= SEC_ALLOC | SEC_LOAD;
3666 if (mips_abi != N64_ABI)
3668 sec = subseg_new (".reginfo", (subsegT) 0);
3670 bfd_set_section_flags (stdoutput, sec, flags);
3671 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3673 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3677 /* The 64-bit ABI uses a .MIPS.options section rather than
3678 .reginfo section. */
3679 sec = subseg_new (".MIPS.options", (subsegT) 0);
3680 bfd_set_section_flags (stdoutput, sec, flags);
3681 bfd_set_section_alignment (stdoutput, sec, 3);
3683 /* Set up the option header. */
3685 Elf_Internal_Options opthdr;
3688 opthdr.kind = ODK_REGINFO;
3689 opthdr.size = (sizeof (Elf_External_Options)
3690 + sizeof (Elf64_External_RegInfo));
3693 f = frag_more (sizeof (Elf_External_Options));
3694 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3695 (Elf_External_Options *) f);
3697 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3701 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3702 bfd_set_section_flags (stdoutput, sec,
3703 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3704 bfd_set_section_alignment (stdoutput, sec, 3);
3705 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3707 if (ECOFF_DEBUGGING)
3709 sec = subseg_new (".mdebug", (subsegT) 0);
3710 (void) bfd_set_section_flags (stdoutput, sec,
3711 SEC_HAS_CONTENTS | SEC_READONLY);
3712 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3714 else if (mips_flag_pdr)
3716 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3717 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3718 SEC_READONLY | SEC_RELOC
3720 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3723 subseg_set (seg, subseg);
3726 if (mips_fix_vr4120)
3727 init_vr4120_conflicts ();
3731 fpabi_incompatible_with (int fpabi, const char *what)
3733 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3734 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3738 fpabi_requires (int fpabi, const char *what)
3740 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3741 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3744 /* Check -mabi and register sizes against the specified FP ABI. */
3746 check_fpabi (int fpabi)
3750 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3751 if (file_mips_opts.soft_float)
3752 fpabi_incompatible_with (fpabi, "softfloat");
3753 else if (file_mips_opts.single_float)
3754 fpabi_incompatible_with (fpabi, "singlefloat");
3755 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3756 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3757 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3758 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3761 case Val_GNU_MIPS_ABI_FP_XX:
3762 if (mips_abi != O32_ABI)
3763 fpabi_requires (fpabi, "-mabi=32");
3764 else if (file_mips_opts.soft_float)
3765 fpabi_incompatible_with (fpabi, "softfloat");
3766 else if (file_mips_opts.single_float)
3767 fpabi_incompatible_with (fpabi, "singlefloat");
3768 else if (file_mips_opts.fp != 0)
3769 fpabi_requires (fpabi, "fp=xx");
3772 case Val_GNU_MIPS_ABI_FP_64A:
3773 case Val_GNU_MIPS_ABI_FP_64:
3774 if (mips_abi != O32_ABI)
3775 fpabi_requires (fpabi, "-mabi=32");
3776 else if (file_mips_opts.soft_float)
3777 fpabi_incompatible_with (fpabi, "softfloat");
3778 else if (file_mips_opts.single_float)
3779 fpabi_incompatible_with (fpabi, "singlefloat");
3780 else if (file_mips_opts.fp != 64)
3781 fpabi_requires (fpabi, "fp=64");
3782 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3783 fpabi_incompatible_with (fpabi, "nooddspreg");
3784 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3785 fpabi_requires (fpabi, "nooddspreg");
3788 case Val_GNU_MIPS_ABI_FP_SINGLE:
3789 if (file_mips_opts.soft_float)
3790 fpabi_incompatible_with (fpabi, "softfloat");
3791 else if (!file_mips_opts.single_float)
3792 fpabi_requires (fpabi, "singlefloat");
3795 case Val_GNU_MIPS_ABI_FP_SOFT:
3796 if (!file_mips_opts.soft_float)
3797 fpabi_requires (fpabi, "softfloat");
3800 case Val_GNU_MIPS_ABI_FP_OLD_64:
3801 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3802 Tag_GNU_MIPS_ABI_FP, fpabi);
3805 case Val_GNU_MIPS_ABI_FP_NAN2008:
3806 /* Silently ignore compatibility value. */
3810 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3811 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3816 /* Perform consistency checks on the current options. */
3819 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3821 /* Check the size of integer registers agrees with the ABI and ISA. */
3822 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3823 as_bad (_("`gp=64' used with a 32-bit processor"));
3825 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3826 as_bad (_("`gp=32' used with a 64-bit ABI"));
3828 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3829 as_bad (_("`gp=64' used with a 32-bit ABI"));
3831 /* Check the size of the float registers agrees with the ABI and ISA. */
3835 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3836 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3837 else if (opts->single_float == 1)
3838 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3841 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3842 as_bad (_("`fp=64' used with a 32-bit fpu"));
3844 && ABI_NEEDS_32BIT_REGS (mips_abi)
3845 && !ISA_HAS_MXHC1 (opts->isa))
3846 as_warn (_("`fp=64' used with a 32-bit ABI"));
3850 && ABI_NEEDS_64BIT_REGS (mips_abi))
3851 as_warn (_("`fp=32' used with a 64-bit ABI"));
3852 if (ISA_IS_R6 (mips_opts.isa) && opts->single_float == 0)
3853 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3856 as_bad (_("Unknown size of floating point registers"));
3860 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3861 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3863 if (opts->micromips == 1 && opts->mips16 == 1)
3864 as_bad (_("`mips16' cannot be used with `micromips'"));
3865 else if (ISA_IS_R6 (mips_opts.isa)
3866 && (opts->micromips == 1
3867 || opts->mips16 == 1))
3868 as_fatal (_("`%s' can not be used with `%s'"),
3869 opts->micromips ? "micromips" : "mips16",
3870 mips_cpu_info_from_isa (mips_opts.isa)->name);
3872 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3873 as_fatal (_("branch relaxation is not supported in `%s'"),
3874 mips_cpu_info_from_isa (opts->isa)->name);
3877 /* Perform consistency checks on the module level options exactly once.
3878 This is a deferred check that happens:
3879 at the first .set directive
3880 or, at the first pseudo op that generates code (inc .dc.a)
3881 or, at the first instruction
3885 file_mips_check_options (void)
3887 const struct mips_cpu_info *arch_info = 0;
3889 if (file_mips_opts_checked)
3892 /* The following code determines the register size.
3893 Similar code was added to GCC 3.3 (see override_options() in
3894 config/mips/mips.c). The GAS and GCC code should be kept in sync
3895 as much as possible. */
3897 if (file_mips_opts.gp < 0)
3899 /* Infer the integer register size from the ABI and processor.
3900 Restrict ourselves to 32-bit registers if that's all the
3901 processor has, or if the ABI cannot handle 64-bit registers. */
3902 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3903 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3907 if (file_mips_opts.fp < 0)
3909 /* No user specified float register size.
3910 ??? GAS treats single-float processors as though they had 64-bit
3911 float registers (although it complains when double-precision
3912 instructions are used). As things stand, saying they have 32-bit
3913 registers would lead to spurious "register must be even" messages.
3914 So here we assume float registers are never smaller than the
3916 if (file_mips_opts.gp == 64)
3917 /* 64-bit integer registers implies 64-bit float registers. */
3918 file_mips_opts.fp = 64;
3919 else if ((file_mips_opts.ase & FP64_ASES)
3920 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3921 /* Handle ASEs that require 64-bit float registers, if possible. */
3922 file_mips_opts.fp = 64;
3923 else if (ISA_IS_R6 (mips_opts.isa))
3924 /* R6 implies 64-bit float registers. */
3925 file_mips_opts.fp = 64;
3927 /* 32-bit float registers. */
3928 file_mips_opts.fp = 32;
3931 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3933 /* Disable operations on odd-numbered floating-point registers by default
3934 when using the FPXX ABI. */
3935 if (file_mips_opts.oddspreg < 0)
3937 if (file_mips_opts.fp == 0)
3938 file_mips_opts.oddspreg = 0;
3940 file_mips_opts.oddspreg = 1;
3943 /* End of GCC-shared inference code. */
3945 /* This flag is set when we have a 64-bit capable CPU but use only
3946 32-bit wide registers. Note that EABI does not use it. */
3947 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3948 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3949 || mips_abi == O32_ABI))
3952 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3953 as_bad (_("trap exception not supported at ISA 1"));
3955 /* If the selected architecture includes support for ASEs, enable
3956 generation of code for them. */
3957 if (file_mips_opts.mips16 == -1)
3958 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3959 if (file_mips_opts.micromips == -1)
3960 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3963 if (mips_nan2008 == -1)
3964 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3965 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3966 as_fatal (_("`%s' does not support legacy NaN"),
3967 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3969 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3970 being selected implicitly. */
3971 if (file_mips_opts.fp != 64)
3972 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3974 /* If the user didn't explicitly select or deselect a particular ASE,
3975 use the default setting for the CPU. */
3976 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
3978 /* Set up the current options. These may change throughout assembly. */
3979 mips_opts = file_mips_opts;
3981 mips_check_isa_supports_ases ();
3982 mips_check_options (&file_mips_opts, TRUE);
3983 file_mips_opts_checked = TRUE;
3985 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3986 as_warn (_("could not set architecture and machine"));
3990 md_assemble (char *str)
3992 struct mips_cl_insn insn;
3993 bfd_reloc_code_real_type unused_reloc[3]
3994 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3996 file_mips_check_options ();
3998 imm_expr.X_op = O_absent;
3999 offset_expr.X_op = O_absent;
4000 offset_reloc[0] = BFD_RELOC_UNUSED;
4001 offset_reloc[1] = BFD_RELOC_UNUSED;
4002 offset_reloc[2] = BFD_RELOC_UNUSED;
4004 mips_mark_labels ();
4005 mips_assembling_insn = TRUE;
4006 clear_insn_error ();
4008 if (mips_opts.mips16)
4009 mips16_ip (str, &insn);
4012 mips_ip (str, &insn);
4013 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4014 str, insn.insn_opcode));
4018 report_insn_error (str);
4019 else if (insn.insn_mo->pinfo == INSN_MACRO)
4022 if (mips_opts.mips16)
4023 mips16_macro (&insn);
4030 if (offset_expr.X_op != O_absent)
4031 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4033 append_insn (&insn, NULL, unused_reloc, FALSE);
4036 mips_assembling_insn = FALSE;
4039 /* Convenience functions for abstracting away the differences between
4040 MIPS16 and non-MIPS16 relocations. */
4042 static inline bfd_boolean
4043 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4047 case BFD_RELOC_MIPS16_JMP:
4048 case BFD_RELOC_MIPS16_GPREL:
4049 case BFD_RELOC_MIPS16_GOT16:
4050 case BFD_RELOC_MIPS16_CALL16:
4051 case BFD_RELOC_MIPS16_HI16_S:
4052 case BFD_RELOC_MIPS16_HI16:
4053 case BFD_RELOC_MIPS16_LO16:
4061 static inline bfd_boolean
4062 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4066 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4067 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4068 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4069 case BFD_RELOC_MICROMIPS_GPREL16:
4070 case BFD_RELOC_MICROMIPS_JMP:
4071 case BFD_RELOC_MICROMIPS_HI16:
4072 case BFD_RELOC_MICROMIPS_HI16_S:
4073 case BFD_RELOC_MICROMIPS_LO16:
4074 case BFD_RELOC_MICROMIPS_LITERAL:
4075 case BFD_RELOC_MICROMIPS_GOT16:
4076 case BFD_RELOC_MICROMIPS_CALL16:
4077 case BFD_RELOC_MICROMIPS_GOT_HI16:
4078 case BFD_RELOC_MICROMIPS_GOT_LO16:
4079 case BFD_RELOC_MICROMIPS_CALL_HI16:
4080 case BFD_RELOC_MICROMIPS_CALL_LO16:
4081 case BFD_RELOC_MICROMIPS_SUB:
4082 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4083 case BFD_RELOC_MICROMIPS_GOT_OFST:
4084 case BFD_RELOC_MICROMIPS_GOT_DISP:
4085 case BFD_RELOC_MICROMIPS_HIGHEST:
4086 case BFD_RELOC_MICROMIPS_HIGHER:
4087 case BFD_RELOC_MICROMIPS_SCN_DISP:
4088 case BFD_RELOC_MICROMIPS_JALR:
4096 static inline bfd_boolean
4097 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4099 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4102 static inline bfd_boolean
4103 got16_reloc_p (bfd_reloc_code_real_type reloc)
4105 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4106 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4109 static inline bfd_boolean
4110 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4112 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4113 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4116 static inline bfd_boolean
4117 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4119 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4120 || reloc == BFD_RELOC_MICROMIPS_LO16);
4123 static inline bfd_boolean
4124 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4126 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4129 static inline bfd_boolean
4130 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4132 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4133 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4136 /* Return true if RELOC is a PC-relative relocation that does not have
4137 full address range. */
4139 static inline bfd_boolean
4140 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4144 case BFD_RELOC_16_PCREL_S2:
4145 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4146 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4147 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4148 case BFD_RELOC_MIPS_21_PCREL_S2:
4149 case BFD_RELOC_MIPS_26_PCREL_S2:
4150 case BFD_RELOC_MIPS_18_PCREL_S3:
4151 case BFD_RELOC_MIPS_19_PCREL_S2:
4154 case BFD_RELOC_32_PCREL:
4155 case BFD_RELOC_HI16_S_PCREL:
4156 case BFD_RELOC_LO16_PCREL:
4157 return HAVE_64BIT_ADDRESSES;
4164 /* Return true if the given relocation might need a matching %lo().
4165 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4166 need a matching %lo() when applied to local symbols. */
4168 static inline bfd_boolean
4169 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4171 return (HAVE_IN_PLACE_ADDENDS
4172 && (hi16_reloc_p (reloc)
4173 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4174 all GOT16 relocations evaluate to "G". */
4175 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4178 /* Return the type of %lo() reloc needed by RELOC, given that
4179 reloc_needs_lo_p. */
4181 static inline bfd_reloc_code_real_type
4182 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4184 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4185 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4189 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4192 static inline bfd_boolean
4193 fixup_has_matching_lo_p (fixS *fixp)
4195 return (fixp->fx_next != NULL
4196 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4197 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4198 && fixp->fx_offset == fixp->fx_next->fx_offset);
4201 /* Move all labels in LABELS to the current insertion point. TEXT_P
4202 says whether the labels refer to text or data. */
4205 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4207 struct insn_label_list *l;
4210 for (l = labels; l != NULL; l = l->next)
4212 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4213 symbol_set_frag (l->label, frag_now);
4214 val = (valueT) frag_now_fix ();
4215 /* MIPS16/microMIPS text labels are stored as odd. */
4216 if (text_p && HAVE_CODE_COMPRESSION)
4218 S_SET_VALUE (l->label, val);
4222 /* Move all labels in insn_labels to the current insertion point
4223 and treat them as text labels. */
4226 mips_move_text_labels (void)
4228 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4232 s_is_linkonce (symbolS *sym, segT from_seg)
4234 bfd_boolean linkonce = FALSE;
4235 segT symseg = S_GET_SEGMENT (sym);
4237 if (symseg != from_seg && !S_IS_LOCAL (sym))
4239 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4241 /* The GNU toolchain uses an extension for ELF: a section
4242 beginning with the magic string .gnu.linkonce is a
4243 linkonce section. */
4244 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4245 sizeof ".gnu.linkonce" - 1) == 0)
4251 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4252 linker to handle them specially, such as generating jalx instructions
4253 when needed. We also make them odd for the duration of the assembly,
4254 in order to generate the right sort of code. We will make them even
4255 in the adjust_symtab routine, while leaving them marked. This is
4256 convenient for the debugger and the disassembler. The linker knows
4257 to make them odd again. */
4260 mips_compressed_mark_label (symbolS *label)
4262 gas_assert (HAVE_CODE_COMPRESSION);
4264 if (mips_opts.mips16)
4265 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4267 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4268 if ((S_GET_VALUE (label) & 1) == 0
4269 /* Don't adjust the address if the label is global or weak, or
4270 in a link-once section, since we'll be emitting symbol reloc
4271 references to it which will be patched up by the linker, and
4272 the final value of the symbol may or may not be MIPS16/microMIPS. */
4273 && !S_IS_WEAK (label)
4274 && !S_IS_EXTERNAL (label)
4275 && !s_is_linkonce (label, now_seg))
4276 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4279 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4282 mips_compressed_mark_labels (void)
4284 struct insn_label_list *l;
4286 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4287 mips_compressed_mark_label (l->label);
4290 /* End the current frag. Make it a variant frag and record the
4294 relax_close_frag (void)
4296 mips_macro_warning.first_frag = frag_now;
4297 frag_var (rs_machine_dependent, 0, 0,
4298 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4299 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4301 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4302 mips_relax.first_fixup = 0;
4305 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4306 See the comment above RELAX_ENCODE for more details. */
4309 relax_start (symbolS *symbol)
4311 gas_assert (mips_relax.sequence == 0);
4312 mips_relax.sequence = 1;
4313 mips_relax.symbol = symbol;
4316 /* Start generating the second version of a relaxable sequence.
4317 See the comment above RELAX_ENCODE for more details. */
4322 gas_assert (mips_relax.sequence == 1);
4323 mips_relax.sequence = 2;
4326 /* End the current relaxable sequence. */
4331 gas_assert (mips_relax.sequence == 2);
4332 relax_close_frag ();
4333 mips_relax.sequence = 0;
4336 /* Return true if IP is a delayed branch or jump. */
4338 static inline bfd_boolean
4339 delayed_branch_p (const struct mips_cl_insn *ip)
4341 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4342 | INSN_COND_BRANCH_DELAY
4343 | INSN_COND_BRANCH_LIKELY)) != 0;
4346 /* Return true if IP is a compact branch or jump. */
4348 static inline bfd_boolean
4349 compact_branch_p (const struct mips_cl_insn *ip)
4351 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4352 | INSN2_COND_BRANCH)) != 0;
4355 /* Return true if IP is an unconditional branch or jump. */
4357 static inline bfd_boolean
4358 uncond_branch_p (const struct mips_cl_insn *ip)
4360 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4361 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4364 /* Return true if IP is a branch-likely instruction. */
4366 static inline bfd_boolean
4367 branch_likely_p (const struct mips_cl_insn *ip)
4369 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4372 /* Return the type of nop that should be used to fill the delay slot
4373 of delayed branch IP. */
4375 static struct mips_cl_insn *
4376 get_delay_slot_nop (const struct mips_cl_insn *ip)
4378 if (mips_opts.micromips
4379 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4380 return µmips_nop32_insn;
4384 /* Return a mask that has bit N set if OPCODE reads the register(s)
4388 insn_read_mask (const struct mips_opcode *opcode)
4390 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4393 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4397 insn_write_mask (const struct mips_opcode *opcode)
4399 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4402 /* Return a mask of the registers specified by operand OPERAND of INSN.
4403 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4407 operand_reg_mask (const struct mips_cl_insn *insn,
4408 const struct mips_operand *operand,
4409 unsigned int type_mask)
4411 unsigned int uval, vsel;
4413 switch (operand->type)
4420 case OP_ADDIUSP_INT:
4421 case OP_ENTRY_EXIT_LIST:
4422 case OP_REPEAT_DEST_REG:
4423 case OP_REPEAT_PREV_REG:
4426 case OP_VU0_MATCH_SUFFIX:
4431 case OP_OPTIONAL_REG:
4433 const struct mips_reg_operand *reg_op;
4435 reg_op = (const struct mips_reg_operand *) operand;
4436 if (!(type_mask & (1 << reg_op->reg_type)))
4438 uval = insn_extract_operand (insn, operand);
4439 return 1 << mips_decode_reg_operand (reg_op, uval);
4444 const struct mips_reg_pair_operand *pair_op;
4446 pair_op = (const struct mips_reg_pair_operand *) operand;
4447 if (!(type_mask & (1 << pair_op->reg_type)))
4449 uval = insn_extract_operand (insn, operand);
4450 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4453 case OP_CLO_CLZ_DEST:
4454 if (!(type_mask & (1 << OP_REG_GP)))
4456 uval = insn_extract_operand (insn, operand);
4457 return (1 << (uval & 31)) | (1 << (uval >> 5));
4460 if (!(type_mask & (1 << OP_REG_GP)))
4462 uval = insn_extract_operand (insn, operand);
4463 gas_assert ((uval & 31) == (uval >> 5));
4464 return 1 << (uval & 31);
4467 case OP_NON_ZERO_REG:
4468 if (!(type_mask & (1 << OP_REG_GP)))
4470 uval = insn_extract_operand (insn, operand);
4471 return 1 << (uval & 31);
4473 case OP_LWM_SWM_LIST:
4476 case OP_SAVE_RESTORE_LIST:
4479 case OP_MDMX_IMM_REG:
4480 if (!(type_mask & (1 << OP_REG_VEC)))
4482 uval = insn_extract_operand (insn, operand);
4484 if ((vsel & 0x18) == 0x18)
4486 return 1 << (uval & 31);
4489 if (!(type_mask & (1 << OP_REG_GP)))
4491 return 1 << insn_extract_operand (insn, operand);
4496 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4497 where bit N of OPNO_MASK is set if operand N should be included.
4498 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4502 insn_reg_mask (const struct mips_cl_insn *insn,
4503 unsigned int type_mask, unsigned int opno_mask)
4505 unsigned int opno, reg_mask;
4509 while (opno_mask != 0)
4512 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4519 /* Return the mask of core registers that IP reads. */
4522 gpr_read_mask (const struct mips_cl_insn *ip)
4524 unsigned long pinfo, pinfo2;
4527 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4528 pinfo = ip->insn_mo->pinfo;
4529 pinfo2 = ip->insn_mo->pinfo2;
4530 if (pinfo & INSN_UDI)
4532 /* UDI instructions have traditionally been assumed to read RS
4534 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4535 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4537 if (pinfo & INSN_READ_GPR_24)
4539 if (pinfo2 & INSN2_READ_GPR_16)
4541 if (pinfo2 & INSN2_READ_SP)
4543 if (pinfo2 & INSN2_READ_GPR_31)
4545 /* Don't include register 0. */
4549 /* Return the mask of core registers that IP writes. */
4552 gpr_write_mask (const struct mips_cl_insn *ip)
4554 unsigned long pinfo, pinfo2;
4557 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4558 pinfo = ip->insn_mo->pinfo;
4559 pinfo2 = ip->insn_mo->pinfo2;
4560 if (pinfo & INSN_WRITE_GPR_24)
4562 if (pinfo & INSN_WRITE_GPR_31)
4564 if (pinfo & INSN_UDI)
4565 /* UDI instructions have traditionally been assumed to write to RD. */
4566 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4567 if (pinfo2 & INSN2_WRITE_SP)
4569 /* Don't include register 0. */
4573 /* Return the mask of floating-point registers that IP reads. */
4576 fpr_read_mask (const struct mips_cl_insn *ip)
4578 unsigned long pinfo;
4581 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4582 | (1 << OP_REG_MSA)),
4583 insn_read_mask (ip->insn_mo));
4584 pinfo = ip->insn_mo->pinfo;
4585 /* Conservatively treat all operands to an FP_D instruction are doubles.
4586 (This is overly pessimistic for things like cvt.d.s.) */
4587 if (FPR_SIZE != 64 && (pinfo & FP_D))
4592 /* Return the mask of floating-point registers that IP writes. */
4595 fpr_write_mask (const struct mips_cl_insn *ip)
4597 unsigned long pinfo;
4600 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4601 | (1 << OP_REG_MSA)),
4602 insn_write_mask (ip->insn_mo));
4603 pinfo = ip->insn_mo->pinfo;
4604 /* Conservatively treat all operands to an FP_D instruction are doubles.
4605 (This is overly pessimistic for things like cvt.s.d.) */
4606 if (FPR_SIZE != 64 && (pinfo & FP_D))
4611 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4612 Check whether that is allowed. */
4615 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4617 const char *s = insn->name;
4618 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4620 && mips_opts.oddspreg;
4622 if (insn->pinfo == INSN_MACRO)
4623 /* Let a macro pass, we'll catch it later when it is expanded. */
4626 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4627 otherwise it depends on oddspreg. */
4628 if ((insn->pinfo & FP_S)
4629 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4630 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4631 return FPR_SIZE == 32 || oddspreg;
4633 /* Allow odd registers for single-precision ops and double-precision if the
4634 floating-point registers are 64-bit wide. */
4635 switch (insn->pinfo & (FP_S | FP_D))
4641 return FPR_SIZE == 64;
4646 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4647 s = strchr (insn->name, '.');
4648 if (s != NULL && opnum == 2)
4649 s = strchr (s + 1, '.');
4650 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4653 return FPR_SIZE == 64;
4656 /* Information about an instruction argument that we're trying to match. */
4657 struct mips_arg_info
4659 /* The instruction so far. */
4660 struct mips_cl_insn *insn;
4662 /* The first unconsumed operand token. */
4663 struct mips_operand_token *token;
4665 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4668 /* The 1-based argument number, for error reporting. This does not
4669 count elided optional registers, etc.. */
4672 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4673 unsigned int last_regno;
4675 /* If the first operand was an OP_REG, this is the register that it
4676 specified, otherwise it is ILLEGAL_REG. */
4677 unsigned int dest_regno;
4679 /* The value of the last OP_INT operand. Only used for OP_MSB,
4680 where it gives the lsb position. */
4681 unsigned int last_op_int;
4683 /* If true, match routines should assume that no later instruction
4684 alternative matches and should therefore be as accomodating as
4685 possible. Match routines should not report errors if something
4686 is only invalid for !LAX_MATCH. */
4687 bfd_boolean lax_match;
4689 /* True if a reference to the current AT register was seen. */
4690 bfd_boolean seen_at;
4693 /* Record that the argument is out of range. */
4696 match_out_of_range (struct mips_arg_info *arg)
4698 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4701 /* Record that the argument isn't constant but needs to be. */
4704 match_not_constant (struct mips_arg_info *arg)
4706 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4710 /* Try to match an OT_CHAR token for character CH. Consume the token
4711 and return true on success, otherwise return false. */
4714 match_char (struct mips_arg_info *arg, char ch)
4716 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4726 /* Try to get an expression from the next tokens in ARG. Consume the
4727 tokens and return true on success, storing the expression value in
4728 VALUE and relocation types in R. */
4731 match_expression (struct mips_arg_info *arg, expressionS *value,
4732 bfd_reloc_code_real_type *r)
4734 /* If the next token is a '(' that was parsed as being part of a base
4735 expression, assume we have an elided offset. The later match will fail
4736 if this turns out to be wrong. */
4737 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4739 value->X_op = O_constant;
4740 value->X_add_number = 0;
4741 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4745 /* Reject register-based expressions such as "0+$2" and "(($2))".
4746 For plain registers the default error seems more appropriate. */
4747 if (arg->token->type == OT_INTEGER
4748 && arg->token->u.integer.value.X_op == O_register)
4750 set_insn_error (arg->argnum, _("register value used as expression"));
4754 if (arg->token->type == OT_INTEGER)
4756 *value = arg->token->u.integer.value;
4757 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4763 (arg->argnum, _("operand %d must be an immediate expression"),
4768 /* Try to get a constant expression from the next tokens in ARG. Consume
4769 the tokens and return return true on success, storing the constant value
4770 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4774 match_const_int (struct mips_arg_info *arg, offsetT *value)
4777 bfd_reloc_code_real_type r[3];
4779 if (!match_expression (arg, &ex, r))
4782 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4783 *value = ex.X_add_number;
4786 match_not_constant (arg);
4792 /* Return the RTYPE_* flags for a register operand of type TYPE that
4793 appears in instruction OPCODE. */
4796 convert_reg_type (const struct mips_opcode *opcode,
4797 enum mips_reg_operand_type type)
4802 return RTYPE_NUM | RTYPE_GP;
4805 /* Allow vector register names for MDMX if the instruction is a 64-bit
4806 FPR load, store or move (including moves to and from GPRs). */
4807 if ((mips_opts.ase & ASE_MDMX)
4808 && (opcode->pinfo & FP_D)
4809 && (opcode->pinfo & (INSN_COPROC_MOVE
4810 | INSN_COPROC_MEMORY_DELAY
4813 | INSN_STORE_MEMORY)))
4814 return RTYPE_FPU | RTYPE_VEC;
4818 if (opcode->pinfo & (FP_D | FP_S))
4819 return RTYPE_CCC | RTYPE_FCC;
4823 if (opcode->membership & INSN_5400)
4825 return RTYPE_FPU | RTYPE_VEC;
4831 if (opcode->name[strlen (opcode->name) - 1] == '0')
4832 return RTYPE_NUM | RTYPE_CP0;
4839 return RTYPE_NUM | RTYPE_VI;
4842 return RTYPE_NUM | RTYPE_VF;
4844 case OP_REG_R5900_I:
4845 return RTYPE_R5900_I;
4847 case OP_REG_R5900_Q:
4848 return RTYPE_R5900_Q;
4850 case OP_REG_R5900_R:
4851 return RTYPE_R5900_R;
4853 case OP_REG_R5900_ACC:
4854 return RTYPE_R5900_ACC;
4859 case OP_REG_MSA_CTRL:
4865 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4868 check_regno (struct mips_arg_info *arg,
4869 enum mips_reg_operand_type type, unsigned int regno)
4871 if (AT && type == OP_REG_GP && regno == AT)
4872 arg->seen_at = TRUE;
4874 if (type == OP_REG_FP
4876 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4878 /* This was a warning prior to introducing O32 FPXX and FP64 support
4879 so maintain a warning for FP32 but raise an error for the new
4882 as_warn (_("float register should be even, was %d"), regno);
4884 as_bad (_("float register should be even, was %d"), regno);
4887 if (type == OP_REG_CCC)
4892 name = arg->insn->insn_mo->name;
4893 length = strlen (name);
4894 if ((regno & 1) != 0
4895 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4896 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4897 as_warn (_("condition code register should be even for %s, was %d"),
4900 if ((regno & 3) != 0
4901 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4902 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4907 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4908 a register of type TYPE. Return true on success, storing the register
4909 number in *REGNO and warning about any dubious uses. */
4912 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4913 unsigned int symval, unsigned int *regno)
4915 if (type == OP_REG_VEC)
4916 symval = mips_prefer_vec_regno (symval);
4917 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4920 *regno = symval & RNUM_MASK;
4921 check_regno (arg, type, *regno);
4925 /* Try to interpret the next token in ARG as a register of type TYPE.
4926 Consume the token and return true on success, storing the register
4927 number in *REGNO. Return false on failure. */
4930 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4931 unsigned int *regno)
4933 if (arg->token->type == OT_REG
4934 && match_regno (arg, type, arg->token->u.regno, regno))
4942 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4943 Consume the token and return true on success, storing the register numbers
4944 in *REGNO1 and *REGNO2. Return false on failure. */
4947 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4948 unsigned int *regno1, unsigned int *regno2)
4950 if (match_reg (arg, type, regno1))
4955 if (arg->token->type == OT_REG_RANGE
4956 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4957 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4958 && *regno1 <= *regno2)
4966 /* OP_INT matcher. */
4969 match_int_operand (struct mips_arg_info *arg,
4970 const struct mips_operand *operand_base)
4972 const struct mips_int_operand *operand;
4974 int min_val, max_val, factor;
4977 operand = (const struct mips_int_operand *) operand_base;
4978 factor = 1 << operand->shift;
4979 min_val = mips_int_operand_min (operand);
4980 max_val = mips_int_operand_max (operand);
4982 if (operand_base->lsb == 0
4983 && operand_base->size == 16
4984 && operand->shift == 0
4985 && operand->bias == 0
4986 && (operand->max_val == 32767 || operand->max_val == 65535))
4988 /* The operand can be relocated. */
4989 if (!match_expression (arg, &offset_expr, offset_reloc))
4992 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4993 /* Relocation operators were used. Accept the arguent and
4994 leave the relocation value in offset_expr and offset_relocs
4995 for the caller to process. */
4998 if (offset_expr.X_op != O_constant)
5000 /* Accept non-constant operands if no later alternative matches,
5001 leaving it for the caller to process. */
5002 if (!arg->lax_match)
5004 offset_reloc[0] = BFD_RELOC_LO16;
5008 /* Clear the global state; we're going to install the operand
5010 sval = offset_expr.X_add_number;
5011 offset_expr.X_op = O_absent;
5013 /* For compatibility with older assemblers, we accept
5014 0x8000-0xffff as signed 16-bit numbers when only
5015 signed numbers are allowed. */
5018 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5019 if (!arg->lax_match && sval <= max_val)
5025 if (!match_const_int (arg, &sval))
5029 arg->last_op_int = sval;
5031 if (sval < min_val || sval > max_val || sval % factor)
5033 match_out_of_range (arg);
5037 uval = (unsigned int) sval >> operand->shift;
5038 uval -= operand->bias;
5040 /* Handle -mfix-cn63xxp1. */
5042 && mips_fix_cn63xxp1
5043 && !mips_opts.micromips
5044 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5059 /* The rest must be changed to 28. */
5064 insn_insert_operand (arg->insn, operand_base, uval);
5068 /* OP_MAPPED_INT matcher. */
5071 match_mapped_int_operand (struct mips_arg_info *arg,
5072 const struct mips_operand *operand_base)
5074 const struct mips_mapped_int_operand *operand;
5075 unsigned int uval, num_vals;
5078 operand = (const struct mips_mapped_int_operand *) operand_base;
5079 if (!match_const_int (arg, &sval))
5082 num_vals = 1 << operand_base->size;
5083 for (uval = 0; uval < num_vals; uval++)
5084 if (operand->int_map[uval] == sval)
5086 if (uval == num_vals)
5088 match_out_of_range (arg);
5092 insn_insert_operand (arg->insn, operand_base, uval);
5096 /* OP_MSB matcher. */
5099 match_msb_operand (struct mips_arg_info *arg,
5100 const struct mips_operand *operand_base)
5102 const struct mips_msb_operand *operand;
5103 int min_val, max_val, max_high;
5104 offsetT size, sval, high;
5106 operand = (const struct mips_msb_operand *) operand_base;
5107 min_val = operand->bias;
5108 max_val = min_val + (1 << operand_base->size) - 1;
5109 max_high = operand->opsize;
5111 if (!match_const_int (arg, &size))
5114 high = size + arg->last_op_int;
5115 sval = operand->add_lsb ? high : size;
5117 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5119 match_out_of_range (arg);
5122 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5126 /* OP_REG matcher. */
5129 match_reg_operand (struct mips_arg_info *arg,
5130 const struct mips_operand *operand_base)
5132 const struct mips_reg_operand *operand;
5133 unsigned int regno, uval, num_vals;
5135 operand = (const struct mips_reg_operand *) operand_base;
5136 if (!match_reg (arg, operand->reg_type, ®no))
5139 if (operand->reg_map)
5141 num_vals = 1 << operand->root.size;
5142 for (uval = 0; uval < num_vals; uval++)
5143 if (operand->reg_map[uval] == regno)
5145 if (num_vals == uval)
5151 arg->last_regno = regno;
5152 if (arg->opnum == 1)
5153 arg->dest_regno = regno;
5154 insn_insert_operand (arg->insn, operand_base, uval);
5158 /* OP_REG_PAIR matcher. */
5161 match_reg_pair_operand (struct mips_arg_info *arg,
5162 const struct mips_operand *operand_base)
5164 const struct mips_reg_pair_operand *operand;
5165 unsigned int regno1, regno2, uval, num_vals;
5167 operand = (const struct mips_reg_pair_operand *) operand_base;
5168 if (!match_reg (arg, operand->reg_type, ®no1)
5169 || !match_char (arg, ',')
5170 || !match_reg (arg, operand->reg_type, ®no2))
5173 num_vals = 1 << operand_base->size;
5174 for (uval = 0; uval < num_vals; uval++)
5175 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5177 if (uval == num_vals)
5180 insn_insert_operand (arg->insn, operand_base, uval);
5184 /* OP_PCREL matcher. The caller chooses the relocation type. */
5187 match_pcrel_operand (struct mips_arg_info *arg)
5189 bfd_reloc_code_real_type r[3];
5191 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5194 /* OP_PERF_REG matcher. */
5197 match_perf_reg_operand (struct mips_arg_info *arg,
5198 const struct mips_operand *operand)
5202 if (!match_const_int (arg, &sval))
5207 || (mips_opts.arch == CPU_R5900
5208 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5209 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5211 set_insn_error (arg->argnum, _("invalid performance register"));
5215 insn_insert_operand (arg->insn, operand, sval);
5219 /* OP_ADDIUSP matcher. */
5222 match_addiusp_operand (struct mips_arg_info *arg,
5223 const struct mips_operand *operand)
5228 if (!match_const_int (arg, &sval))
5233 match_out_of_range (arg);
5238 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5240 match_out_of_range (arg);
5244 uval = (unsigned int) sval;
5245 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5246 insn_insert_operand (arg->insn, operand, uval);
5250 /* OP_CLO_CLZ_DEST matcher. */
5253 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5254 const struct mips_operand *operand)
5258 if (!match_reg (arg, OP_REG_GP, ®no))
5261 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5265 /* OP_CHECK_PREV matcher. */
5268 match_check_prev_operand (struct mips_arg_info *arg,
5269 const struct mips_operand *operand_base)
5271 const struct mips_check_prev_operand *operand;
5274 operand = (const struct mips_check_prev_operand *) operand_base;
5276 if (!match_reg (arg, OP_REG_GP, ®no))
5279 if (!operand->zero_ok && regno == 0)
5282 if ((operand->less_than_ok && regno < arg->last_regno)
5283 || (operand->greater_than_ok && regno > arg->last_regno)
5284 || (operand->equal_ok && regno == arg->last_regno))
5286 arg->last_regno = regno;
5287 insn_insert_operand (arg->insn, operand_base, regno);
5294 /* OP_SAME_RS_RT matcher. */
5297 match_same_rs_rt_operand (struct mips_arg_info *arg,
5298 const struct mips_operand *operand)
5302 if (!match_reg (arg, OP_REG_GP, ®no))
5307 set_insn_error (arg->argnum, _("the source register must not be $0"));
5311 arg->last_regno = regno;
5313 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5317 /* OP_LWM_SWM_LIST matcher. */
5320 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5321 const struct mips_operand *operand)
5323 unsigned int reglist, sregs, ra, regno1, regno2;
5324 struct mips_arg_info reset;
5327 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5331 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5336 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5339 while (match_char (arg, ',')
5340 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5343 if (operand->size == 2)
5345 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5351 and any permutations of these. */
5352 if ((reglist & 0xfff1ffff) != 0x80010000)
5355 sregs = (reglist >> 17) & 7;
5360 /* The list must include at least one of ra and s0-sN,
5361 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5362 which are $23 and $30 respectively.) E.g.:
5370 and any permutations of these. */
5371 if ((reglist & 0x3f00ffff) != 0)
5374 ra = (reglist >> 27) & 0x10;
5375 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5378 if ((sregs & -sregs) != sregs)
5381 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5385 /* OP_ENTRY_EXIT_LIST matcher. */
5388 match_entry_exit_operand (struct mips_arg_info *arg,
5389 const struct mips_operand *operand)
5392 bfd_boolean is_exit;
5394 /* The format is the same for both ENTRY and EXIT, but the constraints
5396 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5397 mask = (is_exit ? 7 << 3 : 0);
5400 unsigned int regno1, regno2;
5401 bfd_boolean is_freg;
5403 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5405 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5410 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5413 mask |= (5 + regno2) << 3;
5415 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5416 mask |= (regno2 - 3) << 3;
5417 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5418 mask |= (regno2 - 15) << 1;
5419 else if (regno1 == RA && regno2 == RA)
5424 while (match_char (arg, ','));
5426 insn_insert_operand (arg->insn, operand, mask);
5430 /* OP_SAVE_RESTORE_LIST matcher. */
5433 match_save_restore_list_operand (struct mips_arg_info *arg)
5435 unsigned int opcode, args, statics, sregs;
5436 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5439 opcode = arg->insn->insn_opcode;
5441 num_frame_sizes = 0;
5447 unsigned int regno1, regno2;
5449 if (arg->token->type == OT_INTEGER)
5451 /* Handle the frame size. */
5452 if (!match_const_int (arg, &frame_size))
5454 num_frame_sizes += 1;
5458 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5461 while (regno1 <= regno2)
5463 if (regno1 >= 4 && regno1 <= 7)
5465 if (num_frame_sizes == 0)
5467 args |= 1 << (regno1 - 4);
5469 /* statics $a0-$a3 */
5470 statics |= 1 << (regno1 - 4);
5472 else if (regno1 >= 16 && regno1 <= 23)
5474 sregs |= 1 << (regno1 - 16);
5475 else if (regno1 == 30)
5478 else if (regno1 == 31)
5479 /* Add $ra to insn. */
5489 while (match_char (arg, ','));
5491 /* Encode args/statics combination. */
5494 else if (args == 0xf)
5495 /* All $a0-$a3 are args. */
5496 opcode |= MIPS16_ALL_ARGS << 16;
5497 else if (statics == 0xf)
5498 /* All $a0-$a3 are statics. */
5499 opcode |= MIPS16_ALL_STATICS << 16;
5502 /* Count arg registers. */
5512 /* Count static registers. */
5514 while (statics & 0x8)
5516 statics = (statics << 1) & 0xf;
5522 /* Encode args/statics. */
5523 opcode |= ((num_args << 2) | num_statics) << 16;
5526 /* Encode $s0/$s1. */
5527 if (sregs & (1 << 0)) /* $s0 */
5529 if (sregs & (1 << 1)) /* $s1 */
5533 /* Encode $s2-$s8. */
5542 opcode |= num_sregs << 24;
5544 /* Encode frame size. */
5545 if (num_frame_sizes == 0)
5547 set_insn_error (arg->argnum, _("missing frame size"));
5550 if (num_frame_sizes > 1)
5552 set_insn_error (arg->argnum, _("frame size specified twice"));
5555 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5557 set_insn_error (arg->argnum, _("invalid frame size"));
5560 if (frame_size != 128 || (opcode >> 16) != 0)
5563 opcode |= (((frame_size & 0xf0) << 16)
5564 | (frame_size & 0x0f));
5567 /* Finally build the instruction. */
5568 if ((opcode >> 16) != 0 || frame_size == 0)
5569 opcode |= MIPS16_EXTEND;
5570 arg->insn->insn_opcode = opcode;
5574 /* OP_MDMX_IMM_REG matcher. */
5577 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5578 const struct mips_operand *operand)
5580 unsigned int regno, uval;
5582 const struct mips_opcode *opcode;
5584 /* The mips_opcode records whether this is an octobyte or quadhalf
5585 instruction. Start out with that bit in place. */
5586 opcode = arg->insn->insn_mo;
5587 uval = mips_extract_operand (operand, opcode->match);
5588 is_qh = (uval != 0);
5590 if (arg->token->type == OT_REG)
5592 if ((opcode->membership & INSN_5400)
5593 && strcmp (opcode->name, "rzu.ob") == 0)
5595 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5600 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5604 /* Check whether this is a vector register or a broadcast of
5605 a single element. */
5606 if (arg->token->type == OT_INTEGER_INDEX)
5608 if (arg->token->u.index > (is_qh ? 3 : 7))
5610 set_insn_error (arg->argnum, _("invalid element selector"));
5613 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5618 /* A full vector. */
5619 if ((opcode->membership & INSN_5400)
5620 && (strcmp (opcode->name, "sll.ob") == 0
5621 || strcmp (opcode->name, "srl.ob") == 0))
5623 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5629 uval |= MDMX_FMTSEL_VEC_QH << 5;
5631 uval |= MDMX_FMTSEL_VEC_OB << 5;
5639 if (!match_const_int (arg, &sval))
5641 if (sval < 0 || sval > 31)
5643 match_out_of_range (arg);
5646 uval |= (sval & 31);
5648 uval |= MDMX_FMTSEL_IMM_QH << 5;
5650 uval |= MDMX_FMTSEL_IMM_OB << 5;
5652 insn_insert_operand (arg->insn, operand, uval);
5656 /* OP_IMM_INDEX matcher. */
5659 match_imm_index_operand (struct mips_arg_info *arg,
5660 const struct mips_operand *operand)
5662 unsigned int max_val;
5664 if (arg->token->type != OT_INTEGER_INDEX)
5667 max_val = (1 << operand->size) - 1;
5668 if (arg->token->u.index > max_val)
5670 match_out_of_range (arg);
5673 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5678 /* OP_REG_INDEX matcher. */
5681 match_reg_index_operand (struct mips_arg_info *arg,
5682 const struct mips_operand *operand)
5686 if (arg->token->type != OT_REG_INDEX)
5689 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5692 insn_insert_operand (arg->insn, operand, regno);
5697 /* OP_PC matcher. */
5700 match_pc_operand (struct mips_arg_info *arg)
5702 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5710 /* OP_NON_ZERO_REG matcher. */
5713 match_non_zero_reg_operand (struct mips_arg_info *arg,
5714 const struct mips_operand *operand)
5718 if (!match_reg (arg, OP_REG_GP, ®no))
5724 arg->last_regno = regno;
5725 insn_insert_operand (arg->insn, operand, regno);
5729 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5730 register that we need to match. */
5733 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5737 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5740 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5741 the length of the value in bytes (4 for float, 8 for double) and
5742 USING_GPRS says whether the destination is a GPR rather than an FPR.
5744 Return the constant in IMM and OFFSET as follows:
5746 - If the constant should be loaded via memory, set IMM to O_absent and
5747 OFFSET to the memory address.
5749 - Otherwise, if the constant should be loaded into two 32-bit registers,
5750 set IMM to the O_constant to load into the high register and OFFSET
5751 to the corresponding value for the low register.
5753 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5755 These constants only appear as the last operand in an instruction,
5756 and every instruction that accepts them in any variant accepts them
5757 in all variants. This means we don't have to worry about backing out
5758 any changes if the instruction does not match. We just match
5759 unconditionally and report an error if the constant is invalid. */
5762 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5763 expressionS *offset, int length, bfd_boolean using_gprs)
5768 const char *newname;
5769 unsigned char *data;
5771 /* Where the constant is placed is based on how the MIPS assembler
5774 length == 4 && using_gprs -- immediate value only
5775 length == 8 && using_gprs -- .rdata or immediate value
5776 length == 4 && !using_gprs -- .lit4 or immediate value
5777 length == 8 && !using_gprs -- .lit8 or immediate value
5779 The .lit4 and .lit8 sections are only used if permitted by the
5781 if (arg->token->type != OT_FLOAT)
5783 set_insn_error (arg->argnum, _("floating-point expression required"));
5787 gas_assert (arg->token->u.flt.length == length);
5788 data = arg->token->u.flt.data;
5791 /* Handle 32-bit constants for which an immediate value is best. */
5794 || g_switch_value < 4
5795 || (data[0] == 0 && data[1] == 0)
5796 || (data[2] == 0 && data[3] == 0)))
5798 imm->X_op = O_constant;
5799 if (!target_big_endian)
5800 imm->X_add_number = bfd_getl32 (data);
5802 imm->X_add_number = bfd_getb32 (data);
5803 offset->X_op = O_absent;
5807 /* Handle 64-bit constants for which an immediate value is best. */
5809 && !mips_disable_float_construction
5810 /* Constants can only be constructed in GPRs and copied to FPRs if the
5811 GPRs are at least as wide as the FPRs or MTHC1 is available.
5812 Unlike most tests for 32-bit floating-point registers this check
5813 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5814 permit 64-bit moves without MXHC1.
5815 Force the constant into memory otherwise. */
5818 || ISA_HAS_MXHC1 (mips_opts.isa)
5820 && ((data[0] == 0 && data[1] == 0)
5821 || (data[2] == 0 && data[3] == 0))
5822 && ((data[4] == 0 && data[5] == 0)
5823 || (data[6] == 0 && data[7] == 0)))
5825 /* The value is simple enough to load with a couple of instructions.
5826 If using 32-bit registers, set IMM to the high order 32 bits and
5827 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5829 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
5831 imm->X_op = O_constant;
5832 offset->X_op = O_constant;
5833 if (!target_big_endian)
5835 imm->X_add_number = bfd_getl32 (data + 4);
5836 offset->X_add_number = bfd_getl32 (data);
5840 imm->X_add_number = bfd_getb32 (data);
5841 offset->X_add_number = bfd_getb32 (data + 4);
5843 if (offset->X_add_number == 0)
5844 offset->X_op = O_absent;
5848 imm->X_op = O_constant;
5849 if (!target_big_endian)
5850 imm->X_add_number = bfd_getl64 (data);
5852 imm->X_add_number = bfd_getb64 (data);
5853 offset->X_op = O_absent;
5858 /* Switch to the right section. */
5860 subseg = now_subseg;
5863 gas_assert (!using_gprs && g_switch_value >= 4);
5868 if (using_gprs || g_switch_value < 8)
5869 newname = RDATA_SECTION_NAME;
5874 new_seg = subseg_new (newname, (subsegT) 0);
5875 bfd_set_section_flags (stdoutput, new_seg,
5876 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5877 frag_align (length == 4 ? 2 : 3, 0, 0);
5878 if (strncmp (TARGET_OS, "elf", 3) != 0)
5879 record_alignment (new_seg, 4);
5881 record_alignment (new_seg, length == 4 ? 2 : 3);
5883 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
5885 /* Set the argument to the current address in the section. */
5886 imm->X_op = O_absent;
5887 offset->X_op = O_symbol;
5888 offset->X_add_symbol = symbol_temp_new_now ();
5889 offset->X_add_number = 0;
5891 /* Put the floating point number into the section. */
5892 p = frag_more (length);
5893 memcpy (p, data, length);
5895 /* Switch back to the original section. */
5896 subseg_set (seg, subseg);
5900 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5904 match_vu0_suffix_operand (struct mips_arg_info *arg,
5905 const struct mips_operand *operand,
5906 bfd_boolean match_p)
5910 /* The operand can be an XYZW mask or a single 2-bit channel index
5911 (with X being 0). */
5912 gas_assert (operand->size == 2 || operand->size == 4);
5914 /* The suffix can be omitted when it is already part of the opcode. */
5915 if (arg->token->type != OT_CHANNELS)
5918 uval = arg->token->u.channels;
5919 if (operand->size == 2)
5921 /* Check that a single bit is set and convert it into a 2-bit index. */
5922 if ((uval & -uval) != uval)
5924 uval = 4 - ffs (uval);
5927 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5932 insn_insert_operand (arg->insn, operand, uval);
5936 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5937 of the argument text if the match is successful, otherwise return null. */
5940 match_operand (struct mips_arg_info *arg,
5941 const struct mips_operand *operand)
5943 switch (operand->type)
5946 return match_int_operand (arg, operand);
5949 return match_mapped_int_operand (arg, operand);
5952 return match_msb_operand (arg, operand);
5955 case OP_OPTIONAL_REG:
5956 return match_reg_operand (arg, operand);
5959 return match_reg_pair_operand (arg, operand);
5962 return match_pcrel_operand (arg);
5965 return match_perf_reg_operand (arg, operand);
5967 case OP_ADDIUSP_INT:
5968 return match_addiusp_operand (arg, operand);
5970 case OP_CLO_CLZ_DEST:
5971 return match_clo_clz_dest_operand (arg, operand);
5973 case OP_LWM_SWM_LIST:
5974 return match_lwm_swm_list_operand (arg, operand);
5976 case OP_ENTRY_EXIT_LIST:
5977 return match_entry_exit_operand (arg, operand);
5979 case OP_SAVE_RESTORE_LIST:
5980 return match_save_restore_list_operand (arg);
5982 case OP_MDMX_IMM_REG:
5983 return match_mdmx_imm_reg_operand (arg, operand);
5985 case OP_REPEAT_DEST_REG:
5986 return match_tied_reg_operand (arg, arg->dest_regno);
5988 case OP_REPEAT_PREV_REG:
5989 return match_tied_reg_operand (arg, arg->last_regno);
5992 return match_pc_operand (arg);
5995 return match_vu0_suffix_operand (arg, operand, FALSE);
5997 case OP_VU0_MATCH_SUFFIX:
5998 return match_vu0_suffix_operand (arg, operand, TRUE);
6001 return match_imm_index_operand (arg, operand);
6004 return match_reg_index_operand (arg, operand);
6007 return match_same_rs_rt_operand (arg, operand);
6010 return match_check_prev_operand (arg, operand);
6012 case OP_NON_ZERO_REG:
6013 return match_non_zero_reg_operand (arg, operand);
6018 /* ARG is the state after successfully matching an instruction.
6019 Issue any queued-up warnings. */
6022 check_completed_insn (struct mips_arg_info *arg)
6027 as_warn (_("used $at without \".set noat\""));
6029 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6033 /* Return true if modifying general-purpose register REG needs a delay. */
6036 reg_needs_delay (unsigned int reg)
6038 unsigned long prev_pinfo;
6040 prev_pinfo = history[0].insn_mo->pinfo;
6041 if (!mips_opts.noreorder
6042 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6043 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6044 && (gpr_write_mask (&history[0]) & (1 << reg)))
6050 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6051 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6052 by VR4120 errata. */
6055 classify_vr4120_insn (const char *name)
6057 if (strncmp (name, "macc", 4) == 0)
6058 return FIX_VR4120_MACC;
6059 if (strncmp (name, "dmacc", 5) == 0)
6060 return FIX_VR4120_DMACC;
6061 if (strncmp (name, "mult", 4) == 0)
6062 return FIX_VR4120_MULT;
6063 if (strncmp (name, "dmult", 5) == 0)
6064 return FIX_VR4120_DMULT;
6065 if (strstr (name, "div"))
6066 return FIX_VR4120_DIV;
6067 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6068 return FIX_VR4120_MTHILO;
6069 return NUM_FIX_VR4120_CLASSES;
6072 #define INSN_ERET 0x42000018
6073 #define INSN_DERET 0x4200001f
6074 #define INSN_DMULT 0x1c
6075 #define INSN_DMULTU 0x1d
6077 /* Return the number of instructions that must separate INSN1 and INSN2,
6078 where INSN1 is the earlier instruction. Return the worst-case value
6079 for any INSN2 if INSN2 is null. */
6082 insns_between (const struct mips_cl_insn *insn1,
6083 const struct mips_cl_insn *insn2)
6085 unsigned long pinfo1, pinfo2;
6088 /* If INFO2 is null, pessimistically assume that all flags are set for
6089 the second instruction. */
6090 pinfo1 = insn1->insn_mo->pinfo;
6091 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6093 /* For most targets, write-after-read dependencies on the HI and LO
6094 registers must be separated by at least two instructions. */
6095 if (!hilo_interlocks)
6097 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6099 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6103 /* If we're working around r7000 errata, there must be two instructions
6104 between an mfhi or mflo and any instruction that uses the result. */
6105 if (mips_7000_hilo_fix
6106 && !mips_opts.micromips
6107 && MF_HILO_INSN (pinfo1)
6108 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6111 /* If we're working around 24K errata, one instruction is required
6112 if an ERET or DERET is followed by a branch instruction. */
6113 if (mips_fix_24k && !mips_opts.micromips)
6115 if (insn1->insn_opcode == INSN_ERET
6116 || insn1->insn_opcode == INSN_DERET)
6119 || insn2->insn_opcode == INSN_ERET
6120 || insn2->insn_opcode == INSN_DERET
6121 || delayed_branch_p (insn2))
6126 /* If we're working around PMC RM7000 errata, there must be three
6127 nops between a dmult and a load instruction. */
6128 if (mips_fix_rm7000 && !mips_opts.micromips)
6130 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6131 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6133 if (pinfo2 & INSN_LOAD_MEMORY)
6138 /* If working around VR4120 errata, check for combinations that need
6139 a single intervening instruction. */
6140 if (mips_fix_vr4120 && !mips_opts.micromips)
6142 unsigned int class1, class2;
6144 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6145 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6149 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6150 if (vr4120_conflicts[class1] & (1 << class2))
6155 if (!HAVE_CODE_COMPRESSION)
6157 /* Check for GPR or coprocessor load delays. All such delays
6158 are on the RT register. */
6159 /* Itbl support may require additional care here. */
6160 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6161 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6163 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6167 /* Check for generic coprocessor hazards.
6169 This case is not handled very well. There is no special
6170 knowledge of CP0 handling, and the coprocessors other than
6171 the floating point unit are not distinguished at all. */
6172 /* Itbl support may require additional care here. FIXME!
6173 Need to modify this to include knowledge about
6174 user specified delays! */
6175 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6176 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6178 /* Handle cases where INSN1 writes to a known general coprocessor
6179 register. There must be a one instruction delay before INSN2
6180 if INSN2 reads that register, otherwise no delay is needed. */
6181 mask = fpr_write_mask (insn1);
6184 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6189 /* Read-after-write dependencies on the control registers
6190 require a two-instruction gap. */
6191 if ((pinfo1 & INSN_WRITE_COND_CODE)
6192 && (pinfo2 & INSN_READ_COND_CODE))
6195 /* We don't know exactly what INSN1 does. If INSN2 is
6196 also a coprocessor instruction, assume there must be
6197 a one instruction gap. */
6198 if (pinfo2 & INSN_COP)
6203 /* Check for read-after-write dependencies on the coprocessor
6204 control registers in cases where INSN1 does not need a general
6205 coprocessor delay. This means that INSN1 is a floating point
6206 comparison instruction. */
6207 /* Itbl support may require additional care here. */
6208 else if (!cop_interlocks
6209 && (pinfo1 & INSN_WRITE_COND_CODE)
6210 && (pinfo2 & INSN_READ_COND_CODE))
6214 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6215 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6217 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6218 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6219 || (insn2 && delayed_branch_p (insn2))))
6225 /* Return the number of nops that would be needed to work around the
6226 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6227 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6228 that are contained within the first IGNORE instructions of HIST. */
6231 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6232 const struct mips_cl_insn *insn)
6237 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6238 are not affected by the errata. */
6240 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6241 || strcmp (insn->insn_mo->name, "mtlo") == 0
6242 || strcmp (insn->insn_mo->name, "mthi") == 0))
6245 /* Search for the first MFLO or MFHI. */
6246 for (i = 0; i < MAX_VR4130_NOPS; i++)
6247 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6249 /* Extract the destination register. */
6250 mask = gpr_write_mask (&hist[i]);
6252 /* No nops are needed if INSN reads that register. */
6253 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6256 /* ...or if any of the intervening instructions do. */
6257 for (j = 0; j < i; j++)
6258 if (gpr_read_mask (&hist[j]) & mask)
6262 return MAX_VR4130_NOPS - i;
6267 #define BASE_REG_EQ(INSN1, INSN2) \
6268 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6269 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6271 /* Return the minimum alignment for this store instruction. */
6274 fix_24k_align_to (const struct mips_opcode *mo)
6276 if (strcmp (mo->name, "sh") == 0)
6279 if (strcmp (mo->name, "swc1") == 0
6280 || strcmp (mo->name, "swc2") == 0
6281 || strcmp (mo->name, "sw") == 0
6282 || strcmp (mo->name, "sc") == 0
6283 || strcmp (mo->name, "s.s") == 0)
6286 if (strcmp (mo->name, "sdc1") == 0
6287 || strcmp (mo->name, "sdc2") == 0
6288 || strcmp (mo->name, "s.d") == 0)
6295 struct fix_24k_store_info
6297 /* Immediate offset, if any, for this store instruction. */
6299 /* Alignment required by this store instruction. */
6301 /* True for register offsets. */
6302 int register_offset;
6305 /* Comparison function used by qsort. */
6308 fix_24k_sort (const void *a, const void *b)
6310 const struct fix_24k_store_info *pos1 = a;
6311 const struct fix_24k_store_info *pos2 = b;
6313 return (pos1->off - pos2->off);
6316 /* INSN is a store instruction. Try to record the store information
6317 in STINFO. Return false if the information isn't known. */
6320 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6321 const struct mips_cl_insn *insn)
6323 /* The instruction must have a known offset. */
6324 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6327 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6328 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6332 /* Return the number of nops that would be needed to work around the 24k
6333 "lost data on stores during refill" errata if instruction INSN
6334 immediately followed the 2 instructions described by HIST.
6335 Ignore hazards that are contained within the first IGNORE
6336 instructions of HIST.
6338 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6339 for the data cache refills and store data. The following describes
6340 the scenario where the store data could be lost.
6342 * A data cache miss, due to either a load or a store, causing fill
6343 data to be supplied by the memory subsystem
6344 * The first three doublewords of fill data are returned and written
6346 * A sequence of four stores occurs in consecutive cycles around the
6347 final doubleword of the fill:
6351 * Zero, One or more instructions
6354 The four stores A-D must be to different doublewords of the line that
6355 is being filled. The fourth instruction in the sequence above permits
6356 the fill of the final doubleword to be transferred from the FSB into
6357 the cache. In the sequence above, the stores may be either integer
6358 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6359 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6360 different doublewords on the line. If the floating point unit is
6361 running in 1:2 mode, it is not possible to create the sequence above
6362 using only floating point store instructions.
6364 In this case, the cache line being filled is incorrectly marked
6365 invalid, thereby losing the data from any store to the line that
6366 occurs between the original miss and the completion of the five
6367 cycle sequence shown above.
6369 The workarounds are:
6371 * Run the data cache in write-through mode.
6372 * Insert a non-store instruction between
6373 Store A and Store B or Store B and Store C. */
6376 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6377 const struct mips_cl_insn *insn)
6379 struct fix_24k_store_info pos[3];
6380 int align, i, base_offset;
6385 /* If the previous instruction wasn't a store, there's nothing to
6387 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6390 /* If the instructions after the previous one are unknown, we have
6391 to assume the worst. */
6395 /* Check whether we are dealing with three consecutive stores. */
6396 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6397 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6400 /* If we don't know the relationship between the store addresses,
6401 assume the worst. */
6402 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6403 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6406 if (!fix_24k_record_store_info (&pos[0], insn)
6407 || !fix_24k_record_store_info (&pos[1], &hist[0])
6408 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6411 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6413 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6414 X bytes and such that the base register + X is known to be aligned
6417 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6421 align = pos[0].align_to;
6422 base_offset = pos[0].off;
6423 for (i = 1; i < 3; i++)
6424 if (align < pos[i].align_to)
6426 align = pos[i].align_to;
6427 base_offset = pos[i].off;
6429 for (i = 0; i < 3; i++)
6430 pos[i].off -= base_offset;
6433 pos[0].off &= ~align + 1;
6434 pos[1].off &= ~align + 1;
6435 pos[2].off &= ~align + 1;
6437 /* If any two stores write to the same chunk, they also write to the
6438 same doubleword. The offsets are still sorted at this point. */
6439 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6442 /* A range of at least 9 bytes is needed for the stores to be in
6443 non-overlapping doublewords. */
6444 if (pos[2].off - pos[0].off <= 8)
6447 if (pos[2].off - pos[1].off >= 24
6448 || pos[1].off - pos[0].off >= 24
6449 || pos[2].off - pos[0].off >= 32)
6455 /* Return the number of nops that would be needed if instruction INSN
6456 immediately followed the MAX_NOPS instructions given by HIST,
6457 where HIST[0] is the most recent instruction. Ignore hazards
6458 between INSN and the first IGNORE instructions in HIST.
6460 If INSN is null, return the worse-case number of nops for any
6464 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6465 const struct mips_cl_insn *insn)
6467 int i, nops, tmp_nops;
6470 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6472 tmp_nops = insns_between (hist + i, insn) - i;
6473 if (tmp_nops > nops)
6477 if (mips_fix_vr4130 && !mips_opts.micromips)
6479 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6480 if (tmp_nops > nops)
6484 if (mips_fix_24k && !mips_opts.micromips)
6486 tmp_nops = nops_for_24k (ignore, hist, insn);
6487 if (tmp_nops > nops)
6494 /* The variable arguments provide NUM_INSNS extra instructions that
6495 might be added to HIST. Return the largest number of nops that
6496 would be needed after the extended sequence, ignoring hazards
6497 in the first IGNORE instructions. */
6500 nops_for_sequence (int num_insns, int ignore,
6501 const struct mips_cl_insn *hist, ...)
6504 struct mips_cl_insn buffer[MAX_NOPS];
6505 struct mips_cl_insn *cursor;
6508 va_start (args, hist);
6509 cursor = buffer + num_insns;
6510 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6511 while (cursor > buffer)
6512 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6514 nops = nops_for_insn (ignore, buffer, NULL);
6519 /* Like nops_for_insn, but if INSN is a branch, take into account the
6520 worst-case delay for the branch target. */
6523 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6524 const struct mips_cl_insn *insn)
6528 nops = nops_for_insn (ignore, hist, insn);
6529 if (delayed_branch_p (insn))
6531 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6532 hist, insn, get_delay_slot_nop (insn));
6533 if (tmp_nops > nops)
6536 else if (compact_branch_p (insn))
6538 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6539 if (tmp_nops > nops)
6545 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6548 fix_loongson2f_nop (struct mips_cl_insn * ip)
6550 gas_assert (!HAVE_CODE_COMPRESSION);
6551 if (strcmp (ip->insn_mo->name, "nop") == 0)
6552 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6555 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6556 jr target pc &= 'hffff_ffff_cfff_ffff. */
6559 fix_loongson2f_jump (struct mips_cl_insn * ip)
6561 gas_assert (!HAVE_CODE_COMPRESSION);
6562 if (strcmp (ip->insn_mo->name, "j") == 0
6563 || strcmp (ip->insn_mo->name, "jr") == 0
6564 || strcmp (ip->insn_mo->name, "jalr") == 0)
6572 sreg = EXTRACT_OPERAND (0, RS, *ip);
6573 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6576 ep.X_op = O_constant;
6577 ep.X_add_number = 0xcfff0000;
6578 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6579 ep.X_add_number = 0xffff;
6580 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6581 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6586 fix_loongson2f (struct mips_cl_insn * ip)
6588 if (mips_fix_loongson2f_nop)
6589 fix_loongson2f_nop (ip);
6591 if (mips_fix_loongson2f_jump)
6592 fix_loongson2f_jump (ip);
6595 /* IP is a branch that has a delay slot, and we need to fill it
6596 automatically. Return true if we can do that by swapping IP
6597 with the previous instruction.
6598 ADDRESS_EXPR is an operand of the instruction to be used with
6602 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6603 bfd_reloc_code_real_type *reloc_type)
6605 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6606 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6607 unsigned int fpr_read, prev_fpr_write;
6609 /* -O2 and above is required for this optimization. */
6610 if (mips_optimize < 2)
6613 /* If we have seen .set volatile or .set nomove, don't optimize. */
6614 if (mips_opts.nomove)
6617 /* We can't swap if the previous instruction's position is fixed. */
6618 if (history[0].fixed_p)
6621 /* If the previous previous insn was in a .set noreorder, we can't
6622 swap. Actually, the MIPS assembler will swap in this situation.
6623 However, gcc configured -with-gnu-as will generate code like
6631 in which we can not swap the bne and INSN. If gcc is not configured
6632 -with-gnu-as, it does not output the .set pseudo-ops. */
6633 if (history[1].noreorder_p)
6636 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6637 This means that the previous instruction was a 4-byte one anyhow. */
6638 if (mips_opts.mips16 && history[0].fixp[0])
6641 /* If the branch is itself the target of a branch, we can not swap.
6642 We cheat on this; all we check for is whether there is a label on
6643 this instruction. If there are any branches to anything other than
6644 a label, users must use .set noreorder. */
6645 if (seg_info (now_seg)->label_list)
6648 /* If the previous instruction is in a variant frag other than this
6649 branch's one, we cannot do the swap. This does not apply to
6650 MIPS16 code, which uses variant frags for different purposes. */
6651 if (!mips_opts.mips16
6653 && history[0].frag->fr_type == rs_machine_dependent)
6656 /* We do not swap with instructions that cannot architecturally
6657 be placed in a branch delay slot, such as SYNC or ERET. We
6658 also refrain from swapping with a trap instruction, since it
6659 complicates trap handlers to have the trap instruction be in
6661 prev_pinfo = history[0].insn_mo->pinfo;
6662 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6665 /* Check for conflicts between the branch and the instructions
6666 before the candidate delay slot. */
6667 if (nops_for_insn (0, history + 1, ip) > 0)
6670 /* Check for conflicts between the swapped sequence and the
6671 target of the branch. */
6672 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6675 /* If the branch reads a register that the previous
6676 instruction sets, we can not swap. */
6677 gpr_read = gpr_read_mask (ip);
6678 prev_gpr_write = gpr_write_mask (&history[0]);
6679 if (gpr_read & prev_gpr_write)
6682 fpr_read = fpr_read_mask (ip);
6683 prev_fpr_write = fpr_write_mask (&history[0]);
6684 if (fpr_read & prev_fpr_write)
6687 /* If the branch writes a register that the previous
6688 instruction sets, we can not swap. */
6689 gpr_write = gpr_write_mask (ip);
6690 if (gpr_write & prev_gpr_write)
6693 /* If the branch writes a register that the previous
6694 instruction reads, we can not swap. */
6695 prev_gpr_read = gpr_read_mask (&history[0]);
6696 if (gpr_write & prev_gpr_read)
6699 /* If one instruction sets a condition code and the
6700 other one uses a condition code, we can not swap. */
6701 pinfo = ip->insn_mo->pinfo;
6702 if ((pinfo & INSN_READ_COND_CODE)
6703 && (prev_pinfo & INSN_WRITE_COND_CODE))
6705 if ((pinfo & INSN_WRITE_COND_CODE)
6706 && (prev_pinfo & INSN_READ_COND_CODE))
6709 /* If the previous instruction uses the PC, we can not swap. */
6710 prev_pinfo2 = history[0].insn_mo->pinfo2;
6711 if (prev_pinfo2 & INSN2_READ_PC)
6714 /* If the previous instruction has an incorrect size for a fixed
6715 branch delay slot in microMIPS mode, we cannot swap. */
6716 pinfo2 = ip->insn_mo->pinfo2;
6717 if (mips_opts.micromips
6718 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6719 && insn_length (history) != 2)
6721 if (mips_opts.micromips
6722 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6723 && insn_length (history) != 4)
6726 /* On R5900 short loops need to be fixed by inserting a nop in
6727 the branch delay slots.
6728 A short loop can be terminated too early. */
6729 if (mips_opts.arch == CPU_R5900
6730 /* Check if instruction has a parameter, ignore "j $31". */
6731 && (address_expr != NULL)
6732 /* Parameter must be 16 bit. */
6733 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6734 /* Branch to same segment. */
6735 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6736 /* Branch to same code fragment. */
6737 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6738 /* Can only calculate branch offset if value is known. */
6739 && symbol_constant_p(address_expr->X_add_symbol)
6740 /* Check if branch is really conditional. */
6741 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6742 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6743 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6746 /* Check if loop is shorter than 6 instructions including
6747 branch and delay slot. */
6748 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6755 /* When the loop includes branches or jumps,
6756 it is not a short loop. */
6757 for (i = 0; i < (distance / 4); i++)
6759 if ((history[i].cleared_p)
6760 || delayed_branch_p(&history[i]))
6768 /* Insert nop after branch to fix short loop. */
6777 /* Decide how we should add IP to the instruction stream.
6778 ADDRESS_EXPR is an operand of the instruction to be used with
6781 static enum append_method
6782 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6783 bfd_reloc_code_real_type *reloc_type)
6785 /* The relaxed version of a macro sequence must be inherently
6787 if (mips_relax.sequence == 2)
6790 /* We must not dabble with instructions in a ".set norerorder" block. */
6791 if (mips_opts.noreorder)
6794 /* Otherwise, it's our responsibility to fill branch delay slots. */
6795 if (delayed_branch_p (ip))
6797 if (!branch_likely_p (ip)
6798 && can_swap_branch_p (ip, address_expr, reloc_type))
6801 if (mips_opts.mips16
6802 && ISA_SUPPORTS_MIPS16E
6803 && gpr_read_mask (ip) != 0)
6804 return APPEND_ADD_COMPACT;
6806 return APPEND_ADD_WITH_NOP;
6812 /* IP is a MIPS16 instruction whose opcode we have just changed.
6813 Point IP->insn_mo to the new opcode's definition. */
6816 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6818 const struct mips_opcode *mo, *end;
6820 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6821 for (mo = ip->insn_mo; mo < end; mo++)
6822 if ((ip->insn_opcode & mo->mask) == mo->match)
6830 /* For microMIPS macros, we need to generate a local number label
6831 as the target of branches. */
6832 #define MICROMIPS_LABEL_CHAR '\037'
6833 static unsigned long micromips_target_label;
6834 static char micromips_target_name[32];
6837 micromips_label_name (void)
6839 char *p = micromips_target_name;
6840 char symbol_name_temporary[24];
6848 l = micromips_target_label;
6849 #ifdef LOCAL_LABEL_PREFIX
6850 *p++ = LOCAL_LABEL_PREFIX;
6853 *p++ = MICROMIPS_LABEL_CHAR;
6856 symbol_name_temporary[i++] = l % 10 + '0';
6861 *p++ = symbol_name_temporary[--i];
6864 return micromips_target_name;
6868 micromips_label_expr (expressionS *label_expr)
6870 label_expr->X_op = O_symbol;
6871 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6872 label_expr->X_add_number = 0;
6876 micromips_label_inc (void)
6878 micromips_target_label++;
6879 *micromips_target_name = '\0';
6883 micromips_add_label (void)
6887 s = colon (micromips_label_name ());
6888 micromips_label_inc ();
6889 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6892 /* If assembling microMIPS code, then return the microMIPS reloc
6893 corresponding to the requested one if any. Otherwise return
6894 the reloc unchanged. */
6896 static bfd_reloc_code_real_type
6897 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6899 static const bfd_reloc_code_real_type relocs[][2] =
6901 /* Keep sorted incrementally by the left-hand key. */
6902 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6903 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6904 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6905 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6906 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6907 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6908 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6909 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6910 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6911 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6912 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6913 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6914 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6915 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6916 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6917 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6918 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6919 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6920 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6921 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6922 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6923 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6924 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6925 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6926 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6927 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6928 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6930 bfd_reloc_code_real_type r;
6933 if (!mips_opts.micromips)
6935 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6941 return relocs[i][1];
6946 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6947 Return true on success, storing the resolved value in RESULT. */
6950 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6955 case BFD_RELOC_MIPS_HIGHEST:
6956 case BFD_RELOC_MICROMIPS_HIGHEST:
6957 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6960 case BFD_RELOC_MIPS_HIGHER:
6961 case BFD_RELOC_MICROMIPS_HIGHER:
6962 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6965 case BFD_RELOC_HI16_S:
6966 case BFD_RELOC_MICROMIPS_HI16_S:
6967 case BFD_RELOC_MIPS16_HI16_S:
6968 *result = ((operand + 0x8000) >> 16) & 0xffff;
6971 case BFD_RELOC_HI16:
6972 case BFD_RELOC_MICROMIPS_HI16:
6973 case BFD_RELOC_MIPS16_HI16:
6974 *result = (operand >> 16) & 0xffff;
6977 case BFD_RELOC_LO16:
6978 case BFD_RELOC_MICROMIPS_LO16:
6979 case BFD_RELOC_MIPS16_LO16:
6980 *result = operand & 0xffff;
6983 case BFD_RELOC_UNUSED:
6992 /* Output an instruction. IP is the instruction information.
6993 ADDRESS_EXPR is an operand of the instruction to be used with
6994 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6995 a macro expansion. */
6998 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
6999 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7001 unsigned long prev_pinfo2, pinfo;
7002 bfd_boolean relaxed_branch = FALSE;
7003 enum append_method method;
7004 bfd_boolean relax32;
7007 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7008 fix_loongson2f (ip);
7010 file_ase_mips16 |= mips_opts.mips16;
7011 file_ase_micromips |= mips_opts.micromips;
7013 prev_pinfo2 = history[0].insn_mo->pinfo2;
7014 pinfo = ip->insn_mo->pinfo;
7016 if (mips_opts.micromips
7018 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7019 && micromips_insn_length (ip->insn_mo) != 2)
7020 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7021 && micromips_insn_length (ip->insn_mo) != 4)))
7022 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7023 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7025 if (address_expr == NULL)
7027 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7028 && reloc_type[1] == BFD_RELOC_UNUSED
7029 && reloc_type[2] == BFD_RELOC_UNUSED
7030 && address_expr->X_op == O_constant)
7032 switch (*reloc_type)
7034 case BFD_RELOC_MIPS_JMP:
7038 shift = mips_opts.micromips ? 1 : 2;
7039 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7040 as_bad (_("jump to misaligned address (0x%lx)"),
7041 (unsigned long) address_expr->X_add_number);
7042 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7048 case BFD_RELOC_MIPS16_JMP:
7049 if ((address_expr->X_add_number & 3) != 0)
7050 as_bad (_("jump to misaligned address (0x%lx)"),
7051 (unsigned long) address_expr->X_add_number);
7053 (((address_expr->X_add_number & 0x7c0000) << 3)
7054 | ((address_expr->X_add_number & 0xf800000) >> 7)
7055 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7059 case BFD_RELOC_16_PCREL_S2:
7063 shift = mips_opts.micromips ? 1 : 2;
7064 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7065 as_bad (_("branch to misaligned address (0x%lx)"),
7066 (unsigned long) address_expr->X_add_number);
7067 if (!mips_relax_branch)
7069 if ((address_expr->X_add_number + (1 << (shift + 15)))
7070 & ~((1 << (shift + 16)) - 1))
7071 as_bad (_("branch address range overflow (0x%lx)"),
7072 (unsigned long) address_expr->X_add_number);
7073 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7079 case BFD_RELOC_MIPS_21_PCREL_S2:
7084 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7085 as_bad (_("branch to misaligned address (0x%lx)"),
7086 (unsigned long) address_expr->X_add_number);
7087 if ((address_expr->X_add_number + (1 << (shift + 20)))
7088 & ~((1 << (shift + 21)) - 1))
7089 as_bad (_("branch address range overflow (0x%lx)"),
7090 (unsigned long) address_expr->X_add_number);
7091 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7096 case BFD_RELOC_MIPS_26_PCREL_S2:
7101 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7102 as_bad (_("branch to misaligned address (0x%lx)"),
7103 (unsigned long) address_expr->X_add_number);
7104 if ((address_expr->X_add_number + (1 << (shift + 25)))
7105 & ~((1 << (shift + 26)) - 1))
7106 as_bad (_("branch address range overflow (0x%lx)"),
7107 (unsigned long) address_expr->X_add_number);
7108 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7117 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7120 ip->insn_opcode |= value & 0xffff;
7128 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7130 /* There are a lot of optimizations we could do that we don't.
7131 In particular, we do not, in general, reorder instructions.
7132 If you use gcc with optimization, it will reorder
7133 instructions and generally do much more optimization then we
7134 do here; repeating all that work in the assembler would only
7135 benefit hand written assembly code, and does not seem worth
7137 int nops = (mips_optimize == 0
7138 ? nops_for_insn (0, history, NULL)
7139 : nops_for_insn_or_target (0, history, ip));
7143 unsigned long old_frag_offset;
7146 old_frag = frag_now;
7147 old_frag_offset = frag_now_fix ();
7149 for (i = 0; i < nops; i++)
7150 add_fixed_insn (NOP_INSN);
7151 insert_into_history (0, nops, NOP_INSN);
7155 listing_prev_line ();
7156 /* We may be at the start of a variant frag. In case we
7157 are, make sure there is enough space for the frag
7158 after the frags created by listing_prev_line. The
7159 argument to frag_grow here must be at least as large
7160 as the argument to all other calls to frag_grow in
7161 this file. We don't have to worry about being in the
7162 middle of a variant frag, because the variants insert
7163 all needed nop instructions themselves. */
7167 mips_move_text_labels ();
7169 #ifndef NO_ECOFF_DEBUGGING
7170 if (ECOFF_DEBUGGING)
7171 ecoff_fix_loc (old_frag, old_frag_offset);
7175 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7179 /* Work out how many nops in prev_nop_frag are needed by IP,
7180 ignoring hazards generated by the first prev_nop_frag_since
7182 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7183 gas_assert (nops <= prev_nop_frag_holds);
7185 /* Enforce NOPS as a minimum. */
7186 if (nops > prev_nop_frag_required)
7187 prev_nop_frag_required = nops;
7189 if (prev_nop_frag_holds == prev_nop_frag_required)
7191 /* Settle for the current number of nops. Update the history
7192 accordingly (for the benefit of any future .set reorder code). */
7193 prev_nop_frag = NULL;
7194 insert_into_history (prev_nop_frag_since,
7195 prev_nop_frag_holds, NOP_INSN);
7199 /* Allow this instruction to replace one of the nops that was
7200 tentatively added to prev_nop_frag. */
7201 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7202 prev_nop_frag_holds--;
7203 prev_nop_frag_since++;
7207 method = get_append_method (ip, address_expr, reloc_type);
7208 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7210 dwarf2_emit_insn (0);
7211 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7212 so "move" the instruction address accordingly.
7214 Also, it doesn't seem appropriate for the assembler to reorder .loc
7215 entries. If this instruction is a branch that we are going to swap
7216 with the previous instruction, the two instructions should be
7217 treated as a unit, and the debug information for both instructions
7218 should refer to the start of the branch sequence. Using the
7219 current position is certainly wrong when swapping a 32-bit branch
7220 and a 16-bit delay slot, since the current position would then be
7221 in the middle of a branch. */
7222 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7224 relax32 = (mips_relax_branch
7225 /* Don't try branch relaxation within .set nomacro, or within
7226 .set noat if we use $at for PIC computations. If it turns
7227 out that the branch was out-of-range, we'll get an error. */
7228 && !mips_opts.warn_about_macros
7229 && (mips_opts.at || mips_pic == NO_PIC)
7230 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7231 as they have no complementing branches. */
7232 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7234 if (!HAVE_CODE_COMPRESSION
7237 && *reloc_type == BFD_RELOC_16_PCREL_S2
7238 && delayed_branch_p (ip))
7240 relaxed_branch = TRUE;
7241 add_relaxed_insn (ip, (relaxed_branch_length
7243 uncond_branch_p (ip) ? -1
7244 : branch_likely_p (ip) ? 1
7248 uncond_branch_p (ip),
7249 branch_likely_p (ip),
7250 pinfo & INSN_WRITE_GPR_31,
7252 address_expr->X_add_symbol,
7253 address_expr->X_add_number);
7254 *reloc_type = BFD_RELOC_UNUSED;
7256 else if (mips_opts.micromips
7258 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7259 || *reloc_type > BFD_RELOC_UNUSED)
7260 && (delayed_branch_p (ip) || compact_branch_p (ip))
7261 /* Don't try branch relaxation when users specify
7262 16-bit/32-bit instructions. */
7263 && !forced_insn_length)
7265 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
7266 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7267 int uncond = uncond_branch_p (ip) ? -1 : 0;
7268 int compact = compact_branch_p (ip);
7269 int al = pinfo & INSN_WRITE_GPR_31;
7272 gas_assert (address_expr != NULL);
7273 gas_assert (!mips_relax.sequence);
7275 relaxed_branch = TRUE;
7276 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7277 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
7278 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
7280 address_expr->X_add_symbol,
7281 address_expr->X_add_number);
7282 *reloc_type = BFD_RELOC_UNUSED;
7284 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7286 /* We need to set up a variant frag. */
7287 gas_assert (address_expr != NULL);
7288 add_relaxed_insn (ip, 4, 0,
7290 (*reloc_type - BFD_RELOC_UNUSED,
7291 forced_insn_length == 2, forced_insn_length == 4,
7292 delayed_branch_p (&history[0]),
7293 history[0].mips16_absolute_jump_p),
7294 make_expr_symbol (address_expr), 0);
7296 else if (mips_opts.mips16 && insn_length (ip) == 2)
7298 if (!delayed_branch_p (ip))
7299 /* Make sure there is enough room to swap this instruction with
7300 a following jump instruction. */
7302 add_fixed_insn (ip);
7306 if (mips_opts.mips16
7307 && mips_opts.noreorder
7308 && delayed_branch_p (&history[0]))
7309 as_warn (_("extended instruction in delay slot"));
7311 if (mips_relax.sequence)
7313 /* If we've reached the end of this frag, turn it into a variant
7314 frag and record the information for the instructions we've
7316 if (frag_room () < 4)
7317 relax_close_frag ();
7318 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7321 if (mips_relax.sequence != 2)
7323 if (mips_macro_warning.first_insn_sizes[0] == 0)
7324 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7325 mips_macro_warning.sizes[0] += insn_length (ip);
7326 mips_macro_warning.insns[0]++;
7328 if (mips_relax.sequence != 1)
7330 if (mips_macro_warning.first_insn_sizes[1] == 0)
7331 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7332 mips_macro_warning.sizes[1] += insn_length (ip);
7333 mips_macro_warning.insns[1]++;
7336 if (mips_opts.mips16)
7339 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7341 add_fixed_insn (ip);
7344 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7346 bfd_reloc_code_real_type final_type[3];
7347 reloc_howto_type *howto0;
7348 reloc_howto_type *howto;
7351 /* Perform any necessary conversion to microMIPS relocations
7352 and find out how many relocations there actually are. */
7353 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7354 final_type[i] = micromips_map_reloc (reloc_type[i]);
7356 /* In a compound relocation, it is the final (outermost)
7357 operator that determines the relocated field. */
7358 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7363 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7364 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7365 bfd_get_reloc_size (howto),
7367 howto0 && howto0->pc_relative,
7370 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7371 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7372 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7374 /* These relocations can have an addend that won't fit in
7375 4 octets for 64bit assembly. */
7377 && ! howto->partial_inplace
7378 && (reloc_type[0] == BFD_RELOC_16
7379 || reloc_type[0] == BFD_RELOC_32
7380 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7381 || reloc_type[0] == BFD_RELOC_GPREL16
7382 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7383 || reloc_type[0] == BFD_RELOC_GPREL32
7384 || reloc_type[0] == BFD_RELOC_64
7385 || reloc_type[0] == BFD_RELOC_CTOR
7386 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7387 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7388 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7389 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7390 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7391 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7392 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7393 || hi16_reloc_p (reloc_type[0])
7394 || lo16_reloc_p (reloc_type[0])))
7395 ip->fixp[0]->fx_no_overflow = 1;
7397 /* These relocations can have an addend that won't fit in 2 octets. */
7398 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7399 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7400 ip->fixp[0]->fx_no_overflow = 1;
7402 if (mips_relax.sequence)
7404 if (mips_relax.first_fixup == 0)
7405 mips_relax.first_fixup = ip->fixp[0];
7407 else if (reloc_needs_lo_p (*reloc_type))
7409 struct mips_hi_fixup *hi_fixup;
7411 /* Reuse the last entry if it already has a matching %lo. */
7412 hi_fixup = mips_hi_fixup_list;
7414 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7416 hi_fixup = ((struct mips_hi_fixup *)
7417 xmalloc (sizeof (struct mips_hi_fixup)));
7418 hi_fixup->next = mips_hi_fixup_list;
7419 mips_hi_fixup_list = hi_fixup;
7421 hi_fixup->fixp = ip->fixp[0];
7422 hi_fixup->seg = now_seg;
7425 /* Add fixups for the second and third relocations, if given.
7426 Note that the ABI allows the second relocation to be
7427 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7428 moment we only use RSS_UNDEF, but we could add support
7429 for the others if it ever becomes necessary. */
7430 for (i = 1; i < 3; i++)
7431 if (reloc_type[i] != BFD_RELOC_UNUSED)
7433 ip->fixp[i] = fix_new (ip->frag, ip->where,
7434 ip->fixp[0]->fx_size, NULL, 0,
7435 FALSE, final_type[i]);
7437 /* Use fx_tcbit to mark compound relocs. */
7438 ip->fixp[0]->fx_tcbit = 1;
7439 ip->fixp[i]->fx_tcbit = 1;
7444 /* Update the register mask information. */
7445 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7446 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7451 insert_into_history (0, 1, ip);
7454 case APPEND_ADD_WITH_NOP:
7456 struct mips_cl_insn *nop;
7458 insert_into_history (0, 1, ip);
7459 nop = get_delay_slot_nop (ip);
7460 add_fixed_insn (nop);
7461 insert_into_history (0, 1, nop);
7462 if (mips_relax.sequence)
7463 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7467 case APPEND_ADD_COMPACT:
7468 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7469 gas_assert (mips_opts.mips16);
7470 ip->insn_opcode |= 0x0080;
7471 find_altered_mips16_opcode (ip);
7473 insert_into_history (0, 1, ip);
7478 struct mips_cl_insn delay = history[0];
7479 if (mips_opts.mips16)
7481 know (delay.frag == ip->frag);
7482 move_insn (ip, delay.frag, delay.where);
7483 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7485 else if (relaxed_branch || delay.frag != ip->frag)
7487 /* Add the delay slot instruction to the end of the
7488 current frag and shrink the fixed part of the
7489 original frag. If the branch occupies the tail of
7490 the latter, move it backwards to cover the gap. */
7491 delay.frag->fr_fix -= branch_disp;
7492 if (delay.frag == ip->frag)
7493 move_insn (ip, ip->frag, ip->where - branch_disp);
7494 add_fixed_insn (&delay);
7498 move_insn (&delay, ip->frag,
7499 ip->where - branch_disp + insn_length (ip));
7500 move_insn (ip, history[0].frag, history[0].where);
7504 insert_into_history (0, 1, &delay);
7509 /* If we have just completed an unconditional branch, clear the history. */
7510 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7511 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7515 mips_no_prev_insn ();
7517 for (i = 0; i < ARRAY_SIZE (history); i++)
7518 history[i].cleared_p = 1;
7521 /* We need to emit a label at the end of branch-likely macros. */
7522 if (emit_branch_likely_macro)
7524 emit_branch_likely_macro = FALSE;
7525 micromips_add_label ();
7528 /* We just output an insn, so the next one doesn't have a label. */
7529 mips_clear_insn_labels ();
7532 /* Forget that there was any previous instruction or label.
7533 When BRANCH is true, the branch history is also flushed. */
7536 mips_no_prev_insn (void)
7538 prev_nop_frag = NULL;
7539 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7540 mips_clear_insn_labels ();
7543 /* This function must be called before we emit something other than
7544 instructions. It is like mips_no_prev_insn except that it inserts
7545 any NOPS that might be needed by previous instructions. */
7548 mips_emit_delays (void)
7550 if (! mips_opts.noreorder)
7552 int nops = nops_for_insn (0, history, NULL);
7556 add_fixed_insn (NOP_INSN);
7557 mips_move_text_labels ();
7560 mips_no_prev_insn ();
7563 /* Start a (possibly nested) noreorder block. */
7566 start_noreorder (void)
7568 if (mips_opts.noreorder == 0)
7573 /* None of the instructions before the .set noreorder can be moved. */
7574 for (i = 0; i < ARRAY_SIZE (history); i++)
7575 history[i].fixed_p = 1;
7577 /* Insert any nops that might be needed between the .set noreorder
7578 block and the previous instructions. We will later remove any
7579 nops that turn out not to be needed. */
7580 nops = nops_for_insn (0, history, NULL);
7583 if (mips_optimize != 0)
7585 /* Record the frag which holds the nop instructions, so
7586 that we can remove them if we don't need them. */
7587 frag_grow (nops * NOP_INSN_SIZE);
7588 prev_nop_frag = frag_now;
7589 prev_nop_frag_holds = nops;
7590 prev_nop_frag_required = 0;
7591 prev_nop_frag_since = 0;
7594 for (; nops > 0; --nops)
7595 add_fixed_insn (NOP_INSN);
7597 /* Move on to a new frag, so that it is safe to simply
7598 decrease the size of prev_nop_frag. */
7599 frag_wane (frag_now);
7601 mips_move_text_labels ();
7603 mips_mark_labels ();
7604 mips_clear_insn_labels ();
7606 mips_opts.noreorder++;
7607 mips_any_noreorder = 1;
7610 /* End a nested noreorder block. */
7613 end_noreorder (void)
7615 mips_opts.noreorder--;
7616 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7618 /* Commit to inserting prev_nop_frag_required nops and go back to
7619 handling nop insertion the .set reorder way. */
7620 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7622 insert_into_history (prev_nop_frag_since,
7623 prev_nop_frag_required, NOP_INSN);
7624 prev_nop_frag = NULL;
7628 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7629 higher bits unset. */
7632 normalize_constant_expr (expressionS *ex)
7634 if (ex->X_op == O_constant
7635 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7636 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7640 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7641 all higher bits unset. */
7644 normalize_address_expr (expressionS *ex)
7646 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7647 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7648 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7649 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7653 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7654 Return true if the match was successful.
7656 OPCODE_EXTRA is a value that should be ORed into the opcode
7657 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7658 there are more alternatives after OPCODE and SOFT_MATCH is
7659 as for mips_arg_info. */
7662 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7663 struct mips_operand_token *tokens, unsigned int opcode_extra,
7664 bfd_boolean lax_match, bfd_boolean complete_p)
7667 struct mips_arg_info arg;
7668 const struct mips_operand *operand;
7671 imm_expr.X_op = O_absent;
7672 offset_expr.X_op = O_absent;
7673 offset_reloc[0] = BFD_RELOC_UNUSED;
7674 offset_reloc[1] = BFD_RELOC_UNUSED;
7675 offset_reloc[2] = BFD_RELOC_UNUSED;
7677 create_insn (insn, opcode);
7678 /* When no opcode suffix is specified, assume ".xyzw". */
7679 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7680 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7682 insn->insn_opcode |= opcode_extra;
7683 memset (&arg, 0, sizeof (arg));
7687 arg.last_regno = ILLEGAL_REG;
7688 arg.dest_regno = ILLEGAL_REG;
7689 arg.lax_match = lax_match;
7690 for (args = opcode->args;; ++args)
7692 if (arg.token->type == OT_END)
7694 /* Handle unary instructions in which only one operand is given.
7695 The source is then the same as the destination. */
7696 if (arg.opnum == 1 && *args == ',')
7698 operand = (mips_opts.micromips
7699 ? decode_micromips_operand (args + 1)
7700 : decode_mips_operand (args + 1));
7701 if (operand && mips_optional_operand_p (operand))
7709 /* Treat elided base registers as $0. */
7710 if (strcmp (args, "(b)") == 0)
7718 /* The register suffix is optional. */
7723 /* Fail the match if there were too few operands. */
7727 /* Successful match. */
7730 clear_insn_error ();
7731 if (arg.dest_regno == arg.last_regno
7732 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7736 (0, _("source and destination must be different"));
7737 else if (arg.last_regno == 31)
7739 (0, _("a destination register must be supplied"));
7741 else if (arg.last_regno == 31
7742 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7743 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7744 set_insn_error (0, _("the source register must not be $31"));
7745 check_completed_insn (&arg);
7749 /* Fail the match if the line has too many operands. */
7753 /* Handle characters that need to match exactly. */
7754 if (*args == '(' || *args == ')' || *args == ',')
7756 if (match_char (&arg, *args))
7763 if (arg.token->type == OT_DOUBLE_CHAR
7764 && arg.token->u.ch == *args)
7772 /* Handle special macro operands. Work out the properties of
7781 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7785 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7794 *offset_reloc = BFD_RELOC_MIPS_JMP;
7798 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7802 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7808 if (!match_const_int (&arg, &imm_expr.X_add_number))
7810 imm_expr.X_op = O_constant;
7812 normalize_constant_expr (&imm_expr);
7816 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7818 /* Assume that the offset has been elided and that what
7819 we saw was a base register. The match will fail later
7820 if that assumption turns out to be wrong. */
7821 offset_expr.X_op = O_constant;
7822 offset_expr.X_add_number = 0;
7826 if (!match_expression (&arg, &offset_expr, offset_reloc))
7828 normalize_address_expr (&offset_expr);
7833 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7839 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7845 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7851 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7857 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7861 *offset_reloc = BFD_RELOC_MIPS_JMP;
7865 gas_assert (mips_opts.micromips);
7871 if (!forced_insn_length)
7872 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7874 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7876 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7882 operand = (mips_opts.micromips
7883 ? decode_micromips_operand (args)
7884 : decode_mips_operand (args));
7888 /* Skip prefixes. */
7889 if (*args == '+' || *args == 'm' || *args == '-')
7892 if (mips_optional_operand_p (operand)
7894 && (arg.token[0].type != OT_REG
7895 || arg.token[1].type == OT_END))
7897 /* Assume that the register has been elided and is the
7898 same as the first operand. */
7903 if (!match_operand (&arg, operand))
7908 /* Like match_insn, but for MIPS16. */
7911 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7912 struct mips_operand_token *tokens)
7915 const struct mips_operand *operand;
7916 const struct mips_operand *ext_operand;
7917 struct mips_arg_info arg;
7920 create_insn (insn, opcode);
7921 imm_expr.X_op = O_absent;
7922 offset_expr.X_op = O_absent;
7923 offset_reloc[0] = BFD_RELOC_UNUSED;
7924 offset_reloc[1] = BFD_RELOC_UNUSED;
7925 offset_reloc[2] = BFD_RELOC_UNUSED;
7928 memset (&arg, 0, sizeof (arg));
7932 arg.last_regno = ILLEGAL_REG;
7933 arg.dest_regno = ILLEGAL_REG;
7935 for (args = opcode->args;; ++args)
7939 if (arg.token->type == OT_END)
7943 /* Handle unary instructions in which only one operand is given.
7944 The source is then the same as the destination. */
7945 if (arg.opnum == 1 && *args == ',')
7947 operand = decode_mips16_operand (args[1], FALSE);
7948 if (operand && mips_optional_operand_p (operand))
7956 /* Fail the match if there were too few operands. */
7960 /* Successful match. Stuff the immediate value in now, if
7962 clear_insn_error ();
7963 if (opcode->pinfo == INSN_MACRO)
7965 gas_assert (relax_char == 0 || relax_char == 'p');
7966 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7969 && offset_expr.X_op == O_constant
7970 && calculate_reloc (*offset_reloc,
7971 offset_expr.X_add_number,
7974 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7975 forced_insn_length, &insn->insn_opcode);
7976 offset_expr.X_op = O_absent;
7977 *offset_reloc = BFD_RELOC_UNUSED;
7979 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7981 if (forced_insn_length == 2)
7982 set_insn_error (0, _("invalid unextended operand value"));
7983 forced_insn_length = 4;
7984 insn->insn_opcode |= MIPS16_EXTEND;
7986 else if (relax_char)
7987 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7989 check_completed_insn (&arg);
7993 /* Fail the match if the line has too many operands. */
7997 /* Handle characters that need to match exactly. */
7998 if (*args == '(' || *args == ')' || *args == ',')
8000 if (match_char (&arg, *args))
8018 if (!match_const_int (&arg, &imm_expr.X_add_number))
8020 imm_expr.X_op = O_constant;
8022 normalize_constant_expr (&imm_expr);
8027 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8028 insn->insn_opcode <<= 16;
8032 operand = decode_mips16_operand (c, FALSE);
8036 /* '6' is a special case. It is used for BREAK and SDBBP,
8037 whose operands are only meaningful to the software that decodes
8038 them. This means that there is no architectural reason why
8039 they cannot be prefixed by EXTEND, but in practice,
8040 exception handlers will only look at the instruction
8041 itself. We therefore allow '6' to be extended when
8042 disassembling but not when assembling. */
8043 if (operand->type != OP_PCREL && c != '6')
8045 ext_operand = decode_mips16_operand (c, TRUE);
8046 if (operand != ext_operand)
8048 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8050 offset_expr.X_op = O_constant;
8051 offset_expr.X_add_number = 0;
8056 /* We need the OT_INTEGER check because some MIPS16
8057 immediate variants are listed before the register ones. */
8058 if (arg.token->type != OT_INTEGER
8059 || !match_expression (&arg, &offset_expr, offset_reloc))
8062 /* '8' is used for SLTI(U) and has traditionally not
8063 been allowed to take relocation operators. */
8064 if (offset_reloc[0] != BFD_RELOC_UNUSED
8065 && (ext_operand->size != 16 || c == '8'))
8073 if (mips_optional_operand_p (operand)
8075 && (arg.token[0].type != OT_REG
8076 || arg.token[1].type == OT_END))
8078 /* Assume that the register has been elided and is the
8079 same as the first operand. */
8084 if (!match_operand (&arg, operand))
8089 /* Record that the current instruction is invalid for the current ISA. */
8092 match_invalid_for_isa (void)
8095 (0, _("opcode not supported on this processor: %s (%s)"),
8096 mips_cpu_info_from_arch (mips_opts.arch)->name,
8097 mips_cpu_info_from_isa (mips_opts.isa)->name);
8100 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8101 Return true if a definite match or failure was found, storing any match
8102 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8103 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8104 tried and failed to match under normal conditions and now want to try a
8105 more relaxed match. */
8108 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8109 const struct mips_opcode *past, struct mips_operand_token *tokens,
8110 int opcode_extra, bfd_boolean lax_match)
8112 const struct mips_opcode *opcode;
8113 const struct mips_opcode *invalid_delay_slot;
8114 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8116 /* Search for a match, ignoring alternatives that don't satisfy the
8117 current ISA or forced_length. */
8118 invalid_delay_slot = 0;
8119 seen_valid_for_isa = FALSE;
8120 seen_valid_for_size = FALSE;
8124 gas_assert (strcmp (opcode->name, first->name) == 0);
8125 if (is_opcode_valid (opcode))
8127 seen_valid_for_isa = TRUE;
8128 if (is_size_valid (opcode))
8130 bfd_boolean delay_slot_ok;
8132 seen_valid_for_size = TRUE;
8133 delay_slot_ok = is_delay_slot_valid (opcode);
8134 if (match_insn (insn, opcode, tokens, opcode_extra,
8135 lax_match, delay_slot_ok))
8139 if (!invalid_delay_slot)
8140 invalid_delay_slot = opcode;
8149 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8151 /* If the only matches we found had the wrong length for the delay slot,
8152 pick the first such match. We'll issue an appropriate warning later. */
8153 if (invalid_delay_slot)
8155 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8161 /* Handle the case where we didn't try to match an instruction because
8162 all the alternatives were incompatible with the current ISA. */
8163 if (!seen_valid_for_isa)
8165 match_invalid_for_isa ();
8169 /* Handle the case where we didn't try to match an instruction because
8170 all the alternatives were of the wrong size. */
8171 if (!seen_valid_for_size)
8173 if (mips_opts.insn32)
8174 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8177 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8178 8 * forced_insn_length);
8185 /* Like match_insns, but for MIPS16. */
8188 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8189 struct mips_operand_token *tokens)
8191 const struct mips_opcode *opcode;
8192 bfd_boolean seen_valid_for_isa;
8194 /* Search for a match, ignoring alternatives that don't satisfy the
8195 current ISA. There are no separate entries for extended forms so
8196 we deal with forced_length later. */
8197 seen_valid_for_isa = FALSE;
8201 gas_assert (strcmp (opcode->name, first->name) == 0);
8202 if (is_opcode_valid_16 (opcode))
8204 seen_valid_for_isa = TRUE;
8205 if (match_mips16_insn (insn, opcode, tokens))
8210 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8211 && strcmp (opcode->name, first->name) == 0);
8213 /* Handle the case where we didn't try to match an instruction because
8214 all the alternatives were incompatible with the current ISA. */
8215 if (!seen_valid_for_isa)
8217 match_invalid_for_isa ();
8224 /* Set up global variables for the start of a new macro. */
8229 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8230 memset (&mips_macro_warning.first_insn_sizes, 0,
8231 sizeof (mips_macro_warning.first_insn_sizes));
8232 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8233 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8234 && delayed_branch_p (&history[0]));
8235 switch (history[0].insn_mo->pinfo2
8236 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8238 case INSN2_BRANCH_DELAY_32BIT:
8239 mips_macro_warning.delay_slot_length = 4;
8241 case INSN2_BRANCH_DELAY_16BIT:
8242 mips_macro_warning.delay_slot_length = 2;
8245 mips_macro_warning.delay_slot_length = 0;
8248 mips_macro_warning.first_frag = NULL;
8251 /* Given that a macro is longer than one instruction or of the wrong size,
8252 return the appropriate warning for it. Return null if no warning is
8253 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8254 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8255 and RELAX_NOMACRO. */
8258 macro_warning (relax_substateT subtype)
8260 if (subtype & RELAX_DELAY_SLOT)
8261 return _("macro instruction expanded into multiple instructions"
8262 " in a branch delay slot");
8263 else if (subtype & RELAX_NOMACRO)
8264 return _("macro instruction expanded into multiple instructions");
8265 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8266 | RELAX_DELAY_SLOT_SIZE_SECOND))
8267 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8268 ? _("macro instruction expanded into a wrong size instruction"
8269 " in a 16-bit branch delay slot")
8270 : _("macro instruction expanded into a wrong size instruction"
8271 " in a 32-bit branch delay slot"));
8276 /* Finish up a macro. Emit warnings as appropriate. */
8281 /* Relaxation warning flags. */
8282 relax_substateT subtype = 0;
8284 /* Check delay slot size requirements. */
8285 if (mips_macro_warning.delay_slot_length == 2)
8286 subtype |= RELAX_DELAY_SLOT_16BIT;
8287 if (mips_macro_warning.delay_slot_length != 0)
8289 if (mips_macro_warning.delay_slot_length
8290 != mips_macro_warning.first_insn_sizes[0])
8291 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8292 if (mips_macro_warning.delay_slot_length
8293 != mips_macro_warning.first_insn_sizes[1])
8294 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8297 /* Check instruction count requirements. */
8298 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8300 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8301 subtype |= RELAX_SECOND_LONGER;
8302 if (mips_opts.warn_about_macros)
8303 subtype |= RELAX_NOMACRO;
8304 if (mips_macro_warning.delay_slot_p)
8305 subtype |= RELAX_DELAY_SLOT;
8308 /* If both alternatives fail to fill a delay slot correctly,
8309 emit the warning now. */
8310 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8311 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8316 s = subtype & (RELAX_DELAY_SLOT_16BIT
8317 | RELAX_DELAY_SLOT_SIZE_FIRST
8318 | RELAX_DELAY_SLOT_SIZE_SECOND);
8319 msg = macro_warning (s);
8321 as_warn ("%s", msg);
8325 /* If both implementations are longer than 1 instruction, then emit the
8327 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8332 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8333 msg = macro_warning (s);
8335 as_warn ("%s", msg);
8339 /* If any flags still set, then one implementation might need a warning
8340 and the other either will need one of a different kind or none at all.
8341 Pass any remaining flags over to relaxation. */
8342 if (mips_macro_warning.first_frag != NULL)
8343 mips_macro_warning.first_frag->fr_subtype |= subtype;
8346 /* Instruction operand formats used in macros that vary between
8347 standard MIPS and microMIPS code. */
8349 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8350 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8351 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8352 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8353 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8354 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8355 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8356 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8358 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8359 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8360 : cop12_fmt[mips_opts.micromips])
8361 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8362 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8363 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8364 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8365 : mem12_fmt[mips_opts.micromips])
8366 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8367 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8368 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8370 /* Read a macro's relocation codes from *ARGS and store them in *R.
8371 The first argument in *ARGS will be either the code for a single
8372 relocation or -1 followed by the three codes that make up a
8373 composite relocation. */
8376 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8380 next = va_arg (*args, int);
8382 r[0] = (bfd_reloc_code_real_type) next;
8385 for (i = 0; i < 3; i++)
8386 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8387 /* This function is only used for 16-bit relocation fields.
8388 To make the macro code simpler, treat an unrelocated value
8389 in the same way as BFD_RELOC_LO16. */
8390 if (r[0] == BFD_RELOC_UNUSED)
8391 r[0] = BFD_RELOC_LO16;
8395 /* Build an instruction created by a macro expansion. This is passed
8396 a pointer to the count of instructions created so far, an
8397 expression, the name of the instruction to build, an operand format
8398 string, and corresponding arguments. */
8401 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8403 const struct mips_opcode *mo = NULL;
8404 bfd_reloc_code_real_type r[3];
8405 const struct mips_opcode *amo;
8406 const struct mips_operand *operand;
8407 struct hash_control *hash;
8408 struct mips_cl_insn insn;
8412 va_start (args, fmt);
8414 if (mips_opts.mips16)
8416 mips16_macro_build (ep, name, fmt, &args);
8421 r[0] = BFD_RELOC_UNUSED;
8422 r[1] = BFD_RELOC_UNUSED;
8423 r[2] = BFD_RELOC_UNUSED;
8424 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8425 amo = (struct mips_opcode *) hash_find (hash, name);
8427 gas_assert (strcmp (name, amo->name) == 0);
8431 /* Search until we get a match for NAME. It is assumed here that
8432 macros will never generate MDMX, MIPS-3D, or MT instructions.
8433 We try to match an instruction that fulfils the branch delay
8434 slot instruction length requirement (if any) of the previous
8435 instruction. While doing this we record the first instruction
8436 seen that matches all the other conditions and use it anyway
8437 if the requirement cannot be met; we will issue an appropriate
8438 warning later on. */
8439 if (strcmp (fmt, amo->args) == 0
8440 && amo->pinfo != INSN_MACRO
8441 && is_opcode_valid (amo)
8442 && is_size_valid (amo))
8444 if (is_delay_slot_valid (amo))
8454 gas_assert (amo->name);
8456 while (strcmp (name, amo->name) == 0);
8459 create_insn (&insn, mo);
8472 macro_read_relocs (&args, r);
8473 gas_assert (*r == BFD_RELOC_GPREL16
8474 || *r == BFD_RELOC_MIPS_HIGHER
8475 || *r == BFD_RELOC_HI16_S
8476 || *r == BFD_RELOC_LO16
8477 || *r == BFD_RELOC_MIPS_GOT_OFST);
8481 macro_read_relocs (&args, r);
8485 macro_read_relocs (&args, r);
8486 gas_assert (ep != NULL
8487 && (ep->X_op == O_constant
8488 || (ep->X_op == O_symbol
8489 && (*r == BFD_RELOC_MIPS_HIGHEST
8490 || *r == BFD_RELOC_HI16_S
8491 || *r == BFD_RELOC_HI16
8492 || *r == BFD_RELOC_GPREL16
8493 || *r == BFD_RELOC_MIPS_GOT_HI16
8494 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8498 gas_assert (ep != NULL);
8501 * This allows macro() to pass an immediate expression for
8502 * creating short branches without creating a symbol.
8504 * We don't allow branch relaxation for these branches, as
8505 * they should only appear in ".set nomacro" anyway.
8507 if (ep->X_op == O_constant)
8509 /* For microMIPS we always use relocations for branches.
8510 So we should not resolve immediate values. */
8511 gas_assert (!mips_opts.micromips);
8513 if ((ep->X_add_number & 3) != 0)
8514 as_bad (_("branch to misaligned address (0x%lx)"),
8515 (unsigned long) ep->X_add_number);
8516 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8517 as_bad (_("branch address range overflow (0x%lx)"),
8518 (unsigned long) ep->X_add_number);
8519 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8523 *r = BFD_RELOC_16_PCREL_S2;
8527 gas_assert (ep != NULL);
8528 *r = BFD_RELOC_MIPS_JMP;
8532 operand = (mips_opts.micromips
8533 ? decode_micromips_operand (fmt)
8534 : decode_mips_operand (fmt));
8538 uval = va_arg (args, int);
8539 if (operand->type == OP_CLO_CLZ_DEST)
8540 uval |= (uval << 5);
8541 insn_insert_operand (&insn, operand, uval);
8543 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8549 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8551 append_insn (&insn, ep, r, TRUE);
8555 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8558 struct mips_opcode *mo;
8559 struct mips_cl_insn insn;
8560 const struct mips_operand *operand;
8561 bfd_reloc_code_real_type r[3]
8562 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8564 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8566 gas_assert (strcmp (name, mo->name) == 0);
8568 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8571 gas_assert (mo->name);
8572 gas_assert (strcmp (name, mo->name) == 0);
8575 create_insn (&insn, mo);
8613 gas_assert (ep != NULL);
8615 if (ep->X_op != O_constant)
8616 *r = (int) BFD_RELOC_UNUSED + c;
8617 else if (calculate_reloc (*r, ep->X_add_number, &value))
8619 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8621 *r = BFD_RELOC_UNUSED;
8627 operand = decode_mips16_operand (c, FALSE);
8631 insn_insert_operand (&insn, operand, va_arg (*args, int));
8636 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8638 append_insn (&insn, ep, r, TRUE);
8642 * Generate a "jalr" instruction with a relocation hint to the called
8643 * function. This occurs in NewABI PIC code.
8646 macro_build_jalr (expressionS *ep, int cprestore)
8648 static const bfd_reloc_code_real_type jalr_relocs[2]
8649 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8650 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8654 if (MIPS_JALR_HINT_P (ep))
8659 if (mips_opts.micromips)
8661 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8662 ? "jalr" : "jalrs");
8663 if (MIPS_JALR_HINT_P (ep)
8665 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8666 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8668 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8671 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
8672 if (MIPS_JALR_HINT_P (ep))
8673 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
8677 * Generate a "lui" instruction.
8680 macro_build_lui (expressionS *ep, int regnum)
8682 gas_assert (! mips_opts.mips16);
8684 if (ep->X_op != O_constant)
8686 gas_assert (ep->X_op == O_symbol);
8687 /* _gp_disp is a special case, used from s_cpload.
8688 __gnu_local_gp is used if mips_no_shared. */
8689 gas_assert (mips_pic == NO_PIC
8691 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8692 || (! mips_in_shared
8693 && strcmp (S_GET_NAME (ep->X_add_symbol),
8694 "__gnu_local_gp") == 0));
8697 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
8700 /* Generate a sequence of instructions to do a load or store from a constant
8701 offset off of a base register (breg) into/from a target register (treg),
8702 using AT if necessary. */
8704 macro_build_ldst_constoffset (expressionS *ep, const char *op,
8705 int treg, int breg, int dbl)
8707 gas_assert (ep->X_op == O_constant);
8709 /* Sign-extending 32-bit constants makes their handling easier. */
8711 normalize_constant_expr (ep);
8713 /* Right now, this routine can only handle signed 32-bit constants. */
8714 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
8715 as_warn (_("operand overflow"));
8717 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8719 /* Signed 16-bit offset will fit in the op. Easy! */
8720 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8724 /* 32-bit offset, need multiple instructions and AT, like:
8725 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8726 addu $tempreg,$tempreg,$breg
8727 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8728 to handle the complete offset. */
8729 macro_build_lui (ep, AT);
8730 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8731 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8734 as_bad (_("macro used $at after \".set noat\""));
8739 * Generates code to set the $at register to true (one)
8740 * if reg is less than the immediate expression.
8743 set_at (int reg, int unsignedp)
8745 if (imm_expr.X_add_number >= -0x8000
8746 && imm_expr.X_add_number < 0x8000)
8747 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8748 AT, reg, BFD_RELOC_LO16);
8751 load_register (AT, &imm_expr, GPR_SIZE == 64);
8752 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8756 /* Count the leading zeroes by performing a binary chop. This is a
8757 bulky bit of source, but performance is a LOT better for the
8758 majority of values than a simple loop to count the bits:
8759 for (lcnt = 0; (lcnt < 32); lcnt++)
8760 if ((v) & (1 << (31 - lcnt)))
8762 However it is not code size friendly, and the gain will drop a bit
8763 on certain cached systems.
8765 #define COUNT_TOP_ZEROES(v) \
8766 (((v) & ~0xffff) == 0 \
8767 ? ((v) & ~0xff) == 0 \
8768 ? ((v) & ~0xf) == 0 \
8769 ? ((v) & ~0x3) == 0 \
8770 ? ((v) & ~0x1) == 0 \
8775 : ((v) & ~0x7) == 0 \
8778 : ((v) & ~0x3f) == 0 \
8779 ? ((v) & ~0x1f) == 0 \
8782 : ((v) & ~0x7f) == 0 \
8785 : ((v) & ~0xfff) == 0 \
8786 ? ((v) & ~0x3ff) == 0 \
8787 ? ((v) & ~0x1ff) == 0 \
8790 : ((v) & ~0x7ff) == 0 \
8793 : ((v) & ~0x3fff) == 0 \
8794 ? ((v) & ~0x1fff) == 0 \
8797 : ((v) & ~0x7fff) == 0 \
8800 : ((v) & ~0xffffff) == 0 \
8801 ? ((v) & ~0xfffff) == 0 \
8802 ? ((v) & ~0x3ffff) == 0 \
8803 ? ((v) & ~0x1ffff) == 0 \
8806 : ((v) & ~0x7ffff) == 0 \
8809 : ((v) & ~0x3fffff) == 0 \
8810 ? ((v) & ~0x1fffff) == 0 \
8813 : ((v) & ~0x7fffff) == 0 \
8816 : ((v) & ~0xfffffff) == 0 \
8817 ? ((v) & ~0x3ffffff) == 0 \
8818 ? ((v) & ~0x1ffffff) == 0 \
8821 : ((v) & ~0x7ffffff) == 0 \
8824 : ((v) & ~0x3fffffff) == 0 \
8825 ? ((v) & ~0x1fffffff) == 0 \
8828 : ((v) & ~0x7fffffff) == 0 \
8833 * This routine generates the least number of instructions necessary to load
8834 * an absolute expression value into a register.
8837 load_register (int reg, expressionS *ep, int dbl)
8840 expressionS hi32, lo32;
8842 if (ep->X_op != O_big)
8844 gas_assert (ep->X_op == O_constant);
8846 /* Sign-extending 32-bit constants makes their handling easier. */
8848 normalize_constant_expr (ep);
8850 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8852 /* We can handle 16 bit signed values with an addiu to
8853 $zero. No need to ever use daddiu here, since $zero and
8854 the result are always correct in 32 bit mode. */
8855 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8858 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8860 /* We can handle 16 bit unsigned values with an ori to
8862 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8865 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8867 /* 32 bit values require an lui. */
8868 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8869 if ((ep->X_add_number & 0xffff) != 0)
8870 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8875 /* The value is larger than 32 bits. */
8877 if (!dbl || GPR_SIZE == 32)
8881 sprintf_vma (value, ep->X_add_number);
8882 as_bad (_("number (0x%s) larger than 32 bits"), value);
8883 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8887 if (ep->X_op != O_big)
8890 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8891 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8892 hi32.X_add_number &= 0xffffffff;
8894 lo32.X_add_number &= 0xffffffff;
8898 gas_assert (ep->X_add_number > 2);
8899 if (ep->X_add_number == 3)
8900 generic_bignum[3] = 0;
8901 else if (ep->X_add_number > 4)
8902 as_bad (_("number larger than 64 bits"));
8903 lo32.X_op = O_constant;
8904 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8905 hi32.X_op = O_constant;
8906 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8909 if (hi32.X_add_number == 0)
8914 unsigned long hi, lo;
8916 if (hi32.X_add_number == (offsetT) 0xffffffff)
8918 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8920 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8923 if (lo32.X_add_number & 0x80000000)
8925 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8926 if (lo32.X_add_number & 0xffff)
8927 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8932 /* Check for 16bit shifted constant. We know that hi32 is
8933 non-zero, so start the mask on the first bit of the hi32
8938 unsigned long himask, lomask;
8942 himask = 0xffff >> (32 - shift);
8943 lomask = (0xffff << shift) & 0xffffffff;
8947 himask = 0xffff << (shift - 32);
8950 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8951 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8955 tmp.X_op = O_constant;
8957 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8958 | (lo32.X_add_number >> shift));
8960 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
8961 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8962 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8963 reg, reg, (shift >= 32) ? shift - 32 : shift);
8968 while (shift <= (64 - 16));
8970 /* Find the bit number of the lowest one bit, and store the
8971 shifted value in hi/lo. */
8972 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8973 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8977 while ((lo & 1) == 0)
8982 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8988 while ((hi & 1) == 0)
8997 /* Optimize if the shifted value is a (power of 2) - 1. */
8998 if ((hi == 0 && ((lo + 1) & lo) == 0)
8999 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9001 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9006 /* This instruction will set the register to be all
9008 tmp.X_op = O_constant;
9009 tmp.X_add_number = (offsetT) -1;
9010 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9014 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9015 reg, reg, (bit >= 32) ? bit - 32 : bit);
9017 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9018 reg, reg, (shift >= 32) ? shift - 32 : shift);
9023 /* Sign extend hi32 before calling load_register, because we can
9024 generally get better code when we load a sign extended value. */
9025 if ((hi32.X_add_number & 0x80000000) != 0)
9026 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9027 load_register (reg, &hi32, 0);
9030 if ((lo32.X_add_number & 0xffff0000) == 0)
9034 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9042 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9044 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9045 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9051 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9055 mid16.X_add_number >>= 16;
9056 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9057 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9060 if ((lo32.X_add_number & 0xffff) != 0)
9061 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9065 load_delay_nop (void)
9067 if (!gpr_interlocks)
9068 macro_build (NULL, "nop", "");
9071 /* Load an address into a register. */
9074 load_address (int reg, expressionS *ep, int *used_at)
9076 if (ep->X_op != O_constant
9077 && ep->X_op != O_symbol)
9079 as_bad (_("expression too complex"));
9080 ep->X_op = O_constant;
9083 if (ep->X_op == O_constant)
9085 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9089 if (mips_pic == NO_PIC)
9091 /* If this is a reference to a GP relative symbol, we want
9092 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9094 lui $reg,<sym> (BFD_RELOC_HI16_S)
9095 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9096 If we have an addend, we always use the latter form.
9098 With 64bit address space and a usable $at we want
9099 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9100 lui $at,<sym> (BFD_RELOC_HI16_S)
9101 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9102 daddiu $at,<sym> (BFD_RELOC_LO16)
9106 If $at is already in use, we use a path which is suboptimal
9107 on superscalar processors.
9108 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9109 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9111 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9113 daddiu $reg,<sym> (BFD_RELOC_LO16)
9115 For GP relative symbols in 64bit address space we can use
9116 the same sequence as in 32bit address space. */
9117 if (HAVE_64BIT_SYMBOLS)
9119 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9120 && !nopic_need_relax (ep->X_add_symbol, 1))
9122 relax_start (ep->X_add_symbol);
9123 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9124 mips_gp_register, BFD_RELOC_GPREL16);
9128 if (*used_at == 0 && mips_opts.at)
9130 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9131 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9132 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9133 BFD_RELOC_MIPS_HIGHER);
9134 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9135 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9136 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9141 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9142 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9143 BFD_RELOC_MIPS_HIGHER);
9144 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9145 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9146 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9147 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9150 if (mips_relax.sequence)
9155 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9156 && !nopic_need_relax (ep->X_add_symbol, 1))
9158 relax_start (ep->X_add_symbol);
9159 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9160 mips_gp_register, BFD_RELOC_GPREL16);
9163 macro_build_lui (ep, reg);
9164 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9165 reg, reg, BFD_RELOC_LO16);
9166 if (mips_relax.sequence)
9170 else if (!mips_big_got)
9174 /* If this is a reference to an external symbol, we want
9175 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9177 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9179 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9180 If there is a constant, it must be added in after.
9182 If we have NewABI, we want
9183 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9184 unless we're referencing a global symbol with a non-zero
9185 offset, in which case cst must be added separately. */
9188 if (ep->X_add_number)
9190 ex.X_add_number = ep->X_add_number;
9191 ep->X_add_number = 0;
9192 relax_start (ep->X_add_symbol);
9193 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9194 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9195 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9196 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9197 ex.X_op = O_constant;
9198 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9199 reg, reg, BFD_RELOC_LO16);
9200 ep->X_add_number = ex.X_add_number;
9203 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9204 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9205 if (mips_relax.sequence)
9210 ex.X_add_number = ep->X_add_number;
9211 ep->X_add_number = 0;
9212 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9213 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9215 relax_start (ep->X_add_symbol);
9217 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9221 if (ex.X_add_number != 0)
9223 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9224 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9225 ex.X_op = O_constant;
9226 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9227 reg, reg, BFD_RELOC_LO16);
9231 else if (mips_big_got)
9235 /* This is the large GOT case. If this is a reference to an
9236 external symbol, we want
9237 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9239 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9241 Otherwise, for a reference to a local symbol in old ABI, we want
9242 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9244 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9245 If there is a constant, it must be added in after.
9247 In the NewABI, for local symbols, with or without offsets, we want:
9248 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9249 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9253 ex.X_add_number = ep->X_add_number;
9254 ep->X_add_number = 0;
9255 relax_start (ep->X_add_symbol);
9256 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9257 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9258 reg, reg, mips_gp_register);
9259 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9260 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9261 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9262 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9263 else if (ex.X_add_number)
9265 ex.X_op = O_constant;
9266 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9270 ep->X_add_number = ex.X_add_number;
9272 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9273 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9274 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9275 BFD_RELOC_MIPS_GOT_OFST);
9280 ex.X_add_number = ep->X_add_number;
9281 ep->X_add_number = 0;
9282 relax_start (ep->X_add_symbol);
9283 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9284 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9285 reg, reg, mips_gp_register);
9286 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9287 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9289 if (reg_needs_delay (mips_gp_register))
9291 /* We need a nop before loading from $gp. This special
9292 check is required because the lui which starts the main
9293 instruction stream does not refer to $gp, and so will not
9294 insert the nop which may be required. */
9295 macro_build (NULL, "nop", "");
9297 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9298 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9300 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9304 if (ex.X_add_number != 0)
9306 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9307 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9308 ex.X_op = O_constant;
9309 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9317 if (!mips_opts.at && *used_at == 1)
9318 as_bad (_("macro used $at after \".set noat\""));
9321 /* Move the contents of register SOURCE into register DEST. */
9324 move_register (int dest, int source)
9326 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9327 instruction specifically requires a 32-bit one. */
9328 if (mips_opts.micromips
9329 && !mips_opts.insn32
9330 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9331 macro_build (NULL, "move", "mp,mj", dest, source);
9333 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9336 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9337 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9338 The two alternatives are:
9340 Global symbol Local sybmol
9341 ------------- ------------
9342 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9344 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9346 load_got_offset emits the first instruction and add_got_offset
9347 emits the second for a 16-bit offset or add_got_offset_hilo emits
9348 a sequence to add a 32-bit offset using a scratch register. */
9351 load_got_offset (int dest, expressionS *local)
9356 global.X_add_number = 0;
9358 relax_start (local->X_add_symbol);
9359 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9360 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9362 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9363 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9368 add_got_offset (int dest, expressionS *local)
9372 global.X_op = O_constant;
9373 global.X_op_symbol = NULL;
9374 global.X_add_symbol = NULL;
9375 global.X_add_number = local->X_add_number;
9377 relax_start (local->X_add_symbol);
9378 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9379 dest, dest, BFD_RELOC_LO16);
9381 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9386 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9389 int hold_mips_optimize;
9391 global.X_op = O_constant;
9392 global.X_op_symbol = NULL;
9393 global.X_add_symbol = NULL;
9394 global.X_add_number = local->X_add_number;
9396 relax_start (local->X_add_symbol);
9397 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9399 /* Set mips_optimize around the lui instruction to avoid
9400 inserting an unnecessary nop after the lw. */
9401 hold_mips_optimize = mips_optimize;
9403 macro_build_lui (&global, tmp);
9404 mips_optimize = hold_mips_optimize;
9405 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9408 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9411 /* Emit a sequence of instructions to emulate a branch likely operation.
9412 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9413 is its complementing branch with the original condition negated.
9414 CALL is set if the original branch specified the link operation.
9415 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9417 Code like this is produced in the noreorder mode:
9422 delay slot (executed only if branch taken)
9430 delay slot (executed only if branch taken)
9433 In the reorder mode the delay slot would be filled with a nop anyway,
9434 so code produced is simply:
9439 This function is used when producing code for the microMIPS ASE that
9440 does not implement branch likely instructions in hardware. */
9443 macro_build_branch_likely (const char *br, const char *brneg,
9444 int call, expressionS *ep, const char *fmt,
9445 unsigned int sreg, unsigned int treg)
9447 int noreorder = mips_opts.noreorder;
9450 gas_assert (mips_opts.micromips);
9454 micromips_label_expr (&expr1);
9455 macro_build (&expr1, brneg, fmt, sreg, treg);
9456 macro_build (NULL, "nop", "");
9457 macro_build (ep, call ? "bal" : "b", "p");
9459 /* Set to true so that append_insn adds a label. */
9460 emit_branch_likely_macro = TRUE;
9464 macro_build (ep, br, fmt, sreg, treg);
9465 macro_build (NULL, "nop", "");
9470 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9471 the condition code tested. EP specifies the branch target. */
9474 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9501 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9504 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9505 the register tested. EP specifies the branch target. */
9508 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9510 const char *brneg = NULL;
9520 br = mips_opts.micromips ? "bgez" : "bgezl";
9524 gas_assert (mips_opts.micromips);
9525 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9533 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9540 br = mips_opts.micromips ? "blez" : "blezl";
9547 br = mips_opts.micromips ? "bltz" : "bltzl";
9551 gas_assert (mips_opts.micromips);
9552 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9559 if (mips_opts.micromips && brneg)
9560 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9562 macro_build (ep, br, "s,p", sreg);
9565 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9566 TREG as the registers tested. EP specifies the branch target. */
9569 macro_build_branch_rsrt (int type, expressionS *ep,
9570 unsigned int sreg, unsigned int treg)
9572 const char *brneg = NULL;
9584 br = mips_opts.micromips ? "beq" : "beql";
9593 br = mips_opts.micromips ? "bne" : "bnel";
9599 if (mips_opts.micromips && brneg)
9600 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9602 macro_build (ep, br, "s,t,p", sreg, treg);
9605 /* Return the high part that should be loaded in order to make the low
9606 part of VALUE accessible using an offset of OFFBITS bits. */
9609 offset_high_part (offsetT value, unsigned int offbits)
9616 bias = 1 << (offbits - 1);
9617 low_mask = bias * 2 - 1;
9618 return (value + bias) & ~low_mask;
9621 /* Return true if the value stored in offset_expr and offset_reloc
9622 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9623 amount that the caller wants to add without inducing overflow
9624 and ALIGN is the known alignment of the value in bytes. */
9627 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9631 /* Accept any relocation operator if overflow isn't a concern. */
9632 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9635 /* These relocations are guaranteed not to overflow in correct links. */
9636 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9637 || gprel16_reloc_p (*offset_reloc))
9640 if (offset_expr.X_op == O_constant
9641 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9642 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9649 * This routine implements the seemingly endless macro or synthesized
9650 * instructions and addressing modes in the mips assembly language. Many
9651 * of these macros are simple and are similar to each other. These could
9652 * probably be handled by some kind of table or grammar approach instead of
9653 * this verbose method. Others are not simple macros but are more like
9654 * optimizing code generation.
9655 * One interesting optimization is when several store macros appear
9656 * consecutively that would load AT with the upper half of the same address.
9657 * The ensuing load upper instructions are ommited. This implies some kind
9658 * of global optimization. We currently only optimize within a single macro.
9659 * For many of the load and store macros if the address is specified as a
9660 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9661 * first load register 'at' with zero and use it as the base register. The
9662 * mips assembler simply uses register $zero. Just one tiny optimization
9666 macro (struct mips_cl_insn *ip, char *str)
9668 const struct mips_operand_array *operands;
9669 unsigned int breg, i;
9670 unsigned int tempreg;
9673 expressionS label_expr;
9688 bfd_boolean large_offset;
9690 int hold_mips_optimize;
9692 unsigned int op[MAX_OPERANDS];
9694 gas_assert (! mips_opts.mips16);
9696 operands = insn_operands (ip);
9697 for (i = 0; i < MAX_OPERANDS; i++)
9698 if (operands->operand[i])
9699 op[i] = insn_extract_operand (ip, operands->operand[i]);
9703 mask = ip->insn_mo->mask;
9705 label_expr.X_op = O_constant;
9706 label_expr.X_op_symbol = NULL;
9707 label_expr.X_add_symbol = NULL;
9708 label_expr.X_add_number = 0;
9710 expr1.X_op = O_constant;
9711 expr1.X_op_symbol = NULL;
9712 expr1.X_add_symbol = NULL;
9713 expr1.X_add_number = 1;
9729 if (mips_opts.micromips)
9730 micromips_label_expr (&label_expr);
9732 label_expr.X_add_number = 8;
9733 macro_build (&label_expr, "bgez", "s,p", op[1]);
9735 macro_build (NULL, "nop", "");
9737 move_register (op[0], op[1]);
9738 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
9739 if (mips_opts.micromips)
9740 micromips_add_label ();
9757 if (!mips_opts.micromips)
9759 if (imm_expr.X_add_number >= -0x200
9760 && imm_expr.X_add_number < 0x200)
9762 macro_build (NULL, s, "t,r,.", op[0], op[1],
9763 (int) imm_expr.X_add_number);
9772 if (imm_expr.X_add_number >= -0x8000
9773 && imm_expr.X_add_number < 0x8000)
9775 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9780 load_register (AT, &imm_expr, dbl);
9781 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9800 if (imm_expr.X_add_number >= 0
9801 && imm_expr.X_add_number < 0x10000)
9803 if (mask != M_NOR_I)
9804 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9807 macro_build (&imm_expr, "ori", "t,r,i",
9808 op[0], op[1], BFD_RELOC_LO16);
9809 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9815 load_register (AT, &imm_expr, GPR_SIZE == 64);
9816 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9820 switch (imm_expr.X_add_number)
9823 macro_build (NULL, "nop", "");
9826 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9830 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9831 (int) imm_expr.X_add_number);
9834 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9835 (unsigned long) imm_expr.X_add_number);
9844 gas_assert (mips_opts.micromips);
9845 macro_build_branch_ccl (mask, &offset_expr,
9846 EXTRACT_OPERAND (1, BCC, *ip));
9853 if (imm_expr.X_add_number == 0)
9859 load_register (op[1], &imm_expr, GPR_SIZE == 64);
9864 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9871 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9872 else if (op[0] == 0)
9873 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9877 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9878 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9879 &offset_expr, AT, ZERO);
9889 macro_build_branch_rs (mask, &offset_expr, op[0]);
9895 /* Check for > max integer. */
9896 if (imm_expr.X_add_number >= GPR_SMAX)
9899 /* Result is always false. */
9901 macro_build (NULL, "nop", "");
9903 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9906 ++imm_expr.X_add_number;
9910 if (mask == M_BGEL_I)
9912 if (imm_expr.X_add_number == 0)
9914 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9915 &offset_expr, op[0]);
9918 if (imm_expr.X_add_number == 1)
9920 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9921 &offset_expr, op[0]);
9924 if (imm_expr.X_add_number <= GPR_SMIN)
9927 /* result is always true */
9928 as_warn (_("branch %s is always true"), ip->insn_mo->name);
9929 macro_build (&offset_expr, "b", "p");
9934 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9935 &offset_expr, AT, ZERO);
9943 else if (op[0] == 0)
9944 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9945 &offset_expr, ZERO, op[1]);
9949 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9950 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9951 &offset_expr, AT, ZERO);
9960 && imm_expr.X_add_number == -1))
9962 ++imm_expr.X_add_number;
9966 if (mask == M_BGEUL_I)
9968 if (imm_expr.X_add_number == 0)
9970 else if (imm_expr.X_add_number == 1)
9971 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9972 &offset_expr, op[0], ZERO);
9977 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9978 &offset_expr, AT, ZERO);
9986 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9987 else if (op[0] == 0)
9988 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
9992 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9993 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9994 &offset_expr, AT, ZERO);
10002 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10003 &offset_expr, op[0], ZERO);
10004 else if (op[0] == 0)
10009 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10010 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10011 &offset_expr, AT, ZERO);
10019 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10020 else if (op[0] == 0)
10021 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10025 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10026 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10027 &offset_expr, AT, ZERO);
10034 if (imm_expr.X_add_number >= GPR_SMAX)
10036 ++imm_expr.X_add_number;
10040 if (mask == M_BLTL_I)
10042 if (imm_expr.X_add_number == 0)
10043 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10044 else if (imm_expr.X_add_number == 1)
10045 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10050 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10051 &offset_expr, AT, ZERO);
10059 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10060 &offset_expr, op[0], ZERO);
10061 else if (op[0] == 0)
10066 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10067 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10068 &offset_expr, AT, ZERO);
10077 && imm_expr.X_add_number == -1))
10079 ++imm_expr.X_add_number;
10083 if (mask == M_BLTUL_I)
10085 if (imm_expr.X_add_number == 0)
10087 else if (imm_expr.X_add_number == 1)
10088 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10089 &offset_expr, op[0], ZERO);
10094 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10095 &offset_expr, AT, ZERO);
10103 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10104 else if (op[0] == 0)
10105 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10109 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10110 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10111 &offset_expr, AT, ZERO);
10120 else if (op[0] == 0)
10121 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10122 &offset_expr, ZERO, op[1]);
10126 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10127 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10128 &offset_expr, AT, ZERO);
10144 as_warn (_("divide by zero"));
10146 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10148 macro_build (NULL, "break", BRK_FMT, 7);
10152 start_noreorder ();
10155 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10156 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10160 if (mips_opts.micromips)
10161 micromips_label_expr (&label_expr);
10163 label_expr.X_add_number = 8;
10164 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10165 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10166 macro_build (NULL, "break", BRK_FMT, 7);
10167 if (mips_opts.micromips)
10168 micromips_add_label ();
10170 expr1.X_add_number = -1;
10172 load_register (AT, &expr1, dbl);
10173 if (mips_opts.micromips)
10174 micromips_label_expr (&label_expr);
10176 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10177 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10180 expr1.X_add_number = 1;
10181 load_register (AT, &expr1, dbl);
10182 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10186 expr1.X_add_number = 0x80000000;
10187 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10191 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10192 /* We want to close the noreorder block as soon as possible, so
10193 that later insns are available for delay slot filling. */
10198 if (mips_opts.micromips)
10199 micromips_label_expr (&label_expr);
10201 label_expr.X_add_number = 8;
10202 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10203 macro_build (NULL, "nop", "");
10205 /* We want to close the noreorder block as soon as possible, so
10206 that later insns are available for delay slot filling. */
10209 macro_build (NULL, "break", BRK_FMT, 6);
10211 if (mips_opts.micromips)
10212 micromips_add_label ();
10213 macro_build (NULL, s, MFHL_FMT, op[0]);
10252 if (imm_expr.X_add_number == 0)
10254 as_warn (_("divide by zero"));
10256 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10258 macro_build (NULL, "break", BRK_FMT, 7);
10261 if (imm_expr.X_add_number == 1)
10263 if (strcmp (s2, "mflo") == 0)
10264 move_register (op[0], op[1]);
10266 move_register (op[0], ZERO);
10269 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10271 if (strcmp (s2, "mflo") == 0)
10272 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10274 move_register (op[0], ZERO);
10279 load_register (AT, &imm_expr, dbl);
10280 macro_build (NULL, s, "z,s,t", op[1], AT);
10281 macro_build (NULL, s2, MFHL_FMT, op[0]);
10300 start_noreorder ();
10303 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10304 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10305 /* We want to close the noreorder block as soon as possible, so
10306 that later insns are available for delay slot filling. */
10311 if (mips_opts.micromips)
10312 micromips_label_expr (&label_expr);
10314 label_expr.X_add_number = 8;
10315 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10316 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10318 /* We want to close the noreorder block as soon as possible, so
10319 that later insns are available for delay slot filling. */
10321 macro_build (NULL, "break", BRK_FMT, 7);
10322 if (mips_opts.micromips)
10323 micromips_add_label ();
10325 macro_build (NULL, s2, MFHL_FMT, op[0]);
10337 /* Load the address of a symbol into a register. If breg is not
10338 zero, we then add a base register to it. */
10341 if (dbl && GPR_SIZE == 32)
10342 as_warn (_("dla used to load 32-bit register; recommend using la "
10345 if (!dbl && HAVE_64BIT_OBJECTS)
10346 as_warn (_("la used to load 64-bit address; recommend using dla "
10349 if (small_offset_p (0, align, 16))
10351 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10352 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10356 if (mips_opts.at && (op[0] == breg))
10364 if (offset_expr.X_op != O_symbol
10365 && offset_expr.X_op != O_constant)
10367 as_bad (_("expression too complex"));
10368 offset_expr.X_op = O_constant;
10371 if (offset_expr.X_op == O_constant)
10372 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10373 else if (mips_pic == NO_PIC)
10375 /* If this is a reference to a GP relative symbol, we want
10376 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10378 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10379 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10380 If we have a constant, we need two instructions anyhow,
10381 so we may as well always use the latter form.
10383 With 64bit address space and a usable $at we want
10384 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10385 lui $at,<sym> (BFD_RELOC_HI16_S)
10386 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10387 daddiu $at,<sym> (BFD_RELOC_LO16)
10389 daddu $tempreg,$tempreg,$at
10391 If $at is already in use, we use a path which is suboptimal
10392 on superscalar processors.
10393 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10394 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10396 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10398 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10400 For GP relative symbols in 64bit address space we can use
10401 the same sequence as in 32bit address space. */
10402 if (HAVE_64BIT_SYMBOLS)
10404 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10405 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10407 relax_start (offset_expr.X_add_symbol);
10408 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10409 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10413 if (used_at == 0 && mips_opts.at)
10415 macro_build (&offset_expr, "lui", LUI_FMT,
10416 tempreg, BFD_RELOC_MIPS_HIGHEST);
10417 macro_build (&offset_expr, "lui", LUI_FMT,
10418 AT, BFD_RELOC_HI16_S);
10419 macro_build (&offset_expr, "daddiu", "t,r,j",
10420 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10421 macro_build (&offset_expr, "daddiu", "t,r,j",
10422 AT, AT, BFD_RELOC_LO16);
10423 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10424 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10429 macro_build (&offset_expr, "lui", LUI_FMT,
10430 tempreg, BFD_RELOC_MIPS_HIGHEST);
10431 macro_build (&offset_expr, "daddiu", "t,r,j",
10432 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10433 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10434 macro_build (&offset_expr, "daddiu", "t,r,j",
10435 tempreg, tempreg, BFD_RELOC_HI16_S);
10436 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10437 macro_build (&offset_expr, "daddiu", "t,r,j",
10438 tempreg, tempreg, BFD_RELOC_LO16);
10441 if (mips_relax.sequence)
10446 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10447 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10449 relax_start (offset_expr.X_add_symbol);
10450 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10451 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10454 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10455 as_bad (_("offset too large"));
10456 macro_build_lui (&offset_expr, tempreg);
10457 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10458 tempreg, tempreg, BFD_RELOC_LO16);
10459 if (mips_relax.sequence)
10463 else if (!mips_big_got && !HAVE_NEWABI)
10465 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10467 /* If this is a reference to an external symbol, and there
10468 is no constant, we want
10469 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10470 or for lca or if tempreg is PIC_CALL_REG
10471 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10472 For a local symbol, we want
10473 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10475 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10477 If we have a small constant, and this is a reference to
10478 an external symbol, we want
10479 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10481 addiu $tempreg,$tempreg,<constant>
10482 For a local symbol, we want the same instruction
10483 sequence, but we output a BFD_RELOC_LO16 reloc on the
10486 If we have a large constant, and this is a reference to
10487 an external symbol, we want
10488 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10489 lui $at,<hiconstant>
10490 addiu $at,$at,<loconstant>
10491 addu $tempreg,$tempreg,$at
10492 For a local symbol, we want the same instruction
10493 sequence, but we output a BFD_RELOC_LO16 reloc on the
10497 if (offset_expr.X_add_number == 0)
10499 if (mips_pic == SVR4_PIC
10501 && (call || tempreg == PIC_CALL_REG))
10502 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10504 relax_start (offset_expr.X_add_symbol);
10505 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10506 lw_reloc_type, mips_gp_register);
10509 /* We're going to put in an addu instruction using
10510 tempreg, so we may as well insert the nop right
10515 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10516 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10518 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10519 tempreg, tempreg, BFD_RELOC_LO16);
10521 /* FIXME: If breg == 0, and the next instruction uses
10522 $tempreg, then if this variant case is used an extra
10523 nop will be generated. */
10525 else if (offset_expr.X_add_number >= -0x8000
10526 && offset_expr.X_add_number < 0x8000)
10528 load_got_offset (tempreg, &offset_expr);
10530 add_got_offset (tempreg, &offset_expr);
10534 expr1.X_add_number = offset_expr.X_add_number;
10535 offset_expr.X_add_number =
10536 SEXT_16BIT (offset_expr.X_add_number);
10537 load_got_offset (tempreg, &offset_expr);
10538 offset_expr.X_add_number = expr1.X_add_number;
10539 /* If we are going to add in a base register, and the
10540 target register and the base register are the same,
10541 then we are using AT as a temporary register. Since
10542 we want to load the constant into AT, we add our
10543 current AT (from the global offset table) and the
10544 register into the register now, and pretend we were
10545 not using a base register. */
10549 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10554 add_got_offset_hilo (tempreg, &offset_expr, AT);
10558 else if (!mips_big_got && HAVE_NEWABI)
10560 int add_breg_early = 0;
10562 /* If this is a reference to an external, and there is no
10563 constant, or local symbol (*), with or without a
10565 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10566 or for lca or if tempreg is PIC_CALL_REG
10567 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10569 If we have a small constant, and this is a reference to
10570 an external symbol, we want
10571 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10572 addiu $tempreg,$tempreg,<constant>
10574 If we have a large constant, and this is a reference to
10575 an external symbol, we want
10576 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10577 lui $at,<hiconstant>
10578 addiu $at,$at,<loconstant>
10579 addu $tempreg,$tempreg,$at
10581 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10582 local symbols, even though it introduces an additional
10585 if (offset_expr.X_add_number)
10587 expr1.X_add_number = offset_expr.X_add_number;
10588 offset_expr.X_add_number = 0;
10590 relax_start (offset_expr.X_add_symbol);
10591 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10592 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10594 if (expr1.X_add_number >= -0x8000
10595 && expr1.X_add_number < 0x8000)
10597 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10598 tempreg, tempreg, BFD_RELOC_LO16);
10600 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10604 /* If we are going to add in a base register, and the
10605 target register and the base register are the same,
10606 then we are using AT as a temporary register. Since
10607 we want to load the constant into AT, we add our
10608 current AT (from the global offset table) and the
10609 register into the register now, and pretend we were
10610 not using a base register. */
10615 gas_assert (tempreg == AT);
10616 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10619 add_breg_early = 1;
10622 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10623 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10629 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10632 offset_expr.X_add_number = expr1.X_add_number;
10634 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10635 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10636 if (add_breg_early)
10638 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10639 op[0], tempreg, breg);
10645 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10647 relax_start (offset_expr.X_add_symbol);
10648 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10649 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10651 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10652 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10657 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10658 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10661 else if (mips_big_got && !HAVE_NEWABI)
10664 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10665 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10666 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10668 /* This is the large GOT case. If this is a reference to an
10669 external symbol, and there is no constant, we want
10670 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10671 addu $tempreg,$tempreg,$gp
10672 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10673 or for lca or if tempreg is PIC_CALL_REG
10674 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10675 addu $tempreg,$tempreg,$gp
10676 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10677 For a local symbol, we want
10678 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10680 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10682 If we have a small constant, and this is a reference to
10683 an external symbol, we want
10684 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10685 addu $tempreg,$tempreg,$gp
10686 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10688 addiu $tempreg,$tempreg,<constant>
10689 For a local symbol, we want
10690 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10692 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10694 If we have a large constant, and this is a reference to
10695 an external symbol, we want
10696 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10697 addu $tempreg,$tempreg,$gp
10698 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10699 lui $at,<hiconstant>
10700 addiu $at,$at,<loconstant>
10701 addu $tempreg,$tempreg,$at
10702 For a local symbol, we want
10703 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10704 lui $at,<hiconstant>
10705 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10706 addu $tempreg,$tempreg,$at
10709 expr1.X_add_number = offset_expr.X_add_number;
10710 offset_expr.X_add_number = 0;
10711 relax_start (offset_expr.X_add_symbol);
10712 gpdelay = reg_needs_delay (mips_gp_register);
10713 if (expr1.X_add_number == 0 && breg == 0
10714 && (call || tempreg == PIC_CALL_REG))
10716 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10717 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10719 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10720 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10721 tempreg, tempreg, mips_gp_register);
10722 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10723 tempreg, lw_reloc_type, tempreg);
10724 if (expr1.X_add_number == 0)
10728 /* We're going to put in an addu instruction using
10729 tempreg, so we may as well insert the nop right
10734 else if (expr1.X_add_number >= -0x8000
10735 && expr1.X_add_number < 0x8000)
10738 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10739 tempreg, tempreg, BFD_RELOC_LO16);
10745 /* If we are going to add in a base register, and the
10746 target register and the base register are the same,
10747 then we are using AT as a temporary register. Since
10748 we want to load the constant into AT, we add our
10749 current AT (from the global offset table) and the
10750 register into the register now, and pretend we were
10751 not using a base register. */
10756 gas_assert (tempreg == AT);
10758 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10763 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10764 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10768 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10773 /* This is needed because this instruction uses $gp, but
10774 the first instruction on the main stream does not. */
10775 macro_build (NULL, "nop", "");
10778 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10779 local_reloc_type, mips_gp_register);
10780 if (expr1.X_add_number >= -0x8000
10781 && expr1.X_add_number < 0x8000)
10784 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10785 tempreg, tempreg, BFD_RELOC_LO16);
10786 /* FIXME: If add_number is 0, and there was no base
10787 register, the external symbol case ended with a load,
10788 so if the symbol turns out to not be external, and
10789 the next instruction uses tempreg, an unnecessary nop
10790 will be inserted. */
10796 /* We must add in the base register now, as in the
10797 external symbol case. */
10798 gas_assert (tempreg == AT);
10800 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10803 /* We set breg to 0 because we have arranged to add
10804 it in in both cases. */
10808 macro_build_lui (&expr1, AT);
10809 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10810 AT, AT, BFD_RELOC_LO16);
10811 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10812 tempreg, tempreg, AT);
10817 else if (mips_big_got && HAVE_NEWABI)
10819 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10820 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10821 int add_breg_early = 0;
10823 /* This is the large GOT case. If this is a reference to an
10824 external symbol, and there is no constant, we want
10825 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10826 add $tempreg,$tempreg,$gp
10827 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10828 or for lca or if tempreg is PIC_CALL_REG
10829 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10830 add $tempreg,$tempreg,$gp
10831 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10833 If we have a small constant, and this is a reference to
10834 an external symbol, we want
10835 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10836 add $tempreg,$tempreg,$gp
10837 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10838 addi $tempreg,$tempreg,<constant>
10840 If we have a large constant, and this is a reference to
10841 an external symbol, we want
10842 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10843 addu $tempreg,$tempreg,$gp
10844 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10845 lui $at,<hiconstant>
10846 addi $at,$at,<loconstant>
10847 add $tempreg,$tempreg,$at
10849 If we have NewABI, and we know it's a local symbol, we want
10850 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10851 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10852 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10854 relax_start (offset_expr.X_add_symbol);
10856 expr1.X_add_number = offset_expr.X_add_number;
10857 offset_expr.X_add_number = 0;
10859 if (expr1.X_add_number == 0 && breg == 0
10860 && (call || tempreg == PIC_CALL_REG))
10862 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10863 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10865 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10866 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10867 tempreg, tempreg, mips_gp_register);
10868 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10869 tempreg, lw_reloc_type, tempreg);
10871 if (expr1.X_add_number == 0)
10873 else if (expr1.X_add_number >= -0x8000
10874 && expr1.X_add_number < 0x8000)
10876 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10877 tempreg, tempreg, BFD_RELOC_LO16);
10879 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10883 /* If we are going to add in a base register, and the
10884 target register and the base register are the same,
10885 then we are using AT as a temporary register. Since
10886 we want to load the constant into AT, we add our
10887 current AT (from the global offset table) and the
10888 register into the register now, and pretend we were
10889 not using a base register. */
10894 gas_assert (tempreg == AT);
10895 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10898 add_breg_early = 1;
10901 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10902 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10907 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10910 offset_expr.X_add_number = expr1.X_add_number;
10911 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10912 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10913 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10914 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10915 if (add_breg_early)
10917 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10918 op[0], tempreg, breg);
10928 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10932 gas_assert (!mips_opts.micromips);
10933 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10937 gas_assert (!mips_opts.micromips);
10938 macro_build (NULL, "c2", "C", 0x02);
10942 gas_assert (!mips_opts.micromips);
10943 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10947 gas_assert (!mips_opts.micromips);
10948 macro_build (NULL, "c2", "C", 3);
10952 gas_assert (!mips_opts.micromips);
10953 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
10957 /* The j instruction may not be used in PIC code, since it
10958 requires an absolute address. We convert it to a b
10960 if (mips_pic == NO_PIC)
10961 macro_build (&offset_expr, "j", "a");
10963 macro_build (&offset_expr, "b", "p");
10966 /* The jal instructions must be handled as macros because when
10967 generating PIC code they expand to multi-instruction
10968 sequences. Normally they are simple instructions. */
10972 /* Fall through. */
10974 gas_assert (mips_opts.micromips);
10975 if (mips_opts.insn32)
10977 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
10985 /* Fall through. */
10988 if (mips_pic == NO_PIC)
10990 s = jals ? "jalrs" : "jalr";
10991 if (mips_opts.micromips
10992 && !mips_opts.insn32
10994 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10995 macro_build (NULL, s, "mj", op[1]);
10997 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11001 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11002 && mips_cprestore_offset >= 0);
11004 if (op[1] != PIC_CALL_REG)
11005 as_warn (_("MIPS PIC call to register other than $25"));
11007 s = ((mips_opts.micromips
11008 && !mips_opts.insn32
11009 && (!mips_opts.noreorder || cprestore))
11010 ? "jalrs" : "jalr");
11011 if (mips_opts.micromips
11012 && !mips_opts.insn32
11014 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11015 macro_build (NULL, s, "mj", op[1]);
11017 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11018 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11020 if (mips_cprestore_offset < 0)
11021 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11024 if (!mips_frame_reg_valid)
11026 as_warn (_("no .frame pseudo-op used in PIC code"));
11027 /* Quiet this warning. */
11028 mips_frame_reg_valid = 1;
11030 if (!mips_cprestore_valid)
11032 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11033 /* Quiet this warning. */
11034 mips_cprestore_valid = 1;
11036 if (mips_opts.noreorder)
11037 macro_build (NULL, "nop", "");
11038 expr1.X_add_number = mips_cprestore_offset;
11039 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11042 HAVE_64BIT_ADDRESSES);
11050 gas_assert (mips_opts.micromips);
11051 if (mips_opts.insn32)
11053 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11057 /* Fall through. */
11059 if (mips_pic == NO_PIC)
11060 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11061 else if (mips_pic == SVR4_PIC)
11063 /* If this is a reference to an external symbol, and we are
11064 using a small GOT, we want
11065 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11069 lw $gp,cprestore($sp)
11070 The cprestore value is set using the .cprestore
11071 pseudo-op. If we are using a big GOT, we want
11072 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11074 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11078 lw $gp,cprestore($sp)
11079 If the symbol is not external, we want
11080 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11082 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11085 lw $gp,cprestore($sp)
11087 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11088 sequences above, minus nops, unless the symbol is local,
11089 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11095 relax_start (offset_expr.X_add_symbol);
11096 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11097 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11100 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11101 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11107 relax_start (offset_expr.X_add_symbol);
11108 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11109 BFD_RELOC_MIPS_CALL_HI16);
11110 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11111 PIC_CALL_REG, mips_gp_register);
11112 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11113 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11116 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11117 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11119 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11120 PIC_CALL_REG, PIC_CALL_REG,
11121 BFD_RELOC_MIPS_GOT_OFST);
11125 macro_build_jalr (&offset_expr, 0);
11129 relax_start (offset_expr.X_add_symbol);
11132 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11133 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11142 gpdelay = reg_needs_delay (mips_gp_register);
11143 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11144 BFD_RELOC_MIPS_CALL_HI16);
11145 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11146 PIC_CALL_REG, mips_gp_register);
11147 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11148 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11153 macro_build (NULL, "nop", "");
11155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11156 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11159 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11160 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11162 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11164 if (mips_cprestore_offset < 0)
11165 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11168 if (!mips_frame_reg_valid)
11170 as_warn (_("no .frame pseudo-op used in PIC code"));
11171 /* Quiet this warning. */
11172 mips_frame_reg_valid = 1;
11174 if (!mips_cprestore_valid)
11176 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11177 /* Quiet this warning. */
11178 mips_cprestore_valid = 1;
11180 if (mips_opts.noreorder)
11181 macro_build (NULL, "nop", "");
11182 expr1.X_add_number = mips_cprestore_offset;
11183 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11186 HAVE_64BIT_ADDRESSES);
11190 else if (mips_pic == VXWORKS_PIC)
11191 as_bad (_("non-PIC jump used in PIC library"));
11298 gas_assert (!mips_opts.micromips);
11301 /* Itbl support may require additional care here. */
11307 /* Itbl support may require additional care here. */
11313 offbits = (mips_opts.micromips ? 12
11314 : ISA_IS_R6 (mips_opts.isa) ? 11
11316 /* Itbl support may require additional care here. */
11320 gas_assert (!mips_opts.micromips);
11323 /* Itbl support may require additional care here. */
11329 offbits = (mips_opts.micromips ? 12 : 16);
11334 offbits = (mips_opts.micromips ? 12 : 16);
11339 /* Itbl support may require additional care here. */
11345 offbits = (mips_opts.micromips ? 12
11346 : ISA_IS_R6 (mips_opts.isa) ? 11
11348 /* Itbl support may require additional care here. */
11354 /* Itbl support may require additional care here. */
11360 /* Itbl support may require additional care here. */
11366 offbits = (mips_opts.micromips ? 12 : 16);
11371 offbits = (mips_opts.micromips ? 12 : 16);
11376 offbits = (mips_opts.micromips ? 12
11377 : ISA_IS_R6 (mips_opts.isa) ? 9
11383 offbits = (mips_opts.micromips ? 12
11384 : ISA_IS_R6 (mips_opts.isa) ? 9
11390 offbits = (mips_opts.micromips ? 12 : 16);
11393 gas_assert (mips_opts.micromips);
11400 gas_assert (mips_opts.micromips);
11407 gas_assert (mips_opts.micromips);
11413 gas_assert (mips_opts.micromips);
11420 /* We don't want to use $0 as tempreg. */
11421 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11424 tempreg = op[0] + lp;
11440 gas_assert (!mips_opts.micromips);
11443 /* Itbl support may require additional care here. */
11449 /* Itbl support may require additional care here. */
11455 offbits = (mips_opts.micromips ? 12
11456 : ISA_IS_R6 (mips_opts.isa) ? 11
11458 /* Itbl support may require additional care here. */
11462 gas_assert (!mips_opts.micromips);
11465 /* Itbl support may require additional care here. */
11471 offbits = (mips_opts.micromips ? 12 : 16);
11476 offbits = (mips_opts.micromips ? 12 : 16);
11481 offbits = (mips_opts.micromips ? 12
11482 : ISA_IS_R6 (mips_opts.isa) ? 9
11488 offbits = (mips_opts.micromips ? 12
11489 : ISA_IS_R6 (mips_opts.isa) ? 9
11494 fmt = (mips_opts.micromips ? "k,~(b)"
11495 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11497 offbits = (mips_opts.micromips ? 12
11498 : ISA_IS_R6 (mips_opts.isa) ? 9
11508 fmt = (mips_opts.micromips ? "k,~(b)"
11509 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11511 offbits = (mips_opts.micromips ? 12
11512 : ISA_IS_R6 (mips_opts.isa) ? 9
11524 /* Itbl support may require additional care here. */
11529 offbits = (mips_opts.micromips ? 12
11530 : ISA_IS_R6 (mips_opts.isa) ? 11
11532 /* Itbl support may require additional care here. */
11538 /* Itbl support may require additional care here. */
11542 gas_assert (!mips_opts.micromips);
11545 /* Itbl support may require additional care here. */
11551 offbits = (mips_opts.micromips ? 12 : 16);
11556 offbits = (mips_opts.micromips ? 12 : 16);
11559 gas_assert (mips_opts.micromips);
11565 gas_assert (mips_opts.micromips);
11571 gas_assert (mips_opts.micromips);
11577 gas_assert (mips_opts.micromips);
11586 if (small_offset_p (0, align, 16))
11588 /* The first case exists for M_LD_AB and M_SD_AB, which are
11589 macros for o32 but which should act like normal instructions
11592 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11593 offset_reloc[1], offset_reloc[2], breg);
11594 else if (small_offset_p (0, align, offbits))
11597 macro_build (NULL, s, fmt, op[0], breg);
11599 macro_build (NULL, s, fmt, op[0],
11600 (int) offset_expr.X_add_number, breg);
11606 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11607 tempreg, breg, -1, offset_reloc[0],
11608 offset_reloc[1], offset_reloc[2]);
11610 macro_build (NULL, s, fmt, op[0], tempreg);
11612 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11620 if (offset_expr.X_op != O_constant
11621 && offset_expr.X_op != O_symbol)
11623 as_bad (_("expression too complex"));
11624 offset_expr.X_op = O_constant;
11627 if (HAVE_32BIT_ADDRESSES
11628 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11632 sprintf_vma (value, offset_expr.X_add_number);
11633 as_bad (_("number (0x%s) larger than 32 bits"), value);
11636 /* A constant expression in PIC code can be handled just as it
11637 is in non PIC code. */
11638 if (offset_expr.X_op == O_constant)
11640 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11641 offbits == 0 ? 16 : offbits);
11642 offset_expr.X_add_number -= expr1.X_add_number;
11644 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11646 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11647 tempreg, tempreg, breg);
11650 if (offset_expr.X_add_number != 0)
11651 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
11652 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
11653 macro_build (NULL, s, fmt, op[0], tempreg);
11655 else if (offbits == 16)
11656 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11658 macro_build (NULL, s, fmt, op[0],
11659 (int) offset_expr.X_add_number, tempreg);
11661 else if (offbits != 16)
11663 /* The offset field is too narrow to be used for a low-part
11664 relocation, so load the whole address into the auxillary
11666 load_address (tempreg, &offset_expr, &used_at);
11668 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11669 tempreg, tempreg, breg);
11671 macro_build (NULL, s, fmt, op[0], tempreg);
11673 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11675 else if (mips_pic == NO_PIC)
11677 /* If this is a reference to a GP relative symbol, and there
11678 is no base register, we want
11679 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11680 Otherwise, if there is no base register, we want
11681 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11682 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11683 If we have a constant, we need two instructions anyhow,
11684 so we always use the latter form.
11686 If we have a base register, and this is a reference to a
11687 GP relative symbol, we want
11688 addu $tempreg,$breg,$gp
11689 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11691 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11692 addu $tempreg,$tempreg,$breg
11693 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11694 With a constant we always use the latter case.
11696 With 64bit address space and no base register and $at usable,
11698 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11699 lui $at,<sym> (BFD_RELOC_HI16_S)
11700 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11703 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11704 If we have a base register, we want
11705 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11706 lui $at,<sym> (BFD_RELOC_HI16_S)
11707 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11711 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11713 Without $at we can't generate the optimal path for superscalar
11714 processors here since this would require two temporary registers.
11715 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11716 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11718 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11720 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11721 If we have a base register, we want
11722 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11723 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11725 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11727 daddu $tempreg,$tempreg,$breg
11728 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11730 For GP relative symbols in 64bit address space we can use
11731 the same sequence as in 32bit address space. */
11732 if (HAVE_64BIT_SYMBOLS)
11734 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11735 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11737 relax_start (offset_expr.X_add_symbol);
11740 macro_build (&offset_expr, s, fmt, op[0],
11741 BFD_RELOC_GPREL16, mips_gp_register);
11745 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11746 tempreg, breg, mips_gp_register);
11747 macro_build (&offset_expr, s, fmt, op[0],
11748 BFD_RELOC_GPREL16, tempreg);
11753 if (used_at == 0 && mips_opts.at)
11755 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11756 BFD_RELOC_MIPS_HIGHEST);
11757 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11759 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11760 tempreg, BFD_RELOC_MIPS_HIGHER);
11762 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11763 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11764 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11765 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11771 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11772 BFD_RELOC_MIPS_HIGHEST);
11773 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11774 tempreg, BFD_RELOC_MIPS_HIGHER);
11775 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11776 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11777 tempreg, BFD_RELOC_HI16_S);
11778 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11780 macro_build (NULL, "daddu", "d,v,t",
11781 tempreg, tempreg, breg);
11782 macro_build (&offset_expr, s, fmt, op[0],
11783 BFD_RELOC_LO16, tempreg);
11786 if (mips_relax.sequence)
11793 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11794 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11796 relax_start (offset_expr.X_add_symbol);
11797 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11801 macro_build_lui (&offset_expr, tempreg);
11802 macro_build (&offset_expr, s, fmt, op[0],
11803 BFD_RELOC_LO16, tempreg);
11804 if (mips_relax.sequence)
11809 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11810 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11812 relax_start (offset_expr.X_add_symbol);
11813 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11814 tempreg, breg, mips_gp_register);
11815 macro_build (&offset_expr, s, fmt, op[0],
11816 BFD_RELOC_GPREL16, tempreg);
11819 macro_build_lui (&offset_expr, tempreg);
11820 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11821 tempreg, tempreg, breg);
11822 macro_build (&offset_expr, s, fmt, op[0],
11823 BFD_RELOC_LO16, tempreg);
11824 if (mips_relax.sequence)
11828 else if (!mips_big_got)
11830 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11832 /* If this is a reference to an external symbol, we want
11833 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11835 <op> op[0],0($tempreg)
11837 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11839 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11840 <op> op[0],0($tempreg)
11842 For NewABI, we want
11843 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11844 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11846 If there is a base register, we add it to $tempreg before
11847 the <op>. If there is a constant, we stick it in the
11848 <op> instruction. We don't handle constants larger than
11849 16 bits, because we have no way to load the upper 16 bits
11850 (actually, we could handle them for the subset of cases
11851 in which we are not using $at). */
11852 gas_assert (offset_expr.X_op == O_symbol);
11855 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11856 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11858 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11859 tempreg, tempreg, breg);
11860 macro_build (&offset_expr, s, fmt, op[0],
11861 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11864 expr1.X_add_number = offset_expr.X_add_number;
11865 offset_expr.X_add_number = 0;
11866 if (expr1.X_add_number < -0x8000
11867 || expr1.X_add_number >= 0x8000)
11868 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11869 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11870 lw_reloc_type, mips_gp_register);
11872 relax_start (offset_expr.X_add_symbol);
11874 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11875 tempreg, BFD_RELOC_LO16);
11878 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11879 tempreg, tempreg, breg);
11880 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11882 else if (mips_big_got && !HAVE_NEWABI)
11886 /* If this is a reference to an external symbol, we want
11887 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11888 addu $tempreg,$tempreg,$gp
11889 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11890 <op> op[0],0($tempreg)
11892 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11894 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11895 <op> op[0],0($tempreg)
11896 If there is a base register, we add it to $tempreg before
11897 the <op>. If there is a constant, we stick it in the
11898 <op> instruction. We don't handle constants larger than
11899 16 bits, because we have no way to load the upper 16 bits
11900 (actually, we could handle them for the subset of cases
11901 in which we are not using $at). */
11902 gas_assert (offset_expr.X_op == O_symbol);
11903 expr1.X_add_number = offset_expr.X_add_number;
11904 offset_expr.X_add_number = 0;
11905 if (expr1.X_add_number < -0x8000
11906 || expr1.X_add_number >= 0x8000)
11907 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11908 gpdelay = reg_needs_delay (mips_gp_register);
11909 relax_start (offset_expr.X_add_symbol);
11910 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11911 BFD_RELOC_MIPS_GOT_HI16);
11912 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11914 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11915 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11918 macro_build (NULL, "nop", "");
11919 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11920 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11922 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11923 tempreg, BFD_RELOC_LO16);
11927 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11928 tempreg, tempreg, breg);
11929 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11931 else if (mips_big_got && HAVE_NEWABI)
11933 /* If this is a reference to an external symbol, we want
11934 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11935 add $tempreg,$tempreg,$gp
11936 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11937 <op> op[0],<ofst>($tempreg)
11938 Otherwise, for local symbols, we want:
11939 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11940 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11941 gas_assert (offset_expr.X_op == O_symbol);
11942 expr1.X_add_number = offset_expr.X_add_number;
11943 offset_expr.X_add_number = 0;
11944 if (expr1.X_add_number < -0x8000
11945 || expr1.X_add_number >= 0x8000)
11946 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11947 relax_start (offset_expr.X_add_symbol);
11948 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11949 BFD_RELOC_MIPS_GOT_HI16);
11950 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11952 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11953 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11955 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11956 tempreg, tempreg, breg);
11957 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11960 offset_expr.X_add_number = expr1.X_add_number;
11961 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11962 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11964 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11965 tempreg, tempreg, breg);
11966 macro_build (&offset_expr, s, fmt, op[0],
11967 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11976 gas_assert (mips_opts.micromips);
11977 gas_assert (mips_opts.insn32);
11978 start_noreorder ();
11979 macro_build (NULL, "jr", "s", RA);
11980 expr1.X_add_number = op[0] << 2;
11981 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11986 gas_assert (mips_opts.micromips);
11987 gas_assert (mips_opts.insn32);
11988 macro_build (NULL, "jr", "s", op[0]);
11989 if (mips_opts.noreorder)
11990 macro_build (NULL, "nop", "");
11995 load_register (op[0], &imm_expr, 0);
11999 load_register (op[0], &imm_expr, 1);
12003 if (imm_expr.X_op == O_constant)
12006 load_register (AT, &imm_expr, 0);
12007 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12012 gas_assert (imm_expr.X_op == O_absent
12013 && offset_expr.X_op == O_symbol
12014 && strcmp (segment_name (S_GET_SEGMENT
12015 (offset_expr.X_add_symbol)),
12017 && offset_expr.X_add_number == 0);
12018 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12019 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12024 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12025 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12026 order 32 bits of the value and the low order 32 bits are either
12027 zero or in OFFSET_EXPR. */
12028 if (imm_expr.X_op == O_constant)
12030 if (GPR_SIZE == 64)
12031 load_register (op[0], &imm_expr, 1);
12036 if (target_big_endian)
12048 load_register (hreg, &imm_expr, 0);
12051 if (offset_expr.X_op == O_absent)
12052 move_register (lreg, 0);
12055 gas_assert (offset_expr.X_op == O_constant);
12056 load_register (lreg, &offset_expr, 0);
12062 gas_assert (imm_expr.X_op == O_absent);
12064 /* We know that sym is in the .rdata section. First we get the
12065 upper 16 bits of the address. */
12066 if (mips_pic == NO_PIC)
12068 macro_build_lui (&offset_expr, AT);
12073 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12074 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12078 /* Now we load the register(s). */
12079 if (GPR_SIZE == 64)
12082 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12083 BFD_RELOC_LO16, AT);
12088 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12089 BFD_RELOC_LO16, AT);
12092 /* FIXME: How in the world do we deal with the possible
12094 offset_expr.X_add_number += 4;
12095 macro_build (&offset_expr, "lw", "t,o(b)",
12096 op[0] + 1, BFD_RELOC_LO16, AT);
12102 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12103 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12104 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12105 the value and the low order 32 bits are either zero or in
12107 if (imm_expr.X_op == O_constant)
12110 load_register (AT, &imm_expr, FPR_SIZE == 64);
12111 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12112 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12115 if (ISA_HAS_MXHC1 (mips_opts.isa))
12116 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12117 else if (FPR_SIZE != 32)
12118 as_bad (_("Unable to generate `%s' compliant code "
12120 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12122 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12123 if (offset_expr.X_op == O_absent)
12124 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12127 gas_assert (offset_expr.X_op == O_constant);
12128 load_register (AT, &offset_expr, 0);
12129 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12135 gas_assert (imm_expr.X_op == O_absent
12136 && offset_expr.X_op == O_symbol
12137 && offset_expr.X_add_number == 0);
12138 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12139 if (strcmp (s, ".lit8") == 0)
12141 op[2] = mips_gp_register;
12142 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12143 offset_reloc[1] = BFD_RELOC_UNUSED;
12144 offset_reloc[2] = BFD_RELOC_UNUSED;
12148 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12150 if (mips_pic != NO_PIC)
12151 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12152 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12155 /* FIXME: This won't work for a 64 bit address. */
12156 macro_build_lui (&offset_expr, AT);
12160 offset_reloc[0] = BFD_RELOC_LO16;
12161 offset_reloc[1] = BFD_RELOC_UNUSED;
12162 offset_reloc[2] = BFD_RELOC_UNUSED;
12169 * The MIPS assembler seems to check for X_add_number not
12170 * being double aligned and generating:
12171 * lui at,%hi(foo+1)
12173 * addiu at,at,%lo(foo+1)
12176 * But, the resulting address is the same after relocation so why
12177 * generate the extra instruction?
12179 /* Itbl support may require additional care here. */
12182 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12191 gas_assert (!mips_opts.micromips);
12192 /* Itbl support may require additional care here. */
12195 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12215 if (GPR_SIZE == 64)
12225 if (GPR_SIZE == 64)
12233 /* Even on a big endian machine $fn comes before $fn+1. We have
12234 to adjust when loading from memory. We set coproc if we must
12235 load $fn+1 first. */
12236 /* Itbl support may require additional care here. */
12237 if (!target_big_endian)
12241 if (small_offset_p (0, align, 16))
12244 if (!small_offset_p (4, align, 16))
12246 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12247 -1, offset_reloc[0], offset_reloc[1],
12249 expr1.X_add_number = 0;
12253 offset_reloc[0] = BFD_RELOC_LO16;
12254 offset_reloc[1] = BFD_RELOC_UNUSED;
12255 offset_reloc[2] = BFD_RELOC_UNUSED;
12257 if (strcmp (s, "lw") == 0 && op[0] == breg)
12259 ep->X_add_number += 4;
12260 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12261 offset_reloc[1], offset_reloc[2], breg);
12262 ep->X_add_number -= 4;
12263 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12264 offset_reloc[1], offset_reloc[2], breg);
12268 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12269 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12271 ep->X_add_number += 4;
12272 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12273 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12279 if (offset_expr.X_op != O_symbol
12280 && offset_expr.X_op != O_constant)
12282 as_bad (_("expression too complex"));
12283 offset_expr.X_op = O_constant;
12286 if (HAVE_32BIT_ADDRESSES
12287 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12291 sprintf_vma (value, offset_expr.X_add_number);
12292 as_bad (_("number (0x%s) larger than 32 bits"), value);
12295 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12297 /* If this is a reference to a GP relative symbol, we want
12298 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12299 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12300 If we have a base register, we use this
12302 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12303 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12304 If this is not a GP relative symbol, we want
12305 lui $at,<sym> (BFD_RELOC_HI16_S)
12306 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12307 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12308 If there is a base register, we add it to $at after the
12309 lui instruction. If there is a constant, we always use
12311 if (offset_expr.X_op == O_symbol
12312 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12313 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12315 relax_start (offset_expr.X_add_symbol);
12318 tempreg = mips_gp_register;
12322 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12323 AT, breg, mips_gp_register);
12328 /* Itbl support may require additional care here. */
12329 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12330 BFD_RELOC_GPREL16, tempreg);
12331 offset_expr.X_add_number += 4;
12333 /* Set mips_optimize to 2 to avoid inserting an
12335 hold_mips_optimize = mips_optimize;
12337 /* Itbl support may require additional care here. */
12338 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12339 BFD_RELOC_GPREL16, tempreg);
12340 mips_optimize = hold_mips_optimize;
12344 offset_expr.X_add_number -= 4;
12347 if (offset_high_part (offset_expr.X_add_number, 16)
12348 != offset_high_part (offset_expr.X_add_number + 4, 16))
12350 load_address (AT, &offset_expr, &used_at);
12351 offset_expr.X_op = O_constant;
12352 offset_expr.X_add_number = 0;
12355 macro_build_lui (&offset_expr, AT);
12357 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12358 /* Itbl support may require additional care here. */
12359 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12360 BFD_RELOC_LO16, AT);
12361 /* FIXME: How do we handle overflow here? */
12362 offset_expr.X_add_number += 4;
12363 /* Itbl support may require additional care here. */
12364 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12365 BFD_RELOC_LO16, AT);
12366 if (mips_relax.sequence)
12369 else if (!mips_big_got)
12371 /* If this is a reference to an external symbol, we want
12372 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12375 <op> op[0]+1,4($at)
12377 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12379 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12380 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12381 If there is a base register we add it to $at before the
12382 lwc1 instructions. If there is a constant we include it
12383 in the lwc1 instructions. */
12385 expr1.X_add_number = offset_expr.X_add_number;
12386 if (expr1.X_add_number < -0x8000
12387 || expr1.X_add_number >= 0x8000 - 4)
12388 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12389 load_got_offset (AT, &offset_expr);
12392 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12394 /* Set mips_optimize to 2 to avoid inserting an undesired
12396 hold_mips_optimize = mips_optimize;
12399 /* Itbl support may require additional care here. */
12400 relax_start (offset_expr.X_add_symbol);
12401 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12402 BFD_RELOC_LO16, AT);
12403 expr1.X_add_number += 4;
12404 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12405 BFD_RELOC_LO16, AT);
12407 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12408 BFD_RELOC_LO16, AT);
12409 offset_expr.X_add_number += 4;
12410 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12411 BFD_RELOC_LO16, AT);
12414 mips_optimize = hold_mips_optimize;
12416 else if (mips_big_got)
12420 /* If this is a reference to an external symbol, we want
12421 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12423 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12426 <op> op[0]+1,4($at)
12428 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12430 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12431 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12432 If there is a base register we add it to $at before the
12433 lwc1 instructions. If there is a constant we include it
12434 in the lwc1 instructions. */
12436 expr1.X_add_number = offset_expr.X_add_number;
12437 offset_expr.X_add_number = 0;
12438 if (expr1.X_add_number < -0x8000
12439 || expr1.X_add_number >= 0x8000 - 4)
12440 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12441 gpdelay = reg_needs_delay (mips_gp_register);
12442 relax_start (offset_expr.X_add_symbol);
12443 macro_build (&offset_expr, "lui", LUI_FMT,
12444 AT, BFD_RELOC_MIPS_GOT_HI16);
12445 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12446 AT, AT, mips_gp_register);
12447 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12448 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12451 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12452 /* Itbl support may require additional care here. */
12453 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12454 BFD_RELOC_LO16, AT);
12455 expr1.X_add_number += 4;
12457 /* Set mips_optimize to 2 to avoid inserting an undesired
12459 hold_mips_optimize = mips_optimize;
12461 /* Itbl support may require additional care here. */
12462 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12463 BFD_RELOC_LO16, AT);
12464 mips_optimize = hold_mips_optimize;
12465 expr1.X_add_number -= 4;
12468 offset_expr.X_add_number = expr1.X_add_number;
12470 macro_build (NULL, "nop", "");
12471 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12472 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12475 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12476 /* Itbl support may require additional care here. */
12477 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12478 BFD_RELOC_LO16, AT);
12479 offset_expr.X_add_number += 4;
12481 /* Set mips_optimize to 2 to avoid inserting an undesired
12483 hold_mips_optimize = mips_optimize;
12485 /* Itbl support may require additional care here. */
12486 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12487 BFD_RELOC_LO16, AT);
12488 mips_optimize = hold_mips_optimize;
12502 gas_assert (!mips_opts.micromips);
12507 /* New code added to support COPZ instructions.
12508 This code builds table entries out of the macros in mip_opcodes.
12509 R4000 uses interlocks to handle coproc delays.
12510 Other chips (like the R3000) require nops to be inserted for delays.
12512 FIXME: Currently, we require that the user handle delays.
12513 In order to fill delay slots for non-interlocked chips,
12514 we must have a way to specify delays based on the coprocessor.
12515 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12516 What are the side-effects of the cop instruction?
12517 What cache support might we have and what are its effects?
12518 Both coprocessor & memory require delays. how long???
12519 What registers are read/set/modified?
12521 If an itbl is provided to interpret cop instructions,
12522 this knowledge can be encoded in the itbl spec. */
12536 gas_assert (!mips_opts.micromips);
12537 /* For now we just do C (same as Cz). The parameter will be
12538 stored in insn_opcode by mips_ip. */
12539 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12543 move_register (op[0], op[1]);
12547 gas_assert (mips_opts.micromips);
12548 gas_assert (mips_opts.insn32);
12549 move_register (micromips_to_32_reg_h_map1[op[0]],
12550 micromips_to_32_reg_m_map[op[1]]);
12551 move_register (micromips_to_32_reg_h_map2[op[0]],
12552 micromips_to_32_reg_n_map[op[2]]);
12558 if (mips_opts.arch == CPU_R5900)
12559 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12563 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12564 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12571 /* The MIPS assembler some times generates shifts and adds. I'm
12572 not trying to be that fancy. GCC should do this for us
12575 load_register (AT, &imm_expr, dbl);
12576 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12577 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12590 start_noreorder ();
12593 load_register (AT, &imm_expr, dbl);
12594 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12595 op[1], imm ? AT : op[2]);
12596 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12597 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12598 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12600 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12603 if (mips_opts.micromips)
12604 micromips_label_expr (&label_expr);
12606 label_expr.X_add_number = 8;
12607 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12608 macro_build (NULL, "nop", "");
12609 macro_build (NULL, "break", BRK_FMT, 6);
12610 if (mips_opts.micromips)
12611 micromips_add_label ();
12614 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12627 start_noreorder ();
12630 load_register (AT, &imm_expr, dbl);
12631 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
12632 op[1], imm ? AT : op[2]);
12633 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12634 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12636 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
12639 if (mips_opts.micromips)
12640 micromips_label_expr (&label_expr);
12642 label_expr.X_add_number = 8;
12643 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
12644 macro_build (NULL, "nop", "");
12645 macro_build (NULL, "break", BRK_FMT, 6);
12646 if (mips_opts.micromips)
12647 micromips_add_label ();
12653 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12655 if (op[0] == op[1])
12662 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12663 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12667 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12668 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12669 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12670 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12674 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12676 if (op[0] == op[1])
12683 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12684 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12688 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12689 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12690 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12691 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12700 rot = imm_expr.X_add_number & 0x3f;
12701 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12703 rot = (64 - rot) & 0x3f;
12705 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12707 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12712 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12715 l = (rot < 0x20) ? "dsll" : "dsll32";
12716 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12719 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12720 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12721 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12729 rot = imm_expr.X_add_number & 0x1f;
12730 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12732 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12733 (32 - rot) & 0x1f);
12738 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12742 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12743 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12744 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12749 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12751 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12755 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12756 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12757 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12758 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12762 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12764 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12768 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12769 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12770 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12771 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12780 rot = imm_expr.X_add_number & 0x3f;
12781 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12784 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12786 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12791 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12794 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12795 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12798 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12799 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12800 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12808 rot = imm_expr.X_add_number & 0x1f;
12809 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12811 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12816 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12820 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12821 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12822 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12828 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12829 else if (op[2] == 0)
12830 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12833 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12834 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12839 if (imm_expr.X_add_number == 0)
12841 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12846 as_warn (_("instruction %s: result is always false"),
12847 ip->insn_mo->name);
12848 move_register (op[0], 0);
12851 if (CPU_HAS_SEQ (mips_opts.arch)
12852 && -512 <= imm_expr.X_add_number
12853 && imm_expr.X_add_number < 512)
12855 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12856 (int) imm_expr.X_add_number);
12859 if (imm_expr.X_add_number >= 0
12860 && imm_expr.X_add_number < 0x10000)
12861 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12862 else if (imm_expr.X_add_number > -0x8000
12863 && imm_expr.X_add_number < 0)
12865 imm_expr.X_add_number = -imm_expr.X_add_number;
12866 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
12867 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12869 else if (CPU_HAS_SEQ (mips_opts.arch))
12872 load_register (AT, &imm_expr, GPR_SIZE == 64);
12873 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12878 load_register (AT, &imm_expr, GPR_SIZE == 64);
12879 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12882 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12885 case M_SGE: /* X >= Y <==> not (X < Y) */
12891 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12892 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12895 case M_SGE_I: /* X >= I <==> not (X < I) */
12897 if (imm_expr.X_add_number >= -0x8000
12898 && imm_expr.X_add_number < 0x8000)
12899 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12900 op[0], op[1], BFD_RELOC_LO16);
12903 load_register (AT, &imm_expr, GPR_SIZE == 64);
12904 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12908 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12911 case M_SGT: /* X > Y <==> Y < X */
12917 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12920 case M_SGT_I: /* X > I <==> I < X */
12927 load_register (AT, &imm_expr, GPR_SIZE == 64);
12928 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12931 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12937 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12938 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12941 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12948 load_register (AT, &imm_expr, GPR_SIZE == 64);
12949 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12950 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12954 if (imm_expr.X_add_number >= -0x8000
12955 && imm_expr.X_add_number < 0x8000)
12957 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12962 load_register (AT, &imm_expr, GPR_SIZE == 64);
12963 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
12967 if (imm_expr.X_add_number >= -0x8000
12968 && imm_expr.X_add_number < 0x8000)
12970 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
12975 load_register (AT, &imm_expr, GPR_SIZE == 64);
12976 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
12981 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12982 else if (op[2] == 0)
12983 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12986 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12987 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12992 if (imm_expr.X_add_number == 0)
12994 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12999 as_warn (_("instruction %s: result is always true"),
13000 ip->insn_mo->name);
13001 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13002 op[0], 0, BFD_RELOC_LO16);
13005 if (CPU_HAS_SEQ (mips_opts.arch)
13006 && -512 <= imm_expr.X_add_number
13007 && imm_expr.X_add_number < 512)
13009 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13010 (int) imm_expr.X_add_number);
13013 if (imm_expr.X_add_number >= 0
13014 && imm_expr.X_add_number < 0x10000)
13016 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13019 else if (imm_expr.X_add_number > -0x8000
13020 && imm_expr.X_add_number < 0)
13022 imm_expr.X_add_number = -imm_expr.X_add_number;
13023 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13024 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13026 else if (CPU_HAS_SEQ (mips_opts.arch))
13029 load_register (AT, &imm_expr, GPR_SIZE == 64);
13030 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13035 load_register (AT, &imm_expr, GPR_SIZE == 64);
13036 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13039 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13054 if (!mips_opts.micromips)
13056 if (imm_expr.X_add_number > -0x200
13057 && imm_expr.X_add_number <= 0x200)
13059 macro_build (NULL, s, "t,r,.", op[0], op[1],
13060 (int) -imm_expr.X_add_number);
13069 if (imm_expr.X_add_number > -0x8000
13070 && imm_expr.X_add_number <= 0x8000)
13072 imm_expr.X_add_number = -imm_expr.X_add_number;
13073 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13078 load_register (AT, &imm_expr, dbl);
13079 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13101 load_register (AT, &imm_expr, GPR_SIZE == 64);
13102 macro_build (NULL, s, "s,t", op[0], AT);
13107 gas_assert (!mips_opts.micromips);
13108 gas_assert (mips_opts.isa == ISA_MIPS1);
13112 * Is the double cfc1 instruction a bug in the mips assembler;
13113 * or is there a reason for it?
13115 start_noreorder ();
13116 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13117 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13118 macro_build (NULL, "nop", "");
13119 expr1.X_add_number = 3;
13120 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13121 expr1.X_add_number = 2;
13122 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13123 macro_build (NULL, "ctc1", "t,G", AT, RA);
13124 macro_build (NULL, "nop", "");
13125 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13127 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13128 macro_build (NULL, "nop", "");
13145 offbits = (mips_opts.micromips ? 12 : 16);
13151 offbits = (mips_opts.micromips ? 12 : 16);
13163 offbits = (mips_opts.micromips ? 12 : 16);
13170 offbits = (mips_opts.micromips ? 12 : 16);
13176 large_offset = !small_offset_p (off, align, offbits);
13178 expr1.X_add_number = 0;
13183 if (small_offset_p (0, align, 16))
13184 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13185 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13188 load_address (tempreg, ep, &used_at);
13190 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13191 tempreg, tempreg, breg);
13193 offset_reloc[0] = BFD_RELOC_LO16;
13194 offset_reloc[1] = BFD_RELOC_UNUSED;
13195 offset_reloc[2] = BFD_RELOC_UNUSED;
13200 else if (!ust && op[0] == breg)
13211 if (!target_big_endian)
13212 ep->X_add_number += off;
13214 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13216 macro_build (ep, s, "t,o(b)", tempreg, -1,
13217 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13219 if (!target_big_endian)
13220 ep->X_add_number -= off;
13222 ep->X_add_number += off;
13224 macro_build (NULL, s2, "t,~(b)",
13225 tempreg, (int) ep->X_add_number, breg);
13227 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13228 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13230 /* If necessary, move the result in tempreg to the final destination. */
13231 if (!ust && op[0] != tempreg)
13233 /* Protect second load's delay slot. */
13235 move_register (op[0], tempreg);
13241 if (target_big_endian == ust)
13242 ep->X_add_number += off;
13243 tempreg = ust || large_offset ? op[0] : AT;
13244 macro_build (ep, s, "t,o(b)", tempreg, -1,
13245 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13247 /* For halfword transfers we need a temporary register to shuffle
13248 bytes. Unfortunately for M_USH_A we have none available before
13249 the next store as AT holds the base address. We deal with this
13250 case by clobbering TREG and then restoring it as with ULH. */
13251 tempreg = ust == large_offset ? op[0] : AT;
13253 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13255 if (target_big_endian == ust)
13256 ep->X_add_number -= off;
13258 ep->X_add_number += off;
13259 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13260 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13262 /* For M_USH_A re-retrieve the LSB. */
13263 if (ust && large_offset)
13265 if (target_big_endian)
13266 ep->X_add_number += off;
13268 ep->X_add_number -= off;
13269 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13270 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13272 /* For ULH and M_USH_A OR the LSB in. */
13273 if (!ust || large_offset)
13275 tempreg = !large_offset ? AT : op[0];
13276 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13277 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13282 /* FIXME: Check if this is one of the itbl macros, since they
13283 are added dynamically. */
13284 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13287 if (!mips_opts.at && used_at)
13288 as_bad (_("macro used $at after \".set noat\""));
13291 /* Implement macros in mips16 mode. */
13294 mips16_macro (struct mips_cl_insn *ip)
13296 const struct mips_operand_array *operands;
13301 const char *s, *s2, *s3;
13302 unsigned int op[MAX_OPERANDS];
13305 mask = ip->insn_mo->mask;
13307 operands = insn_operands (ip);
13308 for (i = 0; i < MAX_OPERANDS; i++)
13309 if (operands->operand[i])
13310 op[i] = insn_extract_operand (ip, operands->operand[i]);
13314 expr1.X_op = O_constant;
13315 expr1.X_op_symbol = NULL;
13316 expr1.X_add_symbol = NULL;
13317 expr1.X_add_number = 1;
13336 start_noreorder ();
13337 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
13338 expr1.X_add_number = 2;
13339 macro_build (&expr1, "bnez", "x,p", op[2]);
13340 macro_build (NULL, "break", "6", 7);
13342 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13343 since that causes an overflow. We should do that as well,
13344 but I don't see how to do the comparisons without a temporary
13347 macro_build (NULL, s, "x", op[0]);
13366 start_noreorder ();
13367 macro_build (NULL, s, "0,x,y", op[1], op[2]);
13368 expr1.X_add_number = 2;
13369 macro_build (&expr1, "bnez", "x,p", op[2]);
13370 macro_build (NULL, "break", "6", 7);
13372 macro_build (NULL, s2, "x", op[0]);
13378 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13379 macro_build (NULL, "mflo", "x", op[0]);
13387 imm_expr.X_add_number = -imm_expr.X_add_number;
13388 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
13392 imm_expr.X_add_number = -imm_expr.X_add_number;
13393 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13397 imm_expr.X_add_number = -imm_expr.X_add_number;
13398 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13420 goto do_reverse_branch;
13424 goto do_reverse_branch;
13436 goto do_reverse_branch;
13447 macro_build (NULL, s, "x,y", op[0], op[1]);
13448 macro_build (&offset_expr, s2, "p");
13475 goto do_addone_branch_i;
13480 goto do_addone_branch_i;
13495 goto do_addone_branch_i;
13501 do_addone_branch_i:
13502 ++imm_expr.X_add_number;
13505 macro_build (&imm_expr, s, s3, op[0]);
13506 macro_build (&offset_expr, s2, "p");
13510 expr1.X_add_number = 0;
13511 macro_build (&expr1, "slti", "x,8", op[1]);
13512 if (op[0] != op[1])
13513 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13514 expr1.X_add_number = 2;
13515 macro_build (&expr1, "bteqz", "p");
13516 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13521 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13522 opcode bits in *OPCODE_EXTRA. */
13524 static struct mips_opcode *
13525 mips_lookup_insn (struct hash_control *hash, const char *start,
13526 ssize_t length, unsigned int *opcode_extra)
13528 char *name, *dot, *p;
13529 unsigned int mask, suffix;
13531 struct mips_opcode *insn;
13533 /* Make a copy of the instruction so that we can fiddle with it. */
13534 name = xstrndup (start, length);
13536 /* Look up the instruction as-is. */
13537 insn = (struct mips_opcode *) hash_find (hash, name);
13541 dot = strchr (name, '.');
13544 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13545 p = mips_parse_vu0_channels (dot + 1, &mask);
13546 if (*p == 0 && mask != 0)
13549 insn = (struct mips_opcode *) hash_find (hash, name);
13551 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13553 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13559 if (mips_opts.micromips)
13561 /* See if there's an instruction size override suffix,
13562 either `16' or `32', at the end of the mnemonic proper,
13563 that defines the operation, i.e. before the first `.'
13564 character if any. Strip it and retry. */
13565 opend = dot != NULL ? dot - name : length;
13566 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13568 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13574 memcpy (name + opend - 2, name + opend, length - opend + 1);
13575 insn = (struct mips_opcode *) hash_find (hash, name);
13578 forced_insn_length = suffix;
13590 /* Assemble an instruction into its binary format. If the instruction
13591 is a macro, set imm_expr and offset_expr to the values associated
13592 with "I" and "A" operands respectively. Otherwise store the value
13593 of the relocatable field (if any) in offset_expr. In both cases
13594 set offset_reloc to the relocation operators applied to offset_expr. */
13597 mips_ip (char *str, struct mips_cl_insn *insn)
13599 const struct mips_opcode *first, *past;
13600 struct hash_control *hash;
13603 struct mips_operand_token *tokens;
13604 unsigned int opcode_extra;
13606 if (mips_opts.micromips)
13608 hash = micromips_op_hash;
13609 past = µmips_opcodes[bfd_micromips_num_opcodes];
13614 past = &mips_opcodes[NUMOPCODES];
13616 forced_insn_length = 0;
13619 /* We first try to match an instruction up to a space or to the end. */
13620 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13623 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13626 set_insn_error (0, _("unrecognized opcode"));
13630 if (strcmp (first->name, "li.s") == 0)
13632 else if (strcmp (first->name, "li.d") == 0)
13636 tokens = mips_parse_arguments (str + end, format);
13640 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13641 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
13642 set_insn_error (0, _("invalid operands"));
13644 obstack_free (&mips_operand_tokens, tokens);
13647 /* As for mips_ip, but used when assembling MIPS16 code.
13648 Also set forced_insn_length to the resulting instruction size in
13649 bytes if the user explicitly requested a small or extended instruction. */
13652 mips16_ip (char *str, struct mips_cl_insn *insn)
13655 struct mips_opcode *first;
13656 struct mips_operand_token *tokens;
13658 forced_insn_length = 0;
13660 for (s = str; ISLOWER (*s); ++s)
13674 if (s[1] == 't' && s[2] == ' ')
13676 forced_insn_length = 2;
13680 else if (s[1] == 'e' && s[2] == ' ')
13682 forced_insn_length = 4;
13686 /* Fall through. */
13688 set_insn_error (0, _("unrecognized opcode"));
13692 if (mips_opts.noautoextend && !forced_insn_length)
13693 forced_insn_length = 2;
13696 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13701 set_insn_error (0, _("unrecognized opcode"));
13705 tokens = mips_parse_arguments (s, 0);
13709 if (!match_mips16_insns (insn, first, tokens))
13710 set_insn_error (0, _("invalid operands"));
13712 obstack_free (&mips_operand_tokens, tokens);
13715 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13716 NBITS is the number of significant bits in VAL. */
13718 static unsigned long
13719 mips16_immed_extend (offsetT val, unsigned int nbits)
13724 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13727 else if (nbits == 15)
13729 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13734 extval = ((val & 0x1f) << 6) | (val & 0x20);
13737 return (extval << 16) | val;
13740 /* Like decode_mips16_operand, but require the operand to be defined and
13741 require it to be an integer. */
13743 static const struct mips_int_operand *
13744 mips16_immed_operand (int type, bfd_boolean extended_p)
13746 const struct mips_operand *operand;
13748 operand = decode_mips16_operand (type, extended_p);
13749 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13751 return (const struct mips_int_operand *) operand;
13754 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13757 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13758 bfd_reloc_code_real_type reloc, offsetT sval)
13760 int min_val, max_val;
13762 min_val = mips_int_operand_min (operand);
13763 max_val = mips_int_operand_max (operand);
13764 if (reloc != BFD_RELOC_UNUSED)
13767 sval = SEXT_16BIT (sval);
13772 return (sval >= min_val
13774 && (sval & ((1 << operand->shift) - 1)) == 0);
13777 /* Install immediate value VAL into MIPS16 instruction *INSN,
13778 extending it if necessary. The instruction in *INSN may
13779 already be extended.
13781 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13782 if none. In the former case, VAL is a 16-bit number with no
13783 defined signedness.
13785 TYPE is the type of the immediate field. USER_INSN_LENGTH
13786 is the length that the user requested, or 0 if none. */
13789 mips16_immed (const char *file, unsigned int line, int type,
13790 bfd_reloc_code_real_type reloc, offsetT val,
13791 unsigned int user_insn_length, unsigned long *insn)
13793 const struct mips_int_operand *operand;
13794 unsigned int uval, length;
13796 operand = mips16_immed_operand (type, FALSE);
13797 if (!mips16_immed_in_range_p (operand, reloc, val))
13799 /* We need an extended instruction. */
13800 if (user_insn_length == 2)
13801 as_bad_where (file, line, _("invalid unextended operand value"));
13803 *insn |= MIPS16_EXTEND;
13805 else if (user_insn_length == 4)
13807 /* The operand doesn't force an unextended instruction to be extended.
13808 Warn if the user wanted an extended instruction anyway. */
13809 *insn |= MIPS16_EXTEND;
13810 as_warn_where (file, line,
13811 _("extended operand requested but not required"));
13814 length = mips16_opcode_length (*insn);
13817 operand = mips16_immed_operand (type, TRUE);
13818 if (!mips16_immed_in_range_p (operand, reloc, val))
13819 as_bad_where (file, line,
13820 _("operand value out of range for instruction"));
13822 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13824 *insn = mips_insert_operand (&operand->root, *insn, uval);
13826 *insn |= mips16_immed_extend (uval, operand->root.size);
13829 struct percent_op_match
13832 bfd_reloc_code_real_type reloc;
13835 static const struct percent_op_match mips_percent_op[] =
13837 {"%lo", BFD_RELOC_LO16},
13838 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13839 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13840 {"%call16", BFD_RELOC_MIPS_CALL16},
13841 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13842 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13843 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13844 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13845 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13846 {"%got", BFD_RELOC_MIPS_GOT16},
13847 {"%gp_rel", BFD_RELOC_GPREL16},
13848 {"%half", BFD_RELOC_16},
13849 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13850 {"%higher", BFD_RELOC_MIPS_HIGHER},
13851 {"%neg", BFD_RELOC_MIPS_SUB},
13852 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13853 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13854 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13855 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13856 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13857 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13858 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13859 {"%hi", BFD_RELOC_HI16_S},
13860 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
13861 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
13864 static const struct percent_op_match mips16_percent_op[] =
13866 {"%lo", BFD_RELOC_MIPS16_LO16},
13867 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13868 {"%got", BFD_RELOC_MIPS16_GOT16},
13869 {"%call16", BFD_RELOC_MIPS16_CALL16},
13870 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13871 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13872 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13873 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13874 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13875 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13876 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13877 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13881 /* Return true if *STR points to a relocation operator. When returning true,
13882 move *STR over the operator and store its relocation code in *RELOC.
13883 Leave both *STR and *RELOC alone when returning false. */
13886 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13888 const struct percent_op_match *percent_op;
13891 if (mips_opts.mips16)
13893 percent_op = mips16_percent_op;
13894 limit = ARRAY_SIZE (mips16_percent_op);
13898 percent_op = mips_percent_op;
13899 limit = ARRAY_SIZE (mips_percent_op);
13902 for (i = 0; i < limit; i++)
13903 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13905 int len = strlen (percent_op[i].str);
13907 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13910 *str += strlen (percent_op[i].str);
13911 *reloc = percent_op[i].reloc;
13913 /* Check whether the output BFD supports this relocation.
13914 If not, issue an error and fall back on something safe. */
13915 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13917 as_bad (_("relocation %s isn't supported by the current ABI"),
13918 percent_op[i].str);
13919 *reloc = BFD_RELOC_UNUSED;
13927 /* Parse string STR as a 16-bit relocatable operand. Store the
13928 expression in *EP and the relocations in the array starting
13929 at RELOC. Return the number of relocation operators used.
13931 On exit, EXPR_END points to the first character after the expression. */
13934 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13937 bfd_reloc_code_real_type reversed_reloc[3];
13938 size_t reloc_index, i;
13939 int crux_depth, str_depth;
13942 /* Search for the start of the main expression, recoding relocations
13943 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13944 of the main expression and with CRUX_DEPTH containing the number
13945 of open brackets at that point. */
13952 crux_depth = str_depth;
13954 /* Skip over whitespace and brackets, keeping count of the number
13956 while (*str == ' ' || *str == '\t' || *str == '(')
13961 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13962 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13964 my_getExpression (ep, crux);
13967 /* Match every open bracket. */
13968 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13972 if (crux_depth > 0)
13973 as_bad (_("unclosed '('"));
13977 if (reloc_index != 0)
13979 prev_reloc_op_frag = frag_now;
13980 for (i = 0; i < reloc_index; i++)
13981 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13984 return reloc_index;
13988 my_getExpression (expressionS *ep, char *str)
13992 save_in = input_line_pointer;
13993 input_line_pointer = str;
13995 expr_end = input_line_pointer;
13996 input_line_pointer = save_in;
14000 md_atof (int type, char *litP, int *sizeP)
14002 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14006 md_number_to_chars (char *buf, valueT val, int n)
14008 if (target_big_endian)
14009 number_to_chars_bigendian (buf, val, n);
14011 number_to_chars_littleendian (buf, val, n);
14014 static int support_64bit_objects(void)
14016 const char **list, **l;
14019 list = bfd_target_list ();
14020 for (l = list; *l != NULL; l++)
14021 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14022 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14024 yes = (*l != NULL);
14029 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14030 NEW_VALUE. Warn if another value was already specified. Note:
14031 we have to defer parsing the -march and -mtune arguments in order
14032 to handle 'from-abi' correctly, since the ABI might be specified
14033 in a later argument. */
14036 mips_set_option_string (const char **string_ptr, const char *new_value)
14038 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14039 as_warn (_("a different %s was already specified, is now %s"),
14040 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14043 *string_ptr = new_value;
14047 md_parse_option (int c, const char *arg)
14051 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14052 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14054 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14055 c == mips_ases[i].option_on);
14061 case OPTION_CONSTRUCT_FLOATS:
14062 mips_disable_float_construction = 0;
14065 case OPTION_NO_CONSTRUCT_FLOATS:
14066 mips_disable_float_construction = 1;
14078 target_big_endian = 1;
14082 target_big_endian = 0;
14088 else if (arg[0] == '0')
14090 else if (arg[0] == '1')
14100 mips_debug = atoi (arg);
14104 file_mips_opts.isa = ISA_MIPS1;
14108 file_mips_opts.isa = ISA_MIPS2;
14112 file_mips_opts.isa = ISA_MIPS3;
14116 file_mips_opts.isa = ISA_MIPS4;
14120 file_mips_opts.isa = ISA_MIPS5;
14123 case OPTION_MIPS32:
14124 file_mips_opts.isa = ISA_MIPS32;
14127 case OPTION_MIPS32R2:
14128 file_mips_opts.isa = ISA_MIPS32R2;
14131 case OPTION_MIPS32R3:
14132 file_mips_opts.isa = ISA_MIPS32R3;
14135 case OPTION_MIPS32R5:
14136 file_mips_opts.isa = ISA_MIPS32R5;
14139 case OPTION_MIPS32R6:
14140 file_mips_opts.isa = ISA_MIPS32R6;
14143 case OPTION_MIPS64R2:
14144 file_mips_opts.isa = ISA_MIPS64R2;
14147 case OPTION_MIPS64R3:
14148 file_mips_opts.isa = ISA_MIPS64R3;
14151 case OPTION_MIPS64R5:
14152 file_mips_opts.isa = ISA_MIPS64R5;
14155 case OPTION_MIPS64R6:
14156 file_mips_opts.isa = ISA_MIPS64R6;
14159 case OPTION_MIPS64:
14160 file_mips_opts.isa = ISA_MIPS64;
14164 mips_set_option_string (&mips_tune_string, arg);
14168 mips_set_option_string (&mips_arch_string, arg);
14172 mips_set_option_string (&mips_arch_string, "4650");
14173 mips_set_option_string (&mips_tune_string, "4650");
14176 case OPTION_NO_M4650:
14180 mips_set_option_string (&mips_arch_string, "4010");
14181 mips_set_option_string (&mips_tune_string, "4010");
14184 case OPTION_NO_M4010:
14188 mips_set_option_string (&mips_arch_string, "4100");
14189 mips_set_option_string (&mips_tune_string, "4100");
14192 case OPTION_NO_M4100:
14196 mips_set_option_string (&mips_arch_string, "3900");
14197 mips_set_option_string (&mips_tune_string, "3900");
14200 case OPTION_NO_M3900:
14203 case OPTION_MICROMIPS:
14204 if (file_mips_opts.mips16 == 1)
14206 as_bad (_("-mmicromips cannot be used with -mips16"));
14209 file_mips_opts.micromips = 1;
14210 mips_no_prev_insn ();
14213 case OPTION_NO_MICROMIPS:
14214 file_mips_opts.micromips = 0;
14215 mips_no_prev_insn ();
14218 case OPTION_MIPS16:
14219 if (file_mips_opts.micromips == 1)
14221 as_bad (_("-mips16 cannot be used with -micromips"));
14224 file_mips_opts.mips16 = 1;
14225 mips_no_prev_insn ();
14228 case OPTION_NO_MIPS16:
14229 file_mips_opts.mips16 = 0;
14230 mips_no_prev_insn ();
14233 case OPTION_FIX_24K:
14237 case OPTION_NO_FIX_24K:
14241 case OPTION_FIX_RM7000:
14242 mips_fix_rm7000 = 1;
14245 case OPTION_NO_FIX_RM7000:
14246 mips_fix_rm7000 = 0;
14249 case OPTION_FIX_LOONGSON2F_JUMP:
14250 mips_fix_loongson2f_jump = TRUE;
14253 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14254 mips_fix_loongson2f_jump = FALSE;
14257 case OPTION_FIX_LOONGSON2F_NOP:
14258 mips_fix_loongson2f_nop = TRUE;
14261 case OPTION_NO_FIX_LOONGSON2F_NOP:
14262 mips_fix_loongson2f_nop = FALSE;
14265 case OPTION_FIX_VR4120:
14266 mips_fix_vr4120 = 1;
14269 case OPTION_NO_FIX_VR4120:
14270 mips_fix_vr4120 = 0;
14273 case OPTION_FIX_VR4130:
14274 mips_fix_vr4130 = 1;
14277 case OPTION_NO_FIX_VR4130:
14278 mips_fix_vr4130 = 0;
14281 case OPTION_FIX_CN63XXP1:
14282 mips_fix_cn63xxp1 = TRUE;
14285 case OPTION_NO_FIX_CN63XXP1:
14286 mips_fix_cn63xxp1 = FALSE;
14289 case OPTION_RELAX_BRANCH:
14290 mips_relax_branch = 1;
14293 case OPTION_NO_RELAX_BRANCH:
14294 mips_relax_branch = 0;
14297 case OPTION_INSN32:
14298 file_mips_opts.insn32 = TRUE;
14301 case OPTION_NO_INSN32:
14302 file_mips_opts.insn32 = FALSE;
14305 case OPTION_MSHARED:
14306 mips_in_shared = TRUE;
14309 case OPTION_MNO_SHARED:
14310 mips_in_shared = FALSE;
14313 case OPTION_MSYM32:
14314 file_mips_opts.sym32 = TRUE;
14317 case OPTION_MNO_SYM32:
14318 file_mips_opts.sym32 = FALSE;
14321 /* When generating ELF code, we permit -KPIC and -call_shared to
14322 select SVR4_PIC, and -non_shared to select no PIC. This is
14323 intended to be compatible with Irix 5. */
14324 case OPTION_CALL_SHARED:
14325 mips_pic = SVR4_PIC;
14326 mips_abicalls = TRUE;
14329 case OPTION_CALL_NONPIC:
14331 mips_abicalls = TRUE;
14334 case OPTION_NON_SHARED:
14336 mips_abicalls = FALSE;
14339 /* The -xgot option tells the assembler to use 32 bit offsets
14340 when accessing the got in SVR4_PIC mode. It is for Irix
14347 g_switch_value = atoi (arg);
14351 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14354 mips_abi = O32_ABI;
14358 mips_abi = N32_ABI;
14362 mips_abi = N64_ABI;
14363 if (!support_64bit_objects())
14364 as_fatal (_("no compiled in support for 64 bit object file format"));
14368 file_mips_opts.gp = 32;
14372 file_mips_opts.gp = 64;
14376 file_mips_opts.fp = 32;
14380 file_mips_opts.fp = 0;
14384 file_mips_opts.fp = 64;
14387 case OPTION_ODD_SPREG:
14388 file_mips_opts.oddspreg = 1;
14391 case OPTION_NO_ODD_SPREG:
14392 file_mips_opts.oddspreg = 0;
14395 case OPTION_SINGLE_FLOAT:
14396 file_mips_opts.single_float = 1;
14399 case OPTION_DOUBLE_FLOAT:
14400 file_mips_opts.single_float = 0;
14403 case OPTION_SOFT_FLOAT:
14404 file_mips_opts.soft_float = 1;
14407 case OPTION_HARD_FLOAT:
14408 file_mips_opts.soft_float = 0;
14412 if (strcmp (arg, "32") == 0)
14413 mips_abi = O32_ABI;
14414 else if (strcmp (arg, "o64") == 0)
14415 mips_abi = O64_ABI;
14416 else if (strcmp (arg, "n32") == 0)
14417 mips_abi = N32_ABI;
14418 else if (strcmp (arg, "64") == 0)
14420 mips_abi = N64_ABI;
14421 if (! support_64bit_objects())
14422 as_fatal (_("no compiled in support for 64 bit object file "
14425 else if (strcmp (arg, "eabi") == 0)
14426 mips_abi = EABI_ABI;
14429 as_fatal (_("invalid abi -mabi=%s"), arg);
14434 case OPTION_M7000_HILO_FIX:
14435 mips_7000_hilo_fix = TRUE;
14438 case OPTION_MNO_7000_HILO_FIX:
14439 mips_7000_hilo_fix = FALSE;
14442 case OPTION_MDEBUG:
14443 mips_flag_mdebug = TRUE;
14446 case OPTION_NO_MDEBUG:
14447 mips_flag_mdebug = FALSE;
14451 mips_flag_pdr = TRUE;
14454 case OPTION_NO_PDR:
14455 mips_flag_pdr = FALSE;
14458 case OPTION_MVXWORKS_PIC:
14459 mips_pic = VXWORKS_PIC;
14463 if (strcmp (arg, "2008") == 0)
14465 else if (strcmp (arg, "legacy") == 0)
14469 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14478 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14483 /* Set up globals to tune for the ISA or processor described by INFO. */
14486 mips_set_tune (const struct mips_cpu_info *info)
14489 mips_tune = info->cpu;
14494 mips_after_parse_args (void)
14496 const struct mips_cpu_info *arch_info = 0;
14497 const struct mips_cpu_info *tune_info = 0;
14499 /* GP relative stuff not working for PE */
14500 if (strncmp (TARGET_OS, "pe", 2) == 0)
14502 if (g_switch_seen && g_switch_value != 0)
14503 as_bad (_("-G not supported in this configuration"));
14504 g_switch_value = 0;
14507 if (mips_abi == NO_ABI)
14508 mips_abi = MIPS_DEFAULT_ABI;
14510 /* The following code determines the architecture.
14511 Similar code was added to GCC 3.3 (see override_options() in
14512 config/mips/mips.c). The GAS and GCC code should be kept in sync
14513 as much as possible. */
14515 if (mips_arch_string != 0)
14516 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14518 if (file_mips_opts.isa != ISA_UNKNOWN)
14520 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14521 ISA level specified by -mipsN, while arch_info->isa contains
14522 the -march selection (if any). */
14523 if (arch_info != 0)
14525 /* -march takes precedence over -mipsN, since it is more descriptive.
14526 There's no harm in specifying both as long as the ISA levels
14528 if (file_mips_opts.isa != arch_info->isa)
14529 as_bad (_("-%s conflicts with the other architecture options,"
14530 " which imply -%s"),
14531 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14532 mips_cpu_info_from_isa (arch_info->isa)->name);
14535 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14538 if (arch_info == 0)
14540 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14541 gas_assert (arch_info);
14544 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14545 as_bad (_("-march=%s is not compatible with the selected ABI"),
14548 file_mips_opts.arch = arch_info->cpu;
14549 file_mips_opts.isa = arch_info->isa;
14551 /* Set up initial mips_opts state. */
14552 mips_opts = file_mips_opts;
14554 /* The register size inference code is now placed in
14555 file_mips_check_options. */
14557 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14559 if (mips_tune_string != 0)
14560 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14562 if (tune_info == 0)
14563 mips_set_tune (arch_info);
14565 mips_set_tune (tune_info);
14567 if (mips_flag_mdebug < 0)
14568 mips_flag_mdebug = 0;
14572 mips_init_after_args (void)
14574 /* initialize opcodes */
14575 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14576 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14580 md_pcrel_from (fixS *fixP)
14582 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14583 switch (fixP->fx_r_type)
14585 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14586 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14587 /* Return the address of the delay slot. */
14590 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14591 case BFD_RELOC_MICROMIPS_JMP:
14592 case BFD_RELOC_16_PCREL_S2:
14593 case BFD_RELOC_MIPS_21_PCREL_S2:
14594 case BFD_RELOC_MIPS_26_PCREL_S2:
14595 case BFD_RELOC_MIPS_JMP:
14596 /* Return the address of the delay slot. */
14604 /* This is called before the symbol table is processed. In order to
14605 work with gcc when using mips-tfile, we must keep all local labels.
14606 However, in other cases, we want to discard them. If we were
14607 called with -g, but we didn't see any debugging information, it may
14608 mean that gcc is smuggling debugging information through to
14609 mips-tfile, in which case we must generate all local labels. */
14612 mips_frob_file_before_adjust (void)
14614 #ifndef NO_ECOFF_DEBUGGING
14615 if (ECOFF_DEBUGGING
14617 && ! ecoff_debugging_seen)
14618 flag_keep_locals = 1;
14622 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14623 the corresponding LO16 reloc. This is called before md_apply_fix and
14624 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14625 relocation operators.
14627 For our purposes, a %lo() expression matches a %got() or %hi()
14630 (a) it refers to the same symbol; and
14631 (b) the offset applied in the %lo() expression is no lower than
14632 the offset applied in the %got() or %hi().
14634 (b) allows us to cope with code like:
14637 lh $4,%lo(foo+2)($4)
14639 ...which is legal on RELA targets, and has a well-defined behaviour
14640 if the user knows that adding 2 to "foo" will not induce a carry to
14643 When several %lo()s match a particular %got() or %hi(), we use the
14644 following rules to distinguish them:
14646 (1) %lo()s with smaller offsets are a better match than %lo()s with
14649 (2) %lo()s with no matching %got() or %hi() are better than those
14650 that already have a matching %got() or %hi().
14652 (3) later %lo()s are better than earlier %lo()s.
14654 These rules are applied in order.
14656 (1) means, among other things, that %lo()s with identical offsets are
14657 chosen if they exist.
14659 (2) means that we won't associate several high-part relocations with
14660 the same low-part relocation unless there's no alternative. Having
14661 several high parts for the same low part is a GNU extension; this rule
14662 allows careful users to avoid it.
14664 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14665 with the last high-part relocation being at the front of the list.
14666 It therefore makes sense to choose the last matching low-part
14667 relocation, all other things being equal. It's also easier
14668 to code that way. */
14671 mips_frob_file (void)
14673 struct mips_hi_fixup *l;
14674 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14676 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14678 segment_info_type *seginfo;
14679 bfd_boolean matched_lo_p;
14680 fixS **hi_pos, **lo_pos, **pos;
14682 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14684 /* If a GOT16 relocation turns out to be against a global symbol,
14685 there isn't supposed to be a matching LO. Ignore %gots against
14686 constants; we'll report an error for those later. */
14687 if (got16_reloc_p (l->fixp->fx_r_type)
14688 && !(l->fixp->fx_addsy
14689 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14692 /* Check quickly whether the next fixup happens to be a matching %lo. */
14693 if (fixup_has_matching_lo_p (l->fixp))
14696 seginfo = seg_info (l->seg);
14698 /* Set HI_POS to the position of this relocation in the chain.
14699 Set LO_POS to the position of the chosen low-part relocation.
14700 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14701 relocation that matches an immediately-preceding high-part
14705 matched_lo_p = FALSE;
14706 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14708 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14710 if (*pos == l->fixp)
14713 if ((*pos)->fx_r_type == looking_for_rtype
14714 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14715 && (*pos)->fx_offset >= l->fixp->fx_offset
14717 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14719 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14722 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14723 && fixup_has_matching_lo_p (*pos));
14726 /* If we found a match, remove the high-part relocation from its
14727 current position and insert it before the low-part relocation.
14728 Make the offsets match so that fixup_has_matching_lo_p()
14731 We don't warn about unmatched high-part relocations since some
14732 versions of gcc have been known to emit dead "lui ...%hi(...)"
14734 if (lo_pos != NULL)
14736 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14737 if (l->fixp->fx_next != *lo_pos)
14739 *hi_pos = l->fixp->fx_next;
14740 l->fixp->fx_next = *lo_pos;
14748 mips_force_relocation (fixS *fixp)
14750 if (generic_force_reloc (fixp))
14753 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14754 so that the linker relaxation can update targets. */
14755 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14756 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14757 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14760 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14761 if (ISA_IS_R6 (mips_opts.isa)
14762 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14763 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14764 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14765 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14766 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14767 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14768 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14774 /* Read the instruction associated with RELOC from BUF. */
14776 static unsigned int
14777 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14779 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14780 return read_compressed_insn (buf, 4);
14782 return read_insn (buf);
14785 /* Write instruction INSN to BUF, given that it has been relocated
14789 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14790 unsigned long insn)
14792 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14793 write_compressed_insn (buf, insn, 4);
14795 write_insn (buf, insn);
14798 /* Apply a fixup to the object file. */
14801 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14804 unsigned long insn;
14805 reloc_howto_type *howto;
14807 if (fixP->fx_pcrel)
14808 switch (fixP->fx_r_type)
14810 case BFD_RELOC_16_PCREL_S2:
14811 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14812 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14813 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14814 case BFD_RELOC_32_PCREL:
14815 case BFD_RELOC_MIPS_21_PCREL_S2:
14816 case BFD_RELOC_MIPS_26_PCREL_S2:
14817 case BFD_RELOC_MIPS_18_PCREL_S3:
14818 case BFD_RELOC_MIPS_19_PCREL_S2:
14819 case BFD_RELOC_HI16_S_PCREL:
14820 case BFD_RELOC_LO16_PCREL:
14824 fixP->fx_r_type = BFD_RELOC_32_PCREL;
14828 as_bad_where (fixP->fx_file, fixP->fx_line,
14829 _("PC-relative reference to a different section"));
14833 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14834 that have no MIPS ELF equivalent. */
14835 if (fixP->fx_r_type != BFD_RELOC_8)
14837 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14842 gas_assert (fixP->fx_size == 2
14843 || fixP->fx_size == 4
14844 || fixP->fx_r_type == BFD_RELOC_8
14845 || fixP->fx_r_type == BFD_RELOC_16
14846 || fixP->fx_r_type == BFD_RELOC_64
14847 || fixP->fx_r_type == BFD_RELOC_CTOR
14848 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14849 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14850 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14851 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14852 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
14853 || fixP->fx_r_type == BFD_RELOC_NONE);
14855 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14857 /* Don't treat parts of a composite relocation as done. There are two
14860 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14861 should nevertheless be emitted if the first part is.
14863 (2) In normal usage, composite relocations are never assembly-time
14864 constants. The easiest way of dealing with the pathological
14865 exceptions is to generate a relocation against STN_UNDEF and
14866 leave everything up to the linker. */
14867 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14870 switch (fixP->fx_r_type)
14872 case BFD_RELOC_MIPS_TLS_GD:
14873 case BFD_RELOC_MIPS_TLS_LDM:
14874 case BFD_RELOC_MIPS_TLS_DTPREL32:
14875 case BFD_RELOC_MIPS_TLS_DTPREL64:
14876 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14877 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14878 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14879 case BFD_RELOC_MIPS_TLS_TPREL32:
14880 case BFD_RELOC_MIPS_TLS_TPREL64:
14881 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14882 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14883 case BFD_RELOC_MICROMIPS_TLS_GD:
14884 case BFD_RELOC_MICROMIPS_TLS_LDM:
14885 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14886 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14887 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14888 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14889 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14890 case BFD_RELOC_MIPS16_TLS_GD:
14891 case BFD_RELOC_MIPS16_TLS_LDM:
14892 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14893 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14894 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14895 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14896 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14897 if (!fixP->fx_addsy)
14899 as_bad_where (fixP->fx_file, fixP->fx_line,
14900 _("TLS relocation against a constant"));
14903 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14906 case BFD_RELOC_MIPS_JMP:
14907 case BFD_RELOC_MIPS_SHIFT5:
14908 case BFD_RELOC_MIPS_SHIFT6:
14909 case BFD_RELOC_MIPS_GOT_DISP:
14910 case BFD_RELOC_MIPS_GOT_PAGE:
14911 case BFD_RELOC_MIPS_GOT_OFST:
14912 case BFD_RELOC_MIPS_SUB:
14913 case BFD_RELOC_MIPS_INSERT_A:
14914 case BFD_RELOC_MIPS_INSERT_B:
14915 case BFD_RELOC_MIPS_DELETE:
14916 case BFD_RELOC_MIPS_HIGHEST:
14917 case BFD_RELOC_MIPS_HIGHER:
14918 case BFD_RELOC_MIPS_SCN_DISP:
14919 case BFD_RELOC_MIPS_REL16:
14920 case BFD_RELOC_MIPS_RELGOT:
14921 case BFD_RELOC_MIPS_JALR:
14922 case BFD_RELOC_HI16:
14923 case BFD_RELOC_HI16_S:
14924 case BFD_RELOC_LO16:
14925 case BFD_RELOC_GPREL16:
14926 case BFD_RELOC_MIPS_LITERAL:
14927 case BFD_RELOC_MIPS_CALL16:
14928 case BFD_RELOC_MIPS_GOT16:
14929 case BFD_RELOC_GPREL32:
14930 case BFD_RELOC_MIPS_GOT_HI16:
14931 case BFD_RELOC_MIPS_GOT_LO16:
14932 case BFD_RELOC_MIPS_CALL_HI16:
14933 case BFD_RELOC_MIPS_CALL_LO16:
14934 case BFD_RELOC_MIPS16_GPREL:
14935 case BFD_RELOC_MIPS16_GOT16:
14936 case BFD_RELOC_MIPS16_CALL16:
14937 case BFD_RELOC_MIPS16_HI16:
14938 case BFD_RELOC_MIPS16_HI16_S:
14939 case BFD_RELOC_MIPS16_LO16:
14940 case BFD_RELOC_MIPS16_JMP:
14941 case BFD_RELOC_MICROMIPS_JMP:
14942 case BFD_RELOC_MICROMIPS_GOT_DISP:
14943 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14944 case BFD_RELOC_MICROMIPS_GOT_OFST:
14945 case BFD_RELOC_MICROMIPS_SUB:
14946 case BFD_RELOC_MICROMIPS_HIGHEST:
14947 case BFD_RELOC_MICROMIPS_HIGHER:
14948 case BFD_RELOC_MICROMIPS_SCN_DISP:
14949 case BFD_RELOC_MICROMIPS_JALR:
14950 case BFD_RELOC_MICROMIPS_HI16:
14951 case BFD_RELOC_MICROMIPS_HI16_S:
14952 case BFD_RELOC_MICROMIPS_LO16:
14953 case BFD_RELOC_MICROMIPS_GPREL16:
14954 case BFD_RELOC_MICROMIPS_LITERAL:
14955 case BFD_RELOC_MICROMIPS_CALL16:
14956 case BFD_RELOC_MICROMIPS_GOT16:
14957 case BFD_RELOC_MICROMIPS_GOT_HI16:
14958 case BFD_RELOC_MICROMIPS_GOT_LO16:
14959 case BFD_RELOC_MICROMIPS_CALL_HI16:
14960 case BFD_RELOC_MICROMIPS_CALL_LO16:
14961 case BFD_RELOC_MIPS_EH:
14966 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14968 insn = read_reloc_insn (buf, fixP->fx_r_type);
14969 if (mips16_reloc_p (fixP->fx_r_type))
14970 insn |= mips16_immed_extend (value, 16);
14972 insn |= (value & 0xffff);
14973 write_reloc_insn (buf, fixP->fx_r_type, insn);
14976 as_bad_where (fixP->fx_file, fixP->fx_line,
14977 _("unsupported constant in relocation"));
14982 /* This is handled like BFD_RELOC_32, but we output a sign
14983 extended value if we are only 32 bits. */
14986 if (8 <= sizeof (valueT))
14987 md_number_to_chars (buf, *valP, 8);
14992 if ((*valP & 0x80000000) != 0)
14996 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14997 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15002 case BFD_RELOC_RVA:
15004 case BFD_RELOC_32_PCREL:
15007 /* If we are deleting this reloc entry, we must fill in the
15008 value now. This can happen if we have a .word which is not
15009 resolved when it appears but is later defined. */
15011 md_number_to_chars (buf, *valP, fixP->fx_size);
15014 case BFD_RELOC_MIPS_21_PCREL_S2:
15015 case BFD_RELOC_MIPS_26_PCREL_S2:
15016 if ((*valP & 0x3) != 0)
15017 as_bad_where (fixP->fx_file, fixP->fx_line,
15018 _("branch to misaligned address (%lx)"), (long) *valP);
15020 gas_assert (!fixP->fx_done);
15023 case BFD_RELOC_MIPS_18_PCREL_S3:
15024 if ((S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15025 as_bad_where (fixP->fx_file, fixP->fx_line,
15026 _("PC-relative access using misaligned symbol (%lx)"),
15027 (long) S_GET_VALUE (fixP->fx_addsy));
15028 if ((fixP->fx_offset & 0x7) != 0)
15029 as_bad_where (fixP->fx_file, fixP->fx_line,
15030 _("PC-relative access using misaligned offset (%lx)"),
15031 (long) fixP->fx_offset);
15033 gas_assert (!fixP->fx_done);
15036 case BFD_RELOC_MIPS_19_PCREL_S2:
15037 if ((*valP & 0x3) != 0)
15038 as_bad_where (fixP->fx_file, fixP->fx_line,
15039 _("PC-relative access to misaligned address (%lx)"),
15040 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15042 gas_assert (!fixP->fx_done);
15045 case BFD_RELOC_HI16_S_PCREL:
15046 case BFD_RELOC_LO16_PCREL:
15047 gas_assert (!fixP->fx_done);
15050 case BFD_RELOC_16_PCREL_S2:
15051 if ((*valP & 0x3) != 0)
15052 as_bad_where (fixP->fx_file, fixP->fx_line,
15053 _("branch to misaligned address (%lx)"), (long) *valP);
15055 /* We need to save the bits in the instruction since fixup_segment()
15056 might be deleting the relocation entry (i.e., a branch within
15057 the current segment). */
15058 if (! fixP->fx_done)
15061 /* Update old instruction data. */
15062 insn = read_insn (buf);
15064 if (*valP + 0x20000 <= 0x3ffff)
15066 insn |= (*valP >> 2) & 0xffff;
15067 write_insn (buf, insn);
15069 else if (mips_pic == NO_PIC
15071 && fixP->fx_frag->fr_address >= text_section->vma
15072 && (fixP->fx_frag->fr_address
15073 < text_section->vma + bfd_get_section_size (text_section))
15074 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15075 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15076 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15078 /* The branch offset is too large. If this is an
15079 unconditional branch, and we are not generating PIC code,
15080 we can convert it to an absolute jump instruction. */
15081 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15082 insn = 0x0c000000; /* jal */
15084 insn = 0x08000000; /* j */
15085 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15087 fixP->fx_addsy = section_symbol (text_section);
15088 *valP += md_pcrel_from (fixP);
15089 write_insn (buf, insn);
15093 /* If we got here, we have branch-relaxation disabled,
15094 and there's nothing we can do to fix this instruction
15095 without turning it into a longer sequence. */
15096 as_bad_where (fixP->fx_file, fixP->fx_line,
15097 _("branch out of range"));
15101 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15102 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15103 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15104 /* We adjust the offset back to even. */
15105 if ((*valP & 0x1) != 0)
15108 if (! fixP->fx_done)
15111 /* Should never visit here, because we keep the relocation. */
15115 case BFD_RELOC_VTABLE_INHERIT:
15118 && !S_IS_DEFINED (fixP->fx_addsy)
15119 && !S_IS_WEAK (fixP->fx_addsy))
15120 S_SET_WEAK (fixP->fx_addsy);
15123 case BFD_RELOC_NONE:
15124 case BFD_RELOC_VTABLE_ENTRY:
15132 /* Remember value for tc_gen_reloc. */
15133 fixP->fx_addnumber = *valP;
15143 c = get_symbol_name (&name);
15144 p = (symbolS *) symbol_find_or_make (name);
15145 (void) restore_line_pointer (c);
15149 /* Align the current frag to a given power of two. If a particular
15150 fill byte should be used, FILL points to an integer that contains
15151 that byte, otherwise FILL is null.
15153 This function used to have the comment:
15155 The MIPS assembler also automatically adjusts any preceding label.
15157 The implementation therefore applied the adjustment to a maximum of
15158 one label. However, other label adjustments are applied to batches
15159 of labels, and adjusting just one caused problems when new labels
15160 were added for the sake of debugging or unwind information.
15161 We therefore adjust all preceding labels (given as LABELS) instead. */
15164 mips_align (int to, int *fill, struct insn_label_list *labels)
15166 mips_emit_delays ();
15167 mips_record_compressed_mode ();
15168 if (fill == NULL && subseg_text_p (now_seg))
15169 frag_align_code (to, 0);
15171 frag_align (to, fill ? *fill : 0, 0);
15172 record_alignment (now_seg, to);
15173 mips_move_labels (labels, FALSE);
15176 /* Align to a given power of two. .align 0 turns off the automatic
15177 alignment used by the data creating pseudo-ops. */
15180 s_align (int x ATTRIBUTE_UNUSED)
15182 int temp, fill_value, *fill_ptr;
15183 long max_alignment = 28;
15185 /* o Note that the assembler pulls down any immediately preceding label
15186 to the aligned address.
15187 o It's not documented but auto alignment is reinstated by
15188 a .align pseudo instruction.
15189 o Note also that after auto alignment is turned off the mips assembler
15190 issues an error on attempt to assemble an improperly aligned data item.
15193 temp = get_absolute_expression ();
15194 if (temp > max_alignment)
15195 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15198 as_warn (_("alignment negative, 0 assumed"));
15201 if (*input_line_pointer == ',')
15203 ++input_line_pointer;
15204 fill_value = get_absolute_expression ();
15205 fill_ptr = &fill_value;
15211 segment_info_type *si = seg_info (now_seg);
15212 struct insn_label_list *l = si->label_list;
15213 /* Auto alignment should be switched on by next section change. */
15215 mips_align (temp, fill_ptr, l);
15222 demand_empty_rest_of_line ();
15226 s_change_sec (int sec)
15230 /* The ELF backend needs to know that we are changing sections, so
15231 that .previous works correctly. We could do something like check
15232 for an obj_section_change_hook macro, but that might be confusing
15233 as it would not be appropriate to use it in the section changing
15234 functions in read.c, since obj-elf.c intercepts those. FIXME:
15235 This should be cleaner, somehow. */
15236 obj_elf_section_change_hook ();
15238 mips_emit_delays ();
15249 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15250 demand_empty_rest_of_line ();
15254 seg = subseg_new (RDATA_SECTION_NAME,
15255 (subsegT) get_absolute_expression ());
15256 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15257 | SEC_READONLY | SEC_RELOC
15259 if (strncmp (TARGET_OS, "elf", 3) != 0)
15260 record_alignment (seg, 4);
15261 demand_empty_rest_of_line ();
15265 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15266 bfd_set_section_flags (stdoutput, seg,
15267 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15268 if (strncmp (TARGET_OS, "elf", 3) != 0)
15269 record_alignment (seg, 4);
15270 demand_empty_rest_of_line ();
15274 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15275 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15276 if (strncmp (TARGET_OS, "elf", 3) != 0)
15277 record_alignment (seg, 4);
15278 demand_empty_rest_of_line ();
15286 s_change_section (int ignore ATTRIBUTE_UNUSED)
15289 char *section_name;
15294 int section_entry_size;
15295 int section_alignment;
15297 saved_ilp = input_line_pointer;
15298 endc = get_symbol_name (§ion_name);
15299 c = (endc == '"' ? input_line_pointer[1] : endc);
15301 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
15303 /* Do we have .section Name<,"flags">? */
15304 if (c != ',' || (c == ',' && next_c == '"'))
15306 /* Just after name is now '\0'. */
15307 (void) restore_line_pointer (endc);
15308 input_line_pointer = saved_ilp;
15309 obj_elf_section (ignore);
15313 section_name = xstrdup (section_name);
15314 c = restore_line_pointer (endc);
15316 input_line_pointer++;
15318 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15320 section_type = get_absolute_expression ();
15324 if (*input_line_pointer++ == ',')
15325 section_flag = get_absolute_expression ();
15329 if (*input_line_pointer++ == ',')
15330 section_entry_size = get_absolute_expression ();
15332 section_entry_size = 0;
15334 if (*input_line_pointer++ == ',')
15335 section_alignment = get_absolute_expression ();
15337 section_alignment = 0;
15339 /* FIXME: really ignore? */
15340 (void) section_alignment;
15342 /* When using the generic form of .section (as implemented by obj-elf.c),
15343 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15344 traditionally had to fall back on the more common @progbits instead.
15346 There's nothing really harmful in this, since bfd will correct
15347 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15348 means that, for backwards compatibility, the special_section entries
15349 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15351 Even so, we shouldn't force users of the MIPS .section syntax to
15352 incorrectly label the sections as SHT_PROGBITS. The best compromise
15353 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15354 generic type-checking code. */
15355 if (section_type == SHT_MIPS_DWARF)
15356 section_type = SHT_PROGBITS;
15358 obj_elf_change_section (section_name, section_type, section_flag,
15359 section_entry_size, 0, 0, 0);
15361 if (now_seg->name != section_name)
15362 free (section_name);
15366 mips_enable_auto_align (void)
15372 s_cons (int log_size)
15374 segment_info_type *si = seg_info (now_seg);
15375 struct insn_label_list *l = si->label_list;
15377 mips_emit_delays ();
15378 if (log_size > 0 && auto_align)
15379 mips_align (log_size, 0, l);
15380 cons (1 << log_size);
15381 mips_clear_insn_labels ();
15385 s_float_cons (int type)
15387 segment_info_type *si = seg_info (now_seg);
15388 struct insn_label_list *l = si->label_list;
15390 mips_emit_delays ();
15395 mips_align (3, 0, l);
15397 mips_align (2, 0, l);
15401 mips_clear_insn_labels ();
15404 /* Handle .globl. We need to override it because on Irix 5 you are
15407 where foo is an undefined symbol, to mean that foo should be
15408 considered to be the address of a function. */
15411 s_mips_globl (int x ATTRIBUTE_UNUSED)
15420 c = get_symbol_name (&name);
15421 symbolP = symbol_find_or_make (name);
15422 S_SET_EXTERNAL (symbolP);
15424 *input_line_pointer = c;
15425 SKIP_WHITESPACE_AFTER_NAME ();
15427 /* On Irix 5, every global symbol that is not explicitly labelled as
15428 being a function is apparently labelled as being an object. */
15431 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15432 && (*input_line_pointer != ','))
15437 c = get_symbol_name (&secname);
15438 sec = bfd_get_section_by_name (stdoutput, secname);
15440 as_bad (_("%s: no such section"), secname);
15441 (void) restore_line_pointer (c);
15443 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15444 flag = BSF_FUNCTION;
15447 symbol_get_bfdsym (symbolP)->flags |= flag;
15449 c = *input_line_pointer;
15452 input_line_pointer++;
15453 SKIP_WHITESPACE ();
15454 if (is_end_of_line[(unsigned char) *input_line_pointer])
15460 demand_empty_rest_of_line ();
15464 s_option (int x ATTRIBUTE_UNUSED)
15469 c = get_symbol_name (&opt);
15473 /* FIXME: What does this mean? */
15475 else if (strncmp (opt, "pic", 3) == 0)
15479 i = atoi (opt + 3);
15484 mips_pic = SVR4_PIC;
15485 mips_abicalls = TRUE;
15488 as_bad (_(".option pic%d not supported"), i);
15490 if (mips_pic == SVR4_PIC)
15492 if (g_switch_seen && g_switch_value != 0)
15493 as_warn (_("-G may not be used with SVR4 PIC code"));
15494 g_switch_value = 0;
15495 bfd_set_gp_size (stdoutput, 0);
15499 as_warn (_("unrecognized option \"%s\""), opt);
15501 (void) restore_line_pointer (c);
15502 demand_empty_rest_of_line ();
15505 /* This structure is used to hold a stack of .set values. */
15507 struct mips_option_stack
15509 struct mips_option_stack *next;
15510 struct mips_set_options options;
15513 static struct mips_option_stack *mips_opts_stack;
15516 parse_code_option (char * name)
15518 const struct mips_ase *ase;
15519 if (strncmp (name, "at=", 3) == 0)
15521 char *s = name + 3;
15523 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15524 as_bad (_("unrecognized register name `%s'"), s);
15526 else if (strcmp (name, "at") == 0)
15527 mips_opts.at = ATREG;
15528 else if (strcmp (name, "noat") == 0)
15529 mips_opts.at = ZERO;
15530 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15531 mips_opts.nomove = 0;
15532 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15533 mips_opts.nomove = 1;
15534 else if (strcmp (name, "bopt") == 0)
15535 mips_opts.nobopt = 0;
15536 else if (strcmp (name, "nobopt") == 0)
15537 mips_opts.nobopt = 1;
15538 else if (strcmp (name, "gp=32") == 0)
15540 else if (strcmp (name, "gp=64") == 0)
15542 else if (strcmp (name, "fp=32") == 0)
15544 else if (strcmp (name, "fp=xx") == 0)
15546 else if (strcmp (name, "fp=64") == 0)
15548 else if (strcmp (name, "softfloat") == 0)
15549 mips_opts.soft_float = 1;
15550 else if (strcmp (name, "hardfloat") == 0)
15551 mips_opts.soft_float = 0;
15552 else if (strcmp (name, "singlefloat") == 0)
15553 mips_opts.single_float = 1;
15554 else if (strcmp (name, "doublefloat") == 0)
15555 mips_opts.single_float = 0;
15556 else if (strcmp (name, "nooddspreg") == 0)
15557 mips_opts.oddspreg = 0;
15558 else if (strcmp (name, "oddspreg") == 0)
15559 mips_opts.oddspreg = 1;
15560 else if (strcmp (name, "mips16") == 0
15561 || strcmp (name, "MIPS-16") == 0)
15562 mips_opts.mips16 = 1;
15563 else if (strcmp (name, "nomips16") == 0
15564 || strcmp (name, "noMIPS-16") == 0)
15565 mips_opts.mips16 = 0;
15566 else if (strcmp (name, "micromips") == 0)
15567 mips_opts.micromips = 1;
15568 else if (strcmp (name, "nomicromips") == 0)
15569 mips_opts.micromips = 0;
15570 else if (name[0] == 'n'
15572 && (ase = mips_lookup_ase (name + 2)))
15573 mips_set_ase (ase, &mips_opts, FALSE);
15574 else if ((ase = mips_lookup_ase (name)))
15575 mips_set_ase (ase, &mips_opts, TRUE);
15576 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
15578 /* Permit the user to change the ISA and architecture on the fly.
15579 Needless to say, misuse can cause serious problems. */
15580 if (strncmp (name, "arch=", 5) == 0)
15582 const struct mips_cpu_info *p;
15584 p = mips_parse_cpu ("internal use", name + 5);
15586 as_bad (_("unknown architecture %s"), name + 5);
15589 mips_opts.arch = p->cpu;
15590 mips_opts.isa = p->isa;
15593 else if (strncmp (name, "mips", 4) == 0)
15595 const struct mips_cpu_info *p;
15597 p = mips_parse_cpu ("internal use", name);
15599 as_bad (_("unknown ISA level %s"), name + 4);
15602 mips_opts.arch = p->cpu;
15603 mips_opts.isa = p->isa;
15607 as_bad (_("unknown ISA or architecture %s"), name);
15609 else if (strcmp (name, "autoextend") == 0)
15610 mips_opts.noautoextend = 0;
15611 else if (strcmp (name, "noautoextend") == 0)
15612 mips_opts.noautoextend = 1;
15613 else if (strcmp (name, "insn32") == 0)
15614 mips_opts.insn32 = TRUE;
15615 else if (strcmp (name, "noinsn32") == 0)
15616 mips_opts.insn32 = FALSE;
15617 else if (strcmp (name, "sym32") == 0)
15618 mips_opts.sym32 = TRUE;
15619 else if (strcmp (name, "nosym32") == 0)
15620 mips_opts.sym32 = FALSE;
15626 /* Handle the .set pseudo-op. */
15629 s_mipsset (int x ATTRIBUTE_UNUSED)
15631 char *name = input_line_pointer, ch;
15632 int prev_isa = mips_opts.isa;
15634 file_mips_check_options ();
15636 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15637 ++input_line_pointer;
15638 ch = *input_line_pointer;
15639 *input_line_pointer = '\0';
15641 if (strchr (name, ','))
15643 /* Generic ".set" directive; use the generic handler. */
15644 *input_line_pointer = ch;
15645 input_line_pointer = name;
15650 if (strcmp (name, "reorder") == 0)
15652 if (mips_opts.noreorder)
15655 else if (strcmp (name, "noreorder") == 0)
15657 if (!mips_opts.noreorder)
15658 start_noreorder ();
15660 else if (strcmp (name, "macro") == 0)
15661 mips_opts.warn_about_macros = 0;
15662 else if (strcmp (name, "nomacro") == 0)
15664 if (mips_opts.noreorder == 0)
15665 as_bad (_("`noreorder' must be set before `nomacro'"));
15666 mips_opts.warn_about_macros = 1;
15668 else if (strcmp (name, "gp=default") == 0)
15669 mips_opts.gp = file_mips_opts.gp;
15670 else if (strcmp (name, "fp=default") == 0)
15671 mips_opts.fp = file_mips_opts.fp;
15672 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15674 mips_opts.isa = file_mips_opts.isa;
15675 mips_opts.arch = file_mips_opts.arch;
15676 mips_opts.gp = file_mips_opts.gp;
15677 mips_opts.fp = file_mips_opts.fp;
15679 else if (strcmp (name, "push") == 0)
15681 struct mips_option_stack *s;
15683 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15684 s->next = mips_opts_stack;
15685 s->options = mips_opts;
15686 mips_opts_stack = s;
15688 else if (strcmp (name, "pop") == 0)
15690 struct mips_option_stack *s;
15692 s = mips_opts_stack;
15694 as_bad (_(".set pop with no .set push"));
15697 /* If we're changing the reorder mode we need to handle
15698 delay slots correctly. */
15699 if (s->options.noreorder && ! mips_opts.noreorder)
15700 start_noreorder ();
15701 else if (! s->options.noreorder && mips_opts.noreorder)
15704 mips_opts = s->options;
15705 mips_opts_stack = s->next;
15709 else if (!parse_code_option (name))
15710 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
15712 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15713 registers based on what is supported by the arch/cpu. */
15714 if (mips_opts.isa != prev_isa)
15716 switch (mips_opts.isa)
15721 /* MIPS I cannot support FPXX. */
15723 /* fall-through. */
15730 if (mips_opts.fp != 0)
15746 if (mips_opts.fp != 0)
15748 if (mips_opts.arch == CPU_R5900)
15755 as_bad (_("unknown ISA level %s"), name + 4);
15760 mips_check_options (&mips_opts, FALSE);
15762 mips_check_isa_supports_ases ();
15763 *input_line_pointer = ch;
15764 demand_empty_rest_of_line ();
15767 /* Handle the .module pseudo-op. */
15770 s_module (int ignore ATTRIBUTE_UNUSED)
15772 char *name = input_line_pointer, ch;
15774 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15775 ++input_line_pointer;
15776 ch = *input_line_pointer;
15777 *input_line_pointer = '\0';
15779 if (!file_mips_opts_checked)
15781 if (!parse_code_option (name))
15782 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
15784 /* Update module level settings from mips_opts. */
15785 file_mips_opts = mips_opts;
15788 as_bad (_(".module is not permitted after generating code"));
15790 *input_line_pointer = ch;
15791 demand_empty_rest_of_line ();
15794 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15795 .option pic2. It means to generate SVR4 PIC calls. */
15798 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15800 mips_pic = SVR4_PIC;
15801 mips_abicalls = TRUE;
15803 if (g_switch_seen && g_switch_value != 0)
15804 as_warn (_("-G may not be used with SVR4 PIC code"));
15805 g_switch_value = 0;
15807 bfd_set_gp_size (stdoutput, 0);
15808 demand_empty_rest_of_line ();
15811 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15812 PIC code. It sets the $gp register for the function based on the
15813 function address, which is in the register named in the argument.
15814 This uses a relocation against _gp_disp, which is handled specially
15815 by the linker. The result is:
15816 lui $gp,%hi(_gp_disp)
15817 addiu $gp,$gp,%lo(_gp_disp)
15818 addu $gp,$gp,.cpload argument
15819 The .cpload argument is normally $25 == $t9.
15821 The -mno-shared option changes this to:
15822 lui $gp,%hi(__gnu_local_gp)
15823 addiu $gp,$gp,%lo(__gnu_local_gp)
15824 and the argument is ignored. This saves an instruction, but the
15825 resulting code is not position independent; it uses an absolute
15826 address for __gnu_local_gp. Thus code assembled with -mno-shared
15827 can go into an ordinary executable, but not into a shared library. */
15830 s_cpload (int ignore ATTRIBUTE_UNUSED)
15836 file_mips_check_options ();
15838 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15839 .cpload is ignored. */
15840 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15846 if (mips_opts.mips16)
15848 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15849 ignore_rest_of_line ();
15853 /* .cpload should be in a .set noreorder section. */
15854 if (mips_opts.noreorder == 0)
15855 as_warn (_(".cpload not in noreorder section"));
15857 reg = tc_get_register (0);
15859 /* If we need to produce a 64-bit address, we are better off using
15860 the default instruction sequence. */
15861 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15863 ex.X_op = O_symbol;
15864 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15866 ex.X_op_symbol = NULL;
15867 ex.X_add_number = 0;
15869 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15870 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15872 mips_mark_labels ();
15873 mips_assembling_insn = TRUE;
15876 macro_build_lui (&ex, mips_gp_register);
15877 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15878 mips_gp_register, BFD_RELOC_LO16);
15880 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15881 mips_gp_register, reg);
15884 mips_assembling_insn = FALSE;
15885 demand_empty_rest_of_line ();
15888 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15889 .cpsetup $reg1, offset|$reg2, label
15891 If offset is given, this results in:
15892 sd $gp, offset($sp)
15893 lui $gp, %hi(%neg(%gp_rel(label)))
15894 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15895 daddu $gp, $gp, $reg1
15897 If $reg2 is given, this results in:
15899 lui $gp, %hi(%neg(%gp_rel(label)))
15900 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15901 daddu $gp, $gp, $reg1
15902 $reg1 is normally $25 == $t9.
15904 The -mno-shared option replaces the last three instructions with
15906 addiu $gp,$gp,%lo(_gp) */
15909 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
15911 expressionS ex_off;
15912 expressionS ex_sym;
15915 file_mips_check_options ();
15917 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15918 We also need NewABI support. */
15919 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15925 if (mips_opts.mips16)
15927 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15928 ignore_rest_of_line ();
15932 reg1 = tc_get_register (0);
15933 SKIP_WHITESPACE ();
15934 if (*input_line_pointer != ',')
15936 as_bad (_("missing argument separator ',' for .cpsetup"));
15940 ++input_line_pointer;
15941 SKIP_WHITESPACE ();
15942 if (*input_line_pointer == '$')
15944 mips_cpreturn_register = tc_get_register (0);
15945 mips_cpreturn_offset = -1;
15949 mips_cpreturn_offset = get_absolute_expression ();
15950 mips_cpreturn_register = -1;
15952 SKIP_WHITESPACE ();
15953 if (*input_line_pointer != ',')
15955 as_bad (_("missing argument separator ',' for .cpsetup"));
15959 ++input_line_pointer;
15960 SKIP_WHITESPACE ();
15961 expression (&ex_sym);
15963 mips_mark_labels ();
15964 mips_assembling_insn = TRUE;
15967 if (mips_cpreturn_register == -1)
15969 ex_off.X_op = O_constant;
15970 ex_off.X_add_symbol = NULL;
15971 ex_off.X_op_symbol = NULL;
15972 ex_off.X_add_number = mips_cpreturn_offset;
15974 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15975 BFD_RELOC_LO16, SP);
15978 move_register (mips_cpreturn_register, mips_gp_register);
15980 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15982 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15983 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15986 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15987 mips_gp_register, -1, BFD_RELOC_GPREL16,
15988 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15990 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15991 mips_gp_register, reg1);
15997 ex.X_op = O_symbol;
15998 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15999 ex.X_op_symbol = NULL;
16000 ex.X_add_number = 0;
16002 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16003 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16005 macro_build_lui (&ex, mips_gp_register);
16006 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16007 mips_gp_register, BFD_RELOC_LO16);
16012 mips_assembling_insn = FALSE;
16013 demand_empty_rest_of_line ();
16017 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16019 file_mips_check_options ();
16021 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16022 .cplocal is ignored. */
16023 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16029 if (mips_opts.mips16)
16031 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16032 ignore_rest_of_line ();
16036 mips_gp_register = tc_get_register (0);
16037 demand_empty_rest_of_line ();
16040 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16041 offset from $sp. The offset is remembered, and after making a PIC
16042 call $gp is restored from that location. */
16045 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16049 file_mips_check_options ();
16051 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16052 .cprestore is ignored. */
16053 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16059 if (mips_opts.mips16)
16061 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16062 ignore_rest_of_line ();
16066 mips_cprestore_offset = get_absolute_expression ();
16067 mips_cprestore_valid = 1;
16069 ex.X_op = O_constant;
16070 ex.X_add_symbol = NULL;
16071 ex.X_op_symbol = NULL;
16072 ex.X_add_number = mips_cprestore_offset;
16074 mips_mark_labels ();
16075 mips_assembling_insn = TRUE;
16078 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16079 SP, HAVE_64BIT_ADDRESSES);
16082 mips_assembling_insn = FALSE;
16083 demand_empty_rest_of_line ();
16086 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16087 was given in the preceding .cpsetup, it results in:
16088 ld $gp, offset($sp)
16090 If a register $reg2 was given there, it results in:
16091 or $gp, $reg2, $0 */
16094 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16098 file_mips_check_options ();
16100 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16101 We also need NewABI support. */
16102 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16108 if (mips_opts.mips16)
16110 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16111 ignore_rest_of_line ();
16115 mips_mark_labels ();
16116 mips_assembling_insn = TRUE;
16119 if (mips_cpreturn_register == -1)
16121 ex.X_op = O_constant;
16122 ex.X_add_symbol = NULL;
16123 ex.X_op_symbol = NULL;
16124 ex.X_add_number = mips_cpreturn_offset;
16126 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16129 move_register (mips_gp_register, mips_cpreturn_register);
16133 mips_assembling_insn = FALSE;
16134 demand_empty_rest_of_line ();
16137 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16138 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16139 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16140 debug information or MIPS16 TLS. */
16143 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16144 bfd_reloc_code_real_type rtype)
16151 if (ex.X_op != O_symbol)
16153 as_bad (_("unsupported use of %s"), dirstr);
16154 ignore_rest_of_line ();
16157 p = frag_more (bytes);
16158 md_number_to_chars (p, 0, bytes);
16159 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16160 demand_empty_rest_of_line ();
16161 mips_clear_insn_labels ();
16164 /* Handle .dtprelword. */
16167 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16169 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16172 /* Handle .dtpreldword. */
16175 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16177 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16180 /* Handle .tprelword. */
16183 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16185 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16188 /* Handle .tpreldword. */
16191 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16193 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16196 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16197 code. It sets the offset to use in gp_rel relocations. */
16200 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16202 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16203 We also need NewABI support. */
16204 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16210 mips_gprel_offset = get_absolute_expression ();
16212 demand_empty_rest_of_line ();
16215 /* Handle the .gpword pseudo-op. This is used when generating PIC
16216 code. It generates a 32 bit GP relative reloc. */
16219 s_gpword (int ignore ATTRIBUTE_UNUSED)
16221 segment_info_type *si;
16222 struct insn_label_list *l;
16226 /* When not generating PIC code, this is treated as .word. */
16227 if (mips_pic != SVR4_PIC)
16233 si = seg_info (now_seg);
16234 l = si->label_list;
16235 mips_emit_delays ();
16237 mips_align (2, 0, l);
16240 mips_clear_insn_labels ();
16242 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16244 as_bad (_("unsupported use of .gpword"));
16245 ignore_rest_of_line ();
16249 md_number_to_chars (p, 0, 4);
16250 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16251 BFD_RELOC_GPREL32);
16253 demand_empty_rest_of_line ();
16257 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16259 segment_info_type *si;
16260 struct insn_label_list *l;
16264 /* When not generating PIC code, this is treated as .dword. */
16265 if (mips_pic != SVR4_PIC)
16271 si = seg_info (now_seg);
16272 l = si->label_list;
16273 mips_emit_delays ();
16275 mips_align (3, 0, l);
16278 mips_clear_insn_labels ();
16280 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16282 as_bad (_("unsupported use of .gpdword"));
16283 ignore_rest_of_line ();
16287 md_number_to_chars (p, 0, 8);
16288 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16289 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16291 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16292 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16293 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16295 demand_empty_rest_of_line ();
16298 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16299 tables. It generates a R_MIPS_EH reloc. */
16302 s_ehword (int ignore ATTRIBUTE_UNUSED)
16307 mips_emit_delays ();
16310 mips_clear_insn_labels ();
16312 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16314 as_bad (_("unsupported use of .ehword"));
16315 ignore_rest_of_line ();
16319 md_number_to_chars (p, 0, 4);
16320 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16321 BFD_RELOC_32_PCREL);
16323 demand_empty_rest_of_line ();
16326 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16327 tables in SVR4 PIC code. */
16330 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16334 file_mips_check_options ();
16336 /* This is ignored when not generating SVR4 PIC code. */
16337 if (mips_pic != SVR4_PIC)
16343 mips_mark_labels ();
16344 mips_assembling_insn = TRUE;
16346 /* Add $gp to the register named as an argument. */
16348 reg = tc_get_register (0);
16349 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16352 mips_assembling_insn = FALSE;
16353 demand_empty_rest_of_line ();
16356 /* Handle the .insn pseudo-op. This marks instruction labels in
16357 mips16/micromips mode. This permits the linker to handle them specially,
16358 such as generating jalx instructions when needed. We also make
16359 them odd for the duration of the assembly, in order to generate the
16360 right sort of code. We will make them even in the adjust_symtab
16361 routine, while leaving them marked. This is convenient for the
16362 debugger and the disassembler. The linker knows to make them odd
16366 s_insn (int ignore ATTRIBUTE_UNUSED)
16368 file_mips_check_options ();
16369 file_ase_mips16 |= mips_opts.mips16;
16370 file_ase_micromips |= mips_opts.micromips;
16372 mips_mark_labels ();
16374 demand_empty_rest_of_line ();
16377 /* Handle the .nan pseudo-op. */
16380 s_nan (int ignore ATTRIBUTE_UNUSED)
16382 static const char str_legacy[] = "legacy";
16383 static const char str_2008[] = "2008";
16386 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16388 if (i == sizeof (str_2008) - 1
16389 && memcmp (input_line_pointer, str_2008, i) == 0)
16391 else if (i == sizeof (str_legacy) - 1
16392 && memcmp (input_line_pointer, str_legacy, i) == 0)
16394 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16397 as_bad (_("`%s' does not support legacy NaN"),
16398 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16401 as_bad (_("bad .nan directive"));
16403 input_line_pointer += i;
16404 demand_empty_rest_of_line ();
16407 /* Handle a .stab[snd] directive. Ideally these directives would be
16408 implemented in a transparent way, so that removing them would not
16409 have any effect on the generated instructions. However, s_stab
16410 internally changes the section, so in practice we need to decide
16411 now whether the preceding label marks compressed code. We do not
16412 support changing the compression mode of a label after a .stab*
16413 directive, such as in:
16419 so the current mode wins. */
16422 s_mips_stab (int type)
16424 mips_mark_labels ();
16428 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16431 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16438 c = get_symbol_name (&name);
16439 symbolP = symbol_find_or_make (name);
16440 S_SET_WEAK (symbolP);
16441 *input_line_pointer = c;
16443 SKIP_WHITESPACE_AFTER_NAME ();
16445 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16447 if (S_IS_DEFINED (symbolP))
16449 as_bad (_("ignoring attempt to redefine symbol %s"),
16450 S_GET_NAME (symbolP));
16451 ignore_rest_of_line ();
16455 if (*input_line_pointer == ',')
16457 ++input_line_pointer;
16458 SKIP_WHITESPACE ();
16462 if (exp.X_op != O_symbol)
16464 as_bad (_("bad .weakext directive"));
16465 ignore_rest_of_line ();
16468 symbol_set_value_expression (symbolP, &exp);
16471 demand_empty_rest_of_line ();
16474 /* Parse a register string into a number. Called from the ECOFF code
16475 to parse .frame. The argument is non-zero if this is the frame
16476 register, so that we can record it in mips_frame_reg. */
16479 tc_get_register (int frame)
16483 SKIP_WHITESPACE ();
16484 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16488 mips_frame_reg = reg != 0 ? reg : SP;
16489 mips_frame_reg_valid = 1;
16490 mips_cprestore_valid = 0;
16496 md_section_align (asection *seg, valueT addr)
16498 int align = bfd_get_section_alignment (stdoutput, seg);
16500 /* We don't need to align ELF sections to the full alignment.
16501 However, Irix 5 may prefer that we align them at least to a 16
16502 byte boundary. We don't bother to align the sections if we
16503 are targeted for an embedded system. */
16504 if (strncmp (TARGET_OS, "elf", 3) == 0)
16509 return ((addr + (1 << align) - 1) & -(1 << align));
16512 /* Utility routine, called from above as well. If called while the
16513 input file is still being read, it's only an approximation. (For
16514 example, a symbol may later become defined which appeared to be
16515 undefined earlier.) */
16518 nopic_need_relax (symbolS *sym, int before_relaxing)
16523 if (g_switch_value > 0)
16525 const char *symname;
16528 /* Find out whether this symbol can be referenced off the $gp
16529 register. It can be if it is smaller than the -G size or if
16530 it is in the .sdata or .sbss section. Certain symbols can
16531 not be referenced off the $gp, although it appears as though
16533 symname = S_GET_NAME (sym);
16534 if (symname != (const char *) NULL
16535 && (strcmp (symname, "eprol") == 0
16536 || strcmp (symname, "etext") == 0
16537 || strcmp (symname, "_gp") == 0
16538 || strcmp (symname, "edata") == 0
16539 || strcmp (symname, "_fbss") == 0
16540 || strcmp (symname, "_fdata") == 0
16541 || strcmp (symname, "_ftext") == 0
16542 || strcmp (symname, "end") == 0
16543 || strcmp (symname, "_gp_disp") == 0))
16545 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16547 #ifndef NO_ECOFF_DEBUGGING
16548 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16549 && (symbol_get_obj (sym)->ecoff_extern_size
16550 <= g_switch_value))
16552 /* We must defer this decision until after the whole
16553 file has been read, since there might be a .extern
16554 after the first use of this symbol. */
16555 || (before_relaxing
16556 #ifndef NO_ECOFF_DEBUGGING
16557 && symbol_get_obj (sym)->ecoff_extern_size == 0
16559 && S_GET_VALUE (sym) == 0)
16560 || (S_GET_VALUE (sym) != 0
16561 && S_GET_VALUE (sym) <= g_switch_value)))
16565 const char *segname;
16567 segname = segment_name (S_GET_SEGMENT (sym));
16568 gas_assert (strcmp (segname, ".lit8") != 0
16569 && strcmp (segname, ".lit4") != 0);
16570 change = (strcmp (segname, ".sdata") != 0
16571 && strcmp (segname, ".sbss") != 0
16572 && strncmp (segname, ".sdata.", 7) != 0
16573 && strncmp (segname, ".sbss.", 6) != 0
16574 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16575 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16580 /* We are not optimizing for the $gp register. */
16585 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16588 pic_need_relax (symbolS *sym, asection *segtype)
16592 /* Handle the case of a symbol equated to another symbol. */
16593 while (symbol_equated_reloc_p (sym))
16597 /* It's possible to get a loop here in a badly written program. */
16598 n = symbol_get_value_expression (sym)->X_add_symbol;
16604 if (symbol_section_p (sym))
16607 symsec = S_GET_SEGMENT (sym);
16609 /* This must duplicate the test in adjust_reloc_syms. */
16610 return (!bfd_is_und_section (symsec)
16611 && !bfd_is_abs_section (symsec)
16612 && !bfd_is_com_section (symsec)
16613 && !s_is_linkonce (sym, segtype)
16614 /* A global or weak symbol is treated as external. */
16615 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
16619 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16620 extended opcode. SEC is the section the frag is in. */
16623 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16626 const struct mips_int_operand *operand;
16631 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16633 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16636 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16637 operand = mips16_immed_operand (type, FALSE);
16639 sym_frag = symbol_get_frag (fragp->fr_symbol);
16640 val = S_GET_VALUE (fragp->fr_symbol);
16641 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16643 if (operand->root.type == OP_PCREL)
16645 const struct mips_pcrel_operand *pcrel_op;
16649 /* We won't have the section when we are called from
16650 mips_relax_frag. However, we will always have been called
16651 from md_estimate_size_before_relax first. If this is a
16652 branch to a different section, we mark it as such. If SEC is
16653 NULL, and the frag is not marked, then it must be a branch to
16654 the same section. */
16655 pcrel_op = (const struct mips_pcrel_operand *) operand;
16658 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16663 /* Must have been called from md_estimate_size_before_relax. */
16666 fragp->fr_subtype =
16667 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16669 /* FIXME: We should support this, and let the linker
16670 catch branches and loads that are out of range. */
16671 as_bad_where (fragp->fr_file, fragp->fr_line,
16672 _("unsupported PC relative reference to different section"));
16676 if (fragp != sym_frag && sym_frag->fr_address == 0)
16677 /* Assume non-extended on the first relaxation pass.
16678 The address we have calculated will be bogus if this is
16679 a forward branch to another frag, as the forward frag
16680 will have fr_address == 0. */
16684 /* In this case, we know for sure that the symbol fragment is in
16685 the same section. If the relax_marker of the symbol fragment
16686 differs from the relax_marker of this fragment, we have not
16687 yet adjusted the symbol fragment fr_address. We want to add
16688 in STRETCH in order to get a better estimate of the address.
16689 This particularly matters because of the shift bits. */
16691 && sym_frag->relax_marker != fragp->relax_marker)
16695 /* Adjust stretch for any alignment frag. Note that if have
16696 been expanding the earlier code, the symbol may be
16697 defined in what appears to be an earlier frag. FIXME:
16698 This doesn't handle the fr_subtype field, which specifies
16699 a maximum number of bytes to skip when doing an
16701 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16703 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16706 stretch = - ((- stretch)
16707 & ~ ((1 << (int) f->fr_offset) - 1));
16709 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16718 addr = fragp->fr_address + fragp->fr_fix;
16720 /* The base address rules are complicated. The base address of
16721 a branch is the following instruction. The base address of a
16722 PC relative load or add is the instruction itself, but if it
16723 is in a delay slot (in which case it can not be extended) use
16724 the address of the instruction whose delay slot it is in. */
16725 if (pcrel_op->include_isa_bit)
16729 /* If we are currently assuming that this frag should be
16730 extended, then, the current address is two bytes
16732 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16735 /* Ignore the low bit in the target, since it will be set
16736 for a text label. */
16739 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16741 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16744 val -= addr & -(1 << pcrel_op->align_log2);
16746 /* If any of the shifted bits are set, we must use an extended
16747 opcode. If the address depends on the size of this
16748 instruction, this can lead to a loop, so we arrange to always
16749 use an extended opcode. We only check this when we are in
16750 the main relaxation loop, when SEC is NULL. */
16751 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
16753 fragp->fr_subtype =
16754 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16758 /* If we are about to mark a frag as extended because the value
16759 is precisely the next value above maxtiny, then there is a
16760 chance of an infinite loop as in the following code:
16765 In this case when the la is extended, foo is 0x3fc bytes
16766 away, so the la can be shrunk, but then foo is 0x400 away, so
16767 the la must be extended. To avoid this loop, we mark the
16768 frag as extended if it was small, and is about to become
16769 extended with the next value above maxtiny. */
16770 maxtiny = mips_int_operand_max (operand);
16771 if (val == maxtiny + (1 << operand->shift)
16772 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16775 fragp->fr_subtype =
16776 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16780 else if (symsec != absolute_section && sec != NULL)
16781 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16783 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16786 /* Compute the length of a branch sequence, and adjust the
16787 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16788 worst-case length is computed, with UPDATE being used to indicate
16789 whether an unconditional (-1), branch-likely (+1) or regular (0)
16790 branch is to be computed. */
16792 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16794 bfd_boolean toofar;
16798 && S_IS_DEFINED (fragp->fr_symbol)
16799 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16804 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16806 addr = fragp->fr_address + fragp->fr_fix + 4;
16810 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16813 /* If the symbol is not defined or it's in a different segment,
16814 assume the user knows what's going on and emit a short
16820 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16822 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16823 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16824 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16825 RELAX_BRANCH_LINK (fragp->fr_subtype),
16831 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16834 if (mips_pic != NO_PIC)
16836 /* Additional space for PIC loading of target address. */
16838 if (mips_opts.isa == ISA_MIPS1)
16839 /* Additional space for $at-stabilizing nop. */
16843 /* If branch is conditional. */
16844 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16851 /* Compute the length of a branch sequence, and adjust the
16852 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16853 worst-case length is computed, with UPDATE being used to indicate
16854 whether an unconditional (-1), or regular (0) branch is to be
16858 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16860 bfd_boolean toofar;
16864 && S_IS_DEFINED (fragp->fr_symbol)
16865 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16870 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16871 /* Ignore the low bit in the target, since it will be set
16872 for a text label. */
16873 if ((val & 1) != 0)
16876 addr = fragp->fr_address + fragp->fr_fix + 4;
16880 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16883 /* If the symbol is not defined or it's in a different segment,
16884 assume the user knows what's going on and emit a short
16890 if (fragp && update
16891 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16892 fragp->fr_subtype = (toofar
16893 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16894 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16899 bfd_boolean compact_known = fragp != NULL;
16900 bfd_boolean compact = FALSE;
16901 bfd_boolean uncond;
16904 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16906 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16908 uncond = update < 0;
16910 /* If label is out of range, we turn branch <br>:
16912 <br> label # 4 bytes
16918 nop # 2 bytes if compact && !PIC
16921 if (mips_pic == NO_PIC && (!compact_known || compact))
16924 /* If assembling PIC code, we further turn:
16930 lw/ld at, %got(label)(gp) # 4 bytes
16931 d/addiu at, %lo(label) # 4 bytes
16934 if (mips_pic != NO_PIC)
16937 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16939 <brneg> 0f # 4 bytes
16940 nop # 2 bytes if !compact
16943 length += (compact_known && compact) ? 4 : 6;
16949 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16950 bit accordingly. */
16953 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16955 bfd_boolean toofar;
16958 && S_IS_DEFINED (fragp->fr_symbol)
16959 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16965 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16966 /* Ignore the low bit in the target, since it will be set
16967 for a text label. */
16968 if ((val & 1) != 0)
16971 /* Assume this is a 2-byte branch. */
16972 addr = fragp->fr_address + fragp->fr_fix + 2;
16974 /* We try to avoid the infinite loop by not adding 2 more bytes for
16979 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16981 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16982 else if (type == 'E')
16983 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16988 /* If the symbol is not defined or it's in a different segment,
16989 we emit a normal 32-bit branch. */
16992 if (fragp && update
16993 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16995 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16996 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17004 /* Estimate the size of a frag before relaxing. Unless this is the
17005 mips16, we are not really relaxing here, and the final size is
17006 encoded in the subtype information. For the mips16, we have to
17007 decide whether we are using an extended opcode or not. */
17010 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17014 if (RELAX_BRANCH_P (fragp->fr_subtype))
17017 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17019 return fragp->fr_var;
17022 if (RELAX_MIPS16_P (fragp->fr_subtype))
17023 /* We don't want to modify the EXTENDED bit here; it might get us
17024 into infinite loops. We change it only in mips_relax_frag(). */
17025 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17027 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17031 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17032 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17033 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17034 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17035 fragp->fr_var = length;
17040 if (mips_pic == NO_PIC)
17041 change = nopic_need_relax (fragp->fr_symbol, 0);
17042 else if (mips_pic == SVR4_PIC)
17043 change = pic_need_relax (fragp->fr_symbol, segtype);
17044 else if (mips_pic == VXWORKS_PIC)
17045 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17052 fragp->fr_subtype |= RELAX_USE_SECOND;
17053 return -RELAX_FIRST (fragp->fr_subtype);
17056 return -RELAX_SECOND (fragp->fr_subtype);
17059 /* This is called to see whether a reloc against a defined symbol
17060 should be converted into a reloc against a section. */
17063 mips_fix_adjustable (fixS *fixp)
17065 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17066 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17069 if (fixp->fx_addsy == NULL)
17072 /* Allow relocs used for EH tables. */
17073 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17076 /* If symbol SYM is in a mergeable section, relocations of the form
17077 SYM + 0 can usually be made section-relative. The mergeable data
17078 is then identified by the section offset rather than by the symbol.
17080 However, if we're generating REL LO16 relocations, the offset is split
17081 between the LO16 and parterning high part relocation. The linker will
17082 need to recalculate the complete offset in order to correctly identify
17085 The linker has traditionally not looked for the parterning high part
17086 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17087 placed anywhere. Rather than break backwards compatibility by changing
17088 this, it seems better not to force the issue, and instead keep the
17089 original symbol. This will work with either linker behavior. */
17090 if ((lo16_reloc_p (fixp->fx_r_type)
17091 || reloc_needs_lo_p (fixp->fx_r_type))
17092 && HAVE_IN_PLACE_ADDENDS
17093 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17096 /* There is no place to store an in-place offset for JALR relocations.
17097 Likewise an in-range offset of limited PC-relative relocations may
17098 overflow the in-place relocatable field if recalculated against the
17099 start address of the symbol's containing section.
17101 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17102 section relative to allow linker relaxations to be performed later on. */
17103 if ((HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (mips_opts.isa))
17104 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17105 || jalr_reloc_p (fixp->fx_r_type)))
17108 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17109 to a floating-point stub. The same is true for non-R_MIPS16_26
17110 relocations against MIPS16 functions; in this case, the stub becomes
17111 the function's canonical address.
17113 Floating-point stubs are stored in unique .mips16.call.* or
17114 .mips16.fn.* sections. If a stub T for function F is in section S,
17115 the first relocation in section S must be against F; this is how the
17116 linker determines the target function. All relocations that might
17117 resolve to T must also be against F. We therefore have the following
17118 restrictions, which are given in an intentionally-redundant way:
17120 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17123 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17124 if that stub might be used.
17126 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17129 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17130 that stub might be used.
17132 There is a further restriction:
17134 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17135 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17136 targets with in-place addends; the relocation field cannot
17137 encode the low bit.
17139 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17140 against a MIPS16 symbol. We deal with (5) by by not reducing any
17141 such relocations on REL targets.
17143 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17144 relocation against some symbol R, no relocation against R may be
17145 reduced. (Note that this deals with (2) as well as (1) because
17146 relocations against global symbols will never be reduced on ELF
17147 targets.) This approach is a little simpler than trying to detect
17148 stub sections, and gives the "all or nothing" per-symbol consistency
17149 that we have for MIPS16 symbols. */
17150 if (fixp->fx_subsy == NULL
17151 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17152 || *symbol_get_tc (fixp->fx_addsy)
17153 || (HAVE_IN_PLACE_ADDENDS
17154 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17155 && jmp_reloc_p (fixp->fx_r_type))))
17161 /* Translate internal representation of relocation info to BFD target
17165 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17167 static arelent *retval[4];
17169 bfd_reloc_code_real_type code;
17171 memset (retval, 0, sizeof(retval));
17172 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17173 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17174 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17175 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17177 if (fixp->fx_pcrel)
17179 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17180 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17181 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17182 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17183 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17184 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17185 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17186 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17187 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17188 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17189 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
17191 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17192 Relocations want only the symbol offset. */
17193 reloc->addend = fixp->fx_addnumber + reloc->address;
17196 reloc->addend = fixp->fx_addnumber;
17198 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17199 entry to be used in the relocation's section offset. */
17200 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17202 reloc->address = reloc->addend;
17206 code = fixp->fx_r_type;
17208 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17209 if (reloc->howto == NULL)
17211 as_bad_where (fixp->fx_file, fixp->fx_line,
17212 _("cannot represent %s relocation in this object file"
17214 bfd_get_reloc_code_name (code));
17221 /* Relax a machine dependent frag. This returns the amount by which
17222 the current size of the frag should change. */
17225 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17227 if (RELAX_BRANCH_P (fragp->fr_subtype))
17229 offsetT old_var = fragp->fr_var;
17231 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17233 return fragp->fr_var - old_var;
17236 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17238 offsetT old_var = fragp->fr_var;
17239 offsetT new_var = 4;
17241 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17242 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17243 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17244 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17245 fragp->fr_var = new_var;
17247 return new_var - old_var;
17250 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17253 if (mips16_extended_frag (fragp, NULL, stretch))
17255 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17257 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17262 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17264 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17271 /* Convert a machine dependent frag. */
17274 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17276 if (RELAX_BRANCH_P (fragp->fr_subtype))
17279 unsigned long insn;
17283 buf = fragp->fr_literal + fragp->fr_fix;
17284 insn = read_insn (buf);
17286 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17288 /* We generate a fixup instead of applying it right now
17289 because, if there are linker relaxations, we're going to
17290 need the relocations. */
17291 exp.X_op = O_symbol;
17292 exp.X_add_symbol = fragp->fr_symbol;
17293 exp.X_add_number = fragp->fr_offset;
17295 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17296 BFD_RELOC_16_PCREL_S2);
17297 fixp->fx_file = fragp->fr_file;
17298 fixp->fx_line = fragp->fr_line;
17300 buf = write_insn (buf, insn);
17306 as_warn_where (fragp->fr_file, fragp->fr_line,
17307 _("relaxed out-of-range branch into a jump"));
17309 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17312 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17314 /* Reverse the branch. */
17315 switch ((insn >> 28) & 0xf)
17318 if ((insn & 0xff000000) == 0x47000000
17319 || (insn & 0xff600000) == 0x45600000)
17321 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17322 reversed by tweaking bit 23. */
17323 insn ^= 0x00800000;
17327 /* bc[0-3][tf]l? instructions can have the condition
17328 reversed by tweaking a single TF bit, and their
17329 opcodes all have 0x4???????. */
17330 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17331 insn ^= 0x00010000;
17336 /* bltz 0x04000000 bgez 0x04010000
17337 bltzal 0x04100000 bgezal 0x04110000 */
17338 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17339 insn ^= 0x00010000;
17343 /* beq 0x10000000 bne 0x14000000
17344 blez 0x18000000 bgtz 0x1c000000 */
17345 insn ^= 0x04000000;
17353 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17355 /* Clear the and-link bit. */
17356 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17358 /* bltzal 0x04100000 bgezal 0x04110000
17359 bltzall 0x04120000 bgezall 0x04130000 */
17360 insn &= ~0x00100000;
17363 /* Branch over the branch (if the branch was likely) or the
17364 full jump (not likely case). Compute the offset from the
17365 current instruction to branch to. */
17366 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17370 /* How many bytes in instructions we've already emitted? */
17371 i = buf - fragp->fr_literal - fragp->fr_fix;
17372 /* How many bytes in instructions from here to the end? */
17373 i = fragp->fr_var - i;
17375 /* Convert to instruction count. */
17377 /* Branch counts from the next instruction. */
17380 /* Branch over the jump. */
17381 buf = write_insn (buf, insn);
17384 buf = write_insn (buf, 0);
17386 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17388 /* beql $0, $0, 2f */
17390 /* Compute the PC offset from the current instruction to
17391 the end of the variable frag. */
17392 /* How many bytes in instructions we've already emitted? */
17393 i = buf - fragp->fr_literal - fragp->fr_fix;
17394 /* How many bytes in instructions from here to the end? */
17395 i = fragp->fr_var - i;
17396 /* Convert to instruction count. */
17398 /* Don't decrement i, because we want to branch over the
17402 buf = write_insn (buf, insn);
17403 buf = write_insn (buf, 0);
17407 if (mips_pic == NO_PIC)
17410 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17411 ? 0x0c000000 : 0x08000000);
17412 exp.X_op = O_symbol;
17413 exp.X_add_symbol = fragp->fr_symbol;
17414 exp.X_add_number = fragp->fr_offset;
17416 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17417 FALSE, BFD_RELOC_MIPS_JMP);
17418 fixp->fx_file = fragp->fr_file;
17419 fixp->fx_line = fragp->fr_line;
17421 buf = write_insn (buf, insn);
17425 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17427 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17428 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17429 insn |= at << OP_SH_RT;
17430 exp.X_op = O_symbol;
17431 exp.X_add_symbol = fragp->fr_symbol;
17432 exp.X_add_number = fragp->fr_offset;
17434 if (fragp->fr_offset)
17436 exp.X_add_symbol = make_expr_symbol (&exp);
17437 exp.X_add_number = 0;
17440 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17441 FALSE, BFD_RELOC_MIPS_GOT16);
17442 fixp->fx_file = fragp->fr_file;
17443 fixp->fx_line = fragp->fr_line;
17445 buf = write_insn (buf, insn);
17447 if (mips_opts.isa == ISA_MIPS1)
17449 buf = write_insn (buf, 0);
17451 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17452 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17453 insn |= at << OP_SH_RS | at << OP_SH_RT;
17455 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17456 FALSE, BFD_RELOC_LO16);
17457 fixp->fx_file = fragp->fr_file;
17458 fixp->fx_line = fragp->fr_line;
17460 buf = write_insn (buf, insn);
17463 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17467 insn |= at << OP_SH_RS;
17469 buf = write_insn (buf, insn);
17473 fragp->fr_fix += fragp->fr_var;
17474 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17478 /* Relax microMIPS branches. */
17479 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17481 char *buf = fragp->fr_literal + fragp->fr_fix;
17482 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17483 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17484 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17485 bfd_boolean short_ds;
17486 unsigned long insn;
17490 exp.X_op = O_symbol;
17491 exp.X_add_symbol = fragp->fr_symbol;
17492 exp.X_add_number = fragp->fr_offset;
17494 fragp->fr_fix += fragp->fr_var;
17496 /* Handle 16-bit branches that fit or are forced to fit. */
17497 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17499 /* We generate a fixup instead of applying it right now,
17500 because if there is linker relaxation, we're going to
17501 need the relocations. */
17503 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17504 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17505 else if (type == 'E')
17506 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17507 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17511 fixp->fx_file = fragp->fr_file;
17512 fixp->fx_line = fragp->fr_line;
17514 /* These relocations can have an addend that won't fit in
17516 fixp->fx_no_overflow = 1;
17521 /* Handle 32-bit branches that fit or are forced to fit. */
17522 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17523 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17525 /* We generate a fixup instead of applying it right now,
17526 because if there is linker relaxation, we're going to
17527 need the relocations. */
17528 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17529 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17530 fixp->fx_file = fragp->fr_file;
17531 fixp->fx_line = fragp->fr_line;
17537 /* Relax 16-bit branches to 32-bit branches. */
17540 insn = read_compressed_insn (buf, 2);
17542 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17543 insn = 0x94000000; /* beq */
17544 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17546 unsigned long regno;
17548 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17549 regno = micromips_to_32_reg_d_map [regno];
17550 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17551 insn |= regno << MICROMIPSOP_SH_RS;
17556 /* Nothing else to do, just write it out. */
17557 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17558 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17560 buf = write_compressed_insn (buf, insn, 4);
17561 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17566 insn = read_compressed_insn (buf, 4);
17568 /* Relax 32-bit branches to a sequence of instructions. */
17569 as_warn_where (fragp->fr_file, fragp->fr_line,
17570 _("relaxed out-of-range branch into a jump"));
17572 /* Set the short-delay-slot bit. */
17573 short_ds = al && (insn & 0x02000000) != 0;
17575 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17579 /* Reverse the branch. */
17580 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17581 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17582 insn ^= 0x20000000;
17583 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17584 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17585 || (insn & 0xffe00000) == 0x40800000 /* blez */
17586 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17587 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17588 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17589 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17590 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17591 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17592 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17593 insn ^= 0x00400000;
17594 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17595 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17596 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17597 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17598 insn ^= 0x00200000;
17599 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
17601 || (insn & 0xff600000) == 0x81600000) /* BZ.V
17603 insn ^= 0x00800000;
17609 /* Clear the and-link and short-delay-slot bits. */
17610 gas_assert ((insn & 0xfda00000) == 0x40200000);
17612 /* bltzal 0x40200000 bgezal 0x40600000 */
17613 /* bltzals 0x42200000 bgezals 0x42600000 */
17614 insn &= ~0x02200000;
17617 /* Make a label at the end for use with the branch. */
17618 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17619 micromips_label_inc ();
17620 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17623 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17624 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17625 fixp->fx_file = fragp->fr_file;
17626 fixp->fx_line = fragp->fr_line;
17628 /* Branch over the jump. */
17629 buf = write_compressed_insn (buf, insn, 4);
17632 buf = write_compressed_insn (buf, 0x0c00, 2);
17635 if (mips_pic == NO_PIC)
17637 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17639 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17640 insn = al ? jal : 0xd4000000;
17642 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17643 BFD_RELOC_MICROMIPS_JMP);
17644 fixp->fx_file = fragp->fr_file;
17645 fixp->fx_line = fragp->fr_line;
17647 buf = write_compressed_insn (buf, insn, 4);
17650 buf = write_compressed_insn (buf, 0x0c00, 2);
17654 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17655 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17656 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17658 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17659 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17660 insn |= at << MICROMIPSOP_SH_RT;
17662 if (exp.X_add_number)
17664 exp.X_add_symbol = make_expr_symbol (&exp);
17665 exp.X_add_number = 0;
17668 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17669 BFD_RELOC_MICROMIPS_GOT16);
17670 fixp->fx_file = fragp->fr_file;
17671 fixp->fx_line = fragp->fr_line;
17673 buf = write_compressed_insn (buf, insn, 4);
17675 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17676 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17677 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17679 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17680 BFD_RELOC_MICROMIPS_LO16);
17681 fixp->fx_file = fragp->fr_file;
17682 fixp->fx_line = fragp->fr_line;
17684 buf = write_compressed_insn (buf, insn, 4);
17686 /* jr/jrc/jalr/jalrs $at */
17687 insn = al ? jalr : jr;
17688 insn |= at << MICROMIPSOP_SH_MJ;
17690 buf = write_compressed_insn (buf, insn, 2);
17693 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17697 if (RELAX_MIPS16_P (fragp->fr_subtype))
17700 const struct mips_int_operand *operand;
17703 unsigned int user_length, length;
17704 unsigned long insn;
17707 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17708 operand = mips16_immed_operand (type, FALSE);
17710 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17711 val = resolve_symbol_value (fragp->fr_symbol);
17712 if (operand->root.type == OP_PCREL)
17714 const struct mips_pcrel_operand *pcrel_op;
17717 pcrel_op = (const struct mips_pcrel_operand *) operand;
17718 addr = fragp->fr_address + fragp->fr_fix;
17720 /* The rules for the base address of a PC relative reloc are
17721 complicated; see mips16_extended_frag. */
17722 if (pcrel_op->include_isa_bit)
17727 /* Ignore the low bit in the target, since it will be
17728 set for a text label. */
17731 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17733 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17736 addr &= -(1 << pcrel_op->align_log2);
17739 /* Make sure the section winds up with the alignment we have
17741 if (operand->shift > 0)
17742 record_alignment (asec, operand->shift);
17746 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17747 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17748 as_warn_where (fragp->fr_file, fragp->fr_line,
17749 _("extended instruction in delay slot"));
17751 buf = fragp->fr_literal + fragp->fr_fix;
17753 insn = read_compressed_insn (buf, 2);
17755 insn |= MIPS16_EXTEND;
17757 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17759 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17764 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17765 BFD_RELOC_UNUSED, val, user_length, &insn);
17767 length = (ext ? 4 : 2);
17768 gas_assert (mips16_opcode_length (insn) == length);
17769 write_compressed_insn (buf, insn, length);
17770 fragp->fr_fix += length;
17774 relax_substateT subtype = fragp->fr_subtype;
17775 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17776 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17780 first = RELAX_FIRST (subtype);
17781 second = RELAX_SECOND (subtype);
17782 fixp = (fixS *) fragp->fr_opcode;
17784 /* If the delay slot chosen does not match the size of the instruction,
17785 then emit a warning. */
17786 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17787 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17792 s = subtype & (RELAX_DELAY_SLOT_16BIT
17793 | RELAX_DELAY_SLOT_SIZE_FIRST
17794 | RELAX_DELAY_SLOT_SIZE_SECOND);
17795 msg = macro_warning (s);
17797 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17801 /* Possibly emit a warning if we've chosen the longer option. */
17802 if (use_second == second_longer)
17808 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17809 msg = macro_warning (s);
17811 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17815 /* Go through all the fixups for the first sequence. Disable them
17816 (by marking them as done) if we're going to use the second
17817 sequence instead. */
17819 && fixp->fx_frag == fragp
17820 && fixp->fx_where < fragp->fr_fix - second)
17822 if (subtype & RELAX_USE_SECOND)
17824 fixp = fixp->fx_next;
17827 /* Go through the fixups for the second sequence. Disable them if
17828 we're going to use the first sequence, otherwise adjust their
17829 addresses to account for the relaxation. */
17830 while (fixp && fixp->fx_frag == fragp)
17832 if (subtype & RELAX_USE_SECOND)
17833 fixp->fx_where -= first;
17836 fixp = fixp->fx_next;
17839 /* Now modify the frag contents. */
17840 if (subtype & RELAX_USE_SECOND)
17844 start = fragp->fr_literal + fragp->fr_fix - first - second;
17845 memmove (start, start + first, second);
17846 fragp->fr_fix -= first;
17849 fragp->fr_fix -= second;
17853 /* This function is called after the relocs have been generated.
17854 We've been storing mips16 text labels as odd. Here we convert them
17855 back to even for the convenience of the debugger. */
17858 mips_frob_file_after_relocs (void)
17861 unsigned int count, i;
17863 syms = bfd_get_outsymbols (stdoutput);
17864 count = bfd_get_symcount (stdoutput);
17865 for (i = 0; i < count; i++, syms++)
17866 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17867 && ((*syms)->value & 1) != 0)
17869 (*syms)->value &= ~1;
17870 /* If the symbol has an odd size, it was probably computed
17871 incorrectly, so adjust that as well. */
17872 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17873 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17877 /* This function is called whenever a label is defined, including fake
17878 labels instantiated off the dot special symbol. It is used when
17879 handling branch delays; if a branch has a label, we assume we cannot
17880 move it. This also bumps the value of the symbol by 1 in compressed
17884 mips_record_label (symbolS *sym)
17886 segment_info_type *si = seg_info (now_seg);
17887 struct insn_label_list *l;
17889 if (free_insn_labels == NULL)
17890 l = (struct insn_label_list *) xmalloc (sizeof *l);
17893 l = free_insn_labels;
17894 free_insn_labels = l->next;
17898 l->next = si->label_list;
17899 si->label_list = l;
17902 /* This function is called as tc_frob_label() whenever a label is defined
17903 and adds a DWARF-2 record we only want for true labels. */
17906 mips_define_label (symbolS *sym)
17908 mips_record_label (sym);
17909 dwarf2_emit_label (sym);
17912 /* This function is called by tc_new_dot_label whenever a new dot symbol
17916 mips_add_dot_label (symbolS *sym)
17918 mips_record_label (sym);
17919 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17920 mips_compressed_mark_label (sym);
17923 /* Converting ASE flags from internal to .MIPS.abiflags values. */
17924 static unsigned int
17925 mips_convert_ase_flags (int ase)
17927 unsigned int ext_ases = 0;
17930 ext_ases |= AFL_ASE_DSP;
17931 if (ase & ASE_DSPR2)
17932 ext_ases |= AFL_ASE_DSPR2;
17934 ext_ases |= AFL_ASE_EVA;
17936 ext_ases |= AFL_ASE_MCU;
17937 if (ase & ASE_MDMX)
17938 ext_ases |= AFL_ASE_MDMX;
17939 if (ase & ASE_MIPS3D)
17940 ext_ases |= AFL_ASE_MIPS3D;
17942 ext_ases |= AFL_ASE_MT;
17943 if (ase & ASE_SMARTMIPS)
17944 ext_ases |= AFL_ASE_SMARTMIPS;
17945 if (ase & ASE_VIRT)
17946 ext_ases |= AFL_ASE_VIRT;
17948 ext_ases |= AFL_ASE_MSA;
17950 ext_ases |= AFL_ASE_XPA;
17954 /* Some special processing for a MIPS ELF file. */
17957 mips_elf_final_processing (void)
17960 Elf_Internal_ABIFlags_v0 flags;
17964 switch (file_mips_opts.isa)
17967 flags.isa_level = 1;
17970 flags.isa_level = 2;
17973 flags.isa_level = 3;
17976 flags.isa_level = 4;
17979 flags.isa_level = 5;
17982 flags.isa_level = 32;
17986 flags.isa_level = 32;
17990 flags.isa_level = 32;
17994 flags.isa_level = 32;
17998 flags.isa_level = 32;
18002 flags.isa_level = 64;
18006 flags.isa_level = 64;
18010 flags.isa_level = 64;
18014 flags.isa_level = 64;
18018 flags.isa_level = 64;
18023 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18024 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18025 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18026 : (file_mips_opts.fp == 64) ? AFL_REG_64
18028 flags.cpr2_size = AFL_REG_NONE;
18029 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18030 Tag_GNU_MIPS_ABI_FP);
18031 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18032 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18033 if (file_ase_mips16)
18034 flags.ases |= AFL_ASE_MIPS16;
18035 if (file_ase_micromips)
18036 flags.ases |= AFL_ASE_MICROMIPS;
18038 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18039 || file_mips_opts.fp == 64)
18040 && file_mips_opts.oddspreg)
18041 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18044 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18045 ((Elf_External_ABIFlags_v0 *)
18048 /* Write out the register information. */
18049 if (mips_abi != N64_ABI)
18053 s.ri_gprmask = mips_gprmask;
18054 s.ri_cprmask[0] = mips_cprmask[0];
18055 s.ri_cprmask[1] = mips_cprmask[1];
18056 s.ri_cprmask[2] = mips_cprmask[2];
18057 s.ri_cprmask[3] = mips_cprmask[3];
18058 /* The gp_value field is set by the MIPS ELF backend. */
18060 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18061 ((Elf32_External_RegInfo *)
18062 mips_regmask_frag));
18066 Elf64_Internal_RegInfo s;
18068 s.ri_gprmask = mips_gprmask;
18070 s.ri_cprmask[0] = mips_cprmask[0];
18071 s.ri_cprmask[1] = mips_cprmask[1];
18072 s.ri_cprmask[2] = mips_cprmask[2];
18073 s.ri_cprmask[3] = mips_cprmask[3];
18074 /* The gp_value field is set by the MIPS ELF backend. */
18076 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18077 ((Elf64_External_RegInfo *)
18078 mips_regmask_frag));
18081 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18082 sort of BFD interface for this. */
18083 if (mips_any_noreorder)
18084 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18085 if (mips_pic != NO_PIC)
18087 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18088 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18091 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18093 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18094 defined at present; this might need to change in future. */
18095 if (file_ase_mips16)
18096 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18097 if (file_ase_micromips)
18098 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18099 if (file_mips_opts.ase & ASE_MDMX)
18100 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18102 /* Set the MIPS ELF ABI flags. */
18103 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18104 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18105 else if (mips_abi == O64_ABI)
18106 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18107 else if (mips_abi == EABI_ABI)
18109 if (file_mips_opts.gp == 64)
18110 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18112 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18114 else if (mips_abi == N32_ABI)
18115 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18117 /* Nothing to do for N64_ABI. */
18119 if (mips_32bitmode)
18120 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18122 if (mips_nan2008 == 1)
18123 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18125 /* 32 bit code with 64 bit FP registers. */
18126 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18127 Tag_GNU_MIPS_ABI_FP);
18128 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
18129 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
18132 typedef struct proc {
18134 symbolS *func_end_sym;
18135 unsigned long reg_mask;
18136 unsigned long reg_offset;
18137 unsigned long fpreg_mask;
18138 unsigned long fpreg_offset;
18139 unsigned long frame_offset;
18140 unsigned long frame_reg;
18141 unsigned long pc_reg;
18144 static procS cur_proc;
18145 static procS *cur_proc_ptr;
18146 static int numprocs;
18148 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18149 as "2", and a normal nop as "0". */
18151 #define NOP_OPCODE_MIPS 0
18152 #define NOP_OPCODE_MIPS16 1
18153 #define NOP_OPCODE_MICROMIPS 2
18156 mips_nop_opcode (void)
18158 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18159 return NOP_OPCODE_MICROMIPS;
18160 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18161 return NOP_OPCODE_MIPS16;
18163 return NOP_OPCODE_MIPS;
18166 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18167 32-bit microMIPS NOPs here (if applicable). */
18170 mips_handle_align (fragS *fragp)
18174 int bytes, size, excess;
18177 if (fragp->fr_type != rs_align_code)
18180 p = fragp->fr_literal + fragp->fr_fix;
18182 switch (nop_opcode)
18184 case NOP_OPCODE_MICROMIPS:
18185 opcode = micromips_nop32_insn.insn_opcode;
18188 case NOP_OPCODE_MIPS16:
18189 opcode = mips16_nop_insn.insn_opcode;
18192 case NOP_OPCODE_MIPS:
18194 opcode = nop_insn.insn_opcode;
18199 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18200 excess = bytes % size;
18202 /* Handle the leading part if we're not inserting a whole number of
18203 instructions, and make it the end of the fixed part of the frag.
18204 Try to fit in a short microMIPS NOP if applicable and possible,
18205 and use zeroes otherwise. */
18206 gas_assert (excess < 4);
18207 fragp->fr_fix += excess;
18212 /* Fall through. */
18214 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18216 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18220 /* Fall through. */
18223 /* Fall through. */
18228 md_number_to_chars (p, opcode, size);
18229 fragp->fr_var = size;
18238 if (*input_line_pointer == '-')
18240 ++input_line_pointer;
18243 if (!ISDIGIT (*input_line_pointer))
18244 as_bad (_("expected simple number"));
18245 if (input_line_pointer[0] == '0')
18247 if (input_line_pointer[1] == 'x')
18249 input_line_pointer += 2;
18250 while (ISXDIGIT (*input_line_pointer))
18253 val |= hex_value (*input_line_pointer++);
18255 return negative ? -val : val;
18259 ++input_line_pointer;
18260 while (ISDIGIT (*input_line_pointer))
18263 val |= *input_line_pointer++ - '0';
18265 return negative ? -val : val;
18268 if (!ISDIGIT (*input_line_pointer))
18270 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18271 *input_line_pointer, *input_line_pointer);
18272 as_warn (_("invalid number"));
18275 while (ISDIGIT (*input_line_pointer))
18278 val += *input_line_pointer++ - '0';
18280 return negative ? -val : val;
18283 /* The .file directive; just like the usual .file directive, but there
18284 is an initial number which is the ECOFF file index. In the non-ECOFF
18285 case .file implies DWARF-2. */
18288 s_mips_file (int x ATTRIBUTE_UNUSED)
18290 static int first_file_directive = 0;
18292 if (ECOFF_DEBUGGING)
18301 filename = dwarf2_directive_file (0);
18303 /* Versions of GCC up to 3.1 start files with a ".file"
18304 directive even for stabs output. Make sure that this
18305 ".file" is handled. Note that you need a version of GCC
18306 after 3.1 in order to support DWARF-2 on MIPS. */
18307 if (filename != NULL && ! first_file_directive)
18309 (void) new_logical_line (filename, -1);
18310 s_app_file_string (filename, 0);
18312 first_file_directive = 1;
18316 /* The .loc directive, implying DWARF-2. */
18319 s_mips_loc (int x ATTRIBUTE_UNUSED)
18321 if (!ECOFF_DEBUGGING)
18322 dwarf2_directive_loc (0);
18325 /* The .end directive. */
18328 s_mips_end (int x ATTRIBUTE_UNUSED)
18332 /* Following functions need their own .frame and .cprestore directives. */
18333 mips_frame_reg_valid = 0;
18334 mips_cprestore_valid = 0;
18336 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18339 demand_empty_rest_of_line ();
18344 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18345 as_warn (_(".end not in text section"));
18349 as_warn (_(".end directive without a preceding .ent directive"));
18350 demand_empty_rest_of_line ();
18356 gas_assert (S_GET_NAME (p));
18357 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18358 as_warn (_(".end symbol does not match .ent symbol"));
18360 if (debug_type == DEBUG_STABS)
18361 stabs_generate_asm_endfunc (S_GET_NAME (p),
18365 as_warn (_(".end directive missing or unknown symbol"));
18367 /* Create an expression to calculate the size of the function. */
18368 if (p && cur_proc_ptr)
18370 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18371 expressionS *exp = xmalloc (sizeof (expressionS));
18374 exp->X_op = O_subtract;
18375 exp->X_add_symbol = symbol_temp_new_now ();
18376 exp->X_op_symbol = p;
18377 exp->X_add_number = 0;
18379 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18382 /* Generate a .pdr section. */
18383 if (!ECOFF_DEBUGGING && mips_flag_pdr)
18385 segT saved_seg = now_seg;
18386 subsegT saved_subseg = now_subseg;
18390 #ifdef md_flush_pending_output
18391 md_flush_pending_output ();
18394 gas_assert (pdr_seg);
18395 subseg_set (pdr_seg, 0);
18397 /* Write the symbol. */
18398 exp.X_op = O_symbol;
18399 exp.X_add_symbol = p;
18400 exp.X_add_number = 0;
18401 emit_expr (&exp, 4);
18403 fragp = frag_more (7 * 4);
18405 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18406 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18407 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18408 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18409 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18410 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18411 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18413 subseg_set (saved_seg, saved_subseg);
18416 cur_proc_ptr = NULL;
18419 /* The .aent and .ent directives. */
18422 s_mips_ent (int aent)
18426 symbolP = get_symbol ();
18427 if (*input_line_pointer == ',')
18428 ++input_line_pointer;
18429 SKIP_WHITESPACE ();
18430 if (ISDIGIT (*input_line_pointer)
18431 || *input_line_pointer == '-')
18434 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18435 as_warn (_(".ent or .aent not in text section"));
18437 if (!aent && cur_proc_ptr)
18438 as_warn (_("missing .end"));
18442 /* This function needs its own .frame and .cprestore directives. */
18443 mips_frame_reg_valid = 0;
18444 mips_cprestore_valid = 0;
18446 cur_proc_ptr = &cur_proc;
18447 memset (cur_proc_ptr, '\0', sizeof (procS));
18449 cur_proc_ptr->func_sym = symbolP;
18453 if (debug_type == DEBUG_STABS)
18454 stabs_generate_asm_func (S_GET_NAME (symbolP),
18455 S_GET_NAME (symbolP));
18458 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18460 demand_empty_rest_of_line ();
18463 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18464 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18465 s_mips_frame is used so that we can set the PDR information correctly.
18466 We can't use the ecoff routines because they make reference to the ecoff
18467 symbol table (in the mdebug section). */
18470 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18472 if (ECOFF_DEBUGGING)
18478 if (cur_proc_ptr == (procS *) NULL)
18480 as_warn (_(".frame outside of .ent"));
18481 demand_empty_rest_of_line ();
18485 cur_proc_ptr->frame_reg = tc_get_register (1);
18487 SKIP_WHITESPACE ();
18488 if (*input_line_pointer++ != ','
18489 || get_absolute_expression_and_terminator (&val) != ',')
18491 as_warn (_("bad .frame directive"));
18492 --input_line_pointer;
18493 demand_empty_rest_of_line ();
18497 cur_proc_ptr->frame_offset = val;
18498 cur_proc_ptr->pc_reg = tc_get_register (0);
18500 demand_empty_rest_of_line ();
18504 /* The .fmask and .mask directives. If the mdebug section is present
18505 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18506 embedded targets, s_mips_mask is used so that we can set the PDR
18507 information correctly. We can't use the ecoff routines because they
18508 make reference to the ecoff symbol table (in the mdebug section). */
18511 s_mips_mask (int reg_type)
18513 if (ECOFF_DEBUGGING)
18514 s_ignore (reg_type);
18519 if (cur_proc_ptr == (procS *) NULL)
18521 as_warn (_(".mask/.fmask outside of .ent"));
18522 demand_empty_rest_of_line ();
18526 if (get_absolute_expression_and_terminator (&mask) != ',')
18528 as_warn (_("bad .mask/.fmask directive"));
18529 --input_line_pointer;
18530 demand_empty_rest_of_line ();
18534 off = get_absolute_expression ();
18536 if (reg_type == 'F')
18538 cur_proc_ptr->fpreg_mask = mask;
18539 cur_proc_ptr->fpreg_offset = off;
18543 cur_proc_ptr->reg_mask = mask;
18544 cur_proc_ptr->reg_offset = off;
18547 demand_empty_rest_of_line ();
18551 /* A table describing all the processors gas knows about. Names are
18552 matched in the order listed.
18554 To ease comparison, please keep this table in the same order as
18555 gcc's mips_cpu_info_table[]. */
18556 static const struct mips_cpu_info mips_cpu_info_table[] =
18558 /* Entries for generic ISAs */
18559 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
18560 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
18561 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
18562 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
18563 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
18564 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
18565 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18566 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
18567 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
18568 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
18569 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
18570 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
18571 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
18572 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
18573 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
18576 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
18577 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
18578 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
18581 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
18584 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
18585 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
18586 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
18587 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
18588 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
18589 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
18590 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
18591 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
18592 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
18593 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
18594 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
18595 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
18596 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
18597 /* ST Microelectronics Loongson 2E and 2F cores */
18598 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
18599 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
18602 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
18603 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
18604 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
18605 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
18606 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
18607 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
18608 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
18609 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
18610 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
18611 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
18612 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
18613 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
18614 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
18615 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
18616 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
18619 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18620 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18621 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18622 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18624 /* MIPS 32 Release 2 */
18625 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18626 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18627 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18628 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18629 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18630 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18631 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18632 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18633 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18634 ISA_MIPS32R2, CPU_MIPS32R2 },
18635 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18636 ISA_MIPS32R2, CPU_MIPS32R2 },
18637 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18638 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18639 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18640 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18641 /* Deprecated forms of the above. */
18642 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18643 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18644 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18645 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18646 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18647 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18648 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18649 /* Deprecated forms of the above. */
18650 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18651 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18652 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18653 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18654 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18655 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18656 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18657 /* Deprecated forms of the above. */
18658 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18659 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18660 /* 34Kn is a 34kc without DSP. */
18661 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18662 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18663 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18664 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18665 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18666 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18667 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18668 /* Deprecated forms of the above. */
18669 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18670 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18671 /* 1004K cores are multiprocessor versions of the 34K. */
18672 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18673 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18674 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18675 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18676 /* interaptiv is the new name for 1004kf */
18677 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18679 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18680 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18681 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18682 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
18685 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18686 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18687 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18688 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18690 /* Broadcom SB-1 CPU core */
18691 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18692 /* Broadcom SB-1A CPU core */
18693 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18695 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
18697 /* MIPS 64 Release 2 */
18699 /* Cavium Networks Octeon CPU core */
18700 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
18701 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
18702 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
18703 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
18706 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
18709 XLP is mostly like XLR, with the prominent exception that it is
18710 MIPS64R2 rather than MIPS64. */
18711 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
18714 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
18717 { NULL, 0, 0, 0, 0 }
18721 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18722 with a final "000" replaced by "k". Ignore case.
18724 Note: this function is shared between GCC and GAS. */
18727 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
18729 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18730 given++, canonical++;
18732 return ((*given == 0 && *canonical == 0)
18733 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18737 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18738 CPU name. We've traditionally allowed a lot of variation here.
18740 Note: this function is shared between GCC and GAS. */
18743 mips_matching_cpu_name_p (const char *canonical, const char *given)
18745 /* First see if the name matches exactly, or with a final "000"
18746 turned into "k". */
18747 if (mips_strict_matching_cpu_name_p (canonical, given))
18750 /* If not, try comparing based on numerical designation alone.
18751 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18752 if (TOLOWER (*given) == 'r')
18754 if (!ISDIGIT (*given))
18757 /* Skip over some well-known prefixes in the canonical name,
18758 hoping to find a number there too. */
18759 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18761 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18763 else if (TOLOWER (canonical[0]) == 'r')
18766 return mips_strict_matching_cpu_name_p (canonical, given);
18770 /* Parse an option that takes the name of a processor as its argument.
18771 OPTION is the name of the option and CPU_STRING is the argument.
18772 Return the corresponding processor enumeration if the CPU_STRING is
18773 recognized, otherwise report an error and return null.
18775 A similar function exists in GCC. */
18777 static const struct mips_cpu_info *
18778 mips_parse_cpu (const char *option, const char *cpu_string)
18780 const struct mips_cpu_info *p;
18782 /* 'from-abi' selects the most compatible architecture for the given
18783 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18784 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18785 version. Look first at the -mgp options, if given, otherwise base
18786 the choice on MIPS_DEFAULT_64BIT.
18788 Treat NO_ABI like the EABIs. One reason to do this is that the
18789 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18790 architecture. This code picks MIPS I for 'mips' and MIPS III for
18791 'mips64', just as we did in the days before 'from-abi'. */
18792 if (strcasecmp (cpu_string, "from-abi") == 0)
18794 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18795 return mips_cpu_info_from_isa (ISA_MIPS1);
18797 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18798 return mips_cpu_info_from_isa (ISA_MIPS3);
18800 if (file_mips_opts.gp >= 0)
18801 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
18802 ? ISA_MIPS1 : ISA_MIPS3);
18804 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18809 /* 'default' has traditionally been a no-op. Probably not very useful. */
18810 if (strcasecmp (cpu_string, "default") == 0)
18813 for (p = mips_cpu_info_table; p->name != 0; p++)
18814 if (mips_matching_cpu_name_p (p->name, cpu_string))
18817 as_bad (_("bad value (%s) for %s"), cpu_string, option);
18821 /* Return the canonical processor information for ISA (a member of the
18822 ISA_MIPS* enumeration). */
18824 static const struct mips_cpu_info *
18825 mips_cpu_info_from_isa (int isa)
18829 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18830 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18831 && isa == mips_cpu_info_table[i].isa)
18832 return (&mips_cpu_info_table[i]);
18837 static const struct mips_cpu_info *
18838 mips_cpu_info_from_arch (int arch)
18842 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18843 if (arch == mips_cpu_info_table[i].cpu)
18844 return (&mips_cpu_info_table[i]);
18850 show (FILE *stream, const char *string, int *col_p, int *first_p)
18854 fprintf (stream, "%24s", "");
18859 fprintf (stream, ", ");
18863 if (*col_p + strlen (string) > 72)
18865 fprintf (stream, "\n%24s", "");
18869 fprintf (stream, "%s", string);
18870 *col_p += strlen (string);
18876 md_show_usage (FILE *stream)
18881 fprintf (stream, _("\
18883 -EB generate big endian output\n\
18884 -EL generate little endian output\n\
18885 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18886 -G NUM allow referencing objects up to NUM bytes\n\
18887 implicitly with the gp register [default 8]\n"));
18888 fprintf (stream, _("\
18889 -mips1 generate MIPS ISA I instructions\n\
18890 -mips2 generate MIPS ISA II instructions\n\
18891 -mips3 generate MIPS ISA III instructions\n\
18892 -mips4 generate MIPS ISA IV instructions\n\
18893 -mips5 generate MIPS ISA V instructions\n\
18894 -mips32 generate MIPS32 ISA instructions\n\
18895 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18896 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18897 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18898 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
18899 -mips64 generate MIPS64 ISA instructions\n\
18900 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18901 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18902 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18903 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
18904 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18908 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18909 show (stream, mips_cpu_info_table[i].name, &column, &first);
18910 show (stream, "from-abi", &column, &first);
18911 fputc ('\n', stream);
18913 fprintf (stream, _("\
18914 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18915 -no-mCPU don't generate code specific to CPU.\n\
18916 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18920 show (stream, "3900", &column, &first);
18921 show (stream, "4010", &column, &first);
18922 show (stream, "4100", &column, &first);
18923 show (stream, "4650", &column, &first);
18924 fputc ('\n', stream);
18926 fprintf (stream, _("\
18927 -mips16 generate mips16 instructions\n\
18928 -no-mips16 do not generate mips16 instructions\n"));
18929 fprintf (stream, _("\
18930 -mmicromips generate microMIPS instructions\n\
18931 -mno-micromips do not generate microMIPS instructions\n"));
18932 fprintf (stream, _("\
18933 -msmartmips generate smartmips instructions\n\
18934 -mno-smartmips do not generate smartmips instructions\n"));
18935 fprintf (stream, _("\
18936 -mdsp generate DSP instructions\n\
18937 -mno-dsp do not generate DSP instructions\n"));
18938 fprintf (stream, _("\
18939 -mdspr2 generate DSP R2 instructions\n\
18940 -mno-dspr2 do not generate DSP R2 instructions\n"));
18941 fprintf (stream, _("\
18942 -mmt generate MT instructions\n\
18943 -mno-mt do not generate MT instructions\n"));
18944 fprintf (stream, _("\
18945 -mmcu generate MCU instructions\n\
18946 -mno-mcu do not generate MCU instructions\n"));
18947 fprintf (stream, _("\
18948 -mmsa generate MSA instructions\n\
18949 -mno-msa do not generate MSA instructions\n"));
18950 fprintf (stream, _("\
18951 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18952 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18953 fprintf (stream, _("\
18954 -mvirt generate Virtualization instructions\n\
18955 -mno-virt do not generate Virtualization instructions\n"));
18956 fprintf (stream, _("\
18957 -minsn32 only generate 32-bit microMIPS instructions\n\
18958 -mno-insn32 generate all microMIPS instructions\n"));
18959 fprintf (stream, _("\
18960 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18961 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18962 -mfix-vr4120 work around certain VR4120 errata\n\
18963 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18964 -mfix-24k insert a nop after ERET and DERET instructions\n\
18965 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18966 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18967 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18968 -msym32 assume all symbols have 32-bit values\n\
18969 -O0 remove unneeded NOPs, do not swap branches\n\
18970 -O remove unneeded NOPs and swap branches\n\
18971 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18972 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18973 fprintf (stream, _("\
18974 -mhard-float allow floating-point instructions\n\
18975 -msoft-float do not allow floating-point instructions\n\
18976 -msingle-float only allow 32-bit floating-point operations\n\
18977 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18978 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18979 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18980 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18984 show (stream, "legacy", &column, &first);
18985 show (stream, "2008", &column, &first);
18987 fputc ('\n', stream);
18989 fprintf (stream, _("\
18990 -KPIC, -call_shared generate SVR4 position independent code\n\
18991 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18992 -mvxworks-pic generate VxWorks position independent code\n\
18993 -non_shared do not generate code that can operate with DSOs\n\
18994 -xgot assume a 32 bit GOT\n\
18995 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18996 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18997 position dependent (non shared) code\n\
18998 -mabi=ABI create ABI conformant object file for:\n"));
19002 show (stream, "32", &column, &first);
19003 show (stream, "o64", &column, &first);
19004 show (stream, "n32", &column, &first);
19005 show (stream, "64", &column, &first);
19006 show (stream, "eabi", &column, &first);
19008 fputc ('\n', stream);
19010 fprintf (stream, _("\
19011 -32 create o32 ABI object file (default)\n\
19012 -n32 create n32 ABI object file\n\
19013 -64 create 64 ABI object file\n"));
19018 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19020 if (HAVE_64BIT_SYMBOLS)
19021 return dwarf2_format_64bit_irix;
19023 return dwarf2_format_32bit;
19028 mips_dwarf2_addr_size (void)
19030 if (HAVE_64BIT_OBJECTS)
19036 /* Standard calling conventions leave the CFA at SP on entry. */
19038 mips_cfi_frame_initial_instructions (void)
19040 cfi_add_CFA_def_cfa_register (SP);
19044 tc_mips_regname_to_dw2regnum (char *regname)
19046 unsigned int regnum = -1;
19049 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
19055 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19056 Given a symbolic attribute NAME, return the proper integer value.
19057 Returns -1 if the attribute is not known. */
19060 mips_convert_symbolic_attribute (const char *name)
19062 static const struct
19067 attribute_table[] =
19069 #define T(tag) {#tag, tag}
19070 T (Tag_GNU_MIPS_ABI_FP),
19071 T (Tag_GNU_MIPS_ABI_MSA),
19079 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19080 if (streq (name, attribute_table[i].name))
19081 return attribute_table[i].tag;
19089 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19091 mips_emit_delays ();
19093 as_warn (_("missing .end at end of assembly"));
19095 /* Just in case no code was emitted, do the consistency check. */
19096 file_mips_check_options ();
19098 /* Set a floating-point ABI if the user did not. */
19099 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19101 /* Perform consistency checks on the floating-point ABI. */
19102 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19103 Tag_GNU_MIPS_ABI_FP);
19104 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19105 check_fpabi (fpabi);
19109 /* Soft-float gets precedence over single-float, the two options should
19110 not be used together so this should not matter. */
19111 if (file_mips_opts.soft_float == 1)
19112 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19113 /* Single-float gets precedence over all double_float cases. */
19114 else if (file_mips_opts.single_float == 1)
19115 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19118 switch (file_mips_opts.fp)
19121 if (file_mips_opts.gp == 32)
19122 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19125 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19128 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19129 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19130 else if (file_mips_opts.gp == 32)
19131 fpabi = Val_GNU_MIPS_ABI_FP_64;
19133 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19138 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19139 Tag_GNU_MIPS_ABI_FP, fpabi);
19143 /* Returns the relocation type required for a particular CFI encoding. */
19145 bfd_reloc_code_real_type
19146 mips_cfi_reloc_for_encoding (int encoding)
19148 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
19149 return BFD_RELOC_32_PCREL;
19150 else return BFD_RELOC_NONE;