1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* True if the given ABI requires 32-bit registers. */
241 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
243 /* Likewise 64-bit registers. */
244 #define ABI_NEEDS_64BIT_REGS(ABI) \
246 || (ABI) == N64_ABI \
249 /* Return true if ISA supports 64 bit gp register instructions. */
250 #define ISA_HAS_64BIT_REGS(ISA) ( \
252 || (ISA) == ISA_MIPS4 \
253 || (ISA) == ISA_MIPS5 \
254 || (ISA) == ISA_MIPS64 \
255 || (ISA) == ISA_MIPS64R2 \
258 /* Return true if ISA supports 64-bit right rotate (dror et al.)
260 #define ISA_HAS_DROR(ISA) ( \
261 (ISA) == ISA_MIPS64R2 \
264 /* Return true if ISA supports 32-bit right rotate (ror et al.)
266 #define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
271 #define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
274 #define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
280 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
282 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
284 /* We can only have 64bit addresses if the object file format
286 #define HAVE_32BIT_ADDRESSES \
288 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS) \
290 && mips_pic != EMBEDDED_PIC))
292 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
294 /* Addresses are loaded in different ways, depending on the address size
295 in use. The n32 ABI Documentation also mandates the use of additions
296 with overflow checking, but existing implementations don't follow it. */
297 #define ADDRESS_ADD_INSN \
298 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
300 #define ADDRESS_ADDI_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
303 #define ADDRESS_LOAD_INSN \
304 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
306 #define ADDRESS_STORE_INSN \
307 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
309 /* Return true if the given CPU supports the MIPS16 ASE. */
310 #define CPU_HAS_MIPS16(cpu) \
311 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
312 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
314 /* Return true if the given CPU supports the MIPS3D ASE. */
315 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
318 /* Return true if the given CPU supports the MDMX ASE. */
319 #define CPU_HAS_MDMX(cpu) (FALSE \
322 /* True if CPU has a dror instruction. */
323 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
325 /* True if CPU has a ror instruction. */
326 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
328 /* Whether the processor uses hardware interlocks to protect
329 reads from the HI and LO registers, and thus does not
330 require nops to be inserted. */
332 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
333 || mips_opts.arch == CPU_VR5500 \
334 || mips_opts.arch == CPU_RM7000 \
335 || mips_opts.arch == CPU_SB1 \
338 /* Whether the processor uses hardware interlocks to protect reads
339 from the GPRs after they are loaded from memory, and thus does not
340 require nops to be inserted. This applies to instructions marked
341 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
343 #define gpr_interlocks \
344 (mips_opts.isa != ISA_MIPS1 \
345 || mips_opts.arch == CPU_VR5400 \
346 || mips_opts.arch == CPU_VR5500 \
347 || mips_opts.arch == CPU_R3900)
349 /* Whether the processor uses hardware interlocks to avoid delays
350 required by coprocessor instructions, and thus does not require
351 nops to be inserted. This applies to instructions marked
352 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
353 between instructions marked INSN_WRITE_COND_CODE and ones marked
354 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
355 levels I, II, and III. */
356 /* Itbl support may require additional care here. */
357 #define cop_interlocks \
358 ((mips_opts.isa != ISA_MIPS1 \
359 && mips_opts.isa != ISA_MIPS2 \
360 && mips_opts.isa != ISA_MIPS3) \
361 || mips_opts.arch == CPU_R4300 \
362 || mips_opts.arch == CPU_VR5400 \
363 || mips_opts.arch == CPU_VR5500 \
364 || mips_opts.arch == CPU_SB1 \
367 /* Whether the processor uses hardware interlocks to protect reads
368 from coprocessor registers after they are loaded from memory, and
369 thus does not require nops to be inserted. This applies to
370 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
371 requires at MIPS ISA level I. */
372 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
374 /* Is this a mfhi or mflo instruction? */
375 #define MF_HILO_INSN(PINFO) \
376 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
378 /* MIPS PIC level. */
380 enum mips_pic_level mips_pic;
382 /* 1 if we should generate 32 bit offsets from the $gp register in
383 SVR4_PIC mode. Currently has no meaning in other modes. */
384 static int mips_big_got = 0;
386 /* 1 if trap instructions should used for overflow rather than break
388 static int mips_trap = 0;
390 /* 1 if double width floating point constants should not be constructed
391 by assembling two single width halves into two single width floating
392 point registers which just happen to alias the double width destination
393 register. On some architectures this aliasing can be disabled by a bit
394 in the status register, and the setting of this bit cannot be determined
395 automatically at assemble time. */
396 static int mips_disable_float_construction;
398 /* Non-zero if any .set noreorder directives were used. */
400 static int mips_any_noreorder;
402 /* Non-zero if nops should be inserted when the register referenced in
403 an mfhi/mflo instruction is read in the next two instructions. */
404 static int mips_7000_hilo_fix;
406 /* The size of the small data section. */
407 static unsigned int g_switch_value = 8;
408 /* Whether the -G option was used. */
409 static int g_switch_seen = 0;
414 /* If we can determine in advance that GP optimization won't be
415 possible, we can skip the relaxation stuff that tries to produce
416 GP-relative references. This makes delay slot optimization work
419 This function can only provide a guess, but it seems to work for
420 gcc output. It needs to guess right for gcc, otherwise gcc
421 will put what it thinks is a GP-relative instruction in a branch
424 I don't know if a fix is needed for the SVR4_PIC mode. I've only
425 fixed it for the non-PIC mode. KR 95/04/07 */
426 static int nopic_need_relax (symbolS *, int);
428 /* handle of the OPCODE hash table */
429 static struct hash_control *op_hash = NULL;
431 /* The opcode hash table we use for the mips16. */
432 static struct hash_control *mips16_op_hash = NULL;
434 /* This array holds the chars that always start a comment. If the
435 pre-processor is disabled, these aren't very useful */
436 const char comment_chars[] = "#";
438 /* This array holds the chars that only start a comment at the beginning of
439 a line. If the line seems to have the form '# 123 filename'
440 .line and .file directives will appear in the pre-processed output */
441 /* Note that input_file.c hand checks for '#' at the beginning of the
442 first line of the input file. This is because the compiler outputs
443 #NO_APP at the beginning of its output. */
444 /* Also note that C style comments are always supported. */
445 const char line_comment_chars[] = "#";
447 /* This array holds machine specific line separator characters. */
448 const char line_separator_chars[] = ";";
450 /* Chars that can be used to separate mant from exp in floating point nums */
451 const char EXP_CHARS[] = "eE";
453 /* Chars that mean this number is a floating point constant */
456 const char FLT_CHARS[] = "rRsSfFdDxXpP";
458 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
459 changed in read.c . Ideally it shouldn't have to know about it at all,
460 but nothing is ideal around here.
463 static char *insn_error;
465 static int auto_align = 1;
467 /* When outputting SVR4 PIC code, the assembler needs to know the
468 offset in the stack frame from which to restore the $gp register.
469 This is set by the .cprestore pseudo-op, and saved in this
471 static offsetT mips_cprestore_offset = -1;
473 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
474 more optimizations, it can use a register value instead of a memory-saved
475 offset and even an other register than $gp as global pointer. */
476 static offsetT mips_cpreturn_offset = -1;
477 static int mips_cpreturn_register = -1;
478 static int mips_gp_register = GP;
479 static int mips_gprel_offset = 0;
481 /* Whether mips_cprestore_offset has been set in the current function
482 (or whether it has already been warned about, if not). */
483 static int mips_cprestore_valid = 0;
485 /* This is the register which holds the stack frame, as set by the
486 .frame pseudo-op. This is needed to implement .cprestore. */
487 static int mips_frame_reg = SP;
489 /* Whether mips_frame_reg has been set in the current function
490 (or whether it has already been warned about, if not). */
491 static int mips_frame_reg_valid = 0;
493 /* To output NOP instructions correctly, we need to keep information
494 about the previous two instructions. */
496 /* Whether we are optimizing. The default value of 2 means to remove
497 unneeded NOPs and swap branch instructions when possible. A value
498 of 1 means to not swap branches. A value of 0 means to always
500 static int mips_optimize = 2;
502 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
503 equivalent to seeing no -g option at all. */
504 static int mips_debug = 0;
506 /* The previous instruction. */
507 static struct mips_cl_insn prev_insn;
509 /* The instruction before prev_insn. */
510 static struct mips_cl_insn prev_prev_insn;
512 /* If we don't want information for prev_insn or prev_prev_insn, we
513 point the insn_mo field at this dummy integer. */
514 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
516 /* Non-zero if prev_insn is valid. */
517 static int prev_insn_valid;
519 /* The frag for the previous instruction. */
520 static struct frag *prev_insn_frag;
522 /* The offset into prev_insn_frag for the previous instruction. */
523 static long prev_insn_where;
525 /* The reloc type for the previous instruction, if any. */
526 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
528 /* The reloc for the previous instruction, if any. */
529 static fixS *prev_insn_fixp[3];
531 /* Non-zero if the previous instruction was in a delay slot. */
532 static int prev_insn_is_delay_slot;
534 /* Non-zero if the previous instruction was in a .set noreorder. */
535 static int prev_insn_unreordered;
537 /* Non-zero if the previous instruction uses an extend opcode (if
539 static int prev_insn_extended;
541 /* Non-zero if the previous previous instruction was in a .set
543 static int prev_prev_insn_unreordered;
545 /* If this is set, it points to a frag holding nop instructions which
546 were inserted before the start of a noreorder section. If those
547 nops turn out to be unnecessary, the size of the frag can be
549 static fragS *prev_nop_frag;
551 /* The number of nop instructions we created in prev_nop_frag. */
552 static int prev_nop_frag_holds;
554 /* The number of nop instructions that we know we need in
556 static int prev_nop_frag_required;
558 /* The number of instructions we've seen since prev_nop_frag. */
559 static int prev_nop_frag_since;
561 /* For ECOFF and ELF, relocations against symbols are done in two
562 parts, with a HI relocation and a LO relocation. Each relocation
563 has only 16 bits of space to store an addend. This means that in
564 order for the linker to handle carries correctly, it must be able
565 to locate both the HI and the LO relocation. This means that the
566 relocations must appear in order in the relocation table.
568 In order to implement this, we keep track of each unmatched HI
569 relocation. We then sort them so that they immediately precede the
570 corresponding LO relocation. */
575 struct mips_hi_fixup *next;
578 /* The section this fixup is in. */
582 /* The list of unmatched HI relocs. */
584 static struct mips_hi_fixup *mips_hi_fixup_list;
586 /* The frag containing the last explicit relocation operator.
587 Null if explicit relocations have not been used. */
589 static fragS *prev_reloc_op_frag;
591 /* Map normal MIPS register numbers to mips16 register numbers. */
593 #define X ILLEGAL_REG
594 static const int mips32_to_16_reg_map[] =
596 X, X, 2, 3, 4, 5, 6, 7,
597 X, X, X, X, X, X, X, X,
598 0, 1, X, X, X, X, X, X,
599 X, X, X, X, X, X, X, X
603 /* Map mips16 register numbers to normal MIPS register numbers. */
605 static const unsigned int mips16_to_32_reg_map[] =
607 16, 17, 2, 3, 4, 5, 6, 7
610 static int mips_fix_4122_bugs;
612 /* We don't relax branches by default, since this causes us to expand
613 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
614 fail to compute the offset before expanding the macro to the most
615 efficient expansion. */
617 static int mips_relax_branch;
619 /* The expansion of many macros depends on the type of symbol that
620 they refer to. For example, when generating position-dependent code,
621 a macro that refers to a symbol may have two different expansions,
622 one which uses GP-relative addresses and one which uses absolute
623 addresses. When generating SVR4-style PIC, a macro may have
624 different expansions for local and global symbols.
626 We handle these situations by generating both sequences and putting
627 them in variant frags. In position-dependent code, the first sequence
628 will be the GP-relative one and the second sequence will be the
629 absolute one. In SVR4 PIC, the first sequence will be for global
630 symbols and the second will be for local symbols.
632 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND, WARN), where
633 FIRST and SECOND are the lengths of the two sequences in bytes
634 and WARN is true if ".set nomacro" was in effect when the macro
635 was expanded. These fields can be extracted using RELAX_FIRST(),
636 RELAX_SECOND() and RELAX_WARN().
638 In addition, the RELAX_USE_SECOND flag is set if it has been decided
639 that we should use the second sequence instead of the first.
641 The frag's "opcode" points to the first fixup for relaxable code.
643 Relaxable macros are generated using a sequence such as:
645 relax_start (SYMBOL);
646 ... generate first expansion ...
648 ... generate second expansion ...
651 The code and fixups for the unwanted alternative are discarded
652 by md_convert_frag. */
653 #define RELAX_ENCODE(FIRST, SECOND, WARN) \
654 (((FIRST) << 8) | ((SECOND) << 1) | ((WARN) != 0))
656 #define RELAX_FIRST(X) (((X) >> 8) & 0x7f)
657 #define RELAX_SECOND(X) (((X) >> 1) & 0x7f)
658 #define RELAX_WARN(X) ((X) & 1)
659 #define RELAX_USE_SECOND 0x8000
661 /* Branch without likely bit. If label is out of range, we turn:
663 beq reg1, reg2, label
673 with the following opcode replacements:
680 bltzal <-> bgezal (with jal label instead of j label)
682 Even though keeping the delay slot instruction in the delay slot of
683 the branch would be more efficient, it would be very tricky to do
684 correctly, because we'd have to introduce a variable frag *after*
685 the delay slot instruction, and expand that instead. Let's do it
686 the easy way for now, even if the branch-not-taken case now costs
687 one additional instruction. Out-of-range branches are not supposed
688 to be common, anyway.
690 Branch likely. If label is out of range, we turn:
692 beql reg1, reg2, label
693 delay slot (annulled if branch not taken)
702 delay slot (executed only if branch taken)
705 It would be possible to generate a shorter sequence by losing the
706 likely bit, generating something like:
711 delay slot (executed only if branch taken)
723 bltzall -> bgezal (with jal label instead of j label)
724 bgezall -> bltzal (ditto)
727 but it's not clear that it would actually improve performance. */
728 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
731 | ((toofar) ? 1 : 0) \
733 | ((likely) ? 4 : 0) \
734 | ((uncond) ? 8 : 0)))
735 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
736 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
737 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
738 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
739 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
741 /* For mips16 code, we use an entirely different form of relaxation.
742 mips16 supports two versions of most instructions which take
743 immediate values: a small one which takes some small value, and a
744 larger one which takes a 16 bit value. Since branches also follow
745 this pattern, relaxing these values is required.
747 We can assemble both mips16 and normal MIPS code in a single
748 object. Therefore, we need to support this type of relaxation at
749 the same time that we support the relaxation described above. We
750 use the high bit of the subtype field to distinguish these cases.
752 The information we store for this type of relaxation is the
753 argument code found in the opcode file for this relocation, whether
754 the user explicitly requested a small or extended form, and whether
755 the relocation is in a jump or jal delay slot. That tells us the
756 size of the value, and how it should be stored. We also store
757 whether the fragment is considered to be extended or not. We also
758 store whether this is known to be a branch to a different section,
759 whether we have tried to relax this frag yet, and whether we have
760 ever extended a PC relative fragment because of a shift count. */
761 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
764 | ((small) ? 0x100 : 0) \
765 | ((ext) ? 0x200 : 0) \
766 | ((dslot) ? 0x400 : 0) \
767 | ((jal_dslot) ? 0x800 : 0))
768 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
769 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
770 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
771 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
772 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
773 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
774 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
775 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
776 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
777 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
778 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
779 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
781 /* Is the given value a sign-extended 32-bit value? */
782 #define IS_SEXT_32BIT_NUM(x) \
783 (((x) &~ (offsetT) 0x7fffffff) == 0 \
784 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
786 /* Is the given value a sign-extended 16-bit value? */
787 #define IS_SEXT_16BIT_NUM(x) \
788 (((x) &~ (offsetT) 0x7fff) == 0 \
789 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
792 /* Global variables used when generating relaxable macros. See the
793 comment above RELAX_ENCODE for more details about how relaxation
796 /* 0 if we're not emitting a relaxable macro.
797 1 if we're emitting the first of the two relaxation alternatives.
798 2 if we're emitting the second alternative. */
801 /* The first relaxable fixup in the current frag. (In other words,
802 the first fixup that refers to relaxable code.) */
805 /* sizes[0] says how many bytes of the first alternative are stored in
806 the current frag. Likewise sizes[1] for the second alternative. */
807 unsigned int sizes[2];
809 /* The symbol on which the choice of sequence depends. */
813 /* Prototypes for static functions. */
815 #define internalError() \
816 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
818 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
820 static void append_insn
821 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
822 static void mips_no_prev_insn (int);
823 static void mips16_macro_build
824 (int *, expressionS *, const char *, const char *, va_list);
825 static void load_register (int *, int, expressionS *, int);
826 static void macro (struct mips_cl_insn * ip);
827 static void mips16_macro (struct mips_cl_insn * ip);
828 #ifdef LOSING_COMPILER
829 static void macro2 (struct mips_cl_insn * ip);
831 static void mips_ip (char *str, struct mips_cl_insn * ip);
832 static void mips16_ip (char *str, struct mips_cl_insn * ip);
833 static void mips16_immed
834 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
835 unsigned long *, bfd_boolean *, unsigned short *);
836 static size_t my_getSmallExpression
837 (expressionS *, bfd_reloc_code_real_type *, char *);
838 static void my_getExpression (expressionS *, char *);
839 static void s_align (int);
840 static void s_change_sec (int);
841 static void s_change_section (int);
842 static void s_cons (int);
843 static void s_float_cons (int);
844 static void s_mips_globl (int);
845 static void s_option (int);
846 static void s_mipsset (int);
847 static void s_abicalls (int);
848 static void s_cpload (int);
849 static void s_cpsetup (int);
850 static void s_cplocal (int);
851 static void s_cprestore (int);
852 static void s_cpreturn (int);
853 static void s_gpvalue (int);
854 static void s_gpword (int);
855 static void s_gpdword (int);
856 static void s_cpadd (int);
857 static void s_insn (int);
858 static void md_obj_begin (void);
859 static void md_obj_end (void);
860 static void s_mips_ent (int);
861 static void s_mips_end (int);
862 static void s_mips_frame (int);
863 static void s_mips_mask (int reg_type);
864 static void s_mips_stab (int);
865 static void s_mips_weakext (int);
866 static void s_mips_file (int);
867 static void s_mips_loc (int);
868 static bfd_boolean pic_need_relax (symbolS *, asection *);
869 static int relaxed_branch_length (fragS *, asection *, int);
870 static int validate_mips_insn (const struct mips_opcode *);
872 /* Table and functions used to map between CPU/ISA names, and
873 ISA levels, and CPU numbers. */
877 const char *name; /* CPU or ISA name. */
878 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
879 int isa; /* ISA level. */
880 int cpu; /* CPU number (default CPU if ISA). */
883 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
884 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
885 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
889 The following pseudo-ops from the Kane and Heinrich MIPS book
890 should be defined here, but are currently unsupported: .alias,
891 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
893 The following pseudo-ops from the Kane and Heinrich MIPS book are
894 specific to the type of debugging information being generated, and
895 should be defined by the object format: .aent, .begin, .bend,
896 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
899 The following pseudo-ops from the Kane and Heinrich MIPS book are
900 not MIPS CPU specific, but are also not specific to the object file
901 format. This file is probably the best place to define them, but
902 they are not currently supported: .asm0, .endr, .lab, .repeat,
905 static const pseudo_typeS mips_pseudo_table[] =
907 /* MIPS specific pseudo-ops. */
908 {"option", s_option, 0},
909 {"set", s_mipsset, 0},
910 {"rdata", s_change_sec, 'r'},
911 {"sdata", s_change_sec, 's'},
912 {"livereg", s_ignore, 0},
913 {"abicalls", s_abicalls, 0},
914 {"cpload", s_cpload, 0},
915 {"cpsetup", s_cpsetup, 0},
916 {"cplocal", s_cplocal, 0},
917 {"cprestore", s_cprestore, 0},
918 {"cpreturn", s_cpreturn, 0},
919 {"gpvalue", s_gpvalue, 0},
920 {"gpword", s_gpword, 0},
921 {"gpdword", s_gpdword, 0},
922 {"cpadd", s_cpadd, 0},
925 /* Relatively generic pseudo-ops that happen to be used on MIPS
927 {"asciiz", stringer, 1},
928 {"bss", s_change_sec, 'b'},
931 {"dword", s_cons, 3},
932 {"weakext", s_mips_weakext, 0},
934 /* These pseudo-ops are defined in read.c, but must be overridden
935 here for one reason or another. */
936 {"align", s_align, 0},
938 {"data", s_change_sec, 'd'},
939 {"double", s_float_cons, 'd'},
940 {"float", s_float_cons, 'f'},
941 {"globl", s_mips_globl, 0},
942 {"global", s_mips_globl, 0},
943 {"hword", s_cons, 1},
948 {"section", s_change_section, 0},
949 {"short", s_cons, 1},
950 {"single", s_float_cons, 'f'},
951 {"stabn", s_mips_stab, 'n'},
952 {"text", s_change_sec, 't'},
955 { "extern", ecoff_directive_extern, 0},
960 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
962 /* These pseudo-ops should be defined by the object file format.
963 However, a.out doesn't support them, so we have versions here. */
964 {"aent", s_mips_ent, 1},
965 {"bgnb", s_ignore, 0},
966 {"end", s_mips_end, 0},
967 {"endb", s_ignore, 0},
968 {"ent", s_mips_ent, 0},
969 {"file", s_mips_file, 0},
970 {"fmask", s_mips_mask, 'F'},
971 {"frame", s_mips_frame, 0},
972 {"loc", s_mips_loc, 0},
973 {"mask", s_mips_mask, 'R'},
974 {"verstamp", s_ignore, 0},
978 extern void pop_insert (const pseudo_typeS *);
981 mips_pop_insert (void)
983 pop_insert (mips_pseudo_table);
984 if (! ECOFF_DEBUGGING)
985 pop_insert (mips_nonecoff_pseudo_table);
988 /* Symbols labelling the current insn. */
990 struct insn_label_list
992 struct insn_label_list *next;
996 static struct insn_label_list *insn_labels;
997 static struct insn_label_list *free_insn_labels;
999 static void mips_clear_insn_labels (void);
1002 mips_clear_insn_labels (void)
1004 register struct insn_label_list **pl;
1006 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1012 static char *expr_end;
1014 /* Expressions which appear in instructions. These are set by
1017 static expressionS imm_expr;
1018 static expressionS imm2_expr;
1019 static expressionS offset_expr;
1021 /* Relocs associated with imm_expr and offset_expr. */
1023 static bfd_reloc_code_real_type imm_reloc[3]
1024 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1025 static bfd_reloc_code_real_type offset_reloc[3]
1026 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1028 /* These are set by mips16_ip if an explicit extension is used. */
1030 static bfd_boolean mips16_small, mips16_ext;
1033 /* The pdr segment for per procedure frame/regmask info. Not used for
1036 static segT pdr_seg;
1039 /* The default target format to use. */
1042 mips_target_format (void)
1044 switch (OUTPUT_FLAVOR)
1046 case bfd_target_aout_flavour:
1047 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1048 case bfd_target_ecoff_flavour:
1049 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1050 case bfd_target_coff_flavour:
1052 case bfd_target_elf_flavour:
1054 /* This is traditional mips. */
1055 return (target_big_endian
1056 ? (HAVE_64BIT_OBJECTS
1057 ? "elf64-tradbigmips"
1059 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1060 : (HAVE_64BIT_OBJECTS
1061 ? "elf64-tradlittlemips"
1063 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1065 return (target_big_endian
1066 ? (HAVE_64BIT_OBJECTS
1069 ? "elf32-nbigmips" : "elf32-bigmips"))
1070 : (HAVE_64BIT_OBJECTS
1071 ? "elf64-littlemips"
1073 ? "elf32-nlittlemips" : "elf32-littlemips")));
1081 /* This function is called once, at assembler startup time. It should
1082 set up all the tables, etc. that the MD part of the assembler will need. */
1087 register const char *retval = NULL;
1091 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1092 as_warn (_("Could not set architecture and machine"));
1094 op_hash = hash_new ();
1096 for (i = 0; i < NUMOPCODES;)
1098 const char *name = mips_opcodes[i].name;
1100 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1103 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1104 mips_opcodes[i].name, retval);
1105 /* Probably a memory allocation problem? Give up now. */
1106 as_fatal (_("Broken assembler. No assembly attempted."));
1110 if (mips_opcodes[i].pinfo != INSN_MACRO)
1112 if (!validate_mips_insn (&mips_opcodes[i]))
1117 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1120 mips16_op_hash = hash_new ();
1123 while (i < bfd_mips16_num_opcodes)
1125 const char *name = mips16_opcodes[i].name;
1127 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1129 as_fatal (_("internal: can't hash `%s': %s"),
1130 mips16_opcodes[i].name, retval);
1133 if (mips16_opcodes[i].pinfo != INSN_MACRO
1134 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1135 != mips16_opcodes[i].match))
1137 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1138 mips16_opcodes[i].name, mips16_opcodes[i].args);
1143 while (i < bfd_mips16_num_opcodes
1144 && strcmp (mips16_opcodes[i].name, name) == 0);
1148 as_fatal (_("Broken assembler. No assembly attempted."));
1150 /* We add all the general register names to the symbol table. This
1151 helps us detect invalid uses of them. */
1152 for (i = 0; i < 32; i++)
1156 sprintf (buf, "$%d", i);
1157 symbol_table_insert (symbol_new (buf, reg_section, i,
1158 &zero_address_frag));
1160 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1161 &zero_address_frag));
1162 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1163 &zero_address_frag));
1164 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1165 &zero_address_frag));
1166 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1167 &zero_address_frag));
1168 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1169 &zero_address_frag));
1170 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1171 &zero_address_frag));
1172 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1173 &zero_address_frag));
1174 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1175 &zero_address_frag));
1176 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1177 &zero_address_frag));
1179 /* If we don't add these register names to the symbol table, they
1180 may end up being added as regular symbols by operand(), and then
1181 make it to the object file as undefined in case they're not
1182 regarded as local symbols. They're local in o32, since `$' is a
1183 local symbol prefix, but not in n32 or n64. */
1184 for (i = 0; i < 8; i++)
1188 sprintf (buf, "$fcc%i", i);
1189 symbol_table_insert (symbol_new (buf, reg_section, -1,
1190 &zero_address_frag));
1193 mips_no_prev_insn (FALSE);
1196 mips_cprmask[0] = 0;
1197 mips_cprmask[1] = 0;
1198 mips_cprmask[2] = 0;
1199 mips_cprmask[3] = 0;
1201 /* set the default alignment for the text section (2**2) */
1202 record_alignment (text_section, 2);
1204 if (USE_GLOBAL_POINTER_OPT)
1205 bfd_set_gp_size (stdoutput, g_switch_value);
1207 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1209 /* On a native system, sections must be aligned to 16 byte
1210 boundaries. When configured for an embedded ELF target, we
1212 if (strcmp (TARGET_OS, "elf") != 0)
1214 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1215 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1216 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1219 /* Create a .reginfo section for register masks and a .mdebug
1220 section for debugging information. */
1228 subseg = now_subseg;
1230 /* The ABI says this section should be loaded so that the
1231 running program can access it. However, we don't load it
1232 if we are configured for an embedded target */
1233 flags = SEC_READONLY | SEC_DATA;
1234 if (strcmp (TARGET_OS, "elf") != 0)
1235 flags |= SEC_ALLOC | SEC_LOAD;
1237 if (mips_abi != N64_ABI)
1239 sec = subseg_new (".reginfo", (subsegT) 0);
1241 bfd_set_section_flags (stdoutput, sec, flags);
1242 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1245 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1250 /* The 64-bit ABI uses a .MIPS.options section rather than
1251 .reginfo section. */
1252 sec = subseg_new (".MIPS.options", (subsegT) 0);
1253 bfd_set_section_flags (stdoutput, sec, flags);
1254 bfd_set_section_alignment (stdoutput, sec, 3);
1257 /* Set up the option header. */
1259 Elf_Internal_Options opthdr;
1262 opthdr.kind = ODK_REGINFO;
1263 opthdr.size = (sizeof (Elf_External_Options)
1264 + sizeof (Elf64_External_RegInfo));
1267 f = frag_more (sizeof (Elf_External_Options));
1268 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1269 (Elf_External_Options *) f);
1271 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1276 if (ECOFF_DEBUGGING)
1278 sec = subseg_new (".mdebug", (subsegT) 0);
1279 (void) bfd_set_section_flags (stdoutput, sec,
1280 SEC_HAS_CONTENTS | SEC_READONLY);
1281 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1284 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1286 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1287 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1288 SEC_READONLY | SEC_RELOC
1290 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1294 subseg_set (seg, subseg);
1298 if (! ECOFF_DEBUGGING)
1305 if (! ECOFF_DEBUGGING)
1310 md_assemble (char *str)
1312 struct mips_cl_insn insn;
1313 bfd_reloc_code_real_type unused_reloc[3]
1314 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1316 imm_expr.X_op = O_absent;
1317 imm2_expr.X_op = O_absent;
1318 offset_expr.X_op = O_absent;
1319 imm_reloc[0] = BFD_RELOC_UNUSED;
1320 imm_reloc[1] = BFD_RELOC_UNUSED;
1321 imm_reloc[2] = BFD_RELOC_UNUSED;
1322 offset_reloc[0] = BFD_RELOC_UNUSED;
1323 offset_reloc[1] = BFD_RELOC_UNUSED;
1324 offset_reloc[2] = BFD_RELOC_UNUSED;
1326 if (mips_opts.mips16)
1327 mips16_ip (str, &insn);
1330 mips_ip (str, &insn);
1331 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1332 str, insn.insn_opcode));
1337 as_bad ("%s `%s'", insn_error, str);
1341 if (insn.insn_mo->pinfo == INSN_MACRO)
1343 if (mips_opts.mips16)
1344 mips16_macro (&insn);
1350 if (imm_expr.X_op != O_absent)
1351 append_insn (&insn, &imm_expr, imm_reloc);
1352 else if (offset_expr.X_op != O_absent)
1353 append_insn (&insn, &offset_expr, offset_reloc);
1355 append_insn (&insn, NULL, unused_reloc);
1359 /* Return true if the given relocation might need a matching %lo().
1360 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1361 applied to local symbols. */
1363 static inline bfd_boolean
1364 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1366 return (reloc == BFD_RELOC_HI16_S
1367 || reloc == BFD_RELOC_MIPS_GOT16);
1370 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1373 static inline bfd_boolean
1374 fixup_has_matching_lo_p (fixS *fixp)
1376 return (fixp->fx_next != NULL
1377 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1378 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1379 && fixp->fx_offset == fixp->fx_next->fx_offset);
1382 /* See whether instruction IP reads register REG. CLASS is the type
1386 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1387 enum mips_regclass class)
1389 if (class == MIPS16_REG)
1391 assert (mips_opts.mips16);
1392 reg = mips16_to_32_reg_map[reg];
1393 class = MIPS_GR_REG;
1396 /* Don't report on general register ZERO, since it never changes. */
1397 if (class == MIPS_GR_REG && reg == ZERO)
1400 if (class == MIPS_FP_REG)
1402 assert (! mips_opts.mips16);
1403 /* If we are called with either $f0 or $f1, we must check $f0.
1404 This is not optimal, because it will introduce an unnecessary
1405 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1406 need to distinguish reading both $f0 and $f1 or just one of
1407 them. Note that we don't have to check the other way,
1408 because there is no instruction that sets both $f0 and $f1
1409 and requires a delay. */
1410 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1411 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1412 == (reg &~ (unsigned) 1)))
1414 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1415 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1416 == (reg &~ (unsigned) 1)))
1419 else if (! mips_opts.mips16)
1421 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1422 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1424 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1425 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1430 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1431 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1432 & MIPS16OP_MASK_RX)]
1435 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1436 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1437 & MIPS16OP_MASK_RY)]
1440 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1441 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1442 & MIPS16OP_MASK_MOVE32Z)]
1445 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1447 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1449 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1451 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1452 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1453 & MIPS16OP_MASK_REGR32) == reg)
1460 /* This function returns true if modifying a register requires a
1464 reg_needs_delay (unsigned int reg)
1466 unsigned long prev_pinfo;
1468 prev_pinfo = prev_insn.insn_mo->pinfo;
1469 if (! mips_opts.noreorder
1470 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1471 && ! gpr_interlocks)
1472 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1473 && ! cop_interlocks)))
1475 /* A load from a coprocessor or from memory. All load delays
1476 delay the use of general register rt for one instruction. */
1477 /* Itbl support may require additional care here. */
1478 know (prev_pinfo & INSN_WRITE_GPR_T);
1479 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1486 /* Mark instruction labels in mips16 mode. This permits the linker to
1487 handle them specially, such as generating jalx instructions when
1488 needed. We also make them odd for the duration of the assembly, in
1489 order to generate the right sort of code. We will make them even
1490 in the adjust_symtab routine, while leaving them marked. This is
1491 convenient for the debugger and the disassembler. The linker knows
1492 to make them odd again. */
1495 mips16_mark_labels (void)
1497 if (mips_opts.mips16)
1499 struct insn_label_list *l;
1502 for (l = insn_labels; l != NULL; l = l->next)
1505 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1506 S_SET_OTHER (l->label, STO_MIPS16);
1508 val = S_GET_VALUE (l->label);
1510 S_SET_VALUE (l->label, val + 1);
1515 /* End the current frag. Make it a variant frag and record the
1519 relax_close_frag (void)
1521 frag_var (rs_machine_dependent, 0, 0,
1522 RELAX_ENCODE (mips_relax.sizes[0],
1523 mips_relax.sizes[1],
1524 mips_opts.warn_about_macros),
1525 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1527 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1528 mips_relax.first_fixup = 0;
1531 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1532 See the comment above RELAX_ENCODE for more details. */
1535 relax_start (symbolS *symbol)
1537 assert (mips_relax.sequence == 0);
1538 mips_relax.sequence = 1;
1539 mips_relax.symbol = symbol;
1542 /* Start generating the second version of a relaxable sequence.
1543 See the comment above RELAX_ENCODE for more details. */
1548 assert (mips_relax.sequence == 1);
1549 mips_relax.sequence = 2;
1552 /* End the current relaxable sequence. */
1557 assert (mips_relax.sequence == 2);
1558 relax_close_frag ();
1559 mips_relax.sequence = 0;
1562 /* Output an instruction. IP is the instruction information.
1563 ADDRESS_EXPR is an operand of the instruction to be used with
1567 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1568 bfd_reloc_code_real_type *reloc_type)
1570 register unsigned long prev_pinfo, pinfo;
1574 relax_stateT prev_insn_frag_type = 0;
1575 bfd_boolean relaxed_branch = FALSE;
1576 bfd_boolean force_new_frag = FALSE;
1578 /* Mark instruction labels in mips16 mode. */
1579 mips16_mark_labels ();
1581 prev_pinfo = prev_insn.insn_mo->pinfo;
1582 pinfo = ip->insn_mo->pinfo;
1584 if (mips_relax.sequence != 2
1585 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1589 /* If the previous insn required any delay slots, see if we need
1590 to insert a NOP or two. There are eight kinds of possible
1591 hazards, of which an instruction can have at most one type.
1592 (1) a load from memory delay
1593 (2) a load from a coprocessor delay
1594 (3) an unconditional branch delay
1595 (4) a conditional branch delay
1596 (5) a move to coprocessor register delay
1597 (6) a load coprocessor register from memory delay
1598 (7) a coprocessor condition code delay
1599 (8) a HI/LO special register delay
1601 There are a lot of optimizations we could do that we don't.
1602 In particular, we do not, in general, reorder instructions.
1603 If you use gcc with optimization, it will reorder
1604 instructions and generally do much more optimization then we
1605 do here; repeating all that work in the assembler would only
1606 benefit hand written assembly code, and does not seem worth
1609 /* This is how a NOP is emitted. */
1610 #define emit_nop() \
1612 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1613 : md_number_to_chars (frag_more (4), 0, 4))
1615 /* The previous insn might require a delay slot, depending upon
1616 the contents of the current insn. */
1617 if (! mips_opts.mips16
1618 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1619 && ! gpr_interlocks)
1620 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1621 && ! cop_interlocks)))
1623 /* A load from a coprocessor or from memory. All load
1624 delays delay the use of general register rt for one
1626 /* Itbl support may require additional care here. */
1627 know (prev_pinfo & INSN_WRITE_GPR_T);
1628 if (mips_optimize == 0
1629 || insn_uses_reg (ip,
1630 ((prev_insn.insn_opcode >> OP_SH_RT)
1635 else if (! mips_opts.mips16
1636 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1637 && ! cop_interlocks)
1638 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1639 && ! cop_mem_interlocks)))
1641 /* A generic coprocessor delay. The previous instruction
1642 modified a coprocessor general or control register. If
1643 it modified a control register, we need to avoid any
1644 coprocessor instruction (this is probably not always
1645 required, but it sometimes is). If it modified a general
1646 register, we avoid using that register.
1648 This case is not handled very well. There is no special
1649 knowledge of CP0 handling, and the coprocessors other
1650 than the floating point unit are not distinguished at
1652 /* Itbl support may require additional care here. FIXME!
1653 Need to modify this to include knowledge about
1654 user specified delays! */
1655 if (prev_pinfo & INSN_WRITE_FPR_T)
1657 if (mips_optimize == 0
1658 || insn_uses_reg (ip,
1659 ((prev_insn.insn_opcode >> OP_SH_FT)
1664 else if (prev_pinfo & INSN_WRITE_FPR_S)
1666 if (mips_optimize == 0
1667 || insn_uses_reg (ip,
1668 ((prev_insn.insn_opcode >> OP_SH_FS)
1675 /* We don't know exactly what the previous instruction
1676 does. If the current instruction uses a coprocessor
1677 register, we must insert a NOP. If previous
1678 instruction may set the condition codes, and the
1679 current instruction uses them, we must insert two
1681 /* Itbl support may require additional care here. */
1682 if (mips_optimize == 0
1683 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1684 && (pinfo & INSN_READ_COND_CODE)))
1686 else if (pinfo & INSN_COP)
1690 else if (! mips_opts.mips16
1691 && (prev_pinfo & INSN_WRITE_COND_CODE)
1692 && ! cop_interlocks)
1694 /* The previous instruction sets the coprocessor condition
1695 codes, but does not require a general coprocessor delay
1696 (this means it is a floating point comparison
1697 instruction). If this instruction uses the condition
1698 codes, we need to insert a single NOP. */
1699 /* Itbl support may require additional care here. */
1700 if (mips_optimize == 0
1701 || (pinfo & INSN_READ_COND_CODE))
1705 /* If we're fixing up mfhi/mflo for the r7000 and the
1706 previous insn was an mfhi/mflo and the current insn
1707 reads the register that the mfhi/mflo wrote to, then
1710 else if (mips_7000_hilo_fix
1711 && MF_HILO_INSN (prev_pinfo)
1712 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1719 /* If we're fixing up mfhi/mflo for the r7000 and the
1720 2nd previous insn was an mfhi/mflo and the current insn
1721 reads the register that the mfhi/mflo wrote to, then
1724 else if (mips_7000_hilo_fix
1725 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1726 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1734 else if (prev_pinfo & INSN_READ_LO)
1736 /* The previous instruction reads the LO register; if the
1737 current instruction writes to the LO register, we must
1738 insert two NOPS. Some newer processors have interlocks.
1739 Also the tx39's multiply instructions can be executed
1740 immediately after a read from HI/LO (without the delay),
1741 though the tx39's divide insns still do require the
1743 if (! (hilo_interlocks
1744 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1745 && (mips_optimize == 0
1746 || (pinfo & INSN_WRITE_LO)))
1748 /* Most mips16 branch insns don't have a delay slot.
1749 If a read from LO is immediately followed by a branch
1750 to a write to LO we have a read followed by a write
1751 less than 2 insns away. We assume the target of
1752 a branch might be a write to LO, and insert a nop
1753 between a read and an immediately following branch. */
1754 else if (mips_opts.mips16
1755 && (mips_optimize == 0
1756 || (pinfo & MIPS16_INSN_BRANCH)))
1759 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1761 /* The previous instruction reads the HI register; if the
1762 current instruction writes to the HI register, we must
1763 insert a NOP. Some newer processors have interlocks.
1764 Also the note tx39's multiply above. */
1765 if (! (hilo_interlocks
1766 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1767 && (mips_optimize == 0
1768 || (pinfo & INSN_WRITE_HI)))
1770 /* Most mips16 branch insns don't have a delay slot.
1771 If a read from HI is immediately followed by a branch
1772 to a write to HI we have a read followed by a write
1773 less than 2 insns away. We assume the target of
1774 a branch might be a write to HI, and insert a nop
1775 between a read and an immediately following branch. */
1776 else if (mips_opts.mips16
1777 && (mips_optimize == 0
1778 || (pinfo & MIPS16_INSN_BRANCH)))
1782 /* If the previous instruction was in a noreorder section, then
1783 we don't want to insert the nop after all. */
1784 /* Itbl support may require additional care here. */
1785 if (prev_insn_unreordered)
1788 /* There are two cases which require two intervening
1789 instructions: 1) setting the condition codes using a move to
1790 coprocessor instruction which requires a general coprocessor
1791 delay and then reading the condition codes 2) reading the HI
1792 or LO register and then writing to it (except on processors
1793 which have interlocks). If we are not already emitting a NOP
1794 instruction, we must check for these cases compared to the
1795 instruction previous to the previous instruction. */
1796 if ((! mips_opts.mips16
1797 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1798 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1799 && (pinfo & INSN_READ_COND_CODE)
1800 && ! cop_interlocks)
1801 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1802 && (pinfo & INSN_WRITE_LO)
1803 && ! (hilo_interlocks
1804 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1805 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1806 && (pinfo & INSN_WRITE_HI)
1807 && ! (hilo_interlocks
1808 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1813 if (prev_prev_insn_unreordered)
1816 if (prev_prev_nop && nops == 0)
1819 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1821 /* We're out of bits in pinfo, so we must resort to string
1822 ops here. Shortcuts are selected based on opcodes being
1823 limited to the VR4122 instruction set. */
1825 const char *pn = prev_insn.insn_mo->name;
1826 const char *tn = ip->insn_mo->name;
1827 if (strncmp(pn, "macc", 4) == 0
1828 || strncmp(pn, "dmacc", 5) == 0)
1830 /* Errata 21 - [D]DIV[U] after [D]MACC */
1831 if (strstr (tn, "div"))
1836 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1837 if (pn[0] == 'd' /* dmacc */
1838 && (strncmp(tn, "dmult", 5) == 0
1839 || strncmp(tn, "dmacc", 5) == 0))
1844 /* Errata 24 - MT{LO,HI} after [D]MACC */
1845 if (strcmp (tn, "mtlo") == 0
1846 || strcmp (tn, "mthi") == 0)
1852 else if (strncmp(pn, "dmult", 5) == 0
1853 && (strncmp(tn, "dmult", 5) == 0
1854 || strncmp(tn, "dmacc", 5) == 0))
1856 /* Here is the rest of errata 23. */
1859 if (nops < min_nops)
1863 /* If we are being given a nop instruction, don't bother with
1864 one of the nops we would otherwise output. This will only
1865 happen when a nop instruction is used with mips_optimize set
1868 && ! mips_opts.noreorder
1869 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1872 /* Now emit the right number of NOP instructions. */
1873 if (nops > 0 && ! mips_opts.noreorder)
1876 unsigned long old_frag_offset;
1878 struct insn_label_list *l;
1880 old_frag = frag_now;
1881 old_frag_offset = frag_now_fix ();
1883 for (i = 0; i < nops; i++)
1888 listing_prev_line ();
1889 /* We may be at the start of a variant frag. In case we
1890 are, make sure there is enough space for the frag
1891 after the frags created by listing_prev_line. The
1892 argument to frag_grow here must be at least as large
1893 as the argument to all other calls to frag_grow in
1894 this file. We don't have to worry about being in the
1895 middle of a variant frag, because the variants insert
1896 all needed nop instructions themselves. */
1900 for (l = insn_labels; l != NULL; l = l->next)
1904 assert (S_GET_SEGMENT (l->label) == now_seg);
1905 symbol_set_frag (l->label, frag_now);
1906 val = (valueT) frag_now_fix ();
1907 /* mips16 text labels are stored as odd. */
1908 if (mips_opts.mips16)
1910 S_SET_VALUE (l->label, val);
1913 #ifndef NO_ECOFF_DEBUGGING
1914 if (ECOFF_DEBUGGING)
1915 ecoff_fix_loc (old_frag, old_frag_offset);
1918 else if (prev_nop_frag != NULL)
1920 /* We have a frag holding nops we may be able to remove. If
1921 we don't need any nops, we can decrease the size of
1922 prev_nop_frag by the size of one instruction. If we do
1923 need some nops, we count them in prev_nops_required. */
1924 if (prev_nop_frag_since == 0)
1928 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1929 --prev_nop_frag_holds;
1932 prev_nop_frag_required += nops;
1936 if (prev_prev_nop == 0)
1938 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1939 --prev_nop_frag_holds;
1942 ++prev_nop_frag_required;
1945 if (prev_nop_frag_holds <= prev_nop_frag_required)
1946 prev_nop_frag = NULL;
1948 ++prev_nop_frag_since;
1950 /* Sanity check: by the time we reach the second instruction
1951 after prev_nop_frag, we should have used up all the nops
1952 one way or another. */
1953 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1957 /* Record the frag type before frag_var. */
1959 prev_insn_frag_type = prev_insn_frag->fr_type;
1962 && *reloc_type == BFD_RELOC_16_PCREL_S2
1963 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1964 || pinfo & INSN_COND_BRANCH_LIKELY)
1965 && mips_relax_branch
1966 /* Don't try branch relaxation within .set nomacro, or within
1967 .set noat if we use $at for PIC computations. If it turns
1968 out that the branch was out-of-range, we'll get an error. */
1969 && !mips_opts.warn_about_macros
1970 && !(mips_opts.noat && mips_pic != NO_PIC)
1971 && !mips_opts.mips16)
1973 relaxed_branch = TRUE;
1974 f = frag_var (rs_machine_dependent,
1975 relaxed_branch_length
1977 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
1978 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
1980 (pinfo & INSN_UNCOND_BRANCH_DELAY,
1981 pinfo & INSN_COND_BRANCH_LIKELY,
1982 pinfo & INSN_WRITE_GPR_31,
1984 address_expr->X_add_symbol,
1985 address_expr->X_add_number,
1987 *reloc_type = BFD_RELOC_UNUSED;
1989 else if (*reloc_type > BFD_RELOC_UNUSED)
1991 /* We need to set up a variant frag. */
1992 assert (mips_opts.mips16 && address_expr != NULL);
1993 f = frag_var (rs_machine_dependent, 4, 0,
1994 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1995 mips16_small, mips16_ext,
1997 & INSN_UNCOND_BRANCH_DELAY),
1998 (*prev_insn_reloc_type
1999 == BFD_RELOC_MIPS16_JMP)),
2000 make_expr_symbol (address_expr), 0, NULL);
2002 else if (mips_opts.mips16
2004 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2006 /* Make sure there is enough room to swap this instruction with
2007 a following jump instruction. */
2013 if (mips_opts.mips16
2014 && mips_opts.noreorder
2015 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2016 as_warn (_("extended instruction in delay slot"));
2018 if (mips_relax.sequence)
2020 /* If we've reached the end of this frag, turn it into a variant
2021 frag and record the information for the instructions we've
2023 if (frag_room () < 4)
2024 relax_close_frag ();
2025 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2031 fixp[0] = fixp[1] = fixp[2] = NULL;
2032 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2034 if (address_expr->X_op == O_constant)
2038 switch (*reloc_type)
2041 ip->insn_opcode |= address_expr->X_add_number;
2044 case BFD_RELOC_MIPS_HIGHEST:
2045 tmp = (address_expr->X_add_number
2046 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2048 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2051 case BFD_RELOC_MIPS_HIGHER:
2052 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2053 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2056 case BFD_RELOC_HI16_S:
2057 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2061 case BFD_RELOC_HI16:
2062 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2065 case BFD_RELOC_LO16:
2066 case BFD_RELOC_MIPS_GOT_DISP:
2067 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2070 case BFD_RELOC_MIPS_JMP:
2071 if ((address_expr->X_add_number & 3) != 0)
2072 as_bad (_("jump to misaligned address (0x%lx)"),
2073 (unsigned long) address_expr->X_add_number);
2074 if (address_expr->X_add_number & ~0xfffffff)
2075 as_bad (_("jump address range overflow (0x%lx)"),
2076 (unsigned long) address_expr->X_add_number);
2077 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2080 case BFD_RELOC_MIPS16_JMP:
2081 if ((address_expr->X_add_number & 3) != 0)
2082 as_bad (_("jump to misaligned address (0x%lx)"),
2083 (unsigned long) address_expr->X_add_number);
2084 if (address_expr->X_add_number & ~0xfffffff)
2085 as_bad (_("jump address range overflow (0x%lx)"),
2086 (unsigned long) address_expr->X_add_number);
2088 (((address_expr->X_add_number & 0x7c0000) << 3)
2089 | ((address_expr->X_add_number & 0xf800000) >> 7)
2090 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2093 case BFD_RELOC_16_PCREL_S2:
2103 reloc_howto_type *howto;
2106 /* In a compound relocation, it is the final (outermost)
2107 operator that determines the relocated field. */
2108 for (i = 1; i < 3; i++)
2109 if (reloc_type[i] == BFD_RELOC_UNUSED)
2112 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2113 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2114 bfd_get_reloc_size(howto),
2116 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2119 /* These relocations can have an addend that won't fit in
2120 4 octets for 64bit assembly. */
2122 && ! howto->partial_inplace
2123 && (reloc_type[0] == BFD_RELOC_16
2124 || reloc_type[0] == BFD_RELOC_32
2125 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2126 || reloc_type[0] == BFD_RELOC_HI16_S
2127 || reloc_type[0] == BFD_RELOC_LO16
2128 || reloc_type[0] == BFD_RELOC_GPREL16
2129 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2130 || reloc_type[0] == BFD_RELOC_GPREL32
2131 || reloc_type[0] == BFD_RELOC_64
2132 || reloc_type[0] == BFD_RELOC_CTOR
2133 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2134 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2135 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2136 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2137 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2138 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2139 fixp[0]->fx_no_overflow = 1;
2141 if (mips_relax.sequence)
2143 if (mips_relax.first_fixup == 0)
2144 mips_relax.first_fixup = fixp[0];
2146 else if (reloc_needs_lo_p (*reloc_type))
2148 struct mips_hi_fixup *hi_fixup;
2150 /* Reuse the last entry if it already has a matching %lo. */
2151 hi_fixup = mips_hi_fixup_list;
2153 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2155 hi_fixup = ((struct mips_hi_fixup *)
2156 xmalloc (sizeof (struct mips_hi_fixup)));
2157 hi_fixup->next = mips_hi_fixup_list;
2158 mips_hi_fixup_list = hi_fixup;
2160 hi_fixup->fixp = fixp[0];
2161 hi_fixup->seg = now_seg;
2164 /* Add fixups for the second and third relocations, if given.
2165 Note that the ABI allows the second relocation to be
2166 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2167 moment we only use RSS_UNDEF, but we could add support
2168 for the others if it ever becomes necessary. */
2169 for (i = 1; i < 3; i++)
2170 if (reloc_type[i] != BFD_RELOC_UNUSED)
2172 address_expr->X_op = O_absent;
2173 address_expr->X_add_symbol = 0;
2174 address_expr->X_add_number = 0;
2176 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2177 fixp[0]->fx_size, address_expr,
2178 FALSE, reloc_type[i]);
2183 if (! mips_opts.mips16)
2185 md_number_to_chars (f, ip->insn_opcode, 4);
2187 dwarf2_emit_insn (4);
2190 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2192 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2193 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2195 dwarf2_emit_insn (4);
2202 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2205 md_number_to_chars (f, ip->insn_opcode, 2);
2207 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2211 /* Update the register mask information. */
2212 if (! mips_opts.mips16)
2214 if (pinfo & INSN_WRITE_GPR_D)
2215 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2216 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2217 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2218 if (pinfo & INSN_READ_GPR_S)
2219 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2220 if (pinfo & INSN_WRITE_GPR_31)
2221 mips_gprmask |= 1 << RA;
2222 if (pinfo & INSN_WRITE_FPR_D)
2223 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2224 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2225 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2226 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2227 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2228 if ((pinfo & INSN_READ_FPR_R) != 0)
2229 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2230 if (pinfo & INSN_COP)
2232 /* We don't keep enough information to sort these cases out.
2233 The itbl support does keep this information however, although
2234 we currently don't support itbl fprmats as part of the cop
2235 instruction. May want to add this support in the future. */
2237 /* Never set the bit for $0, which is always zero. */
2238 mips_gprmask &= ~1 << 0;
2242 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2243 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2244 & MIPS16OP_MASK_RX);
2245 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2246 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2247 & MIPS16OP_MASK_RY);
2248 if (pinfo & MIPS16_INSN_WRITE_Z)
2249 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2250 & MIPS16OP_MASK_RZ);
2251 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2252 mips_gprmask |= 1 << TREG;
2253 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2254 mips_gprmask |= 1 << SP;
2255 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2256 mips_gprmask |= 1 << RA;
2257 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2258 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2259 if (pinfo & MIPS16_INSN_READ_Z)
2260 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2261 & MIPS16OP_MASK_MOVE32Z);
2262 if (pinfo & MIPS16_INSN_READ_GPR_X)
2263 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2264 & MIPS16OP_MASK_REGR32);
2267 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2269 /* Filling the branch delay slot is more complex. We try to
2270 switch the branch with the previous instruction, which we can
2271 do if the previous instruction does not set up a condition
2272 that the branch tests and if the branch is not itself the
2273 target of any branch. */
2274 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2275 || (pinfo & INSN_COND_BRANCH_DELAY))
2277 if (mips_optimize < 2
2278 /* If we have seen .set volatile or .set nomove, don't
2280 || mips_opts.nomove != 0
2281 /* If we had to emit any NOP instructions, then we
2282 already know we can not swap. */
2284 /* If we don't even know the previous insn, we can not
2286 || ! prev_insn_valid
2287 /* If the previous insn is already in a branch delay
2288 slot, then we can not swap. */
2289 || prev_insn_is_delay_slot
2290 /* If the previous previous insn was in a .set
2291 noreorder, we can't swap. Actually, the MIPS
2292 assembler will swap in this situation. However, gcc
2293 configured -with-gnu-as will generate code like
2299 in which we can not swap the bne and INSN. If gcc is
2300 not configured -with-gnu-as, it does not output the
2301 .set pseudo-ops. We don't have to check
2302 prev_insn_unreordered, because prev_insn_valid will
2303 be 0 in that case. We don't want to use
2304 prev_prev_insn_valid, because we do want to be able
2305 to swap at the start of a function. */
2306 || prev_prev_insn_unreordered
2307 /* If the branch is itself the target of a branch, we
2308 can not swap. We cheat on this; all we check for is
2309 whether there is a label on this instruction. If
2310 there are any branches to anything other than a
2311 label, users must use .set noreorder. */
2312 || insn_labels != NULL
2313 /* If the previous instruction is in a variant frag
2314 other than this branch's one, we cannot do the swap.
2315 This does not apply to the mips16, which uses variant
2316 frags for different purposes. */
2317 || (! mips_opts.mips16
2318 && prev_insn_frag_type == rs_machine_dependent)
2319 /* If the branch reads the condition codes, we don't
2320 even try to swap, because in the sequence
2325 we can not swap, and I don't feel like handling that
2327 || (! mips_opts.mips16
2328 && (pinfo & INSN_READ_COND_CODE)
2329 && ! cop_interlocks)
2330 /* We can not swap with an instruction that requires a
2331 delay slot, because the target of the branch might
2332 interfere with that instruction. */
2333 || (! mips_opts.mips16
2335 /* Itbl support may require additional care here. */
2336 & (INSN_LOAD_COPROC_DELAY
2337 | INSN_COPROC_MOVE_DELAY
2338 | INSN_WRITE_COND_CODE))
2339 && ! cop_interlocks)
2340 || (! (hilo_interlocks
2341 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2345 || (! mips_opts.mips16
2346 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2347 && ! gpr_interlocks)
2348 || (! mips_opts.mips16
2349 /* Itbl support may require additional care here. */
2350 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2351 && ! cop_mem_interlocks)
2352 /* We can not swap with a branch instruction. */
2354 & (INSN_UNCOND_BRANCH_DELAY
2355 | INSN_COND_BRANCH_DELAY
2356 | INSN_COND_BRANCH_LIKELY))
2357 /* We do not swap with a trap instruction, since it
2358 complicates trap handlers to have the trap
2359 instruction be in a delay slot. */
2360 || (prev_pinfo & INSN_TRAP)
2361 /* If the branch reads a register that the previous
2362 instruction sets, we can not swap. */
2363 || (! mips_opts.mips16
2364 && (prev_pinfo & INSN_WRITE_GPR_T)
2365 && insn_uses_reg (ip,
2366 ((prev_insn.insn_opcode >> OP_SH_RT)
2369 || (! mips_opts.mips16
2370 && (prev_pinfo & INSN_WRITE_GPR_D)
2371 && insn_uses_reg (ip,
2372 ((prev_insn.insn_opcode >> OP_SH_RD)
2375 || (mips_opts.mips16
2376 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2377 && insn_uses_reg (ip,
2378 ((prev_insn.insn_opcode
2380 & MIPS16OP_MASK_RX),
2382 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2383 && insn_uses_reg (ip,
2384 ((prev_insn.insn_opcode
2386 & MIPS16OP_MASK_RY),
2388 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2389 && insn_uses_reg (ip,
2390 ((prev_insn.insn_opcode
2392 & MIPS16OP_MASK_RZ),
2394 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2395 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2396 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2397 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2398 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2399 && insn_uses_reg (ip,
2400 MIPS16OP_EXTRACT_REG32R (prev_insn.
2403 /* If the branch writes a register that the previous
2404 instruction sets, we can not swap (we know that
2405 branches write only to RD or to $31). */
2406 || (! mips_opts.mips16
2407 && (prev_pinfo & INSN_WRITE_GPR_T)
2408 && (((pinfo & INSN_WRITE_GPR_D)
2409 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2410 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2411 || ((pinfo & INSN_WRITE_GPR_31)
2412 && (((prev_insn.insn_opcode >> OP_SH_RT)
2415 || (! mips_opts.mips16
2416 && (prev_pinfo & INSN_WRITE_GPR_D)
2417 && (((pinfo & INSN_WRITE_GPR_D)
2418 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2419 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2420 || ((pinfo & INSN_WRITE_GPR_31)
2421 && (((prev_insn.insn_opcode >> OP_SH_RD)
2424 || (mips_opts.mips16
2425 && (pinfo & MIPS16_INSN_WRITE_31)
2426 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2427 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2428 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2430 /* If the branch writes a register that the previous
2431 instruction reads, we can not swap (we know that
2432 branches only write to RD or to $31). */
2433 || (! mips_opts.mips16
2434 && (pinfo & INSN_WRITE_GPR_D)
2435 && insn_uses_reg (&prev_insn,
2436 ((ip->insn_opcode >> OP_SH_RD)
2439 || (! mips_opts.mips16
2440 && (pinfo & INSN_WRITE_GPR_31)
2441 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2442 || (mips_opts.mips16
2443 && (pinfo & MIPS16_INSN_WRITE_31)
2444 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2445 /* If we are generating embedded PIC code, the branch
2446 might be expanded into a sequence which uses $at, so
2447 we can't swap with an instruction which reads it. */
2448 || (mips_pic == EMBEDDED_PIC
2449 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2450 /* If the previous previous instruction has a load
2451 delay, and sets a register that the branch reads, we
2453 || (! mips_opts.mips16
2454 /* Itbl support may require additional care here. */
2455 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2456 && ! cop_interlocks)
2457 || ((prev_prev_insn.insn_mo->pinfo
2458 & INSN_LOAD_MEMORY_DELAY)
2459 && ! gpr_interlocks))
2460 && insn_uses_reg (ip,
2461 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2464 /* If one instruction sets a condition code and the
2465 other one uses a condition code, we can not swap. */
2466 || ((pinfo & INSN_READ_COND_CODE)
2467 && (prev_pinfo & INSN_WRITE_COND_CODE))
2468 || ((pinfo & INSN_WRITE_COND_CODE)
2469 && (prev_pinfo & INSN_READ_COND_CODE))
2470 /* If the previous instruction uses the PC, we can not
2472 || (mips_opts.mips16
2473 && (prev_pinfo & MIPS16_INSN_READ_PC))
2474 /* If the previous instruction was extended, we can not
2476 || (mips_opts.mips16 && prev_insn_extended)
2477 /* If the previous instruction had a fixup in mips16
2478 mode, we can not swap. This normally means that the
2479 previous instruction was a 4 byte branch anyhow. */
2480 || (mips_opts.mips16 && prev_insn_fixp[0])
2481 /* If the previous instruction is a sync, sync.l, or
2482 sync.p, we can not swap. */
2483 || (prev_pinfo & INSN_SYNC))
2485 /* We could do even better for unconditional branches to
2486 portions of this object file; we could pick up the
2487 instruction at the destination, put it in the delay
2488 slot, and bump the destination address. */
2490 /* Update the previous insn information. */
2491 prev_prev_insn = *ip;
2492 prev_insn.insn_mo = &dummy_opcode;
2496 /* It looks like we can actually do the swap. */
2497 if (! mips_opts.mips16)
2502 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2503 if (!relaxed_branch)
2505 /* If this is not a relaxed branch, then just
2506 swap the instructions. */
2507 memcpy (temp, prev_f, 4);
2508 memcpy (prev_f, f, 4);
2509 memcpy (f, temp, 4);
2513 /* If this is a relaxed branch, then we move the
2514 instruction to be placed in the delay slot to
2515 the current frag, shrinking the fixed part of
2516 the originating frag. If the branch occupies
2517 the tail of the latter, we move it backwards,
2518 into the space freed by the moved instruction. */
2520 memcpy (f, prev_f, 4);
2521 prev_insn_frag->fr_fix -= 4;
2522 if (prev_insn_frag->fr_type == rs_machine_dependent)
2523 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2526 if (prev_insn_fixp[0])
2528 prev_insn_fixp[0]->fx_frag = frag_now;
2529 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2531 if (prev_insn_fixp[1])
2533 prev_insn_fixp[1]->fx_frag = frag_now;
2534 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2536 if (prev_insn_fixp[2])
2538 prev_insn_fixp[2]->fx_frag = frag_now;
2539 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2541 if (prev_insn_fixp[0] && HAVE_NEWABI
2542 && prev_insn_frag != frag_now
2543 && (prev_insn_fixp[0]->fx_r_type
2544 == BFD_RELOC_MIPS_GOT_DISP
2545 || (prev_insn_fixp[0]->fx_r_type
2546 == BFD_RELOC_MIPS_CALL16)))
2548 /* To avoid confusion in tc_gen_reloc, we must
2549 ensure that this does not become a variant
2551 force_new_frag = TRUE;
2554 if (!relaxed_branch)
2558 fixp[0]->fx_frag = prev_insn_frag;
2559 fixp[0]->fx_where = prev_insn_where;
2563 fixp[1]->fx_frag = prev_insn_frag;
2564 fixp[1]->fx_where = prev_insn_where;
2568 fixp[2]->fx_frag = prev_insn_frag;
2569 fixp[2]->fx_where = prev_insn_where;
2572 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2575 fixp[0]->fx_where -= 4;
2577 fixp[1]->fx_where -= 4;
2579 fixp[2]->fx_where -= 4;
2587 assert (prev_insn_fixp[0] == NULL);
2588 assert (prev_insn_fixp[1] == NULL);
2589 assert (prev_insn_fixp[2] == NULL);
2590 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2591 memcpy (temp, prev_f, 2);
2592 memcpy (prev_f, f, 2);
2593 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2595 assert (*reloc_type == BFD_RELOC_UNUSED);
2596 memcpy (f, temp, 2);
2600 memcpy (f, f + 2, 2);
2601 memcpy (f + 2, temp, 2);
2605 fixp[0]->fx_frag = prev_insn_frag;
2606 fixp[0]->fx_where = prev_insn_where;
2610 fixp[1]->fx_frag = prev_insn_frag;
2611 fixp[1]->fx_where = prev_insn_where;
2615 fixp[2]->fx_frag = prev_insn_frag;
2616 fixp[2]->fx_where = prev_insn_where;
2620 /* Update the previous insn information; leave prev_insn
2622 prev_prev_insn = *ip;
2624 prev_insn_is_delay_slot = 1;
2626 /* If that was an unconditional branch, forget the previous
2627 insn information. */
2628 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2630 prev_prev_insn.insn_mo = &dummy_opcode;
2631 prev_insn.insn_mo = &dummy_opcode;
2634 prev_insn_fixp[0] = NULL;
2635 prev_insn_fixp[1] = NULL;
2636 prev_insn_fixp[2] = NULL;
2637 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2638 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2639 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2640 prev_insn_extended = 0;
2642 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2644 /* We don't yet optimize a branch likely. What we should do
2645 is look at the target, copy the instruction found there
2646 into the delay slot, and increment the branch to jump to
2647 the next instruction. */
2649 /* Update the previous insn information. */
2650 prev_prev_insn = *ip;
2651 prev_insn.insn_mo = &dummy_opcode;
2652 prev_insn_fixp[0] = NULL;
2653 prev_insn_fixp[1] = NULL;
2654 prev_insn_fixp[2] = NULL;
2655 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2656 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2657 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2658 prev_insn_extended = 0;
2662 /* Update the previous insn information. */
2664 prev_prev_insn.insn_mo = &dummy_opcode;
2666 prev_prev_insn = prev_insn;
2669 /* Any time we see a branch, we always fill the delay slot
2670 immediately; since this insn is not a branch, we know it
2671 is not in a delay slot. */
2672 prev_insn_is_delay_slot = 0;
2674 prev_insn_fixp[0] = fixp[0];
2675 prev_insn_fixp[1] = fixp[1];
2676 prev_insn_fixp[2] = fixp[2];
2677 prev_insn_reloc_type[0] = reloc_type[0];
2678 prev_insn_reloc_type[1] = reloc_type[1];
2679 prev_insn_reloc_type[2] = reloc_type[2];
2680 if (mips_opts.mips16)
2681 prev_insn_extended = (ip->use_extend
2682 || *reloc_type > BFD_RELOC_UNUSED);
2685 prev_prev_insn_unreordered = prev_insn_unreordered;
2686 prev_insn_unreordered = 0;
2687 prev_insn_frag = frag_now;
2688 prev_insn_where = f - frag_now->fr_literal;
2689 prev_insn_valid = 1;
2691 else if (mips_relax.sequence != 2)
2693 /* We need to record a bit of information even when we are not
2694 reordering, in order to determine the base address for mips16
2695 PC relative relocs. */
2696 prev_prev_insn = prev_insn;
2698 prev_insn_reloc_type[0] = reloc_type[0];
2699 prev_insn_reloc_type[1] = reloc_type[1];
2700 prev_insn_reloc_type[2] = reloc_type[2];
2701 prev_prev_insn_unreordered = prev_insn_unreordered;
2702 prev_insn_unreordered = 1;
2705 /* We just output an insn, so the next one doesn't have a label. */
2706 mips_clear_insn_labels ();
2709 /* This function forgets that there was any previous instruction or
2710 label. If PRESERVE is non-zero, it remembers enough information to
2711 know whether nops are needed before a noreorder section. */
2714 mips_no_prev_insn (int preserve)
2718 prev_insn.insn_mo = &dummy_opcode;
2719 prev_prev_insn.insn_mo = &dummy_opcode;
2720 prev_nop_frag = NULL;
2721 prev_nop_frag_holds = 0;
2722 prev_nop_frag_required = 0;
2723 prev_nop_frag_since = 0;
2725 prev_insn_valid = 0;
2726 prev_insn_is_delay_slot = 0;
2727 prev_insn_unreordered = 0;
2728 prev_insn_extended = 0;
2729 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2730 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2731 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2732 prev_prev_insn_unreordered = 0;
2733 mips_clear_insn_labels ();
2736 /* This function must be called whenever we turn on noreorder or emit
2737 something other than instructions. It inserts any NOPS which might
2738 be needed by the previous instruction, and clears the information
2739 kept for the previous instructions. The INSNS parameter is true if
2740 instructions are to follow. */
2743 mips_emit_delays (bfd_boolean insns)
2745 if (! mips_opts.noreorder)
2750 if ((! mips_opts.mips16
2751 && ((prev_insn.insn_mo->pinfo
2752 & (INSN_LOAD_COPROC_DELAY
2753 | INSN_COPROC_MOVE_DELAY
2754 | INSN_WRITE_COND_CODE))
2755 && ! cop_interlocks))
2756 || (! hilo_interlocks
2757 && (prev_insn.insn_mo->pinfo
2760 || (! mips_opts.mips16
2761 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2762 && ! gpr_interlocks)
2763 || (! mips_opts.mips16
2764 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2765 && ! cop_mem_interlocks))
2767 /* Itbl support may require additional care here. */
2769 if ((! mips_opts.mips16
2770 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2771 && ! cop_interlocks))
2772 || (! hilo_interlocks
2773 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2774 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2777 if (prev_insn_unreordered)
2780 else if ((! mips_opts.mips16
2781 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2782 && ! cop_interlocks))
2783 || (! hilo_interlocks
2784 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2785 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2787 /* Itbl support may require additional care here. */
2788 if (! prev_prev_insn_unreordered)
2792 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2795 const char *pn = prev_insn.insn_mo->name;
2796 if (strncmp(pn, "macc", 4) == 0
2797 || strncmp(pn, "dmacc", 5) == 0
2798 || strncmp(pn, "dmult", 5) == 0)
2802 if (nops < min_nops)
2808 struct insn_label_list *l;
2812 /* Record the frag which holds the nop instructions, so
2813 that we can remove them if we don't need them. */
2814 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2815 prev_nop_frag = frag_now;
2816 prev_nop_frag_holds = nops;
2817 prev_nop_frag_required = 0;
2818 prev_nop_frag_since = 0;
2821 for (; nops > 0; --nops)
2826 /* Move on to a new frag, so that it is safe to simply
2827 decrease the size of prev_nop_frag. */
2828 frag_wane (frag_now);
2832 for (l = insn_labels; l != NULL; l = l->next)
2836 assert (S_GET_SEGMENT (l->label) == now_seg);
2837 symbol_set_frag (l->label, frag_now);
2838 val = (valueT) frag_now_fix ();
2839 /* mips16 text labels are stored as odd. */
2840 if (mips_opts.mips16)
2842 S_SET_VALUE (l->label, val);
2847 /* Mark instruction labels in mips16 mode. */
2849 mips16_mark_labels ();
2851 mips_no_prev_insn (insns);
2854 /* Build an instruction created by a macro expansion. This is passed
2855 a pointer to the count of instructions created so far, an
2856 expression, the name of the instruction to build, an operand format
2857 string, and corresponding arguments. */
2860 macro_build (char *place ATTRIBUTE_UNUSED, int *counter,
2861 expressionS *ep, const char *name, const char *fmt, ...)
2863 struct mips_cl_insn insn;
2864 bfd_reloc_code_real_type r[3];
2867 va_start (args, fmt);
2869 if (mips_relax.sequence != 2)
2873 /* If the macro is about to expand into a second instruction,
2874 and it is in a delay slot, print a warning. */
2875 if (mips_opts.noreorder
2876 && (prev_prev_insn.insn_mo->pinfo
2877 & (INSN_UNCOND_BRANCH_DELAY
2878 | INSN_COND_BRANCH_DELAY
2879 | INSN_COND_BRANCH_LIKELY)) != 0)
2880 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2882 /* If the macro is about to expand into a second instruction,
2883 print a warning if needed. We need to pass ip as a parameter
2884 to generate a better warning message here... */
2885 else if (mips_opts.warn_about_macros)
2886 as_warn (_("Macro instruction expanded into multiple instructions"));
2891 if (mips_opts.mips16)
2893 mips16_macro_build (counter, ep, name, fmt, args);
2898 r[0] = BFD_RELOC_UNUSED;
2899 r[1] = BFD_RELOC_UNUSED;
2900 r[2] = BFD_RELOC_UNUSED;
2901 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2902 assert (insn.insn_mo);
2903 assert (strcmp (name, insn.insn_mo->name) == 0);
2905 /* Search until we get a match for NAME. */
2908 /* It is assumed here that macros will never generate
2909 MDMX or MIPS-3D instructions. */
2910 if (strcmp (fmt, insn.insn_mo->args) == 0
2911 && insn.insn_mo->pinfo != INSN_MACRO
2912 && OPCODE_IS_MEMBER (insn.insn_mo,
2914 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2916 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2920 assert (insn.insn_mo->name);
2921 assert (strcmp (name, insn.insn_mo->name) == 0);
2924 insn.insn_opcode = insn.insn_mo->match;
2942 insn.insn_opcode |= (va_arg (args, int)
2943 & OP_MASK_SHAMT) << OP_SH_SHAMT;
2948 /* Note that in the macro case, these arguments are already
2949 in MSB form. (When handling the instruction in the
2950 non-macro case, these arguments are sizes from which
2951 MSB values must be calculated.) */
2952 insn.insn_opcode |= (va_arg (args, int)
2953 & OP_MASK_INSMSB) << OP_SH_INSMSB;
2959 /* Note that in the macro case, these arguments are already
2960 in MSBD form. (When handling the instruction in the
2961 non-macro case, these arguments are sizes from which
2962 MSBD values must be calculated.) */
2963 insn.insn_opcode |= (va_arg (args, int)
2964 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
2975 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2979 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2984 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2990 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2995 int tmp = va_arg (args, int);
2997 insn.insn_opcode |= tmp << OP_SH_RT;
2998 insn.insn_opcode |= tmp << OP_SH_RD;
3004 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3011 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3015 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3019 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3023 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3027 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3034 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3040 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3041 assert (*r == BFD_RELOC_GPREL16
3042 || *r == BFD_RELOC_MIPS_LITERAL
3043 || *r == BFD_RELOC_MIPS_HIGHER
3044 || *r == BFD_RELOC_HI16_S
3045 || *r == BFD_RELOC_LO16
3046 || *r == BFD_RELOC_MIPS_GOT16
3047 || *r == BFD_RELOC_MIPS_CALL16
3048 || *r == BFD_RELOC_MIPS_GOT_DISP
3049 || *r == BFD_RELOC_MIPS_GOT_PAGE
3050 || *r == BFD_RELOC_MIPS_GOT_OFST
3051 || *r == BFD_RELOC_MIPS_GOT_LO16
3052 || *r == BFD_RELOC_MIPS_CALL_LO16
3053 || (ep->X_op == O_subtract
3054 && *r == BFD_RELOC_PCREL_LO16));
3058 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3060 && (ep->X_op == O_constant
3061 || (ep->X_op == O_symbol
3062 && (*r == BFD_RELOC_MIPS_HIGHEST
3063 || *r == BFD_RELOC_HI16_S
3064 || *r == BFD_RELOC_HI16
3065 || *r == BFD_RELOC_GPREL16
3066 || *r == BFD_RELOC_MIPS_GOT_HI16
3067 || *r == BFD_RELOC_MIPS_CALL_HI16))
3068 || (ep->X_op == O_subtract
3069 && *r == BFD_RELOC_PCREL_HI16_S)));
3073 assert (ep != NULL);
3075 * This allows macro() to pass an immediate expression for
3076 * creating short branches without creating a symbol.
3077 * Note that the expression still might come from the assembly
3078 * input, in which case the value is not checked for range nor
3079 * is a relocation entry generated (yuck).
3081 if (ep->X_op == O_constant)
3083 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3087 *r = BFD_RELOC_16_PCREL_S2;
3091 assert (ep != NULL);
3092 *r = BFD_RELOC_MIPS_JMP;
3096 insn.insn_opcode |= va_arg (args, unsigned long);
3105 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3107 append_insn (&insn, ep, r);
3111 mips16_macro_build (int *counter ATTRIBUTE_UNUSED,
3112 expressionS *ep, const char *name, const char *fmt,
3115 struct mips_cl_insn insn;
3116 bfd_reloc_code_real_type r[3]
3117 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3119 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3120 assert (insn.insn_mo);
3121 assert (strcmp (name, insn.insn_mo->name) == 0);
3123 while (strcmp (fmt, insn.insn_mo->args) != 0
3124 || insn.insn_mo->pinfo == INSN_MACRO)
3127 assert (insn.insn_mo->name);
3128 assert (strcmp (name, insn.insn_mo->name) == 0);
3131 insn.insn_opcode = insn.insn_mo->match;
3132 insn.use_extend = FALSE;
3151 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3156 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3160 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3164 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3174 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3181 regno = va_arg (args, int);
3182 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3183 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3204 assert (ep != NULL);
3206 if (ep->X_op != O_constant)
3207 *r = (int) BFD_RELOC_UNUSED + c;
3210 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3211 FALSE, &insn.insn_opcode, &insn.use_extend,
3214 *r = BFD_RELOC_UNUSED;
3220 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3227 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3229 append_insn (&insn, ep, r);
3233 * Generate a "jalr" instruction with a relocation hint to the called
3234 * function. This occurs in NewABI PIC code.
3237 macro_build_jalr (int icnt, expressionS *ep)
3246 macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3248 fix_new_exp (frag_now, f - frag_now->fr_literal,
3249 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3253 * Generate a "lui" instruction.
3256 macro_build_lui (char *place ATTRIBUTE_UNUSED, int *counter,
3257 expressionS *ep, int regnum)
3259 expressionS high_expr;
3260 struct mips_cl_insn insn;
3261 bfd_reloc_code_real_type r[3]
3262 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3263 const char *name = "lui";
3264 const char *fmt = "t,u";
3266 assert (! mips_opts.mips16);
3269 if (mips_relax.sequence != 2)
3271 /* If the macro is about to expand into a second instruction,
3272 print a warning if needed. We need to pass ip as a parameter
3273 to generate a better warning message here... */
3274 if (mips_opts.warn_about_macros && *counter == 1)
3275 as_warn (_("Macro instruction expanded into multiple instructions"));
3279 if (high_expr.X_op == O_constant)
3281 /* we can compute the instruction now without a relocation entry */
3282 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3284 *r = BFD_RELOC_UNUSED;
3288 assert (ep->X_op == O_symbol);
3289 /* _gp_disp is a special case, used from s_cpload. */
3290 assert (mips_pic == NO_PIC
3292 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3293 *r = BFD_RELOC_HI16_S;
3296 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3297 assert (insn.insn_mo);
3298 assert (strcmp (name, insn.insn_mo->name) == 0);
3299 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3301 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3302 if (*r == BFD_RELOC_UNUSED)
3304 insn.insn_opcode |= high_expr.X_add_number;
3305 append_insn (&insn, NULL, r);
3308 append_insn (&insn, &high_expr, r);
3311 /* Generate a sequence of instructions to do a load or store from a constant
3312 offset off of a base register (breg) into/from a target register (treg),
3313 using AT if necessary. */
3315 macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
3316 const char *op, int treg, int breg, int dbl)
3318 assert (ep->X_op == O_constant);
3320 /* Sign-extending 32-bit constants makes their handling easier. */
3321 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3322 == ~((bfd_vma) 0x7fffffff)))
3324 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3325 as_bad (_("constant too large"));
3327 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3331 /* Right now, this routine can only handle signed 32-bit constants. */
3332 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3333 as_warn (_("operand overflow"));
3335 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3337 /* Signed 16-bit offset will fit in the op. Easy! */
3338 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3343 /* 32-bit offset, need multiple instructions and AT, like:
3344 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3345 addu $tempreg,$tempreg,$breg
3346 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3347 to handle the complete offset. */
3348 macro_build_lui (place, counter, ep, AT);
3351 macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
3355 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3359 as_warn (_("Macro used $at after \".set noat\""));
3364 * Generates code to set the $at register to true (one)
3365 * if reg is less than the immediate expression.
3368 set_at (int *counter, int reg, int unsignedp)
3370 if (imm_expr.X_op == O_constant
3371 && imm_expr.X_add_number >= -0x8000
3372 && imm_expr.X_add_number < 0x8000)
3373 macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
3374 "t,r,j", AT, reg, BFD_RELOC_LO16);
3377 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3378 macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
3379 "d,v,t", AT, reg, AT);
3384 normalize_constant_expr (expressionS *ex)
3386 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3387 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3391 /* Warn if an expression is not a constant. */
3394 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3396 if (ex->X_op == O_big)
3397 as_bad (_("unsupported large constant"));
3398 else if (ex->X_op != O_constant)
3399 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3401 normalize_constant_expr (ex);
3404 /* Count the leading zeroes by performing a binary chop. This is a
3405 bulky bit of source, but performance is a LOT better for the
3406 majority of values than a simple loop to count the bits:
3407 for (lcnt = 0; (lcnt < 32); lcnt++)
3408 if ((v) & (1 << (31 - lcnt)))
3410 However it is not code size friendly, and the gain will drop a bit
3411 on certain cached systems.
3413 #define COUNT_TOP_ZEROES(v) \
3414 (((v) & ~0xffff) == 0 \
3415 ? ((v) & ~0xff) == 0 \
3416 ? ((v) & ~0xf) == 0 \
3417 ? ((v) & ~0x3) == 0 \
3418 ? ((v) & ~0x1) == 0 \
3423 : ((v) & ~0x7) == 0 \
3426 : ((v) & ~0x3f) == 0 \
3427 ? ((v) & ~0x1f) == 0 \
3430 : ((v) & ~0x7f) == 0 \
3433 : ((v) & ~0xfff) == 0 \
3434 ? ((v) & ~0x3ff) == 0 \
3435 ? ((v) & ~0x1ff) == 0 \
3438 : ((v) & ~0x7ff) == 0 \
3441 : ((v) & ~0x3fff) == 0 \
3442 ? ((v) & ~0x1fff) == 0 \
3445 : ((v) & ~0x7fff) == 0 \
3448 : ((v) & ~0xffffff) == 0 \
3449 ? ((v) & ~0xfffff) == 0 \
3450 ? ((v) & ~0x3ffff) == 0 \
3451 ? ((v) & ~0x1ffff) == 0 \
3454 : ((v) & ~0x7ffff) == 0 \
3457 : ((v) & ~0x3fffff) == 0 \
3458 ? ((v) & ~0x1fffff) == 0 \
3461 : ((v) & ~0x7fffff) == 0 \
3464 : ((v) & ~0xfffffff) == 0 \
3465 ? ((v) & ~0x3ffffff) == 0 \
3466 ? ((v) & ~0x1ffffff) == 0 \
3469 : ((v) & ~0x7ffffff) == 0 \
3472 : ((v) & ~0x3fffffff) == 0 \
3473 ? ((v) & ~0x1fffffff) == 0 \
3476 : ((v) & ~0x7fffffff) == 0 \
3481 * This routine generates the least number of instructions necessary to load
3482 * an absolute expression value into a register.
3485 load_register (int *counter, int reg, expressionS *ep, int dbl)
3488 expressionS hi32, lo32;
3490 if (ep->X_op != O_big)
3492 assert (ep->X_op == O_constant);
3494 /* Sign-extending 32-bit constants makes their handling easier. */
3495 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3496 == ~((bfd_vma) 0x7fffffff)))
3498 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3499 as_bad (_("constant too large"));
3501 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3505 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3507 /* We can handle 16 bit signed values with an addiu to
3508 $zero. No need to ever use daddiu here, since $zero and
3509 the result are always correct in 32 bit mode. */
3510 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3514 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3516 /* We can handle 16 bit unsigned values with an ori to
3518 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
3522 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3524 /* 32 bit values require an lui. */
3525 macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3526 if ((ep->X_add_number & 0xffff) != 0)
3527 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
3533 /* The value is larger than 32 bits. */
3535 if (HAVE_32BIT_GPRS)
3537 as_bad (_("Number (0x%lx) larger than 32 bits"),
3538 (unsigned long) ep->X_add_number);
3539 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3544 if (ep->X_op != O_big)
3547 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3548 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3549 hi32.X_add_number &= 0xffffffff;
3551 lo32.X_add_number &= 0xffffffff;
3555 assert (ep->X_add_number > 2);
3556 if (ep->X_add_number == 3)
3557 generic_bignum[3] = 0;
3558 else if (ep->X_add_number > 4)
3559 as_bad (_("Number larger than 64 bits"));
3560 lo32.X_op = O_constant;
3561 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3562 hi32.X_op = O_constant;
3563 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3566 if (hi32.X_add_number == 0)
3571 unsigned long hi, lo;
3573 if (hi32.X_add_number == (offsetT) 0xffffffff)
3575 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3577 macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
3581 if (lo32.X_add_number & 0x80000000)
3583 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3585 if (lo32.X_add_number & 0xffff)
3586 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
3592 /* Check for 16bit shifted constant. We know that hi32 is
3593 non-zero, so start the mask on the first bit of the hi32
3598 unsigned long himask, lomask;
3602 himask = 0xffff >> (32 - shift);
3603 lomask = (0xffff << shift) & 0xffffffff;
3607 himask = 0xffff << (shift - 32);
3610 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3611 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3615 tmp.X_op = O_constant;
3617 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3618 | (lo32.X_add_number >> shift));
3620 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3621 macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
3623 macro_build (NULL, counter, NULL,
3624 (shift >= 32) ? "dsll32" : "dsll",
3626 (shift >= 32) ? shift - 32 : shift);
3631 while (shift <= (64 - 16));
3633 /* Find the bit number of the lowest one bit, and store the
3634 shifted value in hi/lo. */
3635 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3636 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3640 while ((lo & 1) == 0)
3645 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3651 while ((hi & 1) == 0)
3660 /* Optimize if the shifted value is a (power of 2) - 1. */
3661 if ((hi == 0 && ((lo + 1) & lo) == 0)
3662 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3664 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3669 /* This instruction will set the register to be all
3671 tmp.X_op = O_constant;
3672 tmp.X_add_number = (offsetT) -1;
3673 macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
3678 macro_build (NULL, counter, NULL,
3679 (bit >= 32) ? "dsll32" : "dsll",
3681 (bit >= 32) ? bit - 32 : bit);
3683 macro_build (NULL, counter, NULL,
3684 (shift >= 32) ? "dsrl32" : "dsrl",
3686 (shift >= 32) ? shift - 32 : shift);
3691 /* Sign extend hi32 before calling load_register, because we can
3692 generally get better code when we load a sign extended value. */
3693 if ((hi32.X_add_number & 0x80000000) != 0)
3694 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3695 load_register (counter, reg, &hi32, 0);
3698 if ((lo32.X_add_number & 0xffff0000) == 0)
3702 macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
3710 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3712 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3714 macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
3720 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
3724 mid16.X_add_number >>= 16;
3725 macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
3727 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3730 if ((lo32.X_add_number & 0xffff) != 0)
3731 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3735 /* Load an address into a register. */
3738 load_address (int *counter, int reg, expressionS *ep, int *used_at)
3742 if (ep->X_op != O_constant
3743 && ep->X_op != O_symbol)
3745 as_bad (_("expression too complex"));
3746 ep->X_op = O_constant;
3749 if (ep->X_op == O_constant)
3751 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3755 if (mips_pic == NO_PIC)
3757 /* If this is a reference to a GP relative symbol, we want
3758 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3760 lui $reg,<sym> (BFD_RELOC_HI16_S)
3761 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3762 If we have an addend, we always use the latter form.
3764 With 64bit address space and a usable $at we want
3765 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3766 lui $at,<sym> (BFD_RELOC_HI16_S)
3767 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3768 daddiu $at,<sym> (BFD_RELOC_LO16)
3772 If $at is already in use, we use a path which is suboptimal
3773 on superscalar processors.
3774 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3775 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3777 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3779 daddiu $reg,<sym> (BFD_RELOC_LO16)
3781 if (HAVE_64BIT_ADDRESSES)
3783 /* We don't do GP optimization for now because RELAX_ENCODE can't
3784 hold the data for such large chunks. */
3786 if (*used_at == 0 && ! mips_opts.noat)
3788 macro_build (p, counter, ep, "lui", "t,u",
3789 reg, BFD_RELOC_MIPS_HIGHEST);
3790 macro_build (p, counter, ep, "lui", "t,u",
3791 AT, BFD_RELOC_HI16_S);
3792 macro_build (p, counter, ep, "daddiu", "t,r,j",
3793 reg, reg, BFD_RELOC_MIPS_HIGHER);
3794 macro_build (p, counter, ep, "daddiu", "t,r,j",
3795 AT, AT, BFD_RELOC_LO16);
3796 macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
3797 macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
3802 macro_build (p, counter, ep, "lui", "t,u",
3803 reg, BFD_RELOC_MIPS_HIGHEST);
3804 macro_build (p, counter, ep, "daddiu", "t,r,j",
3805 reg, reg, BFD_RELOC_MIPS_HIGHER);
3806 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3807 macro_build (p, counter, ep, "daddiu", "t,r,j",
3808 reg, reg, BFD_RELOC_HI16_S);
3809 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3810 macro_build (p, counter, ep, "daddiu", "t,r,j",
3811 reg, reg, BFD_RELOC_LO16);
3816 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3817 && ! nopic_need_relax (ep->X_add_symbol, 1))
3819 relax_start (ep->X_add_symbol);
3820 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3821 mips_gp_register, BFD_RELOC_GPREL16);
3824 macro_build_lui (p, counter, ep, reg);
3825 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3827 if (mips_relax.sequence)
3831 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3835 /* If this is a reference to an external symbol, we want
3836 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3838 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3840 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3841 If there is a constant, it must be added in after.
3843 If we have NewABI, we want
3844 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3845 unless we're referencing a global symbol with a non-zero
3846 offset, in which case cst must be added separately. */
3849 if (ep->X_add_number)
3851 ex.X_add_number = ep->X_add_number;
3852 ep->X_add_number = 0;
3853 relax_start (ep->X_add_symbol);
3854 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
3855 reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3856 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3857 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3858 ex.X_op = O_constant;
3859 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3860 reg, reg, BFD_RELOC_LO16);
3861 ep->X_add_number = ex.X_add_number;
3864 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3865 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3866 if (mips_relax.sequence)
3871 ex.X_add_number = ep->X_add_number;
3872 ep->X_add_number = 0;
3873 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3874 BFD_RELOC_MIPS_GOT16,
3876 macro_build (NULL, counter, NULL, "nop", "");
3877 relax_start (ep->X_add_symbol);
3879 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3883 if (ex.X_add_number != 0)
3885 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3886 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3887 ex.X_op = O_constant;
3888 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3889 reg, reg, BFD_RELOC_LO16);
3893 else if (mips_pic == SVR4_PIC)
3897 /* This is the large GOT case. If this is a reference to an
3898 external symbol, we want
3899 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3901 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3903 Otherwise, for a reference to a local symbol in old ABI, we want
3904 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3906 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3907 If there is a constant, it must be added in after.
3909 In the NewABI, for local symbols, with or without offsets, we want:
3910 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3911 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3915 ex.X_add_number = ep->X_add_number;
3916 ep->X_add_number = 0;
3917 relax_start (ep->X_add_symbol);
3918 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3919 BFD_RELOC_MIPS_GOT_HI16);
3920 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3921 reg, mips_gp_register);
3922 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3923 BFD_RELOC_MIPS_GOT_LO16, reg);
3924 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3925 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3926 else if (ex.X_add_number)
3928 ex.X_op = O_constant;
3929 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3930 reg, reg, BFD_RELOC_LO16);
3933 ep->X_add_number = ex.X_add_number;
3935 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3936 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3937 macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3938 reg, BFD_RELOC_MIPS_GOT_OFST);
3943 ex.X_add_number = ep->X_add_number;
3944 ep->X_add_number = 0;
3945 relax_start (ep->X_add_symbol);
3946 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3947 BFD_RELOC_MIPS_GOT_HI16);
3948 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3949 reg, mips_gp_register);
3950 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3951 BFD_RELOC_MIPS_GOT_LO16, reg);
3953 if (reg_needs_delay (mips_gp_register))
3955 /* We need a nop before loading from $gp. This special
3956 check is required because the lui which starts the main
3957 instruction stream does not refer to $gp, and so will not
3958 insert the nop which may be required. */
3959 macro_build (p, counter, NULL, "nop", "");
3961 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3962 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3963 macro_build (p, counter, NULL, "nop", "");
3964 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3968 if (ex.X_add_number != 0)
3970 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3971 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3972 ex.X_op = O_constant;
3973 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3974 reg, reg, BFD_RELOC_LO16);
3978 else if (mips_pic == EMBEDDED_PIC)
3981 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3983 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3984 mips_gp_register, BFD_RELOC_GPREL16);
3990 /* Move the contents of register SOURCE into register DEST. */
3993 move_register (int *counter, int dest, int source)
3995 macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
3996 "d,v,t", dest, source, 0);
3999 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4000 LOCAL is the sum of a symbol and a 16-bit displacement. The two
4003 Global symbol Local sybmol
4004 ------------- ------------
4005 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4007 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4009 load_got_offset emits the first instruction and add_got_offset
4010 emits the second. */
4013 load_got_offset (int *counter, int dest, expressionS *local)
4018 global.X_add_number = 0;
4020 relax_start (local->X_add_symbol);
4021 macro_build (NULL, counter, &global, ADDRESS_LOAD_INSN, "t,o(b)",
4022 dest, BFD_RELOC_MIPS_GOT16, mips_gp_register);
4024 macro_build (NULL, counter, local, ADDRESS_LOAD_INSN, "t,o(b)",
4025 dest, BFD_RELOC_MIPS_GOT16, mips_gp_register);
4030 add_got_offset (int *counter, int dest, expressionS *local)
4034 global.X_op = O_constant;
4035 global.X_op_symbol = NULL;
4036 global.X_add_symbol = NULL;
4037 global.X_add_number = local->X_add_number;
4039 relax_start (local->X_add_symbol);
4040 macro_build (NULL, counter, &global, ADDRESS_ADDI_INSN, "t,r,j",
4041 dest, dest, BFD_RELOC_LO16);
4043 macro_build (NULL, counter, local, ADDRESS_ADDI_INSN, "t,r,j",
4044 dest, dest, BFD_RELOC_LO16);
4050 * This routine implements the seemingly endless macro or synthesized
4051 * instructions and addressing modes in the mips assembly language. Many
4052 * of these macros are simple and are similar to each other. These could
4053 * probably be handled by some kind of table or grammar approach instead of
4054 * this verbose method. Others are not simple macros but are more like
4055 * optimizing code generation.
4056 * One interesting optimization is when several store macros appear
4057 * consecutively that would load AT with the upper half of the same address.
4058 * The ensuing load upper instructions are ommited. This implies some kind
4059 * of global optimization. We currently only optimize within a single macro.
4060 * For many of the load and store macros if the address is specified as a
4061 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4062 * first load register 'at' with zero and use it as the base register. The
4063 * mips assembler simply uses register $zero. Just one tiny optimization
4067 macro (struct mips_cl_insn *ip)
4069 register int treg, sreg, dreg, breg;
4086 bfd_reloc_code_real_type r;
4087 int hold_mips_optimize;
4089 assert (! mips_opts.mips16);
4091 treg = (ip->insn_opcode >> 16) & 0x1f;
4092 dreg = (ip->insn_opcode >> 11) & 0x1f;
4093 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4094 mask = ip->insn_mo->mask;
4096 expr1.X_op = O_constant;
4097 expr1.X_op_symbol = NULL;
4098 expr1.X_add_symbol = NULL;
4099 expr1.X_add_number = 1;
4111 mips_emit_delays (TRUE);
4112 ++mips_opts.noreorder;
4113 mips_any_noreorder = 1;
4115 expr1.X_add_number = 8;
4116 macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4118 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4120 move_register (&icnt, dreg, sreg);
4121 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
4124 --mips_opts.noreorder;
4145 if (imm_expr.X_op == O_constant
4146 && imm_expr.X_add_number >= -0x8000
4147 && imm_expr.X_add_number < 0x8000)
4149 macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4153 load_register (&icnt, AT, &imm_expr, dbl);
4154 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4173 if (imm_expr.X_op == O_constant
4174 && imm_expr.X_add_number >= 0
4175 && imm_expr.X_add_number < 0x10000)
4177 if (mask != M_NOR_I)
4178 macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
4182 macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
4184 macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
4189 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4190 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4207 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4209 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
4212 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4213 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4221 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4227 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4231 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4232 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4239 /* check for > max integer */
4240 maxnum = 0x7fffffff;
4241 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4248 if (imm_expr.X_op == O_constant
4249 && imm_expr.X_add_number >= maxnum
4250 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4253 /* result is always false */
4255 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4257 macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
4260 if (imm_expr.X_op != O_constant)
4261 as_bad (_("Unsupported large constant"));
4262 ++imm_expr.X_add_number;
4266 if (mask == M_BGEL_I)
4268 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4270 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4274 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4276 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4280 maxnum = 0x7fffffff;
4281 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4288 maxnum = - maxnum - 1;
4289 if (imm_expr.X_op == O_constant
4290 && imm_expr.X_add_number <= maxnum
4291 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4294 /* result is always true */
4295 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4296 macro_build (NULL, &icnt, &offset_expr, "b", "p");
4299 set_at (&icnt, sreg, 0);
4300 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4311 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4315 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4316 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4325 && imm_expr.X_op == O_constant
4326 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4328 if (imm_expr.X_op != O_constant)
4329 as_bad (_("Unsupported large constant"));
4330 ++imm_expr.X_add_number;
4334 if (mask == M_BGEUL_I)
4336 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4338 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4340 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4344 set_at (&icnt, sreg, 1);
4345 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4354 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4360 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4364 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4365 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4374 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4380 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4381 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4390 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4396 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4400 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4401 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4408 maxnum = 0x7fffffff;
4409 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4416 if (imm_expr.X_op == O_constant
4417 && imm_expr.X_add_number >= maxnum
4418 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4420 if (imm_expr.X_op != O_constant)
4421 as_bad (_("Unsupported large constant"));
4422 ++imm_expr.X_add_number;
4426 if (mask == M_BLTL_I)
4428 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4430 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4434 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4436 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4440 set_at (&icnt, sreg, 0);
4441 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4450 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4456 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4457 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4466 && imm_expr.X_op == O_constant
4467 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4469 if (imm_expr.X_op != O_constant)
4470 as_bad (_("Unsupported large constant"));
4471 ++imm_expr.X_add_number;
4475 if (mask == M_BLTUL_I)
4477 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4479 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4481 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4485 set_at (&icnt, sreg, 1);
4486 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4495 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4501 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4505 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4506 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4517 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4521 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4522 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4531 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4533 as_bad (_("Unsupported large constant"));
4538 pos = (unsigned long) imm_expr.X_add_number;
4539 size = (unsigned long) imm2_expr.X_add_number;
4544 as_bad (_("Improper position (%lu)"), pos);
4547 if (size == 0 || size > 64
4548 || (pos + size - 1) > 63)
4550 as_bad (_("Improper extract size (%lu, position %lu)"),
4555 if (size <= 32 && pos < 32)
4560 else if (size <= 32)
4570 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4571 fmt, treg, sreg, pos, size - 1);
4580 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4582 as_bad (_("Unsupported large constant"));
4587 pos = (unsigned long) imm_expr.X_add_number;
4588 size = (unsigned long) imm2_expr.X_add_number;
4593 as_bad (_("Improper position (%lu)"), pos);
4596 if (size == 0 || size > 64
4597 || (pos + size - 1) > 63)
4599 as_bad (_("Improper insert size (%lu, position %lu)"),
4604 if (pos < 32 && (pos + size - 1) < 32)
4619 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4620 fmt, treg, sreg, pos, pos + size - 1);
4636 as_warn (_("Divide by zero."));
4638 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4640 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4644 mips_emit_delays (TRUE);
4645 ++mips_opts.noreorder;
4646 mips_any_noreorder = 1;
4649 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4650 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4655 expr1.X_add_number = 8;
4656 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4657 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4659 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4661 expr1.X_add_number = -1;
4662 macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
4663 AT, 0, BFD_RELOC_LO16);
4664 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4665 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4668 expr1.X_add_number = 1;
4669 macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4671 macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
4675 expr1.X_add_number = 0x80000000;
4676 macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
4681 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
4682 /* We want to close the noreorder block as soon as possible, so
4683 that later insns are available for delay slot filling. */
4684 --mips_opts.noreorder;
4688 expr1.X_add_number = 8;
4689 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4690 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4692 /* We want to close the noreorder block as soon as possible, so
4693 that later insns are available for delay slot filling. */
4694 --mips_opts.noreorder;
4696 macro_build (NULL, &icnt, NULL, "break", "c", 6);
4698 macro_build (NULL, &icnt, NULL, s, "d", dreg);
4737 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4739 as_warn (_("Divide by zero."));
4741 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4743 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4746 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4748 if (strcmp (s2, "mflo") == 0)
4749 move_register (&icnt, dreg, sreg);
4751 move_register (&icnt, dreg, 0);
4754 if (imm_expr.X_op == O_constant
4755 && imm_expr.X_add_number == -1
4756 && s[strlen (s) - 1] != 'u')
4758 if (strcmp (s2, "mflo") == 0)
4760 macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
4764 move_register (&icnt, dreg, 0);
4768 load_register (&icnt, AT, &imm_expr, dbl);
4769 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
4770 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4789 mips_emit_delays (TRUE);
4790 ++mips_opts.noreorder;
4791 mips_any_noreorder = 1;
4794 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4795 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4796 /* We want to close the noreorder block as soon as possible, so
4797 that later insns are available for delay slot filling. */
4798 --mips_opts.noreorder;
4802 expr1.X_add_number = 8;
4803 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4804 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4806 /* We want to close the noreorder block as soon as possible, so
4807 that later insns are available for delay slot filling. */
4808 --mips_opts.noreorder;
4809 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4811 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4823 /* Load the address of a symbol into a register. If breg is not
4824 zero, we then add a base register to it. */
4826 if (dbl && HAVE_32BIT_GPRS)
4827 as_warn (_("dla used to load 32-bit register"));
4829 if (! dbl && HAVE_64BIT_OBJECTS)
4830 as_warn (_("la used to load 64-bit address"));
4832 if (offset_expr.X_op == O_constant
4833 && offset_expr.X_add_number >= -0x8000
4834 && offset_expr.X_add_number < 0x8000)
4836 macro_build (NULL, &icnt, &offset_expr,
4837 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4838 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4853 /* When generating embedded PIC code, we permit expressions of
4856 la $treg,foo-bar($breg)
4857 where bar is an address in the current section. These are used
4858 when getting the addresses of functions. We don't permit
4859 X_add_number to be non-zero, because if the symbol is
4860 external the relaxing code needs to know that any addend is
4861 purely the offset to X_op_symbol. */
4862 if (mips_pic == EMBEDDED_PIC
4863 && offset_expr.X_op == O_subtract
4864 && (symbol_constant_p (offset_expr.X_op_symbol)
4865 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4866 : (symbol_equated_p (offset_expr.X_op_symbol)
4868 (symbol_get_value_expression (offset_expr.X_op_symbol)
4871 && (offset_expr.X_add_number == 0
4872 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4878 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4879 BFD_RELOC_PCREL_HI16_S);
4883 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4884 BFD_RELOC_PCREL_HI16_S);
4885 macro_build (NULL, &icnt, NULL,
4886 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4887 "d,v,t", tempreg, tempreg, breg);
4889 macro_build (NULL, &icnt, &offset_expr,
4890 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4891 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4897 if (offset_expr.X_op != O_symbol
4898 && offset_expr.X_op != O_constant)
4900 as_bad (_("expression too complex"));
4901 offset_expr.X_op = O_constant;
4904 if (offset_expr.X_op == O_constant)
4905 load_register (&icnt, tempreg, &offset_expr,
4906 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4907 ? (dbl || HAVE_64BIT_ADDRESSES)
4908 : HAVE_64BIT_ADDRESSES));
4909 else if (mips_pic == NO_PIC)
4911 /* If this is a reference to a GP relative symbol, we want
4912 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4914 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4915 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4916 If we have a constant, we need two instructions anyhow,
4917 so we may as well always use the latter form.
4919 With 64bit address space and a usable $at we want
4920 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4921 lui $at,<sym> (BFD_RELOC_HI16_S)
4922 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4923 daddiu $at,<sym> (BFD_RELOC_LO16)
4925 daddu $tempreg,$tempreg,$at
4927 If $at is already in use, we use a path which is suboptimal
4928 on superscalar processors.
4929 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4930 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4932 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4934 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4937 if (HAVE_64BIT_ADDRESSES)
4939 /* We don't do GP optimization for now because RELAX_ENCODE can't
4940 hold the data for such large chunks. */
4942 if (used_at == 0 && ! mips_opts.noat)
4944 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4945 tempreg, BFD_RELOC_MIPS_HIGHEST);
4946 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4947 AT, BFD_RELOC_HI16_S);
4948 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4949 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4950 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4951 AT, AT, BFD_RELOC_LO16);
4952 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
4953 tempreg, tempreg, 0);
4954 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
4955 tempreg, tempreg, AT);
4960 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4961 tempreg, BFD_RELOC_MIPS_HIGHEST);
4962 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4963 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4964 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4965 tempreg, tempreg, 16);
4966 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4967 tempreg, tempreg, BFD_RELOC_HI16_S);
4968 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4969 tempreg, tempreg, 16);
4970 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4971 tempreg, tempreg, BFD_RELOC_LO16);
4976 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4977 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4979 relax_start (offset_expr.X_add_symbol);
4980 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4981 "t,r,j", tempreg, mips_gp_register,
4985 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4986 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4987 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4988 if (mips_relax.sequence)
4992 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4994 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4996 /* If this is a reference to an external symbol, and there
4997 is no constant, we want
4998 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4999 or for lca or if tempreg is PIC_CALL_REG
5000 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5001 For a local symbol, we want
5002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5004 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5006 If we have a small constant, and this is a reference to
5007 an external symbol, we want
5008 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5010 addiu $tempreg,$tempreg,<constant>
5011 For a local symbol, we want the same instruction
5012 sequence, but we output a BFD_RELOC_LO16 reloc on the
5015 If we have a large constant, and this is a reference to
5016 an external symbol, we want
5017 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5018 lui $at,<hiconstant>
5019 addiu $at,$at,<loconstant>
5020 addu $tempreg,$tempreg,$at
5021 For a local symbol, we want the same instruction
5022 sequence, but we output a BFD_RELOC_LO16 reloc on the
5026 if (offset_expr.X_add_number == 0)
5030 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5031 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5033 relax_start (offset_expr.X_add_symbol);
5034 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5035 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
5038 /* We're going to put in an addu instruction using
5039 tempreg, so we may as well insert the nop right
5041 macro_build (NULL, &icnt, NULL, "nop", "");
5044 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5045 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT16,
5047 macro_build (p, &icnt, NULL, "nop", "");
5048 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5049 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5051 /* FIXME: If breg == 0, and the next instruction uses
5052 $tempreg, then if this variant case is used an extra
5053 nop will be generated. */
5055 else if (offset_expr.X_add_number >= -0x8000
5056 && offset_expr.X_add_number < 0x8000)
5058 load_got_offset (&icnt, tempreg, &offset_expr);
5059 macro_build (NULL, &icnt, NULL, "nop", "");
5060 add_got_offset (&icnt, tempreg, &offset_expr);
5066 expr1.X_add_number = offset_expr.X_add_number;
5067 offset_expr.X_add_number =
5068 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5069 load_got_offset (&icnt, tempreg, &offset_expr);
5070 /* If we are going to add in a base register, and the
5071 target register and the base register are the same,
5072 then we are using AT as a temporary register. Since
5073 we want to load the constant into AT, we add our
5074 current AT (from the global offset table) and the
5075 register into the register now, and pretend we were
5076 not using a base register. */
5081 macro_build (NULL, &icnt, NULL, "nop", "");
5082 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5089 /* Set mips_optimize around the lui instruction to avoid
5090 inserting an unnecessary nop after the lw. */
5091 hold_mips_optimize = mips_optimize;
5093 macro_build_lui (NULL, &icnt, &expr1, AT);
5094 mips_optimize = hold_mips_optimize;
5096 add_got_offset (&icnt, AT, &offset_expr);
5097 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5098 tempreg, tempreg, AT);
5102 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5107 /* If this is a reference to an external, and there is no
5108 constant, or local symbol (*), with or without a
5110 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5111 or for lca or if tempreg is PIC_CALL_REG
5112 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5114 If we have a small constant, and this is a reference to
5115 an external symbol, we want
5116 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5117 addiu $tempreg,$tempreg,<constant>
5119 If we have a large constant, and this is a reference to
5120 an external symbol, we want
5121 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5122 lui $at,<hiconstant>
5123 addiu $at,$at,<loconstant>
5124 addu $tempreg,$tempreg,$at
5126 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5127 local symbols, even though it introduces an additional
5130 if (offset_expr.X_add_number)
5132 expr1.X_add_number = offset_expr.X_add_number;
5133 offset_expr.X_add_number = 0;
5135 relax_start (offset_expr.X_add_symbol);
5136 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5137 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5140 if (expr1.X_add_number >= -0x8000
5141 && expr1.X_add_number < 0x8000)
5143 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5144 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5146 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5150 /* If we are going to add in a base register, and the
5151 target register and the base register are the same,
5152 then we are using AT as a temporary register. Since
5153 we want to load the constant into AT, we add our
5154 current AT (from the global offset table) and the
5155 register into the register now, and pretend we were
5156 not using a base register. */
5161 assert (tempreg == AT);
5162 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN,
5163 "d,v,t", treg, AT, breg);
5168 macro_build_lui (NULL, &icnt, &expr1, AT);
5169 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5170 "t,r,j", AT, AT, BFD_RELOC_LO16);
5171 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5177 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5180 offset_expr.X_add_number = expr1.X_add_number;
5182 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5183 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5187 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5188 treg, tempreg, breg);
5194 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5196 relax_start (offset_expr.X_add_symbol);
5197 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5198 "t,o(b)", tempreg, BFD_RELOC_MIPS_CALL16,
5201 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5202 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5208 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5209 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5213 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5217 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5218 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5219 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5221 /* This is the large GOT case. If this is a reference to an
5222 external symbol, and there is no constant, we want
5223 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5224 addu $tempreg,$tempreg,$gp
5225 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5226 or for lca or if tempreg is PIC_CALL_REG
5227 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5228 addu $tempreg,$tempreg,$gp
5229 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5230 For a local symbol, we want
5231 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5233 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5235 If we have a small constant, and this is a reference to
5236 an external symbol, we want
5237 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5238 addu $tempreg,$tempreg,$gp
5239 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5241 addiu $tempreg,$tempreg,<constant>
5242 For a local symbol, we want
5243 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5245 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5247 If we have a large constant, and this is a reference to
5248 an external symbol, we want
5249 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5250 addu $tempreg,$tempreg,$gp
5251 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5252 lui $at,<hiconstant>
5253 addiu $at,$at,<loconstant>
5254 addu $tempreg,$tempreg,$at
5255 For a local symbol, we want
5256 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5257 lui $at,<hiconstant>
5258 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5259 addu $tempreg,$tempreg,$at
5262 expr1.X_add_number = offset_expr.X_add_number;
5263 offset_expr.X_add_number = 0;
5264 relax_start (offset_expr.X_add_symbol);
5265 if (reg_needs_delay (mips_gp_register))
5269 if (expr1.X_add_number == 0 && breg == 0
5270 && (call || tempreg == PIC_CALL_REG))
5272 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5273 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5275 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5276 tempreg, lui_reloc_type);
5277 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5278 tempreg, tempreg, mips_gp_register);
5279 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5280 tempreg, lw_reloc_type, tempreg);
5281 if (expr1.X_add_number == 0)
5289 /* We're going to put in an addu instruction using
5290 tempreg, so we may as well insert the nop right
5292 macro_build (NULL, &icnt, NULL, "nop", "");
5296 else if (expr1.X_add_number >= -0x8000
5297 && expr1.X_add_number < 0x8000)
5299 macro_build (NULL, &icnt, NULL, "nop", "");
5300 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5301 tempreg, tempreg, BFD_RELOC_LO16);
5307 /* If we are going to add in a base register, and the
5308 target register and the base register are the same,
5309 then we are using AT as a temporary register. Since
5310 we want to load the constant into AT, we add our
5311 current AT (from the global offset table) and the
5312 register into the register now, and pretend we were
5313 not using a base register. */
5321 assert (tempreg == AT);
5322 macro_build (NULL, &icnt, NULL, "nop", "");
5323 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5329 /* Set mips_optimize around the lui instruction to avoid
5330 inserting an unnecessary nop after the lw. */
5331 hold_mips_optimize = mips_optimize;
5333 macro_build_lui (NULL, &icnt, &expr1, AT);
5334 mips_optimize = hold_mips_optimize;
5336 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5337 AT, AT, BFD_RELOC_LO16);
5338 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5343 offset_expr.X_add_number =
5344 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5349 /* This is needed because this instruction uses $gp, but
5350 the first instruction on the main stream does not. */
5351 macro_build (p, &icnt, NULL, "nop", "");
5354 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5355 tempreg, local_reloc_type, mips_gp_register);
5356 if (expr1.X_add_number >= -0x8000
5357 && expr1.X_add_number < 0x8000)
5359 macro_build (p, &icnt, NULL, "nop", "");
5360 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5361 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5362 /* FIXME: If add_number is 0, and there was no base
5363 register, the external symbol case ended with a load,
5364 so if the symbol turns out to not be external, and
5365 the next instruction uses tempreg, an unnecessary nop
5366 will be inserted. */
5372 /* We must add in the base register now, as in the
5373 external symbol case. */
5374 assert (tempreg == AT);
5375 macro_build (p, &icnt, NULL, "nop", "");
5376 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5379 /* We set breg to 0 because we have arranged to add
5380 it in in both cases. */
5384 macro_build_lui (p, &icnt, &expr1, AT);
5385 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5386 AT, AT, BFD_RELOC_LO16);
5387 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5388 tempreg, tempreg, AT);
5392 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5395 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5396 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5399 /* This is the large GOT case. If this is a reference to an
5400 external symbol, and there is no constant, we want
5401 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5402 add $tempreg,$tempreg,$gp
5403 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5404 or for lca or if tempreg is PIC_CALL_REG
5405 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5406 add $tempreg,$tempreg,$gp
5407 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5409 If we have a small constant, and this is a reference to
5410 an external symbol, we want
5411 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5412 add $tempreg,$tempreg,$gp
5413 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5414 addi $tempreg,$tempreg,<constant>
5416 If we have a large constant, and this is a reference to
5417 an external symbol, we want
5418 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5419 addu $tempreg,$tempreg,$gp
5420 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5421 lui $at,<hiconstant>
5422 addi $at,$at,<loconstant>
5423 add $tempreg,$tempreg,$at
5425 If we have NewABI, and we know it's a local symbol, we want
5426 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5427 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5428 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5430 relax_start (offset_expr.X_add_symbol);
5432 expr1.X_add_number = offset_expr.X_add_number;
5433 offset_expr.X_add_number = 0;
5435 if (expr1.X_add_number == 0 && breg == 0
5436 && (call || tempreg == PIC_CALL_REG))
5438 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5439 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5441 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5442 tempreg, lui_reloc_type);
5443 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5444 tempreg, tempreg, mips_gp_register);
5445 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5446 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5448 if (expr1.X_add_number == 0)
5450 else if (expr1.X_add_number >= -0x8000
5451 && expr1.X_add_number < 0x8000)
5453 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5454 tempreg, tempreg, BFD_RELOC_LO16);
5456 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5460 /* If we are going to add in a base register, and the
5461 target register and the base register are the same,
5462 then we are using AT as a temporary register. Since
5463 we want to load the constant into AT, we add our
5464 current AT (from the global offset table) and the
5465 register into the register now, and pretend we were
5466 not using a base register. */
5471 assert (tempreg == AT);
5472 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5478 /* Set mips_optimize around the lui instruction to avoid
5479 inserting an unnecessary nop after the lw. */
5480 macro_build_lui (NULL, &icnt, &expr1, AT);
5481 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5482 "t,r,j", AT, AT, BFD_RELOC_LO16);
5483 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5489 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5492 offset_expr.X_add_number = expr1.X_add_number;
5493 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5494 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5495 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5496 tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
5499 macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5500 treg, tempreg, breg);
5506 else if (mips_pic == EMBEDDED_PIC)
5509 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5511 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5512 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5521 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5522 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5524 s = ADDRESS_ADD_INSN;
5526 macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
5535 /* The j instruction may not be used in PIC code, since it
5536 requires an absolute address. We convert it to a b
5538 if (mips_pic == NO_PIC)
5539 macro_build (NULL, &icnt, &offset_expr, "j", "a");
5541 macro_build (NULL, &icnt, &offset_expr, "b", "p");
5544 /* The jal instructions must be handled as macros because when
5545 generating PIC code they expand to multi-instruction
5546 sequences. Normally they are simple instructions. */
5551 if (mips_pic == NO_PIC
5552 || mips_pic == EMBEDDED_PIC)
5553 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5554 else if (mips_pic == SVR4_PIC)
5556 if (sreg != PIC_CALL_REG)
5557 as_warn (_("MIPS PIC call to register other than $25"));
5559 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5562 if (mips_cprestore_offset < 0)
5563 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5566 if (! mips_frame_reg_valid)
5568 as_warn (_("No .frame pseudo-op used in PIC code"));
5569 /* Quiet this warning. */
5570 mips_frame_reg_valid = 1;
5572 if (! mips_cprestore_valid)
5574 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5575 /* Quiet this warning. */
5576 mips_cprestore_valid = 1;
5578 expr1.X_add_number = mips_cprestore_offset;
5579 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5583 HAVE_64BIT_ADDRESSES);
5593 if (mips_pic == NO_PIC)
5594 macro_build (NULL, &icnt, &offset_expr, "jal", "a");
5595 else if (mips_pic == SVR4_PIC)
5599 /* If this is a reference to an external symbol, and we are
5600 using a small GOT, we want
5601 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5605 lw $gp,cprestore($sp)
5606 The cprestore value is set using the .cprestore
5607 pseudo-op. If we are using a big GOT, we want
5608 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5610 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5614 lw $gp,cprestore($sp)
5615 If the symbol is not external, we want
5616 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5618 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5621 lw $gp,cprestore($sp)
5623 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5624 sequences above, minus nops, unless the symbol is local,
5625 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5631 relax_start (offset_expr.X_add_symbol);
5632 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5633 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5636 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5637 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5643 relax_start (offset_expr.X_add_symbol);
5644 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5645 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5646 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5647 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5648 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5649 "t,o(b)", PIC_CALL_REG,
5650 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5652 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5653 "t,o(b)", PIC_CALL_REG,
5654 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5655 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5656 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5657 BFD_RELOC_MIPS_GOT_OFST);
5661 macro_build_jalr (icnt, &offset_expr);
5665 relax_start (offset_expr.X_add_symbol);
5668 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5669 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5671 macro_build (NULL, &icnt, NULL, "nop", "");
5678 if (reg_needs_delay (mips_gp_register))
5682 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5683 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5684 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5685 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5686 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5687 "t,o(b)", PIC_CALL_REG,
5688 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5689 macro_build (NULL, &icnt, NULL, "nop", "");
5693 macro_build (p, &icnt, NULL, "nop", "");
5697 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5698 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5700 macro_build (p, &icnt, NULL, "nop", "");
5701 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5702 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5705 macro_build_jalr (icnt, &offset_expr);
5707 if (mips_cprestore_offset < 0)
5708 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5711 if (! mips_frame_reg_valid)
5713 as_warn (_("No .frame pseudo-op used in PIC code"));
5714 /* Quiet this warning. */
5715 mips_frame_reg_valid = 1;
5717 if (! mips_cprestore_valid)
5719 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5720 /* Quiet this warning. */
5721 mips_cprestore_valid = 1;
5723 if (mips_opts.noreorder)
5724 macro_build (NULL, &icnt, NULL, "nop", "");
5725 expr1.X_add_number = mips_cprestore_offset;
5726 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5730 HAVE_64BIT_ADDRESSES);
5734 else if (mips_pic == EMBEDDED_PIC)
5736 macro_build (NULL, &icnt, &offset_expr, "bal", "p");
5737 /* The linker may expand the call to a longer sequence which
5738 uses $at, so we must break rather than return. */
5763 /* Itbl support may require additional care here. */
5768 /* Itbl support may require additional care here. */
5773 /* Itbl support may require additional care here. */
5778 /* Itbl support may require additional care here. */
5790 if (mips_opts.arch == CPU_R4650)
5792 as_bad (_("opcode not supported on this processor"));
5796 /* Itbl support may require additional care here. */
5801 /* Itbl support may require additional care here. */
5806 /* Itbl support may require additional care here. */
5826 if (breg == treg || coproc || lr)
5848 /* Itbl support may require additional care here. */
5853 /* Itbl support may require additional care here. */
5858 /* Itbl support may require additional care here. */
5863 /* Itbl support may require additional care here. */
5879 if (mips_opts.arch == CPU_R4650)
5881 as_bad (_("opcode not supported on this processor"));
5886 /* Itbl support may require additional care here. */
5890 /* Itbl support may require additional care here. */
5895 /* Itbl support may require additional care here. */
5907 /* Itbl support may require additional care here. */
5908 if (mask == M_LWC1_AB
5909 || mask == M_SWC1_AB
5910 || mask == M_LDC1_AB
5911 || mask == M_SDC1_AB
5920 /* Sign-extending 32-bit constants makes their handling easier.
5921 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5923 if ((! HAVE_64BIT_ADDRESSES
5924 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5925 && (offset_expr.X_op == O_constant)
5926 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5927 == ~((bfd_vma) 0x7fffffff)))
5929 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5930 as_bad (_("constant too large"));
5932 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5933 ^ 0x80000000) - 0x80000000);
5936 /* For embedded PIC, we allow loads where the offset is calculated
5937 by subtracting a symbol in the current segment from an unknown
5938 symbol, relative to a base register, e.g.:
5939 <op> $treg, <sym>-<localsym>($breg)
5940 This is used by the compiler for switch statements. */
5941 if (mips_pic == EMBEDDED_PIC
5942 && offset_expr.X_op == O_subtract
5943 && (symbol_constant_p (offset_expr.X_op_symbol)
5944 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5945 : (symbol_equated_p (offset_expr.X_op_symbol)
5947 (symbol_get_value_expression (offset_expr.X_op_symbol)
5951 && (offset_expr.X_add_number == 0
5952 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5954 /* For this case, we output the instructions:
5955 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5956 addiu $tempreg,$tempreg,$breg
5957 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5958 If the relocation would fit entirely in 16 bits, it would be
5960 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5961 instead, but that seems quite difficult. */
5962 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
5963 BFD_RELOC_PCREL_HI16_S);
5964 macro_build (NULL, &icnt, NULL,
5965 ((bfd_arch_bits_per_address (stdoutput) == 32
5966 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5967 ? "addu" : "daddu"),
5968 "d,v,t", tempreg, tempreg, breg);
5969 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
5970 BFD_RELOC_PCREL_LO16, tempreg);
5976 if (offset_expr.X_op != O_constant
5977 && offset_expr.X_op != O_symbol)
5979 as_bad (_("expression too complex"));
5980 offset_expr.X_op = O_constant;
5983 /* A constant expression in PIC code can be handled just as it
5984 is in non PIC code. */
5985 if (mips_pic == NO_PIC
5986 || offset_expr.X_op == O_constant)
5990 /* If this is a reference to a GP relative symbol, and there
5991 is no base register, we want
5992 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5993 Otherwise, if there is no base register, we want
5994 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5995 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5996 If we have a constant, we need two instructions anyhow,
5997 so we always use the latter form.
5999 If we have a base register, and this is a reference to a
6000 GP relative symbol, we want
6001 addu $tempreg,$breg,$gp
6002 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6004 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6005 addu $tempreg,$tempreg,$breg
6006 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6007 With a constant we always use the latter case.
6009 With 64bit address space and no base register and $at usable,
6011 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6012 lui $at,<sym> (BFD_RELOC_HI16_S)
6013 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6016 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6017 If we have a base register, we want
6018 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6019 lui $at,<sym> (BFD_RELOC_HI16_S)
6020 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6024 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6026 Without $at we can't generate the optimal path for superscalar
6027 processors here since this would require two temporary registers.
6028 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6029 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6031 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6033 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6034 If we have a base register, we want
6035 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6036 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6038 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6040 daddu $tempreg,$tempreg,$breg
6041 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6043 If we have 64-bit addresses, as an optimization, for
6044 addresses which are 32-bit constants (e.g. kseg0/kseg1
6045 addresses) we fall back to the 32-bit address generation
6046 mechanism since it is more efficient. Note that due to
6047 the signed offset used by memory operations, the 32-bit
6048 range is shifted down by 32768 here. This code should
6049 probably attempt to generate 64-bit constants more
6050 efficiently in general.
6052 As an extension for architectures with 64-bit registers,
6053 we don't truncate 64-bit addresses given as literal
6054 constants down to 32 bits, to support existing practice
6055 in the mips64 Linux (the kernel), that compiles source
6056 files with -mabi=64, assembling them as o32 or n32 (with
6057 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6058 the whole kernel is loaded into a memory region that is
6059 addressable with sign-extended 32-bit addresses, it is
6060 wasteful to compute the upper 32 bits of every
6061 non-literal address, that takes more space and time.
6062 Some day this should probably be implemented as an
6063 assembler option, such that the kernel doesn't have to
6064 use such ugly hacks, even though it will still have to
6065 end up converting the binary to ELF32 for a number of
6066 platforms whose boot loaders don't support ELF64
6068 if ((HAVE_64BIT_ADDRESSES
6069 && ! (offset_expr.X_op == O_constant
6070 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6072 && offset_expr.X_op == O_constant
6073 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6077 /* We don't do GP optimization for now because RELAX_ENCODE can't
6078 hold the data for such large chunks. */
6080 if (used_at == 0 && ! mips_opts.noat)
6082 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6083 tempreg, BFD_RELOC_MIPS_HIGHEST);
6084 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6085 AT, BFD_RELOC_HI16_S);
6086 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6087 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
6089 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6091 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
6092 tempreg, tempreg, 0);
6093 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6094 tempreg, tempreg, AT);
6095 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6096 BFD_RELOC_LO16, tempreg);
6101 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
6102 tempreg, BFD_RELOC_MIPS_HIGHEST);
6103 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6104 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
6105 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
6106 tempreg, tempreg, 16);
6107 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
6108 tempreg, tempreg, BFD_RELOC_HI16_S);
6109 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
6110 tempreg, tempreg, 16);
6112 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
6113 tempreg, tempreg, breg);
6114 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6115 BFD_RELOC_LO16, tempreg);
6121 if (offset_expr.X_op == O_constant
6122 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6123 as_bad (_("load/store address overflow (max 32 bits)"));
6127 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6128 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6132 relax_start (offset_expr.X_add_symbol);
6133 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6134 BFD_RELOC_GPREL16, mips_gp_register);
6138 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6139 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6140 BFD_RELOC_LO16, tempreg);
6141 if (mips_relax.sequence)
6146 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6147 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6151 relax_start (offset_expr.X_add_symbol);
6152 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6153 tempreg, breg, mips_gp_register);
6154 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6155 BFD_RELOC_GPREL16, tempreg);
6158 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6159 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6160 tempreg, tempreg, breg);
6161 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6162 BFD_RELOC_LO16, tempreg);
6163 if (mips_relax.sequence)
6167 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6170 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6172 /* If this is a reference to an external symbol, we want
6173 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6175 <op> $treg,0($tempreg)
6177 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6179 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6180 <op> $treg,0($tempreg)
6183 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6184 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6186 If there is a base register, we add it to $tempreg before
6187 the <op>. If there is a constant, we stick it in the
6188 <op> instruction. We don't handle constants larger than
6189 16 bits, because we have no way to load the upper 16 bits
6190 (actually, we could handle them for the subset of cases
6191 in which we are not using $at). */
6192 assert (offset_expr.X_op == O_symbol);
6195 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6196 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6199 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6200 tempreg, tempreg, breg);
6201 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6202 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6209 expr1.X_add_number = offset_expr.X_add_number;
6210 offset_expr.X_add_number = 0;
6211 if (expr1.X_add_number < -0x8000
6212 || expr1.X_add_number >= 0x8000)
6213 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6214 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6215 tempreg, lw_reloc_type, mips_gp_register);
6216 macro_build (NULL, &icnt, NULL, "nop", "");
6217 relax_start (offset_expr.X_add_symbol);
6219 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6220 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
6223 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6224 tempreg, tempreg, breg);
6225 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6228 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6233 /* If this is a reference to an external symbol, we want
6234 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6235 addu $tempreg,$tempreg,$gp
6236 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6237 <op> $treg,0($tempreg)
6239 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6241 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6242 <op> $treg,0($tempreg)
6243 If there is a base register, we add it to $tempreg before
6244 the <op>. If there is a constant, we stick it in the
6245 <op> instruction. We don't handle constants larger than
6246 16 bits, because we have no way to load the upper 16 bits
6247 (actually, we could handle them for the subset of cases
6248 in which we are not using $at). */
6249 assert (offset_expr.X_op == O_symbol);
6250 expr1.X_add_number = offset_expr.X_add_number;
6251 offset_expr.X_add_number = 0;
6252 if (expr1.X_add_number < -0x8000
6253 || expr1.X_add_number >= 0x8000)
6254 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6255 if (reg_needs_delay (mips_gp_register))
6259 relax_start (offset_expr.X_add_symbol);
6260 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6261 BFD_RELOC_MIPS_GOT_HI16);
6262 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6263 tempreg, tempreg, mips_gp_register);
6264 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6265 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6268 macro_build (p, &icnt, NULL, "nop", "");
6269 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6270 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6271 macro_build (p, &icnt, NULL, "nop", "");
6272 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6273 tempreg, tempreg, BFD_RELOC_LO16);
6277 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6278 tempreg, tempreg, breg);
6279 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6282 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6285 int bregsz = breg != 0 ? 4 : 0;
6287 /* If this is a reference to an external symbol, we want
6288 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6289 add $tempreg,$tempreg,$gp
6290 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6291 <op> $treg,<ofst>($tempreg)
6292 Otherwise, for local symbols, we want:
6293 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6294 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6295 assert (offset_expr.X_op == O_symbol);
6296 expr1.X_add_number = offset_expr.X_add_number;
6297 offset_expr.X_add_number = 0;
6298 if (expr1.X_add_number < -0x8000
6299 || expr1.X_add_number >= 0x8000)
6300 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6301 relax_start (offset_expr.X_add_symbol);
6302 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6303 BFD_RELOC_MIPS_GOT_HI16);
6304 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6305 tempreg, tempreg, mips_gp_register);
6306 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6307 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6309 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6310 tempreg, tempreg, breg);
6311 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6315 offset_expr.X_add_number = expr1.X_add_number;
6316 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6317 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6319 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6320 tempreg, tempreg, breg);
6321 macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
6322 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6325 else if (mips_pic == EMBEDDED_PIC)
6327 /* If there is no base register, we want
6328 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6329 If there is a base register, we want
6330 addu $tempreg,$breg,$gp
6331 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6333 assert (offset_expr.X_op == O_symbol);
6336 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6337 BFD_RELOC_GPREL16, mips_gp_register);
6342 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6343 tempreg, breg, mips_gp_register);
6344 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6345 BFD_RELOC_GPREL16, tempreg);
6358 load_register (&icnt, treg, &imm_expr, 0);
6362 load_register (&icnt, treg, &imm_expr, 1);
6366 if (imm_expr.X_op == O_constant)
6368 load_register (&icnt, AT, &imm_expr, 0);
6369 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6374 assert (offset_expr.X_op == O_symbol
6375 && strcmp (segment_name (S_GET_SEGMENT
6376 (offset_expr.X_add_symbol)),
6378 && offset_expr.X_add_number == 0);
6379 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
6380 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6385 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6386 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6387 order 32 bits of the value and the low order 32 bits are either
6388 zero or in OFFSET_EXPR. */
6389 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6391 if (HAVE_64BIT_GPRS)
6392 load_register (&icnt, treg, &imm_expr, 1);
6397 if (target_big_endian)
6409 load_register (&icnt, hreg, &imm_expr, 0);
6412 if (offset_expr.X_op == O_absent)
6413 move_register (&icnt, lreg, 0);
6416 assert (offset_expr.X_op == O_constant);
6417 load_register (&icnt, lreg, &offset_expr, 0);
6424 /* We know that sym is in the .rdata section. First we get the
6425 upper 16 bits of the address. */
6426 if (mips_pic == NO_PIC)
6428 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6430 else if (mips_pic == SVR4_PIC)
6432 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6433 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6435 else if (mips_pic == EMBEDDED_PIC)
6437 /* For embedded PIC we pick up the entire address off $gp in
6438 a single instruction. */
6439 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6440 AT, mips_gp_register, BFD_RELOC_GPREL16);
6441 offset_expr.X_op = O_constant;
6442 offset_expr.X_add_number = 0;
6447 /* Now we load the register(s). */
6448 if (HAVE_64BIT_GPRS)
6449 macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
6450 BFD_RELOC_LO16, AT);
6453 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
6454 BFD_RELOC_LO16, AT);
6457 /* FIXME: How in the world do we deal with the possible
6459 offset_expr.X_add_number += 4;
6460 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6461 treg + 1, BFD_RELOC_LO16, AT);
6467 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6468 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6469 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6470 the value and the low order 32 bits are either zero or in
6472 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6474 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6475 if (HAVE_64BIT_FPRS)
6477 assert (HAVE_64BIT_GPRS);
6478 macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
6482 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
6483 if (offset_expr.X_op == O_absent)
6484 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
6487 assert (offset_expr.X_op == O_constant);
6488 load_register (&icnt, AT, &offset_expr, 0);
6489 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6495 assert (offset_expr.X_op == O_symbol
6496 && offset_expr.X_add_number == 0);
6497 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6498 if (strcmp (s, ".lit8") == 0)
6500 if (mips_opts.isa != ISA_MIPS1)
6502 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6503 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6506 breg = mips_gp_register;
6507 r = BFD_RELOC_MIPS_LITERAL;
6512 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6513 if (mips_pic == SVR4_PIC)
6514 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6515 "t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
6519 /* FIXME: This won't work for a 64 bit address. */
6520 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6523 if (mips_opts.isa != ISA_MIPS1)
6525 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6526 BFD_RELOC_LO16, AT);
6535 if (mips_opts.arch == CPU_R4650)
6537 as_bad (_("opcode not supported on this processor"));
6540 /* Even on a big endian machine $fn comes before $fn+1. We have
6541 to adjust when loading from memory. */
6544 assert (mips_opts.isa == ISA_MIPS1);
6545 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6546 target_big_endian ? treg + 1 : treg, r, breg);
6547 /* FIXME: A possible overflow which I don't know how to deal
6549 offset_expr.X_add_number += 4;
6550 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6551 target_big_endian ? treg : treg + 1, r, breg);
6559 * The MIPS assembler seems to check for X_add_number not
6560 * being double aligned and generating:
6563 * addiu at,at,%lo(foo+1)
6566 * But, the resulting address is the same after relocation so why
6567 * generate the extra instruction?
6569 if (mips_opts.arch == CPU_R4650)
6571 as_bad (_("opcode not supported on this processor"));
6574 /* Itbl support may require additional care here. */
6576 if (mips_opts.isa != ISA_MIPS1)
6587 if (mips_opts.arch == CPU_R4650)
6589 as_bad (_("opcode not supported on this processor"));
6593 if (mips_opts.isa != ISA_MIPS1)
6601 /* Itbl support may require additional care here. */
6606 if (HAVE_64BIT_GPRS)
6617 if (HAVE_64BIT_GPRS)
6627 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6628 loads for the case of doing a pair of loads to simulate an 'ld'.
6629 This is not currently done by the compiler, and assembly coders
6630 writing embedded-pic code can cope. */
6632 if (offset_expr.X_op != O_symbol
6633 && offset_expr.X_op != O_constant)
6635 as_bad (_("expression too complex"));
6636 offset_expr.X_op = O_constant;
6639 /* Even on a big endian machine $fn comes before $fn+1. We have
6640 to adjust when loading from memory. We set coproc if we must
6641 load $fn+1 first. */
6642 /* Itbl support may require additional care here. */
6643 if (! target_big_endian)
6646 if (mips_pic == NO_PIC
6647 || offset_expr.X_op == O_constant)
6651 /* If this is a reference to a GP relative symbol, we want
6652 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6653 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6654 If we have a base register, we use this
6656 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6657 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6658 If this is not a GP relative symbol, we want
6659 lui $at,<sym> (BFD_RELOC_HI16_S)
6660 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6661 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6662 If there is a base register, we add it to $at after the
6663 lui instruction. If there is a constant, we always use
6665 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6666 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6675 relax_start (offset_expr.X_add_symbol);
6678 tempreg = mips_gp_register;
6684 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6685 AT, breg, mips_gp_register);
6691 /* Itbl support may require additional care here. */
6692 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6693 coproc ? treg + 1 : treg,
6694 BFD_RELOC_GPREL16, tempreg);
6695 offset_expr.X_add_number += 4;
6697 /* Set mips_optimize to 2 to avoid inserting an
6699 hold_mips_optimize = mips_optimize;
6701 /* Itbl support may require additional care here. */
6702 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6703 coproc ? treg : treg + 1,
6704 BFD_RELOC_GPREL16, tempreg);
6705 mips_optimize = hold_mips_optimize;
6709 /* We just generated two relocs. When tc_gen_reloc
6710 handles this case, it will skip the first reloc and
6711 handle the second. The second reloc already has an
6712 extra addend of 4, which we added above. We must
6713 subtract it out, and then subtract another 4 to make
6714 the first reloc come out right. The second reloc
6715 will come out right because we are going to add 4 to
6716 offset_expr when we build its instruction below.
6718 If we have a symbol, then we don't want to include
6719 the offset, because it will wind up being included
6720 when we generate the reloc. */
6722 if (offset_expr.X_op == O_constant)
6723 offset_expr.X_add_number -= 8;
6726 offset_expr.X_add_number = -4;
6727 offset_expr.X_op = O_constant;
6730 macro_build_lui (p, &icnt, &offset_expr, AT);
6732 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6734 /* Itbl support may require additional care here. */
6735 macro_build (p, &icnt, &offset_expr, s, fmt,
6736 coproc ? treg + 1 : treg,
6737 BFD_RELOC_LO16, AT);
6738 /* FIXME: How do we handle overflow here? */
6739 offset_expr.X_add_number += 4;
6740 /* Itbl support may require additional care here. */
6741 macro_build (p, &icnt, &offset_expr, s, fmt,
6742 coproc ? treg : treg + 1,
6743 BFD_RELOC_LO16, AT);
6744 if (mips_relax.sequence)
6747 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6751 /* If this is a reference to an external symbol, we want
6752 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6757 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6759 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6760 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6761 If there is a base register we add it to $at before the
6762 lwc1 instructions. If there is a constant we include it
6763 in the lwc1 instructions. */
6765 expr1.X_add_number = offset_expr.X_add_number;
6766 if (expr1.X_add_number < -0x8000
6767 || expr1.X_add_number >= 0x8000 - 4)
6768 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6773 load_got_offset (&icnt, AT, &offset_expr);
6774 macro_build (NULL, &icnt, NULL, "nop", "");
6776 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6779 /* Set mips_optimize to 2 to avoid inserting an undesired
6781 hold_mips_optimize = mips_optimize;
6784 /* Itbl support may require additional care here. */
6785 relax_start (offset_expr.X_add_symbol);
6786 macro_build (NULL, &icnt, &expr1, s, fmt,
6787 coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
6788 expr1.X_add_number += 4;
6789 macro_build (NULL, &icnt, &expr1, s, fmt,
6790 coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
6792 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6793 coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
6794 offset_expr.X_add_number += 4;
6795 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6796 coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
6799 mips_optimize = hold_mips_optimize;
6801 else if (mips_pic == SVR4_PIC)
6806 /* If this is a reference to an external symbol, we want
6807 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6809 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6814 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6816 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6817 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6818 If there is a base register we add it to $at before the
6819 lwc1 instructions. If there is a constant we include it
6820 in the lwc1 instructions. */
6822 expr1.X_add_number = offset_expr.X_add_number;
6823 offset_expr.X_add_number = 0;
6824 if (expr1.X_add_number < -0x8000
6825 || expr1.X_add_number >= 0x8000 - 4)
6826 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6827 if (reg_needs_delay (mips_gp_register))
6835 relax_start (offset_expr.X_add_symbol);
6836 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
6837 BFD_RELOC_MIPS_GOT_HI16);
6838 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6839 AT, AT, mips_gp_register);
6840 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6841 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6842 macro_build (NULL, &icnt, NULL, "nop", "");
6844 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6846 /* Itbl support may require additional care here. */
6847 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6848 BFD_RELOC_LO16, AT);
6849 expr1.X_add_number += 4;
6851 /* Set mips_optimize to 2 to avoid inserting an undesired
6853 hold_mips_optimize = mips_optimize;
6855 /* Itbl support may require additional care here. */
6856 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6857 BFD_RELOC_LO16, AT);
6858 mips_optimize = hold_mips_optimize;
6859 expr1.X_add_number -= 4;
6862 offset_expr.X_add_number = expr1.X_add_number;
6864 macro_build (p, &icnt, NULL, "nop", "");
6865 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6866 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6867 macro_build (p, &icnt, NULL, "nop", "");
6869 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6871 /* Itbl support may require additional care here. */
6872 macro_build (p, &icnt, &offset_expr, s, fmt,
6873 coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
6874 offset_expr.X_add_number += 4;
6876 /* Set mips_optimize to 2 to avoid inserting an undesired
6878 hold_mips_optimize = mips_optimize;
6880 /* Itbl support may require additional care here. */
6881 macro_build (p, &icnt, &offset_expr, s, fmt,
6882 coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
6883 mips_optimize = hold_mips_optimize;
6886 else if (mips_pic == EMBEDDED_PIC)
6888 /* If there is no base register, we use
6889 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6890 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6891 If we have a base register, we use
6893 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6894 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6898 tempreg = mips_gp_register;
6903 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6904 AT, breg, mips_gp_register);
6909 /* Itbl support may require additional care here. */
6910 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6911 coproc ? treg + 1 : treg,
6912 BFD_RELOC_GPREL16, tempreg);
6913 offset_expr.X_add_number += 4;
6914 /* Itbl support may require additional care here. */
6915 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6916 coproc ? treg : treg + 1,
6917 BFD_RELOC_GPREL16, tempreg);
6933 assert (HAVE_32BIT_ADDRESSES);
6934 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6935 BFD_RELOC_LO16, breg);
6936 offset_expr.X_add_number += 4;
6937 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6938 BFD_RELOC_LO16, breg);
6941 /* New code added to support COPZ instructions.
6942 This code builds table entries out of the macros in mip_opcodes.
6943 R4000 uses interlocks to handle coproc delays.
6944 Other chips (like the R3000) require nops to be inserted for delays.
6946 FIXME: Currently, we require that the user handle delays.
6947 In order to fill delay slots for non-interlocked chips,
6948 we must have a way to specify delays based on the coprocessor.
6949 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6950 What are the side-effects of the cop instruction?
6951 What cache support might we have and what are its effects?
6952 Both coprocessor & memory require delays. how long???
6953 What registers are read/set/modified?
6955 If an itbl is provided to interpret cop instructions,
6956 this knowledge can be encoded in the itbl spec. */
6970 /* For now we just do C (same as Cz). The parameter will be
6971 stored in insn_opcode by mips_ip. */
6972 macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
6976 move_register (&icnt, dreg, sreg);
6979 #ifdef LOSING_COMPILER
6981 /* Try and see if this is a new itbl instruction.
6982 This code builds table entries out of the macros in mip_opcodes.
6983 FIXME: For now we just assemble the expression and pass it's
6984 value along as a 32-bit immediate.
6985 We may want to have the assembler assemble this value,
6986 so that we gain the assembler's knowledge of delay slots,
6988 Would it be more efficient to use mask (id) here? */
6989 if (itbl_have_entries
6990 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6992 s = ip->insn_mo->name;
6994 coproc = ITBL_DECODE_PNUM (immed_expr);;
6995 macro_build (NULL, &icnt, &immed_expr, s, "C");
7002 as_warn (_("Macro used $at after \".set noat\""));
7006 macro2 (struct mips_cl_insn *ip)
7008 register int treg, sreg, dreg, breg;
7024 bfd_reloc_code_real_type r;
7027 treg = (ip->insn_opcode >> 16) & 0x1f;
7028 dreg = (ip->insn_opcode >> 11) & 0x1f;
7029 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7030 mask = ip->insn_mo->mask;
7032 expr1.X_op = O_constant;
7033 expr1.X_op_symbol = NULL;
7034 expr1.X_add_symbol = NULL;
7035 expr1.X_add_number = 1;
7039 #endif /* LOSING_COMPILER */
7044 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7046 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7052 /* The MIPS assembler some times generates shifts and adds. I'm
7053 not trying to be that fancy. GCC should do this for us
7055 load_register (&icnt, AT, &imm_expr, dbl);
7056 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7058 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7071 mips_emit_delays (TRUE);
7072 ++mips_opts.noreorder;
7073 mips_any_noreorder = 1;
7075 load_register (&icnt, AT, &imm_expr, dbl);
7076 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
7077 sreg, imm ? AT : treg);
7078 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7079 macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
7081 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7083 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
7086 expr1.X_add_number = 8;
7087 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
7088 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7089 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7091 --mips_opts.noreorder;
7092 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7105 mips_emit_delays (TRUE);
7106 ++mips_opts.noreorder;
7107 mips_any_noreorder = 1;
7109 load_register (&icnt, AT, &imm_expr, dbl);
7110 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7111 sreg, imm ? AT : treg);
7112 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7113 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7115 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
7118 expr1.X_add_number = 8;
7119 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
7120 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7121 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7123 --mips_opts.noreorder;
7127 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7139 macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
7140 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
7146 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7147 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7148 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7149 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7153 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7165 macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
7166 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
7172 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7173 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
7174 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
7175 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7183 if (imm_expr.X_op != O_constant)
7184 as_bad (_("Improper rotate count"));
7185 rot = imm_expr.X_add_number & 0x3f;
7186 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7188 rot = (64 - rot) & 0x3f;
7190 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7191 dreg, sreg, rot - 32);
7193 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7199 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7202 l = (rot < 0x20) ? "dsll" : "dsll32";
7203 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7205 macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
7206 macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
7207 (0x20 - rot) & 0x1f);
7208 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7216 if (imm_expr.X_op != O_constant)
7217 as_bad (_("Improper rotate count"));
7218 rot = imm_expr.X_add_number & 0x1f;
7219 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7221 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
7227 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7230 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
7231 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
7232 (0x20 - rot) & 0x1f);
7233 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7238 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7240 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
7243 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7244 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
7245 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7246 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7250 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7252 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
7255 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7256 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
7257 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
7258 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7266 if (imm_expr.X_op != O_constant)
7267 as_bad (_("Improper rotate count"));
7268 rot = imm_expr.X_add_number & 0x3f;
7269 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7272 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7273 dreg, sreg, rot - 32);
7275 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7281 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7284 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7285 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7287 macro_build (NULL, &icnt, NULL, r, "d,w,<", AT, sreg, rot);
7288 macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
7289 (0x20 - rot) & 0x1f);
7290 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7298 if (imm_expr.X_op != O_constant)
7299 as_bad (_("Improper rotate count"));
7300 rot = imm_expr.X_add_number & 0x1f;
7301 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7303 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
7308 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7311 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
7312 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
7313 (0x20 - rot) & 0x1f);
7314 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7319 if (mips_opts.arch == CPU_R4650)
7321 as_bad (_("opcode not supported on this processor"));
7324 assert (mips_opts.isa == ISA_MIPS1);
7325 /* Even on a big endian machine $fn comes before $fn+1. We have
7326 to adjust when storing to memory. */
7327 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7328 target_big_endian ? treg + 1 : treg,
7329 BFD_RELOC_LO16, breg);
7330 offset_expr.X_add_number += 4;
7331 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7332 target_big_endian ? treg : treg + 1,
7333 BFD_RELOC_LO16, breg);
7338 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
7341 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7345 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7346 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7352 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7354 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7360 as_warn (_("Instruction %s: result is always false"),
7362 move_register (&icnt, dreg, 0);
7365 if (imm_expr.X_op == O_constant
7366 && imm_expr.X_add_number >= 0
7367 && imm_expr.X_add_number < 0x10000)
7369 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7373 else if (imm_expr.X_op == O_constant
7374 && imm_expr.X_add_number > -0x8000
7375 && imm_expr.X_add_number < 0)
7377 imm_expr.X_add_number = -imm_expr.X_add_number;
7378 macro_build (NULL, &icnt, &imm_expr,
7379 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7380 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7385 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7386 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7389 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7395 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7401 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
7402 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7406 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7408 if (imm_expr.X_op == O_constant
7409 && imm_expr.X_add_number >= -0x8000
7410 && imm_expr.X_add_number < 0x8000)
7412 macro_build (NULL, &icnt, &imm_expr,
7413 mask == M_SGE_I ? "slti" : "sltiu",
7414 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7419 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7420 macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
7421 "d,v,t", dreg, sreg, AT);
7424 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7430 case M_SGT: /* sreg > treg <==> treg < sreg */
7436 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7439 case M_SGT_I: /* sreg > I <==> I < sreg */
7445 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7446 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7449 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7455 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7456 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7460 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7466 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7467 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7468 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7473 if (imm_expr.X_op == O_constant
7474 && imm_expr.X_add_number >= -0x8000
7475 && imm_expr.X_add_number < 0x8000)
7477 macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
7481 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7482 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
7486 if (imm_expr.X_op == O_constant
7487 && imm_expr.X_add_number >= -0x8000
7488 && imm_expr.X_add_number < 0x8000)
7490 macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
7494 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7495 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
7500 macro_build (NULL, &icnt, NULL, "sltu","d,v,t", dreg, 0, treg);
7502 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7505 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7506 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7511 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7513 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7518 as_warn (_("Instruction %s: result is always true"),
7520 macro_build (NULL, &icnt, &expr1,
7521 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7522 "t,r,j", dreg, 0, BFD_RELOC_LO16);
7525 if (imm_expr.X_op == O_constant
7526 && imm_expr.X_add_number >= 0
7527 && imm_expr.X_add_number < 0x10000)
7529 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7533 else if (imm_expr.X_op == O_constant
7534 && imm_expr.X_add_number > -0x8000
7535 && imm_expr.X_add_number < 0)
7537 imm_expr.X_add_number = -imm_expr.X_add_number;
7538 macro_build (NULL, &icnt, &imm_expr,
7539 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7540 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7545 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7546 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7549 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7557 if (imm_expr.X_op == O_constant
7558 && imm_expr.X_add_number > -0x8000
7559 && imm_expr.X_add_number <= 0x8000)
7561 imm_expr.X_add_number = -imm_expr.X_add_number;
7562 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
7563 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7566 load_register (&icnt, AT, &imm_expr, dbl);
7567 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
7574 if (imm_expr.X_op == O_constant
7575 && imm_expr.X_add_number > -0x8000
7576 && imm_expr.X_add_number <= 0x8000)
7578 imm_expr.X_add_number = -imm_expr.X_add_number;
7579 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
7580 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7583 load_register (&icnt, AT, &imm_expr, dbl);
7584 macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
7606 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7607 macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
7612 assert (mips_opts.isa == ISA_MIPS1);
7613 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7614 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7617 * Is the double cfc1 instruction a bug in the mips assembler;
7618 * or is there a reason for it?
7620 mips_emit_delays (TRUE);
7621 ++mips_opts.noreorder;
7622 mips_any_noreorder = 1;
7623 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7624 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7625 macro_build (NULL, &icnt, NULL, "nop", "");
7626 expr1.X_add_number = 3;
7627 macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7629 expr1.X_add_number = 2;
7630 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7632 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
7633 macro_build (NULL, &icnt, NULL, "nop", "");
7634 macro_build (NULL, &icnt, NULL,
7635 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
7637 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
7638 macro_build (NULL, &icnt, NULL, "nop", "");
7639 --mips_opts.noreorder;
7648 if (offset_expr.X_add_number >= 0x7fff)
7649 as_bad (_("operand overflow"));
7650 if (! target_big_endian)
7651 ++offset_expr.X_add_number;
7652 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7653 BFD_RELOC_LO16, breg);
7654 if (! target_big_endian)
7655 --offset_expr.X_add_number;
7657 ++offset_expr.X_add_number;
7658 macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7659 BFD_RELOC_LO16, breg);
7660 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
7661 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7674 if (offset_expr.X_add_number >= 0x8000 - off)
7675 as_bad (_("operand overflow"));
7680 if (! target_big_endian)
7681 offset_expr.X_add_number += off;
7682 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7683 BFD_RELOC_LO16, breg);
7684 if (! target_big_endian)
7685 offset_expr.X_add_number -= off;
7687 offset_expr.X_add_number += off;
7688 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7689 BFD_RELOC_LO16, breg);
7691 /* If necessary, move the result in tempreg the final destination. */
7692 if (treg == tempreg)
7694 /* Protect second load's delay slot. */
7695 if (!gpr_interlocks)
7696 macro_build (NULL, &icnt, NULL, "nop", "");
7697 move_register (&icnt, treg, tempreg);
7711 load_address (&icnt, AT, &offset_expr, &used_at);
7713 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7715 if (! target_big_endian)
7716 expr1.X_add_number = off;
7718 expr1.X_add_number = 0;
7719 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7720 BFD_RELOC_LO16, AT);
7721 if (! target_big_endian)
7722 expr1.X_add_number = 0;
7724 expr1.X_add_number = off;
7725 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7726 BFD_RELOC_LO16, AT);
7732 load_address (&icnt, AT, &offset_expr, &used_at);
7734 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7736 if (target_big_endian)
7737 expr1.X_add_number = 0;
7738 macro_build (NULL, &icnt, &expr1,
7739 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7740 treg, BFD_RELOC_LO16, AT);
7741 if (target_big_endian)
7742 expr1.X_add_number = 1;
7744 expr1.X_add_number = 0;
7745 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
7746 AT, BFD_RELOC_LO16, AT);
7747 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7748 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7752 if (offset_expr.X_add_number >= 0x7fff)
7753 as_bad (_("operand overflow"));
7754 if (target_big_endian)
7755 ++offset_expr.X_add_number;
7756 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7757 BFD_RELOC_LO16, breg);
7758 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
7759 if (target_big_endian)
7760 --offset_expr.X_add_number;
7762 ++offset_expr.X_add_number;
7763 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7764 BFD_RELOC_LO16, breg);
7777 if (offset_expr.X_add_number >= 0x8000 - off)
7778 as_bad (_("operand overflow"));
7779 if (! target_big_endian)
7780 offset_expr.X_add_number += off;
7781 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7782 BFD_RELOC_LO16, breg);
7783 if (! target_big_endian)
7784 offset_expr.X_add_number -= off;
7786 offset_expr.X_add_number += off;
7787 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7788 BFD_RELOC_LO16, breg);
7802 load_address (&icnt, AT, &offset_expr, &used_at);
7804 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7806 if (! target_big_endian)
7807 expr1.X_add_number = off;
7809 expr1.X_add_number = 0;
7810 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7811 BFD_RELOC_LO16, AT);
7812 if (! target_big_endian)
7813 expr1.X_add_number = 0;
7815 expr1.X_add_number = off;
7816 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7817 BFD_RELOC_LO16, AT);
7822 load_address (&icnt, AT, &offset_expr, &used_at);
7824 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7826 if (! target_big_endian)
7827 expr1.X_add_number = 0;
7828 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7829 BFD_RELOC_LO16, AT);
7830 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
7831 if (! target_big_endian)
7832 expr1.X_add_number = 1;
7834 expr1.X_add_number = 0;
7835 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7836 BFD_RELOC_LO16, AT);
7837 if (! target_big_endian)
7838 expr1.X_add_number = 0;
7840 expr1.X_add_number = 1;
7841 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7842 BFD_RELOC_LO16, AT);
7843 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7844 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7848 /* FIXME: Check if this is one of the itbl macros, since they
7849 are added dynamically. */
7850 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7854 as_warn (_("Macro used $at after \".set noat\""));
7857 /* Implement macros in mips16 mode. */
7860 mips16_macro (struct mips_cl_insn *ip)
7863 int xreg, yreg, zreg, tmp;
7867 const char *s, *s2, *s3;
7869 mask = ip->insn_mo->mask;
7871 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7872 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7873 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7877 expr1.X_op = O_constant;
7878 expr1.X_op_symbol = NULL;
7879 expr1.X_add_symbol = NULL;
7880 expr1.X_add_number = 1;
7899 mips_emit_delays (TRUE);
7900 ++mips_opts.noreorder;
7901 mips_any_noreorder = 1;
7902 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
7904 expr1.X_add_number = 2;
7905 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7906 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7908 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7909 since that causes an overflow. We should do that as well,
7910 but I don't see how to do the comparisons without a temporary
7912 --mips_opts.noreorder;
7913 macro_build (NULL, &icnt, NULL, s, "x", zreg);
7932 mips_emit_delays (TRUE);
7933 ++mips_opts.noreorder;
7934 mips_any_noreorder = 1;
7935 macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
7936 expr1.X_add_number = 2;
7937 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7938 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7939 --mips_opts.noreorder;
7940 macro_build (NULL, &icnt, NULL, s2, "x", zreg);
7946 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
7948 macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
7956 if (imm_expr.X_op != O_constant)
7957 as_bad (_("Unsupported large constant"));
7958 imm_expr.X_add_number = -imm_expr.X_add_number;
7959 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
7964 if (imm_expr.X_op != O_constant)
7965 as_bad (_("Unsupported large constant"));
7966 imm_expr.X_add_number = -imm_expr.X_add_number;
7967 macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
7971 if (imm_expr.X_op != O_constant)
7972 as_bad (_("Unsupported large constant"));
7973 imm_expr.X_add_number = -imm_expr.X_add_number;
7974 macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
7996 goto do_reverse_branch;
8000 goto do_reverse_branch;
8012 goto do_reverse_branch;
8023 macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
8024 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8051 goto do_addone_branch_i;
8056 goto do_addone_branch_i;
8071 goto do_addone_branch_i;
8078 if (imm_expr.X_op != O_constant)
8079 as_bad (_("Unsupported large constant"));
8080 ++imm_expr.X_add_number;
8083 macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
8084 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8088 expr1.X_add_number = 0;
8089 macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
8091 move_register (&icnt, xreg, yreg);
8092 expr1.X_add_number = 2;
8093 macro_build (NULL, &icnt, &expr1, "bteqz", "p");
8094 macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
8098 /* For consistency checking, verify that all bits are specified either
8099 by the match/mask part of the instruction definition, or by the
8102 validate_mips_insn (const struct mips_opcode *opc)
8104 const char *p = opc->args;
8106 unsigned long used_bits = opc->mask;
8108 if ((used_bits & opc->match) != opc->match)
8110 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8111 opc->name, opc->args);
8114 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8124 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8125 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8126 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8127 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8128 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8129 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8130 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8131 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8132 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8135 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8136 c, opc->name, opc->args);
8140 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8141 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8143 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8144 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8145 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8146 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8148 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8149 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8151 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8152 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8154 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8155 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8156 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8157 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8158 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8159 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8160 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8161 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8162 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8163 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8164 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8165 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8166 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8167 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8168 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8169 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8170 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8172 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8173 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8174 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8175 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8177 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8178 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8179 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8180 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8181 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8182 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8183 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8184 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8185 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8188 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8189 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8190 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8191 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8192 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8196 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8197 c, opc->name, opc->args);
8201 if (used_bits != 0xffffffff)
8203 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8204 ~used_bits & 0xffffffff, opc->name, opc->args);
8210 /* This routine assembles an instruction into its binary format. As a
8211 side effect, it sets one of the global variables imm_reloc or
8212 offset_reloc to the type of relocation to do if one of the operands
8213 is an address expression. */
8216 mips_ip (char *str, struct mips_cl_insn *ip)
8221 struct mips_opcode *insn;
8224 unsigned int lastregno = 0;
8225 unsigned int lastpos = 0;
8226 unsigned int limlo, limhi;
8232 /* If the instruction contains a '.', we first try to match an instruction
8233 including the '.'. Then we try again without the '.'. */
8235 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8238 /* If we stopped on whitespace, then replace the whitespace with null for
8239 the call to hash_find. Save the character we replaced just in case we
8240 have to re-parse the instruction. */
8247 insn = (struct mips_opcode *) hash_find (op_hash, str);
8249 /* If we didn't find the instruction in the opcode table, try again, but
8250 this time with just the instruction up to, but not including the
8254 /* Restore the character we overwrite above (if any). */
8258 /* Scan up to the first '.' or whitespace. */
8260 *s != '\0' && *s != '.' && !ISSPACE (*s);
8264 /* If we did not find a '.', then we can quit now. */
8267 insn_error = "unrecognized opcode";
8271 /* Lookup the instruction in the hash table. */
8273 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8275 insn_error = "unrecognized opcode";
8285 assert (strcmp (insn->name, str) == 0);
8287 if (OPCODE_IS_MEMBER (insn,
8289 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8290 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8291 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8297 if (insn->pinfo != INSN_MACRO)
8299 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8305 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8306 && strcmp (insn->name, insn[1].name) == 0)
8315 static char buf[100];
8317 _("opcode not supported on this processor: %s (%s)"),
8318 mips_cpu_info_from_arch (mips_opts.arch)->name,
8319 mips_cpu_info_from_isa (mips_opts.isa)->name);
8329 ip->insn_opcode = insn->match;
8331 for (args = insn->args;; ++args)
8335 s += strspn (s, " \t");
8339 case '\0': /* end of args */
8352 ip->insn_opcode |= lastregno << OP_SH_RS;
8356 ip->insn_opcode |= lastregno << OP_SH_RT;
8360 ip->insn_opcode |= lastregno << OP_SH_FT;
8364 ip->insn_opcode |= lastregno << OP_SH_FS;
8370 /* Handle optional base register.
8371 Either the base register is omitted or
8372 we must have a left paren. */
8373 /* This is dependent on the next operand specifier
8374 is a base register specification. */
8375 assert (args[1] == 'b' || args[1] == '5'
8376 || args[1] == '-' || args[1] == '4');
8380 case ')': /* these must match exactly */
8387 case '+': /* Opcode extension character. */
8390 case 'A': /* ins/ext position, becomes LSB. */
8399 my_getExpression (&imm_expr, s);
8400 check_absolute_expr (ip, &imm_expr);
8401 if ((unsigned long) imm_expr.X_add_number < limlo
8402 || (unsigned long) imm_expr.X_add_number > limhi)
8404 as_bad (_("Improper position (%lu)"),
8405 (unsigned long) imm_expr.X_add_number);
8406 imm_expr.X_add_number = limlo;
8408 lastpos = imm_expr.X_add_number;
8409 ip->insn_opcode |= (imm_expr.X_add_number
8410 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8411 imm_expr.X_op = O_absent;
8415 case 'B': /* ins size, becomes MSB. */
8424 my_getExpression (&imm_expr, s);
8425 check_absolute_expr (ip, &imm_expr);
8426 /* Check for negative input so that small negative numbers
8427 will not succeed incorrectly. The checks against
8428 (pos+size) transitively check "size" itself,
8429 assuming that "pos" is reasonable. */
8430 if ((long) imm_expr.X_add_number < 0
8431 || ((unsigned long) imm_expr.X_add_number
8433 || ((unsigned long) imm_expr.X_add_number
8436 as_bad (_("Improper insert size (%lu, position %lu)"),
8437 (unsigned long) imm_expr.X_add_number,
8438 (unsigned long) lastpos);
8439 imm_expr.X_add_number = limlo - lastpos;
8441 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8442 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8443 imm_expr.X_op = O_absent;
8447 case 'C': /* ext size, becomes MSBD. */
8460 my_getExpression (&imm_expr, s);
8461 check_absolute_expr (ip, &imm_expr);
8462 /* Check for negative input so that small negative numbers
8463 will not succeed incorrectly. The checks against
8464 (pos+size) transitively check "size" itself,
8465 assuming that "pos" is reasonable. */
8466 if ((long) imm_expr.X_add_number < 0
8467 || ((unsigned long) imm_expr.X_add_number
8469 || ((unsigned long) imm_expr.X_add_number
8472 as_bad (_("Improper extract size (%lu, position %lu)"),
8473 (unsigned long) imm_expr.X_add_number,
8474 (unsigned long) lastpos);
8475 imm_expr.X_add_number = limlo - lastpos;
8477 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8478 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8479 imm_expr.X_op = O_absent;
8484 /* +D is for disassembly only; never match. */
8488 /* "+I" is like "I", except that imm2_expr is used. */
8489 my_getExpression (&imm2_expr, s);
8490 if (imm2_expr.X_op != O_big
8491 && imm2_expr.X_op != O_constant)
8492 insn_error = _("absolute expression required");
8493 normalize_constant_expr (&imm2_expr);
8498 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8499 *args, insn->name, insn->args);
8500 /* Further processing is fruitless. */
8505 case '<': /* must be at least one digit */
8507 * According to the manual, if the shift amount is greater
8508 * than 31 or less than 0, then the shift amount should be
8509 * mod 32. In reality the mips assembler issues an error.
8510 * We issue a warning and mask out all but the low 5 bits.
8512 my_getExpression (&imm_expr, s);
8513 check_absolute_expr (ip, &imm_expr);
8514 if ((unsigned long) imm_expr.X_add_number > 31)
8516 as_warn (_("Improper shift amount (%lu)"),
8517 (unsigned long) imm_expr.X_add_number);
8518 imm_expr.X_add_number &= OP_MASK_SHAMT;
8520 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8521 imm_expr.X_op = O_absent;
8525 case '>': /* shift amount minus 32 */
8526 my_getExpression (&imm_expr, s);
8527 check_absolute_expr (ip, &imm_expr);
8528 if ((unsigned long) imm_expr.X_add_number < 32
8529 || (unsigned long) imm_expr.X_add_number > 63)
8531 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8532 imm_expr.X_op = O_absent;
8536 case 'k': /* cache code */
8537 case 'h': /* prefx code */
8538 my_getExpression (&imm_expr, s);
8539 check_absolute_expr (ip, &imm_expr);
8540 if ((unsigned long) imm_expr.X_add_number > 31)
8542 as_warn (_("Invalid value for `%s' (%lu)"),
8544 (unsigned long) imm_expr.X_add_number);
8545 imm_expr.X_add_number &= 0x1f;
8548 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8550 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8551 imm_expr.X_op = O_absent;
8555 case 'c': /* break code */
8556 my_getExpression (&imm_expr, s);
8557 check_absolute_expr (ip, &imm_expr);
8558 if ((unsigned long) imm_expr.X_add_number > 1023)
8560 as_warn (_("Illegal break code (%lu)"),
8561 (unsigned long) imm_expr.X_add_number);
8562 imm_expr.X_add_number &= OP_MASK_CODE;
8564 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8565 imm_expr.X_op = O_absent;
8569 case 'q': /* lower break code */
8570 my_getExpression (&imm_expr, s);
8571 check_absolute_expr (ip, &imm_expr);
8572 if ((unsigned long) imm_expr.X_add_number > 1023)
8574 as_warn (_("Illegal lower break code (%lu)"),
8575 (unsigned long) imm_expr.X_add_number);
8576 imm_expr.X_add_number &= OP_MASK_CODE2;
8578 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8579 imm_expr.X_op = O_absent;
8583 case 'B': /* 20-bit syscall/break code. */
8584 my_getExpression (&imm_expr, s);
8585 check_absolute_expr (ip, &imm_expr);
8586 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8587 as_warn (_("Illegal 20-bit code (%lu)"),
8588 (unsigned long) imm_expr.X_add_number);
8589 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8590 imm_expr.X_op = O_absent;
8594 case 'C': /* Coprocessor code */
8595 my_getExpression (&imm_expr, s);
8596 check_absolute_expr (ip, &imm_expr);
8597 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8599 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8600 (unsigned long) imm_expr.X_add_number);
8601 imm_expr.X_add_number &= ((1 << 25) - 1);
8603 ip->insn_opcode |= imm_expr.X_add_number;
8604 imm_expr.X_op = O_absent;
8608 case 'J': /* 19-bit wait code. */
8609 my_getExpression (&imm_expr, s);
8610 check_absolute_expr (ip, &imm_expr);
8611 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8612 as_warn (_("Illegal 19-bit code (%lu)"),
8613 (unsigned long) imm_expr.X_add_number);
8614 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8615 imm_expr.X_op = O_absent;
8619 case 'P': /* Performance register */
8620 my_getExpression (&imm_expr, s);
8621 check_absolute_expr (ip, &imm_expr);
8622 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8624 as_warn (_("Invalid performance register (%lu)"),
8625 (unsigned long) imm_expr.X_add_number);
8626 imm_expr.X_add_number &= OP_MASK_PERFREG;
8628 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8629 imm_expr.X_op = O_absent;
8633 case 'b': /* base register */
8634 case 'd': /* destination register */
8635 case 's': /* source register */
8636 case 't': /* target register */
8637 case 'r': /* both target and source */
8638 case 'v': /* both dest and source */
8639 case 'w': /* both dest and target */
8640 case 'E': /* coprocessor target register */
8641 case 'G': /* coprocessor destination register */
8642 case 'K': /* 'rdhwr' destination register */
8643 case 'x': /* ignore register name */
8644 case 'z': /* must be zero register */
8645 case 'U': /* destination register (clo/clz). */
8660 while (ISDIGIT (*s));
8662 as_bad (_("Invalid register number (%d)"), regno);
8664 else if (*args == 'E' || *args == 'G' || *args == 'K')
8668 if (s[1] == 'r' && s[2] == 'a')
8673 else if (s[1] == 'f' && s[2] == 'p')
8678 else if (s[1] == 's' && s[2] == 'p')
8683 else if (s[1] == 'g' && s[2] == 'p')
8688 else if (s[1] == 'a' && s[2] == 't')
8693 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8698 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8703 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8708 else if (itbl_have_entries)
8713 p = s + 1; /* advance past '$' */
8714 n = itbl_get_field (&p); /* n is name */
8716 /* See if this is a register defined in an
8718 if (itbl_get_reg_val (n, &r))
8720 /* Get_field advances to the start of
8721 the next field, so we need to back
8722 rack to the end of the last field. */
8726 s = strchr (s, '\0');
8740 as_warn (_("Used $at without \".set noat\""));
8746 if (c == 'r' || c == 'v' || c == 'w')
8753 /* 'z' only matches $0. */
8754 if (c == 'z' && regno != 0)
8757 /* Now that we have assembled one operand, we use the args string
8758 * to figure out where it goes in the instruction. */
8765 ip->insn_opcode |= regno << OP_SH_RS;
8770 ip->insn_opcode |= regno << OP_SH_RD;
8773 ip->insn_opcode |= regno << OP_SH_RD;
8774 ip->insn_opcode |= regno << OP_SH_RT;
8779 ip->insn_opcode |= regno << OP_SH_RT;
8782 /* This case exists because on the r3000 trunc
8783 expands into a macro which requires a gp
8784 register. On the r6000 or r4000 it is
8785 assembled into a single instruction which
8786 ignores the register. Thus the insn version
8787 is MIPS_ISA2 and uses 'x', and the macro
8788 version is MIPS_ISA1 and uses 't'. */
8791 /* This case is for the div instruction, which
8792 acts differently if the destination argument
8793 is $0. This only matches $0, and is checked
8794 outside the switch. */
8797 /* Itbl operand; not yet implemented. FIXME ?? */
8799 /* What about all other operands like 'i', which
8800 can be specified in the opcode table? */
8810 ip->insn_opcode |= lastregno << OP_SH_RS;
8813 ip->insn_opcode |= lastregno << OP_SH_RT;
8818 case 'O': /* MDMX alignment immediate constant. */
8819 my_getExpression (&imm_expr, s);
8820 check_absolute_expr (ip, &imm_expr);
8821 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8823 as_warn ("Improper align amount (%ld), using low bits",
8824 (long) imm_expr.X_add_number);
8825 imm_expr.X_add_number &= OP_MASK_ALN;
8827 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8828 imm_expr.X_op = O_absent;
8832 case 'Q': /* MDMX vector, element sel, or const. */
8835 /* MDMX Immediate. */
8836 my_getExpression (&imm_expr, s);
8837 check_absolute_expr (ip, &imm_expr);
8838 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8840 as_warn (_("Invalid MDMX Immediate (%ld)"),
8841 (long) imm_expr.X_add_number);
8842 imm_expr.X_add_number &= OP_MASK_FT;
8844 imm_expr.X_add_number &= OP_MASK_FT;
8845 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8846 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8848 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8849 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8850 imm_expr.X_op = O_absent;
8854 /* Not MDMX Immediate. Fall through. */
8855 case 'X': /* MDMX destination register. */
8856 case 'Y': /* MDMX source register. */
8857 case 'Z': /* MDMX target register. */
8859 case 'D': /* floating point destination register */
8860 case 'S': /* floating point source register */
8861 case 'T': /* floating point target register */
8862 case 'R': /* floating point source register */
8866 /* Accept $fN for FP and MDMX register numbers, and in
8867 addition accept $vN for MDMX register numbers. */
8868 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8869 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8880 while (ISDIGIT (*s));
8883 as_bad (_("Invalid float register number (%d)"), regno);
8885 if ((regno & 1) != 0
8887 && ! (strcmp (str, "mtc1") == 0
8888 || strcmp (str, "mfc1") == 0
8889 || strcmp (str, "lwc1") == 0
8890 || strcmp (str, "swc1") == 0
8891 || strcmp (str, "l.s") == 0
8892 || strcmp (str, "s.s") == 0))
8893 as_warn (_("Float register should be even, was %d"),
8901 if (c == 'V' || c == 'W')
8912 ip->insn_opcode |= regno << OP_SH_FD;
8917 ip->insn_opcode |= regno << OP_SH_FS;
8920 /* This is like 'Z', but also needs to fix the MDMX
8921 vector/scalar select bits. Note that the
8922 scalar immediate case is handled above. */
8925 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8926 int max_el = (is_qh ? 3 : 7);
8928 my_getExpression(&imm_expr, s);
8929 check_absolute_expr (ip, &imm_expr);
8931 if (imm_expr.X_add_number > max_el)
8932 as_bad(_("Bad element selector %ld"),
8933 (long) imm_expr.X_add_number);
8934 imm_expr.X_add_number &= max_el;
8935 ip->insn_opcode |= (imm_expr.X_add_number
8939 as_warn(_("Expecting ']' found '%s'"), s);
8945 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8946 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8949 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8956 ip->insn_opcode |= regno << OP_SH_FT;
8959 ip->insn_opcode |= regno << OP_SH_FR;
8969 ip->insn_opcode |= lastregno << OP_SH_FS;
8972 ip->insn_opcode |= lastregno << OP_SH_FT;
8978 my_getExpression (&imm_expr, s);
8979 if (imm_expr.X_op != O_big
8980 && imm_expr.X_op != O_constant)
8981 insn_error = _("absolute expression required");
8982 normalize_constant_expr (&imm_expr);
8987 my_getExpression (&offset_expr, s);
8988 *imm_reloc = BFD_RELOC_32;
9001 unsigned char temp[8];
9003 unsigned int length;
9008 /* These only appear as the last operand in an
9009 instruction, and every instruction that accepts
9010 them in any variant accepts them in all variants.
9011 This means we don't have to worry about backing out
9012 any changes if the instruction does not match.
9014 The difference between them is the size of the
9015 floating point constant and where it goes. For 'F'
9016 and 'L' the constant is 64 bits; for 'f' and 'l' it
9017 is 32 bits. Where the constant is placed is based
9018 on how the MIPS assembler does things:
9021 f -- immediate value
9024 The .lit4 and .lit8 sections are only used if
9025 permitted by the -G argument.
9027 When generating embedded PIC code, we use the
9028 .lit8 section but not the .lit4 section (we can do
9029 .lit4 inline easily; we need to put .lit8
9030 somewhere in the data segment, and using .lit8
9031 permits the linker to eventually combine identical
9034 The code below needs to know whether the target register
9035 is 32 or 64 bits wide. It relies on the fact 'f' and
9036 'F' are used with GPR-based instructions and 'l' and
9037 'L' are used with FPR-based instructions. */
9039 f64 = *args == 'F' || *args == 'L';
9040 using_gprs = *args == 'F' || *args == 'f';
9042 save_in = input_line_pointer;
9043 input_line_pointer = s;
9044 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9046 s = input_line_pointer;
9047 input_line_pointer = save_in;
9048 if (err != NULL && *err != '\0')
9050 as_bad (_("Bad floating point constant: %s"), err);
9051 memset (temp, '\0', sizeof temp);
9052 length = f64 ? 8 : 4;
9055 assert (length == (unsigned) (f64 ? 8 : 4));
9059 && (! USE_GLOBAL_POINTER_OPT
9060 || mips_pic == EMBEDDED_PIC
9061 || g_switch_value < 4
9062 || (temp[0] == 0 && temp[1] == 0)
9063 || (temp[2] == 0 && temp[3] == 0))))
9065 imm_expr.X_op = O_constant;
9066 if (! target_big_endian)
9067 imm_expr.X_add_number = bfd_getl32 (temp);
9069 imm_expr.X_add_number = bfd_getb32 (temp);
9072 && ! mips_disable_float_construction
9073 /* Constants can only be constructed in GPRs and
9074 copied to FPRs if the GPRs are at least as wide
9075 as the FPRs. Force the constant into memory if
9076 we are using 64-bit FPRs but the GPRs are only
9079 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9080 && ((temp[0] == 0 && temp[1] == 0)
9081 || (temp[2] == 0 && temp[3] == 0))
9082 && ((temp[4] == 0 && temp[5] == 0)
9083 || (temp[6] == 0 && temp[7] == 0)))
9085 /* The value is simple enough to load with a couple of
9086 instructions. If using 32-bit registers, set
9087 imm_expr to the high order 32 bits and offset_expr to
9088 the low order 32 bits. Otherwise, set imm_expr to
9089 the entire 64 bit constant. */
9090 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9092 imm_expr.X_op = O_constant;
9093 offset_expr.X_op = O_constant;
9094 if (! target_big_endian)
9096 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9097 offset_expr.X_add_number = bfd_getl32 (temp);
9101 imm_expr.X_add_number = bfd_getb32 (temp);
9102 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9104 if (offset_expr.X_add_number == 0)
9105 offset_expr.X_op = O_absent;
9107 else if (sizeof (imm_expr.X_add_number) > 4)
9109 imm_expr.X_op = O_constant;
9110 if (! target_big_endian)
9111 imm_expr.X_add_number = bfd_getl64 (temp);
9113 imm_expr.X_add_number = bfd_getb64 (temp);
9117 imm_expr.X_op = O_big;
9118 imm_expr.X_add_number = 4;
9119 if (! target_big_endian)
9121 generic_bignum[0] = bfd_getl16 (temp);
9122 generic_bignum[1] = bfd_getl16 (temp + 2);
9123 generic_bignum[2] = bfd_getl16 (temp + 4);
9124 generic_bignum[3] = bfd_getl16 (temp + 6);
9128 generic_bignum[0] = bfd_getb16 (temp + 6);
9129 generic_bignum[1] = bfd_getb16 (temp + 4);
9130 generic_bignum[2] = bfd_getb16 (temp + 2);
9131 generic_bignum[3] = bfd_getb16 (temp);
9137 const char *newname;
9140 /* Switch to the right section. */
9142 subseg = now_subseg;
9145 default: /* unused default case avoids warnings. */
9147 newname = RDATA_SECTION_NAME;
9148 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9149 || mips_pic == EMBEDDED_PIC)
9153 if (mips_pic == EMBEDDED_PIC)
9156 newname = RDATA_SECTION_NAME;
9159 assert (!USE_GLOBAL_POINTER_OPT
9160 || g_switch_value >= 4);
9164 new_seg = subseg_new (newname, (subsegT) 0);
9165 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9166 bfd_set_section_flags (stdoutput, new_seg,
9171 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9172 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9173 && strcmp (TARGET_OS, "elf") != 0)
9174 record_alignment (new_seg, 4);
9176 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9178 as_bad (_("Can't use floating point insn in this section"));
9180 /* Set the argument to the current address in the
9182 offset_expr.X_op = O_symbol;
9183 offset_expr.X_add_symbol =
9184 symbol_new ("L0\001", now_seg,
9185 (valueT) frag_now_fix (), frag_now);
9186 offset_expr.X_add_number = 0;
9188 /* Put the floating point number into the section. */
9189 p = frag_more ((int) length);
9190 memcpy (p, temp, length);
9192 /* Switch back to the original section. */
9193 subseg_set (seg, subseg);
9198 case 'i': /* 16 bit unsigned immediate */
9199 case 'j': /* 16 bit signed immediate */
9200 *imm_reloc = BFD_RELOC_LO16;
9201 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9204 offsetT minval, maxval;
9206 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9207 && strcmp (insn->name, insn[1].name) == 0);
9209 /* If the expression was written as an unsigned number,
9210 only treat it as signed if there are no more
9214 && sizeof (imm_expr.X_add_number) <= 4
9215 && imm_expr.X_op == O_constant
9216 && imm_expr.X_add_number < 0
9217 && imm_expr.X_unsigned
9221 /* For compatibility with older assemblers, we accept
9222 0x8000-0xffff as signed 16-bit numbers when only
9223 signed numbers are allowed. */
9225 minval = 0, maxval = 0xffff;
9227 minval = -0x8000, maxval = 0x7fff;
9229 minval = -0x8000, maxval = 0xffff;
9231 if (imm_expr.X_op != O_constant
9232 || imm_expr.X_add_number < minval
9233 || imm_expr.X_add_number > maxval)
9237 if (imm_expr.X_op == O_constant
9238 || imm_expr.X_op == O_big)
9239 as_bad (_("expression out of range"));
9245 case 'o': /* 16 bit offset */
9246 /* Check whether there is only a single bracketed expression
9247 left. If so, it must be the base register and the
9248 constant must be zero. */
9249 if (*s == '(' && strchr (s + 1, '(') == 0)
9251 offset_expr.X_op = O_constant;
9252 offset_expr.X_add_number = 0;
9256 /* If this value won't fit into a 16 bit offset, then go
9257 find a macro that will generate the 32 bit offset
9259 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9260 && (offset_expr.X_op != O_constant
9261 || offset_expr.X_add_number >= 0x8000
9262 || offset_expr.X_add_number < -0x8000))
9268 case 'p': /* pc relative offset */
9269 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9270 my_getExpression (&offset_expr, s);
9274 case 'u': /* upper 16 bits */
9275 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9276 && imm_expr.X_op == O_constant
9277 && (imm_expr.X_add_number < 0
9278 || imm_expr.X_add_number >= 0x10000))
9279 as_bad (_("lui expression not in range 0..65535"));
9283 case 'a': /* 26 bit address */
9284 my_getExpression (&offset_expr, s);
9286 *offset_reloc = BFD_RELOC_MIPS_JMP;
9289 case 'N': /* 3 bit branch condition code */
9290 case 'M': /* 3 bit compare condition code */
9291 if (strncmp (s, "$fcc", 4) != 0)
9301 while (ISDIGIT (*s));
9303 as_bad (_("Invalid condition code register $fcc%d"), regno);
9304 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9305 || strcmp(str + strlen(str) - 5, "any2f") == 0
9306 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9307 && (regno & 1) != 0)
9308 as_warn(_("Condition code register should be even for %s, was %d"),
9310 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9311 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9312 && (regno & 3) != 0)
9313 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9316 ip->insn_opcode |= regno << OP_SH_BCC;
9318 ip->insn_opcode |= regno << OP_SH_CCC;
9322 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9333 while (ISDIGIT (*s));
9336 c = 8; /* Invalid sel value. */
9339 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9340 ip->insn_opcode |= c;
9344 /* Must be at least one digit. */
9345 my_getExpression (&imm_expr, s);
9346 check_absolute_expr (ip, &imm_expr);
9348 if ((unsigned long) imm_expr.X_add_number
9349 > (unsigned long) OP_MASK_VECBYTE)
9351 as_bad (_("bad byte vector index (%ld)"),
9352 (long) imm_expr.X_add_number);
9353 imm_expr.X_add_number = 0;
9356 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9357 imm_expr.X_op = O_absent;
9362 my_getExpression (&imm_expr, s);
9363 check_absolute_expr (ip, &imm_expr);
9365 if ((unsigned long) imm_expr.X_add_number
9366 > (unsigned long) OP_MASK_VECALIGN)
9368 as_bad (_("bad byte vector index (%ld)"),
9369 (long) imm_expr.X_add_number);
9370 imm_expr.X_add_number = 0;
9373 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9374 imm_expr.X_op = O_absent;
9379 as_bad (_("bad char = '%c'\n"), *args);
9384 /* Args don't match. */
9385 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9386 !strcmp (insn->name, insn[1].name))
9390 insn_error = _("illegal operands");
9395 insn_error = _("illegal operands");
9400 /* This routine assembles an instruction into its binary format when
9401 assembling for the mips16. As a side effect, it sets one of the
9402 global variables imm_reloc or offset_reloc to the type of
9403 relocation to do if one of the operands is an address expression.
9404 It also sets mips16_small and mips16_ext if the user explicitly
9405 requested a small or extended instruction. */
9408 mips16_ip (char *str, struct mips_cl_insn *ip)
9412 struct mips_opcode *insn;
9415 unsigned int lastregno = 0;
9420 mips16_small = FALSE;
9423 for (s = str; ISLOWER (*s); ++s)
9435 if (s[1] == 't' && s[2] == ' ')
9438 mips16_small = TRUE;
9442 else if (s[1] == 'e' && s[2] == ' ')
9451 insn_error = _("unknown opcode");
9455 if (mips_opts.noautoextend && ! mips16_ext)
9456 mips16_small = TRUE;
9458 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9460 insn_error = _("unrecognized opcode");
9467 assert (strcmp (insn->name, str) == 0);
9470 ip->insn_opcode = insn->match;
9471 ip->use_extend = FALSE;
9472 imm_expr.X_op = O_absent;
9473 imm_reloc[0] = BFD_RELOC_UNUSED;
9474 imm_reloc[1] = BFD_RELOC_UNUSED;
9475 imm_reloc[2] = BFD_RELOC_UNUSED;
9476 imm2_expr.X_op = O_absent;
9477 offset_expr.X_op = O_absent;
9478 offset_reloc[0] = BFD_RELOC_UNUSED;
9479 offset_reloc[1] = BFD_RELOC_UNUSED;
9480 offset_reloc[2] = BFD_RELOC_UNUSED;
9481 for (args = insn->args; 1; ++args)
9488 /* In this switch statement we call break if we did not find
9489 a match, continue if we did find a match, or return if we
9498 /* Stuff the immediate value in now, if we can. */
9499 if (imm_expr.X_op == O_constant
9500 && *imm_reloc > BFD_RELOC_UNUSED
9501 && insn->pinfo != INSN_MACRO)
9503 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9504 imm_expr.X_add_number, TRUE, mips16_small,
9505 mips16_ext, &ip->insn_opcode,
9506 &ip->use_extend, &ip->extend);
9507 imm_expr.X_op = O_absent;
9508 *imm_reloc = BFD_RELOC_UNUSED;
9522 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9525 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9541 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9543 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9570 while (ISDIGIT (*s));
9573 as_bad (_("invalid register number (%d)"), regno);
9579 if (s[1] == 'r' && s[2] == 'a')
9584 else if (s[1] == 'f' && s[2] == 'p')
9589 else if (s[1] == 's' && s[2] == 'p')
9594 else if (s[1] == 'g' && s[2] == 'p')
9599 else if (s[1] == 'a' && s[2] == 't')
9604 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9609 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9614 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9627 if (c == 'v' || c == 'w')
9629 regno = mips16_to_32_reg_map[lastregno];
9643 regno = mips32_to_16_reg_map[regno];
9648 regno = ILLEGAL_REG;
9653 regno = ILLEGAL_REG;
9658 regno = ILLEGAL_REG;
9663 if (regno == AT && ! mips_opts.noat)
9664 as_warn (_("used $at without \".set noat\""));
9671 if (regno == ILLEGAL_REG)
9678 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9682 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9685 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9688 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9694 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9697 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9698 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9708 if (strncmp (s, "$pc", 3) == 0)
9732 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9734 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9735 and generate the appropriate reloc. If the text
9736 inside %gprel is not a symbol name with an
9737 optional offset, then we generate a normal reloc
9738 and will probably fail later. */
9739 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9740 if (imm_expr.X_op == O_symbol)
9743 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9745 ip->use_extend = TRUE;
9752 /* Just pick up a normal expression. */
9753 my_getExpression (&imm_expr, s);
9756 if (imm_expr.X_op == O_register)
9758 /* What we thought was an expression turned out to
9761 if (s[0] == '(' && args[1] == '(')
9763 /* It looks like the expression was omitted
9764 before a register indirection, which means
9765 that the expression is implicitly zero. We
9766 still set up imm_expr, so that we handle
9767 explicit extensions correctly. */
9768 imm_expr.X_op = O_constant;
9769 imm_expr.X_add_number = 0;
9770 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9777 /* We need to relax this instruction. */
9778 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9787 /* We use offset_reloc rather than imm_reloc for the PC
9788 relative operands. This lets macros with both
9789 immediate and address operands work correctly. */
9790 my_getExpression (&offset_expr, s);
9792 if (offset_expr.X_op == O_register)
9795 /* We need to relax this instruction. */
9796 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9800 case '6': /* break code */
9801 my_getExpression (&imm_expr, s);
9802 check_absolute_expr (ip, &imm_expr);
9803 if ((unsigned long) imm_expr.X_add_number > 63)
9805 as_warn (_("Invalid value for `%s' (%lu)"),
9807 (unsigned long) imm_expr.X_add_number);
9808 imm_expr.X_add_number &= 0x3f;
9810 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9811 imm_expr.X_op = O_absent;
9815 case 'a': /* 26 bit address */
9816 my_getExpression (&offset_expr, s);
9818 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9819 ip->insn_opcode <<= 16;
9822 case 'l': /* register list for entry macro */
9823 case 'L': /* register list for exit macro */
9833 int freg, reg1, reg2;
9835 while (*s == ' ' || *s == ',')
9839 as_bad (_("can't parse register list"));
9851 while (ISDIGIT (*s))
9873 as_bad (_("invalid register list"));
9878 while (ISDIGIT (*s))
9885 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9890 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9895 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9896 mask |= (reg2 - 3) << 3;
9897 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9898 mask |= (reg2 - 15) << 1;
9899 else if (reg1 == RA && reg2 == RA)
9903 as_bad (_("invalid register list"));
9907 /* The mask is filled in in the opcode table for the
9908 benefit of the disassembler. We remove it before
9909 applying the actual mask. */
9910 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9911 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9915 case 'e': /* extend code */
9916 my_getExpression (&imm_expr, s);
9917 check_absolute_expr (ip, &imm_expr);
9918 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9920 as_warn (_("Invalid value for `%s' (%lu)"),
9922 (unsigned long) imm_expr.X_add_number);
9923 imm_expr.X_add_number &= 0x7ff;
9925 ip->insn_opcode |= imm_expr.X_add_number;
9926 imm_expr.X_op = O_absent;
9936 /* Args don't match. */
9937 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9938 strcmp (insn->name, insn[1].name) == 0)
9945 insn_error = _("illegal operands");
9951 /* This structure holds information we know about a mips16 immediate
9954 struct mips16_immed_operand
9956 /* The type code used in the argument string in the opcode table. */
9958 /* The number of bits in the short form of the opcode. */
9960 /* The number of bits in the extended form of the opcode. */
9962 /* The amount by which the short form is shifted when it is used;
9963 for example, the sw instruction has a shift count of 2. */
9965 /* The amount by which the short form is shifted when it is stored
9966 into the instruction code. */
9968 /* Non-zero if the short form is unsigned. */
9970 /* Non-zero if the extended form is unsigned. */
9972 /* Non-zero if the value is PC relative. */
9976 /* The mips16 immediate operand types. */
9978 static const struct mips16_immed_operand mips16_immed_operands[] =
9980 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9981 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9982 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9983 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9984 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9985 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9986 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9987 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9988 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9989 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9990 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9991 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9992 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9993 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9994 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9995 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9996 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9997 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9998 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9999 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10000 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10003 #define MIPS16_NUM_IMMED \
10004 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10006 /* Handle a mips16 instruction with an immediate value. This or's the
10007 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10008 whether an extended value is needed; if one is needed, it sets
10009 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10010 If SMALL is true, an unextended opcode was explicitly requested.
10011 If EXT is true, an extended opcode was explicitly requested. If
10012 WARN is true, warn if EXT does not match reality. */
10015 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10016 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10017 unsigned long *insn, bfd_boolean *use_extend,
10018 unsigned short *extend)
10020 register const struct mips16_immed_operand *op;
10021 int mintiny, maxtiny;
10022 bfd_boolean needext;
10024 op = mips16_immed_operands;
10025 while (op->type != type)
10028 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10033 if (type == '<' || type == '>' || type == '[' || type == ']')
10036 maxtiny = 1 << op->nbits;
10041 maxtiny = (1 << op->nbits) - 1;
10046 mintiny = - (1 << (op->nbits - 1));
10047 maxtiny = (1 << (op->nbits - 1)) - 1;
10050 /* Branch offsets have an implicit 0 in the lowest bit. */
10051 if (type == 'p' || type == 'q')
10054 if ((val & ((1 << op->shift) - 1)) != 0
10055 || val < (mintiny << op->shift)
10056 || val > (maxtiny << op->shift))
10061 if (warn && ext && ! needext)
10062 as_warn_where (file, line,
10063 _("extended operand requested but not required"));
10064 if (small && needext)
10065 as_bad_where (file, line, _("invalid unextended operand value"));
10067 if (small || (! ext && ! needext))
10071 *use_extend = FALSE;
10072 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10073 insnval <<= op->op_shift;
10078 long minext, maxext;
10084 maxext = (1 << op->extbits) - 1;
10088 minext = - (1 << (op->extbits - 1));
10089 maxext = (1 << (op->extbits - 1)) - 1;
10091 if (val < minext || val > maxext)
10092 as_bad_where (file, line,
10093 _("operand value out of range for instruction"));
10095 *use_extend = TRUE;
10096 if (op->extbits == 16)
10098 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10101 else if (op->extbits == 15)
10103 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10108 extval = ((val & 0x1f) << 6) | (val & 0x20);
10112 *extend = (unsigned short) extval;
10117 static const struct percent_op_match
10120 bfd_reloc_code_real_type reloc;
10123 {"%lo", BFD_RELOC_LO16},
10125 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10126 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10127 {"%call16", BFD_RELOC_MIPS_CALL16},
10128 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10129 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10130 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10131 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10132 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10133 {"%got", BFD_RELOC_MIPS_GOT16},
10134 {"%gp_rel", BFD_RELOC_GPREL16},
10135 {"%half", BFD_RELOC_16},
10136 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10137 {"%higher", BFD_RELOC_MIPS_HIGHER},
10138 {"%neg", BFD_RELOC_MIPS_SUB},
10140 {"%hi", BFD_RELOC_HI16_S}
10144 /* Return true if *STR points to a relocation operator. When returning true,
10145 move *STR over the operator and store its relocation code in *RELOC.
10146 Leave both *STR and *RELOC alone when returning false. */
10149 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10153 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10154 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10156 *str += strlen (percent_op[i].str);
10157 *reloc = percent_op[i].reloc;
10159 /* Check whether the output BFD supports this relocation.
10160 If not, issue an error and fall back on something safe. */
10161 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10163 as_bad ("relocation %s isn't supported by the current ABI",
10164 percent_op[i].str);
10165 *reloc = BFD_RELOC_LO16;
10173 /* Parse string STR as a 16-bit relocatable operand. Store the
10174 expression in *EP and the relocations in the array starting
10175 at RELOC. Return the number of relocation operators used.
10177 On exit, EXPR_END points to the first character after the expression.
10178 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10181 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10184 bfd_reloc_code_real_type reversed_reloc[3];
10185 size_t reloc_index, i;
10186 int crux_depth, str_depth;
10189 /* Search for the start of the main expression, recoding relocations
10190 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10191 of the main expression and with CRUX_DEPTH containing the number
10192 of open brackets at that point. */
10199 crux_depth = str_depth;
10201 /* Skip over whitespace and brackets, keeping count of the number
10203 while (*str == ' ' || *str == '\t' || *str == '(')
10208 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10209 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10211 my_getExpression (ep, crux);
10214 /* Match every open bracket. */
10215 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10219 if (crux_depth > 0)
10220 as_bad ("unclosed '('");
10224 if (reloc_index == 0)
10225 reloc[0] = BFD_RELOC_LO16;
10228 prev_reloc_op_frag = frag_now;
10229 for (i = 0; i < reloc_index; i++)
10230 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10233 return reloc_index;
10237 my_getExpression (expressionS *ep, char *str)
10242 save_in = input_line_pointer;
10243 input_line_pointer = str;
10245 expr_end = input_line_pointer;
10246 input_line_pointer = save_in;
10248 /* If we are in mips16 mode, and this is an expression based on `.',
10249 then we bump the value of the symbol by 1 since that is how other
10250 text symbols are handled. We don't bother to handle complex
10251 expressions, just `.' plus or minus a constant. */
10252 if (mips_opts.mips16
10253 && ep->X_op == O_symbol
10254 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10255 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10256 && symbol_get_frag (ep->X_add_symbol) == frag_now
10257 && symbol_constant_p (ep->X_add_symbol)
10258 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10259 S_SET_VALUE (ep->X_add_symbol, val + 1);
10262 /* Turn a string in input_line_pointer into a floating point constant
10263 of type TYPE, and store the appropriate bytes in *LITP. The number
10264 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10265 returned, or NULL on OK. */
10268 md_atof (int type, char *litP, int *sizeP)
10271 LITTLENUM_TYPE words[4];
10287 return _("bad call to md_atof");
10290 t = atof_ieee (input_line_pointer, type, words);
10292 input_line_pointer = t;
10296 if (! target_big_endian)
10298 for (i = prec - 1; i >= 0; i--)
10300 md_number_to_chars (litP, words[i], 2);
10306 for (i = 0; i < prec; i++)
10308 md_number_to_chars (litP, words[i], 2);
10317 md_number_to_chars (char *buf, valueT val, int n)
10319 if (target_big_endian)
10320 number_to_chars_bigendian (buf, val, n);
10322 number_to_chars_littleendian (buf, val, n);
10326 static int support_64bit_objects(void)
10328 const char **list, **l;
10331 list = bfd_target_list ();
10332 for (l = list; *l != NULL; l++)
10334 /* This is traditional mips */
10335 if (strcmp (*l, "elf64-tradbigmips") == 0
10336 || strcmp (*l, "elf64-tradlittlemips") == 0)
10338 if (strcmp (*l, "elf64-bigmips") == 0
10339 || strcmp (*l, "elf64-littlemips") == 0)
10342 yes = (*l != NULL);
10346 #endif /* OBJ_ELF */
10348 const char *md_shortopts = "O::g::G:";
10350 struct option md_longopts[] =
10352 /* Options which specify architecture. */
10353 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10354 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10355 {"march", required_argument, NULL, OPTION_MARCH},
10356 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10357 {"mtune", required_argument, NULL, OPTION_MTUNE},
10358 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10359 {"mips0", no_argument, NULL, OPTION_MIPS1},
10360 {"mips1", no_argument, NULL, OPTION_MIPS1},
10361 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10362 {"mips2", no_argument, NULL, OPTION_MIPS2},
10363 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10364 {"mips3", no_argument, NULL, OPTION_MIPS3},
10365 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10366 {"mips4", no_argument, NULL, OPTION_MIPS4},
10367 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10368 {"mips5", no_argument, NULL, OPTION_MIPS5},
10369 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10370 {"mips32", no_argument, NULL, OPTION_MIPS32},
10371 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10372 {"mips64", no_argument, NULL, OPTION_MIPS64},
10373 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10374 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10375 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10376 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10378 /* Options which specify Application Specific Extensions (ASEs). */
10379 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10380 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10381 {"mips16", no_argument, NULL, OPTION_MIPS16},
10382 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10383 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10384 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10385 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10386 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10387 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10388 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10389 {"mdmx", no_argument, NULL, OPTION_MDMX},
10390 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10391 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10393 /* Old-style architecture options. Don't add more of these. */
10394 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10395 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10396 {"m4650", no_argument, NULL, OPTION_M4650},
10397 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10398 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10399 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10400 {"m4010", no_argument, NULL, OPTION_M4010},
10401 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10402 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10403 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10404 {"m4100", no_argument, NULL, OPTION_M4100},
10405 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10406 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10407 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10408 {"m3900", no_argument, NULL, OPTION_M3900},
10409 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10410 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10412 /* Options which enable bug fixes. */
10413 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10414 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10415 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10416 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10417 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10418 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10419 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10420 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10421 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10422 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10424 /* Miscellaneous options. */
10425 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10426 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10427 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10428 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10429 {"trap", no_argument, NULL, OPTION_TRAP},
10430 {"no-break", no_argument, NULL, OPTION_TRAP},
10431 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10432 {"break", no_argument, NULL, OPTION_BREAK},
10433 {"no-trap", no_argument, NULL, OPTION_BREAK},
10434 #define OPTION_EB (OPTION_MISC_BASE + 3)
10435 {"EB", no_argument, NULL, OPTION_EB},
10436 #define OPTION_EL (OPTION_MISC_BASE + 4)
10437 {"EL", no_argument, NULL, OPTION_EL},
10438 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10439 {"mfp32", no_argument, NULL, OPTION_FP32},
10440 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10441 {"mgp32", no_argument, NULL, OPTION_GP32},
10442 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10443 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10444 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10445 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10446 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10447 {"mfp64", no_argument, NULL, OPTION_FP64},
10448 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10449 {"mgp64", no_argument, NULL, OPTION_GP64},
10450 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10451 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10452 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10453 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10455 /* ELF-specific options. */
10457 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10458 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10459 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10460 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10461 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10462 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10463 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10464 {"xgot", no_argument, NULL, OPTION_XGOT},
10465 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10466 {"mabi", required_argument, NULL, OPTION_MABI},
10467 #define OPTION_32 (OPTION_ELF_BASE + 4)
10468 {"32", no_argument, NULL, OPTION_32},
10469 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10470 {"n32", no_argument, NULL, OPTION_N32},
10471 #define OPTION_64 (OPTION_ELF_BASE + 6)
10472 {"64", no_argument, NULL, OPTION_64},
10473 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10474 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10475 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10476 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10477 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10478 {"mpdr", no_argument, NULL, OPTION_PDR},
10479 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10480 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10481 #endif /* OBJ_ELF */
10483 {NULL, no_argument, NULL, 0}
10485 size_t md_longopts_size = sizeof (md_longopts);
10487 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10488 NEW_VALUE. Warn if another value was already specified. Note:
10489 we have to defer parsing the -march and -mtune arguments in order
10490 to handle 'from-abi' correctly, since the ABI might be specified
10491 in a later argument. */
10494 mips_set_option_string (const char **string_ptr, const char *new_value)
10496 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10497 as_warn (_("A different %s was already specified, is now %s"),
10498 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10501 *string_ptr = new_value;
10505 md_parse_option (int c, char *arg)
10509 case OPTION_CONSTRUCT_FLOATS:
10510 mips_disable_float_construction = 0;
10513 case OPTION_NO_CONSTRUCT_FLOATS:
10514 mips_disable_float_construction = 1;
10526 target_big_endian = 1;
10530 target_big_endian = 0;
10534 if (arg && arg[1] == '0')
10544 mips_debug = atoi (arg);
10545 /* When the MIPS assembler sees -g or -g2, it does not do
10546 optimizations which limit full symbolic debugging. We take
10547 that to be equivalent to -O0. */
10548 if (mips_debug == 2)
10553 file_mips_isa = ISA_MIPS1;
10557 file_mips_isa = ISA_MIPS2;
10561 file_mips_isa = ISA_MIPS3;
10565 file_mips_isa = ISA_MIPS4;
10569 file_mips_isa = ISA_MIPS5;
10572 case OPTION_MIPS32:
10573 file_mips_isa = ISA_MIPS32;
10576 case OPTION_MIPS32R2:
10577 file_mips_isa = ISA_MIPS32R2;
10580 case OPTION_MIPS64R2:
10581 file_mips_isa = ISA_MIPS64R2;
10584 case OPTION_MIPS64:
10585 file_mips_isa = ISA_MIPS64;
10589 mips_set_option_string (&mips_tune_string, arg);
10593 mips_set_option_string (&mips_arch_string, arg);
10597 mips_set_option_string (&mips_arch_string, "4650");
10598 mips_set_option_string (&mips_tune_string, "4650");
10601 case OPTION_NO_M4650:
10605 mips_set_option_string (&mips_arch_string, "4010");
10606 mips_set_option_string (&mips_tune_string, "4010");
10609 case OPTION_NO_M4010:
10613 mips_set_option_string (&mips_arch_string, "4100");
10614 mips_set_option_string (&mips_tune_string, "4100");
10617 case OPTION_NO_M4100:
10621 mips_set_option_string (&mips_arch_string, "3900");
10622 mips_set_option_string (&mips_tune_string, "3900");
10625 case OPTION_NO_M3900:
10629 mips_opts.ase_mdmx = 1;
10632 case OPTION_NO_MDMX:
10633 mips_opts.ase_mdmx = 0;
10636 case OPTION_MIPS16:
10637 mips_opts.mips16 = 1;
10638 mips_no_prev_insn (FALSE);
10641 case OPTION_NO_MIPS16:
10642 mips_opts.mips16 = 0;
10643 mips_no_prev_insn (FALSE);
10646 case OPTION_MIPS3D:
10647 mips_opts.ase_mips3d = 1;
10650 case OPTION_NO_MIPS3D:
10651 mips_opts.ase_mips3d = 0;
10654 case OPTION_MEMBEDDED_PIC:
10655 mips_pic = EMBEDDED_PIC;
10656 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10658 as_bad (_("-G may not be used with embedded PIC code"));
10661 g_switch_value = 0x7fffffff;
10664 case OPTION_FIX_VR4122:
10665 mips_fix_4122_bugs = 1;
10668 case OPTION_NO_FIX_VR4122:
10669 mips_fix_4122_bugs = 0;
10672 case OPTION_RELAX_BRANCH:
10673 mips_relax_branch = 1;
10676 case OPTION_NO_RELAX_BRANCH:
10677 mips_relax_branch = 0;
10681 /* When generating ELF code, we permit -KPIC and -call_shared to
10682 select SVR4_PIC, and -non_shared to select no PIC. This is
10683 intended to be compatible with Irix 5. */
10684 case OPTION_CALL_SHARED:
10685 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10687 as_bad (_("-call_shared is supported only for ELF format"));
10690 mips_pic = SVR4_PIC;
10691 mips_abicalls = TRUE;
10692 if (g_switch_seen && g_switch_value != 0)
10694 as_bad (_("-G may not be used with SVR4 PIC code"));
10697 g_switch_value = 0;
10700 case OPTION_NON_SHARED:
10701 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10703 as_bad (_("-non_shared is supported only for ELF format"));
10707 mips_abicalls = FALSE;
10710 /* The -xgot option tells the assembler to use 32 offsets when
10711 accessing the got in SVR4_PIC mode. It is for Irix
10716 #endif /* OBJ_ELF */
10719 if (! USE_GLOBAL_POINTER_OPT)
10721 as_bad (_("-G is not supported for this configuration"));
10724 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10726 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10730 g_switch_value = atoi (arg);
10735 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10738 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10740 as_bad (_("-32 is supported for ELF format only"));
10743 mips_abi = O32_ABI;
10747 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10749 as_bad (_("-n32 is supported for ELF format only"));
10752 mips_abi = N32_ABI;
10756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10758 as_bad (_("-64 is supported for ELF format only"));
10761 mips_abi = N64_ABI;
10762 if (! support_64bit_objects())
10763 as_fatal (_("No compiled in support for 64 bit object file format"));
10765 #endif /* OBJ_ELF */
10768 file_mips_gp32 = 1;
10772 file_mips_gp32 = 0;
10776 file_mips_fp32 = 1;
10780 file_mips_fp32 = 0;
10785 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10787 as_bad (_("-mabi is supported for ELF format only"));
10790 if (strcmp (arg, "32") == 0)
10791 mips_abi = O32_ABI;
10792 else if (strcmp (arg, "o64") == 0)
10793 mips_abi = O64_ABI;
10794 else if (strcmp (arg, "n32") == 0)
10795 mips_abi = N32_ABI;
10796 else if (strcmp (arg, "64") == 0)
10798 mips_abi = N64_ABI;
10799 if (! support_64bit_objects())
10800 as_fatal (_("No compiled in support for 64 bit object file "
10803 else if (strcmp (arg, "eabi") == 0)
10804 mips_abi = EABI_ABI;
10807 as_fatal (_("invalid abi -mabi=%s"), arg);
10811 #endif /* OBJ_ELF */
10813 case OPTION_M7000_HILO_FIX:
10814 mips_7000_hilo_fix = TRUE;
10817 case OPTION_MNO_7000_HILO_FIX:
10818 mips_7000_hilo_fix = FALSE;
10822 case OPTION_MDEBUG:
10823 mips_flag_mdebug = TRUE;
10826 case OPTION_NO_MDEBUG:
10827 mips_flag_mdebug = FALSE;
10831 mips_flag_pdr = TRUE;
10834 case OPTION_NO_PDR:
10835 mips_flag_pdr = FALSE;
10837 #endif /* OBJ_ELF */
10846 /* Set up globals to generate code for the ISA or processor
10847 described by INFO. */
10850 mips_set_architecture (const struct mips_cpu_info *info)
10854 file_mips_arch = info->cpu;
10855 mips_opts.arch = info->cpu;
10856 mips_opts.isa = info->isa;
10861 /* Likewise for tuning. */
10864 mips_set_tune (const struct mips_cpu_info *info)
10867 mips_tune = info->cpu;
10872 mips_after_parse_args (void)
10874 const struct mips_cpu_info *arch_info = 0;
10875 const struct mips_cpu_info *tune_info = 0;
10877 /* GP relative stuff not working for PE */
10878 if (strncmp (TARGET_OS, "pe", 2) == 0
10879 && g_switch_value != 0)
10882 as_bad (_("-G not supported in this configuration."));
10883 g_switch_value = 0;
10886 if (mips_abi == NO_ABI)
10887 mips_abi = MIPS_DEFAULT_ABI;
10889 /* The following code determines the architecture and register size.
10890 Similar code was added to GCC 3.3 (see override_options() in
10891 config/mips/mips.c). The GAS and GCC code should be kept in sync
10892 as much as possible. */
10894 if (mips_arch_string != 0)
10895 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10897 if (file_mips_isa != ISA_UNKNOWN)
10899 /* Handle -mipsN. At this point, file_mips_isa contains the
10900 ISA level specified by -mipsN, while arch_info->isa contains
10901 the -march selection (if any). */
10902 if (arch_info != 0)
10904 /* -march takes precedence over -mipsN, since it is more descriptive.
10905 There's no harm in specifying both as long as the ISA levels
10907 if (file_mips_isa != arch_info->isa)
10908 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10909 mips_cpu_info_from_isa (file_mips_isa)->name,
10910 mips_cpu_info_from_isa (arch_info->isa)->name);
10913 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10916 if (arch_info == 0)
10917 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10919 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10920 as_bad ("-march=%s is not compatible with the selected ABI",
10923 mips_set_architecture (arch_info);
10925 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10926 if (mips_tune_string != 0)
10927 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10929 if (tune_info == 0)
10930 mips_set_tune (arch_info);
10932 mips_set_tune (tune_info);
10934 if (file_mips_gp32 >= 0)
10936 /* The user specified the size of the integer registers. Make sure
10937 it agrees with the ABI and ISA. */
10938 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10939 as_bad (_("-mgp64 used with a 32-bit processor"));
10940 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10941 as_bad (_("-mgp32 used with a 64-bit ABI"));
10942 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10943 as_bad (_("-mgp64 used with a 32-bit ABI"));
10947 /* Infer the integer register size from the ABI and processor.
10948 Restrict ourselves to 32-bit registers if that's all the
10949 processor has, or if the ABI cannot handle 64-bit registers. */
10950 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10951 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10954 /* ??? GAS treats single-float processors as though they had 64-bit
10955 float registers (although it complains when double-precision
10956 instructions are used). As things stand, saying they have 32-bit
10957 registers would lead to spurious "register must be even" messages.
10958 So here we assume float registers are always the same size as
10959 integer ones, unless the user says otherwise. */
10960 if (file_mips_fp32 < 0)
10961 file_mips_fp32 = file_mips_gp32;
10963 /* End of GCC-shared inference code. */
10965 /* This flag is set when we have a 64-bit capable CPU but use only
10966 32-bit wide registers. Note that EABI does not use it. */
10967 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10968 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10969 || mips_abi == O32_ABI))
10970 mips_32bitmode = 1;
10972 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10973 as_bad (_("trap exception not supported at ISA 1"));
10975 /* If the selected architecture includes support for ASEs, enable
10976 generation of code for them. */
10977 if (mips_opts.mips16 == -1)
10978 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10979 if (mips_opts.ase_mips3d == -1)
10980 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10981 if (mips_opts.ase_mdmx == -1)
10982 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10984 file_mips_isa = mips_opts.isa;
10985 file_ase_mips16 = mips_opts.mips16;
10986 file_ase_mips3d = mips_opts.ase_mips3d;
10987 file_ase_mdmx = mips_opts.ase_mdmx;
10988 mips_opts.gp32 = file_mips_gp32;
10989 mips_opts.fp32 = file_mips_fp32;
10991 if (mips_flag_mdebug < 0)
10993 #ifdef OBJ_MAYBE_ECOFF
10994 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10995 mips_flag_mdebug = 1;
10997 #endif /* OBJ_MAYBE_ECOFF */
10998 mips_flag_mdebug = 0;
11003 mips_init_after_args (void)
11005 /* initialize opcodes */
11006 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
11007 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
11011 md_pcrel_from (fixS *fixP)
11013 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11014 switch (fixP->fx_r_type)
11016 case BFD_RELOC_16_PCREL_S2:
11017 case BFD_RELOC_MIPS_JMP:
11018 /* Return the address of the delay slot. */
11025 /* This is called before the symbol table is processed. In order to
11026 work with gcc when using mips-tfile, we must keep all local labels.
11027 However, in other cases, we want to discard them. If we were
11028 called with -g, but we didn't see any debugging information, it may
11029 mean that gcc is smuggling debugging information through to
11030 mips-tfile, in which case we must generate all local labels. */
11033 mips_frob_file_before_adjust (void)
11035 #ifndef NO_ECOFF_DEBUGGING
11036 if (ECOFF_DEBUGGING
11038 && ! ecoff_debugging_seen)
11039 flag_keep_locals = 1;
11043 /* Sort any unmatched HI16_S relocs so that they immediately precede
11044 the corresponding LO reloc. This is called before md_apply_fix3 and
11045 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
11046 explicit use of the %hi modifier. */
11049 mips_frob_file (void)
11051 struct mips_hi_fixup *l;
11053 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
11055 segment_info_type *seginfo;
11058 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
11060 /* If a GOT16 relocation turns out to be against a global symbol,
11061 there isn't supposed to be a matching LO. */
11062 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11063 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
11066 /* Check quickly whether the next fixup happens to be a matching %lo. */
11067 if (fixup_has_matching_lo_p (l->fixp))
11070 /* Look through the fixups for this segment for a matching %lo.
11071 When we find one, move the %hi just in front of it. We do
11072 this in two passes. In the first pass, we try to find a
11073 unique %lo. In the second pass, we permit multiple %hi
11074 relocs for a single %lo (this is a GNU extension). */
11075 seginfo = seg_info (l->seg);
11076 for (pass = 0; pass < 2; pass++)
11081 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
11083 /* Check whether this is a %lo fixup which matches l->fixp. */
11084 if (f->fx_r_type == BFD_RELOC_LO16
11085 && f->fx_addsy == l->fixp->fx_addsy
11086 && f->fx_offset == l->fixp->fx_offset
11089 || !reloc_needs_lo_p (prev->fx_r_type)
11090 || !fixup_has_matching_lo_p (prev)))
11094 /* Move l->fixp before f. */
11095 for (pf = &seginfo->fix_root;
11097 pf = &(*pf)->fx_next)
11098 assert (*pf != NULL);
11100 *pf = l->fixp->fx_next;
11102 l->fixp->fx_next = f;
11104 seginfo->fix_root = l->fixp;
11106 prev->fx_next = l->fixp;
11117 #if 0 /* GCC code motion plus incomplete dead code elimination
11118 can leave a %hi without a %lo. */
11120 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
11121 _("Unmatched %%hi reloc"));
11127 /* When generating embedded PIC code we need to use a special
11128 relocation to represent the difference of two symbols in the .text
11129 section (switch tables use a difference of this sort). See
11130 include/coff/mips.h for details. This macro checks whether this
11131 fixup requires the special reloc. */
11132 #define SWITCH_TABLE(fixp) \
11133 ((fixp)->fx_r_type == BFD_RELOC_32 \
11134 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11135 && (fixp)->fx_addsy != NULL \
11136 && (fixp)->fx_subsy != NULL \
11137 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11138 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11140 /* When generating embedded PIC code we must keep all PC relative
11141 relocations, in case the linker has to relax a call. We also need
11142 to keep relocations for switch table entries.
11144 We may have combined relocations without symbols in the N32/N64 ABI.
11145 We have to prevent gas from dropping them. */
11148 mips_force_relocation (fixS *fixp)
11150 if (generic_force_reloc (fixp))
11154 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11155 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11156 || fixp->fx_r_type == BFD_RELOC_HI16_S
11157 || fixp->fx_r_type == BFD_RELOC_LO16))
11160 return (mips_pic == EMBEDDED_PIC
11162 || SWITCH_TABLE (fixp)
11163 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11164 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11167 /* This hook is called before a fix is simplified. We don't really
11168 decide whether to skip a fix here. Rather, we turn global symbols
11169 used as branch targets into local symbols, such that they undergo
11170 simplification. We can only do this if the symbol is defined and
11171 it is in the same section as the branch. If this doesn't hold, we
11172 emit a better error message than just saying the relocation is not
11173 valid for the selected object format.
11175 FIXP is the fix-up we're going to try to simplify, SEG is the
11176 segment in which the fix up occurs. The return value should be
11177 non-zero to indicate the fix-up is valid for further
11178 simplifications. */
11181 mips_validate_fix (struct fix *fixP, asection *seg)
11183 /* There's a lot of discussion on whether it should be possible to
11184 use R_MIPS_PC16 to represent branch relocations. The outcome
11185 seems to be that it can, but gas/bfd are very broken in creating
11186 RELA relocations for this, so for now we only accept branches to
11187 symbols in the same section. Anything else is of dubious value,
11188 since there's no guarantee that at link time the symbol would be
11189 in range. Even for branches to local symbols this is arguably
11190 wrong, since it we assume the symbol is not going to be
11191 overridden, which should be possible per ELF library semantics,
11192 but then, there isn't a dynamic relocation that could be used to
11193 this effect, and the target would likely be out of range as well.
11195 Unfortunately, it seems that there is too much code out there
11196 that relies on branches to symbols that are global to be resolved
11197 as if they were local, like the IRIX tools do, so we do it as
11198 well, but with a warning so that people are reminded to fix their
11199 code. If we ever get back to using R_MIPS_PC16 for branch
11200 targets, this entire block should go away (and probably the
11201 whole function). */
11203 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11204 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11205 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11206 && mips_pic != EMBEDDED_PIC)
11207 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11210 if (! S_IS_DEFINED (fixP->fx_addsy))
11212 as_bad_where (fixP->fx_file, fixP->fx_line,
11213 _("Cannot branch to undefined symbol."));
11214 /* Avoid any further errors about this fixup. */
11217 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11219 as_bad_where (fixP->fx_file, fixP->fx_line,
11220 _("Cannot branch to symbol in another section."));
11223 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11225 symbolS *sym = fixP->fx_addsy;
11227 if (mips_pic == SVR4_PIC)
11228 as_warn_where (fixP->fx_file, fixP->fx_line,
11229 _("Pretending global symbol used as branch target is local."));
11231 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11232 S_GET_SEGMENT (sym),
11234 symbol_get_frag (sym));
11235 copy_symbol_attributes (fixP->fx_addsy, sym);
11236 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11237 assert (symbol_resolved_p (sym));
11238 symbol_mark_resolved (fixP->fx_addsy);
11245 /* Apply a fixup to the object file. */
11248 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11252 static int previous_fx_r_type = 0;
11253 reloc_howto_type *howto;
11255 /* We ignore generic BFD relocations we don't know about. */
11256 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11260 assert (fixP->fx_size == 4
11261 || fixP->fx_r_type == BFD_RELOC_16
11262 || fixP->fx_r_type == BFD_RELOC_64
11263 || fixP->fx_r_type == BFD_RELOC_CTOR
11264 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11265 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11266 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11268 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11270 /* We are not done if this is a composite relocation to set up gp. */
11271 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11272 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11273 || (fixP->fx_r_type == BFD_RELOC_64
11274 && (previous_fx_r_type == BFD_RELOC_GPREL32
11275 || previous_fx_r_type == BFD_RELOC_GPREL16))
11276 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11277 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11278 || fixP->fx_r_type == BFD_RELOC_LO16))))
11280 previous_fx_r_type = fixP->fx_r_type;
11282 switch (fixP->fx_r_type)
11284 case BFD_RELOC_MIPS_JMP:
11285 case BFD_RELOC_MIPS_SHIFT5:
11286 case BFD_RELOC_MIPS_SHIFT6:
11287 case BFD_RELOC_MIPS_GOT_DISP:
11288 case BFD_RELOC_MIPS_GOT_PAGE:
11289 case BFD_RELOC_MIPS_GOT_OFST:
11290 case BFD_RELOC_MIPS_SUB:
11291 case BFD_RELOC_MIPS_INSERT_A:
11292 case BFD_RELOC_MIPS_INSERT_B:
11293 case BFD_RELOC_MIPS_DELETE:
11294 case BFD_RELOC_MIPS_HIGHEST:
11295 case BFD_RELOC_MIPS_HIGHER:
11296 case BFD_RELOC_MIPS_SCN_DISP:
11297 case BFD_RELOC_MIPS_REL16:
11298 case BFD_RELOC_MIPS_RELGOT:
11299 case BFD_RELOC_MIPS_JALR:
11300 case BFD_RELOC_HI16:
11301 case BFD_RELOC_HI16_S:
11302 case BFD_RELOC_GPREL16:
11303 case BFD_RELOC_MIPS_LITERAL:
11304 case BFD_RELOC_MIPS_CALL16:
11305 case BFD_RELOC_MIPS_GOT16:
11306 case BFD_RELOC_GPREL32:
11307 case BFD_RELOC_MIPS_GOT_HI16:
11308 case BFD_RELOC_MIPS_GOT_LO16:
11309 case BFD_RELOC_MIPS_CALL_HI16:
11310 case BFD_RELOC_MIPS_CALL_LO16:
11311 case BFD_RELOC_MIPS16_GPREL:
11312 if (fixP->fx_pcrel)
11313 as_bad_where (fixP->fx_file, fixP->fx_line,
11314 _("Invalid PC relative reloc"));
11315 /* Nothing needed to do. The value comes from the reloc entry */
11318 case BFD_RELOC_MIPS16_JMP:
11319 /* We currently always generate a reloc against a symbol, which
11320 means that we don't want an addend even if the symbol is
11325 case BFD_RELOC_PCREL_HI16_S:
11326 /* The addend for this is tricky if it is internal, so we just
11327 do everything here rather than in bfd_install_relocation. */
11328 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11331 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11333 /* For an external symbol adjust by the address to make it
11334 pcrel_offset. We use the address of the RELLO reloc
11335 which follows this one. */
11336 *valP += (fixP->fx_next->fx_frag->fr_address
11337 + fixP->fx_next->fx_where);
11339 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11340 if (target_big_endian)
11342 md_number_to_chars (buf, *valP, 2);
11345 case BFD_RELOC_PCREL_LO16:
11346 /* The addend for this is tricky if it is internal, so we just
11347 do everything here rather than in bfd_install_relocation. */
11348 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11351 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11352 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11353 if (target_big_endian)
11355 md_number_to_chars (buf, *valP, 2);
11359 /* This is handled like BFD_RELOC_32, but we output a sign
11360 extended value if we are only 32 bits. */
11362 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11364 if (8 <= sizeof (valueT))
11365 md_number_to_chars (buf, *valP, 8);
11370 if ((*valP & 0x80000000) != 0)
11374 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11376 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11382 case BFD_RELOC_RVA:
11384 /* If we are deleting this reloc entry, we must fill in the
11385 value now. This can happen if we have a .word which is not
11386 resolved when it appears but is later defined. We also need
11387 to fill in the value if this is an embedded PIC switch table
11390 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11391 md_number_to_chars (buf, *valP, 4);
11395 /* If we are deleting this reloc entry, we must fill in the
11397 assert (fixP->fx_size == 2);
11399 md_number_to_chars (buf, *valP, 2);
11402 case BFD_RELOC_LO16:
11403 /* When handling an embedded PIC switch statement, we can wind
11404 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11407 if (*valP + 0x8000 > 0xffff)
11408 as_bad_where (fixP->fx_file, fixP->fx_line,
11409 _("relocation overflow"));
11410 if (target_big_endian)
11412 md_number_to_chars (buf, *valP, 2);
11416 case BFD_RELOC_16_PCREL_S2:
11417 if ((*valP & 0x3) != 0)
11418 as_bad_where (fixP->fx_file, fixP->fx_line,
11419 _("Branch to odd address (%lx)"), (long) *valP);
11422 * We need to save the bits in the instruction since fixup_segment()
11423 * might be deleting the relocation entry (i.e., a branch within
11424 * the current segment).
11426 if (! fixP->fx_done)
11429 /* update old instruction data */
11430 if (target_big_endian)
11431 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11433 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11435 if (*valP + 0x20000 <= 0x3ffff)
11437 insn |= (*valP >> 2) & 0xffff;
11438 md_number_to_chars (buf, insn, 4);
11440 else if (mips_pic == NO_PIC
11442 && fixP->fx_frag->fr_address >= text_section->vma
11443 && (fixP->fx_frag->fr_address
11444 < text_section->vma + text_section->_raw_size)
11445 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11446 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11447 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11449 /* The branch offset is too large. If this is an
11450 unconditional branch, and we are not generating PIC code,
11451 we can convert it to an absolute jump instruction. */
11452 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11453 insn = 0x0c000000; /* jal */
11455 insn = 0x08000000; /* j */
11456 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11458 fixP->fx_addsy = section_symbol (text_section);
11459 *valP += md_pcrel_from (fixP);
11460 md_number_to_chars (buf, insn, 4);
11464 /* If we got here, we have branch-relaxation disabled,
11465 and there's nothing we can do to fix this instruction
11466 without turning it into a longer sequence. */
11467 as_bad_where (fixP->fx_file, fixP->fx_line,
11468 _("Branch out of range"));
11472 case BFD_RELOC_VTABLE_INHERIT:
11475 && !S_IS_DEFINED (fixP->fx_addsy)
11476 && !S_IS_WEAK (fixP->fx_addsy))
11477 S_SET_WEAK (fixP->fx_addsy);
11480 case BFD_RELOC_VTABLE_ENTRY:
11488 /* Remember value for tc_gen_reloc. */
11489 fixP->fx_addnumber = *valP;
11494 printInsn (unsigned long oc)
11496 const struct mips_opcode *p;
11497 int treg, sreg, dreg, shamt;
11502 for (i = 0; i < NUMOPCODES; ++i)
11504 p = &mips_opcodes[i];
11505 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11507 printf ("%08lx %s\t", oc, p->name);
11508 treg = (oc >> 16) & 0x1f;
11509 sreg = (oc >> 21) & 0x1f;
11510 dreg = (oc >> 11) & 0x1f;
11511 shamt = (oc >> 6) & 0x1f;
11513 for (args = p->args;; ++args)
11524 printf ("%c", *args);
11528 assert (treg == sreg);
11529 printf ("$%d,$%d", treg, sreg);
11534 printf ("$%d", dreg);
11539 printf ("$%d", treg);
11543 printf ("0x%x", treg);
11548 printf ("$%d", sreg);
11552 printf ("0x%08lx", oc & 0x1ffffff);
11559 printf ("%d", imm);
11564 printf ("$%d", shamt);
11575 printf (_("%08lx UNDEFINED\n"), oc);
11586 name = input_line_pointer;
11587 c = get_symbol_end ();
11588 p = (symbolS *) symbol_find_or_make (name);
11589 *input_line_pointer = c;
11593 /* Align the current frag to a given power of two. The MIPS assembler
11594 also automatically adjusts any preceding label. */
11597 mips_align (int to, int fill, symbolS *label)
11599 mips_emit_delays (FALSE);
11600 frag_align (to, fill, 0);
11601 record_alignment (now_seg, to);
11604 assert (S_GET_SEGMENT (label) == now_seg);
11605 symbol_set_frag (label, frag_now);
11606 S_SET_VALUE (label, (valueT) frag_now_fix ());
11610 /* Align to a given power of two. .align 0 turns off the automatic
11611 alignment used by the data creating pseudo-ops. */
11614 s_align (int x ATTRIBUTE_UNUSED)
11617 register long temp_fill;
11618 long max_alignment = 15;
11622 o Note that the assembler pulls down any immediately preceding label
11623 to the aligned address.
11624 o It's not documented but auto alignment is reinstated by
11625 a .align pseudo instruction.
11626 o Note also that after auto alignment is turned off the mips assembler
11627 issues an error on attempt to assemble an improperly aligned data item.
11632 temp = get_absolute_expression ();
11633 if (temp > max_alignment)
11634 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11637 as_warn (_("Alignment negative: 0 assumed."));
11640 if (*input_line_pointer == ',')
11642 ++input_line_pointer;
11643 temp_fill = get_absolute_expression ();
11650 mips_align (temp, (int) temp_fill,
11651 insn_labels != NULL ? insn_labels->label : NULL);
11658 demand_empty_rest_of_line ();
11662 mips_flush_pending_output (void)
11664 mips_emit_delays (FALSE);
11665 mips_clear_insn_labels ();
11669 s_change_sec (int sec)
11673 /* When generating embedded PIC code, we only use the .text, .lit8,
11674 .sdata and .sbss sections. We change the .data and .rdata
11675 pseudo-ops to use .sdata. */
11676 if (mips_pic == EMBEDDED_PIC
11677 && (sec == 'd' || sec == 'r'))
11681 /* The ELF backend needs to know that we are changing sections, so
11682 that .previous works correctly. We could do something like check
11683 for an obj_section_change_hook macro, but that might be confusing
11684 as it would not be appropriate to use it in the section changing
11685 functions in read.c, since obj-elf.c intercepts those. FIXME:
11686 This should be cleaner, somehow. */
11687 obj_elf_section_change_hook ();
11690 mips_emit_delays (FALSE);
11700 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11701 demand_empty_rest_of_line ();
11705 if (USE_GLOBAL_POINTER_OPT)
11707 seg = subseg_new (RDATA_SECTION_NAME,
11708 (subsegT) get_absolute_expression ());
11709 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11711 bfd_set_section_flags (stdoutput, seg,
11717 if (strcmp (TARGET_OS, "elf") != 0)
11718 record_alignment (seg, 4);
11720 demand_empty_rest_of_line ();
11724 as_bad (_("No read only data section in this object file format"));
11725 demand_empty_rest_of_line ();
11731 if (USE_GLOBAL_POINTER_OPT)
11733 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11734 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11736 bfd_set_section_flags (stdoutput, seg,
11737 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11739 if (strcmp (TARGET_OS, "elf") != 0)
11740 record_alignment (seg, 4);
11742 demand_empty_rest_of_line ();
11747 as_bad (_("Global pointers not supported; recompile -G 0"));
11748 demand_empty_rest_of_line ();
11757 s_change_section (int ignore ATTRIBUTE_UNUSED)
11760 char *section_name;
11765 int section_entry_size;
11766 int section_alignment;
11768 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11771 section_name = input_line_pointer;
11772 c = get_symbol_end ();
11774 next_c = *(input_line_pointer + 1);
11776 /* Do we have .section Name<,"flags">? */
11777 if (c != ',' || (c == ',' && next_c == '"'))
11779 /* just after name is now '\0'. */
11780 *input_line_pointer = c;
11781 input_line_pointer = section_name;
11782 obj_elf_section (ignore);
11785 input_line_pointer++;
11787 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11789 section_type = get_absolute_expression ();
11792 if (*input_line_pointer++ == ',')
11793 section_flag = get_absolute_expression ();
11796 if (*input_line_pointer++ == ',')
11797 section_entry_size = get_absolute_expression ();
11799 section_entry_size = 0;
11800 if (*input_line_pointer++ == ',')
11801 section_alignment = get_absolute_expression ();
11803 section_alignment = 0;
11805 section_name = xstrdup (section_name);
11807 /* When using the generic form of .section (as implemented by obj-elf.c),
11808 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11809 traditionally had to fall back on the more common @progbits instead.
11811 There's nothing really harmful in this, since bfd will correct
11812 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11813 means that, for backwards compatibiltiy, the special_section entries
11814 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11816 Even so, we shouldn't force users of the MIPS .section syntax to
11817 incorrectly label the sections as SHT_PROGBITS. The best compromise
11818 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11819 generic type-checking code. */
11820 if (section_type == SHT_MIPS_DWARF)
11821 section_type = SHT_PROGBITS;
11823 obj_elf_change_section (section_name, section_type, section_flag,
11824 section_entry_size, 0, 0, 0);
11826 if (now_seg->name != section_name)
11827 free (section_name);
11828 #endif /* OBJ_ELF */
11832 mips_enable_auto_align (void)
11838 s_cons (int log_size)
11842 label = insn_labels != NULL ? insn_labels->label : NULL;
11843 mips_emit_delays (FALSE);
11844 if (log_size > 0 && auto_align)
11845 mips_align (log_size, 0, label);
11846 mips_clear_insn_labels ();
11847 cons (1 << log_size);
11851 s_float_cons (int type)
11855 label = insn_labels != NULL ? insn_labels->label : NULL;
11857 mips_emit_delays (FALSE);
11862 mips_align (3, 0, label);
11864 mips_align (2, 0, label);
11867 mips_clear_insn_labels ();
11872 /* Handle .globl. We need to override it because on Irix 5 you are
11875 where foo is an undefined symbol, to mean that foo should be
11876 considered to be the address of a function. */
11879 s_mips_globl (int x ATTRIBUTE_UNUSED)
11886 name = input_line_pointer;
11887 c = get_symbol_end ();
11888 symbolP = symbol_find_or_make (name);
11889 *input_line_pointer = c;
11890 SKIP_WHITESPACE ();
11892 /* On Irix 5, every global symbol that is not explicitly labelled as
11893 being a function is apparently labelled as being an object. */
11896 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11901 secname = input_line_pointer;
11902 c = get_symbol_end ();
11903 sec = bfd_get_section_by_name (stdoutput, secname);
11905 as_bad (_("%s: no such section"), secname);
11906 *input_line_pointer = c;
11908 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11909 flag = BSF_FUNCTION;
11912 symbol_get_bfdsym (symbolP)->flags |= flag;
11914 S_SET_EXTERNAL (symbolP);
11915 demand_empty_rest_of_line ();
11919 s_option (int x ATTRIBUTE_UNUSED)
11924 opt = input_line_pointer;
11925 c = get_symbol_end ();
11929 /* FIXME: What does this mean? */
11931 else if (strncmp (opt, "pic", 3) == 0)
11935 i = atoi (opt + 3);
11940 mips_pic = SVR4_PIC;
11941 mips_abicalls = TRUE;
11944 as_bad (_(".option pic%d not supported"), i);
11946 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11948 if (g_switch_seen && g_switch_value != 0)
11949 as_warn (_("-G may not be used with SVR4 PIC code"));
11950 g_switch_value = 0;
11951 bfd_set_gp_size (stdoutput, 0);
11955 as_warn (_("Unrecognized option \"%s\""), opt);
11957 *input_line_pointer = c;
11958 demand_empty_rest_of_line ();
11961 /* This structure is used to hold a stack of .set values. */
11963 struct mips_option_stack
11965 struct mips_option_stack *next;
11966 struct mips_set_options options;
11969 static struct mips_option_stack *mips_opts_stack;
11971 /* Handle the .set pseudo-op. */
11974 s_mipsset (int x ATTRIBUTE_UNUSED)
11976 char *name = input_line_pointer, ch;
11978 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11979 ++input_line_pointer;
11980 ch = *input_line_pointer;
11981 *input_line_pointer = '\0';
11983 if (strcmp (name, "reorder") == 0)
11985 if (mips_opts.noreorder && prev_nop_frag != NULL)
11987 /* If we still have pending nops, we can discard them. The
11988 usual nop handling will insert any that are still
11990 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11991 * (mips_opts.mips16 ? 2 : 4));
11992 prev_nop_frag = NULL;
11994 mips_opts.noreorder = 0;
11996 else if (strcmp (name, "noreorder") == 0)
11998 mips_emit_delays (TRUE);
11999 mips_opts.noreorder = 1;
12000 mips_any_noreorder = 1;
12002 else if (strcmp (name, "at") == 0)
12004 mips_opts.noat = 0;
12006 else if (strcmp (name, "noat") == 0)
12008 mips_opts.noat = 1;
12010 else if (strcmp (name, "macro") == 0)
12012 mips_opts.warn_about_macros = 0;
12014 else if (strcmp (name, "nomacro") == 0)
12016 if (mips_opts.noreorder == 0)
12017 as_bad (_("`noreorder' must be set before `nomacro'"));
12018 mips_opts.warn_about_macros = 1;
12020 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12022 mips_opts.nomove = 0;
12024 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12026 mips_opts.nomove = 1;
12028 else if (strcmp (name, "bopt") == 0)
12030 mips_opts.nobopt = 0;
12032 else if (strcmp (name, "nobopt") == 0)
12034 mips_opts.nobopt = 1;
12036 else if (strcmp (name, "mips16") == 0
12037 || strcmp (name, "MIPS-16") == 0)
12038 mips_opts.mips16 = 1;
12039 else if (strcmp (name, "nomips16") == 0
12040 || strcmp (name, "noMIPS-16") == 0)
12041 mips_opts.mips16 = 0;
12042 else if (strcmp (name, "mips3d") == 0)
12043 mips_opts.ase_mips3d = 1;
12044 else if (strcmp (name, "nomips3d") == 0)
12045 mips_opts.ase_mips3d = 0;
12046 else if (strcmp (name, "mdmx") == 0)
12047 mips_opts.ase_mdmx = 1;
12048 else if (strcmp (name, "nomdmx") == 0)
12049 mips_opts.ase_mdmx = 0;
12050 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12054 /* Permit the user to change the ISA and architecture on the fly.
12055 Needless to say, misuse can cause serious problems. */
12056 if (strcmp (name, "mips0") == 0)
12059 mips_opts.isa = file_mips_isa;
12061 else if (strcmp (name, "mips1") == 0)
12062 mips_opts.isa = ISA_MIPS1;
12063 else if (strcmp (name, "mips2") == 0)
12064 mips_opts.isa = ISA_MIPS2;
12065 else if (strcmp (name, "mips3") == 0)
12066 mips_opts.isa = ISA_MIPS3;
12067 else if (strcmp (name, "mips4") == 0)
12068 mips_opts.isa = ISA_MIPS4;
12069 else if (strcmp (name, "mips5") == 0)
12070 mips_opts.isa = ISA_MIPS5;
12071 else if (strcmp (name, "mips32") == 0)
12072 mips_opts.isa = ISA_MIPS32;
12073 else if (strcmp (name, "mips32r2") == 0)
12074 mips_opts.isa = ISA_MIPS32R2;
12075 else if (strcmp (name, "mips64") == 0)
12076 mips_opts.isa = ISA_MIPS64;
12077 else if (strcmp (name, "mips64r2") == 0)
12078 mips_opts.isa = ISA_MIPS64R2;
12079 else if (strcmp (name, "arch=default") == 0)
12082 mips_opts.arch = file_mips_arch;
12083 mips_opts.isa = file_mips_isa;
12085 else if (strncmp (name, "arch=", 5) == 0)
12087 const struct mips_cpu_info *p;
12089 p = mips_parse_cpu("internal use", name + 5);
12091 as_bad (_("unknown architecture %s"), name + 5);
12094 mips_opts.arch = p->cpu;
12095 mips_opts.isa = p->isa;
12099 as_bad (_("unknown ISA level %s"), name + 4);
12101 switch (mips_opts.isa)
12109 mips_opts.gp32 = 1;
12110 mips_opts.fp32 = 1;
12117 mips_opts.gp32 = 0;
12118 mips_opts.fp32 = 0;
12121 as_bad (_("unknown ISA level %s"), name + 4);
12126 mips_opts.gp32 = file_mips_gp32;
12127 mips_opts.fp32 = file_mips_fp32;
12130 else if (strcmp (name, "autoextend") == 0)
12131 mips_opts.noautoextend = 0;
12132 else if (strcmp (name, "noautoextend") == 0)
12133 mips_opts.noautoextend = 1;
12134 else if (strcmp (name, "push") == 0)
12136 struct mips_option_stack *s;
12138 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12139 s->next = mips_opts_stack;
12140 s->options = mips_opts;
12141 mips_opts_stack = s;
12143 else if (strcmp (name, "pop") == 0)
12145 struct mips_option_stack *s;
12147 s = mips_opts_stack;
12149 as_bad (_(".set pop with no .set push"));
12152 /* If we're changing the reorder mode we need to handle
12153 delay slots correctly. */
12154 if (s->options.noreorder && ! mips_opts.noreorder)
12155 mips_emit_delays (TRUE);
12156 else if (! s->options.noreorder && mips_opts.noreorder)
12158 if (prev_nop_frag != NULL)
12160 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12161 * (mips_opts.mips16 ? 2 : 4));
12162 prev_nop_frag = NULL;
12166 mips_opts = s->options;
12167 mips_opts_stack = s->next;
12173 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12175 *input_line_pointer = ch;
12176 demand_empty_rest_of_line ();
12179 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12180 .option pic2. It means to generate SVR4 PIC calls. */
12183 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12185 mips_pic = SVR4_PIC;
12186 mips_abicalls = TRUE;
12187 if (USE_GLOBAL_POINTER_OPT)
12189 if (g_switch_seen && g_switch_value != 0)
12190 as_warn (_("-G may not be used with SVR4 PIC code"));
12191 g_switch_value = 0;
12193 bfd_set_gp_size (stdoutput, 0);
12194 demand_empty_rest_of_line ();
12197 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12198 PIC code. It sets the $gp register for the function based on the
12199 function address, which is in the register named in the argument.
12200 This uses a relocation against _gp_disp, which is handled specially
12201 by the linker. The result is:
12202 lui $gp,%hi(_gp_disp)
12203 addiu $gp,$gp,%lo(_gp_disp)
12204 addu $gp,$gp,.cpload argument
12205 The .cpload argument is normally $25 == $t9. */
12208 s_cpload (int ignore ATTRIBUTE_UNUSED)
12213 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12214 .cpload is ignored. */
12215 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12221 /* .cpload should be in a .set noreorder section. */
12222 if (mips_opts.noreorder == 0)
12223 as_warn (_(".cpload not in noreorder section"));
12225 ex.X_op = O_symbol;
12226 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12227 ex.X_op_symbol = NULL;
12228 ex.X_add_number = 0;
12230 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12231 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12233 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12234 macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
12235 mips_gp_register, BFD_RELOC_LO16);
12237 macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
12238 mips_gp_register, tc_get_register (0));
12240 demand_empty_rest_of_line ();
12243 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12244 .cpsetup $reg1, offset|$reg2, label
12246 If offset is given, this results in:
12247 sd $gp, offset($sp)
12248 lui $gp, %hi(%neg(%gp_rel(label)))
12249 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12250 daddu $gp, $gp, $reg1
12252 If $reg2 is given, this results in:
12253 daddu $reg2, $gp, $0
12254 lui $gp, %hi(%neg(%gp_rel(label)))
12255 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12256 daddu $gp, $gp, $reg1
12257 $reg1 is normally $25 == $t9. */
12259 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12261 expressionS ex_off;
12262 expressionS ex_sym;
12267 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12268 We also need NewABI support. */
12269 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12275 reg1 = tc_get_register (0);
12276 SKIP_WHITESPACE ();
12277 if (*input_line_pointer != ',')
12279 as_bad (_("missing argument separator ',' for .cpsetup"));
12283 ++input_line_pointer;
12284 SKIP_WHITESPACE ();
12285 if (*input_line_pointer == '$')
12287 mips_cpreturn_register = tc_get_register (0);
12288 mips_cpreturn_offset = -1;
12292 mips_cpreturn_offset = get_absolute_expression ();
12293 mips_cpreturn_register = -1;
12295 SKIP_WHITESPACE ();
12296 if (*input_line_pointer != ',')
12298 as_bad (_("missing argument separator ',' for .cpsetup"));
12302 ++input_line_pointer;
12303 SKIP_WHITESPACE ();
12304 expression (&ex_sym);
12306 if (mips_cpreturn_register == -1)
12308 ex_off.X_op = O_constant;
12309 ex_off.X_add_symbol = NULL;
12310 ex_off.X_op_symbol = NULL;
12311 ex_off.X_add_number = mips_cpreturn_offset;
12313 macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
12314 BFD_RELOC_LO16, SP);
12317 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
12318 mips_gp_register, 0);
12320 /* Ensure there's room for the next two instructions, so that `f'
12321 doesn't end up with an address in the wrong frag. */
12324 macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12325 BFD_RELOC_GPREL16);
12326 fix_new (frag_now, f - frag_now->fr_literal,
12327 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12328 fix_new (frag_now, f - frag_now->fr_literal,
12329 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12332 macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
12333 mips_gp_register, BFD_RELOC_GPREL16);
12334 fix_new (frag_now, f - frag_now->fr_literal,
12335 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12336 fix_new (frag_now, f - frag_now->fr_literal,
12337 4, NULL, 0, 0, BFD_RELOC_LO16);
12339 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12340 mips_gp_register, reg1);
12342 demand_empty_rest_of_line ();
12346 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12348 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12349 .cplocal is ignored. */
12350 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12356 mips_gp_register = tc_get_register (0);
12357 demand_empty_rest_of_line ();
12360 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12361 offset from $sp. The offset is remembered, and after making a PIC
12362 call $gp is restored from that location. */
12365 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12370 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12371 .cprestore is ignored. */
12372 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12378 mips_cprestore_offset = get_absolute_expression ();
12379 mips_cprestore_valid = 1;
12381 ex.X_op = O_constant;
12382 ex.X_add_symbol = NULL;
12383 ex.X_op_symbol = NULL;
12384 ex.X_add_number = mips_cprestore_offset;
12386 macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
12387 mips_gp_register, SP, HAVE_64BIT_ADDRESSES);
12389 demand_empty_rest_of_line ();
12392 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12393 was given in the preceding .cpsetup, it results in:
12394 ld $gp, offset($sp)
12396 If a register $reg2 was given there, it results in:
12397 daddu $gp, $reg2, $0
12400 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12405 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12406 We also need NewABI support. */
12407 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12413 if (mips_cpreturn_register == -1)
12415 ex.X_op = O_constant;
12416 ex.X_add_symbol = NULL;
12417 ex.X_op_symbol = NULL;
12418 ex.X_add_number = mips_cpreturn_offset;
12420 macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
12421 BFD_RELOC_LO16, SP);
12424 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
12425 mips_cpreturn_register, 0);
12427 demand_empty_rest_of_line ();
12430 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12431 code. It sets the offset to use in gp_rel relocations. */
12434 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12436 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12437 We also need NewABI support. */
12438 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12444 mips_gprel_offset = get_absolute_expression ();
12446 demand_empty_rest_of_line ();
12449 /* Handle the .gpword pseudo-op. This is used when generating PIC
12450 code. It generates a 32 bit GP relative reloc. */
12453 s_gpword (int ignore ATTRIBUTE_UNUSED)
12459 /* When not generating PIC code, this is treated as .word. */
12460 if (mips_pic != SVR4_PIC)
12466 label = insn_labels != NULL ? insn_labels->label : NULL;
12467 mips_emit_delays (TRUE);
12469 mips_align (2, 0, label);
12470 mips_clear_insn_labels ();
12474 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12476 as_bad (_("Unsupported use of .gpword"));
12477 ignore_rest_of_line ();
12481 md_number_to_chars (p, 0, 4);
12482 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12483 BFD_RELOC_GPREL32);
12485 demand_empty_rest_of_line ();
12489 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12495 /* When not generating PIC code, this is treated as .dword. */
12496 if (mips_pic != SVR4_PIC)
12502 label = insn_labels != NULL ? insn_labels->label : NULL;
12503 mips_emit_delays (TRUE);
12505 mips_align (3, 0, label);
12506 mips_clear_insn_labels ();
12510 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12512 as_bad (_("Unsupported use of .gpdword"));
12513 ignore_rest_of_line ();
12517 md_number_to_chars (p, 0, 8);
12518 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12519 BFD_RELOC_GPREL32);
12521 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12522 ex.X_op = O_absent;
12523 ex.X_add_symbol = 0;
12524 ex.X_add_number = 0;
12525 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12528 demand_empty_rest_of_line ();
12531 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12532 tables in SVR4 PIC code. */
12535 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12540 /* This is ignored when not generating SVR4 PIC code. */
12541 if (mips_pic != SVR4_PIC)
12547 /* Add $gp to the register named as an argument. */
12548 reg = tc_get_register (0);
12549 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
12550 reg, reg, mips_gp_register);
12552 demand_empty_rest_of_line ();
12555 /* Handle the .insn pseudo-op. This marks instruction labels in
12556 mips16 mode. This permits the linker to handle them specially,
12557 such as generating jalx instructions when needed. We also make
12558 them odd for the duration of the assembly, in order to generate the
12559 right sort of code. We will make them even in the adjust_symtab
12560 routine, while leaving them marked. This is convenient for the
12561 debugger and the disassembler. The linker knows to make them odd
12565 s_insn (int ignore ATTRIBUTE_UNUSED)
12567 mips16_mark_labels ();
12569 demand_empty_rest_of_line ();
12572 /* Handle a .stabn directive. We need these in order to mark a label
12573 as being a mips16 text label correctly. Sometimes the compiler
12574 will emit a label, followed by a .stabn, and then switch sections.
12575 If the label and .stabn are in mips16 mode, then the label is
12576 really a mips16 text label. */
12579 s_mips_stab (int type)
12582 mips16_mark_labels ();
12587 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12591 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12598 name = input_line_pointer;
12599 c = get_symbol_end ();
12600 symbolP = symbol_find_or_make (name);
12601 S_SET_WEAK (symbolP);
12602 *input_line_pointer = c;
12604 SKIP_WHITESPACE ();
12606 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12608 if (S_IS_DEFINED (symbolP))
12610 as_bad ("ignoring attempt to redefine symbol %s",
12611 S_GET_NAME (symbolP));
12612 ignore_rest_of_line ();
12616 if (*input_line_pointer == ',')
12618 ++input_line_pointer;
12619 SKIP_WHITESPACE ();
12623 if (exp.X_op != O_symbol)
12625 as_bad ("bad .weakext directive");
12626 ignore_rest_of_line ();
12629 symbol_set_value_expression (symbolP, &exp);
12632 demand_empty_rest_of_line ();
12635 /* Parse a register string into a number. Called from the ECOFF code
12636 to parse .frame. The argument is non-zero if this is the frame
12637 register, so that we can record it in mips_frame_reg. */
12640 tc_get_register (int frame)
12644 SKIP_WHITESPACE ();
12645 if (*input_line_pointer++ != '$')
12647 as_warn (_("expected `$'"));
12650 else if (ISDIGIT (*input_line_pointer))
12652 reg = get_absolute_expression ();
12653 if (reg < 0 || reg >= 32)
12655 as_warn (_("Bad register number"));
12661 if (strncmp (input_line_pointer, "ra", 2) == 0)
12664 input_line_pointer += 2;
12666 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12669 input_line_pointer += 2;
12671 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12674 input_line_pointer += 2;
12676 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12679 input_line_pointer += 2;
12681 else if (strncmp (input_line_pointer, "at", 2) == 0)
12684 input_line_pointer += 2;
12686 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12689 input_line_pointer += 3;
12691 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12694 input_line_pointer += 3;
12696 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12699 input_line_pointer += 4;
12703 as_warn (_("Unrecognized register name"));
12705 while (ISALNUM(*input_line_pointer))
12706 input_line_pointer++;
12711 mips_frame_reg = reg != 0 ? reg : SP;
12712 mips_frame_reg_valid = 1;
12713 mips_cprestore_valid = 0;
12719 md_section_align (asection *seg, valueT addr)
12721 int align = bfd_get_section_alignment (stdoutput, seg);
12724 /* We don't need to align ELF sections to the full alignment.
12725 However, Irix 5 may prefer that we align them at least to a 16
12726 byte boundary. We don't bother to align the sections if we are
12727 targeted for an embedded system. */
12728 if (strcmp (TARGET_OS, "elf") == 0)
12734 return ((addr + (1 << align) - 1) & (-1 << align));
12737 /* Utility routine, called from above as well. If called while the
12738 input file is still being read, it's only an approximation. (For
12739 example, a symbol may later become defined which appeared to be
12740 undefined earlier.) */
12743 nopic_need_relax (symbolS *sym, int before_relaxing)
12748 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12750 const char *symname;
12753 /* Find out whether this symbol can be referenced off the $gp
12754 register. It can be if it is smaller than the -G size or if
12755 it is in the .sdata or .sbss section. Certain symbols can
12756 not be referenced off the $gp, although it appears as though
12758 symname = S_GET_NAME (sym);
12759 if (symname != (const char *) NULL
12760 && (strcmp (symname, "eprol") == 0
12761 || strcmp (symname, "etext") == 0
12762 || strcmp (symname, "_gp") == 0
12763 || strcmp (symname, "edata") == 0
12764 || strcmp (symname, "_fbss") == 0
12765 || strcmp (symname, "_fdata") == 0
12766 || strcmp (symname, "_ftext") == 0
12767 || strcmp (symname, "end") == 0
12768 || strcmp (symname, "_gp_disp") == 0))
12770 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12772 #ifndef NO_ECOFF_DEBUGGING
12773 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12774 && (symbol_get_obj (sym)->ecoff_extern_size
12775 <= g_switch_value))
12777 /* We must defer this decision until after the whole
12778 file has been read, since there might be a .extern
12779 after the first use of this symbol. */
12780 || (before_relaxing
12781 #ifndef NO_ECOFF_DEBUGGING
12782 && symbol_get_obj (sym)->ecoff_extern_size == 0
12784 && S_GET_VALUE (sym) == 0)
12785 || (S_GET_VALUE (sym) != 0
12786 && S_GET_VALUE (sym) <= g_switch_value)))
12790 const char *segname;
12792 segname = segment_name (S_GET_SEGMENT (sym));
12793 assert (strcmp (segname, ".lit8") != 0
12794 && strcmp (segname, ".lit4") != 0);
12795 change = (strcmp (segname, ".sdata") != 0
12796 && strcmp (segname, ".sbss") != 0
12797 && strncmp (segname, ".sdata.", 7) != 0
12798 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12803 /* We are not optimizing for the $gp register. */
12808 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12811 pic_need_relax (symbolS *sym, asection *segtype)
12814 bfd_boolean linkonce;
12816 /* Handle the case of a symbol equated to another symbol. */
12817 while (symbol_equated_reloc_p (sym))
12821 /* It's possible to get a loop here in a badly written
12823 n = symbol_get_value_expression (sym)->X_add_symbol;
12829 symsec = S_GET_SEGMENT (sym);
12831 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12833 if (symsec != segtype && ! S_IS_LOCAL (sym))
12835 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12839 /* The GNU toolchain uses an extension for ELF: a section
12840 beginning with the magic string .gnu.linkonce is a linkonce
12842 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12843 sizeof ".gnu.linkonce" - 1) == 0)
12847 /* This must duplicate the test in adjust_reloc_syms. */
12848 return (symsec != &bfd_und_section
12849 && symsec != &bfd_abs_section
12850 && ! bfd_is_com_section (symsec)
12853 /* A global or weak symbol is treated as external. */
12854 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12855 || (! S_IS_WEAK (sym)
12856 && (! S_IS_EXTERNAL (sym)
12857 || mips_pic == EMBEDDED_PIC)))
12863 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12864 extended opcode. SEC is the section the frag is in. */
12867 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12870 register const struct mips16_immed_operand *op;
12872 int mintiny, maxtiny;
12876 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12878 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12881 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12882 op = mips16_immed_operands;
12883 while (op->type != type)
12886 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12891 if (type == '<' || type == '>' || type == '[' || type == ']')
12894 maxtiny = 1 << op->nbits;
12899 maxtiny = (1 << op->nbits) - 1;
12904 mintiny = - (1 << (op->nbits - 1));
12905 maxtiny = (1 << (op->nbits - 1)) - 1;
12908 sym_frag = symbol_get_frag (fragp->fr_symbol);
12909 val = S_GET_VALUE (fragp->fr_symbol);
12910 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12916 /* We won't have the section when we are called from
12917 mips_relax_frag. However, we will always have been called
12918 from md_estimate_size_before_relax first. If this is a
12919 branch to a different section, we mark it as such. If SEC is
12920 NULL, and the frag is not marked, then it must be a branch to
12921 the same section. */
12924 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12929 /* Must have been called from md_estimate_size_before_relax. */
12932 fragp->fr_subtype =
12933 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12935 /* FIXME: We should support this, and let the linker
12936 catch branches and loads that are out of range. */
12937 as_bad_where (fragp->fr_file, fragp->fr_line,
12938 _("unsupported PC relative reference to different section"));
12942 if (fragp != sym_frag && sym_frag->fr_address == 0)
12943 /* Assume non-extended on the first relaxation pass.
12944 The address we have calculated will be bogus if this is
12945 a forward branch to another frag, as the forward frag
12946 will have fr_address == 0. */
12950 /* In this case, we know for sure that the symbol fragment is in
12951 the same section. If the relax_marker of the symbol fragment
12952 differs from the relax_marker of this fragment, we have not
12953 yet adjusted the symbol fragment fr_address. We want to add
12954 in STRETCH in order to get a better estimate of the address.
12955 This particularly matters because of the shift bits. */
12957 && sym_frag->relax_marker != fragp->relax_marker)
12961 /* Adjust stretch for any alignment frag. Note that if have
12962 been expanding the earlier code, the symbol may be
12963 defined in what appears to be an earlier frag. FIXME:
12964 This doesn't handle the fr_subtype field, which specifies
12965 a maximum number of bytes to skip when doing an
12967 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12969 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12972 stretch = - ((- stretch)
12973 & ~ ((1 << (int) f->fr_offset) - 1));
12975 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12984 addr = fragp->fr_address + fragp->fr_fix;
12986 /* The base address rules are complicated. The base address of
12987 a branch is the following instruction. The base address of a
12988 PC relative load or add is the instruction itself, but if it
12989 is in a delay slot (in which case it can not be extended) use
12990 the address of the instruction whose delay slot it is in. */
12991 if (type == 'p' || type == 'q')
12995 /* If we are currently assuming that this frag should be
12996 extended, then, the current address is two bytes
12998 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13001 /* Ignore the low bit in the target, since it will be set
13002 for a text label. */
13003 if ((val & 1) != 0)
13006 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13008 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13011 val -= addr & ~ ((1 << op->shift) - 1);
13013 /* Branch offsets have an implicit 0 in the lowest bit. */
13014 if (type == 'p' || type == 'q')
13017 /* If any of the shifted bits are set, we must use an extended
13018 opcode. If the address depends on the size of this
13019 instruction, this can lead to a loop, so we arrange to always
13020 use an extended opcode. We only check this when we are in
13021 the main relaxation loop, when SEC is NULL. */
13022 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13024 fragp->fr_subtype =
13025 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13029 /* If we are about to mark a frag as extended because the value
13030 is precisely maxtiny + 1, then there is a chance of an
13031 infinite loop as in the following code:
13036 In this case when the la is extended, foo is 0x3fc bytes
13037 away, so the la can be shrunk, but then foo is 0x400 away, so
13038 the la must be extended. To avoid this loop, we mark the
13039 frag as extended if it was small, and is about to become
13040 extended with a value of maxtiny + 1. */
13041 if (val == ((maxtiny + 1) << op->shift)
13042 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13045 fragp->fr_subtype =
13046 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13050 else if (symsec != absolute_section && sec != NULL)
13051 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13053 if ((val & ((1 << op->shift) - 1)) != 0
13054 || val < (mintiny << op->shift)
13055 || val > (maxtiny << op->shift))
13061 /* Compute the length of a branch sequence, and adjust the
13062 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13063 worst-case length is computed, with UPDATE being used to indicate
13064 whether an unconditional (-1), branch-likely (+1) or regular (0)
13065 branch is to be computed. */
13067 relaxed_branch_length (fragS *fragp, asection *sec, int update)
13069 bfd_boolean toofar;
13073 && S_IS_DEFINED (fragp->fr_symbol)
13074 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13079 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13081 addr = fragp->fr_address + fragp->fr_fix + 4;
13085 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13088 /* If the symbol is not defined or it's in a different segment,
13089 assume the user knows what's going on and emit a short
13095 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13097 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13098 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13099 RELAX_BRANCH_LINK (fragp->fr_subtype),
13105 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13108 if (mips_pic != NO_PIC)
13110 /* Additional space for PIC loading of target address. */
13112 if (mips_opts.isa == ISA_MIPS1)
13113 /* Additional space for $at-stabilizing nop. */
13117 /* If branch is conditional. */
13118 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13125 /* Estimate the size of a frag before relaxing. Unless this is the
13126 mips16, we are not really relaxing here, and the final size is
13127 encoded in the subtype information. For the mips16, we have to
13128 decide whether we are using an extended opcode or not. */
13131 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13135 if (RELAX_BRANCH_P (fragp->fr_subtype))
13138 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13140 return fragp->fr_var;
13143 if (RELAX_MIPS16_P (fragp->fr_subtype))
13144 /* We don't want to modify the EXTENDED bit here; it might get us
13145 into infinite loops. We change it only in mips_relax_frag(). */
13146 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13148 if (mips_pic == NO_PIC)
13149 change = nopic_need_relax (fragp->fr_symbol, 0);
13150 else if (mips_pic == SVR4_PIC)
13151 change = pic_need_relax (fragp->fr_symbol, segtype);
13157 fragp->fr_subtype |= RELAX_USE_SECOND;
13158 /* FIXME: This really needs as_warn_where. */
13159 if (RELAX_WARN (fragp->fr_subtype))
13160 as_warn (_("AT used after \".set noat\" or macro used after "
13161 "\".set nomacro\""));
13163 return -RELAX_FIRST (fragp->fr_subtype);
13166 return -RELAX_SECOND (fragp->fr_subtype);
13169 /* This is called to see whether a reloc against a defined symbol
13170 should be converted into a reloc against a section. Don't adjust
13171 MIPS16 jump relocations, so we don't have to worry about the format
13172 of the offset in the .o file. Don't adjust relocations against
13173 mips16 symbols, so that the linker can find them if it needs to set
13177 mips_fix_adjustable (fixS *fixp)
13179 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13182 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13183 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13186 if (fixp->fx_addsy == NULL)
13190 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13191 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13192 && fixp->fx_subsy == NULL)
13199 /* Translate internal representation of relocation info to BFD target
13203 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13205 static arelent *retval[4];
13207 bfd_reloc_code_real_type code;
13209 memset (retval, 0, sizeof(retval));
13210 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13211 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13212 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13213 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13215 if (mips_pic == EMBEDDED_PIC
13216 && SWITCH_TABLE (fixp))
13218 /* For a switch table entry we use a special reloc. The addend
13219 is actually the difference between the reloc address and the
13221 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13222 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13223 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13224 fixp->fx_r_type = BFD_RELOC_GPREL32;
13226 else if (fixp->fx_pcrel)
13228 bfd_vma pcrel_address;
13230 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13231 high-part relocs is the address of the low-part reloc. */
13232 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13234 assert (fixp->fx_next != NULL
13235 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13236 pcrel_address = (fixp->fx_next->fx_where
13237 + fixp->fx_next->fx_frag->fr_address);
13240 pcrel_address = reloc->address;
13242 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13244 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13245 Relocations want only the symbol offset. */
13246 reloc->addend = fixp->fx_addnumber + pcrel_address;
13248 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
13249 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13251 /* We use a special addend for an internal RELLO or RELHI reloc. */
13252 if (symbol_section_p (fixp->fx_addsy))
13253 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
13255 reloc->addend = fixp->fx_addnumber + pcrel_address;
13259 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13260 /* A gruesome hack which is a result of the gruesome gas reloc
13262 reloc->addend = pcrel_address;
13264 reloc->addend = -pcrel_address;
13268 reloc->addend = fixp->fx_addnumber;
13270 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13271 entry to be used in the relocation's section offset. */
13272 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13274 reloc->address = reloc->addend;
13278 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13279 fixup_segment converted a non-PC relative reloc into a PC
13280 relative reloc. In such a case, we need to convert the reloc
13282 code = fixp->fx_r_type;
13283 if (fixp->fx_pcrel)
13288 code = BFD_RELOC_8_PCREL;
13291 code = BFD_RELOC_16_PCREL;
13294 code = BFD_RELOC_32_PCREL;
13297 code = BFD_RELOC_64_PCREL;
13299 case BFD_RELOC_8_PCREL:
13300 case BFD_RELOC_16_PCREL:
13301 case BFD_RELOC_32_PCREL:
13302 case BFD_RELOC_64_PCREL:
13303 case BFD_RELOC_16_PCREL_S2:
13304 case BFD_RELOC_PCREL_HI16_S:
13305 case BFD_RELOC_PCREL_LO16:
13308 as_bad_where (fixp->fx_file, fixp->fx_line,
13309 _("Cannot make %s relocation PC relative"),
13310 bfd_get_reloc_code_name (code));
13314 /* To support a PC relative reloc when generating embedded PIC code
13315 for ECOFF, we use a Cygnus extension. We check for that here to
13316 make sure that we don't let such a reloc escape normally. */
13317 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13318 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13319 && code == BFD_RELOC_16_PCREL_S2
13320 && mips_pic != EMBEDDED_PIC)
13321 reloc->howto = NULL;
13323 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13325 if (reloc->howto == NULL)
13327 as_bad_where (fixp->fx_file, fixp->fx_line,
13328 _("Can not represent %s relocation in this object file format"),
13329 bfd_get_reloc_code_name (code));
13336 /* Relax a machine dependent frag. This returns the amount by which
13337 the current size of the frag should change. */
13340 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13342 if (RELAX_BRANCH_P (fragp->fr_subtype))
13344 offsetT old_var = fragp->fr_var;
13346 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13348 return fragp->fr_var - old_var;
13351 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13354 if (mips16_extended_frag (fragp, NULL, stretch))
13356 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13358 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13363 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13365 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13372 /* Convert a machine dependent frag. */
13375 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13377 if (RELAX_BRANCH_P (fragp->fr_subtype))
13380 unsigned long insn;
13384 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13386 if (target_big_endian)
13387 insn = bfd_getb32 (buf);
13389 insn = bfd_getl32 (buf);
13391 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13393 /* We generate a fixup instead of applying it right now
13394 because, if there are linker relaxations, we're going to
13395 need the relocations. */
13396 exp.X_op = O_symbol;
13397 exp.X_add_symbol = fragp->fr_symbol;
13398 exp.X_add_number = fragp->fr_offset;
13400 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13402 BFD_RELOC_16_PCREL_S2);
13403 fixp->fx_file = fragp->fr_file;
13404 fixp->fx_line = fragp->fr_line;
13406 md_number_to_chars (buf, insn, 4);
13413 as_warn_where (fragp->fr_file, fragp->fr_line,
13414 _("relaxed out-of-range branch into a jump"));
13416 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13419 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13421 /* Reverse the branch. */
13422 switch ((insn >> 28) & 0xf)
13425 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13426 have the condition reversed by tweaking a single
13427 bit, and their opcodes all have 0x4???????. */
13428 assert ((insn & 0xf1000000) == 0x41000000);
13429 insn ^= 0x00010000;
13433 /* bltz 0x04000000 bgez 0x04010000
13434 bltzal 0x04100000 bgezal 0x04110000 */
13435 assert ((insn & 0xfc0e0000) == 0x04000000);
13436 insn ^= 0x00010000;
13440 /* beq 0x10000000 bne 0x14000000
13441 blez 0x18000000 bgtz 0x1c000000 */
13442 insn ^= 0x04000000;
13450 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13452 /* Clear the and-link bit. */
13453 assert ((insn & 0xfc1c0000) == 0x04100000);
13455 /* bltzal 0x04100000 bgezal 0x04110000
13456 bltzall 0x04120000 bgezall 0x04130000 */
13457 insn &= ~0x00100000;
13460 /* Branch over the branch (if the branch was likely) or the
13461 full jump (not likely case). Compute the offset from the
13462 current instruction to branch to. */
13463 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13467 /* How many bytes in instructions we've already emitted? */
13468 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13469 /* How many bytes in instructions from here to the end? */
13470 i = fragp->fr_var - i;
13472 /* Convert to instruction count. */
13474 /* Branch counts from the next instruction. */
13477 /* Branch over the jump. */
13478 md_number_to_chars (buf, insn, 4);
13482 md_number_to_chars (buf, 0, 4);
13485 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13487 /* beql $0, $0, 2f */
13489 /* Compute the PC offset from the current instruction to
13490 the end of the variable frag. */
13491 /* How many bytes in instructions we've already emitted? */
13492 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13493 /* How many bytes in instructions from here to the end? */
13494 i = fragp->fr_var - i;
13495 /* Convert to instruction count. */
13497 /* Don't decrement i, because we want to branch over the
13501 md_number_to_chars (buf, insn, 4);
13504 md_number_to_chars (buf, 0, 4);
13509 if (mips_pic == NO_PIC)
13512 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13513 ? 0x0c000000 : 0x08000000);
13514 exp.X_op = O_symbol;
13515 exp.X_add_symbol = fragp->fr_symbol;
13516 exp.X_add_number = fragp->fr_offset;
13518 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13519 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13520 fixp->fx_file = fragp->fr_file;
13521 fixp->fx_line = fragp->fr_line;
13523 md_number_to_chars (buf, insn, 4);
13528 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13529 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13530 exp.X_op = O_symbol;
13531 exp.X_add_symbol = fragp->fr_symbol;
13532 exp.X_add_number = fragp->fr_offset;
13534 if (fragp->fr_offset)
13536 exp.X_add_symbol = make_expr_symbol (&exp);
13537 exp.X_add_number = 0;
13540 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13541 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13542 fixp->fx_file = fragp->fr_file;
13543 fixp->fx_line = fragp->fr_line;
13545 md_number_to_chars (buf, insn, 4);
13548 if (mips_opts.isa == ISA_MIPS1)
13551 md_number_to_chars (buf, 0, 4);
13555 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13556 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13558 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13559 4, &exp, 0, BFD_RELOC_LO16);
13560 fixp->fx_file = fragp->fr_file;
13561 fixp->fx_line = fragp->fr_line;
13563 md_number_to_chars (buf, insn, 4);
13567 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13572 md_number_to_chars (buf, insn, 4);
13577 assert (buf == (bfd_byte *)fragp->fr_literal
13578 + fragp->fr_fix + fragp->fr_var);
13580 fragp->fr_fix += fragp->fr_var;
13585 if (RELAX_MIPS16_P (fragp->fr_subtype))
13588 register const struct mips16_immed_operand *op;
13589 bfd_boolean small, ext;
13592 unsigned long insn;
13593 bfd_boolean use_extend;
13594 unsigned short extend;
13596 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13597 op = mips16_immed_operands;
13598 while (op->type != type)
13601 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13612 resolve_symbol_value (fragp->fr_symbol);
13613 val = S_GET_VALUE (fragp->fr_symbol);
13618 addr = fragp->fr_address + fragp->fr_fix;
13620 /* The rules for the base address of a PC relative reloc are
13621 complicated; see mips16_extended_frag. */
13622 if (type == 'p' || type == 'q')
13627 /* Ignore the low bit in the target, since it will be
13628 set for a text label. */
13629 if ((val & 1) != 0)
13632 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13634 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13637 addr &= ~ (addressT) ((1 << op->shift) - 1);
13640 /* Make sure the section winds up with the alignment we have
13643 record_alignment (asec, op->shift);
13647 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13648 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13649 as_warn_where (fragp->fr_file, fragp->fr_line,
13650 _("extended instruction in delay slot"));
13652 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13654 if (target_big_endian)
13655 insn = bfd_getb16 (buf);
13657 insn = bfd_getl16 (buf);
13659 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13660 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13661 small, ext, &insn, &use_extend, &extend);
13665 md_number_to_chars (buf, 0xf000 | extend, 2);
13666 fragp->fr_fix += 2;
13670 md_number_to_chars (buf, insn, 2);
13671 fragp->fr_fix += 2;
13679 first = RELAX_FIRST (fragp->fr_subtype);
13680 second = RELAX_SECOND (fragp->fr_subtype);
13681 fixp = (fixS *) fragp->fr_opcode;
13683 /* Go through all the fixups for the first sequence. Disable them
13684 (by marking them as done) if we're going to use the second
13685 sequence instead. */
13687 && fixp->fx_frag == fragp
13688 && fixp->fx_where < fragp->fr_fix - second)
13690 if (fragp->fr_subtype & RELAX_USE_SECOND)
13692 fixp = fixp->fx_next;
13695 /* Go through the fixups for the second sequence. Disable them if
13696 we're going to use the first sequence, otherwise adjust their
13697 addresses to account for the relaxation. */
13698 while (fixp && fixp->fx_frag == fragp)
13700 if (fragp->fr_subtype & RELAX_USE_SECOND)
13701 fixp->fx_where -= first;
13704 fixp = fixp->fx_next;
13707 /* Now modify the frag contents. */
13708 if (fragp->fr_subtype & RELAX_USE_SECOND)
13712 start = fragp->fr_literal + fragp->fr_fix - first - second;
13713 memmove (start, start + first, second);
13714 fragp->fr_fix -= first;
13717 fragp->fr_fix -= second;
13723 /* This function is called after the relocs have been generated.
13724 We've been storing mips16 text labels as odd. Here we convert them
13725 back to even for the convenience of the debugger. */
13728 mips_frob_file_after_relocs (void)
13731 unsigned int count, i;
13733 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13736 syms = bfd_get_outsymbols (stdoutput);
13737 count = bfd_get_symcount (stdoutput);
13738 for (i = 0; i < count; i++, syms++)
13740 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13741 && ((*syms)->value & 1) != 0)
13743 (*syms)->value &= ~1;
13744 /* If the symbol has an odd size, it was probably computed
13745 incorrectly, so adjust that as well. */
13746 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13747 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13754 /* This function is called whenever a label is defined. It is used
13755 when handling branch delays; if a branch has a label, we assume we
13756 can not move it. */
13759 mips_define_label (symbolS *sym)
13761 struct insn_label_list *l;
13763 if (free_insn_labels == NULL)
13764 l = (struct insn_label_list *) xmalloc (sizeof *l);
13767 l = free_insn_labels;
13768 free_insn_labels = l->next;
13772 l->next = insn_labels;
13776 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13778 /* Some special processing for a MIPS ELF file. */
13781 mips_elf_final_processing (void)
13783 /* Write out the register information. */
13784 if (mips_abi != N64_ABI)
13788 s.ri_gprmask = mips_gprmask;
13789 s.ri_cprmask[0] = mips_cprmask[0];
13790 s.ri_cprmask[1] = mips_cprmask[1];
13791 s.ri_cprmask[2] = mips_cprmask[2];
13792 s.ri_cprmask[3] = mips_cprmask[3];
13793 /* The gp_value field is set by the MIPS ELF backend. */
13795 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13796 ((Elf32_External_RegInfo *)
13797 mips_regmask_frag));
13801 Elf64_Internal_RegInfo s;
13803 s.ri_gprmask = mips_gprmask;
13805 s.ri_cprmask[0] = mips_cprmask[0];
13806 s.ri_cprmask[1] = mips_cprmask[1];
13807 s.ri_cprmask[2] = mips_cprmask[2];
13808 s.ri_cprmask[3] = mips_cprmask[3];
13809 /* The gp_value field is set by the MIPS ELF backend. */
13811 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13812 ((Elf64_External_RegInfo *)
13813 mips_regmask_frag));
13816 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13817 sort of BFD interface for this. */
13818 if (mips_any_noreorder)
13819 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13820 if (mips_pic != NO_PIC)
13822 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13823 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13826 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13828 /* Set MIPS ELF flags for ASEs. */
13829 if (file_ase_mips16)
13830 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13831 #if 0 /* XXX FIXME */
13832 if (file_ase_mips3d)
13833 elf_elfheader (stdoutput)->e_flags |= ???;
13836 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13838 /* Set the MIPS ELF ABI flags. */
13839 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13840 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13841 else if (mips_abi == O64_ABI)
13842 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13843 else if (mips_abi == EABI_ABI)
13845 if (!file_mips_gp32)
13846 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13848 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13850 else if (mips_abi == N32_ABI)
13851 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13853 /* Nothing to do for N64_ABI. */
13855 if (mips_32bitmode)
13856 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13859 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13861 typedef struct proc {
13863 unsigned long reg_mask;
13864 unsigned long reg_offset;
13865 unsigned long fpreg_mask;
13866 unsigned long fpreg_offset;
13867 unsigned long frame_offset;
13868 unsigned long frame_reg;
13869 unsigned long pc_reg;
13872 static procS cur_proc;
13873 static procS *cur_proc_ptr;
13874 static int numprocs;
13876 /* Fill in an rs_align_code fragment. */
13879 mips_handle_align (fragS *fragp)
13881 if (fragp->fr_type != rs_align_code)
13884 if (mips_opts.mips16)
13886 static const unsigned char be_nop[] = { 0x65, 0x00 };
13887 static const unsigned char le_nop[] = { 0x00, 0x65 };
13892 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13893 p = fragp->fr_literal + fragp->fr_fix;
13901 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13905 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13909 md_obj_begin (void)
13916 /* check for premature end, nesting errors, etc */
13918 as_warn (_("missing .end at end of assembly"));
13927 if (*input_line_pointer == '-')
13929 ++input_line_pointer;
13932 if (!ISDIGIT (*input_line_pointer))
13933 as_bad (_("expected simple number"));
13934 if (input_line_pointer[0] == '0')
13936 if (input_line_pointer[1] == 'x')
13938 input_line_pointer += 2;
13939 while (ISXDIGIT (*input_line_pointer))
13942 val |= hex_value (*input_line_pointer++);
13944 return negative ? -val : val;
13948 ++input_line_pointer;
13949 while (ISDIGIT (*input_line_pointer))
13952 val |= *input_line_pointer++ - '0';
13954 return negative ? -val : val;
13957 if (!ISDIGIT (*input_line_pointer))
13959 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13960 *input_line_pointer, *input_line_pointer);
13961 as_warn (_("invalid number"));
13964 while (ISDIGIT (*input_line_pointer))
13967 val += *input_line_pointer++ - '0';
13969 return negative ? -val : val;
13972 /* The .file directive; just like the usual .file directive, but there
13973 is an initial number which is the ECOFF file index. In the non-ECOFF
13974 case .file implies DWARF-2. */
13977 s_mips_file (int x ATTRIBUTE_UNUSED)
13979 static int first_file_directive = 0;
13981 if (ECOFF_DEBUGGING)
13990 filename = dwarf2_directive_file (0);
13992 /* Versions of GCC up to 3.1 start files with a ".file"
13993 directive even for stabs output. Make sure that this
13994 ".file" is handled. Note that you need a version of GCC
13995 after 3.1 in order to support DWARF-2 on MIPS. */
13996 if (filename != NULL && ! first_file_directive)
13998 (void) new_logical_line (filename, -1);
13999 s_app_file_string (filename);
14001 first_file_directive = 1;
14005 /* The .loc directive, implying DWARF-2. */
14008 s_mips_loc (int x ATTRIBUTE_UNUSED)
14010 if (!ECOFF_DEBUGGING)
14011 dwarf2_directive_loc (0);
14014 /* The .end directive. */
14017 s_mips_end (int x ATTRIBUTE_UNUSED)
14021 /* Following functions need their own .frame and .cprestore directives. */
14022 mips_frame_reg_valid = 0;
14023 mips_cprestore_valid = 0;
14025 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14028 demand_empty_rest_of_line ();
14033 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14034 as_warn (_(".end not in text section"));
14038 as_warn (_(".end directive without a preceding .ent directive."));
14039 demand_empty_rest_of_line ();
14045 assert (S_GET_NAME (p));
14046 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14047 as_warn (_(".end symbol does not match .ent symbol."));
14049 if (debug_type == DEBUG_STABS)
14050 stabs_generate_asm_endfunc (S_GET_NAME (p),
14054 as_warn (_(".end directive missing or unknown symbol"));
14057 /* Generate a .pdr section. */
14058 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14061 segT saved_seg = now_seg;
14062 subsegT saved_subseg = now_subseg;
14067 dot = frag_now_fix ();
14069 #ifdef md_flush_pending_output
14070 md_flush_pending_output ();
14074 subseg_set (pdr_seg, 0);
14076 /* Write the symbol. */
14077 exp.X_op = O_symbol;
14078 exp.X_add_symbol = p;
14079 exp.X_add_number = 0;
14080 emit_expr (&exp, 4);
14082 fragp = frag_more (7 * 4);
14084 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14085 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14086 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14087 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14088 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14089 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14090 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14092 subseg_set (saved_seg, saved_subseg);
14094 #endif /* OBJ_ELF */
14096 cur_proc_ptr = NULL;
14099 /* The .aent and .ent directives. */
14102 s_mips_ent (int aent)
14106 symbolP = get_symbol ();
14107 if (*input_line_pointer == ',')
14108 ++input_line_pointer;
14109 SKIP_WHITESPACE ();
14110 if (ISDIGIT (*input_line_pointer)
14111 || *input_line_pointer == '-')
14114 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14115 as_warn (_(".ent or .aent not in text section."));
14117 if (!aent && cur_proc_ptr)
14118 as_warn (_("missing .end"));
14122 /* This function needs its own .frame and .cprestore directives. */
14123 mips_frame_reg_valid = 0;
14124 mips_cprestore_valid = 0;
14126 cur_proc_ptr = &cur_proc;
14127 memset (cur_proc_ptr, '\0', sizeof (procS));
14129 cur_proc_ptr->isym = symbolP;
14131 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14135 if (debug_type == DEBUG_STABS)
14136 stabs_generate_asm_func (S_GET_NAME (symbolP),
14137 S_GET_NAME (symbolP));
14140 demand_empty_rest_of_line ();
14143 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14144 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14145 s_mips_frame is used so that we can set the PDR information correctly.
14146 We can't use the ecoff routines because they make reference to the ecoff
14147 symbol table (in the mdebug section). */
14150 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14153 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14157 if (cur_proc_ptr == (procS *) NULL)
14159 as_warn (_(".frame outside of .ent"));
14160 demand_empty_rest_of_line ();
14164 cur_proc_ptr->frame_reg = tc_get_register (1);
14166 SKIP_WHITESPACE ();
14167 if (*input_line_pointer++ != ','
14168 || get_absolute_expression_and_terminator (&val) != ',')
14170 as_warn (_("Bad .frame directive"));
14171 --input_line_pointer;
14172 demand_empty_rest_of_line ();
14176 cur_proc_ptr->frame_offset = val;
14177 cur_proc_ptr->pc_reg = tc_get_register (0);
14179 demand_empty_rest_of_line ();
14182 #endif /* OBJ_ELF */
14186 /* The .fmask and .mask directives. If the mdebug section is present
14187 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14188 embedded targets, s_mips_mask is used so that we can set the PDR
14189 information correctly. We can't use the ecoff routines because they
14190 make reference to the ecoff symbol table (in the mdebug section). */
14193 s_mips_mask (int reg_type)
14196 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14200 if (cur_proc_ptr == (procS *) NULL)
14202 as_warn (_(".mask/.fmask outside of .ent"));
14203 demand_empty_rest_of_line ();
14207 if (get_absolute_expression_and_terminator (&mask) != ',')
14209 as_warn (_("Bad .mask/.fmask directive"));
14210 --input_line_pointer;
14211 demand_empty_rest_of_line ();
14215 off = get_absolute_expression ();
14217 if (reg_type == 'F')
14219 cur_proc_ptr->fpreg_mask = mask;
14220 cur_proc_ptr->fpreg_offset = off;
14224 cur_proc_ptr->reg_mask = mask;
14225 cur_proc_ptr->reg_offset = off;
14228 demand_empty_rest_of_line ();
14231 #endif /* OBJ_ELF */
14232 s_ignore (reg_type);
14235 /* The .loc directive. */
14245 assert (now_seg == text_section);
14247 lineno = get_number ();
14248 addroff = frag_now_fix ();
14250 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14251 S_SET_TYPE (symbolP, N_SLINE);
14252 S_SET_OTHER (symbolP, 0);
14253 S_SET_DESC (symbolP, lineno);
14254 symbolP->sy_segment = now_seg;
14258 /* A table describing all the processors gas knows about. Names are
14259 matched in the order listed.
14261 To ease comparison, please keep this table in the same order as
14262 gcc's mips_cpu_info_table[]. */
14263 static const struct mips_cpu_info mips_cpu_info_table[] =
14265 /* Entries for generic ISAs */
14266 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14267 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14268 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14269 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14270 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14271 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14272 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14273 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14274 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
14277 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14278 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14279 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14282 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14285 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14286 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14287 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14288 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14289 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14290 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14291 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14292 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14293 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14294 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14295 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14296 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14299 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14300 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14301 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14302 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14303 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14304 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14305 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14306 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14307 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14308 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14309 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14310 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14311 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14314 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14315 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14316 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14319 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14320 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14322 /* Broadcom SB-1 CPU core */
14323 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14330 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14331 with a final "000" replaced by "k". Ignore case.
14333 Note: this function is shared between GCC and GAS. */
14336 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14338 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14339 given++, canonical++;
14341 return ((*given == 0 && *canonical == 0)
14342 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14346 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14347 CPU name. We've traditionally allowed a lot of variation here.
14349 Note: this function is shared between GCC and GAS. */
14352 mips_matching_cpu_name_p (const char *canonical, const char *given)
14354 /* First see if the name matches exactly, or with a final "000"
14355 turned into "k". */
14356 if (mips_strict_matching_cpu_name_p (canonical, given))
14359 /* If not, try comparing based on numerical designation alone.
14360 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14361 if (TOLOWER (*given) == 'r')
14363 if (!ISDIGIT (*given))
14366 /* Skip over some well-known prefixes in the canonical name,
14367 hoping to find a number there too. */
14368 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14370 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14372 else if (TOLOWER (canonical[0]) == 'r')
14375 return mips_strict_matching_cpu_name_p (canonical, given);
14379 /* Parse an option that takes the name of a processor as its argument.
14380 OPTION is the name of the option and CPU_STRING is the argument.
14381 Return the corresponding processor enumeration if the CPU_STRING is
14382 recognized, otherwise report an error and return null.
14384 A similar function exists in GCC. */
14386 static const struct mips_cpu_info *
14387 mips_parse_cpu (const char *option, const char *cpu_string)
14389 const struct mips_cpu_info *p;
14391 /* 'from-abi' selects the most compatible architecture for the given
14392 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14393 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14394 version. Look first at the -mgp options, if given, otherwise base
14395 the choice on MIPS_DEFAULT_64BIT.
14397 Treat NO_ABI like the EABIs. One reason to do this is that the
14398 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14399 architecture. This code picks MIPS I for 'mips' and MIPS III for
14400 'mips64', just as we did in the days before 'from-abi'. */
14401 if (strcasecmp (cpu_string, "from-abi") == 0)
14403 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14404 return mips_cpu_info_from_isa (ISA_MIPS1);
14406 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14407 return mips_cpu_info_from_isa (ISA_MIPS3);
14409 if (file_mips_gp32 >= 0)
14410 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14412 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14417 /* 'default' has traditionally been a no-op. Probably not very useful. */
14418 if (strcasecmp (cpu_string, "default") == 0)
14421 for (p = mips_cpu_info_table; p->name != 0; p++)
14422 if (mips_matching_cpu_name_p (p->name, cpu_string))
14425 as_bad ("Bad value (%s) for %s", cpu_string, option);
14429 /* Return the canonical processor information for ISA (a member of the
14430 ISA_MIPS* enumeration). */
14432 static const struct mips_cpu_info *
14433 mips_cpu_info_from_isa (int isa)
14437 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14438 if (mips_cpu_info_table[i].is_isa
14439 && isa == mips_cpu_info_table[i].isa)
14440 return (&mips_cpu_info_table[i]);
14445 static const struct mips_cpu_info *
14446 mips_cpu_info_from_arch (int arch)
14450 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14451 if (arch == mips_cpu_info_table[i].cpu)
14452 return (&mips_cpu_info_table[i]);
14458 show (FILE *stream, const char *string, int *col_p, int *first_p)
14462 fprintf (stream, "%24s", "");
14467 fprintf (stream, ", ");
14471 if (*col_p + strlen (string) > 72)
14473 fprintf (stream, "\n%24s", "");
14477 fprintf (stream, "%s", string);
14478 *col_p += strlen (string);
14484 md_show_usage (FILE *stream)
14489 fprintf (stream, _("\
14491 -membedded-pic generate embedded position independent code\n\
14492 -EB generate big endian output\n\
14493 -EL generate little endian output\n\
14494 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14495 -G NUM allow referencing objects up to NUM bytes\n\
14496 implicitly with the gp register [default 8]\n"));
14497 fprintf (stream, _("\
14498 -mips1 generate MIPS ISA I instructions\n\
14499 -mips2 generate MIPS ISA II instructions\n\
14500 -mips3 generate MIPS ISA III instructions\n\
14501 -mips4 generate MIPS ISA IV instructions\n\
14502 -mips5 generate MIPS ISA V instructions\n\
14503 -mips32 generate MIPS32 ISA instructions\n\
14504 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14505 -mips64 generate MIPS64 ISA instructions\n\
14506 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14507 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14511 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14512 show (stream, mips_cpu_info_table[i].name, &column, &first);
14513 show (stream, "from-abi", &column, &first);
14514 fputc ('\n', stream);
14516 fprintf (stream, _("\
14517 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14518 -no-mCPU don't generate code specific to CPU.\n\
14519 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14523 show (stream, "3900", &column, &first);
14524 show (stream, "4010", &column, &first);
14525 show (stream, "4100", &column, &first);
14526 show (stream, "4650", &column, &first);
14527 fputc ('\n', stream);
14529 fprintf (stream, _("\
14530 -mips16 generate mips16 instructions\n\
14531 -no-mips16 do not generate mips16 instructions\n"));
14532 fprintf (stream, _("\
14533 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14534 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14535 -O0 remove unneeded NOPs, do not swap branches\n\
14536 -O remove unneeded NOPs and swap branches\n\
14537 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14538 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14539 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14541 fprintf (stream, _("\
14542 -KPIC, -call_shared generate SVR4 position independent code\n\
14543 -non_shared do not generate position independent code\n\
14544 -xgot assume a 32 bit GOT\n\
14545 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14546 -mabi=ABI create ABI conformant object file for:\n"));
14550 show (stream, "32", &column, &first);
14551 show (stream, "o64", &column, &first);
14552 show (stream, "n32", &column, &first);
14553 show (stream, "64", &column, &first);
14554 show (stream, "eabi", &column, &first);
14556 fputc ('\n', stream);
14558 fprintf (stream, _("\
14559 -32 create o32 ABI object file (default)\n\
14560 -n32 create n32 ABI object file\n\
14561 -64 create 64 ABI object file\n"));
14566 mips_dwarf2_format (void)
14568 if (mips_abi == N64_ABI)
14571 return dwarf2_format_64bit_irix;
14573 return dwarf2_format_64bit;
14577 return dwarf2_format_32bit;