1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p : 1;
164 /* The ABI to use. */
175 /* MIPS ABI we are using for this output file. */
176 static enum mips_abi_level mips_abi = NO_ABI;
178 /* Whether or not we have code that can call pic code. */
179 int mips_abicalls = FALSE;
181 /* Whether or not we have code which can be put into a shared
183 static bfd_boolean mips_in_shared = TRUE;
185 /* This is the set of options which may be modified by the .set
186 pseudo-op. We use a struct so that .set push and .set pop are more
189 struct mips_set_options
191 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
192 if it has not been initialized. Changed by `.set mipsN', and the
193 -mipsN command line option, and the default CPU. */
195 /* Enabled Application Specific Extensions (ASEs). These are set to -1
196 if they have not been initialized. Changed by `.set <asename>', by
197 command line options, and based on the default architecture. */
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Non-zero if we should not reorder instructions. Changed by `.set
210 reorder' and `.set noreorder'. */
212 /* Non-zero if we should not permit the register designated "assembler
213 temporary" to be used in instructions. The value is the register
214 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
215 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
217 /* Non-zero if we should warn when a macro instruction expands into
218 more than one machine instruction. Changed by `.set nomacro' and
220 int warn_about_macros;
221 /* Non-zero if we should not move instructions. Changed by `.set
222 move', `.set volatile', `.set nomove', and `.set novolatile'. */
224 /* Non-zero if we should not optimize branches by moving the target
225 of the branch into the delay slot. Actually, we don't perform
226 this optimization anyhow. Changed by `.set bopt' and `.set
229 /* Non-zero if we should not autoextend mips16 instructions.
230 Changed by `.set autoextend' and `.set noautoextend'. */
232 /* Restrict general purpose registers and floating point registers
233 to 32 bit. This is initially determined when -mgp32 or -mfp32
234 is passed but can changed if the assembler code uses .set mipsN. */
237 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
238 command line option, and the default CPU. */
240 /* True if ".set sym32" is in effect. */
242 /* True if floating-point operations are not allowed. Changed by .set
243 softfloat or .set hardfloat, by command line options -msoft-float or
244 -mhard-float. The default is false. */
245 bfd_boolean soft_float;
247 /* True if only single-precision floating-point operations are allowed.
248 Changed by .set singlefloat or .set doublefloat, command-line options
249 -msingle-float or -mdouble-float. The default is false. */
250 bfd_boolean single_float;
253 /* This is the struct we use to hold the current set of options. Note
254 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
255 -1 to indicate that they have not been initialized. */
257 /* True if -mgp32 was passed. */
258 static int file_mips_gp32 = -1;
260 /* True if -mfp32 was passed. */
261 static int file_mips_fp32 = -1;
263 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
264 static int file_mips_soft_float = 0;
266 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
267 static int file_mips_single_float = 0;
269 static struct mips_set_options mips_opts =
271 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
272 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
273 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
274 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
275 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
276 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
279 /* These variables are filled in with the masks of registers used.
280 The object format code reads them and puts them in the appropriate
282 unsigned long mips_gprmask;
283 unsigned long mips_cprmask[4];
285 /* MIPS ISA we are using for this output file. */
286 static int file_mips_isa = ISA_UNKNOWN;
288 /* True if any MIPS16 code was produced. */
289 static int file_ase_mips16;
291 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
292 || mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64 \
294 || mips_opts.isa == ISA_MIPS64R2)
296 /* True if we want to create R_MIPS_JALR for jalr $25. */
298 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
300 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
301 because there's no place for any addend, the only acceptable
302 expression is a bare symbol. */
303 #define MIPS_JALR_HINT_P(EXPR) \
304 (!HAVE_IN_PLACE_ADDENDS \
305 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
308 /* True if -mips3d was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_mips3d;
312 /* True if -mdmx was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314 static int file_ase_mdmx;
316 /* True if -msmartmips was passed or implied by arguments passed on the
317 command line (e.g., by -march). */
318 static int file_ase_smartmips;
320 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
321 || mips_opts.isa == ISA_MIPS32R2)
323 /* True if -mdsp was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_dsp;
327 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS64R2)
330 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
332 /* True if -mdspr2 was passed or implied by arguments passed on the
333 command line (e.g., by -march). */
334 static int file_ase_dspr2;
336 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2)
339 /* True if -mmt was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mt;
343 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
344 || mips_opts.isa == ISA_MIPS64R2)
346 /* The argument of the -march= flag. The architecture we are assembling. */
347 static int file_mips_arch = CPU_UNKNOWN;
348 static const char *mips_arch_string;
350 /* The argument of the -mtune= flag. The architecture for which we
352 static int mips_tune = CPU_UNKNOWN;
353 static const char *mips_tune_string;
355 /* True when generating 32-bit code for a 64-bit processor. */
356 static int mips_32bitmode = 0;
358 /* True if the given ABI requires 32-bit registers. */
359 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
361 /* Likewise 64-bit registers. */
362 #define ABI_NEEDS_64BIT_REGS(ABI) \
364 || (ABI) == N64_ABI \
367 /* Return true if ISA supports 64 bit wide gp registers. */
368 #define ISA_HAS_64BIT_REGS(ISA) \
369 ((ISA) == ISA_MIPS3 \
370 || (ISA) == ISA_MIPS4 \
371 || (ISA) == ISA_MIPS5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2)
375 /* Return true if ISA supports 64 bit wide float registers. */
376 #define ISA_HAS_64BIT_FPRS(ISA) \
377 ((ISA) == ISA_MIPS3 \
378 || (ISA) == ISA_MIPS4 \
379 || (ISA) == ISA_MIPS5 \
380 || (ISA) == ISA_MIPS32R2 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2)
384 /* Return true if ISA supports 64-bit right rotate (dror et al.)
386 #define ISA_HAS_DROR(ISA) \
387 ((ISA) == ISA_MIPS64R2)
389 /* Return true if ISA supports 32-bit right rotate (ror et al.)
391 #define ISA_HAS_ROR(ISA) \
392 ((ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS64R2 \
394 || mips_opts.ase_smartmips)
396 /* Return true if ISA supports single-precision floats in odd registers. */
397 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
398 ((ISA) == ISA_MIPS32 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports move to/from high part of a 64-bit
404 floating-point register. */
405 #define ISA_HAS_MXHC1(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS64R2)
409 #define HAVE_32BIT_GPRS \
410 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
412 #define HAVE_32BIT_FPRS \
413 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
415 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
416 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
418 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
420 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
422 /* True if relocations are stored in-place. */
423 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
425 /* The ABI-derived address size. */
426 #define HAVE_64BIT_ADDRESSES \
427 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
428 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
430 /* The size of symbolic constants (i.e., expressions of the form
431 "SYMBOL" or "SYMBOL + OFFSET"). */
432 #define HAVE_32BIT_SYMBOLS \
433 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
434 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
436 /* Addresses are loaded in different ways, depending on the address size
437 in use. The n32 ABI Documentation also mandates the use of additions
438 with overflow checking, but existing implementations don't follow it. */
439 #define ADDRESS_ADD_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
442 #define ADDRESS_ADDI_INSN \
443 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
445 #define ADDRESS_LOAD_INSN \
446 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
448 #define ADDRESS_STORE_INSN \
449 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
451 /* Return true if the given CPU supports the MIPS16 ASE. */
452 #define CPU_HAS_MIPS16(cpu) \
453 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
454 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
456 /* True if CPU has a dror instruction. */
457 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
459 /* True if CPU has a ror instruction. */
460 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
462 /* True if CPU has seq/sne and seqi/snei instructions. */
463 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
465 /* True if CPU does not implement the all the coprocessor insns. For these
466 CPUs only those COP insns are accepted that are explicitly marked to be
467 available on the CPU. ISA membership for COP insns is ignored. */
468 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
470 /* True if mflo and mfhi can be immediately followed by instructions
471 which write to the HI and LO registers.
473 According to MIPS specifications, MIPS ISAs I, II, and III need
474 (at least) two instructions between the reads of HI/LO and
475 instructions which write them, and later ISAs do not. Contradicting
476 the MIPS specifications, some MIPS IV processor user manuals (e.g.
477 the UM for the NEC Vr5000) document needing the instructions between
478 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
479 MIPS64 and later ISAs to have the interlocks, plus any specific
480 earlier-ISA CPUs for which CPU documentation declares that the
481 instructions are really interlocked. */
482 #define hilo_interlocks \
483 (mips_opts.isa == ISA_MIPS32 \
484 || mips_opts.isa == ISA_MIPS32R2 \
485 || mips_opts.isa == ISA_MIPS64 \
486 || mips_opts.isa == ISA_MIPS64R2 \
487 || mips_opts.arch == CPU_R4010 \
488 || mips_opts.arch == CPU_R10000 \
489 || mips_opts.arch == CPU_R12000 \
490 || mips_opts.arch == CPU_R14000 \
491 || mips_opts.arch == CPU_R16000 \
492 || mips_opts.arch == CPU_RM7000 \
493 || mips_opts.arch == CPU_VR5500 \
496 /* Whether the processor uses hardware interlocks to protect reads
497 from the GPRs after they are loaded from memory, and thus does not
498 require nops to be inserted. This applies to instructions marked
499 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
501 #define gpr_interlocks \
502 (mips_opts.isa != ISA_MIPS1 \
503 || mips_opts.arch == CPU_R3900)
505 /* Whether the processor uses hardware interlocks to avoid delays
506 required by coprocessor instructions, and thus does not require
507 nops to be inserted. This applies to instructions marked
508 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
509 between instructions marked INSN_WRITE_COND_CODE and ones marked
510 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
511 levels I, II, and III. */
512 /* Itbl support may require additional care here. */
513 #define cop_interlocks \
514 ((mips_opts.isa != ISA_MIPS1 \
515 && mips_opts.isa != ISA_MIPS2 \
516 && mips_opts.isa != ISA_MIPS3) \
517 || mips_opts.arch == CPU_R4300 \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I. */
525 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
527 /* Is this a mfhi or mflo instruction? */
528 #define MF_HILO_INSN(PINFO) \
529 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
531 /* Returns true for a (non floating-point) coprocessor instruction. Reading
532 or writing the condition code is only possible on the coprocessors and
533 these insns are not marked with INSN_COP. Thus for these insns use the
534 condition-code flags. */
535 #define COP_INSN(PINFO) \
536 (PINFO != INSN_MACRO \
537 && ((PINFO) & (FP_S | FP_D)) == 0 \
538 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
540 /* MIPS PIC level. */
542 enum mips_pic_level mips_pic;
544 /* 1 if we should generate 32 bit offsets from the $gp register in
545 SVR4_PIC mode. Currently has no meaning in other modes. */
546 static int mips_big_got = 0;
548 /* 1 if trap instructions should used for overflow rather than break
550 static int mips_trap = 0;
552 /* 1 if double width floating point constants should not be constructed
553 by assembling two single width halves into two single width floating
554 point registers which just happen to alias the double width destination
555 register. On some architectures this aliasing can be disabled by a bit
556 in the status register, and the setting of this bit cannot be determined
557 automatically at assemble time. */
558 static int mips_disable_float_construction;
560 /* Non-zero if any .set noreorder directives were used. */
562 static int mips_any_noreorder;
564 /* Non-zero if nops should be inserted when the register referenced in
565 an mfhi/mflo instruction is read in the next two instructions. */
566 static int mips_7000_hilo_fix;
568 /* The size of objects in the small data section. */
569 static unsigned int g_switch_value = 8;
570 /* Whether the -G option was used. */
571 static int g_switch_seen = 0;
576 /* If we can determine in advance that GP optimization won't be
577 possible, we can skip the relaxation stuff that tries to produce
578 GP-relative references. This makes delay slot optimization work
581 This function can only provide a guess, but it seems to work for
582 gcc output. It needs to guess right for gcc, otherwise gcc
583 will put what it thinks is a GP-relative instruction in a branch
586 I don't know if a fix is needed for the SVR4_PIC mode. I've only
587 fixed it for the non-PIC mode. KR 95/04/07 */
588 static int nopic_need_relax (symbolS *, int);
590 /* handle of the OPCODE hash table */
591 static struct hash_control *op_hash = NULL;
593 /* The opcode hash table we use for the mips16. */
594 static struct hash_control *mips16_op_hash = NULL;
596 /* This array holds the chars that always start a comment. If the
597 pre-processor is disabled, these aren't very useful */
598 const char comment_chars[] = "#";
600 /* This array holds the chars that only start a comment at the beginning of
601 a line. If the line seems to have the form '# 123 filename'
602 .line and .file directives will appear in the pre-processed output */
603 /* Note that input_file.c hand checks for '#' at the beginning of the
604 first line of the input file. This is because the compiler outputs
605 #NO_APP at the beginning of its output. */
606 /* Also note that C style comments are always supported. */
607 const char line_comment_chars[] = "#";
609 /* This array holds machine specific line separator characters. */
610 const char line_separator_chars[] = ";";
612 /* Chars that can be used to separate mant from exp in floating point nums */
613 const char EXP_CHARS[] = "eE";
615 /* Chars that mean this number is a floating point constant */
618 const char FLT_CHARS[] = "rRsSfFdDxXpP";
620 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
621 changed in read.c . Ideally it shouldn't have to know about it at all,
622 but nothing is ideal around here.
625 static char *insn_error;
627 static int auto_align = 1;
629 /* When outputting SVR4 PIC code, the assembler needs to know the
630 offset in the stack frame from which to restore the $gp register.
631 This is set by the .cprestore pseudo-op, and saved in this
633 static offsetT mips_cprestore_offset = -1;
635 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
636 more optimizations, it can use a register value instead of a memory-saved
637 offset and even an other register than $gp as global pointer. */
638 static offsetT mips_cpreturn_offset = -1;
639 static int mips_cpreturn_register = -1;
640 static int mips_gp_register = GP;
641 static int mips_gprel_offset = 0;
643 /* Whether mips_cprestore_offset has been set in the current function
644 (or whether it has already been warned about, if not). */
645 static int mips_cprestore_valid = 0;
647 /* This is the register which holds the stack frame, as set by the
648 .frame pseudo-op. This is needed to implement .cprestore. */
649 static int mips_frame_reg = SP;
651 /* Whether mips_frame_reg has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_frame_reg_valid = 0;
655 /* To output NOP instructions correctly, we need to keep information
656 about the previous two instructions. */
658 /* Whether we are optimizing. The default value of 2 means to remove
659 unneeded NOPs and swap branch instructions when possible. A value
660 of 1 means to not swap branches. A value of 0 means to always
662 static int mips_optimize = 2;
664 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
665 equivalent to seeing no -g option at all. */
666 static int mips_debug = 0;
668 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
669 #define MAX_VR4130_NOPS 4
671 /* The maximum number of NOPs needed to fill delay slots. */
672 #define MAX_DELAY_NOPS 2
674 /* The maximum number of NOPs needed for any purpose. */
677 /* A list of previous instructions, with index 0 being the most recent.
678 We need to look back MAX_NOPS instructions when filling delay slots
679 or working around processor errata. We need to look back one
680 instruction further if we're thinking about using history[0] to
681 fill a branch delay slot. */
682 static struct mips_cl_insn history[1 + MAX_NOPS];
684 /* Nop instructions used by emit_nop. */
685 static struct mips_cl_insn nop_insn, mips16_nop_insn;
687 /* The appropriate nop for the current mode. */
688 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
690 /* If this is set, it points to a frag holding nop instructions which
691 were inserted before the start of a noreorder section. If those
692 nops turn out to be unnecessary, the size of the frag can be
694 static fragS *prev_nop_frag;
696 /* The number of nop instructions we created in prev_nop_frag. */
697 static int prev_nop_frag_holds;
699 /* The number of nop instructions that we know we need in
701 static int prev_nop_frag_required;
703 /* The number of instructions we've seen since prev_nop_frag. */
704 static int prev_nop_frag_since;
706 /* For ECOFF and ELF, relocations against symbols are done in two
707 parts, with a HI relocation and a LO relocation. Each relocation
708 has only 16 bits of space to store an addend. This means that in
709 order for the linker to handle carries correctly, it must be able
710 to locate both the HI and the LO relocation. This means that the
711 relocations must appear in order in the relocation table.
713 In order to implement this, we keep track of each unmatched HI
714 relocation. We then sort them so that they immediately precede the
715 corresponding LO relocation. */
720 struct mips_hi_fixup *next;
723 /* The section this fixup is in. */
727 /* The list of unmatched HI relocs. */
729 static struct mips_hi_fixup *mips_hi_fixup_list;
731 /* The frag containing the last explicit relocation operator.
732 Null if explicit relocations have not been used. */
734 static fragS *prev_reloc_op_frag;
736 /* Map normal MIPS register numbers to mips16 register numbers. */
738 #define X ILLEGAL_REG
739 static const int mips32_to_16_reg_map[] =
741 X, X, 2, 3, 4, 5, 6, 7,
742 X, X, X, X, X, X, X, X,
743 0, 1, X, X, X, X, X, X,
744 X, X, X, X, X, X, X, X
748 /* Map mips16 register numbers to normal MIPS register numbers. */
750 static const unsigned int mips16_to_32_reg_map[] =
752 16, 17, 2, 3, 4, 5, 6, 7
755 /* Classifies the kind of instructions we're interested in when
756 implementing -mfix-vr4120. */
757 enum fix_vr4120_class
765 NUM_FIX_VR4120_CLASSES
768 /* ...likewise -mfix-loongson2f-jump. */
769 static bfd_boolean mips_fix_loongson2f_jump;
771 /* ...likewise -mfix-loongson2f-nop. */
772 static bfd_boolean mips_fix_loongson2f_nop;
774 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
775 static bfd_boolean mips_fix_loongson2f;
777 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
778 there must be at least one other instruction between an instruction
779 of type X and an instruction of type Y. */
780 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
782 /* True if -mfix-vr4120 is in force. */
783 static int mips_fix_vr4120;
785 /* ...likewise -mfix-vr4130. */
786 static int mips_fix_vr4130;
788 /* ...likewise -mfix-24k. */
789 static int mips_fix_24k;
791 /* ...likewise -mfix-cn63xxp1 */
792 static bfd_boolean mips_fix_cn63xxp1;
794 /* We don't relax branches by default, since this causes us to expand
795 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
796 fail to compute the offset before expanding the macro to the most
797 efficient expansion. */
799 static int mips_relax_branch;
801 /* The expansion of many macros depends on the type of symbol that
802 they refer to. For example, when generating position-dependent code,
803 a macro that refers to a symbol may have two different expansions,
804 one which uses GP-relative addresses and one which uses absolute
805 addresses. When generating SVR4-style PIC, a macro may have
806 different expansions for local and global symbols.
808 We handle these situations by generating both sequences and putting
809 them in variant frags. In position-dependent code, the first sequence
810 will be the GP-relative one and the second sequence will be the
811 absolute one. In SVR4 PIC, the first sequence will be for global
812 symbols and the second will be for local symbols.
814 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
815 SECOND are the lengths of the two sequences in bytes. These fields
816 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
817 the subtype has the following flags:
820 Set if it has been decided that we should use the second
821 sequence instead of the first.
824 Set in the first variant frag if the macro's second implementation
825 is longer than its first. This refers to the macro as a whole,
826 not an individual relaxation.
829 Set in the first variant frag if the macro appeared in a .set nomacro
830 block and if one alternative requires a warning but the other does not.
833 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
836 The frag's "opcode" points to the first fixup for relaxable code.
838 Relaxable macros are generated using a sequence such as:
840 relax_start (SYMBOL);
841 ... generate first expansion ...
843 ... generate second expansion ...
846 The code and fixups for the unwanted alternative are discarded
847 by md_convert_frag. */
848 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
850 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
851 #define RELAX_SECOND(X) ((X) & 0xff)
852 #define RELAX_USE_SECOND 0x10000
853 #define RELAX_SECOND_LONGER 0x20000
854 #define RELAX_NOMACRO 0x40000
855 #define RELAX_DELAY_SLOT 0x80000
857 /* Branch without likely bit. If label is out of range, we turn:
859 beq reg1, reg2, label
869 with the following opcode replacements:
876 bltzal <-> bgezal (with jal label instead of j label)
878 Even though keeping the delay slot instruction in the delay slot of
879 the branch would be more efficient, it would be very tricky to do
880 correctly, because we'd have to introduce a variable frag *after*
881 the delay slot instruction, and expand that instead. Let's do it
882 the easy way for now, even if the branch-not-taken case now costs
883 one additional instruction. Out-of-range branches are not supposed
884 to be common, anyway.
886 Branch likely. If label is out of range, we turn:
888 beql reg1, reg2, label
889 delay slot (annulled if branch not taken)
898 delay slot (executed only if branch taken)
901 It would be possible to generate a shorter sequence by losing the
902 likely bit, generating something like:
907 delay slot (executed only if branch taken)
919 bltzall -> bgezal (with jal label instead of j label)
920 bgezall -> bltzal (ditto)
923 but it's not clear that it would actually improve performance. */
924 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
928 | ((toofar) ? 0x20 : 0) \
929 | ((link) ? 0x40 : 0) \
930 | ((likely) ? 0x80 : 0) \
931 | ((uncond) ? 0x100 : 0)))
932 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
933 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
934 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
935 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
936 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
937 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
939 /* For mips16 code, we use an entirely different form of relaxation.
940 mips16 supports two versions of most instructions which take
941 immediate values: a small one which takes some small value, and a
942 larger one which takes a 16 bit value. Since branches also follow
943 this pattern, relaxing these values is required.
945 We can assemble both mips16 and normal MIPS code in a single
946 object. Therefore, we need to support this type of relaxation at
947 the same time that we support the relaxation described above. We
948 use the high bit of the subtype field to distinguish these cases.
950 The information we store for this type of relaxation is the
951 argument code found in the opcode file for this relocation, whether
952 the user explicitly requested a small or extended form, and whether
953 the relocation is in a jump or jal delay slot. That tells us the
954 size of the value, and how it should be stored. We also store
955 whether the fragment is considered to be extended or not. We also
956 store whether this is known to be a branch to a different section,
957 whether we have tried to relax this frag yet, and whether we have
958 ever extended a PC relative fragment because of a shift count. */
959 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
962 | ((small) ? 0x100 : 0) \
963 | ((ext) ? 0x200 : 0) \
964 | ((dslot) ? 0x400 : 0) \
965 | ((jal_dslot) ? 0x800 : 0))
966 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
967 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
968 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
969 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
970 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
971 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
972 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
973 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
974 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
975 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
976 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
977 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
979 /* Is the given value a sign-extended 32-bit value? */
980 #define IS_SEXT_32BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fffffff) == 0 \
982 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
984 /* Is the given value a sign-extended 16-bit value? */
985 #define IS_SEXT_16BIT_NUM(x) \
986 (((x) &~ (offsetT) 0x7fff) == 0 \
987 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
989 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
990 #define IS_ZEXT_32BIT_NUM(x) \
991 (((x) &~ (offsetT) 0xffffffff) == 0 \
992 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
994 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
995 VALUE << SHIFT. VALUE is evaluated exactly once. */
996 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
997 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
998 | (((VALUE) & (MASK)) << (SHIFT)))
1000 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1002 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1003 (((STRUCT) >> (SHIFT)) & (MASK))
1005 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1006 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1008 include/opcode/mips.h specifies operand fields using the macros
1009 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1010 with "MIPS16OP" instead of "OP". */
1011 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1012 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1014 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1015 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1017 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1018 #define EXTRACT_OPERAND(FIELD, INSN) \
1019 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1020 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1021 EXTRACT_BITS ((INSN).insn_opcode, \
1022 MIPS16OP_MASK_##FIELD, \
1023 MIPS16OP_SH_##FIELD)
1025 /* Global variables used when generating relaxable macros. See the
1026 comment above RELAX_ENCODE for more details about how relaxation
1029 /* 0 if we're not emitting a relaxable macro.
1030 1 if we're emitting the first of the two relaxation alternatives.
1031 2 if we're emitting the second alternative. */
1034 /* The first relaxable fixup in the current frag. (In other words,
1035 the first fixup that refers to relaxable code.) */
1038 /* sizes[0] says how many bytes of the first alternative are stored in
1039 the current frag. Likewise sizes[1] for the second alternative. */
1040 unsigned int sizes[2];
1042 /* The symbol on which the choice of sequence depends. */
1046 /* Global variables used to decide whether a macro needs a warning. */
1048 /* True if the macro is in a branch delay slot. */
1049 bfd_boolean delay_slot_p;
1051 /* For relaxable macros, sizes[0] is the length of the first alternative
1052 in bytes and sizes[1] is the length of the second alternative.
1053 For non-relaxable macros, both elements give the length of the
1055 unsigned int sizes[2];
1057 /* The first variant frag for this macro. */
1059 } mips_macro_warning;
1061 /* Prototypes for static functions. */
1063 #define internalError() \
1064 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1066 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1068 static void append_insn
1069 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1070 static void mips_no_prev_insn (void);
1071 static void macro_build (expressionS *, const char *, const char *, ...);
1072 static void mips16_macro_build
1073 (expressionS *, const char *, const char *, va_list *);
1074 static void load_register (int, expressionS *, int);
1075 static void macro_start (void);
1076 static void macro_end (void);
1077 static void macro (struct mips_cl_insn * ip);
1078 static void mips16_macro (struct mips_cl_insn * ip);
1079 static void mips_ip (char *str, struct mips_cl_insn * ip);
1080 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1081 static void mips16_immed
1082 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1083 unsigned long *, bfd_boolean *, unsigned short *);
1084 static size_t my_getSmallExpression
1085 (expressionS *, bfd_reloc_code_real_type *, char *);
1086 static void my_getExpression (expressionS *, char *);
1087 static void s_align (int);
1088 static void s_change_sec (int);
1089 static void s_change_section (int);
1090 static void s_cons (int);
1091 static void s_float_cons (int);
1092 static void s_mips_globl (int);
1093 static void s_option (int);
1094 static void s_mipsset (int);
1095 static void s_abicalls (int);
1096 static void s_cpload (int);
1097 static void s_cpsetup (int);
1098 static void s_cplocal (int);
1099 static void s_cprestore (int);
1100 static void s_cpreturn (int);
1101 static void s_dtprelword (int);
1102 static void s_dtpreldword (int);
1103 static void s_gpvalue (int);
1104 static void s_gpword (int);
1105 static void s_gpdword (int);
1106 static void s_cpadd (int);
1107 static void s_insn (int);
1108 static void md_obj_begin (void);
1109 static void md_obj_end (void);
1110 static void s_mips_ent (int);
1111 static void s_mips_end (int);
1112 static void s_mips_frame (int);
1113 static void s_mips_mask (int reg_type);
1114 static void s_mips_stab (int);
1115 static void s_mips_weakext (int);
1116 static void s_mips_file (int);
1117 static void s_mips_loc (int);
1118 static bfd_boolean pic_need_relax (symbolS *, asection *);
1119 static int relaxed_branch_length (fragS *, asection *, int);
1120 static int validate_mips_insn (const struct mips_opcode *);
1122 /* Table and functions used to map between CPU/ISA names, and
1123 ISA levels, and CPU numbers. */
1125 struct mips_cpu_info
1127 const char *name; /* CPU or ISA name. */
1128 int flags; /* ASEs available, or ISA flag. */
1129 int isa; /* ISA level. */
1130 int cpu; /* CPU number (default CPU if ISA). */
1133 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1134 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1135 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1136 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1137 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1138 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1139 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1141 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1142 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1143 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1147 The following pseudo-ops from the Kane and Heinrich MIPS book
1148 should be defined here, but are currently unsupported: .alias,
1149 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1151 The following pseudo-ops from the Kane and Heinrich MIPS book are
1152 specific to the type of debugging information being generated, and
1153 should be defined by the object format: .aent, .begin, .bend,
1154 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1157 The following pseudo-ops from the Kane and Heinrich MIPS book are
1158 not MIPS CPU specific, but are also not specific to the object file
1159 format. This file is probably the best place to define them, but
1160 they are not currently supported: .asm0, .endr, .lab, .struct. */
1162 static const pseudo_typeS mips_pseudo_table[] =
1164 /* MIPS specific pseudo-ops. */
1165 {"option", s_option, 0},
1166 {"set", s_mipsset, 0},
1167 {"rdata", s_change_sec, 'r'},
1168 {"sdata", s_change_sec, 's'},
1169 {"livereg", s_ignore, 0},
1170 {"abicalls", s_abicalls, 0},
1171 {"cpload", s_cpload, 0},
1172 {"cpsetup", s_cpsetup, 0},
1173 {"cplocal", s_cplocal, 0},
1174 {"cprestore", s_cprestore, 0},
1175 {"cpreturn", s_cpreturn, 0},
1176 {"dtprelword", s_dtprelword, 0},
1177 {"dtpreldword", s_dtpreldword, 0},
1178 {"gpvalue", s_gpvalue, 0},
1179 {"gpword", s_gpword, 0},
1180 {"gpdword", s_gpdword, 0},
1181 {"cpadd", s_cpadd, 0},
1182 {"insn", s_insn, 0},
1184 /* Relatively generic pseudo-ops that happen to be used on MIPS
1186 {"asciiz", stringer, 8 + 1},
1187 {"bss", s_change_sec, 'b'},
1189 {"half", s_cons, 1},
1190 {"dword", s_cons, 3},
1191 {"weakext", s_mips_weakext, 0},
1192 {"origin", s_org, 0},
1193 {"repeat", s_rept, 0},
1195 /* For MIPS this is non-standard, but we define it for consistency. */
1196 {"sbss", s_change_sec, 'B'},
1198 /* These pseudo-ops are defined in read.c, but must be overridden
1199 here for one reason or another. */
1200 {"align", s_align, 0},
1201 {"byte", s_cons, 0},
1202 {"data", s_change_sec, 'd'},
1203 {"double", s_float_cons, 'd'},
1204 {"float", s_float_cons, 'f'},
1205 {"globl", s_mips_globl, 0},
1206 {"global", s_mips_globl, 0},
1207 {"hword", s_cons, 1},
1209 {"long", s_cons, 2},
1210 {"octa", s_cons, 4},
1211 {"quad", s_cons, 3},
1212 {"section", s_change_section, 0},
1213 {"short", s_cons, 1},
1214 {"single", s_float_cons, 'f'},
1215 {"stabn", s_mips_stab, 'n'},
1216 {"text", s_change_sec, 't'},
1217 {"word", s_cons, 2},
1219 { "extern", ecoff_directive_extern, 0},
1224 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1226 /* These pseudo-ops should be defined by the object file format.
1227 However, a.out doesn't support them, so we have versions here. */
1228 {"aent", s_mips_ent, 1},
1229 {"bgnb", s_ignore, 0},
1230 {"end", s_mips_end, 0},
1231 {"endb", s_ignore, 0},
1232 {"ent", s_mips_ent, 0},
1233 {"file", s_mips_file, 0},
1234 {"fmask", s_mips_mask, 'F'},
1235 {"frame", s_mips_frame, 0},
1236 {"loc", s_mips_loc, 0},
1237 {"mask", s_mips_mask, 'R'},
1238 {"verstamp", s_ignore, 0},
1242 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1243 purpose of the `.dc.a' internal pseudo-op. */
1246 mips_address_bytes (void)
1248 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1251 extern void pop_insert (const pseudo_typeS *);
1254 mips_pop_insert (void)
1256 pop_insert (mips_pseudo_table);
1257 if (! ECOFF_DEBUGGING)
1258 pop_insert (mips_nonecoff_pseudo_table);
1261 /* Symbols labelling the current insn. */
1263 struct insn_label_list
1265 struct insn_label_list *next;
1269 static struct insn_label_list *free_insn_labels;
1270 #define label_list tc_segment_info_data.labels
1272 static void mips_clear_insn_labels (void);
1275 mips_clear_insn_labels (void)
1277 register struct insn_label_list **pl;
1278 segment_info_type *si;
1282 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1285 si = seg_info (now_seg);
1286 *pl = si->label_list;
1287 si->label_list = NULL;
1292 static char *expr_end;
1294 /* Expressions which appear in instructions. These are set by
1297 static expressionS imm_expr;
1298 static expressionS imm2_expr;
1299 static expressionS offset_expr;
1301 /* Relocs associated with imm_expr and offset_expr. */
1303 static bfd_reloc_code_real_type imm_reloc[3]
1304 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1305 static bfd_reloc_code_real_type offset_reloc[3]
1306 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1308 /* These are set by mips16_ip if an explicit extension is used. */
1310 static bfd_boolean mips16_small, mips16_ext;
1313 /* The pdr segment for per procedure frame/regmask info. Not used for
1316 static segT pdr_seg;
1319 /* The default target format to use. */
1321 #if defined (TE_FreeBSD)
1322 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1323 #elif defined (TE_TMIPS)
1324 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1326 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1330 mips_target_format (void)
1332 switch (OUTPUT_FLAVOR)
1334 case bfd_target_ecoff_flavour:
1335 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1336 case bfd_target_coff_flavour:
1338 case bfd_target_elf_flavour:
1340 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1341 return (target_big_endian
1342 ? "elf32-bigmips-vxworks"
1343 : "elf32-littlemips-vxworks");
1345 return (target_big_endian
1346 ? (HAVE_64BIT_OBJECTS
1347 ? ELF_TARGET ("elf64-", "big")
1349 ? ELF_TARGET ("elf32-n", "big")
1350 : ELF_TARGET ("elf32-", "big")))
1351 : (HAVE_64BIT_OBJECTS
1352 ? ELF_TARGET ("elf64-", "little")
1354 ? ELF_TARGET ("elf32-n", "little")
1355 : ELF_TARGET ("elf32-", "little"))));
1362 /* Return the length of instruction INSN. */
1364 static inline unsigned int
1365 insn_length (const struct mips_cl_insn *insn)
1367 if (!mips_opts.mips16)
1369 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1372 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1375 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1380 insn->use_extend = FALSE;
1382 insn->insn_opcode = mo->match;
1385 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1386 insn->fixp[i] = NULL;
1387 insn->fixed_p = (mips_opts.noreorder > 0);
1388 insn->noreorder_p = (mips_opts.noreorder > 0);
1389 insn->mips16_absolute_jump_p = 0;
1390 insn->complete_p = 0;
1393 /* Record the current MIPS16 mode in now_seg. */
1396 mips_record_mips16_mode (void)
1398 segment_info_type *si;
1400 si = seg_info (now_seg);
1401 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1402 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1405 /* Install INSN at the location specified by its "frag" and "where" fields. */
1408 install_insn (const struct mips_cl_insn *insn)
1410 char *f = insn->frag->fr_literal + insn->where;
1411 if (!mips_opts.mips16)
1412 md_number_to_chars (f, insn->insn_opcode, 4);
1413 else if (insn->mips16_absolute_jump_p)
1415 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1416 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1420 if (insn->use_extend)
1422 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1425 md_number_to_chars (f, insn->insn_opcode, 2);
1427 mips_record_mips16_mode ();
1430 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1431 and install the opcode in the new location. */
1434 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1439 insn->where = where;
1440 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1441 if (insn->fixp[i] != NULL)
1443 insn->fixp[i]->fx_frag = frag;
1444 insn->fixp[i]->fx_where = where;
1446 install_insn (insn);
1449 /* Add INSN to the end of the output. */
1452 add_fixed_insn (struct mips_cl_insn *insn)
1454 char *f = frag_more (insn_length (insn));
1455 move_insn (insn, frag_now, f - frag_now->fr_literal);
1458 /* Start a variant frag and move INSN to the start of the variant part,
1459 marking it as fixed. The other arguments are as for frag_var. */
1462 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1463 relax_substateT subtype, symbolS *symbol, offsetT offset)
1465 frag_grow (max_chars);
1466 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1468 frag_var (rs_machine_dependent, max_chars, var,
1469 subtype, symbol, offset, NULL);
1472 /* Insert N copies of INSN into the history buffer, starting at
1473 position FIRST. Neither FIRST nor N need to be clipped. */
1476 insert_into_history (unsigned int first, unsigned int n,
1477 const struct mips_cl_insn *insn)
1479 if (mips_relax.sequence != 2)
1483 for (i = ARRAY_SIZE (history); i-- > first;)
1485 history[i] = history[i - n];
1491 /* Emit a nop instruction, recording it in the history buffer. */
1496 add_fixed_insn (NOP_INSN);
1497 insert_into_history (0, 1, NOP_INSN);
1500 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1501 the idea is to make it obvious at a glance that each errata is
1505 init_vr4120_conflicts (void)
1507 #define CONFLICT(FIRST, SECOND) \
1508 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1510 /* Errata 21 - [D]DIV[U] after [D]MACC */
1511 CONFLICT (MACC, DIV);
1512 CONFLICT (DMACC, DIV);
1514 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1515 CONFLICT (DMULT, DMULT);
1516 CONFLICT (DMULT, DMACC);
1517 CONFLICT (DMACC, DMULT);
1518 CONFLICT (DMACC, DMACC);
1520 /* Errata 24 - MT{LO,HI} after [D]MACC */
1521 CONFLICT (MACC, MTHILO);
1522 CONFLICT (DMACC, MTHILO);
1524 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1525 instruction is executed immediately after a MACC or DMACC
1526 instruction, the result of [either instruction] is incorrect." */
1527 CONFLICT (MACC, MULT);
1528 CONFLICT (MACC, DMULT);
1529 CONFLICT (DMACC, MULT);
1530 CONFLICT (DMACC, DMULT);
1532 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1533 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1534 DDIV or DDIVU instruction, the result of the MACC or
1535 DMACC instruction is incorrect.". */
1536 CONFLICT (DMULT, MACC);
1537 CONFLICT (DMULT, DMACC);
1538 CONFLICT (DIV, MACC);
1539 CONFLICT (DIV, DMACC);
1549 #define RTYPE_MASK 0x1ff00
1550 #define RTYPE_NUM 0x00100
1551 #define RTYPE_FPU 0x00200
1552 #define RTYPE_FCC 0x00400
1553 #define RTYPE_VEC 0x00800
1554 #define RTYPE_GP 0x01000
1555 #define RTYPE_CP0 0x02000
1556 #define RTYPE_PC 0x04000
1557 #define RTYPE_ACC 0x08000
1558 #define RTYPE_CCC 0x10000
1559 #define RNUM_MASK 0x000ff
1560 #define RWARN 0x80000
1562 #define GENERIC_REGISTER_NUMBERS \
1563 {"$0", RTYPE_NUM | 0}, \
1564 {"$1", RTYPE_NUM | 1}, \
1565 {"$2", RTYPE_NUM | 2}, \
1566 {"$3", RTYPE_NUM | 3}, \
1567 {"$4", RTYPE_NUM | 4}, \
1568 {"$5", RTYPE_NUM | 5}, \
1569 {"$6", RTYPE_NUM | 6}, \
1570 {"$7", RTYPE_NUM | 7}, \
1571 {"$8", RTYPE_NUM | 8}, \
1572 {"$9", RTYPE_NUM | 9}, \
1573 {"$10", RTYPE_NUM | 10}, \
1574 {"$11", RTYPE_NUM | 11}, \
1575 {"$12", RTYPE_NUM | 12}, \
1576 {"$13", RTYPE_NUM | 13}, \
1577 {"$14", RTYPE_NUM | 14}, \
1578 {"$15", RTYPE_NUM | 15}, \
1579 {"$16", RTYPE_NUM | 16}, \
1580 {"$17", RTYPE_NUM | 17}, \
1581 {"$18", RTYPE_NUM | 18}, \
1582 {"$19", RTYPE_NUM | 19}, \
1583 {"$20", RTYPE_NUM | 20}, \
1584 {"$21", RTYPE_NUM | 21}, \
1585 {"$22", RTYPE_NUM | 22}, \
1586 {"$23", RTYPE_NUM | 23}, \
1587 {"$24", RTYPE_NUM | 24}, \
1588 {"$25", RTYPE_NUM | 25}, \
1589 {"$26", RTYPE_NUM | 26}, \
1590 {"$27", RTYPE_NUM | 27}, \
1591 {"$28", RTYPE_NUM | 28}, \
1592 {"$29", RTYPE_NUM | 29}, \
1593 {"$30", RTYPE_NUM | 30}, \
1594 {"$31", RTYPE_NUM | 31}
1596 #define FPU_REGISTER_NAMES \
1597 {"$f0", RTYPE_FPU | 0}, \
1598 {"$f1", RTYPE_FPU | 1}, \
1599 {"$f2", RTYPE_FPU | 2}, \
1600 {"$f3", RTYPE_FPU | 3}, \
1601 {"$f4", RTYPE_FPU | 4}, \
1602 {"$f5", RTYPE_FPU | 5}, \
1603 {"$f6", RTYPE_FPU | 6}, \
1604 {"$f7", RTYPE_FPU | 7}, \
1605 {"$f8", RTYPE_FPU | 8}, \
1606 {"$f9", RTYPE_FPU | 9}, \
1607 {"$f10", RTYPE_FPU | 10}, \
1608 {"$f11", RTYPE_FPU | 11}, \
1609 {"$f12", RTYPE_FPU | 12}, \
1610 {"$f13", RTYPE_FPU | 13}, \
1611 {"$f14", RTYPE_FPU | 14}, \
1612 {"$f15", RTYPE_FPU | 15}, \
1613 {"$f16", RTYPE_FPU | 16}, \
1614 {"$f17", RTYPE_FPU | 17}, \
1615 {"$f18", RTYPE_FPU | 18}, \
1616 {"$f19", RTYPE_FPU | 19}, \
1617 {"$f20", RTYPE_FPU | 20}, \
1618 {"$f21", RTYPE_FPU | 21}, \
1619 {"$f22", RTYPE_FPU | 22}, \
1620 {"$f23", RTYPE_FPU | 23}, \
1621 {"$f24", RTYPE_FPU | 24}, \
1622 {"$f25", RTYPE_FPU | 25}, \
1623 {"$f26", RTYPE_FPU | 26}, \
1624 {"$f27", RTYPE_FPU | 27}, \
1625 {"$f28", RTYPE_FPU | 28}, \
1626 {"$f29", RTYPE_FPU | 29}, \
1627 {"$f30", RTYPE_FPU | 30}, \
1628 {"$f31", RTYPE_FPU | 31}
1630 #define FPU_CONDITION_CODE_NAMES \
1631 {"$fcc0", RTYPE_FCC | 0}, \
1632 {"$fcc1", RTYPE_FCC | 1}, \
1633 {"$fcc2", RTYPE_FCC | 2}, \
1634 {"$fcc3", RTYPE_FCC | 3}, \
1635 {"$fcc4", RTYPE_FCC | 4}, \
1636 {"$fcc5", RTYPE_FCC | 5}, \
1637 {"$fcc6", RTYPE_FCC | 6}, \
1638 {"$fcc7", RTYPE_FCC | 7}
1640 #define COPROC_CONDITION_CODE_NAMES \
1641 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1642 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1643 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1644 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1645 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1646 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1647 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1648 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1650 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1651 {"$a4", RTYPE_GP | 8}, \
1652 {"$a5", RTYPE_GP | 9}, \
1653 {"$a6", RTYPE_GP | 10}, \
1654 {"$a7", RTYPE_GP | 11}, \
1655 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1656 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1657 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1658 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1659 {"$t0", RTYPE_GP | 12}, \
1660 {"$t1", RTYPE_GP | 13}, \
1661 {"$t2", RTYPE_GP | 14}, \
1662 {"$t3", RTYPE_GP | 15}
1664 #define O32_SYMBOLIC_REGISTER_NAMES \
1665 {"$t0", RTYPE_GP | 8}, \
1666 {"$t1", RTYPE_GP | 9}, \
1667 {"$t2", RTYPE_GP | 10}, \
1668 {"$t3", RTYPE_GP | 11}, \
1669 {"$t4", RTYPE_GP | 12}, \
1670 {"$t5", RTYPE_GP | 13}, \
1671 {"$t6", RTYPE_GP | 14}, \
1672 {"$t7", RTYPE_GP | 15}, \
1673 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1674 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1675 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1676 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1678 /* Remaining symbolic register names */
1679 #define SYMBOLIC_REGISTER_NAMES \
1680 {"$zero", RTYPE_GP | 0}, \
1681 {"$at", RTYPE_GP | 1}, \
1682 {"$AT", RTYPE_GP | 1}, \
1683 {"$v0", RTYPE_GP | 2}, \
1684 {"$v1", RTYPE_GP | 3}, \
1685 {"$a0", RTYPE_GP | 4}, \
1686 {"$a1", RTYPE_GP | 5}, \
1687 {"$a2", RTYPE_GP | 6}, \
1688 {"$a3", RTYPE_GP | 7}, \
1689 {"$s0", RTYPE_GP | 16}, \
1690 {"$s1", RTYPE_GP | 17}, \
1691 {"$s2", RTYPE_GP | 18}, \
1692 {"$s3", RTYPE_GP | 19}, \
1693 {"$s4", RTYPE_GP | 20}, \
1694 {"$s5", RTYPE_GP | 21}, \
1695 {"$s6", RTYPE_GP | 22}, \
1696 {"$s7", RTYPE_GP | 23}, \
1697 {"$t8", RTYPE_GP | 24}, \
1698 {"$t9", RTYPE_GP | 25}, \
1699 {"$k0", RTYPE_GP | 26}, \
1700 {"$kt0", RTYPE_GP | 26}, \
1701 {"$k1", RTYPE_GP | 27}, \
1702 {"$kt1", RTYPE_GP | 27}, \
1703 {"$gp", RTYPE_GP | 28}, \
1704 {"$sp", RTYPE_GP | 29}, \
1705 {"$s8", RTYPE_GP | 30}, \
1706 {"$fp", RTYPE_GP | 30}, \
1707 {"$ra", RTYPE_GP | 31}
1709 #define MIPS16_SPECIAL_REGISTER_NAMES \
1710 {"$pc", RTYPE_PC | 0}
1712 #define MDMX_VECTOR_REGISTER_NAMES \
1713 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1714 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1715 {"$v2", RTYPE_VEC | 2}, \
1716 {"$v3", RTYPE_VEC | 3}, \
1717 {"$v4", RTYPE_VEC | 4}, \
1718 {"$v5", RTYPE_VEC | 5}, \
1719 {"$v6", RTYPE_VEC | 6}, \
1720 {"$v7", RTYPE_VEC | 7}, \
1721 {"$v8", RTYPE_VEC | 8}, \
1722 {"$v9", RTYPE_VEC | 9}, \
1723 {"$v10", RTYPE_VEC | 10}, \
1724 {"$v11", RTYPE_VEC | 11}, \
1725 {"$v12", RTYPE_VEC | 12}, \
1726 {"$v13", RTYPE_VEC | 13}, \
1727 {"$v14", RTYPE_VEC | 14}, \
1728 {"$v15", RTYPE_VEC | 15}, \
1729 {"$v16", RTYPE_VEC | 16}, \
1730 {"$v17", RTYPE_VEC | 17}, \
1731 {"$v18", RTYPE_VEC | 18}, \
1732 {"$v19", RTYPE_VEC | 19}, \
1733 {"$v20", RTYPE_VEC | 20}, \
1734 {"$v21", RTYPE_VEC | 21}, \
1735 {"$v22", RTYPE_VEC | 22}, \
1736 {"$v23", RTYPE_VEC | 23}, \
1737 {"$v24", RTYPE_VEC | 24}, \
1738 {"$v25", RTYPE_VEC | 25}, \
1739 {"$v26", RTYPE_VEC | 26}, \
1740 {"$v27", RTYPE_VEC | 27}, \
1741 {"$v28", RTYPE_VEC | 28}, \
1742 {"$v29", RTYPE_VEC | 29}, \
1743 {"$v30", RTYPE_VEC | 30}, \
1744 {"$v31", RTYPE_VEC | 31}
1746 #define MIPS_DSP_ACCUMULATOR_NAMES \
1747 {"$ac0", RTYPE_ACC | 0}, \
1748 {"$ac1", RTYPE_ACC | 1}, \
1749 {"$ac2", RTYPE_ACC | 2}, \
1750 {"$ac3", RTYPE_ACC | 3}
1752 static const struct regname reg_names[] = {
1753 GENERIC_REGISTER_NUMBERS,
1755 FPU_CONDITION_CODE_NAMES,
1756 COPROC_CONDITION_CODE_NAMES,
1758 /* The $txx registers depends on the abi,
1759 these will be added later into the symbol table from
1760 one of the tables below once mips_abi is set after
1761 parsing of arguments from the command line. */
1762 SYMBOLIC_REGISTER_NAMES,
1764 MIPS16_SPECIAL_REGISTER_NAMES,
1765 MDMX_VECTOR_REGISTER_NAMES,
1766 MIPS_DSP_ACCUMULATOR_NAMES,
1770 static const struct regname reg_names_o32[] = {
1771 O32_SYMBOLIC_REGISTER_NAMES,
1775 static const struct regname reg_names_n32n64[] = {
1776 N32N64_SYMBOLIC_REGISTER_NAMES,
1781 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1788 /* Find end of name. */
1790 if (is_name_beginner (*e))
1792 while (is_part_of_name (*e))
1795 /* Terminate name. */
1799 /* Look for a register symbol. */
1800 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1802 int r = S_GET_VALUE (symbolP);
1804 reg = r & RNUM_MASK;
1805 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1806 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1807 reg = (r & RNUM_MASK) - 2;
1809 /* Else see if this is a register defined in an itbl entry. */
1810 else if ((types & RTYPE_GP) && itbl_have_entries)
1817 if (itbl_get_reg_val (n, &r))
1818 reg = r & RNUM_MASK;
1821 /* Advance to next token if a register was recognised. */
1824 else if (types & RWARN)
1825 as_warn (_("Unrecognized register name `%s'"), *s);
1833 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1834 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1837 is_opcode_valid (const struct mips_opcode *mo)
1839 int isa = mips_opts.isa;
1842 if (mips_opts.ase_mdmx)
1844 if (mips_opts.ase_dsp)
1846 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1848 if (mips_opts.ase_dspr2)
1850 if (mips_opts.ase_mt)
1852 if (mips_opts.ase_mips3d)
1854 if (mips_opts.ase_smartmips)
1855 isa |= INSN_SMARTMIPS;
1857 /* Don't accept instructions based on the ISA if the CPU does not implement
1858 all the coprocessor insns. */
1859 if (NO_ISA_COP (mips_opts.arch)
1860 && COP_INSN (mo->pinfo))
1863 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1866 /* Check whether the instruction or macro requires single-precision or
1867 double-precision floating-point support. Note that this information is
1868 stored differently in the opcode table for insns and macros. */
1869 if (mo->pinfo == INSN_MACRO)
1871 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1872 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1876 fp_s = mo->pinfo & FP_S;
1877 fp_d = mo->pinfo & FP_D;
1880 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1883 if (fp_s && mips_opts.soft_float)
1889 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1890 selected ISA and architecture. */
1893 is_opcode_valid_16 (const struct mips_opcode *mo)
1895 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1898 /* This function is called once, at assembler startup time. It should set up
1899 all the tables, etc. that the MD part of the assembler will need. */
1904 const char *retval = NULL;
1908 if (mips_pic != NO_PIC)
1910 if (g_switch_seen && g_switch_value != 0)
1911 as_bad (_("-G may not be used in position-independent code"));
1915 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1916 as_warn (_("Could not set architecture and machine"));
1918 op_hash = hash_new ();
1920 for (i = 0; i < NUMOPCODES;)
1922 const char *name = mips_opcodes[i].name;
1924 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1927 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1928 mips_opcodes[i].name, retval);
1929 /* Probably a memory allocation problem? Give up now. */
1930 as_fatal (_("Broken assembler. No assembly attempted."));
1934 if (mips_opcodes[i].pinfo != INSN_MACRO)
1936 if (!validate_mips_insn (&mips_opcodes[i]))
1938 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1940 create_insn (&nop_insn, mips_opcodes + i);
1941 if (mips_fix_loongson2f_nop)
1942 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1943 nop_insn.fixed_p = 1;
1948 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1951 mips16_op_hash = hash_new ();
1954 while (i < bfd_mips16_num_opcodes)
1956 const char *name = mips16_opcodes[i].name;
1958 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1960 as_fatal (_("internal: can't hash `%s': %s"),
1961 mips16_opcodes[i].name, retval);
1964 if (mips16_opcodes[i].pinfo != INSN_MACRO
1965 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1966 != mips16_opcodes[i].match))
1968 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1969 mips16_opcodes[i].name, mips16_opcodes[i].args);
1972 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1974 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1975 mips16_nop_insn.fixed_p = 1;
1979 while (i < bfd_mips16_num_opcodes
1980 && strcmp (mips16_opcodes[i].name, name) == 0);
1984 as_fatal (_("Broken assembler. No assembly attempted."));
1986 /* We add all the general register names to the symbol table. This
1987 helps us detect invalid uses of them. */
1988 for (i = 0; reg_names[i].name; i++)
1989 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1990 reg_names[i].num, /* & RNUM_MASK, */
1991 &zero_address_frag));
1993 for (i = 0; reg_names_n32n64[i].name; i++)
1994 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1995 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1996 &zero_address_frag));
1998 for (i = 0; reg_names_o32[i].name; i++)
1999 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2000 reg_names_o32[i].num, /* & RNUM_MASK, */
2001 &zero_address_frag));
2003 mips_no_prev_insn ();
2006 mips_cprmask[0] = 0;
2007 mips_cprmask[1] = 0;
2008 mips_cprmask[2] = 0;
2009 mips_cprmask[3] = 0;
2011 /* set the default alignment for the text section (2**2) */
2012 record_alignment (text_section, 2);
2014 bfd_set_gp_size (stdoutput, g_switch_value);
2019 /* On a native system other than VxWorks, sections must be aligned
2020 to 16 byte boundaries. When configured for an embedded ELF
2021 target, we don't bother. */
2022 if (strncmp (TARGET_OS, "elf", 3) != 0
2023 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2025 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2026 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2027 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2030 /* Create a .reginfo section for register masks and a .mdebug
2031 section for debugging information. */
2039 subseg = now_subseg;
2041 /* The ABI says this section should be loaded so that the
2042 running program can access it. However, we don't load it
2043 if we are configured for an embedded target */
2044 flags = SEC_READONLY | SEC_DATA;
2045 if (strncmp (TARGET_OS, "elf", 3) != 0)
2046 flags |= SEC_ALLOC | SEC_LOAD;
2048 if (mips_abi != N64_ABI)
2050 sec = subseg_new (".reginfo", (subsegT) 0);
2052 bfd_set_section_flags (stdoutput, sec, flags);
2053 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2055 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2059 /* The 64-bit ABI uses a .MIPS.options section rather than
2060 .reginfo section. */
2061 sec = subseg_new (".MIPS.options", (subsegT) 0);
2062 bfd_set_section_flags (stdoutput, sec, flags);
2063 bfd_set_section_alignment (stdoutput, sec, 3);
2065 /* Set up the option header. */
2067 Elf_Internal_Options opthdr;
2070 opthdr.kind = ODK_REGINFO;
2071 opthdr.size = (sizeof (Elf_External_Options)
2072 + sizeof (Elf64_External_RegInfo));
2075 f = frag_more (sizeof (Elf_External_Options));
2076 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2077 (Elf_External_Options *) f);
2079 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2083 if (ECOFF_DEBUGGING)
2085 sec = subseg_new (".mdebug", (subsegT) 0);
2086 (void) bfd_set_section_flags (stdoutput, sec,
2087 SEC_HAS_CONTENTS | SEC_READONLY);
2088 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2090 else if (mips_flag_pdr)
2092 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2093 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2094 SEC_READONLY | SEC_RELOC
2096 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2099 subseg_set (seg, subseg);
2102 #endif /* OBJ_ELF */
2104 if (! ECOFF_DEBUGGING)
2107 if (mips_fix_vr4120)
2108 init_vr4120_conflicts ();
2114 mips_emit_delays ();
2115 if (! ECOFF_DEBUGGING)
2120 md_assemble (char *str)
2122 struct mips_cl_insn insn;
2123 bfd_reloc_code_real_type unused_reloc[3]
2124 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2126 imm_expr.X_op = O_absent;
2127 imm2_expr.X_op = O_absent;
2128 offset_expr.X_op = O_absent;
2129 imm_reloc[0] = BFD_RELOC_UNUSED;
2130 imm_reloc[1] = BFD_RELOC_UNUSED;
2131 imm_reloc[2] = BFD_RELOC_UNUSED;
2132 offset_reloc[0] = BFD_RELOC_UNUSED;
2133 offset_reloc[1] = BFD_RELOC_UNUSED;
2134 offset_reloc[2] = BFD_RELOC_UNUSED;
2136 if (mips_opts.mips16)
2137 mips16_ip (str, &insn);
2140 mips_ip (str, &insn);
2141 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2142 str, insn.insn_opcode));
2147 as_bad ("%s `%s'", insn_error, str);
2151 if (insn.insn_mo->pinfo == INSN_MACRO)
2154 if (mips_opts.mips16)
2155 mips16_macro (&insn);
2162 if (imm_expr.X_op != O_absent)
2163 append_insn (&insn, &imm_expr, imm_reloc);
2164 else if (offset_expr.X_op != O_absent)
2165 append_insn (&insn, &offset_expr, offset_reloc);
2167 append_insn (&insn, NULL, unused_reloc);
2171 /* Convenience functions for abstracting away the differences between
2172 MIPS16 and non-MIPS16 relocations. */
2174 static inline bfd_boolean
2175 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2179 case BFD_RELOC_MIPS16_JMP:
2180 case BFD_RELOC_MIPS16_GPREL:
2181 case BFD_RELOC_MIPS16_GOT16:
2182 case BFD_RELOC_MIPS16_CALL16:
2183 case BFD_RELOC_MIPS16_HI16_S:
2184 case BFD_RELOC_MIPS16_HI16:
2185 case BFD_RELOC_MIPS16_LO16:
2193 static inline bfd_boolean
2194 got16_reloc_p (bfd_reloc_code_real_type reloc)
2196 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2199 static inline bfd_boolean
2200 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2202 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2205 static inline bfd_boolean
2206 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2208 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2211 /* Return true if the given relocation might need a matching %lo().
2212 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2213 need a matching %lo() when applied to local symbols. */
2215 static inline bfd_boolean
2216 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2218 return (HAVE_IN_PLACE_ADDENDS
2219 && (hi16_reloc_p (reloc)
2220 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2221 all GOT16 relocations evaluate to "G". */
2222 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2225 /* Return the type of %lo() reloc needed by RELOC, given that
2226 reloc_needs_lo_p. */
2228 static inline bfd_reloc_code_real_type
2229 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2231 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2234 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2237 static inline bfd_boolean
2238 fixup_has_matching_lo_p (fixS *fixp)
2240 return (fixp->fx_next != NULL
2241 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2242 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2243 && fixp->fx_offset == fixp->fx_next->fx_offset);
2246 /* This function returns true if modifying a register requires a
2250 reg_needs_delay (unsigned int reg)
2252 unsigned long prev_pinfo;
2254 prev_pinfo = history[0].insn_mo->pinfo;
2255 if (! mips_opts.noreorder
2256 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2257 && ! gpr_interlocks)
2258 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2259 && ! cop_interlocks)))
2261 /* A load from a coprocessor or from memory. All load delays
2262 delay the use of general register rt for one instruction. */
2263 /* Itbl support may require additional care here. */
2264 know (prev_pinfo & INSN_WRITE_GPR_T);
2265 if (reg == EXTRACT_OPERAND (RT, history[0]))
2272 /* Move all labels in insn_labels to the current insertion point. */
2275 mips_move_labels (void)
2277 segment_info_type *si = seg_info (now_seg);
2278 struct insn_label_list *l;
2281 for (l = si->label_list; l != NULL; l = l->next)
2283 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2284 symbol_set_frag (l->label, frag_now);
2285 val = (valueT) frag_now_fix ();
2286 /* mips16 text labels are stored as odd. */
2287 if (mips_opts.mips16)
2289 S_SET_VALUE (l->label, val);
2294 s_is_linkonce (symbolS *sym, segT from_seg)
2296 bfd_boolean linkonce = FALSE;
2297 segT symseg = S_GET_SEGMENT (sym);
2299 if (symseg != from_seg && !S_IS_LOCAL (sym))
2301 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2304 /* The GNU toolchain uses an extension for ELF: a section
2305 beginning with the magic string .gnu.linkonce is a
2306 linkonce section. */
2307 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2308 sizeof ".gnu.linkonce" - 1) == 0)
2315 /* Mark instruction labels in mips16 mode. This permits the linker to
2316 handle them specially, such as generating jalx instructions when
2317 needed. We also make them odd for the duration of the assembly, in
2318 order to generate the right sort of code. We will make them even
2319 in the adjust_symtab routine, while leaving them marked. This is
2320 convenient for the debugger and the disassembler. The linker knows
2321 to make them odd again. */
2324 mips16_mark_labels (void)
2326 segment_info_type *si = seg_info (now_seg);
2327 struct insn_label_list *l;
2329 if (!mips_opts.mips16)
2332 for (l = si->label_list; l != NULL; l = l->next)
2334 symbolS *label = l->label;
2336 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2338 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2340 if ((S_GET_VALUE (label) & 1) == 0
2341 /* Don't adjust the address if the label is global or weak, or
2342 in a link-once section, since we'll be emitting symbol reloc
2343 references to it which will be patched up by the linker, and
2344 the final value of the symbol may or may not be MIPS16. */
2345 && ! S_IS_WEAK (label)
2346 && ! S_IS_EXTERNAL (label)
2347 && ! s_is_linkonce (label, now_seg))
2348 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2352 /* End the current frag. Make it a variant frag and record the
2356 relax_close_frag (void)
2358 mips_macro_warning.first_frag = frag_now;
2359 frag_var (rs_machine_dependent, 0, 0,
2360 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2361 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2363 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2364 mips_relax.first_fixup = 0;
2367 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2368 See the comment above RELAX_ENCODE for more details. */
2371 relax_start (symbolS *symbol)
2373 gas_assert (mips_relax.sequence == 0);
2374 mips_relax.sequence = 1;
2375 mips_relax.symbol = symbol;
2378 /* Start generating the second version of a relaxable sequence.
2379 See the comment above RELAX_ENCODE for more details. */
2384 gas_assert (mips_relax.sequence == 1);
2385 mips_relax.sequence = 2;
2388 /* End the current relaxable sequence. */
2393 gas_assert (mips_relax.sequence == 2);
2394 relax_close_frag ();
2395 mips_relax.sequence = 0;
2398 /* Return the mask of core registers that IP reads. */
2401 gpr_read_mask (const struct mips_cl_insn *ip)
2403 unsigned long pinfo, pinfo2;
2407 pinfo = ip->insn_mo->pinfo;
2408 pinfo2 = ip->insn_mo->pinfo2;
2409 if (mips_opts.mips16)
2411 if (pinfo & MIPS16_INSN_READ_X)
2412 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2413 if (pinfo & MIPS16_INSN_READ_Y)
2414 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2415 if (pinfo & MIPS16_INSN_READ_T)
2417 if (pinfo & MIPS16_INSN_READ_SP)
2419 if (pinfo & MIPS16_INSN_READ_31)
2421 if (pinfo & MIPS16_INSN_READ_Z)
2422 mask |= 1 << (mips16_to_32_reg_map
2423 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2424 if (pinfo & MIPS16_INSN_READ_GPR_X)
2425 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2429 if (pinfo2 & INSN2_READ_GPR_D)
2430 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2431 if (pinfo & INSN_READ_GPR_T)
2432 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2433 if (pinfo & INSN_READ_GPR_S)
2434 mask |= 1 << EXTRACT_OPERAND (RS, *ip);
2435 if (pinfo2 & INSN2_READ_GPR_Z)
2436 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2441 /* Return the mask of core registers that IP writes. */
2444 gpr_write_mask (const struct mips_cl_insn *ip)
2446 unsigned long pinfo, pinfo2;
2450 pinfo = ip->insn_mo->pinfo;
2451 pinfo2 = ip->insn_mo->pinfo2;
2452 if (mips_opts.mips16)
2454 if (pinfo & MIPS16_INSN_WRITE_X)
2455 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2456 if (pinfo & MIPS16_INSN_WRITE_Y)
2457 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2458 if (pinfo & MIPS16_INSN_WRITE_Z)
2459 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
2460 if (pinfo & MIPS16_INSN_WRITE_T)
2462 if (pinfo & MIPS16_INSN_WRITE_SP)
2464 if (pinfo & MIPS16_INSN_WRITE_31)
2466 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2467 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2471 if (pinfo & INSN_WRITE_GPR_D)
2472 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2473 if (pinfo & INSN_WRITE_GPR_T)
2474 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2475 if (pinfo & INSN_WRITE_GPR_31)
2477 if (pinfo2 & INSN2_WRITE_GPR_Z)
2478 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2483 /* Return the mask of floating-point registers that IP reads. */
2486 fpr_read_mask (const struct mips_cl_insn *ip)
2488 unsigned long pinfo, pinfo2;
2492 pinfo = ip->insn_mo->pinfo;
2493 pinfo2 = ip->insn_mo->pinfo2;
2494 if (!mips_opts.mips16)
2496 if (pinfo & INSN_READ_FPR_S)
2497 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2498 if (pinfo & INSN_READ_FPR_T)
2499 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2500 if (pinfo & INSN_READ_FPR_R)
2501 mask |= 1 << EXTRACT_OPERAND (FR, *ip);
2502 if (pinfo2 & INSN2_READ_FPR_Z)
2503 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2505 /* Conservatively treat all operands to an FP_D instruction are doubles.
2506 (This is overly pessimistic for things like cvt.d.s.) */
2507 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2512 /* Return the mask of floating-point registers that IP writes. */
2515 fpr_write_mask (const struct mips_cl_insn *ip)
2517 unsigned long pinfo, pinfo2;
2521 pinfo = ip->insn_mo->pinfo;
2522 pinfo2 = ip->insn_mo->pinfo2;
2523 if (!mips_opts.mips16)
2525 if (pinfo & INSN_WRITE_FPR_D)
2526 mask |= 1 << EXTRACT_OPERAND (FD, *ip);
2527 if (pinfo & INSN_WRITE_FPR_S)
2528 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2529 if (pinfo & INSN_WRITE_FPR_T)
2530 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2531 if (pinfo2 & INSN2_WRITE_FPR_Z)
2532 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2534 /* Conservatively treat all operands to an FP_D instruction are doubles.
2535 (This is overly pessimistic for things like cvt.s.d.) */
2536 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2541 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2542 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2543 by VR4120 errata. */
2546 classify_vr4120_insn (const char *name)
2548 if (strncmp (name, "macc", 4) == 0)
2549 return FIX_VR4120_MACC;
2550 if (strncmp (name, "dmacc", 5) == 0)
2551 return FIX_VR4120_DMACC;
2552 if (strncmp (name, "mult", 4) == 0)
2553 return FIX_VR4120_MULT;
2554 if (strncmp (name, "dmult", 5) == 0)
2555 return FIX_VR4120_DMULT;
2556 if (strstr (name, "div"))
2557 return FIX_VR4120_DIV;
2558 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2559 return FIX_VR4120_MTHILO;
2560 return NUM_FIX_VR4120_CLASSES;
2563 #define INSN_ERET 0x42000018
2564 #define INSN_DERET 0x4200001f
2566 /* Return the number of instructions that must separate INSN1 and INSN2,
2567 where INSN1 is the earlier instruction. Return the worst-case value
2568 for any INSN2 if INSN2 is null. */
2571 insns_between (const struct mips_cl_insn *insn1,
2572 const struct mips_cl_insn *insn2)
2574 unsigned long pinfo1, pinfo2;
2577 /* This function needs to know which pinfo flags are set for INSN2
2578 and which registers INSN2 uses. The former is stored in PINFO2 and
2579 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
2580 will have every flag set and INSN2_USES_GPR will always return true. */
2581 pinfo1 = insn1->insn_mo->pinfo;
2582 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2584 #define INSN2_USES_GPR(REG) \
2585 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
2587 /* For most targets, write-after-read dependencies on the HI and LO
2588 registers must be separated by at least two instructions. */
2589 if (!hilo_interlocks)
2591 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2593 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2597 /* If we're working around r7000 errata, there must be two instructions
2598 between an mfhi or mflo and any instruction that uses the result. */
2599 if (mips_7000_hilo_fix
2600 && MF_HILO_INSN (pinfo1)
2601 && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1)))
2604 /* If we're working around 24K errata, one instruction is required
2605 if an ERET or DERET is followed by a branch instruction. */
2608 if (insn1->insn_opcode == INSN_ERET
2609 || insn1->insn_opcode == INSN_DERET)
2612 || insn2->insn_opcode == INSN_ERET
2613 || insn2->insn_opcode == INSN_DERET
2614 || (insn2->insn_mo->pinfo
2615 & (INSN_UNCOND_BRANCH_DELAY
2616 | INSN_COND_BRANCH_DELAY
2617 | INSN_COND_BRANCH_LIKELY)) != 0)
2622 /* If working around VR4120 errata, check for combinations that need
2623 a single intervening instruction. */
2624 if (mips_fix_vr4120)
2626 unsigned int class1, class2;
2628 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2629 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2633 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2634 if (vr4120_conflicts[class1] & (1 << class2))
2639 if (!mips_opts.mips16)
2641 /* Check for GPR or coprocessor load delays. All such delays
2642 are on the RT register. */
2643 /* Itbl support may require additional care here. */
2644 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2645 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2647 know (pinfo1 & INSN_WRITE_GPR_T);
2648 if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1)))
2652 /* Check for generic coprocessor hazards.
2654 This case is not handled very well. There is no special
2655 knowledge of CP0 handling, and the coprocessors other than
2656 the floating point unit are not distinguished at all. */
2657 /* Itbl support may require additional care here. FIXME!
2658 Need to modify this to include knowledge about
2659 user specified delays! */
2660 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2661 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2663 /* Handle cases where INSN1 writes to a known general coprocessor
2664 register. There must be a one instruction delay before INSN2
2665 if INSN2 reads that register, otherwise no delay is needed. */
2666 mask = fpr_write_mask (insn1);
2669 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
2674 /* Read-after-write dependencies on the control registers
2675 require a two-instruction gap. */
2676 if ((pinfo1 & INSN_WRITE_COND_CODE)
2677 && (pinfo2 & INSN_READ_COND_CODE))
2680 /* We don't know exactly what INSN1 does. If INSN2 is
2681 also a coprocessor instruction, assume there must be
2682 a one instruction gap. */
2683 if (pinfo2 & INSN_COP)
2688 /* Check for read-after-write dependencies on the coprocessor
2689 control registers in cases where INSN1 does not need a general
2690 coprocessor delay. This means that INSN1 is a floating point
2691 comparison instruction. */
2692 /* Itbl support may require additional care here. */
2693 else if (!cop_interlocks
2694 && (pinfo1 & INSN_WRITE_COND_CODE)
2695 && (pinfo2 & INSN_READ_COND_CODE))
2699 #undef INSN2_USES_GPR
2704 /* Return the number of nops that would be needed to work around the
2705 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2706 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2707 that are contained within the first IGNORE instructions of HIST. */
2710 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2711 const struct mips_cl_insn *insn)
2716 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2717 are not affected by the errata. */
2719 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2720 || strcmp (insn->insn_mo->name, "mtlo") == 0
2721 || strcmp (insn->insn_mo->name, "mthi") == 0))
2724 /* Search for the first MFLO or MFHI. */
2725 for (i = 0; i < MAX_VR4130_NOPS; i++)
2726 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2728 /* Extract the destination register. */
2729 mask = gpr_write_mask (&hist[i]);
2731 /* No nops are needed if INSN reads that register. */
2732 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
2735 /* ...or if any of the intervening instructions do. */
2736 for (j = 0; j < i; j++)
2737 if (gpr_read_mask (&hist[j]) & mask)
2741 return MAX_VR4130_NOPS - i;
2746 #define BASE_REG_EQ(INSN1, INSN2) \
2747 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2748 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2750 /* Return the minimum alignment for this store instruction. */
2753 fix_24k_align_to (const struct mips_opcode *mo)
2755 if (strcmp (mo->name, "sh") == 0)
2758 if (strcmp (mo->name, "swc1") == 0
2759 || strcmp (mo->name, "swc2") == 0
2760 || strcmp (mo->name, "sw") == 0
2761 || strcmp (mo->name, "sc") == 0
2762 || strcmp (mo->name, "s.s") == 0)
2765 if (strcmp (mo->name, "sdc1") == 0
2766 || strcmp (mo->name, "sdc2") == 0
2767 || strcmp (mo->name, "s.d") == 0)
2774 struct fix_24k_store_info
2776 /* Immediate offset, if any, for this store instruction. */
2778 /* Alignment required by this store instruction. */
2780 /* True for register offsets. */
2781 int register_offset;
2784 /* Comparison function used by qsort. */
2787 fix_24k_sort (const void *a, const void *b)
2789 const struct fix_24k_store_info *pos1 = a;
2790 const struct fix_24k_store_info *pos2 = b;
2792 return (pos1->off - pos2->off);
2795 /* INSN is a store instruction. Try to record the store information
2796 in STINFO. Return false if the information isn't known. */
2799 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2800 const struct mips_cl_insn *insn)
2802 /* The instruction must have a known offset. */
2803 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2806 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2807 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2811 /* Return the number of nops that would be needed to work around the 24k
2812 "lost data on stores during refill" errata if instruction INSN
2813 immediately followed the 2 instructions described by HIST.
2814 Ignore hazards that are contained within the first IGNORE
2815 instructions of HIST.
2817 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2818 for the data cache refills and store data. The following describes
2819 the scenario where the store data could be lost.
2821 * A data cache miss, due to either a load or a store, causing fill
2822 data to be supplied by the memory subsystem
2823 * The first three doublewords of fill data are returned and written
2825 * A sequence of four stores occurs in consecutive cycles around the
2826 final doubleword of the fill:
2830 * Zero, One or more instructions
2833 The four stores A-D must be to different doublewords of the line that
2834 is being filled. The fourth instruction in the sequence above permits
2835 the fill of the final doubleword to be transferred from the FSB into
2836 the cache. In the sequence above, the stores may be either integer
2837 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2838 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2839 different doublewords on the line. If the floating point unit is
2840 running in 1:2 mode, it is not possible to create the sequence above
2841 using only floating point store instructions.
2843 In this case, the cache line being filled is incorrectly marked
2844 invalid, thereby losing the data from any store to the line that
2845 occurs between the original miss and the completion of the five
2846 cycle sequence shown above.
2848 The workarounds are:
2850 * Run the data cache in write-through mode.
2851 * Insert a non-store instruction between
2852 Store A and Store B or Store B and Store C. */
2855 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2856 const struct mips_cl_insn *insn)
2858 struct fix_24k_store_info pos[3];
2859 int align, i, base_offset;
2864 /* If the previous instruction wasn't a store, there's nothing to
2866 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2869 /* If the instructions after the previous one are unknown, we have
2870 to assume the worst. */
2874 /* Check whether we are dealing with three consecutive stores. */
2875 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
2876 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2879 /* If we don't know the relationship between the store addresses,
2880 assume the worst. */
2881 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2882 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2885 if (!fix_24k_record_store_info (&pos[0], insn)
2886 || !fix_24k_record_store_info (&pos[1], &hist[0])
2887 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2890 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2892 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2893 X bytes and such that the base register + X is known to be aligned
2896 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2900 align = pos[0].align_to;
2901 base_offset = pos[0].off;
2902 for (i = 1; i < 3; i++)
2903 if (align < pos[i].align_to)
2905 align = pos[i].align_to;
2906 base_offset = pos[i].off;
2908 for (i = 0; i < 3; i++)
2909 pos[i].off -= base_offset;
2912 pos[0].off &= ~align + 1;
2913 pos[1].off &= ~align + 1;
2914 pos[2].off &= ~align + 1;
2916 /* If any two stores write to the same chunk, they also write to the
2917 same doubleword. The offsets are still sorted at this point. */
2918 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2921 /* A range of at least 9 bytes is needed for the stores to be in
2922 non-overlapping doublewords. */
2923 if (pos[2].off - pos[0].off <= 8)
2926 if (pos[2].off - pos[1].off >= 24
2927 || pos[1].off - pos[0].off >= 24
2928 || pos[2].off - pos[0].off >= 32)
2934 /* Return the number of nops that would be needed if instruction INSN
2935 immediately followed the MAX_NOPS instructions given by HIST,
2936 where HIST[0] is the most recent instruction. Ignore hazards
2937 between INSN and the first IGNORE instructions in HIST.
2939 If INSN is null, return the worse-case number of nops for any
2943 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2944 const struct mips_cl_insn *insn)
2946 int i, nops, tmp_nops;
2949 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2951 tmp_nops = insns_between (hist + i, insn) - i;
2952 if (tmp_nops > nops)
2956 if (mips_fix_vr4130)
2958 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2959 if (tmp_nops > nops)
2965 tmp_nops = nops_for_24k (ignore, hist, insn);
2966 if (tmp_nops > nops)
2973 /* The variable arguments provide NUM_INSNS extra instructions that
2974 might be added to HIST. Return the largest number of nops that
2975 would be needed after the extended sequence, ignoring hazards
2976 in the first IGNORE instructions. */
2979 nops_for_sequence (int num_insns, int ignore,
2980 const struct mips_cl_insn *hist, ...)
2983 struct mips_cl_insn buffer[MAX_NOPS];
2984 struct mips_cl_insn *cursor;
2987 va_start (args, hist);
2988 cursor = buffer + num_insns;
2989 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2990 while (cursor > buffer)
2991 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2993 nops = nops_for_insn (ignore, buffer, NULL);
2998 /* Like nops_for_insn, but if INSN is a branch, take into account the
2999 worst-case delay for the branch target. */
3002 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3003 const struct mips_cl_insn *insn)
3007 nops = nops_for_insn (ignore, hist, insn);
3008 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3009 | INSN_COND_BRANCH_DELAY
3010 | INSN_COND_BRANCH_LIKELY))
3012 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3013 hist, insn, NOP_INSN);
3014 if (tmp_nops > nops)
3017 else if (mips_opts.mips16
3018 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3019 | MIPS16_INSN_COND_BRANCH)))
3021 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3022 if (tmp_nops > nops)
3028 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3031 fix_loongson2f_nop (struct mips_cl_insn * ip)
3033 if (strcmp (ip->insn_mo->name, "nop") == 0)
3034 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3037 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3038 jr target pc &= 'hffff_ffff_cfff_ffff. */
3041 fix_loongson2f_jump (struct mips_cl_insn * ip)
3043 if (strcmp (ip->insn_mo->name, "j") == 0
3044 || strcmp (ip->insn_mo->name, "jr") == 0
3045 || strcmp (ip->insn_mo->name, "jalr") == 0)
3053 sreg = EXTRACT_OPERAND (RS, *ip);
3054 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3057 ep.X_op = O_constant;
3058 ep.X_add_number = 0xcfff0000;
3059 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3060 ep.X_add_number = 0xffff;
3061 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3062 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3067 fix_loongson2f (struct mips_cl_insn * ip)
3069 if (mips_fix_loongson2f_nop)
3070 fix_loongson2f_nop (ip);
3072 if (mips_fix_loongson2f_jump)
3073 fix_loongson2f_jump (ip);
3076 /* Output an instruction. IP is the instruction information.
3077 ADDRESS_EXPR is an operand of the instruction to be used with
3081 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3082 bfd_reloc_code_real_type *reloc_type)
3084 unsigned long prev_pinfo, pinfo;
3085 unsigned long prev_pinfo2, pinfo2;
3086 relax_stateT prev_insn_frag_type = 0;
3087 bfd_boolean relaxed_branch = FALSE;
3088 segment_info_type *si = seg_info (now_seg);
3090 if (mips_fix_loongson2f)
3091 fix_loongson2f (ip);
3093 /* Mark instruction labels in mips16 mode. */
3094 mips16_mark_labels ();
3096 file_ase_mips16 |= mips_opts.mips16;
3098 prev_pinfo = history[0].insn_mo->pinfo;
3099 prev_pinfo2 = history[0].insn_mo->pinfo2;
3100 pinfo = ip->insn_mo->pinfo;
3101 pinfo2 = ip->insn_mo->pinfo2;
3103 if (address_expr == NULL)
3105 else if (*reloc_type <= BFD_RELOC_UNUSED
3106 && address_expr->X_op == O_constant)
3111 switch (*reloc_type)
3114 ip->insn_opcode |= address_expr->X_add_number;
3117 case BFD_RELOC_MIPS_HIGHEST:
3118 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3119 ip->insn_opcode |= tmp & 0xffff;
3122 case BFD_RELOC_MIPS_HIGHER:
3123 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3124 ip->insn_opcode |= tmp & 0xffff;
3127 case BFD_RELOC_HI16_S:
3128 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3129 ip->insn_opcode |= tmp & 0xffff;
3132 case BFD_RELOC_HI16:
3133 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3136 case BFD_RELOC_UNUSED:
3137 case BFD_RELOC_LO16:
3138 case BFD_RELOC_MIPS_GOT_DISP:
3139 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3142 case BFD_RELOC_MIPS_JMP:
3143 if ((address_expr->X_add_number & 3) != 0)
3144 as_bad (_("jump to misaligned address (0x%lx)"),
3145 (unsigned long) address_expr->X_add_number);
3146 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3150 case BFD_RELOC_MIPS16_JMP:
3151 if ((address_expr->X_add_number & 3) != 0)
3152 as_bad (_("jump to misaligned address (0x%lx)"),
3153 (unsigned long) address_expr->X_add_number);
3155 (((address_expr->X_add_number & 0x7c0000) << 3)
3156 | ((address_expr->X_add_number & 0xf800000) >> 7)
3157 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3161 case BFD_RELOC_16_PCREL_S2:
3162 if ((address_expr->X_add_number & 3) != 0)
3163 as_bad (_("branch to misaligned address (0x%lx)"),
3164 (unsigned long) address_expr->X_add_number);
3165 if (mips_relax_branch)
3167 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3168 as_bad (_("branch address range overflow (0x%lx)"),
3169 (unsigned long) address_expr->X_add_number);
3170 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3179 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3181 /* There are a lot of optimizations we could do that we don't.
3182 In particular, we do not, in general, reorder instructions.
3183 If you use gcc with optimization, it will reorder
3184 instructions and generally do much more optimization then we
3185 do here; repeating all that work in the assembler would only
3186 benefit hand written assembly code, and does not seem worth
3188 int nops = (mips_optimize == 0
3189 ? nops_for_insn (0, history, NULL)
3190 : nops_for_insn_or_target (0, history, ip));
3194 unsigned long old_frag_offset;
3197 old_frag = frag_now;
3198 old_frag_offset = frag_now_fix ();
3200 for (i = 0; i < nops; i++)
3205 listing_prev_line ();
3206 /* We may be at the start of a variant frag. In case we
3207 are, make sure there is enough space for the frag
3208 after the frags created by listing_prev_line. The
3209 argument to frag_grow here must be at least as large
3210 as the argument to all other calls to frag_grow in
3211 this file. We don't have to worry about being in the
3212 middle of a variant frag, because the variants insert
3213 all needed nop instructions themselves. */
3217 mips_move_labels ();
3219 #ifndef NO_ECOFF_DEBUGGING
3220 if (ECOFF_DEBUGGING)
3221 ecoff_fix_loc (old_frag, old_frag_offset);
3225 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3229 /* Work out how many nops in prev_nop_frag are needed by IP,
3230 ignoring hazards generated by the first prev_nop_frag_since
3232 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3233 gas_assert (nops <= prev_nop_frag_holds);
3235 /* Enforce NOPS as a minimum. */
3236 if (nops > prev_nop_frag_required)
3237 prev_nop_frag_required = nops;
3239 if (prev_nop_frag_holds == prev_nop_frag_required)
3241 /* Settle for the current number of nops. Update the history
3242 accordingly (for the benefit of any future .set reorder code). */
3243 prev_nop_frag = NULL;
3244 insert_into_history (prev_nop_frag_since,
3245 prev_nop_frag_holds, NOP_INSN);
3249 /* Allow this instruction to replace one of the nops that was
3250 tentatively added to prev_nop_frag. */
3251 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3252 prev_nop_frag_holds--;
3253 prev_nop_frag_since++;
3258 /* The value passed to dwarf2_emit_insn is the distance between
3259 the beginning of the current instruction and the address that
3260 should be recorded in the debug tables. For MIPS16 debug info
3261 we want to use ISA-encoded addresses, so we pass -1 for an
3262 address higher by one than the current. */
3263 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
3266 /* Record the frag type before frag_var. */
3267 if (history[0].frag)
3268 prev_insn_frag_type = history[0].frag->fr_type;
3271 && *reloc_type == BFD_RELOC_16_PCREL_S2
3272 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3273 || pinfo & INSN_COND_BRANCH_LIKELY)
3274 && mips_relax_branch
3275 /* Don't try branch relaxation within .set nomacro, or within
3276 .set noat if we use $at for PIC computations. If it turns
3277 out that the branch was out-of-range, we'll get an error. */
3278 && !mips_opts.warn_about_macros
3279 && (mips_opts.at || mips_pic == NO_PIC)
3280 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3281 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3282 && !mips_opts.mips16)
3284 relaxed_branch = TRUE;
3285 add_relaxed_insn (ip, (relaxed_branch_length
3287 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3288 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3292 pinfo & INSN_UNCOND_BRANCH_DELAY,
3293 pinfo & INSN_COND_BRANCH_LIKELY,
3294 pinfo & INSN_WRITE_GPR_31,
3296 address_expr->X_add_symbol,
3297 address_expr->X_add_number);
3298 *reloc_type = BFD_RELOC_UNUSED;
3300 else if (*reloc_type > BFD_RELOC_UNUSED)
3302 /* We need to set up a variant frag. */
3303 gas_assert (mips_opts.mips16 && address_expr != NULL);
3304 add_relaxed_insn (ip, 4, 0,
3306 (*reloc_type - BFD_RELOC_UNUSED,
3307 mips16_small, mips16_ext,
3308 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3309 history[0].mips16_absolute_jump_p),
3310 make_expr_symbol (address_expr), 0);
3312 else if (mips_opts.mips16
3314 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3316 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3317 /* Make sure there is enough room to swap this instruction with
3318 a following jump instruction. */
3320 add_fixed_insn (ip);
3324 if (mips_opts.mips16
3325 && mips_opts.noreorder
3326 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3327 as_warn (_("extended instruction in delay slot"));
3329 if (mips_relax.sequence)
3331 /* If we've reached the end of this frag, turn it into a variant
3332 frag and record the information for the instructions we've
3334 if (frag_room () < 4)
3335 relax_close_frag ();
3336 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3339 if (mips_relax.sequence != 2)
3340 mips_macro_warning.sizes[0] += 4;
3341 if (mips_relax.sequence != 1)
3342 mips_macro_warning.sizes[1] += 4;
3344 if (mips_opts.mips16)
3347 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3349 add_fixed_insn (ip);
3352 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
3355 && *reloc_type < BFD_RELOC_UNUSED)
3358 reloc_howto_type *howto;
3361 /* In a compound relocation, it is the final (outermost)
3362 operator that determines the relocated field. */
3363 for (i = 1; i < 3; i++)
3364 if (reloc_type[i] == BFD_RELOC_UNUSED)
3367 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3370 /* To reproduce this failure try assembling gas/testsuites/
3371 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3373 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3374 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3377 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3378 bfd_get_reloc_size (howto),
3380 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3383 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3384 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3385 && ip->fixp[0]->fx_addsy)
3386 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3388 /* These relocations can have an addend that won't fit in
3389 4 octets for 64bit assembly. */
3391 && ! howto->partial_inplace
3392 && (reloc_type[0] == BFD_RELOC_16
3393 || reloc_type[0] == BFD_RELOC_32
3394 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3395 || reloc_type[0] == BFD_RELOC_GPREL16
3396 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3397 || reloc_type[0] == BFD_RELOC_GPREL32
3398 || reloc_type[0] == BFD_RELOC_64
3399 || reloc_type[0] == BFD_RELOC_CTOR
3400 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3401 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3402 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3403 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3404 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3405 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3406 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3407 || hi16_reloc_p (reloc_type[0])
3408 || lo16_reloc_p (reloc_type[0])))
3409 ip->fixp[0]->fx_no_overflow = 1;
3411 if (mips_relax.sequence)
3413 if (mips_relax.first_fixup == 0)
3414 mips_relax.first_fixup = ip->fixp[0];
3416 else if (reloc_needs_lo_p (*reloc_type))
3418 struct mips_hi_fixup *hi_fixup;
3420 /* Reuse the last entry if it already has a matching %lo. */
3421 hi_fixup = mips_hi_fixup_list;
3423 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3425 hi_fixup = ((struct mips_hi_fixup *)
3426 xmalloc (sizeof (struct mips_hi_fixup)));
3427 hi_fixup->next = mips_hi_fixup_list;
3428 mips_hi_fixup_list = hi_fixup;
3430 hi_fixup->fixp = ip->fixp[0];
3431 hi_fixup->seg = now_seg;
3434 /* Add fixups for the second and third relocations, if given.
3435 Note that the ABI allows the second relocation to be
3436 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3437 moment we only use RSS_UNDEF, but we could add support
3438 for the others if it ever becomes necessary. */
3439 for (i = 1; i < 3; i++)
3440 if (reloc_type[i] != BFD_RELOC_UNUSED)
3442 ip->fixp[i] = fix_new (ip->frag, ip->where,
3443 ip->fixp[0]->fx_size, NULL, 0,
3444 FALSE, reloc_type[i]);
3446 /* Use fx_tcbit to mark compound relocs. */
3447 ip->fixp[0]->fx_tcbit = 1;
3448 ip->fixp[i]->fx_tcbit = 1;
3454 /* Update the register mask information. */
3455 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
3456 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
3458 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3460 /* Filling the branch delay slot is more complex. We try to
3461 switch the branch with the previous instruction, which we can
3462 do if the previous instruction does not set up a condition
3463 that the branch tests and if the branch is not itself the
3464 target of any branch. */
3465 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3466 || (pinfo & INSN_COND_BRANCH_DELAY))
3468 if (mips_optimize < 2
3469 /* If we have seen .set volatile or .set nomove, don't
3471 || mips_opts.nomove != 0
3472 /* We can't swap if the previous instruction's position
3474 || history[0].fixed_p
3475 /* If the previous previous insn was in a .set
3476 noreorder, we can't swap. Actually, the MIPS
3477 assembler will swap in this situation. However, gcc
3478 configured -with-gnu-as will generate code like
3484 in which we can not swap the bne and INSN. If gcc is
3485 not configured -with-gnu-as, it does not output the
3487 || history[1].noreorder_p
3488 /* If the branch is itself the target of a branch, we
3489 can not swap. We cheat on this; all we check for is
3490 whether there is a label on this instruction. If
3491 there are any branches to anything other than a
3492 label, users must use .set noreorder. */
3493 || si->label_list != NULL
3494 /* If the previous instruction is in a variant frag
3495 other than this branch's one, we cannot do the swap.
3496 This does not apply to the mips16, which uses variant
3497 frags for different purposes. */
3498 || (! mips_opts.mips16
3499 && prev_insn_frag_type == rs_machine_dependent)
3500 /* Check for conflicts between the branch and the instructions
3501 before the candidate delay slot. */
3502 || nops_for_insn (0, history + 1, ip) > 0
3503 /* Check for conflicts between the swapped sequence and the
3504 target of the branch. */
3505 || nops_for_sequence (2, 0, history + 1, ip, history) > 0
3506 /* We do not swap with a trap instruction, since it
3507 complicates trap handlers to have the trap
3508 instruction be in a delay slot. */
3509 || (prev_pinfo & INSN_TRAP)
3510 /* If the branch reads a register that the previous
3511 instruction sets, we can not swap. */
3512 || (gpr_read_mask (ip) & gpr_write_mask (&history[0])) != 0
3513 /* If the branch writes a register that the previous
3514 instruction sets, we can not swap. */
3515 || (gpr_write_mask (ip) & gpr_write_mask (&history[0])) != 0
3516 /* If the branch writes a register that the previous
3517 instruction reads, we can not swap. */
3518 || (gpr_write_mask (ip) & gpr_read_mask (&history[0])) != 0
3519 /* If one instruction sets a condition code and the
3520 other one uses a condition code, we can not swap. */
3521 || ((pinfo & INSN_READ_COND_CODE)
3522 && (prev_pinfo & INSN_WRITE_COND_CODE))
3523 || ((pinfo & INSN_WRITE_COND_CODE)
3524 && (prev_pinfo & INSN_READ_COND_CODE))
3525 /* If the previous instruction uses the PC, we can not
3527 || (mips_opts.mips16
3528 && (prev_pinfo & MIPS16_INSN_READ_PC))
3529 /* If the previous instruction had a fixup in mips16
3530 mode, we can not swap. This normally means that the
3531 previous instruction was a 4 byte branch anyhow. */
3532 || (mips_opts.mips16 && history[0].fixp[0])
3533 /* If the previous instruction is a sync, sync.l, or
3534 sync.p, we can not swap. */
3535 || (prev_pinfo & INSN_SYNC)
3536 /* If the previous instruction is an ERET or
3537 DERET, avoid the swap. */
3538 || (history[0].insn_opcode == INSN_ERET)
3539 || (history[0].insn_opcode == INSN_DERET))
3541 if (mips_opts.mips16
3542 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3543 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3544 && ISA_SUPPORTS_MIPS16E)
3546 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3547 ip->insn_opcode |= 0x0080;
3549 insert_into_history (0, 1, ip);
3553 /* We could do even better for unconditional branches to
3554 portions of this object file; we could pick up the
3555 instruction at the destination, put it in the delay
3556 slot, and bump the destination address. */
3557 insert_into_history (0, 1, ip);
3561 if (mips_relax.sequence)
3562 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3566 /* It looks like we can actually do the swap. */
3567 struct mips_cl_insn delay = history[0];
3568 if (mips_opts.mips16)
3570 know (delay.frag == ip->frag);
3571 move_insn (ip, delay.frag, delay.where);
3572 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3574 else if (relaxed_branch)
3576 /* Add the delay slot instruction to the end of the
3577 current frag and shrink the fixed part of the
3578 original frag. If the branch occupies the tail of
3579 the latter, move it backwards to cover the gap. */
3580 delay.frag->fr_fix -= 4;
3581 if (delay.frag == ip->frag)
3582 move_insn (ip, ip->frag, ip->where - 4);
3583 add_fixed_insn (&delay);
3587 move_insn (&delay, ip->frag, ip->where);
3588 move_insn (ip, history[0].frag, history[0].where);
3592 insert_into_history (0, 1, &delay);
3595 /* If that was an unconditional branch, forget the previous
3596 insn information. */
3597 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3599 mips_no_prev_insn ();
3602 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3604 /* We don't yet optimize a branch likely. What we should do
3605 is look at the target, copy the instruction found there
3606 into the delay slot, and increment the branch to jump to
3607 the next instruction. */
3608 insert_into_history (0, 1, ip);
3612 insert_into_history (0, 1, ip);
3615 insert_into_history (0, 1, ip);
3617 /* We just output an insn, so the next one doesn't have a label. */
3618 mips_clear_insn_labels ();
3621 /* Forget that there was any previous instruction or label. */
3624 mips_no_prev_insn (void)
3626 prev_nop_frag = NULL;
3627 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3628 mips_clear_insn_labels ();
3631 /* This function must be called before we emit something other than
3632 instructions. It is like mips_no_prev_insn except that it inserts
3633 any NOPS that might be needed by previous instructions. */
3636 mips_emit_delays (void)
3638 if (! mips_opts.noreorder)
3640 int nops = nops_for_insn (0, history, NULL);
3644 add_fixed_insn (NOP_INSN);
3645 mips_move_labels ();
3648 mips_no_prev_insn ();
3651 /* Start a (possibly nested) noreorder block. */
3654 start_noreorder (void)
3656 if (mips_opts.noreorder == 0)
3661 /* None of the instructions before the .set noreorder can be moved. */
3662 for (i = 0; i < ARRAY_SIZE (history); i++)
3663 history[i].fixed_p = 1;
3665 /* Insert any nops that might be needed between the .set noreorder
3666 block and the previous instructions. We will later remove any
3667 nops that turn out not to be needed. */
3668 nops = nops_for_insn (0, history, NULL);
3671 if (mips_optimize != 0)
3673 /* Record the frag which holds the nop instructions, so
3674 that we can remove them if we don't need them. */
3675 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3676 prev_nop_frag = frag_now;
3677 prev_nop_frag_holds = nops;
3678 prev_nop_frag_required = 0;
3679 prev_nop_frag_since = 0;
3682 for (; nops > 0; --nops)
3683 add_fixed_insn (NOP_INSN);
3685 /* Move on to a new frag, so that it is safe to simply
3686 decrease the size of prev_nop_frag. */
3687 frag_wane (frag_now);
3689 mips_move_labels ();
3691 mips16_mark_labels ();
3692 mips_clear_insn_labels ();
3694 mips_opts.noreorder++;
3695 mips_any_noreorder = 1;
3698 /* End a nested noreorder block. */
3701 end_noreorder (void)
3704 mips_opts.noreorder--;
3705 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3707 /* Commit to inserting prev_nop_frag_required nops and go back to
3708 handling nop insertion the .set reorder way. */
3709 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3710 * (mips_opts.mips16 ? 2 : 4));
3711 insert_into_history (prev_nop_frag_since,
3712 prev_nop_frag_required, NOP_INSN);
3713 prev_nop_frag = NULL;
3717 /* Set up global variables for the start of a new macro. */
3722 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3723 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3724 && (history[0].insn_mo->pinfo
3725 & (INSN_UNCOND_BRANCH_DELAY
3726 | INSN_COND_BRANCH_DELAY
3727 | INSN_COND_BRANCH_LIKELY)) != 0);
3730 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3731 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3732 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3735 macro_warning (relax_substateT subtype)
3737 if (subtype & RELAX_DELAY_SLOT)
3738 return _("Macro instruction expanded into multiple instructions"
3739 " in a branch delay slot");
3740 else if (subtype & RELAX_NOMACRO)
3741 return _("Macro instruction expanded into multiple instructions");
3746 /* Finish up a macro. Emit warnings as appropriate. */
3751 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3753 relax_substateT subtype;
3755 /* Set up the relaxation warning flags. */
3757 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3758 subtype |= RELAX_SECOND_LONGER;
3759 if (mips_opts.warn_about_macros)
3760 subtype |= RELAX_NOMACRO;
3761 if (mips_macro_warning.delay_slot_p)
3762 subtype |= RELAX_DELAY_SLOT;
3764 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3766 /* Either the macro has a single implementation or both
3767 implementations are longer than 4 bytes. Emit the
3769 const char *msg = macro_warning (subtype);
3771 as_warn ("%s", msg);
3775 /* One implementation might need a warning but the other
3776 definitely doesn't. */
3777 mips_macro_warning.first_frag->fr_subtype |= subtype;
3782 /* Read a macro's relocation codes from *ARGS and store them in *R.
3783 The first argument in *ARGS will be either the code for a single
3784 relocation or -1 followed by the three codes that make up a
3785 composite relocation. */
3788 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3792 next = va_arg (*args, int);
3794 r[0] = (bfd_reloc_code_real_type) next;
3796 for (i = 0; i < 3; i++)
3797 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3800 /* Build an instruction created by a macro expansion. This is passed
3801 a pointer to the count of instructions created so far, an
3802 expression, the name of the instruction to build, an operand format
3803 string, and corresponding arguments. */
3806 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3808 const struct mips_opcode *mo;
3809 struct mips_cl_insn insn;
3810 bfd_reloc_code_real_type r[3];
3813 va_start (args, fmt);
3815 if (mips_opts.mips16)
3817 mips16_macro_build (ep, name, fmt, &args);
3822 r[0] = BFD_RELOC_UNUSED;
3823 r[1] = BFD_RELOC_UNUSED;
3824 r[2] = BFD_RELOC_UNUSED;
3825 mo = (struct mips_opcode *) hash_find (op_hash, name);
3827 gas_assert (strcmp (name, mo->name) == 0);
3831 /* Search until we get a match for NAME. It is assumed here that
3832 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3833 if (strcmp (fmt, mo->args) == 0
3834 && mo->pinfo != INSN_MACRO
3835 && is_opcode_valid (mo))
3839 gas_assert (mo->name);
3840 gas_assert (strcmp (name, mo->name) == 0);
3843 create_insn (&insn, mo);
3861 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3866 /* Note that in the macro case, these arguments are already
3867 in MSB form. (When handling the instruction in the
3868 non-macro case, these arguments are sizes from which
3869 MSB values must be calculated.) */
3870 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3876 /* Note that in the macro case, these arguments are already
3877 in MSBD form. (When handling the instruction in the
3878 non-macro case, these arguments are sizes from which
3879 MSBD values must be calculated.) */
3880 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3884 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3893 INSERT_OPERAND (BP, insn, va_arg (args, int));
3899 INSERT_OPERAND (RT, insn, va_arg (args, int));
3903 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3908 INSERT_OPERAND (FT, insn, va_arg (args, int));
3914 INSERT_OPERAND (RD, insn, va_arg (args, int));
3919 int tmp = va_arg (args, int);
3921 INSERT_OPERAND (RT, insn, tmp);
3922 INSERT_OPERAND (RD, insn, tmp);
3928 INSERT_OPERAND (FS, insn, va_arg (args, int));
3935 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3939 INSERT_OPERAND (FD, insn, va_arg (args, int));
3943 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3947 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3951 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3958 INSERT_OPERAND (RS, insn, va_arg (args, int));
3963 macro_read_relocs (&args, r);
3964 gas_assert (*r == BFD_RELOC_GPREL16
3965 || *r == BFD_RELOC_MIPS_HIGHER
3966 || *r == BFD_RELOC_HI16_S
3967 || *r == BFD_RELOC_LO16
3968 || *r == BFD_RELOC_MIPS_GOT_OFST);
3972 macro_read_relocs (&args, r);
3976 macro_read_relocs (&args, r);
3977 gas_assert (ep != NULL
3978 && (ep->X_op == O_constant
3979 || (ep->X_op == O_symbol
3980 && (*r == BFD_RELOC_MIPS_HIGHEST
3981 || *r == BFD_RELOC_HI16_S
3982 || *r == BFD_RELOC_HI16
3983 || *r == BFD_RELOC_GPREL16
3984 || *r == BFD_RELOC_MIPS_GOT_HI16
3985 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3989 gas_assert (ep != NULL);
3992 * This allows macro() to pass an immediate expression for
3993 * creating short branches without creating a symbol.
3995 * We don't allow branch relaxation for these branches, as
3996 * they should only appear in ".set nomacro" anyway.
3998 if (ep->X_op == O_constant)
4000 if ((ep->X_add_number & 3) != 0)
4001 as_bad (_("branch to misaligned address (0x%lx)"),
4002 (unsigned long) ep->X_add_number);
4003 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4004 as_bad (_("branch address range overflow (0x%lx)"),
4005 (unsigned long) ep->X_add_number);
4006 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4010 *r = BFD_RELOC_16_PCREL_S2;
4014 gas_assert (ep != NULL);
4015 *r = BFD_RELOC_MIPS_JMP;
4019 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4023 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4032 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4034 append_insn (&insn, ep, r);
4038 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4041 struct mips_opcode *mo;
4042 struct mips_cl_insn insn;
4043 bfd_reloc_code_real_type r[3]
4044 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4046 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4048 gas_assert (strcmp (name, mo->name) == 0);
4050 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4053 gas_assert (mo->name);
4054 gas_assert (strcmp (name, mo->name) == 0);
4057 create_insn (&insn, mo);
4075 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4080 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4084 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4088 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4098 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4105 regno = va_arg (*args, int);
4106 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4107 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4128 gas_assert (ep != NULL);
4130 if (ep->X_op != O_constant)
4131 *r = (int) BFD_RELOC_UNUSED + c;
4134 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4135 FALSE, &insn.insn_opcode, &insn.use_extend,
4138 *r = BFD_RELOC_UNUSED;
4144 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4151 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4153 append_insn (&insn, ep, r);
4157 * Sign-extend 32-bit mode constants that have bit 31 set and all
4158 * higher bits unset.
4161 normalize_constant_expr (expressionS *ex)
4163 if (ex->X_op == O_constant
4164 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4165 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4170 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4171 * all higher bits unset.
4174 normalize_address_expr (expressionS *ex)
4176 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4177 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4178 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4179 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4184 * Generate a "jalr" instruction with a relocation hint to the called
4185 * function. This occurs in NewABI PIC code.
4188 macro_build_jalr (expressionS *ep)
4192 if (MIPS_JALR_HINT_P (ep))
4197 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4198 if (MIPS_JALR_HINT_P (ep))
4199 fix_new_exp (frag_now, f - frag_now->fr_literal,
4200 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4204 * Generate a "lui" instruction.
4207 macro_build_lui (expressionS *ep, int regnum)
4209 expressionS high_expr;
4210 const struct mips_opcode *mo;
4211 struct mips_cl_insn insn;
4212 bfd_reloc_code_real_type r[3]
4213 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4214 const char *name = "lui";
4215 const char *fmt = "t,u";
4217 gas_assert (! mips_opts.mips16);
4221 if (high_expr.X_op == O_constant)
4223 /* We can compute the instruction now without a relocation entry. */
4224 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4226 *r = BFD_RELOC_UNUSED;
4230 gas_assert (ep->X_op == O_symbol);
4231 /* _gp_disp is a special case, used from s_cpload.
4232 __gnu_local_gp is used if mips_no_shared. */
4233 gas_assert (mips_pic == NO_PIC
4235 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4236 || (! mips_in_shared
4237 && strcmp (S_GET_NAME (ep->X_add_symbol),
4238 "__gnu_local_gp") == 0));
4239 *r = BFD_RELOC_HI16_S;
4242 mo = hash_find (op_hash, name);
4243 gas_assert (strcmp (name, mo->name) == 0);
4244 gas_assert (strcmp (fmt, mo->args) == 0);
4245 create_insn (&insn, mo);
4247 insn.insn_opcode = insn.insn_mo->match;
4248 INSERT_OPERAND (RT, insn, regnum);
4249 if (*r == BFD_RELOC_UNUSED)
4251 insn.insn_opcode |= high_expr.X_add_number;
4252 append_insn (&insn, NULL, r);
4255 append_insn (&insn, &high_expr, r);
4258 /* Generate a sequence of instructions to do a load or store from a constant
4259 offset off of a base register (breg) into/from a target register (treg),
4260 using AT if necessary. */
4262 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4263 int treg, int breg, int dbl)
4265 gas_assert (ep->X_op == O_constant);
4267 /* Sign-extending 32-bit constants makes their handling easier. */
4269 normalize_constant_expr (ep);
4271 /* Right now, this routine can only handle signed 32-bit constants. */
4272 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4273 as_warn (_("operand overflow"));
4275 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4277 /* Signed 16-bit offset will fit in the op. Easy! */
4278 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4282 /* 32-bit offset, need multiple instructions and AT, like:
4283 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4284 addu $tempreg,$tempreg,$breg
4285 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4286 to handle the complete offset. */
4287 macro_build_lui (ep, AT);
4288 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4289 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4292 as_bad (_("Macro used $at after \".set noat\""));
4297 * Generates code to set the $at register to true (one)
4298 * if reg is less than the immediate expression.
4301 set_at (int reg, int unsignedp)
4303 if (imm_expr.X_op == O_constant
4304 && imm_expr.X_add_number >= -0x8000
4305 && imm_expr.X_add_number < 0x8000)
4306 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4307 AT, reg, BFD_RELOC_LO16);
4310 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4311 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4315 /* Warn if an expression is not a constant. */
4318 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4320 if (ex->X_op == O_big)
4321 as_bad (_("unsupported large constant"));
4322 else if (ex->X_op != O_constant)
4323 as_bad (_("Instruction %s requires absolute expression"),
4326 if (HAVE_32BIT_GPRS)
4327 normalize_constant_expr (ex);
4330 /* Count the leading zeroes by performing a binary chop. This is a
4331 bulky bit of source, but performance is a LOT better for the
4332 majority of values than a simple loop to count the bits:
4333 for (lcnt = 0; (lcnt < 32); lcnt++)
4334 if ((v) & (1 << (31 - lcnt)))
4336 However it is not code size friendly, and the gain will drop a bit
4337 on certain cached systems.
4339 #define COUNT_TOP_ZEROES(v) \
4340 (((v) & ~0xffff) == 0 \
4341 ? ((v) & ~0xff) == 0 \
4342 ? ((v) & ~0xf) == 0 \
4343 ? ((v) & ~0x3) == 0 \
4344 ? ((v) & ~0x1) == 0 \
4349 : ((v) & ~0x7) == 0 \
4352 : ((v) & ~0x3f) == 0 \
4353 ? ((v) & ~0x1f) == 0 \
4356 : ((v) & ~0x7f) == 0 \
4359 : ((v) & ~0xfff) == 0 \
4360 ? ((v) & ~0x3ff) == 0 \
4361 ? ((v) & ~0x1ff) == 0 \
4364 : ((v) & ~0x7ff) == 0 \
4367 : ((v) & ~0x3fff) == 0 \
4368 ? ((v) & ~0x1fff) == 0 \
4371 : ((v) & ~0x7fff) == 0 \
4374 : ((v) & ~0xffffff) == 0 \
4375 ? ((v) & ~0xfffff) == 0 \
4376 ? ((v) & ~0x3ffff) == 0 \
4377 ? ((v) & ~0x1ffff) == 0 \
4380 : ((v) & ~0x7ffff) == 0 \
4383 : ((v) & ~0x3fffff) == 0 \
4384 ? ((v) & ~0x1fffff) == 0 \
4387 : ((v) & ~0x7fffff) == 0 \
4390 : ((v) & ~0xfffffff) == 0 \
4391 ? ((v) & ~0x3ffffff) == 0 \
4392 ? ((v) & ~0x1ffffff) == 0 \
4395 : ((v) & ~0x7ffffff) == 0 \
4398 : ((v) & ~0x3fffffff) == 0 \
4399 ? ((v) & ~0x1fffffff) == 0 \
4402 : ((v) & ~0x7fffffff) == 0 \
4407 * This routine generates the least number of instructions necessary to load
4408 * an absolute expression value into a register.
4411 load_register (int reg, expressionS *ep, int dbl)
4414 expressionS hi32, lo32;
4416 if (ep->X_op != O_big)
4418 gas_assert (ep->X_op == O_constant);
4420 /* Sign-extending 32-bit constants makes their handling easier. */
4422 normalize_constant_expr (ep);
4424 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4426 /* We can handle 16 bit signed values with an addiu to
4427 $zero. No need to ever use daddiu here, since $zero and
4428 the result are always correct in 32 bit mode. */
4429 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4432 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4434 /* We can handle 16 bit unsigned values with an ori to
4436 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4439 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4441 /* 32 bit values require an lui. */
4442 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4443 if ((ep->X_add_number & 0xffff) != 0)
4444 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4449 /* The value is larger than 32 bits. */
4451 if (!dbl || HAVE_32BIT_GPRS)
4455 sprintf_vma (value, ep->X_add_number);
4456 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4457 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4461 if (ep->X_op != O_big)
4464 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4465 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4466 hi32.X_add_number &= 0xffffffff;
4468 lo32.X_add_number &= 0xffffffff;
4472 gas_assert (ep->X_add_number > 2);
4473 if (ep->X_add_number == 3)
4474 generic_bignum[3] = 0;
4475 else if (ep->X_add_number > 4)
4476 as_bad (_("Number larger than 64 bits"));
4477 lo32.X_op = O_constant;
4478 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4479 hi32.X_op = O_constant;
4480 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4483 if (hi32.X_add_number == 0)
4488 unsigned long hi, lo;
4490 if (hi32.X_add_number == (offsetT) 0xffffffff)
4492 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4494 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4497 if (lo32.X_add_number & 0x80000000)
4499 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4500 if (lo32.X_add_number & 0xffff)
4501 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4506 /* Check for 16bit shifted constant. We know that hi32 is
4507 non-zero, so start the mask on the first bit of the hi32
4512 unsigned long himask, lomask;
4516 himask = 0xffff >> (32 - shift);
4517 lomask = (0xffff << shift) & 0xffffffff;
4521 himask = 0xffff << (shift - 32);
4524 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4525 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4529 tmp.X_op = O_constant;
4531 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4532 | (lo32.X_add_number >> shift));
4534 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4535 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4536 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4537 reg, reg, (shift >= 32) ? shift - 32 : shift);
4542 while (shift <= (64 - 16));
4544 /* Find the bit number of the lowest one bit, and store the
4545 shifted value in hi/lo. */
4546 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4547 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4551 while ((lo & 1) == 0)
4556 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4562 while ((hi & 1) == 0)
4571 /* Optimize if the shifted value is a (power of 2) - 1. */
4572 if ((hi == 0 && ((lo + 1) & lo) == 0)
4573 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4575 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4580 /* This instruction will set the register to be all
4582 tmp.X_op = O_constant;
4583 tmp.X_add_number = (offsetT) -1;
4584 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4588 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4589 reg, reg, (bit >= 32) ? bit - 32 : bit);
4591 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4592 reg, reg, (shift >= 32) ? shift - 32 : shift);
4597 /* Sign extend hi32 before calling load_register, because we can
4598 generally get better code when we load a sign extended value. */
4599 if ((hi32.X_add_number & 0x80000000) != 0)
4600 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4601 load_register (reg, &hi32, 0);
4604 if ((lo32.X_add_number & 0xffff0000) == 0)
4608 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4616 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4618 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4619 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4625 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4629 mid16.X_add_number >>= 16;
4630 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4631 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4634 if ((lo32.X_add_number & 0xffff) != 0)
4635 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4639 load_delay_nop (void)
4641 if (!gpr_interlocks)
4642 macro_build (NULL, "nop", "");
4645 /* Load an address into a register. */
4648 load_address (int reg, expressionS *ep, int *used_at)
4650 if (ep->X_op != O_constant
4651 && ep->X_op != O_symbol)
4653 as_bad (_("expression too complex"));
4654 ep->X_op = O_constant;
4657 if (ep->X_op == O_constant)
4659 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4663 if (mips_pic == NO_PIC)
4665 /* If this is a reference to a GP relative symbol, we want
4666 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4668 lui $reg,<sym> (BFD_RELOC_HI16_S)
4669 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4670 If we have an addend, we always use the latter form.
4672 With 64bit address space and a usable $at we want
4673 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4674 lui $at,<sym> (BFD_RELOC_HI16_S)
4675 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4676 daddiu $at,<sym> (BFD_RELOC_LO16)
4680 If $at is already in use, we use a path which is suboptimal
4681 on superscalar processors.
4682 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4683 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4685 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4687 daddiu $reg,<sym> (BFD_RELOC_LO16)
4689 For GP relative symbols in 64bit address space we can use
4690 the same sequence as in 32bit address space. */
4691 if (HAVE_64BIT_SYMBOLS)
4693 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4694 && !nopic_need_relax (ep->X_add_symbol, 1))
4696 relax_start (ep->X_add_symbol);
4697 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4698 mips_gp_register, BFD_RELOC_GPREL16);
4702 if (*used_at == 0 && mips_opts.at)
4704 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4705 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4706 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4707 BFD_RELOC_MIPS_HIGHER);
4708 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4709 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4710 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4715 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4716 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4717 BFD_RELOC_MIPS_HIGHER);
4718 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4719 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4720 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4721 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4724 if (mips_relax.sequence)
4729 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4730 && !nopic_need_relax (ep->X_add_symbol, 1))
4732 relax_start (ep->X_add_symbol);
4733 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4734 mips_gp_register, BFD_RELOC_GPREL16);
4737 macro_build_lui (ep, reg);
4738 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4739 reg, reg, BFD_RELOC_LO16);
4740 if (mips_relax.sequence)
4744 else if (!mips_big_got)
4748 /* If this is a reference to an external symbol, we want
4749 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4751 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4753 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4754 If there is a constant, it must be added in after.
4756 If we have NewABI, we want
4757 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4758 unless we're referencing a global symbol with a non-zero
4759 offset, in which case cst must be added separately. */
4762 if (ep->X_add_number)
4764 ex.X_add_number = ep->X_add_number;
4765 ep->X_add_number = 0;
4766 relax_start (ep->X_add_symbol);
4767 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4768 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4769 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4770 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4771 ex.X_op = O_constant;
4772 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4773 reg, reg, BFD_RELOC_LO16);
4774 ep->X_add_number = ex.X_add_number;
4777 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4778 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4779 if (mips_relax.sequence)
4784 ex.X_add_number = ep->X_add_number;
4785 ep->X_add_number = 0;
4786 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4787 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4789 relax_start (ep->X_add_symbol);
4791 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4795 if (ex.X_add_number != 0)
4797 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4798 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4799 ex.X_op = O_constant;
4800 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4801 reg, reg, BFD_RELOC_LO16);
4805 else if (mips_big_got)
4809 /* This is the large GOT case. If this is a reference to an
4810 external symbol, we want
4811 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4813 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4815 Otherwise, for a reference to a local symbol in old ABI, we want
4816 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4818 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4819 If there is a constant, it must be added in after.
4821 In the NewABI, for local symbols, with or without offsets, we want:
4822 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4823 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4827 ex.X_add_number = ep->X_add_number;
4828 ep->X_add_number = 0;
4829 relax_start (ep->X_add_symbol);
4830 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4831 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4832 reg, reg, mips_gp_register);
4833 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4834 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4835 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4836 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4837 else if (ex.X_add_number)
4839 ex.X_op = O_constant;
4840 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4844 ep->X_add_number = ex.X_add_number;
4846 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4847 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4848 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4849 BFD_RELOC_MIPS_GOT_OFST);
4854 ex.X_add_number = ep->X_add_number;
4855 ep->X_add_number = 0;
4856 relax_start (ep->X_add_symbol);
4857 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4858 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4859 reg, reg, mips_gp_register);
4860 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4861 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4863 if (reg_needs_delay (mips_gp_register))
4865 /* We need a nop before loading from $gp. This special
4866 check is required because the lui which starts the main
4867 instruction stream does not refer to $gp, and so will not
4868 insert the nop which may be required. */
4869 macro_build (NULL, "nop", "");
4871 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4872 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4874 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4878 if (ex.X_add_number != 0)
4880 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4881 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4882 ex.X_op = O_constant;
4883 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4891 if (!mips_opts.at && *used_at == 1)
4892 as_bad (_("Macro used $at after \".set noat\""));
4895 /* Move the contents of register SOURCE into register DEST. */
4898 move_register (int dest, int source)
4900 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4904 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4905 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4906 The two alternatives are:
4908 Global symbol Local sybmol
4909 ------------- ------------
4910 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4912 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4914 load_got_offset emits the first instruction and add_got_offset
4915 emits the second for a 16-bit offset or add_got_offset_hilo emits
4916 a sequence to add a 32-bit offset using a scratch register. */
4919 load_got_offset (int dest, expressionS *local)
4924 global.X_add_number = 0;
4926 relax_start (local->X_add_symbol);
4927 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4928 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4930 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4931 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4936 add_got_offset (int dest, expressionS *local)
4940 global.X_op = O_constant;
4941 global.X_op_symbol = NULL;
4942 global.X_add_symbol = NULL;
4943 global.X_add_number = local->X_add_number;
4945 relax_start (local->X_add_symbol);
4946 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4947 dest, dest, BFD_RELOC_LO16);
4949 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4954 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4957 int hold_mips_optimize;
4959 global.X_op = O_constant;
4960 global.X_op_symbol = NULL;
4961 global.X_add_symbol = NULL;
4962 global.X_add_number = local->X_add_number;
4964 relax_start (local->X_add_symbol);
4965 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4967 /* Set mips_optimize around the lui instruction to avoid
4968 inserting an unnecessary nop after the lw. */
4969 hold_mips_optimize = mips_optimize;
4971 macro_build_lui (&global, tmp);
4972 mips_optimize = hold_mips_optimize;
4973 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4976 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4981 * This routine implements the seemingly endless macro or synthesized
4982 * instructions and addressing modes in the mips assembly language. Many
4983 * of these macros are simple and are similar to each other. These could
4984 * probably be handled by some kind of table or grammar approach instead of
4985 * this verbose method. Others are not simple macros but are more like
4986 * optimizing code generation.
4987 * One interesting optimization is when several store macros appear
4988 * consecutively that would load AT with the upper half of the same address.
4989 * The ensuing load upper instructions are ommited. This implies some kind
4990 * of global optimization. We currently only optimize within a single macro.
4991 * For many of the load and store macros if the address is specified as a
4992 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4993 * first load register 'at' with zero and use it as the base register. The
4994 * mips assembler simply uses register $zero. Just one tiny optimization
4998 macro (struct mips_cl_insn *ip)
5000 unsigned int treg, sreg, dreg, breg;
5001 unsigned int tempreg;
5016 bfd_reloc_code_real_type r;
5017 int hold_mips_optimize;
5019 gas_assert (! mips_opts.mips16);
5021 treg = EXTRACT_OPERAND (RT, *ip);
5022 dreg = EXTRACT_OPERAND (RD, *ip);
5023 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5024 mask = ip->insn_mo->mask;
5026 expr1.X_op = O_constant;
5027 expr1.X_op_symbol = NULL;
5028 expr1.X_add_symbol = NULL;
5029 expr1.X_add_number = 1;
5043 expr1.X_add_number = 8;
5044 macro_build (&expr1, "bgez", "s,p", sreg);
5046 macro_build (NULL, "nop", "");
5048 move_register (dreg, sreg);
5049 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5072 if (imm_expr.X_op == O_constant
5073 && imm_expr.X_add_number >= -0x8000
5074 && imm_expr.X_add_number < 0x8000)
5076 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5080 load_register (AT, &imm_expr, dbl);
5081 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5100 if (imm_expr.X_op == O_constant
5101 && imm_expr.X_add_number >= 0
5102 && imm_expr.X_add_number < 0x10000)
5104 if (mask != M_NOR_I)
5105 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5108 macro_build (&imm_expr, "ori", "t,r,i",
5109 treg, sreg, BFD_RELOC_LO16);
5110 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5116 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5117 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5121 switch (imm_expr.X_add_number)
5124 macro_build (NULL, "nop", "");
5127 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5130 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5131 (int) imm_expr.X_add_number);
5150 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5152 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5156 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5157 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5165 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5170 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5174 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5175 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5181 /* Check for > max integer. */
5182 maxnum = 0x7fffffff;
5183 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5190 if (imm_expr.X_op == O_constant
5191 && imm_expr.X_add_number >= maxnum
5192 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5195 /* Result is always false. */
5197 macro_build (NULL, "nop", "");
5199 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5202 if (imm_expr.X_op != O_constant)
5203 as_bad (_("Unsupported large constant"));
5204 ++imm_expr.X_add_number;
5208 if (mask == M_BGEL_I)
5210 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5212 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5215 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5217 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5220 maxnum = 0x7fffffff;
5221 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5228 maxnum = - maxnum - 1;
5229 if (imm_expr.X_op == O_constant
5230 && imm_expr.X_add_number <= maxnum
5231 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5234 /* result is always true */
5235 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5236 macro_build (&offset_expr, "b", "p");
5241 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5251 macro_build (&offset_expr, likely ? "beql" : "beq",
5252 "s,t,p", ZERO, treg);
5256 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5257 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5265 && imm_expr.X_op == O_constant
5266 && imm_expr.X_add_number == -1))
5268 if (imm_expr.X_op != O_constant)
5269 as_bad (_("Unsupported large constant"));
5270 ++imm_expr.X_add_number;
5274 if (mask == M_BGEUL_I)
5276 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5278 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5280 macro_build (&offset_expr, likely ? "bnel" : "bne",
5281 "s,t,p", sreg, ZERO);
5286 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5294 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5299 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5303 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5304 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5312 macro_build (&offset_expr, likely ? "bnel" : "bne",
5313 "s,t,p", sreg, ZERO);
5319 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5320 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5328 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5333 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5337 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5338 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5344 maxnum = 0x7fffffff;
5345 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5352 if (imm_expr.X_op == O_constant
5353 && imm_expr.X_add_number >= maxnum
5354 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5356 if (imm_expr.X_op != O_constant)
5357 as_bad (_("Unsupported large constant"));
5358 ++imm_expr.X_add_number;
5362 if (mask == M_BLTL_I)
5364 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5366 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5369 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5371 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5376 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5384 macro_build (&offset_expr, likely ? "beql" : "beq",
5385 "s,t,p", sreg, ZERO);
5391 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5392 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5400 && imm_expr.X_op == O_constant
5401 && imm_expr.X_add_number == -1))
5403 if (imm_expr.X_op != O_constant)
5404 as_bad (_("Unsupported large constant"));
5405 ++imm_expr.X_add_number;
5409 if (mask == M_BLTUL_I)
5411 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5413 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5415 macro_build (&offset_expr, likely ? "beql" : "beq",
5416 "s,t,p", sreg, ZERO);
5421 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5429 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5434 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5438 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5439 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5449 macro_build (&offset_expr, likely ? "bnel" : "bne",
5450 "s,t,p", ZERO, treg);
5454 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5455 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5460 /* Use unsigned arithmetic. */
5464 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5466 as_bad (_("Unsupported large constant"));
5471 pos = imm_expr.X_add_number;
5472 size = imm2_expr.X_add_number;
5477 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5480 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5482 as_bad (_("Improper extract size (%lu, position %lu)"),
5483 (unsigned long) size, (unsigned long) pos);
5487 if (size <= 32 && pos < 32)
5492 else if (size <= 32)
5502 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5509 /* Use unsigned arithmetic. */
5513 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5515 as_bad (_("Unsupported large constant"));
5520 pos = imm_expr.X_add_number;
5521 size = imm2_expr.X_add_number;
5526 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5529 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5531 as_bad (_("Improper insert size (%lu, position %lu)"),
5532 (unsigned long) size, (unsigned long) pos);
5536 if (pos < 32 && (pos + size - 1) < 32)
5551 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5552 (int) (pos + size - 1));
5568 as_warn (_("Divide by zero."));
5570 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5572 macro_build (NULL, "break", "c", 7);
5579 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5580 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5584 expr1.X_add_number = 8;
5585 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5586 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5587 macro_build (NULL, "break", "c", 7);
5589 expr1.X_add_number = -1;
5591 load_register (AT, &expr1, dbl);
5592 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5593 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5596 expr1.X_add_number = 1;
5597 load_register (AT, &expr1, dbl);
5598 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5602 expr1.X_add_number = 0x80000000;
5603 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5607 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5608 /* We want to close the noreorder block as soon as possible, so
5609 that later insns are available for delay slot filling. */
5614 expr1.X_add_number = 8;
5615 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5616 macro_build (NULL, "nop", "");
5618 /* We want to close the noreorder block as soon as possible, so
5619 that later insns are available for delay slot filling. */
5622 macro_build (NULL, "break", "c", 6);
5624 macro_build (NULL, s, "d", dreg);
5663 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5665 as_warn (_("Divide by zero."));
5667 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5669 macro_build (NULL, "break", "c", 7);
5672 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5674 if (strcmp (s2, "mflo") == 0)
5675 move_register (dreg, sreg);
5677 move_register (dreg, ZERO);
5680 if (imm_expr.X_op == O_constant
5681 && imm_expr.X_add_number == -1
5682 && s[strlen (s) - 1] != 'u')
5684 if (strcmp (s2, "mflo") == 0)
5686 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5689 move_register (dreg, ZERO);
5694 load_register (AT, &imm_expr, dbl);
5695 macro_build (NULL, s, "z,s,t", sreg, AT);
5696 macro_build (NULL, s2, "d", dreg);
5718 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5719 macro_build (NULL, s, "z,s,t", sreg, treg);
5720 /* We want to close the noreorder block as soon as possible, so
5721 that later insns are available for delay slot filling. */
5726 expr1.X_add_number = 8;
5727 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5728 macro_build (NULL, s, "z,s,t", sreg, treg);
5730 /* We want to close the noreorder block as soon as possible, so
5731 that later insns are available for delay slot filling. */
5733 macro_build (NULL, "break", "c", 7);
5735 macro_build (NULL, s2, "d", dreg);
5747 /* Load the address of a symbol into a register. If breg is not
5748 zero, we then add a base register to it. */
5750 if (dbl && HAVE_32BIT_GPRS)
5751 as_warn (_("dla used to load 32-bit register"));
5753 if (!dbl && HAVE_64BIT_OBJECTS)
5754 as_warn (_("la used to load 64-bit address"));
5756 if (offset_expr.X_op == O_constant
5757 && offset_expr.X_add_number >= -0x8000
5758 && offset_expr.X_add_number < 0x8000)
5760 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5761 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5765 if (mips_opts.at && (treg == breg))
5775 if (offset_expr.X_op != O_symbol
5776 && offset_expr.X_op != O_constant)
5778 as_bad (_("Expression too complex"));
5779 offset_expr.X_op = O_constant;
5782 if (offset_expr.X_op == O_constant)
5783 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5784 else if (mips_pic == NO_PIC)
5786 /* If this is a reference to a GP relative symbol, we want
5787 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5789 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5790 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5791 If we have a constant, we need two instructions anyhow,
5792 so we may as well always use the latter form.
5794 With 64bit address space and a usable $at we want
5795 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5796 lui $at,<sym> (BFD_RELOC_HI16_S)
5797 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5798 daddiu $at,<sym> (BFD_RELOC_LO16)
5800 daddu $tempreg,$tempreg,$at
5802 If $at is already in use, we use a path which is suboptimal
5803 on superscalar processors.
5804 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5805 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5807 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5809 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5811 For GP relative symbols in 64bit address space we can use
5812 the same sequence as in 32bit address space. */
5813 if (HAVE_64BIT_SYMBOLS)
5815 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5816 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5818 relax_start (offset_expr.X_add_symbol);
5819 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5820 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5824 if (used_at == 0 && mips_opts.at)
5826 macro_build (&offset_expr, "lui", "t,u",
5827 tempreg, BFD_RELOC_MIPS_HIGHEST);
5828 macro_build (&offset_expr, "lui", "t,u",
5829 AT, BFD_RELOC_HI16_S);
5830 macro_build (&offset_expr, "daddiu", "t,r,j",
5831 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5832 macro_build (&offset_expr, "daddiu", "t,r,j",
5833 AT, AT, BFD_RELOC_LO16);
5834 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5835 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5840 macro_build (&offset_expr, "lui", "t,u",
5841 tempreg, BFD_RELOC_MIPS_HIGHEST);
5842 macro_build (&offset_expr, "daddiu", "t,r,j",
5843 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5844 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5845 macro_build (&offset_expr, "daddiu", "t,r,j",
5846 tempreg, tempreg, BFD_RELOC_HI16_S);
5847 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5848 macro_build (&offset_expr, "daddiu", "t,r,j",
5849 tempreg, tempreg, BFD_RELOC_LO16);
5852 if (mips_relax.sequence)
5857 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5858 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5860 relax_start (offset_expr.X_add_symbol);
5861 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5862 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5865 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5866 as_bad (_("Offset too large"));
5867 macro_build_lui (&offset_expr, tempreg);
5868 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5869 tempreg, tempreg, BFD_RELOC_LO16);
5870 if (mips_relax.sequence)
5874 else if (!mips_big_got && !HAVE_NEWABI)
5876 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5878 /* If this is a reference to an external symbol, and there
5879 is no constant, we want
5880 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5881 or for lca or if tempreg is PIC_CALL_REG
5882 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5883 For a local symbol, we want
5884 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5886 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5888 If we have a small constant, and this is a reference to
5889 an external symbol, we want
5890 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5892 addiu $tempreg,$tempreg,<constant>
5893 For a local symbol, we want the same instruction
5894 sequence, but we output a BFD_RELOC_LO16 reloc on the
5897 If we have a large constant, and this is a reference to
5898 an external symbol, we want
5899 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5900 lui $at,<hiconstant>
5901 addiu $at,$at,<loconstant>
5902 addu $tempreg,$tempreg,$at
5903 For a local symbol, we want the same instruction
5904 sequence, but we output a BFD_RELOC_LO16 reloc on the
5908 if (offset_expr.X_add_number == 0)
5910 if (mips_pic == SVR4_PIC
5912 && (call || tempreg == PIC_CALL_REG))
5913 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5915 relax_start (offset_expr.X_add_symbol);
5916 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5917 lw_reloc_type, mips_gp_register);
5920 /* We're going to put in an addu instruction using
5921 tempreg, so we may as well insert the nop right
5926 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5927 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5929 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5930 tempreg, tempreg, BFD_RELOC_LO16);
5932 /* FIXME: If breg == 0, and the next instruction uses
5933 $tempreg, then if this variant case is used an extra
5934 nop will be generated. */
5936 else if (offset_expr.X_add_number >= -0x8000
5937 && offset_expr.X_add_number < 0x8000)
5939 load_got_offset (tempreg, &offset_expr);
5941 add_got_offset (tempreg, &offset_expr);
5945 expr1.X_add_number = offset_expr.X_add_number;
5946 offset_expr.X_add_number =
5947 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5948 load_got_offset (tempreg, &offset_expr);
5949 offset_expr.X_add_number = expr1.X_add_number;
5950 /* If we are going to add in a base register, and the
5951 target register and the base register are the same,
5952 then we are using AT as a temporary register. Since
5953 we want to load the constant into AT, we add our
5954 current AT (from the global offset table) and the
5955 register into the register now, and pretend we were
5956 not using a base register. */
5960 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5965 add_got_offset_hilo (tempreg, &offset_expr, AT);
5969 else if (!mips_big_got && HAVE_NEWABI)
5971 int add_breg_early = 0;
5973 /* If this is a reference to an external, and there is no
5974 constant, or local symbol (*), with or without a
5976 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5977 or for lca or if tempreg is PIC_CALL_REG
5978 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5980 If we have a small constant, and this is a reference to
5981 an external symbol, we want
5982 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5983 addiu $tempreg,$tempreg,<constant>
5985 If we have a large constant, and this is a reference to
5986 an external symbol, we want
5987 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5988 lui $at,<hiconstant>
5989 addiu $at,$at,<loconstant>
5990 addu $tempreg,$tempreg,$at
5992 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5993 local symbols, even though it introduces an additional
5996 if (offset_expr.X_add_number)
5998 expr1.X_add_number = offset_expr.X_add_number;
5999 offset_expr.X_add_number = 0;
6001 relax_start (offset_expr.X_add_symbol);
6002 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6003 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6005 if (expr1.X_add_number >= -0x8000
6006 && expr1.X_add_number < 0x8000)
6008 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6009 tempreg, tempreg, BFD_RELOC_LO16);
6011 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6013 /* If we are going to add in a base register, and the
6014 target register and the base register are the same,
6015 then we are using AT as a temporary register. Since
6016 we want to load the constant into AT, we add our
6017 current AT (from the global offset table) and the
6018 register into the register now, and pretend we were
6019 not using a base register. */
6024 gas_assert (tempreg == AT);
6025 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6031 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6032 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6038 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6041 offset_expr.X_add_number = expr1.X_add_number;
6043 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6044 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6047 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6048 treg, tempreg, breg);
6054 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6056 relax_start (offset_expr.X_add_symbol);
6057 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6058 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6060 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6061 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6066 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6067 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6070 else if (mips_big_got && !HAVE_NEWABI)
6073 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6074 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6075 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6077 /* This is the large GOT case. If this is a reference to an
6078 external symbol, and there is no constant, we want
6079 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6080 addu $tempreg,$tempreg,$gp
6081 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6082 or for lca or if tempreg is PIC_CALL_REG
6083 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6084 addu $tempreg,$tempreg,$gp
6085 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6086 For a local symbol, we want
6087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6089 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6091 If we have a small constant, and this is a reference to
6092 an external symbol, we want
6093 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6094 addu $tempreg,$tempreg,$gp
6095 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6097 addiu $tempreg,$tempreg,<constant>
6098 For a local symbol, we want
6099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6101 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6103 If we have a large constant, and this is a reference to
6104 an external symbol, we want
6105 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6106 addu $tempreg,$tempreg,$gp
6107 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6108 lui $at,<hiconstant>
6109 addiu $at,$at,<loconstant>
6110 addu $tempreg,$tempreg,$at
6111 For a local symbol, we want
6112 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6113 lui $at,<hiconstant>
6114 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6115 addu $tempreg,$tempreg,$at
6118 expr1.X_add_number = offset_expr.X_add_number;
6119 offset_expr.X_add_number = 0;
6120 relax_start (offset_expr.X_add_symbol);
6121 gpdelay = reg_needs_delay (mips_gp_register);
6122 if (expr1.X_add_number == 0 && breg == 0
6123 && (call || tempreg == PIC_CALL_REG))
6125 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6126 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6128 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6129 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6130 tempreg, tempreg, mips_gp_register);
6131 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6132 tempreg, lw_reloc_type, tempreg);
6133 if (expr1.X_add_number == 0)
6137 /* We're going to put in an addu instruction using
6138 tempreg, so we may as well insert the nop right
6143 else if (expr1.X_add_number >= -0x8000
6144 && expr1.X_add_number < 0x8000)
6147 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6148 tempreg, tempreg, BFD_RELOC_LO16);
6152 /* If we are going to add in a base register, and the
6153 target register and the base register are the same,
6154 then we are using AT as a temporary register. Since
6155 we want to load the constant into AT, we add our
6156 current AT (from the global offset table) and the
6157 register into the register now, and pretend we were
6158 not using a base register. */
6163 gas_assert (tempreg == AT);
6165 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6170 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6171 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6175 offset_expr.X_add_number =
6176 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6181 /* This is needed because this instruction uses $gp, but
6182 the first instruction on the main stream does not. */
6183 macro_build (NULL, "nop", "");
6186 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6187 local_reloc_type, mips_gp_register);
6188 if (expr1.X_add_number >= -0x8000
6189 && expr1.X_add_number < 0x8000)
6192 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6193 tempreg, tempreg, BFD_RELOC_LO16);
6194 /* FIXME: If add_number is 0, and there was no base
6195 register, the external symbol case ended with a load,
6196 so if the symbol turns out to not be external, and
6197 the next instruction uses tempreg, an unnecessary nop
6198 will be inserted. */
6204 /* We must add in the base register now, as in the
6205 external symbol case. */
6206 gas_assert (tempreg == AT);
6208 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6211 /* We set breg to 0 because we have arranged to add
6212 it in in both cases. */
6216 macro_build_lui (&expr1, AT);
6217 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6218 AT, AT, BFD_RELOC_LO16);
6219 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6220 tempreg, tempreg, AT);
6225 else if (mips_big_got && HAVE_NEWABI)
6227 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6228 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6229 int add_breg_early = 0;
6231 /* This is the large GOT case. If this is a reference to an
6232 external symbol, and there is no constant, we want
6233 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6234 add $tempreg,$tempreg,$gp
6235 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6236 or for lca or if tempreg is PIC_CALL_REG
6237 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6238 add $tempreg,$tempreg,$gp
6239 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6241 If we have a small constant, and this is a reference to
6242 an external symbol, we want
6243 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6244 add $tempreg,$tempreg,$gp
6245 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6246 addi $tempreg,$tempreg,<constant>
6248 If we have a large constant, and this is a reference to
6249 an external symbol, we want
6250 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6251 addu $tempreg,$tempreg,$gp
6252 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6253 lui $at,<hiconstant>
6254 addi $at,$at,<loconstant>
6255 add $tempreg,$tempreg,$at
6257 If we have NewABI, and we know it's a local symbol, we want
6258 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6259 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6260 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6262 relax_start (offset_expr.X_add_symbol);
6264 expr1.X_add_number = offset_expr.X_add_number;
6265 offset_expr.X_add_number = 0;
6267 if (expr1.X_add_number == 0 && breg == 0
6268 && (call || tempreg == PIC_CALL_REG))
6270 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6271 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6273 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6274 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6275 tempreg, tempreg, mips_gp_register);
6276 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6277 tempreg, lw_reloc_type, tempreg);
6279 if (expr1.X_add_number == 0)
6281 else if (expr1.X_add_number >= -0x8000
6282 && expr1.X_add_number < 0x8000)
6284 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6285 tempreg, tempreg, BFD_RELOC_LO16);
6287 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6289 /* If we are going to add in a base register, and the
6290 target register and the base register are the same,
6291 then we are using AT as a temporary register. Since
6292 we want to load the constant into AT, we add our
6293 current AT (from the global offset table) and the
6294 register into the register now, and pretend we were
6295 not using a base register. */
6300 gas_assert (tempreg == AT);
6301 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6307 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6308 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6313 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6316 offset_expr.X_add_number = expr1.X_add_number;
6317 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6318 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6319 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6320 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6323 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6324 treg, tempreg, breg);
6334 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6339 unsigned long temp = (treg << 16) | (0x01);
6340 macro_build (NULL, "c2", "C", temp);
6346 unsigned long temp = (0x02);
6347 macro_build (NULL, "c2", "C", temp);
6353 unsigned long temp = (treg << 16) | (0x02);
6354 macro_build (NULL, "c2", "C", temp);
6359 macro_build (NULL, "c2", "C", 3);
6364 unsigned long temp = (treg << 16) | 0x03;
6365 macro_build (NULL, "c2", "C", temp);
6370 /* The j instruction may not be used in PIC code, since it
6371 requires an absolute address. We convert it to a b
6373 if (mips_pic == NO_PIC)
6374 macro_build (&offset_expr, "j", "a");
6376 macro_build (&offset_expr, "b", "p");
6379 /* The jal instructions must be handled as macros because when
6380 generating PIC code they expand to multi-instruction
6381 sequences. Normally they are simple instructions. */
6386 if (mips_pic == NO_PIC)
6387 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6390 if (sreg != PIC_CALL_REG)
6391 as_warn (_("MIPS PIC call to register other than $25"));
6393 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6394 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6396 if (mips_cprestore_offset < 0)
6397 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6400 if (!mips_frame_reg_valid)
6402 as_warn (_("No .frame pseudo-op used in PIC code"));
6403 /* Quiet this warning. */
6404 mips_frame_reg_valid = 1;
6406 if (!mips_cprestore_valid)
6408 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6409 /* Quiet this warning. */
6410 mips_cprestore_valid = 1;
6412 if (mips_opts.noreorder)
6413 macro_build (NULL, "nop", "");
6414 expr1.X_add_number = mips_cprestore_offset;
6415 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6418 HAVE_64BIT_ADDRESSES);
6426 if (mips_pic == NO_PIC)
6427 macro_build (&offset_expr, "jal", "a");
6428 else if (mips_pic == SVR4_PIC)
6430 /* If this is a reference to an external symbol, and we are
6431 using a small GOT, we want
6432 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6436 lw $gp,cprestore($sp)
6437 The cprestore value is set using the .cprestore
6438 pseudo-op. If we are using a big GOT, we want
6439 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6441 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6445 lw $gp,cprestore($sp)
6446 If the symbol is not external, we want
6447 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6449 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6452 lw $gp,cprestore($sp)
6454 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6455 sequences above, minus nops, unless the symbol is local,
6456 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6462 relax_start (offset_expr.X_add_symbol);
6463 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6464 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6467 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6468 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6474 relax_start (offset_expr.X_add_symbol);
6475 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6476 BFD_RELOC_MIPS_CALL_HI16);
6477 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6478 PIC_CALL_REG, mips_gp_register);
6479 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6480 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6483 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6484 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6486 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6487 PIC_CALL_REG, PIC_CALL_REG,
6488 BFD_RELOC_MIPS_GOT_OFST);
6492 macro_build_jalr (&offset_expr);
6496 relax_start (offset_expr.X_add_symbol);
6499 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6500 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6509 gpdelay = reg_needs_delay (mips_gp_register);
6510 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6511 BFD_RELOC_MIPS_CALL_HI16);
6512 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6513 PIC_CALL_REG, mips_gp_register);
6514 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6515 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6520 macro_build (NULL, "nop", "");
6522 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6523 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6526 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6527 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6529 macro_build_jalr (&offset_expr);
6531 if (mips_cprestore_offset < 0)
6532 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6535 if (!mips_frame_reg_valid)
6537 as_warn (_("No .frame pseudo-op used in PIC code"));
6538 /* Quiet this warning. */
6539 mips_frame_reg_valid = 1;
6541 if (!mips_cprestore_valid)
6543 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6544 /* Quiet this warning. */
6545 mips_cprestore_valid = 1;
6547 if (mips_opts.noreorder)
6548 macro_build (NULL, "nop", "");
6549 expr1.X_add_number = mips_cprestore_offset;
6550 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6553 HAVE_64BIT_ADDRESSES);
6557 else if (mips_pic == VXWORKS_PIC)
6558 as_bad (_("Non-PIC jump used in PIC library"));
6581 /* Itbl support may require additional care here. */
6586 /* Itbl support may require additional care here. */
6591 /* Itbl support may require additional care here. */
6596 /* Itbl support may require additional care here. */
6609 /* Itbl support may require additional care here. */
6614 /* Itbl support may require additional care here. */
6619 /* Itbl support may require additional care here. */
6639 if (breg == treg || coproc || lr)
6660 /* Itbl support may require additional care here. */
6665 /* Itbl support may require additional care here. */
6670 /* Itbl support may require additional care here. */
6675 /* Itbl support may require additional care here. */
6699 /* Itbl support may require additional care here. */
6703 /* Itbl support may require additional care here. */
6708 /* Itbl support may require additional care here. */
6721 && NO_ISA_COP (mips_opts.arch)
6722 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6724 as_bad (_("Opcode not supported on this processor: %s"),
6725 mips_cpu_info_from_arch (mips_opts.arch)->name);
6729 /* Itbl support may require additional care here. */
6730 if (mask == M_LWC1_AB
6731 || mask == M_SWC1_AB
6732 || mask == M_LDC1_AB
6733 || mask == M_SDC1_AB
6737 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6744 if (offset_expr.X_op != O_constant
6745 && offset_expr.X_op != O_symbol)
6747 as_bad (_("Expression too complex"));
6748 offset_expr.X_op = O_constant;
6751 if (HAVE_32BIT_ADDRESSES
6752 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6756 sprintf_vma (value, offset_expr.X_add_number);
6757 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6760 /* A constant expression in PIC code can be handled just as it
6761 is in non PIC code. */
6762 if (offset_expr.X_op == O_constant)
6764 expr1.X_add_number = offset_expr.X_add_number;
6765 normalize_address_expr (&expr1);
6766 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6768 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6769 & ~(bfd_vma) 0xffff);
6770 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6772 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6773 tempreg, tempreg, breg);
6776 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6778 else if (mips_pic == NO_PIC)
6780 /* If this is a reference to a GP relative symbol, and there
6781 is no base register, we want
6782 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6783 Otherwise, if there is no base register, we want
6784 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6785 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6786 If we have a constant, we need two instructions anyhow,
6787 so we always use the latter form.
6789 If we have a base register, and this is a reference to a
6790 GP relative symbol, we want
6791 addu $tempreg,$breg,$gp
6792 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6794 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6795 addu $tempreg,$tempreg,$breg
6796 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6797 With a constant we always use the latter case.
6799 With 64bit address space and no base register and $at usable,
6801 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6802 lui $at,<sym> (BFD_RELOC_HI16_S)
6803 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6806 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6807 If we have a base register, we want
6808 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6809 lui $at,<sym> (BFD_RELOC_HI16_S)
6810 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6814 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6816 Without $at we can't generate the optimal path for superscalar
6817 processors here since this would require two temporary registers.
6818 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6819 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6821 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6823 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6824 If we have a base register, we want
6825 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6826 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6828 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6830 daddu $tempreg,$tempreg,$breg
6831 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6833 For GP relative symbols in 64bit address space we can use
6834 the same sequence as in 32bit address space. */
6835 if (HAVE_64BIT_SYMBOLS)
6837 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6838 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6840 relax_start (offset_expr.X_add_symbol);
6843 macro_build (&offset_expr, s, fmt, treg,
6844 BFD_RELOC_GPREL16, mips_gp_register);
6848 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6849 tempreg, breg, mips_gp_register);
6850 macro_build (&offset_expr, s, fmt, treg,
6851 BFD_RELOC_GPREL16, tempreg);
6856 if (used_at == 0 && mips_opts.at)
6858 macro_build (&offset_expr, "lui", "t,u", tempreg,
6859 BFD_RELOC_MIPS_HIGHEST);
6860 macro_build (&offset_expr, "lui", "t,u", AT,
6862 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6863 tempreg, BFD_RELOC_MIPS_HIGHER);
6865 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6866 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6867 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6868 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6874 macro_build (&offset_expr, "lui", "t,u", tempreg,
6875 BFD_RELOC_MIPS_HIGHEST);
6876 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6877 tempreg, BFD_RELOC_MIPS_HIGHER);
6878 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6879 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6880 tempreg, BFD_RELOC_HI16_S);
6881 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6883 macro_build (NULL, "daddu", "d,v,t",
6884 tempreg, tempreg, breg);
6885 macro_build (&offset_expr, s, fmt, treg,
6886 BFD_RELOC_LO16, tempreg);
6889 if (mips_relax.sequence)
6896 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6897 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6899 relax_start (offset_expr.X_add_symbol);
6900 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6904 macro_build_lui (&offset_expr, tempreg);
6905 macro_build (&offset_expr, s, fmt, treg,
6906 BFD_RELOC_LO16, tempreg);
6907 if (mips_relax.sequence)
6912 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6913 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6915 relax_start (offset_expr.X_add_symbol);
6916 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6917 tempreg, breg, mips_gp_register);
6918 macro_build (&offset_expr, s, fmt, treg,
6919 BFD_RELOC_GPREL16, tempreg);
6922 macro_build_lui (&offset_expr, tempreg);
6923 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6924 tempreg, tempreg, breg);
6925 macro_build (&offset_expr, s, fmt, treg,
6926 BFD_RELOC_LO16, tempreg);
6927 if (mips_relax.sequence)
6931 else if (!mips_big_got)
6933 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6935 /* If this is a reference to an external symbol, we want
6936 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6938 <op> $treg,0($tempreg)
6940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6942 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6943 <op> $treg,0($tempreg)
6946 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6947 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6949 If there is a base register, we add it to $tempreg before
6950 the <op>. If there is a constant, we stick it in the
6951 <op> instruction. We don't handle constants larger than
6952 16 bits, because we have no way to load the upper 16 bits
6953 (actually, we could handle them for the subset of cases
6954 in which we are not using $at). */
6955 gas_assert (offset_expr.X_op == O_symbol);
6958 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6959 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6961 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6962 tempreg, tempreg, breg);
6963 macro_build (&offset_expr, s, fmt, treg,
6964 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6967 expr1.X_add_number = offset_expr.X_add_number;
6968 offset_expr.X_add_number = 0;
6969 if (expr1.X_add_number < -0x8000
6970 || expr1.X_add_number >= 0x8000)
6971 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6972 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6973 lw_reloc_type, mips_gp_register);
6975 relax_start (offset_expr.X_add_symbol);
6977 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6978 tempreg, BFD_RELOC_LO16);
6981 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6982 tempreg, tempreg, breg);
6983 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6985 else if (mips_big_got && !HAVE_NEWABI)
6989 /* If this is a reference to an external symbol, we want
6990 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6991 addu $tempreg,$tempreg,$gp
6992 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6993 <op> $treg,0($tempreg)
6995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6997 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6998 <op> $treg,0($tempreg)
6999 If there is a base register, we add it to $tempreg before
7000 the <op>. If there is a constant, we stick it in the
7001 <op> instruction. We don't handle constants larger than
7002 16 bits, because we have no way to load the upper 16 bits
7003 (actually, we could handle them for the subset of cases
7004 in which we are not using $at). */
7005 gas_assert (offset_expr.X_op == O_symbol);
7006 expr1.X_add_number = offset_expr.X_add_number;
7007 offset_expr.X_add_number = 0;
7008 if (expr1.X_add_number < -0x8000
7009 || expr1.X_add_number >= 0x8000)
7010 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7011 gpdelay = reg_needs_delay (mips_gp_register);
7012 relax_start (offset_expr.X_add_symbol);
7013 macro_build (&offset_expr, "lui", "t,u", tempreg,
7014 BFD_RELOC_MIPS_GOT_HI16);
7015 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7017 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7018 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7021 macro_build (NULL, "nop", "");
7022 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7023 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7025 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7026 tempreg, BFD_RELOC_LO16);
7030 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7031 tempreg, tempreg, breg);
7032 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7034 else if (mips_big_got && HAVE_NEWABI)
7036 /* If this is a reference to an external symbol, we want
7037 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7038 add $tempreg,$tempreg,$gp
7039 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7040 <op> $treg,<ofst>($tempreg)
7041 Otherwise, for local symbols, we want:
7042 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7043 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7044 gas_assert (offset_expr.X_op == O_symbol);
7045 expr1.X_add_number = offset_expr.X_add_number;
7046 offset_expr.X_add_number = 0;
7047 if (expr1.X_add_number < -0x8000
7048 || expr1.X_add_number >= 0x8000)
7049 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7050 relax_start (offset_expr.X_add_symbol);
7051 macro_build (&offset_expr, "lui", "t,u", tempreg,
7052 BFD_RELOC_MIPS_GOT_HI16);
7053 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7055 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7056 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7058 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7059 tempreg, tempreg, breg);
7060 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7063 offset_expr.X_add_number = expr1.X_add_number;
7064 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7065 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7067 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7068 tempreg, tempreg, breg);
7069 macro_build (&offset_expr, s, fmt, treg,
7070 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7080 load_register (treg, &imm_expr, 0);
7084 load_register (treg, &imm_expr, 1);
7088 if (imm_expr.X_op == O_constant)
7091 load_register (AT, &imm_expr, 0);
7092 macro_build (NULL, "mtc1", "t,G", AT, treg);
7097 gas_assert (offset_expr.X_op == O_symbol
7098 && strcmp (segment_name (S_GET_SEGMENT
7099 (offset_expr.X_add_symbol)),
7101 && offset_expr.X_add_number == 0);
7102 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7103 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7108 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7109 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7110 order 32 bits of the value and the low order 32 bits are either
7111 zero or in OFFSET_EXPR. */
7112 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7114 if (HAVE_64BIT_GPRS)
7115 load_register (treg, &imm_expr, 1);
7120 if (target_big_endian)
7132 load_register (hreg, &imm_expr, 0);
7135 if (offset_expr.X_op == O_absent)
7136 move_register (lreg, 0);
7139 gas_assert (offset_expr.X_op == O_constant);
7140 load_register (lreg, &offset_expr, 0);
7147 /* We know that sym is in the .rdata section. First we get the
7148 upper 16 bits of the address. */
7149 if (mips_pic == NO_PIC)
7151 macro_build_lui (&offset_expr, AT);
7156 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7157 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7161 /* Now we load the register(s). */
7162 if (HAVE_64BIT_GPRS)
7165 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7170 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7173 /* FIXME: How in the world do we deal with the possible
7175 offset_expr.X_add_number += 4;
7176 macro_build (&offset_expr, "lw", "t,o(b)",
7177 treg + 1, BFD_RELOC_LO16, AT);
7183 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7184 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7185 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7186 the value and the low order 32 bits are either zero or in
7188 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7191 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7192 if (HAVE_64BIT_FPRS)
7194 gas_assert (HAVE_64BIT_GPRS);
7195 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7199 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7200 if (offset_expr.X_op == O_absent)
7201 macro_build (NULL, "mtc1", "t,G", 0, treg);
7204 gas_assert (offset_expr.X_op == O_constant);
7205 load_register (AT, &offset_expr, 0);
7206 macro_build (NULL, "mtc1", "t,G", AT, treg);
7212 gas_assert (offset_expr.X_op == O_symbol
7213 && offset_expr.X_add_number == 0);
7214 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7215 if (strcmp (s, ".lit8") == 0)
7217 if (mips_opts.isa != ISA_MIPS1)
7219 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7220 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7223 breg = mips_gp_register;
7224 r = BFD_RELOC_MIPS_LITERAL;
7229 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7231 if (mips_pic != NO_PIC)
7232 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7233 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7236 /* FIXME: This won't work for a 64 bit address. */
7237 macro_build_lui (&offset_expr, AT);
7240 if (mips_opts.isa != ISA_MIPS1)
7242 macro_build (&offset_expr, "ldc1", "T,o(b)",
7243 treg, BFD_RELOC_LO16, AT);
7252 /* Even on a big endian machine $fn comes before $fn+1. We have
7253 to adjust when loading from memory. */
7256 gas_assert (mips_opts.isa == ISA_MIPS1);
7257 macro_build (&offset_expr, "lwc1", "T,o(b)",
7258 target_big_endian ? treg + 1 : treg, r, breg);
7259 /* FIXME: A possible overflow which I don't know how to deal
7261 offset_expr.X_add_number += 4;
7262 macro_build (&offset_expr, "lwc1", "T,o(b)",
7263 target_big_endian ? treg : treg + 1, r, breg);
7267 gas_assert (mips_opts.isa == ISA_MIPS1);
7268 /* Even on a big endian machine $fn comes before $fn+1. We have
7269 to adjust when storing to memory. */
7270 macro_build (&offset_expr, "swc1", "T,o(b)",
7271 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7272 offset_expr.X_add_number += 4;
7273 macro_build (&offset_expr, "swc1", "T,o(b)",
7274 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7279 * The MIPS assembler seems to check for X_add_number not
7280 * being double aligned and generating:
7283 * addiu at,at,%lo(foo+1)
7286 * But, the resulting address is the same after relocation so why
7287 * generate the extra instruction?
7289 /* Itbl support may require additional care here. */
7291 if (mips_opts.isa != ISA_MIPS1)
7302 if (mips_opts.isa != ISA_MIPS1)
7310 /* Itbl support may require additional care here. */
7315 if (HAVE_64BIT_GPRS)
7326 if (HAVE_64BIT_GPRS)
7336 if (offset_expr.X_op != O_symbol
7337 && offset_expr.X_op != O_constant)
7339 as_bad (_("Expression too complex"));
7340 offset_expr.X_op = O_constant;
7343 if (HAVE_32BIT_ADDRESSES
7344 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7348 sprintf_vma (value, offset_expr.X_add_number);
7349 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7352 /* Even on a big endian machine $fn comes before $fn+1. We have
7353 to adjust when loading from memory. We set coproc if we must
7354 load $fn+1 first. */
7355 /* Itbl support may require additional care here. */
7356 if (!target_big_endian)
7359 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7361 /* If this is a reference to a GP relative symbol, we want
7362 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7363 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7364 If we have a base register, we use this
7366 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7367 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7368 If this is not a GP relative symbol, we want
7369 lui $at,<sym> (BFD_RELOC_HI16_S)
7370 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7371 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7372 If there is a base register, we add it to $at after the
7373 lui instruction. If there is a constant, we always use
7375 if (offset_expr.X_op == O_symbol
7376 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7377 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7379 relax_start (offset_expr.X_add_symbol);
7382 tempreg = mips_gp_register;
7386 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7387 AT, breg, mips_gp_register);
7392 /* Itbl support may require additional care here. */
7393 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7394 BFD_RELOC_GPREL16, tempreg);
7395 offset_expr.X_add_number += 4;
7397 /* Set mips_optimize to 2 to avoid inserting an
7399 hold_mips_optimize = mips_optimize;
7401 /* Itbl support may require additional care here. */
7402 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7403 BFD_RELOC_GPREL16, tempreg);
7404 mips_optimize = hold_mips_optimize;
7408 offset_expr.X_add_number -= 4;
7411 macro_build_lui (&offset_expr, AT);
7413 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7414 /* Itbl support may require additional care here. */
7415 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7416 BFD_RELOC_LO16, AT);
7417 /* FIXME: How do we handle overflow here? */
7418 offset_expr.X_add_number += 4;
7419 /* Itbl support may require additional care here. */
7420 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7421 BFD_RELOC_LO16, AT);
7422 if (mips_relax.sequence)
7425 else if (!mips_big_got)
7427 /* If this is a reference to an external symbol, we want
7428 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7433 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7435 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7436 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7437 If there is a base register we add it to $at before the
7438 lwc1 instructions. If there is a constant we include it
7439 in the lwc1 instructions. */
7441 expr1.X_add_number = offset_expr.X_add_number;
7442 if (expr1.X_add_number < -0x8000
7443 || expr1.X_add_number >= 0x8000 - 4)
7444 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7445 load_got_offset (AT, &offset_expr);
7448 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7450 /* Set mips_optimize to 2 to avoid inserting an undesired
7452 hold_mips_optimize = mips_optimize;
7455 /* Itbl support may require additional care here. */
7456 relax_start (offset_expr.X_add_symbol);
7457 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7458 BFD_RELOC_LO16, AT);
7459 expr1.X_add_number += 4;
7460 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7461 BFD_RELOC_LO16, AT);
7463 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7464 BFD_RELOC_LO16, AT);
7465 offset_expr.X_add_number += 4;
7466 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7467 BFD_RELOC_LO16, AT);
7470 mips_optimize = hold_mips_optimize;
7472 else if (mips_big_got)
7476 /* If this is a reference to an external symbol, we want
7477 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7479 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7484 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7486 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7487 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7488 If there is a base register we add it to $at before the
7489 lwc1 instructions. If there is a constant we include it
7490 in the lwc1 instructions. */
7492 expr1.X_add_number = offset_expr.X_add_number;
7493 offset_expr.X_add_number = 0;
7494 if (expr1.X_add_number < -0x8000
7495 || expr1.X_add_number >= 0x8000 - 4)
7496 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7497 gpdelay = reg_needs_delay (mips_gp_register);
7498 relax_start (offset_expr.X_add_symbol);
7499 macro_build (&offset_expr, "lui", "t,u",
7500 AT, BFD_RELOC_MIPS_GOT_HI16);
7501 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7502 AT, AT, mips_gp_register);
7503 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7504 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7507 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7508 /* Itbl support may require additional care here. */
7509 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7510 BFD_RELOC_LO16, AT);
7511 expr1.X_add_number += 4;
7513 /* Set mips_optimize to 2 to avoid inserting an undesired
7515 hold_mips_optimize = mips_optimize;
7517 /* Itbl support may require additional care here. */
7518 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7519 BFD_RELOC_LO16, AT);
7520 mips_optimize = hold_mips_optimize;
7521 expr1.X_add_number -= 4;
7524 offset_expr.X_add_number = expr1.X_add_number;
7526 macro_build (NULL, "nop", "");
7527 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7528 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7531 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7532 /* Itbl support may require additional care here. */
7533 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7534 BFD_RELOC_LO16, AT);
7535 offset_expr.X_add_number += 4;
7537 /* Set mips_optimize to 2 to avoid inserting an undesired
7539 hold_mips_optimize = mips_optimize;
7541 /* Itbl support may require additional care here. */
7542 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7543 BFD_RELOC_LO16, AT);
7544 mips_optimize = hold_mips_optimize;
7553 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7556 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7558 macro_build (&offset_expr, s, "t,o(b)", treg,
7559 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7561 if (!HAVE_64BIT_GPRS)
7563 offset_expr.X_add_number += 4;
7564 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7565 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7570 /* New code added to support COPZ instructions.
7571 This code builds table entries out of the macros in mip_opcodes.
7572 R4000 uses interlocks to handle coproc delays.
7573 Other chips (like the R3000) require nops to be inserted for delays.
7575 FIXME: Currently, we require that the user handle delays.
7576 In order to fill delay slots for non-interlocked chips,
7577 we must have a way to specify delays based on the coprocessor.
7578 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7579 What are the side-effects of the cop instruction?
7580 What cache support might we have and what are its effects?
7581 Both coprocessor & memory require delays. how long???
7582 What registers are read/set/modified?
7584 If an itbl is provided to interpret cop instructions,
7585 this knowledge can be encoded in the itbl spec. */
7599 if (NO_ISA_COP (mips_opts.arch)
7600 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7602 as_bad (_("opcode not supported on this processor: %s"),
7603 mips_cpu_info_from_arch (mips_opts.arch)->name);
7607 /* For now we just do C (same as Cz). The parameter will be
7608 stored in insn_opcode by mips_ip. */
7609 macro_build (NULL, s, "C", ip->insn_opcode);
7613 move_register (dreg, sreg);
7619 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7620 macro_build (NULL, "mflo", "d", dreg);
7626 /* The MIPS assembler some times generates shifts and adds. I'm
7627 not trying to be that fancy. GCC should do this for us
7630 load_register (AT, &imm_expr, dbl);
7631 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7632 macro_build (NULL, "mflo", "d", dreg);
7648 load_register (AT, &imm_expr, dbl);
7649 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7650 macro_build (NULL, "mflo", "d", dreg);
7651 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7652 macro_build (NULL, "mfhi", "d", AT);
7654 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7657 expr1.X_add_number = 8;
7658 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7659 macro_build (NULL, "nop", "");
7660 macro_build (NULL, "break", "c", 6);
7663 macro_build (NULL, "mflo", "d", dreg);
7679 load_register (AT, &imm_expr, dbl);
7680 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7681 sreg, imm ? AT : treg);
7682 macro_build (NULL, "mfhi", "d", AT);
7683 macro_build (NULL, "mflo", "d", dreg);
7685 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7688 expr1.X_add_number = 8;
7689 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7690 macro_build (NULL, "nop", "");
7691 macro_build (NULL, "break", "c", 6);
7697 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7708 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7709 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7713 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7714 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7715 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7716 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7720 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7731 macro_build (NULL, "negu", "d,w", tempreg, treg);
7732 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7736 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7737 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7738 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7739 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7748 if (imm_expr.X_op != O_constant)
7749 as_bad (_("Improper rotate count"));
7750 rot = imm_expr.X_add_number & 0x3f;
7751 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7753 rot = (64 - rot) & 0x3f;
7755 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7757 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7762 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7765 l = (rot < 0x20) ? "dsll" : "dsll32";
7766 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7769 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7770 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7771 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7779 if (imm_expr.X_op != O_constant)
7780 as_bad (_("Improper rotate count"));
7781 rot = imm_expr.X_add_number & 0x1f;
7782 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7784 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7789 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7793 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7794 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7795 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7800 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7802 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7806 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7807 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7808 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7809 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7813 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7815 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7819 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7820 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7821 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7822 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7831 if (imm_expr.X_op != O_constant)
7832 as_bad (_("Improper rotate count"));
7833 rot = imm_expr.X_add_number & 0x3f;
7834 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7837 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7839 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7844 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7847 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7848 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7851 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7852 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7853 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7861 if (imm_expr.X_op != O_constant)
7862 as_bad (_("Improper rotate count"));
7863 rot = imm_expr.X_add_number & 0x1f;
7864 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7866 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7871 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7875 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7876 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7877 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7883 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7885 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7888 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7889 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7894 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7896 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7901 as_warn (_("Instruction %s: result is always false"),
7903 move_register (dreg, 0);
7906 if (CPU_HAS_SEQ (mips_opts.arch)
7907 && -512 <= imm_expr.X_add_number
7908 && imm_expr.X_add_number < 512)
7910 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7911 (int) imm_expr.X_add_number);
7914 if (imm_expr.X_op == O_constant
7915 && imm_expr.X_add_number >= 0
7916 && imm_expr.X_add_number < 0x10000)
7918 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7920 else if (imm_expr.X_op == O_constant
7921 && imm_expr.X_add_number > -0x8000
7922 && imm_expr.X_add_number < 0)
7924 imm_expr.X_add_number = -imm_expr.X_add_number;
7925 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7926 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7928 else if (CPU_HAS_SEQ (mips_opts.arch))
7931 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7932 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7937 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7938 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7941 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7944 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7950 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7951 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7954 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7956 if (imm_expr.X_op == O_constant
7957 && imm_expr.X_add_number >= -0x8000
7958 && imm_expr.X_add_number < 0x8000)
7960 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7961 dreg, sreg, BFD_RELOC_LO16);
7965 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7966 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7970 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7973 case M_SGT: /* sreg > treg <==> treg < sreg */
7979 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7982 case M_SGT_I: /* sreg > I <==> I < sreg */
7989 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7990 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7993 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7999 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8000 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8003 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8010 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8011 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8012 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8016 if (imm_expr.X_op == O_constant
8017 && imm_expr.X_add_number >= -0x8000
8018 && imm_expr.X_add_number < 0x8000)
8020 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8024 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8025 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8029 if (imm_expr.X_op == O_constant
8030 && imm_expr.X_add_number >= -0x8000
8031 && imm_expr.X_add_number < 0x8000)
8033 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8038 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8039 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8044 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8046 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8049 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8050 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8055 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8057 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8062 as_warn (_("Instruction %s: result is always true"),
8064 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8065 dreg, 0, BFD_RELOC_LO16);
8068 if (CPU_HAS_SEQ (mips_opts.arch)
8069 && -512 <= imm_expr.X_add_number
8070 && imm_expr.X_add_number < 512)
8072 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8073 (int) imm_expr.X_add_number);
8076 if (imm_expr.X_op == O_constant
8077 && imm_expr.X_add_number >= 0
8078 && imm_expr.X_add_number < 0x10000)
8080 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8082 else if (imm_expr.X_op == O_constant
8083 && imm_expr.X_add_number > -0x8000
8084 && imm_expr.X_add_number < 0)
8086 imm_expr.X_add_number = -imm_expr.X_add_number;
8087 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8088 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8090 else if (CPU_HAS_SEQ (mips_opts.arch))
8093 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8094 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8099 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8100 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8103 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8109 if (imm_expr.X_op == O_constant
8110 && imm_expr.X_add_number > -0x8000
8111 && imm_expr.X_add_number <= 0x8000)
8113 imm_expr.X_add_number = -imm_expr.X_add_number;
8114 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8115 dreg, sreg, BFD_RELOC_LO16);
8119 load_register (AT, &imm_expr, dbl);
8120 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8126 if (imm_expr.X_op == O_constant
8127 && imm_expr.X_add_number > -0x8000
8128 && imm_expr.X_add_number <= 0x8000)
8130 imm_expr.X_add_number = -imm_expr.X_add_number;
8131 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8132 dreg, sreg, BFD_RELOC_LO16);
8136 load_register (AT, &imm_expr, dbl);
8137 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8159 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8160 macro_build (NULL, s, "s,t", sreg, AT);
8165 gas_assert (mips_opts.isa == ISA_MIPS1);
8167 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8168 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8171 * Is the double cfc1 instruction a bug in the mips assembler;
8172 * or is there a reason for it?
8175 macro_build (NULL, "cfc1", "t,G", treg, RA);
8176 macro_build (NULL, "cfc1", "t,G", treg, RA);
8177 macro_build (NULL, "nop", "");
8178 expr1.X_add_number = 3;
8179 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8180 expr1.X_add_number = 2;
8181 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8182 macro_build (NULL, "ctc1", "t,G", AT, RA);
8183 macro_build (NULL, "nop", "");
8184 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8186 macro_build (NULL, "ctc1", "t,G", treg, RA);
8187 macro_build (NULL, "nop", "");
8198 if (offset_expr.X_add_number >= 0x7fff)
8199 as_bad (_("Operand overflow"));
8200 if (!target_big_endian)
8201 ++offset_expr.X_add_number;
8202 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8203 if (!target_big_endian)
8204 --offset_expr.X_add_number;
8206 ++offset_expr.X_add_number;
8207 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8208 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8209 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8222 if (offset_expr.X_add_number >= 0x8000 - off)
8223 as_bad (_("Operand overflow"));
8231 if (!target_big_endian)
8232 offset_expr.X_add_number += off;
8233 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8234 if (!target_big_endian)
8235 offset_expr.X_add_number -= off;
8237 offset_expr.X_add_number += off;
8238 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8240 /* If necessary, move the result in tempreg to the final destination. */
8241 if (treg == tempreg)
8243 /* Protect second load's delay slot. */
8245 move_register (treg, tempreg);
8259 load_address (AT, &offset_expr, &used_at);
8261 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8262 if (!target_big_endian)
8263 expr1.X_add_number = off;
8265 expr1.X_add_number = 0;
8266 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8267 if (!target_big_endian)
8268 expr1.X_add_number = 0;
8270 expr1.X_add_number = off;
8271 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8277 load_address (AT, &offset_expr, &used_at);
8279 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8280 if (target_big_endian)
8281 expr1.X_add_number = 0;
8282 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8283 treg, BFD_RELOC_LO16, AT);
8284 if (target_big_endian)
8285 expr1.X_add_number = 1;
8287 expr1.X_add_number = 0;
8288 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8289 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8290 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8295 if (offset_expr.X_add_number >= 0x7fff)
8296 as_bad (_("Operand overflow"));
8297 if (target_big_endian)
8298 ++offset_expr.X_add_number;
8299 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8300 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8301 if (target_big_endian)
8302 --offset_expr.X_add_number;
8304 ++offset_expr.X_add_number;
8305 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8318 if (offset_expr.X_add_number >= 0x8000 - off)
8319 as_bad (_("Operand overflow"));
8320 if (!target_big_endian)
8321 offset_expr.X_add_number += off;
8322 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8323 if (!target_big_endian)
8324 offset_expr.X_add_number -= off;
8326 offset_expr.X_add_number += off;
8327 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8341 load_address (AT, &offset_expr, &used_at);
8343 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8344 if (!target_big_endian)
8345 expr1.X_add_number = off;
8347 expr1.X_add_number = 0;
8348 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8349 if (!target_big_endian)
8350 expr1.X_add_number = 0;
8352 expr1.X_add_number = off;
8353 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8358 load_address (AT, &offset_expr, &used_at);
8360 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8361 if (!target_big_endian)
8362 expr1.X_add_number = 0;
8363 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8364 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8365 if (!target_big_endian)
8366 expr1.X_add_number = 1;
8368 expr1.X_add_number = 0;
8369 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8370 if (!target_big_endian)
8371 expr1.X_add_number = 0;
8373 expr1.X_add_number = 1;
8374 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8375 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8376 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8380 /* FIXME: Check if this is one of the itbl macros, since they
8381 are added dynamically. */
8382 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8385 if (!mips_opts.at && used_at)
8386 as_bad (_("Macro used $at after \".set noat\""));
8389 /* Implement macros in mips16 mode. */
8392 mips16_macro (struct mips_cl_insn *ip)
8395 int xreg, yreg, zreg, tmp;
8398 const char *s, *s2, *s3;
8400 mask = ip->insn_mo->mask;
8402 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8403 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8404 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8406 expr1.X_op = O_constant;
8407 expr1.X_op_symbol = NULL;
8408 expr1.X_add_symbol = NULL;
8409 expr1.X_add_number = 1;
8429 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8430 expr1.X_add_number = 2;
8431 macro_build (&expr1, "bnez", "x,p", yreg);
8432 macro_build (NULL, "break", "6", 7);
8434 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8435 since that causes an overflow. We should do that as well,
8436 but I don't see how to do the comparisons without a temporary
8439 macro_build (NULL, s, "x", zreg);
8459 macro_build (NULL, s, "0,x,y", xreg, yreg);
8460 expr1.X_add_number = 2;
8461 macro_build (&expr1, "bnez", "x,p", yreg);
8462 macro_build (NULL, "break", "6", 7);
8464 macro_build (NULL, s2, "x", zreg);
8470 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8471 macro_build (NULL, "mflo", "x", zreg);
8479 if (imm_expr.X_op != O_constant)
8480 as_bad (_("Unsupported large constant"));
8481 imm_expr.X_add_number = -imm_expr.X_add_number;
8482 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8486 if (imm_expr.X_op != O_constant)
8487 as_bad (_("Unsupported large constant"));
8488 imm_expr.X_add_number = -imm_expr.X_add_number;
8489 macro_build (&imm_expr, "addiu", "x,k", xreg);
8493 if (imm_expr.X_op != O_constant)
8494 as_bad (_("Unsupported large constant"));
8495 imm_expr.X_add_number = -imm_expr.X_add_number;
8496 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8518 goto do_reverse_branch;
8522 goto do_reverse_branch;
8534 goto do_reverse_branch;
8545 macro_build (NULL, s, "x,y", xreg, yreg);
8546 macro_build (&offset_expr, s2, "p");
8573 goto do_addone_branch_i;
8578 goto do_addone_branch_i;
8593 goto do_addone_branch_i;
8600 if (imm_expr.X_op != O_constant)
8601 as_bad (_("Unsupported large constant"));
8602 ++imm_expr.X_add_number;
8605 macro_build (&imm_expr, s, s3, xreg);
8606 macro_build (&offset_expr, s2, "p");
8610 expr1.X_add_number = 0;
8611 macro_build (&expr1, "slti", "x,8", yreg);
8613 move_register (xreg, yreg);
8614 expr1.X_add_number = 2;
8615 macro_build (&expr1, "bteqz", "p");
8616 macro_build (NULL, "neg", "x,w", xreg, xreg);
8620 /* For consistency checking, verify that all bits are specified either
8621 by the match/mask part of the instruction definition, or by the
8624 validate_mips_insn (const struct mips_opcode *opc)
8626 const char *p = opc->args;
8628 unsigned long used_bits = opc->mask;
8630 if ((used_bits & opc->match) != opc->match)
8632 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8633 opc->name, opc->args);
8636 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8646 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8647 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8648 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8649 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8650 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8651 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8652 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8653 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8654 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8655 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8656 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8657 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8658 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8660 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8661 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8662 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8663 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8664 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8665 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8666 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8667 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8668 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8669 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8670 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8671 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8672 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8673 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8674 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8677 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8678 c, opc->name, opc->args);
8682 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8683 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8685 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8686 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8687 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8688 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8690 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8691 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8693 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8694 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8696 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8697 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8698 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8699 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8700 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8701 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8702 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8703 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8704 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8705 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8706 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8707 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8708 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8709 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8710 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8711 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8712 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8714 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8715 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8716 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8717 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8719 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8720 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8721 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8722 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8723 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8724 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8725 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8726 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8727 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8730 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8731 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8732 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8733 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8734 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8737 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8738 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8739 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8740 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8741 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8742 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8743 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8744 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8745 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8746 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8747 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8748 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8749 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8750 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8751 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8752 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8753 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8754 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8756 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8757 c, opc->name, opc->args);
8761 if (used_bits != 0xffffffff)
8763 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8764 ~used_bits & 0xffffffff, opc->name, opc->args);
8770 /* UDI immediates. */
8778 static const struct mips_immed mips_immed[] = {
8779 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8780 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8781 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8782 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8786 /* Check whether an odd floating-point register is allowed. */
8788 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8790 const char *s = insn->name;
8792 if (insn->pinfo == INSN_MACRO)
8793 /* Let a macro pass, we'll catch it later when it is expanded. */
8796 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8798 /* Allow odd registers for single-precision ops. */
8799 switch (insn->pinfo & (FP_S | FP_D))
8803 return 1; /* both single precision - ok */
8805 return 0; /* both double precision - fail */
8810 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8811 s = strchr (insn->name, '.');
8813 s = s != NULL ? strchr (s + 1, '.') : NULL;
8814 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8817 /* Single-precision coprocessor loads and moves are OK too. */
8818 if ((insn->pinfo & FP_S)
8819 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8820 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8826 /* This routine assembles an instruction into its binary format. As a
8827 side effect, it sets one of the global variables imm_reloc or
8828 offset_reloc to the type of relocation to do if one of the operands
8829 is an address expression. */
8832 mips_ip (char *str, struct mips_cl_insn *ip)
8837 struct mips_opcode *insn;
8840 unsigned int lastregno;
8841 unsigned int lastpos = 0;
8842 unsigned int limlo, limhi;
8845 offsetT min_range, max_range;
8851 /* If the instruction contains a '.', we first try to match an instruction
8852 including the '.'. Then we try again without the '.'. */
8854 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8857 /* If we stopped on whitespace, then replace the whitespace with null for
8858 the call to hash_find. Save the character we replaced just in case we
8859 have to re-parse the instruction. */
8866 insn = (struct mips_opcode *) hash_find (op_hash, str);
8868 /* If we didn't find the instruction in the opcode table, try again, but
8869 this time with just the instruction up to, but not including the
8873 /* Restore the character we overwrite above (if any). */
8877 /* Scan up to the first '.' or whitespace. */
8879 *s != '\0' && *s != '.' && !ISSPACE (*s);
8883 /* If we did not find a '.', then we can quit now. */
8886 insn_error = _("Unrecognized opcode");
8890 /* Lookup the instruction in the hash table. */
8892 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8894 insn_error = _("Unrecognized opcode");
8904 gas_assert (strcmp (insn->name, str) == 0);
8906 ok = is_opcode_valid (insn);
8909 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8910 && strcmp (insn->name, insn[1].name) == 0)
8919 static char buf[100];
8921 _("opcode not supported on this processor: %s (%s)"),
8922 mips_cpu_info_from_arch (mips_opts.arch)->name,
8923 mips_cpu_info_from_isa (mips_opts.isa)->name);
8932 create_insn (ip, insn);
8935 lastregno = 0xffffffff;
8936 for (args = insn->args;; ++args)
8940 s += strspn (s, " \t");
8944 case '\0': /* end of args */
8949 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
8950 my_getExpression (&imm_expr, s);
8951 check_absolute_expr (ip, &imm_expr);
8952 if ((unsigned long) imm_expr.X_add_number != 1
8953 && (unsigned long) imm_expr.X_add_number != 3)
8955 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8956 (unsigned long) imm_expr.X_add_number);
8958 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8959 imm_expr.X_op = O_absent;
8963 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
8964 my_getExpression (&imm_expr, s);
8965 check_absolute_expr (ip, &imm_expr);
8966 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8968 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8969 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8971 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8972 imm_expr.X_op = O_absent;
8976 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
8977 my_getExpression (&imm_expr, s);
8978 check_absolute_expr (ip, &imm_expr);
8979 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8981 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8982 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8984 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8985 imm_expr.X_op = O_absent;
8989 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
8990 my_getExpression (&imm_expr, s);
8991 check_absolute_expr (ip, &imm_expr);
8992 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8994 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8995 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8997 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8998 imm_expr.X_op = O_absent;
9002 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9003 my_getExpression (&imm_expr, s);
9004 check_absolute_expr (ip, &imm_expr);
9005 if (imm_expr.X_add_number & ~OP_MASK_RS)
9007 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9008 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9010 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9011 imm_expr.X_op = O_absent;
9015 case '7': /* Four DSP accumulators in bits 11,12. */
9016 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9017 s[3] >= '0' && s[3] <= '3')
9021 INSERT_OPERAND (DSPACC, *ip, regno);
9025 as_bad (_("Invalid dsp acc register"));
9028 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9029 my_getExpression (&imm_expr, s);
9030 check_absolute_expr (ip, &imm_expr);
9031 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9033 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9035 (unsigned long) imm_expr.X_add_number);
9037 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9038 imm_expr.X_op = O_absent;
9042 case '9': /* Four DSP accumulators in bits 21,22. */
9043 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9044 s[3] >= '0' && s[3] <= '3')
9048 INSERT_OPERAND (DSPACC_S, *ip, regno);
9052 as_bad (_("Invalid dsp acc register"));
9055 case '0': /* DSP 6-bit signed immediate in bit 20. */
9056 my_getExpression (&imm_expr, s);
9057 check_absolute_expr (ip, &imm_expr);
9058 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9059 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9060 if (imm_expr.X_add_number < min_range ||
9061 imm_expr.X_add_number > max_range)
9063 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9064 (long) min_range, (long) max_range,
9065 (long) imm_expr.X_add_number);
9067 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9068 imm_expr.X_op = O_absent;
9072 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9073 my_getExpression (&imm_expr, s);
9074 check_absolute_expr (ip, &imm_expr);
9075 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9077 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9079 (unsigned long) imm_expr.X_add_number);
9081 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9082 imm_expr.X_op = O_absent;
9086 case ':': /* DSP 7-bit signed immediate in bit 19. */
9087 my_getExpression (&imm_expr, s);
9088 check_absolute_expr (ip, &imm_expr);
9089 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9090 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9091 if (imm_expr.X_add_number < min_range ||
9092 imm_expr.X_add_number > max_range)
9094 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9095 (long) min_range, (long) max_range,
9096 (long) imm_expr.X_add_number);
9098 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9099 imm_expr.X_op = O_absent;
9103 case '@': /* DSP 10-bit signed immediate in bit 16. */
9104 my_getExpression (&imm_expr, s);
9105 check_absolute_expr (ip, &imm_expr);
9106 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9107 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9108 if (imm_expr.X_add_number < min_range ||
9109 imm_expr.X_add_number > max_range)
9111 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9112 (long) min_range, (long) max_range,
9113 (long) imm_expr.X_add_number);
9115 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9116 imm_expr.X_op = O_absent;
9120 case '!': /* MT usermode flag bit. */
9121 my_getExpression (&imm_expr, s);
9122 check_absolute_expr (ip, &imm_expr);
9123 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9124 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9125 (unsigned long) imm_expr.X_add_number);
9126 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9127 imm_expr.X_op = O_absent;
9131 case '$': /* MT load high flag bit. */
9132 my_getExpression (&imm_expr, s);
9133 check_absolute_expr (ip, &imm_expr);
9134 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9135 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9136 (unsigned long) imm_expr.X_add_number);
9137 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9138 imm_expr.X_op = O_absent;
9142 case '*': /* Four DSP accumulators in bits 18,19. */
9143 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9144 s[3] >= '0' && s[3] <= '3')
9148 INSERT_OPERAND (MTACC_T, *ip, regno);
9152 as_bad (_("Invalid dsp/smartmips acc register"));
9155 case '&': /* Four DSP accumulators in bits 13,14. */
9156 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9157 s[3] >= '0' && s[3] <= '3')
9161 INSERT_OPERAND (MTACC_D, *ip, regno);
9165 as_bad (_("Invalid dsp/smartmips acc register"));
9177 INSERT_OPERAND (RS, *ip, lastregno);
9181 INSERT_OPERAND (RT, *ip, lastregno);
9185 INSERT_OPERAND (FT, *ip, lastregno);
9189 INSERT_OPERAND (FS, *ip, lastregno);
9195 /* Handle optional base register.
9196 Either the base register is omitted or
9197 we must have a left paren. */
9198 /* This is dependent on the next operand specifier
9199 is a base register specification. */
9200 gas_assert (args[1] == 'b');
9204 case ')': /* These must match exactly. */
9211 case '+': /* Opcode extension character. */
9214 case '1': /* UDI immediates. */
9219 const struct mips_immed *imm = mips_immed;
9221 while (imm->type && imm->type != *args)
9225 my_getExpression (&imm_expr, s);
9226 check_absolute_expr (ip, &imm_expr);
9227 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9229 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9230 imm->desc ? imm->desc : ip->insn_mo->name,
9231 (unsigned long) imm_expr.X_add_number,
9232 (unsigned long) imm_expr.X_add_number);
9233 imm_expr.X_add_number &= imm->mask;
9235 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9237 imm_expr.X_op = O_absent;
9242 case 'A': /* ins/ext position, becomes LSB. */
9251 my_getExpression (&imm_expr, s);
9252 check_absolute_expr (ip, &imm_expr);
9253 if ((unsigned long) imm_expr.X_add_number < limlo
9254 || (unsigned long) imm_expr.X_add_number > limhi)
9256 as_bad (_("Improper position (%lu)"),
9257 (unsigned long) imm_expr.X_add_number);
9258 imm_expr.X_add_number = limlo;
9260 lastpos = imm_expr.X_add_number;
9261 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9262 imm_expr.X_op = O_absent;
9266 case 'B': /* ins size, becomes MSB. */
9275 my_getExpression (&imm_expr, s);
9276 check_absolute_expr (ip, &imm_expr);
9277 /* Check for negative input so that small negative numbers
9278 will not succeed incorrectly. The checks against
9279 (pos+size) transitively check "size" itself,
9280 assuming that "pos" is reasonable. */
9281 if ((long) imm_expr.X_add_number < 0
9282 || ((unsigned long) imm_expr.X_add_number
9284 || ((unsigned long) imm_expr.X_add_number
9287 as_bad (_("Improper insert size (%lu, position %lu)"),
9288 (unsigned long) imm_expr.X_add_number,
9289 (unsigned long) lastpos);
9290 imm_expr.X_add_number = limlo - lastpos;
9292 INSERT_OPERAND (INSMSB, *ip,
9293 lastpos + imm_expr.X_add_number - 1);
9294 imm_expr.X_op = O_absent;
9298 case 'C': /* ext size, becomes MSBD. */
9311 my_getExpression (&imm_expr, s);
9312 check_absolute_expr (ip, &imm_expr);
9313 /* Check for negative input so that small negative numbers
9314 will not succeed incorrectly. The checks against
9315 (pos+size) transitively check "size" itself,
9316 assuming that "pos" is reasonable. */
9317 if ((long) imm_expr.X_add_number < 0
9318 || ((unsigned long) imm_expr.X_add_number
9320 || ((unsigned long) imm_expr.X_add_number
9323 as_bad (_("Improper extract size (%lu, position %lu)"),
9324 (unsigned long) imm_expr.X_add_number,
9325 (unsigned long) lastpos);
9326 imm_expr.X_add_number = limlo - lastpos;
9328 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9329 imm_expr.X_op = O_absent;
9334 /* +D is for disassembly only; never match. */
9338 /* "+I" is like "I", except that imm2_expr is used. */
9339 my_getExpression (&imm2_expr, s);
9340 if (imm2_expr.X_op != O_big
9341 && imm2_expr.X_op != O_constant)
9342 insn_error = _("absolute expression required");
9343 if (HAVE_32BIT_GPRS)
9344 normalize_constant_expr (&imm2_expr);
9348 case 'T': /* Coprocessor register. */
9349 /* +T is for disassembly only; never match. */
9352 case 't': /* Coprocessor register number. */
9353 if (s[0] == '$' && ISDIGIT (s[1]))
9363 while (ISDIGIT (*s));
9365 as_bad (_("Invalid register number (%d)"), regno);
9368 INSERT_OPERAND (RT, *ip, regno);
9373 as_bad (_("Invalid coprocessor 0 register number"));
9377 /* bbit[01] and bbit[01]32 bit index. Give error if index
9378 is not in the valid range. */
9379 my_getExpression (&imm_expr, s);
9380 check_absolute_expr (ip, &imm_expr);
9381 if ((unsigned) imm_expr.X_add_number > 31)
9383 as_bad (_("Improper bit index (%lu)"),
9384 (unsigned long) imm_expr.X_add_number);
9385 imm_expr.X_add_number = 0;
9387 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9388 imm_expr.X_op = O_absent;
9393 /* bbit[01] bit index when bbit is used but we generate
9394 bbit[01]32 because the index is over 32. Move to the
9395 next candidate if index is not in the valid range. */
9396 my_getExpression (&imm_expr, s);
9397 check_absolute_expr (ip, &imm_expr);
9398 if ((unsigned) imm_expr.X_add_number < 32
9399 || (unsigned) imm_expr.X_add_number > 63)
9401 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9402 imm_expr.X_op = O_absent;
9407 /* cins, cins32, exts and exts32 position field. Give error
9408 if it's not in the valid range. */
9409 my_getExpression (&imm_expr, s);
9410 check_absolute_expr (ip, &imm_expr);
9411 if ((unsigned) imm_expr.X_add_number > 31)
9413 as_bad (_("Improper position (%lu)"),
9414 (unsigned long) imm_expr.X_add_number);
9415 imm_expr.X_add_number = 0;
9417 /* Make the pos explicit to simplify +S. */
9418 lastpos = imm_expr.X_add_number + 32;
9419 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9420 imm_expr.X_op = O_absent;
9425 /* cins, cins32, exts and exts32 position field. Move to
9426 the next candidate if it's not in the valid range. */
9427 my_getExpression (&imm_expr, s);
9428 check_absolute_expr (ip, &imm_expr);
9429 if ((unsigned) imm_expr.X_add_number < 32
9430 || (unsigned) imm_expr.X_add_number > 63)
9432 lastpos = imm_expr.X_add_number;
9433 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9434 imm_expr.X_op = O_absent;
9439 /* cins and exts length-minus-one field. */
9440 my_getExpression (&imm_expr, s);
9441 check_absolute_expr (ip, &imm_expr);
9442 if ((unsigned long) imm_expr.X_add_number > 31)
9444 as_bad (_("Improper size (%lu)"),
9445 (unsigned long) imm_expr.X_add_number);
9446 imm_expr.X_add_number = 0;
9448 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9449 imm_expr.X_op = O_absent;
9454 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9455 length-minus-one field. */
9456 my_getExpression (&imm_expr, s);
9457 check_absolute_expr (ip, &imm_expr);
9458 if ((long) imm_expr.X_add_number < 0
9459 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9461 as_bad (_("Improper size (%lu)"),
9462 (unsigned long) imm_expr.X_add_number);
9463 imm_expr.X_add_number = 0;
9465 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9466 imm_expr.X_op = O_absent;
9471 /* seqi/snei immediate field. */
9472 my_getExpression (&imm_expr, s);
9473 check_absolute_expr (ip, &imm_expr);
9474 if ((long) imm_expr.X_add_number < -512
9475 || (long) imm_expr.X_add_number >= 512)
9477 as_bad (_("Improper immediate (%ld)"),
9478 (long) imm_expr.X_add_number);
9479 imm_expr.X_add_number = 0;
9481 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9482 imm_expr.X_op = O_absent;
9486 case 'a': /* 8-bit signed offset in bit 6 */
9487 my_getExpression (&imm_expr, s);
9488 check_absolute_expr (ip, &imm_expr);
9489 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9490 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9491 if (imm_expr.X_add_number < min_range
9492 || imm_expr.X_add_number > max_range)
9494 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9495 (long) min_range, (long) max_range,
9496 (long) imm_expr.X_add_number);
9498 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9499 imm_expr.X_op = O_absent;
9503 case 'b': /* 8-bit signed offset in bit 3 */
9504 my_getExpression (&imm_expr, s);
9505 check_absolute_expr (ip, &imm_expr);
9506 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9507 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9508 if (imm_expr.X_add_number < min_range
9509 || imm_expr.X_add_number > max_range)
9511 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9512 (long) min_range, (long) max_range,
9513 (long) imm_expr.X_add_number);
9515 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9516 imm_expr.X_op = O_absent;
9520 case 'c': /* 9-bit signed offset in bit 6 */
9521 my_getExpression (&imm_expr, s);
9522 check_absolute_expr (ip, &imm_expr);
9523 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9524 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9525 /* We check the offset range before adjusted. */
9528 if (imm_expr.X_add_number < min_range
9529 || imm_expr.X_add_number > max_range)
9531 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9532 (long) min_range, (long) max_range,
9533 (long) imm_expr.X_add_number);
9535 if (imm_expr.X_add_number & 0xf)
9537 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9538 (long) imm_expr.X_add_number);
9540 /* Right shift 4 bits to adjust the offset operand. */
9541 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9542 imm_expr.X_op = O_absent;
9547 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9549 if (regno == AT && mips_opts.at)
9551 if (mips_opts.at == ATREG)
9552 as_warn (_("used $at without \".set noat\""));
9554 as_warn (_("used $%u with \".set at=$%u\""),
9555 regno, mips_opts.at);
9557 INSERT_OPERAND (RZ, *ip, regno);
9561 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9563 INSERT_OPERAND (FZ, *ip, regno);
9567 as_bad (_("Internal error: bad mips opcode "
9568 "(unknown extension operand type `+%c'): %s %s"),
9569 *args, insn->name, insn->args);
9570 /* Further processing is fruitless. */
9575 case '<': /* must be at least one digit */
9577 * According to the manual, if the shift amount is greater
9578 * than 31 or less than 0, then the shift amount should be
9579 * mod 32. In reality the mips assembler issues an error.
9580 * We issue a warning and mask out all but the low 5 bits.
9582 my_getExpression (&imm_expr, s);
9583 check_absolute_expr (ip, &imm_expr);
9584 if ((unsigned long) imm_expr.X_add_number > 31)
9585 as_warn (_("Improper shift amount (%lu)"),
9586 (unsigned long) imm_expr.X_add_number);
9587 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9588 imm_expr.X_op = O_absent;
9592 case '>': /* shift amount minus 32 */
9593 my_getExpression (&imm_expr, s);
9594 check_absolute_expr (ip, &imm_expr);
9595 if ((unsigned long) imm_expr.X_add_number < 32
9596 || (unsigned long) imm_expr.X_add_number > 63)
9598 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9599 imm_expr.X_op = O_absent;
9603 case 'k': /* CACHE code. */
9604 case 'h': /* PREFX code. */
9605 case '1': /* SYNC type. */
9606 my_getExpression (&imm_expr, s);
9607 check_absolute_expr (ip, &imm_expr);
9608 if ((unsigned long) imm_expr.X_add_number > 31)
9609 as_warn (_("Invalid value for `%s' (%lu)"),
9611 (unsigned long) imm_expr.X_add_number);
9614 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9615 switch (imm_expr.X_add_number)
9624 case 31: /* These are ok. */
9627 default: /* The rest must be changed to 28. */
9628 imm_expr.X_add_number = 28;
9631 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9633 else if (*args == 'h')
9634 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9636 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9637 imm_expr.X_op = O_absent;
9641 case 'c': /* BREAK code. */
9642 my_getExpression (&imm_expr, s);
9643 check_absolute_expr (ip, &imm_expr);
9644 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9645 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9647 (unsigned long) imm_expr.X_add_number);
9648 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9649 imm_expr.X_op = O_absent;
9653 case 'q': /* Lower BREAK code. */
9654 my_getExpression (&imm_expr, s);
9655 check_absolute_expr (ip, &imm_expr);
9656 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9657 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9659 (unsigned long) imm_expr.X_add_number);
9660 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9661 imm_expr.X_op = O_absent;
9665 case 'B': /* 20-bit SYSCALL/BREAK code. */
9666 my_getExpression (&imm_expr, s);
9667 check_absolute_expr (ip, &imm_expr);
9668 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9669 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9671 (unsigned long) imm_expr.X_add_number);
9672 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9673 imm_expr.X_op = O_absent;
9677 case 'C': /* Coprocessor code. */
9678 my_getExpression (&imm_expr, s);
9679 check_absolute_expr (ip, &imm_expr);
9680 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9682 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9683 (unsigned long) imm_expr.X_add_number);
9684 imm_expr.X_add_number &= OP_MASK_COPZ;
9686 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9687 imm_expr.X_op = O_absent;
9691 case 'J': /* 19-bit WAIT code. */
9692 my_getExpression (&imm_expr, s);
9693 check_absolute_expr (ip, &imm_expr);
9694 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9696 as_warn (_("Illegal 19-bit code (%lu)"),
9697 (unsigned long) imm_expr.X_add_number);
9698 imm_expr.X_add_number &= OP_MASK_CODE19;
9700 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9701 imm_expr.X_op = O_absent;
9705 case 'P': /* Performance register. */
9706 my_getExpression (&imm_expr, s);
9707 check_absolute_expr (ip, &imm_expr);
9708 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9709 as_warn (_("Invalid performance register (%lu)"),
9710 (unsigned long) imm_expr.X_add_number);
9711 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9712 imm_expr.X_op = O_absent;
9716 case 'G': /* Coprocessor destination register. */
9717 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9718 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9720 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9721 INSERT_OPERAND (RD, *ip, regno);
9730 case 'b': /* Base register. */
9731 case 'd': /* Destination register. */
9732 case 's': /* Source register. */
9733 case 't': /* Target register. */
9734 case 'r': /* Both target and source. */
9735 case 'v': /* Both dest and source. */
9736 case 'w': /* Both dest and target. */
9737 case 'E': /* Coprocessor target register. */
9738 case 'K': /* RDHWR destination register. */
9739 case 'x': /* Ignore register name. */
9740 case 'z': /* Must be zero register. */
9741 case 'U': /* Destination register (CLO/CLZ). */
9742 case 'g': /* Coprocessor destination register. */
9744 if (*args == 'E' || *args == 'K')
9745 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9748 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9749 if (regno == AT && mips_opts.at)
9751 if (mips_opts.at == ATREG)
9752 as_warn (_("Used $at without \".set noat\""));
9754 as_warn (_("Used $%u with \".set at=$%u\""),
9755 regno, mips_opts.at);
9765 if (c == 'r' || c == 'v' || c == 'w')
9772 /* 'z' only matches $0. */
9773 if (c == 'z' && regno != 0)
9776 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9778 if (regno == lastregno)
9781 = _("Source and destination must be different");
9784 if (regno == 31 && lastregno == 0xffffffff)
9787 = _("A destination register must be supplied");
9791 /* Now that we have assembled one operand, we use the args
9792 string to figure out where it goes in the instruction. */
9799 INSERT_OPERAND (RS, *ip, regno);
9804 INSERT_OPERAND (RD, *ip, regno);
9807 INSERT_OPERAND (RD, *ip, regno);
9808 INSERT_OPERAND (RT, *ip, regno);
9813 INSERT_OPERAND (RT, *ip, regno);
9816 /* This case exists because on the r3000 trunc
9817 expands into a macro which requires a gp
9818 register. On the r6000 or r4000 it is
9819 assembled into a single instruction which
9820 ignores the register. Thus the insn version
9821 is MIPS_ISA2 and uses 'x', and the macro
9822 version is MIPS_ISA1 and uses 't'. */
9825 /* This case is for the div instruction, which
9826 acts differently if the destination argument
9827 is $0. This only matches $0, and is checked
9828 outside the switch. */
9838 INSERT_OPERAND (RS, *ip, lastregno);
9841 INSERT_OPERAND (RT, *ip, lastregno);
9846 case 'O': /* MDMX alignment immediate constant. */
9847 my_getExpression (&imm_expr, s);
9848 check_absolute_expr (ip, &imm_expr);
9849 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9850 as_warn (_("Improper align amount (%ld), using low bits"),
9851 (long) imm_expr.X_add_number);
9852 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9853 imm_expr.X_op = O_absent;
9857 case 'Q': /* MDMX vector, element sel, or const. */
9860 /* MDMX Immediate. */
9861 my_getExpression (&imm_expr, s);
9862 check_absolute_expr (ip, &imm_expr);
9863 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9864 as_warn (_("Invalid MDMX Immediate (%ld)"),
9865 (long) imm_expr.X_add_number);
9866 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9867 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9868 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9870 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9871 imm_expr.X_op = O_absent;
9875 /* Not MDMX Immediate. Fall through. */
9876 case 'X': /* MDMX destination register. */
9877 case 'Y': /* MDMX source register. */
9878 case 'Z': /* MDMX target register. */
9880 case 'D': /* Floating point destination register. */
9881 case 'S': /* Floating point source register. */
9882 case 'T': /* Floating point target register. */
9883 case 'R': /* Floating point source register. */
9888 || (mips_opts.ase_mdmx
9889 && (ip->insn_mo->pinfo & FP_D)
9890 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9891 | INSN_COPROC_MEMORY_DELAY
9892 | INSN_LOAD_COPROC_DELAY
9893 | INSN_LOAD_MEMORY_DELAY
9894 | INSN_STORE_MEMORY))))
9897 if (reg_lookup (&s, rtype, ®no))
9899 if ((regno & 1) != 0
9901 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9902 as_warn (_("Float register should be even, was %d"),
9910 if (c == 'V' || c == 'W')
9921 INSERT_OPERAND (FD, *ip, regno);
9926 INSERT_OPERAND (FS, *ip, regno);
9929 /* This is like 'Z', but also needs to fix the MDMX
9930 vector/scalar select bits. Note that the
9931 scalar immediate case is handled above. */
9934 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9935 int max_el = (is_qh ? 3 : 7);
9937 my_getExpression(&imm_expr, s);
9938 check_absolute_expr (ip, &imm_expr);
9940 if (imm_expr.X_add_number > max_el)
9941 as_bad (_("Bad element selector %ld"),
9942 (long) imm_expr.X_add_number);
9943 imm_expr.X_add_number &= max_el;
9944 ip->insn_opcode |= (imm_expr.X_add_number
9947 imm_expr.X_op = O_absent;
9949 as_warn (_("Expecting ']' found '%s'"), s);
9955 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9956 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9959 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9966 INSERT_OPERAND (FT, *ip, regno);
9969 INSERT_OPERAND (FR, *ip, regno);
9979 INSERT_OPERAND (FS, *ip, lastregno);
9982 INSERT_OPERAND (FT, *ip, lastregno);
9988 my_getExpression (&imm_expr, s);
9989 if (imm_expr.X_op != O_big
9990 && imm_expr.X_op != O_constant)
9991 insn_error = _("absolute expression required");
9992 if (HAVE_32BIT_GPRS)
9993 normalize_constant_expr (&imm_expr);
9998 my_getExpression (&offset_expr, s);
9999 normalize_address_expr (&offset_expr);
10000 *imm_reloc = BFD_RELOC_32;
10013 unsigned char temp[8];
10015 unsigned int length;
10020 /* These only appear as the last operand in an
10021 instruction, and every instruction that accepts
10022 them in any variant accepts them in all variants.
10023 This means we don't have to worry about backing out
10024 any changes if the instruction does not match.
10026 The difference between them is the size of the
10027 floating point constant and where it goes. For 'F'
10028 and 'L' the constant is 64 bits; for 'f' and 'l' it
10029 is 32 bits. Where the constant is placed is based
10030 on how the MIPS assembler does things:
10033 f -- immediate value
10036 The .lit4 and .lit8 sections are only used if
10037 permitted by the -G argument.
10039 The code below needs to know whether the target register
10040 is 32 or 64 bits wide. It relies on the fact 'f' and
10041 'F' are used with GPR-based instructions and 'l' and
10042 'L' are used with FPR-based instructions. */
10044 f64 = *args == 'F' || *args == 'L';
10045 using_gprs = *args == 'F' || *args == 'f';
10047 save_in = input_line_pointer;
10048 input_line_pointer = s;
10049 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10051 s = input_line_pointer;
10052 input_line_pointer = save_in;
10053 if (err != NULL && *err != '\0')
10055 as_bad (_("Bad floating point constant: %s"), err);
10056 memset (temp, '\0', sizeof temp);
10057 length = f64 ? 8 : 4;
10060 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10064 && (g_switch_value < 4
10065 || (temp[0] == 0 && temp[1] == 0)
10066 || (temp[2] == 0 && temp[3] == 0))))
10068 imm_expr.X_op = O_constant;
10069 if (!target_big_endian)
10070 imm_expr.X_add_number = bfd_getl32 (temp);
10072 imm_expr.X_add_number = bfd_getb32 (temp);
10074 else if (length > 4
10075 && !mips_disable_float_construction
10076 /* Constants can only be constructed in GPRs and
10077 copied to FPRs if the GPRs are at least as wide
10078 as the FPRs. Force the constant into memory if
10079 we are using 64-bit FPRs but the GPRs are only
10082 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10083 && ((temp[0] == 0 && temp[1] == 0)
10084 || (temp[2] == 0 && temp[3] == 0))
10085 && ((temp[4] == 0 && temp[5] == 0)
10086 || (temp[6] == 0 && temp[7] == 0)))
10088 /* The value is simple enough to load with a couple of
10089 instructions. If using 32-bit registers, set
10090 imm_expr to the high order 32 bits and offset_expr to
10091 the low order 32 bits. Otherwise, set imm_expr to
10092 the entire 64 bit constant. */
10093 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10095 imm_expr.X_op = O_constant;
10096 offset_expr.X_op = O_constant;
10097 if (!target_big_endian)
10099 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10100 offset_expr.X_add_number = bfd_getl32 (temp);
10104 imm_expr.X_add_number = bfd_getb32 (temp);
10105 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10107 if (offset_expr.X_add_number == 0)
10108 offset_expr.X_op = O_absent;
10110 else if (sizeof (imm_expr.X_add_number) > 4)
10112 imm_expr.X_op = O_constant;
10113 if (!target_big_endian)
10114 imm_expr.X_add_number = bfd_getl64 (temp);
10116 imm_expr.X_add_number = bfd_getb64 (temp);
10120 imm_expr.X_op = O_big;
10121 imm_expr.X_add_number = 4;
10122 if (!target_big_endian)
10124 generic_bignum[0] = bfd_getl16 (temp);
10125 generic_bignum[1] = bfd_getl16 (temp + 2);
10126 generic_bignum[2] = bfd_getl16 (temp + 4);
10127 generic_bignum[3] = bfd_getl16 (temp + 6);
10131 generic_bignum[0] = bfd_getb16 (temp + 6);
10132 generic_bignum[1] = bfd_getb16 (temp + 4);
10133 generic_bignum[2] = bfd_getb16 (temp + 2);
10134 generic_bignum[3] = bfd_getb16 (temp);
10140 const char *newname;
10143 /* Switch to the right section. */
10145 subseg = now_subseg;
10148 default: /* unused default case avoids warnings. */
10150 newname = RDATA_SECTION_NAME;
10151 if (g_switch_value >= 8)
10155 newname = RDATA_SECTION_NAME;
10158 gas_assert (g_switch_value >= 4);
10162 new_seg = subseg_new (newname, (subsegT) 0);
10164 bfd_set_section_flags (stdoutput, new_seg,
10169 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10170 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10171 record_alignment (new_seg, 4);
10173 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10174 if (seg == now_seg)
10175 as_bad (_("Can't use floating point insn in this section"));
10177 /* Set the argument to the current address in the
10179 offset_expr.X_op = O_symbol;
10180 offset_expr.X_add_symbol = symbol_temp_new_now ();
10181 offset_expr.X_add_number = 0;
10183 /* Put the floating point number into the section. */
10184 p = frag_more ((int) length);
10185 memcpy (p, temp, length);
10187 /* Switch back to the original section. */
10188 subseg_set (seg, subseg);
10193 case 'i': /* 16-bit unsigned immediate. */
10194 case 'j': /* 16-bit signed immediate. */
10195 *imm_reloc = BFD_RELOC_LO16;
10196 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10199 offsetT minval, maxval;
10201 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10202 && strcmp (insn->name, insn[1].name) == 0);
10204 /* If the expression was written as an unsigned number,
10205 only treat it as signed if there are no more
10209 && sizeof (imm_expr.X_add_number) <= 4
10210 && imm_expr.X_op == O_constant
10211 && imm_expr.X_add_number < 0
10212 && imm_expr.X_unsigned
10213 && HAVE_64BIT_GPRS)
10216 /* For compatibility with older assemblers, we accept
10217 0x8000-0xffff as signed 16-bit numbers when only
10218 signed numbers are allowed. */
10220 minval = 0, maxval = 0xffff;
10222 minval = -0x8000, maxval = 0x7fff;
10224 minval = -0x8000, maxval = 0xffff;
10226 if (imm_expr.X_op != O_constant
10227 || imm_expr.X_add_number < minval
10228 || imm_expr.X_add_number > maxval)
10232 if (imm_expr.X_op == O_constant
10233 || imm_expr.X_op == O_big)
10234 as_bad (_("Expression out of range"));
10240 case 'o': /* 16-bit offset. */
10241 offset_reloc[0] = BFD_RELOC_LO16;
10242 offset_reloc[1] = BFD_RELOC_UNUSED;
10243 offset_reloc[2] = BFD_RELOC_UNUSED;
10245 /* Check whether there is only a single bracketed expression
10246 left. If so, it must be the base register and the
10247 constant must be zero. */
10248 if (*s == '(' && strchr (s + 1, '(') == 0)
10250 offset_expr.X_op = O_constant;
10251 offset_expr.X_add_number = 0;
10255 /* If this value won't fit into a 16 bit offset, then go
10256 find a macro that will generate the 32 bit offset
10258 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10259 && (offset_expr.X_op != O_constant
10260 || offset_expr.X_add_number >= 0x8000
10261 || offset_expr.X_add_number < -0x8000))
10267 case 'p': /* PC-relative offset. */
10268 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10269 my_getExpression (&offset_expr, s);
10273 case 'u': /* Upper 16 bits. */
10274 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10275 && imm_expr.X_op == O_constant
10276 && (imm_expr.X_add_number < 0
10277 || imm_expr.X_add_number >= 0x10000))
10278 as_bad (_("lui expression (%lu) not in range 0..65535"),
10279 (unsigned long) imm_expr.X_add_number);
10283 case 'a': /* 26-bit address. */
10284 my_getExpression (&offset_expr, s);
10286 *offset_reloc = BFD_RELOC_MIPS_JMP;
10289 case 'N': /* 3-bit branch condition code. */
10290 case 'M': /* 3-bit compare condition code. */
10292 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10293 rtype |= RTYPE_FCC;
10294 if (!reg_lookup (&s, rtype, ®no))
10296 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10297 || strcmp (str + strlen (str) - 5, "any2f") == 0
10298 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10299 && (regno & 1) != 0)
10300 as_warn (_("Condition code register should be even for %s, "
10303 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10304 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10305 && (regno & 3) != 0)
10306 as_warn (_("Condition code register should be 0 or 4 for %s, "
10310 INSERT_OPERAND (BCC, *ip, regno);
10312 INSERT_OPERAND (CCC, *ip, regno);
10316 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10327 while (ISDIGIT (*s));
10330 c = 8; /* Invalid sel value. */
10333 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10334 ip->insn_opcode |= c;
10338 /* Must be at least one digit. */
10339 my_getExpression (&imm_expr, s);
10340 check_absolute_expr (ip, &imm_expr);
10342 if ((unsigned long) imm_expr.X_add_number
10343 > (unsigned long) OP_MASK_VECBYTE)
10345 as_bad (_("bad byte vector index (%ld)"),
10346 (long) imm_expr.X_add_number);
10347 imm_expr.X_add_number = 0;
10350 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10351 imm_expr.X_op = O_absent;
10356 my_getExpression (&imm_expr, s);
10357 check_absolute_expr (ip, &imm_expr);
10359 if ((unsigned long) imm_expr.X_add_number
10360 > (unsigned long) OP_MASK_VECALIGN)
10362 as_bad (_("bad byte vector index (%ld)"),
10363 (long) imm_expr.X_add_number);
10364 imm_expr.X_add_number = 0;
10367 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10368 imm_expr.X_op = O_absent;
10373 as_bad (_("Bad char = '%c'\n"), *args);
10378 /* Args don't match. */
10379 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10380 !strcmp (insn->name, insn[1].name))
10384 insn_error = _("Illegal operands");
10388 *(--argsStart) = save_c;
10389 insn_error = _("Illegal operands");
10394 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10396 /* This routine assembles an instruction into its binary format when
10397 assembling for the mips16. As a side effect, it sets one of the
10398 global variables imm_reloc or offset_reloc to the type of
10399 relocation to do if one of the operands is an address expression.
10400 It also sets mips16_small and mips16_ext if the user explicitly
10401 requested a small or extended instruction. */
10404 mips16_ip (char *str, struct mips_cl_insn *ip)
10408 struct mips_opcode *insn;
10410 unsigned int regno;
10411 unsigned int lastregno = 0;
10417 mips16_small = FALSE;
10418 mips16_ext = FALSE;
10420 for (s = str; ISLOWER (*s); ++s)
10432 if (s[1] == 't' && s[2] == ' ')
10435 mips16_small = TRUE;
10439 else if (s[1] == 'e' && s[2] == ' ')
10446 /* Fall through. */
10448 insn_error = _("unknown opcode");
10452 if (mips_opts.noautoextend && ! mips16_ext)
10453 mips16_small = TRUE;
10455 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10457 insn_error = _("unrecognized opcode");
10466 gas_assert (strcmp (insn->name, str) == 0);
10468 ok = is_opcode_valid_16 (insn);
10471 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10472 && strcmp (insn->name, insn[1].name) == 0)
10481 static char buf[100];
10483 _("opcode not supported on this processor: %s (%s)"),
10484 mips_cpu_info_from_arch (mips_opts.arch)->name,
10485 mips_cpu_info_from_isa (mips_opts.isa)->name);
10492 create_insn (ip, insn);
10493 imm_expr.X_op = O_absent;
10494 imm_reloc[0] = BFD_RELOC_UNUSED;
10495 imm_reloc[1] = BFD_RELOC_UNUSED;
10496 imm_reloc[2] = BFD_RELOC_UNUSED;
10497 imm2_expr.X_op = O_absent;
10498 offset_expr.X_op = O_absent;
10499 offset_reloc[0] = BFD_RELOC_UNUSED;
10500 offset_reloc[1] = BFD_RELOC_UNUSED;
10501 offset_reloc[2] = BFD_RELOC_UNUSED;
10502 for (args = insn->args; 1; ++args)
10509 /* In this switch statement we call break if we did not find
10510 a match, continue if we did find a match, or return if we
10519 /* Stuff the immediate value in now, if we can. */
10520 if (imm_expr.X_op == O_constant
10521 && *imm_reloc > BFD_RELOC_UNUSED
10522 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10523 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10524 && insn->pinfo != INSN_MACRO)
10528 switch (*offset_reloc)
10530 case BFD_RELOC_MIPS16_HI16_S:
10531 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10534 case BFD_RELOC_MIPS16_HI16:
10535 tmp = imm_expr.X_add_number >> 16;
10538 case BFD_RELOC_MIPS16_LO16:
10539 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10543 case BFD_RELOC_UNUSED:
10544 tmp = imm_expr.X_add_number;
10550 *offset_reloc = BFD_RELOC_UNUSED;
10552 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10553 tmp, TRUE, mips16_small,
10554 mips16_ext, &ip->insn_opcode,
10555 &ip->use_extend, &ip->extend);
10556 imm_expr.X_op = O_absent;
10557 *imm_reloc = BFD_RELOC_UNUSED;
10571 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10574 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10590 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10592 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10596 /* Fall through. */
10607 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10609 if (c == 'v' || c == 'w')
10612 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10614 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10625 if (c == 'v' || c == 'w')
10627 regno = mips16_to_32_reg_map[lastregno];
10641 regno = mips32_to_16_reg_map[regno];
10646 regno = ILLEGAL_REG;
10651 regno = ILLEGAL_REG;
10656 regno = ILLEGAL_REG;
10661 if (regno == AT && mips_opts.at)
10663 if (mips_opts.at == ATREG)
10664 as_warn (_("used $at without \".set noat\""));
10666 as_warn (_("used $%u with \".set at=$%u\""),
10667 regno, mips_opts.at);
10675 if (regno == ILLEGAL_REG)
10682 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10686 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10689 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10692 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10698 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10701 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10702 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10712 if (strncmp (s, "$pc", 3) == 0)
10729 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10732 if (imm_expr.X_op != O_constant)
10735 ip->use_extend = TRUE;
10740 /* We need to relax this instruction. */
10741 *offset_reloc = *imm_reloc;
10742 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10747 *imm_reloc = BFD_RELOC_UNUSED;
10748 /* Fall through. */
10755 my_getExpression (&imm_expr, s);
10756 if (imm_expr.X_op == O_register)
10758 /* What we thought was an expression turned out to
10761 if (s[0] == '(' && args[1] == '(')
10763 /* It looks like the expression was omitted
10764 before a register indirection, which means
10765 that the expression is implicitly zero. We
10766 still set up imm_expr, so that we handle
10767 explicit extensions correctly. */
10768 imm_expr.X_op = O_constant;
10769 imm_expr.X_add_number = 0;
10770 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10777 /* We need to relax this instruction. */
10778 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10787 /* We use offset_reloc rather than imm_reloc for the PC
10788 relative operands. This lets macros with both
10789 immediate and address operands work correctly. */
10790 my_getExpression (&offset_expr, s);
10792 if (offset_expr.X_op == O_register)
10795 /* We need to relax this instruction. */
10796 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10800 case '6': /* break code */
10801 my_getExpression (&imm_expr, s);
10802 check_absolute_expr (ip, &imm_expr);
10803 if ((unsigned long) imm_expr.X_add_number > 63)
10804 as_warn (_("Invalid value for `%s' (%lu)"),
10806 (unsigned long) imm_expr.X_add_number);
10807 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10808 imm_expr.X_op = O_absent;
10812 case 'a': /* 26 bit address */
10813 my_getExpression (&offset_expr, s);
10815 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10816 ip->insn_opcode <<= 16;
10819 case 'l': /* register list for entry macro */
10820 case 'L': /* register list for exit macro */
10830 unsigned int freg, reg1, reg2;
10832 while (*s == ' ' || *s == ',')
10834 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10836 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10840 as_bad (_("can't parse register list"));
10850 if (!reg_lookup (&s, freg ? RTYPE_FPU
10851 : (RTYPE_GP | RTYPE_NUM), ®2))
10853 as_bad (_("invalid register list"));
10857 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10859 mask &= ~ (7 << 3);
10862 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10864 mask &= ~ (7 << 3);
10867 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10868 mask |= (reg2 - 3) << 3;
10869 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10870 mask |= (reg2 - 15) << 1;
10871 else if (reg1 == RA && reg2 == RA)
10875 as_bad (_("invalid register list"));
10879 /* The mask is filled in in the opcode table for the
10880 benefit of the disassembler. We remove it before
10881 applying the actual mask. */
10882 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10883 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10887 case 'm': /* Register list for save insn. */
10888 case 'M': /* Register list for restore insn. */
10891 int framesz = 0, seen_framesz = 0;
10892 int nargs = 0, statics = 0, sregs = 0;
10896 unsigned int reg1, reg2;
10898 SKIP_SPACE_TABS (s);
10901 SKIP_SPACE_TABS (s);
10903 my_getExpression (&imm_expr, s);
10904 if (imm_expr.X_op == O_constant)
10906 /* Handle the frame size. */
10909 as_bad (_("more than one frame size in list"));
10913 framesz = imm_expr.X_add_number;
10914 imm_expr.X_op = O_absent;
10919 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10921 as_bad (_("can't parse register list"));
10933 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10936 as_bad (_("can't parse register list"));
10941 while (reg1 <= reg2)
10943 if (reg1 >= 4 && reg1 <= 7)
10947 nargs |= 1 << (reg1 - 4);
10949 /* statics $a0-$a3 */
10950 statics |= 1 << (reg1 - 4);
10952 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10955 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10957 else if (reg1 == 31)
10959 /* Add $ra to insn. */
10964 as_bad (_("unexpected register in list"));
10972 /* Encode args/statics combination. */
10973 if (nargs & statics)
10974 as_bad (_("arg/static registers overlap"));
10975 else if (nargs == 0xf)
10976 /* All $a0-$a3 are args. */
10977 opcode |= MIPS16_ALL_ARGS << 16;
10978 else if (statics == 0xf)
10979 /* All $a0-$a3 are statics. */
10980 opcode |= MIPS16_ALL_STATICS << 16;
10983 int narg = 0, nstat = 0;
10985 /* Count arg registers. */
10986 while (nargs & 0x1)
10992 as_bad (_("invalid arg register list"));
10994 /* Count static registers. */
10995 while (statics & 0x8)
10997 statics = (statics << 1) & 0xf;
11001 as_bad (_("invalid static register list"));
11003 /* Encode args/statics. */
11004 opcode |= ((narg << 2) | nstat) << 16;
11007 /* Encode $s0/$s1. */
11008 if (sregs & (1 << 0)) /* $s0 */
11010 if (sregs & (1 << 1)) /* $s1 */
11016 /* Count regs $s2-$s8. */
11024 as_bad (_("invalid static register list"));
11025 /* Encode $s2-$s8. */
11026 opcode |= nsreg << 24;
11029 /* Encode frame size. */
11031 as_bad (_("missing frame size"));
11032 else if ((framesz & 7) != 0 || framesz < 0
11033 || framesz > 0xff * 8)
11034 as_bad (_("invalid frame size"));
11035 else if (framesz != 128 || (opcode >> 16) != 0)
11038 opcode |= (((framesz & 0xf0) << 16)
11039 | (framesz & 0x0f));
11042 /* Finally build the instruction. */
11043 if ((opcode >> 16) != 0 || framesz == 0)
11045 ip->use_extend = TRUE;
11046 ip->extend = opcode >> 16;
11048 ip->insn_opcode |= opcode & 0x7f;
11052 case 'e': /* extend code */
11053 my_getExpression (&imm_expr, s);
11054 check_absolute_expr (ip, &imm_expr);
11055 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11057 as_warn (_("Invalid value for `%s' (%lu)"),
11059 (unsigned long) imm_expr.X_add_number);
11060 imm_expr.X_add_number &= 0x7ff;
11062 ip->insn_opcode |= imm_expr.X_add_number;
11063 imm_expr.X_op = O_absent;
11073 /* Args don't match. */
11074 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11075 strcmp (insn->name, insn[1].name) == 0)
11082 insn_error = _("illegal operands");
11088 /* This structure holds information we know about a mips16 immediate
11091 struct mips16_immed_operand
11093 /* The type code used in the argument string in the opcode table. */
11095 /* The number of bits in the short form of the opcode. */
11097 /* The number of bits in the extended form of the opcode. */
11099 /* The amount by which the short form is shifted when it is used;
11100 for example, the sw instruction has a shift count of 2. */
11102 /* The amount by which the short form is shifted when it is stored
11103 into the instruction code. */
11105 /* Non-zero if the short form is unsigned. */
11107 /* Non-zero if the extended form is unsigned. */
11109 /* Non-zero if the value is PC relative. */
11113 /* The mips16 immediate operand types. */
11115 static const struct mips16_immed_operand mips16_immed_operands[] =
11117 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11118 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11119 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11120 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11121 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11122 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11123 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11124 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11125 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11126 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11127 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11128 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11129 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11130 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11131 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11132 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11133 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11134 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11135 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11136 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11137 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11140 #define MIPS16_NUM_IMMED \
11141 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11143 /* Handle a mips16 instruction with an immediate value. This or's the
11144 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11145 whether an extended value is needed; if one is needed, it sets
11146 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11147 If SMALL is true, an unextended opcode was explicitly requested.
11148 If EXT is true, an extended opcode was explicitly requested. If
11149 WARN is true, warn if EXT does not match reality. */
11152 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11153 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11154 unsigned long *insn, bfd_boolean *use_extend,
11155 unsigned short *extend)
11157 const struct mips16_immed_operand *op;
11158 int mintiny, maxtiny;
11159 bfd_boolean needext;
11161 op = mips16_immed_operands;
11162 while (op->type != type)
11165 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11170 if (type == '<' || type == '>' || type == '[' || type == ']')
11173 maxtiny = 1 << op->nbits;
11178 maxtiny = (1 << op->nbits) - 1;
11183 mintiny = - (1 << (op->nbits - 1));
11184 maxtiny = (1 << (op->nbits - 1)) - 1;
11187 /* Branch offsets have an implicit 0 in the lowest bit. */
11188 if (type == 'p' || type == 'q')
11191 if ((val & ((1 << op->shift) - 1)) != 0
11192 || val < (mintiny << op->shift)
11193 || val > (maxtiny << op->shift))
11198 if (warn && ext && ! needext)
11199 as_warn_where (file, line,
11200 _("extended operand requested but not required"));
11201 if (small && needext)
11202 as_bad_where (file, line, _("invalid unextended operand value"));
11204 if (small || (! ext && ! needext))
11208 *use_extend = FALSE;
11209 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11210 insnval <<= op->op_shift;
11215 long minext, maxext;
11221 maxext = (1 << op->extbits) - 1;
11225 minext = - (1 << (op->extbits - 1));
11226 maxext = (1 << (op->extbits - 1)) - 1;
11228 if (val < minext || val > maxext)
11229 as_bad_where (file, line,
11230 _("operand value out of range for instruction"));
11232 *use_extend = TRUE;
11233 if (op->extbits == 16)
11235 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11238 else if (op->extbits == 15)
11240 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11245 extval = ((val & 0x1f) << 6) | (val & 0x20);
11249 *extend = (unsigned short) extval;
11254 struct percent_op_match
11257 bfd_reloc_code_real_type reloc;
11260 static const struct percent_op_match mips_percent_op[] =
11262 {"%lo", BFD_RELOC_LO16},
11264 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11265 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11266 {"%call16", BFD_RELOC_MIPS_CALL16},
11267 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11268 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11269 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11270 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11271 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11272 {"%got", BFD_RELOC_MIPS_GOT16},
11273 {"%gp_rel", BFD_RELOC_GPREL16},
11274 {"%half", BFD_RELOC_16},
11275 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11276 {"%higher", BFD_RELOC_MIPS_HIGHER},
11277 {"%neg", BFD_RELOC_MIPS_SUB},
11278 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11279 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11280 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11281 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11282 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11283 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11284 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11286 {"%hi", BFD_RELOC_HI16_S}
11289 static const struct percent_op_match mips16_percent_op[] =
11291 {"%lo", BFD_RELOC_MIPS16_LO16},
11292 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11293 {"%got", BFD_RELOC_MIPS16_GOT16},
11294 {"%call16", BFD_RELOC_MIPS16_CALL16},
11295 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11299 /* Return true if *STR points to a relocation operator. When returning true,
11300 move *STR over the operator and store its relocation code in *RELOC.
11301 Leave both *STR and *RELOC alone when returning false. */
11304 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11306 const struct percent_op_match *percent_op;
11309 if (mips_opts.mips16)
11311 percent_op = mips16_percent_op;
11312 limit = ARRAY_SIZE (mips16_percent_op);
11316 percent_op = mips_percent_op;
11317 limit = ARRAY_SIZE (mips_percent_op);
11320 for (i = 0; i < limit; i++)
11321 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11323 int len = strlen (percent_op[i].str);
11325 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11328 *str += strlen (percent_op[i].str);
11329 *reloc = percent_op[i].reloc;
11331 /* Check whether the output BFD supports this relocation.
11332 If not, issue an error and fall back on something safe. */
11333 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11335 as_bad (_("relocation %s isn't supported by the current ABI"),
11336 percent_op[i].str);
11337 *reloc = BFD_RELOC_UNUSED;
11345 /* Parse string STR as a 16-bit relocatable operand. Store the
11346 expression in *EP and the relocations in the array starting
11347 at RELOC. Return the number of relocation operators used.
11349 On exit, EXPR_END points to the first character after the expression. */
11352 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11355 bfd_reloc_code_real_type reversed_reloc[3];
11356 size_t reloc_index, i;
11357 int crux_depth, str_depth;
11360 /* Search for the start of the main expression, recoding relocations
11361 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11362 of the main expression and with CRUX_DEPTH containing the number
11363 of open brackets at that point. */
11370 crux_depth = str_depth;
11372 /* Skip over whitespace and brackets, keeping count of the number
11374 while (*str == ' ' || *str == '\t' || *str == '(')
11379 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11380 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11382 my_getExpression (ep, crux);
11385 /* Match every open bracket. */
11386 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11390 if (crux_depth > 0)
11391 as_bad (_("unclosed '('"));
11395 if (reloc_index != 0)
11397 prev_reloc_op_frag = frag_now;
11398 for (i = 0; i < reloc_index; i++)
11399 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11402 return reloc_index;
11406 my_getExpression (expressionS *ep, char *str)
11410 save_in = input_line_pointer;
11411 input_line_pointer = str;
11413 expr_end = input_line_pointer;
11414 input_line_pointer = save_in;
11418 md_atof (int type, char *litP, int *sizeP)
11420 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11424 md_number_to_chars (char *buf, valueT val, int n)
11426 if (target_big_endian)
11427 number_to_chars_bigendian (buf, val, n);
11429 number_to_chars_littleendian (buf, val, n);
11433 static int support_64bit_objects(void)
11435 const char **list, **l;
11438 list = bfd_target_list ();
11439 for (l = list; *l != NULL; l++)
11440 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11441 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11443 yes = (*l != NULL);
11447 #endif /* OBJ_ELF */
11449 const char *md_shortopts = "O::g::G:";
11453 OPTION_MARCH = OPTION_MD_BASE,
11475 OPTION_NO_SMARTMIPS,
11478 OPTION_COMPAT_ARCH_BASE,
11487 OPTION_M7000_HILO_FIX,
11488 OPTION_MNO_7000_HILO_FIX,
11491 OPTION_FIX_LOONGSON2F_JUMP,
11492 OPTION_NO_FIX_LOONGSON2F_JUMP,
11493 OPTION_FIX_LOONGSON2F_NOP,
11494 OPTION_NO_FIX_LOONGSON2F_NOP,
11496 OPTION_NO_FIX_VR4120,
11498 OPTION_NO_FIX_VR4130,
11499 OPTION_FIX_CN63XXP1,
11500 OPTION_NO_FIX_CN63XXP1,
11507 OPTION_CONSTRUCT_FLOATS,
11508 OPTION_NO_CONSTRUCT_FLOATS,
11511 OPTION_RELAX_BRANCH,
11512 OPTION_NO_RELAX_BRANCH,
11519 OPTION_SINGLE_FLOAT,
11520 OPTION_DOUBLE_FLOAT,
11523 OPTION_CALL_SHARED,
11524 OPTION_CALL_NONPIC,
11534 OPTION_MVXWORKS_PIC,
11535 #endif /* OBJ_ELF */
11539 struct option md_longopts[] =
11541 /* Options which specify architecture. */
11542 {"march", required_argument, NULL, OPTION_MARCH},
11543 {"mtune", required_argument, NULL, OPTION_MTUNE},
11544 {"mips0", no_argument, NULL, OPTION_MIPS1},
11545 {"mips1", no_argument, NULL, OPTION_MIPS1},
11546 {"mips2", no_argument, NULL, OPTION_MIPS2},
11547 {"mips3", no_argument, NULL, OPTION_MIPS3},
11548 {"mips4", no_argument, NULL, OPTION_MIPS4},
11549 {"mips5", no_argument, NULL, OPTION_MIPS5},
11550 {"mips32", no_argument, NULL, OPTION_MIPS32},
11551 {"mips64", no_argument, NULL, OPTION_MIPS64},
11552 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11553 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11555 /* Options which specify Application Specific Extensions (ASEs). */
11556 {"mips16", no_argument, NULL, OPTION_MIPS16},
11557 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11558 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11559 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11560 {"mdmx", no_argument, NULL, OPTION_MDMX},
11561 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11562 {"mdsp", no_argument, NULL, OPTION_DSP},
11563 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11564 {"mmt", no_argument, NULL, OPTION_MT},
11565 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11566 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11567 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11568 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11569 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11571 /* Old-style architecture options. Don't add more of these. */
11572 {"m4650", no_argument, NULL, OPTION_M4650},
11573 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11574 {"m4010", no_argument, NULL, OPTION_M4010},
11575 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11576 {"m4100", no_argument, NULL, OPTION_M4100},
11577 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11578 {"m3900", no_argument, NULL, OPTION_M3900},
11579 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11581 /* Options which enable bug fixes. */
11582 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11583 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11584 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11585 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11586 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11587 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11588 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11589 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11590 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11591 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11592 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11593 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11594 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11595 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11596 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11598 /* Miscellaneous options. */
11599 {"trap", no_argument, NULL, OPTION_TRAP},
11600 {"no-break", no_argument, NULL, OPTION_TRAP},
11601 {"break", no_argument, NULL, OPTION_BREAK},
11602 {"no-trap", no_argument, NULL, OPTION_BREAK},
11603 {"EB", no_argument, NULL, OPTION_EB},
11604 {"EL", no_argument, NULL, OPTION_EL},
11605 {"mfp32", no_argument, NULL, OPTION_FP32},
11606 {"mgp32", no_argument, NULL, OPTION_GP32},
11607 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11608 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11609 {"mfp64", no_argument, NULL, OPTION_FP64},
11610 {"mgp64", no_argument, NULL, OPTION_GP64},
11611 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11612 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11613 {"mshared", no_argument, NULL, OPTION_MSHARED},
11614 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11615 {"msym32", no_argument, NULL, OPTION_MSYM32},
11616 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11617 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11618 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11619 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11620 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11622 /* Strictly speaking this next option is ELF specific,
11623 but we allow it for other ports as well in order to
11624 make testing easier. */
11625 {"32", no_argument, NULL, OPTION_32},
11627 /* ELF-specific options. */
11629 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11630 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11631 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11632 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11633 {"xgot", no_argument, NULL, OPTION_XGOT},
11634 {"mabi", required_argument, NULL, OPTION_MABI},
11635 {"n32", no_argument, NULL, OPTION_N32},
11636 {"64", no_argument, NULL, OPTION_64},
11637 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11638 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11639 {"mpdr", no_argument, NULL, OPTION_PDR},
11640 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11641 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11642 #endif /* OBJ_ELF */
11644 {NULL, no_argument, NULL, 0}
11646 size_t md_longopts_size = sizeof (md_longopts);
11648 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11649 NEW_VALUE. Warn if another value was already specified. Note:
11650 we have to defer parsing the -march and -mtune arguments in order
11651 to handle 'from-abi' correctly, since the ABI might be specified
11652 in a later argument. */
11655 mips_set_option_string (const char **string_ptr, const char *new_value)
11657 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11658 as_warn (_("A different %s was already specified, is now %s"),
11659 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11662 *string_ptr = new_value;
11666 md_parse_option (int c, char *arg)
11670 case OPTION_CONSTRUCT_FLOATS:
11671 mips_disable_float_construction = 0;
11674 case OPTION_NO_CONSTRUCT_FLOATS:
11675 mips_disable_float_construction = 1;
11687 target_big_endian = 1;
11691 target_big_endian = 0;
11697 else if (arg[0] == '0')
11699 else if (arg[0] == '1')
11709 mips_debug = atoi (arg);
11713 file_mips_isa = ISA_MIPS1;
11717 file_mips_isa = ISA_MIPS2;
11721 file_mips_isa = ISA_MIPS3;
11725 file_mips_isa = ISA_MIPS4;
11729 file_mips_isa = ISA_MIPS5;
11732 case OPTION_MIPS32:
11733 file_mips_isa = ISA_MIPS32;
11736 case OPTION_MIPS32R2:
11737 file_mips_isa = ISA_MIPS32R2;
11740 case OPTION_MIPS64R2:
11741 file_mips_isa = ISA_MIPS64R2;
11744 case OPTION_MIPS64:
11745 file_mips_isa = ISA_MIPS64;
11749 mips_set_option_string (&mips_tune_string, arg);
11753 mips_set_option_string (&mips_arch_string, arg);
11757 mips_set_option_string (&mips_arch_string, "4650");
11758 mips_set_option_string (&mips_tune_string, "4650");
11761 case OPTION_NO_M4650:
11765 mips_set_option_string (&mips_arch_string, "4010");
11766 mips_set_option_string (&mips_tune_string, "4010");
11769 case OPTION_NO_M4010:
11773 mips_set_option_string (&mips_arch_string, "4100");
11774 mips_set_option_string (&mips_tune_string, "4100");
11777 case OPTION_NO_M4100:
11781 mips_set_option_string (&mips_arch_string, "3900");
11782 mips_set_option_string (&mips_tune_string, "3900");
11785 case OPTION_NO_M3900:
11789 mips_opts.ase_mdmx = 1;
11792 case OPTION_NO_MDMX:
11793 mips_opts.ase_mdmx = 0;
11797 mips_opts.ase_dsp = 1;
11798 mips_opts.ase_dspr2 = 0;
11801 case OPTION_NO_DSP:
11802 mips_opts.ase_dsp = 0;
11803 mips_opts.ase_dspr2 = 0;
11807 mips_opts.ase_dspr2 = 1;
11808 mips_opts.ase_dsp = 1;
11811 case OPTION_NO_DSPR2:
11812 mips_opts.ase_dspr2 = 0;
11813 mips_opts.ase_dsp = 0;
11817 mips_opts.ase_mt = 1;
11821 mips_opts.ase_mt = 0;
11824 case OPTION_MIPS16:
11825 mips_opts.mips16 = 1;
11826 mips_no_prev_insn ();
11829 case OPTION_NO_MIPS16:
11830 mips_opts.mips16 = 0;
11831 mips_no_prev_insn ();
11834 case OPTION_MIPS3D:
11835 mips_opts.ase_mips3d = 1;
11838 case OPTION_NO_MIPS3D:
11839 mips_opts.ase_mips3d = 0;
11842 case OPTION_SMARTMIPS:
11843 mips_opts.ase_smartmips = 1;
11846 case OPTION_NO_SMARTMIPS:
11847 mips_opts.ase_smartmips = 0;
11850 case OPTION_FIX_24K:
11854 case OPTION_NO_FIX_24K:
11858 case OPTION_FIX_LOONGSON2F_JUMP:
11859 mips_fix_loongson2f_jump = TRUE;
11862 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11863 mips_fix_loongson2f_jump = FALSE;
11866 case OPTION_FIX_LOONGSON2F_NOP:
11867 mips_fix_loongson2f_nop = TRUE;
11870 case OPTION_NO_FIX_LOONGSON2F_NOP:
11871 mips_fix_loongson2f_nop = FALSE;
11874 case OPTION_FIX_VR4120:
11875 mips_fix_vr4120 = 1;
11878 case OPTION_NO_FIX_VR4120:
11879 mips_fix_vr4120 = 0;
11882 case OPTION_FIX_VR4130:
11883 mips_fix_vr4130 = 1;
11886 case OPTION_NO_FIX_VR4130:
11887 mips_fix_vr4130 = 0;
11890 case OPTION_FIX_CN63XXP1:
11891 mips_fix_cn63xxp1 = TRUE;
11894 case OPTION_NO_FIX_CN63XXP1:
11895 mips_fix_cn63xxp1 = FALSE;
11898 case OPTION_RELAX_BRANCH:
11899 mips_relax_branch = 1;
11902 case OPTION_NO_RELAX_BRANCH:
11903 mips_relax_branch = 0;
11906 case OPTION_MSHARED:
11907 mips_in_shared = TRUE;
11910 case OPTION_MNO_SHARED:
11911 mips_in_shared = FALSE;
11914 case OPTION_MSYM32:
11915 mips_opts.sym32 = TRUE;
11918 case OPTION_MNO_SYM32:
11919 mips_opts.sym32 = FALSE;
11923 /* When generating ELF code, we permit -KPIC and -call_shared to
11924 select SVR4_PIC, and -non_shared to select no PIC. This is
11925 intended to be compatible with Irix 5. */
11926 case OPTION_CALL_SHARED:
11929 as_bad (_("-call_shared is supported only for ELF format"));
11932 mips_pic = SVR4_PIC;
11933 mips_abicalls = TRUE;
11936 case OPTION_CALL_NONPIC:
11939 as_bad (_("-call_nonpic is supported only for ELF format"));
11943 mips_abicalls = TRUE;
11946 case OPTION_NON_SHARED:
11949 as_bad (_("-non_shared is supported only for ELF format"));
11953 mips_abicalls = FALSE;
11956 /* The -xgot option tells the assembler to use 32 bit offsets
11957 when accessing the got in SVR4_PIC mode. It is for Irix
11962 #endif /* OBJ_ELF */
11965 g_switch_value = atoi (arg);
11969 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11973 mips_abi = O32_ABI;
11974 /* We silently ignore -32 for non-ELF targets. This greatly
11975 simplifies the construction of the MIPS GAS test cases. */
11982 as_bad (_("-n32 is supported for ELF format only"));
11985 mips_abi = N32_ABI;
11991 as_bad (_("-64 is supported for ELF format only"));
11994 mips_abi = N64_ABI;
11995 if (!support_64bit_objects())
11996 as_fatal (_("No compiled in support for 64 bit object file format"));
11998 #endif /* OBJ_ELF */
12001 file_mips_gp32 = 1;
12005 file_mips_gp32 = 0;
12009 file_mips_fp32 = 1;
12013 file_mips_fp32 = 0;
12016 case OPTION_SINGLE_FLOAT:
12017 file_mips_single_float = 1;
12020 case OPTION_DOUBLE_FLOAT:
12021 file_mips_single_float = 0;
12024 case OPTION_SOFT_FLOAT:
12025 file_mips_soft_float = 1;
12028 case OPTION_HARD_FLOAT:
12029 file_mips_soft_float = 0;
12036 as_bad (_("-mabi is supported for ELF format only"));
12039 if (strcmp (arg, "32") == 0)
12040 mips_abi = O32_ABI;
12041 else if (strcmp (arg, "o64") == 0)
12042 mips_abi = O64_ABI;
12043 else if (strcmp (arg, "n32") == 0)
12044 mips_abi = N32_ABI;
12045 else if (strcmp (arg, "64") == 0)
12047 mips_abi = N64_ABI;
12048 if (! support_64bit_objects())
12049 as_fatal (_("No compiled in support for 64 bit object file "
12052 else if (strcmp (arg, "eabi") == 0)
12053 mips_abi = EABI_ABI;
12056 as_fatal (_("invalid abi -mabi=%s"), arg);
12060 #endif /* OBJ_ELF */
12062 case OPTION_M7000_HILO_FIX:
12063 mips_7000_hilo_fix = TRUE;
12066 case OPTION_MNO_7000_HILO_FIX:
12067 mips_7000_hilo_fix = FALSE;
12071 case OPTION_MDEBUG:
12072 mips_flag_mdebug = TRUE;
12075 case OPTION_NO_MDEBUG:
12076 mips_flag_mdebug = FALSE;
12080 mips_flag_pdr = TRUE;
12083 case OPTION_NO_PDR:
12084 mips_flag_pdr = FALSE;
12087 case OPTION_MVXWORKS_PIC:
12088 mips_pic = VXWORKS_PIC;
12090 #endif /* OBJ_ELF */
12096 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12101 /* Set up globals to generate code for the ISA or processor
12102 described by INFO. */
12105 mips_set_architecture (const struct mips_cpu_info *info)
12109 file_mips_arch = info->cpu;
12110 mips_opts.arch = info->cpu;
12111 mips_opts.isa = info->isa;
12116 /* Likewise for tuning. */
12119 mips_set_tune (const struct mips_cpu_info *info)
12122 mips_tune = info->cpu;
12127 mips_after_parse_args (void)
12129 const struct mips_cpu_info *arch_info = 0;
12130 const struct mips_cpu_info *tune_info = 0;
12132 /* GP relative stuff not working for PE */
12133 if (strncmp (TARGET_OS, "pe", 2) == 0)
12135 if (g_switch_seen && g_switch_value != 0)
12136 as_bad (_("-G not supported in this configuration."));
12137 g_switch_value = 0;
12140 if (mips_abi == NO_ABI)
12141 mips_abi = MIPS_DEFAULT_ABI;
12143 /* The following code determines the architecture and register size.
12144 Similar code was added to GCC 3.3 (see override_options() in
12145 config/mips/mips.c). The GAS and GCC code should be kept in sync
12146 as much as possible. */
12148 if (mips_arch_string != 0)
12149 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12151 if (file_mips_isa != ISA_UNKNOWN)
12153 /* Handle -mipsN. At this point, file_mips_isa contains the
12154 ISA level specified by -mipsN, while arch_info->isa contains
12155 the -march selection (if any). */
12156 if (arch_info != 0)
12158 /* -march takes precedence over -mipsN, since it is more descriptive.
12159 There's no harm in specifying both as long as the ISA levels
12161 if (file_mips_isa != arch_info->isa)
12162 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12163 mips_cpu_info_from_isa (file_mips_isa)->name,
12164 mips_cpu_info_from_isa (arch_info->isa)->name);
12167 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12170 if (arch_info == 0)
12171 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12173 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12174 as_bad (_("-march=%s is not compatible with the selected ABI"),
12177 mips_set_architecture (arch_info);
12179 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12180 if (mips_tune_string != 0)
12181 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12183 if (tune_info == 0)
12184 mips_set_tune (arch_info);
12186 mips_set_tune (tune_info);
12188 if (file_mips_gp32 >= 0)
12190 /* The user specified the size of the integer registers. Make sure
12191 it agrees with the ABI and ISA. */
12192 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12193 as_bad (_("-mgp64 used with a 32-bit processor"));
12194 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12195 as_bad (_("-mgp32 used with a 64-bit ABI"));
12196 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12197 as_bad (_("-mgp64 used with a 32-bit ABI"));
12201 /* Infer the integer register size from the ABI and processor.
12202 Restrict ourselves to 32-bit registers if that's all the
12203 processor has, or if the ABI cannot handle 64-bit registers. */
12204 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12205 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12208 switch (file_mips_fp32)
12212 /* No user specified float register size.
12213 ??? GAS treats single-float processors as though they had 64-bit
12214 float registers (although it complains when double-precision
12215 instructions are used). As things stand, saying they have 32-bit
12216 registers would lead to spurious "register must be even" messages.
12217 So here we assume float registers are never smaller than the
12219 if (file_mips_gp32 == 0)
12220 /* 64-bit integer registers implies 64-bit float registers. */
12221 file_mips_fp32 = 0;
12222 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12223 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12224 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12225 file_mips_fp32 = 0;
12227 /* 32-bit float registers. */
12228 file_mips_fp32 = 1;
12231 /* The user specified the size of the float registers. Check if it
12232 agrees with the ABI and ISA. */
12234 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12235 as_bad (_("-mfp64 used with a 32-bit fpu"));
12236 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12237 && !ISA_HAS_MXHC1 (mips_opts.isa))
12238 as_warn (_("-mfp64 used with a 32-bit ABI"));
12241 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12242 as_warn (_("-mfp32 used with a 64-bit ABI"));
12246 /* End of GCC-shared inference code. */
12248 /* This flag is set when we have a 64-bit capable CPU but use only
12249 32-bit wide registers. Note that EABI does not use it. */
12250 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12251 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12252 || mips_abi == O32_ABI))
12253 mips_32bitmode = 1;
12255 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12256 as_bad (_("trap exception not supported at ISA 1"));
12258 /* If the selected architecture includes support for ASEs, enable
12259 generation of code for them. */
12260 if (mips_opts.mips16 == -1)
12261 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12262 if (mips_opts.ase_mips3d == -1)
12263 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12264 && file_mips_fp32 == 0) ? 1 : 0;
12265 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12266 as_bad (_("-mfp32 used with -mips3d"));
12268 if (mips_opts.ase_mdmx == -1)
12269 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12270 && file_mips_fp32 == 0) ? 1 : 0;
12271 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12272 as_bad (_("-mfp32 used with -mdmx"));
12274 if (mips_opts.ase_smartmips == -1)
12275 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12276 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12277 as_warn (_("%s ISA does not support SmartMIPS"),
12278 mips_cpu_info_from_isa (mips_opts.isa)->name);
12280 if (mips_opts.ase_dsp == -1)
12281 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12282 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12283 as_warn (_("%s ISA does not support DSP ASE"),
12284 mips_cpu_info_from_isa (mips_opts.isa)->name);
12286 if (mips_opts.ase_dspr2 == -1)
12288 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12289 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12291 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12292 as_warn (_("%s ISA does not support DSP R2 ASE"),
12293 mips_cpu_info_from_isa (mips_opts.isa)->name);
12295 if (mips_opts.ase_mt == -1)
12296 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12297 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12298 as_warn (_("%s ISA does not support MT ASE"),
12299 mips_cpu_info_from_isa (mips_opts.isa)->name);
12301 file_mips_isa = mips_opts.isa;
12302 file_ase_mips3d = mips_opts.ase_mips3d;
12303 file_ase_mdmx = mips_opts.ase_mdmx;
12304 file_ase_smartmips = mips_opts.ase_smartmips;
12305 file_ase_dsp = mips_opts.ase_dsp;
12306 file_ase_dspr2 = mips_opts.ase_dspr2;
12307 file_ase_mt = mips_opts.ase_mt;
12308 mips_opts.gp32 = file_mips_gp32;
12309 mips_opts.fp32 = file_mips_fp32;
12310 mips_opts.soft_float = file_mips_soft_float;
12311 mips_opts.single_float = file_mips_single_float;
12313 if (mips_flag_mdebug < 0)
12315 #ifdef OBJ_MAYBE_ECOFF
12316 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12317 mips_flag_mdebug = 1;
12319 #endif /* OBJ_MAYBE_ECOFF */
12320 mips_flag_mdebug = 0;
12325 mips_init_after_args (void)
12327 /* initialize opcodes */
12328 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12329 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12333 md_pcrel_from (fixS *fixP)
12335 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12336 switch (fixP->fx_r_type)
12338 case BFD_RELOC_16_PCREL_S2:
12339 case BFD_RELOC_MIPS_JMP:
12340 /* Return the address of the delay slot. */
12343 /* We have no relocation type for PC relative MIPS16 instructions. */
12344 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12345 as_bad_where (fixP->fx_file, fixP->fx_line,
12346 _("PC relative MIPS16 instruction references a different section"));
12351 /* This is called before the symbol table is processed. In order to
12352 work with gcc when using mips-tfile, we must keep all local labels.
12353 However, in other cases, we want to discard them. If we were
12354 called with -g, but we didn't see any debugging information, it may
12355 mean that gcc is smuggling debugging information through to
12356 mips-tfile, in which case we must generate all local labels. */
12359 mips_frob_file_before_adjust (void)
12361 #ifndef NO_ECOFF_DEBUGGING
12362 if (ECOFF_DEBUGGING
12364 && ! ecoff_debugging_seen)
12365 flag_keep_locals = 1;
12369 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12370 the corresponding LO16 reloc. This is called before md_apply_fix and
12371 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12372 relocation operators.
12374 For our purposes, a %lo() expression matches a %got() or %hi()
12377 (a) it refers to the same symbol; and
12378 (b) the offset applied in the %lo() expression is no lower than
12379 the offset applied in the %got() or %hi().
12381 (b) allows us to cope with code like:
12384 lh $4,%lo(foo+2)($4)
12386 ...which is legal on RELA targets, and has a well-defined behaviour
12387 if the user knows that adding 2 to "foo" will not induce a carry to
12390 When several %lo()s match a particular %got() or %hi(), we use the
12391 following rules to distinguish them:
12393 (1) %lo()s with smaller offsets are a better match than %lo()s with
12396 (2) %lo()s with no matching %got() or %hi() are better than those
12397 that already have a matching %got() or %hi().
12399 (3) later %lo()s are better than earlier %lo()s.
12401 These rules are applied in order.
12403 (1) means, among other things, that %lo()s with identical offsets are
12404 chosen if they exist.
12406 (2) means that we won't associate several high-part relocations with
12407 the same low-part relocation unless there's no alternative. Having
12408 several high parts for the same low part is a GNU extension; this rule
12409 allows careful users to avoid it.
12411 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12412 with the last high-part relocation being at the front of the list.
12413 It therefore makes sense to choose the last matching low-part
12414 relocation, all other things being equal. It's also easier
12415 to code that way. */
12418 mips_frob_file (void)
12420 struct mips_hi_fixup *l;
12421 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12423 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12425 segment_info_type *seginfo;
12426 bfd_boolean matched_lo_p;
12427 fixS **hi_pos, **lo_pos, **pos;
12429 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12431 /* If a GOT16 relocation turns out to be against a global symbol,
12432 there isn't supposed to be a matching LO. */
12433 if (got16_reloc_p (l->fixp->fx_r_type)
12434 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12437 /* Check quickly whether the next fixup happens to be a matching %lo. */
12438 if (fixup_has_matching_lo_p (l->fixp))
12441 seginfo = seg_info (l->seg);
12443 /* Set HI_POS to the position of this relocation in the chain.
12444 Set LO_POS to the position of the chosen low-part relocation.
12445 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12446 relocation that matches an immediately-preceding high-part
12450 matched_lo_p = FALSE;
12451 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12453 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12455 if (*pos == l->fixp)
12458 if ((*pos)->fx_r_type == looking_for_rtype
12459 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12460 && (*pos)->fx_offset >= l->fixp->fx_offset
12462 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12464 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12467 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12468 && fixup_has_matching_lo_p (*pos));
12471 /* If we found a match, remove the high-part relocation from its
12472 current position and insert it before the low-part relocation.
12473 Make the offsets match so that fixup_has_matching_lo_p()
12476 We don't warn about unmatched high-part relocations since some
12477 versions of gcc have been known to emit dead "lui ...%hi(...)"
12479 if (lo_pos != NULL)
12481 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12482 if (l->fixp->fx_next != *lo_pos)
12484 *hi_pos = l->fixp->fx_next;
12485 l->fixp->fx_next = *lo_pos;
12492 /* We may have combined relocations without symbols in the N32/N64 ABI.
12493 We have to prevent gas from dropping them. */
12496 mips_force_relocation (fixS *fixp)
12498 if (generic_force_reloc (fixp))
12502 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12503 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12504 || hi16_reloc_p (fixp->fx_r_type)
12505 || lo16_reloc_p (fixp->fx_r_type)))
12511 /* Apply a fixup to the object file. */
12514 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12518 reloc_howto_type *howto;
12520 /* We ignore generic BFD relocations we don't know about. */
12521 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12525 gas_assert (fixP->fx_size == 4
12526 || fixP->fx_r_type == BFD_RELOC_16
12527 || fixP->fx_r_type == BFD_RELOC_64
12528 || fixP->fx_r_type == BFD_RELOC_CTOR
12529 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12530 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12531 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12532 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12534 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12536 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12538 /* Don't treat parts of a composite relocation as done. There are two
12541 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12542 should nevertheless be emitted if the first part is.
12544 (2) In normal usage, composite relocations are never assembly-time
12545 constants. The easiest way of dealing with the pathological
12546 exceptions is to generate a relocation against STN_UNDEF and
12547 leave everything up to the linker. */
12548 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12551 switch (fixP->fx_r_type)
12553 case BFD_RELOC_MIPS_TLS_GD:
12554 case BFD_RELOC_MIPS_TLS_LDM:
12555 case BFD_RELOC_MIPS_TLS_DTPREL32:
12556 case BFD_RELOC_MIPS_TLS_DTPREL64:
12557 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12558 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12559 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12560 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12561 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12562 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12565 case BFD_RELOC_MIPS_JMP:
12566 case BFD_RELOC_MIPS_SHIFT5:
12567 case BFD_RELOC_MIPS_SHIFT6:
12568 case BFD_RELOC_MIPS_GOT_DISP:
12569 case BFD_RELOC_MIPS_GOT_PAGE:
12570 case BFD_RELOC_MIPS_GOT_OFST:
12571 case BFD_RELOC_MIPS_SUB:
12572 case BFD_RELOC_MIPS_INSERT_A:
12573 case BFD_RELOC_MIPS_INSERT_B:
12574 case BFD_RELOC_MIPS_DELETE:
12575 case BFD_RELOC_MIPS_HIGHEST:
12576 case BFD_RELOC_MIPS_HIGHER:
12577 case BFD_RELOC_MIPS_SCN_DISP:
12578 case BFD_RELOC_MIPS_REL16:
12579 case BFD_RELOC_MIPS_RELGOT:
12580 case BFD_RELOC_MIPS_JALR:
12581 case BFD_RELOC_HI16:
12582 case BFD_RELOC_HI16_S:
12583 case BFD_RELOC_GPREL16:
12584 case BFD_RELOC_MIPS_LITERAL:
12585 case BFD_RELOC_MIPS_CALL16:
12586 case BFD_RELOC_MIPS_GOT16:
12587 case BFD_RELOC_GPREL32:
12588 case BFD_RELOC_MIPS_GOT_HI16:
12589 case BFD_RELOC_MIPS_GOT_LO16:
12590 case BFD_RELOC_MIPS_CALL_HI16:
12591 case BFD_RELOC_MIPS_CALL_LO16:
12592 case BFD_RELOC_MIPS16_GPREL:
12593 case BFD_RELOC_MIPS16_GOT16:
12594 case BFD_RELOC_MIPS16_CALL16:
12595 case BFD_RELOC_MIPS16_HI16:
12596 case BFD_RELOC_MIPS16_HI16_S:
12597 case BFD_RELOC_MIPS16_JMP:
12598 /* Nothing needed to do. The value comes from the reloc entry. */
12602 /* This is handled like BFD_RELOC_32, but we output a sign
12603 extended value if we are only 32 bits. */
12606 if (8 <= sizeof (valueT))
12607 md_number_to_chars ((char *) buf, *valP, 8);
12612 if ((*valP & 0x80000000) != 0)
12616 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12618 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12624 case BFD_RELOC_RVA:
12627 /* If we are deleting this reloc entry, we must fill in the
12628 value now. This can happen if we have a .word which is not
12629 resolved when it appears but is later defined. */
12631 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12634 case BFD_RELOC_LO16:
12635 case BFD_RELOC_MIPS16_LO16:
12636 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12637 may be safe to remove, but if so it's not obvious. */
12638 /* When handling an embedded PIC switch statement, we can wind
12639 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12642 if (*valP + 0x8000 > 0xffff)
12643 as_bad_where (fixP->fx_file, fixP->fx_line,
12644 _("relocation overflow"));
12645 if (target_big_endian)
12647 md_number_to_chars ((char *) buf, *valP, 2);
12651 case BFD_RELOC_16_PCREL_S2:
12652 if ((*valP & 0x3) != 0)
12653 as_bad_where (fixP->fx_file, fixP->fx_line,
12654 _("Branch to misaligned address (%lx)"), (long) *valP);
12656 /* We need to save the bits in the instruction since fixup_segment()
12657 might be deleting the relocation entry (i.e., a branch within
12658 the current segment). */
12659 if (! fixP->fx_done)
12662 /* Update old instruction data. */
12663 if (target_big_endian)
12664 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12666 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12668 if (*valP + 0x20000 <= 0x3ffff)
12670 insn |= (*valP >> 2) & 0xffff;
12671 md_number_to_chars ((char *) buf, insn, 4);
12673 else if (mips_pic == NO_PIC
12675 && fixP->fx_frag->fr_address >= text_section->vma
12676 && (fixP->fx_frag->fr_address
12677 < text_section->vma + bfd_get_section_size (text_section))
12678 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12679 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12680 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12682 /* The branch offset is too large. If this is an
12683 unconditional branch, and we are not generating PIC code,
12684 we can convert it to an absolute jump instruction. */
12685 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12686 insn = 0x0c000000; /* jal */
12688 insn = 0x08000000; /* j */
12689 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12691 fixP->fx_addsy = section_symbol (text_section);
12692 *valP += md_pcrel_from (fixP);
12693 md_number_to_chars ((char *) buf, insn, 4);
12697 /* If we got here, we have branch-relaxation disabled,
12698 and there's nothing we can do to fix this instruction
12699 without turning it into a longer sequence. */
12700 as_bad_where (fixP->fx_file, fixP->fx_line,
12701 _("Branch out of range"));
12705 case BFD_RELOC_VTABLE_INHERIT:
12708 && !S_IS_DEFINED (fixP->fx_addsy)
12709 && !S_IS_WEAK (fixP->fx_addsy))
12710 S_SET_WEAK (fixP->fx_addsy);
12713 case BFD_RELOC_VTABLE_ENTRY:
12721 /* Remember value for tc_gen_reloc. */
12722 fixP->fx_addnumber = *valP;
12732 name = input_line_pointer;
12733 c = get_symbol_end ();
12734 p = (symbolS *) symbol_find_or_make (name);
12735 *input_line_pointer = c;
12739 /* Align the current frag to a given power of two. If a particular
12740 fill byte should be used, FILL points to an integer that contains
12741 that byte, otherwise FILL is null.
12743 The MIPS assembler also automatically adjusts any preceding
12747 mips_align (int to, int *fill, symbolS *label)
12749 mips_emit_delays ();
12750 mips_record_mips16_mode ();
12751 if (fill == NULL && subseg_text_p (now_seg))
12752 frag_align_code (to, 0);
12754 frag_align (to, fill ? *fill : 0, 0);
12755 record_alignment (now_seg, to);
12758 gas_assert (S_GET_SEGMENT (label) == now_seg);
12759 symbol_set_frag (label, frag_now);
12760 S_SET_VALUE (label, (valueT) frag_now_fix ());
12764 /* Align to a given power of two. .align 0 turns off the automatic
12765 alignment used by the data creating pseudo-ops. */
12768 s_align (int x ATTRIBUTE_UNUSED)
12770 int temp, fill_value, *fill_ptr;
12771 long max_alignment = 28;
12773 /* o Note that the assembler pulls down any immediately preceding label
12774 to the aligned address.
12775 o It's not documented but auto alignment is reinstated by
12776 a .align pseudo instruction.
12777 o Note also that after auto alignment is turned off the mips assembler
12778 issues an error on attempt to assemble an improperly aligned data item.
12781 temp = get_absolute_expression ();
12782 if (temp > max_alignment)
12783 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12786 as_warn (_("Alignment negative: 0 assumed."));
12789 if (*input_line_pointer == ',')
12791 ++input_line_pointer;
12792 fill_value = get_absolute_expression ();
12793 fill_ptr = &fill_value;
12799 segment_info_type *si = seg_info (now_seg);
12800 struct insn_label_list *l = si->label_list;
12801 /* Auto alignment should be switched on by next section change. */
12803 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12810 demand_empty_rest_of_line ();
12814 s_change_sec (int sec)
12819 /* The ELF backend needs to know that we are changing sections, so
12820 that .previous works correctly. We could do something like check
12821 for an obj_section_change_hook macro, but that might be confusing
12822 as it would not be appropriate to use it in the section changing
12823 functions in read.c, since obj-elf.c intercepts those. FIXME:
12824 This should be cleaner, somehow. */
12826 obj_elf_section_change_hook ();
12829 mips_emit_delays ();
12840 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12841 demand_empty_rest_of_line ();
12845 seg = subseg_new (RDATA_SECTION_NAME,
12846 (subsegT) get_absolute_expression ());
12849 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12850 | SEC_READONLY | SEC_RELOC
12852 if (strncmp (TARGET_OS, "elf", 3) != 0)
12853 record_alignment (seg, 4);
12855 demand_empty_rest_of_line ();
12859 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12862 bfd_set_section_flags (stdoutput, seg,
12863 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12864 if (strncmp (TARGET_OS, "elf", 3) != 0)
12865 record_alignment (seg, 4);
12867 demand_empty_rest_of_line ();
12871 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12874 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12875 if (strncmp (TARGET_OS, "elf", 3) != 0)
12876 record_alignment (seg, 4);
12878 demand_empty_rest_of_line ();
12886 s_change_section (int ignore ATTRIBUTE_UNUSED)
12889 char *section_name;
12894 int section_entry_size;
12895 int section_alignment;
12900 section_name = input_line_pointer;
12901 c = get_symbol_end ();
12903 next_c = *(input_line_pointer + 1);
12905 /* Do we have .section Name<,"flags">? */
12906 if (c != ',' || (c == ',' && next_c == '"'))
12908 /* just after name is now '\0'. */
12909 *input_line_pointer = c;
12910 input_line_pointer = section_name;
12911 obj_elf_section (ignore);
12914 input_line_pointer++;
12916 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12918 section_type = get_absolute_expression ();
12921 if (*input_line_pointer++ == ',')
12922 section_flag = get_absolute_expression ();
12925 if (*input_line_pointer++ == ',')
12926 section_entry_size = get_absolute_expression ();
12928 section_entry_size = 0;
12929 if (*input_line_pointer++ == ',')
12930 section_alignment = get_absolute_expression ();
12932 section_alignment = 0;
12933 /* FIXME: really ignore? */
12934 (void) section_alignment;
12936 section_name = xstrdup (section_name);
12938 /* When using the generic form of .section (as implemented by obj-elf.c),
12939 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12940 traditionally had to fall back on the more common @progbits instead.
12942 There's nothing really harmful in this, since bfd will correct
12943 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12944 means that, for backwards compatibility, the special_section entries
12945 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12947 Even so, we shouldn't force users of the MIPS .section syntax to
12948 incorrectly label the sections as SHT_PROGBITS. The best compromise
12949 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12950 generic type-checking code. */
12951 if (section_type == SHT_MIPS_DWARF)
12952 section_type = SHT_PROGBITS;
12954 obj_elf_change_section (section_name, section_type, section_flag,
12955 section_entry_size, 0, 0, 0);
12957 if (now_seg->name != section_name)
12958 free (section_name);
12959 #endif /* OBJ_ELF */
12963 mips_enable_auto_align (void)
12969 s_cons (int log_size)
12971 segment_info_type *si = seg_info (now_seg);
12972 struct insn_label_list *l = si->label_list;
12975 label = l != NULL ? l->label : NULL;
12976 mips_emit_delays ();
12977 if (log_size > 0 && auto_align)
12978 mips_align (log_size, 0, label);
12979 cons (1 << log_size);
12980 mips_clear_insn_labels ();
12984 s_float_cons (int type)
12986 segment_info_type *si = seg_info (now_seg);
12987 struct insn_label_list *l = si->label_list;
12990 label = l != NULL ? l->label : NULL;
12992 mips_emit_delays ();
12997 mips_align (3, 0, label);
12999 mips_align (2, 0, label);
13003 mips_clear_insn_labels ();
13006 /* Handle .globl. We need to override it because on Irix 5 you are
13009 where foo is an undefined symbol, to mean that foo should be
13010 considered to be the address of a function. */
13013 s_mips_globl (int x ATTRIBUTE_UNUSED)
13022 name = input_line_pointer;
13023 c = get_symbol_end ();
13024 symbolP = symbol_find_or_make (name);
13025 S_SET_EXTERNAL (symbolP);
13027 *input_line_pointer = c;
13028 SKIP_WHITESPACE ();
13030 /* On Irix 5, every global symbol that is not explicitly labelled as
13031 being a function is apparently labelled as being an object. */
13034 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13035 && (*input_line_pointer != ','))
13040 secname = input_line_pointer;
13041 c = get_symbol_end ();
13042 sec = bfd_get_section_by_name (stdoutput, secname);
13044 as_bad (_("%s: no such section"), secname);
13045 *input_line_pointer = c;
13047 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13048 flag = BSF_FUNCTION;
13051 symbol_get_bfdsym (symbolP)->flags |= flag;
13053 c = *input_line_pointer;
13056 input_line_pointer++;
13057 SKIP_WHITESPACE ();
13058 if (is_end_of_line[(unsigned char) *input_line_pointer])
13064 demand_empty_rest_of_line ();
13068 s_option (int x ATTRIBUTE_UNUSED)
13073 opt = input_line_pointer;
13074 c = get_symbol_end ();
13078 /* FIXME: What does this mean? */
13080 else if (strncmp (opt, "pic", 3) == 0)
13084 i = atoi (opt + 3);
13089 mips_pic = SVR4_PIC;
13090 mips_abicalls = TRUE;
13093 as_bad (_(".option pic%d not supported"), i);
13095 if (mips_pic == SVR4_PIC)
13097 if (g_switch_seen && g_switch_value != 0)
13098 as_warn (_("-G may not be used with SVR4 PIC code"));
13099 g_switch_value = 0;
13100 bfd_set_gp_size (stdoutput, 0);
13104 as_warn (_("Unrecognized option \"%s\""), opt);
13106 *input_line_pointer = c;
13107 demand_empty_rest_of_line ();
13110 /* This structure is used to hold a stack of .set values. */
13112 struct mips_option_stack
13114 struct mips_option_stack *next;
13115 struct mips_set_options options;
13118 static struct mips_option_stack *mips_opts_stack;
13120 /* Handle the .set pseudo-op. */
13123 s_mipsset (int x ATTRIBUTE_UNUSED)
13125 char *name = input_line_pointer, ch;
13127 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13128 ++input_line_pointer;
13129 ch = *input_line_pointer;
13130 *input_line_pointer = '\0';
13132 if (strcmp (name, "reorder") == 0)
13134 if (mips_opts.noreorder)
13137 else if (strcmp (name, "noreorder") == 0)
13139 if (!mips_opts.noreorder)
13140 start_noreorder ();
13142 else if (strncmp (name, "at=", 3) == 0)
13144 char *s = name + 3;
13146 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13147 as_bad (_("Unrecognized register name `%s'"), s);
13149 else if (strcmp (name, "at") == 0)
13151 mips_opts.at = ATREG;
13153 else if (strcmp (name, "noat") == 0)
13155 mips_opts.at = ZERO;
13157 else if (strcmp (name, "macro") == 0)
13159 mips_opts.warn_about_macros = 0;
13161 else if (strcmp (name, "nomacro") == 0)
13163 if (mips_opts.noreorder == 0)
13164 as_bad (_("`noreorder' must be set before `nomacro'"));
13165 mips_opts.warn_about_macros = 1;
13167 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13169 mips_opts.nomove = 0;
13171 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13173 mips_opts.nomove = 1;
13175 else if (strcmp (name, "bopt") == 0)
13177 mips_opts.nobopt = 0;
13179 else if (strcmp (name, "nobopt") == 0)
13181 mips_opts.nobopt = 1;
13183 else if (strcmp (name, "gp=default") == 0)
13184 mips_opts.gp32 = file_mips_gp32;
13185 else if (strcmp (name, "gp=32") == 0)
13186 mips_opts.gp32 = 1;
13187 else if (strcmp (name, "gp=64") == 0)
13189 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13190 as_warn (_("%s isa does not support 64-bit registers"),
13191 mips_cpu_info_from_isa (mips_opts.isa)->name);
13192 mips_opts.gp32 = 0;
13194 else if (strcmp (name, "fp=default") == 0)
13195 mips_opts.fp32 = file_mips_fp32;
13196 else if (strcmp (name, "fp=32") == 0)
13197 mips_opts.fp32 = 1;
13198 else if (strcmp (name, "fp=64") == 0)
13200 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13201 as_warn (_("%s isa does not support 64-bit floating point registers"),
13202 mips_cpu_info_from_isa (mips_opts.isa)->name);
13203 mips_opts.fp32 = 0;
13205 else if (strcmp (name, "softfloat") == 0)
13206 mips_opts.soft_float = 1;
13207 else if (strcmp (name, "hardfloat") == 0)
13208 mips_opts.soft_float = 0;
13209 else if (strcmp (name, "singlefloat") == 0)
13210 mips_opts.single_float = 1;
13211 else if (strcmp (name, "doublefloat") == 0)
13212 mips_opts.single_float = 0;
13213 else if (strcmp (name, "mips16") == 0
13214 || strcmp (name, "MIPS-16") == 0)
13215 mips_opts.mips16 = 1;
13216 else if (strcmp (name, "nomips16") == 0
13217 || strcmp (name, "noMIPS-16") == 0)
13218 mips_opts.mips16 = 0;
13219 else if (strcmp (name, "smartmips") == 0)
13221 if (!ISA_SUPPORTS_SMARTMIPS)
13222 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13223 mips_cpu_info_from_isa (mips_opts.isa)->name);
13224 mips_opts.ase_smartmips = 1;
13226 else if (strcmp (name, "nosmartmips") == 0)
13227 mips_opts.ase_smartmips = 0;
13228 else if (strcmp (name, "mips3d") == 0)
13229 mips_opts.ase_mips3d = 1;
13230 else if (strcmp (name, "nomips3d") == 0)
13231 mips_opts.ase_mips3d = 0;
13232 else if (strcmp (name, "mdmx") == 0)
13233 mips_opts.ase_mdmx = 1;
13234 else if (strcmp (name, "nomdmx") == 0)
13235 mips_opts.ase_mdmx = 0;
13236 else if (strcmp (name, "dsp") == 0)
13238 if (!ISA_SUPPORTS_DSP_ASE)
13239 as_warn (_("%s ISA does not support DSP ASE"),
13240 mips_cpu_info_from_isa (mips_opts.isa)->name);
13241 mips_opts.ase_dsp = 1;
13242 mips_opts.ase_dspr2 = 0;
13244 else if (strcmp (name, "nodsp") == 0)
13246 mips_opts.ase_dsp = 0;
13247 mips_opts.ase_dspr2 = 0;
13249 else if (strcmp (name, "dspr2") == 0)
13251 if (!ISA_SUPPORTS_DSPR2_ASE)
13252 as_warn (_("%s ISA does not support DSP R2 ASE"),
13253 mips_cpu_info_from_isa (mips_opts.isa)->name);
13254 mips_opts.ase_dspr2 = 1;
13255 mips_opts.ase_dsp = 1;
13257 else if (strcmp (name, "nodspr2") == 0)
13259 mips_opts.ase_dspr2 = 0;
13260 mips_opts.ase_dsp = 0;
13262 else if (strcmp (name, "mt") == 0)
13264 if (!ISA_SUPPORTS_MT_ASE)
13265 as_warn (_("%s ISA does not support MT ASE"),
13266 mips_cpu_info_from_isa (mips_opts.isa)->name);
13267 mips_opts.ase_mt = 1;
13269 else if (strcmp (name, "nomt") == 0)
13270 mips_opts.ase_mt = 0;
13271 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13275 /* Permit the user to change the ISA and architecture on the fly.
13276 Needless to say, misuse can cause serious problems. */
13277 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13280 mips_opts.isa = file_mips_isa;
13281 mips_opts.arch = file_mips_arch;
13283 else if (strncmp (name, "arch=", 5) == 0)
13285 const struct mips_cpu_info *p;
13287 p = mips_parse_cpu("internal use", name + 5);
13289 as_bad (_("unknown architecture %s"), name + 5);
13292 mips_opts.arch = p->cpu;
13293 mips_opts.isa = p->isa;
13296 else if (strncmp (name, "mips", 4) == 0)
13298 const struct mips_cpu_info *p;
13300 p = mips_parse_cpu("internal use", name);
13302 as_bad (_("unknown ISA level %s"), name + 4);
13305 mips_opts.arch = p->cpu;
13306 mips_opts.isa = p->isa;
13310 as_bad (_("unknown ISA or architecture %s"), name);
13312 switch (mips_opts.isa)
13320 mips_opts.gp32 = 1;
13321 mips_opts.fp32 = 1;
13328 mips_opts.gp32 = 0;
13329 mips_opts.fp32 = 0;
13332 as_bad (_("unknown ISA level %s"), name + 4);
13337 mips_opts.gp32 = file_mips_gp32;
13338 mips_opts.fp32 = file_mips_fp32;
13341 else if (strcmp (name, "autoextend") == 0)
13342 mips_opts.noautoextend = 0;
13343 else if (strcmp (name, "noautoextend") == 0)
13344 mips_opts.noautoextend = 1;
13345 else if (strcmp (name, "push") == 0)
13347 struct mips_option_stack *s;
13349 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13350 s->next = mips_opts_stack;
13351 s->options = mips_opts;
13352 mips_opts_stack = s;
13354 else if (strcmp (name, "pop") == 0)
13356 struct mips_option_stack *s;
13358 s = mips_opts_stack;
13360 as_bad (_(".set pop with no .set push"));
13363 /* If we're changing the reorder mode we need to handle
13364 delay slots correctly. */
13365 if (s->options.noreorder && ! mips_opts.noreorder)
13366 start_noreorder ();
13367 else if (! s->options.noreorder && mips_opts.noreorder)
13370 mips_opts = s->options;
13371 mips_opts_stack = s->next;
13375 else if (strcmp (name, "sym32") == 0)
13376 mips_opts.sym32 = TRUE;
13377 else if (strcmp (name, "nosym32") == 0)
13378 mips_opts.sym32 = FALSE;
13379 else if (strchr (name, ','))
13381 /* Generic ".set" directive; use the generic handler. */
13382 *input_line_pointer = ch;
13383 input_line_pointer = name;
13389 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13391 *input_line_pointer = ch;
13392 demand_empty_rest_of_line ();
13395 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13396 .option pic2. It means to generate SVR4 PIC calls. */
13399 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13401 mips_pic = SVR4_PIC;
13402 mips_abicalls = TRUE;
13404 if (g_switch_seen && g_switch_value != 0)
13405 as_warn (_("-G may not be used with SVR4 PIC code"));
13406 g_switch_value = 0;
13408 bfd_set_gp_size (stdoutput, 0);
13409 demand_empty_rest_of_line ();
13412 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13413 PIC code. It sets the $gp register for the function based on the
13414 function address, which is in the register named in the argument.
13415 This uses a relocation against _gp_disp, which is handled specially
13416 by the linker. The result is:
13417 lui $gp,%hi(_gp_disp)
13418 addiu $gp,$gp,%lo(_gp_disp)
13419 addu $gp,$gp,.cpload argument
13420 The .cpload argument is normally $25 == $t9.
13422 The -mno-shared option changes this to:
13423 lui $gp,%hi(__gnu_local_gp)
13424 addiu $gp,$gp,%lo(__gnu_local_gp)
13425 and the argument is ignored. This saves an instruction, but the
13426 resulting code is not position independent; it uses an absolute
13427 address for __gnu_local_gp. Thus code assembled with -mno-shared
13428 can go into an ordinary executable, but not into a shared library. */
13431 s_cpload (int ignore ATTRIBUTE_UNUSED)
13437 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13438 .cpload is ignored. */
13439 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13445 /* .cpload should be in a .set noreorder section. */
13446 if (mips_opts.noreorder == 0)
13447 as_warn (_(".cpload not in noreorder section"));
13449 reg = tc_get_register (0);
13451 /* If we need to produce a 64-bit address, we are better off using
13452 the default instruction sequence. */
13453 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13455 ex.X_op = O_symbol;
13456 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13458 ex.X_op_symbol = NULL;
13459 ex.X_add_number = 0;
13461 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13462 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13465 macro_build_lui (&ex, mips_gp_register);
13466 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13467 mips_gp_register, BFD_RELOC_LO16);
13469 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13470 mips_gp_register, reg);
13473 demand_empty_rest_of_line ();
13476 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13477 .cpsetup $reg1, offset|$reg2, label
13479 If offset is given, this results in:
13480 sd $gp, offset($sp)
13481 lui $gp, %hi(%neg(%gp_rel(label)))
13482 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13483 daddu $gp, $gp, $reg1
13485 If $reg2 is given, this results in:
13486 daddu $reg2, $gp, $0
13487 lui $gp, %hi(%neg(%gp_rel(label)))
13488 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13489 daddu $gp, $gp, $reg1
13490 $reg1 is normally $25 == $t9.
13492 The -mno-shared option replaces the last three instructions with
13494 addiu $gp,$gp,%lo(_gp) */
13497 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13499 expressionS ex_off;
13500 expressionS ex_sym;
13503 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13504 We also need NewABI support. */
13505 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13511 reg1 = tc_get_register (0);
13512 SKIP_WHITESPACE ();
13513 if (*input_line_pointer != ',')
13515 as_bad (_("missing argument separator ',' for .cpsetup"));
13519 ++input_line_pointer;
13520 SKIP_WHITESPACE ();
13521 if (*input_line_pointer == '$')
13523 mips_cpreturn_register = tc_get_register (0);
13524 mips_cpreturn_offset = -1;
13528 mips_cpreturn_offset = get_absolute_expression ();
13529 mips_cpreturn_register = -1;
13531 SKIP_WHITESPACE ();
13532 if (*input_line_pointer != ',')
13534 as_bad (_("missing argument separator ',' for .cpsetup"));
13538 ++input_line_pointer;
13539 SKIP_WHITESPACE ();
13540 expression (&ex_sym);
13543 if (mips_cpreturn_register == -1)
13545 ex_off.X_op = O_constant;
13546 ex_off.X_add_symbol = NULL;
13547 ex_off.X_op_symbol = NULL;
13548 ex_off.X_add_number = mips_cpreturn_offset;
13550 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13551 BFD_RELOC_LO16, SP);
13554 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13555 mips_gp_register, 0);
13557 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13559 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13560 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13563 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13564 mips_gp_register, -1, BFD_RELOC_GPREL16,
13565 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13567 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13568 mips_gp_register, reg1);
13574 ex.X_op = O_symbol;
13575 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13576 ex.X_op_symbol = NULL;
13577 ex.X_add_number = 0;
13579 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13580 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13582 macro_build_lui (&ex, mips_gp_register);
13583 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13584 mips_gp_register, BFD_RELOC_LO16);
13589 demand_empty_rest_of_line ();
13593 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13595 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13596 .cplocal is ignored. */
13597 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13603 mips_gp_register = tc_get_register (0);
13604 demand_empty_rest_of_line ();
13607 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13608 offset from $sp. The offset is remembered, and after making a PIC
13609 call $gp is restored from that location. */
13612 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13616 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13617 .cprestore is ignored. */
13618 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13624 mips_cprestore_offset = get_absolute_expression ();
13625 mips_cprestore_valid = 1;
13627 ex.X_op = O_constant;
13628 ex.X_add_symbol = NULL;
13629 ex.X_op_symbol = NULL;
13630 ex.X_add_number = mips_cprestore_offset;
13633 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13634 SP, HAVE_64BIT_ADDRESSES);
13637 demand_empty_rest_of_line ();
13640 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13641 was given in the preceding .cpsetup, it results in:
13642 ld $gp, offset($sp)
13644 If a register $reg2 was given there, it results in:
13645 daddu $gp, $reg2, $0 */
13648 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13652 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13653 We also need NewABI support. */
13654 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13661 if (mips_cpreturn_register == -1)
13663 ex.X_op = O_constant;
13664 ex.X_add_symbol = NULL;
13665 ex.X_op_symbol = NULL;
13666 ex.X_add_number = mips_cpreturn_offset;
13668 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13671 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13672 mips_cpreturn_register, 0);
13675 demand_empty_rest_of_line ();
13678 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13679 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13680 use in DWARF debug information. */
13683 s_dtprel_internal (size_t bytes)
13690 if (ex.X_op != O_symbol)
13692 as_bad (_("Unsupported use of %s"), (bytes == 8
13695 ignore_rest_of_line ();
13698 p = frag_more (bytes);
13699 md_number_to_chars (p, 0, bytes);
13700 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13702 ? BFD_RELOC_MIPS_TLS_DTPREL64
13703 : BFD_RELOC_MIPS_TLS_DTPREL32));
13705 demand_empty_rest_of_line ();
13708 /* Handle .dtprelword. */
13711 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13713 s_dtprel_internal (4);
13716 /* Handle .dtpreldword. */
13719 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13721 s_dtprel_internal (8);
13724 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13725 code. It sets the offset to use in gp_rel relocations. */
13728 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13730 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13731 We also need NewABI support. */
13732 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13738 mips_gprel_offset = get_absolute_expression ();
13740 demand_empty_rest_of_line ();
13743 /* Handle the .gpword pseudo-op. This is used when generating PIC
13744 code. It generates a 32 bit GP relative reloc. */
13747 s_gpword (int ignore ATTRIBUTE_UNUSED)
13749 segment_info_type *si;
13750 struct insn_label_list *l;
13755 /* When not generating PIC code, this is treated as .word. */
13756 if (mips_pic != SVR4_PIC)
13762 si = seg_info (now_seg);
13763 l = si->label_list;
13764 label = l != NULL ? l->label : NULL;
13765 mips_emit_delays ();
13767 mips_align (2, 0, label);
13770 mips_clear_insn_labels ();
13772 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13774 as_bad (_("Unsupported use of .gpword"));
13775 ignore_rest_of_line ();
13779 md_number_to_chars (p, 0, 4);
13780 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13781 BFD_RELOC_GPREL32);
13783 demand_empty_rest_of_line ();
13787 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13789 segment_info_type *si;
13790 struct insn_label_list *l;
13795 /* When not generating PIC code, this is treated as .dword. */
13796 if (mips_pic != SVR4_PIC)
13802 si = seg_info (now_seg);
13803 l = si->label_list;
13804 label = l != NULL ? l->label : NULL;
13805 mips_emit_delays ();
13807 mips_align (3, 0, label);
13810 mips_clear_insn_labels ();
13812 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13814 as_bad (_("Unsupported use of .gpdword"));
13815 ignore_rest_of_line ();
13819 md_number_to_chars (p, 0, 8);
13820 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13821 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13823 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13824 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13825 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13827 demand_empty_rest_of_line ();
13830 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13831 tables in SVR4 PIC code. */
13834 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13838 /* This is ignored when not generating SVR4 PIC code. */
13839 if (mips_pic != SVR4_PIC)
13845 /* Add $gp to the register named as an argument. */
13847 reg = tc_get_register (0);
13848 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13851 demand_empty_rest_of_line ();
13854 /* Handle the .insn pseudo-op. This marks instruction labels in
13855 mips16 mode. This permits the linker to handle them specially,
13856 such as generating jalx instructions when needed. We also make
13857 them odd for the duration of the assembly, in order to generate the
13858 right sort of code. We will make them even in the adjust_symtab
13859 routine, while leaving them marked. This is convenient for the
13860 debugger and the disassembler. The linker knows to make them odd
13864 s_insn (int ignore ATTRIBUTE_UNUSED)
13866 mips16_mark_labels ();
13868 demand_empty_rest_of_line ();
13871 /* Handle a .stabn directive. We need these in order to mark a label
13872 as being a mips16 text label correctly. Sometimes the compiler
13873 will emit a label, followed by a .stabn, and then switch sections.
13874 If the label and .stabn are in mips16 mode, then the label is
13875 really a mips16 text label. */
13878 s_mips_stab (int type)
13881 mips16_mark_labels ();
13886 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13889 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13896 name = input_line_pointer;
13897 c = get_symbol_end ();
13898 symbolP = symbol_find_or_make (name);
13899 S_SET_WEAK (symbolP);
13900 *input_line_pointer = c;
13902 SKIP_WHITESPACE ();
13904 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13906 if (S_IS_DEFINED (symbolP))
13908 as_bad (_("ignoring attempt to redefine symbol %s"),
13909 S_GET_NAME (symbolP));
13910 ignore_rest_of_line ();
13914 if (*input_line_pointer == ',')
13916 ++input_line_pointer;
13917 SKIP_WHITESPACE ();
13921 if (exp.X_op != O_symbol)
13923 as_bad (_("bad .weakext directive"));
13924 ignore_rest_of_line ();
13927 symbol_set_value_expression (symbolP, &exp);
13930 demand_empty_rest_of_line ();
13933 /* Parse a register string into a number. Called from the ECOFF code
13934 to parse .frame. The argument is non-zero if this is the frame
13935 register, so that we can record it in mips_frame_reg. */
13938 tc_get_register (int frame)
13942 SKIP_WHITESPACE ();
13943 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13947 mips_frame_reg = reg != 0 ? reg : SP;
13948 mips_frame_reg_valid = 1;
13949 mips_cprestore_valid = 0;
13955 md_section_align (asection *seg, valueT addr)
13957 int align = bfd_get_section_alignment (stdoutput, seg);
13961 /* We don't need to align ELF sections to the full alignment.
13962 However, Irix 5 may prefer that we align them at least to a 16
13963 byte boundary. We don't bother to align the sections if we
13964 are targeted for an embedded system. */
13965 if (strncmp (TARGET_OS, "elf", 3) == 0)
13971 return ((addr + (1 << align) - 1) & (-1 << align));
13974 /* Utility routine, called from above as well. If called while the
13975 input file is still being read, it's only an approximation. (For
13976 example, a symbol may later become defined which appeared to be
13977 undefined earlier.) */
13980 nopic_need_relax (symbolS *sym, int before_relaxing)
13985 if (g_switch_value > 0)
13987 const char *symname;
13990 /* Find out whether this symbol can be referenced off the $gp
13991 register. It can be if it is smaller than the -G size or if
13992 it is in the .sdata or .sbss section. Certain symbols can
13993 not be referenced off the $gp, although it appears as though
13995 symname = S_GET_NAME (sym);
13996 if (symname != (const char *) NULL
13997 && (strcmp (symname, "eprol") == 0
13998 || strcmp (symname, "etext") == 0
13999 || strcmp (symname, "_gp") == 0
14000 || strcmp (symname, "edata") == 0
14001 || strcmp (symname, "_fbss") == 0
14002 || strcmp (symname, "_fdata") == 0
14003 || strcmp (symname, "_ftext") == 0
14004 || strcmp (symname, "end") == 0
14005 || strcmp (symname, "_gp_disp") == 0))
14007 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14009 #ifndef NO_ECOFF_DEBUGGING
14010 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14011 && (symbol_get_obj (sym)->ecoff_extern_size
14012 <= g_switch_value))
14014 /* We must defer this decision until after the whole
14015 file has been read, since there might be a .extern
14016 after the first use of this symbol. */
14017 || (before_relaxing
14018 #ifndef NO_ECOFF_DEBUGGING
14019 && symbol_get_obj (sym)->ecoff_extern_size == 0
14021 && S_GET_VALUE (sym) == 0)
14022 || (S_GET_VALUE (sym) != 0
14023 && S_GET_VALUE (sym) <= g_switch_value)))
14027 const char *segname;
14029 segname = segment_name (S_GET_SEGMENT (sym));
14030 gas_assert (strcmp (segname, ".lit8") != 0
14031 && strcmp (segname, ".lit4") != 0);
14032 change = (strcmp (segname, ".sdata") != 0
14033 && strcmp (segname, ".sbss") != 0
14034 && strncmp (segname, ".sdata.", 7) != 0
14035 && strncmp (segname, ".sbss.", 6) != 0
14036 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14037 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14042 /* We are not optimizing for the $gp register. */
14047 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14050 pic_need_relax (symbolS *sym, asection *segtype)
14054 /* Handle the case of a symbol equated to another symbol. */
14055 while (symbol_equated_reloc_p (sym))
14059 /* It's possible to get a loop here in a badly written program. */
14060 n = symbol_get_value_expression (sym)->X_add_symbol;
14066 if (symbol_section_p (sym))
14069 symsec = S_GET_SEGMENT (sym);
14071 /* This must duplicate the test in adjust_reloc_syms. */
14072 return (symsec != &bfd_und_section
14073 && symsec != &bfd_abs_section
14074 && !bfd_is_com_section (symsec)
14075 && !s_is_linkonce (sym, segtype)
14077 /* A global or weak symbol is treated as external. */
14078 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14084 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14085 extended opcode. SEC is the section the frag is in. */
14088 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14091 const struct mips16_immed_operand *op;
14093 int mintiny, maxtiny;
14097 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14099 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14102 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14103 op = mips16_immed_operands;
14104 while (op->type != type)
14107 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14112 if (type == '<' || type == '>' || type == '[' || type == ']')
14115 maxtiny = 1 << op->nbits;
14120 maxtiny = (1 << op->nbits) - 1;
14125 mintiny = - (1 << (op->nbits - 1));
14126 maxtiny = (1 << (op->nbits - 1)) - 1;
14129 sym_frag = symbol_get_frag (fragp->fr_symbol);
14130 val = S_GET_VALUE (fragp->fr_symbol);
14131 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14137 /* We won't have the section when we are called from
14138 mips_relax_frag. However, we will always have been called
14139 from md_estimate_size_before_relax first. If this is a
14140 branch to a different section, we mark it as such. If SEC is
14141 NULL, and the frag is not marked, then it must be a branch to
14142 the same section. */
14145 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14150 /* Must have been called from md_estimate_size_before_relax. */
14153 fragp->fr_subtype =
14154 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14156 /* FIXME: We should support this, and let the linker
14157 catch branches and loads that are out of range. */
14158 as_bad_where (fragp->fr_file, fragp->fr_line,
14159 _("unsupported PC relative reference to different section"));
14163 if (fragp != sym_frag && sym_frag->fr_address == 0)
14164 /* Assume non-extended on the first relaxation pass.
14165 The address we have calculated will be bogus if this is
14166 a forward branch to another frag, as the forward frag
14167 will have fr_address == 0. */
14171 /* In this case, we know for sure that the symbol fragment is in
14172 the same section. If the relax_marker of the symbol fragment
14173 differs from the relax_marker of this fragment, we have not
14174 yet adjusted the symbol fragment fr_address. We want to add
14175 in STRETCH in order to get a better estimate of the address.
14176 This particularly matters because of the shift bits. */
14178 && sym_frag->relax_marker != fragp->relax_marker)
14182 /* Adjust stretch for any alignment frag. Note that if have
14183 been expanding the earlier code, the symbol may be
14184 defined in what appears to be an earlier frag. FIXME:
14185 This doesn't handle the fr_subtype field, which specifies
14186 a maximum number of bytes to skip when doing an
14188 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14190 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14193 stretch = - ((- stretch)
14194 & ~ ((1 << (int) f->fr_offset) - 1));
14196 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14205 addr = fragp->fr_address + fragp->fr_fix;
14207 /* The base address rules are complicated. The base address of
14208 a branch is the following instruction. The base address of a
14209 PC relative load or add is the instruction itself, but if it
14210 is in a delay slot (in which case it can not be extended) use
14211 the address of the instruction whose delay slot it is in. */
14212 if (type == 'p' || type == 'q')
14216 /* If we are currently assuming that this frag should be
14217 extended, then, the current address is two bytes
14219 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14222 /* Ignore the low bit in the target, since it will be set
14223 for a text label. */
14224 if ((val & 1) != 0)
14227 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14229 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14232 val -= addr & ~ ((1 << op->shift) - 1);
14234 /* Branch offsets have an implicit 0 in the lowest bit. */
14235 if (type == 'p' || type == 'q')
14238 /* If any of the shifted bits are set, we must use an extended
14239 opcode. If the address depends on the size of this
14240 instruction, this can lead to a loop, so we arrange to always
14241 use an extended opcode. We only check this when we are in
14242 the main relaxation loop, when SEC is NULL. */
14243 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14245 fragp->fr_subtype =
14246 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14250 /* If we are about to mark a frag as extended because the value
14251 is precisely maxtiny + 1, then there is a chance of an
14252 infinite loop as in the following code:
14257 In this case when the la is extended, foo is 0x3fc bytes
14258 away, so the la can be shrunk, but then foo is 0x400 away, so
14259 the la must be extended. To avoid this loop, we mark the
14260 frag as extended if it was small, and is about to become
14261 extended with a value of maxtiny + 1. */
14262 if (val == ((maxtiny + 1) << op->shift)
14263 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14266 fragp->fr_subtype =
14267 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14271 else if (symsec != absolute_section && sec != NULL)
14272 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14274 if ((val & ((1 << op->shift) - 1)) != 0
14275 || val < (mintiny << op->shift)
14276 || val > (maxtiny << op->shift))
14282 /* Compute the length of a branch sequence, and adjust the
14283 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14284 worst-case length is computed, with UPDATE being used to indicate
14285 whether an unconditional (-1), branch-likely (+1) or regular (0)
14286 branch is to be computed. */
14288 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14290 bfd_boolean toofar;
14294 && S_IS_DEFINED (fragp->fr_symbol)
14295 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14300 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14302 addr = fragp->fr_address + fragp->fr_fix + 4;
14306 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14309 /* If the symbol is not defined or it's in a different segment,
14310 assume the user knows what's going on and emit a short
14316 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14318 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14319 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14320 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14321 RELAX_BRANCH_LINK (fragp->fr_subtype),
14327 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14330 if (mips_pic != NO_PIC)
14332 /* Additional space for PIC loading of target address. */
14334 if (mips_opts.isa == ISA_MIPS1)
14335 /* Additional space for $at-stabilizing nop. */
14339 /* If branch is conditional. */
14340 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14347 /* Estimate the size of a frag before relaxing. Unless this is the
14348 mips16, we are not really relaxing here, and the final size is
14349 encoded in the subtype information. For the mips16, we have to
14350 decide whether we are using an extended opcode or not. */
14353 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14357 if (RELAX_BRANCH_P (fragp->fr_subtype))
14360 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14362 return fragp->fr_var;
14365 if (RELAX_MIPS16_P (fragp->fr_subtype))
14366 /* We don't want to modify the EXTENDED bit here; it might get us
14367 into infinite loops. We change it only in mips_relax_frag(). */
14368 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14370 if (mips_pic == NO_PIC)
14371 change = nopic_need_relax (fragp->fr_symbol, 0);
14372 else if (mips_pic == SVR4_PIC)
14373 change = pic_need_relax (fragp->fr_symbol, segtype);
14374 else if (mips_pic == VXWORKS_PIC)
14375 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14382 fragp->fr_subtype |= RELAX_USE_SECOND;
14383 return -RELAX_FIRST (fragp->fr_subtype);
14386 return -RELAX_SECOND (fragp->fr_subtype);
14389 /* This is called to see whether a reloc against a defined symbol
14390 should be converted into a reloc against a section. */
14393 mips_fix_adjustable (fixS *fixp)
14395 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14396 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14399 if (fixp->fx_addsy == NULL)
14402 /* If symbol SYM is in a mergeable section, relocations of the form
14403 SYM + 0 can usually be made section-relative. The mergeable data
14404 is then identified by the section offset rather than by the symbol.
14406 However, if we're generating REL LO16 relocations, the offset is split
14407 between the LO16 and parterning high part relocation. The linker will
14408 need to recalculate the complete offset in order to correctly identify
14411 The linker has traditionally not looked for the parterning high part
14412 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14413 placed anywhere. Rather than break backwards compatibility by changing
14414 this, it seems better not to force the issue, and instead keep the
14415 original symbol. This will work with either linker behavior. */
14416 if ((lo16_reloc_p (fixp->fx_r_type)
14417 || reloc_needs_lo_p (fixp->fx_r_type))
14418 && HAVE_IN_PLACE_ADDENDS
14419 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14422 /* There is no place to store an in-place offset for JALR relocations.
14423 Likewise an in-range offset of PC-relative relocations may overflow
14424 the in-place relocatable field if recalculated against the start
14425 address of the symbol's containing section. */
14426 if (HAVE_IN_PLACE_ADDENDS
14427 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14431 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14432 to a floating-point stub. The same is true for non-R_MIPS16_26
14433 relocations against MIPS16 functions; in this case, the stub becomes
14434 the function's canonical address.
14436 Floating-point stubs are stored in unique .mips16.call.* or
14437 .mips16.fn.* sections. If a stub T for function F is in section S,
14438 the first relocation in section S must be against F; this is how the
14439 linker determines the target function. All relocations that might
14440 resolve to T must also be against F. We therefore have the following
14441 restrictions, which are given in an intentionally-redundant way:
14443 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14446 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14447 if that stub might be used.
14449 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14452 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14453 that stub might be used.
14455 There is a further restriction:
14457 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14458 on targets with in-place addends; the relocation field cannot
14459 encode the low bit.
14461 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14462 against a MIPS16 symbol.
14464 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14465 relocation against some symbol R, no relocation against R may be
14466 reduced. (Note that this deals with (2) as well as (1) because
14467 relocations against global symbols will never be reduced on ELF
14468 targets.) This approach is a little simpler than trying to detect
14469 stub sections, and gives the "all or nothing" per-symbol consistency
14470 that we have for MIPS16 symbols. */
14472 && fixp->fx_subsy == NULL
14473 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14474 || *symbol_get_tc (fixp->fx_addsy)))
14481 /* Translate internal representation of relocation info to BFD target
14485 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14487 static arelent *retval[4];
14489 bfd_reloc_code_real_type code;
14491 memset (retval, 0, sizeof(retval));
14492 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14493 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14494 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14495 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14497 if (fixp->fx_pcrel)
14499 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14501 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14502 Relocations want only the symbol offset. */
14503 reloc->addend = fixp->fx_addnumber + reloc->address;
14506 /* A gruesome hack which is a result of the gruesome gas
14507 reloc handling. What's worse, for COFF (as opposed to
14508 ECOFF), we might need yet another copy of reloc->address.
14509 See bfd_install_relocation. */
14510 reloc->addend += reloc->address;
14514 reloc->addend = fixp->fx_addnumber;
14516 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14517 entry to be used in the relocation's section offset. */
14518 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14520 reloc->address = reloc->addend;
14524 code = fixp->fx_r_type;
14526 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14527 if (reloc->howto == NULL)
14529 as_bad_where (fixp->fx_file, fixp->fx_line,
14530 _("Can not represent %s relocation in this object file format"),
14531 bfd_get_reloc_code_name (code));
14538 /* Relax a machine dependent frag. This returns the amount by which
14539 the current size of the frag should change. */
14542 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14544 if (RELAX_BRANCH_P (fragp->fr_subtype))
14546 offsetT old_var = fragp->fr_var;
14548 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14550 return fragp->fr_var - old_var;
14553 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14556 if (mips16_extended_frag (fragp, NULL, stretch))
14558 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14560 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14565 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14567 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14574 /* Convert a machine dependent frag. */
14577 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14579 if (RELAX_BRANCH_P (fragp->fr_subtype))
14582 unsigned long insn;
14586 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14588 if (target_big_endian)
14589 insn = bfd_getb32 (buf);
14591 insn = bfd_getl32 (buf);
14593 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14595 /* We generate a fixup instead of applying it right now
14596 because, if there are linker relaxations, we're going to
14597 need the relocations. */
14598 exp.X_op = O_symbol;
14599 exp.X_add_symbol = fragp->fr_symbol;
14600 exp.X_add_number = fragp->fr_offset;
14602 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14603 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14604 fixp->fx_file = fragp->fr_file;
14605 fixp->fx_line = fragp->fr_line;
14607 md_number_to_chars ((char *) buf, insn, 4);
14614 as_warn_where (fragp->fr_file, fragp->fr_line,
14615 _("Relaxed out-of-range branch into a jump"));
14617 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14620 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14622 /* Reverse the branch. */
14623 switch ((insn >> 28) & 0xf)
14626 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14627 have the condition reversed by tweaking a single
14628 bit, and their opcodes all have 0x4???????. */
14629 gas_assert ((insn & 0xf1000000) == 0x41000000);
14630 insn ^= 0x00010000;
14634 /* bltz 0x04000000 bgez 0x04010000
14635 bltzal 0x04100000 bgezal 0x04110000 */
14636 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14637 insn ^= 0x00010000;
14641 /* beq 0x10000000 bne 0x14000000
14642 blez 0x18000000 bgtz 0x1c000000 */
14643 insn ^= 0x04000000;
14651 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14653 /* Clear the and-link bit. */
14654 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14656 /* bltzal 0x04100000 bgezal 0x04110000
14657 bltzall 0x04120000 bgezall 0x04130000 */
14658 insn &= ~0x00100000;
14661 /* Branch over the branch (if the branch was likely) or the
14662 full jump (not likely case). Compute the offset from the
14663 current instruction to branch to. */
14664 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14668 /* How many bytes in instructions we've already emitted? */
14669 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14670 /* How many bytes in instructions from here to the end? */
14671 i = fragp->fr_var - i;
14673 /* Convert to instruction count. */
14675 /* Branch counts from the next instruction. */
14678 /* Branch over the jump. */
14679 md_number_to_chars ((char *) buf, insn, 4);
14683 md_number_to_chars ((char *) buf, 0, 4);
14686 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14688 /* beql $0, $0, 2f */
14690 /* Compute the PC offset from the current instruction to
14691 the end of the variable frag. */
14692 /* How many bytes in instructions we've already emitted? */
14693 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14694 /* How many bytes in instructions from here to the end? */
14695 i = fragp->fr_var - i;
14696 /* Convert to instruction count. */
14698 /* Don't decrement i, because we want to branch over the
14702 md_number_to_chars ((char *) buf, insn, 4);
14705 md_number_to_chars ((char *) buf, 0, 4);
14710 if (mips_pic == NO_PIC)
14713 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14714 ? 0x0c000000 : 0x08000000);
14715 exp.X_op = O_symbol;
14716 exp.X_add_symbol = fragp->fr_symbol;
14717 exp.X_add_number = fragp->fr_offset;
14719 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14720 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14721 fixp->fx_file = fragp->fr_file;
14722 fixp->fx_line = fragp->fr_line;
14724 md_number_to_chars ((char *) buf, insn, 4);
14729 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14731 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14732 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14733 insn |= at << OP_SH_RT;
14734 exp.X_op = O_symbol;
14735 exp.X_add_symbol = fragp->fr_symbol;
14736 exp.X_add_number = fragp->fr_offset;
14738 if (fragp->fr_offset)
14740 exp.X_add_symbol = make_expr_symbol (&exp);
14741 exp.X_add_number = 0;
14744 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14745 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14746 fixp->fx_file = fragp->fr_file;
14747 fixp->fx_line = fragp->fr_line;
14749 md_number_to_chars ((char *) buf, insn, 4);
14752 if (mips_opts.isa == ISA_MIPS1)
14755 md_number_to_chars ((char *) buf, 0, 4);
14759 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14760 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14761 insn |= at << OP_SH_RS | at << OP_SH_RT;
14763 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14764 4, &exp, FALSE, BFD_RELOC_LO16);
14765 fixp->fx_file = fragp->fr_file;
14766 fixp->fx_line = fragp->fr_line;
14768 md_number_to_chars ((char *) buf, insn, 4);
14772 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14776 insn |= at << OP_SH_RS;
14778 md_number_to_chars ((char *) buf, insn, 4);
14783 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14784 + fragp->fr_fix + fragp->fr_var);
14786 fragp->fr_fix += fragp->fr_var;
14791 if (RELAX_MIPS16_P (fragp->fr_subtype))
14794 const struct mips16_immed_operand *op;
14795 bfd_boolean small, ext;
14798 unsigned long insn;
14799 bfd_boolean use_extend;
14800 unsigned short extend;
14802 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14803 op = mips16_immed_operands;
14804 while (op->type != type)
14807 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14818 val = resolve_symbol_value (fragp->fr_symbol);
14823 addr = fragp->fr_address + fragp->fr_fix;
14825 /* The rules for the base address of a PC relative reloc are
14826 complicated; see mips16_extended_frag. */
14827 if (type == 'p' || type == 'q')
14832 /* Ignore the low bit in the target, since it will be
14833 set for a text label. */
14834 if ((val & 1) != 0)
14837 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14839 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14842 addr &= ~ (addressT) ((1 << op->shift) - 1);
14845 /* Make sure the section winds up with the alignment we have
14848 record_alignment (asec, op->shift);
14852 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14853 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14854 as_warn_where (fragp->fr_file, fragp->fr_line,
14855 _("extended instruction in delay slot"));
14857 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14859 if (target_big_endian)
14860 insn = bfd_getb16 (buf);
14862 insn = bfd_getl16 (buf);
14864 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14865 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14866 small, ext, &insn, &use_extend, &extend);
14870 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14871 fragp->fr_fix += 2;
14875 md_number_to_chars ((char *) buf, insn, 2);
14876 fragp->fr_fix += 2;
14884 first = RELAX_FIRST (fragp->fr_subtype);
14885 second = RELAX_SECOND (fragp->fr_subtype);
14886 fixp = (fixS *) fragp->fr_opcode;
14888 /* Possibly emit a warning if we've chosen the longer option. */
14889 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14890 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14892 const char *msg = macro_warning (fragp->fr_subtype);
14894 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14897 /* Go through all the fixups for the first sequence. Disable them
14898 (by marking them as done) if we're going to use the second
14899 sequence instead. */
14901 && fixp->fx_frag == fragp
14902 && fixp->fx_where < fragp->fr_fix - second)
14904 if (fragp->fr_subtype & RELAX_USE_SECOND)
14906 fixp = fixp->fx_next;
14909 /* Go through the fixups for the second sequence. Disable them if
14910 we're going to use the first sequence, otherwise adjust their
14911 addresses to account for the relaxation. */
14912 while (fixp && fixp->fx_frag == fragp)
14914 if (fragp->fr_subtype & RELAX_USE_SECOND)
14915 fixp->fx_where -= first;
14918 fixp = fixp->fx_next;
14921 /* Now modify the frag contents. */
14922 if (fragp->fr_subtype & RELAX_USE_SECOND)
14926 start = fragp->fr_literal + fragp->fr_fix - first - second;
14927 memmove (start, start + first, second);
14928 fragp->fr_fix -= first;
14931 fragp->fr_fix -= second;
14937 /* This function is called after the relocs have been generated.
14938 We've been storing mips16 text labels as odd. Here we convert them
14939 back to even for the convenience of the debugger. */
14942 mips_frob_file_after_relocs (void)
14945 unsigned int count, i;
14950 syms = bfd_get_outsymbols (stdoutput);
14951 count = bfd_get_symcount (stdoutput);
14952 for (i = 0; i < count; i++, syms++)
14954 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14955 && ((*syms)->value & 1) != 0)
14957 (*syms)->value &= ~1;
14958 /* If the symbol has an odd size, it was probably computed
14959 incorrectly, so adjust that as well. */
14960 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14961 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14968 /* This function is called whenever a label is defined, including fake
14969 labels instantiated off the dot special symbol. It is used when
14970 handling branch delays; if a branch has a label, we assume we cannot
14971 move it. This also bumps the value of the symbol by 1 in compressed
14975 mips_record_label (symbolS *sym)
14977 segment_info_type *si = seg_info (now_seg);
14978 struct insn_label_list *l;
14980 if (free_insn_labels == NULL)
14981 l = (struct insn_label_list *) xmalloc (sizeof *l);
14984 l = free_insn_labels;
14985 free_insn_labels = l->next;
14989 l->next = si->label_list;
14990 si->label_list = l;
14993 /* This function is called as tc_frob_label() whenever a label is defined
14994 and adds a DWARF-2 record we only want for true labels. */
14997 mips_define_label (symbolS *sym)
14999 mips_record_label (sym);
15001 dwarf2_emit_label (sym);
15005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15007 /* Some special processing for a MIPS ELF file. */
15010 mips_elf_final_processing (void)
15012 /* Write out the register information. */
15013 if (mips_abi != N64_ABI)
15017 s.ri_gprmask = mips_gprmask;
15018 s.ri_cprmask[0] = mips_cprmask[0];
15019 s.ri_cprmask[1] = mips_cprmask[1];
15020 s.ri_cprmask[2] = mips_cprmask[2];
15021 s.ri_cprmask[3] = mips_cprmask[3];
15022 /* The gp_value field is set by the MIPS ELF backend. */
15024 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15025 ((Elf32_External_RegInfo *)
15026 mips_regmask_frag));
15030 Elf64_Internal_RegInfo s;
15032 s.ri_gprmask = mips_gprmask;
15034 s.ri_cprmask[0] = mips_cprmask[0];
15035 s.ri_cprmask[1] = mips_cprmask[1];
15036 s.ri_cprmask[2] = mips_cprmask[2];
15037 s.ri_cprmask[3] = mips_cprmask[3];
15038 /* The gp_value field is set by the MIPS ELF backend. */
15040 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15041 ((Elf64_External_RegInfo *)
15042 mips_regmask_frag));
15045 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15046 sort of BFD interface for this. */
15047 if (mips_any_noreorder)
15048 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15049 if (mips_pic != NO_PIC)
15051 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15052 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15055 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15057 /* Set MIPS ELF flags for ASEs. */
15058 /* We may need to define a new flag for DSP ASE, and set this flag when
15059 file_ase_dsp is true. */
15060 /* Same for DSP R2. */
15061 /* We may need to define a new flag for MT ASE, and set this flag when
15062 file_ase_mt is true. */
15063 if (file_ase_mips16)
15064 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15065 #if 0 /* XXX FIXME */
15066 if (file_ase_mips3d)
15067 elf_elfheader (stdoutput)->e_flags |= ???;
15070 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15072 /* Set the MIPS ELF ABI flags. */
15073 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15074 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15075 else if (mips_abi == O64_ABI)
15076 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15077 else if (mips_abi == EABI_ABI)
15079 if (!file_mips_gp32)
15080 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15082 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15084 else if (mips_abi == N32_ABI)
15085 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15087 /* Nothing to do for N64_ABI. */
15089 if (mips_32bitmode)
15090 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15092 #if 0 /* XXX FIXME */
15093 /* 32 bit code with 64 bit FP registers. */
15094 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15095 elf_elfheader (stdoutput)->e_flags |= ???;
15099 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15101 typedef struct proc {
15103 symbolS *func_end_sym;
15104 unsigned long reg_mask;
15105 unsigned long reg_offset;
15106 unsigned long fpreg_mask;
15107 unsigned long fpreg_offset;
15108 unsigned long frame_offset;
15109 unsigned long frame_reg;
15110 unsigned long pc_reg;
15113 static procS cur_proc;
15114 static procS *cur_proc_ptr;
15115 static int numprocs;
15117 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15121 mips_nop_opcode (void)
15123 return seg_info (now_seg)->tc_segment_info_data.mips16;
15126 /* Fill in an rs_align_code fragment. This only needs to do something
15127 for MIPS16 code, where 0 is not a nop. */
15130 mips_handle_align (fragS *fragp)
15133 int bytes, size, excess;
15136 if (fragp->fr_type != rs_align_code)
15139 p = fragp->fr_literal + fragp->fr_fix;
15142 opcode = mips16_nop_insn.insn_opcode;
15147 opcode = nop_insn.insn_opcode;
15151 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15152 excess = bytes % size;
15155 /* If we're not inserting a whole number of instructions,
15156 pad the end of the fixed part of the frag with zeros. */
15157 memset (p, 0, excess);
15159 fragp->fr_fix += excess;
15162 md_number_to_chars (p, opcode, size);
15163 fragp->fr_var = size;
15167 md_obj_begin (void)
15174 /* Check for premature end, nesting errors, etc. */
15176 as_warn (_("missing .end at end of assembly"));
15185 if (*input_line_pointer == '-')
15187 ++input_line_pointer;
15190 if (!ISDIGIT (*input_line_pointer))
15191 as_bad (_("expected simple number"));
15192 if (input_line_pointer[0] == '0')
15194 if (input_line_pointer[1] == 'x')
15196 input_line_pointer += 2;
15197 while (ISXDIGIT (*input_line_pointer))
15200 val |= hex_value (*input_line_pointer++);
15202 return negative ? -val : val;
15206 ++input_line_pointer;
15207 while (ISDIGIT (*input_line_pointer))
15210 val |= *input_line_pointer++ - '0';
15212 return negative ? -val : val;
15215 if (!ISDIGIT (*input_line_pointer))
15217 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15218 *input_line_pointer, *input_line_pointer);
15219 as_warn (_("invalid number"));
15222 while (ISDIGIT (*input_line_pointer))
15225 val += *input_line_pointer++ - '0';
15227 return negative ? -val : val;
15230 /* The .file directive; just like the usual .file directive, but there
15231 is an initial number which is the ECOFF file index. In the non-ECOFF
15232 case .file implies DWARF-2. */
15235 s_mips_file (int x ATTRIBUTE_UNUSED)
15237 static int first_file_directive = 0;
15239 if (ECOFF_DEBUGGING)
15248 filename = dwarf2_directive_file (0);
15250 /* Versions of GCC up to 3.1 start files with a ".file"
15251 directive even for stabs output. Make sure that this
15252 ".file" is handled. Note that you need a version of GCC
15253 after 3.1 in order to support DWARF-2 on MIPS. */
15254 if (filename != NULL && ! first_file_directive)
15256 (void) new_logical_line (filename, -1);
15257 s_app_file_string (filename, 0);
15259 first_file_directive = 1;
15263 /* The .loc directive, implying DWARF-2. */
15266 s_mips_loc (int x ATTRIBUTE_UNUSED)
15268 if (!ECOFF_DEBUGGING)
15269 dwarf2_directive_loc (0);
15272 /* The .end directive. */
15275 s_mips_end (int x ATTRIBUTE_UNUSED)
15279 /* Following functions need their own .frame and .cprestore directives. */
15280 mips_frame_reg_valid = 0;
15281 mips_cprestore_valid = 0;
15283 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15286 demand_empty_rest_of_line ();
15291 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15292 as_warn (_(".end not in text section"));
15296 as_warn (_(".end directive without a preceding .ent directive."));
15297 demand_empty_rest_of_line ();
15303 gas_assert (S_GET_NAME (p));
15304 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15305 as_warn (_(".end symbol does not match .ent symbol."));
15307 if (debug_type == DEBUG_STABS)
15308 stabs_generate_asm_endfunc (S_GET_NAME (p),
15312 as_warn (_(".end directive missing or unknown symbol"));
15315 /* Create an expression to calculate the size of the function. */
15316 if (p && cur_proc_ptr)
15318 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15319 expressionS *exp = xmalloc (sizeof (expressionS));
15322 exp->X_op = O_subtract;
15323 exp->X_add_symbol = symbol_temp_new_now ();
15324 exp->X_op_symbol = p;
15325 exp->X_add_number = 0;
15327 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15330 /* Generate a .pdr section. */
15331 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15333 segT saved_seg = now_seg;
15334 subsegT saved_subseg = now_subseg;
15338 #ifdef md_flush_pending_output
15339 md_flush_pending_output ();
15342 gas_assert (pdr_seg);
15343 subseg_set (pdr_seg, 0);
15345 /* Write the symbol. */
15346 exp.X_op = O_symbol;
15347 exp.X_add_symbol = p;
15348 exp.X_add_number = 0;
15349 emit_expr (&exp, 4);
15351 fragp = frag_more (7 * 4);
15353 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15354 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15355 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15356 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15357 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15358 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15359 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15361 subseg_set (saved_seg, saved_subseg);
15363 #endif /* OBJ_ELF */
15365 cur_proc_ptr = NULL;
15368 /* The .aent and .ent directives. */
15371 s_mips_ent (int aent)
15375 symbolP = get_symbol ();
15376 if (*input_line_pointer == ',')
15377 ++input_line_pointer;
15378 SKIP_WHITESPACE ();
15379 if (ISDIGIT (*input_line_pointer)
15380 || *input_line_pointer == '-')
15383 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15384 as_warn (_(".ent or .aent not in text section."));
15386 if (!aent && cur_proc_ptr)
15387 as_warn (_("missing .end"));
15391 /* This function needs its own .frame and .cprestore directives. */
15392 mips_frame_reg_valid = 0;
15393 mips_cprestore_valid = 0;
15395 cur_proc_ptr = &cur_proc;
15396 memset (cur_proc_ptr, '\0', sizeof (procS));
15398 cur_proc_ptr->func_sym = symbolP;
15402 if (debug_type == DEBUG_STABS)
15403 stabs_generate_asm_func (S_GET_NAME (symbolP),
15404 S_GET_NAME (symbolP));
15407 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15409 demand_empty_rest_of_line ();
15412 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15413 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15414 s_mips_frame is used so that we can set the PDR information correctly.
15415 We can't use the ecoff routines because they make reference to the ecoff
15416 symbol table (in the mdebug section). */
15419 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15422 if (IS_ELF && !ECOFF_DEBUGGING)
15426 if (cur_proc_ptr == (procS *) NULL)
15428 as_warn (_(".frame outside of .ent"));
15429 demand_empty_rest_of_line ();
15433 cur_proc_ptr->frame_reg = tc_get_register (1);
15435 SKIP_WHITESPACE ();
15436 if (*input_line_pointer++ != ','
15437 || get_absolute_expression_and_terminator (&val) != ',')
15439 as_warn (_("Bad .frame directive"));
15440 --input_line_pointer;
15441 demand_empty_rest_of_line ();
15445 cur_proc_ptr->frame_offset = val;
15446 cur_proc_ptr->pc_reg = tc_get_register (0);
15448 demand_empty_rest_of_line ();
15451 #endif /* OBJ_ELF */
15455 /* The .fmask and .mask directives. If the mdebug section is present
15456 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15457 embedded targets, s_mips_mask is used so that we can set the PDR
15458 information correctly. We can't use the ecoff routines because they
15459 make reference to the ecoff symbol table (in the mdebug section). */
15462 s_mips_mask (int reg_type)
15465 if (IS_ELF && !ECOFF_DEBUGGING)
15469 if (cur_proc_ptr == (procS *) NULL)
15471 as_warn (_(".mask/.fmask outside of .ent"));
15472 demand_empty_rest_of_line ();
15476 if (get_absolute_expression_and_terminator (&mask) != ',')
15478 as_warn (_("Bad .mask/.fmask directive"));
15479 --input_line_pointer;
15480 demand_empty_rest_of_line ();
15484 off = get_absolute_expression ();
15486 if (reg_type == 'F')
15488 cur_proc_ptr->fpreg_mask = mask;
15489 cur_proc_ptr->fpreg_offset = off;
15493 cur_proc_ptr->reg_mask = mask;
15494 cur_proc_ptr->reg_offset = off;
15497 demand_empty_rest_of_line ();
15500 #endif /* OBJ_ELF */
15501 s_ignore (reg_type);
15504 /* A table describing all the processors gas knows about. Names are
15505 matched in the order listed.
15507 To ease comparison, please keep this table in the same order as
15508 gcc's mips_cpu_info_table[]. */
15509 static const struct mips_cpu_info mips_cpu_info_table[] =
15511 /* Entries for generic ISAs */
15512 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15513 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15514 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15515 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15516 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15517 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15518 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15519 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15520 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15523 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15524 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15525 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15528 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15531 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15532 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15533 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15534 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15535 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15536 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15537 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15538 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15539 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15540 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15541 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15542 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15543 /* ST Microelectronics Loongson 2E and 2F cores */
15544 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15545 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15548 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15549 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15550 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15551 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15552 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15553 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15554 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15555 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15556 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15557 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15558 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15559 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15560 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15561 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15562 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15565 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15566 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15567 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15568 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15570 /* MIPS 32 Release 2 */
15571 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15572 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15573 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15574 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15575 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15576 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15577 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15578 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15579 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15580 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15581 /* Deprecated forms of the above. */
15582 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15583 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15584 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15585 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15586 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15587 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15588 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15589 /* Deprecated forms of the above. */
15590 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15591 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15592 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15593 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15594 ISA_MIPS32R2, CPU_MIPS32R2 },
15595 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15596 ISA_MIPS32R2, CPU_MIPS32R2 },
15597 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15598 ISA_MIPS32R2, CPU_MIPS32R2 },
15599 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15600 ISA_MIPS32R2, CPU_MIPS32R2 },
15601 /* Deprecated forms of the above. */
15602 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15603 ISA_MIPS32R2, CPU_MIPS32R2 },
15604 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15605 ISA_MIPS32R2, CPU_MIPS32R2 },
15606 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15607 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15608 ISA_MIPS32R2, CPU_MIPS32R2 },
15609 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15610 ISA_MIPS32R2, CPU_MIPS32R2 },
15611 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15612 ISA_MIPS32R2, CPU_MIPS32R2 },
15613 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15614 ISA_MIPS32R2, CPU_MIPS32R2 },
15615 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15616 ISA_MIPS32R2, CPU_MIPS32R2 },
15617 /* Deprecated forms of the above. */
15618 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15619 ISA_MIPS32R2, CPU_MIPS32R2 },
15620 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15621 ISA_MIPS32R2, CPU_MIPS32R2 },
15622 /* 1004K cores are multiprocessor versions of the 34K. */
15623 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15624 ISA_MIPS32R2, CPU_MIPS32R2 },
15625 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15626 ISA_MIPS32R2, CPU_MIPS32R2 },
15627 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15628 ISA_MIPS32R2, CPU_MIPS32R2 },
15629 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15630 ISA_MIPS32R2, CPU_MIPS32R2 },
15633 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15634 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15635 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15636 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15638 /* Broadcom SB-1 CPU core */
15639 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15640 ISA_MIPS64, CPU_SB1 },
15641 /* Broadcom SB-1A CPU core */
15642 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15643 ISA_MIPS64, CPU_SB1 },
15645 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15647 /* MIPS 64 Release 2 */
15649 /* Cavium Networks Octeon CPU core */
15650 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15653 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15660 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15661 with a final "000" replaced by "k". Ignore case.
15663 Note: this function is shared between GCC and GAS. */
15666 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15668 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15669 given++, canonical++;
15671 return ((*given == 0 && *canonical == 0)
15672 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15676 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15677 CPU name. We've traditionally allowed a lot of variation here.
15679 Note: this function is shared between GCC and GAS. */
15682 mips_matching_cpu_name_p (const char *canonical, const char *given)
15684 /* First see if the name matches exactly, or with a final "000"
15685 turned into "k". */
15686 if (mips_strict_matching_cpu_name_p (canonical, given))
15689 /* If not, try comparing based on numerical designation alone.
15690 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15691 if (TOLOWER (*given) == 'r')
15693 if (!ISDIGIT (*given))
15696 /* Skip over some well-known prefixes in the canonical name,
15697 hoping to find a number there too. */
15698 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15700 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15702 else if (TOLOWER (canonical[0]) == 'r')
15705 return mips_strict_matching_cpu_name_p (canonical, given);
15709 /* Parse an option that takes the name of a processor as its argument.
15710 OPTION is the name of the option and CPU_STRING is the argument.
15711 Return the corresponding processor enumeration if the CPU_STRING is
15712 recognized, otherwise report an error and return null.
15714 A similar function exists in GCC. */
15716 static const struct mips_cpu_info *
15717 mips_parse_cpu (const char *option, const char *cpu_string)
15719 const struct mips_cpu_info *p;
15721 /* 'from-abi' selects the most compatible architecture for the given
15722 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15723 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15724 version. Look first at the -mgp options, if given, otherwise base
15725 the choice on MIPS_DEFAULT_64BIT.
15727 Treat NO_ABI like the EABIs. One reason to do this is that the
15728 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15729 architecture. This code picks MIPS I for 'mips' and MIPS III for
15730 'mips64', just as we did in the days before 'from-abi'. */
15731 if (strcasecmp (cpu_string, "from-abi") == 0)
15733 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15734 return mips_cpu_info_from_isa (ISA_MIPS1);
15736 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15737 return mips_cpu_info_from_isa (ISA_MIPS3);
15739 if (file_mips_gp32 >= 0)
15740 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15742 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15747 /* 'default' has traditionally been a no-op. Probably not very useful. */
15748 if (strcasecmp (cpu_string, "default") == 0)
15751 for (p = mips_cpu_info_table; p->name != 0; p++)
15752 if (mips_matching_cpu_name_p (p->name, cpu_string))
15755 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15759 /* Return the canonical processor information for ISA (a member of the
15760 ISA_MIPS* enumeration). */
15762 static const struct mips_cpu_info *
15763 mips_cpu_info_from_isa (int isa)
15767 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15768 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15769 && isa == mips_cpu_info_table[i].isa)
15770 return (&mips_cpu_info_table[i]);
15775 static const struct mips_cpu_info *
15776 mips_cpu_info_from_arch (int arch)
15780 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15781 if (arch == mips_cpu_info_table[i].cpu)
15782 return (&mips_cpu_info_table[i]);
15788 show (FILE *stream, const char *string, int *col_p, int *first_p)
15792 fprintf (stream, "%24s", "");
15797 fprintf (stream, ", ");
15801 if (*col_p + strlen (string) > 72)
15803 fprintf (stream, "\n%24s", "");
15807 fprintf (stream, "%s", string);
15808 *col_p += strlen (string);
15814 md_show_usage (FILE *stream)
15819 fprintf (stream, _("\
15821 -EB generate big endian output\n\
15822 -EL generate little endian output\n\
15823 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15824 -G NUM allow referencing objects up to NUM bytes\n\
15825 implicitly with the gp register [default 8]\n"));
15826 fprintf (stream, _("\
15827 -mips1 generate MIPS ISA I instructions\n\
15828 -mips2 generate MIPS ISA II instructions\n\
15829 -mips3 generate MIPS ISA III instructions\n\
15830 -mips4 generate MIPS ISA IV instructions\n\
15831 -mips5 generate MIPS ISA V instructions\n\
15832 -mips32 generate MIPS32 ISA instructions\n\
15833 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15834 -mips64 generate MIPS64 ISA instructions\n\
15835 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15836 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15840 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15841 show (stream, mips_cpu_info_table[i].name, &column, &first);
15842 show (stream, "from-abi", &column, &first);
15843 fputc ('\n', stream);
15845 fprintf (stream, _("\
15846 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15847 -no-mCPU don't generate code specific to CPU.\n\
15848 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15852 show (stream, "3900", &column, &first);
15853 show (stream, "4010", &column, &first);
15854 show (stream, "4100", &column, &first);
15855 show (stream, "4650", &column, &first);
15856 fputc ('\n', stream);
15858 fprintf (stream, _("\
15859 -mips16 generate mips16 instructions\n\
15860 -no-mips16 do not generate mips16 instructions\n"));
15861 fprintf (stream, _("\
15862 -msmartmips generate smartmips instructions\n\
15863 -mno-smartmips do not generate smartmips instructions\n"));
15864 fprintf (stream, _("\
15865 -mdsp generate DSP instructions\n\
15866 -mno-dsp do not generate DSP instructions\n"));
15867 fprintf (stream, _("\
15868 -mdspr2 generate DSP R2 instructions\n\
15869 -mno-dspr2 do not generate DSP R2 instructions\n"));
15870 fprintf (stream, _("\
15871 -mmt generate MT instructions\n\
15872 -mno-mt do not generate MT instructions\n"));
15873 fprintf (stream, _("\
15874 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15875 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15876 -mfix-vr4120 work around certain VR4120 errata\n\
15877 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15878 -mfix-24k insert a nop after ERET and DERET instructions\n\
15879 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15880 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15881 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15882 -msym32 assume all symbols have 32-bit values\n\
15883 -O0 remove unneeded NOPs, do not swap branches\n\
15884 -O remove unneeded NOPs and swap branches\n\
15885 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15886 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15887 fprintf (stream, _("\
15888 -mhard-float allow floating-point instructions\n\
15889 -msoft-float do not allow floating-point instructions\n\
15890 -msingle-float only allow 32-bit floating-point operations\n\
15891 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15892 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15895 fprintf (stream, _("\
15896 -KPIC, -call_shared generate SVR4 position independent code\n\
15897 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15898 -mvxworks-pic generate VxWorks position independent code\n\
15899 -non_shared do not generate code that can operate with DSOs\n\
15900 -xgot assume a 32 bit GOT\n\
15901 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15902 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15903 position dependent (non shared) code\n\
15904 -mabi=ABI create ABI conformant object file for:\n"));
15908 show (stream, "32", &column, &first);
15909 show (stream, "o64", &column, &first);
15910 show (stream, "n32", &column, &first);
15911 show (stream, "64", &column, &first);
15912 show (stream, "eabi", &column, &first);
15914 fputc ('\n', stream);
15916 fprintf (stream, _("\
15917 -32 create o32 ABI object file (default)\n\
15918 -n32 create n32 ABI object file\n\
15919 -64 create 64 ABI object file\n"));
15925 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15927 if (HAVE_64BIT_SYMBOLS)
15928 return dwarf2_format_64bit_irix;
15930 return dwarf2_format_32bit;
15935 mips_dwarf2_addr_size (void)
15937 if (HAVE_64BIT_OBJECTS)
15943 /* Standard calling conventions leave the CFA at SP on entry. */
15945 mips_cfi_frame_initial_instructions (void)
15947 cfi_add_CFA_def_cfa_register (SP);
15951 tc_mips_regname_to_dw2regnum (char *regname)
15953 unsigned int regnum = -1;
15956 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))