1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug = -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi = NO_ABI;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32 = -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32 = -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts =
194 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask;
201 unsigned long mips_cprmask[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa = ISA_UNKNOWN;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch = CPU_UNKNOWN;
220 static const char *mips_arch_string;
221 static const struct mips_cpu_info *mips_arch_info;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune = CPU_UNKNOWN;
226 static const char *mips_tune_string;
227 static const struct mips_cpu_info *mips_tune_info;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode = 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
289 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
291 /* Return true if the given CPU supports the MIPS3D ASE. */
292 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
295 /* Return true if the given CPU supports the MDMX ASE. */
296 #define CPU_HAS_MDMX(cpu) (false \
299 /* True if CPU has a dror instruction. */
300 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
302 /* True if CPU has a ror instruction. */
303 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
305 /* Whether the processor uses hardware interlocks to protect
306 reads from the HI and LO registers, and thus does not
307 require nops to be inserted. */
309 #define hilo_interlocks (mips_arch == CPU_R4010 \
310 || mips_arch == CPU_VR5500 \
311 || mips_arch == CPU_SB1 \
314 /* Whether the processor uses hardware interlocks to protect reads
315 from the GPRs, and thus does not require nops to be inserted. */
316 #define gpr_interlocks \
317 (mips_opts.isa != ISA_MIPS1 \
318 || mips_arch == CPU_VR5400 \
319 || mips_arch == CPU_VR5500 \
320 || mips_arch == CPU_R3900)
322 /* As with other "interlocks" this is used by hardware that has FP
323 (co-processor) interlocks. */
324 /* Itbl support may require additional care here. */
325 #define cop_interlocks (mips_arch == CPU_R4300 \
326 || mips_arch == CPU_VR5400 \
327 || mips_arch == CPU_VR5500 \
328 || mips_arch == CPU_SB1 \
331 /* Is this a mfhi or mflo instruction? */
332 #define MF_HILO_INSN(PINFO) \
333 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
335 /* MIPS PIC level. */
337 enum mips_pic_level mips_pic;
339 /* Warn about all NOPS that the assembler generates. */
340 static int warn_nops = 0;
342 /* 1 if we should generate 32 bit offsets from the $gp register in
343 SVR4_PIC mode. Currently has no meaning in other modes. */
344 static int mips_big_got = 0;
346 /* 1 if trap instructions should used for overflow rather than break
348 static int mips_trap = 0;
350 /* 1 if double width floating point constants should not be constructed
351 by assembling two single width halves into two single width floating
352 point registers which just happen to alias the double width destination
353 register. On some architectures this aliasing can be disabled by a bit
354 in the status register, and the setting of this bit cannot be determined
355 automatically at assemble time. */
356 static int mips_disable_float_construction;
358 /* Non-zero if any .set noreorder directives were used. */
360 static int mips_any_noreorder;
362 /* Non-zero if nops should be inserted when the register referenced in
363 an mfhi/mflo instruction is read in the next two instructions. */
364 static int mips_7000_hilo_fix;
366 /* The size of the small data section. */
367 static unsigned int g_switch_value = 8;
368 /* Whether the -G option was used. */
369 static int g_switch_seen = 0;
374 /* If we can determine in advance that GP optimization won't be
375 possible, we can skip the relaxation stuff that tries to produce
376 GP-relative references. This makes delay slot optimization work
379 This function can only provide a guess, but it seems to work for
380 gcc output. It needs to guess right for gcc, otherwise gcc
381 will put what it thinks is a GP-relative instruction in a branch
384 I don't know if a fix is needed for the SVR4_PIC mode. I've only
385 fixed it for the non-PIC mode. KR 95/04/07 */
386 static int nopic_need_relax PARAMS ((symbolS *, int));
388 /* handle of the OPCODE hash table */
389 static struct hash_control *op_hash = NULL;
391 /* The opcode hash table we use for the mips16. */
392 static struct hash_control *mips16_op_hash = NULL;
394 /* This array holds the chars that always start a comment. If the
395 pre-processor is disabled, these aren't very useful */
396 const char comment_chars[] = "#";
398 /* This array holds the chars that only start a comment at the beginning of
399 a line. If the line seems to have the form '# 123 filename'
400 .line and .file directives will appear in the pre-processed output */
401 /* Note that input_file.c hand checks for '#' at the beginning of the
402 first line of the input file. This is because the compiler outputs
403 #NO_APP at the beginning of its output. */
404 /* Also note that C style comments are always supported. */
405 const char line_comment_chars[] = "#";
407 /* This array holds machine specific line separator characters. */
408 const char line_separator_chars[] = ";";
410 /* Chars that can be used to separate mant from exp in floating point nums */
411 const char EXP_CHARS[] = "eE";
413 /* Chars that mean this number is a floating point constant */
416 const char FLT_CHARS[] = "rRsSfFdDxXpP";
418 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
419 changed in read.c . Ideally it shouldn't have to know about it at all,
420 but nothing is ideal around here.
423 static char *insn_error;
425 static int auto_align = 1;
427 /* When outputting SVR4 PIC code, the assembler needs to know the
428 offset in the stack frame from which to restore the $gp register.
429 This is set by the .cprestore pseudo-op, and saved in this
431 static offsetT mips_cprestore_offset = -1;
433 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
434 more optimizations, it can use a register value instead of a memory-saved
435 offset and even an other register than $gp as global pointer. */
436 static offsetT mips_cpreturn_offset = -1;
437 static int mips_cpreturn_register = -1;
438 static int mips_gp_register = GP;
439 static int mips_gprel_offset = 0;
441 /* Whether mips_cprestore_offset has been set in the current function
442 (or whether it has already been warned about, if not). */
443 static int mips_cprestore_valid = 0;
445 /* This is the register which holds the stack frame, as set by the
446 .frame pseudo-op. This is needed to implement .cprestore. */
447 static int mips_frame_reg = SP;
449 /* Whether mips_frame_reg has been set in the current function
450 (or whether it has already been warned about, if not). */
451 static int mips_frame_reg_valid = 0;
453 /* To output NOP instructions correctly, we need to keep information
454 about the previous two instructions. */
456 /* Whether we are optimizing. The default value of 2 means to remove
457 unneeded NOPs and swap branch instructions when possible. A value
458 of 1 means to not swap branches. A value of 0 means to always
460 static int mips_optimize = 2;
462 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
463 equivalent to seeing no -g option at all. */
464 static int mips_debug = 0;
466 /* The previous instruction. */
467 static struct mips_cl_insn prev_insn;
469 /* The instruction before prev_insn. */
470 static struct mips_cl_insn prev_prev_insn;
472 /* If we don't want information for prev_insn or prev_prev_insn, we
473 point the insn_mo field at this dummy integer. */
474 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
476 /* Non-zero if prev_insn is valid. */
477 static int prev_insn_valid;
479 /* The frag for the previous instruction. */
480 static struct frag *prev_insn_frag;
482 /* The offset into prev_insn_frag for the previous instruction. */
483 static long prev_insn_where;
485 /* The reloc type for the previous instruction, if any. */
486 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
488 /* The reloc for the previous instruction, if any. */
489 static fixS *prev_insn_fixp[3];
491 /* Non-zero if the previous instruction was in a delay slot. */
492 static int prev_insn_is_delay_slot;
494 /* Non-zero if the previous instruction was in a .set noreorder. */
495 static int prev_insn_unreordered;
497 /* Non-zero if the previous instruction uses an extend opcode (if
499 static int prev_insn_extended;
501 /* Non-zero if the previous previous instruction was in a .set
503 static int prev_prev_insn_unreordered;
505 /* If this is set, it points to a frag holding nop instructions which
506 were inserted before the start of a noreorder section. If those
507 nops turn out to be unnecessary, the size of the frag can be
509 static fragS *prev_nop_frag;
511 /* The number of nop instructions we created in prev_nop_frag. */
512 static int prev_nop_frag_holds;
514 /* The number of nop instructions that we know we need in
516 static int prev_nop_frag_required;
518 /* The number of instructions we've seen since prev_nop_frag. */
519 static int prev_nop_frag_since;
521 /* For ECOFF and ELF, relocations against symbols are done in two
522 parts, with a HI relocation and a LO relocation. Each relocation
523 has only 16 bits of space to store an addend. This means that in
524 order for the linker to handle carries correctly, it must be able
525 to locate both the HI and the LO relocation. This means that the
526 relocations must appear in order in the relocation table.
528 In order to implement this, we keep track of each unmatched HI
529 relocation. We then sort them so that they immediately precede the
530 corresponding LO relocation. */
535 struct mips_hi_fixup *next;
538 /* The section this fixup is in. */
542 /* The list of unmatched HI relocs. */
544 static struct mips_hi_fixup *mips_hi_fixup_list;
546 /* Map normal MIPS register numbers to mips16 register numbers. */
548 #define X ILLEGAL_REG
549 static const int mips32_to_16_reg_map[] =
551 X, X, 2, 3, 4, 5, 6, 7,
552 X, X, X, X, X, X, X, X,
553 0, 1, X, X, X, X, X, X,
554 X, X, X, X, X, X, X, X
558 /* Map mips16 register numbers to normal MIPS register numbers. */
560 static const unsigned int mips16_to_32_reg_map[] =
562 16, 17, 2, 3, 4, 5, 6, 7
565 static int mips_fix_4122_bugs;
567 /* We don't relax branches by default, since this causes us to expand
568 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
569 fail to compute the offset before expanding the macro to the most
570 efficient expansion. */
572 static int mips_relax_branch;
574 /* Since the MIPS does not have multiple forms of PC relative
575 instructions, we do not have to do relaxing as is done on other
576 platforms. However, we do have to handle GP relative addressing
577 correctly, which turns out to be a similar problem.
579 Every macro that refers to a symbol can occur in (at least) two
580 forms, one with GP relative addressing and one without. For
581 example, loading a global variable into a register generally uses
582 a macro instruction like this:
584 If i can be addressed off the GP register (this is true if it is in
585 the .sbss or .sdata section, or if it is known to be smaller than
586 the -G argument) this will generate the following instruction:
588 This instruction will use a GPREL reloc. If i can not be addressed
589 off the GP register, the following instruction sequence will be used:
592 In this case the first instruction will have a HI16 reloc, and the
593 second reloc will have a LO16 reloc. Both relocs will be against
596 The issue here is that we may not know whether i is GP addressable
597 until after we see the instruction that uses it. Therefore, we
598 want to be able to choose the final instruction sequence only at
599 the end of the assembly. This is similar to the way other
600 platforms choose the size of a PC relative instruction only at the
603 When generating position independent code we do not use GP
604 addressing in quite the same way, but the issue still arises as
605 external symbols and local symbols must be handled differently.
607 We handle these issues by actually generating both possible
608 instruction sequences. The longer one is put in a frag_var with
609 type rs_machine_dependent. We encode what to do with the frag in
610 the subtype field. We encode (1) the number of existing bytes to
611 replace, (2) the number of new bytes to use, (3) the offset from
612 the start of the existing bytes to the first reloc we must generate
613 (that is, the offset is applied from the start of the existing
614 bytes after they are replaced by the new bytes, if any), (4) the
615 offset from the start of the existing bytes to the second reloc,
616 (5) whether a third reloc is needed (the third reloc is always four
617 bytes after the second reloc), and (6) whether to warn if this
618 variant is used (this is sometimes needed if .set nomacro or .set
619 noat is in effect). All these numbers are reasonably small.
621 Generating two instruction sequences must be handled carefully to
622 ensure that delay slots are handled correctly. Fortunately, there
623 are a limited number of cases. When the second instruction
624 sequence is generated, append_insn is directed to maintain the
625 existing delay slot information, so it continues to apply to any
626 code after the second instruction sequence. This means that the
627 second instruction sequence must not impose any requirements not
628 required by the first instruction sequence.
630 These variant frags are then handled in functions called by the
631 machine independent code. md_estimate_size_before_relax returns
632 the final size of the frag. md_convert_frag sets up the final form
633 of the frag. tc_gen_reloc adjust the first reloc and adds a second
635 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
639 | (((reloc1) + 64) << 9) \
640 | (((reloc2) + 64) << 2) \
641 | ((reloc3) ? (1 << 1) : 0) \
643 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
644 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
645 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
646 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
647 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
648 #define RELAX_WARN(i) ((i) & 1)
650 /* Branch without likely bit. If label is out of range, we turn:
652 beq reg1, reg2, label
662 with the following opcode replacements:
669 bltzal <-> bgezal (with jal label instead of j label)
671 Even though keeping the delay slot instruction in the delay slot of
672 the branch would be more efficient, it would be very tricky to do
673 correctly, because we'd have to introduce a variable frag *after*
674 the delay slot instruction, and expand that instead. Let's do it
675 the easy way for now, even if the branch-not-taken case now costs
676 one additional instruction. Out-of-range branches are not supposed
677 to be common, anyway.
679 Branch likely. If label is out of range, we turn:
681 beql reg1, reg2, label
682 delay slot (annulled if branch not taken)
691 delay slot (executed only if branch taken)
694 It would be possible to generate a shorter sequence by losing the
695 likely bit, generating something like:
700 delay slot (executed only if branch taken)
712 bltzall -> bgezal (with jal label instead of j label)
713 bgezall -> bltzal (ditto)
716 but it's not clear that it would actually improve performance. */
717 #define RELAX_BRANCH_ENCODE(reloc_s2, uncond, likely, link, toofar) \
720 | ((toofar) ? 1 : 0) \
722 | ((likely) ? 4 : 0) \
723 | ((uncond) ? 8 : 0) \
724 | ((reloc_s2) ? 16 : 0)))
725 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
726 #define RELAX_BRANCH_RELOC_S2(i) (((i) & 16) != 0)
727 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
728 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
729 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
730 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1))
732 /* For mips16 code, we use an entirely different form of relaxation.
733 mips16 supports two versions of most instructions which take
734 immediate values: a small one which takes some small value, and a
735 larger one which takes a 16 bit value. Since branches also follow
736 this pattern, relaxing these values is required.
738 We can assemble both mips16 and normal MIPS code in a single
739 object. Therefore, we need to support this type of relaxation at
740 the same time that we support the relaxation described above. We
741 use the high bit of the subtype field to distinguish these cases.
743 The information we store for this type of relaxation is the
744 argument code found in the opcode file for this relocation, whether
745 the user explicitly requested a small or extended form, and whether
746 the relocation is in a jump or jal delay slot. That tells us the
747 size of the value, and how it should be stored. We also store
748 whether the fragment is considered to be extended or not. We also
749 store whether this is known to be a branch to a different section,
750 whether we have tried to relax this frag yet, and whether we have
751 ever extended a PC relative fragment because of a shift count. */
752 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
755 | ((small) ? 0x100 : 0) \
756 | ((ext) ? 0x200 : 0) \
757 | ((dslot) ? 0x400 : 0) \
758 | ((jal_dslot) ? 0x800 : 0))
759 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
760 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
761 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
762 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
763 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
764 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
765 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
766 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
767 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
768 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
769 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
770 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
772 /* Is the given value a sign-extended 32-bit value? */
773 #define IS_SEXT_32BIT_NUM(x) \
774 (((x) &~ (offsetT) 0x7fffffff) == 0 \
775 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
777 /* Is the given value a sign-extended 16-bit value? */
778 #define IS_SEXT_16BIT_NUM(x) \
779 (((x) &~ (offsetT) 0x7fff) == 0 \
780 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
783 /* Prototypes for static functions. */
786 #define internalError() \
787 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
789 #define internalError() as_fatal (_("MIPS internal Error"));
792 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
794 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
795 unsigned int reg, enum mips_regclass class));
796 static int reg_needs_delay PARAMS ((unsigned int));
797 static void mips16_mark_labels PARAMS ((void));
798 static void append_insn PARAMS ((char *place,
799 struct mips_cl_insn * ip,
801 bfd_reloc_code_real_type *r,
803 static void mips_no_prev_insn PARAMS ((int));
804 static void mips_emit_delays PARAMS ((boolean));
806 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
807 const char *name, const char *fmt,
810 static void macro_build ();
812 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
813 const char *, const char *,
815 static void macro_build_jalr PARAMS ((int, expressionS *));
816 static void macro_build_lui PARAMS ((char *place, int *counter,
817 expressionS * ep, int regnum));
818 static void macro_build_ldst_constoffset PARAMS ((char *place, int *counter,
819 expressionS * ep, const char *op,
820 int valreg, int breg));
821 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
822 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
824 static void load_register PARAMS ((int *, int, expressionS *, int));
825 static void load_address PARAMS ((int *, int, expressionS *, int *));
826 static void move_register PARAMS ((int *, int, int));
827 static void macro PARAMS ((struct mips_cl_insn * ip));
828 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
829 #ifdef LOSING_COMPILER
830 static void macro2 PARAMS ((struct mips_cl_insn * ip));
832 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
833 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
834 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
835 boolean, boolean, unsigned long *,
836 boolean *, unsigned short *));
837 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
838 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
839 static int my_getSmallExpression PARAMS ((expressionS *, char *));
840 static void my_getExpression PARAMS ((expressionS *, char *));
842 static int support_64bit_objects PARAMS((void));
844 static void mips_set_option_string PARAMS ((const char **, const char *));
845 static symbolS *get_symbol PARAMS ((void));
846 static void mips_align PARAMS ((int to, int fill, symbolS *label));
847 static void s_align PARAMS ((int));
848 static void s_change_sec PARAMS ((int));
849 static void s_change_section PARAMS ((int));
850 static void s_cons PARAMS ((int));
851 static void s_float_cons PARAMS ((int));
852 static void s_mips_globl PARAMS ((int));
853 static void s_option PARAMS ((int));
854 static void s_mipsset PARAMS ((int));
855 static void s_abicalls PARAMS ((int));
856 static void s_cpload PARAMS ((int));
857 static void s_cpsetup PARAMS ((int));
858 static void s_cplocal PARAMS ((int));
859 static void s_cprestore PARAMS ((int));
860 static void s_cpreturn PARAMS ((int));
861 static void s_gpvalue PARAMS ((int));
862 static void s_gpword PARAMS ((int));
863 static void s_cpadd PARAMS ((int));
864 static void s_insn PARAMS ((int));
865 static void md_obj_begin PARAMS ((void));
866 static void md_obj_end PARAMS ((void));
867 static long get_number PARAMS ((void));
868 static void s_mips_ent PARAMS ((int));
869 static void s_mips_end PARAMS ((int));
870 static void s_mips_frame PARAMS ((int));
871 static void s_mips_mask PARAMS ((int));
872 static void s_mips_stab PARAMS ((int));
873 static void s_mips_weakext PARAMS ((int));
874 static void s_mips_file PARAMS ((int));
875 static void s_mips_loc PARAMS ((int));
876 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
877 static int relaxed_branch_length (fragS *, asection *, int);
878 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
879 static void show PARAMS ((FILE *, const char *, int *, int *));
881 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
884 /* Return values of my_getSmallExpression(). */
891 /* Direct relocation creation by %percent_op(). */
910 /* Table and functions used to map between CPU/ISA names, and
911 ISA levels, and CPU numbers. */
915 const char *name; /* CPU or ISA name. */
916 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
917 int isa; /* ISA level. */
918 int cpu; /* CPU number (default CPU if ISA). */
921 static void mips_set_architecture PARAMS ((const struct mips_cpu_info *));
922 static void mips_set_tune PARAMS ((const struct mips_cpu_info *));
923 static boolean mips_strict_matching_cpu_name_p PARAMS ((const char *,
925 static boolean mips_matching_cpu_name_p PARAMS ((const char *, const char *));
926 static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *,
928 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
932 The following pseudo-ops from the Kane and Heinrich MIPS book
933 should be defined here, but are currently unsupported: .alias,
934 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
936 The following pseudo-ops from the Kane and Heinrich MIPS book are
937 specific to the type of debugging information being generated, and
938 should be defined by the object format: .aent, .begin, .bend,
939 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
942 The following pseudo-ops from the Kane and Heinrich MIPS book are
943 not MIPS CPU specific, but are also not specific to the object file
944 format. This file is probably the best place to define them, but
945 they are not currently supported: .asm0, .endr, .lab, .repeat,
948 static const pseudo_typeS mips_pseudo_table[] =
950 /* MIPS specific pseudo-ops. */
951 {"option", s_option, 0},
952 {"set", s_mipsset, 0},
953 {"rdata", s_change_sec, 'r'},
954 {"sdata", s_change_sec, 's'},
955 {"livereg", s_ignore, 0},
956 {"abicalls", s_abicalls, 0},
957 {"cpload", s_cpload, 0},
958 {"cpsetup", s_cpsetup, 0},
959 {"cplocal", s_cplocal, 0},
960 {"cprestore", s_cprestore, 0},
961 {"cpreturn", s_cpreturn, 0},
962 {"gpvalue", s_gpvalue, 0},
963 {"gpword", s_gpword, 0},
964 {"cpadd", s_cpadd, 0},
967 /* Relatively generic pseudo-ops that happen to be used on MIPS
969 {"asciiz", stringer, 1},
970 {"bss", s_change_sec, 'b'},
973 {"dword", s_cons, 3},
974 {"weakext", s_mips_weakext, 0},
976 /* These pseudo-ops are defined in read.c, but must be overridden
977 here for one reason or another. */
978 {"align", s_align, 0},
980 {"data", s_change_sec, 'd'},
981 {"double", s_float_cons, 'd'},
982 {"float", s_float_cons, 'f'},
983 {"globl", s_mips_globl, 0},
984 {"global", s_mips_globl, 0},
985 {"hword", s_cons, 1},
990 {"section", s_change_section, 0},
991 {"short", s_cons, 1},
992 {"single", s_float_cons, 'f'},
993 {"stabn", s_mips_stab, 'n'},
994 {"text", s_change_sec, 't'},
997 { "extern", ecoff_directive_extern, 0},
1002 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1004 /* These pseudo-ops should be defined by the object file format.
1005 However, a.out doesn't support them, so we have versions here. */
1006 {"aent", s_mips_ent, 1},
1007 {"bgnb", s_ignore, 0},
1008 {"end", s_mips_end, 0},
1009 {"endb", s_ignore, 0},
1010 {"ent", s_mips_ent, 0},
1011 {"file", s_mips_file, 0},
1012 {"fmask", s_mips_mask, 'F'},
1013 {"frame", s_mips_frame, 0},
1014 {"loc", s_mips_loc, 0},
1015 {"mask", s_mips_mask, 'R'},
1016 {"verstamp", s_ignore, 0},
1020 extern void pop_insert PARAMS ((const pseudo_typeS *));
1025 pop_insert (mips_pseudo_table);
1026 if (! ECOFF_DEBUGGING)
1027 pop_insert (mips_nonecoff_pseudo_table);
1030 /* Symbols labelling the current insn. */
1032 struct insn_label_list
1034 struct insn_label_list *next;
1038 static struct insn_label_list *insn_labels;
1039 static struct insn_label_list *free_insn_labels;
1041 static void mips_clear_insn_labels PARAMS ((void));
1044 mips_clear_insn_labels ()
1046 register struct insn_label_list **pl;
1048 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1054 static char *expr_end;
1056 /* Expressions which appear in instructions. These are set by
1059 static expressionS imm_expr;
1060 static expressionS offset_expr;
1062 /* Relocs associated with imm_expr and offset_expr. */
1064 static bfd_reloc_code_real_type imm_reloc[3]
1065 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1066 static bfd_reloc_code_real_type offset_reloc[3]
1067 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1069 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
1071 static boolean imm_unmatched_hi;
1073 /* These are set by mips16_ip if an explicit extension is used. */
1075 static boolean mips16_small, mips16_ext;
1078 /* The pdr segment for per procedure frame/regmask info. Not used for
1081 static segT pdr_seg;
1084 /* The default target format to use. */
1087 mips_target_format ()
1089 switch (OUTPUT_FLAVOR)
1091 case bfd_target_aout_flavour:
1092 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1093 case bfd_target_ecoff_flavour:
1094 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1095 case bfd_target_coff_flavour:
1097 case bfd_target_elf_flavour:
1099 /* This is traditional mips. */
1100 return (target_big_endian
1101 ? (HAVE_64BIT_OBJECTS
1102 ? "elf64-tradbigmips"
1104 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1105 : (HAVE_64BIT_OBJECTS
1106 ? "elf64-tradlittlemips"
1108 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1110 return (target_big_endian
1111 ? (HAVE_64BIT_OBJECTS
1114 ? "elf32-nbigmips" : "elf32-bigmips"))
1115 : (HAVE_64BIT_OBJECTS
1116 ? "elf64-littlemips"
1118 ? "elf32-nlittlemips" : "elf32-littlemips")));
1126 /* This function is called once, at assembler startup time. It should
1127 set up all the tables, etc. that the MD part of the assembler will need. */
1132 register const char *retval = NULL;
1136 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1137 as_warn (_("Could not set architecture and machine"));
1139 op_hash = hash_new ();
1141 for (i = 0; i < NUMOPCODES;)
1143 const char *name = mips_opcodes[i].name;
1145 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1148 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1149 mips_opcodes[i].name, retval);
1150 /* Probably a memory allocation problem? Give up now. */
1151 as_fatal (_("Broken assembler. No assembly attempted."));
1155 if (mips_opcodes[i].pinfo != INSN_MACRO)
1157 if (!validate_mips_insn (&mips_opcodes[i]))
1162 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1165 mips16_op_hash = hash_new ();
1168 while (i < bfd_mips16_num_opcodes)
1170 const char *name = mips16_opcodes[i].name;
1172 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1174 as_fatal (_("internal: can't hash `%s': %s"),
1175 mips16_opcodes[i].name, retval);
1178 if (mips16_opcodes[i].pinfo != INSN_MACRO
1179 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1180 != mips16_opcodes[i].match))
1182 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1183 mips16_opcodes[i].name, mips16_opcodes[i].args);
1188 while (i < bfd_mips16_num_opcodes
1189 && strcmp (mips16_opcodes[i].name, name) == 0);
1193 as_fatal (_("Broken assembler. No assembly attempted."));
1195 /* We add all the general register names to the symbol table. This
1196 helps us detect invalid uses of them. */
1197 for (i = 0; i < 32; i++)
1201 sprintf (buf, "$%d", i);
1202 symbol_table_insert (symbol_new (buf, reg_section, i,
1203 &zero_address_frag));
1205 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1206 &zero_address_frag));
1207 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1208 &zero_address_frag));
1209 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1210 &zero_address_frag));
1211 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1212 &zero_address_frag));
1213 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1214 &zero_address_frag));
1215 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1216 &zero_address_frag));
1217 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1218 &zero_address_frag));
1219 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1220 &zero_address_frag));
1221 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1222 &zero_address_frag));
1224 mips_no_prev_insn (false);
1227 mips_cprmask[0] = 0;
1228 mips_cprmask[1] = 0;
1229 mips_cprmask[2] = 0;
1230 mips_cprmask[3] = 0;
1232 /* set the default alignment for the text section (2**2) */
1233 record_alignment (text_section, 2);
1235 if (USE_GLOBAL_POINTER_OPT)
1236 bfd_set_gp_size (stdoutput, g_switch_value);
1238 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1240 /* On a native system, sections must be aligned to 16 byte
1241 boundaries. When configured for an embedded ELF target, we
1243 if (strcmp (TARGET_OS, "elf") != 0)
1245 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1246 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1247 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1250 /* Create a .reginfo section for register masks and a .mdebug
1251 section for debugging information. */
1259 subseg = now_subseg;
1261 /* The ABI says this section should be loaded so that the
1262 running program can access it. However, we don't load it
1263 if we are configured for an embedded target */
1264 flags = SEC_READONLY | SEC_DATA;
1265 if (strcmp (TARGET_OS, "elf") != 0)
1266 flags |= SEC_ALLOC | SEC_LOAD;
1268 if (mips_abi != N64_ABI)
1270 sec = subseg_new (".reginfo", (subsegT) 0);
1272 bfd_set_section_flags (stdoutput, sec, flags);
1273 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1276 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1281 /* The 64-bit ABI uses a .MIPS.options section rather than
1282 .reginfo section. */
1283 sec = subseg_new (".MIPS.options", (subsegT) 0);
1284 bfd_set_section_flags (stdoutput, sec, flags);
1285 bfd_set_section_alignment (stdoutput, sec, 3);
1288 /* Set up the option header. */
1290 Elf_Internal_Options opthdr;
1293 opthdr.kind = ODK_REGINFO;
1294 opthdr.size = (sizeof (Elf_External_Options)
1295 + sizeof (Elf64_External_RegInfo));
1298 f = frag_more (sizeof (Elf_External_Options));
1299 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1300 (Elf_External_Options *) f);
1302 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1307 if (ECOFF_DEBUGGING)
1309 sec = subseg_new (".mdebug", (subsegT) 0);
1310 (void) bfd_set_section_flags (stdoutput, sec,
1311 SEC_HAS_CONTENTS | SEC_READONLY);
1312 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1315 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1317 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1318 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1319 SEC_READONLY | SEC_RELOC
1321 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1325 subseg_set (seg, subseg);
1329 if (! ECOFF_DEBUGGING)
1336 if (! ECOFF_DEBUGGING)
1344 struct mips_cl_insn insn;
1345 bfd_reloc_code_real_type unused_reloc[3]
1346 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1348 imm_expr.X_op = O_absent;
1349 imm_unmatched_hi = false;
1350 offset_expr.X_op = O_absent;
1351 imm_reloc[0] = BFD_RELOC_UNUSED;
1352 imm_reloc[1] = BFD_RELOC_UNUSED;
1353 imm_reloc[2] = BFD_RELOC_UNUSED;
1354 offset_reloc[0] = BFD_RELOC_UNUSED;
1355 offset_reloc[1] = BFD_RELOC_UNUSED;
1356 offset_reloc[2] = BFD_RELOC_UNUSED;
1358 if (mips_opts.mips16)
1359 mips16_ip (str, &insn);
1362 mips_ip (str, &insn);
1363 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1364 str, insn.insn_opcode));
1369 as_bad ("%s `%s'", insn_error, str);
1373 if (insn.insn_mo->pinfo == INSN_MACRO)
1375 if (mips_opts.mips16)
1376 mips16_macro (&insn);
1382 if (imm_expr.X_op != O_absent)
1383 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1384 else if (offset_expr.X_op != O_absent)
1385 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1387 append_insn (NULL, &insn, NULL, unused_reloc, false);
1391 /* See whether instruction IP reads register REG. CLASS is the type
1395 insn_uses_reg (ip, reg, class)
1396 struct mips_cl_insn *ip;
1398 enum mips_regclass class;
1400 if (class == MIPS16_REG)
1402 assert (mips_opts.mips16);
1403 reg = mips16_to_32_reg_map[reg];
1404 class = MIPS_GR_REG;
1407 /* Don't report on general register ZERO, since it never changes. */
1408 if (class == MIPS_GR_REG && reg == ZERO)
1411 if (class == MIPS_FP_REG)
1413 assert (! mips_opts.mips16);
1414 /* If we are called with either $f0 or $f1, we must check $f0.
1415 This is not optimal, because it will introduce an unnecessary
1416 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1417 need to distinguish reading both $f0 and $f1 or just one of
1418 them. Note that we don't have to check the other way,
1419 because there is no instruction that sets both $f0 and $f1
1420 and requires a delay. */
1421 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1422 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1423 == (reg &~ (unsigned) 1)))
1425 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1426 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1427 == (reg &~ (unsigned) 1)))
1430 else if (! mips_opts.mips16)
1432 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1433 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1435 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1436 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1441 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1442 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1443 & MIPS16OP_MASK_RX)]
1446 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1447 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1448 & MIPS16OP_MASK_RY)]
1451 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1452 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1453 & MIPS16OP_MASK_MOVE32Z)]
1456 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1458 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1460 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1462 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1463 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1464 & MIPS16OP_MASK_REGR32) == reg)
1471 /* This function returns true if modifying a register requires a
1475 reg_needs_delay (reg)
1478 unsigned long prev_pinfo;
1480 prev_pinfo = prev_insn.insn_mo->pinfo;
1481 if (! mips_opts.noreorder
1482 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1483 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1484 || (! gpr_interlocks
1485 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1487 /* A load from a coprocessor or from memory. All load
1488 delays delay the use of general register rt for one
1489 instruction on the r3000. The r6000 and r4000 use
1491 /* Itbl support may require additional care here. */
1492 know (prev_pinfo & INSN_WRITE_GPR_T);
1493 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1500 /* Mark instruction labels in mips16 mode. This permits the linker to
1501 handle them specially, such as generating jalx instructions when
1502 needed. We also make them odd for the duration of the assembly, in
1503 order to generate the right sort of code. We will make them even
1504 in the adjust_symtab routine, while leaving them marked. This is
1505 convenient for the debugger and the disassembler. The linker knows
1506 to make them odd again. */
1509 mips16_mark_labels ()
1511 if (mips_opts.mips16)
1513 struct insn_label_list *l;
1516 for (l = insn_labels; l != NULL; l = l->next)
1519 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1520 S_SET_OTHER (l->label, STO_MIPS16);
1522 val = S_GET_VALUE (l->label);
1524 S_SET_VALUE (l->label, val + 1);
1529 /* Output an instruction. PLACE is where to put the instruction; if
1530 it is NULL, this uses frag_more to get room. IP is the instruction
1531 information. ADDRESS_EXPR is an operand of the instruction to be
1532 used with RELOC_TYPE. */
1535 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1537 struct mips_cl_insn *ip;
1538 expressionS *address_expr;
1539 bfd_reloc_code_real_type *reloc_type;
1540 boolean unmatched_hi;
1542 register unsigned long prev_pinfo, pinfo;
1547 /* Mark instruction labels in mips16 mode. */
1548 mips16_mark_labels ();
1550 prev_pinfo = prev_insn.insn_mo->pinfo;
1551 pinfo = ip->insn_mo->pinfo;
1553 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1557 /* If the previous insn required any delay slots, see if we need
1558 to insert a NOP or two. There are eight kinds of possible
1559 hazards, of which an instruction can have at most one type.
1560 (1) a load from memory delay
1561 (2) a load from a coprocessor delay
1562 (3) an unconditional branch delay
1563 (4) a conditional branch delay
1564 (5) a move to coprocessor register delay
1565 (6) a load coprocessor register from memory delay
1566 (7) a coprocessor condition code delay
1567 (8) a HI/LO special register delay
1569 There are a lot of optimizations we could do that we don't.
1570 In particular, we do not, in general, reorder instructions.
1571 If you use gcc with optimization, it will reorder
1572 instructions and generally do much more optimization then we
1573 do here; repeating all that work in the assembler would only
1574 benefit hand written assembly code, and does not seem worth
1577 /* This is how a NOP is emitted. */
1578 #define emit_nop() \
1580 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1581 : md_number_to_chars (frag_more (4), 0, 4))
1583 /* The previous insn might require a delay slot, depending upon
1584 the contents of the current insn. */
1585 if (! mips_opts.mips16
1586 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1587 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1588 && ! cop_interlocks)
1589 || (! gpr_interlocks
1590 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1592 /* A load from a coprocessor or from memory. All load
1593 delays delay the use of general register rt for one
1594 instruction on the r3000. The r6000 and r4000 use
1596 /* Itbl support may require additional care here. */
1597 know (prev_pinfo & INSN_WRITE_GPR_T);
1598 if (mips_optimize == 0
1599 || insn_uses_reg (ip,
1600 ((prev_insn.insn_opcode >> OP_SH_RT)
1605 else if (! mips_opts.mips16
1606 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1607 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1608 && ! cop_interlocks)
1609 || (mips_opts.isa == ISA_MIPS1
1610 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1612 /* A generic coprocessor delay. The previous instruction
1613 modified a coprocessor general or control register. If
1614 it modified a control register, we need to avoid any
1615 coprocessor instruction (this is probably not always
1616 required, but it sometimes is). If it modified a general
1617 register, we avoid using that register.
1619 On the r6000 and r4000 loading a coprocessor register
1620 from memory is interlocked, and does not require a delay.
1622 This case is not handled very well. There is no special
1623 knowledge of CP0 handling, and the coprocessors other
1624 than the floating point unit are not distinguished at
1626 /* Itbl support may require additional care here. FIXME!
1627 Need to modify this to include knowledge about
1628 user specified delays! */
1629 if (prev_pinfo & INSN_WRITE_FPR_T)
1631 if (mips_optimize == 0
1632 || insn_uses_reg (ip,
1633 ((prev_insn.insn_opcode >> OP_SH_FT)
1638 else if (prev_pinfo & INSN_WRITE_FPR_S)
1640 if (mips_optimize == 0
1641 || insn_uses_reg (ip,
1642 ((prev_insn.insn_opcode >> OP_SH_FS)
1649 /* We don't know exactly what the previous instruction
1650 does. If the current instruction uses a coprocessor
1651 register, we must insert a NOP. If previous
1652 instruction may set the condition codes, and the
1653 current instruction uses them, we must insert two
1655 /* Itbl support may require additional care here. */
1656 if (mips_optimize == 0
1657 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1658 && (pinfo & INSN_READ_COND_CODE)))
1660 else if (pinfo & INSN_COP)
1664 else if (! mips_opts.mips16
1665 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1666 && (prev_pinfo & INSN_WRITE_COND_CODE)
1667 && ! cop_interlocks)
1669 /* The previous instruction sets the coprocessor condition
1670 codes, but does not require a general coprocessor delay
1671 (this means it is a floating point comparison
1672 instruction). If this instruction uses the condition
1673 codes, we need to insert a single NOP. */
1674 /* Itbl support may require additional care here. */
1675 if (mips_optimize == 0
1676 || (pinfo & INSN_READ_COND_CODE))
1680 /* If we're fixing up mfhi/mflo for the r7000 and the
1681 previous insn was an mfhi/mflo and the current insn
1682 reads the register that the mfhi/mflo wrote to, then
1685 else if (mips_7000_hilo_fix
1686 && MF_HILO_INSN (prev_pinfo)
1687 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1694 /* If we're fixing up mfhi/mflo for the r7000 and the
1695 2nd previous insn was an mfhi/mflo and the current insn
1696 reads the register that the mfhi/mflo wrote to, then
1699 else if (mips_7000_hilo_fix
1700 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1701 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1709 else if (prev_pinfo & INSN_READ_LO)
1711 /* The previous instruction reads the LO register; if the
1712 current instruction writes to the LO register, we must
1713 insert two NOPS. Some newer processors have interlocks.
1714 Also the tx39's multiply instructions can be exectuted
1715 immediatly after a read from HI/LO (without the delay),
1716 though the tx39's divide insns still do require the
1718 if (! (hilo_interlocks
1719 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1720 && (mips_optimize == 0
1721 || (pinfo & INSN_WRITE_LO)))
1723 /* Most mips16 branch insns don't have a delay slot.
1724 If a read from LO is immediately followed by a branch
1725 to a write to LO we have a read followed by a write
1726 less than 2 insns away. We assume the target of
1727 a branch might be a write to LO, and insert a nop
1728 between a read and an immediately following branch. */
1729 else if (mips_opts.mips16
1730 && (mips_optimize == 0
1731 || (pinfo & MIPS16_INSN_BRANCH)))
1734 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1736 /* The previous instruction reads the HI register; if the
1737 current instruction writes to the HI register, we must
1738 insert a NOP. Some newer processors have interlocks.
1739 Also the note tx39's multiply above. */
1740 if (! (hilo_interlocks
1741 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1742 && (mips_optimize == 0
1743 || (pinfo & INSN_WRITE_HI)))
1745 /* Most mips16 branch insns don't have a delay slot.
1746 If a read from HI is immediately followed by a branch
1747 to a write to HI we have a read followed by a write
1748 less than 2 insns away. We assume the target of
1749 a branch might be a write to HI, and insert a nop
1750 between a read and an immediately following branch. */
1751 else if (mips_opts.mips16
1752 && (mips_optimize == 0
1753 || (pinfo & MIPS16_INSN_BRANCH)))
1757 /* If the previous instruction was in a noreorder section, then
1758 we don't want to insert the nop after all. */
1759 /* Itbl support may require additional care here. */
1760 if (prev_insn_unreordered)
1763 /* There are two cases which require two intervening
1764 instructions: 1) setting the condition codes using a move to
1765 coprocessor instruction which requires a general coprocessor
1766 delay and then reading the condition codes 2) reading the HI
1767 or LO register and then writing to it (except on processors
1768 which have interlocks). If we are not already emitting a NOP
1769 instruction, we must check for these cases compared to the
1770 instruction previous to the previous instruction. */
1771 if ((! mips_opts.mips16
1772 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1773 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1774 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1775 && (pinfo & INSN_READ_COND_CODE)
1776 && ! cop_interlocks)
1777 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1778 && (pinfo & INSN_WRITE_LO)
1779 && ! (hilo_interlocks
1780 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1781 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1782 && (pinfo & INSN_WRITE_HI)
1783 && ! (hilo_interlocks
1784 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1789 if (prev_prev_insn_unreordered)
1792 if (prev_prev_nop && nops == 0)
1795 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1797 /* We're out of bits in pinfo, so we must resort to string
1798 ops here. Shortcuts are selected based on opcodes being
1799 limited to the VR4122 instruction set. */
1801 const char *pn = prev_insn.insn_mo->name;
1802 const char *tn = ip->insn_mo->name;
1803 if (strncmp(pn, "macc", 4) == 0
1804 || strncmp(pn, "dmacc", 5) == 0)
1806 /* Errata 21 - [D]DIV[U] after [D]MACC */
1807 if (strstr (tn, "div"))
1812 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1813 if (pn[0] == 'd' /* dmacc */
1814 && (strncmp(tn, "dmult", 5) == 0
1815 || strncmp(tn, "dmacc", 5) == 0))
1820 /* Errata 24 - MT{LO,HI} after [D]MACC */
1821 if (strcmp (tn, "mtlo") == 0
1822 || strcmp (tn, "mthi") == 0)
1828 else if (strncmp(pn, "dmult", 5) == 0
1829 && (strncmp(tn, "dmult", 5) == 0
1830 || strncmp(tn, "dmacc", 5) == 0))
1832 /* Here is the rest of errata 23. */
1835 if (nops < min_nops)
1839 /* If we are being given a nop instruction, don't bother with
1840 one of the nops we would otherwise output. This will only
1841 happen when a nop instruction is used with mips_optimize set
1844 && ! mips_opts.noreorder
1845 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1848 /* Now emit the right number of NOP instructions. */
1849 if (nops > 0 && ! mips_opts.noreorder)
1852 unsigned long old_frag_offset;
1854 struct insn_label_list *l;
1856 old_frag = frag_now;
1857 old_frag_offset = frag_now_fix ();
1859 for (i = 0; i < nops; i++)
1864 listing_prev_line ();
1865 /* We may be at the start of a variant frag. In case we
1866 are, make sure there is enough space for the frag
1867 after the frags created by listing_prev_line. The
1868 argument to frag_grow here must be at least as large
1869 as the argument to all other calls to frag_grow in
1870 this file. We don't have to worry about being in the
1871 middle of a variant frag, because the variants insert
1872 all needed nop instructions themselves. */
1876 for (l = insn_labels; l != NULL; l = l->next)
1880 assert (S_GET_SEGMENT (l->label) == now_seg);
1881 symbol_set_frag (l->label, frag_now);
1882 val = (valueT) frag_now_fix ();
1883 /* mips16 text labels are stored as odd. */
1884 if (mips_opts.mips16)
1886 S_SET_VALUE (l->label, val);
1889 #ifndef NO_ECOFF_DEBUGGING
1890 if (ECOFF_DEBUGGING)
1891 ecoff_fix_loc (old_frag, old_frag_offset);
1894 else if (prev_nop_frag != NULL)
1896 /* We have a frag holding nops we may be able to remove. If
1897 we don't need any nops, we can decrease the size of
1898 prev_nop_frag by the size of one instruction. If we do
1899 need some nops, we count them in prev_nops_required. */
1900 if (prev_nop_frag_since == 0)
1904 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1905 --prev_nop_frag_holds;
1908 prev_nop_frag_required += nops;
1912 if (prev_prev_nop == 0)
1914 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1915 --prev_nop_frag_holds;
1918 ++prev_nop_frag_required;
1921 if (prev_nop_frag_holds <= prev_nop_frag_required)
1922 prev_nop_frag = NULL;
1924 ++prev_nop_frag_since;
1926 /* Sanity check: by the time we reach the second instruction
1927 after prev_nop_frag, we should have used up all the nops
1928 one way or another. */
1929 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1935 && ((*reloc_type == BFD_RELOC_16_PCREL
1936 && address_expr->X_op != O_constant)
1937 || *reloc_type == BFD_RELOC_16_PCREL_S2)
1938 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1939 || pinfo & INSN_COND_BRANCH_LIKELY)
1940 && mips_relax_branch
1941 /* Don't try branch relaxation within .set nomacro, or within
1942 .set noat if we use $at for PIC computations. If it turns
1943 out that the branch was out-of-range, we'll get an error. */
1944 && !mips_opts.warn_about_macros
1945 && !(mips_opts.noat && mips_pic != NO_PIC)
1946 && !mips_opts.mips16)
1948 f = frag_var (rs_machine_dependent,
1949 relaxed_branch_length
1951 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
1952 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
1954 (*reloc_type == BFD_RELOC_16_PCREL_S2,
1955 pinfo & INSN_UNCOND_BRANCH_DELAY,
1956 pinfo & INSN_COND_BRANCH_LIKELY,
1957 pinfo & INSN_WRITE_GPR_31,
1959 address_expr->X_add_symbol,
1960 address_expr->X_add_number,
1962 *reloc_type = BFD_RELOC_UNUSED;
1964 else if (*reloc_type > BFD_RELOC_UNUSED)
1966 /* We need to set up a variant frag. */
1967 assert (mips_opts.mips16 && address_expr != NULL);
1968 f = frag_var (rs_machine_dependent, 4, 0,
1969 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1970 mips16_small, mips16_ext,
1972 & INSN_UNCOND_BRANCH_DELAY),
1973 (*prev_insn_reloc_type
1974 == BFD_RELOC_MIPS16_JMP)),
1975 make_expr_symbol (address_expr), 0, NULL);
1977 else if (place != NULL)
1979 else if (mips_opts.mips16
1981 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1983 /* Make sure there is enough room to swap this instruction with
1984 a following jump instruction. */
1990 if (mips_opts.mips16
1991 && mips_opts.noreorder
1992 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1993 as_warn (_("extended instruction in delay slot"));
1998 fixp[0] = fixp[1] = fixp[2] = NULL;
1999 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2001 if (address_expr->X_op == O_constant)
2005 switch (*reloc_type)
2008 ip->insn_opcode |= address_expr->X_add_number;
2011 case BFD_RELOC_MIPS_HIGHEST:
2012 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
2014 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2017 case BFD_RELOC_MIPS_HIGHER:
2018 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2019 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2022 case BFD_RELOC_HI16_S:
2023 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2027 case BFD_RELOC_HI16:
2028 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2031 case BFD_RELOC_LO16:
2032 case BFD_RELOC_MIPS_GOT_DISP:
2033 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2036 case BFD_RELOC_MIPS_JMP:
2037 if ((address_expr->X_add_number & 3) != 0)
2038 as_bad (_("jump to misaligned address (0x%lx)"),
2039 (unsigned long) address_expr->X_add_number);
2040 if (address_expr->X_add_number & ~0xfffffff)
2041 as_bad (_("jump address range overflow (0x%lx)"),
2042 (unsigned long) address_expr->X_add_number);
2043 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2046 case BFD_RELOC_MIPS16_JMP:
2047 if ((address_expr->X_add_number & 3) != 0)
2048 as_bad (_("jump to misaligned address (0x%lx)"),
2049 (unsigned long) address_expr->X_add_number);
2050 if (address_expr->X_add_number & ~0xfffffff)
2051 as_bad (_("jump address range overflow (0x%lx)"),
2052 (unsigned long) address_expr->X_add_number);
2054 (((address_expr->X_add_number & 0x7c0000) << 3)
2055 | ((address_expr->X_add_number & 0xf800000) >> 7)
2056 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2059 case BFD_RELOC_16_PCREL:
2060 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2063 case BFD_RELOC_16_PCREL_S2:
2073 /* Don't generate a reloc if we are writing into a variant frag. */
2076 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
2078 (*reloc_type == BFD_RELOC_16_PCREL
2079 || *reloc_type == BFD_RELOC_16_PCREL_S2),
2082 /* These relocations can have an addend that won't fit in
2083 4 octets for 64bit assembly. */
2084 if (HAVE_64BIT_GPRS &&
2085 (*reloc_type == BFD_RELOC_16
2086 || *reloc_type == BFD_RELOC_32
2087 || *reloc_type == BFD_RELOC_MIPS_JMP
2088 || *reloc_type == BFD_RELOC_HI16_S
2089 || *reloc_type == BFD_RELOC_LO16
2090 || *reloc_type == BFD_RELOC_GPREL16
2091 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2092 || *reloc_type == BFD_RELOC_GPREL32
2093 || *reloc_type == BFD_RELOC_64
2094 || *reloc_type == BFD_RELOC_CTOR
2095 || *reloc_type == BFD_RELOC_MIPS_SUB
2096 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2097 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2098 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2099 || *reloc_type == BFD_RELOC_MIPS_REL16
2100 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2101 fixp[0]->fx_no_overflow = 1;
2105 struct mips_hi_fixup *hi_fixup;
2107 assert (*reloc_type == BFD_RELOC_HI16_S);
2108 hi_fixup = ((struct mips_hi_fixup *)
2109 xmalloc (sizeof (struct mips_hi_fixup)));
2110 hi_fixup->fixp = fixp[0];
2111 hi_fixup->seg = now_seg;
2112 hi_fixup->next = mips_hi_fixup_list;
2113 mips_hi_fixup_list = hi_fixup;
2116 if (reloc_type[1] != BFD_RELOC_UNUSED)
2118 /* FIXME: This symbol can be one of
2119 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2120 address_expr->X_op = O_absent;
2121 address_expr->X_add_symbol = 0;
2122 address_expr->X_add_number = 0;
2124 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2125 4, address_expr, false,
2128 /* These relocations can have an addend that won't fit in
2129 4 octets for 64bit assembly. */
2130 if (HAVE_64BIT_GPRS &&
2131 (*reloc_type == BFD_RELOC_16
2132 || *reloc_type == BFD_RELOC_32
2133 || *reloc_type == BFD_RELOC_MIPS_JMP
2134 || *reloc_type == BFD_RELOC_HI16_S
2135 || *reloc_type == BFD_RELOC_LO16
2136 || *reloc_type == BFD_RELOC_GPREL16
2137 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2138 || *reloc_type == BFD_RELOC_GPREL32
2139 || *reloc_type == BFD_RELOC_64
2140 || *reloc_type == BFD_RELOC_CTOR
2141 || *reloc_type == BFD_RELOC_MIPS_SUB
2142 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2143 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2144 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2145 || *reloc_type == BFD_RELOC_MIPS_REL16
2146 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2147 fixp[1]->fx_no_overflow = 1;
2149 if (reloc_type[2] != BFD_RELOC_UNUSED)
2151 address_expr->X_op = O_absent;
2152 address_expr->X_add_symbol = 0;
2153 address_expr->X_add_number = 0;
2155 fixp[2] = fix_new_exp (frag_now,
2156 f - frag_now->fr_literal, 4,
2157 address_expr, false,
2160 /* These relocations can have an addend that won't fit in
2161 4 octets for 64bit assembly. */
2162 if (HAVE_64BIT_GPRS &&
2163 (*reloc_type == BFD_RELOC_16
2164 || *reloc_type == BFD_RELOC_32
2165 || *reloc_type == BFD_RELOC_MIPS_JMP
2166 || *reloc_type == BFD_RELOC_HI16_S
2167 || *reloc_type == BFD_RELOC_LO16
2168 || *reloc_type == BFD_RELOC_GPREL16
2169 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2170 || *reloc_type == BFD_RELOC_GPREL32
2171 || *reloc_type == BFD_RELOC_64
2172 || *reloc_type == BFD_RELOC_CTOR
2173 || *reloc_type == BFD_RELOC_MIPS_SUB
2174 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2175 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2176 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2177 || *reloc_type == BFD_RELOC_MIPS_REL16
2178 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2179 fixp[2]->fx_no_overflow = 1;
2186 if (! mips_opts.mips16)
2188 md_number_to_chars (f, ip->insn_opcode, 4);
2190 dwarf2_emit_insn (4);
2193 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2195 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2196 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2198 dwarf2_emit_insn (4);
2205 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2208 md_number_to_chars (f, ip->insn_opcode, 2);
2210 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2214 /* Update the register mask information. */
2215 if (! mips_opts.mips16)
2217 if (pinfo & INSN_WRITE_GPR_D)
2218 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2219 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2220 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2221 if (pinfo & INSN_READ_GPR_S)
2222 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2223 if (pinfo & INSN_WRITE_GPR_31)
2224 mips_gprmask |= 1 << RA;
2225 if (pinfo & INSN_WRITE_FPR_D)
2226 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2227 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2228 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2229 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2230 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2231 if ((pinfo & INSN_READ_FPR_R) != 0)
2232 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2233 if (pinfo & INSN_COP)
2235 /* We don't keep enough information to sort these cases out.
2236 The itbl support does keep this information however, although
2237 we currently don't support itbl fprmats as part of the cop
2238 instruction. May want to add this support in the future. */
2240 /* Never set the bit for $0, which is always zero. */
2241 mips_gprmask &= ~1 << 0;
2245 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2246 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2247 & MIPS16OP_MASK_RX);
2248 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2249 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2250 & MIPS16OP_MASK_RY);
2251 if (pinfo & MIPS16_INSN_WRITE_Z)
2252 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2253 & MIPS16OP_MASK_RZ);
2254 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2255 mips_gprmask |= 1 << TREG;
2256 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2257 mips_gprmask |= 1 << SP;
2258 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2259 mips_gprmask |= 1 << RA;
2260 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2261 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2262 if (pinfo & MIPS16_INSN_READ_Z)
2263 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2264 & MIPS16OP_MASK_MOVE32Z);
2265 if (pinfo & MIPS16_INSN_READ_GPR_X)
2266 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2267 & MIPS16OP_MASK_REGR32);
2270 if (place == NULL && ! mips_opts.noreorder)
2272 /* Filling the branch delay slot is more complex. We try to
2273 switch the branch with the previous instruction, which we can
2274 do if the previous instruction does not set up a condition
2275 that the branch tests and if the branch is not itself the
2276 target of any branch. */
2277 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2278 || (pinfo & INSN_COND_BRANCH_DELAY))
2280 if (mips_optimize < 2
2281 /* If we have seen .set volatile or .set nomove, don't
2283 || mips_opts.nomove != 0
2284 /* If we had to emit any NOP instructions, then we
2285 already know we can not swap. */
2287 /* If we don't even know the previous insn, we can not
2289 || ! prev_insn_valid
2290 /* If the previous insn is already in a branch delay
2291 slot, then we can not swap. */
2292 || prev_insn_is_delay_slot
2293 /* If the previous previous insn was in a .set
2294 noreorder, we can't swap. Actually, the MIPS
2295 assembler will swap in this situation. However, gcc
2296 configured -with-gnu-as will generate code like
2302 in which we can not swap the bne and INSN. If gcc is
2303 not configured -with-gnu-as, it does not output the
2304 .set pseudo-ops. We don't have to check
2305 prev_insn_unreordered, because prev_insn_valid will
2306 be 0 in that case. We don't want to use
2307 prev_prev_insn_valid, because we do want to be able
2308 to swap at the start of a function. */
2309 || prev_prev_insn_unreordered
2310 /* If the branch is itself the target of a branch, we
2311 can not swap. We cheat on this; all we check for is
2312 whether there is a label on this instruction. If
2313 there are any branches to anything other than a
2314 label, users must use .set noreorder. */
2315 || insn_labels != NULL
2316 /* If the previous instruction is in a variant frag, we
2317 can not do the swap. This does not apply to the
2318 mips16, which uses variant frags for different
2320 || (! mips_opts.mips16
2321 && prev_insn_frag->fr_type == rs_machine_dependent)
2322 /* If the branch reads the condition codes, we don't
2323 even try to swap, because in the sequence
2328 we can not swap, and I don't feel like handling that
2330 || (! mips_opts.mips16
2331 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2332 && (pinfo & INSN_READ_COND_CODE))
2333 /* We can not swap with an instruction that requires a
2334 delay slot, becase the target of the branch might
2335 interfere with that instruction. */
2336 || (! mips_opts.mips16
2337 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2339 /* Itbl support may require additional care here. */
2340 & (INSN_LOAD_COPROC_DELAY
2341 | INSN_COPROC_MOVE_DELAY
2342 | INSN_WRITE_COND_CODE)))
2343 || (! (hilo_interlocks
2344 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2348 || (! mips_opts.mips16
2350 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2351 || (! mips_opts.mips16
2352 && mips_opts.isa == ISA_MIPS1
2353 /* Itbl support may require additional care here. */
2354 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2355 /* We can not swap with a branch instruction. */
2357 & (INSN_UNCOND_BRANCH_DELAY
2358 | INSN_COND_BRANCH_DELAY
2359 | INSN_COND_BRANCH_LIKELY))
2360 /* We do not swap with a trap instruction, since it
2361 complicates trap handlers to have the trap
2362 instruction be in a delay slot. */
2363 || (prev_pinfo & INSN_TRAP)
2364 /* If the branch reads a register that the previous
2365 instruction sets, we can not swap. */
2366 || (! mips_opts.mips16
2367 && (prev_pinfo & INSN_WRITE_GPR_T)
2368 && insn_uses_reg (ip,
2369 ((prev_insn.insn_opcode >> OP_SH_RT)
2372 || (! mips_opts.mips16
2373 && (prev_pinfo & INSN_WRITE_GPR_D)
2374 && insn_uses_reg (ip,
2375 ((prev_insn.insn_opcode >> OP_SH_RD)
2378 || (mips_opts.mips16
2379 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2380 && insn_uses_reg (ip,
2381 ((prev_insn.insn_opcode
2383 & MIPS16OP_MASK_RX),
2385 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2386 && insn_uses_reg (ip,
2387 ((prev_insn.insn_opcode
2389 & MIPS16OP_MASK_RY),
2391 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2392 && insn_uses_reg (ip,
2393 ((prev_insn.insn_opcode
2395 & MIPS16OP_MASK_RZ),
2397 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2398 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2399 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2400 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2401 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2402 && insn_uses_reg (ip,
2403 MIPS16OP_EXTRACT_REG32R (prev_insn.
2406 /* If the branch writes a register that the previous
2407 instruction sets, we can not swap (we know that
2408 branches write only to RD or to $31). */
2409 || (! mips_opts.mips16
2410 && (prev_pinfo & INSN_WRITE_GPR_T)
2411 && (((pinfo & INSN_WRITE_GPR_D)
2412 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2413 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2414 || ((pinfo & INSN_WRITE_GPR_31)
2415 && (((prev_insn.insn_opcode >> OP_SH_RT)
2418 || (! mips_opts.mips16
2419 && (prev_pinfo & INSN_WRITE_GPR_D)
2420 && (((pinfo & INSN_WRITE_GPR_D)
2421 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2422 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2423 || ((pinfo & INSN_WRITE_GPR_31)
2424 && (((prev_insn.insn_opcode >> OP_SH_RD)
2427 || (mips_opts.mips16
2428 && (pinfo & MIPS16_INSN_WRITE_31)
2429 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2430 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2431 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2433 /* If the branch writes a register that the previous
2434 instruction reads, we can not swap (we know that
2435 branches only write to RD or to $31). */
2436 || (! mips_opts.mips16
2437 && (pinfo & INSN_WRITE_GPR_D)
2438 && insn_uses_reg (&prev_insn,
2439 ((ip->insn_opcode >> OP_SH_RD)
2442 || (! mips_opts.mips16
2443 && (pinfo & INSN_WRITE_GPR_31)
2444 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2445 || (mips_opts.mips16
2446 && (pinfo & MIPS16_INSN_WRITE_31)
2447 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2448 /* If we are generating embedded PIC code, the branch
2449 might be expanded into a sequence which uses $at, so
2450 we can't swap with an instruction which reads it. */
2451 || (mips_pic == EMBEDDED_PIC
2452 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2453 /* If the previous previous instruction has a load
2454 delay, and sets a register that the branch reads, we
2456 || (! mips_opts.mips16
2457 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2458 /* Itbl support may require additional care here. */
2459 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2460 || (! gpr_interlocks
2461 && (prev_prev_insn.insn_mo->pinfo
2462 & INSN_LOAD_MEMORY_DELAY)))
2463 && insn_uses_reg (ip,
2464 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2467 /* If one instruction sets a condition code and the
2468 other one uses a condition code, we can not swap. */
2469 || ((pinfo & INSN_READ_COND_CODE)
2470 && (prev_pinfo & INSN_WRITE_COND_CODE))
2471 || ((pinfo & INSN_WRITE_COND_CODE)
2472 && (prev_pinfo & INSN_READ_COND_CODE))
2473 /* If the previous instruction uses the PC, we can not
2475 || (mips_opts.mips16
2476 && (prev_pinfo & MIPS16_INSN_READ_PC))
2477 /* If the previous instruction was extended, we can not
2479 || (mips_opts.mips16 && prev_insn_extended)
2480 /* If the previous instruction had a fixup in mips16
2481 mode, we can not swap. This normally means that the
2482 previous instruction was a 4 byte branch anyhow. */
2483 || (mips_opts.mips16 && prev_insn_fixp[0])
2484 /* If the previous instruction is a sync, sync.l, or
2485 sync.p, we can not swap. */
2486 || (prev_pinfo & INSN_SYNC))
2488 /* We could do even better for unconditional branches to
2489 portions of this object file; we could pick up the
2490 instruction at the destination, put it in the delay
2491 slot, and bump the destination address. */
2493 /* Update the previous insn information. */
2494 prev_prev_insn = *ip;
2495 prev_insn.insn_mo = &dummy_opcode;
2499 /* It looks like we can actually do the swap. */
2500 if (! mips_opts.mips16)
2505 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2506 memcpy (temp, prev_f, 4);
2507 memcpy (prev_f, f, 4);
2508 memcpy (f, temp, 4);
2509 if (prev_insn_fixp[0])
2511 prev_insn_fixp[0]->fx_frag = frag_now;
2512 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2514 if (prev_insn_fixp[1])
2516 prev_insn_fixp[1]->fx_frag = frag_now;
2517 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2519 if (prev_insn_fixp[2])
2521 prev_insn_fixp[2]->fx_frag = frag_now;
2522 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2526 fixp[0]->fx_frag = prev_insn_frag;
2527 fixp[0]->fx_where = prev_insn_where;
2531 fixp[1]->fx_frag = prev_insn_frag;
2532 fixp[1]->fx_where = prev_insn_where;
2536 fixp[2]->fx_frag = prev_insn_frag;
2537 fixp[2]->fx_where = prev_insn_where;
2545 assert (prev_insn_fixp[0] == NULL);
2546 assert (prev_insn_fixp[1] == NULL);
2547 assert (prev_insn_fixp[2] == NULL);
2548 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2549 memcpy (temp, prev_f, 2);
2550 memcpy (prev_f, f, 2);
2551 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2553 assert (*reloc_type == BFD_RELOC_UNUSED);
2554 memcpy (f, temp, 2);
2558 memcpy (f, f + 2, 2);
2559 memcpy (f + 2, temp, 2);
2563 fixp[0]->fx_frag = prev_insn_frag;
2564 fixp[0]->fx_where = prev_insn_where;
2568 fixp[1]->fx_frag = prev_insn_frag;
2569 fixp[1]->fx_where = prev_insn_where;
2573 fixp[2]->fx_frag = prev_insn_frag;
2574 fixp[2]->fx_where = prev_insn_where;
2578 /* Update the previous insn information; leave prev_insn
2580 prev_prev_insn = *ip;
2582 prev_insn_is_delay_slot = 1;
2584 /* If that was an unconditional branch, forget the previous
2585 insn information. */
2586 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2588 prev_prev_insn.insn_mo = &dummy_opcode;
2589 prev_insn.insn_mo = &dummy_opcode;
2592 prev_insn_fixp[0] = NULL;
2593 prev_insn_fixp[1] = NULL;
2594 prev_insn_fixp[2] = NULL;
2595 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2596 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2597 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2598 prev_insn_extended = 0;
2600 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2602 /* We don't yet optimize a branch likely. What we should do
2603 is look at the target, copy the instruction found there
2604 into the delay slot, and increment the branch to jump to
2605 the next instruction. */
2607 /* Update the previous insn information. */
2608 prev_prev_insn = *ip;
2609 prev_insn.insn_mo = &dummy_opcode;
2610 prev_insn_fixp[0] = NULL;
2611 prev_insn_fixp[1] = NULL;
2612 prev_insn_fixp[2] = NULL;
2613 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2614 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2615 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2616 prev_insn_extended = 0;
2620 /* Update the previous insn information. */
2622 prev_prev_insn.insn_mo = &dummy_opcode;
2624 prev_prev_insn = prev_insn;
2627 /* Any time we see a branch, we always fill the delay slot
2628 immediately; since this insn is not a branch, we know it
2629 is not in a delay slot. */
2630 prev_insn_is_delay_slot = 0;
2632 prev_insn_fixp[0] = fixp[0];
2633 prev_insn_fixp[1] = fixp[1];
2634 prev_insn_fixp[2] = fixp[2];
2635 prev_insn_reloc_type[0] = reloc_type[0];
2636 prev_insn_reloc_type[1] = reloc_type[1];
2637 prev_insn_reloc_type[2] = reloc_type[2];
2638 if (mips_opts.mips16)
2639 prev_insn_extended = (ip->use_extend
2640 || *reloc_type > BFD_RELOC_UNUSED);
2643 prev_prev_insn_unreordered = prev_insn_unreordered;
2644 prev_insn_unreordered = 0;
2645 prev_insn_frag = frag_now;
2646 prev_insn_where = f - frag_now->fr_literal;
2647 prev_insn_valid = 1;
2649 else if (place == NULL)
2651 /* We need to record a bit of information even when we are not
2652 reordering, in order to determine the base address for mips16
2653 PC relative relocs. */
2654 prev_prev_insn = prev_insn;
2656 prev_insn_reloc_type[0] = reloc_type[0];
2657 prev_insn_reloc_type[1] = reloc_type[1];
2658 prev_insn_reloc_type[2] = reloc_type[2];
2659 prev_prev_insn_unreordered = prev_insn_unreordered;
2660 prev_insn_unreordered = 1;
2663 /* We just output an insn, so the next one doesn't have a label. */
2664 mips_clear_insn_labels ();
2666 /* We must ensure that a fixup associated with an unmatched %hi
2667 reloc does not become a variant frag. Otherwise, the
2668 rearrangement of %hi relocs in frob_file may confuse
2672 frag_wane (frag_now);
2677 /* This function forgets that there was any previous instruction or
2678 label. If PRESERVE is non-zero, it remembers enough information to
2679 know whether nops are needed before a noreorder section. */
2682 mips_no_prev_insn (preserve)
2687 prev_insn.insn_mo = &dummy_opcode;
2688 prev_prev_insn.insn_mo = &dummy_opcode;
2689 prev_nop_frag = NULL;
2690 prev_nop_frag_holds = 0;
2691 prev_nop_frag_required = 0;
2692 prev_nop_frag_since = 0;
2694 prev_insn_valid = 0;
2695 prev_insn_is_delay_slot = 0;
2696 prev_insn_unreordered = 0;
2697 prev_insn_extended = 0;
2698 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2699 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2700 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2701 prev_prev_insn_unreordered = 0;
2702 mips_clear_insn_labels ();
2705 /* This function must be called whenever we turn on noreorder or emit
2706 something other than instructions. It inserts any NOPS which might
2707 be needed by the previous instruction, and clears the information
2708 kept for the previous instructions. The INSNS parameter is true if
2709 instructions are to follow. */
2712 mips_emit_delays (insns)
2715 if (! mips_opts.noreorder)
2720 if ((! mips_opts.mips16
2721 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2722 && (! cop_interlocks
2723 && (prev_insn.insn_mo->pinfo
2724 & (INSN_LOAD_COPROC_DELAY
2725 | INSN_COPROC_MOVE_DELAY
2726 | INSN_WRITE_COND_CODE))))
2727 || (! hilo_interlocks
2728 && (prev_insn.insn_mo->pinfo
2731 || (! mips_opts.mips16
2733 && (prev_insn.insn_mo->pinfo
2734 & INSN_LOAD_MEMORY_DELAY))
2735 || (! mips_opts.mips16
2736 && mips_opts.isa == ISA_MIPS1
2737 && (prev_insn.insn_mo->pinfo
2738 & INSN_COPROC_MEMORY_DELAY)))
2740 /* Itbl support may require additional care here. */
2742 if ((! mips_opts.mips16
2743 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2744 && (! cop_interlocks
2745 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2746 || (! hilo_interlocks
2747 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2748 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2751 if (prev_insn_unreordered)
2754 else if ((! mips_opts.mips16
2755 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2756 && (! cop_interlocks
2757 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2758 || (! hilo_interlocks
2759 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2760 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2762 /* Itbl support may require additional care here. */
2763 if (! prev_prev_insn_unreordered)
2767 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2770 const char *pn = prev_insn.insn_mo->name;
2771 if (strncmp(pn, "macc", 4) == 0
2772 || strncmp(pn, "dmacc", 5) == 0
2773 || strncmp(pn, "dmult", 5) == 0)
2777 if (nops < min_nops)
2783 struct insn_label_list *l;
2787 /* Record the frag which holds the nop instructions, so
2788 that we can remove them if we don't need them. */
2789 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2790 prev_nop_frag = frag_now;
2791 prev_nop_frag_holds = nops;
2792 prev_nop_frag_required = 0;
2793 prev_nop_frag_since = 0;
2796 for (; nops > 0; --nops)
2801 /* Move on to a new frag, so that it is safe to simply
2802 decrease the size of prev_nop_frag. */
2803 frag_wane (frag_now);
2807 for (l = insn_labels; l != NULL; l = l->next)
2811 assert (S_GET_SEGMENT (l->label) == now_seg);
2812 symbol_set_frag (l->label, frag_now);
2813 val = (valueT) frag_now_fix ();
2814 /* mips16 text labels are stored as odd. */
2815 if (mips_opts.mips16)
2817 S_SET_VALUE (l->label, val);
2822 /* Mark instruction labels in mips16 mode. */
2824 mips16_mark_labels ();
2826 mips_no_prev_insn (insns);
2829 /* Build an instruction created by a macro expansion. This is passed
2830 a pointer to the count of instructions created so far, an
2831 expression, the name of the instruction to build, an operand format
2832 string, and corresponding arguments. */
2836 macro_build (char *place,
2844 macro_build (place, counter, ep, name, fmt, va_alist)
2853 struct mips_cl_insn insn;
2854 bfd_reloc_code_real_type r[3];
2858 va_start (args, fmt);
2864 * If the macro is about to expand into a second instruction,
2865 * print a warning if needed. We need to pass ip as a parameter
2866 * to generate a better warning message here...
2868 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2869 as_warn (_("Macro instruction expanded into multiple instructions"));
2872 * If the macro is about to expand into a second instruction,
2873 * and it is in a delay slot, print a warning.
2877 && mips_opts.noreorder
2878 && (prev_prev_insn.insn_mo->pinfo
2879 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2880 | INSN_COND_BRANCH_LIKELY)) != 0)
2881 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2884 ++*counter; /* bump instruction counter */
2886 if (mips_opts.mips16)
2888 mips16_macro_build (place, counter, ep, name, fmt, args);
2893 r[0] = BFD_RELOC_UNUSED;
2894 r[1] = BFD_RELOC_UNUSED;
2895 r[2] = BFD_RELOC_UNUSED;
2896 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2897 assert (insn.insn_mo);
2898 assert (strcmp (name, insn.insn_mo->name) == 0);
2900 /* Search until we get a match for NAME. */
2903 /* It is assumed here that macros will never generate
2904 MDMX or MIPS-3D instructions. */
2905 if (strcmp (fmt, insn.insn_mo->args) == 0
2906 && insn.insn_mo->pinfo != INSN_MACRO
2907 && OPCODE_IS_MEMBER (insn.insn_mo,
2909 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2911 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2915 assert (insn.insn_mo->name);
2916 assert (strcmp (name, insn.insn_mo->name) == 0);
2919 insn.insn_opcode = insn.insn_mo->match;
2935 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2939 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2944 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2949 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2954 int tmp = va_arg (args, int);
2956 insn.insn_opcode |= tmp << OP_SH_RT;
2957 insn.insn_opcode |= tmp << OP_SH_RD;
2963 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2970 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2974 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2978 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2982 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2986 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2993 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2999 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3000 assert (*r == BFD_RELOC_GPREL16
3001 || *r == BFD_RELOC_MIPS_LITERAL
3002 || *r == BFD_RELOC_MIPS_HIGHER
3003 || *r == BFD_RELOC_HI16_S
3004 || *r == BFD_RELOC_LO16
3005 || *r == BFD_RELOC_MIPS_GOT16
3006 || *r == BFD_RELOC_MIPS_CALL16
3007 || *r == BFD_RELOC_MIPS_GOT_DISP
3008 || *r == BFD_RELOC_MIPS_GOT_PAGE
3009 || *r == BFD_RELOC_MIPS_GOT_OFST
3010 || *r == BFD_RELOC_MIPS_GOT_LO16
3011 || *r == BFD_RELOC_MIPS_CALL_LO16
3012 || (ep->X_op == O_subtract
3013 && *r == BFD_RELOC_PCREL_LO16));
3017 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3019 && (ep->X_op == O_constant
3020 || (ep->X_op == O_symbol
3021 && (*r == BFD_RELOC_MIPS_HIGHEST
3022 || *r == BFD_RELOC_HI16_S
3023 || *r == BFD_RELOC_HI16
3024 || *r == BFD_RELOC_GPREL16
3025 || *r == BFD_RELOC_MIPS_GOT_HI16
3026 || *r == BFD_RELOC_MIPS_CALL_HI16))
3027 || (ep->X_op == O_subtract
3028 && *r == BFD_RELOC_PCREL_HI16_S)));
3032 assert (ep != NULL);
3034 * This allows macro() to pass an immediate expression for
3035 * creating short branches without creating a symbol.
3036 * Note that the expression still might come from the assembly
3037 * input, in which case the value is not checked for range nor
3038 * is a relocation entry generated (yuck).
3040 if (ep->X_op == O_constant)
3042 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3046 if (mips_pic == EMBEDDED_PIC)
3047 *r = BFD_RELOC_16_PCREL_S2;
3049 *r = BFD_RELOC_16_PCREL;
3053 assert (ep != NULL);
3054 *r = BFD_RELOC_MIPS_JMP;
3058 insn.insn_opcode |= va_arg (args, unsigned long);
3067 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3069 append_insn (place, &insn, ep, r, false);
3073 mips16_macro_build (place, counter, ep, name, fmt, args)
3075 int *counter ATTRIBUTE_UNUSED;
3081 struct mips_cl_insn insn;
3082 bfd_reloc_code_real_type r[3]
3083 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3085 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3086 assert (insn.insn_mo);
3087 assert (strcmp (name, insn.insn_mo->name) == 0);
3089 while (strcmp (fmt, insn.insn_mo->args) != 0
3090 || insn.insn_mo->pinfo == INSN_MACRO)
3093 assert (insn.insn_mo->name);
3094 assert (strcmp (name, insn.insn_mo->name) == 0);
3097 insn.insn_opcode = insn.insn_mo->match;
3098 insn.use_extend = false;
3117 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3122 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3126 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3130 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3140 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3147 regno = va_arg (args, int);
3148 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3149 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3170 assert (ep != NULL);
3172 if (ep->X_op != O_constant)
3173 *r = (int) BFD_RELOC_UNUSED + c;
3176 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
3177 false, &insn.insn_opcode, &insn.use_extend,
3180 *r = BFD_RELOC_UNUSED;
3186 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3193 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3195 append_insn (place, &insn, ep, r, false);
3199 * Generate a "jalr" instruction with a relocation hint to the called
3200 * function. This occurs in NewABI PIC code.
3203 macro_build_jalr (icnt, ep)
3214 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3217 fix_new_exp (frag_now, f - frag_now->fr_literal,
3218 0, ep, false, BFD_RELOC_MIPS_JALR);
3222 * Generate a "lui" instruction.
3225 macro_build_lui (place, counter, ep, regnum)
3231 expressionS high_expr;
3232 struct mips_cl_insn insn;
3233 bfd_reloc_code_real_type r[3]
3234 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3235 const char *name = "lui";
3236 const char *fmt = "t,u";
3238 assert (! mips_opts.mips16);
3244 high_expr.X_op = O_constant;
3245 high_expr.X_add_number = ep->X_add_number;
3248 if (high_expr.X_op == O_constant)
3250 /* we can compute the instruction now without a relocation entry */
3251 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3253 *r = BFD_RELOC_UNUSED;
3255 else if (! HAVE_NEWABI)
3257 assert (ep->X_op == O_symbol);
3258 /* _gp_disp is a special case, used from s_cpload. */
3259 assert (mips_pic == NO_PIC
3260 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3261 *r = BFD_RELOC_HI16_S;
3265 * If the macro is about to expand into a second instruction,
3266 * print a warning if needed. We need to pass ip as a parameter
3267 * to generate a better warning message here...
3269 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3270 as_warn (_("Macro instruction expanded into multiple instructions"));
3273 ++*counter; /* bump instruction counter */
3275 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3276 assert (insn.insn_mo);
3277 assert (strcmp (name, insn.insn_mo->name) == 0);
3278 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3280 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3281 if (*r == BFD_RELOC_UNUSED)
3283 insn.insn_opcode |= high_expr.X_add_number;
3284 append_insn (place, &insn, NULL, r, false);
3287 append_insn (place, &insn, &high_expr, r, false);
3290 /* Generate a sequence of instructions to do a load or store from a constant
3291 offset off of a base register (breg) into/from a target register (treg),
3292 using AT if necessary. */
3294 macro_build_ldst_constoffset (place, counter, ep, op, treg, breg)
3301 assert (ep->X_op == O_constant);
3303 /* Right now, this routine can only handle signed 32-bit contants. */
3304 if (! IS_SEXT_32BIT_NUM(ep->X_add_number))
3305 as_warn (_("operand overflow"));
3307 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3309 /* Signed 16-bit offset will fit in the op. Easy! */
3310 macro_build (place, counter, ep, op, "t,o(b)", treg,
3311 (int) BFD_RELOC_LO16, breg);
3315 /* 32-bit offset, need multiple instructions and AT, like:
3316 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3317 addu $tempreg,$tempreg,$breg
3318 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3319 to handle the complete offset. */
3320 macro_build_lui (place, counter, ep, AT);
3323 macro_build (place, counter, (expressionS *) NULL,
3324 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
3325 "d,v,t", AT, AT, breg);
3328 macro_build (place, counter, ep, op, "t,o(b)", treg,
3329 (int) BFD_RELOC_LO16, AT);
3332 as_warn (_("Macro used $at after \".set noat\""));
3337 * Generates code to set the $at register to true (one)
3338 * if reg is less than the immediate expression.
3341 set_at (counter, reg, unsignedp)
3346 if (imm_expr.X_op == O_constant
3347 && imm_expr.X_add_number >= -0x8000
3348 && imm_expr.X_add_number < 0x8000)
3349 macro_build ((char *) NULL, counter, &imm_expr,
3350 unsignedp ? "sltiu" : "slti",
3351 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3354 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3355 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3356 unsignedp ? "sltu" : "slt",
3357 "d,v,t", AT, reg, AT);
3361 /* Warn if an expression is not a constant. */
3364 check_absolute_expr (ip, ex)
3365 struct mips_cl_insn *ip;
3368 if (ex->X_op == O_big)
3369 as_bad (_("unsupported large constant"));
3370 else if (ex->X_op != O_constant)
3371 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3374 /* Count the leading zeroes by performing a binary chop. This is a
3375 bulky bit of source, but performance is a LOT better for the
3376 majority of values than a simple loop to count the bits:
3377 for (lcnt = 0; (lcnt < 32); lcnt++)
3378 if ((v) & (1 << (31 - lcnt)))
3380 However it is not code size friendly, and the gain will drop a bit
3381 on certain cached systems.
3383 #define COUNT_TOP_ZEROES(v) \
3384 (((v) & ~0xffff) == 0 \
3385 ? ((v) & ~0xff) == 0 \
3386 ? ((v) & ~0xf) == 0 \
3387 ? ((v) & ~0x3) == 0 \
3388 ? ((v) & ~0x1) == 0 \
3393 : ((v) & ~0x7) == 0 \
3396 : ((v) & ~0x3f) == 0 \
3397 ? ((v) & ~0x1f) == 0 \
3400 : ((v) & ~0x7f) == 0 \
3403 : ((v) & ~0xfff) == 0 \
3404 ? ((v) & ~0x3ff) == 0 \
3405 ? ((v) & ~0x1ff) == 0 \
3408 : ((v) & ~0x7ff) == 0 \
3411 : ((v) & ~0x3fff) == 0 \
3412 ? ((v) & ~0x1fff) == 0 \
3415 : ((v) & ~0x7fff) == 0 \
3418 : ((v) & ~0xffffff) == 0 \
3419 ? ((v) & ~0xfffff) == 0 \
3420 ? ((v) & ~0x3ffff) == 0 \
3421 ? ((v) & ~0x1ffff) == 0 \
3424 : ((v) & ~0x7ffff) == 0 \
3427 : ((v) & ~0x3fffff) == 0 \
3428 ? ((v) & ~0x1fffff) == 0 \
3431 : ((v) & ~0x7fffff) == 0 \
3434 : ((v) & ~0xfffffff) == 0 \
3435 ? ((v) & ~0x3ffffff) == 0 \
3436 ? ((v) & ~0x1ffffff) == 0 \
3439 : ((v) & ~0x7ffffff) == 0 \
3442 : ((v) & ~0x3fffffff) == 0 \
3443 ? ((v) & ~0x1fffffff) == 0 \
3446 : ((v) & ~0x7fffffff) == 0 \
3451 * This routine generates the least number of instructions neccessary to load
3452 * an absolute expression value into a register.
3455 load_register (counter, reg, ep, dbl)
3462 expressionS hi32, lo32;
3464 if (ep->X_op != O_big)
3466 assert (ep->X_op == O_constant);
3467 if (ep->X_add_number < 0x8000
3468 && (ep->X_add_number >= 0
3469 || (ep->X_add_number >= -0x8000
3472 || sizeof (ep->X_add_number) > 4))))
3474 /* We can handle 16 bit signed values with an addiu to
3475 $zero. No need to ever use daddiu here, since $zero and
3476 the result are always correct in 32 bit mode. */
3477 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3478 (int) BFD_RELOC_LO16);
3481 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3483 /* We can handle 16 bit unsigned values with an ori to
3485 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3486 (int) BFD_RELOC_LO16);
3489 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3492 || sizeof (ep->X_add_number) > 4
3493 || (ep->X_add_number & 0x80000000) == 0))
3494 || ((HAVE_32BIT_GPRS || ! dbl)
3495 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3498 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3499 == ~ (offsetT) 0xffffffff)))
3501 /* 32 bit values require an lui. */
3502 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3503 (int) BFD_RELOC_HI16);
3504 if ((ep->X_add_number & 0xffff) != 0)
3505 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3506 (int) BFD_RELOC_LO16);
3511 /* The value is larger than 32 bits. */
3513 if (HAVE_32BIT_GPRS)
3515 as_bad (_("Number (0x%lx) larger than 32 bits"),
3516 (unsigned long) ep->X_add_number);
3517 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3518 (int) BFD_RELOC_LO16);
3522 if (ep->X_op != O_big)
3525 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3526 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3527 hi32.X_add_number &= 0xffffffff;
3529 lo32.X_add_number &= 0xffffffff;
3533 assert (ep->X_add_number > 2);
3534 if (ep->X_add_number == 3)
3535 generic_bignum[3] = 0;
3536 else if (ep->X_add_number > 4)
3537 as_bad (_("Number larger than 64 bits"));
3538 lo32.X_op = O_constant;
3539 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3540 hi32.X_op = O_constant;
3541 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3544 if (hi32.X_add_number == 0)
3549 unsigned long hi, lo;
3551 if (hi32.X_add_number == (offsetT) 0xffffffff)
3553 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3555 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3556 reg, 0, (int) BFD_RELOC_LO16);
3559 if (lo32.X_add_number & 0x80000000)
3561 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3562 (int) BFD_RELOC_HI16);
3563 if (lo32.X_add_number & 0xffff)
3564 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3565 reg, reg, (int) BFD_RELOC_LO16);
3570 /* Check for 16bit shifted constant. We know that hi32 is
3571 non-zero, so start the mask on the first bit of the hi32
3576 unsigned long himask, lomask;
3580 himask = 0xffff >> (32 - shift);
3581 lomask = (0xffff << shift) & 0xffffffff;
3585 himask = 0xffff << (shift - 32);
3588 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3589 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3593 tmp.X_op = O_constant;
3595 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3596 | (lo32.X_add_number >> shift));
3598 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3599 macro_build ((char *) NULL, counter, &tmp,
3600 "ori", "t,r,i", reg, 0,
3601 (int) BFD_RELOC_LO16);
3602 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3603 (shift >= 32) ? "dsll32" : "dsll",
3605 (shift >= 32) ? shift - 32 : shift);
3610 while (shift <= (64 - 16));
3612 /* Find the bit number of the lowest one bit, and store the
3613 shifted value in hi/lo. */
3614 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3615 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3619 while ((lo & 1) == 0)
3624 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3630 while ((hi & 1) == 0)
3639 /* Optimize if the shifted value is a (power of 2) - 1. */
3640 if ((hi == 0 && ((lo + 1) & lo) == 0)
3641 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3643 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3648 /* This instruction will set the register to be all
3650 tmp.X_op = O_constant;
3651 tmp.X_add_number = (offsetT) -1;
3652 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3653 reg, 0, (int) BFD_RELOC_LO16);
3657 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3658 (bit >= 32) ? "dsll32" : "dsll",
3660 (bit >= 32) ? bit - 32 : bit);
3662 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3663 (shift >= 32) ? "dsrl32" : "dsrl",
3665 (shift >= 32) ? shift - 32 : shift);
3670 /* Sign extend hi32 before calling load_register, because we can
3671 generally get better code when we load a sign extended value. */
3672 if ((hi32.X_add_number & 0x80000000) != 0)
3673 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3674 load_register (counter, reg, &hi32, 0);
3677 if ((lo32.X_add_number & 0xffff0000) == 0)
3681 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3682 "dsll32", "d,w,<", reg, freg, 0);
3690 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3692 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3693 (int) BFD_RELOC_HI16);
3694 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3695 "dsrl32", "d,w,<", reg, reg, 0);
3701 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3702 "d,w,<", reg, freg, 16);
3706 mid16.X_add_number >>= 16;
3707 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3708 freg, (int) BFD_RELOC_LO16);
3709 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3710 "d,w,<", reg, reg, 16);
3713 if ((lo32.X_add_number & 0xffff) != 0)
3714 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3715 (int) BFD_RELOC_LO16);
3718 /* Load an address into a register. */
3721 load_address (counter, reg, ep, used_at)
3729 if (ep->X_op != O_constant
3730 && ep->X_op != O_symbol)
3732 as_bad (_("expression too complex"));
3733 ep->X_op = O_constant;
3736 if (ep->X_op == O_constant)
3738 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3742 if (mips_pic == NO_PIC)
3744 /* If this is a reference to a GP relative symbol, we want
3745 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3747 lui $reg,<sym> (BFD_RELOC_HI16_S)
3748 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3749 If we have an addend, we always use the latter form.
3751 With 64bit address space and a usable $at we want
3752 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3753 lui $at,<sym> (BFD_RELOC_HI16_S)
3754 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3755 daddiu $at,<sym> (BFD_RELOC_LO16)
3759 If $at is already in use, we use an path which is suboptimal
3760 on superscalar processors.
3761 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3762 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3764 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3766 daddiu $reg,<sym> (BFD_RELOC_LO16)
3768 if (HAVE_64BIT_ADDRESSES)
3770 /* We don't do GP optimization for now because RELAX_ENCODE can't
3771 hold the data for such large chunks. */
3773 if (*used_at == 0 && ! mips_opts.noat)
3775 macro_build (p, counter, ep, "lui", "t,u",
3776 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3777 macro_build (p, counter, ep, "lui", "t,u",
3778 AT, (int) BFD_RELOC_HI16_S);
3779 macro_build (p, counter, ep, "daddiu", "t,r,j",
3780 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3781 macro_build (p, counter, ep, "daddiu", "t,r,j",
3782 AT, AT, (int) BFD_RELOC_LO16);
3783 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3784 "d,w,<", reg, reg, 0);
3785 macro_build (p, counter, (expressionS *) NULL, "daddu",
3786 "d,v,t", reg, reg, AT);
3791 macro_build (p, counter, ep, "lui", "t,u",
3792 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3793 macro_build (p, counter, ep, "daddiu", "t,r,j",
3794 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3795 macro_build (p, counter, (expressionS *) NULL, "dsll",
3796 "d,w,<", reg, reg, 16);
3797 macro_build (p, counter, ep, "daddiu", "t,r,j",
3798 reg, reg, (int) BFD_RELOC_HI16_S);
3799 macro_build (p, counter, (expressionS *) NULL, "dsll",
3800 "d,w,<", reg, reg, 16);
3801 macro_build (p, counter, ep, "daddiu", "t,r,j",
3802 reg, reg, (int) BFD_RELOC_LO16);
3807 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3808 && ! nopic_need_relax (ep->X_add_symbol, 1))
3811 macro_build ((char *) NULL, counter, ep,
3812 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3813 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3814 p = frag_var (rs_machine_dependent, 8, 0,
3815 RELAX_ENCODE (4, 8, 0, 4, 0,
3816 mips_opts.warn_about_macros),
3817 ep->X_add_symbol, 0, NULL);
3819 macro_build_lui (p, counter, ep, reg);
3822 macro_build (p, counter, ep,
3823 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3824 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3827 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3831 /* If this is a reference to an external symbol, we want
3832 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3834 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3836 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3837 If we have NewABI, we want
3838 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3839 If there is a constant, it must be added in after. */
3840 ex.X_add_number = ep->X_add_number;
3841 ep->X_add_number = 0;
3845 macro_build ((char *) NULL, counter, ep,
3846 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3847 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3851 macro_build ((char *) NULL, counter, ep,
3852 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3853 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3854 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3855 p = frag_var (rs_machine_dependent, 4, 0,
3856 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3857 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3858 macro_build (p, counter, ep,
3859 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3860 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3863 if (ex.X_add_number != 0)
3865 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3866 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3867 ex.X_op = O_constant;
3868 macro_build ((char *) NULL, counter, &ex,
3869 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3870 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3873 else if (mips_pic == SVR4_PIC)
3878 /* This is the large GOT case. If this is a reference to an
3879 external symbol, we want
3880 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3882 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3883 Otherwise, for a reference to a local symbol, we want
3884 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3886 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3887 If we have NewABI, we want
3888 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3889 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3890 If there is a constant, it must be added in after. */
3891 ex.X_add_number = ep->X_add_number;
3892 ep->X_add_number = 0;
3895 macro_build ((char *) NULL, counter, ep,
3896 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3897 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3898 macro_build (p, counter, ep,
3899 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3900 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3904 if (reg_needs_delay (mips_gp_register))
3909 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3910 (int) BFD_RELOC_MIPS_GOT_HI16);
3911 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3912 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3913 reg, mips_gp_register);
3914 macro_build ((char *) NULL, counter, ep,
3915 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3916 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3917 p = frag_var (rs_machine_dependent, 12 + off, 0,
3918 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3919 mips_opts.warn_about_macros),
3920 ep->X_add_symbol, 0, NULL);
3923 /* We need a nop before loading from $gp. This special
3924 check is required because the lui which starts the main
3925 instruction stream does not refer to $gp, and so will not
3926 insert the nop which may be required. */
3927 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3930 macro_build (p, counter, ep,
3931 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3932 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3934 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3936 macro_build (p, counter, ep,
3937 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3938 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3941 if (ex.X_add_number != 0)
3943 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3944 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3945 ex.X_op = O_constant;
3946 macro_build ((char *) NULL, counter, &ex,
3947 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3948 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3951 else if (mips_pic == EMBEDDED_PIC)
3954 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3956 macro_build ((char *) NULL, counter, ep,
3957 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3958 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3964 /* Move the contents of register SOURCE into register DEST. */
3967 move_register (counter, dest, source)
3972 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3973 HAVE_32BIT_GPRS ? "addu" : "daddu",
3974 "d,v,t", dest, source, 0);
3979 * This routine implements the seemingly endless macro or synthesized
3980 * instructions and addressing modes in the mips assembly language. Many
3981 * of these macros are simple and are similar to each other. These could
3982 * probably be handled by some kind of table or grammer aproach instead of
3983 * this verbose method. Others are not simple macros but are more like
3984 * optimizing code generation.
3985 * One interesting optimization is when several store macros appear
3986 * consecutivly that would load AT with the upper half of the same address.
3987 * The ensuing load upper instructions are ommited. This implies some kind
3988 * of global optimization. We currently only optimize within a single macro.
3989 * For many of the load and store macros if the address is specified as a
3990 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3991 * first load register 'at' with zero and use it as the base register. The
3992 * mips assembler simply uses register $zero. Just one tiny optimization
3997 struct mips_cl_insn *ip;
3999 register int treg, sreg, dreg, breg;
4015 bfd_reloc_code_real_type r;
4016 int hold_mips_optimize;
4018 assert (! mips_opts.mips16);
4020 treg = (ip->insn_opcode >> 16) & 0x1f;
4021 dreg = (ip->insn_opcode >> 11) & 0x1f;
4022 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4023 mask = ip->insn_mo->mask;
4025 expr1.X_op = O_constant;
4026 expr1.X_op_symbol = NULL;
4027 expr1.X_add_symbol = NULL;
4028 expr1.X_add_number = 1;
4040 mips_emit_delays (true);
4041 ++mips_opts.noreorder;
4042 mips_any_noreorder = 1;
4044 expr1.X_add_number = 8;
4045 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4047 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4050 move_register (&icnt, dreg, sreg);
4051 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4052 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4054 --mips_opts.noreorder;
4075 if (imm_expr.X_op == O_constant
4076 && imm_expr.X_add_number >= -0x8000
4077 && imm_expr.X_add_number < 0x8000)
4079 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4080 (int) BFD_RELOC_LO16);
4083 load_register (&icnt, AT, &imm_expr, dbl);
4084 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4104 if (imm_expr.X_op == O_constant
4105 && imm_expr.X_add_number >= 0
4106 && imm_expr.X_add_number < 0x10000)
4108 if (mask != M_NOR_I)
4109 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
4110 sreg, (int) BFD_RELOC_LO16);
4113 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
4114 treg, sreg, (int) BFD_RELOC_LO16);
4115 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
4116 "d,v,t", treg, treg, 0);
4121 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4122 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4140 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4142 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
4146 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4147 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4155 macro_build ((char *) NULL, &icnt, &offset_expr,
4156 likely ? "bgezl" : "bgez", "s,p", sreg);
4161 macro_build ((char *) NULL, &icnt, &offset_expr,
4162 likely ? "blezl" : "blez", "s,p", treg);
4165 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4167 macro_build ((char *) NULL, &icnt, &offset_expr,
4168 likely ? "beql" : "beq", "s,t,p", AT, 0);
4174 /* check for > max integer */
4175 maxnum = 0x7fffffff;
4176 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4183 if (imm_expr.X_op == O_constant
4184 && imm_expr.X_add_number >= maxnum
4185 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4188 /* result is always false */
4192 as_warn (_("Branch %s is always false (nop)"),
4194 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
4200 as_warn (_("Branch likely %s is always false"),
4202 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
4207 if (imm_expr.X_op != O_constant)
4208 as_bad (_("Unsupported large constant"));
4209 ++imm_expr.X_add_number;
4213 if (mask == M_BGEL_I)
4215 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4217 macro_build ((char *) NULL, &icnt, &offset_expr,
4218 likely ? "bgezl" : "bgez", "s,p", sreg);
4221 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4223 macro_build ((char *) NULL, &icnt, &offset_expr,
4224 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4227 maxnum = 0x7fffffff;
4228 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4235 maxnum = - maxnum - 1;
4236 if (imm_expr.X_op == O_constant
4237 && imm_expr.X_add_number <= maxnum
4238 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4241 /* result is always true */
4242 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4243 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4246 set_at (&icnt, sreg, 0);
4247 macro_build ((char *) NULL, &icnt, &offset_expr,
4248 likely ? "beql" : "beq", "s,t,p", AT, 0);
4258 macro_build ((char *) NULL, &icnt, &offset_expr,
4259 likely ? "beql" : "beq", "s,t,p", 0, treg);
4262 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4263 "d,v,t", AT, sreg, treg);
4264 macro_build ((char *) NULL, &icnt, &offset_expr,
4265 likely ? "beql" : "beq", "s,t,p", AT, 0);
4273 && imm_expr.X_op == O_constant
4274 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4276 if (imm_expr.X_op != O_constant)
4277 as_bad (_("Unsupported large constant"));
4278 ++imm_expr.X_add_number;
4282 if (mask == M_BGEUL_I)
4284 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4286 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4288 macro_build ((char *) NULL, &icnt, &offset_expr,
4289 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4292 set_at (&icnt, sreg, 1);
4293 macro_build ((char *) NULL, &icnt, &offset_expr,
4294 likely ? "beql" : "beq", "s,t,p", AT, 0);
4302 macro_build ((char *) NULL, &icnt, &offset_expr,
4303 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4308 macro_build ((char *) NULL, &icnt, &offset_expr,
4309 likely ? "bltzl" : "bltz", "s,p", treg);
4312 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4314 macro_build ((char *) NULL, &icnt, &offset_expr,
4315 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4323 macro_build ((char *) NULL, &icnt, &offset_expr,
4324 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4329 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4330 "d,v,t", AT, treg, sreg);
4331 macro_build ((char *) NULL, &icnt, &offset_expr,
4332 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4340 macro_build ((char *) NULL, &icnt, &offset_expr,
4341 likely ? "blezl" : "blez", "s,p", sreg);
4346 macro_build ((char *) NULL, &icnt, &offset_expr,
4347 likely ? "bgezl" : "bgez", "s,p", treg);
4350 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4352 macro_build ((char *) NULL, &icnt, &offset_expr,
4353 likely ? "beql" : "beq", "s,t,p", AT, 0);
4359 maxnum = 0x7fffffff;
4360 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4367 if (imm_expr.X_op == O_constant
4368 && imm_expr.X_add_number >= maxnum
4369 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4371 if (imm_expr.X_op != O_constant)
4372 as_bad (_("Unsupported large constant"));
4373 ++imm_expr.X_add_number;
4377 if (mask == M_BLTL_I)
4379 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4381 macro_build ((char *) NULL, &icnt, &offset_expr,
4382 likely ? "bltzl" : "bltz", "s,p", sreg);
4385 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4387 macro_build ((char *) NULL, &icnt, &offset_expr,
4388 likely ? "blezl" : "blez", "s,p", sreg);
4391 set_at (&icnt, sreg, 0);
4392 macro_build ((char *) NULL, &icnt, &offset_expr,
4393 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4401 macro_build ((char *) NULL, &icnt, &offset_expr,
4402 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4407 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4408 "d,v,t", AT, treg, sreg);
4409 macro_build ((char *) NULL, &icnt, &offset_expr,
4410 likely ? "beql" : "beq", "s,t,p", AT, 0);
4418 && imm_expr.X_op == O_constant
4419 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4421 if (imm_expr.X_op != O_constant)
4422 as_bad (_("Unsupported large constant"));
4423 ++imm_expr.X_add_number;
4427 if (mask == M_BLTUL_I)
4429 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4431 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4433 macro_build ((char *) NULL, &icnt, &offset_expr,
4434 likely ? "beql" : "beq",
4438 set_at (&icnt, sreg, 1);
4439 macro_build ((char *) NULL, &icnt, &offset_expr,
4440 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4448 macro_build ((char *) NULL, &icnt, &offset_expr,
4449 likely ? "bltzl" : "bltz", "s,p", sreg);
4454 macro_build ((char *) NULL, &icnt, &offset_expr,
4455 likely ? "bgtzl" : "bgtz", "s,p", treg);
4458 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4460 macro_build ((char *) NULL, &icnt, &offset_expr,
4461 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4471 macro_build ((char *) NULL, &icnt, &offset_expr,
4472 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4475 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4478 macro_build ((char *) NULL, &icnt, &offset_expr,
4479 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4494 as_warn (_("Divide by zero."));
4496 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4499 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4504 mips_emit_delays (true);
4505 ++mips_opts.noreorder;
4506 mips_any_noreorder = 1;
4509 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4510 "s,t,q", treg, 0, 7);
4511 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4512 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4516 expr1.X_add_number = 8;
4517 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4518 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4519 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4520 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4523 expr1.X_add_number = -1;
4524 macro_build ((char *) NULL, &icnt, &expr1,
4525 dbl ? "daddiu" : "addiu",
4526 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4527 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4528 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4531 expr1.X_add_number = 1;
4532 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4533 (int) BFD_RELOC_LO16);
4534 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4535 "d,w,<", AT, AT, 31);
4539 expr1.X_add_number = 0x80000000;
4540 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4541 (int) BFD_RELOC_HI16);
4545 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4546 "s,t,q", sreg, AT, 6);
4547 /* We want to close the noreorder block as soon as possible, so
4548 that later insns are available for delay slot filling. */
4549 --mips_opts.noreorder;
4553 expr1.X_add_number = 8;
4554 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4555 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4558 /* We want to close the noreorder block as soon as possible, so
4559 that later insns are available for delay slot filling. */
4560 --mips_opts.noreorder;
4562 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4565 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4604 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4606 as_warn (_("Divide by zero."));
4608 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4611 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4615 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4617 if (strcmp (s2, "mflo") == 0)
4618 move_register (&icnt, dreg, sreg);
4620 move_register (&icnt, dreg, 0);
4623 if (imm_expr.X_op == O_constant
4624 && imm_expr.X_add_number == -1
4625 && s[strlen (s) - 1] != 'u')
4627 if (strcmp (s2, "mflo") == 0)
4629 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4630 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4633 move_register (&icnt, dreg, 0);
4637 load_register (&icnt, AT, &imm_expr, dbl);
4638 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4640 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4659 mips_emit_delays (true);
4660 ++mips_opts.noreorder;
4661 mips_any_noreorder = 1;
4664 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4665 "s,t,q", treg, 0, 7);
4666 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4668 /* We want to close the noreorder block as soon as possible, so
4669 that later insns are available for delay slot filling. */
4670 --mips_opts.noreorder;
4674 expr1.X_add_number = 8;
4675 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4676 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4679 /* We want to close the noreorder block as soon as possible, so
4680 that later insns are available for delay slot filling. */
4681 --mips_opts.noreorder;
4682 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4685 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4691 /* Load the address of a symbol into a register. If breg is not
4692 zero, we then add a base register to it. */
4694 if (dbl && HAVE_32BIT_GPRS)
4695 as_warn (_("dla used to load 32-bit register"));
4697 if (! dbl && HAVE_64BIT_OBJECTS)
4698 as_warn (_("la used to load 64-bit address"));
4700 if (offset_expr.X_op == O_constant
4701 && offset_expr.X_add_number >= -0x8000
4702 && offset_expr.X_add_number < 0x8000)
4704 macro_build ((char *) NULL, &icnt, &offset_expr,
4705 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4706 "t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
4721 /* When generating embedded PIC code, we permit expressions of
4724 la $treg,foo-bar($breg)
4725 where bar is an address in the current section. These are used
4726 when getting the addresses of functions. We don't permit
4727 X_add_number to be non-zero, because if the symbol is
4728 external the relaxing code needs to know that any addend is
4729 purely the offset to X_op_symbol. */
4730 if (mips_pic == EMBEDDED_PIC
4731 && offset_expr.X_op == O_subtract
4732 && (symbol_constant_p (offset_expr.X_op_symbol)
4733 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4734 : (symbol_equated_p (offset_expr.X_op_symbol)
4736 (symbol_get_value_expression (offset_expr.X_op_symbol)
4739 && (offset_expr.X_add_number == 0
4740 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4746 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4747 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4751 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4752 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4753 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4754 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4755 "d,v,t", tempreg, tempreg, breg);
4757 macro_build ((char *) NULL, &icnt, &offset_expr,
4758 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4759 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4765 if (offset_expr.X_op != O_symbol
4766 && offset_expr.X_op != O_constant)
4768 as_bad (_("expression too complex"));
4769 offset_expr.X_op = O_constant;
4772 if (offset_expr.X_op == O_constant)
4773 load_register (&icnt, tempreg, &offset_expr,
4774 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4775 ? (dbl || HAVE_64BIT_ADDRESSES)
4776 : HAVE_64BIT_ADDRESSES));
4777 else if (mips_pic == NO_PIC)
4779 /* If this is a reference to a GP relative symbol, we want
4780 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4782 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4783 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4784 If we have a constant, we need two instructions anyhow,
4785 so we may as well always use the latter form.
4787 With 64bit address space and a usable $at we want
4788 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4789 lui $at,<sym> (BFD_RELOC_HI16_S)
4790 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4791 daddiu $at,<sym> (BFD_RELOC_LO16)
4793 daddu $tempreg,$tempreg,$at
4795 If $at is already in use, we use an path which is suboptimal
4796 on superscalar processors.
4797 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4798 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4800 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4802 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4805 if (HAVE_64BIT_ADDRESSES)
4807 /* We don't do GP optimization for now because RELAX_ENCODE can't
4808 hold the data for such large chunks. */
4810 if (used_at == 0 && ! mips_opts.noat)
4812 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4813 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4814 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4815 AT, (int) BFD_RELOC_HI16_S);
4816 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4817 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4818 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4819 AT, AT, (int) BFD_RELOC_LO16);
4820 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4821 "d,w,<", tempreg, tempreg, 0);
4822 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
4823 "d,v,t", tempreg, tempreg, AT);
4828 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4829 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4830 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4831 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4832 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4833 tempreg, tempreg, 16);
4834 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4835 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4836 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4837 tempreg, tempreg, 16);
4838 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4839 tempreg, tempreg, (int) BFD_RELOC_LO16);
4844 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4845 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4848 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4849 "t,r,j", tempreg, mips_gp_register,
4850 (int) BFD_RELOC_GPREL16);
4851 p = frag_var (rs_machine_dependent, 8, 0,
4852 RELAX_ENCODE (4, 8, 0, 4, 0,
4853 mips_opts.warn_about_macros),
4854 offset_expr.X_add_symbol, 0, NULL);
4856 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4859 macro_build (p, &icnt, &offset_expr, "addiu",
4860 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4863 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4865 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4867 /* If this is a reference to an external symbol, and there
4868 is no constant, we want
4869 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4870 or if tempreg is PIC_CALL_REG
4871 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4872 For a local symbol, we want
4873 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4875 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4877 If we have a small constant, and this is a reference to
4878 an external symbol, we want
4879 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4881 addiu $tempreg,$tempreg,<constant>
4882 For a local symbol, we want the same instruction
4883 sequence, but we output a BFD_RELOC_LO16 reloc on the
4886 If we have a large constant, and this is a reference to
4887 an external symbol, we want
4888 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4889 lui $at,<hiconstant>
4890 addiu $at,$at,<loconstant>
4891 addu $tempreg,$tempreg,$at
4892 For a local symbol, we want the same instruction
4893 sequence, but we output a BFD_RELOC_LO16 reloc on the
4896 For NewABI, we want for local or external data addresses
4897 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4898 For a local function symbol, we want
4899 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4901 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4904 expr1.X_add_number = offset_expr.X_add_number;
4905 offset_expr.X_add_number = 0;
4907 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4908 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4909 else if (HAVE_NEWABI)
4910 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
4911 macro_build ((char *) NULL, &icnt, &offset_expr,
4912 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4913 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4914 if (expr1.X_add_number == 0)
4923 /* We're going to put in an addu instruction using
4924 tempreg, so we may as well insert the nop right
4926 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4930 p = frag_var (rs_machine_dependent, 8 - off, 0,
4931 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4933 ? mips_opts.warn_about_macros
4935 offset_expr.X_add_symbol, 0, NULL);
4938 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4941 macro_build (p, &icnt, &expr1,
4942 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4943 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4944 /* FIXME: If breg == 0, and the next instruction uses
4945 $tempreg, then if this variant case is used an extra
4946 nop will be generated. */
4948 else if (expr1.X_add_number >= -0x8000
4949 && expr1.X_add_number < 0x8000)
4951 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4953 macro_build ((char *) NULL, &icnt, &expr1,
4954 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4955 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4956 frag_var (rs_machine_dependent, 0, 0,
4957 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4958 offset_expr.X_add_symbol, 0, NULL);
4964 /* If we are going to add in a base register, and the
4965 target register and the base register are the same,
4966 then we are using AT as a temporary register. Since
4967 we want to load the constant into AT, we add our
4968 current AT (from the global offset table) and the
4969 register into the register now, and pretend we were
4970 not using a base register. */
4975 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4977 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4978 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4979 "d,v,t", treg, AT, breg);
4985 /* Set mips_optimize around the lui instruction to avoid
4986 inserting an unnecessary nop after the lw. */
4987 hold_mips_optimize = mips_optimize;
4989 macro_build_lui (NULL, &icnt, &expr1, AT);
4990 mips_optimize = hold_mips_optimize;
4992 macro_build ((char *) NULL, &icnt, &expr1,
4993 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4994 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4995 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4996 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4997 "d,v,t", tempreg, tempreg, AT);
4998 frag_var (rs_machine_dependent, 0, 0,
4999 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
5000 offset_expr.X_add_symbol, 0, NULL);
5004 else if (mips_pic == SVR4_PIC)
5008 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5009 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5010 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5012 /* This is the large GOT case. If this is a reference to an
5013 external symbol, and there is no constant, we want
5014 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5015 addu $tempreg,$tempreg,$gp
5016 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5017 or if tempreg is PIC_CALL_REG
5018 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5019 addu $tempreg,$tempreg,$gp
5020 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5021 For a local symbol, we want
5022 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5024 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5026 If we have a small constant, and this is a reference to
5027 an external symbol, we want
5028 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5029 addu $tempreg,$tempreg,$gp
5030 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5032 addiu $tempreg,$tempreg,<constant>
5033 For a local symbol, we want
5034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5036 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5038 If we have a large constant, and this is a reference to
5039 an external symbol, we want
5040 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5041 addu $tempreg,$tempreg,$gp
5042 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5043 lui $at,<hiconstant>
5044 addiu $at,$at,<loconstant>
5045 addu $tempreg,$tempreg,$at
5046 For a local symbol, we want
5047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5048 lui $at,<hiconstant>
5049 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5050 addu $tempreg,$tempreg,$at
5052 For NewABI, we want for local data addresses
5053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5056 expr1.X_add_number = offset_expr.X_add_number;
5057 offset_expr.X_add_number = 0;
5059 if (reg_needs_delay (mips_gp_register))
5063 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5065 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5066 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5068 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5069 tempreg, lui_reloc_type);
5070 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5071 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5072 "d,v,t", tempreg, tempreg, mips_gp_register);
5073 macro_build ((char *) NULL, &icnt, &offset_expr,
5074 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5075 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5076 if (expr1.X_add_number == 0)
5084 /* We're going to put in an addu instruction using
5085 tempreg, so we may as well insert the nop right
5087 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5092 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5093 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5096 ? mips_opts.warn_about_macros
5098 offset_expr.X_add_symbol, 0, NULL);
5100 else if (expr1.X_add_number >= -0x8000
5101 && expr1.X_add_number < 0x8000)
5103 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5105 macro_build ((char *) NULL, &icnt, &expr1,
5106 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5107 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5109 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5110 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5112 ? mips_opts.warn_about_macros
5114 offset_expr.X_add_symbol, 0, NULL);
5120 /* If we are going to add in a base register, and the
5121 target register and the base register are the same,
5122 then we are using AT as a temporary register. Since
5123 we want to load the constant into AT, we add our
5124 current AT (from the global offset table) and the
5125 register into the register now, and pretend we were
5126 not using a base register. */
5134 assert (tempreg == AT);
5135 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5137 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5138 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5139 "d,v,t", treg, AT, breg);
5144 /* Set mips_optimize around the lui instruction to avoid
5145 inserting an unnecessary nop after the lw. */
5146 hold_mips_optimize = mips_optimize;
5148 macro_build_lui (NULL, &icnt, &expr1, AT);
5149 mips_optimize = hold_mips_optimize;
5151 macro_build ((char *) NULL, &icnt, &expr1,
5152 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5153 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5154 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5155 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5156 "d,v,t", dreg, dreg, AT);
5158 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5159 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5162 ? mips_opts.warn_about_macros
5164 offset_expr.X_add_symbol, 0, NULL);
5171 /* This is needed because this instruction uses $gp, but
5172 the first instruction on the main stream does not. */
5173 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5178 local_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5179 macro_build (p, &icnt, &offset_expr,
5180 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5185 if (expr1.X_add_number == 0 && HAVE_NEWABI)
5187 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5190 if (expr1.X_add_number >= -0x8000
5191 && expr1.X_add_number < 0x8000)
5193 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5195 macro_build (p, &icnt, &expr1,
5196 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5197 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5198 /* FIXME: If add_number is 0, and there was no base
5199 register, the external symbol case ended with a load,
5200 so if the symbol turns out to not be external, and
5201 the next instruction uses tempreg, an unnecessary nop
5202 will be inserted. */
5208 /* We must add in the base register now, as in the
5209 external symbol case. */
5210 assert (tempreg == AT);
5211 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5213 macro_build (p, &icnt, (expressionS *) NULL,
5214 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5215 "d,v,t", treg, AT, breg);
5218 /* We set breg to 0 because we have arranged to add
5219 it in in both cases. */
5223 macro_build_lui (p, &icnt, &expr1, AT);
5225 macro_build (p, &icnt, &expr1,
5226 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5227 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5229 macro_build (p, &icnt, (expressionS *) NULL,
5230 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5231 "d,v,t", tempreg, tempreg, AT);
5235 else if (mips_pic == EMBEDDED_PIC)
5238 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5240 macro_build ((char *) NULL, &icnt, &offset_expr,
5241 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
5242 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
5251 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5252 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5254 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5256 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5257 "d,v,t", treg, tempreg, breg);
5266 /* The j instruction may not be used in PIC code, since it
5267 requires an absolute address. We convert it to a b
5269 if (mips_pic == NO_PIC)
5270 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5272 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5275 /* The jal instructions must be handled as macros because when
5276 generating PIC code they expand to multi-instruction
5277 sequences. Normally they are simple instructions. */
5282 if (mips_pic == NO_PIC
5283 || mips_pic == EMBEDDED_PIC)
5284 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5286 else if (mips_pic == SVR4_PIC)
5288 if (sreg != PIC_CALL_REG)
5289 as_warn (_("MIPS PIC call to register other than $25"));
5291 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5295 if (mips_cprestore_offset < 0)
5296 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5299 if (! mips_frame_reg_valid)
5301 as_warn (_("No .frame pseudo-op used in PIC code"));
5302 /* Quiet this warning. */
5303 mips_frame_reg_valid = 1;
5305 if (! mips_cprestore_valid)
5307 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5308 /* Quiet this warning. */
5309 mips_cprestore_valid = 1;
5311 expr1.X_add_number = mips_cprestore_offset;
5312 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5313 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5314 mips_gp_register, mips_frame_reg);
5324 if (mips_pic == NO_PIC)
5325 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5326 else if (mips_pic == SVR4_PIC)
5330 /* If this is a reference to an external symbol, and we are
5331 using a small GOT, we want
5332 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5336 lw $gp,cprestore($sp)
5337 The cprestore value is set using the .cprestore
5338 pseudo-op. If we are using a big GOT, we want
5339 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5341 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5345 lw $gp,cprestore($sp)
5346 If the symbol is not external, we want
5347 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5349 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5352 lw $gp,cprestore($sp)
5354 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5355 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5359 macro_build ((char *) NULL, &icnt, &offset_expr,
5360 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5361 "t,o(b)", PIC_CALL_REG,
5362 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5363 macro_build_jalr (icnt, &offset_expr);
5370 macro_build ((char *) NULL, &icnt, &offset_expr,
5371 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5372 "t,o(b)", PIC_CALL_REG,
5373 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5374 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5376 p = frag_var (rs_machine_dependent, 4, 0,
5377 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5378 offset_expr.X_add_symbol, 0, NULL);
5384 if (reg_needs_delay (mips_gp_register))
5388 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5389 "t,u", PIC_CALL_REG,
5390 (int) BFD_RELOC_MIPS_CALL_HI16);
5391 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5392 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5393 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5395 macro_build ((char *) NULL, &icnt, &offset_expr,
5396 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5397 "t,o(b)", PIC_CALL_REG,
5398 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5399 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5401 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5402 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5404 offset_expr.X_add_symbol, 0, NULL);
5407 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5410 macro_build (p, &icnt, &offset_expr,
5411 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5412 "t,o(b)", PIC_CALL_REG,
5413 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5415 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5418 macro_build (p, &icnt, &offset_expr,
5419 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5420 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5421 (int) BFD_RELOC_LO16);
5422 macro_build_jalr (icnt, &offset_expr);
5424 if (mips_cprestore_offset < 0)
5425 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5428 if (! mips_frame_reg_valid)
5430 as_warn (_("No .frame pseudo-op used in PIC code"));
5431 /* Quiet this warning. */
5432 mips_frame_reg_valid = 1;
5434 if (! mips_cprestore_valid)
5436 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5437 /* Quiet this warning. */
5438 mips_cprestore_valid = 1;
5440 if (mips_opts.noreorder)
5441 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5443 expr1.X_add_number = mips_cprestore_offset;
5444 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5445 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5446 mips_gp_register, mips_frame_reg);
5450 else if (mips_pic == EMBEDDED_PIC)
5452 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5453 /* The linker may expand the call to a longer sequence which
5454 uses $at, so we must break rather than return. */
5479 /* Itbl support may require additional care here. */
5484 /* Itbl support may require additional care here. */
5489 /* Itbl support may require additional care here. */
5494 /* Itbl support may require additional care here. */
5506 if (mips_arch == CPU_R4650)
5508 as_bad (_("opcode not supported on this processor"));
5512 /* Itbl support may require additional care here. */
5517 /* Itbl support may require additional care here. */
5522 /* Itbl support may require additional care here. */
5542 if (breg == treg || coproc || lr)
5564 /* Itbl support may require additional care here. */
5569 /* Itbl support may require additional care here. */
5574 /* Itbl support may require additional care here. */
5579 /* Itbl support may require additional care here. */
5595 if (mips_arch == CPU_R4650)
5597 as_bad (_("opcode not supported on this processor"));
5602 /* Itbl support may require additional care here. */
5606 /* Itbl support may require additional care here. */
5611 /* Itbl support may require additional care here. */
5623 /* Itbl support may require additional care here. */
5624 if (mask == M_LWC1_AB
5625 || mask == M_SWC1_AB
5626 || mask == M_LDC1_AB
5627 || mask == M_SDC1_AB
5636 /* For embedded PIC, we allow loads where the offset is calculated
5637 by subtracting a symbol in the current segment from an unknown
5638 symbol, relative to a base register, e.g.:
5639 <op> $treg, <sym>-<localsym>($breg)
5640 This is used by the compiler for switch statements. */
5641 if (mips_pic == EMBEDDED_PIC
5642 && offset_expr.X_op == O_subtract
5643 && (symbol_constant_p (offset_expr.X_op_symbol)
5644 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5645 : (symbol_equated_p (offset_expr.X_op_symbol)
5647 (symbol_get_value_expression (offset_expr.X_op_symbol)
5651 && (offset_expr.X_add_number == 0
5652 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5654 /* For this case, we output the instructions:
5655 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5656 addiu $tempreg,$tempreg,$breg
5657 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5658 If the relocation would fit entirely in 16 bits, it would be
5660 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5661 instead, but that seems quite difficult. */
5662 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5663 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5664 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5665 ((bfd_arch_bits_per_address (stdoutput) == 32
5666 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5667 ? "addu" : "daddu"),
5668 "d,v,t", tempreg, tempreg, breg);
5669 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5670 (int) BFD_RELOC_PCREL_LO16, tempreg);
5676 if (offset_expr.X_op != O_constant
5677 && offset_expr.X_op != O_symbol)
5679 as_bad (_("expression too complex"));
5680 offset_expr.X_op = O_constant;
5683 /* A constant expression in PIC code can be handled just as it
5684 is in non PIC code. */
5685 if (mips_pic == NO_PIC
5686 || offset_expr.X_op == O_constant)
5690 /* If this is a reference to a GP relative symbol, and there
5691 is no base register, we want
5692 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5693 Otherwise, if there is no base register, we want
5694 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5695 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5696 If we have a constant, we need two instructions anyhow,
5697 so we always use the latter form.
5699 If we have a base register, and this is a reference to a
5700 GP relative symbol, we want
5701 addu $tempreg,$breg,$gp
5702 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5704 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5705 addu $tempreg,$tempreg,$breg
5706 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5707 With a constant we always use the latter case.
5709 With 64bit address space and no base register and $at usable,
5711 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5712 lui $at,<sym> (BFD_RELOC_HI16_S)
5713 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5716 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5717 If we have a base register, we want
5718 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5719 lui $at,<sym> (BFD_RELOC_HI16_S)
5720 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5724 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5726 Without $at we can't generate the optimal path for superscalar
5727 processors here since this would require two temporary registers.
5728 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5729 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5731 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5733 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5734 If we have a base register, we want
5735 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5736 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5738 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5740 daddu $tempreg,$tempreg,$breg
5741 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5743 If we have 64-bit addresses, as an optimization, for
5744 addresses which are 32-bit constants (e.g. kseg0/kseg1
5745 addresses) we fall back to the 32-bit address generation
5746 mechanism since it is more efficient. Note that due to
5747 the signed offset used by memory operations, the 32-bit
5748 range is shifted down by 32768 here. This code should
5749 probably attempt to generate 64-bit constants more
5750 efficiently in general.
5752 if (HAVE_64BIT_ADDRESSES
5753 && !(offset_expr.X_op == O_constant
5754 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5758 /* We don't do GP optimization for now because RELAX_ENCODE can't
5759 hold the data for such large chunks. */
5761 if (used_at == 0 && ! mips_opts.noat)
5763 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5764 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5765 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5766 AT, (int) BFD_RELOC_HI16_S);
5767 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5768 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5770 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5771 "d,v,t", AT, AT, breg);
5772 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5773 "d,w,<", tempreg, tempreg, 0);
5774 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5775 "d,v,t", tempreg, tempreg, AT);
5776 macro_build (p, &icnt, &offset_expr, s,
5777 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5782 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5783 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5784 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5785 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5786 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5787 "d,w,<", tempreg, tempreg, 16);
5788 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5789 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5790 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5791 "d,w,<", tempreg, tempreg, 16);
5793 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5794 "d,v,t", tempreg, tempreg, breg);
5795 macro_build (p, &icnt, &offset_expr, s,
5796 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5804 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5805 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5810 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5811 treg, (int) BFD_RELOC_GPREL16,
5813 p = frag_var (rs_machine_dependent, 8, 0,
5814 RELAX_ENCODE (4, 8, 0, 4, 0,
5815 (mips_opts.warn_about_macros
5817 && mips_opts.noat))),
5818 offset_expr.X_add_symbol, 0, NULL);
5821 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5824 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5825 (int) BFD_RELOC_LO16, tempreg);
5829 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5830 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5835 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5836 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5837 "d,v,t", tempreg, breg, mips_gp_register);
5838 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5839 treg, (int) BFD_RELOC_GPREL16, tempreg);
5840 p = frag_var (rs_machine_dependent, 12, 0,
5841 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5842 offset_expr.X_add_symbol, 0, NULL);
5844 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5847 macro_build (p, &icnt, (expressionS *) NULL,
5848 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5849 "d,v,t", tempreg, tempreg, breg);
5852 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5853 (int) BFD_RELOC_LO16, tempreg);
5856 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5859 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5861 /* If this is a reference to an external symbol, we want
5862 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5864 <op> $treg,0($tempreg)
5866 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5868 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5869 <op> $treg,0($tempreg)
5870 If we have NewABI, we want
5871 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5872 If there is a base register, we add it to $tempreg before
5873 the <op>. If there is a constant, we stick it in the
5874 <op> instruction. We don't handle constants larger than
5875 16 bits, because we have no way to load the upper 16 bits
5876 (actually, we could handle them for the subset of cases
5877 in which we are not using $at). */
5878 assert (offset_expr.X_op == O_symbol);
5879 expr1.X_add_number = offset_expr.X_add_number;
5880 offset_expr.X_add_number = 0;
5882 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5883 if (expr1.X_add_number < -0x8000
5884 || expr1.X_add_number >= 0x8000)
5885 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5887 macro_build ((char *) NULL, &icnt, &offset_expr,
5888 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5889 (int) lw_reloc_type, mips_gp_register);
5890 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5891 p = frag_var (rs_machine_dependent, 4, 0,
5892 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5893 offset_expr.X_add_symbol, 0, NULL);
5894 macro_build (p, &icnt, &offset_expr,
5895 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5896 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5898 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5899 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5900 "d,v,t", tempreg, tempreg, breg);
5901 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5902 (int) BFD_RELOC_LO16, tempreg);
5904 else if (mips_pic == SVR4_PIC)
5909 /* If this is a reference to an external symbol, we want
5910 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5911 addu $tempreg,$tempreg,$gp
5912 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5913 <op> $treg,0($tempreg)
5915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5917 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5918 <op> $treg,0($tempreg)
5919 If there is a base register, we add it to $tempreg before
5920 the <op>. If there is a constant, we stick it in the
5921 <op> instruction. We don't handle constants larger than
5922 16 bits, because we have no way to load the upper 16 bits
5923 (actually, we could handle them for the subset of cases
5924 in which we are not using $at).
5927 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5928 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5929 <op> $treg,0($tempreg)
5931 assert (offset_expr.X_op == O_symbol);
5932 expr1.X_add_number = offset_expr.X_add_number;
5933 offset_expr.X_add_number = 0;
5934 if (expr1.X_add_number < -0x8000
5935 || expr1.X_add_number >= 0x8000)
5936 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5939 macro_build ((char *) NULL, &icnt, &offset_expr,
5940 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5941 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5943 macro_build ((char *) NULL, &icnt, &offset_expr,
5944 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5945 "t,r,j", tempreg, tempreg,
5946 BFD_RELOC_MIPS_GOT_OFST);
5948 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5949 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5950 "d,v,t", tempreg, tempreg, breg);
5951 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5952 (int) BFD_RELOC_LO16, tempreg);
5959 if (reg_needs_delay (mips_gp_register))
5964 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5965 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5966 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5967 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5968 "d,v,t", tempreg, tempreg, mips_gp_register);
5969 macro_build ((char *) NULL, &icnt, &offset_expr,
5970 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5971 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5973 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5974 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5975 offset_expr.X_add_symbol, 0, NULL);
5978 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5981 macro_build (p, &icnt, &offset_expr,
5982 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5983 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5986 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5988 macro_build (p, &icnt, &offset_expr,
5989 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5990 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5992 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5993 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5994 "d,v,t", tempreg, tempreg, breg);
5995 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5996 (int) BFD_RELOC_LO16, tempreg);
5998 else if (mips_pic == EMBEDDED_PIC)
6000 /* If there is no base register, we want
6001 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6002 If there is a base register, we want
6003 addu $tempreg,$breg,$gp
6004 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6006 assert (offset_expr.X_op == O_symbol);
6009 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6010 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
6015 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6016 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6017 "d,v,t", tempreg, breg, mips_gp_register);
6018 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6019 treg, (int) BFD_RELOC_GPREL16, tempreg);
6032 load_register (&icnt, treg, &imm_expr, 0);
6036 load_register (&icnt, treg, &imm_expr, 1);
6040 if (imm_expr.X_op == O_constant)
6042 load_register (&icnt, AT, &imm_expr, 0);
6043 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6044 "mtc1", "t,G", AT, treg);
6049 assert (offset_expr.X_op == O_symbol
6050 && strcmp (segment_name (S_GET_SEGMENT
6051 (offset_expr.X_add_symbol)),
6053 && offset_expr.X_add_number == 0);
6054 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6055 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6060 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6061 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6062 order 32 bits of the value and the low order 32 bits are either
6063 zero or in OFFSET_EXPR. */
6064 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6066 if (HAVE_64BIT_GPRS)
6067 load_register (&icnt, treg, &imm_expr, 1);
6072 if (target_big_endian)
6084 load_register (&icnt, hreg, &imm_expr, 0);
6087 if (offset_expr.X_op == O_absent)
6088 move_register (&icnt, lreg, 0);
6091 assert (offset_expr.X_op == O_constant);
6092 load_register (&icnt, lreg, &offset_expr, 0);
6099 /* We know that sym is in the .rdata section. First we get the
6100 upper 16 bits of the address. */
6101 if (mips_pic == NO_PIC)
6103 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6105 else if (mips_pic == SVR4_PIC)
6107 macro_build ((char *) NULL, &icnt, &offset_expr,
6108 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6109 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6112 else if (mips_pic == EMBEDDED_PIC)
6114 /* For embedded PIC we pick up the entire address off $gp in
6115 a single instruction. */
6116 macro_build ((char *) NULL, &icnt, &offset_expr,
6117 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
6118 mips_gp_register, (int) BFD_RELOC_GPREL16);
6119 offset_expr.X_op = O_constant;
6120 offset_expr.X_add_number = 0;
6125 /* Now we load the register(s). */
6126 if (HAVE_64BIT_GPRS)
6127 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
6128 treg, (int) BFD_RELOC_LO16, AT);
6131 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6132 treg, (int) BFD_RELOC_LO16, AT);
6135 /* FIXME: How in the world do we deal with the possible
6137 offset_expr.X_add_number += 4;
6138 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6139 treg + 1, (int) BFD_RELOC_LO16, AT);
6143 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6144 does not become a variant frag. */
6145 frag_wane (frag_now);
6151 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6152 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6153 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6154 the value and the low order 32 bits are either zero or in
6156 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6158 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6159 if (HAVE_64BIT_FPRS)
6161 assert (HAVE_64BIT_GPRS);
6162 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6163 "dmtc1", "t,S", AT, treg);
6167 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6168 "mtc1", "t,G", AT, treg + 1);
6169 if (offset_expr.X_op == O_absent)
6170 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6171 "mtc1", "t,G", 0, treg);
6174 assert (offset_expr.X_op == O_constant);
6175 load_register (&icnt, AT, &offset_expr, 0);
6176 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6177 "mtc1", "t,G", AT, treg);
6183 assert (offset_expr.X_op == O_symbol
6184 && offset_expr.X_add_number == 0);
6185 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6186 if (strcmp (s, ".lit8") == 0)
6188 if (mips_opts.isa != ISA_MIPS1)
6190 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6191 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
6195 breg = mips_gp_register;
6196 r = BFD_RELOC_MIPS_LITERAL;
6201 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6202 if (mips_pic == SVR4_PIC)
6203 macro_build ((char *) NULL, &icnt, &offset_expr,
6204 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6205 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6209 /* FIXME: This won't work for a 64 bit address. */
6210 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6213 if (mips_opts.isa != ISA_MIPS1)
6215 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6216 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
6218 /* To avoid confusion in tc_gen_reloc, we must ensure
6219 that this does not become a variant frag. */
6220 frag_wane (frag_now);
6231 if (mips_arch == CPU_R4650)
6233 as_bad (_("opcode not supported on this processor"));
6236 /* Even on a big endian machine $fn comes before $fn+1. We have
6237 to adjust when loading from memory. */
6240 assert (mips_opts.isa == ISA_MIPS1);
6241 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6242 target_big_endian ? treg + 1 : treg,
6244 /* FIXME: A possible overflow which I don't know how to deal
6246 offset_expr.X_add_number += 4;
6247 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6248 target_big_endian ? treg : treg + 1,
6251 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6252 does not become a variant frag. */
6253 frag_wane (frag_now);
6262 * The MIPS assembler seems to check for X_add_number not
6263 * being double aligned and generating:
6266 * addiu at,at,%lo(foo+1)
6269 * But, the resulting address is the same after relocation so why
6270 * generate the extra instruction?
6272 if (mips_arch == CPU_R4650)
6274 as_bad (_("opcode not supported on this processor"));
6277 /* Itbl support may require additional care here. */
6279 if (mips_opts.isa != ISA_MIPS1)
6290 if (mips_arch == CPU_R4650)
6292 as_bad (_("opcode not supported on this processor"));
6296 if (mips_opts.isa != ISA_MIPS1)
6304 /* Itbl support may require additional care here. */
6309 if (HAVE_64BIT_GPRS)
6320 if (HAVE_64BIT_GPRS)
6330 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6331 loads for the case of doing a pair of loads to simulate an 'ld'.
6332 This is not currently done by the compiler, and assembly coders
6333 writing embedded-pic code can cope. */
6335 if (offset_expr.X_op != O_symbol
6336 && offset_expr.X_op != O_constant)
6338 as_bad (_("expression too complex"));
6339 offset_expr.X_op = O_constant;
6342 /* Even on a big endian machine $fn comes before $fn+1. We have
6343 to adjust when loading from memory. We set coproc if we must
6344 load $fn+1 first. */
6345 /* Itbl support may require additional care here. */
6346 if (! target_big_endian)
6349 if (mips_pic == NO_PIC
6350 || offset_expr.X_op == O_constant)
6354 /* If this is a reference to a GP relative symbol, we want
6355 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6356 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6357 If we have a base register, we use this
6359 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6360 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6361 If this is not a GP relative symbol, we want
6362 lui $at,<sym> (BFD_RELOC_HI16_S)
6363 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6364 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6365 If there is a base register, we add it to $at after the
6366 lui instruction. If there is a constant, we always use
6368 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6369 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6381 tempreg = mips_gp_register;
6388 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6389 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6390 "d,v,t", AT, breg, mips_gp_register);
6396 /* Itbl support may require additional care here. */
6397 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6398 coproc ? treg + 1 : treg,
6399 (int) BFD_RELOC_GPREL16, tempreg);
6400 offset_expr.X_add_number += 4;
6402 /* Set mips_optimize to 2 to avoid inserting an
6404 hold_mips_optimize = mips_optimize;
6406 /* Itbl support may require additional care here. */
6407 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6408 coproc ? treg : treg + 1,
6409 (int) BFD_RELOC_GPREL16, tempreg);
6410 mips_optimize = hold_mips_optimize;
6412 p = frag_var (rs_machine_dependent, 12 + off, 0,
6413 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6414 used_at && mips_opts.noat),
6415 offset_expr.X_add_symbol, 0, NULL);
6417 /* We just generated two relocs. When tc_gen_reloc
6418 handles this case, it will skip the first reloc and
6419 handle the second. The second reloc already has an
6420 extra addend of 4, which we added above. We must
6421 subtract it out, and then subtract another 4 to make
6422 the first reloc come out right. The second reloc
6423 will come out right because we are going to add 4 to
6424 offset_expr when we build its instruction below.
6426 If we have a symbol, then we don't want to include
6427 the offset, because it will wind up being included
6428 when we generate the reloc. */
6430 if (offset_expr.X_op == O_constant)
6431 offset_expr.X_add_number -= 8;
6434 offset_expr.X_add_number = -4;
6435 offset_expr.X_op = O_constant;
6438 macro_build_lui (p, &icnt, &offset_expr, AT);
6443 macro_build (p, &icnt, (expressionS *) NULL,
6444 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6445 "d,v,t", AT, breg, AT);
6449 /* Itbl support may require additional care here. */
6450 macro_build (p, &icnt, &offset_expr, s, fmt,
6451 coproc ? treg + 1 : treg,
6452 (int) BFD_RELOC_LO16, AT);
6455 /* FIXME: How do we handle overflow here? */
6456 offset_expr.X_add_number += 4;
6457 /* Itbl support may require additional care here. */
6458 macro_build (p, &icnt, &offset_expr, s, fmt,
6459 coproc ? treg : treg + 1,
6460 (int) BFD_RELOC_LO16, AT);
6462 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6466 /* If this is a reference to an external symbol, we want
6467 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6472 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6474 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6475 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6476 If there is a base register we add it to $at before the
6477 lwc1 instructions. If there is a constant we include it
6478 in the lwc1 instructions. */
6480 expr1.X_add_number = offset_expr.X_add_number;
6481 offset_expr.X_add_number = 0;
6482 if (expr1.X_add_number < -0x8000
6483 || expr1.X_add_number >= 0x8000 - 4)
6484 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6489 frag_grow (24 + off);
6490 macro_build ((char *) NULL, &icnt, &offset_expr,
6491 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6492 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6493 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6495 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6496 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6497 "d,v,t", AT, breg, AT);
6498 /* Itbl support may require additional care here. */
6499 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6500 coproc ? treg + 1 : treg,
6501 (int) BFD_RELOC_LO16, AT);
6502 expr1.X_add_number += 4;
6504 /* Set mips_optimize to 2 to avoid inserting an undesired
6506 hold_mips_optimize = mips_optimize;
6508 /* Itbl support may require additional care here. */
6509 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6510 coproc ? treg : treg + 1,
6511 (int) BFD_RELOC_LO16, AT);
6512 mips_optimize = hold_mips_optimize;
6514 (void) frag_var (rs_machine_dependent, 0, 0,
6515 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6516 offset_expr.X_add_symbol, 0, NULL);
6518 else if (mips_pic == SVR4_PIC)
6523 /* If this is a reference to an external symbol, we want
6524 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6526 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6531 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6533 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6534 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6535 If there is a base register we add it to $at before the
6536 lwc1 instructions. If there is a constant we include it
6537 in the lwc1 instructions. */
6539 expr1.X_add_number = offset_expr.X_add_number;
6540 offset_expr.X_add_number = 0;
6541 if (expr1.X_add_number < -0x8000
6542 || expr1.X_add_number >= 0x8000 - 4)
6543 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6544 if (reg_needs_delay (mips_gp_register))
6553 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6554 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6555 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6556 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6557 "d,v,t", AT, AT, mips_gp_register);
6558 macro_build ((char *) NULL, &icnt, &offset_expr,
6559 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6560 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6561 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6563 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6564 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6565 "d,v,t", AT, breg, AT);
6566 /* Itbl support may require additional care here. */
6567 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6568 coproc ? treg + 1 : treg,
6569 (int) BFD_RELOC_LO16, AT);
6570 expr1.X_add_number += 4;
6572 /* Set mips_optimize to 2 to avoid inserting an undesired
6574 hold_mips_optimize = mips_optimize;
6576 /* Itbl support may require additional care here. */
6577 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6578 coproc ? treg : treg + 1,
6579 (int) BFD_RELOC_LO16, AT);
6580 mips_optimize = hold_mips_optimize;
6581 expr1.X_add_number -= 4;
6583 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6584 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6585 8 + gpdel + off, 1, 0),
6586 offset_expr.X_add_symbol, 0, NULL);
6589 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6592 macro_build (p, &icnt, &offset_expr,
6593 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6594 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6597 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6601 macro_build (p, &icnt, (expressionS *) NULL,
6602 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6603 "d,v,t", AT, breg, AT);
6606 /* Itbl support may require additional care here. */
6607 macro_build (p, &icnt, &expr1, s, fmt,
6608 coproc ? treg + 1 : treg,
6609 (int) BFD_RELOC_LO16, AT);
6611 expr1.X_add_number += 4;
6613 /* Set mips_optimize to 2 to avoid inserting an undesired
6615 hold_mips_optimize = mips_optimize;
6617 /* Itbl support may require additional care here. */
6618 macro_build (p, &icnt, &expr1, s, fmt,
6619 coproc ? treg : treg + 1,
6620 (int) BFD_RELOC_LO16, AT);
6621 mips_optimize = hold_mips_optimize;
6623 else if (mips_pic == EMBEDDED_PIC)
6625 /* If there is no base register, we use
6626 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6627 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6628 If we have a base register, we use
6630 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6631 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6635 tempreg = mips_gp_register;
6640 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6641 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6642 "d,v,t", AT, breg, mips_gp_register);
6647 /* Itbl support may require additional care here. */
6648 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6649 coproc ? treg + 1 : treg,
6650 (int) BFD_RELOC_GPREL16, tempreg);
6651 offset_expr.X_add_number += 4;
6652 /* Itbl support may require additional care here. */
6653 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6654 coproc ? treg : treg + 1,
6655 (int) BFD_RELOC_GPREL16, tempreg);
6671 assert (HAVE_32BIT_ADDRESSES);
6672 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6673 (int) BFD_RELOC_LO16, breg);
6674 offset_expr.X_add_number += 4;
6675 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6676 (int) BFD_RELOC_LO16, breg);
6679 /* New code added to support COPZ instructions.
6680 This code builds table entries out of the macros in mip_opcodes.
6681 R4000 uses interlocks to handle coproc delays.
6682 Other chips (like the R3000) require nops to be inserted for delays.
6684 FIXME: Currently, we require that the user handle delays.
6685 In order to fill delay slots for non-interlocked chips,
6686 we must have a way to specify delays based on the coprocessor.
6687 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6688 What are the side-effects of the cop instruction?
6689 What cache support might we have and what are its effects?
6690 Both coprocessor & memory require delays. how long???
6691 What registers are read/set/modified?
6693 If an itbl is provided to interpret cop instructions,
6694 this knowledge can be encoded in the itbl spec. */
6708 /* For now we just do C (same as Cz). The parameter will be
6709 stored in insn_opcode by mips_ip. */
6710 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6715 move_register (&icnt, dreg, sreg);
6718 #ifdef LOSING_COMPILER
6720 /* Try and see if this is a new itbl instruction.
6721 This code builds table entries out of the macros in mip_opcodes.
6722 FIXME: For now we just assemble the expression and pass it's
6723 value along as a 32-bit immediate.
6724 We may want to have the assembler assemble this value,
6725 so that we gain the assembler's knowledge of delay slots,
6727 Would it be more efficient to use mask (id) here? */
6728 if (itbl_have_entries
6729 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6731 s = ip->insn_mo->name;
6733 coproc = ITBL_DECODE_PNUM (immed_expr);;
6734 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6741 as_warn (_("Macro used $at after \".set noat\""));
6746 struct mips_cl_insn *ip;
6748 register int treg, sreg, dreg, breg;
6764 bfd_reloc_code_real_type r;
6767 treg = (ip->insn_opcode >> 16) & 0x1f;
6768 dreg = (ip->insn_opcode >> 11) & 0x1f;
6769 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6770 mask = ip->insn_mo->mask;
6772 expr1.X_op = O_constant;
6773 expr1.X_op_symbol = NULL;
6774 expr1.X_add_symbol = NULL;
6775 expr1.X_add_number = 1;
6779 #endif /* LOSING_COMPILER */
6784 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6785 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6786 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6793 /* The MIPS assembler some times generates shifts and adds. I'm
6794 not trying to be that fancy. GCC should do this for us
6796 load_register (&icnt, AT, &imm_expr, dbl);
6797 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6798 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6799 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6813 mips_emit_delays (true);
6814 ++mips_opts.noreorder;
6815 mips_any_noreorder = 1;
6817 load_register (&icnt, AT, &imm_expr, dbl);
6818 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6819 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6820 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6822 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6823 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6824 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6827 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6828 "s,t,q", dreg, AT, 6);
6831 expr1.X_add_number = 8;
6832 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6834 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6836 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6839 --mips_opts.noreorder;
6840 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6853 mips_emit_delays (true);
6854 ++mips_opts.noreorder;
6855 mips_any_noreorder = 1;
6857 load_register (&icnt, AT, &imm_expr, dbl);
6858 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6859 dbl ? "dmultu" : "multu",
6860 "s,t", sreg, imm ? AT : treg);
6861 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6863 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6866 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6870 expr1.X_add_number = 8;
6871 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6872 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6874 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6877 --mips_opts.noreorder;
6881 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6882 "d,v,t", AT, 0, treg);
6883 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6884 "d,t,s", AT, sreg, AT);
6885 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6886 "d,t,s", dreg, sreg, treg);
6887 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6888 "d,v,t", dreg, dreg, AT);
6892 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6893 "d,v,t", AT, 0, treg);
6894 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6895 "d,t,s", AT, sreg, AT);
6896 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6897 "d,t,s", dreg, sreg, treg);
6898 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6899 "d,v,t", dreg, dreg, AT);
6906 if (imm_expr.X_op != O_constant)
6907 as_bad (_("rotate count too large"));
6908 rot = imm_expr.X_add_number & 0x3f;
6909 if (CPU_HAS_DROR (mips_arch))
6911 rot = (64 - rot) & 0x3f;
6913 macro_build ((char *) NULL, &icnt, NULL, "dror32",
6914 "d,w,<", dreg, sreg, rot - 32);
6916 macro_build ((char *) NULL, &icnt, NULL, "dror",
6917 "d,w,<", dreg, sreg, rot);
6921 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
6922 "d,w,<", dreg, sreg, 0);
6927 l = (rot < 0x20) ? "dsll" : "dsll32";
6928 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6930 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6931 "d,w,<", AT, sreg, rot);
6932 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6933 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6934 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6935 "d,v,t", dreg, dreg, AT);
6944 if (imm_expr.X_op != O_constant)
6945 as_bad (_("rotate count too large"));
6946 rot = imm_expr.X_add_number & 0x1f;
6947 if (CPU_HAS_ROR (mips_arch))
6949 macro_build ((char *) NULL, &icnt, NULL, "ror",
6950 "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
6954 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6955 "d,w,<", dreg, sreg, 0);
6958 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6959 "d,w,<", AT, sreg, rot);
6960 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6961 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6962 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6963 "d,v,t", dreg, dreg, AT);
6969 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6970 "d,v,t", AT, 0, treg);
6971 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6972 "d,t,s", AT, sreg, AT);
6973 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6974 "d,t,s", dreg, sreg, treg);
6975 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6976 "d,v,t", dreg, dreg, AT);
6980 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6981 "d,v,t", AT, 0, treg);
6982 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6983 "d,t,s", AT, sreg, AT);
6984 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6985 "d,t,s", dreg, sreg, treg);
6986 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6987 "d,v,t", dreg, dreg, AT);
6994 if (imm_expr.X_op != O_constant)
6995 as_bad (_("rotate count too large"));
6996 rot = imm_expr.X_add_number & 0x3f;
6998 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
6999 "d,w,<", dreg, sreg, 0);
7004 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7005 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7007 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
7008 "d,w,<", AT, sreg, rot);
7009 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
7010 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7011 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7012 "d,v,t", dreg, dreg, AT);
7021 if (imm_expr.X_op != O_constant)
7022 as_bad (_("rotate count too large"));
7023 rot = imm_expr.X_add_number & 0x1f;
7025 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7026 "d,w,<", dreg, sreg, 0);
7029 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
7030 "d,w,<", AT, sreg, rot);
7031 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
7032 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7033 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
7034 "d,v,t", dreg, dreg, AT);
7040 if (mips_arch == CPU_R4650)
7042 as_bad (_("opcode not supported on this processor"));
7045 assert (mips_opts.isa == ISA_MIPS1);
7046 /* Even on a big endian machine $fn comes before $fn+1. We have
7047 to adjust when storing to memory. */
7048 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7049 target_big_endian ? treg + 1 : treg,
7050 (int) BFD_RELOC_LO16, breg);
7051 offset_expr.X_add_number += 4;
7052 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7053 target_big_endian ? treg : treg + 1,
7054 (int) BFD_RELOC_LO16, breg);
7059 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7060 treg, (int) BFD_RELOC_LO16);
7062 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7063 sreg, (int) BFD_RELOC_LO16);
7066 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7067 "d,v,t", dreg, sreg, treg);
7068 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7069 dreg, (int) BFD_RELOC_LO16);
7074 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7076 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
7077 sreg, (int) BFD_RELOC_LO16);
7082 as_warn (_("Instruction %s: result is always false"),
7084 move_register (&icnt, dreg, 0);
7087 if (imm_expr.X_op == O_constant
7088 && imm_expr.X_add_number >= 0
7089 && imm_expr.X_add_number < 0x10000)
7091 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
7092 sreg, (int) BFD_RELOC_LO16);
7095 else if (imm_expr.X_op == O_constant
7096 && imm_expr.X_add_number > -0x8000
7097 && imm_expr.X_add_number < 0)
7099 imm_expr.X_add_number = -imm_expr.X_add_number;
7100 macro_build ((char *) NULL, &icnt, &imm_expr,
7101 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7102 "t,r,j", dreg, sreg,
7103 (int) BFD_RELOC_LO16);
7108 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7109 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7110 "d,v,t", dreg, sreg, AT);
7113 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7114 (int) BFD_RELOC_LO16);
7119 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7125 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7127 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7128 (int) BFD_RELOC_LO16);
7131 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7133 if (imm_expr.X_op == O_constant
7134 && imm_expr.X_add_number >= -0x8000
7135 && imm_expr.X_add_number < 0x8000)
7137 macro_build ((char *) NULL, &icnt, &imm_expr,
7138 mask == M_SGE_I ? "slti" : "sltiu",
7139 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7144 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7145 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7146 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
7150 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7151 (int) BFD_RELOC_LO16);
7156 case M_SGT: /* sreg > treg <==> treg < sreg */
7162 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7166 case M_SGT_I: /* sreg > I <==> I < sreg */
7172 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7173 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7177 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7183 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7185 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7186 (int) BFD_RELOC_LO16);
7189 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7195 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7196 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
7198 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7199 (int) BFD_RELOC_LO16);
7203 if (imm_expr.X_op == O_constant
7204 && imm_expr.X_add_number >= -0x8000
7205 && imm_expr.X_add_number < 0x8000)
7207 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
7208 dreg, sreg, (int) BFD_RELOC_LO16);
7211 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7212 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
7217 if (imm_expr.X_op == O_constant
7218 && imm_expr.X_add_number >= -0x8000
7219 && imm_expr.X_add_number < 0x8000)
7221 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
7222 dreg, sreg, (int) BFD_RELOC_LO16);
7225 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7226 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7227 "d,v,t", dreg, sreg, AT);
7232 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7233 "d,v,t", dreg, 0, treg);
7235 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7236 "d,v,t", dreg, 0, sreg);
7239 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7240 "d,v,t", dreg, sreg, treg);
7241 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7242 "d,v,t", dreg, 0, dreg);
7247 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7249 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7250 "d,v,t", dreg, 0, sreg);
7255 as_warn (_("Instruction %s: result is always true"),
7257 macro_build ((char *) NULL, &icnt, &expr1,
7258 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7259 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
7262 if (imm_expr.X_op == O_constant
7263 && imm_expr.X_add_number >= 0
7264 && imm_expr.X_add_number < 0x10000)
7266 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
7267 dreg, sreg, (int) BFD_RELOC_LO16);
7270 else if (imm_expr.X_op == O_constant
7271 && imm_expr.X_add_number > -0x8000
7272 && imm_expr.X_add_number < 0)
7274 imm_expr.X_add_number = -imm_expr.X_add_number;
7275 macro_build ((char *) NULL, &icnt, &imm_expr,
7276 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7277 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7282 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7283 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7284 "d,v,t", dreg, sreg, AT);
7287 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7288 "d,v,t", dreg, 0, dreg);
7296 if (imm_expr.X_op == O_constant
7297 && imm_expr.X_add_number > -0x8000
7298 && imm_expr.X_add_number <= 0x8000)
7300 imm_expr.X_add_number = -imm_expr.X_add_number;
7301 macro_build ((char *) NULL, &icnt, &imm_expr,
7302 dbl ? "daddi" : "addi",
7303 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7306 load_register (&icnt, AT, &imm_expr, dbl);
7307 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7308 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7314 if (imm_expr.X_op == O_constant
7315 && imm_expr.X_add_number > -0x8000
7316 && imm_expr.X_add_number <= 0x8000)
7318 imm_expr.X_add_number = -imm_expr.X_add_number;
7319 macro_build ((char *) NULL, &icnt, &imm_expr,
7320 dbl ? "daddiu" : "addiu",
7321 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7324 load_register (&icnt, AT, &imm_expr, dbl);
7325 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7326 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7347 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7348 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7354 assert (mips_opts.isa == ISA_MIPS1);
7355 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7356 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7359 * Is the double cfc1 instruction a bug in the mips assembler;
7360 * or is there a reason for it?
7362 mips_emit_delays (true);
7363 ++mips_opts.noreorder;
7364 mips_any_noreorder = 1;
7365 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7367 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7369 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7370 expr1.X_add_number = 3;
7371 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7372 (int) BFD_RELOC_LO16);
7373 expr1.X_add_number = 2;
7374 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7375 (int) BFD_RELOC_LO16);
7376 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7378 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7379 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7380 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7381 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7383 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7384 --mips_opts.noreorder;
7393 if (offset_expr.X_add_number >= 0x7fff)
7394 as_bad (_("operand overflow"));
7395 /* avoid load delay */
7396 if (! target_big_endian)
7397 ++offset_expr.X_add_number;
7398 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7399 (int) BFD_RELOC_LO16, breg);
7400 if (! target_big_endian)
7401 --offset_expr.X_add_number;
7403 ++offset_expr.X_add_number;
7404 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7405 (int) BFD_RELOC_LO16, breg);
7406 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7408 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7422 if (offset_expr.X_add_number >= 0x8000 - off)
7423 as_bad (_("operand overflow"));
7424 if (! target_big_endian)
7425 offset_expr.X_add_number += off;
7426 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7427 (int) BFD_RELOC_LO16, breg);
7428 if (! target_big_endian)
7429 offset_expr.X_add_number -= off;
7431 offset_expr.X_add_number += off;
7432 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7433 (int) BFD_RELOC_LO16, breg);
7447 load_address (&icnt, AT, &offset_expr, &used_at);
7449 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7450 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7451 "d,v,t", AT, AT, breg);
7452 if (! target_big_endian)
7453 expr1.X_add_number = off;
7455 expr1.X_add_number = 0;
7456 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7457 (int) BFD_RELOC_LO16, AT);
7458 if (! target_big_endian)
7459 expr1.X_add_number = 0;
7461 expr1.X_add_number = off;
7462 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7463 (int) BFD_RELOC_LO16, AT);
7469 load_address (&icnt, AT, &offset_expr, &used_at);
7471 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7472 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7473 "d,v,t", AT, AT, breg);
7474 if (target_big_endian)
7475 expr1.X_add_number = 0;
7476 macro_build ((char *) NULL, &icnt, &expr1,
7477 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7478 (int) BFD_RELOC_LO16, AT);
7479 if (target_big_endian)
7480 expr1.X_add_number = 1;
7482 expr1.X_add_number = 0;
7483 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7484 (int) BFD_RELOC_LO16, AT);
7485 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7487 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7492 if (offset_expr.X_add_number >= 0x7fff)
7493 as_bad (_("operand overflow"));
7494 if (target_big_endian)
7495 ++offset_expr.X_add_number;
7496 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7497 (int) BFD_RELOC_LO16, breg);
7498 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7500 if (target_big_endian)
7501 --offset_expr.X_add_number;
7503 ++offset_expr.X_add_number;
7504 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7505 (int) BFD_RELOC_LO16, breg);
7518 if (offset_expr.X_add_number >= 0x8000 - off)
7519 as_bad (_("operand overflow"));
7520 if (! target_big_endian)
7521 offset_expr.X_add_number += off;
7522 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7523 (int) BFD_RELOC_LO16, breg);
7524 if (! target_big_endian)
7525 offset_expr.X_add_number -= off;
7527 offset_expr.X_add_number += off;
7528 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7529 (int) BFD_RELOC_LO16, breg);
7543 load_address (&icnt, AT, &offset_expr, &used_at);
7545 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7546 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7547 "d,v,t", AT, AT, breg);
7548 if (! target_big_endian)
7549 expr1.X_add_number = off;
7551 expr1.X_add_number = 0;
7552 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7553 (int) BFD_RELOC_LO16, AT);
7554 if (! target_big_endian)
7555 expr1.X_add_number = 0;
7557 expr1.X_add_number = off;
7558 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7559 (int) BFD_RELOC_LO16, AT);
7564 load_address (&icnt, AT, &offset_expr, &used_at);
7566 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7567 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7568 "d,v,t", AT, AT, breg);
7569 if (! target_big_endian)
7570 expr1.X_add_number = 0;
7571 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7572 (int) BFD_RELOC_LO16, AT);
7573 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7575 if (! target_big_endian)
7576 expr1.X_add_number = 1;
7578 expr1.X_add_number = 0;
7579 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7580 (int) BFD_RELOC_LO16, AT);
7581 if (! target_big_endian)
7582 expr1.X_add_number = 0;
7584 expr1.X_add_number = 1;
7585 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7586 (int) BFD_RELOC_LO16, AT);
7587 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7589 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7594 /* FIXME: Check if this is one of the itbl macros, since they
7595 are added dynamically. */
7596 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7600 as_warn (_("Macro used $at after \".set noat\""));
7603 /* Implement macros in mips16 mode. */
7607 struct mips_cl_insn *ip;
7610 int xreg, yreg, zreg, tmp;
7614 const char *s, *s2, *s3;
7616 mask = ip->insn_mo->mask;
7618 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7619 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7620 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7624 expr1.X_op = O_constant;
7625 expr1.X_op_symbol = NULL;
7626 expr1.X_add_symbol = NULL;
7627 expr1.X_add_number = 1;
7646 mips_emit_delays (true);
7647 ++mips_opts.noreorder;
7648 mips_any_noreorder = 1;
7649 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7650 dbl ? "ddiv" : "div",
7651 "0,x,y", xreg, yreg);
7652 expr1.X_add_number = 2;
7653 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7654 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7657 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7658 since that causes an overflow. We should do that as well,
7659 but I don't see how to do the comparisons without a temporary
7661 --mips_opts.noreorder;
7662 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7681 mips_emit_delays (true);
7682 ++mips_opts.noreorder;
7683 mips_any_noreorder = 1;
7684 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7686 expr1.X_add_number = 2;
7687 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7688 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7690 --mips_opts.noreorder;
7691 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7697 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7698 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7699 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7708 if (imm_expr.X_op != O_constant)
7709 as_bad (_("Unsupported large constant"));
7710 imm_expr.X_add_number = -imm_expr.X_add_number;
7711 macro_build ((char *) NULL, &icnt, &imm_expr,
7712 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7716 if (imm_expr.X_op != O_constant)
7717 as_bad (_("Unsupported large constant"));
7718 imm_expr.X_add_number = -imm_expr.X_add_number;
7719 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7724 if (imm_expr.X_op != O_constant)
7725 as_bad (_("Unsupported large constant"));
7726 imm_expr.X_add_number = -imm_expr.X_add_number;
7727 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7750 goto do_reverse_branch;
7754 goto do_reverse_branch;
7766 goto do_reverse_branch;
7777 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7779 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7806 goto do_addone_branch_i;
7811 goto do_addone_branch_i;
7826 goto do_addone_branch_i;
7833 if (imm_expr.X_op != O_constant)
7834 as_bad (_("Unsupported large constant"));
7835 ++imm_expr.X_add_number;
7838 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7839 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7843 expr1.X_add_number = 0;
7844 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7846 move_register (&icnt, xreg, yreg);
7847 expr1.X_add_number = 2;
7848 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7849 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7850 "neg", "x,w", xreg, xreg);
7854 /* For consistency checking, verify that all bits are specified either
7855 by the match/mask part of the instruction definition, or by the
7858 validate_mips_insn (opc)
7859 const struct mips_opcode *opc;
7861 const char *p = opc->args;
7863 unsigned long used_bits = opc->mask;
7865 if ((used_bits & opc->match) != opc->match)
7867 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7868 opc->name, opc->args);
7871 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7878 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7879 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7881 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7882 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7883 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7884 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7886 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7887 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7889 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7891 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7892 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7893 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7894 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7895 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7896 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7897 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7898 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7899 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7900 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7901 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7902 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7903 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7904 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7905 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7906 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7907 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7909 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7910 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7911 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7912 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7914 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7915 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7916 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7917 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7918 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7919 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7920 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7921 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7922 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7925 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7926 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7927 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7928 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
7929 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
7933 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7934 c, opc->name, opc->args);
7938 if (used_bits != 0xffffffff)
7940 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7941 ~used_bits & 0xffffffff, opc->name, opc->args);
7947 /* This routine assembles an instruction into its binary format. As a
7948 side effect, it sets one of the global variables imm_reloc or
7949 offset_reloc to the type of relocation to do if one of the operands
7950 is an address expression. */
7955 struct mips_cl_insn *ip;
7960 struct mips_opcode *insn;
7963 unsigned int lastregno = 0;
7969 /* If the instruction contains a '.', we first try to match an instruction
7970 including the '.'. Then we try again without the '.'. */
7972 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7975 /* If we stopped on whitespace, then replace the whitespace with null for
7976 the call to hash_find. Save the character we replaced just in case we
7977 have to re-parse the instruction. */
7984 insn = (struct mips_opcode *) hash_find (op_hash, str);
7986 /* If we didn't find the instruction in the opcode table, try again, but
7987 this time with just the instruction up to, but not including the
7991 /* Restore the character we overwrite above (if any). */
7995 /* Scan up to the first '.' or whitespace. */
7997 *s != '\0' && *s != '.' && !ISSPACE (*s);
8001 /* If we did not find a '.', then we can quit now. */
8004 insn_error = "unrecognized opcode";
8008 /* Lookup the instruction in the hash table. */
8010 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8012 insn_error = "unrecognized opcode";
8022 assert (strcmp (insn->name, str) == 0);
8024 if (OPCODE_IS_MEMBER (insn,
8026 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8027 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8028 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8034 if (insn->pinfo != INSN_MACRO)
8036 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8042 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8043 && strcmp (insn->name, insn[1].name) == 0)
8052 static char buf[100];
8053 if (mips_arch_info->is_isa)
8055 _("opcode not supported at this ISA level (%s)"),
8056 mips_cpu_info_from_isa (mips_opts.isa)->name);
8059 _("opcode not supported on this processor: %s (%s)"),
8060 mips_arch_info->name,
8061 mips_cpu_info_from_isa (mips_opts.isa)->name);
8071 ip->insn_opcode = insn->match;
8073 for (args = insn->args;; ++args)
8077 s += strspn (s, " \t");
8081 case '\0': /* end of args */
8094 ip->insn_opcode |= lastregno << OP_SH_RS;
8098 ip->insn_opcode |= lastregno << OP_SH_RT;
8102 ip->insn_opcode |= lastregno << OP_SH_FT;
8106 ip->insn_opcode |= lastregno << OP_SH_FS;
8112 /* Handle optional base register.
8113 Either the base register is omitted or
8114 we must have a left paren. */
8115 /* This is dependent on the next operand specifier
8116 is a base register specification. */
8117 assert (args[1] == 'b' || args[1] == '5'
8118 || args[1] == '-' || args[1] == '4');
8122 case ')': /* these must match exactly */
8129 case '<': /* must be at least one digit */
8131 * According to the manual, if the shift amount is greater
8132 * than 31 or less than 0, then the shift amount should be
8133 * mod 32. In reality the mips assembler issues an error.
8134 * We issue a warning and mask out all but the low 5 bits.
8136 my_getExpression (&imm_expr, s);
8137 check_absolute_expr (ip, &imm_expr);
8138 if ((unsigned long) imm_expr.X_add_number > 31)
8140 as_warn (_("Improper shift amount (%lu)"),
8141 (unsigned long) imm_expr.X_add_number);
8142 imm_expr.X_add_number &= OP_MASK_SHAMT;
8144 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8145 imm_expr.X_op = O_absent;
8149 case '>': /* shift amount minus 32 */
8150 my_getExpression (&imm_expr, s);
8151 check_absolute_expr (ip, &imm_expr);
8152 if ((unsigned long) imm_expr.X_add_number < 32
8153 || (unsigned long) imm_expr.X_add_number > 63)
8155 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8156 imm_expr.X_op = O_absent;
8160 case 'k': /* cache code */
8161 case 'h': /* prefx code */
8162 my_getExpression (&imm_expr, s);
8163 check_absolute_expr (ip, &imm_expr);
8164 if ((unsigned long) imm_expr.X_add_number > 31)
8166 as_warn (_("Invalid value for `%s' (%lu)"),
8168 (unsigned long) imm_expr.X_add_number);
8169 imm_expr.X_add_number &= 0x1f;
8172 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8174 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8175 imm_expr.X_op = O_absent;
8179 case 'c': /* break code */
8180 my_getExpression (&imm_expr, s);
8181 check_absolute_expr (ip, &imm_expr);
8182 if ((unsigned long) imm_expr.X_add_number > 1023)
8184 as_warn (_("Illegal break code (%lu)"),
8185 (unsigned long) imm_expr.X_add_number);
8186 imm_expr.X_add_number &= OP_MASK_CODE;
8188 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8189 imm_expr.X_op = O_absent;
8193 case 'q': /* lower break code */
8194 my_getExpression (&imm_expr, s);
8195 check_absolute_expr (ip, &imm_expr);
8196 if ((unsigned long) imm_expr.X_add_number > 1023)
8198 as_warn (_("Illegal lower break code (%lu)"),
8199 (unsigned long) imm_expr.X_add_number);
8200 imm_expr.X_add_number &= OP_MASK_CODE2;
8202 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8203 imm_expr.X_op = O_absent;
8207 case 'B': /* 20-bit syscall/break code. */
8208 my_getExpression (&imm_expr, s);
8209 check_absolute_expr (ip, &imm_expr);
8210 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8211 as_warn (_("Illegal 20-bit code (%lu)"),
8212 (unsigned long) imm_expr.X_add_number);
8213 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8214 imm_expr.X_op = O_absent;
8218 case 'C': /* Coprocessor code */
8219 my_getExpression (&imm_expr, s);
8220 check_absolute_expr (ip, &imm_expr);
8221 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8223 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8224 (unsigned long) imm_expr.X_add_number);
8225 imm_expr.X_add_number &= ((1 << 25) - 1);
8227 ip->insn_opcode |= imm_expr.X_add_number;
8228 imm_expr.X_op = O_absent;
8232 case 'J': /* 19-bit wait code. */
8233 my_getExpression (&imm_expr, s);
8234 check_absolute_expr (ip, &imm_expr);
8235 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8236 as_warn (_("Illegal 19-bit code (%lu)"),
8237 (unsigned long) imm_expr.X_add_number);
8238 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8239 imm_expr.X_op = O_absent;
8243 case 'P': /* Performance register */
8244 my_getExpression (&imm_expr, s);
8245 check_absolute_expr (ip, &imm_expr);
8246 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8248 as_warn (_("Invalid performance register (%lu)"),
8249 (unsigned long) imm_expr.X_add_number);
8250 imm_expr.X_add_number &= OP_MASK_PERFREG;
8252 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8253 imm_expr.X_op = O_absent;
8257 case 'b': /* base register */
8258 case 'd': /* destination register */
8259 case 's': /* source register */
8260 case 't': /* target register */
8261 case 'r': /* both target and source */
8262 case 'v': /* both dest and source */
8263 case 'w': /* both dest and target */
8264 case 'E': /* coprocessor target register */
8265 case 'G': /* coprocessor destination register */
8266 case 'x': /* ignore register name */
8267 case 'z': /* must be zero register */
8268 case 'U': /* destination register (clo/clz). */
8283 while (ISDIGIT (*s));
8285 as_bad (_("Invalid register number (%d)"), regno);
8287 else if (*args == 'E' || *args == 'G')
8291 if (s[1] == 'r' && s[2] == 'a')
8296 else if (s[1] == 'f' && s[2] == 'p')
8301 else if (s[1] == 's' && s[2] == 'p')
8306 else if (s[1] == 'g' && s[2] == 'p')
8311 else if (s[1] == 'a' && s[2] == 't')
8316 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8321 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8326 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8331 else if (itbl_have_entries)
8336 p = s + 1; /* advance past '$' */
8337 n = itbl_get_field (&p); /* n is name */
8339 /* See if this is a register defined in an
8341 if (itbl_get_reg_val (n, &r))
8343 /* Get_field advances to the start of
8344 the next field, so we need to back
8345 rack to the end of the last field. */
8349 s = strchr (s, '\0');
8362 as_warn (_("Used $at without \".set noat\""));
8368 if (c == 'r' || c == 'v' || c == 'w')
8375 /* 'z' only matches $0. */
8376 if (c == 'z' && regno != 0)
8379 /* Now that we have assembled one operand, we use the args string
8380 * to figure out where it goes in the instruction. */
8387 ip->insn_opcode |= regno << OP_SH_RS;
8391 ip->insn_opcode |= regno << OP_SH_RD;
8394 ip->insn_opcode |= regno << OP_SH_RD;
8395 ip->insn_opcode |= regno << OP_SH_RT;
8400 ip->insn_opcode |= regno << OP_SH_RT;
8403 /* This case exists because on the r3000 trunc
8404 expands into a macro which requires a gp
8405 register. On the r6000 or r4000 it is
8406 assembled into a single instruction which
8407 ignores the register. Thus the insn version
8408 is MIPS_ISA2 and uses 'x', and the macro
8409 version is MIPS_ISA1 and uses 't'. */
8412 /* This case is for the div instruction, which
8413 acts differently if the destination argument
8414 is $0. This only matches $0, and is checked
8415 outside the switch. */
8418 /* Itbl operand; not yet implemented. FIXME ?? */
8420 /* What about all other operands like 'i', which
8421 can be specified in the opcode table? */
8431 ip->insn_opcode |= lastregno << OP_SH_RS;
8434 ip->insn_opcode |= lastregno << OP_SH_RT;
8439 case 'O': /* MDMX alignment immediate constant. */
8440 my_getExpression (&imm_expr, s);
8441 check_absolute_expr (ip, &imm_expr);
8442 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8444 as_warn ("Improper align amount (%ld), using low bits",
8445 (long) imm_expr.X_add_number);
8446 imm_expr.X_add_number &= OP_MASK_ALN;
8448 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8449 imm_expr.X_op = O_absent;
8453 case 'Q': /* MDMX vector, element sel, or const. */
8456 /* MDMX Immediate. */
8457 my_getExpression (&imm_expr, s);
8458 check_absolute_expr (ip, &imm_expr);
8459 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8461 as_warn (_("Invalid MDMX Immediate (%ld)"),
8462 (long) imm_expr.X_add_number);
8463 imm_expr.X_add_number &= OP_MASK_FT;
8465 imm_expr.X_add_number &= OP_MASK_FT;
8466 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8467 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8469 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8470 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8471 imm_expr.X_op = O_absent;
8475 /* Not MDMX Immediate. Fall through. */
8476 case 'X': /* MDMX destination register. */
8477 case 'Y': /* MDMX source register. */
8478 case 'Z': /* MDMX target register. */
8480 case 'D': /* floating point destination register */
8481 case 'S': /* floating point source register */
8482 case 'T': /* floating point target register */
8483 case 'R': /* floating point source register */
8487 /* Accept $fN for FP and MDMX register numbers, and in
8488 addition accept $vN for MDMX register numbers. */
8489 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8490 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8501 while (ISDIGIT (*s));
8504 as_bad (_("Invalid float register number (%d)"), regno);
8506 if ((regno & 1) != 0
8508 && ! (strcmp (str, "mtc1") == 0
8509 || strcmp (str, "mfc1") == 0
8510 || strcmp (str, "lwc1") == 0
8511 || strcmp (str, "swc1") == 0
8512 || strcmp (str, "l.s") == 0
8513 || strcmp (str, "s.s") == 0))
8514 as_warn (_("Float register should be even, was %d"),
8522 if (c == 'V' || c == 'W')
8533 ip->insn_opcode |= regno << OP_SH_FD;
8538 ip->insn_opcode |= regno << OP_SH_FS;
8541 /* This is like 'Z', but also needs to fix the MDMX
8542 vector/scalar select bits. Note that the
8543 scalar immediate case is handled above. */
8546 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8547 int max_el = (is_qh ? 3 : 7);
8549 my_getExpression(&imm_expr, s);
8550 check_absolute_expr (ip, &imm_expr);
8552 if (imm_expr.X_add_number > max_el)
8553 as_bad(_("Bad element selector %ld"),
8554 (long) imm_expr.X_add_number);
8555 imm_expr.X_add_number &= max_el;
8556 ip->insn_opcode |= (imm_expr.X_add_number
8560 as_warn(_("Expecting ']' found '%s'"), s);
8566 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8567 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8570 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8577 ip->insn_opcode |= regno << OP_SH_FT;
8580 ip->insn_opcode |= regno << OP_SH_FR;
8590 ip->insn_opcode |= lastregno << OP_SH_FS;
8593 ip->insn_opcode |= lastregno << OP_SH_FT;
8599 my_getExpression (&imm_expr, s);
8600 if (imm_expr.X_op != O_big
8601 && imm_expr.X_op != O_constant)
8602 insn_error = _("absolute expression required");
8607 my_getExpression (&offset_expr, s);
8608 *imm_reloc = BFD_RELOC_32;
8621 unsigned char temp[8];
8623 unsigned int length;
8628 /* These only appear as the last operand in an
8629 instruction, and every instruction that accepts
8630 them in any variant accepts them in all variants.
8631 This means we don't have to worry about backing out
8632 any changes if the instruction does not match.
8634 The difference between them is the size of the
8635 floating point constant and where it goes. For 'F'
8636 and 'L' the constant is 64 bits; for 'f' and 'l' it
8637 is 32 bits. Where the constant is placed is based
8638 on how the MIPS assembler does things:
8641 f -- immediate value
8644 The .lit4 and .lit8 sections are only used if
8645 permitted by the -G argument.
8647 When generating embedded PIC code, we use the
8648 .lit8 section but not the .lit4 section (we can do
8649 .lit4 inline easily; we need to put .lit8
8650 somewhere in the data segment, and using .lit8
8651 permits the linker to eventually combine identical
8654 The code below needs to know whether the target register
8655 is 32 or 64 bits wide. It relies on the fact 'f' and
8656 'F' are used with GPR-based instructions and 'l' and
8657 'L' are used with FPR-based instructions. */
8659 f64 = *args == 'F' || *args == 'L';
8660 using_gprs = *args == 'F' || *args == 'f';
8662 save_in = input_line_pointer;
8663 input_line_pointer = s;
8664 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8666 s = input_line_pointer;
8667 input_line_pointer = save_in;
8668 if (err != NULL && *err != '\0')
8670 as_bad (_("Bad floating point constant: %s"), err);
8671 memset (temp, '\0', sizeof temp);
8672 length = f64 ? 8 : 4;
8675 assert (length == (unsigned) (f64 ? 8 : 4));
8679 && (! USE_GLOBAL_POINTER_OPT
8680 || mips_pic == EMBEDDED_PIC
8681 || g_switch_value < 4
8682 || (temp[0] == 0 && temp[1] == 0)
8683 || (temp[2] == 0 && temp[3] == 0))))
8685 imm_expr.X_op = O_constant;
8686 if (! target_big_endian)
8687 imm_expr.X_add_number = bfd_getl32 (temp);
8689 imm_expr.X_add_number = bfd_getb32 (temp);
8692 && ! mips_disable_float_construction
8693 /* Constants can only be constructed in GPRs and
8694 copied to FPRs if the GPRs are at least as wide
8695 as the FPRs. Force the constant into memory if
8696 we are using 64-bit FPRs but the GPRs are only
8699 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8700 && ((temp[0] == 0 && temp[1] == 0)
8701 || (temp[2] == 0 && temp[3] == 0))
8702 && ((temp[4] == 0 && temp[5] == 0)
8703 || (temp[6] == 0 && temp[7] == 0)))
8705 /* The value is simple enough to load with a couple of
8706 instructions. If using 32-bit registers, set
8707 imm_expr to the high order 32 bits and offset_expr to
8708 the low order 32 bits. Otherwise, set imm_expr to
8709 the entire 64 bit constant. */
8710 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8712 imm_expr.X_op = O_constant;
8713 offset_expr.X_op = O_constant;
8714 if (! target_big_endian)
8716 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8717 offset_expr.X_add_number = bfd_getl32 (temp);
8721 imm_expr.X_add_number = bfd_getb32 (temp);
8722 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8724 if (offset_expr.X_add_number == 0)
8725 offset_expr.X_op = O_absent;
8727 else if (sizeof (imm_expr.X_add_number) > 4)
8729 imm_expr.X_op = O_constant;
8730 if (! target_big_endian)
8731 imm_expr.X_add_number = bfd_getl64 (temp);
8733 imm_expr.X_add_number = bfd_getb64 (temp);
8737 imm_expr.X_op = O_big;
8738 imm_expr.X_add_number = 4;
8739 if (! target_big_endian)
8741 generic_bignum[0] = bfd_getl16 (temp);
8742 generic_bignum[1] = bfd_getl16 (temp + 2);
8743 generic_bignum[2] = bfd_getl16 (temp + 4);
8744 generic_bignum[3] = bfd_getl16 (temp + 6);
8748 generic_bignum[0] = bfd_getb16 (temp + 6);
8749 generic_bignum[1] = bfd_getb16 (temp + 4);
8750 generic_bignum[2] = bfd_getb16 (temp + 2);
8751 generic_bignum[3] = bfd_getb16 (temp);
8757 const char *newname;
8760 /* Switch to the right section. */
8762 subseg = now_subseg;
8765 default: /* unused default case avoids warnings. */
8767 newname = RDATA_SECTION_NAME;
8768 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8769 || mips_pic == EMBEDDED_PIC)
8773 if (mips_pic == EMBEDDED_PIC)
8776 newname = RDATA_SECTION_NAME;
8779 assert (!USE_GLOBAL_POINTER_OPT
8780 || g_switch_value >= 4);
8784 new_seg = subseg_new (newname, (subsegT) 0);
8785 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8786 bfd_set_section_flags (stdoutput, new_seg,
8791 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8792 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8793 && strcmp (TARGET_OS, "elf") != 0)
8794 record_alignment (new_seg, 4);
8796 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8798 as_bad (_("Can't use floating point insn in this section"));
8800 /* Set the argument to the current address in the
8802 offset_expr.X_op = O_symbol;
8803 offset_expr.X_add_symbol =
8804 symbol_new ("L0\001", now_seg,
8805 (valueT) frag_now_fix (), frag_now);
8806 offset_expr.X_add_number = 0;
8808 /* Put the floating point number into the section. */
8809 p = frag_more ((int) length);
8810 memcpy (p, temp, length);
8812 /* Switch back to the original section. */
8813 subseg_set (seg, subseg);
8818 case 'i': /* 16 bit unsigned immediate */
8819 case 'j': /* 16 bit signed immediate */
8820 *imm_reloc = BFD_RELOC_LO16;
8821 c = my_getSmallExpression (&imm_expr, s);
8828 *imm_reloc = BFD_RELOC_HI16_S;
8829 imm_unmatched_hi = true;
8832 else if (c == S_EX_HIGHEST)
8833 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8834 else if (c == S_EX_HIGHER)
8835 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8836 else if (c == S_EX_GP_REL)
8838 /* This occurs in NewABI only. */
8839 c = my_getSmallExpression (&imm_expr, s);
8841 as_bad (_("bad composition of relocations"));
8844 c = my_getSmallExpression (&imm_expr, s);
8846 as_bad (_("bad composition of relocations"));
8849 imm_reloc[0] = BFD_RELOC_GPREL16;
8850 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8851 imm_reloc[2] = BFD_RELOC_LO16;
8857 *imm_reloc = BFD_RELOC_HI16;
8859 else if (imm_expr.X_op == O_constant)
8860 imm_expr.X_add_number &= 0xffff;
8864 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8865 || ((imm_expr.X_add_number < 0
8866 || imm_expr.X_add_number >= 0x10000)
8867 && imm_expr.X_op == O_constant))
8869 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8870 !strcmp (insn->name, insn[1].name))
8872 if (imm_expr.X_op == O_constant
8873 || imm_expr.X_op == O_big)
8874 as_bad (_("16 bit expression not in range 0..65535"));
8882 /* The upper bound should be 0x8000, but
8883 unfortunately the MIPS assembler accepts numbers
8884 from 0x8000 to 0xffff and sign extends them, and
8885 we want to be compatible. We only permit this
8886 extended range for an instruction which does not
8887 provide any further alternates, since those
8888 alternates may handle other cases. People should
8889 use the numbers they mean, rather than relying on
8890 a mysterious sign extension. */
8891 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8892 strcmp (insn->name, insn[1].name) == 0);
8897 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8898 || ((imm_expr.X_add_number < -0x8000
8899 || imm_expr.X_add_number >= max)
8900 && imm_expr.X_op == O_constant)
8902 && imm_expr.X_add_number < 0
8904 && imm_expr.X_unsigned
8905 && sizeof (imm_expr.X_add_number) <= 4))
8909 if (imm_expr.X_op == O_constant
8910 || imm_expr.X_op == O_big)
8911 as_bad (_("16 bit expression not in range -32768..32767"));
8917 case 'o': /* 16 bit offset */
8918 c = my_getSmallExpression (&offset_expr, s);
8920 /* If this value won't fit into a 16 bit offset, then go
8921 find a macro that will generate the 32 bit offset
8924 && (offset_expr.X_op != O_constant
8925 || offset_expr.X_add_number >= 0x8000
8926 || offset_expr.X_add_number < -0x8000))
8931 if (offset_expr.X_op != O_constant)
8933 offset_expr.X_add_number =
8934 (offset_expr.X_add_number >> 16) & 0xffff;
8936 *offset_reloc = BFD_RELOC_LO16;
8940 case 'p': /* pc relative offset */
8941 if (mips_pic == EMBEDDED_PIC)
8942 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8944 *offset_reloc = BFD_RELOC_16_PCREL;
8945 my_getExpression (&offset_expr, s);
8949 case 'u': /* upper 16 bits */
8950 c = my_getSmallExpression (&imm_expr, s);
8951 *imm_reloc = BFD_RELOC_LO16;
8958 *imm_reloc = BFD_RELOC_HI16_S;
8959 imm_unmatched_hi = true;
8962 else if (c == S_EX_HIGHEST)
8963 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8964 else if (c == S_EX_GP_REL)
8966 /* This occurs in NewABI only. */
8967 c = my_getSmallExpression (&imm_expr, s);
8969 as_bad (_("bad composition of relocations"));
8972 c = my_getSmallExpression (&imm_expr, s);
8974 as_bad (_("bad composition of relocations"));
8977 imm_reloc[0] = BFD_RELOC_GPREL16;
8978 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8979 imm_reloc[2] = BFD_RELOC_HI16_S;
8985 *imm_reloc = BFD_RELOC_HI16;
8987 else if (imm_expr.X_op == O_constant)
8988 imm_expr.X_add_number &= 0xffff;
8990 else if (imm_expr.X_op == O_constant
8991 && (imm_expr.X_add_number < 0
8992 || imm_expr.X_add_number >= 0x10000))
8993 as_bad (_("lui expression not in range 0..65535"));
8997 case 'a': /* 26 bit address */
8998 my_getExpression (&offset_expr, s);
9000 *offset_reloc = BFD_RELOC_MIPS_JMP;
9003 case 'N': /* 3 bit branch condition code */
9004 case 'M': /* 3 bit compare condition code */
9005 if (strncmp (s, "$fcc", 4) != 0)
9015 while (ISDIGIT (*s));
9017 as_bad (_("invalid condition code register $fcc%d"), regno);
9019 ip->insn_opcode |= regno << OP_SH_BCC;
9021 ip->insn_opcode |= regno << OP_SH_CCC;
9025 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9036 while (ISDIGIT (*s));
9039 c = 8; /* Invalid sel value. */
9042 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9043 ip->insn_opcode |= c;
9047 /* Must be at least one digit. */
9048 my_getExpression (&imm_expr, s);
9049 check_absolute_expr (ip, &imm_expr);
9051 if ((unsigned long) imm_expr.X_add_number
9052 > (unsigned long) OP_MASK_VECBYTE)
9054 as_bad (_("bad byte vector index (%ld)"),
9055 (long) imm_expr.X_add_number);
9056 imm_expr.X_add_number = 0;
9059 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9060 imm_expr.X_op = O_absent;
9065 my_getExpression (&imm_expr, s);
9066 check_absolute_expr (ip, &imm_expr);
9068 if ((unsigned long) imm_expr.X_add_number
9069 > (unsigned long) OP_MASK_VECALIGN)
9071 as_bad (_("bad byte vector index (%ld)"),
9072 (long) imm_expr.X_add_number);
9073 imm_expr.X_add_number = 0;
9076 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9077 imm_expr.X_op = O_absent;
9082 as_bad (_("bad char = '%c'\n"), *args);
9087 /* Args don't match. */
9088 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9089 !strcmp (insn->name, insn[1].name))
9093 insn_error = _("illegal operands");
9098 insn_error = _("illegal operands");
9103 /* This routine assembles an instruction into its binary format when
9104 assembling for the mips16. As a side effect, it sets one of the
9105 global variables imm_reloc or offset_reloc to the type of
9106 relocation to do if one of the operands is an address expression.
9107 It also sets mips16_small and mips16_ext if the user explicitly
9108 requested a small or extended instruction. */
9113 struct mips_cl_insn *ip;
9117 struct mips_opcode *insn;
9120 unsigned int lastregno = 0;
9125 mips16_small = false;
9128 for (s = str; ISLOWER (*s); ++s)
9140 if (s[1] == 't' && s[2] == ' ')
9143 mips16_small = true;
9147 else if (s[1] == 'e' && s[2] == ' ')
9156 insn_error = _("unknown opcode");
9160 if (mips_opts.noautoextend && ! mips16_ext)
9161 mips16_small = true;
9163 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9165 insn_error = _("unrecognized opcode");
9172 assert (strcmp (insn->name, str) == 0);
9175 ip->insn_opcode = insn->match;
9176 ip->use_extend = false;
9177 imm_expr.X_op = O_absent;
9178 imm_reloc[0] = BFD_RELOC_UNUSED;
9179 imm_reloc[1] = BFD_RELOC_UNUSED;
9180 imm_reloc[2] = BFD_RELOC_UNUSED;
9181 offset_expr.X_op = O_absent;
9182 offset_reloc[0] = BFD_RELOC_UNUSED;
9183 offset_reloc[1] = BFD_RELOC_UNUSED;
9184 offset_reloc[2] = BFD_RELOC_UNUSED;
9185 for (args = insn->args; 1; ++args)
9192 /* In this switch statement we call break if we did not find
9193 a match, continue if we did find a match, or return if we
9202 /* Stuff the immediate value in now, if we can. */
9203 if (imm_expr.X_op == O_constant
9204 && *imm_reloc > BFD_RELOC_UNUSED
9205 && insn->pinfo != INSN_MACRO)
9207 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9208 imm_expr.X_add_number, true, mips16_small,
9209 mips16_ext, &ip->insn_opcode,
9210 &ip->use_extend, &ip->extend);
9211 imm_expr.X_op = O_absent;
9212 *imm_reloc = BFD_RELOC_UNUSED;
9226 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9229 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9245 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9247 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9274 while (ISDIGIT (*s));
9277 as_bad (_("invalid register number (%d)"), regno);
9283 if (s[1] == 'r' && s[2] == 'a')
9288 else if (s[1] == 'f' && s[2] == 'p')
9293 else if (s[1] == 's' && s[2] == 'p')
9298 else if (s[1] == 'g' && s[2] == 'p')
9303 else if (s[1] == 'a' && s[2] == 't')
9308 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9313 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9318 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9331 if (c == 'v' || c == 'w')
9333 regno = mips16_to_32_reg_map[lastregno];
9347 regno = mips32_to_16_reg_map[regno];
9352 regno = ILLEGAL_REG;
9357 regno = ILLEGAL_REG;
9362 regno = ILLEGAL_REG;
9367 if (regno == AT && ! mips_opts.noat)
9368 as_warn (_("used $at without \".set noat\""));
9375 if (regno == ILLEGAL_REG)
9382 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9386 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9389 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9392 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9398 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9401 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9402 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9412 if (strncmp (s, "$pc", 3) == 0)
9436 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9438 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9439 and generate the appropriate reloc. If the text
9440 inside %gprel is not a symbol name with an
9441 optional offset, then we generate a normal reloc
9442 and will probably fail later. */
9443 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9444 if (imm_expr.X_op == O_symbol)
9447 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9449 ip->use_extend = true;
9456 /* Just pick up a normal expression. */
9457 my_getExpression (&imm_expr, s);
9460 if (imm_expr.X_op == O_register)
9462 /* What we thought was an expression turned out to
9465 if (s[0] == '(' && args[1] == '(')
9467 /* It looks like the expression was omitted
9468 before a register indirection, which means
9469 that the expression is implicitly zero. We
9470 still set up imm_expr, so that we handle
9471 explicit extensions correctly. */
9472 imm_expr.X_op = O_constant;
9473 imm_expr.X_add_number = 0;
9474 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9481 /* We need to relax this instruction. */
9482 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9491 /* We use offset_reloc rather than imm_reloc for the PC
9492 relative operands. This lets macros with both
9493 immediate and address operands work correctly. */
9494 my_getExpression (&offset_expr, s);
9496 if (offset_expr.X_op == O_register)
9499 /* We need to relax this instruction. */
9500 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9504 case '6': /* break code */
9505 my_getExpression (&imm_expr, s);
9506 check_absolute_expr (ip, &imm_expr);
9507 if ((unsigned long) imm_expr.X_add_number > 63)
9509 as_warn (_("Invalid value for `%s' (%lu)"),
9511 (unsigned long) imm_expr.X_add_number);
9512 imm_expr.X_add_number &= 0x3f;
9514 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9515 imm_expr.X_op = O_absent;
9519 case 'a': /* 26 bit address */
9520 my_getExpression (&offset_expr, s);
9522 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9523 ip->insn_opcode <<= 16;
9526 case 'l': /* register list for entry macro */
9527 case 'L': /* register list for exit macro */
9537 int freg, reg1, reg2;
9539 while (*s == ' ' || *s == ',')
9543 as_bad (_("can't parse register list"));
9555 while (ISDIGIT (*s))
9577 as_bad (_("invalid register list"));
9582 while (ISDIGIT (*s))
9589 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9594 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9599 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9600 mask |= (reg2 - 3) << 3;
9601 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9602 mask |= (reg2 - 15) << 1;
9603 else if (reg1 == RA && reg2 == RA)
9607 as_bad (_("invalid register list"));
9611 /* The mask is filled in in the opcode table for the
9612 benefit of the disassembler. We remove it before
9613 applying the actual mask. */
9614 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9615 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9619 case 'e': /* extend code */
9620 my_getExpression (&imm_expr, s);
9621 check_absolute_expr (ip, &imm_expr);
9622 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9624 as_warn (_("Invalid value for `%s' (%lu)"),
9626 (unsigned long) imm_expr.X_add_number);
9627 imm_expr.X_add_number &= 0x7ff;
9629 ip->insn_opcode |= imm_expr.X_add_number;
9630 imm_expr.X_op = O_absent;
9640 /* Args don't match. */
9641 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9642 strcmp (insn->name, insn[1].name) == 0)
9649 insn_error = _("illegal operands");
9655 /* This structure holds information we know about a mips16 immediate
9658 struct mips16_immed_operand
9660 /* The type code used in the argument string in the opcode table. */
9662 /* The number of bits in the short form of the opcode. */
9664 /* The number of bits in the extended form of the opcode. */
9666 /* The amount by which the short form is shifted when it is used;
9667 for example, the sw instruction has a shift count of 2. */
9669 /* The amount by which the short form is shifted when it is stored
9670 into the instruction code. */
9672 /* Non-zero if the short form is unsigned. */
9674 /* Non-zero if the extended form is unsigned. */
9676 /* Non-zero if the value is PC relative. */
9680 /* The mips16 immediate operand types. */
9682 static const struct mips16_immed_operand mips16_immed_operands[] =
9684 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9685 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9686 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9687 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9688 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9689 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9690 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9691 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9692 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9693 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9694 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9695 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9696 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9697 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9698 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9699 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9700 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9701 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9702 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9703 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9704 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9707 #define MIPS16_NUM_IMMED \
9708 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9710 /* Handle a mips16 instruction with an immediate value. This or's the
9711 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9712 whether an extended value is needed; if one is needed, it sets
9713 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9714 If SMALL is true, an unextended opcode was explicitly requested.
9715 If EXT is true, an extended opcode was explicitly requested. If
9716 WARN is true, warn if EXT does not match reality. */
9719 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9728 unsigned long *insn;
9729 boolean *use_extend;
9730 unsigned short *extend;
9732 register const struct mips16_immed_operand *op;
9733 int mintiny, maxtiny;
9736 op = mips16_immed_operands;
9737 while (op->type != type)
9740 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9745 if (type == '<' || type == '>' || type == '[' || type == ']')
9748 maxtiny = 1 << op->nbits;
9753 maxtiny = (1 << op->nbits) - 1;
9758 mintiny = - (1 << (op->nbits - 1));
9759 maxtiny = (1 << (op->nbits - 1)) - 1;
9762 /* Branch offsets have an implicit 0 in the lowest bit. */
9763 if (type == 'p' || type == 'q')
9766 if ((val & ((1 << op->shift) - 1)) != 0
9767 || val < (mintiny << op->shift)
9768 || val > (maxtiny << op->shift))
9773 if (warn && ext && ! needext)
9774 as_warn_where (file, line,
9775 _("extended operand requested but not required"));
9776 if (small && needext)
9777 as_bad_where (file, line, _("invalid unextended operand value"));
9779 if (small || (! ext && ! needext))
9783 *use_extend = false;
9784 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9785 insnval <<= op->op_shift;
9790 long minext, maxext;
9796 maxext = (1 << op->extbits) - 1;
9800 minext = - (1 << (op->extbits - 1));
9801 maxext = (1 << (op->extbits - 1)) - 1;
9803 if (val < minext || val > maxext)
9804 as_bad_where (file, line,
9805 _("operand value out of range for instruction"));
9808 if (op->extbits == 16)
9810 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9813 else if (op->extbits == 15)
9815 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9820 extval = ((val & 0x1f) << 6) | (val & 0x20);
9824 *extend = (unsigned short) extval;
9829 static struct percent_op_match
9832 const enum small_ex_type type;
9837 {"%call_hi", S_EX_CALL_HI},
9838 {"%call_lo", S_EX_CALL_LO},
9839 {"%call16", S_EX_CALL16},
9840 {"%got_disp", S_EX_GOT_DISP},
9841 {"%got_page", S_EX_GOT_PAGE},
9842 {"%got_ofst", S_EX_GOT_OFST},
9843 {"%got_hi", S_EX_GOT_HI},
9844 {"%got_lo", S_EX_GOT_LO},
9846 {"%gp_rel", S_EX_GP_REL},
9847 {"%half", S_EX_HALF},
9848 {"%highest", S_EX_HIGHEST},
9849 {"%higher", S_EX_HIGHER},
9855 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9856 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9857 can be nested, this is handled by blanking the innermost, parsing the
9858 rest by subsequent calls. */
9861 my_getSmallParser (str, len, nestlevel)
9867 *str += strspn (*str, " \t");
9868 /* Check for expression in parentheses. */
9871 char *b = *str + 1 + strspn (*str + 1, " \t");
9874 /* Check for base register. */
9878 && (e = b + strcspn (b, ") \t"))
9879 && e - b > 1 && e - b < 4)
9882 && ((b[1] == 'f' && b[2] == 'p')
9883 || (b[1] == 's' && b[2] == 'p')
9884 || (b[1] == 'g' && b[2] == 'p')
9885 || (b[1] == 'a' && b[2] == 't')
9887 && ISDIGIT (b[2]))))
9888 || (ISDIGIT (b[1])))
9890 *len = strcspn (*str, ")") + 1;
9891 return S_EX_REGISTER;
9895 /* Check for percent_op (in parentheses). */
9896 else if (b[0] == '%')
9899 return my_getPercentOp (str, len, nestlevel);
9902 /* Some other expression in the parentheses, which can contain
9903 parentheses itself. Attempt to find the matching one. */
9909 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9918 /* Check for percent_op (outside of parentheses). */
9919 else if (*str[0] == '%')
9920 return my_getPercentOp (str, len, nestlevel);
9922 /* Any other expression. */
9927 my_getPercentOp (str, len, nestlevel)
9932 char *tmp = *str + 1;
9935 while (ISALPHA (*tmp) || *tmp == '_')
9937 *tmp = TOLOWER (*tmp);
9940 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9942 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9946 int type = percent_op[i].type;
9948 /* Only %hi and %lo are allowed for OldABI. */
9949 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9952 *len = strlen (percent_op[i].str);
9961 my_getSmallExpression (ep, str)
9965 static char *oldstr = NULL;
9971 /* Don't update oldstr if the last call had nested percent_op's. We need
9972 it to parse the outer ones later. */
9979 c = my_getSmallParser (&str, &len, &nestlevel);
9980 if (c != S_EX_NONE && c != S_EX_REGISTER)
9983 while (c != S_EX_NONE && c != S_EX_REGISTER);
9987 /* A percent_op was encountered. Don't try to get an expression if
9988 it is already blanked out. */
9989 if (*(str + strspn (str + 1, " )")) != ')')
9993 /* Let my_getExpression() stop at the closing parenthesis. */
9994 save = *(str + len);
9995 *(str + len) = '\0';
9996 my_getExpression (ep, str);
9997 *(str + len) = save;
10001 /* Blank out including the % sign and the proper matching
10004 char *s = strrchr (oldstr, '%');
10007 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
10011 else if (*end == ')')
10015 memset (s, ' ', end - s);
10019 expr_end = str + len;
10023 else if (c == S_EX_NONE)
10025 my_getExpression (ep, str);
10027 else if (c == S_EX_REGISTER)
10029 ep->X_op = O_constant;
10031 ep->X_add_symbol = NULL;
10032 ep->X_op_symbol = NULL;
10033 ep->X_add_number = 0;
10037 as_fatal (_("internal error"));
10040 if (nestlevel <= 0)
10041 /* All percent_op's have been handled. */
10048 my_getExpression (ep, str)
10055 save_in = input_line_pointer;
10056 input_line_pointer = str;
10058 expr_end = input_line_pointer;
10059 input_line_pointer = save_in;
10061 /* If we are in mips16 mode, and this is an expression based on `.',
10062 then we bump the value of the symbol by 1 since that is how other
10063 text symbols are handled. We don't bother to handle complex
10064 expressions, just `.' plus or minus a constant. */
10065 if (mips_opts.mips16
10066 && ep->X_op == O_symbol
10067 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10068 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10069 && symbol_get_frag (ep->X_add_symbol) == frag_now
10070 && symbol_constant_p (ep->X_add_symbol)
10071 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10072 S_SET_VALUE (ep->X_add_symbol, val + 1);
10075 /* Turn a string in input_line_pointer into a floating point constant
10076 of type TYPE, and store the appropriate bytes in *LITP. The number
10077 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10078 returned, or NULL on OK. */
10081 md_atof (type, litP, sizeP)
10087 LITTLENUM_TYPE words[4];
10103 return _("bad call to md_atof");
10106 t = atof_ieee (input_line_pointer, type, words);
10108 input_line_pointer = t;
10112 if (! target_big_endian)
10114 for (i = prec - 1; i >= 0; i--)
10116 md_number_to_chars (litP, (valueT) words[i], 2);
10122 for (i = 0; i < prec; i++)
10124 md_number_to_chars (litP, (valueT) words[i], 2);
10133 md_number_to_chars (buf, val, n)
10138 if (target_big_endian)
10139 number_to_chars_bigendian (buf, val, n);
10141 number_to_chars_littleendian (buf, val, n);
10145 static int support_64bit_objects(void)
10147 const char **list, **l;
10149 list = bfd_target_list ();
10150 for (l = list; *l != NULL; l++)
10152 /* This is traditional mips */
10153 if (strcmp (*l, "elf64-tradbigmips") == 0
10154 || strcmp (*l, "elf64-tradlittlemips") == 0)
10156 if (strcmp (*l, "elf64-bigmips") == 0
10157 || strcmp (*l, "elf64-littlemips") == 0)
10161 return (*l != NULL);
10163 #endif /* OBJ_ELF */
10165 const char *md_shortopts = "nO::g::G:";
10167 struct option md_longopts[] =
10169 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10170 {"mips0", no_argument, NULL, OPTION_MIPS1},
10171 {"mips1", no_argument, NULL, OPTION_MIPS1},
10172 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10173 {"mips2", no_argument, NULL, OPTION_MIPS2},
10174 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10175 {"mips3", no_argument, NULL, OPTION_MIPS3},
10176 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10177 {"mips4", no_argument, NULL, OPTION_MIPS4},
10178 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10179 {"mips5", no_argument, NULL, OPTION_MIPS5},
10180 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10181 {"mips32", no_argument, NULL, OPTION_MIPS32},
10182 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10183 {"mips64", no_argument, NULL, OPTION_MIPS64},
10184 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10185 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10186 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10187 {"trap", no_argument, NULL, OPTION_TRAP},
10188 {"no-break", no_argument, NULL, OPTION_TRAP},
10189 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10190 {"break", no_argument, NULL, OPTION_BREAK},
10191 {"no-trap", no_argument, NULL, OPTION_BREAK},
10192 #define OPTION_EB (OPTION_MD_BASE + 11)
10193 {"EB", no_argument, NULL, OPTION_EB},
10194 #define OPTION_EL (OPTION_MD_BASE + 12)
10195 {"EL", no_argument, NULL, OPTION_EL},
10196 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10197 {"mips16", no_argument, NULL, OPTION_MIPS16},
10198 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10199 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10200 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10201 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10202 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10203 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10204 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10205 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10206 {"mfp32", no_argument, NULL, OPTION_FP32},
10207 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10208 {"mgp32", no_argument, NULL, OPTION_GP32},
10209 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10210 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10211 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10212 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10213 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10214 {"march", required_argument, NULL, OPTION_MARCH},
10215 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10216 {"mtune", required_argument, NULL, OPTION_MTUNE},
10217 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10218 {"mfp64", no_argument, NULL, OPTION_FP64},
10219 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10220 {"m4650", no_argument, NULL, OPTION_M4650},
10221 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10222 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10223 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10224 {"m4010", no_argument, NULL, OPTION_M4010},
10225 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10226 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10227 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10228 {"m4100", no_argument, NULL, OPTION_M4100},
10229 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10230 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10231 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10232 {"m3900", no_argument, NULL, OPTION_M3900},
10233 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10234 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10235 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10236 {"mgp64", no_argument, NULL, OPTION_GP64},
10237 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10238 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10239 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10240 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10241 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10242 {"mdmx", no_argument, NULL, OPTION_MDMX},
10243 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10244 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10245 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10246 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10247 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10248 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10249 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10250 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10251 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10252 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10254 #define OPTION_ELF_BASE (OPTION_MD_BASE + 41)
10255 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10256 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10257 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10258 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10259 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10260 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10261 {"xgot", no_argument, NULL, OPTION_XGOT},
10262 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10263 {"mabi", required_argument, NULL, OPTION_MABI},
10264 #define OPTION_32 (OPTION_ELF_BASE + 4)
10265 {"32", no_argument, NULL, OPTION_32},
10266 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10267 {"n32", no_argument, NULL, OPTION_N32},
10268 #define OPTION_64 (OPTION_ELF_BASE + 6)
10269 {"64", no_argument, NULL, OPTION_64},
10270 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10271 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10272 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10273 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10274 #endif /* OBJ_ELF */
10275 {NULL, no_argument, NULL, 0}
10277 size_t md_longopts_size = sizeof (md_longopts);
10279 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10280 NEW_VALUE. Warn if another value was already specified. Note:
10281 we have to defer parsing the -march and -mtune arguments in order
10282 to handle 'from-abi' correctly, since the ABI might be specified
10283 in a later argument. */
10286 mips_set_option_string (string_ptr, new_value)
10287 const char **string_ptr, *new_value;
10289 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10290 as_warn (_("A different %s was already specified, is now %s"),
10291 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10294 *string_ptr = new_value;
10298 md_parse_option (c, arg)
10304 case OPTION_CONSTRUCT_FLOATS:
10305 mips_disable_float_construction = 0;
10308 case OPTION_NO_CONSTRUCT_FLOATS:
10309 mips_disable_float_construction = 1;
10321 target_big_endian = 1;
10325 target_big_endian = 0;
10333 if (arg && arg[1] == '0')
10343 mips_debug = atoi (arg);
10344 /* When the MIPS assembler sees -g or -g2, it does not do
10345 optimizations which limit full symbolic debugging. We take
10346 that to be equivalent to -O0. */
10347 if (mips_debug == 2)
10352 file_mips_isa = ISA_MIPS1;
10356 file_mips_isa = ISA_MIPS2;
10360 file_mips_isa = ISA_MIPS3;
10364 file_mips_isa = ISA_MIPS4;
10368 file_mips_isa = ISA_MIPS5;
10371 case OPTION_MIPS32:
10372 file_mips_isa = ISA_MIPS32;
10375 case OPTION_MIPS64:
10376 file_mips_isa = ISA_MIPS64;
10380 mips_set_option_string (&mips_tune_string, arg);
10384 mips_set_option_string (&mips_arch_string, arg);
10388 mips_set_option_string (&mips_arch_string, "4650");
10389 mips_set_option_string (&mips_tune_string, "4650");
10392 case OPTION_NO_M4650:
10396 mips_set_option_string (&mips_arch_string, "4010");
10397 mips_set_option_string (&mips_tune_string, "4010");
10400 case OPTION_NO_M4010:
10404 mips_set_option_string (&mips_arch_string, "4100");
10405 mips_set_option_string (&mips_tune_string, "4100");
10408 case OPTION_NO_M4100:
10412 mips_set_option_string (&mips_arch_string, "3900");
10413 mips_set_option_string (&mips_tune_string, "3900");
10416 case OPTION_NO_M3900:
10420 mips_opts.ase_mdmx = 1;
10423 case OPTION_NO_MDMX:
10424 mips_opts.ase_mdmx = 0;
10427 case OPTION_MIPS16:
10428 mips_opts.mips16 = 1;
10429 mips_no_prev_insn (false);
10432 case OPTION_NO_MIPS16:
10433 mips_opts.mips16 = 0;
10434 mips_no_prev_insn (false);
10437 case OPTION_MIPS3D:
10438 mips_opts.ase_mips3d = 1;
10441 case OPTION_NO_MIPS3D:
10442 mips_opts.ase_mips3d = 0;
10445 case OPTION_MEMBEDDED_PIC:
10446 mips_pic = EMBEDDED_PIC;
10447 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10449 as_bad (_("-G may not be used with embedded PIC code"));
10452 g_switch_value = 0x7fffffff;
10455 case OPTION_FIX_VR4122:
10456 mips_fix_4122_bugs = 1;
10459 case OPTION_NO_FIX_VR4122:
10460 mips_fix_4122_bugs = 0;
10463 case OPTION_RELAX_BRANCH:
10464 mips_relax_branch = 1;
10467 case OPTION_NO_RELAX_BRANCH:
10468 mips_relax_branch = 0;
10472 /* When generating ELF code, we permit -KPIC and -call_shared to
10473 select SVR4_PIC, and -non_shared to select no PIC. This is
10474 intended to be compatible with Irix 5. */
10475 case OPTION_CALL_SHARED:
10476 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10478 as_bad (_("-call_shared is supported only for ELF format"));
10481 mips_pic = SVR4_PIC;
10482 if (g_switch_seen && g_switch_value != 0)
10484 as_bad (_("-G may not be used with SVR4 PIC code"));
10487 g_switch_value = 0;
10490 case OPTION_NON_SHARED:
10491 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10493 as_bad (_("-non_shared is supported only for ELF format"));
10499 /* The -xgot option tells the assembler to use 32 offsets when
10500 accessing the got in SVR4_PIC mode. It is for Irix
10505 #endif /* OBJ_ELF */
10508 if (! USE_GLOBAL_POINTER_OPT)
10510 as_bad (_("-G is not supported for this configuration"));
10513 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10515 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10519 g_switch_value = atoi (arg);
10524 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10527 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10529 as_bad (_("-32 is supported for ELF format only"));
10532 mips_abi = O32_ABI;
10536 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10538 as_bad (_("-n32 is supported for ELF format only"));
10541 mips_abi = N32_ABI;
10545 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10547 as_bad (_("-64 is supported for ELF format only"));
10550 mips_abi = N64_ABI;
10551 if (! support_64bit_objects())
10552 as_fatal (_("No compiled in support for 64 bit object file format"));
10554 #endif /* OBJ_ELF */
10557 file_mips_gp32 = 1;
10561 file_mips_gp32 = 0;
10565 file_mips_fp32 = 1;
10569 file_mips_fp32 = 0;
10574 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10576 as_bad (_("-mabi is supported for ELF format only"));
10579 if (strcmp (arg, "32") == 0)
10580 mips_abi = O32_ABI;
10581 else if (strcmp (arg, "o64") == 0)
10582 mips_abi = O64_ABI;
10583 else if (strcmp (arg, "n32") == 0)
10584 mips_abi = N32_ABI;
10585 else if (strcmp (arg, "64") == 0)
10587 mips_abi = N64_ABI;
10588 if (! support_64bit_objects())
10589 as_fatal (_("No compiled in support for 64 bit object file "
10592 else if (strcmp (arg, "eabi") == 0)
10593 mips_abi = EABI_ABI;
10596 as_fatal (_("invalid abi -mabi=%s"), arg);
10600 #endif /* OBJ_ELF */
10602 case OPTION_M7000_HILO_FIX:
10603 mips_7000_hilo_fix = true;
10606 case OPTION_MNO_7000_HILO_FIX:
10607 mips_7000_hilo_fix = false;
10611 case OPTION_MDEBUG:
10612 mips_flag_mdebug = true;
10615 case OPTION_NO_MDEBUG:
10616 mips_flag_mdebug = false;
10618 #endif /* OBJ_ELF */
10627 /* Set up globals to generate code for the ISA or processor
10628 described by INFO. */
10631 mips_set_architecture (info)
10632 const struct mips_cpu_info *info;
10636 mips_arch_info = info;
10637 mips_arch = info->cpu;
10638 mips_opts.isa = info->isa;
10643 /* Likewise for tuning. */
10646 mips_set_tune (info)
10647 const struct mips_cpu_info *info;
10651 mips_tune_info = info;
10652 mips_tune = info->cpu;
10658 mips_after_parse_args ()
10660 /* GP relative stuff not working for PE */
10661 if (strncmp (TARGET_OS, "pe", 2) == 0
10662 && g_switch_value != 0)
10665 as_bad (_("-G not supported in this configuration."));
10666 g_switch_value = 0;
10669 /* The following code determines the architecture and register size.
10670 Similar code was added to GCC 3.3 (see override_options() in
10671 config/mips/mips.c). The GAS and GCC code should be kept in sync
10672 as much as possible. */
10674 if (mips_arch_string != 0)
10675 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
10677 if (mips_tune_string != 0)
10678 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
10680 if (file_mips_isa != ISA_UNKNOWN)
10682 /* Handle -mipsN. At this point, file_mips_isa contains the
10683 ISA level specified by -mipsN, while mips_opts.isa contains
10684 the -march selection (if any). */
10685 if (mips_arch_info != 0)
10687 /* -march takes precedence over -mipsN, since it is more descriptive.
10688 There's no harm in specifying both as long as the ISA levels
10690 if (file_mips_isa != mips_opts.isa)
10691 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10692 mips_cpu_info_from_isa (file_mips_isa)->name,
10693 mips_cpu_info_from_isa (mips_opts.isa)->name);
10696 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa));
10699 if (mips_arch_info == 0)
10700 mips_set_architecture (mips_parse_cpu ("default CPU",
10701 MIPS_CPU_STRING_DEFAULT));
10703 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10704 as_bad ("-march=%s is not compatible with the selected ABI",
10705 mips_arch_info->name);
10707 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10708 if (mips_tune_info == 0)
10709 mips_set_tune (mips_arch_info);
10711 if (file_mips_gp32 >= 0)
10713 /* The user specified the size of the integer registers. Make sure
10714 it agrees with the ABI and ISA. */
10715 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10716 as_bad (_("-mgp64 used with a 32-bit processor"));
10717 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10718 as_bad (_("-mgp32 used with a 64-bit ABI"));
10719 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10720 as_bad (_("-mgp64 used with a 32-bit ABI"));
10724 /* Infer the integer register size from the ABI and processor.
10725 Restrict ourselves to 32-bit registers if that's all the
10726 processor has, or if the ABI cannot handle 64-bit registers. */
10727 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10728 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10731 /* ??? GAS treats single-float processors as though they had 64-bit
10732 float registers (although it complains when double-precision
10733 instructions are used). As things stand, saying they have 32-bit
10734 registers would lead to spurious "register must be even" messages.
10735 So here we assume float registers are always the same size as
10736 integer ones, unless the user says otherwise. */
10737 if (file_mips_fp32 < 0)
10738 file_mips_fp32 = file_mips_gp32;
10740 /* End of GCC-shared inference code. */
10742 /* ??? When do we want this flag to be set? Who uses it? */
10743 if (file_mips_gp32 == 1
10744 && mips_abi == NO_ABI
10745 && ISA_HAS_64BIT_REGS (mips_opts.isa))
10746 mips_32bitmode = 1;
10748 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10749 as_bad (_("trap exception not supported at ISA 1"));
10751 /* If the selected architecture includes support for ASEs, enable
10752 generation of code for them. */
10753 if (mips_opts.mips16 == -1)
10754 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10755 if (mips_opts.ase_mips3d == -1)
10756 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10757 if (mips_opts.ase_mdmx == -1)
10758 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10760 file_mips_isa = mips_opts.isa;
10761 file_ase_mips16 = mips_opts.mips16;
10762 file_ase_mips3d = mips_opts.ase_mips3d;
10763 file_ase_mdmx = mips_opts.ase_mdmx;
10764 mips_opts.gp32 = file_mips_gp32;
10765 mips_opts.fp32 = file_mips_fp32;
10767 if (mips_flag_mdebug < 0)
10769 #ifdef OBJ_MAYBE_ECOFF
10770 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10771 mips_flag_mdebug = 1;
10773 #endif /* OBJ_MAYBE_ECOFF */
10774 mips_flag_mdebug = 0;
10779 mips_init_after_args ()
10781 /* initialize opcodes */
10782 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10783 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10787 md_pcrel_from (fixP)
10790 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10791 && fixP->fx_addsy != (symbolS *) NULL
10792 && ! S_IS_DEFINED (fixP->fx_addsy))
10794 /* This makes a branch to an undefined symbol be a branch to the
10795 current location. */
10796 if (mips_pic == EMBEDDED_PIC)
10802 /* Return the address of the delay slot. */
10803 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10806 /* This is called before the symbol table is processed. In order to
10807 work with gcc when using mips-tfile, we must keep all local labels.
10808 However, in other cases, we want to discard them. If we were
10809 called with -g, but we didn't see any debugging information, it may
10810 mean that gcc is smuggling debugging information through to
10811 mips-tfile, in which case we must generate all local labels. */
10814 mips_frob_file_before_adjust ()
10816 #ifndef NO_ECOFF_DEBUGGING
10817 if (ECOFF_DEBUGGING
10819 && ! ecoff_debugging_seen)
10820 flag_keep_locals = 1;
10824 /* Sort any unmatched HI16_S relocs so that they immediately precede
10825 the corresponding LO reloc. This is called before md_apply_fix3 and
10826 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10827 explicit use of the %hi modifier. */
10832 struct mips_hi_fixup *l;
10834 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10836 segment_info_type *seginfo;
10839 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10841 /* Check quickly whether the next fixup happens to be a matching
10843 if (l->fixp->fx_next != NULL
10844 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10845 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10846 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10849 /* Look through the fixups for this segment for a matching %lo.
10850 When we find one, move the %hi just in front of it. We do
10851 this in two passes. In the first pass, we try to find a
10852 unique %lo. In the second pass, we permit multiple %hi
10853 relocs for a single %lo (this is a GNU extension). */
10854 seginfo = seg_info (l->seg);
10855 for (pass = 0; pass < 2; pass++)
10860 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10862 /* Check whether this is a %lo fixup which matches l->fixp. */
10863 if (f->fx_r_type == BFD_RELOC_LO16
10864 && f->fx_addsy == l->fixp->fx_addsy
10865 && f->fx_offset == l->fixp->fx_offset
10868 || prev->fx_r_type != BFD_RELOC_HI16_S
10869 || prev->fx_addsy != f->fx_addsy
10870 || prev->fx_offset != f->fx_offset))
10874 /* Move l->fixp before f. */
10875 for (pf = &seginfo->fix_root;
10877 pf = &(*pf)->fx_next)
10878 assert (*pf != NULL);
10880 *pf = l->fixp->fx_next;
10882 l->fixp->fx_next = f;
10884 seginfo->fix_root = l->fixp;
10886 prev->fx_next = l->fixp;
10897 #if 0 /* GCC code motion plus incomplete dead code elimination
10898 can leave a %hi without a %lo. */
10900 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10901 _("Unmatched %%hi reloc"));
10907 /* When generating embedded PIC code we need to use a special
10908 relocation to represent the difference of two symbols in the .text
10909 section (switch tables use a difference of this sort). See
10910 include/coff/mips.h for details. This macro checks whether this
10911 fixup requires the special reloc. */
10912 #define SWITCH_TABLE(fixp) \
10913 ((fixp)->fx_r_type == BFD_RELOC_32 \
10914 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10915 && (fixp)->fx_addsy != NULL \
10916 && (fixp)->fx_subsy != NULL \
10917 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10918 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10920 /* When generating embedded PIC code we must keep all PC relative
10921 relocations, in case the linker has to relax a call. We also need
10922 to keep relocations for switch table entries.
10924 We may have combined relocations without symbols in the N32/N64 ABI.
10925 We have to prevent gas from dropping them. */
10928 mips_force_relocation (fixp)
10931 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10932 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10933 || S_FORCE_RELOC (fixp->fx_addsy))
10937 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10938 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10939 || fixp->fx_r_type == BFD_RELOC_HI16_S
10940 || fixp->fx_r_type == BFD_RELOC_LO16))
10943 return (mips_pic == EMBEDDED_PIC
10945 || SWITCH_TABLE (fixp)
10946 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10947 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10952 mips_need_elf_addend_fixup (fixP)
10955 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10957 if (mips_pic == EMBEDDED_PIC
10958 && S_IS_WEAK (fixP->fx_addsy))
10960 if (mips_pic != EMBEDDED_PIC
10961 && (S_IS_WEAK (fixP->fx_addsy)
10962 || S_IS_EXTERNAL (fixP->fx_addsy))
10963 && !S_IS_COMMON (fixP->fx_addsy))
10965 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10966 && (((bfd_get_section_flags (stdoutput,
10967 S_GET_SEGMENT (fixP->fx_addsy))
10968 & SEC_LINK_ONCE) != 0)
10969 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10971 sizeof (".gnu.linkonce") - 1)))
10977 /* Apply a fixup to the object file. */
10980 md_apply_fix3 (fixP, valP, seg)
10983 segT seg ATTRIBUTE_UNUSED;
10988 static int previous_fx_r_type = 0;
10990 /* FIXME: Maybe just return for all reloc types not listed below?
10991 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
10992 if (fixP->fx_r_type == BFD_RELOC_8)
10995 assert (fixP->fx_size == 4
10996 || fixP->fx_r_type == BFD_RELOC_16
10997 || fixP->fx_r_type == BFD_RELOC_32
10998 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10999 || fixP->fx_r_type == BFD_RELOC_HI16_S
11000 || fixP->fx_r_type == BFD_RELOC_LO16
11001 || fixP->fx_r_type == BFD_RELOC_GPREL16
11002 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
11003 || fixP->fx_r_type == BFD_RELOC_GPREL32
11004 || fixP->fx_r_type == BFD_RELOC_64
11005 || fixP->fx_r_type == BFD_RELOC_CTOR
11006 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11007 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
11008 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
11009 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
11010 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
11011 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
11012 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11013 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
11014 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
11018 /* If we aren't adjusting this fixup to be against the section
11019 symbol, we need to adjust the value. */
11021 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
11023 if (mips_need_elf_addend_fixup (fixP))
11025 reloc_howto_type *howto;
11026 valueT symval = S_GET_VALUE (fixP->fx_addsy);
11030 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11031 if (value != 0 && howto->partial_inplace
11032 && (! fixP->fx_pcrel || howto->pcrel_offset))
11034 /* In this case, the bfd_install_relocation routine will
11035 incorrectly add the symbol value back in. We just want
11036 the addend to appear in the object file.
11038 howto->pcrel_offset is added for R_MIPS_PC16, which is
11039 generated for code like
11050 /* Make sure the addend is still non-zero. If it became zero
11051 after the last operation, set it to a spurious value and
11052 subtract the same value from the object file's contents. */
11057 /* The in-place addends for LO16 relocations are signed;
11058 leave the matching HI16 in-place addends as zero. */
11059 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
11061 bfd_vma contents, mask, field;
11063 contents = bfd_get_bits (fixP->fx_frag->fr_literal
11066 target_big_endian);
11068 /* MASK has bits set where the relocation should go.
11069 FIELD is -value, shifted into the appropriate place
11070 for this relocation. */
11071 mask = 1 << (howto->bitsize - 1);
11072 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
11073 field = (-value >> howto->rightshift) << howto->bitpos;
11075 bfd_put_bits ((field & mask) | (contents & ~mask),
11076 fixP->fx_frag->fr_literal + fixP->fx_where,
11078 target_big_endian);
11084 /* This code was generated using trial and error and so is
11085 fragile and not trustworthy. If you change it, you should
11086 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11087 they still pass. */
11088 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
11090 value += fixP->fx_frag->fr_address + fixP->fx_where;
11092 /* BFD's REL handling, for MIPS, is _very_ weird.
11093 This gives the right results, but it can't possibly
11094 be the way things are supposed to work. */
11095 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
11096 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
11097 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
11098 value += fixP->fx_frag->fr_address + fixP->fx_where;
11103 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
11105 /* We are not done if this is a composite relocation to set up gp. */
11106 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11107 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11108 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11109 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11110 || fixP->fx_r_type == BFD_RELOC_LO16))))
11112 previous_fx_r_type = fixP->fx_r_type;
11114 switch (fixP->fx_r_type)
11116 case BFD_RELOC_MIPS_JMP:
11117 case BFD_RELOC_MIPS_SHIFT5:
11118 case BFD_RELOC_MIPS_SHIFT6:
11119 case BFD_RELOC_MIPS_GOT_DISP:
11120 case BFD_RELOC_MIPS_GOT_PAGE:
11121 case BFD_RELOC_MIPS_GOT_OFST:
11122 case BFD_RELOC_MIPS_SUB:
11123 case BFD_RELOC_MIPS_INSERT_A:
11124 case BFD_RELOC_MIPS_INSERT_B:
11125 case BFD_RELOC_MIPS_DELETE:
11126 case BFD_RELOC_MIPS_HIGHEST:
11127 case BFD_RELOC_MIPS_HIGHER:
11128 case BFD_RELOC_MIPS_SCN_DISP:
11129 case BFD_RELOC_MIPS_REL16:
11130 case BFD_RELOC_MIPS_RELGOT:
11131 case BFD_RELOC_MIPS_JALR:
11132 case BFD_RELOC_HI16:
11133 case BFD_RELOC_HI16_S:
11134 case BFD_RELOC_GPREL16:
11135 case BFD_RELOC_MIPS_LITERAL:
11136 case BFD_RELOC_MIPS_CALL16:
11137 case BFD_RELOC_MIPS_GOT16:
11138 case BFD_RELOC_GPREL32:
11139 case BFD_RELOC_MIPS_GOT_HI16:
11140 case BFD_RELOC_MIPS_GOT_LO16:
11141 case BFD_RELOC_MIPS_CALL_HI16:
11142 case BFD_RELOC_MIPS_CALL_LO16:
11143 case BFD_RELOC_MIPS16_GPREL:
11144 if (fixP->fx_pcrel)
11145 as_bad_where (fixP->fx_file, fixP->fx_line,
11146 _("Invalid PC relative reloc"));
11147 /* Nothing needed to do. The value comes from the reloc entry */
11150 case BFD_RELOC_MIPS16_JMP:
11151 /* We currently always generate a reloc against a symbol, which
11152 means that we don't want an addend even if the symbol is
11154 fixP->fx_addnumber = 0;
11157 case BFD_RELOC_PCREL_HI16_S:
11158 /* The addend for this is tricky if it is internal, so we just
11159 do everything here rather than in bfd_install_relocation. */
11160 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11165 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11167 /* For an external symbol adjust by the address to make it
11168 pcrel_offset. We use the address of the RELLO reloc
11169 which follows this one. */
11170 value += (fixP->fx_next->fx_frag->fr_address
11171 + fixP->fx_next->fx_where);
11173 value = ((value + 0x8000) >> 16) & 0xffff;
11174 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11175 if (target_big_endian)
11177 md_number_to_chars ((char *) buf, value, 2);
11180 case BFD_RELOC_PCREL_LO16:
11181 /* The addend for this is tricky if it is internal, so we just
11182 do everything here rather than in bfd_install_relocation. */
11183 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11188 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11189 value += fixP->fx_frag->fr_address + fixP->fx_where;
11190 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11191 if (target_big_endian)
11193 md_number_to_chars ((char *) buf, value, 2);
11197 /* This is handled like BFD_RELOC_32, but we output a sign
11198 extended value if we are only 32 bits. */
11200 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11202 if (8 <= sizeof (valueT))
11203 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11210 w1 = w2 = fixP->fx_where;
11211 if (target_big_endian)
11215 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
11216 if ((value & 0x80000000) != 0)
11220 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
11225 case BFD_RELOC_RVA:
11227 /* If we are deleting this reloc entry, we must fill in the
11228 value now. This can happen if we have a .word which is not
11229 resolved when it appears but is later defined. We also need
11230 to fill in the value if this is an embedded PIC switch table
11233 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11234 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11239 /* If we are deleting this reloc entry, we must fill in the
11241 assert (fixP->fx_size == 2);
11243 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11247 case BFD_RELOC_LO16:
11248 /* When handling an embedded PIC switch statement, we can wind
11249 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11252 if (value + 0x8000 > 0xffff)
11253 as_bad_where (fixP->fx_file, fixP->fx_line,
11254 _("relocation overflow"));
11255 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11256 if (target_big_endian)
11258 md_number_to_chars ((char *) buf, value, 2);
11262 case BFD_RELOC_16_PCREL_S2:
11263 if ((value & 0x3) != 0)
11264 as_bad_where (fixP->fx_file, fixP->fx_line,
11265 _("Branch to odd address (%lx)"), (long) value);
11267 /* Fall through. */
11269 case BFD_RELOC_16_PCREL:
11271 * We need to save the bits in the instruction since fixup_segment()
11272 * might be deleting the relocation entry (i.e., a branch within
11273 * the current segment).
11275 if (!fixP->fx_done && value != 0)
11277 /* If 'value' is zero, the remaining reloc code won't actually
11278 do the store, so it must be done here. This is probably
11279 a bug somewhere. */
11281 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
11282 || fixP->fx_addsy == NULL /* ??? */
11283 || ! S_IS_DEFINED (fixP->fx_addsy)))
11284 value -= fixP->fx_frag->fr_address + fixP->fx_where;
11286 value = (offsetT) value >> 2;
11288 /* update old instruction data */
11289 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
11290 if (target_big_endian)
11291 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11293 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11295 if (value + 0x8000 <= 0xffff)
11296 insn |= value & 0xffff;
11299 /* The branch offset is too large. If this is an
11300 unconditional branch, and we are not generating PIC code,
11301 we can convert it to an absolute jump instruction. */
11302 if (mips_pic == NO_PIC
11304 && fixP->fx_frag->fr_address >= text_section->vma
11305 && (fixP->fx_frag->fr_address
11306 < text_section->vma + text_section->_raw_size)
11307 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11308 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11309 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11311 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11312 insn = 0x0c000000; /* jal */
11314 insn = 0x08000000; /* j */
11315 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11317 fixP->fx_addsy = section_symbol (text_section);
11318 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
11322 /* If we got here, we have branch-relaxation disabled,
11323 and there's nothing we can do to fix this instruction
11324 without turning it into a longer sequence. */
11325 as_bad_where (fixP->fx_file, fixP->fx_line,
11326 _("Branch out of range"));
11330 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11333 case BFD_RELOC_VTABLE_INHERIT:
11336 && !S_IS_DEFINED (fixP->fx_addsy)
11337 && !S_IS_WEAK (fixP->fx_addsy))
11338 S_SET_WEAK (fixP->fx_addsy);
11341 case BFD_RELOC_VTABLE_ENTRY:
11355 const struct mips_opcode *p;
11356 int treg, sreg, dreg, shamt;
11361 for (i = 0; i < NUMOPCODES; ++i)
11363 p = &mips_opcodes[i];
11364 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11366 printf ("%08lx %s\t", oc, p->name);
11367 treg = (oc >> 16) & 0x1f;
11368 sreg = (oc >> 21) & 0x1f;
11369 dreg = (oc >> 11) & 0x1f;
11370 shamt = (oc >> 6) & 0x1f;
11372 for (args = p->args;; ++args)
11383 printf ("%c", *args);
11387 assert (treg == sreg);
11388 printf ("$%d,$%d", treg, sreg);
11393 printf ("$%d", dreg);
11398 printf ("$%d", treg);
11402 printf ("0x%x", treg);
11407 printf ("$%d", sreg);
11411 printf ("0x%08lx", oc & 0x1ffffff);
11418 printf ("%d", imm);
11423 printf ("$%d", shamt);
11434 printf (_("%08lx UNDEFINED\n"), oc);
11445 name = input_line_pointer;
11446 c = get_symbol_end ();
11447 p = (symbolS *) symbol_find_or_make (name);
11448 *input_line_pointer = c;
11452 /* Align the current frag to a given power of two. The MIPS assembler
11453 also automatically adjusts any preceding label. */
11456 mips_align (to, fill, label)
11461 mips_emit_delays (false);
11462 frag_align (to, fill, 0);
11463 record_alignment (now_seg, to);
11466 assert (S_GET_SEGMENT (label) == now_seg);
11467 symbol_set_frag (label, frag_now);
11468 S_SET_VALUE (label, (valueT) frag_now_fix ());
11472 /* Align to a given power of two. .align 0 turns off the automatic
11473 alignment used by the data creating pseudo-ops. */
11477 int x ATTRIBUTE_UNUSED;
11480 register long temp_fill;
11481 long max_alignment = 15;
11485 o Note that the assembler pulls down any immediately preceeding label
11486 to the aligned address.
11487 o It's not documented but auto alignment is reinstated by
11488 a .align pseudo instruction.
11489 o Note also that after auto alignment is turned off the mips assembler
11490 issues an error on attempt to assemble an improperly aligned data item.
11495 temp = get_absolute_expression ();
11496 if (temp > max_alignment)
11497 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11500 as_warn (_("Alignment negative: 0 assumed."));
11503 if (*input_line_pointer == ',')
11505 ++input_line_pointer;
11506 temp_fill = get_absolute_expression ();
11513 mips_align (temp, (int) temp_fill,
11514 insn_labels != NULL ? insn_labels->label : NULL);
11521 demand_empty_rest_of_line ();
11525 mips_flush_pending_output ()
11527 mips_emit_delays (false);
11528 mips_clear_insn_labels ();
11537 /* When generating embedded PIC code, we only use the .text, .lit8,
11538 .sdata and .sbss sections. We change the .data and .rdata
11539 pseudo-ops to use .sdata. */
11540 if (mips_pic == EMBEDDED_PIC
11541 && (sec == 'd' || sec == 'r'))
11545 /* The ELF backend needs to know that we are changing sections, so
11546 that .previous works correctly. We could do something like check
11547 for an obj_section_change_hook macro, but that might be confusing
11548 as it would not be appropriate to use it in the section changing
11549 functions in read.c, since obj-elf.c intercepts those. FIXME:
11550 This should be cleaner, somehow. */
11551 obj_elf_section_change_hook ();
11554 mips_emit_delays (false);
11564 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11565 demand_empty_rest_of_line ();
11569 if (USE_GLOBAL_POINTER_OPT)
11571 seg = subseg_new (RDATA_SECTION_NAME,
11572 (subsegT) get_absolute_expression ());
11573 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11575 bfd_set_section_flags (stdoutput, seg,
11581 if (strcmp (TARGET_OS, "elf") != 0)
11582 record_alignment (seg, 4);
11584 demand_empty_rest_of_line ();
11588 as_bad (_("No read only data section in this object file format"));
11589 demand_empty_rest_of_line ();
11595 if (USE_GLOBAL_POINTER_OPT)
11597 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11598 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11600 bfd_set_section_flags (stdoutput, seg,
11601 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11603 if (strcmp (TARGET_OS, "elf") != 0)
11604 record_alignment (seg, 4);
11606 demand_empty_rest_of_line ();
11611 as_bad (_("Global pointers not supported; recompile -G 0"));
11612 demand_empty_rest_of_line ();
11621 s_change_section (ignore)
11622 int ignore ATTRIBUTE_UNUSED;
11625 char *section_name;
11630 int section_entry_size;
11631 int section_alignment;
11633 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11636 section_name = input_line_pointer;
11637 c = get_symbol_end ();
11638 next_c = *(input_line_pointer + 1);
11640 /* Do we have .section Name<,"flags">? */
11641 if (c != ',' || (c == ',' && next_c == '"'))
11643 /* just after name is now '\0'. */
11644 *input_line_pointer = c;
11645 input_line_pointer = section_name;
11646 obj_elf_section (ignore);
11649 input_line_pointer++;
11651 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11653 section_type = get_absolute_expression ();
11656 if (*input_line_pointer++ == ',')
11657 section_flag = get_absolute_expression ();
11660 if (*input_line_pointer++ == ',')
11661 section_entry_size = get_absolute_expression ();
11663 section_entry_size = 0;
11664 if (*input_line_pointer++ == ',')
11665 section_alignment = get_absolute_expression ();
11667 section_alignment = 0;
11669 obj_elf_change_section (section_name, section_type, section_flag,
11670 section_entry_size, 0, 0, 0);
11671 #endif /* OBJ_ELF */
11675 mips_enable_auto_align ()
11686 label = insn_labels != NULL ? insn_labels->label : NULL;
11687 mips_emit_delays (false);
11688 if (log_size > 0 && auto_align)
11689 mips_align (log_size, 0, label);
11690 mips_clear_insn_labels ();
11691 cons (1 << log_size);
11695 s_float_cons (type)
11700 label = insn_labels != NULL ? insn_labels->label : NULL;
11702 mips_emit_delays (false);
11707 mips_align (3, 0, label);
11709 mips_align (2, 0, label);
11712 mips_clear_insn_labels ();
11717 /* Handle .globl. We need to override it because on Irix 5 you are
11720 where foo is an undefined symbol, to mean that foo should be
11721 considered to be the address of a function. */
11725 int x ATTRIBUTE_UNUSED;
11732 name = input_line_pointer;
11733 c = get_symbol_end ();
11734 symbolP = symbol_find_or_make (name);
11735 *input_line_pointer = c;
11736 SKIP_WHITESPACE ();
11738 /* On Irix 5, every global symbol that is not explicitly labelled as
11739 being a function is apparently labelled as being an object. */
11742 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11747 secname = input_line_pointer;
11748 c = get_symbol_end ();
11749 sec = bfd_get_section_by_name (stdoutput, secname);
11751 as_bad (_("%s: no such section"), secname);
11752 *input_line_pointer = c;
11754 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11755 flag = BSF_FUNCTION;
11758 symbol_get_bfdsym (symbolP)->flags |= flag;
11760 S_SET_EXTERNAL (symbolP);
11761 demand_empty_rest_of_line ();
11766 int x ATTRIBUTE_UNUSED;
11771 opt = input_line_pointer;
11772 c = get_symbol_end ();
11776 /* FIXME: What does this mean? */
11778 else if (strncmp (opt, "pic", 3) == 0)
11782 i = atoi (opt + 3);
11786 mips_pic = SVR4_PIC;
11788 as_bad (_(".option pic%d not supported"), i);
11790 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11792 if (g_switch_seen && g_switch_value != 0)
11793 as_warn (_("-G may not be used with SVR4 PIC code"));
11794 g_switch_value = 0;
11795 bfd_set_gp_size (stdoutput, 0);
11799 as_warn (_("Unrecognized option \"%s\""), opt);
11801 *input_line_pointer = c;
11802 demand_empty_rest_of_line ();
11805 /* This structure is used to hold a stack of .set values. */
11807 struct mips_option_stack
11809 struct mips_option_stack *next;
11810 struct mips_set_options options;
11813 static struct mips_option_stack *mips_opts_stack;
11815 /* Handle the .set pseudo-op. */
11819 int x ATTRIBUTE_UNUSED;
11821 char *name = input_line_pointer, ch;
11823 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11824 ++input_line_pointer;
11825 ch = *input_line_pointer;
11826 *input_line_pointer = '\0';
11828 if (strcmp (name, "reorder") == 0)
11830 if (mips_opts.noreorder && prev_nop_frag != NULL)
11832 /* If we still have pending nops, we can discard them. The
11833 usual nop handling will insert any that are still
11835 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11836 * (mips_opts.mips16 ? 2 : 4));
11837 prev_nop_frag = NULL;
11839 mips_opts.noreorder = 0;
11841 else if (strcmp (name, "noreorder") == 0)
11843 mips_emit_delays (true);
11844 mips_opts.noreorder = 1;
11845 mips_any_noreorder = 1;
11847 else if (strcmp (name, "at") == 0)
11849 mips_opts.noat = 0;
11851 else if (strcmp (name, "noat") == 0)
11853 mips_opts.noat = 1;
11855 else if (strcmp (name, "macro") == 0)
11857 mips_opts.warn_about_macros = 0;
11859 else if (strcmp (name, "nomacro") == 0)
11861 if (mips_opts.noreorder == 0)
11862 as_bad (_("`noreorder' must be set before `nomacro'"));
11863 mips_opts.warn_about_macros = 1;
11865 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11867 mips_opts.nomove = 0;
11869 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11871 mips_opts.nomove = 1;
11873 else if (strcmp (name, "bopt") == 0)
11875 mips_opts.nobopt = 0;
11877 else if (strcmp (name, "nobopt") == 0)
11879 mips_opts.nobopt = 1;
11881 else if (strcmp (name, "mips16") == 0
11882 || strcmp (name, "MIPS-16") == 0)
11883 mips_opts.mips16 = 1;
11884 else if (strcmp (name, "nomips16") == 0
11885 || strcmp (name, "noMIPS-16") == 0)
11886 mips_opts.mips16 = 0;
11887 else if (strcmp (name, "mips3d") == 0)
11888 mips_opts.ase_mips3d = 1;
11889 else if (strcmp (name, "nomips3d") == 0)
11890 mips_opts.ase_mips3d = 0;
11891 else if (strcmp (name, "mdmx") == 0)
11892 mips_opts.ase_mdmx = 1;
11893 else if (strcmp (name, "nomdmx") == 0)
11894 mips_opts.ase_mdmx = 0;
11895 else if (strncmp (name, "mips", 4) == 0)
11899 /* Permit the user to change the ISA on the fly. Needless to
11900 say, misuse can cause serious problems. */
11901 isa = atoi (name + 4);
11905 mips_opts.gp32 = file_mips_gp32;
11906 mips_opts.fp32 = file_mips_fp32;
11911 mips_opts.gp32 = 1;
11912 mips_opts.fp32 = 1;
11918 mips_opts.gp32 = 0;
11919 mips_opts.fp32 = 0;
11922 as_bad (_("unknown ISA level %s"), name + 4);
11928 case 0: mips_opts.isa = file_mips_isa; break;
11929 case 1: mips_opts.isa = ISA_MIPS1; break;
11930 case 2: mips_opts.isa = ISA_MIPS2; break;
11931 case 3: mips_opts.isa = ISA_MIPS3; break;
11932 case 4: mips_opts.isa = ISA_MIPS4; break;
11933 case 5: mips_opts.isa = ISA_MIPS5; break;
11934 case 32: mips_opts.isa = ISA_MIPS32; break;
11935 case 64: mips_opts.isa = ISA_MIPS64; break;
11936 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11939 else if (strcmp (name, "autoextend") == 0)
11940 mips_opts.noautoextend = 0;
11941 else if (strcmp (name, "noautoextend") == 0)
11942 mips_opts.noautoextend = 1;
11943 else if (strcmp (name, "push") == 0)
11945 struct mips_option_stack *s;
11947 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11948 s->next = mips_opts_stack;
11949 s->options = mips_opts;
11950 mips_opts_stack = s;
11952 else if (strcmp (name, "pop") == 0)
11954 struct mips_option_stack *s;
11956 s = mips_opts_stack;
11958 as_bad (_(".set pop with no .set push"));
11961 /* If we're changing the reorder mode we need to handle
11962 delay slots correctly. */
11963 if (s->options.noreorder && ! mips_opts.noreorder)
11964 mips_emit_delays (true);
11965 else if (! s->options.noreorder && mips_opts.noreorder)
11967 if (prev_nop_frag != NULL)
11969 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11970 * (mips_opts.mips16 ? 2 : 4));
11971 prev_nop_frag = NULL;
11975 mips_opts = s->options;
11976 mips_opts_stack = s->next;
11982 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11984 *input_line_pointer = ch;
11985 demand_empty_rest_of_line ();
11988 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11989 .option pic2. It means to generate SVR4 PIC calls. */
11992 s_abicalls (ignore)
11993 int ignore ATTRIBUTE_UNUSED;
11995 mips_pic = SVR4_PIC;
11996 if (USE_GLOBAL_POINTER_OPT)
11998 if (g_switch_seen && g_switch_value != 0)
11999 as_warn (_("-G may not be used with SVR4 PIC code"));
12000 g_switch_value = 0;
12002 bfd_set_gp_size (stdoutput, 0);
12003 demand_empty_rest_of_line ();
12006 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12007 PIC code. It sets the $gp register for the function based on the
12008 function address, which is in the register named in the argument.
12009 This uses a relocation against _gp_disp, which is handled specially
12010 by the linker. The result is:
12011 lui $gp,%hi(_gp_disp)
12012 addiu $gp,$gp,%lo(_gp_disp)
12013 addu $gp,$gp,.cpload argument
12014 The .cpload argument is normally $25 == $t9. */
12018 int ignore ATTRIBUTE_UNUSED;
12023 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12024 .cpload is ignored. */
12025 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12031 /* .cpload should be in a .set noreorder section. */
12032 if (mips_opts.noreorder == 0)
12033 as_warn (_(".cpload not in noreorder section"));
12035 ex.X_op = O_symbol;
12036 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12037 ex.X_op_symbol = NULL;
12038 ex.X_add_number = 0;
12040 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12041 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12043 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12044 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
12045 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
12047 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
12048 mips_gp_register, mips_gp_register, tc_get_register (0));
12050 demand_empty_rest_of_line ();
12053 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12054 .cpsetup $reg1, offset|$reg2, label
12056 If offset is given, this results in:
12057 sd $gp, offset($sp)
12058 lui $gp, %hi(%neg(%gp_rel(label)))
12059 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12060 daddu $gp, $gp, $reg1
12062 If $reg2 is given, this results in:
12063 daddu $reg2, $gp, $0
12064 lui $gp, %hi(%neg(%gp_rel(label)))
12065 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12066 daddu $gp, $gp, $reg1
12067 $reg1 is normally $25 == $t9. */
12070 int ignore ATTRIBUTE_UNUSED;
12072 expressionS ex_off;
12073 expressionS ex_sym;
12078 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12079 We also need NewABI support. */
12080 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12086 reg1 = tc_get_register (0);
12087 SKIP_WHITESPACE ();
12088 if (*input_line_pointer != ',')
12090 as_bad (_("missing argument separator ',' for .cpsetup"));
12094 ++input_line_pointer;
12095 SKIP_WHITESPACE ();
12096 if (*input_line_pointer == '$')
12098 mips_cpreturn_register = tc_get_register (0);
12099 mips_cpreturn_offset = -1;
12103 mips_cpreturn_offset = get_absolute_expression ();
12104 mips_cpreturn_register = -1;
12106 SKIP_WHITESPACE ();
12107 if (*input_line_pointer != ',')
12109 as_bad (_("missing argument separator ',' for .cpsetup"));
12113 ++input_line_pointer;
12114 SKIP_WHITESPACE ();
12115 expression (&ex_sym);
12117 if (mips_cpreturn_register == -1)
12119 ex_off.X_op = O_constant;
12120 ex_off.X_add_symbol = NULL;
12121 ex_off.X_op_symbol = NULL;
12122 ex_off.X_add_number = mips_cpreturn_offset;
12124 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
12125 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12128 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12129 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
12131 /* Ensure there's room for the next two instructions, so that `f'
12132 doesn't end up with an address in the wrong frag. */
12135 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12136 (int) BFD_RELOC_GPREL16);
12137 fix_new (frag_now, f - frag_now->fr_literal,
12138 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12139 fix_new (frag_now, f - frag_now->fr_literal,
12140 0, NULL, 0, 0, BFD_RELOC_HI16_S);
12143 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
12144 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
12145 fix_new (frag_now, f - frag_now->fr_literal,
12146 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12147 fix_new (frag_now, f - frag_now->fr_literal,
12148 0, NULL, 0, 0, BFD_RELOC_LO16);
12150 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12151 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
12152 mips_gp_register, mips_gp_register, reg1);
12154 demand_empty_rest_of_line ();
12159 int ignore ATTRIBUTE_UNUSED;
12161 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12162 .cplocal is ignored. */
12163 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12169 mips_gp_register = tc_get_register (0);
12170 demand_empty_rest_of_line ();
12173 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12174 offset from $sp. The offset is remembered, and after making a PIC
12175 call $gp is restored from that location. */
12178 s_cprestore (ignore)
12179 int ignore ATTRIBUTE_UNUSED;
12184 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12185 .cprestore is ignored. */
12186 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12192 mips_cprestore_offset = get_absolute_expression ();
12193 mips_cprestore_valid = 1;
12195 ex.X_op = O_constant;
12196 ex.X_add_symbol = NULL;
12197 ex.X_op_symbol = NULL;
12198 ex.X_add_number = mips_cprestore_offset;
12200 macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex,
12201 HAVE_32BIT_ADDRESSES ? "sw" : "sd",
12202 mips_gp_register, SP);
12204 demand_empty_rest_of_line ();
12207 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12208 was given in the preceeding .gpsetup, it results in:
12209 ld $gp, offset($sp)
12211 If a register $reg2 was given there, it results in:
12212 daddiu $gp, $gp, $reg2
12215 s_cpreturn (ignore)
12216 int ignore ATTRIBUTE_UNUSED;
12221 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12222 We also need NewABI support. */
12223 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12229 if (mips_cpreturn_register == -1)
12231 ex.X_op = O_constant;
12232 ex.X_add_symbol = NULL;
12233 ex.X_op_symbol = NULL;
12234 ex.X_add_number = mips_cpreturn_offset;
12236 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
12237 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12240 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12241 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
12243 demand_empty_rest_of_line ();
12246 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12247 code. It sets the offset to use in gp_rel relocations. */
12251 int ignore ATTRIBUTE_UNUSED;
12253 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12254 We also need NewABI support. */
12255 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12261 mips_gprel_offset = get_absolute_expression ();
12263 demand_empty_rest_of_line ();
12266 /* Handle the .gpword pseudo-op. This is used when generating PIC
12267 code. It generates a 32 bit GP relative reloc. */
12271 int ignore ATTRIBUTE_UNUSED;
12277 /* When not generating PIC code, this is treated as .word. */
12278 if (mips_pic != SVR4_PIC)
12284 label = insn_labels != NULL ? insn_labels->label : NULL;
12285 mips_emit_delays (true);
12287 mips_align (2, 0, label);
12288 mips_clear_insn_labels ();
12292 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12294 as_bad (_("Unsupported use of .gpword"));
12295 ignore_rest_of_line ();
12299 md_number_to_chars (p, (valueT) 0, 4);
12300 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
12301 BFD_RELOC_GPREL32);
12303 demand_empty_rest_of_line ();
12306 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12307 tables in SVR4 PIC code. */
12311 int ignore ATTRIBUTE_UNUSED;
12316 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12318 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12324 /* Add $gp to the register named as an argument. */
12325 reg = tc_get_register (0);
12326 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12327 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
12328 "d,v,t", reg, reg, mips_gp_register);
12330 demand_empty_rest_of_line ();
12333 /* Handle the .insn pseudo-op. This marks instruction labels in
12334 mips16 mode. This permits the linker to handle them specially,
12335 such as generating jalx instructions when needed. We also make
12336 them odd for the duration of the assembly, in order to generate the
12337 right sort of code. We will make them even in the adjust_symtab
12338 routine, while leaving them marked. This is convenient for the
12339 debugger and the disassembler. The linker knows to make them odd
12344 int ignore ATTRIBUTE_UNUSED;
12346 mips16_mark_labels ();
12348 demand_empty_rest_of_line ();
12351 /* Handle a .stabn directive. We need these in order to mark a label
12352 as being a mips16 text label correctly. Sometimes the compiler
12353 will emit a label, followed by a .stabn, and then switch sections.
12354 If the label and .stabn are in mips16 mode, then the label is
12355 really a mips16 text label. */
12362 mips16_mark_labels ();
12367 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12371 s_mips_weakext (ignore)
12372 int ignore ATTRIBUTE_UNUSED;
12379 name = input_line_pointer;
12380 c = get_symbol_end ();
12381 symbolP = symbol_find_or_make (name);
12382 S_SET_WEAK (symbolP);
12383 *input_line_pointer = c;
12385 SKIP_WHITESPACE ();
12387 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12389 if (S_IS_DEFINED (symbolP))
12391 as_bad ("ignoring attempt to redefine symbol %s",
12392 S_GET_NAME (symbolP));
12393 ignore_rest_of_line ();
12397 if (*input_line_pointer == ',')
12399 ++input_line_pointer;
12400 SKIP_WHITESPACE ();
12404 if (exp.X_op != O_symbol)
12406 as_bad ("bad .weakext directive");
12407 ignore_rest_of_line ();
12410 symbol_set_value_expression (symbolP, &exp);
12413 demand_empty_rest_of_line ();
12416 /* Parse a register string into a number. Called from the ECOFF code
12417 to parse .frame. The argument is non-zero if this is the frame
12418 register, so that we can record it in mips_frame_reg. */
12421 tc_get_register (frame)
12426 SKIP_WHITESPACE ();
12427 if (*input_line_pointer++ != '$')
12429 as_warn (_("expected `$'"));
12432 else if (ISDIGIT (*input_line_pointer))
12434 reg = get_absolute_expression ();
12435 if (reg < 0 || reg >= 32)
12437 as_warn (_("Bad register number"));
12443 if (strncmp (input_line_pointer, "ra", 2) == 0)
12446 input_line_pointer += 2;
12448 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12451 input_line_pointer += 2;
12453 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12456 input_line_pointer += 2;
12458 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12461 input_line_pointer += 2;
12463 else if (strncmp (input_line_pointer, "at", 2) == 0)
12466 input_line_pointer += 2;
12468 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12471 input_line_pointer += 3;
12473 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12476 input_line_pointer += 3;
12478 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12481 input_line_pointer += 4;
12485 as_warn (_("Unrecognized register name"));
12487 while (ISALNUM(*input_line_pointer))
12488 input_line_pointer++;
12493 mips_frame_reg = reg != 0 ? reg : SP;
12494 mips_frame_reg_valid = 1;
12495 mips_cprestore_valid = 0;
12501 md_section_align (seg, addr)
12505 int align = bfd_get_section_alignment (stdoutput, seg);
12508 /* We don't need to align ELF sections to the full alignment.
12509 However, Irix 5 may prefer that we align them at least to a 16
12510 byte boundary. We don't bother to align the sections if we are
12511 targeted for an embedded system. */
12512 if (strcmp (TARGET_OS, "elf") == 0)
12518 return ((addr + (1 << align) - 1) & (-1 << align));
12521 /* Utility routine, called from above as well. If called while the
12522 input file is still being read, it's only an approximation. (For
12523 example, a symbol may later become defined which appeared to be
12524 undefined earlier.) */
12527 nopic_need_relax (sym, before_relaxing)
12529 int before_relaxing;
12534 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12536 const char *symname;
12539 /* Find out whether this symbol can be referenced off the $gp
12540 register. It can be if it is smaller than the -G size or if
12541 it is in the .sdata or .sbss section. Certain symbols can
12542 not be referenced off the $gp, although it appears as though
12544 symname = S_GET_NAME (sym);
12545 if (symname != (const char *) NULL
12546 && (strcmp (symname, "eprol") == 0
12547 || strcmp (symname, "etext") == 0
12548 || strcmp (symname, "_gp") == 0
12549 || strcmp (symname, "edata") == 0
12550 || strcmp (symname, "_fbss") == 0
12551 || strcmp (symname, "_fdata") == 0
12552 || strcmp (symname, "_ftext") == 0
12553 || strcmp (symname, "end") == 0
12554 || strcmp (symname, "_gp_disp") == 0))
12556 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12558 #ifndef NO_ECOFF_DEBUGGING
12559 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12560 && (symbol_get_obj (sym)->ecoff_extern_size
12561 <= g_switch_value))
12563 /* We must defer this decision until after the whole
12564 file has been read, since there might be a .extern
12565 after the first use of this symbol. */
12566 || (before_relaxing
12567 #ifndef NO_ECOFF_DEBUGGING
12568 && symbol_get_obj (sym)->ecoff_extern_size == 0
12570 && S_GET_VALUE (sym) == 0)
12571 || (S_GET_VALUE (sym) != 0
12572 && S_GET_VALUE (sym) <= g_switch_value)))
12576 const char *segname;
12578 segname = segment_name (S_GET_SEGMENT (sym));
12579 assert (strcmp (segname, ".lit8") != 0
12580 && strcmp (segname, ".lit4") != 0);
12581 change = (strcmp (segname, ".sdata") != 0
12582 && strcmp (segname, ".sbss") != 0
12583 && strncmp (segname, ".sdata.", 7) != 0
12584 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12589 /* We are not optimizing for the $gp register. */
12593 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12594 extended opcode. SEC is the section the frag is in. */
12597 mips16_extended_frag (fragp, sec, stretch)
12603 register const struct mips16_immed_operand *op;
12605 int mintiny, maxtiny;
12609 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12611 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12614 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12615 op = mips16_immed_operands;
12616 while (op->type != type)
12619 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12624 if (type == '<' || type == '>' || type == '[' || type == ']')
12627 maxtiny = 1 << op->nbits;
12632 maxtiny = (1 << op->nbits) - 1;
12637 mintiny = - (1 << (op->nbits - 1));
12638 maxtiny = (1 << (op->nbits - 1)) - 1;
12641 sym_frag = symbol_get_frag (fragp->fr_symbol);
12642 val = S_GET_VALUE (fragp->fr_symbol);
12643 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12649 /* We won't have the section when we are called from
12650 mips_relax_frag. However, we will always have been called
12651 from md_estimate_size_before_relax first. If this is a
12652 branch to a different section, we mark it as such. If SEC is
12653 NULL, and the frag is not marked, then it must be a branch to
12654 the same section. */
12657 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12662 /* Must have been called from md_estimate_size_before_relax. */
12665 fragp->fr_subtype =
12666 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12668 /* FIXME: We should support this, and let the linker
12669 catch branches and loads that are out of range. */
12670 as_bad_where (fragp->fr_file, fragp->fr_line,
12671 _("unsupported PC relative reference to different section"));
12675 if (fragp != sym_frag && sym_frag->fr_address == 0)
12676 /* Assume non-extended on the first relaxation pass.
12677 The address we have calculated will be bogus if this is
12678 a forward branch to another frag, as the forward frag
12679 will have fr_address == 0. */
12683 /* In this case, we know for sure that the symbol fragment is in
12684 the same section. If the relax_marker of the symbol fragment
12685 differs from the relax_marker of this fragment, we have not
12686 yet adjusted the symbol fragment fr_address. We want to add
12687 in STRETCH in order to get a better estimate of the address.
12688 This particularly matters because of the shift bits. */
12690 && sym_frag->relax_marker != fragp->relax_marker)
12694 /* Adjust stretch for any alignment frag. Note that if have
12695 been expanding the earlier code, the symbol may be
12696 defined in what appears to be an earlier frag. FIXME:
12697 This doesn't handle the fr_subtype field, which specifies
12698 a maximum number of bytes to skip when doing an
12700 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12702 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12705 stretch = - ((- stretch)
12706 & ~ ((1 << (int) f->fr_offset) - 1));
12708 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12717 addr = fragp->fr_address + fragp->fr_fix;
12719 /* The base address rules are complicated. The base address of
12720 a branch is the following instruction. The base address of a
12721 PC relative load or add is the instruction itself, but if it
12722 is in a delay slot (in which case it can not be extended) use
12723 the address of the instruction whose delay slot it is in. */
12724 if (type == 'p' || type == 'q')
12728 /* If we are currently assuming that this frag should be
12729 extended, then, the current address is two bytes
12731 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12734 /* Ignore the low bit in the target, since it will be set
12735 for a text label. */
12736 if ((val & 1) != 0)
12739 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12741 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12744 val -= addr & ~ ((1 << op->shift) - 1);
12746 /* Branch offsets have an implicit 0 in the lowest bit. */
12747 if (type == 'p' || type == 'q')
12750 /* If any of the shifted bits are set, we must use an extended
12751 opcode. If the address depends on the size of this
12752 instruction, this can lead to a loop, so we arrange to always
12753 use an extended opcode. We only check this when we are in
12754 the main relaxation loop, when SEC is NULL. */
12755 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12757 fragp->fr_subtype =
12758 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12762 /* If we are about to mark a frag as extended because the value
12763 is precisely maxtiny + 1, then there is a chance of an
12764 infinite loop as in the following code:
12769 In this case when the la is extended, foo is 0x3fc bytes
12770 away, so the la can be shrunk, but then foo is 0x400 away, so
12771 the la must be extended. To avoid this loop, we mark the
12772 frag as extended if it was small, and is about to become
12773 extended with a value of maxtiny + 1. */
12774 if (val == ((maxtiny + 1) << op->shift)
12775 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12778 fragp->fr_subtype =
12779 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12783 else if (symsec != absolute_section && sec != NULL)
12784 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12786 if ((val & ((1 << op->shift) - 1)) != 0
12787 || val < (mintiny << op->shift)
12788 || val > (maxtiny << op->shift))
12794 /* Compute the length of a branch sequence, and adjust the
12795 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12796 worst-case length is computed, with UPDATE being used to indicate
12797 whether an unconditional (-1), branch-likely (+1) or regular (0)
12798 branch is to be computed. */
12800 relaxed_branch_length (fragp, sec, update)
12809 && S_IS_DEFINED (fragp->fr_symbol)
12810 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12815 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12817 addr = fragp->fr_address + fragp->fr_fix + 4;
12821 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12824 /* If the symbol is not defined or it's in a different segment,
12825 assume the user knows what's going on and emit a short
12831 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12833 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_RELOC_S2 (fragp->fr_subtype),
12834 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12835 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12836 RELAX_BRANCH_LINK (fragp->fr_subtype),
12842 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12845 if (mips_pic != NO_PIC)
12847 /* Additional space for PIC loading of target address. */
12849 if (mips_opts.isa == ISA_MIPS1)
12850 /* Additional space for $at-stabilizing nop. */
12854 /* If branch is conditional. */
12855 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12862 /* Estimate the size of a frag before relaxing. Unless this is the
12863 mips16, we are not really relaxing here, and the final size is
12864 encoded in the subtype information. For the mips16, we have to
12865 decide whether we are using an extended opcode or not. */
12868 md_estimate_size_before_relax (fragp, segtype)
12873 boolean linkonce = false;
12875 if (RELAX_BRANCH_P (fragp->fr_subtype))
12878 fragp->fr_var = relaxed_branch_length (fragp, segtype, false);
12880 return fragp->fr_var;
12883 if (RELAX_MIPS16_P (fragp->fr_subtype))
12884 /* We don't want to modify the EXTENDED bit here; it might get us
12885 into infinite loops. We change it only in mips_relax_frag(). */
12886 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12888 if (mips_pic == NO_PIC)
12890 change = nopic_need_relax (fragp->fr_symbol, 0);
12892 else if (mips_pic == SVR4_PIC)
12897 sym = fragp->fr_symbol;
12899 /* Handle the case of a symbol equated to another symbol. */
12900 while (symbol_equated_reloc_p (sym))
12904 /* It's possible to get a loop here in a badly written
12906 n = symbol_get_value_expression (sym)->X_add_symbol;
12912 symsec = S_GET_SEGMENT (sym);
12914 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12915 if (symsec != segtype && ! S_IS_LOCAL (sym))
12917 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12921 /* The GNU toolchain uses an extension for ELF: a section
12922 beginning with the magic string .gnu.linkonce is a linkonce
12924 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12925 sizeof ".gnu.linkonce" - 1) == 0)
12929 /* This must duplicate the test in adjust_reloc_syms. */
12930 change = (symsec != &bfd_und_section
12931 && symsec != &bfd_abs_section
12932 && ! bfd_is_com_section (symsec)
12935 /* A global or weak symbol is treated as external. */
12936 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12937 || (! S_IS_WEAK (sym)
12938 && (! S_IS_EXTERNAL (sym)
12939 || mips_pic == EMBEDDED_PIC)))
12948 /* Record the offset to the first reloc in the fr_opcode field.
12949 This lets md_convert_frag and tc_gen_reloc know that the code
12950 must be expanded. */
12951 fragp->fr_opcode = (fragp->fr_literal
12953 - RELAX_OLD (fragp->fr_subtype)
12954 + RELAX_RELOC1 (fragp->fr_subtype));
12955 /* FIXME: This really needs as_warn_where. */
12956 if (RELAX_WARN (fragp->fr_subtype))
12957 as_warn (_("AT used after \".set noat\" or macro used after "
12958 "\".set nomacro\""));
12960 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12966 /* This is called to see whether a reloc against a defined symbol
12967 should be converted into a reloc against a section. Don't adjust
12968 MIPS16 jump relocations, so we don't have to worry about the format
12969 of the offset in the .o file. Don't adjust relocations against
12970 mips16 symbols, so that the linker can find them if it needs to set
12974 mips_fix_adjustable (fixp)
12977 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12980 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12981 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12984 if (fixp->fx_addsy == NULL)
12988 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12989 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12990 && fixp->fx_subsy == NULL)
12997 /* Translate internal representation of relocation info to BFD target
13001 tc_gen_reloc (section, fixp)
13002 asection *section ATTRIBUTE_UNUSED;
13005 static arelent *retval[4];
13007 bfd_reloc_code_real_type code;
13009 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
13012 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13013 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13014 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13016 if (mips_pic == EMBEDDED_PIC
13017 && SWITCH_TABLE (fixp))
13019 /* For a switch table entry we use a special reloc. The addend
13020 is actually the difference between the reloc address and the
13022 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13023 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13024 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13025 fixp->fx_r_type = BFD_RELOC_GPREL32;
13027 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
13029 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13030 reloc->addend = fixp->fx_addnumber;
13033 /* We use a special addend for an internal RELLO reloc. */
13034 if (symbol_section_p (fixp->fx_addsy))
13035 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13037 reloc->addend = fixp->fx_addnumber + reloc->address;
13040 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13042 assert (fixp->fx_next != NULL
13043 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13045 /* The reloc is relative to the RELLO; adjust the addend
13047 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13048 reloc->addend = fixp->fx_next->fx_addnumber;
13051 /* We use a special addend for an internal RELHI reloc. */
13052 if (symbol_section_p (fixp->fx_addsy))
13053 reloc->addend = (fixp->fx_next->fx_frag->fr_address
13054 + fixp->fx_next->fx_where
13055 - S_GET_VALUE (fixp->fx_subsy));
13057 reloc->addend = (fixp->fx_addnumber
13058 + fixp->fx_next->fx_frag->fr_address
13059 + fixp->fx_next->fx_where);
13062 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13063 reloc->addend = fixp->fx_addnumber;
13066 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13067 /* A gruesome hack which is a result of the gruesome gas reloc
13069 reloc->addend = reloc->address;
13071 reloc->addend = -reloc->address;
13074 /* If this is a variant frag, we may need to adjust the existing
13075 reloc and generate a new one. */
13076 if (fixp->fx_frag->fr_opcode != NULL
13077 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13079 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13080 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13081 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13082 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13083 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13084 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13089 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13091 /* If this is not the last reloc in this frag, then we have two
13092 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13093 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13094 the second one handle all of them. */
13095 if (fixp->fx_next != NULL
13096 && fixp->fx_frag == fixp->fx_next->fx_frag)
13098 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13099 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13100 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13101 && (fixp->fx_next->fx_r_type
13102 == BFD_RELOC_MIPS_GOT_LO16))
13103 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13104 && (fixp->fx_next->fx_r_type
13105 == BFD_RELOC_MIPS_CALL_LO16)));
13110 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13111 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13112 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13114 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13115 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13116 reloc2->address = (reloc->address
13117 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13118 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13119 reloc2->addend = fixp->fx_addnumber;
13120 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13121 assert (reloc2->howto != NULL);
13123 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13127 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13130 reloc3->address += 4;
13133 if (mips_pic == NO_PIC)
13135 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13136 fixp->fx_r_type = BFD_RELOC_HI16_S;
13138 else if (mips_pic == SVR4_PIC)
13140 switch (fixp->fx_r_type)
13144 case BFD_RELOC_MIPS_GOT16:
13146 case BFD_RELOC_MIPS_GOT_LO16:
13147 case BFD_RELOC_MIPS_CALL_LO16:
13148 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13150 case BFD_RELOC_MIPS_CALL16:
13153 /* BFD_RELOC_MIPS_GOT16;*/
13154 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13155 reloc2->howto = bfd_reloc_type_lookup
13156 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13159 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13166 /* newabi uses R_MIPS_GOT_DISP for local symbols */
13167 if (HAVE_NEWABI && BFD_RELOC_MIPS_GOT_LO16)
13169 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13174 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13175 entry to be used in the relocation's section offset. */
13176 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13178 reloc->address = reloc->addend;
13182 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13183 fixup_segment converted a non-PC relative reloc into a PC
13184 relative reloc. In such a case, we need to convert the reloc
13186 code = fixp->fx_r_type;
13187 if (fixp->fx_pcrel)
13192 code = BFD_RELOC_8_PCREL;
13195 code = BFD_RELOC_16_PCREL;
13198 code = BFD_RELOC_32_PCREL;
13201 code = BFD_RELOC_64_PCREL;
13203 case BFD_RELOC_8_PCREL:
13204 case BFD_RELOC_16_PCREL:
13205 case BFD_RELOC_32_PCREL:
13206 case BFD_RELOC_64_PCREL:
13207 case BFD_RELOC_16_PCREL_S2:
13208 case BFD_RELOC_PCREL_HI16_S:
13209 case BFD_RELOC_PCREL_LO16:
13212 as_bad_where (fixp->fx_file, fixp->fx_line,
13213 _("Cannot make %s relocation PC relative"),
13214 bfd_get_reloc_code_name (code));
13219 /* md_apply_fix3 has a double-subtraction hack to get
13220 bfd_install_relocation to behave nicely. GPREL relocations are
13221 handled correctly without this hack, so undo it here. We can't
13222 stop md_apply_fix3 from subtracting twice in the first place since
13223 the fake addend is required for variant frags above. */
13224 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
13225 && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL)
13226 && reloc->addend != 0
13227 && mips_need_elf_addend_fixup (fixp))
13228 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
13231 /* To support a PC relative reloc when generating embedded PIC code
13232 for ECOFF, we use a Cygnus extension. We check for that here to
13233 make sure that we don't let such a reloc escape normally. */
13234 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13235 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13236 && code == BFD_RELOC_16_PCREL_S2
13237 && mips_pic != EMBEDDED_PIC)
13238 reloc->howto = NULL;
13240 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13242 if (reloc->howto == NULL)
13244 as_bad_where (fixp->fx_file, fixp->fx_line,
13245 _("Can not represent %s relocation in this object file format"),
13246 bfd_get_reloc_code_name (code));
13253 /* Relax a machine dependent frag. This returns the amount by which
13254 the current size of the frag should change. */
13257 mips_relax_frag (sec, fragp, stretch)
13262 if (RELAX_BRANCH_P (fragp->fr_subtype))
13264 offsetT old_var = fragp->fr_var;
13266 fragp->fr_var = relaxed_branch_length (fragp, sec, true);
13268 return fragp->fr_var - old_var;
13271 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13274 if (mips16_extended_frag (fragp, NULL, stretch))
13276 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13278 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13283 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13285 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13292 /* Convert a machine dependent frag. */
13295 md_convert_frag (abfd, asec, fragp)
13296 bfd *abfd ATTRIBUTE_UNUSED;
13303 if (RELAX_BRANCH_P (fragp->fr_subtype))
13306 unsigned long insn;
13310 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13312 if (target_big_endian)
13313 insn = bfd_getb32 (buf);
13315 insn = bfd_getl32 (buf);
13317 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13319 /* We generate a fixup instead of applying it right now
13320 because, if there are linker relaxations, we're going to
13321 need the relocations. */
13322 exp.X_op = O_symbol;
13323 exp.X_add_symbol = fragp->fr_symbol;
13324 exp.X_add_number = fragp->fr_offset;
13326 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13328 RELAX_BRANCH_RELOC_S2 (fragp->fr_subtype)
13329 ? BFD_RELOC_16_PCREL_S2
13330 : BFD_RELOC_16_PCREL);
13331 fixp->fx_file = fragp->fr_file;
13332 fixp->fx_line = fragp->fr_line;
13334 md_number_to_chars ((char *)buf, insn, 4);
13341 as_warn_where (fragp->fr_file, fragp->fr_line,
13342 _("relaxed out-of-range branch into a jump"));
13344 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13347 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13349 /* Reverse the branch. */
13350 switch ((insn >> 28) & 0xf)
13353 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13354 have the condition reversed by tweaking a single
13355 bit, and their opcodes all have 0x4???????. */
13356 assert ((insn & 0xf1000000) == 0x41000000);
13357 insn ^= 0x00010000;
13361 /* bltz 0x04000000 bgez 0x04010000
13362 bltzal 0x04100000 bgezal 0x04110000 */
13363 assert ((insn & 0xfc0e0000) == 0x04000000);
13364 insn ^= 0x00010000;
13368 /* beq 0x10000000 bne 0x14000000
13369 blez 0x18000000 bgtz 0x1c000000 */
13370 insn ^= 0x04000000;
13378 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13380 /* Clear the and-link bit. */
13381 assert ((insn & 0xfc1c0000) == 0x04100000);
13383 /* bltzal 0x04100000 bgezal 0x04110000
13384 bltzall 0x04120000 bgezall 0x04130000 */
13385 insn &= ~0x00100000;
13388 /* Branch over the branch (if the branch was likely) or the
13389 full jump (not likely case). Compute the offset from the
13390 current instruction to branch to. */
13391 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13395 /* How many bytes in instructions we've already emitted? */
13396 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13397 /* How many bytes in instructions from here to the end? */
13398 i = fragp->fr_var - i;
13400 /* Convert to instruction count. */
13402 /* Branch counts from the next instruction. */
13405 /* Branch over the jump. */
13406 md_number_to_chars ((char *)buf, insn, 4);
13410 md_number_to_chars ((char*)buf, 0, 4);
13413 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13415 /* beql $0, $0, 2f */
13417 /* Compute the PC offset from the current instruction to
13418 the end of the variable frag. */
13419 /* How many bytes in instructions we've already emitted? */
13420 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13421 /* How many bytes in instructions from here to the end? */
13422 i = fragp->fr_var - i;
13423 /* Convert to instruction count. */
13425 /* Don't decrement i, because we want to branch over the
13429 md_number_to_chars ((char *)buf, insn, 4);
13432 md_number_to_chars ((char *)buf, 0, 4);
13437 if (mips_pic == NO_PIC)
13440 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13441 ? 0x0c000000 : 0x08000000);
13442 exp.X_op = O_symbol;
13443 exp.X_add_symbol = fragp->fr_symbol;
13444 exp.X_add_number = fragp->fr_offset;
13446 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13447 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13448 fixp->fx_file = fragp->fr_file;
13449 fixp->fx_line = fragp->fr_line;
13451 md_number_to_chars ((char*)buf, insn, 4);
13456 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13457 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13458 exp.X_op = O_symbol;
13459 exp.X_add_symbol = fragp->fr_symbol;
13460 exp.X_add_number = fragp->fr_offset;
13462 if (fragp->fr_offset)
13464 exp.X_add_symbol = make_expr_symbol (&exp);
13465 exp.X_add_number = 0;
13468 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13469 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13470 fixp->fx_file = fragp->fr_file;
13471 fixp->fx_line = fragp->fr_line;
13473 md_number_to_chars ((char*)buf, insn, 4);
13476 if (mips_opts.isa == ISA_MIPS1)
13479 md_number_to_chars ((char*)buf, 0, 4);
13483 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13484 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13486 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13487 4, &exp, 0, BFD_RELOC_LO16);
13488 fixp->fx_file = fragp->fr_file;
13489 fixp->fx_line = fragp->fr_line;
13491 md_number_to_chars ((char*)buf, insn, 4);
13495 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13500 md_number_to_chars ((char*)buf, insn, 4);
13505 assert (buf == (bfd_byte *)fragp->fr_literal
13506 + fragp->fr_fix + fragp->fr_var);
13508 fragp->fr_fix += fragp->fr_var;
13513 if (RELAX_MIPS16_P (fragp->fr_subtype))
13516 register const struct mips16_immed_operand *op;
13517 boolean small, ext;
13520 unsigned long insn;
13521 boolean use_extend;
13522 unsigned short extend;
13524 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13525 op = mips16_immed_operands;
13526 while (op->type != type)
13529 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13540 resolve_symbol_value (fragp->fr_symbol);
13541 val = S_GET_VALUE (fragp->fr_symbol);
13546 addr = fragp->fr_address + fragp->fr_fix;
13548 /* The rules for the base address of a PC relative reloc are
13549 complicated; see mips16_extended_frag. */
13550 if (type == 'p' || type == 'q')
13555 /* Ignore the low bit in the target, since it will be
13556 set for a text label. */
13557 if ((val & 1) != 0)
13560 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13562 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13565 addr &= ~ (addressT) ((1 << op->shift) - 1);
13568 /* Make sure the section winds up with the alignment we have
13571 record_alignment (asec, op->shift);
13575 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13576 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13577 as_warn_where (fragp->fr_file, fragp->fr_line,
13578 _("extended instruction in delay slot"));
13580 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13582 if (target_big_endian)
13583 insn = bfd_getb16 (buf);
13585 insn = bfd_getl16 (buf);
13587 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13588 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13589 small, ext, &insn, &use_extend, &extend);
13593 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13594 fragp->fr_fix += 2;
13598 md_number_to_chars ((char *) buf, insn, 2);
13599 fragp->fr_fix += 2;
13604 if (fragp->fr_opcode == NULL)
13607 old = RELAX_OLD (fragp->fr_subtype);
13608 new = RELAX_NEW (fragp->fr_subtype);
13609 fixptr = fragp->fr_literal + fragp->fr_fix;
13612 memcpy (fixptr - old, fixptr, new);
13614 fragp->fr_fix += new - old;
13620 /* This function is called after the relocs have been generated.
13621 We've been storing mips16 text labels as odd. Here we convert them
13622 back to even for the convenience of the debugger. */
13625 mips_frob_file_after_relocs ()
13628 unsigned int count, i;
13630 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13633 syms = bfd_get_outsymbols (stdoutput);
13634 count = bfd_get_symcount (stdoutput);
13635 for (i = 0; i < count; i++, syms++)
13637 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13638 && ((*syms)->value & 1) != 0)
13640 (*syms)->value &= ~1;
13641 /* If the symbol has an odd size, it was probably computed
13642 incorrectly, so adjust that as well. */
13643 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13644 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13651 /* This function is called whenever a label is defined. It is used
13652 when handling branch delays; if a branch has a label, we assume we
13653 can not move it. */
13656 mips_define_label (sym)
13659 struct insn_label_list *l;
13661 if (free_insn_labels == NULL)
13662 l = (struct insn_label_list *) xmalloc (sizeof *l);
13665 l = free_insn_labels;
13666 free_insn_labels = l->next;
13670 l->next = insn_labels;
13674 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13676 /* Some special processing for a MIPS ELF file. */
13679 mips_elf_final_processing ()
13681 /* Write out the register information. */
13682 if (mips_abi != N64_ABI)
13686 s.ri_gprmask = mips_gprmask;
13687 s.ri_cprmask[0] = mips_cprmask[0];
13688 s.ri_cprmask[1] = mips_cprmask[1];
13689 s.ri_cprmask[2] = mips_cprmask[2];
13690 s.ri_cprmask[3] = mips_cprmask[3];
13691 /* The gp_value field is set by the MIPS ELF backend. */
13693 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13694 ((Elf32_External_RegInfo *)
13695 mips_regmask_frag));
13699 Elf64_Internal_RegInfo s;
13701 s.ri_gprmask = mips_gprmask;
13703 s.ri_cprmask[0] = mips_cprmask[0];
13704 s.ri_cprmask[1] = mips_cprmask[1];
13705 s.ri_cprmask[2] = mips_cprmask[2];
13706 s.ri_cprmask[3] = mips_cprmask[3];
13707 /* The gp_value field is set by the MIPS ELF backend. */
13709 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13710 ((Elf64_External_RegInfo *)
13711 mips_regmask_frag));
13714 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13715 sort of BFD interface for this. */
13716 if (mips_any_noreorder)
13717 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13718 if (mips_pic != NO_PIC)
13719 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13721 /* Set MIPS ELF flags for ASEs. */
13722 if (file_ase_mips16)
13723 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13724 #if 0 /* XXX FIXME */
13725 if (file_ase_mips3d)
13726 elf_elfheader (stdoutput)->e_flags |= ???;
13729 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13731 /* Set the MIPS ELF ABI flags. */
13732 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13733 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13734 else if (mips_abi == O64_ABI)
13735 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13736 else if (mips_abi == EABI_ABI)
13738 if (!file_mips_gp32)
13739 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13741 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13743 else if (mips_abi == N32_ABI)
13744 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13746 /* Nothing to do for N64_ABI. */
13748 if (mips_32bitmode)
13749 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13752 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13754 typedef struct proc {
13756 unsigned long reg_mask;
13757 unsigned long reg_offset;
13758 unsigned long fpreg_mask;
13759 unsigned long fpreg_offset;
13760 unsigned long frame_offset;
13761 unsigned long frame_reg;
13762 unsigned long pc_reg;
13765 static procS cur_proc;
13766 static procS *cur_proc_ptr;
13767 static int numprocs;
13769 /* Fill in an rs_align_code fragment. */
13772 mips_handle_align (fragp)
13775 if (fragp->fr_type != rs_align_code)
13778 if (mips_opts.mips16)
13780 static const unsigned char be_nop[] = { 0x65, 0x00 };
13781 static const unsigned char le_nop[] = { 0x00, 0x65 };
13786 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13787 p = fragp->fr_literal + fragp->fr_fix;
13795 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13799 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13810 /* check for premature end, nesting errors, etc */
13812 as_warn (_("missing .end at end of assembly"));
13821 if (*input_line_pointer == '-')
13823 ++input_line_pointer;
13826 if (!ISDIGIT (*input_line_pointer))
13827 as_bad (_("expected simple number"));
13828 if (input_line_pointer[0] == '0')
13830 if (input_line_pointer[1] == 'x')
13832 input_line_pointer += 2;
13833 while (ISXDIGIT (*input_line_pointer))
13836 val |= hex_value (*input_line_pointer++);
13838 return negative ? -val : val;
13842 ++input_line_pointer;
13843 while (ISDIGIT (*input_line_pointer))
13846 val |= *input_line_pointer++ - '0';
13848 return negative ? -val : val;
13851 if (!ISDIGIT (*input_line_pointer))
13853 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13854 *input_line_pointer, *input_line_pointer);
13855 as_warn (_("invalid number"));
13858 while (ISDIGIT (*input_line_pointer))
13861 val += *input_line_pointer++ - '0';
13863 return negative ? -val : val;
13866 /* The .file directive; just like the usual .file directive, but there
13867 is an initial number which is the ECOFF file index. In the non-ECOFF
13868 case .file implies DWARF-2. */
13872 int x ATTRIBUTE_UNUSED;
13874 static int first_file_directive = 0;
13876 if (ECOFF_DEBUGGING)
13885 filename = dwarf2_directive_file (0);
13887 /* Versions of GCC up to 3.1 start files with a ".file"
13888 directive even for stabs output. Make sure that this
13889 ".file" is handled. Note that you need a version of GCC
13890 after 3.1 in order to support DWARF-2 on MIPS. */
13891 if (filename != NULL && ! first_file_directive)
13893 (void) new_logical_line (filename, -1);
13894 s_app_file_string (filename);
13896 first_file_directive = 1;
13900 /* The .loc directive, implying DWARF-2. */
13904 int x ATTRIBUTE_UNUSED;
13906 if (!ECOFF_DEBUGGING)
13907 dwarf2_directive_loc (0);
13910 /* The .end directive. */
13914 int x ATTRIBUTE_UNUSED;
13919 /* Following functions need their own .frame and .cprestore directives. */
13920 mips_frame_reg_valid = 0;
13921 mips_cprestore_valid = 0;
13923 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13926 demand_empty_rest_of_line ();
13931 #ifdef BFD_ASSEMBLER
13932 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13937 if (now_seg != data_section && now_seg != bss_section)
13944 as_warn (_(".end not in text section"));
13948 as_warn (_(".end directive without a preceding .ent directive."));
13949 demand_empty_rest_of_line ();
13955 assert (S_GET_NAME (p));
13956 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13957 as_warn (_(".end symbol does not match .ent symbol."));
13959 if (debug_type == DEBUG_STABS)
13960 stabs_generate_asm_endfunc (S_GET_NAME (p),
13964 as_warn (_(".end directive missing or unknown symbol"));
13967 /* Generate a .pdr section. */
13968 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13970 segT saved_seg = now_seg;
13971 subsegT saved_subseg = now_subseg;
13976 dot = frag_now_fix ();
13978 #ifdef md_flush_pending_output
13979 md_flush_pending_output ();
13983 subseg_set (pdr_seg, 0);
13985 /* Write the symbol. */
13986 exp.X_op = O_symbol;
13987 exp.X_add_symbol = p;
13988 exp.X_add_number = 0;
13989 emit_expr (&exp, 4);
13991 fragp = frag_more (7 * 4);
13993 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13994 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13995 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13996 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13997 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13998 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13999 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
14001 subseg_set (saved_seg, saved_subseg);
14003 #endif /* OBJ_ELF */
14005 cur_proc_ptr = NULL;
14008 /* The .aent and .ent directives. */
14017 symbolP = get_symbol ();
14018 if (*input_line_pointer == ',')
14019 ++input_line_pointer;
14020 SKIP_WHITESPACE ();
14021 if (ISDIGIT (*input_line_pointer)
14022 || *input_line_pointer == '-')
14025 #ifdef BFD_ASSEMBLER
14026 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
14031 if (now_seg != data_section && now_seg != bss_section)
14038 as_warn (_(".ent or .aent not in text section."));
14040 if (!aent && cur_proc_ptr)
14041 as_warn (_("missing .end"));
14045 /* This function needs its own .frame and .cprestore directives. */
14046 mips_frame_reg_valid = 0;
14047 mips_cprestore_valid = 0;
14049 cur_proc_ptr = &cur_proc;
14050 memset (cur_proc_ptr, '\0', sizeof (procS));
14052 cur_proc_ptr->isym = symbolP;
14054 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14058 if (debug_type == DEBUG_STABS)
14059 stabs_generate_asm_func (S_GET_NAME (symbolP),
14060 S_GET_NAME (symbolP));
14063 demand_empty_rest_of_line ();
14066 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14067 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14068 s_mips_frame is used so that we can set the PDR information correctly.
14069 We can't use the ecoff routines because they make reference to the ecoff
14070 symbol table (in the mdebug section). */
14073 s_mips_frame (ignore)
14074 int ignore ATTRIBUTE_UNUSED;
14077 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14081 if (cur_proc_ptr == (procS *) NULL)
14083 as_warn (_(".frame outside of .ent"));
14084 demand_empty_rest_of_line ();
14088 cur_proc_ptr->frame_reg = tc_get_register (1);
14090 SKIP_WHITESPACE ();
14091 if (*input_line_pointer++ != ','
14092 || get_absolute_expression_and_terminator (&val) != ',')
14094 as_warn (_("Bad .frame directive"));
14095 --input_line_pointer;
14096 demand_empty_rest_of_line ();
14100 cur_proc_ptr->frame_offset = val;
14101 cur_proc_ptr->pc_reg = tc_get_register (0);
14103 demand_empty_rest_of_line ();
14106 #endif /* OBJ_ELF */
14110 /* The .fmask and .mask directives. If the mdebug section is present
14111 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14112 embedded targets, s_mips_mask is used so that we can set the PDR
14113 information correctly. We can't use the ecoff routines because they
14114 make reference to the ecoff symbol table (in the mdebug section). */
14117 s_mips_mask (reg_type)
14121 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14125 if (cur_proc_ptr == (procS *) NULL)
14127 as_warn (_(".mask/.fmask outside of .ent"));
14128 demand_empty_rest_of_line ();
14132 if (get_absolute_expression_and_terminator (&mask) != ',')
14134 as_warn (_("Bad .mask/.fmask directive"));
14135 --input_line_pointer;
14136 demand_empty_rest_of_line ();
14140 off = get_absolute_expression ();
14142 if (reg_type == 'F')
14144 cur_proc_ptr->fpreg_mask = mask;
14145 cur_proc_ptr->fpreg_offset = off;
14149 cur_proc_ptr->reg_mask = mask;
14150 cur_proc_ptr->reg_offset = off;
14153 demand_empty_rest_of_line ();
14156 #endif /* OBJ_ELF */
14157 s_ignore (reg_type);
14160 /* The .loc directive. */
14171 assert (now_seg == text_section);
14173 lineno = get_number ();
14174 addroff = frag_now_fix ();
14176 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14177 S_SET_TYPE (symbolP, N_SLINE);
14178 S_SET_OTHER (symbolP, 0);
14179 S_SET_DESC (symbolP, lineno);
14180 symbolP->sy_segment = now_seg;
14184 /* A table describing all the processors gas knows about. Names are
14185 matched in the order listed.
14187 To ease comparison, please keep this table in the same order as
14188 gcc's mips_cpu_info_table[]. */
14189 static const struct mips_cpu_info mips_cpu_info_table[] =
14191 /* Entries for generic ISAs */
14192 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14193 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14194 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14195 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14196 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14197 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14198 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14201 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14202 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14203 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14206 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14209 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14210 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14211 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14212 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14213 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14214 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14215 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14216 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14217 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14218 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14219 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14220 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14223 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14224 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14225 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14226 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14227 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14228 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14229 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14230 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14231 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14232 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14233 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14234 { "r7000", 0, ISA_MIPS4, CPU_R5000 },
14237 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
14238 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14239 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14242 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14243 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14245 /* Broadcom SB-1 CPU core */
14246 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14253 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14254 with a final "000" replaced by "k". Ignore case.
14256 Note: this function is shared between GCC and GAS. */
14259 mips_strict_matching_cpu_name_p (canonical, given)
14260 const char *canonical, *given;
14262 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14263 given++, canonical++;
14265 return ((*given == 0 && *canonical == 0)
14266 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14270 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14271 CPU name. We've traditionally allowed a lot of variation here.
14273 Note: this function is shared between GCC and GAS. */
14276 mips_matching_cpu_name_p (canonical, given)
14277 const char *canonical, *given;
14279 /* First see if the name matches exactly, or with a final "000"
14280 turned into "k". */
14281 if (mips_strict_matching_cpu_name_p (canonical, given))
14284 /* If not, try comparing based on numerical designation alone.
14285 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14286 if (TOLOWER (*given) == 'r')
14288 if (!ISDIGIT (*given))
14291 /* Skip over some well-known prefixes in the canonical name,
14292 hoping to find a number there too. */
14293 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14295 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14297 else if (TOLOWER (canonical[0]) == 'r')
14300 return mips_strict_matching_cpu_name_p (canonical, given);
14304 /* Parse an option that takes the name of a processor as its argument.
14305 OPTION is the name of the option and CPU_STRING is the argument.
14306 Return the corresponding processor enumeration if the CPU_STRING is
14307 recognized, otherwise report an error and return null.
14309 A similar function exists in GCC. */
14311 static const struct mips_cpu_info *
14312 mips_parse_cpu (option, cpu_string)
14313 const char *option, *cpu_string;
14315 const struct mips_cpu_info *p;
14317 /* 'from-abi' selects the most compatible architecture for the given
14318 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14319 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14320 version. Look first at the -mgp options, if given, otherwise base
14321 the choice on MIPS_DEFAULT_64BIT.
14323 Treat NO_ABI like the EABIs. One reason to do this is that the
14324 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14325 architecture. This code picks MIPS I for 'mips' and MIPS III for
14326 'mips64', just as we did in the days before 'from-abi'. */
14327 if (strcasecmp (cpu_string, "from-abi") == 0)
14329 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14330 return mips_cpu_info_from_isa (ISA_MIPS1);
14332 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14333 return mips_cpu_info_from_isa (ISA_MIPS3);
14335 if (file_mips_gp32 >= 0)
14336 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14338 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14343 /* 'default' has traditionally been a no-op. Probably not very useful. */
14344 if (strcasecmp (cpu_string, "default") == 0)
14347 for (p = mips_cpu_info_table; p->name != 0; p++)
14348 if (mips_matching_cpu_name_p (p->name, cpu_string))
14351 as_bad ("Bad value (%s) for %s", cpu_string, option);
14355 /* Return the canonical processor information for ISA (a member of the
14356 ISA_MIPS* enumeration). */
14358 static const struct mips_cpu_info *
14359 mips_cpu_info_from_isa (isa)
14364 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14365 if (mips_cpu_info_table[i].is_isa
14366 && isa == mips_cpu_info_table[i].isa)
14367 return (&mips_cpu_info_table[i]);
14373 show (stream, string, col_p, first_p)
14375 const char *string;
14381 fprintf (stream, "%24s", "");
14386 fprintf (stream, ", ");
14390 if (*col_p + strlen (string) > 72)
14392 fprintf (stream, "\n%24s", "");
14396 fprintf (stream, "%s", string);
14397 *col_p += strlen (string);
14403 md_show_usage (stream)
14409 fprintf (stream, _("\
14411 -membedded-pic generate embedded position independent code\n\
14412 -EB generate big endian output\n\
14413 -EL generate little endian output\n\
14414 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14415 -G NUM allow referencing objects up to NUM bytes\n\
14416 implicitly with the gp register [default 8]\n"));
14417 fprintf (stream, _("\
14418 -mips1 generate MIPS ISA I instructions\n\
14419 -mips2 generate MIPS ISA II instructions\n\
14420 -mips3 generate MIPS ISA III instructions\n\
14421 -mips4 generate MIPS ISA IV instructions\n\
14422 -mips5 generate MIPS ISA V instructions\n\
14423 -mips32 generate MIPS32 ISA instructions\n\
14424 -mips64 generate MIPS64 ISA instructions\n\
14425 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14429 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14430 show (stream, mips_cpu_info_table[i].name, &column, &first);
14431 show (stream, "from-abi", &column, &first);
14432 fputc ('\n', stream);
14434 fprintf (stream, _("\
14435 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14436 -no-mCPU don't generate code specific to CPU.\n\
14437 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14441 show (stream, "3900", &column, &first);
14442 show (stream, "4010", &column, &first);
14443 show (stream, "4100", &column, &first);
14444 show (stream, "4650", &column, &first);
14445 fputc ('\n', stream);
14447 fprintf (stream, _("\
14448 -mips16 generate mips16 instructions\n\
14449 -no-mips16 do not generate mips16 instructions\n"));
14450 fprintf (stream, _("\
14451 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14452 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14453 -O0 remove unneeded NOPs, do not swap branches\n\
14454 -O remove unneeded NOPs and swap branches\n\
14455 -n warn about NOPs generated from macros\n\
14456 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14457 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14458 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14460 fprintf (stream, _("\
14461 -KPIC, -call_shared generate SVR4 position independent code\n\
14462 -non_shared do not generate position independent code\n\
14463 -xgot assume a 32 bit GOT\n\
14464 -mabi=ABI create ABI conformant object file for:\n"));
14468 show (stream, "32", &column, &first);
14469 show (stream, "o64", &column, &first);
14470 show (stream, "n32", &column, &first);
14471 show (stream, "64", &column, &first);
14472 show (stream, "eabi", &column, &first);
14474 fputc ('\n', stream);
14476 fprintf (stream, _("\
14477 -32 create o32 ABI object file (default)\n\
14478 -n32 create n32 ABI object file\n\
14479 -64 create 64 ABI object file\n"));