1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p : 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p : 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p : 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p : 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi = NO_ABI;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls = FALSE;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared = TRUE;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32 = -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32 = -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float = 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float = 0;
292 static struct mips_set_options mips_opts =
294 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
297 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
298 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
299 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
302 /* These variables are filled in with the masks of registers used.
303 The object format code reads them and puts them in the appropriate
305 unsigned long mips_gprmask;
306 unsigned long mips_cprmask[4];
308 /* MIPS ISA we are using for this output file. */
309 static int file_mips_isa = ISA_UNKNOWN;
311 /* True if any MIPS16 code was produced. */
312 static int file_ase_mips16;
314 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
315 || mips_opts.isa == ISA_MIPS32R2 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2)
319 /* True if any microMIPS code was produced. */
320 static int file_ase_micromips;
322 /* True if we want to create R_MIPS_JALR for jalr $25. */
324 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
326 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
327 because there's no place for any addend, the only acceptable
328 expression is a bare symbol. */
329 #define MIPS_JALR_HINT_P(EXPR) \
330 (!HAVE_IN_PLACE_ADDENDS \
331 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
334 /* True if -mips3d was passed or implied by arguments passed on the
335 command line (e.g., by -march). */
336 static int file_ase_mips3d;
338 /* True if -mdmx was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_mdmx;
342 /* True if -msmartmips was passed or implied by arguments passed on the
343 command line (e.g., by -march). */
344 static int file_ase_smartmips;
346 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
347 || mips_opts.isa == ISA_MIPS32R2)
349 /* True if -mdsp was passed or implied by arguments passed on the
350 command line (e.g., by -march). */
351 static int file_ase_dsp;
353 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
354 || mips_opts.isa == ISA_MIPS64R2 \
355 || mips_opts.micromips)
357 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
359 /* True if -mdspr2 was passed or implied by arguments passed on the
360 command line (e.g., by -march). */
361 static int file_ase_dspr2;
363 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
364 || mips_opts.isa == ISA_MIPS64R2 \
365 || mips_opts.micromips)
367 /* True if -mmt was passed or implied by arguments passed on the
368 command line (e.g., by -march). */
369 static int file_ase_mt;
371 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
372 || mips_opts.isa == ISA_MIPS64R2)
374 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
375 || mips_opts.isa == ISA_MIPS64R2 \
376 || mips_opts.micromips)
378 /* The argument of the -march= flag. The architecture we are assembling. */
379 static int file_mips_arch = CPU_UNKNOWN;
380 static const char *mips_arch_string;
382 /* The argument of the -mtune= flag. The architecture for which we
384 static int mips_tune = CPU_UNKNOWN;
385 static const char *mips_tune_string;
387 /* True when generating 32-bit code for a 64-bit processor. */
388 static int mips_32bitmode = 0;
390 /* True if the given ABI requires 32-bit registers. */
391 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
393 /* Likewise 64-bit registers. */
394 #define ABI_NEEDS_64BIT_REGS(ABI) \
396 || (ABI) == N64_ABI \
399 /* Return true if ISA supports 64 bit wide gp registers. */
400 #define ISA_HAS_64BIT_REGS(ISA) \
401 ((ISA) == ISA_MIPS3 \
402 || (ISA) == ISA_MIPS4 \
403 || (ISA) == ISA_MIPS5 \
404 || (ISA) == ISA_MIPS64 \
405 || (ISA) == ISA_MIPS64R2)
407 /* Return true if ISA supports 64 bit wide float registers. */
408 #define ISA_HAS_64BIT_FPRS(ISA) \
409 ((ISA) == ISA_MIPS3 \
410 || (ISA) == ISA_MIPS4 \
411 || (ISA) == ISA_MIPS5 \
412 || (ISA) == ISA_MIPS32R2 \
413 || (ISA) == ISA_MIPS64 \
414 || (ISA) == ISA_MIPS64R2)
416 /* Return true if ISA supports 64-bit right rotate (dror et al.)
418 #define ISA_HAS_DROR(ISA) \
419 ((ISA) == ISA_MIPS64R2 \
420 || (mips_opts.micromips \
421 && ISA_HAS_64BIT_REGS (ISA)) \
424 /* Return true if ISA supports 32-bit right rotate (ror et al.)
426 #define ISA_HAS_ROR(ISA) \
427 ((ISA) == ISA_MIPS32R2 \
428 || (ISA) == ISA_MIPS64R2 \
429 || mips_opts.ase_smartmips \
430 || mips_opts.micromips \
433 /* Return true if ISA supports single-precision floats in odd registers. */
434 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
435 ((ISA) == ISA_MIPS32 \
436 || (ISA) == ISA_MIPS32R2 \
437 || (ISA) == ISA_MIPS64 \
438 || (ISA) == ISA_MIPS64R2)
440 /* Return true if ISA supports move to/from high part of a 64-bit
441 floating-point register. */
442 #define ISA_HAS_MXHC1(ISA) \
443 ((ISA) == ISA_MIPS32R2 \
444 || (ISA) == ISA_MIPS64R2)
446 #define HAVE_32BIT_GPRS \
447 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
449 #define HAVE_32BIT_FPRS \
450 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
452 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
453 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
455 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
457 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
459 /* True if relocations are stored in-place. */
460 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
462 /* The ABI-derived address size. */
463 #define HAVE_64BIT_ADDRESSES \
464 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
465 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
467 /* The size of symbolic constants (i.e., expressions of the form
468 "SYMBOL" or "SYMBOL + OFFSET"). */
469 #define HAVE_32BIT_SYMBOLS \
470 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
471 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
473 /* Addresses are loaded in different ways, depending on the address size
474 in use. The n32 ABI Documentation also mandates the use of additions
475 with overflow checking, but existing implementations don't follow it. */
476 #define ADDRESS_ADD_INSN \
477 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
479 #define ADDRESS_ADDI_INSN \
480 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
482 #define ADDRESS_LOAD_INSN \
483 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
485 #define ADDRESS_STORE_INSN \
486 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
488 /* Return true if the given CPU supports the MIPS16 ASE. */
489 #define CPU_HAS_MIPS16(cpu) \
490 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
491 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
493 /* Return true if the given CPU supports the microMIPS ASE. */
494 #define CPU_HAS_MICROMIPS(cpu) 0
496 /* True if CPU has a dror instruction. */
497 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
499 /* True if CPU has a ror instruction. */
500 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
502 /* True if CPU is in the Octeon family */
503 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
505 /* True if CPU has seq/sne and seqi/snei instructions. */
506 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
508 /* True if CPU does not implement the all the coprocessor insns. For these
509 CPUs only those COP insns are accepted that are explicitly marked to be
510 available on the CPU. ISA membership for COP insns is ignored. */
511 #define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU))
513 /* True if mflo and mfhi can be immediately followed by instructions
514 which write to the HI and LO registers.
516 According to MIPS specifications, MIPS ISAs I, II, and III need
517 (at least) two instructions between the reads of HI/LO and
518 instructions which write them, and later ISAs do not. Contradicting
519 the MIPS specifications, some MIPS IV processor user manuals (e.g.
520 the UM for the NEC Vr5000) document needing the instructions between
521 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
522 MIPS64 and later ISAs to have the interlocks, plus any specific
523 earlier-ISA CPUs for which CPU documentation declares that the
524 instructions are really interlocked. */
525 #define hilo_interlocks \
526 (mips_opts.isa == ISA_MIPS32 \
527 || mips_opts.isa == ISA_MIPS32R2 \
528 || mips_opts.isa == ISA_MIPS64 \
529 || mips_opts.isa == ISA_MIPS64R2 \
530 || mips_opts.arch == CPU_R4010 \
531 || mips_opts.arch == CPU_R10000 \
532 || mips_opts.arch == CPU_R12000 \
533 || mips_opts.arch == CPU_R14000 \
534 || mips_opts.arch == CPU_R16000 \
535 || mips_opts.arch == CPU_RM7000 \
536 || mips_opts.arch == CPU_VR5500 \
537 || mips_opts.micromips \
540 /* Whether the processor uses hardware interlocks to protect reads
541 from the GPRs after they are loaded from memory, and thus does not
542 require nops to be inserted. This applies to instructions marked
543 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
544 level I and microMIPS mode instructions are always interlocked. */
545 #define gpr_interlocks \
546 (mips_opts.isa != ISA_MIPS1 \
547 || mips_opts.arch == CPU_R3900 \
548 || mips_opts.micromips \
551 /* Whether the processor uses hardware interlocks to avoid delays
552 required by coprocessor instructions, and thus does not require
553 nops to be inserted. This applies to instructions marked
554 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
555 between instructions marked INSN_WRITE_COND_CODE and ones marked
556 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
557 levels I, II, and III and microMIPS mode instructions are always
559 /* Itbl support may require additional care here. */
560 #define cop_interlocks \
561 ((mips_opts.isa != ISA_MIPS1 \
562 && mips_opts.isa != ISA_MIPS2 \
563 && mips_opts.isa != ISA_MIPS3) \
564 || mips_opts.arch == CPU_R4300 \
565 || mips_opts.micromips \
568 /* Whether the processor uses hardware interlocks to protect reads
569 from coprocessor registers after they are loaded from memory, and
570 thus does not require nops to be inserted. This applies to
571 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
572 requires at MIPS ISA level I and microMIPS mode instructions are
573 always interlocked. */
574 #define cop_mem_interlocks \
575 (mips_opts.isa != ISA_MIPS1 \
576 || mips_opts.micromips \
579 /* Is this a mfhi or mflo instruction? */
580 #define MF_HILO_INSN(PINFO) \
581 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
583 /* Returns true for a (non floating-point) coprocessor instruction. Reading
584 or writing the condition code is only possible on the coprocessors and
585 these insns are not marked with INSN_COP. Thus for these insns use the
586 condition-code flags. */
587 #define COP_INSN(PINFO) \
588 (PINFO != INSN_MACRO \
589 && ((PINFO) & (FP_S | FP_D)) == 0 \
590 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
592 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
593 has been selected. This implies, in particular, that addresses of text
594 labels have their LSB set. */
595 #define HAVE_CODE_COMPRESSION \
596 ((mips_opts.mips16 | mips_opts.micromips) != 0)
598 /* MIPS PIC level. */
600 enum mips_pic_level mips_pic;
602 /* 1 if we should generate 32 bit offsets from the $gp register in
603 SVR4_PIC mode. Currently has no meaning in other modes. */
604 static int mips_big_got = 0;
606 /* 1 if trap instructions should used for overflow rather than break
608 static int mips_trap = 0;
610 /* 1 if double width floating point constants should not be constructed
611 by assembling two single width halves into two single width floating
612 point registers which just happen to alias the double width destination
613 register. On some architectures this aliasing can be disabled by a bit
614 in the status register, and the setting of this bit cannot be determined
615 automatically at assemble time. */
616 static int mips_disable_float_construction;
618 /* Non-zero if any .set noreorder directives were used. */
620 static int mips_any_noreorder;
622 /* Non-zero if nops should be inserted when the register referenced in
623 an mfhi/mflo instruction is read in the next two instructions. */
624 static int mips_7000_hilo_fix;
626 /* The size of objects in the small data section. */
627 static unsigned int g_switch_value = 8;
628 /* Whether the -G option was used. */
629 static int g_switch_seen = 0;
634 /* If we can determine in advance that GP optimization won't be
635 possible, we can skip the relaxation stuff that tries to produce
636 GP-relative references. This makes delay slot optimization work
639 This function can only provide a guess, but it seems to work for
640 gcc output. It needs to guess right for gcc, otherwise gcc
641 will put what it thinks is a GP-relative instruction in a branch
644 I don't know if a fix is needed for the SVR4_PIC mode. I've only
645 fixed it for the non-PIC mode. KR 95/04/07 */
646 static int nopic_need_relax (symbolS *, int);
648 /* handle of the OPCODE hash table */
649 static struct hash_control *op_hash = NULL;
651 /* The opcode hash table we use for the mips16. */
652 static struct hash_control *mips16_op_hash = NULL;
654 /* The opcode hash table we use for the microMIPS ASE. */
655 static struct hash_control *micromips_op_hash = NULL;
657 /* This array holds the chars that always start a comment. If the
658 pre-processor is disabled, these aren't very useful */
659 const char comment_chars[] = "#";
661 /* This array holds the chars that only start a comment at the beginning of
662 a line. If the line seems to have the form '# 123 filename'
663 .line and .file directives will appear in the pre-processed output */
664 /* Note that input_file.c hand checks for '#' at the beginning of the
665 first line of the input file. This is because the compiler outputs
666 #NO_APP at the beginning of its output. */
667 /* Also note that C style comments are always supported. */
668 const char line_comment_chars[] = "#";
670 /* This array holds machine specific line separator characters. */
671 const char line_separator_chars[] = ";";
673 /* Chars that can be used to separate mant from exp in floating point nums */
674 const char EXP_CHARS[] = "eE";
676 /* Chars that mean this number is a floating point constant */
679 const char FLT_CHARS[] = "rRsSfFdDxXpP";
681 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
682 changed in read.c . Ideally it shouldn't have to know about it at all,
683 but nothing is ideal around here.
686 static char *insn_error;
688 static int auto_align = 1;
690 /* When outputting SVR4 PIC code, the assembler needs to know the
691 offset in the stack frame from which to restore the $gp register.
692 This is set by the .cprestore pseudo-op, and saved in this
694 static offsetT mips_cprestore_offset = -1;
696 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
697 more optimizations, it can use a register value instead of a memory-saved
698 offset and even an other register than $gp as global pointer. */
699 static offsetT mips_cpreturn_offset = -1;
700 static int mips_cpreturn_register = -1;
701 static int mips_gp_register = GP;
702 static int mips_gprel_offset = 0;
704 /* Whether mips_cprestore_offset has been set in the current function
705 (or whether it has already been warned about, if not). */
706 static int mips_cprestore_valid = 0;
708 /* This is the register which holds the stack frame, as set by the
709 .frame pseudo-op. This is needed to implement .cprestore. */
710 static int mips_frame_reg = SP;
712 /* Whether mips_frame_reg has been set in the current function
713 (or whether it has already been warned about, if not). */
714 static int mips_frame_reg_valid = 0;
716 /* To output NOP instructions correctly, we need to keep information
717 about the previous two instructions. */
719 /* Whether we are optimizing. The default value of 2 means to remove
720 unneeded NOPs and swap branch instructions when possible. A value
721 of 1 means to not swap branches. A value of 0 means to always
723 static int mips_optimize = 2;
725 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
726 equivalent to seeing no -g option at all. */
727 static int mips_debug = 0;
729 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
730 #define MAX_VR4130_NOPS 4
732 /* The maximum number of NOPs needed to fill delay slots. */
733 #define MAX_DELAY_NOPS 2
735 /* The maximum number of NOPs needed for any purpose. */
738 /* A list of previous instructions, with index 0 being the most recent.
739 We need to look back MAX_NOPS instructions when filling delay slots
740 or working around processor errata. We need to look back one
741 instruction further if we're thinking about using history[0] to
742 fill a branch delay slot. */
743 static struct mips_cl_insn history[1 + MAX_NOPS];
745 /* Nop instructions used by emit_nop. */
746 static struct mips_cl_insn nop_insn;
747 static struct mips_cl_insn mips16_nop_insn;
748 static struct mips_cl_insn micromips_nop16_insn;
749 static struct mips_cl_insn micromips_nop32_insn;
751 /* The appropriate nop for the current mode. */
752 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
753 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
755 /* The size of NOP_INSN in bytes. */
756 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
758 /* If this is set, it points to a frag holding nop instructions which
759 were inserted before the start of a noreorder section. If those
760 nops turn out to be unnecessary, the size of the frag can be
762 static fragS *prev_nop_frag;
764 /* The number of nop instructions we created in prev_nop_frag. */
765 static int prev_nop_frag_holds;
767 /* The number of nop instructions that we know we need in
769 static int prev_nop_frag_required;
771 /* The number of instructions we've seen since prev_nop_frag. */
772 static int prev_nop_frag_since;
774 /* For ECOFF and ELF, relocations against symbols are done in two
775 parts, with a HI relocation and a LO relocation. Each relocation
776 has only 16 bits of space to store an addend. This means that in
777 order for the linker to handle carries correctly, it must be able
778 to locate both the HI and the LO relocation. This means that the
779 relocations must appear in order in the relocation table.
781 In order to implement this, we keep track of each unmatched HI
782 relocation. We then sort them so that they immediately precede the
783 corresponding LO relocation. */
788 struct mips_hi_fixup *next;
791 /* The section this fixup is in. */
795 /* The list of unmatched HI relocs. */
797 static struct mips_hi_fixup *mips_hi_fixup_list;
799 /* The frag containing the last explicit relocation operator.
800 Null if explicit relocations have not been used. */
802 static fragS *prev_reloc_op_frag;
804 /* Map normal MIPS register numbers to mips16 register numbers. */
806 #define X ILLEGAL_REG
807 static const int mips32_to_16_reg_map[] =
809 X, X, 2, 3, 4, 5, 6, 7,
810 X, X, X, X, X, X, X, X,
811 0, 1, X, X, X, X, X, X,
812 X, X, X, X, X, X, X, X
816 /* Map mips16 register numbers to normal MIPS register numbers. */
818 static const unsigned int mips16_to_32_reg_map[] =
820 16, 17, 2, 3, 4, 5, 6, 7
823 /* Map normal MIPS register numbers to microMIPS register numbers. */
825 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
826 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
827 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
828 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
829 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
830 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
831 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
833 #define X ILLEGAL_REG
834 /* reg type h: 4, 5, 6. */
835 static const int mips32_to_micromips_reg_h_map[] =
837 X, X, X, X, 4, 5, 6, X,
838 X, X, X, X, X, X, X, X,
839 X, X, X, X, X, X, X, X,
840 X, X, X, X, X, X, X, X
843 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
844 static const int mips32_to_micromips_reg_m_map[] =
846 0, X, 2, 3, X, X, X, X,
847 X, X, X, X, X, X, X, X,
848 4, 1, 5, 6, 7, X, X, X,
849 X, X, X, X, X, X, X, X
852 /* reg type q: 0, 2-7. 17. */
853 static const int mips32_to_micromips_reg_q_map[] =
855 0, X, 2, 3, 4, 5, 6, 7,
856 X, X, X, X, X, X, X, X,
857 X, 1, X, X, X, X, X, X,
858 X, X, X, X, X, X, X, X
861 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
864 /* Map microMIPS register numbers to normal MIPS register numbers. */
866 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
867 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
868 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
869 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
870 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
871 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
873 /* The microMIPS registers with type h. */
874 static const unsigned int micromips_to_32_reg_h_map[] =
876 5, 5, 6, 4, 4, 4, 4, 4
879 /* The microMIPS registers with type i. */
880 static const unsigned int micromips_to_32_reg_i_map[] =
882 6, 7, 7, 21, 22, 5, 6, 7
885 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
887 /* The microMIPS registers with type m. */
888 static const unsigned int micromips_to_32_reg_m_map[] =
890 0, 17, 2, 3, 16, 18, 19, 20
893 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
895 /* The microMIPS registers with type q. */
896 static const unsigned int micromips_to_32_reg_q_map[] =
898 0, 17, 2, 3, 4, 5, 6, 7
901 /* microMIPS imm type B. */
902 static const int micromips_imm_b_map[] =
904 1, 4, 8, 12, 16, 20, 24, -1
907 /* microMIPS imm type C. */
908 static const int micromips_imm_c_map[] =
910 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
913 /* Classifies the kind of instructions we're interested in when
914 implementing -mfix-vr4120. */
915 enum fix_vr4120_class
923 NUM_FIX_VR4120_CLASSES
926 /* ...likewise -mfix-loongson2f-jump. */
927 static bfd_boolean mips_fix_loongson2f_jump;
929 /* ...likewise -mfix-loongson2f-nop. */
930 static bfd_boolean mips_fix_loongson2f_nop;
932 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
933 static bfd_boolean mips_fix_loongson2f;
935 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
936 there must be at least one other instruction between an instruction
937 of type X and an instruction of type Y. */
938 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
940 /* True if -mfix-vr4120 is in force. */
941 static int mips_fix_vr4120;
943 /* ...likewise -mfix-vr4130. */
944 static int mips_fix_vr4130;
946 /* ...likewise -mfix-24k. */
947 static int mips_fix_24k;
949 /* ...likewise -mfix-cn63xxp1 */
950 static bfd_boolean mips_fix_cn63xxp1;
952 /* We don't relax branches by default, since this causes us to expand
953 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
954 fail to compute the offset before expanding the macro to the most
955 efficient expansion. */
957 static int mips_relax_branch;
959 /* The expansion of many macros depends on the type of symbol that
960 they refer to. For example, when generating position-dependent code,
961 a macro that refers to a symbol may have two different expansions,
962 one which uses GP-relative addresses and one which uses absolute
963 addresses. When generating SVR4-style PIC, a macro may have
964 different expansions for local and global symbols.
966 We handle these situations by generating both sequences and putting
967 them in variant frags. In position-dependent code, the first sequence
968 will be the GP-relative one and the second sequence will be the
969 absolute one. In SVR4 PIC, the first sequence will be for global
970 symbols and the second will be for local symbols.
972 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
973 SECOND are the lengths of the two sequences in bytes. These fields
974 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
975 the subtype has the following flags:
978 Set if it has been decided that we should use the second
979 sequence instead of the first.
982 Set in the first variant frag if the macro's second implementation
983 is longer than its first. This refers to the macro as a whole,
984 not an individual relaxation.
987 Set in the first variant frag if the macro appeared in a .set nomacro
988 block and if one alternative requires a warning but the other does not.
991 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
994 RELAX_DELAY_SLOT_16BIT
995 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
998 RELAX_DELAY_SLOT_SIZE_FIRST
999 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 RELAX_DELAY_SLOT_SIZE_SECOND
1003 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1004 the macro is of the wrong size for the branch delay slot.
1006 The frag's "opcode" points to the first fixup for relaxable code.
1008 Relaxable macros are generated using a sequence such as:
1010 relax_start (SYMBOL);
1011 ... generate first expansion ...
1013 ... generate second expansion ...
1016 The code and fixups for the unwanted alternative are discarded
1017 by md_convert_frag. */
1018 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1020 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1021 #define RELAX_SECOND(X) ((X) & 0xff)
1022 #define RELAX_USE_SECOND 0x10000
1023 #define RELAX_SECOND_LONGER 0x20000
1024 #define RELAX_NOMACRO 0x40000
1025 #define RELAX_DELAY_SLOT 0x80000
1026 #define RELAX_DELAY_SLOT_16BIT 0x100000
1027 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1028 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1030 /* Branch without likely bit. If label is out of range, we turn:
1032 beq reg1, reg2, label
1042 with the following opcode replacements:
1049 bltzal <-> bgezal (with jal label instead of j label)
1051 Even though keeping the delay slot instruction in the delay slot of
1052 the branch would be more efficient, it would be very tricky to do
1053 correctly, because we'd have to introduce a variable frag *after*
1054 the delay slot instruction, and expand that instead. Let's do it
1055 the easy way for now, even if the branch-not-taken case now costs
1056 one additional instruction. Out-of-range branches are not supposed
1057 to be common, anyway.
1059 Branch likely. If label is out of range, we turn:
1061 beql reg1, reg2, label
1062 delay slot (annulled if branch not taken)
1071 delay slot (executed only if branch taken)
1074 It would be possible to generate a shorter sequence by losing the
1075 likely bit, generating something like:
1080 delay slot (executed only if branch taken)
1092 bltzall -> bgezal (with jal label instead of j label)
1093 bgezall -> bltzal (ditto)
1096 but it's not clear that it would actually improve performance. */
1097 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1098 ((relax_substateT) \
1101 | ((toofar) ? 0x20 : 0) \
1102 | ((link) ? 0x40 : 0) \
1103 | ((likely) ? 0x80 : 0) \
1104 | ((uncond) ? 0x100 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1110 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1112 /* For mips16 code, we use an entirely different form of relaxation.
1113 mips16 supports two versions of most instructions which take
1114 immediate values: a small one which takes some small value, and a
1115 larger one which takes a 16 bit value. Since branches also follow
1116 this pattern, relaxing these values is required.
1118 We can assemble both mips16 and normal MIPS code in a single
1119 object. Therefore, we need to support this type of relaxation at
1120 the same time that we support the relaxation described above. We
1121 use the high bit of the subtype field to distinguish these cases.
1123 The information we store for this type of relaxation is the
1124 argument code found in the opcode file for this relocation, whether
1125 the user explicitly requested a small or extended form, and whether
1126 the relocation is in a jump or jal delay slot. That tells us the
1127 size of the value, and how it should be stored. We also store
1128 whether the fragment is considered to be extended or not. We also
1129 store whether this is known to be a branch to a different section,
1130 whether we have tried to relax this frag yet, and whether we have
1131 ever extended a PC relative fragment because of a shift count. */
1132 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1135 | ((small) ? 0x100 : 0) \
1136 | ((ext) ? 0x200 : 0) \
1137 | ((dslot) ? 0x400 : 0) \
1138 | ((jal_dslot) ? 0x800 : 0))
1139 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1140 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1141 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1142 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1143 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1144 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1145 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1146 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1147 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1148 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1149 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1150 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1152 /* For microMIPS code, we use relaxation similar to one we use for
1153 MIPS16 code. Some instructions that take immediate values support
1154 two encodings: a small one which takes some small value, and a
1155 larger one which takes a 16 bit value. As some branches also follow
1156 this pattern, relaxing these values is required.
1158 We can assemble both microMIPS and normal MIPS code in a single
1159 object. Therefore, we need to support this type of relaxation at
1160 the same time that we support the relaxation described above. We
1161 use one of the high bits of the subtype field to distinguish these
1164 The information we store for this type of relaxation is the argument
1165 code found in the opcode file for this relocation, the register
1166 selected as the assembler temporary, whether the branch is
1167 unconditional, whether it is compact, whether it stores the link
1168 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1169 branches to a sequence of instructions is enabled, and whether the
1170 displacement of a branch is too large to fit as an immediate argument
1171 of a 16-bit and a 32-bit branch, respectively. */
1172 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1173 relax32, toofar16, toofar32) \
1176 | (((at) & 0x1f) << 8) \
1177 | ((uncond) ? 0x2000 : 0) \
1178 | ((compact) ? 0x4000 : 0) \
1179 | ((link) ? 0x8000 : 0) \
1180 | ((relax32) ? 0x10000 : 0) \
1181 | ((toofar16) ? 0x20000 : 0) \
1182 | ((toofar32) ? 0x40000 : 0))
1183 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1184 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1185 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1186 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1187 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1188 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1189 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1191 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1192 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1193 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1194 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1195 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1196 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1198 /* Is the given value a sign-extended 32-bit value? */
1199 #define IS_SEXT_32BIT_NUM(x) \
1200 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1201 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1203 /* Is the given value a sign-extended 16-bit value? */
1204 #define IS_SEXT_16BIT_NUM(x) \
1205 (((x) &~ (offsetT) 0x7fff) == 0 \
1206 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1208 /* Is the given value a sign-extended 12-bit value? */
1209 #define IS_SEXT_12BIT_NUM(x) \
1210 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1212 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1213 #define IS_ZEXT_32BIT_NUM(x) \
1214 (((x) &~ (offsetT) 0xffffffff) == 0 \
1215 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1217 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1218 VALUE << SHIFT. VALUE is evaluated exactly once. */
1219 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1220 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1221 | (((VALUE) & (MASK)) << (SHIFT)))
1223 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1225 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1226 (((STRUCT) >> (SHIFT)) & (MASK))
1228 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1229 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1231 include/opcode/mips.h specifies operand fields using the macros
1232 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1233 with "MIPS16OP" instead of "OP". */
1234 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1237 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1238 OP_MASK_##FIELD, OP_SH_##FIELD); \
1240 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1241 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1243 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1244 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1245 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1247 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1248 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1250 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1251 : EXTRACT_BITS ((INSN).insn_opcode, \
1252 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1253 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1254 EXTRACT_BITS ((INSN).insn_opcode, \
1255 MIPS16OP_MASK_##FIELD, \
1256 MIPS16OP_SH_##FIELD)
1258 /* Whether or not we are emitting a branch-likely macro. */
1259 static bfd_boolean emit_branch_likely_macro = FALSE;
1261 /* Global variables used when generating relaxable macros. See the
1262 comment above RELAX_ENCODE for more details about how relaxation
1265 /* 0 if we're not emitting a relaxable macro.
1266 1 if we're emitting the first of the two relaxation alternatives.
1267 2 if we're emitting the second alternative. */
1270 /* The first relaxable fixup in the current frag. (In other words,
1271 the first fixup that refers to relaxable code.) */
1274 /* sizes[0] says how many bytes of the first alternative are stored in
1275 the current frag. Likewise sizes[1] for the second alternative. */
1276 unsigned int sizes[2];
1278 /* The symbol on which the choice of sequence depends. */
1282 /* Global variables used to decide whether a macro needs a warning. */
1284 /* True if the macro is in a branch delay slot. */
1285 bfd_boolean delay_slot_p;
1287 /* Set to the length in bytes required if the macro is in a delay slot
1288 that requires a specific length of instruction, otherwise zero. */
1289 unsigned int delay_slot_length;
1291 /* For relaxable macros, sizes[0] is the length of the first alternative
1292 in bytes and sizes[1] is the length of the second alternative.
1293 For non-relaxable macros, both elements give the length of the
1295 unsigned int sizes[2];
1297 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1298 instruction of the first alternative in bytes and first_insn_sizes[1]
1299 is the length of the first instruction of the second alternative.
1300 For non-relaxable macros, both elements give the length of the first
1301 instruction in bytes.
1303 Set to zero if we haven't yet seen the first instruction. */
1304 unsigned int first_insn_sizes[2];
1306 /* For relaxable macros, insns[0] is the number of instructions for the
1307 first alternative and insns[1] is the number of instructions for the
1310 For non-relaxable macros, both elements give the number of
1311 instructions for the macro. */
1312 unsigned int insns[2];
1314 /* The first variant frag for this macro. */
1316 } mips_macro_warning;
1318 /* Prototypes for static functions. */
1320 #define internalError() \
1321 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1323 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1325 static void append_insn
1326 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1327 bfd_boolean expansionp);
1328 static void mips_no_prev_insn (void);
1329 static void macro_build (expressionS *, const char *, const char *, ...);
1330 static void mips16_macro_build
1331 (expressionS *, const char *, const char *, va_list *);
1332 static void load_register (int, expressionS *, int);
1333 static void macro_start (void);
1334 static void macro_end (void);
1335 static void macro (struct mips_cl_insn * ip);
1336 static void mips16_macro (struct mips_cl_insn * ip);
1337 static void mips_ip (char *str, struct mips_cl_insn * ip);
1338 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1339 static void mips16_immed
1340 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1341 unsigned long *, bfd_boolean *, unsigned short *);
1342 static size_t my_getSmallExpression
1343 (expressionS *, bfd_reloc_code_real_type *, char *);
1344 static void my_getExpression (expressionS *, char *);
1345 static void s_align (int);
1346 static void s_change_sec (int);
1347 static void s_change_section (int);
1348 static void s_cons (int);
1349 static void s_float_cons (int);
1350 static void s_mips_globl (int);
1351 static void s_option (int);
1352 static void s_mipsset (int);
1353 static void s_abicalls (int);
1354 static void s_cpload (int);
1355 static void s_cpsetup (int);
1356 static void s_cplocal (int);
1357 static void s_cprestore (int);
1358 static void s_cpreturn (int);
1359 static void s_dtprelword (int);
1360 static void s_dtpreldword (int);
1361 static void s_tprelword (int);
1362 static void s_tpreldword (int);
1363 static void s_gpvalue (int);
1364 static void s_gpword (int);
1365 static void s_gpdword (int);
1366 static void s_cpadd (int);
1367 static void s_insn (int);
1368 static void md_obj_begin (void);
1369 static void md_obj_end (void);
1370 static void s_mips_ent (int);
1371 static void s_mips_end (int);
1372 static void s_mips_frame (int);
1373 static void s_mips_mask (int reg_type);
1374 static void s_mips_stab (int);
1375 static void s_mips_weakext (int);
1376 static void s_mips_file (int);
1377 static void s_mips_loc (int);
1378 static bfd_boolean pic_need_relax (symbolS *, asection *);
1379 static int relaxed_branch_length (fragS *, asection *, int);
1380 static int validate_mips_insn (const struct mips_opcode *);
1381 static int validate_micromips_insn (const struct mips_opcode *);
1382 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1383 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1385 /* Table and functions used to map between CPU/ISA names, and
1386 ISA levels, and CPU numbers. */
1388 struct mips_cpu_info
1390 const char *name; /* CPU or ISA name. */
1391 int flags; /* ASEs available, or ISA flag. */
1392 int isa; /* ISA level. */
1393 int cpu; /* CPU number (default CPU if ISA). */
1396 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1397 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1398 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1399 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1400 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1401 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1402 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1403 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1405 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1406 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1407 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1411 The following pseudo-ops from the Kane and Heinrich MIPS book
1412 should be defined here, but are currently unsupported: .alias,
1413 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1415 The following pseudo-ops from the Kane and Heinrich MIPS book are
1416 specific to the type of debugging information being generated, and
1417 should be defined by the object format: .aent, .begin, .bend,
1418 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1421 The following pseudo-ops from the Kane and Heinrich MIPS book are
1422 not MIPS CPU specific, but are also not specific to the object file
1423 format. This file is probably the best place to define them, but
1424 they are not currently supported: .asm0, .endr, .lab, .struct. */
1426 static const pseudo_typeS mips_pseudo_table[] =
1428 /* MIPS specific pseudo-ops. */
1429 {"option", s_option, 0},
1430 {"set", s_mipsset, 0},
1431 {"rdata", s_change_sec, 'r'},
1432 {"sdata", s_change_sec, 's'},
1433 {"livereg", s_ignore, 0},
1434 {"abicalls", s_abicalls, 0},
1435 {"cpload", s_cpload, 0},
1436 {"cpsetup", s_cpsetup, 0},
1437 {"cplocal", s_cplocal, 0},
1438 {"cprestore", s_cprestore, 0},
1439 {"cpreturn", s_cpreturn, 0},
1440 {"dtprelword", s_dtprelword, 0},
1441 {"dtpreldword", s_dtpreldword, 0},
1442 {"tprelword", s_tprelword, 0},
1443 {"tpreldword", s_tpreldword, 0},
1444 {"gpvalue", s_gpvalue, 0},
1445 {"gpword", s_gpword, 0},
1446 {"gpdword", s_gpdword, 0},
1447 {"cpadd", s_cpadd, 0},
1448 {"insn", s_insn, 0},
1450 /* Relatively generic pseudo-ops that happen to be used on MIPS
1452 {"asciiz", stringer, 8 + 1},
1453 {"bss", s_change_sec, 'b'},
1455 {"half", s_cons, 1},
1456 {"dword", s_cons, 3},
1457 {"weakext", s_mips_weakext, 0},
1458 {"origin", s_org, 0},
1459 {"repeat", s_rept, 0},
1461 /* For MIPS this is non-standard, but we define it for consistency. */
1462 {"sbss", s_change_sec, 'B'},
1464 /* These pseudo-ops are defined in read.c, but must be overridden
1465 here for one reason or another. */
1466 {"align", s_align, 0},
1467 {"byte", s_cons, 0},
1468 {"data", s_change_sec, 'd'},
1469 {"double", s_float_cons, 'd'},
1470 {"float", s_float_cons, 'f'},
1471 {"globl", s_mips_globl, 0},
1472 {"global", s_mips_globl, 0},
1473 {"hword", s_cons, 1},
1475 {"long", s_cons, 2},
1476 {"octa", s_cons, 4},
1477 {"quad", s_cons, 3},
1478 {"section", s_change_section, 0},
1479 {"short", s_cons, 1},
1480 {"single", s_float_cons, 'f'},
1481 {"stabn", s_mips_stab, 'n'},
1482 {"text", s_change_sec, 't'},
1483 {"word", s_cons, 2},
1485 { "extern", ecoff_directive_extern, 0},
1490 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1492 /* These pseudo-ops should be defined by the object file format.
1493 However, a.out doesn't support them, so we have versions here. */
1494 {"aent", s_mips_ent, 1},
1495 {"bgnb", s_ignore, 0},
1496 {"end", s_mips_end, 0},
1497 {"endb", s_ignore, 0},
1498 {"ent", s_mips_ent, 0},
1499 {"file", s_mips_file, 0},
1500 {"fmask", s_mips_mask, 'F'},
1501 {"frame", s_mips_frame, 0},
1502 {"loc", s_mips_loc, 0},
1503 {"mask", s_mips_mask, 'R'},
1504 {"verstamp", s_ignore, 0},
1508 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1509 purpose of the `.dc.a' internal pseudo-op. */
1512 mips_address_bytes (void)
1514 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1517 extern void pop_insert (const pseudo_typeS *);
1520 mips_pop_insert (void)
1522 pop_insert (mips_pseudo_table);
1523 if (! ECOFF_DEBUGGING)
1524 pop_insert (mips_nonecoff_pseudo_table);
1527 /* Symbols labelling the current insn. */
1529 struct insn_label_list
1531 struct insn_label_list *next;
1535 static struct insn_label_list *free_insn_labels;
1536 #define label_list tc_segment_info_data.labels
1538 static void mips_clear_insn_labels (void);
1539 static void mips_mark_labels (void);
1540 static void mips_compressed_mark_labels (void);
1543 mips_clear_insn_labels (void)
1545 register struct insn_label_list **pl;
1546 segment_info_type *si;
1550 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1553 si = seg_info (now_seg);
1554 *pl = si->label_list;
1555 si->label_list = NULL;
1559 /* Mark instruction labels in MIPS16/microMIPS mode. */
1562 mips_mark_labels (void)
1564 if (HAVE_CODE_COMPRESSION)
1565 mips_compressed_mark_labels ();
1568 static char *expr_end;
1570 /* Expressions which appear in instructions. These are set by
1573 static expressionS imm_expr;
1574 static expressionS imm2_expr;
1575 static expressionS offset_expr;
1577 /* Relocs associated with imm_expr and offset_expr. */
1579 static bfd_reloc_code_real_type imm_reloc[3]
1580 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1581 static bfd_reloc_code_real_type offset_reloc[3]
1582 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1584 /* This is set to the resulting size of the instruction to be produced
1585 by mips16_ip if an explicit extension is used or by mips_ip if an
1586 explicit size is supplied. */
1588 static unsigned int forced_insn_length;
1591 /* The pdr segment for per procedure frame/regmask info. Not used for
1594 static segT pdr_seg;
1597 /* The default target format to use. */
1599 #if defined (TE_FreeBSD)
1600 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1601 #elif defined (TE_TMIPS)
1602 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1604 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1608 mips_target_format (void)
1610 switch (OUTPUT_FLAVOR)
1612 case bfd_target_ecoff_flavour:
1613 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1614 case bfd_target_coff_flavour:
1616 case bfd_target_elf_flavour:
1618 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1619 return (target_big_endian
1620 ? "elf32-bigmips-vxworks"
1621 : "elf32-littlemips-vxworks");
1623 return (target_big_endian
1624 ? (HAVE_64BIT_OBJECTS
1625 ? ELF_TARGET ("elf64-", "big")
1627 ? ELF_TARGET ("elf32-n", "big")
1628 : ELF_TARGET ("elf32-", "big")))
1629 : (HAVE_64BIT_OBJECTS
1630 ? ELF_TARGET ("elf64-", "little")
1632 ? ELF_TARGET ("elf32-n", "little")
1633 : ELF_TARGET ("elf32-", "little"))));
1640 /* Return the length of a microMIPS instruction in bytes. If bits of
1641 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1642 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1643 major opcode) will require further modifications to the opcode
1646 static inline unsigned int
1647 micromips_insn_length (const struct mips_opcode *mo)
1649 return (mo->mask >> 16) == 0 ? 2 : 4;
1652 /* Return the length of instruction INSN. */
1654 static inline unsigned int
1655 insn_length (const struct mips_cl_insn *insn)
1657 if (mips_opts.micromips)
1658 return micromips_insn_length (insn->insn_mo);
1659 else if (mips_opts.mips16)
1660 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1665 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1668 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1673 insn->use_extend = FALSE;
1675 insn->insn_opcode = mo->match;
1678 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1679 insn->fixp[i] = NULL;
1680 insn->fixed_p = (mips_opts.noreorder > 0);
1681 insn->noreorder_p = (mips_opts.noreorder > 0);
1682 insn->mips16_absolute_jump_p = 0;
1683 insn->complete_p = 0;
1686 /* Record the current MIPS16/microMIPS mode in now_seg. */
1689 mips_record_compressed_mode (void)
1691 segment_info_type *si;
1693 si = seg_info (now_seg);
1694 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1695 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1696 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1697 si->tc_segment_info_data.micromips = mips_opts.micromips;
1700 /* Install INSN at the location specified by its "frag" and "where" fields. */
1703 install_insn (const struct mips_cl_insn *insn)
1705 char *f = insn->frag->fr_literal + insn->where;
1706 if (!HAVE_CODE_COMPRESSION)
1707 md_number_to_chars (f, insn->insn_opcode, 4);
1708 else if (mips_opts.micromips)
1710 unsigned int length = insn_length (insn);
1712 md_number_to_chars (f, insn->insn_opcode, 2);
1713 else if (length == 4)
1715 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1717 md_number_to_chars (f, insn->insn_opcode & 0xffff, 2);
1720 as_bad (_("48-bit microMIPS instructions are not supported"));
1722 else if (insn->mips16_absolute_jump_p)
1724 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1725 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1729 if (insn->use_extend)
1731 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1734 md_number_to_chars (f, insn->insn_opcode, 2);
1736 mips_record_compressed_mode ();
1739 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1740 and install the opcode in the new location. */
1743 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1748 insn->where = where;
1749 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1750 if (insn->fixp[i] != NULL)
1752 insn->fixp[i]->fx_frag = frag;
1753 insn->fixp[i]->fx_where = where;
1755 install_insn (insn);
1758 /* Add INSN to the end of the output. */
1761 add_fixed_insn (struct mips_cl_insn *insn)
1763 char *f = frag_more (insn_length (insn));
1764 move_insn (insn, frag_now, f - frag_now->fr_literal);
1767 /* Start a variant frag and move INSN to the start of the variant part,
1768 marking it as fixed. The other arguments are as for frag_var. */
1771 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1772 relax_substateT subtype, symbolS *symbol, offsetT offset)
1774 frag_grow (max_chars);
1775 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1777 frag_var (rs_machine_dependent, max_chars, var,
1778 subtype, symbol, offset, NULL);
1781 /* Insert N copies of INSN into the history buffer, starting at
1782 position FIRST. Neither FIRST nor N need to be clipped. */
1785 insert_into_history (unsigned int first, unsigned int n,
1786 const struct mips_cl_insn *insn)
1788 if (mips_relax.sequence != 2)
1792 for (i = ARRAY_SIZE (history); i-- > first;)
1794 history[i] = history[i - n];
1800 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1801 the idea is to make it obvious at a glance that each errata is
1805 init_vr4120_conflicts (void)
1807 #define CONFLICT(FIRST, SECOND) \
1808 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1810 /* Errata 21 - [D]DIV[U] after [D]MACC */
1811 CONFLICT (MACC, DIV);
1812 CONFLICT (DMACC, DIV);
1814 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1815 CONFLICT (DMULT, DMULT);
1816 CONFLICT (DMULT, DMACC);
1817 CONFLICT (DMACC, DMULT);
1818 CONFLICT (DMACC, DMACC);
1820 /* Errata 24 - MT{LO,HI} after [D]MACC */
1821 CONFLICT (MACC, MTHILO);
1822 CONFLICT (DMACC, MTHILO);
1824 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1825 instruction is executed immediately after a MACC or DMACC
1826 instruction, the result of [either instruction] is incorrect." */
1827 CONFLICT (MACC, MULT);
1828 CONFLICT (MACC, DMULT);
1829 CONFLICT (DMACC, MULT);
1830 CONFLICT (DMACC, DMULT);
1832 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1833 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1834 DDIV or DDIVU instruction, the result of the MACC or
1835 DMACC instruction is incorrect.". */
1836 CONFLICT (DMULT, MACC);
1837 CONFLICT (DMULT, DMACC);
1838 CONFLICT (DIV, MACC);
1839 CONFLICT (DIV, DMACC);
1849 #define RTYPE_MASK 0x1ff00
1850 #define RTYPE_NUM 0x00100
1851 #define RTYPE_FPU 0x00200
1852 #define RTYPE_FCC 0x00400
1853 #define RTYPE_VEC 0x00800
1854 #define RTYPE_GP 0x01000
1855 #define RTYPE_CP0 0x02000
1856 #define RTYPE_PC 0x04000
1857 #define RTYPE_ACC 0x08000
1858 #define RTYPE_CCC 0x10000
1859 #define RNUM_MASK 0x000ff
1860 #define RWARN 0x80000
1862 #define GENERIC_REGISTER_NUMBERS \
1863 {"$0", RTYPE_NUM | 0}, \
1864 {"$1", RTYPE_NUM | 1}, \
1865 {"$2", RTYPE_NUM | 2}, \
1866 {"$3", RTYPE_NUM | 3}, \
1867 {"$4", RTYPE_NUM | 4}, \
1868 {"$5", RTYPE_NUM | 5}, \
1869 {"$6", RTYPE_NUM | 6}, \
1870 {"$7", RTYPE_NUM | 7}, \
1871 {"$8", RTYPE_NUM | 8}, \
1872 {"$9", RTYPE_NUM | 9}, \
1873 {"$10", RTYPE_NUM | 10}, \
1874 {"$11", RTYPE_NUM | 11}, \
1875 {"$12", RTYPE_NUM | 12}, \
1876 {"$13", RTYPE_NUM | 13}, \
1877 {"$14", RTYPE_NUM | 14}, \
1878 {"$15", RTYPE_NUM | 15}, \
1879 {"$16", RTYPE_NUM | 16}, \
1880 {"$17", RTYPE_NUM | 17}, \
1881 {"$18", RTYPE_NUM | 18}, \
1882 {"$19", RTYPE_NUM | 19}, \
1883 {"$20", RTYPE_NUM | 20}, \
1884 {"$21", RTYPE_NUM | 21}, \
1885 {"$22", RTYPE_NUM | 22}, \
1886 {"$23", RTYPE_NUM | 23}, \
1887 {"$24", RTYPE_NUM | 24}, \
1888 {"$25", RTYPE_NUM | 25}, \
1889 {"$26", RTYPE_NUM | 26}, \
1890 {"$27", RTYPE_NUM | 27}, \
1891 {"$28", RTYPE_NUM | 28}, \
1892 {"$29", RTYPE_NUM | 29}, \
1893 {"$30", RTYPE_NUM | 30}, \
1894 {"$31", RTYPE_NUM | 31}
1896 #define FPU_REGISTER_NAMES \
1897 {"$f0", RTYPE_FPU | 0}, \
1898 {"$f1", RTYPE_FPU | 1}, \
1899 {"$f2", RTYPE_FPU | 2}, \
1900 {"$f3", RTYPE_FPU | 3}, \
1901 {"$f4", RTYPE_FPU | 4}, \
1902 {"$f5", RTYPE_FPU | 5}, \
1903 {"$f6", RTYPE_FPU | 6}, \
1904 {"$f7", RTYPE_FPU | 7}, \
1905 {"$f8", RTYPE_FPU | 8}, \
1906 {"$f9", RTYPE_FPU | 9}, \
1907 {"$f10", RTYPE_FPU | 10}, \
1908 {"$f11", RTYPE_FPU | 11}, \
1909 {"$f12", RTYPE_FPU | 12}, \
1910 {"$f13", RTYPE_FPU | 13}, \
1911 {"$f14", RTYPE_FPU | 14}, \
1912 {"$f15", RTYPE_FPU | 15}, \
1913 {"$f16", RTYPE_FPU | 16}, \
1914 {"$f17", RTYPE_FPU | 17}, \
1915 {"$f18", RTYPE_FPU | 18}, \
1916 {"$f19", RTYPE_FPU | 19}, \
1917 {"$f20", RTYPE_FPU | 20}, \
1918 {"$f21", RTYPE_FPU | 21}, \
1919 {"$f22", RTYPE_FPU | 22}, \
1920 {"$f23", RTYPE_FPU | 23}, \
1921 {"$f24", RTYPE_FPU | 24}, \
1922 {"$f25", RTYPE_FPU | 25}, \
1923 {"$f26", RTYPE_FPU | 26}, \
1924 {"$f27", RTYPE_FPU | 27}, \
1925 {"$f28", RTYPE_FPU | 28}, \
1926 {"$f29", RTYPE_FPU | 29}, \
1927 {"$f30", RTYPE_FPU | 30}, \
1928 {"$f31", RTYPE_FPU | 31}
1930 #define FPU_CONDITION_CODE_NAMES \
1931 {"$fcc0", RTYPE_FCC | 0}, \
1932 {"$fcc1", RTYPE_FCC | 1}, \
1933 {"$fcc2", RTYPE_FCC | 2}, \
1934 {"$fcc3", RTYPE_FCC | 3}, \
1935 {"$fcc4", RTYPE_FCC | 4}, \
1936 {"$fcc5", RTYPE_FCC | 5}, \
1937 {"$fcc6", RTYPE_FCC | 6}, \
1938 {"$fcc7", RTYPE_FCC | 7}
1940 #define COPROC_CONDITION_CODE_NAMES \
1941 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1942 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1943 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1944 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1945 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1946 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1947 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1948 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1950 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1951 {"$a4", RTYPE_GP | 8}, \
1952 {"$a5", RTYPE_GP | 9}, \
1953 {"$a6", RTYPE_GP | 10}, \
1954 {"$a7", RTYPE_GP | 11}, \
1955 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1956 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1957 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1958 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1959 {"$t0", RTYPE_GP | 12}, \
1960 {"$t1", RTYPE_GP | 13}, \
1961 {"$t2", RTYPE_GP | 14}, \
1962 {"$t3", RTYPE_GP | 15}
1964 #define O32_SYMBOLIC_REGISTER_NAMES \
1965 {"$t0", RTYPE_GP | 8}, \
1966 {"$t1", RTYPE_GP | 9}, \
1967 {"$t2", RTYPE_GP | 10}, \
1968 {"$t3", RTYPE_GP | 11}, \
1969 {"$t4", RTYPE_GP | 12}, \
1970 {"$t5", RTYPE_GP | 13}, \
1971 {"$t6", RTYPE_GP | 14}, \
1972 {"$t7", RTYPE_GP | 15}, \
1973 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1974 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1975 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1976 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1978 /* Remaining symbolic register names */
1979 #define SYMBOLIC_REGISTER_NAMES \
1980 {"$zero", RTYPE_GP | 0}, \
1981 {"$at", RTYPE_GP | 1}, \
1982 {"$AT", RTYPE_GP | 1}, \
1983 {"$v0", RTYPE_GP | 2}, \
1984 {"$v1", RTYPE_GP | 3}, \
1985 {"$a0", RTYPE_GP | 4}, \
1986 {"$a1", RTYPE_GP | 5}, \
1987 {"$a2", RTYPE_GP | 6}, \
1988 {"$a3", RTYPE_GP | 7}, \
1989 {"$s0", RTYPE_GP | 16}, \
1990 {"$s1", RTYPE_GP | 17}, \
1991 {"$s2", RTYPE_GP | 18}, \
1992 {"$s3", RTYPE_GP | 19}, \
1993 {"$s4", RTYPE_GP | 20}, \
1994 {"$s5", RTYPE_GP | 21}, \
1995 {"$s6", RTYPE_GP | 22}, \
1996 {"$s7", RTYPE_GP | 23}, \
1997 {"$t8", RTYPE_GP | 24}, \
1998 {"$t9", RTYPE_GP | 25}, \
1999 {"$k0", RTYPE_GP | 26}, \
2000 {"$kt0", RTYPE_GP | 26}, \
2001 {"$k1", RTYPE_GP | 27}, \
2002 {"$kt1", RTYPE_GP | 27}, \
2003 {"$gp", RTYPE_GP | 28}, \
2004 {"$sp", RTYPE_GP | 29}, \
2005 {"$s8", RTYPE_GP | 30}, \
2006 {"$fp", RTYPE_GP | 30}, \
2007 {"$ra", RTYPE_GP | 31}
2009 #define MIPS16_SPECIAL_REGISTER_NAMES \
2010 {"$pc", RTYPE_PC | 0}
2012 #define MDMX_VECTOR_REGISTER_NAMES \
2013 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2014 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2015 {"$v2", RTYPE_VEC | 2}, \
2016 {"$v3", RTYPE_VEC | 3}, \
2017 {"$v4", RTYPE_VEC | 4}, \
2018 {"$v5", RTYPE_VEC | 5}, \
2019 {"$v6", RTYPE_VEC | 6}, \
2020 {"$v7", RTYPE_VEC | 7}, \
2021 {"$v8", RTYPE_VEC | 8}, \
2022 {"$v9", RTYPE_VEC | 9}, \
2023 {"$v10", RTYPE_VEC | 10}, \
2024 {"$v11", RTYPE_VEC | 11}, \
2025 {"$v12", RTYPE_VEC | 12}, \
2026 {"$v13", RTYPE_VEC | 13}, \
2027 {"$v14", RTYPE_VEC | 14}, \
2028 {"$v15", RTYPE_VEC | 15}, \
2029 {"$v16", RTYPE_VEC | 16}, \
2030 {"$v17", RTYPE_VEC | 17}, \
2031 {"$v18", RTYPE_VEC | 18}, \
2032 {"$v19", RTYPE_VEC | 19}, \
2033 {"$v20", RTYPE_VEC | 20}, \
2034 {"$v21", RTYPE_VEC | 21}, \
2035 {"$v22", RTYPE_VEC | 22}, \
2036 {"$v23", RTYPE_VEC | 23}, \
2037 {"$v24", RTYPE_VEC | 24}, \
2038 {"$v25", RTYPE_VEC | 25}, \
2039 {"$v26", RTYPE_VEC | 26}, \
2040 {"$v27", RTYPE_VEC | 27}, \
2041 {"$v28", RTYPE_VEC | 28}, \
2042 {"$v29", RTYPE_VEC | 29}, \
2043 {"$v30", RTYPE_VEC | 30}, \
2044 {"$v31", RTYPE_VEC | 31}
2046 #define MIPS_DSP_ACCUMULATOR_NAMES \
2047 {"$ac0", RTYPE_ACC | 0}, \
2048 {"$ac1", RTYPE_ACC | 1}, \
2049 {"$ac2", RTYPE_ACC | 2}, \
2050 {"$ac3", RTYPE_ACC | 3}
2052 static const struct regname reg_names[] = {
2053 GENERIC_REGISTER_NUMBERS,
2055 FPU_CONDITION_CODE_NAMES,
2056 COPROC_CONDITION_CODE_NAMES,
2058 /* The $txx registers depends on the abi,
2059 these will be added later into the symbol table from
2060 one of the tables below once mips_abi is set after
2061 parsing of arguments from the command line. */
2062 SYMBOLIC_REGISTER_NAMES,
2064 MIPS16_SPECIAL_REGISTER_NAMES,
2065 MDMX_VECTOR_REGISTER_NAMES,
2066 MIPS_DSP_ACCUMULATOR_NAMES,
2070 static const struct regname reg_names_o32[] = {
2071 O32_SYMBOLIC_REGISTER_NAMES,
2075 static const struct regname reg_names_n32n64[] = {
2076 N32N64_SYMBOLIC_REGISTER_NAMES,
2080 /* Check if S points at a valid register specifier according to TYPES.
2081 If so, then return 1, advance S to consume the specifier and store
2082 the register's number in REGNOP, otherwise return 0. */
2085 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2092 /* Find end of name. */
2094 if (is_name_beginner (*e))
2096 while (is_part_of_name (*e))
2099 /* Terminate name. */
2103 /* Look for a register symbol. */
2104 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2106 int r = S_GET_VALUE (symbolP);
2108 reg = r & RNUM_MASK;
2109 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2110 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2111 reg = (r & RNUM_MASK) - 2;
2113 /* Else see if this is a register defined in an itbl entry. */
2114 else if ((types & RTYPE_GP) && itbl_have_entries)
2121 if (itbl_get_reg_val (n, &r))
2122 reg = r & RNUM_MASK;
2125 /* Advance to next token if a register was recognised. */
2128 else if (types & RWARN)
2129 as_warn (_("Unrecognized register name `%s'"), *s);
2137 /* Check if S points at a valid register list according to TYPES.
2138 If so, then return 1, advance S to consume the list and store
2139 the registers present on the list as a bitmask of ones in REGLISTP,
2140 otherwise return 0. A valid list comprises a comma-separated
2141 enumeration of valid single registers and/or dash-separated
2142 contiguous register ranges as determined by their numbers.
2144 As a special exception if one of s0-s7 registers is specified as
2145 the range's lower delimiter and s8 (fp) is its upper one, then no
2146 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2147 are selected; they have to be listed separately if needed. */
2150 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2152 unsigned int reglist = 0;
2153 unsigned int lastregno;
2154 bfd_boolean ok = TRUE;
2155 unsigned int regmask;
2156 char *s_endlist = *s;
2160 while (reg_lookup (s, types, ®no))
2166 ok = reg_lookup (s, types, &lastregno);
2167 if (ok && lastregno < regno)
2173 if (lastregno == FP && regno >= S0 && regno <= S7)
2178 regmask = 1 << lastregno;
2179 regmask = (regmask << 1) - 1;
2180 regmask ^= (1 << regno) - 1;
2194 *reglistp = reglist;
2195 return ok && reglist != 0;
2198 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2199 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2202 is_opcode_valid (const struct mips_opcode *mo)
2204 int isa = mips_opts.isa;
2207 if (mips_opts.ase_mdmx)
2209 if (mips_opts.ase_dsp)
2211 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2213 if (mips_opts.ase_dspr2)
2215 if (mips_opts.ase_mt)
2217 if (mips_opts.ase_mips3d)
2219 if (mips_opts.ase_smartmips)
2220 isa |= INSN_SMARTMIPS;
2221 if (mips_opts.ase_mcu)
2224 /* Don't accept instructions based on the ISA if the CPU does not implement
2225 all the coprocessor insns. */
2226 if (NO_ISA_COP (mips_opts.arch)
2227 && COP_INSN (mo->pinfo))
2230 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
2233 /* Check whether the instruction or macro requires single-precision or
2234 double-precision floating-point support. Note that this information is
2235 stored differently in the opcode table for insns and macros. */
2236 if (mo->pinfo == INSN_MACRO)
2238 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2239 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2243 fp_s = mo->pinfo & FP_S;
2244 fp_d = mo->pinfo & FP_D;
2247 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2250 if (fp_s && mips_opts.soft_float)
2256 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2257 selected ISA and architecture. */
2260 is_opcode_valid_16 (const struct mips_opcode *mo)
2262 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
2265 /* Return TRUE if the size of the microMIPS opcode MO matches one
2266 explicitly requested. Always TRUE in the standard MIPS mode. */
2269 is_size_valid (const struct mips_opcode *mo)
2271 if (!mips_opts.micromips)
2274 if (!forced_insn_length)
2276 if (mo->pinfo == INSN_MACRO)
2278 return forced_insn_length == micromips_insn_length (mo);
2281 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2282 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2285 is_delay_slot_valid (const struct mips_opcode *mo)
2287 if (!mips_opts.micromips)
2290 if (mo->pinfo == INSN_MACRO)
2292 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2293 && micromips_insn_length (mo) != 4)
2295 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2296 && micromips_insn_length (mo) != 2)
2302 /* This function is called once, at assembler startup time. It should set up
2303 all the tables, etc. that the MD part of the assembler will need. */
2308 const char *retval = NULL;
2312 if (mips_pic != NO_PIC)
2314 if (g_switch_seen && g_switch_value != 0)
2315 as_bad (_("-G may not be used in position-independent code"));
2319 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2320 as_warn (_("Could not set architecture and machine"));
2322 op_hash = hash_new ();
2324 for (i = 0; i < NUMOPCODES;)
2326 const char *name = mips_opcodes[i].name;
2328 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2331 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2332 mips_opcodes[i].name, retval);
2333 /* Probably a memory allocation problem? Give up now. */
2334 as_fatal (_("Broken assembler. No assembly attempted."));
2338 if (mips_opcodes[i].pinfo != INSN_MACRO)
2340 if (!validate_mips_insn (&mips_opcodes[i]))
2342 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2344 create_insn (&nop_insn, mips_opcodes + i);
2345 if (mips_fix_loongson2f_nop)
2346 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2347 nop_insn.fixed_p = 1;
2352 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2355 mips16_op_hash = hash_new ();
2358 while (i < bfd_mips16_num_opcodes)
2360 const char *name = mips16_opcodes[i].name;
2362 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2364 as_fatal (_("internal: can't hash `%s': %s"),
2365 mips16_opcodes[i].name, retval);
2368 if (mips16_opcodes[i].pinfo != INSN_MACRO
2369 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2370 != mips16_opcodes[i].match))
2372 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2373 mips16_opcodes[i].name, mips16_opcodes[i].args);
2376 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2378 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2379 mips16_nop_insn.fixed_p = 1;
2383 while (i < bfd_mips16_num_opcodes
2384 && strcmp (mips16_opcodes[i].name, name) == 0);
2387 micromips_op_hash = hash_new ();
2390 while (i < bfd_micromips_num_opcodes)
2392 const char *name = micromips_opcodes[i].name;
2394 retval = hash_insert (micromips_op_hash, name,
2395 (void *) µmips_opcodes[i]);
2397 as_fatal (_("internal: can't hash `%s': %s"),
2398 micromips_opcodes[i].name, retval);
2400 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2402 struct mips_cl_insn *micromips_nop_insn;
2404 if (!validate_micromips_insn (µmips_opcodes[i]))
2407 if (micromips_insn_length (micromips_opcodes + i) == 2)
2408 micromips_nop_insn = µmips_nop16_insn;
2409 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2410 micromips_nop_insn = µmips_nop32_insn;
2414 if (micromips_nop_insn->insn_mo == NULL
2415 && strcmp (name, "nop") == 0)
2417 create_insn (micromips_nop_insn, micromips_opcodes + i);
2418 micromips_nop_insn->fixed_p = 1;
2421 while (++i < bfd_micromips_num_opcodes
2422 && strcmp (micromips_opcodes[i].name, name) == 0);
2426 as_fatal (_("Broken assembler. No assembly attempted."));
2428 /* We add all the general register names to the symbol table. This
2429 helps us detect invalid uses of them. */
2430 for (i = 0; reg_names[i].name; i++)
2431 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2432 reg_names[i].num, /* & RNUM_MASK, */
2433 &zero_address_frag));
2435 for (i = 0; reg_names_n32n64[i].name; i++)
2436 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2437 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2438 &zero_address_frag));
2440 for (i = 0; reg_names_o32[i].name; i++)
2441 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2442 reg_names_o32[i].num, /* & RNUM_MASK, */
2443 &zero_address_frag));
2445 mips_no_prev_insn ();
2448 mips_cprmask[0] = 0;
2449 mips_cprmask[1] = 0;
2450 mips_cprmask[2] = 0;
2451 mips_cprmask[3] = 0;
2453 /* set the default alignment for the text section (2**2) */
2454 record_alignment (text_section, 2);
2456 bfd_set_gp_size (stdoutput, g_switch_value);
2461 /* On a native system other than VxWorks, sections must be aligned
2462 to 16 byte boundaries. When configured for an embedded ELF
2463 target, we don't bother. */
2464 if (strncmp (TARGET_OS, "elf", 3) != 0
2465 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2467 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2468 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2469 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2472 /* Create a .reginfo section for register masks and a .mdebug
2473 section for debugging information. */
2481 subseg = now_subseg;
2483 /* The ABI says this section should be loaded so that the
2484 running program can access it. However, we don't load it
2485 if we are configured for an embedded target */
2486 flags = SEC_READONLY | SEC_DATA;
2487 if (strncmp (TARGET_OS, "elf", 3) != 0)
2488 flags |= SEC_ALLOC | SEC_LOAD;
2490 if (mips_abi != N64_ABI)
2492 sec = subseg_new (".reginfo", (subsegT) 0);
2494 bfd_set_section_flags (stdoutput, sec, flags);
2495 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2497 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2501 /* The 64-bit ABI uses a .MIPS.options section rather than
2502 .reginfo section. */
2503 sec = subseg_new (".MIPS.options", (subsegT) 0);
2504 bfd_set_section_flags (stdoutput, sec, flags);
2505 bfd_set_section_alignment (stdoutput, sec, 3);
2507 /* Set up the option header. */
2509 Elf_Internal_Options opthdr;
2512 opthdr.kind = ODK_REGINFO;
2513 opthdr.size = (sizeof (Elf_External_Options)
2514 + sizeof (Elf64_External_RegInfo));
2517 f = frag_more (sizeof (Elf_External_Options));
2518 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2519 (Elf_External_Options *) f);
2521 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2525 if (ECOFF_DEBUGGING)
2527 sec = subseg_new (".mdebug", (subsegT) 0);
2528 (void) bfd_set_section_flags (stdoutput, sec,
2529 SEC_HAS_CONTENTS | SEC_READONLY);
2530 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2532 else if (mips_flag_pdr)
2534 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2535 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2536 SEC_READONLY | SEC_RELOC
2538 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2541 subseg_set (seg, subseg);
2544 #endif /* OBJ_ELF */
2546 if (! ECOFF_DEBUGGING)
2549 if (mips_fix_vr4120)
2550 init_vr4120_conflicts ();
2556 mips_emit_delays ();
2557 if (! ECOFF_DEBUGGING)
2562 md_assemble (char *str)
2564 struct mips_cl_insn insn;
2565 bfd_reloc_code_real_type unused_reloc[3]
2566 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2568 imm_expr.X_op = O_absent;
2569 imm2_expr.X_op = O_absent;
2570 offset_expr.X_op = O_absent;
2571 imm_reloc[0] = BFD_RELOC_UNUSED;
2572 imm_reloc[1] = BFD_RELOC_UNUSED;
2573 imm_reloc[2] = BFD_RELOC_UNUSED;
2574 offset_reloc[0] = BFD_RELOC_UNUSED;
2575 offset_reloc[1] = BFD_RELOC_UNUSED;
2576 offset_reloc[2] = BFD_RELOC_UNUSED;
2578 if (mips_opts.mips16)
2579 mips16_ip (str, &insn);
2582 mips_ip (str, &insn);
2583 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2584 str, insn.insn_opcode));
2589 as_bad ("%s `%s'", insn_error, str);
2593 if (insn.insn_mo->pinfo == INSN_MACRO)
2596 if (mips_opts.mips16)
2597 mips16_macro (&insn);
2604 if (imm_expr.X_op != O_absent)
2605 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2606 else if (offset_expr.X_op != O_absent)
2607 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2609 append_insn (&insn, NULL, unused_reloc, FALSE);
2613 /* Convenience functions for abstracting away the differences between
2614 MIPS16 and non-MIPS16 relocations. */
2616 static inline bfd_boolean
2617 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2621 case BFD_RELOC_MIPS16_JMP:
2622 case BFD_RELOC_MIPS16_GPREL:
2623 case BFD_RELOC_MIPS16_GOT16:
2624 case BFD_RELOC_MIPS16_CALL16:
2625 case BFD_RELOC_MIPS16_HI16_S:
2626 case BFD_RELOC_MIPS16_HI16:
2627 case BFD_RELOC_MIPS16_LO16:
2635 static inline bfd_boolean
2636 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2640 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2641 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2642 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2643 case BFD_RELOC_MICROMIPS_GPREL16:
2644 case BFD_RELOC_MICROMIPS_JMP:
2645 case BFD_RELOC_MICROMIPS_HI16:
2646 case BFD_RELOC_MICROMIPS_HI16_S:
2647 case BFD_RELOC_MICROMIPS_LO16:
2648 case BFD_RELOC_MICROMIPS_LITERAL:
2649 case BFD_RELOC_MICROMIPS_GOT16:
2650 case BFD_RELOC_MICROMIPS_CALL16:
2651 case BFD_RELOC_MICROMIPS_GOT_HI16:
2652 case BFD_RELOC_MICROMIPS_GOT_LO16:
2653 case BFD_RELOC_MICROMIPS_CALL_HI16:
2654 case BFD_RELOC_MICROMIPS_CALL_LO16:
2655 case BFD_RELOC_MICROMIPS_SUB:
2656 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2657 case BFD_RELOC_MICROMIPS_GOT_OFST:
2658 case BFD_RELOC_MICROMIPS_GOT_DISP:
2659 case BFD_RELOC_MICROMIPS_HIGHEST:
2660 case BFD_RELOC_MICROMIPS_HIGHER:
2661 case BFD_RELOC_MICROMIPS_SCN_DISP:
2662 case BFD_RELOC_MICROMIPS_JALR:
2670 static inline bfd_boolean
2671 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2673 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2676 static inline bfd_boolean
2677 got16_reloc_p (bfd_reloc_code_real_type reloc)
2679 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2680 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2683 static inline bfd_boolean
2684 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2686 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2687 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2690 static inline bfd_boolean
2691 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2693 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2694 || reloc == BFD_RELOC_MICROMIPS_LO16);
2697 static inline bfd_boolean
2698 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2700 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2703 /* Return true if the given relocation might need a matching %lo().
2704 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2705 need a matching %lo() when applied to local symbols. */
2707 static inline bfd_boolean
2708 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2710 return (HAVE_IN_PLACE_ADDENDS
2711 && (hi16_reloc_p (reloc)
2712 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2713 all GOT16 relocations evaluate to "G". */
2714 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2717 /* Return the type of %lo() reloc needed by RELOC, given that
2718 reloc_needs_lo_p. */
2720 static inline bfd_reloc_code_real_type
2721 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2723 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2724 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2728 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2731 static inline bfd_boolean
2732 fixup_has_matching_lo_p (fixS *fixp)
2734 return (fixp->fx_next != NULL
2735 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2736 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2737 && fixp->fx_offset == fixp->fx_next->fx_offset);
2740 /* This function returns true if modifying a register requires a
2744 reg_needs_delay (unsigned int reg)
2746 unsigned long prev_pinfo;
2748 prev_pinfo = history[0].insn_mo->pinfo;
2749 if (! mips_opts.noreorder
2750 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2751 && ! gpr_interlocks)
2752 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2753 && ! cop_interlocks)))
2755 /* A load from a coprocessor or from memory. All load delays
2756 delay the use of general register rt for one instruction. */
2757 /* Itbl support may require additional care here. */
2758 know (prev_pinfo & INSN_WRITE_GPR_T);
2759 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2766 /* Move all labels in LABELS to the current insertion point. TEXT_P
2767 says whether the labels refer to text or data. */
2770 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2772 struct insn_label_list *l;
2775 for (l = labels; l != NULL; l = l->next)
2777 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2778 symbol_set_frag (l->label, frag_now);
2779 val = (valueT) frag_now_fix ();
2780 /* MIPS16/microMIPS text labels are stored as odd. */
2781 if (text_p && HAVE_CODE_COMPRESSION)
2783 S_SET_VALUE (l->label, val);
2787 /* Move all labels in insn_labels to the current insertion point
2788 and treat them as text labels. */
2791 mips_move_text_labels (void)
2793 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2797 s_is_linkonce (symbolS *sym, segT from_seg)
2799 bfd_boolean linkonce = FALSE;
2800 segT symseg = S_GET_SEGMENT (sym);
2802 if (symseg != from_seg && !S_IS_LOCAL (sym))
2804 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2807 /* The GNU toolchain uses an extension for ELF: a section
2808 beginning with the magic string .gnu.linkonce is a
2809 linkonce section. */
2810 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2811 sizeof ".gnu.linkonce" - 1) == 0)
2818 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2819 linker to handle them specially, such as generating jalx instructions
2820 when needed. We also make them odd for the duration of the assembly,
2821 in order to generate the right sort of code. We will make them even
2822 in the adjust_symtab routine, while leaving them marked. This is
2823 convenient for the debugger and the disassembler. The linker knows
2824 to make them odd again. */
2827 mips_compressed_mark_labels (void)
2829 segment_info_type *si = seg_info (now_seg);
2830 struct insn_label_list *l;
2832 gas_assert (HAVE_CODE_COMPRESSION);
2834 for (l = si->label_list; l != NULL; l = l->next)
2836 symbolS *label = l->label;
2838 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2841 if (mips_opts.mips16)
2842 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2844 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2847 if ((S_GET_VALUE (label) & 1) == 0
2848 /* Don't adjust the address if the label is global or weak, or
2849 in a link-once section, since we'll be emitting symbol reloc
2850 references to it which will be patched up by the linker, and
2851 the final value of the symbol may or may not be MIPS16/microMIPS. */
2852 && ! S_IS_WEAK (label)
2853 && ! S_IS_EXTERNAL (label)
2854 && ! s_is_linkonce (label, now_seg))
2855 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2859 /* End the current frag. Make it a variant frag and record the
2863 relax_close_frag (void)
2865 mips_macro_warning.first_frag = frag_now;
2866 frag_var (rs_machine_dependent, 0, 0,
2867 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2868 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2870 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2871 mips_relax.first_fixup = 0;
2874 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2875 See the comment above RELAX_ENCODE for more details. */
2878 relax_start (symbolS *symbol)
2880 gas_assert (mips_relax.sequence == 0);
2881 mips_relax.sequence = 1;
2882 mips_relax.symbol = symbol;
2885 /* Start generating the second version of a relaxable sequence.
2886 See the comment above RELAX_ENCODE for more details. */
2891 gas_assert (mips_relax.sequence == 1);
2892 mips_relax.sequence = 2;
2895 /* End the current relaxable sequence. */
2900 gas_assert (mips_relax.sequence == 2);
2901 relax_close_frag ();
2902 mips_relax.sequence = 0;
2905 /* Return true if IP is a delayed branch or jump. */
2907 static inline bfd_boolean
2908 delayed_branch_p (const struct mips_cl_insn *ip)
2910 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2911 | INSN_COND_BRANCH_DELAY
2912 | INSN_COND_BRANCH_LIKELY)) != 0;
2915 /* Return true if IP is a compact branch or jump. */
2917 static inline bfd_boolean
2918 compact_branch_p (const struct mips_cl_insn *ip)
2920 if (mips_opts.mips16)
2921 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2922 | MIPS16_INSN_COND_BRANCH)) != 0;
2924 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2925 | INSN2_COND_BRANCH)) != 0;
2928 /* Return true if IP is an unconditional branch or jump. */
2930 static inline bfd_boolean
2931 uncond_branch_p (const struct mips_cl_insn *ip)
2933 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2934 || (mips_opts.mips16
2935 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2936 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2939 /* Return true if IP is a branch-likely instruction. */
2941 static inline bfd_boolean
2942 branch_likely_p (const struct mips_cl_insn *ip)
2944 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2947 /* Return the type of nop that should be used to fill the delay slot
2948 of delayed branch IP. */
2950 static struct mips_cl_insn *
2951 get_delay_slot_nop (const struct mips_cl_insn *ip)
2953 if (mips_opts.micromips
2954 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2955 return µmips_nop32_insn;
2959 /* Return the mask of core registers that IP reads or writes. */
2962 gpr_mod_mask (const struct mips_cl_insn *ip)
2964 unsigned long pinfo2;
2968 pinfo2 = ip->insn_mo->pinfo2;
2969 if (mips_opts.micromips)
2971 if (pinfo2 & INSN2_MOD_GPR_MD)
2972 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2973 if (pinfo2 & INSN2_MOD_GPR_MF)
2974 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2975 if (pinfo2 & INSN2_MOD_SP)
2981 /* Return the mask of core registers that IP reads. */
2984 gpr_read_mask (const struct mips_cl_insn *ip)
2986 unsigned long pinfo, pinfo2;
2989 mask = gpr_mod_mask (ip);
2990 pinfo = ip->insn_mo->pinfo;
2991 pinfo2 = ip->insn_mo->pinfo2;
2992 if (mips_opts.mips16)
2994 if (pinfo & MIPS16_INSN_READ_X)
2995 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2996 if (pinfo & MIPS16_INSN_READ_Y)
2997 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2998 if (pinfo & MIPS16_INSN_READ_T)
3000 if (pinfo & MIPS16_INSN_READ_SP)
3002 if (pinfo & MIPS16_INSN_READ_31)
3004 if (pinfo & MIPS16_INSN_READ_Z)
3005 mask |= 1 << (mips16_to_32_reg_map
3006 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3007 if (pinfo & MIPS16_INSN_READ_GPR_X)
3008 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3012 if (pinfo2 & INSN2_READ_GPR_D)
3013 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3014 if (pinfo & INSN_READ_GPR_T)
3015 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3016 if (pinfo & INSN_READ_GPR_S)
3017 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3018 if (pinfo2 & INSN2_READ_GP)
3020 if (pinfo2 & INSN2_READ_GPR_31)
3022 if (pinfo2 & INSN2_READ_GPR_Z)
3023 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3025 if (mips_opts.micromips)
3027 if (pinfo2 & INSN2_READ_GPR_MC)
3028 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3029 if (pinfo2 & INSN2_READ_GPR_ME)
3030 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3031 if (pinfo2 & INSN2_READ_GPR_MG)
3032 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3033 if (pinfo2 & INSN2_READ_GPR_MJ)
3034 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3035 if (pinfo2 & INSN2_READ_GPR_MMN)
3037 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3038 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3040 if (pinfo2 & INSN2_READ_GPR_MP)
3041 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3042 if (pinfo2 & INSN2_READ_GPR_MQ)
3043 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3045 /* Don't include register 0. */
3049 /* Return the mask of core registers that IP writes. */
3052 gpr_write_mask (const struct mips_cl_insn *ip)
3054 unsigned long pinfo, pinfo2;
3057 mask = gpr_mod_mask (ip);
3058 pinfo = ip->insn_mo->pinfo;
3059 pinfo2 = ip->insn_mo->pinfo2;
3060 if (mips_opts.mips16)
3062 if (pinfo & MIPS16_INSN_WRITE_X)
3063 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3064 if (pinfo & MIPS16_INSN_WRITE_Y)
3065 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3066 if (pinfo & MIPS16_INSN_WRITE_Z)
3067 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3068 if (pinfo & MIPS16_INSN_WRITE_T)
3070 if (pinfo & MIPS16_INSN_WRITE_SP)
3072 if (pinfo & MIPS16_INSN_WRITE_31)
3074 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3075 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3079 if (pinfo & INSN_WRITE_GPR_D)
3080 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3081 if (pinfo & INSN_WRITE_GPR_T)
3082 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3083 if (pinfo & INSN_WRITE_GPR_S)
3084 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3085 if (pinfo & INSN_WRITE_GPR_31)
3087 if (pinfo2 & INSN2_WRITE_GPR_Z)
3088 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3090 if (mips_opts.micromips)
3092 if (pinfo2 & INSN2_WRITE_GPR_MB)
3093 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3094 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3096 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3097 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3099 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3100 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3101 if (pinfo2 & INSN2_WRITE_GPR_MP)
3102 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3104 /* Don't include register 0. */
3108 /* Return the mask of floating-point registers that IP reads. */
3111 fpr_read_mask (const struct mips_cl_insn *ip)
3113 unsigned long pinfo, pinfo2;
3117 pinfo = ip->insn_mo->pinfo;
3118 pinfo2 = ip->insn_mo->pinfo2;
3119 if (!mips_opts.mips16)
3121 if (pinfo2 & INSN2_READ_FPR_D)
3122 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3123 if (pinfo & INSN_READ_FPR_S)
3124 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3125 if (pinfo & INSN_READ_FPR_T)
3126 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3127 if (pinfo & INSN_READ_FPR_R)
3128 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3129 if (pinfo2 & INSN2_READ_FPR_Z)
3130 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3132 /* Conservatively treat all operands to an FP_D instruction are doubles.
3133 (This is overly pessimistic for things like cvt.d.s.) */
3134 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3139 /* Return the mask of floating-point registers that IP writes. */
3142 fpr_write_mask (const struct mips_cl_insn *ip)
3144 unsigned long pinfo, pinfo2;
3148 pinfo = ip->insn_mo->pinfo;
3149 pinfo2 = ip->insn_mo->pinfo2;
3150 if (!mips_opts.mips16)
3152 if (pinfo & INSN_WRITE_FPR_D)
3153 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3154 if (pinfo & INSN_WRITE_FPR_S)
3155 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3156 if (pinfo & INSN_WRITE_FPR_T)
3157 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3158 if (pinfo2 & INSN2_WRITE_FPR_Z)
3159 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3161 /* Conservatively treat all operands to an FP_D instruction are doubles.
3162 (This is overly pessimistic for things like cvt.s.d.) */
3163 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3168 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3169 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3170 by VR4120 errata. */
3173 classify_vr4120_insn (const char *name)
3175 if (strncmp (name, "macc", 4) == 0)
3176 return FIX_VR4120_MACC;
3177 if (strncmp (name, "dmacc", 5) == 0)
3178 return FIX_VR4120_DMACC;
3179 if (strncmp (name, "mult", 4) == 0)
3180 return FIX_VR4120_MULT;
3181 if (strncmp (name, "dmult", 5) == 0)
3182 return FIX_VR4120_DMULT;
3183 if (strstr (name, "div"))
3184 return FIX_VR4120_DIV;
3185 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3186 return FIX_VR4120_MTHILO;
3187 return NUM_FIX_VR4120_CLASSES;
3190 #define INSN_ERET 0x42000018
3191 #define INSN_DERET 0x4200001f
3193 /* Return the number of instructions that must separate INSN1 and INSN2,
3194 where INSN1 is the earlier instruction. Return the worst-case value
3195 for any INSN2 if INSN2 is null. */
3198 insns_between (const struct mips_cl_insn *insn1,
3199 const struct mips_cl_insn *insn2)
3201 unsigned long pinfo1, pinfo2;
3204 /* This function needs to know which pinfo flags are set for INSN2
3205 and which registers INSN2 uses. The former is stored in PINFO2 and
3206 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3207 will have every flag set and INSN2_USES_GPR will always return true. */
3208 pinfo1 = insn1->insn_mo->pinfo;
3209 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3211 #define INSN2_USES_GPR(REG) \
3212 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3214 /* For most targets, write-after-read dependencies on the HI and LO
3215 registers must be separated by at least two instructions. */
3216 if (!hilo_interlocks)
3218 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3220 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3224 /* If we're working around r7000 errata, there must be two instructions
3225 between an mfhi or mflo and any instruction that uses the result. */
3226 if (mips_7000_hilo_fix
3227 && !mips_opts.micromips
3228 && MF_HILO_INSN (pinfo1)
3229 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3232 /* If we're working around 24K errata, one instruction is required
3233 if an ERET or DERET is followed by a branch instruction. */
3234 if (mips_fix_24k && !mips_opts.micromips)
3236 if (insn1->insn_opcode == INSN_ERET
3237 || insn1->insn_opcode == INSN_DERET)
3240 || insn2->insn_opcode == INSN_ERET
3241 || insn2->insn_opcode == INSN_DERET
3242 || delayed_branch_p (insn2))
3247 /* If working around VR4120 errata, check for combinations that need
3248 a single intervening instruction. */
3249 if (mips_fix_vr4120 && !mips_opts.micromips)
3251 unsigned int class1, class2;
3253 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3254 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3258 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3259 if (vr4120_conflicts[class1] & (1 << class2))
3264 if (!HAVE_CODE_COMPRESSION)
3266 /* Check for GPR or coprocessor load delays. All such delays
3267 are on the RT register. */
3268 /* Itbl support may require additional care here. */
3269 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3270 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3272 know (pinfo1 & INSN_WRITE_GPR_T);
3273 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3277 /* Check for generic coprocessor hazards.
3279 This case is not handled very well. There is no special
3280 knowledge of CP0 handling, and the coprocessors other than
3281 the floating point unit are not distinguished at all. */
3282 /* Itbl support may require additional care here. FIXME!
3283 Need to modify this to include knowledge about
3284 user specified delays! */
3285 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3286 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3288 /* Handle cases where INSN1 writes to a known general coprocessor
3289 register. There must be a one instruction delay before INSN2
3290 if INSN2 reads that register, otherwise no delay is needed. */
3291 mask = fpr_write_mask (insn1);
3294 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3299 /* Read-after-write dependencies on the control registers
3300 require a two-instruction gap. */
3301 if ((pinfo1 & INSN_WRITE_COND_CODE)
3302 && (pinfo2 & INSN_READ_COND_CODE))
3305 /* We don't know exactly what INSN1 does. If INSN2 is
3306 also a coprocessor instruction, assume there must be
3307 a one instruction gap. */
3308 if (pinfo2 & INSN_COP)
3313 /* Check for read-after-write dependencies on the coprocessor
3314 control registers in cases where INSN1 does not need a general
3315 coprocessor delay. This means that INSN1 is a floating point
3316 comparison instruction. */
3317 /* Itbl support may require additional care here. */
3318 else if (!cop_interlocks
3319 && (pinfo1 & INSN_WRITE_COND_CODE)
3320 && (pinfo2 & INSN_READ_COND_CODE))
3324 #undef INSN2_USES_GPR
3329 /* Return the number of nops that would be needed to work around the
3330 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3331 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3332 that are contained within the first IGNORE instructions of HIST. */
3335 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3336 const struct mips_cl_insn *insn)
3341 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3342 are not affected by the errata. */
3344 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3345 || strcmp (insn->insn_mo->name, "mtlo") == 0
3346 || strcmp (insn->insn_mo->name, "mthi") == 0))
3349 /* Search for the first MFLO or MFHI. */
3350 for (i = 0; i < MAX_VR4130_NOPS; i++)
3351 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3353 /* Extract the destination register. */
3354 mask = gpr_write_mask (&hist[i]);
3356 /* No nops are needed if INSN reads that register. */
3357 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3360 /* ...or if any of the intervening instructions do. */
3361 for (j = 0; j < i; j++)
3362 if (gpr_read_mask (&hist[j]) & mask)
3366 return MAX_VR4130_NOPS - i;
3371 #define BASE_REG_EQ(INSN1, INSN2) \
3372 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3373 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3375 /* Return the minimum alignment for this store instruction. */
3378 fix_24k_align_to (const struct mips_opcode *mo)
3380 if (strcmp (mo->name, "sh") == 0)
3383 if (strcmp (mo->name, "swc1") == 0
3384 || strcmp (mo->name, "swc2") == 0
3385 || strcmp (mo->name, "sw") == 0
3386 || strcmp (mo->name, "sc") == 0
3387 || strcmp (mo->name, "s.s") == 0)
3390 if (strcmp (mo->name, "sdc1") == 0
3391 || strcmp (mo->name, "sdc2") == 0
3392 || strcmp (mo->name, "s.d") == 0)
3399 struct fix_24k_store_info
3401 /* Immediate offset, if any, for this store instruction. */
3403 /* Alignment required by this store instruction. */
3405 /* True for register offsets. */
3406 int register_offset;
3409 /* Comparison function used by qsort. */
3412 fix_24k_sort (const void *a, const void *b)
3414 const struct fix_24k_store_info *pos1 = a;
3415 const struct fix_24k_store_info *pos2 = b;
3417 return (pos1->off - pos2->off);
3420 /* INSN is a store instruction. Try to record the store information
3421 in STINFO. Return false if the information isn't known. */
3424 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3425 const struct mips_cl_insn *insn)
3427 /* The instruction must have a known offset. */
3428 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3431 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3432 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3436 /* Return the number of nops that would be needed to work around the 24k
3437 "lost data on stores during refill" errata if instruction INSN
3438 immediately followed the 2 instructions described by HIST.
3439 Ignore hazards that are contained within the first IGNORE
3440 instructions of HIST.
3442 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3443 for the data cache refills and store data. The following describes
3444 the scenario where the store data could be lost.
3446 * A data cache miss, due to either a load or a store, causing fill
3447 data to be supplied by the memory subsystem
3448 * The first three doublewords of fill data are returned and written
3450 * A sequence of four stores occurs in consecutive cycles around the
3451 final doubleword of the fill:
3455 * Zero, One or more instructions
3458 The four stores A-D must be to different doublewords of the line that
3459 is being filled. The fourth instruction in the sequence above permits
3460 the fill of the final doubleword to be transferred from the FSB into
3461 the cache. In the sequence above, the stores may be either integer
3462 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3463 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3464 different doublewords on the line. If the floating point unit is
3465 running in 1:2 mode, it is not possible to create the sequence above
3466 using only floating point store instructions.
3468 In this case, the cache line being filled is incorrectly marked
3469 invalid, thereby losing the data from any store to the line that
3470 occurs between the original miss and the completion of the five
3471 cycle sequence shown above.
3473 The workarounds are:
3475 * Run the data cache in write-through mode.
3476 * Insert a non-store instruction between
3477 Store A and Store B or Store B and Store C. */
3480 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3481 const struct mips_cl_insn *insn)
3483 struct fix_24k_store_info pos[3];
3484 int align, i, base_offset;
3489 /* If the previous instruction wasn't a store, there's nothing to
3491 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3494 /* If the instructions after the previous one are unknown, we have
3495 to assume the worst. */
3499 /* Check whether we are dealing with three consecutive stores. */
3500 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3501 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3504 /* If we don't know the relationship between the store addresses,
3505 assume the worst. */
3506 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3507 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3510 if (!fix_24k_record_store_info (&pos[0], insn)
3511 || !fix_24k_record_store_info (&pos[1], &hist[0])
3512 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3515 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3517 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3518 X bytes and such that the base register + X is known to be aligned
3521 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3525 align = pos[0].align_to;
3526 base_offset = pos[0].off;
3527 for (i = 1; i < 3; i++)
3528 if (align < pos[i].align_to)
3530 align = pos[i].align_to;
3531 base_offset = pos[i].off;
3533 for (i = 0; i < 3; i++)
3534 pos[i].off -= base_offset;
3537 pos[0].off &= ~align + 1;
3538 pos[1].off &= ~align + 1;
3539 pos[2].off &= ~align + 1;
3541 /* If any two stores write to the same chunk, they also write to the
3542 same doubleword. The offsets are still sorted at this point. */
3543 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3546 /* A range of at least 9 bytes is needed for the stores to be in
3547 non-overlapping doublewords. */
3548 if (pos[2].off - pos[0].off <= 8)
3551 if (pos[2].off - pos[1].off >= 24
3552 || pos[1].off - pos[0].off >= 24
3553 || pos[2].off - pos[0].off >= 32)
3559 /* Return the number of nops that would be needed if instruction INSN
3560 immediately followed the MAX_NOPS instructions given by HIST,
3561 where HIST[0] is the most recent instruction. Ignore hazards
3562 between INSN and the first IGNORE instructions in HIST.
3564 If INSN is null, return the worse-case number of nops for any
3568 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3569 const struct mips_cl_insn *insn)
3571 int i, nops, tmp_nops;
3574 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3576 tmp_nops = insns_between (hist + i, insn) - i;
3577 if (tmp_nops > nops)
3581 if (mips_fix_vr4130 && !mips_opts.micromips)
3583 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3584 if (tmp_nops > nops)
3588 if (mips_fix_24k && !mips_opts.micromips)
3590 tmp_nops = nops_for_24k (ignore, hist, insn);
3591 if (tmp_nops > nops)
3598 /* The variable arguments provide NUM_INSNS extra instructions that
3599 might be added to HIST. Return the largest number of nops that
3600 would be needed after the extended sequence, ignoring hazards
3601 in the first IGNORE instructions. */
3604 nops_for_sequence (int num_insns, int ignore,
3605 const struct mips_cl_insn *hist, ...)
3608 struct mips_cl_insn buffer[MAX_NOPS];
3609 struct mips_cl_insn *cursor;
3612 va_start (args, hist);
3613 cursor = buffer + num_insns;
3614 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3615 while (cursor > buffer)
3616 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3618 nops = nops_for_insn (ignore, buffer, NULL);
3623 /* Like nops_for_insn, but if INSN is a branch, take into account the
3624 worst-case delay for the branch target. */
3627 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3628 const struct mips_cl_insn *insn)
3632 nops = nops_for_insn (ignore, hist, insn);
3633 if (delayed_branch_p (insn))
3635 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3636 hist, insn, get_delay_slot_nop (insn));
3637 if (tmp_nops > nops)
3640 else if (compact_branch_p (insn))
3642 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3643 if (tmp_nops > nops)
3649 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3652 fix_loongson2f_nop (struct mips_cl_insn * ip)
3654 gas_assert (!HAVE_CODE_COMPRESSION);
3655 if (strcmp (ip->insn_mo->name, "nop") == 0)
3656 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3659 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3660 jr target pc &= 'hffff_ffff_cfff_ffff. */
3663 fix_loongson2f_jump (struct mips_cl_insn * ip)
3665 gas_assert (!HAVE_CODE_COMPRESSION);
3666 if (strcmp (ip->insn_mo->name, "j") == 0
3667 || strcmp (ip->insn_mo->name, "jr") == 0
3668 || strcmp (ip->insn_mo->name, "jalr") == 0)
3676 sreg = EXTRACT_OPERAND (0, RS, *ip);
3677 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3680 ep.X_op = O_constant;
3681 ep.X_add_number = 0xcfff0000;
3682 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3683 ep.X_add_number = 0xffff;
3684 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3685 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3690 fix_loongson2f (struct mips_cl_insn * ip)
3692 if (mips_fix_loongson2f_nop)
3693 fix_loongson2f_nop (ip);
3695 if (mips_fix_loongson2f_jump)
3696 fix_loongson2f_jump (ip);
3699 /* IP is a branch that has a delay slot, and we need to fill it
3700 automatically. Return true if we can do that by swapping IP
3701 with the previous instruction. */
3704 can_swap_branch_p (struct mips_cl_insn *ip)
3706 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3707 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3709 /* -O2 and above is required for this optimization. */
3710 if (mips_optimize < 2)
3713 /* If we have seen .set volatile or .set nomove, don't optimize. */
3714 if (mips_opts.nomove)
3717 /* We can't swap if the previous instruction's position is fixed. */
3718 if (history[0].fixed_p)
3721 /* If the previous previous insn was in a .set noreorder, we can't
3722 swap. Actually, the MIPS assembler will swap in this situation.
3723 However, gcc configured -with-gnu-as will generate code like
3731 in which we can not swap the bne and INSN. If gcc is not configured
3732 -with-gnu-as, it does not output the .set pseudo-ops. */
3733 if (history[1].noreorder_p)
3736 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3737 This means that the previous instruction was a 4-byte one anyhow. */
3738 if (mips_opts.mips16 && history[0].fixp[0])
3741 /* If the branch is itself the target of a branch, we can not swap.
3742 We cheat on this; all we check for is whether there is a label on
3743 this instruction. If there are any branches to anything other than
3744 a label, users must use .set noreorder. */
3745 if (seg_info (now_seg)->label_list)
3748 /* If the previous instruction is in a variant frag other than this
3749 branch's one, we cannot do the swap. This does not apply to
3750 MIPS16 code, which uses variant frags for different purposes. */
3751 if (!mips_opts.mips16
3753 && history[0].frag->fr_type == rs_machine_dependent)
3756 /* We do not swap with instructions that cannot architecturally
3757 be placed in a branch delay slot, such as SYNC or ERET. We
3758 also refrain from swapping with a trap instruction, since it
3759 complicates trap handlers to have the trap instruction be in
3761 prev_pinfo = history[0].insn_mo->pinfo;
3762 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3765 /* Check for conflicts between the branch and the instructions
3766 before the candidate delay slot. */
3767 if (nops_for_insn (0, history + 1, ip) > 0)
3770 /* Check for conflicts between the swapped sequence and the
3771 target of the branch. */
3772 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3775 /* If the branch reads a register that the previous
3776 instruction sets, we can not swap. */
3777 gpr_read = gpr_read_mask (ip);
3778 prev_gpr_write = gpr_write_mask (&history[0]);
3779 if (gpr_read & prev_gpr_write)
3782 /* If the branch writes a register that the previous
3783 instruction sets, we can not swap. */
3784 gpr_write = gpr_write_mask (ip);
3785 if (gpr_write & prev_gpr_write)
3788 /* If the branch writes a register that the previous
3789 instruction reads, we can not swap. */
3790 prev_gpr_read = gpr_read_mask (&history[0]);
3791 if (gpr_write & prev_gpr_read)
3794 /* If one instruction sets a condition code and the
3795 other one uses a condition code, we can not swap. */
3796 pinfo = ip->insn_mo->pinfo;
3797 if ((pinfo & INSN_READ_COND_CODE)
3798 && (prev_pinfo & INSN_WRITE_COND_CODE))
3800 if ((pinfo & INSN_WRITE_COND_CODE)
3801 && (prev_pinfo & INSN_READ_COND_CODE))
3804 /* If the previous instruction uses the PC, we can not swap. */
3805 prev_pinfo2 = history[0].insn_mo->pinfo2;
3806 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3808 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3811 /* If the previous instruction has an incorrect size for a fixed
3812 branch delay slot in microMIPS mode, we cannot swap. */
3813 pinfo2 = ip->insn_mo->pinfo2;
3814 if (mips_opts.micromips
3815 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3816 && insn_length (history) != 2)
3818 if (mips_opts.micromips
3819 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3820 && insn_length (history) != 4)
3826 /* Decide how we should add IP to the instruction stream. */
3828 static enum append_method
3829 get_append_method (struct mips_cl_insn *ip)
3831 unsigned long pinfo;
3833 /* The relaxed version of a macro sequence must be inherently
3835 if (mips_relax.sequence == 2)
3838 /* We must not dabble with instructions in a ".set norerorder" block. */
3839 if (mips_opts.noreorder)
3842 /* Otherwise, it's our responsibility to fill branch delay slots. */
3843 if (delayed_branch_p (ip))
3845 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3848 pinfo = ip->insn_mo->pinfo;
3849 if (mips_opts.mips16
3850 && ISA_SUPPORTS_MIPS16E
3851 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3852 return APPEND_ADD_COMPACT;
3854 return APPEND_ADD_WITH_NOP;
3860 /* IP is a MIPS16 instruction whose opcode we have just changed.
3861 Point IP->insn_mo to the new opcode's definition. */
3864 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3866 const struct mips_opcode *mo, *end;
3868 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3869 for (mo = ip->insn_mo; mo < end; mo++)
3870 if ((ip->insn_opcode & mo->mask) == mo->match)
3878 /* For microMIPS macros, we need to generate a local number label
3879 as the target of branches. */
3880 #define MICROMIPS_LABEL_CHAR '\037'
3881 static unsigned long micromips_target_label;
3882 static char micromips_target_name[32];
3885 micromips_label_name (void)
3887 char *p = micromips_target_name;
3888 char symbol_name_temporary[24];
3896 l = micromips_target_label;
3897 #ifdef LOCAL_LABEL_PREFIX
3898 *p++ = LOCAL_LABEL_PREFIX;
3901 *p++ = MICROMIPS_LABEL_CHAR;
3904 symbol_name_temporary[i++] = l % 10 + '0';
3909 *p++ = symbol_name_temporary[--i];
3912 return micromips_target_name;
3916 micromips_label_expr (expressionS *label_expr)
3918 label_expr->X_op = O_symbol;
3919 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3920 label_expr->X_add_number = 0;
3924 micromips_label_inc (void)
3926 micromips_target_label++;
3927 *micromips_target_name = '\0';
3931 micromips_add_label (void)
3935 s = colon (micromips_label_name ());
3936 micromips_label_inc ();
3937 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3939 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3945 /* If assembling microMIPS code, then return the microMIPS reloc
3946 corresponding to the requested one if any. Otherwise return
3947 the reloc unchanged. */
3949 static bfd_reloc_code_real_type
3950 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3952 static const bfd_reloc_code_real_type relocs[][2] =
3954 /* Keep sorted incrementally by the left-hand key. */
3955 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3956 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3957 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3958 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3959 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3960 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3961 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3962 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3963 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3964 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3965 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3966 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3967 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3968 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3969 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3970 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3971 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3972 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3973 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3974 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3975 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3976 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3977 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3978 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3979 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3980 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3981 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
3983 bfd_reloc_code_real_type r;
3986 if (!mips_opts.micromips)
3988 for (i = 0; i < ARRAY_SIZE (relocs); i++)
3994 return relocs[i][1];
3999 /* Output an instruction. IP is the instruction information.
4000 ADDRESS_EXPR is an operand of the instruction to be used with
4001 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4002 a macro expansion. */
4005 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4006 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4008 unsigned long prev_pinfo2, pinfo;
4009 bfd_boolean relaxed_branch = FALSE;
4010 enum append_method method;
4011 bfd_boolean relax32;
4014 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4015 fix_loongson2f (ip);
4017 mips_mark_labels ();
4019 file_ase_mips16 |= mips_opts.mips16;
4020 file_ase_micromips |= mips_opts.micromips;
4022 prev_pinfo2 = history[0].insn_mo->pinfo2;
4023 pinfo = ip->insn_mo->pinfo;
4025 if (mips_opts.micromips
4027 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4028 && micromips_insn_length (ip->insn_mo) != 2)
4029 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4030 && micromips_insn_length (ip->insn_mo) != 4)))
4031 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4032 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4034 if (address_expr == NULL)
4036 else if (*reloc_type <= BFD_RELOC_UNUSED
4037 && address_expr->X_op == O_constant)
4042 switch (*reloc_type)
4045 ip->insn_opcode |= address_expr->X_add_number;
4048 case BFD_RELOC_MIPS_HIGHEST:
4049 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
4050 ip->insn_opcode |= tmp & 0xffff;
4053 case BFD_RELOC_MIPS_HIGHER:
4054 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
4055 ip->insn_opcode |= tmp & 0xffff;
4058 case BFD_RELOC_HI16_S:
4059 tmp = (address_expr->X_add_number + 0x8000) >> 16;
4060 ip->insn_opcode |= tmp & 0xffff;
4063 case BFD_RELOC_HI16:
4064 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4067 case BFD_RELOC_UNUSED:
4068 case BFD_RELOC_LO16:
4069 case BFD_RELOC_MIPS_GOT_DISP:
4070 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4073 case BFD_RELOC_MIPS_JMP:
4077 shift = mips_opts.micromips ? 1 : 2;
4078 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4079 as_bad (_("jump to misaligned address (0x%lx)"),
4080 (unsigned long) address_expr->X_add_number);
4081 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4087 case BFD_RELOC_MIPS16_JMP:
4088 if ((address_expr->X_add_number & 3) != 0)
4089 as_bad (_("jump to misaligned address (0x%lx)"),
4090 (unsigned long) address_expr->X_add_number);
4092 (((address_expr->X_add_number & 0x7c0000) << 3)
4093 | ((address_expr->X_add_number & 0xf800000) >> 7)
4094 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4098 case BFD_RELOC_16_PCREL_S2:
4102 shift = mips_opts.micromips ? 1 : 2;
4103 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4104 as_bad (_("branch to misaligned address (0x%lx)"),
4105 (unsigned long) address_expr->X_add_number);
4106 if (!mips_relax_branch)
4108 if ((address_expr->X_add_number + (1 << (shift + 15)))
4109 & ~((1 << (shift + 16)) - 1))
4110 as_bad (_("branch address range overflow (0x%lx)"),
4111 (unsigned long) address_expr->X_add_number);
4112 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4124 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4126 /* There are a lot of optimizations we could do that we don't.
4127 In particular, we do not, in general, reorder instructions.
4128 If you use gcc with optimization, it will reorder
4129 instructions and generally do much more optimization then we
4130 do here; repeating all that work in the assembler would only
4131 benefit hand written assembly code, and does not seem worth
4133 int nops = (mips_optimize == 0
4134 ? nops_for_insn (0, history, NULL)
4135 : nops_for_insn_or_target (0, history, ip));
4139 unsigned long old_frag_offset;
4142 old_frag = frag_now;
4143 old_frag_offset = frag_now_fix ();
4145 for (i = 0; i < nops; i++)
4146 add_fixed_insn (NOP_INSN);
4147 insert_into_history (0, nops, NOP_INSN);
4151 listing_prev_line ();
4152 /* We may be at the start of a variant frag. In case we
4153 are, make sure there is enough space for the frag
4154 after the frags created by listing_prev_line. The
4155 argument to frag_grow here must be at least as large
4156 as the argument to all other calls to frag_grow in
4157 this file. We don't have to worry about being in the
4158 middle of a variant frag, because the variants insert
4159 all needed nop instructions themselves. */
4163 mips_move_text_labels ();
4165 #ifndef NO_ECOFF_DEBUGGING
4166 if (ECOFF_DEBUGGING)
4167 ecoff_fix_loc (old_frag, old_frag_offset);
4171 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4175 /* Work out how many nops in prev_nop_frag are needed by IP,
4176 ignoring hazards generated by the first prev_nop_frag_since
4178 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4179 gas_assert (nops <= prev_nop_frag_holds);
4181 /* Enforce NOPS as a minimum. */
4182 if (nops > prev_nop_frag_required)
4183 prev_nop_frag_required = nops;
4185 if (prev_nop_frag_holds == prev_nop_frag_required)
4187 /* Settle for the current number of nops. Update the history
4188 accordingly (for the benefit of any future .set reorder code). */
4189 prev_nop_frag = NULL;
4190 insert_into_history (prev_nop_frag_since,
4191 prev_nop_frag_holds, NOP_INSN);
4195 /* Allow this instruction to replace one of the nops that was
4196 tentatively added to prev_nop_frag. */
4197 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4198 prev_nop_frag_holds--;
4199 prev_nop_frag_since++;
4203 method = get_append_method (ip);
4204 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4207 /* The value passed to dwarf2_emit_insn is the distance between
4208 the beginning of the current instruction and the address that
4209 should be recorded in the debug tables. This is normally the
4212 For MIPS16/microMIPS debug info we want to use ISA-encoded
4213 addresses, so we use -1 for an address higher by one than the
4216 If the instruction produced is a branch that we will swap with
4217 the preceding instruction, then we add the displacement by which
4218 the branch will be moved backwards. This is more appropriate
4219 and for MIPS16/microMIPS code also prevents a debugger from
4220 placing a breakpoint in the middle of the branch (and corrupting
4221 code if software breakpoints are used). */
4222 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4225 relax32 = (mips_relax_branch
4226 /* Don't try branch relaxation within .set nomacro, or within
4227 .set noat if we use $at for PIC computations. If it turns
4228 out that the branch was out-of-range, we'll get an error. */
4229 && !mips_opts.warn_about_macros
4230 && (mips_opts.at || mips_pic == NO_PIC)
4231 /* Don't relax BPOSGE32/64 as they have no complementing
4233 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4235 if (!HAVE_CODE_COMPRESSION
4238 && *reloc_type == BFD_RELOC_16_PCREL_S2
4239 && delayed_branch_p (ip))
4241 relaxed_branch = TRUE;
4242 add_relaxed_insn (ip, (relaxed_branch_length
4244 uncond_branch_p (ip) ? -1
4245 : branch_likely_p (ip) ? 1
4249 uncond_branch_p (ip),
4250 branch_likely_p (ip),
4251 pinfo & INSN_WRITE_GPR_31,
4253 address_expr->X_add_symbol,
4254 address_expr->X_add_number);
4255 *reloc_type = BFD_RELOC_UNUSED;
4257 else if (mips_opts.micromips
4259 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4260 || *reloc_type > BFD_RELOC_UNUSED)
4261 && (delayed_branch_p (ip) || compact_branch_p (ip))
4262 /* Don't try branch relaxation when users specify
4263 16-bit/32-bit instructions. */
4264 && !forced_insn_length)
4266 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4267 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4268 int uncond = uncond_branch_p (ip) ? -1 : 0;
4269 int compact = compact_branch_p (ip);
4270 int al = pinfo & INSN_WRITE_GPR_31;
4273 gas_assert (address_expr != NULL);
4274 gas_assert (!mips_relax.sequence);
4276 relaxed_branch = TRUE;
4277 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4278 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4279 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4281 address_expr->X_add_symbol,
4282 address_expr->X_add_number);
4283 *reloc_type = BFD_RELOC_UNUSED;
4285 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4287 /* We need to set up a variant frag. */
4288 gas_assert (address_expr != NULL);
4289 add_relaxed_insn (ip, 4, 0,
4291 (*reloc_type - BFD_RELOC_UNUSED,
4292 forced_insn_length == 2, forced_insn_length == 4,
4293 delayed_branch_p (&history[0]),
4294 history[0].mips16_absolute_jump_p),
4295 make_expr_symbol (address_expr), 0);
4297 else if (mips_opts.mips16
4299 && *reloc_type != BFD_RELOC_MIPS16_JMP)
4301 if (!delayed_branch_p (ip))
4302 /* Make sure there is enough room to swap this instruction with
4303 a following jump instruction. */
4305 add_fixed_insn (ip);
4309 if (mips_opts.mips16
4310 && mips_opts.noreorder
4311 && delayed_branch_p (&history[0]))
4312 as_warn (_("extended instruction in delay slot"));
4314 if (mips_relax.sequence)
4316 /* If we've reached the end of this frag, turn it into a variant
4317 frag and record the information for the instructions we've
4319 if (frag_room () < 4)
4320 relax_close_frag ();
4321 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4324 if (mips_relax.sequence != 2)
4326 if (mips_macro_warning.first_insn_sizes[0] == 0)
4327 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4328 mips_macro_warning.sizes[0] += insn_length (ip);
4329 mips_macro_warning.insns[0]++;
4331 if (mips_relax.sequence != 1)
4333 if (mips_macro_warning.first_insn_sizes[1] == 0)
4334 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4335 mips_macro_warning.sizes[1] += insn_length (ip);
4336 mips_macro_warning.insns[1]++;
4339 if (mips_opts.mips16)
4342 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4344 add_fixed_insn (ip);
4347 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4349 bfd_reloc_code_real_type final_type[3];
4350 reloc_howto_type *howto0;
4351 reloc_howto_type *howto;
4354 /* Perform any necessary conversion to microMIPS relocations
4355 and find out how many relocations there actually are. */
4356 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4357 final_type[i] = micromips_map_reloc (reloc_type[i]);
4359 /* In a compound relocation, it is the final (outermost)
4360 operator that determines the relocated field. */
4361 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4365 /* To reproduce this failure try assembling gas/testsuites/
4366 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4368 as_bad (_("Unsupported MIPS relocation number %d"),
4370 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4374 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4375 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4376 bfd_get_reloc_size (howto),
4378 howto0 && howto0->pc_relative,
4381 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4382 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4383 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4385 /* These relocations can have an addend that won't fit in
4386 4 octets for 64bit assembly. */
4388 && ! howto->partial_inplace
4389 && (reloc_type[0] == BFD_RELOC_16
4390 || reloc_type[0] == BFD_RELOC_32
4391 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4392 || reloc_type[0] == BFD_RELOC_GPREL16
4393 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4394 || reloc_type[0] == BFD_RELOC_GPREL32
4395 || reloc_type[0] == BFD_RELOC_64
4396 || reloc_type[0] == BFD_RELOC_CTOR
4397 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4398 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4399 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4400 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4401 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4402 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4403 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4404 || hi16_reloc_p (reloc_type[0])
4405 || lo16_reloc_p (reloc_type[0])))
4406 ip->fixp[0]->fx_no_overflow = 1;
4408 if (mips_relax.sequence)
4410 if (mips_relax.first_fixup == 0)
4411 mips_relax.first_fixup = ip->fixp[0];
4413 else if (reloc_needs_lo_p (*reloc_type))
4415 struct mips_hi_fixup *hi_fixup;
4417 /* Reuse the last entry if it already has a matching %lo. */
4418 hi_fixup = mips_hi_fixup_list;
4420 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4422 hi_fixup = ((struct mips_hi_fixup *)
4423 xmalloc (sizeof (struct mips_hi_fixup)));
4424 hi_fixup->next = mips_hi_fixup_list;
4425 mips_hi_fixup_list = hi_fixup;
4427 hi_fixup->fixp = ip->fixp[0];
4428 hi_fixup->seg = now_seg;
4431 /* Add fixups for the second and third relocations, if given.
4432 Note that the ABI allows the second relocation to be
4433 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4434 moment we only use RSS_UNDEF, but we could add support
4435 for the others if it ever becomes necessary. */
4436 for (i = 1; i < 3; i++)
4437 if (reloc_type[i] != BFD_RELOC_UNUSED)
4439 ip->fixp[i] = fix_new (ip->frag, ip->where,
4440 ip->fixp[0]->fx_size, NULL, 0,
4441 FALSE, final_type[i]);
4443 /* Use fx_tcbit to mark compound relocs. */
4444 ip->fixp[0]->fx_tcbit = 1;
4445 ip->fixp[i]->fx_tcbit = 1;
4450 /* Update the register mask information. */
4451 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4452 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4457 insert_into_history (0, 1, ip);
4460 case APPEND_ADD_WITH_NOP:
4462 struct mips_cl_insn *nop;
4464 insert_into_history (0, 1, ip);
4465 nop = get_delay_slot_nop (ip);
4466 add_fixed_insn (nop);
4467 insert_into_history (0, 1, nop);
4468 if (mips_relax.sequence)
4469 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4473 case APPEND_ADD_COMPACT:
4474 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4475 gas_assert (mips_opts.mips16);
4476 ip->insn_opcode |= 0x0080;
4477 find_altered_mips16_opcode (ip);
4479 insert_into_history (0, 1, ip);
4484 struct mips_cl_insn delay = history[0];
4485 if (mips_opts.mips16)
4487 know (delay.frag == ip->frag);
4488 move_insn (ip, delay.frag, delay.where);
4489 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4491 else if (relaxed_branch || delay.frag != ip->frag)
4493 /* Add the delay slot instruction to the end of the
4494 current frag and shrink the fixed part of the
4495 original frag. If the branch occupies the tail of
4496 the latter, move it backwards to cover the gap. */
4497 delay.frag->fr_fix -= branch_disp;
4498 if (delay.frag == ip->frag)
4499 move_insn (ip, ip->frag, ip->where - branch_disp);
4500 add_fixed_insn (&delay);
4504 move_insn (&delay, ip->frag,
4505 ip->where - branch_disp + insn_length (ip));
4506 move_insn (ip, history[0].frag, history[0].where);
4510 insert_into_history (0, 1, &delay);
4515 /* If we have just completed an unconditional branch, clear the history. */
4516 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4517 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4518 mips_no_prev_insn ();
4520 /* We need to emit a label at the end of branch-likely macros. */
4521 if (emit_branch_likely_macro)
4523 emit_branch_likely_macro = FALSE;
4524 micromips_add_label ();
4527 /* We just output an insn, so the next one doesn't have a label. */
4528 mips_clear_insn_labels ();
4531 /* Forget that there was any previous instruction or label. */
4534 mips_no_prev_insn (void)
4536 prev_nop_frag = NULL;
4537 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4538 mips_clear_insn_labels ();
4541 /* This function must be called before we emit something other than
4542 instructions. It is like mips_no_prev_insn except that it inserts
4543 any NOPS that might be needed by previous instructions. */
4546 mips_emit_delays (void)
4548 if (! mips_opts.noreorder)
4550 int nops = nops_for_insn (0, history, NULL);
4554 add_fixed_insn (NOP_INSN);
4555 mips_move_text_labels ();
4558 mips_no_prev_insn ();
4561 /* Start a (possibly nested) noreorder block. */
4564 start_noreorder (void)
4566 if (mips_opts.noreorder == 0)
4571 /* None of the instructions before the .set noreorder can be moved. */
4572 for (i = 0; i < ARRAY_SIZE (history); i++)
4573 history[i].fixed_p = 1;
4575 /* Insert any nops that might be needed between the .set noreorder
4576 block and the previous instructions. We will later remove any
4577 nops that turn out not to be needed. */
4578 nops = nops_for_insn (0, history, NULL);
4581 if (mips_optimize != 0)
4583 /* Record the frag which holds the nop instructions, so
4584 that we can remove them if we don't need them. */
4585 frag_grow (nops * NOP_INSN_SIZE);
4586 prev_nop_frag = frag_now;
4587 prev_nop_frag_holds = nops;
4588 prev_nop_frag_required = 0;
4589 prev_nop_frag_since = 0;
4592 for (; nops > 0; --nops)
4593 add_fixed_insn (NOP_INSN);
4595 /* Move on to a new frag, so that it is safe to simply
4596 decrease the size of prev_nop_frag. */
4597 frag_wane (frag_now);
4599 mips_move_text_labels ();
4601 mips_mark_labels ();
4602 mips_clear_insn_labels ();
4604 mips_opts.noreorder++;
4605 mips_any_noreorder = 1;
4608 /* End a nested noreorder block. */
4611 end_noreorder (void)
4613 mips_opts.noreorder--;
4614 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4616 /* Commit to inserting prev_nop_frag_required nops and go back to
4617 handling nop insertion the .set reorder way. */
4618 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4620 insert_into_history (prev_nop_frag_since,
4621 prev_nop_frag_required, NOP_INSN);
4622 prev_nop_frag = NULL;
4626 /* Set up global variables for the start of a new macro. */
4631 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4632 memset (&mips_macro_warning.first_insn_sizes, 0,
4633 sizeof (mips_macro_warning.first_insn_sizes));
4634 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4635 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4636 && delayed_branch_p (&history[0]));
4637 switch (history[0].insn_mo->pinfo2
4638 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4640 case INSN2_BRANCH_DELAY_32BIT:
4641 mips_macro_warning.delay_slot_length = 4;
4643 case INSN2_BRANCH_DELAY_16BIT:
4644 mips_macro_warning.delay_slot_length = 2;
4647 mips_macro_warning.delay_slot_length = 0;
4650 mips_macro_warning.first_frag = NULL;
4653 /* Given that a macro is longer than one instruction or of the wrong size,
4654 return the appropriate warning for it. Return null if no warning is
4655 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4656 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4657 and RELAX_NOMACRO. */
4660 macro_warning (relax_substateT subtype)
4662 if (subtype & RELAX_DELAY_SLOT)
4663 return _("Macro instruction expanded into multiple instructions"
4664 " in a branch delay slot");
4665 else if (subtype & RELAX_NOMACRO)
4666 return _("Macro instruction expanded into multiple instructions");
4667 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4668 | RELAX_DELAY_SLOT_SIZE_SECOND))
4669 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4670 ? _("Macro instruction expanded into a wrong size instruction"
4671 " in a 16-bit branch delay slot")
4672 : _("Macro instruction expanded into a wrong size instruction"
4673 " in a 32-bit branch delay slot"));
4678 /* Finish up a macro. Emit warnings as appropriate. */
4683 /* Relaxation warning flags. */
4684 relax_substateT subtype = 0;
4686 /* Check delay slot size requirements. */
4687 if (mips_macro_warning.delay_slot_length == 2)
4688 subtype |= RELAX_DELAY_SLOT_16BIT;
4689 if (mips_macro_warning.delay_slot_length != 0)
4691 if (mips_macro_warning.delay_slot_length
4692 != mips_macro_warning.first_insn_sizes[0])
4693 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4694 if (mips_macro_warning.delay_slot_length
4695 != mips_macro_warning.first_insn_sizes[1])
4696 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4699 /* Check instruction count requirements. */
4700 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4702 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4703 subtype |= RELAX_SECOND_LONGER;
4704 if (mips_opts.warn_about_macros)
4705 subtype |= RELAX_NOMACRO;
4706 if (mips_macro_warning.delay_slot_p)
4707 subtype |= RELAX_DELAY_SLOT;
4710 /* If both alternatives fail to fill a delay slot correctly,
4711 emit the warning now. */
4712 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4713 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4718 s = subtype & (RELAX_DELAY_SLOT_16BIT
4719 | RELAX_DELAY_SLOT_SIZE_FIRST
4720 | RELAX_DELAY_SLOT_SIZE_SECOND);
4721 msg = macro_warning (s);
4723 as_warn ("%s", msg);
4727 /* If both implementations are longer than 1 instruction, then emit the
4729 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4734 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4735 msg = macro_warning (s);
4737 as_warn ("%s", msg);
4741 /* If any flags still set, then one implementation might need a warning
4742 and the other either will need one of a different kind or none at all.
4743 Pass any remaining flags over to relaxation. */
4744 if (mips_macro_warning.first_frag != NULL)
4745 mips_macro_warning.first_frag->fr_subtype |= subtype;
4748 /* Instruction operand formats used in macros that vary between
4749 standard MIPS and microMIPS code. */
4751 static const char * const brk_fmt[2] = { "c", "mF" };
4752 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4753 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4754 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4755 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4756 static const char * const mfhl_fmt[2] = { "d", "mj" };
4757 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4758 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4760 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4761 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4762 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4763 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4764 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4765 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4766 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4767 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4769 /* Read a macro's relocation codes from *ARGS and store them in *R.
4770 The first argument in *ARGS will be either the code for a single
4771 relocation or -1 followed by the three codes that make up a
4772 composite relocation. */
4775 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4779 next = va_arg (*args, int);
4781 r[0] = (bfd_reloc_code_real_type) next;
4783 for (i = 0; i < 3; i++)
4784 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4787 /* Build an instruction created by a macro expansion. This is passed
4788 a pointer to the count of instructions created so far, an
4789 expression, the name of the instruction to build, an operand format
4790 string, and corresponding arguments. */
4793 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4795 const struct mips_opcode *mo = NULL;
4796 bfd_reloc_code_real_type r[3];
4797 const struct mips_opcode *amo;
4798 struct hash_control *hash;
4799 struct mips_cl_insn insn;
4802 va_start (args, fmt);
4804 if (mips_opts.mips16)
4806 mips16_macro_build (ep, name, fmt, &args);
4811 r[0] = BFD_RELOC_UNUSED;
4812 r[1] = BFD_RELOC_UNUSED;
4813 r[2] = BFD_RELOC_UNUSED;
4814 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4815 amo = (struct mips_opcode *) hash_find (hash, name);
4817 gas_assert (strcmp (name, amo->name) == 0);
4821 /* Search until we get a match for NAME. It is assumed here that
4822 macros will never generate MDMX, MIPS-3D, or MT instructions.
4823 We try to match an instruction that fulfils the branch delay
4824 slot instruction length requirement (if any) of the previous
4825 instruction. While doing this we record the first instruction
4826 seen that matches all the other conditions and use it anyway
4827 if the requirement cannot be met; we will issue an appropriate
4828 warning later on. */
4829 if (strcmp (fmt, amo->args) == 0
4830 && amo->pinfo != INSN_MACRO
4831 && is_opcode_valid (amo)
4832 && is_size_valid (amo))
4834 if (is_delay_slot_valid (amo))
4844 gas_assert (amo->name);
4846 while (strcmp (name, amo->name) == 0);
4849 create_insn (&insn, mo);
4867 INSERT_OPERAND (mips_opts.micromips,
4868 EXTLSB, insn, va_arg (args, int));
4873 /* Note that in the macro case, these arguments are already
4874 in MSB form. (When handling the instruction in the
4875 non-macro case, these arguments are sizes from which
4876 MSB values must be calculated.) */
4877 INSERT_OPERAND (mips_opts.micromips,
4878 INSMSB, insn, va_arg (args, int));
4884 /* Note that in the macro case, these arguments are already
4885 in MSBD form. (When handling the instruction in the
4886 non-macro case, these arguments are sizes from which
4887 MSBD values must be calculated.) */
4888 INSERT_OPERAND (mips_opts.micromips,
4889 EXTMSBD, insn, va_arg (args, int));
4893 gas_assert (!mips_opts.micromips);
4894 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4903 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
4907 gas_assert (mips_opts.micromips);
4911 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4915 gas_assert (!mips_opts.micromips);
4916 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4920 gas_assert (!mips_opts.micromips);
4922 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4926 if (mips_opts.micromips)
4927 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4929 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4933 gas_assert (!mips_opts.micromips);
4935 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
4939 gas_assert (!mips_opts.micromips);
4941 int tmp = va_arg (args, int);
4943 INSERT_OPERAND (0, RT, insn, tmp);
4944 INSERT_OPERAND (0, RD, insn, tmp);
4950 gas_assert (!mips_opts.micromips);
4951 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
4958 INSERT_OPERAND (mips_opts.micromips,
4959 SHAMT, insn, va_arg (args, int));
4963 gas_assert (!mips_opts.micromips);
4964 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
4968 gas_assert (!mips_opts.micromips);
4969 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
4973 gas_assert (!mips_opts.micromips);
4974 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4978 gas_assert (!mips_opts.micromips);
4979 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
4986 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
4991 macro_read_relocs (&args, r);
4992 gas_assert (*r == BFD_RELOC_GPREL16
4993 || *r == BFD_RELOC_MIPS_HIGHER
4994 || *r == BFD_RELOC_HI16_S
4995 || *r == BFD_RELOC_LO16
4996 || *r == BFD_RELOC_MIPS_GOT_OFST);
5000 macro_read_relocs (&args, r);
5004 macro_read_relocs (&args, r);
5005 gas_assert (ep != NULL
5006 && (ep->X_op == O_constant
5007 || (ep->X_op == O_symbol
5008 && (*r == BFD_RELOC_MIPS_HIGHEST
5009 || *r == BFD_RELOC_HI16_S
5010 || *r == BFD_RELOC_HI16
5011 || *r == BFD_RELOC_GPREL16
5012 || *r == BFD_RELOC_MIPS_GOT_HI16
5013 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5017 gas_assert (ep != NULL);
5020 * This allows macro() to pass an immediate expression for
5021 * creating short branches without creating a symbol.
5023 * We don't allow branch relaxation for these branches, as
5024 * they should only appear in ".set nomacro" anyway.
5026 if (ep->X_op == O_constant)
5028 /* For microMIPS we always use relocations for branches.
5029 So we should not resolve immediate values. */
5030 gas_assert (!mips_opts.micromips);
5032 if ((ep->X_add_number & 3) != 0)
5033 as_bad (_("branch to misaligned address (0x%lx)"),
5034 (unsigned long) ep->X_add_number);
5035 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5036 as_bad (_("branch address range overflow (0x%lx)"),
5037 (unsigned long) ep->X_add_number);
5038 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5042 *r = BFD_RELOC_16_PCREL_S2;
5046 gas_assert (ep != NULL);
5047 *r = BFD_RELOC_MIPS_JMP;
5051 gas_assert (!mips_opts.micromips);
5052 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5056 INSERT_OPERAND (mips_opts.micromips,
5057 CACHE, insn, va_arg (args, unsigned long));
5061 gas_assert (mips_opts.micromips);
5062 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5066 gas_assert (mips_opts.micromips);
5067 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5071 INSERT_OPERAND (mips_opts.micromips,
5072 3BITPOS, insn, va_arg (args, unsigned int));
5076 INSERT_OPERAND (mips_opts.micromips,
5077 OFFSET12, insn, va_arg (args, unsigned long));
5081 gas_assert (mips_opts.micromips);
5082 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5085 case 'm': /* Opcode extension character. */
5086 gas_assert (mips_opts.micromips);
5090 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5094 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5098 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5112 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5114 append_insn (&insn, ep, r, TRUE);
5118 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5121 struct mips_opcode *mo;
5122 struct mips_cl_insn insn;
5123 bfd_reloc_code_real_type r[3]
5124 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5126 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5128 gas_assert (strcmp (name, mo->name) == 0);
5130 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5133 gas_assert (mo->name);
5134 gas_assert (strcmp (name, mo->name) == 0);
5137 create_insn (&insn, mo);
5155 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5160 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5164 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5168 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5178 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5185 regno = va_arg (*args, int);
5186 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5187 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5208 gas_assert (ep != NULL);
5210 if (ep->X_op != O_constant)
5211 *r = (int) BFD_RELOC_UNUSED + c;
5214 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
5215 FALSE, &insn.insn_opcode, &insn.use_extend,
5218 *r = BFD_RELOC_UNUSED;
5224 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5231 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5233 append_insn (&insn, ep, r, TRUE);
5237 * Sign-extend 32-bit mode constants that have bit 31 set and all
5238 * higher bits unset.
5241 normalize_constant_expr (expressionS *ex)
5243 if (ex->X_op == O_constant
5244 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5245 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5250 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5251 * all higher bits unset.
5254 normalize_address_expr (expressionS *ex)
5256 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5257 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5258 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5259 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5264 * Generate a "jalr" instruction with a relocation hint to the called
5265 * function. This occurs in NewABI PIC code.
5268 macro_build_jalr (expressionS *ep, int cprestore)
5270 static const bfd_reloc_code_real_type jalr_relocs[2]
5271 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5272 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5276 if (MIPS_JALR_HINT_P (ep))
5281 if (mips_opts.micromips)
5283 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5284 if (MIPS_JALR_HINT_P (ep))
5285 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5287 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5290 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5291 if (MIPS_JALR_HINT_P (ep))
5292 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5296 * Generate a "lui" instruction.
5299 macro_build_lui (expressionS *ep, int regnum)
5301 gas_assert (! mips_opts.mips16);
5303 if (ep->X_op != O_constant)
5305 gas_assert (ep->X_op == O_symbol);
5306 /* _gp_disp is a special case, used from s_cpload.
5307 __gnu_local_gp is used if mips_no_shared. */
5308 gas_assert (mips_pic == NO_PIC
5310 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5311 || (! mips_in_shared
5312 && strcmp (S_GET_NAME (ep->X_add_symbol),
5313 "__gnu_local_gp") == 0));
5316 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5319 /* Generate a sequence of instructions to do a load or store from a constant
5320 offset off of a base register (breg) into/from a target register (treg),
5321 using AT if necessary. */
5323 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5324 int treg, int breg, int dbl)
5326 gas_assert (ep->X_op == O_constant);
5328 /* Sign-extending 32-bit constants makes their handling easier. */
5330 normalize_constant_expr (ep);
5332 /* Right now, this routine can only handle signed 32-bit constants. */
5333 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5334 as_warn (_("operand overflow"));
5336 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5338 /* Signed 16-bit offset will fit in the op. Easy! */
5339 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5343 /* 32-bit offset, need multiple instructions and AT, like:
5344 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5345 addu $tempreg,$tempreg,$breg
5346 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5347 to handle the complete offset. */
5348 macro_build_lui (ep, AT);
5349 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5350 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5353 as_bad (_("Macro used $at after \".set noat\""));
5358 * Generates code to set the $at register to true (one)
5359 * if reg is less than the immediate expression.
5362 set_at (int reg, int unsignedp)
5364 if (imm_expr.X_op == O_constant
5365 && imm_expr.X_add_number >= -0x8000
5366 && imm_expr.X_add_number < 0x8000)
5367 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5368 AT, reg, BFD_RELOC_LO16);
5371 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5372 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5376 /* Warn if an expression is not a constant. */
5379 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5381 if (ex->X_op == O_big)
5382 as_bad (_("unsupported large constant"));
5383 else if (ex->X_op != O_constant)
5384 as_bad (_("Instruction %s requires absolute expression"),
5387 if (HAVE_32BIT_GPRS)
5388 normalize_constant_expr (ex);
5391 /* Count the leading zeroes by performing a binary chop. This is a
5392 bulky bit of source, but performance is a LOT better for the
5393 majority of values than a simple loop to count the bits:
5394 for (lcnt = 0; (lcnt < 32); lcnt++)
5395 if ((v) & (1 << (31 - lcnt)))
5397 However it is not code size friendly, and the gain will drop a bit
5398 on certain cached systems.
5400 #define COUNT_TOP_ZEROES(v) \
5401 (((v) & ~0xffff) == 0 \
5402 ? ((v) & ~0xff) == 0 \
5403 ? ((v) & ~0xf) == 0 \
5404 ? ((v) & ~0x3) == 0 \
5405 ? ((v) & ~0x1) == 0 \
5410 : ((v) & ~0x7) == 0 \
5413 : ((v) & ~0x3f) == 0 \
5414 ? ((v) & ~0x1f) == 0 \
5417 : ((v) & ~0x7f) == 0 \
5420 : ((v) & ~0xfff) == 0 \
5421 ? ((v) & ~0x3ff) == 0 \
5422 ? ((v) & ~0x1ff) == 0 \
5425 : ((v) & ~0x7ff) == 0 \
5428 : ((v) & ~0x3fff) == 0 \
5429 ? ((v) & ~0x1fff) == 0 \
5432 : ((v) & ~0x7fff) == 0 \
5435 : ((v) & ~0xffffff) == 0 \
5436 ? ((v) & ~0xfffff) == 0 \
5437 ? ((v) & ~0x3ffff) == 0 \
5438 ? ((v) & ~0x1ffff) == 0 \
5441 : ((v) & ~0x7ffff) == 0 \
5444 : ((v) & ~0x3fffff) == 0 \
5445 ? ((v) & ~0x1fffff) == 0 \
5448 : ((v) & ~0x7fffff) == 0 \
5451 : ((v) & ~0xfffffff) == 0 \
5452 ? ((v) & ~0x3ffffff) == 0 \
5453 ? ((v) & ~0x1ffffff) == 0 \
5456 : ((v) & ~0x7ffffff) == 0 \
5459 : ((v) & ~0x3fffffff) == 0 \
5460 ? ((v) & ~0x1fffffff) == 0 \
5463 : ((v) & ~0x7fffffff) == 0 \
5468 * This routine generates the least number of instructions necessary to load
5469 * an absolute expression value into a register.
5472 load_register (int reg, expressionS *ep, int dbl)
5475 expressionS hi32, lo32;
5477 if (ep->X_op != O_big)
5479 gas_assert (ep->X_op == O_constant);
5481 /* Sign-extending 32-bit constants makes their handling easier. */
5483 normalize_constant_expr (ep);
5485 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5487 /* We can handle 16 bit signed values with an addiu to
5488 $zero. No need to ever use daddiu here, since $zero and
5489 the result are always correct in 32 bit mode. */
5490 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5493 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5495 /* We can handle 16 bit unsigned values with an ori to
5497 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5500 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5502 /* 32 bit values require an lui. */
5503 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5504 if ((ep->X_add_number & 0xffff) != 0)
5505 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5510 /* The value is larger than 32 bits. */
5512 if (!dbl || HAVE_32BIT_GPRS)
5516 sprintf_vma (value, ep->X_add_number);
5517 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5518 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5522 if (ep->X_op != O_big)
5525 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5526 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5527 hi32.X_add_number &= 0xffffffff;
5529 lo32.X_add_number &= 0xffffffff;
5533 gas_assert (ep->X_add_number > 2);
5534 if (ep->X_add_number == 3)
5535 generic_bignum[3] = 0;
5536 else if (ep->X_add_number > 4)
5537 as_bad (_("Number larger than 64 bits"));
5538 lo32.X_op = O_constant;
5539 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5540 hi32.X_op = O_constant;
5541 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5544 if (hi32.X_add_number == 0)
5549 unsigned long hi, lo;
5551 if (hi32.X_add_number == (offsetT) 0xffffffff)
5553 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5555 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5558 if (lo32.X_add_number & 0x80000000)
5560 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5561 if (lo32.X_add_number & 0xffff)
5562 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5567 /* Check for 16bit shifted constant. We know that hi32 is
5568 non-zero, so start the mask on the first bit of the hi32
5573 unsigned long himask, lomask;
5577 himask = 0xffff >> (32 - shift);
5578 lomask = (0xffff << shift) & 0xffffffff;
5582 himask = 0xffff << (shift - 32);
5585 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5586 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5590 tmp.X_op = O_constant;
5592 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5593 | (lo32.X_add_number >> shift));
5595 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5596 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5597 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5598 reg, reg, (shift >= 32) ? shift - 32 : shift);
5603 while (shift <= (64 - 16));
5605 /* Find the bit number of the lowest one bit, and store the
5606 shifted value in hi/lo. */
5607 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5608 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5612 while ((lo & 1) == 0)
5617 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5623 while ((hi & 1) == 0)
5632 /* Optimize if the shifted value is a (power of 2) - 1. */
5633 if ((hi == 0 && ((lo + 1) & lo) == 0)
5634 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5636 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5641 /* This instruction will set the register to be all
5643 tmp.X_op = O_constant;
5644 tmp.X_add_number = (offsetT) -1;
5645 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5649 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5650 reg, reg, (bit >= 32) ? bit - 32 : bit);
5652 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5653 reg, reg, (shift >= 32) ? shift - 32 : shift);
5658 /* Sign extend hi32 before calling load_register, because we can
5659 generally get better code when we load a sign extended value. */
5660 if ((hi32.X_add_number & 0x80000000) != 0)
5661 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5662 load_register (reg, &hi32, 0);
5665 if ((lo32.X_add_number & 0xffff0000) == 0)
5669 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5677 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5679 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5680 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5686 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5690 mid16.X_add_number >>= 16;
5691 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5692 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5695 if ((lo32.X_add_number & 0xffff) != 0)
5696 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5700 load_delay_nop (void)
5702 if (!gpr_interlocks)
5703 macro_build (NULL, "nop", "");
5706 /* Load an address into a register. */
5709 load_address (int reg, expressionS *ep, int *used_at)
5711 if (ep->X_op != O_constant
5712 && ep->X_op != O_symbol)
5714 as_bad (_("expression too complex"));
5715 ep->X_op = O_constant;
5718 if (ep->X_op == O_constant)
5720 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5724 if (mips_pic == NO_PIC)
5726 /* If this is a reference to a GP relative symbol, we want
5727 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5729 lui $reg,<sym> (BFD_RELOC_HI16_S)
5730 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5731 If we have an addend, we always use the latter form.
5733 With 64bit address space and a usable $at we want
5734 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5735 lui $at,<sym> (BFD_RELOC_HI16_S)
5736 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5737 daddiu $at,<sym> (BFD_RELOC_LO16)
5741 If $at is already in use, we use a path which is suboptimal
5742 on superscalar processors.
5743 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5744 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5746 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5748 daddiu $reg,<sym> (BFD_RELOC_LO16)
5750 For GP relative symbols in 64bit address space we can use
5751 the same sequence as in 32bit address space. */
5752 if (HAVE_64BIT_SYMBOLS)
5754 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5755 && !nopic_need_relax (ep->X_add_symbol, 1))
5757 relax_start (ep->X_add_symbol);
5758 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5759 mips_gp_register, BFD_RELOC_GPREL16);
5763 if (*used_at == 0 && mips_opts.at)
5765 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5766 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5767 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5768 BFD_RELOC_MIPS_HIGHER);
5769 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5770 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5771 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5776 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5777 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5778 BFD_RELOC_MIPS_HIGHER);
5779 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5780 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5781 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5782 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5785 if (mips_relax.sequence)
5790 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5791 && !nopic_need_relax (ep->X_add_symbol, 1))
5793 relax_start (ep->X_add_symbol);
5794 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5795 mips_gp_register, BFD_RELOC_GPREL16);
5798 macro_build_lui (ep, reg);
5799 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5800 reg, reg, BFD_RELOC_LO16);
5801 if (mips_relax.sequence)
5805 else if (!mips_big_got)
5809 /* If this is a reference to an external symbol, we want
5810 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5812 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5814 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5815 If there is a constant, it must be added in after.
5817 If we have NewABI, we want
5818 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5819 unless we're referencing a global symbol with a non-zero
5820 offset, in which case cst must be added separately. */
5823 if (ep->X_add_number)
5825 ex.X_add_number = ep->X_add_number;
5826 ep->X_add_number = 0;
5827 relax_start (ep->X_add_symbol);
5828 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5829 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5830 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5831 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5832 ex.X_op = O_constant;
5833 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5834 reg, reg, BFD_RELOC_LO16);
5835 ep->X_add_number = ex.X_add_number;
5838 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5839 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5840 if (mips_relax.sequence)
5845 ex.X_add_number = ep->X_add_number;
5846 ep->X_add_number = 0;
5847 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5848 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5850 relax_start (ep->X_add_symbol);
5852 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5856 if (ex.X_add_number != 0)
5858 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5859 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5860 ex.X_op = O_constant;
5861 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5862 reg, reg, BFD_RELOC_LO16);
5866 else if (mips_big_got)
5870 /* This is the large GOT case. If this is a reference to an
5871 external symbol, we want
5872 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5874 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5876 Otherwise, for a reference to a local symbol in old ABI, we want
5877 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5879 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5880 If there is a constant, it must be added in after.
5882 In the NewABI, for local symbols, with or without offsets, we want:
5883 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5884 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5888 ex.X_add_number = ep->X_add_number;
5889 ep->X_add_number = 0;
5890 relax_start (ep->X_add_symbol);
5891 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5892 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5893 reg, reg, mips_gp_register);
5894 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5895 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5896 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5897 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5898 else if (ex.X_add_number)
5900 ex.X_op = O_constant;
5901 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5905 ep->X_add_number = ex.X_add_number;
5907 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5908 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5909 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5910 BFD_RELOC_MIPS_GOT_OFST);
5915 ex.X_add_number = ep->X_add_number;
5916 ep->X_add_number = 0;
5917 relax_start (ep->X_add_symbol);
5918 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5919 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5920 reg, reg, mips_gp_register);
5921 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5922 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5924 if (reg_needs_delay (mips_gp_register))
5926 /* We need a nop before loading from $gp. This special
5927 check is required because the lui which starts the main
5928 instruction stream does not refer to $gp, and so will not
5929 insert the nop which may be required. */
5930 macro_build (NULL, "nop", "");
5932 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5933 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5935 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5939 if (ex.X_add_number != 0)
5941 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5942 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5943 ex.X_op = O_constant;
5944 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5952 if (!mips_opts.at && *used_at == 1)
5953 as_bad (_("Macro used $at after \".set noat\""));
5956 /* Move the contents of register SOURCE into register DEST. */
5959 move_register (int dest, int source)
5961 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5962 instruction specifically requires a 32-bit one. */
5963 if (mips_opts.micromips
5964 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5965 macro_build (NULL, "move", "mp,mj", dest, source);
5967 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5971 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5972 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5973 The two alternatives are:
5975 Global symbol Local sybmol
5976 ------------- ------------
5977 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5979 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5981 load_got_offset emits the first instruction and add_got_offset
5982 emits the second for a 16-bit offset or add_got_offset_hilo emits
5983 a sequence to add a 32-bit offset using a scratch register. */
5986 load_got_offset (int dest, expressionS *local)
5991 global.X_add_number = 0;
5993 relax_start (local->X_add_symbol);
5994 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5995 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5997 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5998 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6003 add_got_offset (int dest, expressionS *local)
6007 global.X_op = O_constant;
6008 global.X_op_symbol = NULL;
6009 global.X_add_symbol = NULL;
6010 global.X_add_number = local->X_add_number;
6012 relax_start (local->X_add_symbol);
6013 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6014 dest, dest, BFD_RELOC_LO16);
6016 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6021 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6024 int hold_mips_optimize;
6026 global.X_op = O_constant;
6027 global.X_op_symbol = NULL;
6028 global.X_add_symbol = NULL;
6029 global.X_add_number = local->X_add_number;
6031 relax_start (local->X_add_symbol);
6032 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6034 /* Set mips_optimize around the lui instruction to avoid
6035 inserting an unnecessary nop after the lw. */
6036 hold_mips_optimize = mips_optimize;
6038 macro_build_lui (&global, tmp);
6039 mips_optimize = hold_mips_optimize;
6040 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6043 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6046 /* Emit a sequence of instructions to emulate a branch likely operation.
6047 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6048 is its complementing branch with the original condition negated.
6049 CALL is set if the original branch specified the link operation.
6050 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6052 Code like this is produced in the noreorder mode:
6057 delay slot (executed only if branch taken)
6065 delay slot (executed only if branch taken)
6068 In the reorder mode the delay slot would be filled with a nop anyway,
6069 so code produced is simply:
6074 This function is used when producing code for the microMIPS ASE that
6075 does not implement branch likely instructions in hardware. */
6078 macro_build_branch_likely (const char *br, const char *brneg,
6079 int call, expressionS *ep, const char *fmt,
6080 unsigned int sreg, unsigned int treg)
6082 int noreorder = mips_opts.noreorder;
6085 gas_assert (mips_opts.micromips);
6089 micromips_label_expr (&expr1);
6090 macro_build (&expr1, brneg, fmt, sreg, treg);
6091 macro_build (NULL, "nop", "");
6092 macro_build (ep, call ? "bal" : "b", "p");
6094 /* Set to true so that append_insn adds a label. */
6095 emit_branch_likely_macro = TRUE;
6099 macro_build (ep, br, fmt, sreg, treg);
6100 macro_build (NULL, "nop", "");
6105 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6106 the condition code tested. EP specifies the branch target. */
6109 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6136 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6139 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6140 the register tested. EP specifies the branch target. */
6143 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6145 const char *brneg = NULL;
6155 br = mips_opts.micromips ? "bgez" : "bgezl";
6159 gas_assert (mips_opts.micromips);
6168 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6175 br = mips_opts.micromips ? "blez" : "blezl";
6182 br = mips_opts.micromips ? "bltz" : "bltzl";
6186 gas_assert (mips_opts.micromips);
6194 if (mips_opts.micromips && brneg)
6195 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6197 macro_build (ep, br, "s,p", sreg);
6200 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6201 TREG as the registers tested. EP specifies the branch target. */
6204 macro_build_branch_rsrt (int type, expressionS *ep,
6205 unsigned int sreg, unsigned int treg)
6207 const char *brneg = NULL;
6219 br = mips_opts.micromips ? "beq" : "beql";
6228 br = mips_opts.micromips ? "bne" : "bnel";
6234 if (mips_opts.micromips && brneg)
6235 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6237 macro_build (ep, br, "s,t,p", sreg, treg);
6242 * This routine implements the seemingly endless macro or synthesized
6243 * instructions and addressing modes in the mips assembly language. Many
6244 * of these macros are simple and are similar to each other. These could
6245 * probably be handled by some kind of table or grammar approach instead of
6246 * this verbose method. Others are not simple macros but are more like
6247 * optimizing code generation.
6248 * One interesting optimization is when several store macros appear
6249 * consecutively that would load AT with the upper half of the same address.
6250 * The ensuing load upper instructions are ommited. This implies some kind
6251 * of global optimization. We currently only optimize within a single macro.
6252 * For many of the load and store macros if the address is specified as a
6253 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6254 * first load register 'at' with zero and use it as the base register. The
6255 * mips assembler simply uses register $zero. Just one tiny optimization
6259 macro (struct mips_cl_insn *ip)
6261 unsigned int treg, sreg, dreg, breg;
6262 unsigned int tempreg;
6265 expressionS label_expr;
6284 bfd_reloc_code_real_type r;
6285 int hold_mips_optimize;
6287 gas_assert (! mips_opts.mips16);
6289 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6290 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6291 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6292 mask = ip->insn_mo->mask;
6294 label_expr.X_op = O_constant;
6295 label_expr.X_op_symbol = NULL;
6296 label_expr.X_add_symbol = NULL;
6297 label_expr.X_add_number = 0;
6299 expr1.X_op = O_constant;
6300 expr1.X_op_symbol = NULL;
6301 expr1.X_add_symbol = NULL;
6302 expr1.X_add_number = 1;
6317 if (mips_opts.micromips)
6318 micromips_label_expr (&label_expr);
6320 label_expr.X_add_number = 8;
6321 macro_build (&label_expr, "bgez", "s,p", sreg);
6323 macro_build (NULL, "nop", "");
6325 move_register (dreg, sreg);
6326 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6327 if (mips_opts.micromips)
6328 micromips_add_label ();
6345 if (!mips_opts.micromips)
6347 if (imm_expr.X_op == O_constant
6348 && imm_expr.X_add_number >= -0x200
6349 && imm_expr.X_add_number < 0x200)
6351 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6360 if (imm_expr.X_op == O_constant
6361 && imm_expr.X_add_number >= -0x8000
6362 && imm_expr.X_add_number < 0x8000)
6364 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6369 load_register (AT, &imm_expr, dbl);
6370 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6389 if (imm_expr.X_op == O_constant
6390 && imm_expr.X_add_number >= 0
6391 && imm_expr.X_add_number < 0x10000)
6393 if (mask != M_NOR_I)
6394 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6397 macro_build (&imm_expr, "ori", "t,r,i",
6398 treg, sreg, BFD_RELOC_LO16);
6399 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6405 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6406 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6410 switch (imm_expr.X_add_number)
6413 macro_build (NULL, "nop", "");
6416 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6420 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6421 (int) imm_expr.X_add_number);
6424 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6425 (unsigned long) imm_expr.X_add_number);
6434 gas_assert (mips_opts.micromips);
6435 macro_build_branch_ccl (mask, &offset_expr,
6436 EXTRACT_OPERAND (1, BCC, *ip));
6443 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6449 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6454 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6461 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6463 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6467 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6468 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6469 &offset_expr, AT, ZERO);
6479 macro_build_branch_rs (mask, &offset_expr, sreg);
6485 /* Check for > max integer. */
6486 maxnum = 0x7fffffff;
6487 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6494 if (imm_expr.X_op == O_constant
6495 && imm_expr.X_add_number >= maxnum
6496 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6499 /* Result is always false. */
6501 macro_build (NULL, "nop", "");
6503 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6506 if (imm_expr.X_op != O_constant)
6507 as_bad (_("Unsupported large constant"));
6508 ++imm_expr.X_add_number;
6512 if (mask == M_BGEL_I)
6514 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6516 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6517 &offset_expr, sreg);
6520 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6522 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6523 &offset_expr, sreg);
6526 maxnum = 0x7fffffff;
6527 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6534 maxnum = - maxnum - 1;
6535 if (imm_expr.X_op == O_constant
6536 && imm_expr.X_add_number <= maxnum
6537 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6540 /* result is always true */
6541 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6542 macro_build (&offset_expr, "b", "p");
6547 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6548 &offset_expr, AT, ZERO);
6557 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6558 &offset_expr, ZERO, treg);
6562 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6563 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6564 &offset_expr, AT, ZERO);
6573 && imm_expr.X_op == O_constant
6574 && imm_expr.X_add_number == -1))
6576 if (imm_expr.X_op != O_constant)
6577 as_bad (_("Unsupported large constant"));
6578 ++imm_expr.X_add_number;
6582 if (mask == M_BGEUL_I)
6584 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6586 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6587 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6588 &offset_expr, sreg, ZERO);
6593 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6594 &offset_expr, AT, ZERO);
6602 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6604 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6608 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6609 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6610 &offset_expr, AT, ZERO);
6618 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6619 &offset_expr, sreg, ZERO);
6625 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6626 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6627 &offset_expr, AT, ZERO);
6635 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6637 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6641 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6642 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6643 &offset_expr, AT, ZERO);
6650 maxnum = 0x7fffffff;
6651 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6658 if (imm_expr.X_op == O_constant
6659 && imm_expr.X_add_number >= maxnum
6660 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6662 if (imm_expr.X_op != O_constant)
6663 as_bad (_("Unsupported large constant"));
6664 ++imm_expr.X_add_number;
6668 if (mask == M_BLTL_I)
6670 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6671 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6672 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6673 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6678 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6679 &offset_expr, AT, ZERO);
6687 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6688 &offset_expr, sreg, ZERO);
6694 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6695 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6696 &offset_expr, AT, ZERO);
6705 && imm_expr.X_op == O_constant
6706 && imm_expr.X_add_number == -1))
6708 if (imm_expr.X_op != O_constant)
6709 as_bad (_("Unsupported large constant"));
6710 ++imm_expr.X_add_number;
6714 if (mask == M_BLTUL_I)
6716 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6718 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6719 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6720 &offset_expr, sreg, ZERO);
6725 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6726 &offset_expr, AT, ZERO);
6734 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6736 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6740 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6741 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6742 &offset_expr, AT, ZERO);
6752 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6753 &offset_expr, ZERO, treg);
6757 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6758 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6759 &offset_expr, AT, ZERO);
6765 /* Use unsigned arithmetic. */
6769 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6771 as_bad (_("Unsupported large constant"));
6776 pos = imm_expr.X_add_number;
6777 size = imm2_expr.X_add_number;
6782 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6785 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6787 as_bad (_("Improper extract size (%lu, position %lu)"),
6788 (unsigned long) size, (unsigned long) pos);
6792 if (size <= 32 && pos < 32)
6797 else if (size <= 32)
6807 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6814 /* Use unsigned arithmetic. */
6818 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6820 as_bad (_("Unsupported large constant"));
6825 pos = imm_expr.X_add_number;
6826 size = imm2_expr.X_add_number;
6831 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6834 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6836 as_bad (_("Improper insert size (%lu, position %lu)"),
6837 (unsigned long) size, (unsigned long) pos);
6841 if (pos < 32 && (pos + size - 1) < 32)
6856 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6857 (int) (pos + size - 1));
6873 as_warn (_("Divide by zero."));
6875 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6877 macro_build (NULL, "break", BRK_FMT, 7);
6884 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6885 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6889 if (mips_opts.micromips)
6890 micromips_label_expr (&label_expr);
6892 label_expr.X_add_number = 8;
6893 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6894 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6895 macro_build (NULL, "break", BRK_FMT, 7);
6896 if (mips_opts.micromips)
6897 micromips_add_label ();
6899 expr1.X_add_number = -1;
6901 load_register (AT, &expr1, dbl);
6902 if (mips_opts.micromips)
6903 micromips_label_expr (&label_expr);
6905 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6906 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6909 expr1.X_add_number = 1;
6910 load_register (AT, &expr1, dbl);
6911 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6915 expr1.X_add_number = 0x80000000;
6916 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6920 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6921 /* We want to close the noreorder block as soon as possible, so
6922 that later insns are available for delay slot filling. */
6927 if (mips_opts.micromips)
6928 micromips_label_expr (&label_expr);
6930 label_expr.X_add_number = 8;
6931 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6932 macro_build (NULL, "nop", "");
6934 /* We want to close the noreorder block as soon as possible, so
6935 that later insns are available for delay slot filling. */
6938 macro_build (NULL, "break", BRK_FMT, 6);
6940 if (mips_opts.micromips)
6941 micromips_add_label ();
6942 macro_build (NULL, s, MFHL_FMT, dreg);
6981 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6983 as_warn (_("Divide by zero."));
6985 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6987 macro_build (NULL, "break", BRK_FMT, 7);
6990 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6992 if (strcmp (s2, "mflo") == 0)
6993 move_register (dreg, sreg);
6995 move_register (dreg, ZERO);
6998 if (imm_expr.X_op == O_constant
6999 && imm_expr.X_add_number == -1
7000 && s[strlen (s) - 1] != 'u')
7002 if (strcmp (s2, "mflo") == 0)
7004 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7007 move_register (dreg, ZERO);
7012 load_register (AT, &imm_expr, dbl);
7013 macro_build (NULL, s, "z,s,t", sreg, AT);
7014 macro_build (NULL, s2, MFHL_FMT, dreg);
7036 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7037 macro_build (NULL, s, "z,s,t", sreg, treg);
7038 /* We want to close the noreorder block as soon as possible, so
7039 that later insns are available for delay slot filling. */
7044 if (mips_opts.micromips)
7045 micromips_label_expr (&label_expr);
7047 label_expr.X_add_number = 8;
7048 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7049 macro_build (NULL, s, "z,s,t", sreg, treg);
7051 /* We want to close the noreorder block as soon as possible, so
7052 that later insns are available for delay slot filling. */
7054 macro_build (NULL, "break", BRK_FMT, 7);
7055 if (mips_opts.micromips)
7056 micromips_add_label ();
7058 macro_build (NULL, s2, MFHL_FMT, dreg);
7070 /* Load the address of a symbol into a register. If breg is not
7071 zero, we then add a base register to it. */
7073 if (dbl && HAVE_32BIT_GPRS)
7074 as_warn (_("dla used to load 32-bit register"));
7076 if (!dbl && HAVE_64BIT_OBJECTS)
7077 as_warn (_("la used to load 64-bit address"));
7079 if (offset_expr.X_op == O_constant
7080 && offset_expr.X_add_number >= -0x8000
7081 && offset_expr.X_add_number < 0x8000)
7083 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7084 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7088 if (mips_opts.at && (treg == breg))
7098 if (offset_expr.X_op != O_symbol
7099 && offset_expr.X_op != O_constant)
7101 as_bad (_("Expression too complex"));
7102 offset_expr.X_op = O_constant;
7105 if (offset_expr.X_op == O_constant)
7106 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7107 else if (mips_pic == NO_PIC)
7109 /* If this is a reference to a GP relative symbol, we want
7110 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7112 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7113 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7114 If we have a constant, we need two instructions anyhow,
7115 so we may as well always use the latter form.
7117 With 64bit address space and a usable $at we want
7118 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7119 lui $at,<sym> (BFD_RELOC_HI16_S)
7120 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7121 daddiu $at,<sym> (BFD_RELOC_LO16)
7123 daddu $tempreg,$tempreg,$at
7125 If $at is already in use, we use a path which is suboptimal
7126 on superscalar processors.
7127 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7128 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7130 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7132 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7134 For GP relative symbols in 64bit address space we can use
7135 the same sequence as in 32bit address space. */
7136 if (HAVE_64BIT_SYMBOLS)
7138 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7139 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7141 relax_start (offset_expr.X_add_symbol);
7142 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7143 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7147 if (used_at == 0 && mips_opts.at)
7149 macro_build (&offset_expr, "lui", LUI_FMT,
7150 tempreg, BFD_RELOC_MIPS_HIGHEST);
7151 macro_build (&offset_expr, "lui", LUI_FMT,
7152 AT, BFD_RELOC_HI16_S);
7153 macro_build (&offset_expr, "daddiu", "t,r,j",
7154 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7155 macro_build (&offset_expr, "daddiu", "t,r,j",
7156 AT, AT, BFD_RELOC_LO16);
7157 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7158 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7163 macro_build (&offset_expr, "lui", LUI_FMT,
7164 tempreg, BFD_RELOC_MIPS_HIGHEST);
7165 macro_build (&offset_expr, "daddiu", "t,r,j",
7166 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7167 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7168 macro_build (&offset_expr, "daddiu", "t,r,j",
7169 tempreg, tempreg, BFD_RELOC_HI16_S);
7170 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7171 macro_build (&offset_expr, "daddiu", "t,r,j",
7172 tempreg, tempreg, BFD_RELOC_LO16);
7175 if (mips_relax.sequence)
7180 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7181 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7183 relax_start (offset_expr.X_add_symbol);
7184 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7185 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7188 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7189 as_bad (_("Offset too large"));
7190 macro_build_lui (&offset_expr, tempreg);
7191 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7192 tempreg, tempreg, BFD_RELOC_LO16);
7193 if (mips_relax.sequence)
7197 else if (!mips_big_got && !HAVE_NEWABI)
7199 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7201 /* If this is a reference to an external symbol, and there
7202 is no constant, we want
7203 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7204 or for lca or if tempreg is PIC_CALL_REG
7205 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7206 For a local symbol, we want
7207 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7209 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7211 If we have a small constant, and this is a reference to
7212 an external symbol, we want
7213 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7215 addiu $tempreg,$tempreg,<constant>
7216 For a local symbol, we want the same instruction
7217 sequence, but we output a BFD_RELOC_LO16 reloc on the
7220 If we have a large constant, and this is a reference to
7221 an external symbol, we want
7222 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7223 lui $at,<hiconstant>
7224 addiu $at,$at,<loconstant>
7225 addu $tempreg,$tempreg,$at
7226 For a local symbol, we want the same instruction
7227 sequence, but we output a BFD_RELOC_LO16 reloc on the
7231 if (offset_expr.X_add_number == 0)
7233 if (mips_pic == SVR4_PIC
7235 && (call || tempreg == PIC_CALL_REG))
7236 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7238 relax_start (offset_expr.X_add_symbol);
7239 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7240 lw_reloc_type, mips_gp_register);
7243 /* We're going to put in an addu instruction using
7244 tempreg, so we may as well insert the nop right
7249 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7250 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7252 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7253 tempreg, tempreg, BFD_RELOC_LO16);
7255 /* FIXME: If breg == 0, and the next instruction uses
7256 $tempreg, then if this variant case is used an extra
7257 nop will be generated. */
7259 else if (offset_expr.X_add_number >= -0x8000
7260 && offset_expr.X_add_number < 0x8000)
7262 load_got_offset (tempreg, &offset_expr);
7264 add_got_offset (tempreg, &offset_expr);
7268 expr1.X_add_number = offset_expr.X_add_number;
7269 offset_expr.X_add_number =
7270 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
7271 load_got_offset (tempreg, &offset_expr);
7272 offset_expr.X_add_number = expr1.X_add_number;
7273 /* If we are going to add in a base register, and the
7274 target register and the base register are the same,
7275 then we are using AT as a temporary register. Since
7276 we want to load the constant into AT, we add our
7277 current AT (from the global offset table) and the
7278 register into the register now, and pretend we were
7279 not using a base register. */
7283 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7288 add_got_offset_hilo (tempreg, &offset_expr, AT);
7292 else if (!mips_big_got && HAVE_NEWABI)
7294 int add_breg_early = 0;
7296 /* If this is a reference to an external, and there is no
7297 constant, or local symbol (*), with or without a
7299 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7300 or for lca or if tempreg is PIC_CALL_REG
7301 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7303 If we have a small constant, and this is a reference to
7304 an external symbol, we want
7305 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7306 addiu $tempreg,$tempreg,<constant>
7308 If we have a large constant, and this is a reference to
7309 an external symbol, we want
7310 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7311 lui $at,<hiconstant>
7312 addiu $at,$at,<loconstant>
7313 addu $tempreg,$tempreg,$at
7315 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7316 local symbols, even though it introduces an additional
7319 if (offset_expr.X_add_number)
7321 expr1.X_add_number = offset_expr.X_add_number;
7322 offset_expr.X_add_number = 0;
7324 relax_start (offset_expr.X_add_symbol);
7325 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7326 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7328 if (expr1.X_add_number >= -0x8000
7329 && expr1.X_add_number < 0x8000)
7331 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7332 tempreg, tempreg, BFD_RELOC_LO16);
7334 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7336 /* If we are going to add in a base register, and the
7337 target register and the base register are the same,
7338 then we are using AT as a temporary register. Since
7339 we want to load the constant into AT, we add our
7340 current AT (from the global offset table) and the
7341 register into the register now, and pretend we were
7342 not using a base register. */
7347 gas_assert (tempreg == AT);
7348 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7354 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7355 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7361 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7364 offset_expr.X_add_number = expr1.X_add_number;
7366 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7367 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7370 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7371 treg, tempreg, breg);
7377 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7379 relax_start (offset_expr.X_add_symbol);
7380 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7381 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7383 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7384 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7389 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7390 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7393 else if (mips_big_got && !HAVE_NEWABI)
7396 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7397 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7398 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7400 /* This is the large GOT case. If this is a reference to an
7401 external symbol, and there is no constant, we want
7402 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7403 addu $tempreg,$tempreg,$gp
7404 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7405 or for lca or if tempreg is PIC_CALL_REG
7406 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7407 addu $tempreg,$tempreg,$gp
7408 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7409 For a local symbol, we want
7410 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7412 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7414 If we have a small constant, and this is a reference to
7415 an external symbol, we want
7416 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7417 addu $tempreg,$tempreg,$gp
7418 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7420 addiu $tempreg,$tempreg,<constant>
7421 For a local symbol, we want
7422 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7424 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7426 If we have a large constant, and this is a reference to
7427 an external symbol, we want
7428 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7429 addu $tempreg,$tempreg,$gp
7430 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7431 lui $at,<hiconstant>
7432 addiu $at,$at,<loconstant>
7433 addu $tempreg,$tempreg,$at
7434 For a local symbol, we want
7435 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7436 lui $at,<hiconstant>
7437 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7438 addu $tempreg,$tempreg,$at
7441 expr1.X_add_number = offset_expr.X_add_number;
7442 offset_expr.X_add_number = 0;
7443 relax_start (offset_expr.X_add_symbol);
7444 gpdelay = reg_needs_delay (mips_gp_register);
7445 if (expr1.X_add_number == 0 && breg == 0
7446 && (call || tempreg == PIC_CALL_REG))
7448 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7449 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7451 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7452 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7453 tempreg, tempreg, mips_gp_register);
7454 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7455 tempreg, lw_reloc_type, tempreg);
7456 if (expr1.X_add_number == 0)
7460 /* We're going to put in an addu instruction using
7461 tempreg, so we may as well insert the nop right
7466 else if (expr1.X_add_number >= -0x8000
7467 && expr1.X_add_number < 0x8000)
7470 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7471 tempreg, tempreg, BFD_RELOC_LO16);
7475 /* If we are going to add in a base register, and the
7476 target register and the base register are the same,
7477 then we are using AT as a temporary register. Since
7478 we want to load the constant into AT, we add our
7479 current AT (from the global offset table) and the
7480 register into the register now, and pretend we were
7481 not using a base register. */
7486 gas_assert (tempreg == AT);
7488 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7493 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7494 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7498 offset_expr.X_add_number =
7499 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
7504 /* This is needed because this instruction uses $gp, but
7505 the first instruction on the main stream does not. */
7506 macro_build (NULL, "nop", "");
7509 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7510 local_reloc_type, mips_gp_register);
7511 if (expr1.X_add_number >= -0x8000
7512 && expr1.X_add_number < 0x8000)
7515 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7516 tempreg, tempreg, BFD_RELOC_LO16);
7517 /* FIXME: If add_number is 0, and there was no base
7518 register, the external symbol case ended with a load,
7519 so if the symbol turns out to not be external, and
7520 the next instruction uses tempreg, an unnecessary nop
7521 will be inserted. */
7527 /* We must add in the base register now, as in the
7528 external symbol case. */
7529 gas_assert (tempreg == AT);
7531 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7534 /* We set breg to 0 because we have arranged to add
7535 it in in both cases. */
7539 macro_build_lui (&expr1, AT);
7540 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7541 AT, AT, BFD_RELOC_LO16);
7542 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7543 tempreg, tempreg, AT);
7548 else if (mips_big_got && HAVE_NEWABI)
7550 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7551 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7552 int add_breg_early = 0;
7554 /* This is the large GOT case. If this is a reference to an
7555 external symbol, and there is no constant, we want
7556 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7557 add $tempreg,$tempreg,$gp
7558 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7559 or for lca or if tempreg is PIC_CALL_REG
7560 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7561 add $tempreg,$tempreg,$gp
7562 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7564 If we have a small constant, and this is a reference to
7565 an external symbol, we want
7566 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7567 add $tempreg,$tempreg,$gp
7568 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7569 addi $tempreg,$tempreg,<constant>
7571 If we have a large constant, and this is a reference to
7572 an external symbol, we want
7573 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7574 addu $tempreg,$tempreg,$gp
7575 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7576 lui $at,<hiconstant>
7577 addi $at,$at,<loconstant>
7578 add $tempreg,$tempreg,$at
7580 If we have NewABI, and we know it's a local symbol, we want
7581 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7582 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7583 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7585 relax_start (offset_expr.X_add_symbol);
7587 expr1.X_add_number = offset_expr.X_add_number;
7588 offset_expr.X_add_number = 0;
7590 if (expr1.X_add_number == 0 && breg == 0
7591 && (call || tempreg == PIC_CALL_REG))
7593 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7594 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7596 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7597 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7598 tempreg, tempreg, mips_gp_register);
7599 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7600 tempreg, lw_reloc_type, tempreg);
7602 if (expr1.X_add_number == 0)
7604 else if (expr1.X_add_number >= -0x8000
7605 && expr1.X_add_number < 0x8000)
7607 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7608 tempreg, tempreg, BFD_RELOC_LO16);
7610 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7612 /* If we are going to add in a base register, and the
7613 target register and the base register are the same,
7614 then we are using AT as a temporary register. Since
7615 we want to load the constant into AT, we add our
7616 current AT (from the global offset table) and the
7617 register into the register now, and pretend we were
7618 not using a base register. */
7623 gas_assert (tempreg == AT);
7624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7630 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7631 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7636 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7639 offset_expr.X_add_number = expr1.X_add_number;
7640 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7641 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7642 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7643 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7646 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7647 treg, tempreg, breg);
7657 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7661 gas_assert (!mips_opts.micromips);
7663 unsigned long temp = (treg << 16) | (0x01);
7664 macro_build (NULL, "c2", "C", temp);
7669 gas_assert (!mips_opts.micromips);
7671 unsigned long temp = (0x02);
7672 macro_build (NULL, "c2", "C", temp);
7677 gas_assert (!mips_opts.micromips);
7679 unsigned long temp = (treg << 16) | (0x02);
7680 macro_build (NULL, "c2", "C", temp);
7685 gas_assert (!mips_opts.micromips);
7686 macro_build (NULL, "c2", "C", 3);
7690 gas_assert (!mips_opts.micromips);
7692 unsigned long temp = (treg << 16) | 0x03;
7693 macro_build (NULL, "c2", "C", temp);
7698 /* The j instruction may not be used in PIC code, since it
7699 requires an absolute address. We convert it to a b
7701 if (mips_pic == NO_PIC)
7702 macro_build (&offset_expr, "j", "a");
7704 macro_build (&offset_expr, "b", "p");
7707 /* The jal instructions must be handled as macros because when
7708 generating PIC code they expand to multi-instruction
7709 sequences. Normally they are simple instructions. */
7714 gas_assert (mips_opts.micromips);
7722 if (mips_pic == NO_PIC)
7724 s = jals ? "jalrs" : "jalr";
7725 if (mips_opts.micromips && dreg == RA)
7726 macro_build (NULL, s, "mj", sreg);
7728 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7732 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7733 && mips_cprestore_offset >= 0);
7735 if (sreg != PIC_CALL_REG)
7736 as_warn (_("MIPS PIC call to register other than $25"));
7738 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7739 ? "jalrs" : "jalr");
7740 if (mips_opts.micromips && dreg == RA)
7741 macro_build (NULL, s, "mj", sreg);
7743 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7744 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7746 if (mips_cprestore_offset < 0)
7747 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7750 if (!mips_frame_reg_valid)
7752 as_warn (_("No .frame pseudo-op used in PIC code"));
7753 /* Quiet this warning. */
7754 mips_frame_reg_valid = 1;
7756 if (!mips_cprestore_valid)
7758 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7759 /* Quiet this warning. */
7760 mips_cprestore_valid = 1;
7762 if (mips_opts.noreorder)
7763 macro_build (NULL, "nop", "");
7764 expr1.X_add_number = mips_cprestore_offset;
7765 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7768 HAVE_64BIT_ADDRESSES);
7776 gas_assert (mips_opts.micromips);
7780 if (mips_pic == NO_PIC)
7781 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7782 else if (mips_pic == SVR4_PIC)
7784 /* If this is a reference to an external symbol, and we are
7785 using a small GOT, we want
7786 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7790 lw $gp,cprestore($sp)
7791 The cprestore value is set using the .cprestore
7792 pseudo-op. If we are using a big GOT, we want
7793 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7795 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7799 lw $gp,cprestore($sp)
7800 If the symbol is not external, we want
7801 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7803 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7806 lw $gp,cprestore($sp)
7808 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7809 sequences above, minus nops, unless the symbol is local,
7810 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7816 relax_start (offset_expr.X_add_symbol);
7817 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7818 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7821 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7822 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7828 relax_start (offset_expr.X_add_symbol);
7829 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7830 BFD_RELOC_MIPS_CALL_HI16);
7831 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7832 PIC_CALL_REG, mips_gp_register);
7833 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7834 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7837 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7838 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7840 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7841 PIC_CALL_REG, PIC_CALL_REG,
7842 BFD_RELOC_MIPS_GOT_OFST);
7846 macro_build_jalr (&offset_expr, 0);
7850 relax_start (offset_expr.X_add_symbol);
7853 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7854 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7863 gpdelay = reg_needs_delay (mips_gp_register);
7864 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7865 BFD_RELOC_MIPS_CALL_HI16);
7866 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7867 PIC_CALL_REG, mips_gp_register);
7868 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7869 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7874 macro_build (NULL, "nop", "");
7876 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7877 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7880 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7881 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7883 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7885 if (mips_cprestore_offset < 0)
7886 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7889 if (!mips_frame_reg_valid)
7891 as_warn (_("No .frame pseudo-op used in PIC code"));
7892 /* Quiet this warning. */
7893 mips_frame_reg_valid = 1;
7895 if (!mips_cprestore_valid)
7897 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7898 /* Quiet this warning. */
7899 mips_cprestore_valid = 1;
7901 if (mips_opts.noreorder)
7902 macro_build (NULL, "nop", "");
7903 expr1.X_add_number = mips_cprestore_offset;
7904 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7907 HAVE_64BIT_ADDRESSES);
7911 else if (mips_pic == VXWORKS_PIC)
7912 as_bad (_("Non-PIC jump used in PIC library"));
7922 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7930 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7961 gas_assert (!mips_opts.micromips);
7964 /* Itbl support may require additional care here. */
7971 /* Itbl support may require additional care here. */
7979 off12 = mips_opts.micromips;
7980 /* Itbl support may require additional care here. */
7985 gas_assert (!mips_opts.micromips);
7988 /* Itbl support may require additional care here. */
7996 off12 = mips_opts.micromips;
8003 off12 = mips_opts.micromips;
8009 /* Itbl support may require additional care here. */
8017 off12 = mips_opts.micromips;
8018 /* Itbl support may require additional care here. */
8025 /* Itbl support may require additional care here. */
8033 off12 = mips_opts.micromips;
8040 off12 = mips_opts.micromips;
8047 off12 = mips_opts.micromips;
8054 off12 = mips_opts.micromips;
8061 off12 = mips_opts.micromips;
8066 gas_assert (mips_opts.micromips);
8075 gas_assert (mips_opts.micromips);
8084 gas_assert (mips_opts.micromips);
8092 gas_assert (mips_opts.micromips);
8099 if (breg == treg + lp)
8102 tempreg = treg + lp;
8122 gas_assert (!mips_opts.micromips);
8125 /* Itbl support may require additional care here. */
8132 /* Itbl support may require additional care here. */
8140 off12 = mips_opts.micromips;
8141 /* Itbl support may require additional care here. */
8146 gas_assert (!mips_opts.micromips);
8149 /* Itbl support may require additional care here. */
8157 off12 = mips_opts.micromips;
8164 off12 = mips_opts.micromips;
8171 off12 = mips_opts.micromips;
8178 off12 = mips_opts.micromips;
8184 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8185 off12 = mips_opts.micromips;
8191 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8192 off12 = mips_opts.micromips;
8199 /* Itbl support may require additional care here. */
8206 off12 = mips_opts.micromips;
8207 /* Itbl support may require additional care here. */
8212 gas_assert (!mips_opts.micromips);
8215 /* Itbl support may require additional care here. */
8223 off12 = mips_opts.micromips;
8230 off12 = mips_opts.micromips;
8235 gas_assert (mips_opts.micromips);
8243 gas_assert (mips_opts.micromips);
8251 gas_assert (mips_opts.micromips);
8259 gas_assert (mips_opts.micromips);
8269 && NO_ISA_COP (mips_opts.arch)
8270 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
8272 as_bad (_("Opcode not supported on this processor: %s"),
8273 mips_cpu_info_from_arch (mips_opts.arch)->name);
8277 if (offset_expr.X_op != O_constant
8278 && offset_expr.X_op != O_symbol)
8280 as_bad (_("Expression too complex"));
8281 offset_expr.X_op = O_constant;
8284 if (HAVE_32BIT_ADDRESSES
8285 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8289 sprintf_vma (value, offset_expr.X_add_number);
8290 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8293 /* A constant expression in PIC code can be handled just as it
8294 is in non PIC code. */
8295 if (offset_expr.X_op == O_constant)
8299 expr1.X_add_number = offset_expr.X_add_number;
8300 normalize_address_expr (&expr1);
8301 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8303 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8304 & ~(bfd_vma) 0xffff);
8307 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8309 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8310 & ~(bfd_vma) 0xfff);
8315 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8317 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8318 tempreg, tempreg, breg);
8323 if (offset_expr.X_add_number == 0)
8326 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8327 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8328 macro_build (NULL, s, fmt, treg, tempreg);
8331 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8333 macro_build (NULL, s, fmt,
8334 treg, (unsigned long) offset_expr.X_add_number, breg);
8336 else if (off12 || off0)
8338 /* A 12-bit or 0-bit offset field is too narrow to be used
8339 for a low-part relocation, so load the whole address into
8340 the auxillary register. In the case of "A(b)" addresses,
8341 we first load absolute address "A" into the register and
8342 then add base register "b". In the case of "o(b)" addresses,
8343 we simply need to add 16-bit offset "o" to base register "b", and
8344 offset_reloc already contains the relocations associated
8348 load_address (tempreg, &offset_expr, &used_at);
8350 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8351 tempreg, tempreg, breg);
8354 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8356 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8357 expr1.X_add_number = 0;
8359 macro_build (NULL, s, fmt, treg, tempreg);
8361 macro_build (NULL, s, fmt,
8362 treg, (unsigned long) expr1.X_add_number, tempreg);
8364 else if (mips_pic == NO_PIC)
8366 /* If this is a reference to a GP relative symbol, and there
8367 is no base register, we want
8368 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8369 Otherwise, if there is no base register, we want
8370 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8371 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8372 If we have a constant, we need two instructions anyhow,
8373 so we always use the latter form.
8375 If we have a base register, and this is a reference to a
8376 GP relative symbol, we want
8377 addu $tempreg,$breg,$gp
8378 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8380 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8381 addu $tempreg,$tempreg,$breg
8382 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8383 With a constant we always use the latter case.
8385 With 64bit address space and no base register and $at usable,
8387 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8388 lui $at,<sym> (BFD_RELOC_HI16_S)
8389 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8392 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8393 If we have a base register, we want
8394 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8395 lui $at,<sym> (BFD_RELOC_HI16_S)
8396 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8400 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8402 Without $at we can't generate the optimal path for superscalar
8403 processors here since this would require two temporary registers.
8404 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8405 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8407 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8409 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8410 If we have a base register, we want
8411 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8412 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8414 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8416 daddu $tempreg,$tempreg,$breg
8417 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8419 For GP relative symbols in 64bit address space we can use
8420 the same sequence as in 32bit address space. */
8421 if (HAVE_64BIT_SYMBOLS)
8423 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8424 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8426 relax_start (offset_expr.X_add_symbol);
8429 macro_build (&offset_expr, s, fmt, treg,
8430 BFD_RELOC_GPREL16, mips_gp_register);
8434 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8435 tempreg, breg, mips_gp_register);
8436 macro_build (&offset_expr, s, fmt, treg,
8437 BFD_RELOC_GPREL16, tempreg);
8442 if (used_at == 0 && mips_opts.at)
8444 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8445 BFD_RELOC_MIPS_HIGHEST);
8446 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8448 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8449 tempreg, BFD_RELOC_MIPS_HIGHER);
8451 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8452 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8453 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8454 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8460 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8461 BFD_RELOC_MIPS_HIGHEST);
8462 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8463 tempreg, BFD_RELOC_MIPS_HIGHER);
8464 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8465 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8466 tempreg, BFD_RELOC_HI16_S);
8467 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8469 macro_build (NULL, "daddu", "d,v,t",
8470 tempreg, tempreg, breg);
8471 macro_build (&offset_expr, s, fmt, treg,
8472 BFD_RELOC_LO16, tempreg);
8475 if (mips_relax.sequence)
8482 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8483 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8485 relax_start (offset_expr.X_add_symbol);
8486 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8490 macro_build_lui (&offset_expr, tempreg);
8491 macro_build (&offset_expr, s, fmt, treg,
8492 BFD_RELOC_LO16, tempreg);
8493 if (mips_relax.sequence)
8498 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8499 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8501 relax_start (offset_expr.X_add_symbol);
8502 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8503 tempreg, breg, mips_gp_register);
8504 macro_build (&offset_expr, s, fmt, treg,
8505 BFD_RELOC_GPREL16, tempreg);
8508 macro_build_lui (&offset_expr, tempreg);
8509 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8510 tempreg, tempreg, breg);
8511 macro_build (&offset_expr, s, fmt, treg,
8512 BFD_RELOC_LO16, tempreg);
8513 if (mips_relax.sequence)
8517 else if (!mips_big_got)
8519 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8521 /* If this is a reference to an external symbol, we want
8522 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8524 <op> $treg,0($tempreg)
8526 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8528 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8529 <op> $treg,0($tempreg)
8532 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8533 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8535 If there is a base register, we add it to $tempreg before
8536 the <op>. If there is a constant, we stick it in the
8537 <op> instruction. We don't handle constants larger than
8538 16 bits, because we have no way to load the upper 16 bits
8539 (actually, we could handle them for the subset of cases
8540 in which we are not using $at). */
8541 gas_assert (offset_expr.X_op == O_symbol);
8544 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8545 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8547 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8548 tempreg, tempreg, breg);
8549 macro_build (&offset_expr, s, fmt, treg,
8550 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8553 expr1.X_add_number = offset_expr.X_add_number;
8554 offset_expr.X_add_number = 0;
8555 if (expr1.X_add_number < -0x8000
8556 || expr1.X_add_number >= 0x8000)
8557 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8558 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8559 lw_reloc_type, mips_gp_register);
8561 relax_start (offset_expr.X_add_symbol);
8563 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8564 tempreg, BFD_RELOC_LO16);
8567 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8568 tempreg, tempreg, breg);
8569 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8571 else if (mips_big_got && !HAVE_NEWABI)
8575 /* If this is a reference to an external symbol, we want
8576 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8577 addu $tempreg,$tempreg,$gp
8578 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8579 <op> $treg,0($tempreg)
8581 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8583 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8584 <op> $treg,0($tempreg)
8585 If there is a base register, we add it to $tempreg before
8586 the <op>. If there is a constant, we stick it in the
8587 <op> instruction. We don't handle constants larger than
8588 16 bits, because we have no way to load the upper 16 bits
8589 (actually, we could handle them for the subset of cases
8590 in which we are not using $at). */
8591 gas_assert (offset_expr.X_op == O_symbol);
8592 expr1.X_add_number = offset_expr.X_add_number;
8593 offset_expr.X_add_number = 0;
8594 if (expr1.X_add_number < -0x8000
8595 || expr1.X_add_number >= 0x8000)
8596 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8597 gpdelay = reg_needs_delay (mips_gp_register);
8598 relax_start (offset_expr.X_add_symbol);
8599 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8600 BFD_RELOC_MIPS_GOT_HI16);
8601 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8603 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8604 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8607 macro_build (NULL, "nop", "");
8608 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8609 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8611 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8612 tempreg, BFD_RELOC_LO16);
8616 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8617 tempreg, tempreg, breg);
8618 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8620 else if (mips_big_got && HAVE_NEWABI)
8622 /* If this is a reference to an external symbol, we want
8623 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8624 add $tempreg,$tempreg,$gp
8625 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8626 <op> $treg,<ofst>($tempreg)
8627 Otherwise, for local symbols, we want:
8628 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8629 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8630 gas_assert (offset_expr.X_op == O_symbol);
8631 expr1.X_add_number = offset_expr.X_add_number;
8632 offset_expr.X_add_number = 0;
8633 if (expr1.X_add_number < -0x8000
8634 || expr1.X_add_number >= 0x8000)
8635 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8636 relax_start (offset_expr.X_add_symbol);
8637 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8638 BFD_RELOC_MIPS_GOT_HI16);
8639 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8641 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8642 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8644 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8645 tempreg, tempreg, breg);
8646 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8649 offset_expr.X_add_number = expr1.X_add_number;
8650 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8651 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8653 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8654 tempreg, tempreg, breg);
8655 macro_build (&offset_expr, s, fmt, treg,
8656 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8666 load_register (treg, &imm_expr, 0);
8670 load_register (treg, &imm_expr, 1);
8674 if (imm_expr.X_op == O_constant)
8677 load_register (AT, &imm_expr, 0);
8678 macro_build (NULL, "mtc1", "t,G", AT, treg);
8683 gas_assert (offset_expr.X_op == O_symbol
8684 && strcmp (segment_name (S_GET_SEGMENT
8685 (offset_expr.X_add_symbol)),
8687 && offset_expr.X_add_number == 0);
8688 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8689 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8694 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8695 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8696 order 32 bits of the value and the low order 32 bits are either
8697 zero or in OFFSET_EXPR. */
8698 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8700 if (HAVE_64BIT_GPRS)
8701 load_register (treg, &imm_expr, 1);
8706 if (target_big_endian)
8718 load_register (hreg, &imm_expr, 0);
8721 if (offset_expr.X_op == O_absent)
8722 move_register (lreg, 0);
8725 gas_assert (offset_expr.X_op == O_constant);
8726 load_register (lreg, &offset_expr, 0);
8733 /* We know that sym is in the .rdata section. First we get the
8734 upper 16 bits of the address. */
8735 if (mips_pic == NO_PIC)
8737 macro_build_lui (&offset_expr, AT);
8742 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8743 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8747 /* Now we load the register(s). */
8748 if (HAVE_64BIT_GPRS)
8751 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8756 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8759 /* FIXME: How in the world do we deal with the possible
8761 offset_expr.X_add_number += 4;
8762 macro_build (&offset_expr, "lw", "t,o(b)",
8763 treg + 1, BFD_RELOC_LO16, AT);
8769 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8770 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8771 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8772 the value and the low order 32 bits are either zero or in
8774 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8777 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8778 if (HAVE_64BIT_FPRS)
8780 gas_assert (HAVE_64BIT_GPRS);
8781 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8785 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8786 if (offset_expr.X_op == O_absent)
8787 macro_build (NULL, "mtc1", "t,G", 0, treg);
8790 gas_assert (offset_expr.X_op == O_constant);
8791 load_register (AT, &offset_expr, 0);
8792 macro_build (NULL, "mtc1", "t,G", AT, treg);
8798 gas_assert (offset_expr.X_op == O_symbol
8799 && offset_expr.X_add_number == 0);
8800 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8801 if (strcmp (s, ".lit8") == 0)
8803 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8805 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8806 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8809 breg = mips_gp_register;
8810 r = BFD_RELOC_MIPS_LITERAL;
8815 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8817 if (mips_pic != NO_PIC)
8818 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8819 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8822 /* FIXME: This won't work for a 64 bit address. */
8823 macro_build_lui (&offset_expr, AT);
8826 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8828 macro_build (&offset_expr, "ldc1", "T,o(b)",
8829 treg, BFD_RELOC_LO16, AT);
8838 /* Even on a big endian machine $fn comes before $fn+1. We have
8839 to adjust when loading from memory. */
8842 gas_assert (!mips_opts.micromips);
8843 gas_assert (mips_opts.isa == ISA_MIPS1);
8844 macro_build (&offset_expr, "lwc1", "T,o(b)",
8845 target_big_endian ? treg + 1 : treg, r, breg);
8846 /* FIXME: A possible overflow which I don't know how to deal
8848 offset_expr.X_add_number += 4;
8849 macro_build (&offset_expr, "lwc1", "T,o(b)",
8850 target_big_endian ? treg : treg + 1, r, breg);
8854 gas_assert (!mips_opts.micromips);
8855 gas_assert (mips_opts.isa == ISA_MIPS1);
8856 /* Even on a big endian machine $fn comes before $fn+1. We have
8857 to adjust when storing to memory. */
8858 macro_build (&offset_expr, "swc1", "T,o(b)",
8859 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8860 offset_expr.X_add_number += 4;
8861 macro_build (&offset_expr, "swc1", "T,o(b)",
8862 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8866 gas_assert (!mips_opts.micromips);
8868 * The MIPS assembler seems to check for X_add_number not
8869 * being double aligned and generating:
8872 * addiu at,at,%lo(foo+1)
8875 * But, the resulting address is the same after relocation so why
8876 * generate the extra instruction?
8878 /* Itbl support may require additional care here. */
8881 if (mips_opts.isa != ISA_MIPS1)
8890 gas_assert (!mips_opts.micromips);
8891 /* Itbl support may require additional care here. */
8894 if (mips_opts.isa != ISA_MIPS1)
8904 if (HAVE_64BIT_GPRS)
8914 if (HAVE_64BIT_GPRS)
8922 if (offset_expr.X_op != O_symbol
8923 && offset_expr.X_op != O_constant)
8925 as_bad (_("Expression too complex"));
8926 offset_expr.X_op = O_constant;
8929 if (HAVE_32BIT_ADDRESSES
8930 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8934 sprintf_vma (value, offset_expr.X_add_number);
8935 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8938 /* Even on a big endian machine $fn comes before $fn+1. We have
8939 to adjust when loading from memory. We set coproc if we must
8940 load $fn+1 first. */
8941 /* Itbl support may require additional care here. */
8942 if (!target_big_endian)
8945 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
8947 /* If this is a reference to a GP relative symbol, we want
8948 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8949 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8950 If we have a base register, we use this
8952 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8953 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8954 If this is not a GP relative symbol, we want
8955 lui $at,<sym> (BFD_RELOC_HI16_S)
8956 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8957 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8958 If there is a base register, we add it to $at after the
8959 lui instruction. If there is a constant, we always use
8961 if (offset_expr.X_op == O_symbol
8962 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8963 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8965 relax_start (offset_expr.X_add_symbol);
8968 tempreg = mips_gp_register;
8972 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8973 AT, breg, mips_gp_register);
8978 /* Itbl support may require additional care here. */
8979 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8980 BFD_RELOC_GPREL16, tempreg);
8981 offset_expr.X_add_number += 4;
8983 /* Set mips_optimize to 2 to avoid inserting an
8985 hold_mips_optimize = mips_optimize;
8987 /* Itbl support may require additional care here. */
8988 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8989 BFD_RELOC_GPREL16, tempreg);
8990 mips_optimize = hold_mips_optimize;
8994 offset_expr.X_add_number -= 4;
8997 macro_build_lui (&offset_expr, AT);
8999 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9000 /* Itbl support may require additional care here. */
9001 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9002 BFD_RELOC_LO16, AT);
9003 /* FIXME: How do we handle overflow here? */
9004 offset_expr.X_add_number += 4;
9005 /* Itbl support may require additional care here. */
9006 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9007 BFD_RELOC_LO16, AT);
9008 if (mips_relax.sequence)
9011 else if (!mips_big_got)
9013 /* If this is a reference to an external symbol, we want
9014 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9019 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9021 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9022 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9023 If there is a base register we add it to $at before the
9024 lwc1 instructions. If there is a constant we include it
9025 in the lwc1 instructions. */
9027 expr1.X_add_number = offset_expr.X_add_number;
9028 if (expr1.X_add_number < -0x8000
9029 || expr1.X_add_number >= 0x8000 - 4)
9030 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9031 load_got_offset (AT, &offset_expr);
9034 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9036 /* Set mips_optimize to 2 to avoid inserting an undesired
9038 hold_mips_optimize = mips_optimize;
9041 /* Itbl support may require additional care here. */
9042 relax_start (offset_expr.X_add_symbol);
9043 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9044 BFD_RELOC_LO16, AT);
9045 expr1.X_add_number += 4;
9046 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9047 BFD_RELOC_LO16, AT);
9049 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9050 BFD_RELOC_LO16, AT);
9051 offset_expr.X_add_number += 4;
9052 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9053 BFD_RELOC_LO16, AT);
9056 mips_optimize = hold_mips_optimize;
9058 else if (mips_big_got)
9062 /* If this is a reference to an external symbol, we want
9063 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9065 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9070 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9072 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9073 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9074 If there is a base register we add it to $at before the
9075 lwc1 instructions. If there is a constant we include it
9076 in the lwc1 instructions. */
9078 expr1.X_add_number = offset_expr.X_add_number;
9079 offset_expr.X_add_number = 0;
9080 if (expr1.X_add_number < -0x8000
9081 || expr1.X_add_number >= 0x8000 - 4)
9082 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9083 gpdelay = reg_needs_delay (mips_gp_register);
9084 relax_start (offset_expr.X_add_symbol);
9085 macro_build (&offset_expr, "lui", LUI_FMT,
9086 AT, BFD_RELOC_MIPS_GOT_HI16);
9087 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9088 AT, AT, mips_gp_register);
9089 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9090 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9093 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9094 /* Itbl support may require additional care here. */
9095 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9096 BFD_RELOC_LO16, AT);
9097 expr1.X_add_number += 4;
9099 /* Set mips_optimize to 2 to avoid inserting an undesired
9101 hold_mips_optimize = mips_optimize;
9103 /* Itbl support may require additional care here. */
9104 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9105 BFD_RELOC_LO16, AT);
9106 mips_optimize = hold_mips_optimize;
9107 expr1.X_add_number -= 4;
9110 offset_expr.X_add_number = expr1.X_add_number;
9112 macro_build (NULL, "nop", "");
9113 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9114 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9117 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9118 /* Itbl support may require additional care here. */
9119 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9120 BFD_RELOC_LO16, AT);
9121 offset_expr.X_add_number += 4;
9123 /* Set mips_optimize to 2 to avoid inserting an undesired
9125 hold_mips_optimize = mips_optimize;
9127 /* Itbl support may require additional care here. */
9128 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9129 BFD_RELOC_LO16, AT);
9130 mips_optimize = hold_mips_optimize;
9139 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9142 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9144 macro_build (&offset_expr, s, "t,o(b)", treg,
9145 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9147 if (!HAVE_64BIT_GPRS)
9149 offset_expr.X_add_number += 4;
9150 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9151 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9172 /* New code added to support COPZ instructions.
9173 This code builds table entries out of the macros in mip_opcodes.
9174 R4000 uses interlocks to handle coproc delays.
9175 Other chips (like the R3000) require nops to be inserted for delays.
9177 FIXME: Currently, we require that the user handle delays.
9178 In order to fill delay slots for non-interlocked chips,
9179 we must have a way to specify delays based on the coprocessor.
9180 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9181 What are the side-effects of the cop instruction?
9182 What cache support might we have and what are its effects?
9183 Both coprocessor & memory require delays. how long???
9184 What registers are read/set/modified?
9186 If an itbl is provided to interpret cop instructions,
9187 this knowledge can be encoded in the itbl spec. */
9201 gas_assert (!mips_opts.micromips);
9202 if (NO_ISA_COP (mips_opts.arch)
9203 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
9205 as_bad (_("Opcode not supported on this processor: %s"),
9206 mips_cpu_info_from_arch (mips_opts.arch)->name);
9210 /* For now we just do C (same as Cz). The parameter will be
9211 stored in insn_opcode by mips_ip. */
9212 macro_build (NULL, s, "C", ip->insn_opcode);
9216 move_register (dreg, sreg);
9222 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9223 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9229 /* The MIPS assembler some times generates shifts and adds. I'm
9230 not trying to be that fancy. GCC should do this for us
9233 load_register (AT, &imm_expr, dbl);
9234 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9235 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9251 load_register (AT, &imm_expr, dbl);
9252 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9253 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9254 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9255 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9257 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9260 if (mips_opts.micromips)
9261 micromips_label_expr (&label_expr);
9263 label_expr.X_add_number = 8;
9264 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9265 macro_build (NULL, "nop", "");
9266 macro_build (NULL, "break", BRK_FMT, 6);
9267 if (mips_opts.micromips)
9268 micromips_add_label ();
9271 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9287 load_register (AT, &imm_expr, dbl);
9288 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9289 sreg, imm ? AT : treg);
9290 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9291 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9293 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9296 if (mips_opts.micromips)
9297 micromips_label_expr (&label_expr);
9299 label_expr.X_add_number = 8;
9300 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9301 macro_build (NULL, "nop", "");
9302 macro_build (NULL, "break", BRK_FMT, 6);
9303 if (mips_opts.micromips)
9304 micromips_add_label ();
9310 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9321 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9322 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9326 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9327 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9328 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9329 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9333 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9344 macro_build (NULL, "negu", "d,w", tempreg, treg);
9345 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9349 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9350 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9351 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9352 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9361 if (imm_expr.X_op != O_constant)
9362 as_bad (_("Improper rotate count"));
9363 rot = imm_expr.X_add_number & 0x3f;
9364 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9366 rot = (64 - rot) & 0x3f;
9368 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9370 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9375 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9378 l = (rot < 0x20) ? "dsll" : "dsll32";
9379 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9382 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9383 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9384 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9392 if (imm_expr.X_op != O_constant)
9393 as_bad (_("Improper rotate count"));
9394 rot = imm_expr.X_add_number & 0x1f;
9395 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9397 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9402 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9406 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9407 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9408 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9413 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9415 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9419 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9420 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9421 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9422 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9426 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9428 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9432 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9433 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9434 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9435 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9444 if (imm_expr.X_op != O_constant)
9445 as_bad (_("Improper rotate count"));
9446 rot = imm_expr.X_add_number & 0x3f;
9447 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9450 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9452 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9457 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9460 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9461 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9464 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9465 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9466 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9474 if (imm_expr.X_op != O_constant)
9475 as_bad (_("Improper rotate count"));
9476 rot = imm_expr.X_add_number & 0x1f;
9477 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9479 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9484 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9488 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9489 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9490 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9496 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9498 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9501 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9502 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9507 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9509 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9514 as_warn (_("Instruction %s: result is always false"),
9516 move_register (dreg, 0);
9519 if (CPU_HAS_SEQ (mips_opts.arch)
9520 && -512 <= imm_expr.X_add_number
9521 && imm_expr.X_add_number < 512)
9523 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9524 (int) imm_expr.X_add_number);
9527 if (imm_expr.X_op == O_constant
9528 && imm_expr.X_add_number >= 0
9529 && imm_expr.X_add_number < 0x10000)
9531 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9533 else if (imm_expr.X_op == O_constant
9534 && imm_expr.X_add_number > -0x8000
9535 && imm_expr.X_add_number < 0)
9537 imm_expr.X_add_number = -imm_expr.X_add_number;
9538 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9539 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9541 else if (CPU_HAS_SEQ (mips_opts.arch))
9544 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9545 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9550 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9551 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9554 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9557 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9563 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9564 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9567 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9569 if (imm_expr.X_op == O_constant
9570 && imm_expr.X_add_number >= -0x8000
9571 && imm_expr.X_add_number < 0x8000)
9573 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9574 dreg, sreg, BFD_RELOC_LO16);
9578 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9579 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9583 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9586 case M_SGT: /* sreg > treg <==> treg < sreg */
9592 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9595 case M_SGT_I: /* sreg > I <==> I < sreg */
9602 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9603 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9606 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9612 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9613 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9616 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9623 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9624 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9625 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9629 if (imm_expr.X_op == O_constant
9630 && imm_expr.X_add_number >= -0x8000
9631 && imm_expr.X_add_number < 0x8000)
9633 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9637 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9638 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9642 if (imm_expr.X_op == O_constant
9643 && imm_expr.X_add_number >= -0x8000
9644 && imm_expr.X_add_number < 0x8000)
9646 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9651 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9652 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9657 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9659 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9662 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9663 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9668 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9670 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9675 as_warn (_("Instruction %s: result is always true"),
9677 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9678 dreg, 0, BFD_RELOC_LO16);
9681 if (CPU_HAS_SEQ (mips_opts.arch)
9682 && -512 <= imm_expr.X_add_number
9683 && imm_expr.X_add_number < 512)
9685 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9686 (int) imm_expr.X_add_number);
9689 if (imm_expr.X_op == O_constant
9690 && imm_expr.X_add_number >= 0
9691 && imm_expr.X_add_number < 0x10000)
9693 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9695 else if (imm_expr.X_op == O_constant
9696 && imm_expr.X_add_number > -0x8000
9697 && imm_expr.X_add_number < 0)
9699 imm_expr.X_add_number = -imm_expr.X_add_number;
9700 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9701 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9703 else if (CPU_HAS_SEQ (mips_opts.arch))
9706 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9707 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9712 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9713 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9716 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9731 if (!mips_opts.micromips)
9733 if (imm_expr.X_op == O_constant
9734 && imm_expr.X_add_number > -0x200
9735 && imm_expr.X_add_number <= 0x200)
9737 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9746 if (imm_expr.X_op == O_constant
9747 && imm_expr.X_add_number > -0x8000
9748 && imm_expr.X_add_number <= 0x8000)
9750 imm_expr.X_add_number = -imm_expr.X_add_number;
9751 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9756 load_register (AT, &imm_expr, dbl);
9757 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9779 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9780 macro_build (NULL, s, "s,t", sreg, AT);
9785 gas_assert (!mips_opts.micromips);
9786 gas_assert (mips_opts.isa == ISA_MIPS1);
9788 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9789 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9792 * Is the double cfc1 instruction a bug in the mips assembler;
9793 * or is there a reason for it?
9796 macro_build (NULL, "cfc1", "t,G", treg, RA);
9797 macro_build (NULL, "cfc1", "t,G", treg, RA);
9798 macro_build (NULL, "nop", "");
9799 expr1.X_add_number = 3;
9800 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9801 expr1.X_add_number = 2;
9802 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9803 macro_build (NULL, "ctc1", "t,G", AT, RA);
9804 macro_build (NULL, "nop", "");
9805 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9807 macro_build (NULL, "ctc1", "t,G", treg, RA);
9808 macro_build (NULL, "nop", "");
9831 off12 = mips_opts.micromips;
9839 off12 = mips_opts.micromips;
9855 off12 = mips_opts.micromips;
9864 off12 = mips_opts.micromips;
9869 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9870 as_bad (_("Operand overflow"));
9873 expr1.X_add_number = 0;
9878 load_address (tempreg, ep, &used_at);
9880 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9881 tempreg, tempreg, breg);
9887 && (offset_expr.X_op != O_constant
9888 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9889 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9893 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9894 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9899 else if (!ust && treg == breg)
9910 if (!target_big_endian)
9911 ep->X_add_number += off;
9913 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9915 macro_build (NULL, s, "t,~(b)",
9916 tempreg, (unsigned long) ep->X_add_number, breg);
9918 if (!target_big_endian)
9919 ep->X_add_number -= off;
9921 ep->X_add_number += off;
9923 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9925 macro_build (NULL, s2, "t,~(b)",
9926 tempreg, (unsigned long) ep->X_add_number, breg);
9928 /* If necessary, move the result in tempreg to the final destination. */
9929 if (!ust && treg != tempreg)
9931 /* Protect second load's delay slot. */
9933 move_register (treg, tempreg);
9939 if (target_big_endian == ust)
9940 ep->X_add_number += off;
9941 tempreg = ust || ab ? treg : AT;
9942 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9944 /* For halfword transfers we need a temporary register to shuffle
9945 bytes. Unfortunately for M_USH_A we have none available before
9946 the next store as AT holds the base address. We deal with this
9947 case by clobbering TREG and then restoring it as with ULH. */
9948 tempreg = ust == ab ? treg : AT;
9950 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9952 if (target_big_endian == ust)
9953 ep->X_add_number -= off;
9955 ep->X_add_number += off;
9956 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9958 /* For M_USH_A re-retrieve the LSB. */
9961 if (target_big_endian)
9962 ep->X_add_number += off;
9964 ep->X_add_number -= off;
9965 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9967 /* For ULH and M_USH_A OR the LSB in. */
9970 tempreg = !ab ? AT : treg;
9971 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9972 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9977 /* FIXME: Check if this is one of the itbl macros, since they
9978 are added dynamically. */
9979 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9982 if (!mips_opts.at && used_at)
9983 as_bad (_("Macro used $at after \".set noat\""));
9986 /* Implement macros in mips16 mode. */
9989 mips16_macro (struct mips_cl_insn *ip)
9992 int xreg, yreg, zreg, tmp;
9995 const char *s, *s2, *s3;
9997 mask = ip->insn_mo->mask;
9999 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10000 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10001 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10003 expr1.X_op = O_constant;
10004 expr1.X_op_symbol = NULL;
10005 expr1.X_add_symbol = NULL;
10006 expr1.X_add_number = 1;
10025 start_noreorder ();
10026 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10027 expr1.X_add_number = 2;
10028 macro_build (&expr1, "bnez", "x,p", yreg);
10029 macro_build (NULL, "break", "6", 7);
10031 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10032 since that causes an overflow. We should do that as well,
10033 but I don't see how to do the comparisons without a temporary
10036 macro_build (NULL, s, "x", zreg);
10055 start_noreorder ();
10056 macro_build (NULL, s, "0,x,y", xreg, yreg);
10057 expr1.X_add_number = 2;
10058 macro_build (&expr1, "bnez", "x,p", yreg);
10059 macro_build (NULL, "break", "6", 7);
10061 macro_build (NULL, s2, "x", zreg);
10067 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10068 macro_build (NULL, "mflo", "x", zreg);
10076 if (imm_expr.X_op != O_constant)
10077 as_bad (_("Unsupported large constant"));
10078 imm_expr.X_add_number = -imm_expr.X_add_number;
10079 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10083 if (imm_expr.X_op != O_constant)
10084 as_bad (_("Unsupported large constant"));
10085 imm_expr.X_add_number = -imm_expr.X_add_number;
10086 macro_build (&imm_expr, "addiu", "x,k", xreg);
10090 if (imm_expr.X_op != O_constant)
10091 as_bad (_("Unsupported large constant"));
10092 imm_expr.X_add_number = -imm_expr.X_add_number;
10093 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10115 goto do_reverse_branch;
10119 goto do_reverse_branch;
10131 goto do_reverse_branch;
10142 macro_build (NULL, s, "x,y", xreg, yreg);
10143 macro_build (&offset_expr, s2, "p");
10170 goto do_addone_branch_i;
10175 goto do_addone_branch_i;
10190 goto do_addone_branch_i;
10196 do_addone_branch_i:
10197 if (imm_expr.X_op != O_constant)
10198 as_bad (_("Unsupported large constant"));
10199 ++imm_expr.X_add_number;
10202 macro_build (&imm_expr, s, s3, xreg);
10203 macro_build (&offset_expr, s2, "p");
10207 expr1.X_add_number = 0;
10208 macro_build (&expr1, "slti", "x,8", yreg);
10210 move_register (xreg, yreg);
10211 expr1.X_add_number = 2;
10212 macro_build (&expr1, "bteqz", "p");
10213 macro_build (NULL, "neg", "x,w", xreg, xreg);
10217 /* For consistency checking, verify that all bits are specified either
10218 by the match/mask part of the instruction definition, or by the
10221 validate_mips_insn (const struct mips_opcode *opc)
10223 const char *p = opc->args;
10225 unsigned long used_bits = opc->mask;
10227 if ((used_bits & opc->match) != opc->match)
10229 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10230 opc->name, opc->args);
10233 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10243 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10244 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10245 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10246 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10247 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10248 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10249 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10250 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10251 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10252 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10253 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10254 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10255 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10257 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10258 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10259 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10260 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10261 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10262 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10263 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10264 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10265 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10266 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10267 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10268 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10269 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10270 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10271 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10274 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10275 c, opc->name, opc->args);
10279 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10280 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10282 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10283 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10284 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10285 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10287 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10288 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10290 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10291 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10293 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10294 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10295 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10296 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10297 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10298 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10299 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10300 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10301 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10302 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10303 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10304 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10305 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10306 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10307 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10308 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10309 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10311 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10312 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10313 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10314 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10316 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10317 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10318 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10319 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10320 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10321 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10322 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10323 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10324 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10327 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10328 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10329 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10330 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10331 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10334 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10335 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10336 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10337 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10338 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10339 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10340 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10341 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10342 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10343 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10344 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10345 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10346 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10347 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10348 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10349 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10350 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10351 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10352 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10353 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10355 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10356 c, opc->name, opc->args);
10360 if (used_bits != 0xffffffff)
10362 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10363 ~used_bits & 0xffffffff, opc->name, opc->args);
10369 /* For consistency checking, verify that the length implied matches the
10370 major opcode and that all bits are specified either by the match/mask
10371 part of the instruction definition, or by the operand list. */
10374 validate_micromips_insn (const struct mips_opcode *opc)
10376 unsigned long match = opc->match;
10377 unsigned long mask = opc->mask;
10378 const char *p = opc->args;
10379 unsigned long insn_bits;
10380 unsigned long used_bits;
10381 unsigned long major;
10382 unsigned int length;
10386 if ((mask & match) != match)
10388 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10389 opc->name, opc->args);
10392 length = micromips_insn_length (opc);
10393 if (length != 2 && length != 4)
10395 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10396 "%s %s"), length, opc->name, opc->args);
10399 major = match >> (10 + 8 * (length - 2));
10400 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10401 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10403 as_bad (_("Internal error: bad microMIPS opcode "
10404 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10408 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10409 insn_bits = 1 << 4 * length;
10410 insn_bits <<= 4 * length;
10413 #define USE_BITS(field) \
10414 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10425 case 'A': USE_BITS (EXTLSB); break;
10426 case 'B': USE_BITS (INSMSB); break;
10427 case 'C': USE_BITS (EXTMSBD); break;
10428 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10429 case 'E': USE_BITS (EXTLSB); break;
10430 case 'F': USE_BITS (INSMSB); break;
10431 case 'G': USE_BITS (EXTMSBD); break;
10432 case 'H': USE_BITS (EXTMSBD); break;
10434 as_bad (_("Internal error: bad mips opcode "
10435 "(unknown extension operand type `%c%c'): %s %s"),
10436 e, c, opc->name, opc->args);
10444 case 'A': USE_BITS (IMMA); break;
10445 case 'B': USE_BITS (IMMB); break;
10446 case 'C': USE_BITS (IMMC); break;
10447 case 'D': USE_BITS (IMMD); break;
10448 case 'E': USE_BITS (IMME); break;
10449 case 'F': USE_BITS (IMMF); break;
10450 case 'G': USE_BITS (IMMG); break;
10451 case 'H': USE_BITS (IMMH); break;
10452 case 'I': USE_BITS (IMMI); break;
10453 case 'J': USE_BITS (IMMJ); break;
10454 case 'L': USE_BITS (IMML); break;
10455 case 'M': USE_BITS (IMMM); break;
10456 case 'N': USE_BITS (IMMN); break;
10457 case 'O': USE_BITS (IMMO); break;
10458 case 'P': USE_BITS (IMMP); break;
10459 case 'Q': USE_BITS (IMMQ); break;
10460 case 'U': USE_BITS (IMMU); break;
10461 case 'W': USE_BITS (IMMW); break;
10462 case 'X': USE_BITS (IMMX); break;
10463 case 'Y': USE_BITS (IMMY); break;
10466 case 'b': USE_BITS (MB); break;
10467 case 'c': USE_BITS (MC); break;
10468 case 'd': USE_BITS (MD); break;
10469 case 'e': USE_BITS (ME); break;
10470 case 'f': USE_BITS (MF); break;
10471 case 'g': USE_BITS (MG); break;
10472 case 'h': USE_BITS (MH); break;
10473 case 'i': USE_BITS (MI); break;
10474 case 'j': USE_BITS (MJ); break;
10475 case 'l': USE_BITS (ML); break;
10476 case 'm': USE_BITS (MM); break;
10477 case 'n': USE_BITS (MN); break;
10478 case 'p': USE_BITS (MP); break;
10479 case 'q': USE_BITS (MQ); break;
10487 as_bad (_("Internal error: bad mips opcode "
10488 "(unknown extension operand type `%c%c'): %s %s"),
10489 e, c, opc->name, opc->args);
10493 case '.': USE_BITS (OFFSET10); break;
10494 case '1': USE_BITS (STYPE); break;
10495 case '2': USE_BITS (BP); break;
10496 case '3': USE_BITS (SA3); break;
10497 case '4': USE_BITS (SA4); break;
10498 case '5': USE_BITS (IMM8); break;
10499 case '6': USE_BITS (RS); break;
10500 case '7': USE_BITS (DSPACC); break;
10501 case '8': USE_BITS (WRDSP); break;
10502 case '0': USE_BITS (DSPSFT); break;
10503 case '<': USE_BITS (SHAMT); break;
10504 case '>': USE_BITS (SHAMT); break;
10505 case '@': USE_BITS (IMM10); break;
10506 case 'B': USE_BITS (CODE10); break;
10507 case 'C': USE_BITS (COPZ); break;
10508 case 'D': USE_BITS (FD); break;
10509 case 'E': USE_BITS (RT); break;
10510 case 'G': USE_BITS (RS); break;
10511 case 'H': USE_BITS (SEL); break;
10512 case 'K': USE_BITS (RS); break;
10513 case 'M': USE_BITS (CCC); break;
10514 case 'N': USE_BITS (BCC); break;
10515 case 'R': USE_BITS (FR); break;
10516 case 'S': USE_BITS (FS); break;
10517 case 'T': USE_BITS (FT); break;
10518 case 'V': USE_BITS (FS); break;
10519 case '\\': USE_BITS (3BITPOS); break;
10520 case '^': USE_BITS (RD); break;
10521 case 'a': USE_BITS (TARGET); break;
10522 case 'b': USE_BITS (RS); break;
10523 case 'c': USE_BITS (CODE); break;
10524 case 'd': USE_BITS (RD); break;
10525 case 'h': USE_BITS (PREFX); break;
10526 case 'i': USE_BITS (IMMEDIATE); break;
10527 case 'j': USE_BITS (DELTA); break;
10528 case 'k': USE_BITS (CACHE); break;
10529 case 'n': USE_BITS (RT); break;
10530 case 'o': USE_BITS (DELTA); break;
10531 case 'p': USE_BITS (DELTA); break;
10532 case 'q': USE_BITS (CODE2); break;
10533 case 'r': USE_BITS (RS); break;
10534 case 's': USE_BITS (RS); break;
10535 case 't': USE_BITS (RT); break;
10536 case 'u': USE_BITS (IMMEDIATE); break;
10537 case 'v': USE_BITS (RS); break;
10538 case 'w': USE_BITS (RT); break;
10539 case 'y': USE_BITS (RS3); break;
10541 case '|': USE_BITS (TRAP); break;
10542 case '~': USE_BITS (OFFSET12); break;
10544 as_bad (_("Internal error: bad microMIPS opcode "
10545 "(unknown operand type `%c'): %s %s"),
10546 c, opc->name, opc->args);
10550 if (used_bits != insn_bits)
10552 if (~used_bits & insn_bits)
10553 as_bad (_("Internal error: bad microMIPS opcode "
10554 "(bits 0x%lx undefined): %s %s"),
10555 ~used_bits & insn_bits, opc->name, opc->args);
10556 if (used_bits & ~insn_bits)
10557 as_bad (_("Internal error: bad microMIPS opcode "
10558 "(bits 0x%lx defined): %s %s"),
10559 used_bits & ~insn_bits, opc->name, opc->args);
10565 /* UDI immediates. */
10566 struct mips_immed {
10568 unsigned int shift;
10569 unsigned long mask;
10573 static const struct mips_immed mips_immed[] = {
10574 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10575 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10576 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10577 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10581 /* Check whether an odd floating-point register is allowed. */
10583 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10585 const char *s = insn->name;
10587 if (insn->pinfo == INSN_MACRO)
10588 /* Let a macro pass, we'll catch it later when it is expanded. */
10591 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10593 /* Allow odd registers for single-precision ops. */
10594 switch (insn->pinfo & (FP_S | FP_D))
10598 return 1; /* both single precision - ok */
10600 return 0; /* both double precision - fail */
10605 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10606 s = strchr (insn->name, '.');
10608 s = s != NULL ? strchr (s + 1, '.') : NULL;
10609 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10612 /* Single-precision coprocessor loads and moves are OK too. */
10613 if ((insn->pinfo & FP_S)
10614 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10615 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10621 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10622 taking bits from BIT up. */
10624 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10626 return (ep->X_op == O_constant
10627 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10628 && ep->X_add_number >= min << bit
10629 && ep->X_add_number < max << bit);
10632 /* This routine assembles an instruction into its binary format. As a
10633 side effect, it sets one of the global variables imm_reloc or
10634 offset_reloc to the type of relocation to do if one of the operands
10635 is an address expression. */
10638 mips_ip (char *str, struct mips_cl_insn *ip)
10640 bfd_boolean wrong_delay_slot_insns = FALSE;
10641 bfd_boolean need_delay_slot_ok = TRUE;
10642 struct mips_opcode *firstinsn = NULL;
10643 const struct mips_opcode *past;
10644 struct hash_control *hash;
10648 struct mips_opcode *insn;
10650 unsigned int regno;
10651 unsigned int lastregno;
10652 unsigned int destregno = 0;
10653 unsigned int lastpos = 0;
10654 unsigned int limlo, limhi;
10656 offsetT min_range, max_range;
10660 unsigned int rtype;
10666 if (mips_opts.micromips)
10668 hash = micromips_op_hash;
10669 past = µmips_opcodes[bfd_micromips_num_opcodes];
10674 past = &mips_opcodes[NUMOPCODES];
10676 forced_insn_length = 0;
10679 /* We first try to match an instruction up to a space or to the end. */
10680 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10683 /* Make a copy of the instruction so that we can fiddle with it. */
10684 name = alloca (end + 1);
10685 memcpy (name, str, end);
10690 insn = (struct mips_opcode *) hash_find (hash, name);
10692 if (insn != NULL || !mips_opts.micromips)
10694 if (forced_insn_length)
10697 /* See if there's an instruction size override suffix,
10698 either `16' or `32', at the end of the mnemonic proper,
10699 that defines the operation, i.e. before the first `.'
10700 character if any. Strip it and retry. */
10701 dot = strchr (name, '.');
10702 opend = dot != NULL ? dot - name : end;
10705 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10706 forced_insn_length = 2;
10707 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10708 forced_insn_length = 4;
10711 memcpy (name + opend - 2, name + opend, end - opend + 1);
10715 insn_error = _("Unrecognized opcode");
10719 /* For microMIPS instructions placed in a fixed-length branch delay slot
10720 we make up to two passes over the relevant fragment of the opcode
10721 table. First we try instructions that meet the delay slot's length
10722 requirement. If none matched, then we retry with the remaining ones
10723 and if one matches, then we use it and then issue an appropriate
10724 warning later on. */
10725 argsStart = s = str + end;
10728 bfd_boolean delay_slot_ok;
10729 bfd_boolean size_ok;
10732 gas_assert (strcmp (insn->name, name) == 0);
10734 ok = is_opcode_valid (insn);
10735 size_ok = is_size_valid (insn);
10736 delay_slot_ok = is_delay_slot_valid (insn);
10737 if (!delay_slot_ok && !wrong_delay_slot_insns)
10740 wrong_delay_slot_insns = TRUE;
10742 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10744 static char buf[256];
10746 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10751 if (wrong_delay_slot_insns && need_delay_slot_ok)
10753 gas_assert (firstinsn);
10754 need_delay_slot_ok = FALSE;
10764 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10765 mips_cpu_info_from_arch (mips_opts.arch)->name,
10766 mips_cpu_info_from_isa (mips_opts.isa)->name);
10768 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10769 8 * forced_insn_length);
10775 create_insn (ip, insn);
10778 lastregno = 0xffffffff;
10779 for (args = insn->args;; ++args)
10783 s += strspn (s, " \t");
10787 case '\0': /* end of args */
10793 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10794 code) or 14 (for microMIPS code). */
10795 my_getExpression (&imm_expr, s);
10796 check_absolute_expr (ip, &imm_expr);
10797 if ((unsigned long) imm_expr.X_add_number != 1
10798 && (unsigned long) imm_expr.X_add_number != 3)
10800 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10801 (unsigned long) imm_expr.X_add_number);
10803 INSERT_OPERAND (mips_opts.micromips,
10804 BP, *ip, imm_expr.X_add_number);
10805 imm_expr.X_op = O_absent;
10810 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10811 code) or 21 (for microMIPS code). */
10813 unsigned long mask = (mips_opts.micromips
10814 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
10816 my_getExpression (&imm_expr, s);
10817 check_absolute_expr (ip, &imm_expr);
10818 if ((unsigned long) imm_expr.X_add_number > mask)
10819 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10820 mask, (unsigned long) imm_expr.X_add_number);
10821 INSERT_OPERAND (mips_opts.micromips,
10822 SA3, *ip, imm_expr.X_add_number);
10823 imm_expr.X_op = O_absent;
10829 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10830 code) or 21 (for microMIPS code). */
10832 unsigned long mask = (mips_opts.micromips
10833 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
10835 my_getExpression (&imm_expr, s);
10836 check_absolute_expr (ip, &imm_expr);
10837 if ((unsigned long) imm_expr.X_add_number > mask)
10838 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10839 mask, (unsigned long) imm_expr.X_add_number);
10840 INSERT_OPERAND (mips_opts.micromips,
10841 SA4, *ip, imm_expr.X_add_number);
10842 imm_expr.X_op = O_absent;
10848 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10849 code) or 16 (for microMIPS code). */
10851 unsigned long mask = (mips_opts.micromips
10852 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
10854 my_getExpression (&imm_expr, s);
10855 check_absolute_expr (ip, &imm_expr);
10856 if ((unsigned long) imm_expr.X_add_number > mask)
10857 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10858 mask, (unsigned long) imm_expr.X_add_number);
10859 INSERT_OPERAND (mips_opts.micromips,
10860 IMM8, *ip, imm_expr.X_add_number);
10861 imm_expr.X_op = O_absent;
10867 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
10868 code) or 21 (for microMIPS code). */
10870 unsigned long mask = (mips_opts.micromips
10871 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
10873 my_getExpression (&imm_expr, s);
10874 check_absolute_expr (ip, &imm_expr);
10875 if ((unsigned long) imm_expr.X_add_number > mask)
10876 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10877 mask, (unsigned long) imm_expr.X_add_number);
10878 INSERT_OPERAND (mips_opts.micromips,
10879 RS, *ip, imm_expr.X_add_number);
10880 imm_expr.X_op = O_absent;
10885 case '7': /* Four DSP accumulators in bits 11,12. */
10886 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
10887 && s[3] >= '0' && s[3] <= '3')
10889 regno = s[3] - '0';
10891 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
10895 as_bad (_("Invalid dsp acc register"));
10899 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
10900 code) or 14 (for microMIPS code). */
10902 unsigned long mask = (mips_opts.micromips
10903 ? MICROMIPSOP_MASK_WRDSP
10906 my_getExpression (&imm_expr, s);
10907 check_absolute_expr (ip, &imm_expr);
10908 if ((unsigned long) imm_expr.X_add_number > mask)
10909 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10910 mask, (unsigned long) imm_expr.X_add_number);
10911 INSERT_OPERAND (mips_opts.micromips,
10912 WRDSP, *ip, imm_expr.X_add_number);
10913 imm_expr.X_op = O_absent;
10918 case '9': /* Four DSP accumulators in bits 21,22. */
10919 gas_assert (!mips_opts.micromips);
10920 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
10921 && s[3] >= '0' && s[3] <= '3')
10923 regno = s[3] - '0';
10925 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10929 as_bad (_("Invalid dsp acc register"));
10933 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
10934 code) or 20 (for microMIPS code). */
10936 long mask = (mips_opts.micromips
10937 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
10939 my_getExpression (&imm_expr, s);
10940 check_absolute_expr (ip, &imm_expr);
10941 min_range = -((mask + 1) >> 1);
10942 max_range = ((mask + 1) >> 1) - 1;
10943 if (imm_expr.X_add_number < min_range
10944 || imm_expr.X_add_number > max_range)
10945 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10946 (long) min_range, (long) max_range,
10947 (long) imm_expr.X_add_number);
10948 INSERT_OPERAND (mips_opts.micromips,
10949 DSPSFT, *ip, imm_expr.X_add_number);
10950 imm_expr.X_op = O_absent;
10955 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10956 gas_assert (!mips_opts.micromips);
10957 my_getExpression (&imm_expr, s);
10958 check_absolute_expr (ip, &imm_expr);
10959 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10961 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10963 (unsigned long) imm_expr.X_add_number);
10965 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
10966 imm_expr.X_op = O_absent;
10970 case ':': /* DSP 7-bit signed immediate in bit 19. */
10971 gas_assert (!mips_opts.micromips);
10972 my_getExpression (&imm_expr, s);
10973 check_absolute_expr (ip, &imm_expr);
10974 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10975 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10976 if (imm_expr.X_add_number < min_range ||
10977 imm_expr.X_add_number > max_range)
10979 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10980 (long) min_range, (long) max_range,
10981 (long) imm_expr.X_add_number);
10983 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
10984 imm_expr.X_op = O_absent;
10988 case '@': /* DSP 10-bit signed immediate in bit 16. */
10990 long mask = (mips_opts.micromips
10991 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
10993 my_getExpression (&imm_expr, s);
10994 check_absolute_expr (ip, &imm_expr);
10995 min_range = -((mask + 1) >> 1);
10996 max_range = ((mask + 1) >> 1) - 1;
10997 if (imm_expr.X_add_number < min_range
10998 || imm_expr.X_add_number > max_range)
10999 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11000 (long) min_range, (long) max_range,
11001 (long) imm_expr.X_add_number);
11002 INSERT_OPERAND (mips_opts.micromips,
11003 IMM10, *ip, imm_expr.X_add_number);
11004 imm_expr.X_op = O_absent;
11009 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11010 gas_assert (mips_opts.micromips);
11011 my_getExpression (&imm_expr, s);
11012 check_absolute_expr (ip, &imm_expr);
11013 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11014 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11015 MICROMIPSOP_MASK_RD,
11016 (unsigned long) imm_expr.X_add_number);
11017 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11018 imm_expr.X_op = O_absent;
11022 case '!': /* MT usermode flag bit. */
11023 gas_assert (!mips_opts.micromips);
11024 my_getExpression (&imm_expr, s);
11025 check_absolute_expr (ip, &imm_expr);
11026 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11027 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11028 (unsigned long) imm_expr.X_add_number);
11029 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11030 imm_expr.X_op = O_absent;
11034 case '$': /* MT load high flag bit. */
11035 gas_assert (!mips_opts.micromips);
11036 my_getExpression (&imm_expr, s);
11037 check_absolute_expr (ip, &imm_expr);
11038 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11039 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11040 (unsigned long) imm_expr.X_add_number);
11041 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11042 imm_expr.X_op = O_absent;
11046 case '*': /* Four DSP accumulators in bits 18,19. */
11047 gas_assert (!mips_opts.micromips);
11048 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11049 s[3] >= '0' && s[3] <= '3')
11051 regno = s[3] - '0';
11053 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11057 as_bad (_("Invalid dsp/smartmips acc register"));
11060 case '&': /* Four DSP accumulators in bits 13,14. */
11061 gas_assert (!mips_opts.micromips);
11062 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11063 s[3] >= '0' && s[3] <= '3')
11065 regno = s[3] - '0';
11067 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11071 as_bad (_("Invalid dsp/smartmips acc register"));
11074 case '\\': /* 3-bit bit position. */
11076 unsigned long mask = (mips_opts.micromips
11077 ? MICROMIPSOP_MASK_3BITPOS
11078 : OP_MASK_3BITPOS);
11080 my_getExpression (&imm_expr, s);
11081 check_absolute_expr (ip, &imm_expr);
11082 if ((unsigned long) imm_expr.X_add_number > mask)
11083 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11085 mask, (unsigned long) imm_expr.X_add_number);
11086 INSERT_OPERAND (mips_opts.micromips,
11087 3BITPOS, *ip, imm_expr.X_add_number);
11088 imm_expr.X_op = O_absent;
11102 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11106 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11110 gas_assert (!mips_opts.micromips);
11111 INSERT_OPERAND (0, FT, *ip, lastregno);
11115 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11121 /* Handle optional base register.
11122 Either the base register is omitted or
11123 we must have a left paren. */
11124 /* This is dependent on the next operand specifier
11125 is a base register specification. */
11126 gas_assert (args[1] == 'b'
11127 || (mips_opts.micromips
11129 && (args[2] == 'l' || args[2] == 'n'
11130 || args[2] == 's' || args[2] == 'a')));
11131 if (*s == '\0' && args[1] == 'b')
11133 /* Fall through. */
11135 case ')': /* These must match exactly. */
11140 case '[': /* These must match exactly. */
11142 gas_assert (!mips_opts.micromips);
11147 case '+': /* Opcode extension character. */
11150 case '1': /* UDI immediates. */
11154 gas_assert (!mips_opts.micromips);
11156 const struct mips_immed *imm = mips_immed;
11158 while (imm->type && imm->type != *args)
11162 my_getExpression (&imm_expr, s);
11163 check_absolute_expr (ip, &imm_expr);
11164 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11166 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11167 imm->desc ? imm->desc : ip->insn_mo->name,
11168 (unsigned long) imm_expr.X_add_number,
11169 (unsigned long) imm_expr.X_add_number);
11170 imm_expr.X_add_number &= imm->mask;
11172 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11174 imm_expr.X_op = O_absent;
11179 case 'A': /* ins/ext position, becomes LSB. */
11188 my_getExpression (&imm_expr, s);
11189 check_absolute_expr (ip, &imm_expr);
11190 if ((unsigned long) imm_expr.X_add_number < limlo
11191 || (unsigned long) imm_expr.X_add_number > limhi)
11193 as_bad (_("Improper position (%lu)"),
11194 (unsigned long) imm_expr.X_add_number);
11195 imm_expr.X_add_number = limlo;
11197 lastpos = imm_expr.X_add_number;
11198 INSERT_OPERAND (mips_opts.micromips,
11199 EXTLSB, *ip, imm_expr.X_add_number);
11200 imm_expr.X_op = O_absent;
11204 case 'B': /* ins size, becomes MSB. */
11213 my_getExpression (&imm_expr, s);
11214 check_absolute_expr (ip, &imm_expr);
11215 /* Check for negative input so that small negative numbers
11216 will not succeed incorrectly. The checks against
11217 (pos+size) transitively check "size" itself,
11218 assuming that "pos" is reasonable. */
11219 if ((long) imm_expr.X_add_number < 0
11220 || ((unsigned long) imm_expr.X_add_number
11222 || ((unsigned long) imm_expr.X_add_number
11223 + lastpos) > limhi)
11225 as_bad (_("Improper insert size (%lu, position %lu)"),
11226 (unsigned long) imm_expr.X_add_number,
11227 (unsigned long) lastpos);
11228 imm_expr.X_add_number = limlo - lastpos;
11230 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11231 lastpos + imm_expr.X_add_number - 1);
11232 imm_expr.X_op = O_absent;
11236 case 'C': /* ext size, becomes MSBD. */
11249 my_getExpression (&imm_expr, s);
11250 check_absolute_expr (ip, &imm_expr);
11251 /* Check for negative input so that small negative numbers
11252 will not succeed incorrectly. The checks against
11253 (pos+size) transitively check "size" itself,
11254 assuming that "pos" is reasonable. */
11255 if ((long) imm_expr.X_add_number < 0
11256 || ((unsigned long) imm_expr.X_add_number
11258 || ((unsigned long) imm_expr.X_add_number
11259 + lastpos) > limhi)
11261 as_bad (_("Improper extract size (%lu, position %lu)"),
11262 (unsigned long) imm_expr.X_add_number,
11263 (unsigned long) lastpos);
11264 imm_expr.X_add_number = limlo - lastpos;
11266 INSERT_OPERAND (mips_opts.micromips,
11267 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11268 imm_expr.X_op = O_absent;
11273 /* +D is for disassembly only; never match. */
11277 /* "+I" is like "I", except that imm2_expr is used. */
11278 my_getExpression (&imm2_expr, s);
11279 if (imm2_expr.X_op != O_big
11280 && imm2_expr.X_op != O_constant)
11281 insn_error = _("absolute expression required");
11282 if (HAVE_32BIT_GPRS)
11283 normalize_constant_expr (&imm2_expr);
11287 case 'T': /* Coprocessor register. */
11288 gas_assert (!mips_opts.micromips);
11289 /* +T is for disassembly only; never match. */
11292 case 't': /* Coprocessor register number. */
11293 gas_assert (!mips_opts.micromips);
11294 if (s[0] == '$' && ISDIGIT (s[1]))
11304 while (ISDIGIT (*s));
11306 as_bad (_("Invalid register number (%d)"), regno);
11309 INSERT_OPERAND (0, RT, *ip, regno);
11314 as_bad (_("Invalid coprocessor 0 register number"));
11318 /* bbit[01] and bbit[01]32 bit index. Give error if index
11319 is not in the valid range. */
11320 gas_assert (!mips_opts.micromips);
11321 my_getExpression (&imm_expr, s);
11322 check_absolute_expr (ip, &imm_expr);
11323 if ((unsigned) imm_expr.X_add_number > 31)
11325 as_bad (_("Improper bit index (%lu)"),
11326 (unsigned long) imm_expr.X_add_number);
11327 imm_expr.X_add_number = 0;
11329 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11330 imm_expr.X_op = O_absent;
11335 /* bbit[01] bit index when bbit is used but we generate
11336 bbit[01]32 because the index is over 32. Move to the
11337 next candidate if index is not in the valid range. */
11338 gas_assert (!mips_opts.micromips);
11339 my_getExpression (&imm_expr, s);
11340 check_absolute_expr (ip, &imm_expr);
11341 if ((unsigned) imm_expr.X_add_number < 32
11342 || (unsigned) imm_expr.X_add_number > 63)
11344 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11345 imm_expr.X_op = O_absent;
11350 /* cins, cins32, exts and exts32 position field. Give error
11351 if it's not in the valid range. */
11352 gas_assert (!mips_opts.micromips);
11353 my_getExpression (&imm_expr, s);
11354 check_absolute_expr (ip, &imm_expr);
11355 if ((unsigned) imm_expr.X_add_number > 31)
11357 as_bad (_("Improper position (%lu)"),
11358 (unsigned long) imm_expr.X_add_number);
11359 imm_expr.X_add_number = 0;
11361 /* Make the pos explicit to simplify +S. */
11362 lastpos = imm_expr.X_add_number + 32;
11363 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11364 imm_expr.X_op = O_absent;
11369 /* cins, cins32, exts and exts32 position field. Move to
11370 the next candidate if it's not in the valid range. */
11371 gas_assert (!mips_opts.micromips);
11372 my_getExpression (&imm_expr, s);
11373 check_absolute_expr (ip, &imm_expr);
11374 if ((unsigned) imm_expr.X_add_number < 32
11375 || (unsigned) imm_expr.X_add_number > 63)
11377 lastpos = imm_expr.X_add_number;
11378 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11379 imm_expr.X_op = O_absent;
11384 /* cins and exts length-minus-one field. */
11385 gas_assert (!mips_opts.micromips);
11386 my_getExpression (&imm_expr, s);
11387 check_absolute_expr (ip, &imm_expr);
11388 if ((unsigned long) imm_expr.X_add_number > 31)
11390 as_bad (_("Improper size (%lu)"),
11391 (unsigned long) imm_expr.X_add_number);
11392 imm_expr.X_add_number = 0;
11394 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11395 imm_expr.X_op = O_absent;
11400 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11401 length-minus-one field. */
11402 gas_assert (!mips_opts.micromips);
11403 my_getExpression (&imm_expr, s);
11404 check_absolute_expr (ip, &imm_expr);
11405 if ((long) imm_expr.X_add_number < 0
11406 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11408 as_bad (_("Improper size (%lu)"),
11409 (unsigned long) imm_expr.X_add_number);
11410 imm_expr.X_add_number = 0;
11412 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11413 imm_expr.X_op = O_absent;
11418 /* seqi/snei immediate field. */
11419 gas_assert (!mips_opts.micromips);
11420 my_getExpression (&imm_expr, s);
11421 check_absolute_expr (ip, &imm_expr);
11422 if ((long) imm_expr.X_add_number < -512
11423 || (long) imm_expr.X_add_number >= 512)
11425 as_bad (_("Improper immediate (%ld)"),
11426 (long) imm_expr.X_add_number);
11427 imm_expr.X_add_number = 0;
11429 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11430 imm_expr.X_op = O_absent;
11434 case 'a': /* 8-bit signed offset in bit 6 */
11435 gas_assert (!mips_opts.micromips);
11436 my_getExpression (&imm_expr, s);
11437 check_absolute_expr (ip, &imm_expr);
11438 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11439 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11440 if (imm_expr.X_add_number < min_range
11441 || imm_expr.X_add_number > max_range)
11443 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11444 (long) min_range, (long) max_range,
11445 (long) imm_expr.X_add_number);
11447 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11448 imm_expr.X_op = O_absent;
11452 case 'b': /* 8-bit signed offset in bit 3 */
11453 gas_assert (!mips_opts.micromips);
11454 my_getExpression (&imm_expr, s);
11455 check_absolute_expr (ip, &imm_expr);
11456 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11457 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11458 if (imm_expr.X_add_number < min_range
11459 || imm_expr.X_add_number > max_range)
11461 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11462 (long) min_range, (long) max_range,
11463 (long) imm_expr.X_add_number);
11465 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11466 imm_expr.X_op = O_absent;
11470 case 'c': /* 9-bit signed offset in bit 6 */
11471 gas_assert (!mips_opts.micromips);
11472 my_getExpression (&imm_expr, s);
11473 check_absolute_expr (ip, &imm_expr);
11474 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11475 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11476 /* We check the offset range before adjusted. */
11479 if (imm_expr.X_add_number < min_range
11480 || imm_expr.X_add_number > max_range)
11482 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11483 (long) min_range, (long) max_range,
11484 (long) imm_expr.X_add_number);
11486 if (imm_expr.X_add_number & 0xf)
11488 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11489 (long) imm_expr.X_add_number);
11491 /* Right shift 4 bits to adjust the offset operand. */
11492 INSERT_OPERAND (0, OFFSET_C, *ip,
11493 imm_expr.X_add_number >> 4);
11494 imm_expr.X_op = O_absent;
11499 gas_assert (!mips_opts.micromips);
11500 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11502 if (regno == AT && mips_opts.at)
11504 if (mips_opts.at == ATREG)
11505 as_warn (_("used $at without \".set noat\""));
11507 as_warn (_("used $%u with \".set at=$%u\""),
11508 regno, mips_opts.at);
11510 INSERT_OPERAND (0, RZ, *ip, regno);
11514 gas_assert (!mips_opts.micromips);
11515 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11517 INSERT_OPERAND (0, FZ, *ip, regno);
11521 as_bad (_("Internal error: bad %s opcode "
11522 "(unknown extension operand type `+%c'): %s %s"),
11523 mips_opts.micromips ? "microMIPS" : "MIPS",
11524 *args, insn->name, insn->args);
11525 /* Further processing is fruitless. */
11530 case '.': /* 10-bit offset. */
11531 gas_assert (mips_opts.micromips);
11532 case '~': /* 12-bit offset. */
11534 int shift = *args == '.' ? 9 : 11;
11537 /* Check whether there is only a single bracketed expression
11538 left. If so, it must be the base register and the
11539 constant must be zero. */
11540 if (*s == '(' && strchr (s + 1, '(') == 0)
11543 /* If this value won't fit into the offset, then go find
11544 a macro that will generate a 16- or 32-bit offset code
11546 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11547 if ((i == 0 && (imm_expr.X_op != O_constant
11548 || imm_expr.X_add_number >= 1 << shift
11549 || imm_expr.X_add_number < -1 << shift))
11552 imm_expr.X_op = O_absent;
11556 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11558 INSERT_OPERAND (mips_opts.micromips,
11559 OFFSET12, *ip, imm_expr.X_add_number);
11560 imm_expr.X_op = O_absent;
11565 case '<': /* must be at least one digit */
11567 * According to the manual, if the shift amount is greater
11568 * than 31 or less than 0, then the shift amount should be
11569 * mod 32. In reality the mips assembler issues an error.
11570 * We issue a warning and mask out all but the low 5 bits.
11572 my_getExpression (&imm_expr, s);
11573 check_absolute_expr (ip, &imm_expr);
11574 if ((unsigned long) imm_expr.X_add_number > 31)
11575 as_warn (_("Improper shift amount (%lu)"),
11576 (unsigned long) imm_expr.X_add_number);
11577 INSERT_OPERAND (mips_opts.micromips,
11578 SHAMT, *ip, imm_expr.X_add_number);
11579 imm_expr.X_op = O_absent;
11583 case '>': /* shift amount minus 32 */
11584 my_getExpression (&imm_expr, s);
11585 check_absolute_expr (ip, &imm_expr);
11586 if ((unsigned long) imm_expr.X_add_number < 32
11587 || (unsigned long) imm_expr.X_add_number > 63)
11589 INSERT_OPERAND (mips_opts.micromips,
11590 SHAMT, *ip, imm_expr.X_add_number - 32);
11591 imm_expr.X_op = O_absent;
11595 case 'k': /* CACHE code. */
11596 case 'h': /* PREFX code. */
11597 case '1': /* SYNC type. */
11598 my_getExpression (&imm_expr, s);
11599 check_absolute_expr (ip, &imm_expr);
11600 if ((unsigned long) imm_expr.X_add_number > 31)
11601 as_warn (_("Invalid value for `%s' (%lu)"),
11603 (unsigned long) imm_expr.X_add_number);
11607 if (mips_fix_cn63xxp1
11608 && !mips_opts.micromips
11609 && strcmp ("pref", insn->name) == 0)
11610 switch (imm_expr.X_add_number)
11619 case 31: /* These are ok. */
11622 default: /* The rest must be changed to 28. */
11623 imm_expr.X_add_number = 28;
11626 INSERT_OPERAND (mips_opts.micromips,
11627 CACHE, *ip, imm_expr.X_add_number);
11630 INSERT_OPERAND (mips_opts.micromips,
11631 PREFX, *ip, imm_expr.X_add_number);
11634 INSERT_OPERAND (mips_opts.micromips,
11635 STYPE, *ip, imm_expr.X_add_number);
11638 imm_expr.X_op = O_absent;
11642 case 'c': /* BREAK code. */
11644 unsigned long mask = (mips_opts.micromips
11645 ? MICROMIPSOP_MASK_CODE
11648 my_getExpression (&imm_expr, s);
11649 check_absolute_expr (ip, &imm_expr);
11650 if ((unsigned long) imm_expr.X_add_number > mask)
11651 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11653 mask, (unsigned long) imm_expr.X_add_number);
11654 INSERT_OPERAND (mips_opts.micromips,
11655 CODE, *ip, imm_expr.X_add_number);
11656 imm_expr.X_op = O_absent;
11661 case 'q': /* Lower BREAK code. */
11663 unsigned long mask = (mips_opts.micromips
11664 ? MICROMIPSOP_MASK_CODE2
11667 my_getExpression (&imm_expr, s);
11668 check_absolute_expr (ip, &imm_expr);
11669 if ((unsigned long) imm_expr.X_add_number > mask)
11670 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11672 mask, (unsigned long) imm_expr.X_add_number);
11673 INSERT_OPERAND (mips_opts.micromips,
11674 CODE2, *ip, imm_expr.X_add_number);
11675 imm_expr.X_op = O_absent;
11680 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11682 unsigned long mask = (mips_opts.micromips
11683 ? MICROMIPSOP_MASK_CODE10
11686 my_getExpression (&imm_expr, s);
11687 check_absolute_expr (ip, &imm_expr);
11688 if ((unsigned long) imm_expr.X_add_number > mask)
11689 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11691 mask, (unsigned long) imm_expr.X_add_number);
11692 if (mips_opts.micromips)
11693 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11695 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11696 imm_expr.X_op = O_absent;
11701 case 'C': /* 25- or 23-bit coprocessor code. */
11703 unsigned long mask = (mips_opts.micromips
11704 ? MICROMIPSOP_MASK_COPZ
11707 my_getExpression (&imm_expr, s);
11708 check_absolute_expr (ip, &imm_expr);
11709 if ((unsigned long) imm_expr.X_add_number > mask)
11710 as_warn (_("Coproccesor code > %u bits (%lu)"),
11711 mips_opts.micromips ? 23U : 25U,
11712 (unsigned long) imm_expr.X_add_number);
11713 INSERT_OPERAND (mips_opts.micromips,
11714 COPZ, *ip, imm_expr.X_add_number);
11715 imm_expr.X_op = O_absent;
11720 case 'J': /* 19-bit WAIT code. */
11721 gas_assert (!mips_opts.micromips);
11722 my_getExpression (&imm_expr, s);
11723 check_absolute_expr (ip, &imm_expr);
11724 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11726 as_warn (_("Illegal 19-bit code (%lu)"),
11727 (unsigned long) imm_expr.X_add_number);
11728 imm_expr.X_add_number &= OP_MASK_CODE19;
11730 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11731 imm_expr.X_op = O_absent;
11735 case 'P': /* Performance register. */
11736 gas_assert (!mips_opts.micromips);
11737 my_getExpression (&imm_expr, s);
11738 check_absolute_expr (ip, &imm_expr);
11739 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11740 as_warn (_("Invalid performance register (%lu)"),
11741 (unsigned long) imm_expr.X_add_number);
11742 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11743 imm_expr.X_op = O_absent;
11747 case 'G': /* Coprocessor destination register. */
11749 unsigned long opcode = ip->insn_opcode;
11750 unsigned long mask;
11751 unsigned int types;
11754 if (mips_opts.micromips)
11756 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11757 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11758 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11762 case 0x000000fc: /* mfc0 */
11763 case 0x000002fc: /* mtc0 */
11764 case 0x580000fc: /* dmfc0 */
11765 case 0x580002fc: /* dmtc0 */
11775 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11776 cop0 = opcode == OP_OP_COP0;
11778 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11779 ok = reg_lookup (&s, types, ®no);
11780 if (mips_opts.micromips)
11781 INSERT_OPERAND (1, RS, *ip, regno);
11783 INSERT_OPERAND (0, RD, *ip, regno);
11792 case 'y': /* ALNV.PS source register. */
11793 gas_assert (mips_opts.micromips);
11795 case 'x': /* Ignore register name. */
11796 case 'U': /* Destination register (CLO/CLZ). */
11797 case 'g': /* Coprocessor destination register. */
11798 gas_assert (!mips_opts.micromips);
11799 case 'b': /* Base register. */
11800 case 'd': /* Destination register. */
11801 case 's': /* Source register. */
11802 case 't': /* Target register. */
11803 case 'r': /* Both target and source. */
11804 case 'v': /* Both dest and source. */
11805 case 'w': /* Both dest and target. */
11806 case 'E': /* Coprocessor target register. */
11807 case 'K': /* RDHWR destination register. */
11808 case 'z': /* Must be zero register. */
11811 if (*args == 'E' || *args == 'K')
11812 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11815 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11816 if (regno == AT && mips_opts.at)
11818 if (mips_opts.at == ATREG)
11819 as_warn (_("Used $at without \".set noat\""));
11821 as_warn (_("Used $%u with \".set at=$%u\""),
11822 regno, mips_opts.at);
11832 if (c == 'r' || c == 'v' || c == 'w')
11839 /* 'z' only matches $0. */
11840 if (c == 'z' && regno != 0)
11843 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11845 if (regno == lastregno)
11848 = _("Source and destination must be different");
11851 if (regno == 31 && lastregno == 0xffffffff)
11854 = _("A destination register must be supplied");
11858 /* Now that we have assembled one operand, we use the args
11859 string to figure out where it goes in the instruction. */
11866 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11870 if (mips_opts.micromips)
11871 INSERT_OPERAND (1, RS, *ip, regno);
11873 INSERT_OPERAND (0, RD, *ip, regno);
11878 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11882 gas_assert (!mips_opts.micromips);
11883 INSERT_OPERAND (0, RD, *ip, regno);
11884 INSERT_OPERAND (0, RT, *ip, regno);
11890 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11894 gas_assert (mips_opts.micromips);
11895 INSERT_OPERAND (1, RS3, *ip, regno);
11899 /* This case exists because on the r3000 trunc
11900 expands into a macro which requires a gp
11901 register. On the r6000 or r4000 it is
11902 assembled into a single instruction which
11903 ignores the register. Thus the insn version
11904 is MIPS_ISA2 and uses 'x', and the macro
11905 version is MIPS_ISA1 and uses 't'. */
11909 /* This case is for the div instruction, which
11910 acts differently if the destination argument
11911 is $0. This only matches $0, and is checked
11912 outside the switch. */
11922 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11926 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11931 case 'O': /* MDMX alignment immediate constant. */
11932 gas_assert (!mips_opts.micromips);
11933 my_getExpression (&imm_expr, s);
11934 check_absolute_expr (ip, &imm_expr);
11935 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11936 as_warn (_("Improper align amount (%ld), using low bits"),
11937 (long) imm_expr.X_add_number);
11938 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11939 imm_expr.X_op = O_absent;
11943 case 'Q': /* MDMX vector, element sel, or const. */
11946 /* MDMX Immediate. */
11947 gas_assert (!mips_opts.micromips);
11948 my_getExpression (&imm_expr, s);
11949 check_absolute_expr (ip, &imm_expr);
11950 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
11951 as_warn (_("Invalid MDMX Immediate (%ld)"),
11952 (long) imm_expr.X_add_number);
11953 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
11954 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11955 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11957 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
11958 imm_expr.X_op = O_absent;
11962 /* Not MDMX Immediate. Fall through. */
11963 case 'X': /* MDMX destination register. */
11964 case 'Y': /* MDMX source register. */
11965 case 'Z': /* MDMX target register. */
11968 gas_assert (!mips_opts.micromips);
11969 case 'D': /* Floating point destination register. */
11970 case 'S': /* Floating point source register. */
11971 case 'T': /* Floating point target register. */
11972 case 'R': /* Floating point source register. */
11976 || (mips_opts.ase_mdmx
11977 && (ip->insn_mo->pinfo & FP_D)
11978 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11979 | INSN_COPROC_MEMORY_DELAY
11980 | INSN_LOAD_COPROC_DELAY
11981 | INSN_LOAD_MEMORY_DELAY
11982 | INSN_STORE_MEMORY))))
11983 rtype |= RTYPE_VEC;
11985 if (reg_lookup (&s, rtype, ®no))
11987 if ((regno & 1) != 0
11989 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
11990 as_warn (_("Float register should be even, was %d"),
11998 if (c == 'V' || c == 'W')
12009 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12015 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12019 /* This is like 'Z', but also needs to fix the MDMX
12020 vector/scalar select bits. Note that the
12021 scalar immediate case is handled above. */
12024 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12025 int max_el = (is_qh ? 3 : 7);
12027 my_getExpression(&imm_expr, s);
12028 check_absolute_expr (ip, &imm_expr);
12030 if (imm_expr.X_add_number > max_el)
12031 as_bad (_("Bad element selector %ld"),
12032 (long) imm_expr.X_add_number);
12033 imm_expr.X_add_number &= max_el;
12034 ip->insn_opcode |= (imm_expr.X_add_number
12037 imm_expr.X_op = O_absent;
12039 as_warn (_("Expecting ']' found '%s'"), s);
12045 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12046 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12049 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12052 /* Fall through. */
12056 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12060 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12070 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12074 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12080 my_getExpression (&imm_expr, s);
12081 if (imm_expr.X_op != O_big
12082 && imm_expr.X_op != O_constant)
12083 insn_error = _("absolute expression required");
12084 if (HAVE_32BIT_GPRS)
12085 normalize_constant_expr (&imm_expr);
12090 my_getExpression (&offset_expr, s);
12091 normalize_address_expr (&offset_expr);
12092 *imm_reloc = BFD_RELOC_32;
12105 unsigned char temp[8];
12107 unsigned int length;
12112 /* These only appear as the last operand in an
12113 instruction, and every instruction that accepts
12114 them in any variant accepts them in all variants.
12115 This means we don't have to worry about backing out
12116 any changes if the instruction does not match.
12118 The difference between them is the size of the
12119 floating point constant and where it goes. For 'F'
12120 and 'L' the constant is 64 bits; for 'f' and 'l' it
12121 is 32 bits. Where the constant is placed is based
12122 on how the MIPS assembler does things:
12125 f -- immediate value
12128 The .lit4 and .lit8 sections are only used if
12129 permitted by the -G argument.
12131 The code below needs to know whether the target register
12132 is 32 or 64 bits wide. It relies on the fact 'f' and
12133 'F' are used with GPR-based instructions and 'l' and
12134 'L' are used with FPR-based instructions. */
12136 f64 = *args == 'F' || *args == 'L';
12137 using_gprs = *args == 'F' || *args == 'f';
12139 save_in = input_line_pointer;
12140 input_line_pointer = s;
12141 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12143 s = input_line_pointer;
12144 input_line_pointer = save_in;
12145 if (err != NULL && *err != '\0')
12147 as_bad (_("Bad floating point constant: %s"), err);
12148 memset (temp, '\0', sizeof temp);
12149 length = f64 ? 8 : 4;
12152 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12156 && (g_switch_value < 4
12157 || (temp[0] == 0 && temp[1] == 0)
12158 || (temp[2] == 0 && temp[3] == 0))))
12160 imm_expr.X_op = O_constant;
12161 if (!target_big_endian)
12162 imm_expr.X_add_number = bfd_getl32 (temp);
12164 imm_expr.X_add_number = bfd_getb32 (temp);
12166 else if (length > 4
12167 && !mips_disable_float_construction
12168 /* Constants can only be constructed in GPRs and
12169 copied to FPRs if the GPRs are at least as wide
12170 as the FPRs. Force the constant into memory if
12171 we are using 64-bit FPRs but the GPRs are only
12174 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12175 && ((temp[0] == 0 && temp[1] == 0)
12176 || (temp[2] == 0 && temp[3] == 0))
12177 && ((temp[4] == 0 && temp[5] == 0)
12178 || (temp[6] == 0 && temp[7] == 0)))
12180 /* The value is simple enough to load with a couple of
12181 instructions. If using 32-bit registers, set
12182 imm_expr to the high order 32 bits and offset_expr to
12183 the low order 32 bits. Otherwise, set imm_expr to
12184 the entire 64 bit constant. */
12185 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12187 imm_expr.X_op = O_constant;
12188 offset_expr.X_op = O_constant;
12189 if (!target_big_endian)
12191 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12192 offset_expr.X_add_number = bfd_getl32 (temp);
12196 imm_expr.X_add_number = bfd_getb32 (temp);
12197 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12199 if (offset_expr.X_add_number == 0)
12200 offset_expr.X_op = O_absent;
12202 else if (sizeof (imm_expr.X_add_number) > 4)
12204 imm_expr.X_op = O_constant;
12205 if (!target_big_endian)
12206 imm_expr.X_add_number = bfd_getl64 (temp);
12208 imm_expr.X_add_number = bfd_getb64 (temp);
12212 imm_expr.X_op = O_big;
12213 imm_expr.X_add_number = 4;
12214 if (!target_big_endian)
12216 generic_bignum[0] = bfd_getl16 (temp);
12217 generic_bignum[1] = bfd_getl16 (temp + 2);
12218 generic_bignum[2] = bfd_getl16 (temp + 4);
12219 generic_bignum[3] = bfd_getl16 (temp + 6);
12223 generic_bignum[0] = bfd_getb16 (temp + 6);
12224 generic_bignum[1] = bfd_getb16 (temp + 4);
12225 generic_bignum[2] = bfd_getb16 (temp + 2);
12226 generic_bignum[3] = bfd_getb16 (temp);
12232 const char *newname;
12235 /* Switch to the right section. */
12237 subseg = now_subseg;
12240 default: /* unused default case avoids warnings. */
12242 newname = RDATA_SECTION_NAME;
12243 if (g_switch_value >= 8)
12247 newname = RDATA_SECTION_NAME;
12250 gas_assert (g_switch_value >= 4);
12254 new_seg = subseg_new (newname, (subsegT) 0);
12256 bfd_set_section_flags (stdoutput, new_seg,
12261 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12262 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12263 record_alignment (new_seg, 4);
12265 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12266 if (seg == now_seg)
12267 as_bad (_("Can't use floating point insn in this section"));
12269 /* Set the argument to the current address in the
12271 offset_expr.X_op = O_symbol;
12272 offset_expr.X_add_symbol = symbol_temp_new_now ();
12273 offset_expr.X_add_number = 0;
12275 /* Put the floating point number into the section. */
12276 p = frag_more ((int) length);
12277 memcpy (p, temp, length);
12279 /* Switch back to the original section. */
12280 subseg_set (seg, subseg);
12285 case 'i': /* 16-bit unsigned immediate. */
12286 case 'j': /* 16-bit signed immediate. */
12287 *imm_reloc = BFD_RELOC_LO16;
12288 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12291 offsetT minval, maxval;
12293 more = (insn + 1 < past
12294 && strcmp (insn->name, insn[1].name) == 0);
12296 /* If the expression was written as an unsigned number,
12297 only treat it as signed if there are no more
12301 && sizeof (imm_expr.X_add_number) <= 4
12302 && imm_expr.X_op == O_constant
12303 && imm_expr.X_add_number < 0
12304 && imm_expr.X_unsigned
12305 && HAVE_64BIT_GPRS)
12308 /* For compatibility with older assemblers, we accept
12309 0x8000-0xffff as signed 16-bit numbers when only
12310 signed numbers are allowed. */
12312 minval = 0, maxval = 0xffff;
12314 minval = -0x8000, maxval = 0x7fff;
12316 minval = -0x8000, maxval = 0xffff;
12318 if (imm_expr.X_op != O_constant
12319 || imm_expr.X_add_number < minval
12320 || imm_expr.X_add_number > maxval)
12324 if (imm_expr.X_op == O_constant
12325 || imm_expr.X_op == O_big)
12326 as_bad (_("Expression out of range"));
12332 case 'o': /* 16-bit offset. */
12333 offset_reloc[0] = BFD_RELOC_LO16;
12334 offset_reloc[1] = BFD_RELOC_UNUSED;
12335 offset_reloc[2] = BFD_RELOC_UNUSED;
12337 /* Check whether there is only a single bracketed expression
12338 left. If so, it must be the base register and the
12339 constant must be zero. */
12340 if (*s == '(' && strchr (s + 1, '(') == 0)
12342 offset_expr.X_op = O_constant;
12343 offset_expr.X_add_number = 0;
12347 /* If this value won't fit into a 16 bit offset, then go
12348 find a macro that will generate the 32 bit offset
12350 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12351 && (offset_expr.X_op != O_constant
12352 || offset_expr.X_add_number >= 0x8000
12353 || offset_expr.X_add_number < -0x8000))
12359 case 'p': /* PC-relative offset. */
12360 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12361 my_getExpression (&offset_expr, s);
12365 case 'u': /* Upper 16 bits. */
12366 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12367 && imm_expr.X_op == O_constant
12368 && (imm_expr.X_add_number < 0
12369 || imm_expr.X_add_number >= 0x10000))
12370 as_bad (_("lui expression (%lu) not in range 0..65535"),
12371 (unsigned long) imm_expr.X_add_number);
12375 case 'a': /* 26-bit address. */
12376 *offset_reloc = BFD_RELOC_MIPS_JMP;
12377 my_getExpression (&offset_expr, s);
12381 case 'N': /* 3-bit branch condition code. */
12382 case 'M': /* 3-bit compare condition code. */
12384 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12385 rtype |= RTYPE_FCC;
12386 if (!reg_lookup (&s, rtype, ®no))
12388 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12389 || strcmp (str + strlen (str) - 5, "any2f") == 0
12390 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12391 && (regno & 1) != 0)
12392 as_warn (_("Condition code register should be even for %s, "
12395 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12396 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12397 && (regno & 3) != 0)
12398 as_warn (_("Condition code register should be 0 or 4 for %s, "
12402 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12404 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12408 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12419 while (ISDIGIT (*s));
12422 c = 8; /* Invalid sel value. */
12425 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12426 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12430 gas_assert (!mips_opts.micromips);
12431 /* Must be at least one digit. */
12432 my_getExpression (&imm_expr, s);
12433 check_absolute_expr (ip, &imm_expr);
12435 if ((unsigned long) imm_expr.X_add_number
12436 > (unsigned long) OP_MASK_VECBYTE)
12438 as_bad (_("bad byte vector index (%ld)"),
12439 (long) imm_expr.X_add_number);
12440 imm_expr.X_add_number = 0;
12443 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12444 imm_expr.X_op = O_absent;
12449 gas_assert (!mips_opts.micromips);
12450 my_getExpression (&imm_expr, s);
12451 check_absolute_expr (ip, &imm_expr);
12453 if ((unsigned long) imm_expr.X_add_number
12454 > (unsigned long) OP_MASK_VECALIGN)
12456 as_bad (_("bad byte vector index (%ld)"),
12457 (long) imm_expr.X_add_number);
12458 imm_expr.X_add_number = 0;
12461 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12462 imm_expr.X_op = O_absent;
12466 case 'm': /* Opcode extension character. */
12467 gas_assert (mips_opts.micromips);
12472 if (strncmp (s, "$pc", 3) == 0)
12500 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12501 if (regno == AT && mips_opts.at)
12503 if (mips_opts.at == ATREG)
12504 as_warn (_("Used $at without \".set noat\""));
12506 as_warn (_("Used $%u with \".set at=$%u\""),
12507 regno, mips_opts.at);
12513 gas_assert (args[1] == ',');
12519 gas_assert (args[1] == ',');
12521 continue; /* Nothing to do. */
12527 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12529 if (regno == lastregno)
12532 = _("Source and destination must be different");
12535 if (regno == 31 && lastregno == 0xffffffff)
12538 = _("A destination register must be supplied");
12549 gas_assert (args[1] == ',');
12556 gas_assert (args[1] == ',');
12559 continue; /* Nothing to do. */
12563 /* Make sure regno is the same as lastregno. */
12564 if (c == 't' && regno != lastregno)
12567 /* Make sure regno is the same as destregno. */
12568 if (c == 'x' && regno != destregno)
12571 /* We need to save regno, before regno maps to the
12572 microMIPS register encoding. */
12582 regno = ILLEGAL_REG;
12586 regno = mips32_to_micromips_reg_b_map[regno];
12590 regno = mips32_to_micromips_reg_c_map[regno];
12594 regno = mips32_to_micromips_reg_d_map[regno];
12598 regno = mips32_to_micromips_reg_e_map[regno];
12602 regno = mips32_to_micromips_reg_f_map[regno];
12606 regno = mips32_to_micromips_reg_g_map[regno];
12610 regno = mips32_to_micromips_reg_h_map[regno];
12614 switch (EXTRACT_OPERAND (1, MI, *ip))
12619 else if (regno == 22)
12621 else if (regno == 5)
12623 else if (regno == 6)
12625 else if (regno == 7)
12628 regno = ILLEGAL_REG;
12634 else if (regno == 7)
12637 regno = ILLEGAL_REG;
12644 regno = ILLEGAL_REG;
12648 regno = ILLEGAL_REG;
12654 regno = mips32_to_micromips_reg_l_map[regno];
12658 regno = mips32_to_micromips_reg_m_map[regno];
12662 regno = mips32_to_micromips_reg_n_map[regno];
12666 regno = mips32_to_micromips_reg_q_map[regno];
12671 regno = ILLEGAL_REG;
12676 regno = ILLEGAL_REG;
12681 regno = ILLEGAL_REG;
12684 case 'j': /* Do nothing. */
12694 if (regno == ILLEGAL_REG)
12700 INSERT_OPERAND (1, MB, *ip, regno);
12704 INSERT_OPERAND (1, MC, *ip, regno);
12708 INSERT_OPERAND (1, MD, *ip, regno);
12712 INSERT_OPERAND (1, ME, *ip, regno);
12716 INSERT_OPERAND (1, MF, *ip, regno);
12720 INSERT_OPERAND (1, MG, *ip, regno);
12724 INSERT_OPERAND (1, MH, *ip, regno);
12728 INSERT_OPERAND (1, MI, *ip, regno);
12732 INSERT_OPERAND (1, MJ, *ip, regno);
12736 INSERT_OPERAND (1, ML, *ip, regno);
12740 INSERT_OPERAND (1, MM, *ip, regno);
12744 INSERT_OPERAND (1, MN, *ip, regno);
12748 INSERT_OPERAND (1, MP, *ip, regno);
12752 INSERT_OPERAND (1, MQ, *ip, regno);
12755 case 'a': /* Do nothing. */
12756 case 's': /* Do nothing. */
12757 case 't': /* Do nothing. */
12758 case 'x': /* Do nothing. */
12759 case 'y': /* Do nothing. */
12760 case 'z': /* Do nothing. */
12770 bfd_reloc_code_real_type r[3];
12774 /* Check whether there is only a single bracketed
12775 expression left. If so, it must be the base register
12776 and the constant must be zero. */
12777 if (*s == '(' && strchr (s + 1, '(') == 0)
12779 INSERT_OPERAND (1, IMMA, *ip, 0);
12783 if (my_getSmallExpression (&ep, r, s) > 0
12784 || !expr_const_in_range (&ep, -64, 64, 2))
12787 imm = ep.X_add_number >> 2;
12788 INSERT_OPERAND (1, IMMA, *ip, imm);
12795 bfd_reloc_code_real_type r[3];
12799 if (my_getSmallExpression (&ep, r, s) > 0
12800 || ep.X_op != O_constant)
12803 for (imm = 0; imm < 8; imm++)
12804 if (micromips_imm_b_map[imm] == ep.X_add_number)
12809 INSERT_OPERAND (1, IMMB, *ip, imm);
12816 bfd_reloc_code_real_type r[3];
12820 if (my_getSmallExpression (&ep, r, s) > 0
12821 || ep.X_op != O_constant)
12824 for (imm = 0; imm < 16; imm++)
12825 if (micromips_imm_c_map[imm] == ep.X_add_number)
12830 INSERT_OPERAND (1, IMMC, *ip, imm);
12835 case 'D': /* pc relative offset */
12836 case 'E': /* pc relative offset */
12837 my_getExpression (&offset_expr, s);
12838 if (offset_expr.X_op == O_register)
12841 if (!forced_insn_length)
12842 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12844 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12846 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12852 bfd_reloc_code_real_type r[3];
12856 if (my_getSmallExpression (&ep, r, s) > 0
12857 || !expr_const_in_range (&ep, 0, 16, 0))
12860 imm = ep.X_add_number;
12861 INSERT_OPERAND (1, IMMF, *ip, imm);
12868 bfd_reloc_code_real_type r[3];
12872 /* Check whether there is only a single bracketed
12873 expression left. If so, it must be the base register
12874 and the constant must be zero. */
12875 if (*s == '(' && strchr (s + 1, '(') == 0)
12877 INSERT_OPERAND (1, IMMG, *ip, 0);
12881 if (my_getSmallExpression (&ep, r, s) > 0
12882 || !expr_const_in_range (&ep, -1, 15, 0))
12885 imm = ep.X_add_number & 15;
12886 INSERT_OPERAND (1, IMMG, *ip, imm);
12893 bfd_reloc_code_real_type r[3];
12897 /* Check whether there is only a single bracketed
12898 expression left. If so, it must be the base register
12899 and the constant must be zero. */
12900 if (*s == '(' && strchr (s + 1, '(') == 0)
12902 INSERT_OPERAND (1, IMMH, *ip, 0);
12906 if (my_getSmallExpression (&ep, r, s) > 0
12907 || !expr_const_in_range (&ep, 0, 16, 1))
12910 imm = ep.X_add_number >> 1;
12911 INSERT_OPERAND (1, IMMH, *ip, imm);
12918 bfd_reloc_code_real_type r[3];
12922 if (my_getSmallExpression (&ep, r, s) > 0
12923 || !expr_const_in_range (&ep, -1, 127, 0))
12926 imm = ep.X_add_number & 127;
12927 INSERT_OPERAND (1, IMMI, *ip, imm);
12934 bfd_reloc_code_real_type r[3];
12938 /* Check whether there is only a single bracketed
12939 expression left. If so, it must be the base register
12940 and the constant must be zero. */
12941 if (*s == '(' && strchr (s + 1, '(') == 0)
12943 INSERT_OPERAND (1, IMMJ, *ip, 0);
12947 if (my_getSmallExpression (&ep, r, s) > 0
12948 || !expr_const_in_range (&ep, 0, 16, 2))
12951 imm = ep.X_add_number >> 2;
12952 INSERT_OPERAND (1, IMMJ, *ip, imm);
12959 bfd_reloc_code_real_type r[3];
12963 /* Check whether there is only a single bracketed
12964 expression left. If so, it must be the base register
12965 and the constant must be zero. */
12966 if (*s == '(' && strchr (s + 1, '(') == 0)
12968 INSERT_OPERAND (1, IMML, *ip, 0);
12972 if (my_getSmallExpression (&ep, r, s) > 0
12973 || !expr_const_in_range (&ep, 0, 16, 0))
12976 imm = ep.X_add_number;
12977 INSERT_OPERAND (1, IMML, *ip, imm);
12984 bfd_reloc_code_real_type r[3];
12988 if (my_getSmallExpression (&ep, r, s) > 0
12989 || !expr_const_in_range (&ep, 1, 9, 0))
12992 imm = ep.X_add_number & 7;
12993 INSERT_OPERAND (1, IMMM, *ip, imm);
12998 case 'N': /* Register list for lwm and swm. */
13000 /* A comma-separated list of registers and/or
13001 dash-separated contiguous ranges including
13002 both ra and a set of one or more registers
13003 starting at s0 up to s3 which have to be
13010 and any permutations of these. */
13011 unsigned int reglist;
13014 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13017 if ((reglist & 0xfff1ffff) != 0x80010000)
13020 reglist = (reglist >> 17) & 7;
13022 if ((reglist & -reglist) != reglist)
13025 imm = ffs (reglist) - 1;
13026 INSERT_OPERAND (1, IMMN, *ip, imm);
13030 case 'O': /* sdbbp 4-bit code. */
13032 bfd_reloc_code_real_type r[3];
13036 if (my_getSmallExpression (&ep, r, s) > 0
13037 || !expr_const_in_range (&ep, 0, 16, 0))
13040 imm = ep.X_add_number;
13041 INSERT_OPERAND (1, IMMO, *ip, imm);
13048 bfd_reloc_code_real_type r[3];
13052 if (my_getSmallExpression (&ep, r, s) > 0
13053 || !expr_const_in_range (&ep, 0, 32, 2))
13056 imm = ep.X_add_number >> 2;
13057 INSERT_OPERAND (1, IMMP, *ip, imm);
13064 bfd_reloc_code_real_type r[3];
13068 if (my_getSmallExpression (&ep, r, s) > 0
13069 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13072 imm = ep.X_add_number >> 2;
13073 INSERT_OPERAND (1, IMMQ, *ip, imm);
13080 bfd_reloc_code_real_type r[3];
13084 /* Check whether there is only a single bracketed
13085 expression left. If so, it must be the base register
13086 and the constant must be zero. */
13087 if (*s == '(' && strchr (s + 1, '(') == 0)
13089 INSERT_OPERAND (1, IMMU, *ip, 0);
13093 if (my_getSmallExpression (&ep, r, s) > 0
13094 || !expr_const_in_range (&ep, 0, 32, 2))
13097 imm = ep.X_add_number >> 2;
13098 INSERT_OPERAND (1, IMMU, *ip, imm);
13105 bfd_reloc_code_real_type r[3];
13109 if (my_getSmallExpression (&ep, r, s) > 0
13110 || !expr_const_in_range (&ep, 0, 64, 2))
13113 imm = ep.X_add_number >> 2;
13114 INSERT_OPERAND (1, IMMW, *ip, imm);
13121 bfd_reloc_code_real_type r[3];
13125 if (my_getSmallExpression (&ep, r, s) > 0
13126 || !expr_const_in_range (&ep, -8, 8, 0))
13129 imm = ep.X_add_number;
13130 INSERT_OPERAND (1, IMMX, *ip, imm);
13137 bfd_reloc_code_real_type r[3];
13141 if (my_getSmallExpression (&ep, r, s) > 0
13142 || expr_const_in_range (&ep, -2, 2, 2)
13143 || !expr_const_in_range (&ep, -258, 258, 2))
13146 imm = ep.X_add_number >> 2;
13147 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13148 INSERT_OPERAND (1, IMMY, *ip, imm);
13155 bfd_reloc_code_real_type r[3];
13158 if (my_getSmallExpression (&ep, r, s) > 0
13159 || !expr_const_in_range (&ep, 0, 1, 0))
13166 as_bad (_("Internal error: bad microMIPS opcode "
13167 "(unknown extension operand type `m%c'): %s %s"),
13168 *args, insn->name, insn->args);
13169 /* Further processing is fruitless. */
13174 case 'n': /* Register list for 32-bit lwm and swm. */
13175 gas_assert (mips_opts.micromips);
13177 /* A comma-separated list of registers and/or
13178 dash-separated contiguous ranges including
13179 at least one of ra and a set of one or more
13180 registers starting at s0 up to s7 and then
13181 s8 which have to be consecutive, e.g.:
13189 and any permutations of these. */
13190 unsigned int reglist;
13194 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13197 if ((reglist & 0x3f00ffff) != 0)
13200 ra = (reglist >> 27) & 0x10;
13201 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13203 if ((reglist & -reglist) != reglist)
13206 imm = (ffs (reglist) - 1) | ra;
13207 INSERT_OPERAND (1, RT, *ip, imm);
13208 imm_expr.X_op = O_absent;
13212 case '|': /* 4-bit trap code. */
13213 gas_assert (mips_opts.micromips);
13214 my_getExpression (&imm_expr, s);
13215 check_absolute_expr (ip, &imm_expr);
13216 if ((unsigned long) imm_expr.X_add_number
13217 > MICROMIPSOP_MASK_TRAP)
13218 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13219 (unsigned long) imm_expr.X_add_number,
13220 ip->insn_mo->name);
13221 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13222 imm_expr.X_op = O_absent;
13227 as_bad (_("Bad char = '%c'\n"), *args);
13232 /* Args don't match. */
13234 insn_error = _("Illegal operands");
13235 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13240 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13242 gas_assert (firstinsn);
13243 need_delay_slot_ok = FALSE;
13252 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13254 /* This routine assembles an instruction into its binary format when
13255 assembling for the mips16. As a side effect, it sets one of the
13256 global variables imm_reloc or offset_reloc to the type of relocation
13257 to do if one of the operands is an address expression. It also sets
13258 forced_insn_length to the resulting instruction size in bytes if the
13259 user explicitly requested a small or extended instruction. */
13262 mips16_ip (char *str, struct mips_cl_insn *ip)
13266 struct mips_opcode *insn;
13268 unsigned int regno;
13269 unsigned int lastregno = 0;
13275 forced_insn_length = 0;
13277 for (s = str; ISLOWER (*s); ++s)
13289 if (s[1] == 't' && s[2] == ' ')
13292 forced_insn_length = 2;
13296 else if (s[1] == 'e' && s[2] == ' ')
13299 forced_insn_length = 4;
13303 /* Fall through. */
13305 insn_error = _("unknown opcode");
13309 if (mips_opts.noautoextend && !forced_insn_length)
13310 forced_insn_length = 2;
13312 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13314 insn_error = _("unrecognized opcode");
13323 gas_assert (strcmp (insn->name, str) == 0);
13325 ok = is_opcode_valid_16 (insn);
13328 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13329 && strcmp (insn->name, insn[1].name) == 0)
13338 static char buf[100];
13340 _("Opcode not supported on this processor: %s (%s)"),
13341 mips_cpu_info_from_arch (mips_opts.arch)->name,
13342 mips_cpu_info_from_isa (mips_opts.isa)->name);
13349 create_insn (ip, insn);
13350 imm_expr.X_op = O_absent;
13351 imm_reloc[0] = BFD_RELOC_UNUSED;
13352 imm_reloc[1] = BFD_RELOC_UNUSED;
13353 imm_reloc[2] = BFD_RELOC_UNUSED;
13354 imm2_expr.X_op = O_absent;
13355 offset_expr.X_op = O_absent;
13356 offset_reloc[0] = BFD_RELOC_UNUSED;
13357 offset_reloc[1] = BFD_RELOC_UNUSED;
13358 offset_reloc[2] = BFD_RELOC_UNUSED;
13359 for (args = insn->args; 1; ++args)
13366 /* In this switch statement we call break if we did not find
13367 a match, continue if we did find a match, or return if we
13376 /* Stuff the immediate value in now, if we can. */
13377 if (imm_expr.X_op == O_constant
13378 && *imm_reloc > BFD_RELOC_UNUSED
13379 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13380 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
13381 && insn->pinfo != INSN_MACRO)
13385 switch (*offset_reloc)
13387 case BFD_RELOC_MIPS16_HI16_S:
13388 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13391 case BFD_RELOC_MIPS16_HI16:
13392 tmp = imm_expr.X_add_number >> 16;
13395 case BFD_RELOC_MIPS16_LO16:
13396 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13400 case BFD_RELOC_UNUSED:
13401 tmp = imm_expr.X_add_number;
13407 *offset_reloc = BFD_RELOC_UNUSED;
13409 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13410 tmp, TRUE, forced_insn_length == 2,
13411 forced_insn_length == 4, &ip->insn_opcode,
13412 &ip->use_extend, &ip->extend);
13413 imm_expr.X_op = O_absent;
13414 *imm_reloc = BFD_RELOC_UNUSED;
13428 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13431 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13447 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13449 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13453 /* Fall through. */
13464 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13466 if (c == 'v' || c == 'w')
13469 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13471 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13482 if (c == 'v' || c == 'w')
13484 regno = mips16_to_32_reg_map[lastregno];
13498 regno = mips32_to_16_reg_map[regno];
13503 regno = ILLEGAL_REG;
13508 regno = ILLEGAL_REG;
13513 regno = ILLEGAL_REG;
13518 if (regno == AT && mips_opts.at)
13520 if (mips_opts.at == ATREG)
13521 as_warn (_("used $at without \".set noat\""));
13523 as_warn (_("used $%u with \".set at=$%u\""),
13524 regno, mips_opts.at);
13532 if (regno == ILLEGAL_REG)
13539 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13543 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13546 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13549 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13555 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13558 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13559 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13569 if (strncmp (s, "$pc", 3) == 0)
13586 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13589 if (imm_expr.X_op != O_constant)
13591 forced_insn_length = 4;
13592 ip->use_extend = TRUE;
13597 /* We need to relax this instruction. */
13598 *offset_reloc = *imm_reloc;
13599 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13604 *imm_reloc = BFD_RELOC_UNUSED;
13605 /* Fall through. */
13612 my_getExpression (&imm_expr, s);
13613 if (imm_expr.X_op == O_register)
13615 /* What we thought was an expression turned out to
13618 if (s[0] == '(' && args[1] == '(')
13620 /* It looks like the expression was omitted
13621 before a register indirection, which means
13622 that the expression is implicitly zero. We
13623 still set up imm_expr, so that we handle
13624 explicit extensions correctly. */
13625 imm_expr.X_op = O_constant;
13626 imm_expr.X_add_number = 0;
13627 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13634 /* We need to relax this instruction. */
13635 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13644 /* We use offset_reloc rather than imm_reloc for the PC
13645 relative operands. This lets macros with both
13646 immediate and address operands work correctly. */
13647 my_getExpression (&offset_expr, s);
13649 if (offset_expr.X_op == O_register)
13652 /* We need to relax this instruction. */
13653 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13657 case '6': /* break code */
13658 my_getExpression (&imm_expr, s);
13659 check_absolute_expr (ip, &imm_expr);
13660 if ((unsigned long) imm_expr.X_add_number > 63)
13661 as_warn (_("Invalid value for `%s' (%lu)"),
13663 (unsigned long) imm_expr.X_add_number);
13664 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13665 imm_expr.X_op = O_absent;
13669 case 'a': /* 26 bit address */
13670 my_getExpression (&offset_expr, s);
13672 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13673 ip->insn_opcode <<= 16;
13676 case 'l': /* register list for entry macro */
13677 case 'L': /* register list for exit macro */
13687 unsigned int freg, reg1, reg2;
13689 while (*s == ' ' || *s == ',')
13691 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13693 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13697 as_bad (_("can't parse register list"));
13707 if (!reg_lookup (&s, freg ? RTYPE_FPU
13708 : (RTYPE_GP | RTYPE_NUM), ®2))
13710 as_bad (_("invalid register list"));
13714 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13716 mask &= ~ (7 << 3);
13719 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13721 mask &= ~ (7 << 3);
13724 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13725 mask |= (reg2 - 3) << 3;
13726 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13727 mask |= (reg2 - 15) << 1;
13728 else if (reg1 == RA && reg2 == RA)
13732 as_bad (_("invalid register list"));
13736 /* The mask is filled in in the opcode table for the
13737 benefit of the disassembler. We remove it before
13738 applying the actual mask. */
13739 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13740 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13744 case 'm': /* Register list for save insn. */
13745 case 'M': /* Register list for restore insn. */
13748 int framesz = 0, seen_framesz = 0;
13749 int nargs = 0, statics = 0, sregs = 0;
13753 unsigned int reg1, reg2;
13755 SKIP_SPACE_TABS (s);
13758 SKIP_SPACE_TABS (s);
13760 my_getExpression (&imm_expr, s);
13761 if (imm_expr.X_op == O_constant)
13763 /* Handle the frame size. */
13766 as_bad (_("more than one frame size in list"));
13770 framesz = imm_expr.X_add_number;
13771 imm_expr.X_op = O_absent;
13776 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13778 as_bad (_("can't parse register list"));
13790 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13793 as_bad (_("can't parse register list"));
13798 while (reg1 <= reg2)
13800 if (reg1 >= 4 && reg1 <= 7)
13804 nargs |= 1 << (reg1 - 4);
13806 /* statics $a0-$a3 */
13807 statics |= 1 << (reg1 - 4);
13809 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13812 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13814 else if (reg1 == 31)
13816 /* Add $ra to insn. */
13821 as_bad (_("unexpected register in list"));
13829 /* Encode args/statics combination. */
13830 if (nargs & statics)
13831 as_bad (_("arg/static registers overlap"));
13832 else if (nargs == 0xf)
13833 /* All $a0-$a3 are args. */
13834 opcode |= MIPS16_ALL_ARGS << 16;
13835 else if (statics == 0xf)
13836 /* All $a0-$a3 are statics. */
13837 opcode |= MIPS16_ALL_STATICS << 16;
13840 int narg = 0, nstat = 0;
13842 /* Count arg registers. */
13843 while (nargs & 0x1)
13849 as_bad (_("invalid arg register list"));
13851 /* Count static registers. */
13852 while (statics & 0x8)
13854 statics = (statics << 1) & 0xf;
13858 as_bad (_("invalid static register list"));
13860 /* Encode args/statics. */
13861 opcode |= ((narg << 2) | nstat) << 16;
13864 /* Encode $s0/$s1. */
13865 if (sregs & (1 << 0)) /* $s0 */
13867 if (sregs & (1 << 1)) /* $s1 */
13873 /* Count regs $s2-$s8. */
13881 as_bad (_("invalid static register list"));
13882 /* Encode $s2-$s8. */
13883 opcode |= nsreg << 24;
13886 /* Encode frame size. */
13888 as_bad (_("missing frame size"));
13889 else if ((framesz & 7) != 0 || framesz < 0
13890 || framesz > 0xff * 8)
13891 as_bad (_("invalid frame size"));
13892 else if (framesz != 128 || (opcode >> 16) != 0)
13895 opcode |= (((framesz & 0xf0) << 16)
13896 | (framesz & 0x0f));
13899 /* Finally build the instruction. */
13900 if ((opcode >> 16) != 0 || framesz == 0)
13902 ip->use_extend = TRUE;
13903 ip->extend = opcode >> 16;
13905 ip->insn_opcode |= opcode & 0x7f;
13909 case 'e': /* extend code */
13910 my_getExpression (&imm_expr, s);
13911 check_absolute_expr (ip, &imm_expr);
13912 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13914 as_warn (_("Invalid value for `%s' (%lu)"),
13916 (unsigned long) imm_expr.X_add_number);
13917 imm_expr.X_add_number &= 0x7ff;
13919 ip->insn_opcode |= imm_expr.X_add_number;
13920 imm_expr.X_op = O_absent;
13930 /* Args don't match. */
13931 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13932 strcmp (insn->name, insn[1].name) == 0)
13939 insn_error = _("illegal operands");
13945 /* This structure holds information we know about a mips16 immediate
13948 struct mips16_immed_operand
13950 /* The type code used in the argument string in the opcode table. */
13952 /* The number of bits in the short form of the opcode. */
13954 /* The number of bits in the extended form of the opcode. */
13956 /* The amount by which the short form is shifted when it is used;
13957 for example, the sw instruction has a shift count of 2. */
13959 /* The amount by which the short form is shifted when it is stored
13960 into the instruction code. */
13962 /* Non-zero if the short form is unsigned. */
13964 /* Non-zero if the extended form is unsigned. */
13966 /* Non-zero if the value is PC relative. */
13970 /* The mips16 immediate operand types. */
13972 static const struct mips16_immed_operand mips16_immed_operands[] =
13974 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13975 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13976 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13977 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13978 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13979 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13980 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13981 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13982 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13983 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13984 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13985 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13986 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13987 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13988 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13989 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13990 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13991 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13992 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13993 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13994 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13997 #define MIPS16_NUM_IMMED \
13998 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14000 /* Handle a mips16 instruction with an immediate value. This or's the
14001 small immediate value into *INSN. It sets *USE_EXTEND to indicate
14002 whether an extended value is needed; if one is needed, it sets
14003 *EXTEND to the value. The argument type is TYPE. The value is VAL.
14004 If SMALL is true, an unextended opcode was explicitly requested.
14005 If EXT is true, an extended opcode was explicitly requested. If
14006 WARN is true, warn if EXT does not match reality. */
14009 mips16_immed (char *file, unsigned int line, int type, offsetT val,
14010 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
14011 unsigned long *insn, bfd_boolean *use_extend,
14012 unsigned short *extend)
14014 const struct mips16_immed_operand *op;
14015 int mintiny, maxtiny;
14016 bfd_boolean needext;
14018 op = mips16_immed_operands;
14019 while (op->type != type)
14022 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14027 if (type == '<' || type == '>' || type == '[' || type == ']')
14030 maxtiny = 1 << op->nbits;
14035 maxtiny = (1 << op->nbits) - 1;
14040 mintiny = - (1 << (op->nbits - 1));
14041 maxtiny = (1 << (op->nbits - 1)) - 1;
14044 /* Branch offsets have an implicit 0 in the lowest bit. */
14045 if (type == 'p' || type == 'q')
14048 if ((val & ((1 << op->shift) - 1)) != 0
14049 || val < (mintiny << op->shift)
14050 || val > (maxtiny << op->shift))
14055 if (warn && ext && ! needext)
14056 as_warn_where (file, line,
14057 _("extended operand requested but not required"));
14058 if (small && needext)
14059 as_bad_where (file, line, _("invalid unextended operand value"));
14061 if (small || (! ext && ! needext))
14065 *use_extend = FALSE;
14066 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14067 insnval <<= op->op_shift;
14072 long minext, maxext;
14078 maxext = (1 << op->extbits) - 1;
14082 minext = - (1 << (op->extbits - 1));
14083 maxext = (1 << (op->extbits - 1)) - 1;
14085 if (val < minext || val > maxext)
14086 as_bad_where (file, line,
14087 _("operand value out of range for instruction"));
14089 *use_extend = TRUE;
14090 if (op->extbits == 16)
14092 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14095 else if (op->extbits == 15)
14097 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14102 extval = ((val & 0x1f) << 6) | (val & 0x20);
14106 *extend = (unsigned short) extval;
14111 struct percent_op_match
14114 bfd_reloc_code_real_type reloc;
14117 static const struct percent_op_match mips_percent_op[] =
14119 {"%lo", BFD_RELOC_LO16},
14121 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14122 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14123 {"%call16", BFD_RELOC_MIPS_CALL16},
14124 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14125 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14126 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14127 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14128 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14129 {"%got", BFD_RELOC_MIPS_GOT16},
14130 {"%gp_rel", BFD_RELOC_GPREL16},
14131 {"%half", BFD_RELOC_16},
14132 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14133 {"%higher", BFD_RELOC_MIPS_HIGHER},
14134 {"%neg", BFD_RELOC_MIPS_SUB},
14135 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14136 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14137 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14138 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14139 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14140 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14141 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14143 {"%hi", BFD_RELOC_HI16_S}
14146 static const struct percent_op_match mips16_percent_op[] =
14148 {"%lo", BFD_RELOC_MIPS16_LO16},
14149 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14150 {"%got", BFD_RELOC_MIPS16_GOT16},
14151 {"%call16", BFD_RELOC_MIPS16_CALL16},
14152 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14153 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14154 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14155 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14156 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14157 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14158 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14159 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14163 /* Return true if *STR points to a relocation operator. When returning true,
14164 move *STR over the operator and store its relocation code in *RELOC.
14165 Leave both *STR and *RELOC alone when returning false. */
14168 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14170 const struct percent_op_match *percent_op;
14173 if (mips_opts.mips16)
14175 percent_op = mips16_percent_op;
14176 limit = ARRAY_SIZE (mips16_percent_op);
14180 percent_op = mips_percent_op;
14181 limit = ARRAY_SIZE (mips_percent_op);
14184 for (i = 0; i < limit; i++)
14185 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14187 int len = strlen (percent_op[i].str);
14189 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14192 *str += strlen (percent_op[i].str);
14193 *reloc = percent_op[i].reloc;
14195 /* Check whether the output BFD supports this relocation.
14196 If not, issue an error and fall back on something safe. */
14197 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14199 as_bad (_("relocation %s isn't supported by the current ABI"),
14200 percent_op[i].str);
14201 *reloc = BFD_RELOC_UNUSED;
14209 /* Parse string STR as a 16-bit relocatable operand. Store the
14210 expression in *EP and the relocations in the array starting
14211 at RELOC. Return the number of relocation operators used.
14213 On exit, EXPR_END points to the first character after the expression. */
14216 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14219 bfd_reloc_code_real_type reversed_reloc[3];
14220 size_t reloc_index, i;
14221 int crux_depth, str_depth;
14224 /* Search for the start of the main expression, recoding relocations
14225 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14226 of the main expression and with CRUX_DEPTH containing the number
14227 of open brackets at that point. */
14234 crux_depth = str_depth;
14236 /* Skip over whitespace and brackets, keeping count of the number
14238 while (*str == ' ' || *str == '\t' || *str == '(')
14243 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14244 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14246 my_getExpression (ep, crux);
14249 /* Match every open bracket. */
14250 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14254 if (crux_depth > 0)
14255 as_bad (_("unclosed '('"));
14259 if (reloc_index != 0)
14261 prev_reloc_op_frag = frag_now;
14262 for (i = 0; i < reloc_index; i++)
14263 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14266 return reloc_index;
14270 my_getExpression (expressionS *ep, char *str)
14274 save_in = input_line_pointer;
14275 input_line_pointer = str;
14277 expr_end = input_line_pointer;
14278 input_line_pointer = save_in;
14282 md_atof (int type, char *litP, int *sizeP)
14284 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14288 md_number_to_chars (char *buf, valueT val, int n)
14290 if (target_big_endian)
14291 number_to_chars_bigendian (buf, val, n);
14293 number_to_chars_littleendian (buf, val, n);
14297 static int support_64bit_objects(void)
14299 const char **list, **l;
14302 list = bfd_target_list ();
14303 for (l = list; *l != NULL; l++)
14304 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14305 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14307 yes = (*l != NULL);
14311 #endif /* OBJ_ELF */
14313 const char *md_shortopts = "O::g::G:";
14317 OPTION_MARCH = OPTION_MD_BASE,
14339 OPTION_NO_SMARTMIPS,
14343 OPTION_NO_MICROMIPS,
14346 OPTION_COMPAT_ARCH_BASE,
14355 OPTION_M7000_HILO_FIX,
14356 OPTION_MNO_7000_HILO_FIX,
14359 OPTION_FIX_LOONGSON2F_JUMP,
14360 OPTION_NO_FIX_LOONGSON2F_JUMP,
14361 OPTION_FIX_LOONGSON2F_NOP,
14362 OPTION_NO_FIX_LOONGSON2F_NOP,
14364 OPTION_NO_FIX_VR4120,
14366 OPTION_NO_FIX_VR4130,
14367 OPTION_FIX_CN63XXP1,
14368 OPTION_NO_FIX_CN63XXP1,
14375 OPTION_CONSTRUCT_FLOATS,
14376 OPTION_NO_CONSTRUCT_FLOATS,
14379 OPTION_RELAX_BRANCH,
14380 OPTION_NO_RELAX_BRANCH,
14387 OPTION_SINGLE_FLOAT,
14388 OPTION_DOUBLE_FLOAT,
14391 OPTION_CALL_SHARED,
14392 OPTION_CALL_NONPIC,
14402 OPTION_MVXWORKS_PIC,
14403 #endif /* OBJ_ELF */
14407 struct option md_longopts[] =
14409 /* Options which specify architecture. */
14410 {"march", required_argument, NULL, OPTION_MARCH},
14411 {"mtune", required_argument, NULL, OPTION_MTUNE},
14412 {"mips0", no_argument, NULL, OPTION_MIPS1},
14413 {"mips1", no_argument, NULL, OPTION_MIPS1},
14414 {"mips2", no_argument, NULL, OPTION_MIPS2},
14415 {"mips3", no_argument, NULL, OPTION_MIPS3},
14416 {"mips4", no_argument, NULL, OPTION_MIPS4},
14417 {"mips5", no_argument, NULL, OPTION_MIPS5},
14418 {"mips32", no_argument, NULL, OPTION_MIPS32},
14419 {"mips64", no_argument, NULL, OPTION_MIPS64},
14420 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14421 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14423 /* Options which specify Application Specific Extensions (ASEs). */
14424 {"mips16", no_argument, NULL, OPTION_MIPS16},
14425 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14426 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14427 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14428 {"mdmx", no_argument, NULL, OPTION_MDMX},
14429 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14430 {"mdsp", no_argument, NULL, OPTION_DSP},
14431 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14432 {"mmt", no_argument, NULL, OPTION_MT},
14433 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14434 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14435 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14436 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14437 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14438 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14439 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14440 {"mmcu", no_argument, NULL, OPTION_MCU},
14441 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14443 /* Old-style architecture options. Don't add more of these. */
14444 {"m4650", no_argument, NULL, OPTION_M4650},
14445 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14446 {"m4010", no_argument, NULL, OPTION_M4010},
14447 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14448 {"m4100", no_argument, NULL, OPTION_M4100},
14449 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14450 {"m3900", no_argument, NULL, OPTION_M3900},
14451 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14453 /* Options which enable bug fixes. */
14454 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14455 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14456 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14457 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14458 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14459 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14460 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14461 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14462 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14463 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14464 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14465 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14466 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14467 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14468 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14470 /* Miscellaneous options. */
14471 {"trap", no_argument, NULL, OPTION_TRAP},
14472 {"no-break", no_argument, NULL, OPTION_TRAP},
14473 {"break", no_argument, NULL, OPTION_BREAK},
14474 {"no-trap", no_argument, NULL, OPTION_BREAK},
14475 {"EB", no_argument, NULL, OPTION_EB},
14476 {"EL", no_argument, NULL, OPTION_EL},
14477 {"mfp32", no_argument, NULL, OPTION_FP32},
14478 {"mgp32", no_argument, NULL, OPTION_GP32},
14479 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14480 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14481 {"mfp64", no_argument, NULL, OPTION_FP64},
14482 {"mgp64", no_argument, NULL, OPTION_GP64},
14483 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14484 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14485 {"mshared", no_argument, NULL, OPTION_MSHARED},
14486 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14487 {"msym32", no_argument, NULL, OPTION_MSYM32},
14488 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14489 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14490 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14491 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14492 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14494 /* Strictly speaking this next option is ELF specific,
14495 but we allow it for other ports as well in order to
14496 make testing easier. */
14497 {"32", no_argument, NULL, OPTION_32},
14499 /* ELF-specific options. */
14501 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14502 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14503 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14504 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14505 {"xgot", no_argument, NULL, OPTION_XGOT},
14506 {"mabi", required_argument, NULL, OPTION_MABI},
14507 {"n32", no_argument, NULL, OPTION_N32},
14508 {"64", no_argument, NULL, OPTION_64},
14509 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14510 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14511 {"mpdr", no_argument, NULL, OPTION_PDR},
14512 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14513 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14514 #endif /* OBJ_ELF */
14516 {NULL, no_argument, NULL, 0}
14518 size_t md_longopts_size = sizeof (md_longopts);
14520 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14521 NEW_VALUE. Warn if another value was already specified. Note:
14522 we have to defer parsing the -march and -mtune arguments in order
14523 to handle 'from-abi' correctly, since the ABI might be specified
14524 in a later argument. */
14527 mips_set_option_string (const char **string_ptr, const char *new_value)
14529 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14530 as_warn (_("A different %s was already specified, is now %s"),
14531 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14534 *string_ptr = new_value;
14538 md_parse_option (int c, char *arg)
14542 case OPTION_CONSTRUCT_FLOATS:
14543 mips_disable_float_construction = 0;
14546 case OPTION_NO_CONSTRUCT_FLOATS:
14547 mips_disable_float_construction = 1;
14559 target_big_endian = 1;
14563 target_big_endian = 0;
14569 else if (arg[0] == '0')
14571 else if (arg[0] == '1')
14581 mips_debug = atoi (arg);
14585 file_mips_isa = ISA_MIPS1;
14589 file_mips_isa = ISA_MIPS2;
14593 file_mips_isa = ISA_MIPS3;
14597 file_mips_isa = ISA_MIPS4;
14601 file_mips_isa = ISA_MIPS5;
14604 case OPTION_MIPS32:
14605 file_mips_isa = ISA_MIPS32;
14608 case OPTION_MIPS32R2:
14609 file_mips_isa = ISA_MIPS32R2;
14612 case OPTION_MIPS64R2:
14613 file_mips_isa = ISA_MIPS64R2;
14616 case OPTION_MIPS64:
14617 file_mips_isa = ISA_MIPS64;
14621 mips_set_option_string (&mips_tune_string, arg);
14625 mips_set_option_string (&mips_arch_string, arg);
14629 mips_set_option_string (&mips_arch_string, "4650");
14630 mips_set_option_string (&mips_tune_string, "4650");
14633 case OPTION_NO_M4650:
14637 mips_set_option_string (&mips_arch_string, "4010");
14638 mips_set_option_string (&mips_tune_string, "4010");
14641 case OPTION_NO_M4010:
14645 mips_set_option_string (&mips_arch_string, "4100");
14646 mips_set_option_string (&mips_tune_string, "4100");
14649 case OPTION_NO_M4100:
14653 mips_set_option_string (&mips_arch_string, "3900");
14654 mips_set_option_string (&mips_tune_string, "3900");
14657 case OPTION_NO_M3900:
14661 mips_opts.ase_mdmx = 1;
14664 case OPTION_NO_MDMX:
14665 mips_opts.ase_mdmx = 0;
14669 mips_opts.ase_dsp = 1;
14670 mips_opts.ase_dspr2 = 0;
14673 case OPTION_NO_DSP:
14674 mips_opts.ase_dsp = 0;
14675 mips_opts.ase_dspr2 = 0;
14679 mips_opts.ase_dspr2 = 1;
14680 mips_opts.ase_dsp = 1;
14683 case OPTION_NO_DSPR2:
14684 mips_opts.ase_dspr2 = 0;
14685 mips_opts.ase_dsp = 0;
14689 mips_opts.ase_mt = 1;
14693 mips_opts.ase_mt = 0;
14697 mips_opts.ase_mcu = 1;
14700 case OPTION_NO_MCU:
14701 mips_opts.ase_mcu = 0;
14704 case OPTION_MICROMIPS:
14705 if (mips_opts.mips16 == 1)
14707 as_bad (_("-mmicromips cannot be used with -mips16"));
14710 mips_opts.micromips = 1;
14711 mips_no_prev_insn ();
14714 case OPTION_NO_MICROMIPS:
14715 mips_opts.micromips = 0;
14716 mips_no_prev_insn ();
14719 case OPTION_MIPS16:
14720 if (mips_opts.micromips == 1)
14722 as_bad (_("-mips16 cannot be used with -micromips"));
14725 mips_opts.mips16 = 1;
14726 mips_no_prev_insn ();
14729 case OPTION_NO_MIPS16:
14730 mips_opts.mips16 = 0;
14731 mips_no_prev_insn ();
14734 case OPTION_MIPS3D:
14735 mips_opts.ase_mips3d = 1;
14738 case OPTION_NO_MIPS3D:
14739 mips_opts.ase_mips3d = 0;
14742 case OPTION_SMARTMIPS:
14743 mips_opts.ase_smartmips = 1;
14746 case OPTION_NO_SMARTMIPS:
14747 mips_opts.ase_smartmips = 0;
14750 case OPTION_FIX_24K:
14754 case OPTION_NO_FIX_24K:
14758 case OPTION_FIX_LOONGSON2F_JUMP:
14759 mips_fix_loongson2f_jump = TRUE;
14762 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14763 mips_fix_loongson2f_jump = FALSE;
14766 case OPTION_FIX_LOONGSON2F_NOP:
14767 mips_fix_loongson2f_nop = TRUE;
14770 case OPTION_NO_FIX_LOONGSON2F_NOP:
14771 mips_fix_loongson2f_nop = FALSE;
14774 case OPTION_FIX_VR4120:
14775 mips_fix_vr4120 = 1;
14778 case OPTION_NO_FIX_VR4120:
14779 mips_fix_vr4120 = 0;
14782 case OPTION_FIX_VR4130:
14783 mips_fix_vr4130 = 1;
14786 case OPTION_NO_FIX_VR4130:
14787 mips_fix_vr4130 = 0;
14790 case OPTION_FIX_CN63XXP1:
14791 mips_fix_cn63xxp1 = TRUE;
14794 case OPTION_NO_FIX_CN63XXP1:
14795 mips_fix_cn63xxp1 = FALSE;
14798 case OPTION_RELAX_BRANCH:
14799 mips_relax_branch = 1;
14802 case OPTION_NO_RELAX_BRANCH:
14803 mips_relax_branch = 0;
14806 case OPTION_MSHARED:
14807 mips_in_shared = TRUE;
14810 case OPTION_MNO_SHARED:
14811 mips_in_shared = FALSE;
14814 case OPTION_MSYM32:
14815 mips_opts.sym32 = TRUE;
14818 case OPTION_MNO_SYM32:
14819 mips_opts.sym32 = FALSE;
14823 /* When generating ELF code, we permit -KPIC and -call_shared to
14824 select SVR4_PIC, and -non_shared to select no PIC. This is
14825 intended to be compatible with Irix 5. */
14826 case OPTION_CALL_SHARED:
14829 as_bad (_("-call_shared is supported only for ELF format"));
14832 mips_pic = SVR4_PIC;
14833 mips_abicalls = TRUE;
14836 case OPTION_CALL_NONPIC:
14839 as_bad (_("-call_nonpic is supported only for ELF format"));
14843 mips_abicalls = TRUE;
14846 case OPTION_NON_SHARED:
14849 as_bad (_("-non_shared is supported only for ELF format"));
14853 mips_abicalls = FALSE;
14856 /* The -xgot option tells the assembler to use 32 bit offsets
14857 when accessing the got in SVR4_PIC mode. It is for Irix
14862 #endif /* OBJ_ELF */
14865 g_switch_value = atoi (arg);
14869 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14873 mips_abi = O32_ABI;
14874 /* We silently ignore -32 for non-ELF targets. This greatly
14875 simplifies the construction of the MIPS GAS test cases. */
14882 as_bad (_("-n32 is supported for ELF format only"));
14885 mips_abi = N32_ABI;
14891 as_bad (_("-64 is supported for ELF format only"));
14894 mips_abi = N64_ABI;
14895 if (!support_64bit_objects())
14896 as_fatal (_("No compiled in support for 64 bit object file format"));
14898 #endif /* OBJ_ELF */
14901 file_mips_gp32 = 1;
14905 file_mips_gp32 = 0;
14909 file_mips_fp32 = 1;
14913 file_mips_fp32 = 0;
14916 case OPTION_SINGLE_FLOAT:
14917 file_mips_single_float = 1;
14920 case OPTION_DOUBLE_FLOAT:
14921 file_mips_single_float = 0;
14924 case OPTION_SOFT_FLOAT:
14925 file_mips_soft_float = 1;
14928 case OPTION_HARD_FLOAT:
14929 file_mips_soft_float = 0;
14936 as_bad (_("-mabi is supported for ELF format only"));
14939 if (strcmp (arg, "32") == 0)
14940 mips_abi = O32_ABI;
14941 else if (strcmp (arg, "o64") == 0)
14942 mips_abi = O64_ABI;
14943 else if (strcmp (arg, "n32") == 0)
14944 mips_abi = N32_ABI;
14945 else if (strcmp (arg, "64") == 0)
14947 mips_abi = N64_ABI;
14948 if (! support_64bit_objects())
14949 as_fatal (_("No compiled in support for 64 bit object file "
14952 else if (strcmp (arg, "eabi") == 0)
14953 mips_abi = EABI_ABI;
14956 as_fatal (_("invalid abi -mabi=%s"), arg);
14960 #endif /* OBJ_ELF */
14962 case OPTION_M7000_HILO_FIX:
14963 mips_7000_hilo_fix = TRUE;
14966 case OPTION_MNO_7000_HILO_FIX:
14967 mips_7000_hilo_fix = FALSE;
14971 case OPTION_MDEBUG:
14972 mips_flag_mdebug = TRUE;
14975 case OPTION_NO_MDEBUG:
14976 mips_flag_mdebug = FALSE;
14980 mips_flag_pdr = TRUE;
14983 case OPTION_NO_PDR:
14984 mips_flag_pdr = FALSE;
14987 case OPTION_MVXWORKS_PIC:
14988 mips_pic = VXWORKS_PIC;
14990 #endif /* OBJ_ELF */
14996 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15001 /* Set up globals to generate code for the ISA or processor
15002 described by INFO. */
15005 mips_set_architecture (const struct mips_cpu_info *info)
15009 file_mips_arch = info->cpu;
15010 mips_opts.arch = info->cpu;
15011 mips_opts.isa = info->isa;
15016 /* Likewise for tuning. */
15019 mips_set_tune (const struct mips_cpu_info *info)
15022 mips_tune = info->cpu;
15027 mips_after_parse_args (void)
15029 const struct mips_cpu_info *arch_info = 0;
15030 const struct mips_cpu_info *tune_info = 0;
15032 /* GP relative stuff not working for PE */
15033 if (strncmp (TARGET_OS, "pe", 2) == 0)
15035 if (g_switch_seen && g_switch_value != 0)
15036 as_bad (_("-G not supported in this configuration."));
15037 g_switch_value = 0;
15040 if (mips_abi == NO_ABI)
15041 mips_abi = MIPS_DEFAULT_ABI;
15043 /* The following code determines the architecture and register size.
15044 Similar code was added to GCC 3.3 (see override_options() in
15045 config/mips/mips.c). The GAS and GCC code should be kept in sync
15046 as much as possible. */
15048 if (mips_arch_string != 0)
15049 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15051 if (file_mips_isa != ISA_UNKNOWN)
15053 /* Handle -mipsN. At this point, file_mips_isa contains the
15054 ISA level specified by -mipsN, while arch_info->isa contains
15055 the -march selection (if any). */
15056 if (arch_info != 0)
15058 /* -march takes precedence over -mipsN, since it is more descriptive.
15059 There's no harm in specifying both as long as the ISA levels
15061 if (file_mips_isa != arch_info->isa)
15062 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15063 mips_cpu_info_from_isa (file_mips_isa)->name,
15064 mips_cpu_info_from_isa (arch_info->isa)->name);
15067 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15070 if (arch_info == 0)
15072 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15073 gas_assert (arch_info);
15076 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15077 as_bad (_("-march=%s is not compatible with the selected ABI"),
15080 mips_set_architecture (arch_info);
15082 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15083 if (mips_tune_string != 0)
15084 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15086 if (tune_info == 0)
15087 mips_set_tune (arch_info);
15089 mips_set_tune (tune_info);
15091 if (file_mips_gp32 >= 0)
15093 /* The user specified the size of the integer registers. Make sure
15094 it agrees with the ABI and ISA. */
15095 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15096 as_bad (_("-mgp64 used with a 32-bit processor"));
15097 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15098 as_bad (_("-mgp32 used with a 64-bit ABI"));
15099 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15100 as_bad (_("-mgp64 used with a 32-bit ABI"));
15104 /* Infer the integer register size from the ABI and processor.
15105 Restrict ourselves to 32-bit registers if that's all the
15106 processor has, or if the ABI cannot handle 64-bit registers. */
15107 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15108 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15111 switch (file_mips_fp32)
15115 /* No user specified float register size.
15116 ??? GAS treats single-float processors as though they had 64-bit
15117 float registers (although it complains when double-precision
15118 instructions are used). As things stand, saying they have 32-bit
15119 registers would lead to spurious "register must be even" messages.
15120 So here we assume float registers are never smaller than the
15122 if (file_mips_gp32 == 0)
15123 /* 64-bit integer registers implies 64-bit float registers. */
15124 file_mips_fp32 = 0;
15125 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15126 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15127 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15128 file_mips_fp32 = 0;
15130 /* 32-bit float registers. */
15131 file_mips_fp32 = 1;
15134 /* The user specified the size of the float registers. Check if it
15135 agrees with the ABI and ISA. */
15137 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15138 as_bad (_("-mfp64 used with a 32-bit fpu"));
15139 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15140 && !ISA_HAS_MXHC1 (mips_opts.isa))
15141 as_warn (_("-mfp64 used with a 32-bit ABI"));
15144 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15145 as_warn (_("-mfp32 used with a 64-bit ABI"));
15149 /* End of GCC-shared inference code. */
15151 /* This flag is set when we have a 64-bit capable CPU but use only
15152 32-bit wide registers. Note that EABI does not use it. */
15153 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15154 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15155 || mips_abi == O32_ABI))
15156 mips_32bitmode = 1;
15158 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15159 as_bad (_("trap exception not supported at ISA 1"));
15161 /* If the selected architecture includes support for ASEs, enable
15162 generation of code for them. */
15163 if (mips_opts.mips16 == -1)
15164 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15165 if (mips_opts.micromips == -1)
15166 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15167 if (mips_opts.ase_mips3d == -1)
15168 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15169 && file_mips_fp32 == 0) ? 1 : 0;
15170 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15171 as_bad (_("-mfp32 used with -mips3d"));
15173 if (mips_opts.ase_mdmx == -1)
15174 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15175 && file_mips_fp32 == 0) ? 1 : 0;
15176 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15177 as_bad (_("-mfp32 used with -mdmx"));
15179 if (mips_opts.ase_smartmips == -1)
15180 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15181 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15182 as_warn (_("%s ISA does not support SmartMIPS"),
15183 mips_cpu_info_from_isa (mips_opts.isa)->name);
15185 if (mips_opts.ase_dsp == -1)
15186 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15187 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15188 as_warn (_("%s ISA does not support DSP ASE"),
15189 mips_cpu_info_from_isa (mips_opts.isa)->name);
15191 if (mips_opts.ase_dspr2 == -1)
15193 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15194 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15196 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15197 as_warn (_("%s ISA does not support DSP R2 ASE"),
15198 mips_cpu_info_from_isa (mips_opts.isa)->name);
15200 if (mips_opts.ase_mt == -1)
15201 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15202 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15203 as_warn (_("%s ISA does not support MT ASE"),
15204 mips_cpu_info_from_isa (mips_opts.isa)->name);
15206 if (mips_opts.ase_mcu == -1)
15207 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15208 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15209 as_warn (_("%s ISA does not support MCU ASE"),
15210 mips_cpu_info_from_isa (mips_opts.isa)->name);
15212 file_mips_isa = mips_opts.isa;
15213 file_ase_mips3d = mips_opts.ase_mips3d;
15214 file_ase_mdmx = mips_opts.ase_mdmx;
15215 file_ase_smartmips = mips_opts.ase_smartmips;
15216 file_ase_dsp = mips_opts.ase_dsp;
15217 file_ase_dspr2 = mips_opts.ase_dspr2;
15218 file_ase_mt = mips_opts.ase_mt;
15219 mips_opts.gp32 = file_mips_gp32;
15220 mips_opts.fp32 = file_mips_fp32;
15221 mips_opts.soft_float = file_mips_soft_float;
15222 mips_opts.single_float = file_mips_single_float;
15224 if (mips_flag_mdebug < 0)
15226 #ifdef OBJ_MAYBE_ECOFF
15227 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15228 mips_flag_mdebug = 1;
15230 #endif /* OBJ_MAYBE_ECOFF */
15231 mips_flag_mdebug = 0;
15236 mips_init_after_args (void)
15238 /* initialize opcodes */
15239 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15240 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15244 md_pcrel_from (fixS *fixP)
15246 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15247 switch (fixP->fx_r_type)
15249 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15250 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15251 /* Return the address of the delay slot. */
15254 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15255 case BFD_RELOC_MICROMIPS_JMP:
15256 case BFD_RELOC_16_PCREL_S2:
15257 case BFD_RELOC_MIPS_JMP:
15258 /* Return the address of the delay slot. */
15262 /* We have no relocation type for PC relative MIPS16 instructions. */
15263 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15264 as_bad_where (fixP->fx_file, fixP->fx_line,
15265 _("PC relative MIPS16 instruction references a different section"));
15270 /* This is called before the symbol table is processed. In order to
15271 work with gcc when using mips-tfile, we must keep all local labels.
15272 However, in other cases, we want to discard them. If we were
15273 called with -g, but we didn't see any debugging information, it may
15274 mean that gcc is smuggling debugging information through to
15275 mips-tfile, in which case we must generate all local labels. */
15278 mips_frob_file_before_adjust (void)
15280 #ifndef NO_ECOFF_DEBUGGING
15281 if (ECOFF_DEBUGGING
15283 && ! ecoff_debugging_seen)
15284 flag_keep_locals = 1;
15288 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15289 the corresponding LO16 reloc. This is called before md_apply_fix and
15290 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15291 relocation operators.
15293 For our purposes, a %lo() expression matches a %got() or %hi()
15296 (a) it refers to the same symbol; and
15297 (b) the offset applied in the %lo() expression is no lower than
15298 the offset applied in the %got() or %hi().
15300 (b) allows us to cope with code like:
15303 lh $4,%lo(foo+2)($4)
15305 ...which is legal on RELA targets, and has a well-defined behaviour
15306 if the user knows that adding 2 to "foo" will not induce a carry to
15309 When several %lo()s match a particular %got() or %hi(), we use the
15310 following rules to distinguish them:
15312 (1) %lo()s with smaller offsets are a better match than %lo()s with
15315 (2) %lo()s with no matching %got() or %hi() are better than those
15316 that already have a matching %got() or %hi().
15318 (3) later %lo()s are better than earlier %lo()s.
15320 These rules are applied in order.
15322 (1) means, among other things, that %lo()s with identical offsets are
15323 chosen if they exist.
15325 (2) means that we won't associate several high-part relocations with
15326 the same low-part relocation unless there's no alternative. Having
15327 several high parts for the same low part is a GNU extension; this rule
15328 allows careful users to avoid it.
15330 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15331 with the last high-part relocation being at the front of the list.
15332 It therefore makes sense to choose the last matching low-part
15333 relocation, all other things being equal. It's also easier
15334 to code that way. */
15337 mips_frob_file (void)
15339 struct mips_hi_fixup *l;
15340 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15342 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15344 segment_info_type *seginfo;
15345 bfd_boolean matched_lo_p;
15346 fixS **hi_pos, **lo_pos, **pos;
15348 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15350 /* If a GOT16 relocation turns out to be against a global symbol,
15351 there isn't supposed to be a matching LO. */
15352 if (got16_reloc_p (l->fixp->fx_r_type)
15353 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15356 /* Check quickly whether the next fixup happens to be a matching %lo. */
15357 if (fixup_has_matching_lo_p (l->fixp))
15360 seginfo = seg_info (l->seg);
15362 /* Set HI_POS to the position of this relocation in the chain.
15363 Set LO_POS to the position of the chosen low-part relocation.
15364 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15365 relocation that matches an immediately-preceding high-part
15369 matched_lo_p = FALSE;
15370 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15372 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15374 if (*pos == l->fixp)
15377 if ((*pos)->fx_r_type == looking_for_rtype
15378 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15379 && (*pos)->fx_offset >= l->fixp->fx_offset
15381 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15383 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15386 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15387 && fixup_has_matching_lo_p (*pos));
15390 /* If we found a match, remove the high-part relocation from its
15391 current position and insert it before the low-part relocation.
15392 Make the offsets match so that fixup_has_matching_lo_p()
15395 We don't warn about unmatched high-part relocations since some
15396 versions of gcc have been known to emit dead "lui ...%hi(...)"
15398 if (lo_pos != NULL)
15400 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15401 if (l->fixp->fx_next != *lo_pos)
15403 *hi_pos = l->fixp->fx_next;
15404 l->fixp->fx_next = *lo_pos;
15411 /* We may have combined relocations without symbols in the N32/N64 ABI.
15412 We have to prevent gas from dropping them. */
15415 mips_force_relocation (fixS *fixp)
15417 if (generic_force_reloc (fixp))
15420 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15421 so that the linker relaxation can update targets. */
15422 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15423 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15424 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15428 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15429 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
15430 || hi16_reloc_p (fixp->fx_r_type)
15431 || lo16_reloc_p (fixp->fx_r_type)))
15437 /* Apply a fixup to the object file. */
15440 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15444 reloc_howto_type *howto;
15446 /* We ignore generic BFD relocations we don't know about. */
15447 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15451 gas_assert (fixP->fx_size == 2
15452 || fixP->fx_size == 4
15453 || fixP->fx_r_type == BFD_RELOC_16
15454 || fixP->fx_r_type == BFD_RELOC_64
15455 || fixP->fx_r_type == BFD_RELOC_CTOR
15456 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15457 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15458 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15459 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15460 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15462 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
15464 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15465 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15466 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15467 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15469 /* Don't treat parts of a composite relocation as done. There are two
15472 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15473 should nevertheless be emitted if the first part is.
15475 (2) In normal usage, composite relocations are never assembly-time
15476 constants. The easiest way of dealing with the pathological
15477 exceptions is to generate a relocation against STN_UNDEF and
15478 leave everything up to the linker. */
15479 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15482 switch (fixP->fx_r_type)
15484 case BFD_RELOC_MIPS_TLS_GD:
15485 case BFD_RELOC_MIPS_TLS_LDM:
15486 case BFD_RELOC_MIPS_TLS_DTPREL32:
15487 case BFD_RELOC_MIPS_TLS_DTPREL64:
15488 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15489 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15490 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15491 case BFD_RELOC_MIPS_TLS_TPREL32:
15492 case BFD_RELOC_MIPS_TLS_TPREL64:
15493 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15494 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15495 case BFD_RELOC_MICROMIPS_TLS_GD:
15496 case BFD_RELOC_MICROMIPS_TLS_LDM:
15497 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15498 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15499 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15500 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15501 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15502 case BFD_RELOC_MIPS16_TLS_GD:
15503 case BFD_RELOC_MIPS16_TLS_LDM:
15504 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15505 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15506 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15507 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15508 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15509 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15512 case BFD_RELOC_MIPS_JMP:
15513 case BFD_RELOC_MIPS_SHIFT5:
15514 case BFD_RELOC_MIPS_SHIFT6:
15515 case BFD_RELOC_MIPS_GOT_DISP:
15516 case BFD_RELOC_MIPS_GOT_PAGE:
15517 case BFD_RELOC_MIPS_GOT_OFST:
15518 case BFD_RELOC_MIPS_SUB:
15519 case BFD_RELOC_MIPS_INSERT_A:
15520 case BFD_RELOC_MIPS_INSERT_B:
15521 case BFD_RELOC_MIPS_DELETE:
15522 case BFD_RELOC_MIPS_HIGHEST:
15523 case BFD_RELOC_MIPS_HIGHER:
15524 case BFD_RELOC_MIPS_SCN_DISP:
15525 case BFD_RELOC_MIPS_REL16:
15526 case BFD_RELOC_MIPS_RELGOT:
15527 case BFD_RELOC_MIPS_JALR:
15528 case BFD_RELOC_HI16:
15529 case BFD_RELOC_HI16_S:
15530 case BFD_RELOC_GPREL16:
15531 case BFD_RELOC_MIPS_LITERAL:
15532 case BFD_RELOC_MIPS_CALL16:
15533 case BFD_RELOC_MIPS_GOT16:
15534 case BFD_RELOC_GPREL32:
15535 case BFD_RELOC_MIPS_GOT_HI16:
15536 case BFD_RELOC_MIPS_GOT_LO16:
15537 case BFD_RELOC_MIPS_CALL_HI16:
15538 case BFD_RELOC_MIPS_CALL_LO16:
15539 case BFD_RELOC_MIPS16_GPREL:
15540 case BFD_RELOC_MIPS16_GOT16:
15541 case BFD_RELOC_MIPS16_CALL16:
15542 case BFD_RELOC_MIPS16_HI16:
15543 case BFD_RELOC_MIPS16_HI16_S:
15544 case BFD_RELOC_MIPS16_JMP:
15545 case BFD_RELOC_MICROMIPS_JMP:
15546 case BFD_RELOC_MICROMIPS_GOT_DISP:
15547 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15548 case BFD_RELOC_MICROMIPS_GOT_OFST:
15549 case BFD_RELOC_MICROMIPS_SUB:
15550 case BFD_RELOC_MICROMIPS_HIGHEST:
15551 case BFD_RELOC_MICROMIPS_HIGHER:
15552 case BFD_RELOC_MICROMIPS_SCN_DISP:
15553 case BFD_RELOC_MICROMIPS_JALR:
15554 case BFD_RELOC_MICROMIPS_HI16:
15555 case BFD_RELOC_MICROMIPS_HI16_S:
15556 case BFD_RELOC_MICROMIPS_GPREL16:
15557 case BFD_RELOC_MICROMIPS_LITERAL:
15558 case BFD_RELOC_MICROMIPS_CALL16:
15559 case BFD_RELOC_MICROMIPS_GOT16:
15560 case BFD_RELOC_MICROMIPS_GOT_HI16:
15561 case BFD_RELOC_MICROMIPS_GOT_LO16:
15562 case BFD_RELOC_MICROMIPS_CALL_HI16:
15563 case BFD_RELOC_MICROMIPS_CALL_LO16:
15564 /* Nothing needed to do. The value comes from the reloc entry. */
15568 /* This is handled like BFD_RELOC_32, but we output a sign
15569 extended value if we are only 32 bits. */
15572 if (8 <= sizeof (valueT))
15573 md_number_to_chars ((char *) buf, *valP, 8);
15578 if ((*valP & 0x80000000) != 0)
15582 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
15584 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
15590 case BFD_RELOC_RVA:
15593 /* If we are deleting this reloc entry, we must fill in the
15594 value now. This can happen if we have a .word which is not
15595 resolved when it appears but is later defined. */
15597 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
15600 case BFD_RELOC_LO16:
15601 case BFD_RELOC_MIPS16_LO16:
15602 case BFD_RELOC_MICROMIPS_LO16:
15603 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15604 may be safe to remove, but if so it's not obvious. */
15605 /* When handling an embedded PIC switch statement, we can wind
15606 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15609 if (*valP + 0x8000 > 0xffff)
15610 as_bad_where (fixP->fx_file, fixP->fx_line,
15611 _("relocation overflow"));
15612 /* 32-bit microMIPS instructions are divided into two halfwords.
15613 Relocations always refer to the second halfword, regardless
15615 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
15617 md_number_to_chars ((char *) buf, *valP, 2);
15621 case BFD_RELOC_16_PCREL_S2:
15622 if ((*valP & 0x3) != 0)
15623 as_bad_where (fixP->fx_file, fixP->fx_line,
15624 _("Branch to misaligned address (%lx)"), (long) *valP);
15626 /* We need to save the bits in the instruction since fixup_segment()
15627 might be deleting the relocation entry (i.e., a branch within
15628 the current segment). */
15629 if (! fixP->fx_done)
15632 /* Update old instruction data. */
15633 if (target_big_endian)
15634 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
15636 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
15638 if (*valP + 0x20000 <= 0x3ffff)
15640 insn |= (*valP >> 2) & 0xffff;
15641 md_number_to_chars ((char *) buf, insn, 4);
15643 else if (mips_pic == NO_PIC
15645 && fixP->fx_frag->fr_address >= text_section->vma
15646 && (fixP->fx_frag->fr_address
15647 < text_section->vma + bfd_get_section_size (text_section))
15648 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15649 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15650 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15652 /* The branch offset is too large. If this is an
15653 unconditional branch, and we are not generating PIC code,
15654 we can convert it to an absolute jump instruction. */
15655 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15656 insn = 0x0c000000; /* jal */
15658 insn = 0x08000000; /* j */
15659 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15661 fixP->fx_addsy = section_symbol (text_section);
15662 *valP += md_pcrel_from (fixP);
15663 md_number_to_chars ((char *) buf, insn, 4);
15667 /* If we got here, we have branch-relaxation disabled,
15668 and there's nothing we can do to fix this instruction
15669 without turning it into a longer sequence. */
15670 as_bad_where (fixP->fx_file, fixP->fx_line,
15671 _("Branch out of range"));
15675 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15676 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15677 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15678 /* We adjust the offset back to even. */
15679 if ((*valP & 0x1) != 0)
15682 if (! fixP->fx_done)
15685 /* Should never visit here, because we keep the relocation. */
15689 case BFD_RELOC_VTABLE_INHERIT:
15692 && !S_IS_DEFINED (fixP->fx_addsy)
15693 && !S_IS_WEAK (fixP->fx_addsy))
15694 S_SET_WEAK (fixP->fx_addsy);
15697 case BFD_RELOC_VTABLE_ENTRY:
15705 /* Remember value for tc_gen_reloc. */
15706 fixP->fx_addnumber = *valP;
15716 name = input_line_pointer;
15717 c = get_symbol_end ();
15718 p = (symbolS *) symbol_find_or_make (name);
15719 *input_line_pointer = c;
15723 /* Align the current frag to a given power of two. If a particular
15724 fill byte should be used, FILL points to an integer that contains
15725 that byte, otherwise FILL is null.
15727 This function used to have the comment:
15729 The MIPS assembler also automatically adjusts any preceding label.
15731 The implementation therefore applied the adjustment to a maximum of
15732 one label. However, other label adjustments are applied to batches
15733 of labels, and adjusting just one caused problems when new labels
15734 were added for the sake of debugging or unwind information.
15735 We therefore adjust all preceding labels (given as LABELS) instead. */
15738 mips_align (int to, int *fill, struct insn_label_list *labels)
15740 mips_emit_delays ();
15741 mips_record_compressed_mode ();
15742 if (fill == NULL && subseg_text_p (now_seg))
15743 frag_align_code (to, 0);
15745 frag_align (to, fill ? *fill : 0, 0);
15746 record_alignment (now_seg, to);
15747 mips_move_labels (labels, FALSE);
15750 /* Align to a given power of two. .align 0 turns off the automatic
15751 alignment used by the data creating pseudo-ops. */
15754 s_align (int x ATTRIBUTE_UNUSED)
15756 int temp, fill_value, *fill_ptr;
15757 long max_alignment = 28;
15759 /* o Note that the assembler pulls down any immediately preceding label
15760 to the aligned address.
15761 o It's not documented but auto alignment is reinstated by
15762 a .align pseudo instruction.
15763 o Note also that after auto alignment is turned off the mips assembler
15764 issues an error on attempt to assemble an improperly aligned data item.
15767 temp = get_absolute_expression ();
15768 if (temp > max_alignment)
15769 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15772 as_warn (_("Alignment negative: 0 assumed."));
15775 if (*input_line_pointer == ',')
15777 ++input_line_pointer;
15778 fill_value = get_absolute_expression ();
15779 fill_ptr = &fill_value;
15785 segment_info_type *si = seg_info (now_seg);
15786 struct insn_label_list *l = si->label_list;
15787 /* Auto alignment should be switched on by next section change. */
15789 mips_align (temp, fill_ptr, l);
15796 demand_empty_rest_of_line ();
15800 s_change_sec (int sec)
15805 /* The ELF backend needs to know that we are changing sections, so
15806 that .previous works correctly. We could do something like check
15807 for an obj_section_change_hook macro, but that might be confusing
15808 as it would not be appropriate to use it in the section changing
15809 functions in read.c, since obj-elf.c intercepts those. FIXME:
15810 This should be cleaner, somehow. */
15812 obj_elf_section_change_hook ();
15815 mips_emit_delays ();
15826 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15827 demand_empty_rest_of_line ();
15831 seg = subseg_new (RDATA_SECTION_NAME,
15832 (subsegT) get_absolute_expression ());
15835 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15836 | SEC_READONLY | SEC_RELOC
15838 if (strncmp (TARGET_OS, "elf", 3) != 0)
15839 record_alignment (seg, 4);
15841 demand_empty_rest_of_line ();
15845 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15848 bfd_set_section_flags (stdoutput, seg,
15849 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15850 if (strncmp (TARGET_OS, "elf", 3) != 0)
15851 record_alignment (seg, 4);
15853 demand_empty_rest_of_line ();
15857 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15860 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15861 if (strncmp (TARGET_OS, "elf", 3) != 0)
15862 record_alignment (seg, 4);
15864 demand_empty_rest_of_line ();
15872 s_change_section (int ignore ATTRIBUTE_UNUSED)
15875 char *section_name;
15880 int section_entry_size;
15881 int section_alignment;
15886 section_name = input_line_pointer;
15887 c = get_symbol_end ();
15889 next_c = *(input_line_pointer + 1);
15891 /* Do we have .section Name<,"flags">? */
15892 if (c != ',' || (c == ',' && next_c == '"'))
15894 /* just after name is now '\0'. */
15895 *input_line_pointer = c;
15896 input_line_pointer = section_name;
15897 obj_elf_section (ignore);
15900 input_line_pointer++;
15902 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15904 section_type = get_absolute_expression ();
15907 if (*input_line_pointer++ == ',')
15908 section_flag = get_absolute_expression ();
15911 if (*input_line_pointer++ == ',')
15912 section_entry_size = get_absolute_expression ();
15914 section_entry_size = 0;
15915 if (*input_line_pointer++ == ',')
15916 section_alignment = get_absolute_expression ();
15918 section_alignment = 0;
15919 /* FIXME: really ignore? */
15920 (void) section_alignment;
15922 section_name = xstrdup (section_name);
15924 /* When using the generic form of .section (as implemented by obj-elf.c),
15925 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15926 traditionally had to fall back on the more common @progbits instead.
15928 There's nothing really harmful in this, since bfd will correct
15929 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15930 means that, for backwards compatibility, the special_section entries
15931 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15933 Even so, we shouldn't force users of the MIPS .section syntax to
15934 incorrectly label the sections as SHT_PROGBITS. The best compromise
15935 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15936 generic type-checking code. */
15937 if (section_type == SHT_MIPS_DWARF)
15938 section_type = SHT_PROGBITS;
15940 obj_elf_change_section (section_name, section_type, section_flag,
15941 section_entry_size, 0, 0, 0);
15943 if (now_seg->name != section_name)
15944 free (section_name);
15945 #endif /* OBJ_ELF */
15949 mips_enable_auto_align (void)
15955 s_cons (int log_size)
15957 segment_info_type *si = seg_info (now_seg);
15958 struct insn_label_list *l = si->label_list;
15960 mips_emit_delays ();
15961 if (log_size > 0 && auto_align)
15962 mips_align (log_size, 0, l);
15963 cons (1 << log_size);
15964 mips_clear_insn_labels ();
15968 s_float_cons (int type)
15970 segment_info_type *si = seg_info (now_seg);
15971 struct insn_label_list *l = si->label_list;
15973 mips_emit_delays ();
15978 mips_align (3, 0, l);
15980 mips_align (2, 0, l);
15984 mips_clear_insn_labels ();
15987 /* Handle .globl. We need to override it because on Irix 5 you are
15990 where foo is an undefined symbol, to mean that foo should be
15991 considered to be the address of a function. */
15994 s_mips_globl (int x ATTRIBUTE_UNUSED)
16003 name = input_line_pointer;
16004 c = get_symbol_end ();
16005 symbolP = symbol_find_or_make (name);
16006 S_SET_EXTERNAL (symbolP);
16008 *input_line_pointer = c;
16009 SKIP_WHITESPACE ();
16011 /* On Irix 5, every global symbol that is not explicitly labelled as
16012 being a function is apparently labelled as being an object. */
16015 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16016 && (*input_line_pointer != ','))
16021 secname = input_line_pointer;
16022 c = get_symbol_end ();
16023 sec = bfd_get_section_by_name (stdoutput, secname);
16025 as_bad (_("%s: no such section"), secname);
16026 *input_line_pointer = c;
16028 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16029 flag = BSF_FUNCTION;
16032 symbol_get_bfdsym (symbolP)->flags |= flag;
16034 c = *input_line_pointer;
16037 input_line_pointer++;
16038 SKIP_WHITESPACE ();
16039 if (is_end_of_line[(unsigned char) *input_line_pointer])
16045 demand_empty_rest_of_line ();
16049 s_option (int x ATTRIBUTE_UNUSED)
16054 opt = input_line_pointer;
16055 c = get_symbol_end ();
16059 /* FIXME: What does this mean? */
16061 else if (strncmp (opt, "pic", 3) == 0)
16065 i = atoi (opt + 3);
16070 mips_pic = SVR4_PIC;
16071 mips_abicalls = TRUE;
16074 as_bad (_(".option pic%d not supported"), i);
16076 if (mips_pic == SVR4_PIC)
16078 if (g_switch_seen && g_switch_value != 0)
16079 as_warn (_("-G may not be used with SVR4 PIC code"));
16080 g_switch_value = 0;
16081 bfd_set_gp_size (stdoutput, 0);
16085 as_warn (_("Unrecognized option \"%s\""), opt);
16087 *input_line_pointer = c;
16088 demand_empty_rest_of_line ();
16091 /* This structure is used to hold a stack of .set values. */
16093 struct mips_option_stack
16095 struct mips_option_stack *next;
16096 struct mips_set_options options;
16099 static struct mips_option_stack *mips_opts_stack;
16101 /* Handle the .set pseudo-op. */
16104 s_mipsset (int x ATTRIBUTE_UNUSED)
16106 char *name = input_line_pointer, ch;
16108 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16109 ++input_line_pointer;
16110 ch = *input_line_pointer;
16111 *input_line_pointer = '\0';
16113 if (strcmp (name, "reorder") == 0)
16115 if (mips_opts.noreorder)
16118 else if (strcmp (name, "noreorder") == 0)
16120 if (!mips_opts.noreorder)
16121 start_noreorder ();
16123 else if (strncmp (name, "at=", 3) == 0)
16125 char *s = name + 3;
16127 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16128 as_bad (_("Unrecognized register name `%s'"), s);
16130 else if (strcmp (name, "at") == 0)
16132 mips_opts.at = ATREG;
16134 else if (strcmp (name, "noat") == 0)
16136 mips_opts.at = ZERO;
16138 else if (strcmp (name, "macro") == 0)
16140 mips_opts.warn_about_macros = 0;
16142 else if (strcmp (name, "nomacro") == 0)
16144 if (mips_opts.noreorder == 0)
16145 as_bad (_("`noreorder' must be set before `nomacro'"));
16146 mips_opts.warn_about_macros = 1;
16148 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16150 mips_opts.nomove = 0;
16152 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16154 mips_opts.nomove = 1;
16156 else if (strcmp (name, "bopt") == 0)
16158 mips_opts.nobopt = 0;
16160 else if (strcmp (name, "nobopt") == 0)
16162 mips_opts.nobopt = 1;
16164 else if (strcmp (name, "gp=default") == 0)
16165 mips_opts.gp32 = file_mips_gp32;
16166 else if (strcmp (name, "gp=32") == 0)
16167 mips_opts.gp32 = 1;
16168 else if (strcmp (name, "gp=64") == 0)
16170 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16171 as_warn (_("%s isa does not support 64-bit registers"),
16172 mips_cpu_info_from_isa (mips_opts.isa)->name);
16173 mips_opts.gp32 = 0;
16175 else if (strcmp (name, "fp=default") == 0)
16176 mips_opts.fp32 = file_mips_fp32;
16177 else if (strcmp (name, "fp=32") == 0)
16178 mips_opts.fp32 = 1;
16179 else if (strcmp (name, "fp=64") == 0)
16181 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16182 as_warn (_("%s isa does not support 64-bit floating point registers"),
16183 mips_cpu_info_from_isa (mips_opts.isa)->name);
16184 mips_opts.fp32 = 0;
16186 else if (strcmp (name, "softfloat") == 0)
16187 mips_opts.soft_float = 1;
16188 else if (strcmp (name, "hardfloat") == 0)
16189 mips_opts.soft_float = 0;
16190 else if (strcmp (name, "singlefloat") == 0)
16191 mips_opts.single_float = 1;
16192 else if (strcmp (name, "doublefloat") == 0)
16193 mips_opts.single_float = 0;
16194 else if (strcmp (name, "mips16") == 0
16195 || strcmp (name, "MIPS-16") == 0)
16197 if (mips_opts.micromips == 1)
16198 as_fatal (_("`mips16' cannot be used with `micromips'"));
16199 mips_opts.mips16 = 1;
16201 else if (strcmp (name, "nomips16") == 0
16202 || strcmp (name, "noMIPS-16") == 0)
16203 mips_opts.mips16 = 0;
16204 else if (strcmp (name, "micromips") == 0)
16206 if (mips_opts.mips16 == 1)
16207 as_fatal (_("`micromips' cannot be used with `mips16'"));
16208 mips_opts.micromips = 1;
16210 else if (strcmp (name, "nomicromips") == 0)
16211 mips_opts.micromips = 0;
16212 else if (strcmp (name, "smartmips") == 0)
16214 if (!ISA_SUPPORTS_SMARTMIPS)
16215 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16216 mips_cpu_info_from_isa (mips_opts.isa)->name);
16217 mips_opts.ase_smartmips = 1;
16219 else if (strcmp (name, "nosmartmips") == 0)
16220 mips_opts.ase_smartmips = 0;
16221 else if (strcmp (name, "mips3d") == 0)
16222 mips_opts.ase_mips3d = 1;
16223 else if (strcmp (name, "nomips3d") == 0)
16224 mips_opts.ase_mips3d = 0;
16225 else if (strcmp (name, "mdmx") == 0)
16226 mips_opts.ase_mdmx = 1;
16227 else if (strcmp (name, "nomdmx") == 0)
16228 mips_opts.ase_mdmx = 0;
16229 else if (strcmp (name, "dsp") == 0)
16231 if (!ISA_SUPPORTS_DSP_ASE)
16232 as_warn (_("%s ISA does not support DSP ASE"),
16233 mips_cpu_info_from_isa (mips_opts.isa)->name);
16234 mips_opts.ase_dsp = 1;
16235 mips_opts.ase_dspr2 = 0;
16237 else if (strcmp (name, "nodsp") == 0)
16239 mips_opts.ase_dsp = 0;
16240 mips_opts.ase_dspr2 = 0;
16242 else if (strcmp (name, "dspr2") == 0)
16244 if (!ISA_SUPPORTS_DSPR2_ASE)
16245 as_warn (_("%s ISA does not support DSP R2 ASE"),
16246 mips_cpu_info_from_isa (mips_opts.isa)->name);
16247 mips_opts.ase_dspr2 = 1;
16248 mips_opts.ase_dsp = 1;
16250 else if (strcmp (name, "nodspr2") == 0)
16252 mips_opts.ase_dspr2 = 0;
16253 mips_opts.ase_dsp = 0;
16255 else if (strcmp (name, "mt") == 0)
16257 if (!ISA_SUPPORTS_MT_ASE)
16258 as_warn (_("%s ISA does not support MT ASE"),
16259 mips_cpu_info_from_isa (mips_opts.isa)->name);
16260 mips_opts.ase_mt = 1;
16262 else if (strcmp (name, "nomt") == 0)
16263 mips_opts.ase_mt = 0;
16264 else if (strcmp (name, "mcu") == 0)
16265 mips_opts.ase_mcu = 1;
16266 else if (strcmp (name, "nomcu") == 0)
16267 mips_opts.ase_mcu = 0;
16268 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16272 /* Permit the user to change the ISA and architecture on the fly.
16273 Needless to say, misuse can cause serious problems. */
16274 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16277 mips_opts.isa = file_mips_isa;
16278 mips_opts.arch = file_mips_arch;
16280 else if (strncmp (name, "arch=", 5) == 0)
16282 const struct mips_cpu_info *p;
16284 p = mips_parse_cpu("internal use", name + 5);
16286 as_bad (_("unknown architecture %s"), name + 5);
16289 mips_opts.arch = p->cpu;
16290 mips_opts.isa = p->isa;
16293 else if (strncmp (name, "mips", 4) == 0)
16295 const struct mips_cpu_info *p;
16297 p = mips_parse_cpu("internal use", name);
16299 as_bad (_("unknown ISA level %s"), name + 4);
16302 mips_opts.arch = p->cpu;
16303 mips_opts.isa = p->isa;
16307 as_bad (_("unknown ISA or architecture %s"), name);
16309 switch (mips_opts.isa)
16317 mips_opts.gp32 = 1;
16318 mips_opts.fp32 = 1;
16325 mips_opts.gp32 = 0;
16326 mips_opts.fp32 = 0;
16329 as_bad (_("unknown ISA level %s"), name + 4);
16334 mips_opts.gp32 = file_mips_gp32;
16335 mips_opts.fp32 = file_mips_fp32;
16338 else if (strcmp (name, "autoextend") == 0)
16339 mips_opts.noautoextend = 0;
16340 else if (strcmp (name, "noautoextend") == 0)
16341 mips_opts.noautoextend = 1;
16342 else if (strcmp (name, "push") == 0)
16344 struct mips_option_stack *s;
16346 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16347 s->next = mips_opts_stack;
16348 s->options = mips_opts;
16349 mips_opts_stack = s;
16351 else if (strcmp (name, "pop") == 0)
16353 struct mips_option_stack *s;
16355 s = mips_opts_stack;
16357 as_bad (_(".set pop with no .set push"));
16360 /* If we're changing the reorder mode we need to handle
16361 delay slots correctly. */
16362 if (s->options.noreorder && ! mips_opts.noreorder)
16363 start_noreorder ();
16364 else if (! s->options.noreorder && mips_opts.noreorder)
16367 mips_opts = s->options;
16368 mips_opts_stack = s->next;
16372 else if (strcmp (name, "sym32") == 0)
16373 mips_opts.sym32 = TRUE;
16374 else if (strcmp (name, "nosym32") == 0)
16375 mips_opts.sym32 = FALSE;
16376 else if (strchr (name, ','))
16378 /* Generic ".set" directive; use the generic handler. */
16379 *input_line_pointer = ch;
16380 input_line_pointer = name;
16386 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16388 *input_line_pointer = ch;
16389 demand_empty_rest_of_line ();
16392 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16393 .option pic2. It means to generate SVR4 PIC calls. */
16396 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16398 mips_pic = SVR4_PIC;
16399 mips_abicalls = TRUE;
16401 if (g_switch_seen && g_switch_value != 0)
16402 as_warn (_("-G may not be used with SVR4 PIC code"));
16403 g_switch_value = 0;
16405 bfd_set_gp_size (stdoutput, 0);
16406 demand_empty_rest_of_line ();
16409 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16410 PIC code. It sets the $gp register for the function based on the
16411 function address, which is in the register named in the argument.
16412 This uses a relocation against _gp_disp, which is handled specially
16413 by the linker. The result is:
16414 lui $gp,%hi(_gp_disp)
16415 addiu $gp,$gp,%lo(_gp_disp)
16416 addu $gp,$gp,.cpload argument
16417 The .cpload argument is normally $25 == $t9.
16419 The -mno-shared option changes this to:
16420 lui $gp,%hi(__gnu_local_gp)
16421 addiu $gp,$gp,%lo(__gnu_local_gp)
16422 and the argument is ignored. This saves an instruction, but the
16423 resulting code is not position independent; it uses an absolute
16424 address for __gnu_local_gp. Thus code assembled with -mno-shared
16425 can go into an ordinary executable, but not into a shared library. */
16428 s_cpload (int ignore ATTRIBUTE_UNUSED)
16434 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16435 .cpload is ignored. */
16436 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16442 /* .cpload should be in a .set noreorder section. */
16443 if (mips_opts.noreorder == 0)
16444 as_warn (_(".cpload not in noreorder section"));
16446 reg = tc_get_register (0);
16448 /* If we need to produce a 64-bit address, we are better off using
16449 the default instruction sequence. */
16450 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16452 ex.X_op = O_symbol;
16453 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16455 ex.X_op_symbol = NULL;
16456 ex.X_add_number = 0;
16458 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16459 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16462 macro_build_lui (&ex, mips_gp_register);
16463 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16464 mips_gp_register, BFD_RELOC_LO16);
16466 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16467 mips_gp_register, reg);
16470 demand_empty_rest_of_line ();
16473 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16474 .cpsetup $reg1, offset|$reg2, label
16476 If offset is given, this results in:
16477 sd $gp, offset($sp)
16478 lui $gp, %hi(%neg(%gp_rel(label)))
16479 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16480 daddu $gp, $gp, $reg1
16482 If $reg2 is given, this results in:
16483 daddu $reg2, $gp, $0
16484 lui $gp, %hi(%neg(%gp_rel(label)))
16485 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16486 daddu $gp, $gp, $reg1
16487 $reg1 is normally $25 == $t9.
16489 The -mno-shared option replaces the last three instructions with
16491 addiu $gp,$gp,%lo(_gp) */
16494 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16496 expressionS ex_off;
16497 expressionS ex_sym;
16500 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16501 We also need NewABI support. */
16502 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16508 reg1 = tc_get_register (0);
16509 SKIP_WHITESPACE ();
16510 if (*input_line_pointer != ',')
16512 as_bad (_("missing argument separator ',' for .cpsetup"));
16516 ++input_line_pointer;
16517 SKIP_WHITESPACE ();
16518 if (*input_line_pointer == '$')
16520 mips_cpreturn_register = tc_get_register (0);
16521 mips_cpreturn_offset = -1;
16525 mips_cpreturn_offset = get_absolute_expression ();
16526 mips_cpreturn_register = -1;
16528 SKIP_WHITESPACE ();
16529 if (*input_line_pointer != ',')
16531 as_bad (_("missing argument separator ',' for .cpsetup"));
16535 ++input_line_pointer;
16536 SKIP_WHITESPACE ();
16537 expression (&ex_sym);
16540 if (mips_cpreturn_register == -1)
16542 ex_off.X_op = O_constant;
16543 ex_off.X_add_symbol = NULL;
16544 ex_off.X_op_symbol = NULL;
16545 ex_off.X_add_number = mips_cpreturn_offset;
16547 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16548 BFD_RELOC_LO16, SP);
16551 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16552 mips_gp_register, 0);
16554 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16556 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16557 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16560 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16561 mips_gp_register, -1, BFD_RELOC_GPREL16,
16562 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16564 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16565 mips_gp_register, reg1);
16571 ex.X_op = O_symbol;
16572 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16573 ex.X_op_symbol = NULL;
16574 ex.X_add_number = 0;
16576 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16577 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16579 macro_build_lui (&ex, mips_gp_register);
16580 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16581 mips_gp_register, BFD_RELOC_LO16);
16586 demand_empty_rest_of_line ();
16590 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16592 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16593 .cplocal is ignored. */
16594 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16600 mips_gp_register = tc_get_register (0);
16601 demand_empty_rest_of_line ();
16604 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16605 offset from $sp. The offset is remembered, and after making a PIC
16606 call $gp is restored from that location. */
16609 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16613 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16614 .cprestore is ignored. */
16615 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16621 mips_cprestore_offset = get_absolute_expression ();
16622 mips_cprestore_valid = 1;
16624 ex.X_op = O_constant;
16625 ex.X_add_symbol = NULL;
16626 ex.X_op_symbol = NULL;
16627 ex.X_add_number = mips_cprestore_offset;
16630 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16631 SP, HAVE_64BIT_ADDRESSES);
16634 demand_empty_rest_of_line ();
16637 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16638 was given in the preceding .cpsetup, it results in:
16639 ld $gp, offset($sp)
16641 If a register $reg2 was given there, it results in:
16642 daddu $gp, $reg2, $0 */
16645 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16649 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16650 We also need NewABI support. */
16651 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16658 if (mips_cpreturn_register == -1)
16660 ex.X_op = O_constant;
16661 ex.X_add_symbol = NULL;
16662 ex.X_op_symbol = NULL;
16663 ex.X_add_number = mips_cpreturn_offset;
16665 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16668 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16669 mips_cpreturn_register, 0);
16672 demand_empty_rest_of_line ();
16675 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16676 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16677 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16678 debug information or MIPS16 TLS. */
16681 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16682 bfd_reloc_code_real_type rtype)
16689 if (ex.X_op != O_symbol)
16691 as_bad (_("Unsupported use of %s"), dirstr);
16692 ignore_rest_of_line ();
16695 p = frag_more (bytes);
16696 md_number_to_chars (p, 0, bytes);
16697 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16698 demand_empty_rest_of_line ();
16699 mips_clear_insn_labels ();
16702 /* Handle .dtprelword. */
16705 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16707 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16710 /* Handle .dtpreldword. */
16713 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16715 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16718 /* Handle .tprelword. */
16721 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16723 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16726 /* Handle .tpreldword. */
16729 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16731 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16734 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16735 code. It sets the offset to use in gp_rel relocations. */
16738 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16740 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16741 We also need NewABI support. */
16742 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16748 mips_gprel_offset = get_absolute_expression ();
16750 demand_empty_rest_of_line ();
16753 /* Handle the .gpword pseudo-op. This is used when generating PIC
16754 code. It generates a 32 bit GP relative reloc. */
16757 s_gpword (int ignore ATTRIBUTE_UNUSED)
16759 segment_info_type *si;
16760 struct insn_label_list *l;
16764 /* When not generating PIC code, this is treated as .word. */
16765 if (mips_pic != SVR4_PIC)
16771 si = seg_info (now_seg);
16772 l = si->label_list;
16773 mips_emit_delays ();
16775 mips_align (2, 0, l);
16778 mips_clear_insn_labels ();
16780 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16782 as_bad (_("Unsupported use of .gpword"));
16783 ignore_rest_of_line ();
16787 md_number_to_chars (p, 0, 4);
16788 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16789 BFD_RELOC_GPREL32);
16791 demand_empty_rest_of_line ();
16795 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16797 segment_info_type *si;
16798 struct insn_label_list *l;
16802 /* When not generating PIC code, this is treated as .dword. */
16803 if (mips_pic != SVR4_PIC)
16809 si = seg_info (now_seg);
16810 l = si->label_list;
16811 mips_emit_delays ();
16813 mips_align (3, 0, l);
16816 mips_clear_insn_labels ();
16818 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16820 as_bad (_("Unsupported use of .gpdword"));
16821 ignore_rest_of_line ();
16825 md_number_to_chars (p, 0, 8);
16826 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16827 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16829 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16830 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16831 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16833 demand_empty_rest_of_line ();
16836 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16837 tables in SVR4 PIC code. */
16840 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16844 /* This is ignored when not generating SVR4 PIC code. */
16845 if (mips_pic != SVR4_PIC)
16851 /* Add $gp to the register named as an argument. */
16853 reg = tc_get_register (0);
16854 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16857 demand_empty_rest_of_line ();
16860 /* Handle the .insn pseudo-op. This marks instruction labels in
16861 mips16/micromips mode. This permits the linker to handle them specially,
16862 such as generating jalx instructions when needed. We also make
16863 them odd for the duration of the assembly, in order to generate the
16864 right sort of code. We will make them even in the adjust_symtab
16865 routine, while leaving them marked. This is convenient for the
16866 debugger and the disassembler. The linker knows to make them odd
16870 s_insn (int ignore ATTRIBUTE_UNUSED)
16872 mips_mark_labels ();
16874 demand_empty_rest_of_line ();
16877 /* Handle a .stabn directive. We need these in order to mark a label
16878 as being a mips16 text label correctly. Sometimes the compiler
16879 will emit a label, followed by a .stabn, and then switch sections.
16880 If the label and .stabn are in mips16 mode, then the label is
16881 really a mips16 text label. */
16884 s_mips_stab (int type)
16887 mips_mark_labels ();
16892 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16895 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16902 name = input_line_pointer;
16903 c = get_symbol_end ();
16904 symbolP = symbol_find_or_make (name);
16905 S_SET_WEAK (symbolP);
16906 *input_line_pointer = c;
16908 SKIP_WHITESPACE ();
16910 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16912 if (S_IS_DEFINED (symbolP))
16914 as_bad (_("ignoring attempt to redefine symbol %s"),
16915 S_GET_NAME (symbolP));
16916 ignore_rest_of_line ();
16920 if (*input_line_pointer == ',')
16922 ++input_line_pointer;
16923 SKIP_WHITESPACE ();
16927 if (exp.X_op != O_symbol)
16929 as_bad (_("bad .weakext directive"));
16930 ignore_rest_of_line ();
16933 symbol_set_value_expression (symbolP, &exp);
16936 demand_empty_rest_of_line ();
16939 /* Parse a register string into a number. Called from the ECOFF code
16940 to parse .frame. The argument is non-zero if this is the frame
16941 register, so that we can record it in mips_frame_reg. */
16944 tc_get_register (int frame)
16948 SKIP_WHITESPACE ();
16949 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16953 mips_frame_reg = reg != 0 ? reg : SP;
16954 mips_frame_reg_valid = 1;
16955 mips_cprestore_valid = 0;
16961 md_section_align (asection *seg, valueT addr)
16963 int align = bfd_get_section_alignment (stdoutput, seg);
16967 /* We don't need to align ELF sections to the full alignment.
16968 However, Irix 5 may prefer that we align them at least to a 16
16969 byte boundary. We don't bother to align the sections if we
16970 are targeted for an embedded system. */
16971 if (strncmp (TARGET_OS, "elf", 3) == 0)
16977 return ((addr + (1 << align) - 1) & (-1 << align));
16980 /* Utility routine, called from above as well. If called while the
16981 input file is still being read, it's only an approximation. (For
16982 example, a symbol may later become defined which appeared to be
16983 undefined earlier.) */
16986 nopic_need_relax (symbolS *sym, int before_relaxing)
16991 if (g_switch_value > 0)
16993 const char *symname;
16996 /* Find out whether this symbol can be referenced off the $gp
16997 register. It can be if it is smaller than the -G size or if
16998 it is in the .sdata or .sbss section. Certain symbols can
16999 not be referenced off the $gp, although it appears as though
17001 symname = S_GET_NAME (sym);
17002 if (symname != (const char *) NULL
17003 && (strcmp (symname, "eprol") == 0
17004 || strcmp (symname, "etext") == 0
17005 || strcmp (symname, "_gp") == 0
17006 || strcmp (symname, "edata") == 0
17007 || strcmp (symname, "_fbss") == 0
17008 || strcmp (symname, "_fdata") == 0
17009 || strcmp (symname, "_ftext") == 0
17010 || strcmp (symname, "end") == 0
17011 || strcmp (symname, "_gp_disp") == 0))
17013 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17015 #ifndef NO_ECOFF_DEBUGGING
17016 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17017 && (symbol_get_obj (sym)->ecoff_extern_size
17018 <= g_switch_value))
17020 /* We must defer this decision until after the whole
17021 file has been read, since there might be a .extern
17022 after the first use of this symbol. */
17023 || (before_relaxing
17024 #ifndef NO_ECOFF_DEBUGGING
17025 && symbol_get_obj (sym)->ecoff_extern_size == 0
17027 && S_GET_VALUE (sym) == 0)
17028 || (S_GET_VALUE (sym) != 0
17029 && S_GET_VALUE (sym) <= g_switch_value)))
17033 const char *segname;
17035 segname = segment_name (S_GET_SEGMENT (sym));
17036 gas_assert (strcmp (segname, ".lit8") != 0
17037 && strcmp (segname, ".lit4") != 0);
17038 change = (strcmp (segname, ".sdata") != 0
17039 && strcmp (segname, ".sbss") != 0
17040 && strncmp (segname, ".sdata.", 7) != 0
17041 && strncmp (segname, ".sbss.", 6) != 0
17042 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17043 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17048 /* We are not optimizing for the $gp register. */
17053 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17056 pic_need_relax (symbolS *sym, asection *segtype)
17060 /* Handle the case of a symbol equated to another symbol. */
17061 while (symbol_equated_reloc_p (sym))
17065 /* It's possible to get a loop here in a badly written program. */
17066 n = symbol_get_value_expression (sym)->X_add_symbol;
17072 if (symbol_section_p (sym))
17075 symsec = S_GET_SEGMENT (sym);
17077 /* This must duplicate the test in adjust_reloc_syms. */
17078 return (!bfd_is_und_section (symsec)
17079 && !bfd_is_abs_section (symsec)
17080 && !bfd_is_com_section (symsec)
17081 && !s_is_linkonce (sym, segtype)
17083 /* A global or weak symbol is treated as external. */
17084 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17090 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17091 extended opcode. SEC is the section the frag is in. */
17094 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17097 const struct mips16_immed_operand *op;
17099 int mintiny, maxtiny;
17103 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17105 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17108 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17109 op = mips16_immed_operands;
17110 while (op->type != type)
17113 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17118 if (type == '<' || type == '>' || type == '[' || type == ']')
17121 maxtiny = 1 << op->nbits;
17126 maxtiny = (1 << op->nbits) - 1;
17131 mintiny = - (1 << (op->nbits - 1));
17132 maxtiny = (1 << (op->nbits - 1)) - 1;
17135 sym_frag = symbol_get_frag (fragp->fr_symbol);
17136 val = S_GET_VALUE (fragp->fr_symbol);
17137 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17143 /* We won't have the section when we are called from
17144 mips_relax_frag. However, we will always have been called
17145 from md_estimate_size_before_relax first. If this is a
17146 branch to a different section, we mark it as such. If SEC is
17147 NULL, and the frag is not marked, then it must be a branch to
17148 the same section. */
17151 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17156 /* Must have been called from md_estimate_size_before_relax. */
17159 fragp->fr_subtype =
17160 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17162 /* FIXME: We should support this, and let the linker
17163 catch branches and loads that are out of range. */
17164 as_bad_where (fragp->fr_file, fragp->fr_line,
17165 _("unsupported PC relative reference to different section"));
17169 if (fragp != sym_frag && sym_frag->fr_address == 0)
17170 /* Assume non-extended on the first relaxation pass.
17171 The address we have calculated will be bogus if this is
17172 a forward branch to another frag, as the forward frag
17173 will have fr_address == 0. */
17177 /* In this case, we know for sure that the symbol fragment is in
17178 the same section. If the relax_marker of the symbol fragment
17179 differs from the relax_marker of this fragment, we have not
17180 yet adjusted the symbol fragment fr_address. We want to add
17181 in STRETCH in order to get a better estimate of the address.
17182 This particularly matters because of the shift bits. */
17184 && sym_frag->relax_marker != fragp->relax_marker)
17188 /* Adjust stretch for any alignment frag. Note that if have
17189 been expanding the earlier code, the symbol may be
17190 defined in what appears to be an earlier frag. FIXME:
17191 This doesn't handle the fr_subtype field, which specifies
17192 a maximum number of bytes to skip when doing an
17194 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17196 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17199 stretch = - ((- stretch)
17200 & ~ ((1 << (int) f->fr_offset) - 1));
17202 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17211 addr = fragp->fr_address + fragp->fr_fix;
17213 /* The base address rules are complicated. The base address of
17214 a branch is the following instruction. The base address of a
17215 PC relative load or add is the instruction itself, but if it
17216 is in a delay slot (in which case it can not be extended) use
17217 the address of the instruction whose delay slot it is in. */
17218 if (type == 'p' || type == 'q')
17222 /* If we are currently assuming that this frag should be
17223 extended, then, the current address is two bytes
17225 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17228 /* Ignore the low bit in the target, since it will be set
17229 for a text label. */
17230 if ((val & 1) != 0)
17233 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17235 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17238 val -= addr & ~ ((1 << op->shift) - 1);
17240 /* Branch offsets have an implicit 0 in the lowest bit. */
17241 if (type == 'p' || type == 'q')
17244 /* If any of the shifted bits are set, we must use an extended
17245 opcode. If the address depends on the size of this
17246 instruction, this can lead to a loop, so we arrange to always
17247 use an extended opcode. We only check this when we are in
17248 the main relaxation loop, when SEC is NULL. */
17249 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17251 fragp->fr_subtype =
17252 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17256 /* If we are about to mark a frag as extended because the value
17257 is precisely maxtiny + 1, then there is a chance of an
17258 infinite loop as in the following code:
17263 In this case when the la is extended, foo is 0x3fc bytes
17264 away, so the la can be shrunk, but then foo is 0x400 away, so
17265 the la must be extended. To avoid this loop, we mark the
17266 frag as extended if it was small, and is about to become
17267 extended with a value of maxtiny + 1. */
17268 if (val == ((maxtiny + 1) << op->shift)
17269 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17272 fragp->fr_subtype =
17273 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17277 else if (symsec != absolute_section && sec != NULL)
17278 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17280 if ((val & ((1 << op->shift) - 1)) != 0
17281 || val < (mintiny << op->shift)
17282 || val > (maxtiny << op->shift))
17288 /* Compute the length of a branch sequence, and adjust the
17289 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17290 worst-case length is computed, with UPDATE being used to indicate
17291 whether an unconditional (-1), branch-likely (+1) or regular (0)
17292 branch is to be computed. */
17294 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17296 bfd_boolean toofar;
17300 && S_IS_DEFINED (fragp->fr_symbol)
17301 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17306 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17308 addr = fragp->fr_address + fragp->fr_fix + 4;
17312 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17315 /* If the symbol is not defined or it's in a different segment,
17316 assume the user knows what's going on and emit a short
17322 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17324 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17325 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17326 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17327 RELAX_BRANCH_LINK (fragp->fr_subtype),
17333 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17336 if (mips_pic != NO_PIC)
17338 /* Additional space for PIC loading of target address. */
17340 if (mips_opts.isa == ISA_MIPS1)
17341 /* Additional space for $at-stabilizing nop. */
17345 /* If branch is conditional. */
17346 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17353 /* Compute the length of a branch sequence, and adjust the
17354 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17355 worst-case length is computed, with UPDATE being used to indicate
17356 whether an unconditional (-1), or regular (0) branch is to be
17360 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17362 bfd_boolean toofar;
17366 && S_IS_DEFINED (fragp->fr_symbol)
17367 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17372 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17373 /* Ignore the low bit in the target, since it will be set
17374 for a text label. */
17375 if ((val & 1) != 0)
17378 addr = fragp->fr_address + fragp->fr_fix + 4;
17382 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17385 /* If the symbol is not defined or it's in a different segment,
17386 assume the user knows what's going on and emit a short
17392 if (fragp && update
17393 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17394 fragp->fr_subtype = (toofar
17395 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17396 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17401 bfd_boolean compact_known = fragp != NULL;
17402 bfd_boolean compact = FALSE;
17403 bfd_boolean uncond;
17406 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17408 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17410 uncond = update < 0;
17412 /* If label is out of range, we turn branch <br>:
17414 <br> label # 4 bytes
17420 nop # 2 bytes if compact && !PIC
17423 if (mips_pic == NO_PIC && (!compact_known || compact))
17426 /* If assembling PIC code, we further turn:
17432 lw/ld at, %got(label)(gp) # 4 bytes
17433 d/addiu at, %lo(label) # 4 bytes
17436 if (mips_pic != NO_PIC)
17439 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17441 <brneg> 0f # 4 bytes
17442 nop # 2 bytes if !compact
17445 length += (compact_known && compact) ? 4 : 6;
17451 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17452 bit accordingly. */
17455 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17457 bfd_boolean toofar;
17460 && S_IS_DEFINED (fragp->fr_symbol)
17461 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17467 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17468 /* Ignore the low bit in the target, since it will be set
17469 for a text label. */
17470 if ((val & 1) != 0)
17473 /* Assume this is a 2-byte branch. */
17474 addr = fragp->fr_address + fragp->fr_fix + 2;
17476 /* We try to avoid the infinite loop by not adding 2 more bytes for
17481 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17483 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17484 else if (type == 'E')
17485 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17490 /* If the symbol is not defined or it's in a different segment,
17491 we emit a normal 32-bit branch. */
17494 if (fragp && update
17495 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17497 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17498 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17506 /* Estimate the size of a frag before relaxing. Unless this is the
17507 mips16, we are not really relaxing here, and the final size is
17508 encoded in the subtype information. For the mips16, we have to
17509 decide whether we are using an extended opcode or not. */
17512 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17516 if (RELAX_BRANCH_P (fragp->fr_subtype))
17519 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17521 return fragp->fr_var;
17524 if (RELAX_MIPS16_P (fragp->fr_subtype))
17525 /* We don't want to modify the EXTENDED bit here; it might get us
17526 into infinite loops. We change it only in mips_relax_frag(). */
17527 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17529 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17533 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17534 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17535 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17536 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17537 fragp->fr_var = length;
17542 if (mips_pic == NO_PIC)
17543 change = nopic_need_relax (fragp->fr_symbol, 0);
17544 else if (mips_pic == SVR4_PIC)
17545 change = pic_need_relax (fragp->fr_symbol, segtype);
17546 else if (mips_pic == VXWORKS_PIC)
17547 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17554 fragp->fr_subtype |= RELAX_USE_SECOND;
17555 return -RELAX_FIRST (fragp->fr_subtype);
17558 return -RELAX_SECOND (fragp->fr_subtype);
17561 /* This is called to see whether a reloc against a defined symbol
17562 should be converted into a reloc against a section. */
17565 mips_fix_adjustable (fixS *fixp)
17567 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17568 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17571 if (fixp->fx_addsy == NULL)
17574 /* If symbol SYM is in a mergeable section, relocations of the form
17575 SYM + 0 can usually be made section-relative. The mergeable data
17576 is then identified by the section offset rather than by the symbol.
17578 However, if we're generating REL LO16 relocations, the offset is split
17579 between the LO16 and parterning high part relocation. The linker will
17580 need to recalculate the complete offset in order to correctly identify
17583 The linker has traditionally not looked for the parterning high part
17584 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17585 placed anywhere. Rather than break backwards compatibility by changing
17586 this, it seems better not to force the issue, and instead keep the
17587 original symbol. This will work with either linker behavior. */
17588 if ((lo16_reloc_p (fixp->fx_r_type)
17589 || reloc_needs_lo_p (fixp->fx_r_type))
17590 && HAVE_IN_PLACE_ADDENDS
17591 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17594 /* There is no place to store an in-place offset for JALR relocations.
17595 Likewise an in-range offset of PC-relative relocations may overflow
17596 the in-place relocatable field if recalculated against the start
17597 address of the symbol's containing section. */
17598 if (HAVE_IN_PLACE_ADDENDS
17599 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17603 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17604 to a floating-point stub. The same is true for non-R_MIPS16_26
17605 relocations against MIPS16 functions; in this case, the stub becomes
17606 the function's canonical address.
17608 Floating-point stubs are stored in unique .mips16.call.* or
17609 .mips16.fn.* sections. If a stub T for function F is in section S,
17610 the first relocation in section S must be against F; this is how the
17611 linker determines the target function. All relocations that might
17612 resolve to T must also be against F. We therefore have the following
17613 restrictions, which are given in an intentionally-redundant way:
17615 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17618 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17619 if that stub might be used.
17621 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17624 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17625 that stub might be used.
17627 There is a further restriction:
17629 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17630 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17631 targets with in-place addends; the relocation field cannot
17632 encode the low bit.
17634 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17635 against a MIPS16 symbol. We deal with (5) by by not reducing any
17636 such relocations on REL targets.
17638 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17639 relocation against some symbol R, no relocation against R may be
17640 reduced. (Note that this deals with (2) as well as (1) because
17641 relocations against global symbols will never be reduced on ELF
17642 targets.) This approach is a little simpler than trying to detect
17643 stub sections, and gives the "all or nothing" per-symbol consistency
17644 that we have for MIPS16 symbols. */
17646 && fixp->fx_subsy == NULL
17647 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17648 || *symbol_get_tc (fixp->fx_addsy)
17649 || (HAVE_IN_PLACE_ADDENDS
17650 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17651 && jmp_reloc_p (fixp->fx_r_type))))
17658 /* Translate internal representation of relocation info to BFD target
17662 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17664 static arelent *retval[4];
17666 bfd_reloc_code_real_type code;
17668 memset (retval, 0, sizeof(retval));
17669 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17670 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17671 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17672 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17674 if (fixp->fx_pcrel)
17676 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17677 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17678 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17679 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17681 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17682 Relocations want only the symbol offset. */
17683 reloc->addend = fixp->fx_addnumber + reloc->address;
17686 /* A gruesome hack which is a result of the gruesome gas
17687 reloc handling. What's worse, for COFF (as opposed to
17688 ECOFF), we might need yet another copy of reloc->address.
17689 See bfd_install_relocation. */
17690 reloc->addend += reloc->address;
17694 reloc->addend = fixp->fx_addnumber;
17696 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17697 entry to be used in the relocation's section offset. */
17698 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17700 reloc->address = reloc->addend;
17704 code = fixp->fx_r_type;
17706 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17707 if (reloc->howto == NULL)
17709 as_bad_where (fixp->fx_file, fixp->fx_line,
17710 _("Can not represent %s relocation in this object file format"),
17711 bfd_get_reloc_code_name (code));
17718 /* Relax a machine dependent frag. This returns the amount by which
17719 the current size of the frag should change. */
17722 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17724 if (RELAX_BRANCH_P (fragp->fr_subtype))
17726 offsetT old_var = fragp->fr_var;
17728 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17730 return fragp->fr_var - old_var;
17733 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17735 offsetT old_var = fragp->fr_var;
17736 offsetT new_var = 4;
17738 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17739 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17740 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17741 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17742 fragp->fr_var = new_var;
17744 return new_var - old_var;
17747 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17750 if (mips16_extended_frag (fragp, NULL, stretch))
17752 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17754 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17759 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17761 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17768 /* Convert a machine dependent frag. */
17771 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17773 if (RELAX_BRANCH_P (fragp->fr_subtype))
17776 unsigned long insn;
17780 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
17782 if (target_big_endian)
17783 insn = bfd_getb32 (buf);
17785 insn = bfd_getl32 (buf);
17787 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17789 /* We generate a fixup instead of applying it right now
17790 because, if there are linker relaxations, we're going to
17791 need the relocations. */
17792 exp.X_op = O_symbol;
17793 exp.X_add_symbol = fragp->fr_symbol;
17794 exp.X_add_number = fragp->fr_offset;
17796 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17797 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
17798 fixp->fx_file = fragp->fr_file;
17799 fixp->fx_line = fragp->fr_line;
17801 md_number_to_chars ((char *) buf, insn, 4);
17808 as_warn_where (fragp->fr_file, fragp->fr_line,
17809 _("Relaxed out-of-range branch into a jump"));
17811 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17814 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17816 /* Reverse the branch. */
17817 switch ((insn >> 28) & 0xf)
17820 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17821 have the condition reversed by tweaking a single
17822 bit, and their opcodes all have 0x4???????. */
17823 gas_assert ((insn & 0xf1000000) == 0x41000000);
17824 insn ^= 0x00010000;
17828 /* bltz 0x04000000 bgez 0x04010000
17829 bltzal 0x04100000 bgezal 0x04110000 */
17830 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17831 insn ^= 0x00010000;
17835 /* beq 0x10000000 bne 0x14000000
17836 blez 0x18000000 bgtz 0x1c000000 */
17837 insn ^= 0x04000000;
17845 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17847 /* Clear the and-link bit. */
17848 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17850 /* bltzal 0x04100000 bgezal 0x04110000
17851 bltzall 0x04120000 bgezall 0x04130000 */
17852 insn &= ~0x00100000;
17855 /* Branch over the branch (if the branch was likely) or the
17856 full jump (not likely case). Compute the offset from the
17857 current instruction to branch to. */
17858 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17862 /* How many bytes in instructions we've already emitted? */
17863 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17864 /* How many bytes in instructions from here to the end? */
17865 i = fragp->fr_var - i;
17867 /* Convert to instruction count. */
17869 /* Branch counts from the next instruction. */
17872 /* Branch over the jump. */
17873 md_number_to_chars ((char *) buf, insn, 4);
17877 md_number_to_chars ((char *) buf, 0, 4);
17880 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17882 /* beql $0, $0, 2f */
17884 /* Compute the PC offset from the current instruction to
17885 the end of the variable frag. */
17886 /* How many bytes in instructions we've already emitted? */
17887 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17888 /* How many bytes in instructions from here to the end? */
17889 i = fragp->fr_var - i;
17890 /* Convert to instruction count. */
17892 /* Don't decrement i, because we want to branch over the
17896 md_number_to_chars ((char *) buf, insn, 4);
17899 md_number_to_chars ((char *) buf, 0, 4);
17904 if (mips_pic == NO_PIC)
17907 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17908 ? 0x0c000000 : 0x08000000);
17909 exp.X_op = O_symbol;
17910 exp.X_add_symbol = fragp->fr_symbol;
17911 exp.X_add_number = fragp->fr_offset;
17913 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17914 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
17915 fixp->fx_file = fragp->fr_file;
17916 fixp->fx_line = fragp->fr_line;
17918 md_number_to_chars ((char *) buf, insn, 4);
17923 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17925 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17926 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17927 insn |= at << OP_SH_RT;
17928 exp.X_op = O_symbol;
17929 exp.X_add_symbol = fragp->fr_symbol;
17930 exp.X_add_number = fragp->fr_offset;
17932 if (fragp->fr_offset)
17934 exp.X_add_symbol = make_expr_symbol (&exp);
17935 exp.X_add_number = 0;
17938 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17939 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
17940 fixp->fx_file = fragp->fr_file;
17941 fixp->fx_line = fragp->fr_line;
17943 md_number_to_chars ((char *) buf, insn, 4);
17946 if (mips_opts.isa == ISA_MIPS1)
17949 md_number_to_chars ((char *) buf, 0, 4);
17953 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17954 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17955 insn |= at << OP_SH_RS | at << OP_SH_RT;
17957 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17958 4, &exp, FALSE, BFD_RELOC_LO16);
17959 fixp->fx_file = fragp->fr_file;
17960 fixp->fx_line = fragp->fr_line;
17962 md_number_to_chars ((char *) buf, insn, 4);
17966 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17970 insn |= at << OP_SH_RS;
17972 md_number_to_chars ((char *) buf, insn, 4);
17977 gas_assert (buf == (bfd_byte *)fragp->fr_literal
17978 + fragp->fr_fix + fragp->fr_var);
17980 fragp->fr_fix += fragp->fr_var;
17985 /* Relax microMIPS branches. */
17986 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17988 bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
17989 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17990 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17991 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17992 bfd_boolean short_ds;
17993 unsigned long insn;
17997 exp.X_op = O_symbol;
17998 exp.X_add_symbol = fragp->fr_symbol;
17999 exp.X_add_number = fragp->fr_offset;
18001 fragp->fr_fix += fragp->fr_var;
18003 /* Handle 16-bit branches that fit or are forced to fit. */
18004 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18006 /* We generate a fixup instead of applying it right now,
18007 because if there is linker relaxation, we're going to
18008 need the relocations. */
18010 fixp = fix_new_exp (fragp,
18011 buf - (bfd_byte *) fragp->fr_literal,
18013 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18014 else if (type == 'E')
18015 fixp = fix_new_exp (fragp,
18016 buf - (bfd_byte *) fragp->fr_literal,
18018 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18022 fixp->fx_file = fragp->fr_file;
18023 fixp->fx_line = fragp->fr_line;
18025 /* These relocations can have an addend that won't fit in
18027 fixp->fx_no_overflow = 1;
18032 /* Handle 32-bit branches that fit or are forced to fit. */
18033 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18034 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18036 /* We generate a fixup instead of applying it right now,
18037 because if there is linker relaxation, we're going to
18038 need the relocations. */
18039 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18040 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18041 fixp->fx_file = fragp->fr_file;
18042 fixp->fx_line = fragp->fr_line;
18048 /* Relax 16-bit branches to 32-bit branches. */
18051 if (target_big_endian)
18052 insn = bfd_getb16 (buf);
18054 insn = bfd_getl16 (buf);
18056 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18057 insn = 0x94000000; /* beq */
18058 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18060 unsigned long regno;
18062 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18063 regno = micromips_to_32_reg_d_map [regno];
18064 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18065 insn |= regno << MICROMIPSOP_SH_RS;
18070 /* Nothing else to do, just write it out. */
18071 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18072 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18074 md_number_to_chars ((char *) buf, insn >> 16, 2);
18076 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18079 gas_assert (buf == ((bfd_byte *) fragp->fr_literal
18086 unsigned long next;
18088 if (target_big_endian)
18090 insn = bfd_getb16 (buf);
18091 next = bfd_getb16 (buf + 2);
18095 insn = bfd_getl16 (buf);
18096 next = bfd_getl16 (buf + 2);
18098 insn = (insn << 16) | next;
18101 /* Relax 32-bit branches to a sequence of instructions. */
18102 as_warn_where (fragp->fr_file, fragp->fr_line,
18103 _("Relaxed out-of-range branch into a jump"));
18105 /* Set the short-delay-slot bit. */
18106 short_ds = al && (insn & 0x02000000) != 0;
18108 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18112 /* Reverse the branch. */
18113 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18114 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18115 insn ^= 0x20000000;
18116 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18117 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18118 || (insn & 0xffe00000) == 0x40800000 /* blez */
18119 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18120 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18121 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18122 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18123 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18124 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18125 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18126 insn ^= 0x00400000;
18127 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18128 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18129 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18130 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18131 insn ^= 0x00200000;
18137 /* Clear the and-link and short-delay-slot bits. */
18138 gas_assert ((insn & 0xfda00000) == 0x40200000);
18140 /* bltzal 0x40200000 bgezal 0x40600000 */
18141 /* bltzals 0x42200000 bgezals 0x42600000 */
18142 insn &= ~0x02200000;
18145 /* Make a label at the end for use with the branch. */
18146 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18147 micromips_label_inc ();
18148 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18150 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18154 fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
18155 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18156 fixp->fx_file = fragp->fr_file;
18157 fixp->fx_line = fragp->fr_line;
18159 /* Branch over the jump. */
18160 md_number_to_chars ((char *) buf, insn >> 16, 2);
18162 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18169 md_number_to_chars ((char *) buf, insn, 2);
18174 if (mips_pic == NO_PIC)
18176 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18178 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18179 insn = al ? jal : 0xd4000000;
18181 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18182 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
18183 fixp->fx_file = fragp->fr_file;
18184 fixp->fx_line = fragp->fr_line;
18186 md_number_to_chars ((char *) buf, insn >> 16, 2);
18188 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18195 md_number_to_chars ((char *) buf, insn, 2);
18201 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18202 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18203 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18205 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18206 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18207 insn |= at << MICROMIPSOP_SH_RT;
18209 if (exp.X_add_number)
18211 exp.X_add_symbol = make_expr_symbol (&exp);
18212 exp.X_add_number = 0;
18215 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18216 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
18217 fixp->fx_file = fragp->fr_file;
18218 fixp->fx_line = fragp->fr_line;
18220 md_number_to_chars ((char *) buf, insn >> 16, 2);
18222 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18225 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18226 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18227 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18229 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18230 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
18231 fixp->fx_file = fragp->fr_file;
18232 fixp->fx_line = fragp->fr_line;
18234 md_number_to_chars ((char *) buf, insn >> 16, 2);
18236 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18239 /* jr/jrc/jalr/jalrs $at */
18240 insn = al ? jalr : jr;
18241 insn |= at << MICROMIPSOP_SH_MJ;
18243 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18247 gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
18251 if (RELAX_MIPS16_P (fragp->fr_subtype))
18254 const struct mips16_immed_operand *op;
18255 bfd_boolean small, ext;
18258 unsigned long insn;
18259 bfd_boolean use_extend;
18260 unsigned short extend;
18262 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18263 op = mips16_immed_operands;
18264 while (op->type != type)
18267 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18278 val = resolve_symbol_value (fragp->fr_symbol);
18283 addr = fragp->fr_address + fragp->fr_fix;
18285 /* The rules for the base address of a PC relative reloc are
18286 complicated; see mips16_extended_frag. */
18287 if (type == 'p' || type == 'q')
18292 /* Ignore the low bit in the target, since it will be
18293 set for a text label. */
18294 if ((val & 1) != 0)
18297 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18299 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18302 addr &= ~ (addressT) ((1 << op->shift) - 1);
18305 /* Make sure the section winds up with the alignment we have
18308 record_alignment (asec, op->shift);
18312 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18313 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18314 as_warn_where (fragp->fr_file, fragp->fr_line,
18315 _("extended instruction in delay slot"));
18317 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
18319 if (target_big_endian)
18320 insn = bfd_getb16 (buf);
18322 insn = bfd_getl16 (buf);
18324 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
18325 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
18326 small, ext, &insn, &use_extend, &extend);
18330 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
18331 fragp->fr_fix += 2;
18335 md_number_to_chars ((char *) buf, insn, 2);
18336 fragp->fr_fix += 2;
18341 relax_substateT subtype = fragp->fr_subtype;
18342 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18343 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18347 first = RELAX_FIRST (subtype);
18348 second = RELAX_SECOND (subtype);
18349 fixp = (fixS *) fragp->fr_opcode;
18351 /* If the delay slot chosen does not match the size of the instruction,
18352 then emit a warning. */
18353 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18354 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18359 s = subtype & (RELAX_DELAY_SLOT_16BIT
18360 | RELAX_DELAY_SLOT_SIZE_FIRST
18361 | RELAX_DELAY_SLOT_SIZE_SECOND);
18362 msg = macro_warning (s);
18364 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18368 /* Possibly emit a warning if we've chosen the longer option. */
18369 if (use_second == second_longer)
18375 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18376 msg = macro_warning (s);
18378 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18382 /* Go through all the fixups for the first sequence. Disable them
18383 (by marking them as done) if we're going to use the second
18384 sequence instead. */
18386 && fixp->fx_frag == fragp
18387 && fixp->fx_where < fragp->fr_fix - second)
18389 if (subtype & RELAX_USE_SECOND)
18391 fixp = fixp->fx_next;
18394 /* Go through the fixups for the second sequence. Disable them if
18395 we're going to use the first sequence, otherwise adjust their
18396 addresses to account for the relaxation. */
18397 while (fixp && fixp->fx_frag == fragp)
18399 if (subtype & RELAX_USE_SECOND)
18400 fixp->fx_where -= first;
18403 fixp = fixp->fx_next;
18406 /* Now modify the frag contents. */
18407 if (subtype & RELAX_USE_SECOND)
18411 start = fragp->fr_literal + fragp->fr_fix - first - second;
18412 memmove (start, start + first, second);
18413 fragp->fr_fix -= first;
18416 fragp->fr_fix -= second;
18422 /* This function is called after the relocs have been generated.
18423 We've been storing mips16 text labels as odd. Here we convert them
18424 back to even for the convenience of the debugger. */
18427 mips_frob_file_after_relocs (void)
18430 unsigned int count, i;
18435 syms = bfd_get_outsymbols (stdoutput);
18436 count = bfd_get_symcount (stdoutput);
18437 for (i = 0; i < count; i++, syms++)
18438 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18439 && ((*syms)->value & 1) != 0)
18441 (*syms)->value &= ~1;
18442 /* If the symbol has an odd size, it was probably computed
18443 incorrectly, so adjust that as well. */
18444 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18445 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18451 /* This function is called whenever a label is defined, including fake
18452 labels instantiated off the dot special symbol. It is used when
18453 handling branch delays; if a branch has a label, we assume we cannot
18454 move it. This also bumps the value of the symbol by 1 in compressed
18458 mips_record_label (symbolS *sym)
18460 segment_info_type *si = seg_info (now_seg);
18461 struct insn_label_list *l;
18463 if (free_insn_labels == NULL)
18464 l = (struct insn_label_list *) xmalloc (sizeof *l);
18467 l = free_insn_labels;
18468 free_insn_labels = l->next;
18472 l->next = si->label_list;
18473 si->label_list = l;
18476 /* This function is called as tc_frob_label() whenever a label is defined
18477 and adds a DWARF-2 record we only want for true labels. */
18480 mips_define_label (symbolS *sym)
18482 mips_record_label (sym);
18484 dwarf2_emit_label (sym);
18488 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18490 /* Some special processing for a MIPS ELF file. */
18493 mips_elf_final_processing (void)
18495 /* Write out the register information. */
18496 if (mips_abi != N64_ABI)
18500 s.ri_gprmask = mips_gprmask;
18501 s.ri_cprmask[0] = mips_cprmask[0];
18502 s.ri_cprmask[1] = mips_cprmask[1];
18503 s.ri_cprmask[2] = mips_cprmask[2];
18504 s.ri_cprmask[3] = mips_cprmask[3];
18505 /* The gp_value field is set by the MIPS ELF backend. */
18507 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18508 ((Elf32_External_RegInfo *)
18509 mips_regmask_frag));
18513 Elf64_Internal_RegInfo s;
18515 s.ri_gprmask = mips_gprmask;
18517 s.ri_cprmask[0] = mips_cprmask[0];
18518 s.ri_cprmask[1] = mips_cprmask[1];
18519 s.ri_cprmask[2] = mips_cprmask[2];
18520 s.ri_cprmask[3] = mips_cprmask[3];
18521 /* The gp_value field is set by the MIPS ELF backend. */
18523 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18524 ((Elf64_External_RegInfo *)
18525 mips_regmask_frag));
18528 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18529 sort of BFD interface for this. */
18530 if (mips_any_noreorder)
18531 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18532 if (mips_pic != NO_PIC)
18534 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18535 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18538 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18540 /* Set MIPS ELF flags for ASEs. */
18541 /* We may need to define a new flag for DSP ASE, and set this flag when
18542 file_ase_dsp is true. */
18543 /* Same for DSP R2. */
18544 /* We may need to define a new flag for MT ASE, and set this flag when
18545 file_ase_mt is true. */
18546 if (file_ase_mips16)
18547 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18548 if (file_ase_micromips)
18549 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18550 #if 0 /* XXX FIXME */
18551 if (file_ase_mips3d)
18552 elf_elfheader (stdoutput)->e_flags |= ???;
18555 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18557 /* Set the MIPS ELF ABI flags. */
18558 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18559 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18560 else if (mips_abi == O64_ABI)
18561 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18562 else if (mips_abi == EABI_ABI)
18564 if (!file_mips_gp32)
18565 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18567 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18569 else if (mips_abi == N32_ABI)
18570 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18572 /* Nothing to do for N64_ABI. */
18574 if (mips_32bitmode)
18575 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18577 #if 0 /* XXX FIXME */
18578 /* 32 bit code with 64 bit FP registers. */
18579 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18580 elf_elfheader (stdoutput)->e_flags |= ???;
18584 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18586 typedef struct proc {
18588 symbolS *func_end_sym;
18589 unsigned long reg_mask;
18590 unsigned long reg_offset;
18591 unsigned long fpreg_mask;
18592 unsigned long fpreg_offset;
18593 unsigned long frame_offset;
18594 unsigned long frame_reg;
18595 unsigned long pc_reg;
18598 static procS cur_proc;
18599 static procS *cur_proc_ptr;
18600 static int numprocs;
18602 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18603 as "2", and a normal nop as "0". */
18605 #define NOP_OPCODE_MIPS 0
18606 #define NOP_OPCODE_MIPS16 1
18607 #define NOP_OPCODE_MICROMIPS 2
18610 mips_nop_opcode (void)
18612 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18613 return NOP_OPCODE_MICROMIPS;
18614 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18615 return NOP_OPCODE_MIPS16;
18617 return NOP_OPCODE_MIPS;
18620 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18621 32-bit microMIPS NOPs here (if applicable). */
18624 mips_handle_align (fragS *fragp)
18628 int bytes, size, excess;
18631 if (fragp->fr_type != rs_align_code)
18634 p = fragp->fr_literal + fragp->fr_fix;
18636 switch (nop_opcode)
18638 case NOP_OPCODE_MICROMIPS:
18639 opcode = micromips_nop32_insn.insn_opcode;
18642 case NOP_OPCODE_MIPS16:
18643 opcode = mips16_nop_insn.insn_opcode;
18646 case NOP_OPCODE_MIPS:
18648 opcode = nop_insn.insn_opcode;
18653 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18654 excess = bytes % size;
18656 /* Handle the leading part if we're not inserting a whole number of
18657 instructions, and make it the end of the fixed part of the frag.
18658 Try to fit in a short microMIPS NOP if applicable and possible,
18659 and use zeroes otherwise. */
18660 gas_assert (excess < 4);
18661 fragp->fr_fix += excess;
18666 /* Fall through. */
18668 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18670 md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
18675 /* Fall through. */
18678 /* Fall through. */
18683 md_number_to_chars (p, opcode, size);
18684 fragp->fr_var = size;
18688 md_obj_begin (void)
18695 /* Check for premature end, nesting errors, etc. */
18697 as_warn (_("missing .end at end of assembly"));
18706 if (*input_line_pointer == '-')
18708 ++input_line_pointer;
18711 if (!ISDIGIT (*input_line_pointer))
18712 as_bad (_("expected simple number"));
18713 if (input_line_pointer[0] == '0')
18715 if (input_line_pointer[1] == 'x')
18717 input_line_pointer += 2;
18718 while (ISXDIGIT (*input_line_pointer))
18721 val |= hex_value (*input_line_pointer++);
18723 return negative ? -val : val;
18727 ++input_line_pointer;
18728 while (ISDIGIT (*input_line_pointer))
18731 val |= *input_line_pointer++ - '0';
18733 return negative ? -val : val;
18736 if (!ISDIGIT (*input_line_pointer))
18738 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18739 *input_line_pointer, *input_line_pointer);
18740 as_warn (_("invalid number"));
18743 while (ISDIGIT (*input_line_pointer))
18746 val += *input_line_pointer++ - '0';
18748 return negative ? -val : val;
18751 /* The .file directive; just like the usual .file directive, but there
18752 is an initial number which is the ECOFF file index. In the non-ECOFF
18753 case .file implies DWARF-2. */
18756 s_mips_file (int x ATTRIBUTE_UNUSED)
18758 static int first_file_directive = 0;
18760 if (ECOFF_DEBUGGING)
18769 filename = dwarf2_directive_file (0);
18771 /* Versions of GCC up to 3.1 start files with a ".file"
18772 directive even for stabs output. Make sure that this
18773 ".file" is handled. Note that you need a version of GCC
18774 after 3.1 in order to support DWARF-2 on MIPS. */
18775 if (filename != NULL && ! first_file_directive)
18777 (void) new_logical_line (filename, -1);
18778 s_app_file_string (filename, 0);
18780 first_file_directive = 1;
18784 /* The .loc directive, implying DWARF-2. */
18787 s_mips_loc (int x ATTRIBUTE_UNUSED)
18789 if (!ECOFF_DEBUGGING)
18790 dwarf2_directive_loc (0);
18793 /* The .end directive. */
18796 s_mips_end (int x ATTRIBUTE_UNUSED)
18800 /* Following functions need their own .frame and .cprestore directives. */
18801 mips_frame_reg_valid = 0;
18802 mips_cprestore_valid = 0;
18804 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18807 demand_empty_rest_of_line ();
18812 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18813 as_warn (_(".end not in text section"));
18817 as_warn (_(".end directive without a preceding .ent directive."));
18818 demand_empty_rest_of_line ();
18824 gas_assert (S_GET_NAME (p));
18825 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18826 as_warn (_(".end symbol does not match .ent symbol."));
18828 if (debug_type == DEBUG_STABS)
18829 stabs_generate_asm_endfunc (S_GET_NAME (p),
18833 as_warn (_(".end directive missing or unknown symbol"));
18836 /* Create an expression to calculate the size of the function. */
18837 if (p && cur_proc_ptr)
18839 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18840 expressionS *exp = xmalloc (sizeof (expressionS));
18843 exp->X_op = O_subtract;
18844 exp->X_add_symbol = symbol_temp_new_now ();
18845 exp->X_op_symbol = p;
18846 exp->X_add_number = 0;
18848 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18851 /* Generate a .pdr section. */
18852 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18854 segT saved_seg = now_seg;
18855 subsegT saved_subseg = now_subseg;
18859 #ifdef md_flush_pending_output
18860 md_flush_pending_output ();
18863 gas_assert (pdr_seg);
18864 subseg_set (pdr_seg, 0);
18866 /* Write the symbol. */
18867 exp.X_op = O_symbol;
18868 exp.X_add_symbol = p;
18869 exp.X_add_number = 0;
18870 emit_expr (&exp, 4);
18872 fragp = frag_more (7 * 4);
18874 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18875 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18876 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18877 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18878 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18879 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18880 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18882 subseg_set (saved_seg, saved_subseg);
18884 #endif /* OBJ_ELF */
18886 cur_proc_ptr = NULL;
18889 /* The .aent and .ent directives. */
18892 s_mips_ent (int aent)
18896 symbolP = get_symbol ();
18897 if (*input_line_pointer == ',')
18898 ++input_line_pointer;
18899 SKIP_WHITESPACE ();
18900 if (ISDIGIT (*input_line_pointer)
18901 || *input_line_pointer == '-')
18904 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18905 as_warn (_(".ent or .aent not in text section."));
18907 if (!aent && cur_proc_ptr)
18908 as_warn (_("missing .end"));
18912 /* This function needs its own .frame and .cprestore directives. */
18913 mips_frame_reg_valid = 0;
18914 mips_cprestore_valid = 0;
18916 cur_proc_ptr = &cur_proc;
18917 memset (cur_proc_ptr, '\0', sizeof (procS));
18919 cur_proc_ptr->func_sym = symbolP;
18923 if (debug_type == DEBUG_STABS)
18924 stabs_generate_asm_func (S_GET_NAME (symbolP),
18925 S_GET_NAME (symbolP));
18928 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18930 demand_empty_rest_of_line ();
18933 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18934 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18935 s_mips_frame is used so that we can set the PDR information correctly.
18936 We can't use the ecoff routines because they make reference to the ecoff
18937 symbol table (in the mdebug section). */
18940 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18943 if (IS_ELF && !ECOFF_DEBUGGING)
18947 if (cur_proc_ptr == (procS *) NULL)
18949 as_warn (_(".frame outside of .ent"));
18950 demand_empty_rest_of_line ();
18954 cur_proc_ptr->frame_reg = tc_get_register (1);
18956 SKIP_WHITESPACE ();
18957 if (*input_line_pointer++ != ','
18958 || get_absolute_expression_and_terminator (&val) != ',')
18960 as_warn (_("Bad .frame directive"));
18961 --input_line_pointer;
18962 demand_empty_rest_of_line ();
18966 cur_proc_ptr->frame_offset = val;
18967 cur_proc_ptr->pc_reg = tc_get_register (0);
18969 demand_empty_rest_of_line ();
18972 #endif /* OBJ_ELF */
18976 /* The .fmask and .mask directives. If the mdebug section is present
18977 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18978 embedded targets, s_mips_mask is used so that we can set the PDR
18979 information correctly. We can't use the ecoff routines because they
18980 make reference to the ecoff symbol table (in the mdebug section). */
18983 s_mips_mask (int reg_type)
18986 if (IS_ELF && !ECOFF_DEBUGGING)
18990 if (cur_proc_ptr == (procS *) NULL)
18992 as_warn (_(".mask/.fmask outside of .ent"));
18993 demand_empty_rest_of_line ();
18997 if (get_absolute_expression_and_terminator (&mask) != ',')
18999 as_warn (_("Bad .mask/.fmask directive"));
19000 --input_line_pointer;
19001 demand_empty_rest_of_line ();
19005 off = get_absolute_expression ();
19007 if (reg_type == 'F')
19009 cur_proc_ptr->fpreg_mask = mask;
19010 cur_proc_ptr->fpreg_offset = off;
19014 cur_proc_ptr->reg_mask = mask;
19015 cur_proc_ptr->reg_offset = off;
19018 demand_empty_rest_of_line ();
19021 #endif /* OBJ_ELF */
19022 s_ignore (reg_type);
19025 /* A table describing all the processors gas knows about. Names are
19026 matched in the order listed.
19028 To ease comparison, please keep this table in the same order as
19029 gcc's mips_cpu_info_table[]. */
19030 static const struct mips_cpu_info mips_cpu_info_table[] =
19032 /* Entries for generic ISAs */
19033 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
19034 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
19035 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
19036 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
19037 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
19038 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
19039 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
19040 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
19041 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
19044 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
19045 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
19046 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
19049 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19052 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19053 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19054 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19055 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19056 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19057 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19058 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19059 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19060 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19061 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19062 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19063 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19064 /* ST Microelectronics Loongson 2E and 2F cores */
19065 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19066 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19069 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19070 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19071 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19072 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19073 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19074 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19075 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19076 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19077 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19078 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19079 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19080 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19081 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19082 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19083 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19086 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19087 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19088 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19089 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19091 /* MIPS 32 Release 2 */
19092 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19093 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19094 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19095 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19096 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19097 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19098 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19099 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19100 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19101 ISA_MIPS32R2, CPU_MIPS32R2 },
19102 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19103 ISA_MIPS32R2, CPU_MIPS32R2 },
19104 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19105 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19106 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19107 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19108 /* Deprecated forms of the above. */
19109 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19110 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19111 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19112 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19113 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19114 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19115 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19116 /* Deprecated forms of the above. */
19117 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19118 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19119 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19120 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19121 ISA_MIPS32R2, CPU_MIPS32R2 },
19122 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19123 ISA_MIPS32R2, CPU_MIPS32R2 },
19124 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19125 ISA_MIPS32R2, CPU_MIPS32R2 },
19126 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19127 ISA_MIPS32R2, CPU_MIPS32R2 },
19128 /* Deprecated forms of the above. */
19129 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19130 ISA_MIPS32R2, CPU_MIPS32R2 },
19131 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19132 ISA_MIPS32R2, CPU_MIPS32R2 },
19133 /* 34Kn is a 34kc without DSP. */
19134 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19135 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19136 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19137 ISA_MIPS32R2, CPU_MIPS32R2 },
19138 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19139 ISA_MIPS32R2, CPU_MIPS32R2 },
19140 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19141 ISA_MIPS32R2, CPU_MIPS32R2 },
19142 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19143 ISA_MIPS32R2, CPU_MIPS32R2 },
19144 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19145 ISA_MIPS32R2, CPU_MIPS32R2 },
19146 /* Deprecated forms of the above. */
19147 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19148 ISA_MIPS32R2, CPU_MIPS32R2 },
19149 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19150 ISA_MIPS32R2, CPU_MIPS32R2 },
19151 /* 1004K cores are multiprocessor versions of the 34K. */
19152 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19153 ISA_MIPS32R2, CPU_MIPS32R2 },
19154 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19155 ISA_MIPS32R2, CPU_MIPS32R2 },
19156 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19157 ISA_MIPS32R2, CPU_MIPS32R2 },
19158 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19159 ISA_MIPS32R2, CPU_MIPS32R2 },
19162 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19163 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19164 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19165 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19167 /* Broadcom SB-1 CPU core */
19168 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19169 ISA_MIPS64, CPU_SB1 },
19170 /* Broadcom SB-1A CPU core */
19171 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19172 ISA_MIPS64, CPU_SB1 },
19174 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19176 /* MIPS 64 Release 2 */
19178 /* Cavium Networks Octeon CPU core */
19179 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19180 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19181 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19184 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19187 XLP is mostly like XLR, with the prominent exception that it is
19188 MIPS64R2 rather than MIPS64. */
19189 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19196 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19197 with a final "000" replaced by "k". Ignore case.
19199 Note: this function is shared between GCC and GAS. */
19202 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19204 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19205 given++, canonical++;
19207 return ((*given == 0 && *canonical == 0)
19208 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19212 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19213 CPU name. We've traditionally allowed a lot of variation here.
19215 Note: this function is shared between GCC and GAS. */
19218 mips_matching_cpu_name_p (const char *canonical, const char *given)
19220 /* First see if the name matches exactly, or with a final "000"
19221 turned into "k". */
19222 if (mips_strict_matching_cpu_name_p (canonical, given))
19225 /* If not, try comparing based on numerical designation alone.
19226 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19227 if (TOLOWER (*given) == 'r')
19229 if (!ISDIGIT (*given))
19232 /* Skip over some well-known prefixes in the canonical name,
19233 hoping to find a number there too. */
19234 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19236 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19238 else if (TOLOWER (canonical[0]) == 'r')
19241 return mips_strict_matching_cpu_name_p (canonical, given);
19245 /* Parse an option that takes the name of a processor as its argument.
19246 OPTION is the name of the option and CPU_STRING is the argument.
19247 Return the corresponding processor enumeration if the CPU_STRING is
19248 recognized, otherwise report an error and return null.
19250 A similar function exists in GCC. */
19252 static const struct mips_cpu_info *
19253 mips_parse_cpu (const char *option, const char *cpu_string)
19255 const struct mips_cpu_info *p;
19257 /* 'from-abi' selects the most compatible architecture for the given
19258 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19259 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19260 version. Look first at the -mgp options, if given, otherwise base
19261 the choice on MIPS_DEFAULT_64BIT.
19263 Treat NO_ABI like the EABIs. One reason to do this is that the
19264 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19265 architecture. This code picks MIPS I for 'mips' and MIPS III for
19266 'mips64', just as we did in the days before 'from-abi'. */
19267 if (strcasecmp (cpu_string, "from-abi") == 0)
19269 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19270 return mips_cpu_info_from_isa (ISA_MIPS1);
19272 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19273 return mips_cpu_info_from_isa (ISA_MIPS3);
19275 if (file_mips_gp32 >= 0)
19276 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19278 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19283 /* 'default' has traditionally been a no-op. Probably not very useful. */
19284 if (strcasecmp (cpu_string, "default") == 0)
19287 for (p = mips_cpu_info_table; p->name != 0; p++)
19288 if (mips_matching_cpu_name_p (p->name, cpu_string))
19291 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19295 /* Return the canonical processor information for ISA (a member of the
19296 ISA_MIPS* enumeration). */
19298 static const struct mips_cpu_info *
19299 mips_cpu_info_from_isa (int isa)
19303 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19304 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19305 && isa == mips_cpu_info_table[i].isa)
19306 return (&mips_cpu_info_table[i]);
19311 static const struct mips_cpu_info *
19312 mips_cpu_info_from_arch (int arch)
19316 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19317 if (arch == mips_cpu_info_table[i].cpu)
19318 return (&mips_cpu_info_table[i]);
19324 show (FILE *stream, const char *string, int *col_p, int *first_p)
19328 fprintf (stream, "%24s", "");
19333 fprintf (stream, ", ");
19337 if (*col_p + strlen (string) > 72)
19339 fprintf (stream, "\n%24s", "");
19343 fprintf (stream, "%s", string);
19344 *col_p += strlen (string);
19350 md_show_usage (FILE *stream)
19355 fprintf (stream, _("\
19357 -EB generate big endian output\n\
19358 -EL generate little endian output\n\
19359 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19360 -G NUM allow referencing objects up to NUM bytes\n\
19361 implicitly with the gp register [default 8]\n"));
19362 fprintf (stream, _("\
19363 -mips1 generate MIPS ISA I instructions\n\
19364 -mips2 generate MIPS ISA II instructions\n\
19365 -mips3 generate MIPS ISA III instructions\n\
19366 -mips4 generate MIPS ISA IV instructions\n\
19367 -mips5 generate MIPS ISA V instructions\n\
19368 -mips32 generate MIPS32 ISA instructions\n\
19369 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19370 -mips64 generate MIPS64 ISA instructions\n\
19371 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19372 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19376 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19377 show (stream, mips_cpu_info_table[i].name, &column, &first);
19378 show (stream, "from-abi", &column, &first);
19379 fputc ('\n', stream);
19381 fprintf (stream, _("\
19382 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19383 -no-mCPU don't generate code specific to CPU.\n\
19384 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19388 show (stream, "3900", &column, &first);
19389 show (stream, "4010", &column, &first);
19390 show (stream, "4100", &column, &first);
19391 show (stream, "4650", &column, &first);
19392 fputc ('\n', stream);
19394 fprintf (stream, _("\
19395 -mips16 generate mips16 instructions\n\
19396 -no-mips16 do not generate mips16 instructions\n"));
19397 fprintf (stream, _("\
19398 -mmicromips generate microMIPS instructions\n\
19399 -mno-micromips do not generate microMIPS instructions\n"));
19400 fprintf (stream, _("\
19401 -msmartmips generate smartmips instructions\n\
19402 -mno-smartmips do not generate smartmips instructions\n"));
19403 fprintf (stream, _("\
19404 -mdsp generate DSP instructions\n\
19405 -mno-dsp do not generate DSP instructions\n"));
19406 fprintf (stream, _("\
19407 -mdspr2 generate DSP R2 instructions\n\
19408 -mno-dspr2 do not generate DSP R2 instructions\n"));
19409 fprintf (stream, _("\
19410 -mmt generate MT instructions\n\
19411 -mno-mt do not generate MT instructions\n"));
19412 fprintf (stream, _("\
19413 -mmcu generate MCU instructions\n\
19414 -mno-mcu do not generate MCU instructions\n"));
19415 fprintf (stream, _("\
19416 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19417 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19418 -mfix-vr4120 work around certain VR4120 errata\n\
19419 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19420 -mfix-24k insert a nop after ERET and DERET instructions\n\
19421 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19422 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19423 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19424 -msym32 assume all symbols have 32-bit values\n\
19425 -O0 remove unneeded NOPs, do not swap branches\n\
19426 -O remove unneeded NOPs and swap branches\n\
19427 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19428 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19429 fprintf (stream, _("\
19430 -mhard-float allow floating-point instructions\n\
19431 -msoft-float do not allow floating-point instructions\n\
19432 -msingle-float only allow 32-bit floating-point operations\n\
19433 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19434 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19437 fprintf (stream, _("\
19438 -KPIC, -call_shared generate SVR4 position independent code\n\
19439 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19440 -mvxworks-pic generate VxWorks position independent code\n\
19441 -non_shared do not generate code that can operate with DSOs\n\
19442 -xgot assume a 32 bit GOT\n\
19443 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19444 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19445 position dependent (non shared) code\n\
19446 -mabi=ABI create ABI conformant object file for:\n"));
19450 show (stream, "32", &column, &first);
19451 show (stream, "o64", &column, &first);
19452 show (stream, "n32", &column, &first);
19453 show (stream, "64", &column, &first);
19454 show (stream, "eabi", &column, &first);
19456 fputc ('\n', stream);
19458 fprintf (stream, _("\
19459 -32 create o32 ABI object file (default)\n\
19460 -n32 create n32 ABI object file\n\
19461 -64 create 64 ABI object file\n"));
19467 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19469 if (HAVE_64BIT_SYMBOLS)
19470 return dwarf2_format_64bit_irix;
19472 return dwarf2_format_32bit;
19477 mips_dwarf2_addr_size (void)
19479 if (HAVE_64BIT_OBJECTS)
19485 /* Standard calling conventions leave the CFA at SP on entry. */
19487 mips_cfi_frame_initial_instructions (void)
19489 cfi_add_CFA_def_cfa_register (SP);
19493 tc_mips_regname_to_dw2regnum (char *regname)
19495 unsigned int regnum = -1;
19498 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))