1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p : 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p : 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p : 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p : 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi = NO_ABI;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls = FALSE;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared = TRUE;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32 = -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32 = -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float = 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float = 0;
292 static struct mips_set_options mips_opts =
294 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
297 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
298 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
299 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
302 /* These variables are filled in with the masks of registers used.
303 The object format code reads them and puts them in the appropriate
305 unsigned long mips_gprmask;
306 unsigned long mips_cprmask[4];
308 /* MIPS ISA we are using for this output file. */
309 static int file_mips_isa = ISA_UNKNOWN;
311 /* True if any MIPS16 code was produced. */
312 static int file_ase_mips16;
314 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
315 || mips_opts.isa == ISA_MIPS32R2 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2)
319 /* True if any microMIPS code was produced. */
320 static int file_ase_micromips;
322 /* True if we want to create R_MIPS_JALR for jalr $25. */
324 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
326 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
327 because there's no place for any addend, the only acceptable
328 expression is a bare symbol. */
329 #define MIPS_JALR_HINT_P(EXPR) \
330 (!HAVE_IN_PLACE_ADDENDS \
331 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
334 /* True if -mips3d was passed or implied by arguments passed on the
335 command line (e.g., by -march). */
336 static int file_ase_mips3d;
338 /* True if -mdmx was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_mdmx;
342 /* True if -msmartmips was passed or implied by arguments passed on the
343 command line (e.g., by -march). */
344 static int file_ase_smartmips;
346 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
347 || mips_opts.isa == ISA_MIPS32R2)
349 /* True if -mdsp was passed or implied by arguments passed on the
350 command line (e.g., by -march). */
351 static int file_ase_dsp;
353 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
354 || mips_opts.isa == ISA_MIPS64R2)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2)
365 /* True if -mmt was passed or implied by arguments passed on the
366 command line (e.g., by -march). */
367 static int file_ase_mt;
369 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2)
372 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
373 || mips_opts.isa == ISA_MIPS64R2)
375 /* The argument of the -march= flag. The architecture we are assembling. */
376 static int file_mips_arch = CPU_UNKNOWN;
377 static const char *mips_arch_string;
379 /* The argument of the -mtune= flag. The architecture for which we
381 static int mips_tune = CPU_UNKNOWN;
382 static const char *mips_tune_string;
384 /* True when generating 32-bit code for a 64-bit processor. */
385 static int mips_32bitmode = 0;
387 /* True if the given ABI requires 32-bit registers. */
388 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
390 /* Likewise 64-bit registers. */
391 #define ABI_NEEDS_64BIT_REGS(ABI) \
393 || (ABI) == N64_ABI \
396 /* Return true if ISA supports 64 bit wide gp registers. */
397 #define ISA_HAS_64BIT_REGS(ISA) \
398 ((ISA) == ISA_MIPS3 \
399 || (ISA) == ISA_MIPS4 \
400 || (ISA) == ISA_MIPS5 \
401 || (ISA) == ISA_MIPS64 \
402 || (ISA) == ISA_MIPS64R2)
404 /* Return true if ISA supports 64 bit wide float registers. */
405 #define ISA_HAS_64BIT_FPRS(ISA) \
406 ((ISA) == ISA_MIPS3 \
407 || (ISA) == ISA_MIPS4 \
408 || (ISA) == ISA_MIPS5 \
409 || (ISA) == ISA_MIPS32R2 \
410 || (ISA) == ISA_MIPS64 \
411 || (ISA) == ISA_MIPS64R2)
413 /* Return true if ISA supports 64-bit right rotate (dror et al.)
415 #define ISA_HAS_DROR(ISA) \
416 ((ISA) == ISA_MIPS64R2 \
417 || (mips_opts.micromips \
418 && ISA_HAS_64BIT_REGS (ISA)) \
421 /* Return true if ISA supports 32-bit right rotate (ror et al.)
423 #define ISA_HAS_ROR(ISA) \
424 ((ISA) == ISA_MIPS32R2 \
425 || (ISA) == ISA_MIPS64R2 \
426 || mips_opts.ase_smartmips \
427 || mips_opts.micromips \
430 /* Return true if ISA supports single-precision floats in odd registers. */
431 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
432 ((ISA) == ISA_MIPS32 \
433 || (ISA) == ISA_MIPS32R2 \
434 || (ISA) == ISA_MIPS64 \
435 || (ISA) == ISA_MIPS64R2)
437 /* Return true if ISA supports move to/from high part of a 64-bit
438 floating-point register. */
439 #define ISA_HAS_MXHC1(ISA) \
440 ((ISA) == ISA_MIPS32R2 \
441 || (ISA) == ISA_MIPS64R2)
443 #define HAVE_32BIT_GPRS \
444 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
446 #define HAVE_32BIT_FPRS \
447 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
449 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
450 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
452 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
454 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
456 /* True if relocations are stored in-place. */
457 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
459 /* The ABI-derived address size. */
460 #define HAVE_64BIT_ADDRESSES \
461 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
462 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
464 /* The size of symbolic constants (i.e., expressions of the form
465 "SYMBOL" or "SYMBOL + OFFSET"). */
466 #define HAVE_32BIT_SYMBOLS \
467 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
468 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
470 /* Addresses are loaded in different ways, depending on the address size
471 in use. The n32 ABI Documentation also mandates the use of additions
472 with overflow checking, but existing implementations don't follow it. */
473 #define ADDRESS_ADD_INSN \
474 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
476 #define ADDRESS_ADDI_INSN \
477 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
479 #define ADDRESS_LOAD_INSN \
480 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
482 #define ADDRESS_STORE_INSN \
483 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
485 /* Return true if the given CPU supports the MIPS16 ASE. */
486 #define CPU_HAS_MIPS16(cpu) \
487 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
488 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
490 /* Return true if the given CPU supports the microMIPS ASE. */
491 #define CPU_HAS_MICROMIPS(cpu) 0
493 /* True if CPU has a dror instruction. */
494 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
496 /* True if CPU has a ror instruction. */
497 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
499 /* True if CPU has seq/sne and seqi/snei instructions. */
500 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
502 /* True if CPU does not implement the all the coprocessor insns. For these
503 CPUs only those COP insns are accepted that are explicitly marked to be
504 available on the CPU. ISA membership for COP insns is ignored. */
505 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
507 /* True if mflo and mfhi can be immediately followed by instructions
508 which write to the HI and LO registers.
510 According to MIPS specifications, MIPS ISAs I, II, and III need
511 (at least) two instructions between the reads of HI/LO and
512 instructions which write them, and later ISAs do not. Contradicting
513 the MIPS specifications, some MIPS IV processor user manuals (e.g.
514 the UM for the NEC Vr5000) document needing the instructions between
515 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
516 MIPS64 and later ISAs to have the interlocks, plus any specific
517 earlier-ISA CPUs for which CPU documentation declares that the
518 instructions are really interlocked. */
519 #define hilo_interlocks \
520 (mips_opts.isa == ISA_MIPS32 \
521 || mips_opts.isa == ISA_MIPS32R2 \
522 || mips_opts.isa == ISA_MIPS64 \
523 || mips_opts.isa == ISA_MIPS64R2 \
524 || mips_opts.arch == CPU_R4010 \
525 || mips_opts.arch == CPU_R10000 \
526 || mips_opts.arch == CPU_R12000 \
527 || mips_opts.arch == CPU_R14000 \
528 || mips_opts.arch == CPU_R16000 \
529 || mips_opts.arch == CPU_RM7000 \
530 || mips_opts.arch == CPU_VR5500 \
531 || mips_opts.micromips \
534 /* Whether the processor uses hardware interlocks to protect reads
535 from the GPRs after they are loaded from memory, and thus does not
536 require nops to be inserted. This applies to instructions marked
537 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
538 level I and microMIPS mode instructions are always interlocked. */
539 #define gpr_interlocks \
540 (mips_opts.isa != ISA_MIPS1 \
541 || mips_opts.arch == CPU_R3900 \
542 || mips_opts.micromips \
545 /* Whether the processor uses hardware interlocks to avoid delays
546 required by coprocessor instructions, and thus does not require
547 nops to be inserted. This applies to instructions marked
548 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
549 between instructions marked INSN_WRITE_COND_CODE and ones marked
550 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
551 levels I, II, and III and microMIPS mode instructions are always
553 /* Itbl support may require additional care here. */
554 #define cop_interlocks \
555 ((mips_opts.isa != ISA_MIPS1 \
556 && mips_opts.isa != ISA_MIPS2 \
557 && mips_opts.isa != ISA_MIPS3) \
558 || mips_opts.arch == CPU_R4300 \
559 || mips_opts.micromips \
562 /* Whether the processor uses hardware interlocks to protect reads
563 from coprocessor registers after they are loaded from memory, and
564 thus does not require nops to be inserted. This applies to
565 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
566 requires at MIPS ISA level I and microMIPS mode instructions are
567 always interlocked. */
568 #define cop_mem_interlocks \
569 (mips_opts.isa != ISA_MIPS1 \
570 || mips_opts.micromips \
573 /* Is this a mfhi or mflo instruction? */
574 #define MF_HILO_INSN(PINFO) \
575 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
577 /* Returns true for a (non floating-point) coprocessor instruction. Reading
578 or writing the condition code is only possible on the coprocessors and
579 these insns are not marked with INSN_COP. Thus for these insns use the
580 condition-code flags. */
581 #define COP_INSN(PINFO) \
582 (PINFO != INSN_MACRO \
583 && ((PINFO) & (FP_S | FP_D)) == 0 \
584 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
586 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
587 has been selected. This implies, in particular, that addresses of text
588 labels have their LSB set. */
589 #define HAVE_CODE_COMPRESSION \
590 ((mips_opts.mips16 | mips_opts.micromips) != 0)
592 /* MIPS PIC level. */
594 enum mips_pic_level mips_pic;
596 /* 1 if we should generate 32 bit offsets from the $gp register in
597 SVR4_PIC mode. Currently has no meaning in other modes. */
598 static int mips_big_got = 0;
600 /* 1 if trap instructions should used for overflow rather than break
602 static int mips_trap = 0;
604 /* 1 if double width floating point constants should not be constructed
605 by assembling two single width halves into two single width floating
606 point registers which just happen to alias the double width destination
607 register. On some architectures this aliasing can be disabled by a bit
608 in the status register, and the setting of this bit cannot be determined
609 automatically at assemble time. */
610 static int mips_disable_float_construction;
612 /* Non-zero if any .set noreorder directives were used. */
614 static int mips_any_noreorder;
616 /* Non-zero if nops should be inserted when the register referenced in
617 an mfhi/mflo instruction is read in the next two instructions. */
618 static int mips_7000_hilo_fix;
620 /* The size of objects in the small data section. */
621 static unsigned int g_switch_value = 8;
622 /* Whether the -G option was used. */
623 static int g_switch_seen = 0;
628 /* If we can determine in advance that GP optimization won't be
629 possible, we can skip the relaxation stuff that tries to produce
630 GP-relative references. This makes delay slot optimization work
633 This function can only provide a guess, but it seems to work for
634 gcc output. It needs to guess right for gcc, otherwise gcc
635 will put what it thinks is a GP-relative instruction in a branch
638 I don't know if a fix is needed for the SVR4_PIC mode. I've only
639 fixed it for the non-PIC mode. KR 95/04/07 */
640 static int nopic_need_relax (symbolS *, int);
642 /* handle of the OPCODE hash table */
643 static struct hash_control *op_hash = NULL;
645 /* The opcode hash table we use for the mips16. */
646 static struct hash_control *mips16_op_hash = NULL;
648 /* The opcode hash table we use for the microMIPS ASE. */
649 static struct hash_control *micromips_op_hash = NULL;
651 /* This array holds the chars that always start a comment. If the
652 pre-processor is disabled, these aren't very useful */
653 const char comment_chars[] = "#";
655 /* This array holds the chars that only start a comment at the beginning of
656 a line. If the line seems to have the form '# 123 filename'
657 .line and .file directives will appear in the pre-processed output */
658 /* Note that input_file.c hand checks for '#' at the beginning of the
659 first line of the input file. This is because the compiler outputs
660 #NO_APP at the beginning of its output. */
661 /* Also note that C style comments are always supported. */
662 const char line_comment_chars[] = "#";
664 /* This array holds machine specific line separator characters. */
665 const char line_separator_chars[] = ";";
667 /* Chars that can be used to separate mant from exp in floating point nums */
668 const char EXP_CHARS[] = "eE";
670 /* Chars that mean this number is a floating point constant */
673 const char FLT_CHARS[] = "rRsSfFdDxXpP";
675 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
676 changed in read.c . Ideally it shouldn't have to know about it at all,
677 but nothing is ideal around here.
680 static char *insn_error;
682 static int auto_align = 1;
684 /* When outputting SVR4 PIC code, the assembler needs to know the
685 offset in the stack frame from which to restore the $gp register.
686 This is set by the .cprestore pseudo-op, and saved in this
688 static offsetT mips_cprestore_offset = -1;
690 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
691 more optimizations, it can use a register value instead of a memory-saved
692 offset and even an other register than $gp as global pointer. */
693 static offsetT mips_cpreturn_offset = -1;
694 static int mips_cpreturn_register = -1;
695 static int mips_gp_register = GP;
696 static int mips_gprel_offset = 0;
698 /* Whether mips_cprestore_offset has been set in the current function
699 (or whether it has already been warned about, if not). */
700 static int mips_cprestore_valid = 0;
702 /* This is the register which holds the stack frame, as set by the
703 .frame pseudo-op. This is needed to implement .cprestore. */
704 static int mips_frame_reg = SP;
706 /* Whether mips_frame_reg has been set in the current function
707 (or whether it has already been warned about, if not). */
708 static int mips_frame_reg_valid = 0;
710 /* To output NOP instructions correctly, we need to keep information
711 about the previous two instructions. */
713 /* Whether we are optimizing. The default value of 2 means to remove
714 unneeded NOPs and swap branch instructions when possible. A value
715 of 1 means to not swap branches. A value of 0 means to always
717 static int mips_optimize = 2;
719 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
720 equivalent to seeing no -g option at all. */
721 static int mips_debug = 0;
723 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
724 #define MAX_VR4130_NOPS 4
726 /* The maximum number of NOPs needed to fill delay slots. */
727 #define MAX_DELAY_NOPS 2
729 /* The maximum number of NOPs needed for any purpose. */
732 /* A list of previous instructions, with index 0 being the most recent.
733 We need to look back MAX_NOPS instructions when filling delay slots
734 or working around processor errata. We need to look back one
735 instruction further if we're thinking about using history[0] to
736 fill a branch delay slot. */
737 static struct mips_cl_insn history[1 + MAX_NOPS];
739 /* Nop instructions used by emit_nop. */
740 static struct mips_cl_insn nop_insn;
741 static struct mips_cl_insn mips16_nop_insn;
742 static struct mips_cl_insn micromips_nop16_insn;
743 static struct mips_cl_insn micromips_nop32_insn;
745 /* The appropriate nop for the current mode. */
746 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
747 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
749 /* The size of NOP_INSN in bytes. */
750 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
752 /* If this is set, it points to a frag holding nop instructions which
753 were inserted before the start of a noreorder section. If those
754 nops turn out to be unnecessary, the size of the frag can be
756 static fragS *prev_nop_frag;
758 /* The number of nop instructions we created in prev_nop_frag. */
759 static int prev_nop_frag_holds;
761 /* The number of nop instructions that we know we need in
763 static int prev_nop_frag_required;
765 /* The number of instructions we've seen since prev_nop_frag. */
766 static int prev_nop_frag_since;
768 /* For ECOFF and ELF, relocations against symbols are done in two
769 parts, with a HI relocation and a LO relocation. Each relocation
770 has only 16 bits of space to store an addend. This means that in
771 order for the linker to handle carries correctly, it must be able
772 to locate both the HI and the LO relocation. This means that the
773 relocations must appear in order in the relocation table.
775 In order to implement this, we keep track of each unmatched HI
776 relocation. We then sort them so that they immediately precede the
777 corresponding LO relocation. */
782 struct mips_hi_fixup *next;
785 /* The section this fixup is in. */
789 /* The list of unmatched HI relocs. */
791 static struct mips_hi_fixup *mips_hi_fixup_list;
793 /* The frag containing the last explicit relocation operator.
794 Null if explicit relocations have not been used. */
796 static fragS *prev_reloc_op_frag;
798 /* Map normal MIPS register numbers to mips16 register numbers. */
800 #define X ILLEGAL_REG
801 static const int mips32_to_16_reg_map[] =
803 X, X, 2, 3, 4, 5, 6, 7,
804 X, X, X, X, X, X, X, X,
805 0, 1, X, X, X, X, X, X,
806 X, X, X, X, X, X, X, X
810 /* Map mips16 register numbers to normal MIPS register numbers. */
812 static const unsigned int mips16_to_32_reg_map[] =
814 16, 17, 2, 3, 4, 5, 6, 7
817 /* Map normal MIPS register numbers to microMIPS register numbers. */
819 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
822 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
823 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
824 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
825 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
827 #define X ILLEGAL_REG
828 /* reg type h: 4, 5, 6. */
829 static const int mips32_to_micromips_reg_h_map[] =
831 X, X, X, X, 4, 5, 6, X,
832 X, X, X, X, X, X, X, X,
833 X, X, X, X, X, X, X, X,
834 X, X, X, X, X, X, X, X
837 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
838 static const int mips32_to_micromips_reg_m_map[] =
840 0, X, 2, 3, X, X, X, X,
841 X, X, X, X, X, X, X, X,
842 4, 1, 5, 6, 7, X, X, X,
843 X, X, X, X, X, X, X, X
846 /* reg type q: 0, 2-7. 17. */
847 static const int mips32_to_micromips_reg_q_map[] =
849 0, X, 2, 3, 4, 5, 6, 7,
850 X, X, X, X, X, X, X, X,
851 X, 1, X, X, X, X, X, X,
852 X, X, X, X, X, X, X, X
855 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
858 /* Map microMIPS register numbers to normal MIPS register numbers. */
860 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
862 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
863 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
864 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
865 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
867 /* The microMIPS registers with type h. */
868 static const unsigned int micromips_to_32_reg_h_map[] =
870 5, 5, 6, 4, 4, 4, 4, 4
873 /* The microMIPS registers with type i. */
874 static const unsigned int micromips_to_32_reg_i_map[] =
876 6, 7, 7, 21, 22, 5, 6, 7
879 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
881 /* The microMIPS registers with type m. */
882 static const unsigned int micromips_to_32_reg_m_map[] =
884 0, 17, 2, 3, 16, 18, 19, 20
887 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
889 /* The microMIPS registers with type q. */
890 static const unsigned int micromips_to_32_reg_q_map[] =
892 0, 17, 2, 3, 4, 5, 6, 7
895 /* microMIPS imm type B. */
896 static const int micromips_imm_b_map[] =
898 1, 4, 8, 12, 16, 20, 24, -1
901 /* microMIPS imm type C. */
902 static const int micromips_imm_c_map[] =
904 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
907 /* Classifies the kind of instructions we're interested in when
908 implementing -mfix-vr4120. */
909 enum fix_vr4120_class
917 NUM_FIX_VR4120_CLASSES
920 /* ...likewise -mfix-loongson2f-jump. */
921 static bfd_boolean mips_fix_loongson2f_jump;
923 /* ...likewise -mfix-loongson2f-nop. */
924 static bfd_boolean mips_fix_loongson2f_nop;
926 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
927 static bfd_boolean mips_fix_loongson2f;
929 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
930 there must be at least one other instruction between an instruction
931 of type X and an instruction of type Y. */
932 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
934 /* True if -mfix-vr4120 is in force. */
935 static int mips_fix_vr4120;
937 /* ...likewise -mfix-vr4130. */
938 static int mips_fix_vr4130;
940 /* ...likewise -mfix-24k. */
941 static int mips_fix_24k;
943 /* ...likewise -mfix-cn63xxp1 */
944 static bfd_boolean mips_fix_cn63xxp1;
946 /* We don't relax branches by default, since this causes us to expand
947 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
948 fail to compute the offset before expanding the macro to the most
949 efficient expansion. */
951 static int mips_relax_branch;
953 /* The expansion of many macros depends on the type of symbol that
954 they refer to. For example, when generating position-dependent code,
955 a macro that refers to a symbol may have two different expansions,
956 one which uses GP-relative addresses and one which uses absolute
957 addresses. When generating SVR4-style PIC, a macro may have
958 different expansions for local and global symbols.
960 We handle these situations by generating both sequences and putting
961 them in variant frags. In position-dependent code, the first sequence
962 will be the GP-relative one and the second sequence will be the
963 absolute one. In SVR4 PIC, the first sequence will be for global
964 symbols and the second will be for local symbols.
966 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
967 SECOND are the lengths of the two sequences in bytes. These fields
968 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
969 the subtype has the following flags:
972 Set if it has been decided that we should use the second
973 sequence instead of the first.
976 Set in the first variant frag if the macro's second implementation
977 is longer than its first. This refers to the macro as a whole,
978 not an individual relaxation.
981 Set in the first variant frag if the macro appeared in a .set nomacro
982 block and if one alternative requires a warning but the other does not.
985 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
988 RELAX_DELAY_SLOT_16BIT
989 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
992 RELAX_DELAY_SLOT_SIZE_FIRST
993 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
994 the macro is of the wrong size for the branch delay slot.
996 RELAX_DELAY_SLOT_SIZE_SECOND
997 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
998 the macro is of the wrong size for the branch delay slot.
1000 The frag's "opcode" points to the first fixup for relaxable code.
1002 Relaxable macros are generated using a sequence such as:
1004 relax_start (SYMBOL);
1005 ... generate first expansion ...
1007 ... generate second expansion ...
1010 The code and fixups for the unwanted alternative are discarded
1011 by md_convert_frag. */
1012 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1014 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1015 #define RELAX_SECOND(X) ((X) & 0xff)
1016 #define RELAX_USE_SECOND 0x10000
1017 #define RELAX_SECOND_LONGER 0x20000
1018 #define RELAX_NOMACRO 0x40000
1019 #define RELAX_DELAY_SLOT 0x80000
1020 #define RELAX_DELAY_SLOT_16BIT 0x100000
1021 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1022 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1024 /* Branch without likely bit. If label is out of range, we turn:
1026 beq reg1, reg2, label
1036 with the following opcode replacements:
1043 bltzal <-> bgezal (with jal label instead of j label)
1045 Even though keeping the delay slot instruction in the delay slot of
1046 the branch would be more efficient, it would be very tricky to do
1047 correctly, because we'd have to introduce a variable frag *after*
1048 the delay slot instruction, and expand that instead. Let's do it
1049 the easy way for now, even if the branch-not-taken case now costs
1050 one additional instruction. Out-of-range branches are not supposed
1051 to be common, anyway.
1053 Branch likely. If label is out of range, we turn:
1055 beql reg1, reg2, label
1056 delay slot (annulled if branch not taken)
1065 delay slot (executed only if branch taken)
1068 It would be possible to generate a shorter sequence by losing the
1069 likely bit, generating something like:
1074 delay slot (executed only if branch taken)
1086 bltzall -> bgezal (with jal label instead of j label)
1087 bgezall -> bltzal (ditto)
1090 but it's not clear that it would actually improve performance. */
1091 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1092 ((relax_substateT) \
1095 | ((toofar) ? 0x20 : 0) \
1096 | ((link) ? 0x40 : 0) \
1097 | ((likely) ? 0x80 : 0) \
1098 | ((uncond) ? 0x100 : 0)))
1099 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1100 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1101 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1102 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1103 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1104 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1106 /* For mips16 code, we use an entirely different form of relaxation.
1107 mips16 supports two versions of most instructions which take
1108 immediate values: a small one which takes some small value, and a
1109 larger one which takes a 16 bit value. Since branches also follow
1110 this pattern, relaxing these values is required.
1112 We can assemble both mips16 and normal MIPS code in a single
1113 object. Therefore, we need to support this type of relaxation at
1114 the same time that we support the relaxation described above. We
1115 use the high bit of the subtype field to distinguish these cases.
1117 The information we store for this type of relaxation is the
1118 argument code found in the opcode file for this relocation, whether
1119 the user explicitly requested a small or extended form, and whether
1120 the relocation is in a jump or jal delay slot. That tells us the
1121 size of the value, and how it should be stored. We also store
1122 whether the fragment is considered to be extended or not. We also
1123 store whether this is known to be a branch to a different section,
1124 whether we have tried to relax this frag yet, and whether we have
1125 ever extended a PC relative fragment because of a shift count. */
1126 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1129 | ((small) ? 0x100 : 0) \
1130 | ((ext) ? 0x200 : 0) \
1131 | ((dslot) ? 0x400 : 0) \
1132 | ((jal_dslot) ? 0x800 : 0))
1133 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1134 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1135 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1136 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1137 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1138 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1139 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1140 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1141 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1142 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1143 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1144 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1146 /* For microMIPS code, we use relaxation similar to one we use for
1147 MIPS16 code. Some instructions that take immediate values support
1148 two encodings: a small one which takes some small value, and a
1149 larger one which takes a 16 bit value. As some branches also follow
1150 this pattern, relaxing these values is required.
1152 We can assemble both microMIPS and normal MIPS code in a single
1153 object. Therefore, we need to support this type of relaxation at
1154 the same time that we support the relaxation described above. We
1155 use one of the high bits of the subtype field to distinguish these
1158 The information we store for this type of relaxation is the argument
1159 code found in the opcode file for this relocation, the register
1160 selected as the assembler temporary, whether the branch is
1161 unconditional, whether it is compact, whether it stores the link
1162 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1163 branches to a sequence of instructions is enabled, and whether the
1164 displacement of a branch is too large to fit as an immediate argument
1165 of a 16-bit and a 32-bit branch, respectively. */
1166 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1167 relax32, toofar16, toofar32) \
1170 | (((at) & 0x1f) << 8) \
1171 | ((uncond) ? 0x2000 : 0) \
1172 | ((compact) ? 0x4000 : 0) \
1173 | ((link) ? 0x8000 : 0) \
1174 | ((relax32) ? 0x10000 : 0) \
1175 | ((toofar16) ? 0x20000 : 0) \
1176 | ((toofar32) ? 0x40000 : 0))
1177 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1178 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1179 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1180 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1181 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1182 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1183 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1185 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1186 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1187 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1188 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1189 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1190 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1192 /* Is the given value a sign-extended 32-bit value? */
1193 #define IS_SEXT_32BIT_NUM(x) \
1194 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1195 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1197 /* Is the given value a sign-extended 16-bit value? */
1198 #define IS_SEXT_16BIT_NUM(x) \
1199 (((x) &~ (offsetT) 0x7fff) == 0 \
1200 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1202 /* Is the given value a sign-extended 12-bit value? */
1203 #define IS_SEXT_12BIT_NUM(x) \
1204 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1206 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1207 #define IS_ZEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0xffffffff) == 0 \
1209 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1211 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1212 VALUE << SHIFT. VALUE is evaluated exactly once. */
1213 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1214 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1215 | (((VALUE) & (MASK)) << (SHIFT)))
1217 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1219 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1220 (((STRUCT) >> (SHIFT)) & (MASK))
1222 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1223 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1225 include/opcode/mips.h specifies operand fields using the macros
1226 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1227 with "MIPS16OP" instead of "OP". */
1228 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1231 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1232 OP_MASK_##FIELD, OP_SH_##FIELD); \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1237 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1238 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1239 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1241 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1242 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1244 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1245 : EXTRACT_BITS ((INSN).insn_opcode, \
1246 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1247 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1248 EXTRACT_BITS ((INSN).insn_opcode, \
1249 MIPS16OP_MASK_##FIELD, \
1250 MIPS16OP_SH_##FIELD)
1252 /* Whether or not we are emitting a branch-likely macro. */
1253 static bfd_boolean emit_branch_likely_macro = FALSE;
1255 /* Global variables used when generating relaxable macros. See the
1256 comment above RELAX_ENCODE for more details about how relaxation
1259 /* 0 if we're not emitting a relaxable macro.
1260 1 if we're emitting the first of the two relaxation alternatives.
1261 2 if we're emitting the second alternative. */
1264 /* The first relaxable fixup in the current frag. (In other words,
1265 the first fixup that refers to relaxable code.) */
1268 /* sizes[0] says how many bytes of the first alternative are stored in
1269 the current frag. Likewise sizes[1] for the second alternative. */
1270 unsigned int sizes[2];
1272 /* The symbol on which the choice of sequence depends. */
1276 /* Global variables used to decide whether a macro needs a warning. */
1278 /* True if the macro is in a branch delay slot. */
1279 bfd_boolean delay_slot_p;
1281 /* Set to the length in bytes required if the macro is in a delay slot
1282 that requires a specific length of instruction, otherwise zero. */
1283 unsigned int delay_slot_length;
1285 /* For relaxable macros, sizes[0] is the length of the first alternative
1286 in bytes and sizes[1] is the length of the second alternative.
1287 For non-relaxable macros, both elements give the length of the
1289 unsigned int sizes[2];
1291 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1292 instruction of the first alternative in bytes and first_insn_sizes[1]
1293 is the length of the first instruction of the second alternative.
1294 For non-relaxable macros, both elements give the length of the first
1295 instruction in bytes.
1297 Set to zero if we haven't yet seen the first instruction. */
1298 unsigned int first_insn_sizes[2];
1300 /* For relaxable macros, insns[0] is the number of instructions for the
1301 first alternative and insns[1] is the number of instructions for the
1304 For non-relaxable macros, both elements give the number of
1305 instructions for the macro. */
1306 unsigned int insns[2];
1308 /* The first variant frag for this macro. */
1310 } mips_macro_warning;
1312 /* Prototypes for static functions. */
1314 #define internalError() \
1315 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1317 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1319 static void append_insn
1320 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1321 bfd_boolean expansionp);
1322 static void mips_no_prev_insn (void);
1323 static void macro_build (expressionS *, const char *, const char *, ...);
1324 static void mips16_macro_build
1325 (expressionS *, const char *, const char *, va_list *);
1326 static void load_register (int, expressionS *, int);
1327 static void macro_start (void);
1328 static void macro_end (void);
1329 static void macro (struct mips_cl_insn * ip);
1330 static void mips16_macro (struct mips_cl_insn * ip);
1331 static void mips_ip (char *str, struct mips_cl_insn * ip);
1332 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1333 static void mips16_immed
1334 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1335 unsigned long *, bfd_boolean *, unsigned short *);
1336 static size_t my_getSmallExpression
1337 (expressionS *, bfd_reloc_code_real_type *, char *);
1338 static void my_getExpression (expressionS *, char *);
1339 static void s_align (int);
1340 static void s_change_sec (int);
1341 static void s_change_section (int);
1342 static void s_cons (int);
1343 static void s_float_cons (int);
1344 static void s_mips_globl (int);
1345 static void s_option (int);
1346 static void s_mipsset (int);
1347 static void s_abicalls (int);
1348 static void s_cpload (int);
1349 static void s_cpsetup (int);
1350 static void s_cplocal (int);
1351 static void s_cprestore (int);
1352 static void s_cpreturn (int);
1353 static void s_dtprelword (int);
1354 static void s_dtpreldword (int);
1355 static void s_gpvalue (int);
1356 static void s_gpword (int);
1357 static void s_gpdword (int);
1358 static void s_cpadd (int);
1359 static void s_insn (int);
1360 static void md_obj_begin (void);
1361 static void md_obj_end (void);
1362 static void s_mips_ent (int);
1363 static void s_mips_end (int);
1364 static void s_mips_frame (int);
1365 static void s_mips_mask (int reg_type);
1366 static void s_mips_stab (int);
1367 static void s_mips_weakext (int);
1368 static void s_mips_file (int);
1369 static void s_mips_loc (int);
1370 static bfd_boolean pic_need_relax (symbolS *, asection *);
1371 static int relaxed_branch_length (fragS *, asection *, int);
1372 static int validate_mips_insn (const struct mips_opcode *);
1373 static int validate_micromips_insn (const struct mips_opcode *);
1374 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1375 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1377 /* Table and functions used to map between CPU/ISA names, and
1378 ISA levels, and CPU numbers. */
1380 struct mips_cpu_info
1382 const char *name; /* CPU or ISA name. */
1383 int flags; /* ASEs available, or ISA flag. */
1384 int isa; /* ISA level. */
1385 int cpu; /* CPU number (default CPU if ISA). */
1388 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1389 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1390 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1391 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1392 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1393 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1394 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1395 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1397 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1398 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1399 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1403 The following pseudo-ops from the Kane and Heinrich MIPS book
1404 should be defined here, but are currently unsupported: .alias,
1405 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1407 The following pseudo-ops from the Kane and Heinrich MIPS book are
1408 specific to the type of debugging information being generated, and
1409 should be defined by the object format: .aent, .begin, .bend,
1410 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1413 The following pseudo-ops from the Kane and Heinrich MIPS book are
1414 not MIPS CPU specific, but are also not specific to the object file
1415 format. This file is probably the best place to define them, but
1416 they are not currently supported: .asm0, .endr, .lab, .struct. */
1418 static const pseudo_typeS mips_pseudo_table[] =
1420 /* MIPS specific pseudo-ops. */
1421 {"option", s_option, 0},
1422 {"set", s_mipsset, 0},
1423 {"rdata", s_change_sec, 'r'},
1424 {"sdata", s_change_sec, 's'},
1425 {"livereg", s_ignore, 0},
1426 {"abicalls", s_abicalls, 0},
1427 {"cpload", s_cpload, 0},
1428 {"cpsetup", s_cpsetup, 0},
1429 {"cplocal", s_cplocal, 0},
1430 {"cprestore", s_cprestore, 0},
1431 {"cpreturn", s_cpreturn, 0},
1432 {"dtprelword", s_dtprelword, 0},
1433 {"dtpreldword", s_dtpreldword, 0},
1434 {"gpvalue", s_gpvalue, 0},
1435 {"gpword", s_gpword, 0},
1436 {"gpdword", s_gpdword, 0},
1437 {"cpadd", s_cpadd, 0},
1438 {"insn", s_insn, 0},
1440 /* Relatively generic pseudo-ops that happen to be used on MIPS
1442 {"asciiz", stringer, 8 + 1},
1443 {"bss", s_change_sec, 'b'},
1445 {"half", s_cons, 1},
1446 {"dword", s_cons, 3},
1447 {"weakext", s_mips_weakext, 0},
1448 {"origin", s_org, 0},
1449 {"repeat", s_rept, 0},
1451 /* For MIPS this is non-standard, but we define it for consistency. */
1452 {"sbss", s_change_sec, 'B'},
1454 /* These pseudo-ops are defined in read.c, but must be overridden
1455 here for one reason or another. */
1456 {"align", s_align, 0},
1457 {"byte", s_cons, 0},
1458 {"data", s_change_sec, 'd'},
1459 {"double", s_float_cons, 'd'},
1460 {"float", s_float_cons, 'f'},
1461 {"globl", s_mips_globl, 0},
1462 {"global", s_mips_globl, 0},
1463 {"hword", s_cons, 1},
1465 {"long", s_cons, 2},
1466 {"octa", s_cons, 4},
1467 {"quad", s_cons, 3},
1468 {"section", s_change_section, 0},
1469 {"short", s_cons, 1},
1470 {"single", s_float_cons, 'f'},
1471 {"stabn", s_mips_stab, 'n'},
1472 {"text", s_change_sec, 't'},
1473 {"word", s_cons, 2},
1475 { "extern", ecoff_directive_extern, 0},
1480 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1482 /* These pseudo-ops should be defined by the object file format.
1483 However, a.out doesn't support them, so we have versions here. */
1484 {"aent", s_mips_ent, 1},
1485 {"bgnb", s_ignore, 0},
1486 {"end", s_mips_end, 0},
1487 {"endb", s_ignore, 0},
1488 {"ent", s_mips_ent, 0},
1489 {"file", s_mips_file, 0},
1490 {"fmask", s_mips_mask, 'F'},
1491 {"frame", s_mips_frame, 0},
1492 {"loc", s_mips_loc, 0},
1493 {"mask", s_mips_mask, 'R'},
1494 {"verstamp", s_ignore, 0},
1498 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1499 purpose of the `.dc.a' internal pseudo-op. */
1502 mips_address_bytes (void)
1504 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1507 extern void pop_insert (const pseudo_typeS *);
1510 mips_pop_insert (void)
1512 pop_insert (mips_pseudo_table);
1513 if (! ECOFF_DEBUGGING)
1514 pop_insert (mips_nonecoff_pseudo_table);
1517 /* Symbols labelling the current insn. */
1519 struct insn_label_list
1521 struct insn_label_list *next;
1525 static struct insn_label_list *free_insn_labels;
1526 #define label_list tc_segment_info_data.labels
1528 static void mips_clear_insn_labels (void);
1529 static void mips_mark_labels (void);
1530 static void mips_compressed_mark_labels (void);
1533 mips_clear_insn_labels (void)
1535 register struct insn_label_list **pl;
1536 segment_info_type *si;
1540 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1543 si = seg_info (now_seg);
1544 *pl = si->label_list;
1545 si->label_list = NULL;
1549 /* Mark instruction labels in MIPS16/microMIPS mode. */
1552 mips_mark_labels (void)
1554 if (HAVE_CODE_COMPRESSION)
1555 mips_compressed_mark_labels ();
1558 static char *expr_end;
1560 /* Expressions which appear in instructions. These are set by
1563 static expressionS imm_expr;
1564 static expressionS imm2_expr;
1565 static expressionS offset_expr;
1567 /* Relocs associated with imm_expr and offset_expr. */
1569 static bfd_reloc_code_real_type imm_reloc[3]
1570 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1571 static bfd_reloc_code_real_type offset_reloc[3]
1572 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1574 /* This is set to the resulting size of the instruction to be produced
1575 by mips16_ip if an explicit extension is used or by mips_ip if an
1576 explicit size is supplied. */
1578 static unsigned int forced_insn_length;
1581 /* The pdr segment for per procedure frame/regmask info. Not used for
1584 static segT pdr_seg;
1587 /* The default target format to use. */
1589 #if defined (TE_FreeBSD)
1590 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1591 #elif defined (TE_TMIPS)
1592 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1594 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1598 mips_target_format (void)
1600 switch (OUTPUT_FLAVOR)
1602 case bfd_target_ecoff_flavour:
1603 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1604 case bfd_target_coff_flavour:
1606 case bfd_target_elf_flavour:
1608 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1609 return (target_big_endian
1610 ? "elf32-bigmips-vxworks"
1611 : "elf32-littlemips-vxworks");
1613 return (target_big_endian
1614 ? (HAVE_64BIT_OBJECTS
1615 ? ELF_TARGET ("elf64-", "big")
1617 ? ELF_TARGET ("elf32-n", "big")
1618 : ELF_TARGET ("elf32-", "big")))
1619 : (HAVE_64BIT_OBJECTS
1620 ? ELF_TARGET ("elf64-", "little")
1622 ? ELF_TARGET ("elf32-n", "little")
1623 : ELF_TARGET ("elf32-", "little"))));
1630 /* Return the length of a microMIPS instruction in bytes. If bits of
1631 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1632 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1633 major opcode) will require further modifications to the opcode
1636 static inline unsigned int
1637 micromips_insn_length (const struct mips_opcode *mo)
1639 return (mo->mask >> 16) == 0 ? 2 : 4;
1642 /* Return the length of instruction INSN. */
1644 static inline unsigned int
1645 insn_length (const struct mips_cl_insn *insn)
1647 if (mips_opts.micromips)
1648 return micromips_insn_length (insn->insn_mo);
1649 else if (mips_opts.mips16)
1650 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1655 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1658 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1663 insn->use_extend = FALSE;
1665 insn->insn_opcode = mo->match;
1668 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1669 insn->fixp[i] = NULL;
1670 insn->fixed_p = (mips_opts.noreorder > 0);
1671 insn->noreorder_p = (mips_opts.noreorder > 0);
1672 insn->mips16_absolute_jump_p = 0;
1673 insn->complete_p = 0;
1676 /* Record the current MIPS16/microMIPS mode in now_seg. */
1679 mips_record_compressed_mode (void)
1681 segment_info_type *si;
1683 si = seg_info (now_seg);
1684 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1685 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1686 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1687 si->tc_segment_info_data.micromips = mips_opts.micromips;
1690 /* Install INSN at the location specified by its "frag" and "where" fields. */
1693 install_insn (const struct mips_cl_insn *insn)
1695 char *f = insn->frag->fr_literal + insn->where;
1696 if (!HAVE_CODE_COMPRESSION)
1697 md_number_to_chars (f, insn->insn_opcode, 4);
1698 else if (mips_opts.micromips)
1700 unsigned int length = insn_length (insn);
1702 md_number_to_chars (f, insn->insn_opcode, 2);
1703 else if (length == 4)
1705 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1707 md_number_to_chars (f, insn->insn_opcode & 0xffff, 2);
1710 as_bad (_("48-bit microMIPS instructions are not supported"));
1712 else if (insn->mips16_absolute_jump_p)
1714 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1715 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1719 if (insn->use_extend)
1721 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1724 md_number_to_chars (f, insn->insn_opcode, 2);
1726 mips_record_compressed_mode ();
1729 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1730 and install the opcode in the new location. */
1733 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1738 insn->where = where;
1739 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1740 if (insn->fixp[i] != NULL)
1742 insn->fixp[i]->fx_frag = frag;
1743 insn->fixp[i]->fx_where = where;
1745 install_insn (insn);
1748 /* Add INSN to the end of the output. */
1751 add_fixed_insn (struct mips_cl_insn *insn)
1753 char *f = frag_more (insn_length (insn));
1754 move_insn (insn, frag_now, f - frag_now->fr_literal);
1757 /* Start a variant frag and move INSN to the start of the variant part,
1758 marking it as fixed. The other arguments are as for frag_var. */
1761 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1762 relax_substateT subtype, symbolS *symbol, offsetT offset)
1764 frag_grow (max_chars);
1765 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1767 frag_var (rs_machine_dependent, max_chars, var,
1768 subtype, symbol, offset, NULL);
1771 /* Insert N copies of INSN into the history buffer, starting at
1772 position FIRST. Neither FIRST nor N need to be clipped. */
1775 insert_into_history (unsigned int first, unsigned int n,
1776 const struct mips_cl_insn *insn)
1778 if (mips_relax.sequence != 2)
1782 for (i = ARRAY_SIZE (history); i-- > first;)
1784 history[i] = history[i - n];
1790 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1791 the idea is to make it obvious at a glance that each errata is
1795 init_vr4120_conflicts (void)
1797 #define CONFLICT(FIRST, SECOND) \
1798 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1800 /* Errata 21 - [D]DIV[U] after [D]MACC */
1801 CONFLICT (MACC, DIV);
1802 CONFLICT (DMACC, DIV);
1804 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1805 CONFLICT (DMULT, DMULT);
1806 CONFLICT (DMULT, DMACC);
1807 CONFLICT (DMACC, DMULT);
1808 CONFLICT (DMACC, DMACC);
1810 /* Errata 24 - MT{LO,HI} after [D]MACC */
1811 CONFLICT (MACC, MTHILO);
1812 CONFLICT (DMACC, MTHILO);
1814 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1815 instruction is executed immediately after a MACC or DMACC
1816 instruction, the result of [either instruction] is incorrect." */
1817 CONFLICT (MACC, MULT);
1818 CONFLICT (MACC, DMULT);
1819 CONFLICT (DMACC, MULT);
1820 CONFLICT (DMACC, DMULT);
1822 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1823 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1824 DDIV or DDIVU instruction, the result of the MACC or
1825 DMACC instruction is incorrect.". */
1826 CONFLICT (DMULT, MACC);
1827 CONFLICT (DMULT, DMACC);
1828 CONFLICT (DIV, MACC);
1829 CONFLICT (DIV, DMACC);
1839 #define RTYPE_MASK 0x1ff00
1840 #define RTYPE_NUM 0x00100
1841 #define RTYPE_FPU 0x00200
1842 #define RTYPE_FCC 0x00400
1843 #define RTYPE_VEC 0x00800
1844 #define RTYPE_GP 0x01000
1845 #define RTYPE_CP0 0x02000
1846 #define RTYPE_PC 0x04000
1847 #define RTYPE_ACC 0x08000
1848 #define RTYPE_CCC 0x10000
1849 #define RNUM_MASK 0x000ff
1850 #define RWARN 0x80000
1852 #define GENERIC_REGISTER_NUMBERS \
1853 {"$0", RTYPE_NUM | 0}, \
1854 {"$1", RTYPE_NUM | 1}, \
1855 {"$2", RTYPE_NUM | 2}, \
1856 {"$3", RTYPE_NUM | 3}, \
1857 {"$4", RTYPE_NUM | 4}, \
1858 {"$5", RTYPE_NUM | 5}, \
1859 {"$6", RTYPE_NUM | 6}, \
1860 {"$7", RTYPE_NUM | 7}, \
1861 {"$8", RTYPE_NUM | 8}, \
1862 {"$9", RTYPE_NUM | 9}, \
1863 {"$10", RTYPE_NUM | 10}, \
1864 {"$11", RTYPE_NUM | 11}, \
1865 {"$12", RTYPE_NUM | 12}, \
1866 {"$13", RTYPE_NUM | 13}, \
1867 {"$14", RTYPE_NUM | 14}, \
1868 {"$15", RTYPE_NUM | 15}, \
1869 {"$16", RTYPE_NUM | 16}, \
1870 {"$17", RTYPE_NUM | 17}, \
1871 {"$18", RTYPE_NUM | 18}, \
1872 {"$19", RTYPE_NUM | 19}, \
1873 {"$20", RTYPE_NUM | 20}, \
1874 {"$21", RTYPE_NUM | 21}, \
1875 {"$22", RTYPE_NUM | 22}, \
1876 {"$23", RTYPE_NUM | 23}, \
1877 {"$24", RTYPE_NUM | 24}, \
1878 {"$25", RTYPE_NUM | 25}, \
1879 {"$26", RTYPE_NUM | 26}, \
1880 {"$27", RTYPE_NUM | 27}, \
1881 {"$28", RTYPE_NUM | 28}, \
1882 {"$29", RTYPE_NUM | 29}, \
1883 {"$30", RTYPE_NUM | 30}, \
1884 {"$31", RTYPE_NUM | 31}
1886 #define FPU_REGISTER_NAMES \
1887 {"$f0", RTYPE_FPU | 0}, \
1888 {"$f1", RTYPE_FPU | 1}, \
1889 {"$f2", RTYPE_FPU | 2}, \
1890 {"$f3", RTYPE_FPU | 3}, \
1891 {"$f4", RTYPE_FPU | 4}, \
1892 {"$f5", RTYPE_FPU | 5}, \
1893 {"$f6", RTYPE_FPU | 6}, \
1894 {"$f7", RTYPE_FPU | 7}, \
1895 {"$f8", RTYPE_FPU | 8}, \
1896 {"$f9", RTYPE_FPU | 9}, \
1897 {"$f10", RTYPE_FPU | 10}, \
1898 {"$f11", RTYPE_FPU | 11}, \
1899 {"$f12", RTYPE_FPU | 12}, \
1900 {"$f13", RTYPE_FPU | 13}, \
1901 {"$f14", RTYPE_FPU | 14}, \
1902 {"$f15", RTYPE_FPU | 15}, \
1903 {"$f16", RTYPE_FPU | 16}, \
1904 {"$f17", RTYPE_FPU | 17}, \
1905 {"$f18", RTYPE_FPU | 18}, \
1906 {"$f19", RTYPE_FPU | 19}, \
1907 {"$f20", RTYPE_FPU | 20}, \
1908 {"$f21", RTYPE_FPU | 21}, \
1909 {"$f22", RTYPE_FPU | 22}, \
1910 {"$f23", RTYPE_FPU | 23}, \
1911 {"$f24", RTYPE_FPU | 24}, \
1912 {"$f25", RTYPE_FPU | 25}, \
1913 {"$f26", RTYPE_FPU | 26}, \
1914 {"$f27", RTYPE_FPU | 27}, \
1915 {"$f28", RTYPE_FPU | 28}, \
1916 {"$f29", RTYPE_FPU | 29}, \
1917 {"$f30", RTYPE_FPU | 30}, \
1918 {"$f31", RTYPE_FPU | 31}
1920 #define FPU_CONDITION_CODE_NAMES \
1921 {"$fcc0", RTYPE_FCC | 0}, \
1922 {"$fcc1", RTYPE_FCC | 1}, \
1923 {"$fcc2", RTYPE_FCC | 2}, \
1924 {"$fcc3", RTYPE_FCC | 3}, \
1925 {"$fcc4", RTYPE_FCC | 4}, \
1926 {"$fcc5", RTYPE_FCC | 5}, \
1927 {"$fcc6", RTYPE_FCC | 6}, \
1928 {"$fcc7", RTYPE_FCC | 7}
1930 #define COPROC_CONDITION_CODE_NAMES \
1931 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1932 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1933 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1934 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1935 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1936 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1937 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1938 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1940 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1941 {"$a4", RTYPE_GP | 8}, \
1942 {"$a5", RTYPE_GP | 9}, \
1943 {"$a6", RTYPE_GP | 10}, \
1944 {"$a7", RTYPE_GP | 11}, \
1945 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1946 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1947 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1948 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1949 {"$t0", RTYPE_GP | 12}, \
1950 {"$t1", RTYPE_GP | 13}, \
1951 {"$t2", RTYPE_GP | 14}, \
1952 {"$t3", RTYPE_GP | 15}
1954 #define O32_SYMBOLIC_REGISTER_NAMES \
1955 {"$t0", RTYPE_GP | 8}, \
1956 {"$t1", RTYPE_GP | 9}, \
1957 {"$t2", RTYPE_GP | 10}, \
1958 {"$t3", RTYPE_GP | 11}, \
1959 {"$t4", RTYPE_GP | 12}, \
1960 {"$t5", RTYPE_GP | 13}, \
1961 {"$t6", RTYPE_GP | 14}, \
1962 {"$t7", RTYPE_GP | 15}, \
1963 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1964 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1965 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1966 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1968 /* Remaining symbolic register names */
1969 #define SYMBOLIC_REGISTER_NAMES \
1970 {"$zero", RTYPE_GP | 0}, \
1971 {"$at", RTYPE_GP | 1}, \
1972 {"$AT", RTYPE_GP | 1}, \
1973 {"$v0", RTYPE_GP | 2}, \
1974 {"$v1", RTYPE_GP | 3}, \
1975 {"$a0", RTYPE_GP | 4}, \
1976 {"$a1", RTYPE_GP | 5}, \
1977 {"$a2", RTYPE_GP | 6}, \
1978 {"$a3", RTYPE_GP | 7}, \
1979 {"$s0", RTYPE_GP | 16}, \
1980 {"$s1", RTYPE_GP | 17}, \
1981 {"$s2", RTYPE_GP | 18}, \
1982 {"$s3", RTYPE_GP | 19}, \
1983 {"$s4", RTYPE_GP | 20}, \
1984 {"$s5", RTYPE_GP | 21}, \
1985 {"$s6", RTYPE_GP | 22}, \
1986 {"$s7", RTYPE_GP | 23}, \
1987 {"$t8", RTYPE_GP | 24}, \
1988 {"$t9", RTYPE_GP | 25}, \
1989 {"$k0", RTYPE_GP | 26}, \
1990 {"$kt0", RTYPE_GP | 26}, \
1991 {"$k1", RTYPE_GP | 27}, \
1992 {"$kt1", RTYPE_GP | 27}, \
1993 {"$gp", RTYPE_GP | 28}, \
1994 {"$sp", RTYPE_GP | 29}, \
1995 {"$s8", RTYPE_GP | 30}, \
1996 {"$fp", RTYPE_GP | 30}, \
1997 {"$ra", RTYPE_GP | 31}
1999 #define MIPS16_SPECIAL_REGISTER_NAMES \
2000 {"$pc", RTYPE_PC | 0}
2002 #define MDMX_VECTOR_REGISTER_NAMES \
2003 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2004 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2005 {"$v2", RTYPE_VEC | 2}, \
2006 {"$v3", RTYPE_VEC | 3}, \
2007 {"$v4", RTYPE_VEC | 4}, \
2008 {"$v5", RTYPE_VEC | 5}, \
2009 {"$v6", RTYPE_VEC | 6}, \
2010 {"$v7", RTYPE_VEC | 7}, \
2011 {"$v8", RTYPE_VEC | 8}, \
2012 {"$v9", RTYPE_VEC | 9}, \
2013 {"$v10", RTYPE_VEC | 10}, \
2014 {"$v11", RTYPE_VEC | 11}, \
2015 {"$v12", RTYPE_VEC | 12}, \
2016 {"$v13", RTYPE_VEC | 13}, \
2017 {"$v14", RTYPE_VEC | 14}, \
2018 {"$v15", RTYPE_VEC | 15}, \
2019 {"$v16", RTYPE_VEC | 16}, \
2020 {"$v17", RTYPE_VEC | 17}, \
2021 {"$v18", RTYPE_VEC | 18}, \
2022 {"$v19", RTYPE_VEC | 19}, \
2023 {"$v20", RTYPE_VEC | 20}, \
2024 {"$v21", RTYPE_VEC | 21}, \
2025 {"$v22", RTYPE_VEC | 22}, \
2026 {"$v23", RTYPE_VEC | 23}, \
2027 {"$v24", RTYPE_VEC | 24}, \
2028 {"$v25", RTYPE_VEC | 25}, \
2029 {"$v26", RTYPE_VEC | 26}, \
2030 {"$v27", RTYPE_VEC | 27}, \
2031 {"$v28", RTYPE_VEC | 28}, \
2032 {"$v29", RTYPE_VEC | 29}, \
2033 {"$v30", RTYPE_VEC | 30}, \
2034 {"$v31", RTYPE_VEC | 31}
2036 #define MIPS_DSP_ACCUMULATOR_NAMES \
2037 {"$ac0", RTYPE_ACC | 0}, \
2038 {"$ac1", RTYPE_ACC | 1}, \
2039 {"$ac2", RTYPE_ACC | 2}, \
2040 {"$ac3", RTYPE_ACC | 3}
2042 static const struct regname reg_names[] = {
2043 GENERIC_REGISTER_NUMBERS,
2045 FPU_CONDITION_CODE_NAMES,
2046 COPROC_CONDITION_CODE_NAMES,
2048 /* The $txx registers depends on the abi,
2049 these will be added later into the symbol table from
2050 one of the tables below once mips_abi is set after
2051 parsing of arguments from the command line. */
2052 SYMBOLIC_REGISTER_NAMES,
2054 MIPS16_SPECIAL_REGISTER_NAMES,
2055 MDMX_VECTOR_REGISTER_NAMES,
2056 MIPS_DSP_ACCUMULATOR_NAMES,
2060 static const struct regname reg_names_o32[] = {
2061 O32_SYMBOLIC_REGISTER_NAMES,
2065 static const struct regname reg_names_n32n64[] = {
2066 N32N64_SYMBOLIC_REGISTER_NAMES,
2070 /* Check if S points at a valid register specifier according to TYPES.
2071 If so, then return 1, advance S to consume the specifier and store
2072 the register's number in REGNOP, otherwise return 0. */
2075 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2082 /* Find end of name. */
2084 if (is_name_beginner (*e))
2086 while (is_part_of_name (*e))
2089 /* Terminate name. */
2093 /* Look for a register symbol. */
2094 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2096 int r = S_GET_VALUE (symbolP);
2098 reg = r & RNUM_MASK;
2099 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2100 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2101 reg = (r & RNUM_MASK) - 2;
2103 /* Else see if this is a register defined in an itbl entry. */
2104 else if ((types & RTYPE_GP) && itbl_have_entries)
2111 if (itbl_get_reg_val (n, &r))
2112 reg = r & RNUM_MASK;
2115 /* Advance to next token if a register was recognised. */
2118 else if (types & RWARN)
2119 as_warn (_("Unrecognized register name `%s'"), *s);
2127 /* Check if S points at a valid register list according to TYPES.
2128 If so, then return 1, advance S to consume the list and store
2129 the registers present on the list as a bitmask of ones in REGLISTP,
2130 otherwise return 0. A valid list comprises a comma-separated
2131 enumeration of valid single registers and/or dash-separated
2132 contiguous register ranges as determined by their numbers.
2134 As a special exception if one of s0-s7 registers is specified as
2135 the range's lower delimiter and s8 (fp) is its upper one, then no
2136 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2137 are selected; they have to be listed separately if needed. */
2140 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2142 unsigned int reglist = 0;
2143 unsigned int lastregno;
2144 bfd_boolean ok = TRUE;
2145 unsigned int regmask;
2146 char *s_endlist = *s;
2150 while (reg_lookup (s, types, ®no))
2156 ok = reg_lookup (s, types, &lastregno);
2157 if (ok && lastregno < regno)
2163 if (lastregno == FP && regno >= S0 && regno <= S7)
2168 regmask = 1 << lastregno;
2169 regmask = (regmask << 1) - 1;
2170 regmask ^= (1 << regno) - 1;
2184 *reglistp = reglist;
2185 return ok && reglist != 0;
2188 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2189 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2192 is_opcode_valid (const struct mips_opcode *mo)
2194 int isa = mips_opts.isa;
2197 if (mips_opts.ase_mdmx)
2199 if (mips_opts.ase_dsp)
2201 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2203 if (mips_opts.ase_dspr2)
2205 if (mips_opts.ase_mt)
2207 if (mips_opts.ase_mips3d)
2209 if (mips_opts.ase_smartmips)
2210 isa |= INSN_SMARTMIPS;
2211 if (mips_opts.ase_mcu)
2214 /* Don't accept instructions based on the ISA if the CPU does not implement
2215 all the coprocessor insns. */
2216 if (NO_ISA_COP (mips_opts.arch)
2217 && COP_INSN (mo->pinfo))
2220 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
2223 /* Check whether the instruction or macro requires single-precision or
2224 double-precision floating-point support. Note that this information is
2225 stored differently in the opcode table for insns and macros. */
2226 if (mo->pinfo == INSN_MACRO)
2228 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2229 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2233 fp_s = mo->pinfo & FP_S;
2234 fp_d = mo->pinfo & FP_D;
2237 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2240 if (fp_s && mips_opts.soft_float)
2246 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2247 selected ISA and architecture. */
2250 is_opcode_valid_16 (const struct mips_opcode *mo)
2252 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
2255 /* Return TRUE if the size of the microMIPS opcode MO matches one
2256 explicitly requested. Always TRUE in the standard MIPS mode. */
2259 is_size_valid (const struct mips_opcode *mo)
2261 if (!mips_opts.micromips)
2264 if (!forced_insn_length)
2266 if (mo->pinfo == INSN_MACRO)
2268 return forced_insn_length == micromips_insn_length (mo);
2271 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2272 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2275 is_delay_slot_valid (const struct mips_opcode *mo)
2277 if (!mips_opts.micromips)
2280 if (mo->pinfo == INSN_MACRO)
2282 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2283 && micromips_insn_length (mo) != 4)
2285 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2286 && micromips_insn_length (mo) != 2)
2292 /* This function is called once, at assembler startup time. It should set up
2293 all the tables, etc. that the MD part of the assembler will need. */
2298 const char *retval = NULL;
2302 if (mips_pic != NO_PIC)
2304 if (g_switch_seen && g_switch_value != 0)
2305 as_bad (_("-G may not be used in position-independent code"));
2309 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2310 as_warn (_("Could not set architecture and machine"));
2312 op_hash = hash_new ();
2314 for (i = 0; i < NUMOPCODES;)
2316 const char *name = mips_opcodes[i].name;
2318 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2321 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2322 mips_opcodes[i].name, retval);
2323 /* Probably a memory allocation problem? Give up now. */
2324 as_fatal (_("Broken assembler. No assembly attempted."));
2328 if (mips_opcodes[i].pinfo != INSN_MACRO)
2330 if (!validate_mips_insn (&mips_opcodes[i]))
2332 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2334 create_insn (&nop_insn, mips_opcodes + i);
2335 if (mips_fix_loongson2f_nop)
2336 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2337 nop_insn.fixed_p = 1;
2342 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2345 mips16_op_hash = hash_new ();
2348 while (i < bfd_mips16_num_opcodes)
2350 const char *name = mips16_opcodes[i].name;
2352 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2354 as_fatal (_("internal: can't hash `%s': %s"),
2355 mips16_opcodes[i].name, retval);
2358 if (mips16_opcodes[i].pinfo != INSN_MACRO
2359 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2360 != mips16_opcodes[i].match))
2362 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2363 mips16_opcodes[i].name, mips16_opcodes[i].args);
2366 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2368 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2369 mips16_nop_insn.fixed_p = 1;
2373 while (i < bfd_mips16_num_opcodes
2374 && strcmp (mips16_opcodes[i].name, name) == 0);
2377 micromips_op_hash = hash_new ();
2380 while (i < bfd_micromips_num_opcodes)
2382 const char *name = micromips_opcodes[i].name;
2384 retval = hash_insert (micromips_op_hash, name,
2385 (void *) µmips_opcodes[i]);
2387 as_fatal (_("internal: can't hash `%s': %s"),
2388 micromips_opcodes[i].name, retval);
2390 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2392 struct mips_cl_insn *micromips_nop_insn;
2394 if (!validate_micromips_insn (µmips_opcodes[i]))
2397 if (micromips_insn_length (micromips_opcodes + i) == 2)
2398 micromips_nop_insn = µmips_nop16_insn;
2399 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2400 micromips_nop_insn = µmips_nop32_insn;
2404 if (micromips_nop_insn->insn_mo == NULL
2405 && strcmp (name, "nop") == 0)
2407 create_insn (micromips_nop_insn, micromips_opcodes + i);
2408 micromips_nop_insn->fixed_p = 1;
2411 while (++i < bfd_micromips_num_opcodes
2412 && strcmp (micromips_opcodes[i].name, name) == 0);
2416 as_fatal (_("Broken assembler. No assembly attempted."));
2418 /* We add all the general register names to the symbol table. This
2419 helps us detect invalid uses of them. */
2420 for (i = 0; reg_names[i].name; i++)
2421 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2422 reg_names[i].num, /* & RNUM_MASK, */
2423 &zero_address_frag));
2425 for (i = 0; reg_names_n32n64[i].name; i++)
2426 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2427 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2428 &zero_address_frag));
2430 for (i = 0; reg_names_o32[i].name; i++)
2431 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2432 reg_names_o32[i].num, /* & RNUM_MASK, */
2433 &zero_address_frag));
2435 mips_no_prev_insn ();
2438 mips_cprmask[0] = 0;
2439 mips_cprmask[1] = 0;
2440 mips_cprmask[2] = 0;
2441 mips_cprmask[3] = 0;
2443 /* set the default alignment for the text section (2**2) */
2444 record_alignment (text_section, 2);
2446 bfd_set_gp_size (stdoutput, g_switch_value);
2451 /* On a native system other than VxWorks, sections must be aligned
2452 to 16 byte boundaries. When configured for an embedded ELF
2453 target, we don't bother. */
2454 if (strncmp (TARGET_OS, "elf", 3) != 0
2455 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2457 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2458 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2459 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2462 /* Create a .reginfo section for register masks and a .mdebug
2463 section for debugging information. */
2471 subseg = now_subseg;
2473 /* The ABI says this section should be loaded so that the
2474 running program can access it. However, we don't load it
2475 if we are configured for an embedded target */
2476 flags = SEC_READONLY | SEC_DATA;
2477 if (strncmp (TARGET_OS, "elf", 3) != 0)
2478 flags |= SEC_ALLOC | SEC_LOAD;
2480 if (mips_abi != N64_ABI)
2482 sec = subseg_new (".reginfo", (subsegT) 0);
2484 bfd_set_section_flags (stdoutput, sec, flags);
2485 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2487 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2491 /* The 64-bit ABI uses a .MIPS.options section rather than
2492 .reginfo section. */
2493 sec = subseg_new (".MIPS.options", (subsegT) 0);
2494 bfd_set_section_flags (stdoutput, sec, flags);
2495 bfd_set_section_alignment (stdoutput, sec, 3);
2497 /* Set up the option header. */
2499 Elf_Internal_Options opthdr;
2502 opthdr.kind = ODK_REGINFO;
2503 opthdr.size = (sizeof (Elf_External_Options)
2504 + sizeof (Elf64_External_RegInfo));
2507 f = frag_more (sizeof (Elf_External_Options));
2508 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2509 (Elf_External_Options *) f);
2511 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2515 if (ECOFF_DEBUGGING)
2517 sec = subseg_new (".mdebug", (subsegT) 0);
2518 (void) bfd_set_section_flags (stdoutput, sec,
2519 SEC_HAS_CONTENTS | SEC_READONLY);
2520 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2522 else if (mips_flag_pdr)
2524 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2525 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2526 SEC_READONLY | SEC_RELOC
2528 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2531 subseg_set (seg, subseg);
2534 #endif /* OBJ_ELF */
2536 if (! ECOFF_DEBUGGING)
2539 if (mips_fix_vr4120)
2540 init_vr4120_conflicts ();
2546 mips_emit_delays ();
2547 if (! ECOFF_DEBUGGING)
2552 md_assemble (char *str)
2554 struct mips_cl_insn insn;
2555 bfd_reloc_code_real_type unused_reloc[3]
2556 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2558 imm_expr.X_op = O_absent;
2559 imm2_expr.X_op = O_absent;
2560 offset_expr.X_op = O_absent;
2561 imm_reloc[0] = BFD_RELOC_UNUSED;
2562 imm_reloc[1] = BFD_RELOC_UNUSED;
2563 imm_reloc[2] = BFD_RELOC_UNUSED;
2564 offset_reloc[0] = BFD_RELOC_UNUSED;
2565 offset_reloc[1] = BFD_RELOC_UNUSED;
2566 offset_reloc[2] = BFD_RELOC_UNUSED;
2568 if (mips_opts.mips16)
2569 mips16_ip (str, &insn);
2572 mips_ip (str, &insn);
2573 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2574 str, insn.insn_opcode));
2579 as_bad ("%s `%s'", insn_error, str);
2583 if (insn.insn_mo->pinfo == INSN_MACRO)
2586 if (mips_opts.mips16)
2587 mips16_macro (&insn);
2594 if (imm_expr.X_op != O_absent)
2595 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2596 else if (offset_expr.X_op != O_absent)
2597 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2599 append_insn (&insn, NULL, unused_reloc, FALSE);
2603 /* Convenience functions for abstracting away the differences between
2604 MIPS16 and non-MIPS16 relocations. */
2606 static inline bfd_boolean
2607 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2611 case BFD_RELOC_MIPS16_JMP:
2612 case BFD_RELOC_MIPS16_GPREL:
2613 case BFD_RELOC_MIPS16_GOT16:
2614 case BFD_RELOC_MIPS16_CALL16:
2615 case BFD_RELOC_MIPS16_HI16_S:
2616 case BFD_RELOC_MIPS16_HI16:
2617 case BFD_RELOC_MIPS16_LO16:
2625 static inline bfd_boolean
2626 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2630 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2631 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2632 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2633 case BFD_RELOC_MICROMIPS_GPREL16:
2634 case BFD_RELOC_MICROMIPS_JMP:
2635 case BFD_RELOC_MICROMIPS_HI16:
2636 case BFD_RELOC_MICROMIPS_HI16_S:
2637 case BFD_RELOC_MICROMIPS_LO16:
2638 case BFD_RELOC_MICROMIPS_LITERAL:
2639 case BFD_RELOC_MICROMIPS_GOT16:
2640 case BFD_RELOC_MICROMIPS_CALL16:
2641 case BFD_RELOC_MICROMIPS_GOT_HI16:
2642 case BFD_RELOC_MICROMIPS_GOT_LO16:
2643 case BFD_RELOC_MICROMIPS_CALL_HI16:
2644 case BFD_RELOC_MICROMIPS_CALL_LO16:
2645 case BFD_RELOC_MICROMIPS_SUB:
2646 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2647 case BFD_RELOC_MICROMIPS_GOT_OFST:
2648 case BFD_RELOC_MICROMIPS_GOT_DISP:
2649 case BFD_RELOC_MICROMIPS_HIGHEST:
2650 case BFD_RELOC_MICROMIPS_HIGHER:
2651 case BFD_RELOC_MICROMIPS_SCN_DISP:
2652 case BFD_RELOC_MICROMIPS_JALR:
2660 static inline bfd_boolean
2661 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2663 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2666 static inline bfd_boolean
2667 got16_reloc_p (bfd_reloc_code_real_type reloc)
2669 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2670 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2673 static inline bfd_boolean
2674 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2676 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2677 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2680 static inline bfd_boolean
2681 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2683 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2684 || reloc == BFD_RELOC_MICROMIPS_LO16);
2687 static inline bfd_boolean
2688 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2690 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2693 /* Return true if the given relocation might need a matching %lo().
2694 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2695 need a matching %lo() when applied to local symbols. */
2697 static inline bfd_boolean
2698 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2700 return (HAVE_IN_PLACE_ADDENDS
2701 && (hi16_reloc_p (reloc)
2702 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2703 all GOT16 relocations evaluate to "G". */
2704 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2707 /* Return the type of %lo() reloc needed by RELOC, given that
2708 reloc_needs_lo_p. */
2710 static inline bfd_reloc_code_real_type
2711 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2713 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2714 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2718 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2721 static inline bfd_boolean
2722 fixup_has_matching_lo_p (fixS *fixp)
2724 return (fixp->fx_next != NULL
2725 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2726 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2727 && fixp->fx_offset == fixp->fx_next->fx_offset);
2730 /* This function returns true if modifying a register requires a
2734 reg_needs_delay (unsigned int reg)
2736 unsigned long prev_pinfo;
2738 prev_pinfo = history[0].insn_mo->pinfo;
2739 if (! mips_opts.noreorder
2740 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2741 && ! gpr_interlocks)
2742 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2743 && ! cop_interlocks)))
2745 /* A load from a coprocessor or from memory. All load delays
2746 delay the use of general register rt for one instruction. */
2747 /* Itbl support may require additional care here. */
2748 know (prev_pinfo & INSN_WRITE_GPR_T);
2749 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2756 /* Move all labels in insn_labels to the current insertion point. */
2759 mips_move_labels (void)
2761 segment_info_type *si = seg_info (now_seg);
2762 struct insn_label_list *l;
2765 for (l = si->label_list; l != NULL; l = l->next)
2767 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2768 symbol_set_frag (l->label, frag_now);
2769 val = (valueT) frag_now_fix ();
2770 /* MIPS16/microMIPS text labels are stored as odd. */
2771 if (HAVE_CODE_COMPRESSION)
2773 S_SET_VALUE (l->label, val);
2778 s_is_linkonce (symbolS *sym, segT from_seg)
2780 bfd_boolean linkonce = FALSE;
2781 segT symseg = S_GET_SEGMENT (sym);
2783 if (symseg != from_seg && !S_IS_LOCAL (sym))
2785 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2788 /* The GNU toolchain uses an extension for ELF: a section
2789 beginning with the magic string .gnu.linkonce is a
2790 linkonce section. */
2791 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2792 sizeof ".gnu.linkonce" - 1) == 0)
2799 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2800 linker to handle them specially, such as generating jalx instructions
2801 when needed. We also make them odd for the duration of the assembly,
2802 in order to generate the right sort of code. We will make them even
2803 in the adjust_symtab routine, while leaving them marked. This is
2804 convenient for the debugger and the disassembler. The linker knows
2805 to make them odd again. */
2808 mips_compressed_mark_labels (void)
2810 segment_info_type *si = seg_info (now_seg);
2811 struct insn_label_list *l;
2813 gas_assert (HAVE_CODE_COMPRESSION);
2815 for (l = si->label_list; l != NULL; l = l->next)
2817 symbolS *label = l->label;
2819 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2822 if (mips_opts.mips16)
2823 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2825 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2828 if ((S_GET_VALUE (label) & 1) == 0
2829 /* Don't adjust the address if the label is global or weak, or
2830 in a link-once section, since we'll be emitting symbol reloc
2831 references to it which will be patched up by the linker, and
2832 the final value of the symbol may or may not be MIPS16/microMIPS. */
2833 && ! S_IS_WEAK (label)
2834 && ! S_IS_EXTERNAL (label)
2835 && ! s_is_linkonce (label, now_seg))
2836 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2840 /* End the current frag. Make it a variant frag and record the
2844 relax_close_frag (void)
2846 mips_macro_warning.first_frag = frag_now;
2847 frag_var (rs_machine_dependent, 0, 0,
2848 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2849 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2851 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2852 mips_relax.first_fixup = 0;
2855 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2856 See the comment above RELAX_ENCODE for more details. */
2859 relax_start (symbolS *symbol)
2861 gas_assert (mips_relax.sequence == 0);
2862 mips_relax.sequence = 1;
2863 mips_relax.symbol = symbol;
2866 /* Start generating the second version of a relaxable sequence.
2867 See the comment above RELAX_ENCODE for more details. */
2872 gas_assert (mips_relax.sequence == 1);
2873 mips_relax.sequence = 2;
2876 /* End the current relaxable sequence. */
2881 gas_assert (mips_relax.sequence == 2);
2882 relax_close_frag ();
2883 mips_relax.sequence = 0;
2886 /* Return true if IP is a delayed branch or jump. */
2888 static inline bfd_boolean
2889 delayed_branch_p (const struct mips_cl_insn *ip)
2891 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2892 | INSN_COND_BRANCH_DELAY
2893 | INSN_COND_BRANCH_LIKELY)) != 0;
2896 /* Return true if IP is a compact branch or jump. */
2898 static inline bfd_boolean
2899 compact_branch_p (const struct mips_cl_insn *ip)
2901 if (mips_opts.mips16)
2902 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2903 | MIPS16_INSN_COND_BRANCH)) != 0;
2905 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2906 | INSN2_COND_BRANCH)) != 0;
2909 /* Return true if IP is an unconditional branch or jump. */
2911 static inline bfd_boolean
2912 uncond_branch_p (const struct mips_cl_insn *ip)
2914 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2915 || (mips_opts.mips16
2916 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2917 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2920 /* Return true if IP is a branch-likely instruction. */
2922 static inline bfd_boolean
2923 branch_likely_p (const struct mips_cl_insn *ip)
2925 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2928 /* Return the type of nop that should be used to fill the delay slot
2929 of delayed branch IP. */
2931 static struct mips_cl_insn *
2932 get_delay_slot_nop (const struct mips_cl_insn *ip)
2934 if (mips_opts.micromips
2935 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2936 return µmips_nop32_insn;
2940 /* Return the mask of core registers that IP reads or writes. */
2943 gpr_mod_mask (const struct mips_cl_insn *ip)
2945 unsigned long pinfo2;
2949 pinfo2 = ip->insn_mo->pinfo2;
2950 if (mips_opts.micromips)
2952 if (pinfo2 & INSN2_MOD_GPR_MD)
2953 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2954 if (pinfo2 & INSN2_MOD_GPR_MF)
2955 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2956 if (pinfo2 & INSN2_MOD_SP)
2962 /* Return the mask of core registers that IP reads. */
2965 gpr_read_mask (const struct mips_cl_insn *ip)
2967 unsigned long pinfo, pinfo2;
2970 mask = gpr_mod_mask (ip);
2971 pinfo = ip->insn_mo->pinfo;
2972 pinfo2 = ip->insn_mo->pinfo2;
2973 if (mips_opts.mips16)
2975 if (pinfo & MIPS16_INSN_READ_X)
2976 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2977 if (pinfo & MIPS16_INSN_READ_Y)
2978 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2979 if (pinfo & MIPS16_INSN_READ_T)
2981 if (pinfo & MIPS16_INSN_READ_SP)
2983 if (pinfo & MIPS16_INSN_READ_31)
2985 if (pinfo & MIPS16_INSN_READ_Z)
2986 mask |= 1 << (mips16_to_32_reg_map
2987 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2988 if (pinfo & MIPS16_INSN_READ_GPR_X)
2989 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2993 if (pinfo2 & INSN2_READ_GPR_D)
2994 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
2995 if (pinfo & INSN_READ_GPR_T)
2996 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
2997 if (pinfo & INSN_READ_GPR_S)
2998 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
2999 if (pinfo2 & INSN2_READ_GP)
3001 if (pinfo2 & INSN2_READ_GPR_31)
3003 if (pinfo2 & INSN2_READ_GPR_Z)
3004 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3006 if (mips_opts.micromips)
3008 if (pinfo2 & INSN2_READ_GPR_MC)
3009 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3010 if (pinfo2 & INSN2_READ_GPR_ME)
3011 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3012 if (pinfo2 & INSN2_READ_GPR_MG)
3013 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3014 if (pinfo2 & INSN2_READ_GPR_MJ)
3015 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3016 if (pinfo2 & INSN2_READ_GPR_MMN)
3018 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3019 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3021 if (pinfo2 & INSN2_READ_GPR_MP)
3022 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3023 if (pinfo2 & INSN2_READ_GPR_MQ)
3024 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3026 /* Don't include register 0. */
3030 /* Return the mask of core registers that IP writes. */
3033 gpr_write_mask (const struct mips_cl_insn *ip)
3035 unsigned long pinfo, pinfo2;
3038 mask = gpr_mod_mask (ip);
3039 pinfo = ip->insn_mo->pinfo;
3040 pinfo2 = ip->insn_mo->pinfo2;
3041 if (mips_opts.mips16)
3043 if (pinfo & MIPS16_INSN_WRITE_X)
3044 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3045 if (pinfo & MIPS16_INSN_WRITE_Y)
3046 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3047 if (pinfo & MIPS16_INSN_WRITE_Z)
3048 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3049 if (pinfo & MIPS16_INSN_WRITE_T)
3051 if (pinfo & MIPS16_INSN_WRITE_SP)
3053 if (pinfo & MIPS16_INSN_WRITE_31)
3055 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3056 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3060 if (pinfo & INSN_WRITE_GPR_D)
3061 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3062 if (pinfo & INSN_WRITE_GPR_T)
3063 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3064 if (pinfo & INSN_WRITE_GPR_S)
3065 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3066 if (pinfo & INSN_WRITE_GPR_31)
3068 if (pinfo2 & INSN2_WRITE_GPR_Z)
3069 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3071 if (mips_opts.micromips)
3073 if (pinfo2 & INSN2_WRITE_GPR_MB)
3074 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3075 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3077 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3078 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3080 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3081 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3082 if (pinfo2 & INSN2_WRITE_GPR_MP)
3083 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3085 /* Don't include register 0. */
3089 /* Return the mask of floating-point registers that IP reads. */
3092 fpr_read_mask (const struct mips_cl_insn *ip)
3094 unsigned long pinfo, pinfo2;
3098 pinfo = ip->insn_mo->pinfo;
3099 pinfo2 = ip->insn_mo->pinfo2;
3100 if (!mips_opts.mips16)
3102 if (pinfo2 & INSN2_READ_FPR_D)
3103 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3104 if (pinfo & INSN_READ_FPR_S)
3105 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3106 if (pinfo & INSN_READ_FPR_T)
3107 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3108 if (pinfo & INSN_READ_FPR_R)
3109 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3110 if (pinfo2 & INSN2_READ_FPR_Z)
3111 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3113 /* Conservatively treat all operands to an FP_D instruction are doubles.
3114 (This is overly pessimistic for things like cvt.d.s.) */
3115 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3120 /* Return the mask of floating-point registers that IP writes. */
3123 fpr_write_mask (const struct mips_cl_insn *ip)
3125 unsigned long pinfo, pinfo2;
3129 pinfo = ip->insn_mo->pinfo;
3130 pinfo2 = ip->insn_mo->pinfo2;
3131 if (!mips_opts.mips16)
3133 if (pinfo & INSN_WRITE_FPR_D)
3134 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3135 if (pinfo & INSN_WRITE_FPR_S)
3136 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3137 if (pinfo & INSN_WRITE_FPR_T)
3138 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3139 if (pinfo2 & INSN2_WRITE_FPR_Z)
3140 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3142 /* Conservatively treat all operands to an FP_D instruction are doubles.
3143 (This is overly pessimistic for things like cvt.s.d.) */
3144 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3149 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3150 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3151 by VR4120 errata. */
3154 classify_vr4120_insn (const char *name)
3156 if (strncmp (name, "macc", 4) == 0)
3157 return FIX_VR4120_MACC;
3158 if (strncmp (name, "dmacc", 5) == 0)
3159 return FIX_VR4120_DMACC;
3160 if (strncmp (name, "mult", 4) == 0)
3161 return FIX_VR4120_MULT;
3162 if (strncmp (name, "dmult", 5) == 0)
3163 return FIX_VR4120_DMULT;
3164 if (strstr (name, "div"))
3165 return FIX_VR4120_DIV;
3166 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3167 return FIX_VR4120_MTHILO;
3168 return NUM_FIX_VR4120_CLASSES;
3171 #define INSN_ERET 0x42000018
3172 #define INSN_DERET 0x4200001f
3174 /* Return the number of instructions that must separate INSN1 and INSN2,
3175 where INSN1 is the earlier instruction. Return the worst-case value
3176 for any INSN2 if INSN2 is null. */
3179 insns_between (const struct mips_cl_insn *insn1,
3180 const struct mips_cl_insn *insn2)
3182 unsigned long pinfo1, pinfo2;
3185 /* This function needs to know which pinfo flags are set for INSN2
3186 and which registers INSN2 uses. The former is stored in PINFO2 and
3187 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3188 will have every flag set and INSN2_USES_GPR will always return true. */
3189 pinfo1 = insn1->insn_mo->pinfo;
3190 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3192 #define INSN2_USES_GPR(REG) \
3193 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3195 /* For most targets, write-after-read dependencies on the HI and LO
3196 registers must be separated by at least two instructions. */
3197 if (!hilo_interlocks)
3199 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3201 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3205 /* If we're working around r7000 errata, there must be two instructions
3206 between an mfhi or mflo and any instruction that uses the result. */
3207 if (mips_7000_hilo_fix
3208 && !mips_opts.micromips
3209 && MF_HILO_INSN (pinfo1)
3210 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3213 /* If we're working around 24K errata, one instruction is required
3214 if an ERET or DERET is followed by a branch instruction. */
3215 if (mips_fix_24k && !mips_opts.micromips)
3217 if (insn1->insn_opcode == INSN_ERET
3218 || insn1->insn_opcode == INSN_DERET)
3221 || insn2->insn_opcode == INSN_ERET
3222 || insn2->insn_opcode == INSN_DERET
3223 || delayed_branch_p (insn2))
3228 /* If working around VR4120 errata, check for combinations that need
3229 a single intervening instruction. */
3230 if (mips_fix_vr4120 && !mips_opts.micromips)
3232 unsigned int class1, class2;
3234 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3235 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3239 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3240 if (vr4120_conflicts[class1] & (1 << class2))
3245 if (!HAVE_CODE_COMPRESSION)
3247 /* Check for GPR or coprocessor load delays. All such delays
3248 are on the RT register. */
3249 /* Itbl support may require additional care here. */
3250 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3251 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3253 know (pinfo1 & INSN_WRITE_GPR_T);
3254 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3258 /* Check for generic coprocessor hazards.
3260 This case is not handled very well. There is no special
3261 knowledge of CP0 handling, and the coprocessors other than
3262 the floating point unit are not distinguished at all. */
3263 /* Itbl support may require additional care here. FIXME!
3264 Need to modify this to include knowledge about
3265 user specified delays! */
3266 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3267 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3269 /* Handle cases where INSN1 writes to a known general coprocessor
3270 register. There must be a one instruction delay before INSN2
3271 if INSN2 reads that register, otherwise no delay is needed. */
3272 mask = fpr_write_mask (insn1);
3275 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3280 /* Read-after-write dependencies on the control registers
3281 require a two-instruction gap. */
3282 if ((pinfo1 & INSN_WRITE_COND_CODE)
3283 && (pinfo2 & INSN_READ_COND_CODE))
3286 /* We don't know exactly what INSN1 does. If INSN2 is
3287 also a coprocessor instruction, assume there must be
3288 a one instruction gap. */
3289 if (pinfo2 & INSN_COP)
3294 /* Check for read-after-write dependencies on the coprocessor
3295 control registers in cases where INSN1 does not need a general
3296 coprocessor delay. This means that INSN1 is a floating point
3297 comparison instruction. */
3298 /* Itbl support may require additional care here. */
3299 else if (!cop_interlocks
3300 && (pinfo1 & INSN_WRITE_COND_CODE)
3301 && (pinfo2 & INSN_READ_COND_CODE))
3305 #undef INSN2_USES_GPR
3310 /* Return the number of nops that would be needed to work around the
3311 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3312 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3313 that are contained within the first IGNORE instructions of HIST. */
3316 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3317 const struct mips_cl_insn *insn)
3322 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3323 are not affected by the errata. */
3325 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3326 || strcmp (insn->insn_mo->name, "mtlo") == 0
3327 || strcmp (insn->insn_mo->name, "mthi") == 0))
3330 /* Search for the first MFLO or MFHI. */
3331 for (i = 0; i < MAX_VR4130_NOPS; i++)
3332 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3334 /* Extract the destination register. */
3335 mask = gpr_write_mask (&hist[i]);
3337 /* No nops are needed if INSN reads that register. */
3338 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3341 /* ...or if any of the intervening instructions do. */
3342 for (j = 0; j < i; j++)
3343 if (gpr_read_mask (&hist[j]) & mask)
3347 return MAX_VR4130_NOPS - i;
3352 #define BASE_REG_EQ(INSN1, INSN2) \
3353 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3354 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3356 /* Return the minimum alignment for this store instruction. */
3359 fix_24k_align_to (const struct mips_opcode *mo)
3361 if (strcmp (mo->name, "sh") == 0)
3364 if (strcmp (mo->name, "swc1") == 0
3365 || strcmp (mo->name, "swc2") == 0
3366 || strcmp (mo->name, "sw") == 0
3367 || strcmp (mo->name, "sc") == 0
3368 || strcmp (mo->name, "s.s") == 0)
3371 if (strcmp (mo->name, "sdc1") == 0
3372 || strcmp (mo->name, "sdc2") == 0
3373 || strcmp (mo->name, "s.d") == 0)
3380 struct fix_24k_store_info
3382 /* Immediate offset, if any, for this store instruction. */
3384 /* Alignment required by this store instruction. */
3386 /* True for register offsets. */
3387 int register_offset;
3390 /* Comparison function used by qsort. */
3393 fix_24k_sort (const void *a, const void *b)
3395 const struct fix_24k_store_info *pos1 = a;
3396 const struct fix_24k_store_info *pos2 = b;
3398 return (pos1->off - pos2->off);
3401 /* INSN is a store instruction. Try to record the store information
3402 in STINFO. Return false if the information isn't known. */
3405 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3406 const struct mips_cl_insn *insn)
3408 /* The instruction must have a known offset. */
3409 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3412 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3413 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3417 /* Return the number of nops that would be needed to work around the 24k
3418 "lost data on stores during refill" errata if instruction INSN
3419 immediately followed the 2 instructions described by HIST.
3420 Ignore hazards that are contained within the first IGNORE
3421 instructions of HIST.
3423 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3424 for the data cache refills and store data. The following describes
3425 the scenario where the store data could be lost.
3427 * A data cache miss, due to either a load or a store, causing fill
3428 data to be supplied by the memory subsystem
3429 * The first three doublewords of fill data are returned and written
3431 * A sequence of four stores occurs in consecutive cycles around the
3432 final doubleword of the fill:
3436 * Zero, One or more instructions
3439 The four stores A-D must be to different doublewords of the line that
3440 is being filled. The fourth instruction in the sequence above permits
3441 the fill of the final doubleword to be transferred from the FSB into
3442 the cache. In the sequence above, the stores may be either integer
3443 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3444 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3445 different doublewords on the line. If the floating point unit is
3446 running in 1:2 mode, it is not possible to create the sequence above
3447 using only floating point store instructions.
3449 In this case, the cache line being filled is incorrectly marked
3450 invalid, thereby losing the data from any store to the line that
3451 occurs between the original miss and the completion of the five
3452 cycle sequence shown above.
3454 The workarounds are:
3456 * Run the data cache in write-through mode.
3457 * Insert a non-store instruction between
3458 Store A and Store B or Store B and Store C. */
3461 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3462 const struct mips_cl_insn *insn)
3464 struct fix_24k_store_info pos[3];
3465 int align, i, base_offset;
3470 /* If the previous instruction wasn't a store, there's nothing to
3472 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3475 /* If the instructions after the previous one are unknown, we have
3476 to assume the worst. */
3480 /* Check whether we are dealing with three consecutive stores. */
3481 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3482 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3485 /* If we don't know the relationship between the store addresses,
3486 assume the worst. */
3487 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3488 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3491 if (!fix_24k_record_store_info (&pos[0], insn)
3492 || !fix_24k_record_store_info (&pos[1], &hist[0])
3493 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3496 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3498 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3499 X bytes and such that the base register + X is known to be aligned
3502 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3506 align = pos[0].align_to;
3507 base_offset = pos[0].off;
3508 for (i = 1; i < 3; i++)
3509 if (align < pos[i].align_to)
3511 align = pos[i].align_to;
3512 base_offset = pos[i].off;
3514 for (i = 0; i < 3; i++)
3515 pos[i].off -= base_offset;
3518 pos[0].off &= ~align + 1;
3519 pos[1].off &= ~align + 1;
3520 pos[2].off &= ~align + 1;
3522 /* If any two stores write to the same chunk, they also write to the
3523 same doubleword. The offsets are still sorted at this point. */
3524 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3527 /* A range of at least 9 bytes is needed for the stores to be in
3528 non-overlapping doublewords. */
3529 if (pos[2].off - pos[0].off <= 8)
3532 if (pos[2].off - pos[1].off >= 24
3533 || pos[1].off - pos[0].off >= 24
3534 || pos[2].off - pos[0].off >= 32)
3540 /* Return the number of nops that would be needed if instruction INSN
3541 immediately followed the MAX_NOPS instructions given by HIST,
3542 where HIST[0] is the most recent instruction. Ignore hazards
3543 between INSN and the first IGNORE instructions in HIST.
3545 If INSN is null, return the worse-case number of nops for any
3549 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3550 const struct mips_cl_insn *insn)
3552 int i, nops, tmp_nops;
3555 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3557 tmp_nops = insns_between (hist + i, insn) - i;
3558 if (tmp_nops > nops)
3562 if (mips_fix_vr4130 && !mips_opts.micromips)
3564 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3565 if (tmp_nops > nops)
3569 if (mips_fix_24k && !mips_opts.micromips)
3571 tmp_nops = nops_for_24k (ignore, hist, insn);
3572 if (tmp_nops > nops)
3579 /* The variable arguments provide NUM_INSNS extra instructions that
3580 might be added to HIST. Return the largest number of nops that
3581 would be needed after the extended sequence, ignoring hazards
3582 in the first IGNORE instructions. */
3585 nops_for_sequence (int num_insns, int ignore,
3586 const struct mips_cl_insn *hist, ...)
3589 struct mips_cl_insn buffer[MAX_NOPS];
3590 struct mips_cl_insn *cursor;
3593 va_start (args, hist);
3594 cursor = buffer + num_insns;
3595 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3596 while (cursor > buffer)
3597 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3599 nops = nops_for_insn (ignore, buffer, NULL);
3604 /* Like nops_for_insn, but if INSN is a branch, take into account the
3605 worst-case delay for the branch target. */
3608 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3609 const struct mips_cl_insn *insn)
3613 nops = nops_for_insn (ignore, hist, insn);
3614 if (delayed_branch_p (insn))
3616 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3617 hist, insn, get_delay_slot_nop (insn));
3618 if (tmp_nops > nops)
3621 else if (compact_branch_p (insn))
3623 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3624 if (tmp_nops > nops)
3630 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3633 fix_loongson2f_nop (struct mips_cl_insn * ip)
3635 gas_assert (!HAVE_CODE_COMPRESSION);
3636 if (strcmp (ip->insn_mo->name, "nop") == 0)
3637 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3640 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3641 jr target pc &= 'hffff_ffff_cfff_ffff. */
3644 fix_loongson2f_jump (struct mips_cl_insn * ip)
3646 gas_assert (!HAVE_CODE_COMPRESSION);
3647 if (strcmp (ip->insn_mo->name, "j") == 0
3648 || strcmp (ip->insn_mo->name, "jr") == 0
3649 || strcmp (ip->insn_mo->name, "jalr") == 0)
3657 sreg = EXTRACT_OPERAND (0, RS, *ip);
3658 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3661 ep.X_op = O_constant;
3662 ep.X_add_number = 0xcfff0000;
3663 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3664 ep.X_add_number = 0xffff;
3665 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3666 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3671 fix_loongson2f (struct mips_cl_insn * ip)
3673 if (mips_fix_loongson2f_nop)
3674 fix_loongson2f_nop (ip);
3676 if (mips_fix_loongson2f_jump)
3677 fix_loongson2f_jump (ip);
3680 /* IP is a branch that has a delay slot, and we need to fill it
3681 automatically. Return true if we can do that by swapping IP
3682 with the previous instruction. */
3685 can_swap_branch_p (struct mips_cl_insn *ip)
3687 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3688 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3691 /* -O2 and above is required for this optimization. */
3692 if (mips_optimize < 2)
3695 /* If we have seen .set volatile or .set nomove, don't optimize. */
3696 if (mips_opts.nomove)
3699 /* We can't swap if the previous instruction's position is fixed. */
3700 if (history[0].fixed_p)
3703 /* If the previous previous insn was in a .set noreorder, we can't
3704 swap. Actually, the MIPS assembler will swap in this situation.
3705 However, gcc configured -with-gnu-as will generate code like
3713 in which we can not swap the bne and INSN. If gcc is not configured
3714 -with-gnu-as, it does not output the .set pseudo-ops. */
3715 if (history[1].noreorder_p)
3718 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3719 This means that the previous instruction was a 4-byte one anyhow. */
3720 if (mips_opts.mips16 && history[0].fixp[0])
3723 /* If the branch is itself the target of a branch, we can not swap.
3724 We cheat on this; all we check for is whether there is a label on
3725 this instruction. If there are any branches to anything other than
3726 a label, users must use .set noreorder. */
3727 if (seg_info (now_seg)->label_list)
3730 /* If the previous instruction is in a variant frag other than this
3731 branch's one, we cannot do the swap. This does not apply to
3732 MIPS16/microMIPS code, which uses variant frags for different
3734 if (!HAVE_CODE_COMPRESSION
3736 && history[0].frag->fr_type == rs_machine_dependent)
3739 /* We do not swap with instructions that cannot architecturally
3740 be placed in a branch delay slot, such as SYNC or ERET. We
3741 also refrain from swapping with a trap instruction, since it
3742 complicates trap handlers to have the trap instruction be in
3744 prev_pinfo = history[0].insn_mo->pinfo;
3745 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3748 /* Check for conflicts between the branch and the instructions
3749 before the candidate delay slot. */
3750 if (nops_for_insn (0, history + 1, ip) > 0)
3753 /* Check for conflicts between the swapped sequence and the
3754 target of the branch. */
3755 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3758 /* If the branch reads a register that the previous
3759 instruction sets, we can not swap. */
3760 gpr_read = gpr_read_mask (ip);
3761 prev_gpr_write = gpr_write_mask (&history[0]);
3762 if (gpr_read & prev_gpr_write)
3765 /* If the branch writes a register that the previous
3766 instruction sets, we can not swap. */
3767 gpr_write = gpr_write_mask (ip);
3768 if (gpr_write & prev_gpr_write)
3771 /* If the branch writes a register that the previous
3772 instruction reads, we can not swap. */
3773 prev_gpr_read = gpr_read_mask (&history[0]);
3774 if (gpr_write & prev_gpr_read)
3777 /* If one instruction sets a condition code and the
3778 other one uses a condition code, we can not swap. */
3779 pinfo = ip->insn_mo->pinfo;
3780 if ((pinfo & INSN_READ_COND_CODE)
3781 && (prev_pinfo & INSN_WRITE_COND_CODE))
3783 if ((pinfo & INSN_WRITE_COND_CODE)
3784 && (prev_pinfo & INSN_READ_COND_CODE))
3787 /* If the previous instruction uses the PC, we can not swap. */
3788 prev_pinfo2 = history[0].insn_mo->pinfo2;
3789 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3791 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3794 /* If the previous instruction has an incorrect size for a fixed
3795 branch delay slot in microMIPS mode, we cannot swap. */
3796 pinfo2 = ip->insn_mo->pinfo2;
3797 if (mips_opts.micromips
3798 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3799 && insn_length (history) != 2)
3801 if (mips_opts.micromips
3802 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3803 && insn_length (history) != 4)
3809 /* Decide how we should add IP to the instruction stream. */
3811 static enum append_method
3812 get_append_method (struct mips_cl_insn *ip)
3814 unsigned long pinfo;
3816 /* The relaxed version of a macro sequence must be inherently
3818 if (mips_relax.sequence == 2)
3821 /* We must not dabble with instructions in a ".set norerorder" block. */
3822 if (mips_opts.noreorder)
3825 /* Otherwise, it's our responsibility to fill branch delay slots. */
3826 if (delayed_branch_p (ip))
3828 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3831 pinfo = ip->insn_mo->pinfo;
3832 if (mips_opts.mips16
3833 && ISA_SUPPORTS_MIPS16E
3834 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3835 return APPEND_ADD_COMPACT;
3837 return APPEND_ADD_WITH_NOP;
3843 /* IP is a MIPS16 instruction whose opcode we have just changed.
3844 Point IP->insn_mo to the new opcode's definition. */
3847 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3849 const struct mips_opcode *mo, *end;
3851 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3852 for (mo = ip->insn_mo; mo < end; mo++)
3853 if ((ip->insn_opcode & mo->mask) == mo->match)
3861 /* For microMIPS macros, we need to generate a local number label
3862 as the target of branches. */
3863 #define MICROMIPS_LABEL_CHAR '\037'
3864 static unsigned long micromips_target_label;
3865 static char micromips_target_name[32];
3868 micromips_label_name (void)
3870 char *p = micromips_target_name;
3871 char symbol_name_temporary[24];
3879 l = micromips_target_label;
3880 #ifdef LOCAL_LABEL_PREFIX
3881 *p++ = LOCAL_LABEL_PREFIX;
3884 *p++ = MICROMIPS_LABEL_CHAR;
3887 symbol_name_temporary[i++] = l % 10 + '0';
3892 *p++ = symbol_name_temporary[--i];
3895 return micromips_target_name;
3899 micromips_label_expr (expressionS *label_expr)
3901 label_expr->X_op = O_symbol;
3902 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3903 label_expr->X_add_number = 0;
3907 micromips_label_inc (void)
3909 micromips_target_label++;
3910 *micromips_target_name = '\0';
3914 micromips_add_label (void)
3918 s = colon (micromips_label_name ());
3919 micromips_label_inc ();
3920 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3922 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3928 /* If assembling microMIPS code, then return the microMIPS reloc
3929 corresponding to the requested one if any. Otherwise return
3930 the reloc unchanged. */
3932 static bfd_reloc_code_real_type
3933 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3935 static const bfd_reloc_code_real_type relocs[][2] =
3937 /* Keep sorted incrementally by the left-hand key. */
3938 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3939 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3940 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3941 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3942 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3943 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3944 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3945 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3946 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3947 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3948 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3949 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3950 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3951 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3952 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3953 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3954 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3955 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3956 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3957 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3958 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3959 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3960 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3961 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3962 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3963 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3964 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
3966 bfd_reloc_code_real_type r;
3969 if (!mips_opts.micromips)
3971 for (i = 0; i < ARRAY_SIZE (relocs); i++)
3977 return relocs[i][1];
3982 /* Output an instruction. IP is the instruction information.
3983 ADDRESS_EXPR is an operand of the instruction to be used with
3984 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3985 a macro expansion. */
3988 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3989 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
3991 unsigned long prev_pinfo2, pinfo;
3992 bfd_boolean relaxed_branch = FALSE;
3993 enum append_method method;
3994 bfd_boolean relax32;
3997 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
3998 fix_loongson2f (ip);
4000 mips_mark_labels ();
4002 file_ase_mips16 |= mips_opts.mips16;
4003 file_ase_micromips |= mips_opts.micromips;
4005 prev_pinfo2 = history[0].insn_mo->pinfo2;
4006 pinfo = ip->insn_mo->pinfo;
4008 if (mips_opts.micromips
4010 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4011 && micromips_insn_length (ip->insn_mo) != 2)
4012 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4013 && micromips_insn_length (ip->insn_mo) != 4)))
4014 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4015 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4017 if (address_expr == NULL)
4019 else if (*reloc_type <= BFD_RELOC_UNUSED
4020 && address_expr->X_op == O_constant)
4025 switch (*reloc_type)
4028 ip->insn_opcode |= address_expr->X_add_number;
4031 case BFD_RELOC_MIPS_HIGHEST:
4032 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
4033 ip->insn_opcode |= tmp & 0xffff;
4036 case BFD_RELOC_MIPS_HIGHER:
4037 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
4038 ip->insn_opcode |= tmp & 0xffff;
4041 case BFD_RELOC_HI16_S:
4042 tmp = (address_expr->X_add_number + 0x8000) >> 16;
4043 ip->insn_opcode |= tmp & 0xffff;
4046 case BFD_RELOC_HI16:
4047 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4050 case BFD_RELOC_UNUSED:
4051 case BFD_RELOC_LO16:
4052 case BFD_RELOC_MIPS_GOT_DISP:
4053 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4056 case BFD_RELOC_MIPS_JMP:
4060 shift = mips_opts.micromips ? 1 : 2;
4061 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4062 as_bad (_("jump to misaligned address (0x%lx)"),
4063 (unsigned long) address_expr->X_add_number);
4064 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4070 case BFD_RELOC_MIPS16_JMP:
4071 if ((address_expr->X_add_number & 3) != 0)
4072 as_bad (_("jump to misaligned address (0x%lx)"),
4073 (unsigned long) address_expr->X_add_number);
4075 (((address_expr->X_add_number & 0x7c0000) << 3)
4076 | ((address_expr->X_add_number & 0xf800000) >> 7)
4077 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4081 case BFD_RELOC_16_PCREL_S2:
4085 shift = mips_opts.micromips ? 1 : 2;
4086 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4087 as_bad (_("branch to misaligned address (0x%lx)"),
4088 (unsigned long) address_expr->X_add_number);
4089 if (!mips_relax_branch)
4091 if ((address_expr->X_add_number + (1 << (shift + 15)))
4092 & ~((1 << (shift + 16)) - 1))
4093 as_bad (_("branch address range overflow (0x%lx)"),
4094 (unsigned long) address_expr->X_add_number);
4095 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4107 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4109 /* There are a lot of optimizations we could do that we don't.
4110 In particular, we do not, in general, reorder instructions.
4111 If you use gcc with optimization, it will reorder
4112 instructions and generally do much more optimization then we
4113 do here; repeating all that work in the assembler would only
4114 benefit hand written assembly code, and does not seem worth
4116 int nops = (mips_optimize == 0
4117 ? nops_for_insn (0, history, NULL)
4118 : nops_for_insn_or_target (0, history, ip));
4122 unsigned long old_frag_offset;
4125 old_frag = frag_now;
4126 old_frag_offset = frag_now_fix ();
4128 for (i = 0; i < nops; i++)
4129 add_fixed_insn (NOP_INSN);
4130 insert_into_history (0, nops, NOP_INSN);
4134 listing_prev_line ();
4135 /* We may be at the start of a variant frag. In case we
4136 are, make sure there is enough space for the frag
4137 after the frags created by listing_prev_line. The
4138 argument to frag_grow here must be at least as large
4139 as the argument to all other calls to frag_grow in
4140 this file. We don't have to worry about being in the
4141 middle of a variant frag, because the variants insert
4142 all needed nop instructions themselves. */
4146 mips_move_labels ();
4148 #ifndef NO_ECOFF_DEBUGGING
4149 if (ECOFF_DEBUGGING)
4150 ecoff_fix_loc (old_frag, old_frag_offset);
4154 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4158 /* Work out how many nops in prev_nop_frag are needed by IP,
4159 ignoring hazards generated by the first prev_nop_frag_since
4161 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4162 gas_assert (nops <= prev_nop_frag_holds);
4164 /* Enforce NOPS as a minimum. */
4165 if (nops > prev_nop_frag_required)
4166 prev_nop_frag_required = nops;
4168 if (prev_nop_frag_holds == prev_nop_frag_required)
4170 /* Settle for the current number of nops. Update the history
4171 accordingly (for the benefit of any future .set reorder code). */
4172 prev_nop_frag = NULL;
4173 insert_into_history (prev_nop_frag_since,
4174 prev_nop_frag_holds, NOP_INSN);
4178 /* Allow this instruction to replace one of the nops that was
4179 tentatively added to prev_nop_frag. */
4180 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4181 prev_nop_frag_holds--;
4182 prev_nop_frag_since++;
4186 method = get_append_method (ip);
4187 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4190 /* The value passed to dwarf2_emit_insn is the distance between
4191 the beginning of the current instruction and the address that
4192 should be recorded in the debug tables. This is normally the
4195 For MIPS16/microMIPS debug info we want to use ISA-encoded
4196 addresses, so we use -1 for an address higher by one than the
4199 If the instruction produced is a branch that we will swap with
4200 the preceding instruction, then we add the displacement by which
4201 the branch will be moved backwards. This is more appropriate
4202 and for MIPS16/microMIPS code also prevents a debugger from
4203 placing a breakpoint in the middle of the branch (and corrupting
4204 code if software breakpoints are used). */
4205 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4208 relax32 = (mips_relax_branch
4209 /* Don't try branch relaxation within .set nomacro, or within
4210 .set noat if we use $at for PIC computations. If it turns
4211 out that the branch was out-of-range, we'll get an error. */
4212 && !mips_opts.warn_about_macros
4213 && (mips_opts.at || mips_pic == NO_PIC)
4214 /* Don't relax BPOSGE32/64 as they have no complementing
4216 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4218 if (!HAVE_CODE_COMPRESSION
4221 && *reloc_type == BFD_RELOC_16_PCREL_S2
4222 && delayed_branch_p (ip))
4224 relaxed_branch = TRUE;
4225 add_relaxed_insn (ip, (relaxed_branch_length
4227 uncond_branch_p (ip) ? -1
4228 : branch_likely_p (ip) ? 1
4232 uncond_branch_p (ip),
4233 branch_likely_p (ip),
4234 pinfo & INSN_WRITE_GPR_31,
4236 address_expr->X_add_symbol,
4237 address_expr->X_add_number);
4238 *reloc_type = BFD_RELOC_UNUSED;
4240 else if (mips_opts.micromips
4242 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4243 || *reloc_type > BFD_RELOC_UNUSED)
4244 && (delayed_branch_p (ip) || compact_branch_p (ip))
4245 /* Don't try branch relaxation when users specify
4246 16-bit/32-bit instructions. */
4247 && !forced_insn_length)
4249 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4250 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4251 int uncond = uncond_branch_p (ip) ? -1 : 0;
4252 int compact = compact_branch_p (ip);
4253 int al = pinfo & INSN_WRITE_GPR_31;
4256 gas_assert (address_expr != NULL);
4257 gas_assert (!mips_relax.sequence);
4259 relaxed_branch = TRUE;
4260 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4261 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4262 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4264 address_expr->X_add_symbol,
4265 address_expr->X_add_number);
4266 *reloc_type = BFD_RELOC_UNUSED;
4268 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4270 /* We need to set up a variant frag. */
4271 gas_assert (address_expr != NULL);
4272 add_relaxed_insn (ip, 4, 0,
4274 (*reloc_type - BFD_RELOC_UNUSED,
4275 forced_insn_length == 2, forced_insn_length == 4,
4276 delayed_branch_p (&history[0]),
4277 history[0].mips16_absolute_jump_p),
4278 make_expr_symbol (address_expr), 0);
4280 else if (mips_opts.mips16
4282 && *reloc_type != BFD_RELOC_MIPS16_JMP)
4284 if (!delayed_branch_p (ip))
4285 /* Make sure there is enough room to swap this instruction with
4286 a following jump instruction. */
4288 add_fixed_insn (ip);
4292 if (mips_opts.mips16
4293 && mips_opts.noreorder
4294 && delayed_branch_p (&history[0]))
4295 as_warn (_("extended instruction in delay slot"));
4297 if (mips_relax.sequence)
4299 /* If we've reached the end of this frag, turn it into a variant
4300 frag and record the information for the instructions we've
4302 if (frag_room () < 4)
4303 relax_close_frag ();
4304 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4307 if (mips_relax.sequence != 2)
4309 if (mips_macro_warning.first_insn_sizes[0] == 0)
4310 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4311 mips_macro_warning.sizes[0] += insn_length (ip);
4312 mips_macro_warning.insns[0]++;
4314 if (mips_relax.sequence != 1)
4316 if (mips_macro_warning.first_insn_sizes[1] == 0)
4317 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4318 mips_macro_warning.sizes[1] += insn_length (ip);
4319 mips_macro_warning.insns[1]++;
4322 if (mips_opts.mips16)
4325 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4327 add_fixed_insn (ip);
4330 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4332 bfd_reloc_code_real_type final_type[3];
4333 reloc_howto_type *howto0;
4334 reloc_howto_type *howto;
4337 /* Perform any necessary conversion to microMIPS relocations
4338 and find out how many relocations there actually are. */
4339 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4340 final_type[i] = micromips_map_reloc (reloc_type[i]);
4342 /* In a compound relocation, it is the final (outermost)
4343 operator that determines the relocated field. */
4344 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4348 /* To reproduce this failure try assembling gas/testsuites/
4349 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4351 as_bad (_("Unsupported MIPS relocation number %d"),
4353 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4357 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4358 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4359 bfd_get_reloc_size (howto),
4361 howto0 && howto0->pc_relative,
4364 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4365 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4366 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4368 /* These relocations can have an addend that won't fit in
4369 4 octets for 64bit assembly. */
4371 && ! howto->partial_inplace
4372 && (reloc_type[0] == BFD_RELOC_16
4373 || reloc_type[0] == BFD_RELOC_32
4374 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4375 || reloc_type[0] == BFD_RELOC_GPREL16
4376 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4377 || reloc_type[0] == BFD_RELOC_GPREL32
4378 || reloc_type[0] == BFD_RELOC_64
4379 || reloc_type[0] == BFD_RELOC_CTOR
4380 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4381 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4382 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4383 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4384 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4385 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4386 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4387 || hi16_reloc_p (reloc_type[0])
4388 || lo16_reloc_p (reloc_type[0])))
4389 ip->fixp[0]->fx_no_overflow = 1;
4391 if (mips_relax.sequence)
4393 if (mips_relax.first_fixup == 0)
4394 mips_relax.first_fixup = ip->fixp[0];
4396 else if (reloc_needs_lo_p (*reloc_type))
4398 struct mips_hi_fixup *hi_fixup;
4400 /* Reuse the last entry if it already has a matching %lo. */
4401 hi_fixup = mips_hi_fixup_list;
4403 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4405 hi_fixup = ((struct mips_hi_fixup *)
4406 xmalloc (sizeof (struct mips_hi_fixup)));
4407 hi_fixup->next = mips_hi_fixup_list;
4408 mips_hi_fixup_list = hi_fixup;
4410 hi_fixup->fixp = ip->fixp[0];
4411 hi_fixup->seg = now_seg;
4414 /* Add fixups for the second and third relocations, if given.
4415 Note that the ABI allows the second relocation to be
4416 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4417 moment we only use RSS_UNDEF, but we could add support
4418 for the others if it ever becomes necessary. */
4419 for (i = 1; i < 3; i++)
4420 if (reloc_type[i] != BFD_RELOC_UNUSED)
4422 ip->fixp[i] = fix_new (ip->frag, ip->where,
4423 ip->fixp[0]->fx_size, NULL, 0,
4424 FALSE, final_type[i]);
4426 /* Use fx_tcbit to mark compound relocs. */
4427 ip->fixp[0]->fx_tcbit = 1;
4428 ip->fixp[i]->fx_tcbit = 1;
4433 /* Update the register mask information. */
4434 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4435 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4440 insert_into_history (0, 1, ip);
4443 case APPEND_ADD_WITH_NOP:
4445 struct mips_cl_insn *nop;
4447 insert_into_history (0, 1, ip);
4448 nop = get_delay_slot_nop (ip);
4449 add_fixed_insn (nop);
4450 insert_into_history (0, 1, nop);
4451 if (mips_relax.sequence)
4452 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4456 case APPEND_ADD_COMPACT:
4457 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4458 gas_assert (mips_opts.mips16);
4459 ip->insn_opcode |= 0x0080;
4460 find_altered_mips16_opcode (ip);
4462 insert_into_history (0, 1, ip);
4467 struct mips_cl_insn delay = history[0];
4468 if (mips_opts.mips16)
4470 know (delay.frag == ip->frag);
4471 move_insn (ip, delay.frag, delay.where);
4472 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4474 else if (relaxed_branch)
4476 /* Add the delay slot instruction to the end of the
4477 current frag and shrink the fixed part of the
4478 original frag. If the branch occupies the tail of
4479 the latter, move it backwards to cover the gap. */
4480 delay.frag->fr_fix -= branch_disp;
4481 if (delay.frag == ip->frag)
4482 move_insn (ip, ip->frag, ip->where - branch_disp);
4483 add_fixed_insn (&delay);
4487 move_insn (&delay, ip->frag,
4488 ip->where - branch_disp + insn_length (ip));
4489 move_insn (ip, history[0].frag, history[0].where);
4493 insert_into_history (0, 1, &delay);
4498 /* If we have just completed an unconditional branch, clear the history. */
4499 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4500 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4501 mips_no_prev_insn ();
4503 /* We need to emit a label at the end of branch-likely macros. */
4504 if (emit_branch_likely_macro)
4506 emit_branch_likely_macro = FALSE;
4507 micromips_add_label ();
4510 /* We just output an insn, so the next one doesn't have a label. */
4511 mips_clear_insn_labels ();
4514 /* Forget that there was any previous instruction or label. */
4517 mips_no_prev_insn (void)
4519 prev_nop_frag = NULL;
4520 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4521 mips_clear_insn_labels ();
4524 /* This function must be called before we emit something other than
4525 instructions. It is like mips_no_prev_insn except that it inserts
4526 any NOPS that might be needed by previous instructions. */
4529 mips_emit_delays (void)
4531 if (! mips_opts.noreorder)
4533 int nops = nops_for_insn (0, history, NULL);
4537 add_fixed_insn (NOP_INSN);
4538 mips_move_labels ();
4541 mips_no_prev_insn ();
4544 /* Start a (possibly nested) noreorder block. */
4547 start_noreorder (void)
4549 if (mips_opts.noreorder == 0)
4554 /* None of the instructions before the .set noreorder can be moved. */
4555 for (i = 0; i < ARRAY_SIZE (history); i++)
4556 history[i].fixed_p = 1;
4558 /* Insert any nops that might be needed between the .set noreorder
4559 block and the previous instructions. We will later remove any
4560 nops that turn out not to be needed. */
4561 nops = nops_for_insn (0, history, NULL);
4564 if (mips_optimize != 0)
4566 /* Record the frag which holds the nop instructions, so
4567 that we can remove them if we don't need them. */
4568 frag_grow (nops * NOP_INSN_SIZE);
4569 prev_nop_frag = frag_now;
4570 prev_nop_frag_holds = nops;
4571 prev_nop_frag_required = 0;
4572 prev_nop_frag_since = 0;
4575 for (; nops > 0; --nops)
4576 add_fixed_insn (NOP_INSN);
4578 /* Move on to a new frag, so that it is safe to simply
4579 decrease the size of prev_nop_frag. */
4580 frag_wane (frag_now);
4582 mips_move_labels ();
4584 mips_mark_labels ();
4585 mips_clear_insn_labels ();
4587 mips_opts.noreorder++;
4588 mips_any_noreorder = 1;
4591 /* End a nested noreorder block. */
4594 end_noreorder (void)
4597 mips_opts.noreorder--;
4598 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4600 /* Commit to inserting prev_nop_frag_required nops and go back to
4601 handling nop insertion the .set reorder way. */
4602 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4604 insert_into_history (prev_nop_frag_since,
4605 prev_nop_frag_required, NOP_INSN);
4606 prev_nop_frag = NULL;
4610 /* Set up global variables for the start of a new macro. */
4615 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4616 memset (&mips_macro_warning.first_insn_sizes, 0,
4617 sizeof (mips_macro_warning.first_insn_sizes));
4618 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4619 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4620 && delayed_branch_p (&history[0]));
4621 switch (history[0].insn_mo->pinfo2
4622 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4624 case INSN2_BRANCH_DELAY_32BIT:
4625 mips_macro_warning.delay_slot_length = 4;
4627 case INSN2_BRANCH_DELAY_16BIT:
4628 mips_macro_warning.delay_slot_length = 2;
4631 mips_macro_warning.delay_slot_length = 0;
4634 mips_macro_warning.first_frag = NULL;
4637 /* Given that a macro is longer than one instruction or of the wrong size,
4638 return the appropriate warning for it. Return null if no warning is
4639 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4640 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4641 and RELAX_NOMACRO. */
4644 macro_warning (relax_substateT subtype)
4646 if (subtype & RELAX_DELAY_SLOT)
4647 return _("Macro instruction expanded into multiple instructions"
4648 " in a branch delay slot");
4649 else if (subtype & RELAX_NOMACRO)
4650 return _("Macro instruction expanded into multiple instructions");
4651 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4652 | RELAX_DELAY_SLOT_SIZE_SECOND))
4653 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4654 ? _("Macro instruction expanded into a wrong size instruction"
4655 " in a 16-bit branch delay slot")
4656 : _("Macro instruction expanded into a wrong size instruction"
4657 " in a 32-bit branch delay slot"));
4662 /* Finish up a macro. Emit warnings as appropriate. */
4667 /* Relaxation warning flags. */
4668 relax_substateT subtype = 0;
4670 /* Check delay slot size requirements. */
4671 if (mips_macro_warning.delay_slot_length == 2)
4672 subtype |= RELAX_DELAY_SLOT_16BIT;
4673 if (mips_macro_warning.delay_slot_length != 0)
4675 if (mips_macro_warning.delay_slot_length
4676 != mips_macro_warning.first_insn_sizes[0])
4677 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4678 if (mips_macro_warning.delay_slot_length
4679 != mips_macro_warning.first_insn_sizes[1])
4680 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4683 /* Check instruction count requirements. */
4684 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4686 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4687 subtype |= RELAX_SECOND_LONGER;
4688 if (mips_opts.warn_about_macros)
4689 subtype |= RELAX_NOMACRO;
4690 if (mips_macro_warning.delay_slot_p)
4691 subtype |= RELAX_DELAY_SLOT;
4694 /* If both alternatives fail to fill a delay slot correctly,
4695 emit the warning now. */
4696 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4697 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4702 s = subtype & (RELAX_DELAY_SLOT_16BIT
4703 | RELAX_DELAY_SLOT_SIZE_FIRST
4704 | RELAX_DELAY_SLOT_SIZE_SECOND);
4705 msg = macro_warning (s);
4707 as_warn ("%s", msg);
4711 /* If both implementations are longer than 1 instruction, then emit the
4713 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4718 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4719 msg = macro_warning (s);
4721 as_warn ("%s", msg);
4725 /* If any flags still set, then one implementation might need a warning
4726 and the other either will need one of a different kind or none at all.
4727 Pass any remaining flags over to relaxation. */
4728 if (mips_macro_warning.first_frag != NULL)
4729 mips_macro_warning.first_frag->fr_subtype |= subtype;
4732 /* Instruction operand formats used in macros that vary between
4733 standard MIPS and microMIPS code. */
4735 static const char * const brk_fmt[2] = { "c", "mF" };
4736 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4737 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4738 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4739 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4740 static const char * const mfhl_fmt[2] = { "d", "mj" };
4741 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4742 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4744 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4745 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4746 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4747 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4748 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4749 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4750 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4751 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4753 /* Read a macro's relocation codes from *ARGS and store them in *R.
4754 The first argument in *ARGS will be either the code for a single
4755 relocation or -1 followed by the three codes that make up a
4756 composite relocation. */
4759 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4763 next = va_arg (*args, int);
4765 r[0] = (bfd_reloc_code_real_type) next;
4767 for (i = 0; i < 3; i++)
4768 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4771 /* Build an instruction created by a macro expansion. This is passed
4772 a pointer to the count of instructions created so far, an
4773 expression, the name of the instruction to build, an operand format
4774 string, and corresponding arguments. */
4777 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4779 const struct mips_opcode *mo = NULL;
4780 bfd_reloc_code_real_type r[3];
4781 const struct mips_opcode *amo;
4782 struct hash_control *hash;
4783 struct mips_cl_insn insn;
4786 va_start (args, fmt);
4788 if (mips_opts.mips16)
4790 mips16_macro_build (ep, name, fmt, &args);
4795 r[0] = BFD_RELOC_UNUSED;
4796 r[1] = BFD_RELOC_UNUSED;
4797 r[2] = BFD_RELOC_UNUSED;
4798 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4799 amo = (struct mips_opcode *) hash_find (hash, name);
4801 gas_assert (strcmp (name, amo->name) == 0);
4805 /* Search until we get a match for NAME. It is assumed here that
4806 macros will never generate MDMX, MIPS-3D, or MT instructions.
4807 We try to match an instruction that fulfils the branch delay
4808 slot instruction length requirement (if any) of the previous
4809 instruction. While doing this we record the first instruction
4810 seen that matches all the other conditions and use it anyway
4811 if the requirement cannot be met; we will issue an appropriate
4812 warning later on. */
4813 if (strcmp (fmt, amo->args) == 0
4814 && amo->pinfo != INSN_MACRO
4815 && is_opcode_valid (amo)
4816 && is_size_valid (amo))
4818 if (is_delay_slot_valid (amo))
4828 gas_assert (amo->name);
4830 while (strcmp (name, amo->name) == 0);
4833 create_insn (&insn, mo);
4851 INSERT_OPERAND (mips_opts.micromips,
4852 EXTLSB, insn, va_arg (args, int));
4857 /* Note that in the macro case, these arguments are already
4858 in MSB form. (When handling the instruction in the
4859 non-macro case, these arguments are sizes from which
4860 MSB values must be calculated.) */
4861 INSERT_OPERAND (mips_opts.micromips,
4862 INSMSB, insn, va_arg (args, int));
4868 /* Note that in the macro case, these arguments are already
4869 in MSBD form. (When handling the instruction in the
4870 non-macro case, these arguments are sizes from which
4871 MSBD values must be calculated.) */
4872 INSERT_OPERAND (mips_opts.micromips,
4873 EXTMSBD, insn, va_arg (args, int));
4877 gas_assert (!mips_opts.micromips);
4878 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4887 gas_assert (!mips_opts.micromips);
4888 INSERT_OPERAND (0, BP, insn, va_arg (args, int));
4892 gas_assert (mips_opts.micromips);
4896 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4900 gas_assert (!mips_opts.micromips);
4901 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4905 gas_assert (!mips_opts.micromips);
4907 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4911 if (mips_opts.micromips)
4912 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4914 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4918 gas_assert (!mips_opts.micromips);
4920 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
4924 gas_assert (!mips_opts.micromips);
4926 int tmp = va_arg (args, int);
4928 INSERT_OPERAND (0, RT, insn, tmp);
4929 INSERT_OPERAND (0, RD, insn, tmp);
4935 gas_assert (!mips_opts.micromips);
4936 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
4943 INSERT_OPERAND (mips_opts.micromips,
4944 SHAMT, insn, va_arg (args, int));
4948 gas_assert (!mips_opts.micromips);
4949 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
4953 gas_assert (!mips_opts.micromips);
4954 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
4958 gas_assert (!mips_opts.micromips);
4959 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4963 gas_assert (!mips_opts.micromips);
4964 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
4971 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
4976 macro_read_relocs (&args, r);
4977 gas_assert (*r == BFD_RELOC_GPREL16
4978 || *r == BFD_RELOC_MIPS_HIGHER
4979 || *r == BFD_RELOC_HI16_S
4980 || *r == BFD_RELOC_LO16
4981 || *r == BFD_RELOC_MIPS_GOT_OFST);
4985 macro_read_relocs (&args, r);
4989 macro_read_relocs (&args, r);
4990 gas_assert (ep != NULL
4991 && (ep->X_op == O_constant
4992 || (ep->X_op == O_symbol
4993 && (*r == BFD_RELOC_MIPS_HIGHEST
4994 || *r == BFD_RELOC_HI16_S
4995 || *r == BFD_RELOC_HI16
4996 || *r == BFD_RELOC_GPREL16
4997 || *r == BFD_RELOC_MIPS_GOT_HI16
4998 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5002 gas_assert (ep != NULL);
5005 * This allows macro() to pass an immediate expression for
5006 * creating short branches without creating a symbol.
5008 * We don't allow branch relaxation for these branches, as
5009 * they should only appear in ".set nomacro" anyway.
5011 if (ep->X_op == O_constant)
5013 /* For microMIPS we always use relocations for branches.
5014 So we should not resolve immediate values. */
5015 gas_assert (!mips_opts.micromips);
5017 if ((ep->X_add_number & 3) != 0)
5018 as_bad (_("branch to misaligned address (0x%lx)"),
5019 (unsigned long) ep->X_add_number);
5020 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5021 as_bad (_("branch address range overflow (0x%lx)"),
5022 (unsigned long) ep->X_add_number);
5023 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5027 *r = BFD_RELOC_16_PCREL_S2;
5031 gas_assert (ep != NULL);
5032 *r = BFD_RELOC_MIPS_JMP;
5036 gas_assert (!mips_opts.micromips);
5037 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5041 INSERT_OPERAND (mips_opts.micromips,
5042 CACHE, insn, va_arg (args, unsigned long));
5046 gas_assert (mips_opts.micromips);
5047 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5051 gas_assert (mips_opts.micromips);
5052 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5056 INSERT_OPERAND (mips_opts.micromips,
5057 3BITPOS, insn, va_arg (args, unsigned int));
5061 INSERT_OPERAND (mips_opts.micromips,
5062 OFFSET12, insn, va_arg (args, unsigned long));
5066 gas_assert (mips_opts.micromips);
5067 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5070 case 'm': /* Opcode extension character. */
5071 gas_assert (mips_opts.micromips);
5075 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5079 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5083 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5097 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5099 append_insn (&insn, ep, r, TRUE);
5103 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5106 struct mips_opcode *mo;
5107 struct mips_cl_insn insn;
5108 bfd_reloc_code_real_type r[3]
5109 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5111 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5113 gas_assert (strcmp (name, mo->name) == 0);
5115 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5118 gas_assert (mo->name);
5119 gas_assert (strcmp (name, mo->name) == 0);
5122 create_insn (&insn, mo);
5140 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5145 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5149 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5153 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5163 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5170 regno = va_arg (*args, int);
5171 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5172 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5193 gas_assert (ep != NULL);
5195 if (ep->X_op != O_constant)
5196 *r = (int) BFD_RELOC_UNUSED + c;
5199 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
5200 FALSE, &insn.insn_opcode, &insn.use_extend,
5203 *r = BFD_RELOC_UNUSED;
5209 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5216 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5218 append_insn (&insn, ep, r, TRUE);
5222 * Sign-extend 32-bit mode constants that have bit 31 set and all
5223 * higher bits unset.
5226 normalize_constant_expr (expressionS *ex)
5228 if (ex->X_op == O_constant
5229 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5230 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5235 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5236 * all higher bits unset.
5239 normalize_address_expr (expressionS *ex)
5241 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5242 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5243 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5244 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5249 * Generate a "jalr" instruction with a relocation hint to the called
5250 * function. This occurs in NewABI PIC code.
5253 macro_build_jalr (expressionS *ep, int cprestore)
5255 static const bfd_reloc_code_real_type jalr_relocs[2]
5256 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5257 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5261 if (MIPS_JALR_HINT_P (ep))
5266 if (!mips_opts.micromips)
5267 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5270 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5271 if (MIPS_JALR_HINT_P (ep))
5272 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5274 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5276 if (MIPS_JALR_HINT_P (ep))
5277 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5281 * Generate a "lui" instruction.
5284 macro_build_lui (expressionS *ep, int regnum)
5286 gas_assert (! mips_opts.mips16);
5288 if (ep->X_op != O_constant)
5290 gas_assert (ep->X_op == O_symbol);
5291 /* _gp_disp is a special case, used from s_cpload.
5292 __gnu_local_gp is used if mips_no_shared. */
5293 gas_assert (mips_pic == NO_PIC
5295 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5296 || (! mips_in_shared
5297 && strcmp (S_GET_NAME (ep->X_add_symbol),
5298 "__gnu_local_gp") == 0));
5301 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5304 /* Generate a sequence of instructions to do a load or store from a constant
5305 offset off of a base register (breg) into/from a target register (treg),
5306 using AT if necessary. */
5308 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5309 int treg, int breg, int dbl)
5311 gas_assert (ep->X_op == O_constant);
5313 /* Sign-extending 32-bit constants makes their handling easier. */
5315 normalize_constant_expr (ep);
5317 /* Right now, this routine can only handle signed 32-bit constants. */
5318 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5319 as_warn (_("operand overflow"));
5321 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5323 /* Signed 16-bit offset will fit in the op. Easy! */
5324 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5328 /* 32-bit offset, need multiple instructions and AT, like:
5329 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5330 addu $tempreg,$tempreg,$breg
5331 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5332 to handle the complete offset. */
5333 macro_build_lui (ep, AT);
5334 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5335 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5338 as_bad (_("Macro used $at after \".set noat\""));
5343 * Generates code to set the $at register to true (one)
5344 * if reg is less than the immediate expression.
5347 set_at (int reg, int unsignedp)
5349 if (imm_expr.X_op == O_constant
5350 && imm_expr.X_add_number >= -0x8000
5351 && imm_expr.X_add_number < 0x8000)
5352 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5353 AT, reg, BFD_RELOC_LO16);
5356 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5357 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5361 /* Warn if an expression is not a constant. */
5364 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5366 if (ex->X_op == O_big)
5367 as_bad (_("unsupported large constant"));
5368 else if (ex->X_op != O_constant)
5369 as_bad (_("Instruction %s requires absolute expression"),
5372 if (HAVE_32BIT_GPRS)
5373 normalize_constant_expr (ex);
5376 /* Count the leading zeroes by performing a binary chop. This is a
5377 bulky bit of source, but performance is a LOT better for the
5378 majority of values than a simple loop to count the bits:
5379 for (lcnt = 0; (lcnt < 32); lcnt++)
5380 if ((v) & (1 << (31 - lcnt)))
5382 However it is not code size friendly, and the gain will drop a bit
5383 on certain cached systems.
5385 #define COUNT_TOP_ZEROES(v) \
5386 (((v) & ~0xffff) == 0 \
5387 ? ((v) & ~0xff) == 0 \
5388 ? ((v) & ~0xf) == 0 \
5389 ? ((v) & ~0x3) == 0 \
5390 ? ((v) & ~0x1) == 0 \
5395 : ((v) & ~0x7) == 0 \
5398 : ((v) & ~0x3f) == 0 \
5399 ? ((v) & ~0x1f) == 0 \
5402 : ((v) & ~0x7f) == 0 \
5405 : ((v) & ~0xfff) == 0 \
5406 ? ((v) & ~0x3ff) == 0 \
5407 ? ((v) & ~0x1ff) == 0 \
5410 : ((v) & ~0x7ff) == 0 \
5413 : ((v) & ~0x3fff) == 0 \
5414 ? ((v) & ~0x1fff) == 0 \
5417 : ((v) & ~0x7fff) == 0 \
5420 : ((v) & ~0xffffff) == 0 \
5421 ? ((v) & ~0xfffff) == 0 \
5422 ? ((v) & ~0x3ffff) == 0 \
5423 ? ((v) & ~0x1ffff) == 0 \
5426 : ((v) & ~0x7ffff) == 0 \
5429 : ((v) & ~0x3fffff) == 0 \
5430 ? ((v) & ~0x1fffff) == 0 \
5433 : ((v) & ~0x7fffff) == 0 \
5436 : ((v) & ~0xfffffff) == 0 \
5437 ? ((v) & ~0x3ffffff) == 0 \
5438 ? ((v) & ~0x1ffffff) == 0 \
5441 : ((v) & ~0x7ffffff) == 0 \
5444 : ((v) & ~0x3fffffff) == 0 \
5445 ? ((v) & ~0x1fffffff) == 0 \
5448 : ((v) & ~0x7fffffff) == 0 \
5453 * This routine generates the least number of instructions necessary to load
5454 * an absolute expression value into a register.
5457 load_register (int reg, expressionS *ep, int dbl)
5460 expressionS hi32, lo32;
5462 if (ep->X_op != O_big)
5464 gas_assert (ep->X_op == O_constant);
5466 /* Sign-extending 32-bit constants makes their handling easier. */
5468 normalize_constant_expr (ep);
5470 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5472 /* We can handle 16 bit signed values with an addiu to
5473 $zero. No need to ever use daddiu here, since $zero and
5474 the result are always correct in 32 bit mode. */
5475 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5478 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5480 /* We can handle 16 bit unsigned values with an ori to
5482 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5485 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5487 /* 32 bit values require an lui. */
5488 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5489 if ((ep->X_add_number & 0xffff) != 0)
5490 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5495 /* The value is larger than 32 bits. */
5497 if (!dbl || HAVE_32BIT_GPRS)
5501 sprintf_vma (value, ep->X_add_number);
5502 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5503 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5507 if (ep->X_op != O_big)
5510 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5511 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5512 hi32.X_add_number &= 0xffffffff;
5514 lo32.X_add_number &= 0xffffffff;
5518 gas_assert (ep->X_add_number > 2);
5519 if (ep->X_add_number == 3)
5520 generic_bignum[3] = 0;
5521 else if (ep->X_add_number > 4)
5522 as_bad (_("Number larger than 64 bits"));
5523 lo32.X_op = O_constant;
5524 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5525 hi32.X_op = O_constant;
5526 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5529 if (hi32.X_add_number == 0)
5534 unsigned long hi, lo;
5536 if (hi32.X_add_number == (offsetT) 0xffffffff)
5538 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5540 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5543 if (lo32.X_add_number & 0x80000000)
5545 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5546 if (lo32.X_add_number & 0xffff)
5547 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5552 /* Check for 16bit shifted constant. We know that hi32 is
5553 non-zero, so start the mask on the first bit of the hi32
5558 unsigned long himask, lomask;
5562 himask = 0xffff >> (32 - shift);
5563 lomask = (0xffff << shift) & 0xffffffff;
5567 himask = 0xffff << (shift - 32);
5570 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5571 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5575 tmp.X_op = O_constant;
5577 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5578 | (lo32.X_add_number >> shift));
5580 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5581 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5582 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5583 reg, reg, (shift >= 32) ? shift - 32 : shift);
5588 while (shift <= (64 - 16));
5590 /* Find the bit number of the lowest one bit, and store the
5591 shifted value in hi/lo. */
5592 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5593 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5597 while ((lo & 1) == 0)
5602 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5608 while ((hi & 1) == 0)
5617 /* Optimize if the shifted value is a (power of 2) - 1. */
5618 if ((hi == 0 && ((lo + 1) & lo) == 0)
5619 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5621 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5626 /* This instruction will set the register to be all
5628 tmp.X_op = O_constant;
5629 tmp.X_add_number = (offsetT) -1;
5630 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5634 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5635 reg, reg, (bit >= 32) ? bit - 32 : bit);
5637 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5638 reg, reg, (shift >= 32) ? shift - 32 : shift);
5643 /* Sign extend hi32 before calling load_register, because we can
5644 generally get better code when we load a sign extended value. */
5645 if ((hi32.X_add_number & 0x80000000) != 0)
5646 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5647 load_register (reg, &hi32, 0);
5650 if ((lo32.X_add_number & 0xffff0000) == 0)
5654 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5662 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5664 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5665 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5671 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5675 mid16.X_add_number >>= 16;
5676 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5677 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5680 if ((lo32.X_add_number & 0xffff) != 0)
5681 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5685 load_delay_nop (void)
5687 if (!gpr_interlocks)
5688 macro_build (NULL, "nop", "");
5691 /* Load an address into a register. */
5694 load_address (int reg, expressionS *ep, int *used_at)
5696 if (ep->X_op != O_constant
5697 && ep->X_op != O_symbol)
5699 as_bad (_("expression too complex"));
5700 ep->X_op = O_constant;
5703 if (ep->X_op == O_constant)
5705 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5709 if (mips_pic == NO_PIC)
5711 /* If this is a reference to a GP relative symbol, we want
5712 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5714 lui $reg,<sym> (BFD_RELOC_HI16_S)
5715 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5716 If we have an addend, we always use the latter form.
5718 With 64bit address space and a usable $at we want
5719 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5720 lui $at,<sym> (BFD_RELOC_HI16_S)
5721 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5722 daddiu $at,<sym> (BFD_RELOC_LO16)
5726 If $at is already in use, we use a path which is suboptimal
5727 on superscalar processors.
5728 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5729 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5731 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5733 daddiu $reg,<sym> (BFD_RELOC_LO16)
5735 For GP relative symbols in 64bit address space we can use
5736 the same sequence as in 32bit address space. */
5737 if (HAVE_64BIT_SYMBOLS)
5739 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5740 && !nopic_need_relax (ep->X_add_symbol, 1))
5742 relax_start (ep->X_add_symbol);
5743 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5744 mips_gp_register, BFD_RELOC_GPREL16);
5748 if (*used_at == 0 && mips_opts.at)
5750 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5751 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5752 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5753 BFD_RELOC_MIPS_HIGHER);
5754 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5755 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5756 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5761 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5762 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5763 BFD_RELOC_MIPS_HIGHER);
5764 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5765 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5766 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5767 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5770 if (mips_relax.sequence)
5775 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5776 && !nopic_need_relax (ep->X_add_symbol, 1))
5778 relax_start (ep->X_add_symbol);
5779 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5780 mips_gp_register, BFD_RELOC_GPREL16);
5783 macro_build_lui (ep, reg);
5784 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5785 reg, reg, BFD_RELOC_LO16);
5786 if (mips_relax.sequence)
5790 else if (!mips_big_got)
5794 /* If this is a reference to an external symbol, we want
5795 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5797 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5799 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5800 If there is a constant, it must be added in after.
5802 If we have NewABI, we want
5803 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5804 unless we're referencing a global symbol with a non-zero
5805 offset, in which case cst must be added separately. */
5808 if (ep->X_add_number)
5810 ex.X_add_number = ep->X_add_number;
5811 ep->X_add_number = 0;
5812 relax_start (ep->X_add_symbol);
5813 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5814 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5815 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5816 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5817 ex.X_op = O_constant;
5818 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5819 reg, reg, BFD_RELOC_LO16);
5820 ep->X_add_number = ex.X_add_number;
5823 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5824 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5825 if (mips_relax.sequence)
5830 ex.X_add_number = ep->X_add_number;
5831 ep->X_add_number = 0;
5832 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5833 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5835 relax_start (ep->X_add_symbol);
5837 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5841 if (ex.X_add_number != 0)
5843 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5844 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5845 ex.X_op = O_constant;
5846 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5847 reg, reg, BFD_RELOC_LO16);
5851 else if (mips_big_got)
5855 /* This is the large GOT case. If this is a reference to an
5856 external symbol, we want
5857 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5859 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5861 Otherwise, for a reference to a local symbol in old ABI, we want
5862 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5864 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5865 If there is a constant, it must be added in after.
5867 In the NewABI, for local symbols, with or without offsets, we want:
5868 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5869 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5873 ex.X_add_number = ep->X_add_number;
5874 ep->X_add_number = 0;
5875 relax_start (ep->X_add_symbol);
5876 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5877 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5878 reg, reg, mips_gp_register);
5879 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5880 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5881 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5882 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5883 else if (ex.X_add_number)
5885 ex.X_op = O_constant;
5886 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5890 ep->X_add_number = ex.X_add_number;
5892 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5893 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5894 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5895 BFD_RELOC_MIPS_GOT_OFST);
5900 ex.X_add_number = ep->X_add_number;
5901 ep->X_add_number = 0;
5902 relax_start (ep->X_add_symbol);
5903 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5904 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5905 reg, reg, mips_gp_register);
5906 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5907 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5909 if (reg_needs_delay (mips_gp_register))
5911 /* We need a nop before loading from $gp. This special
5912 check is required because the lui which starts the main
5913 instruction stream does not refer to $gp, and so will not
5914 insert the nop which may be required. */
5915 macro_build (NULL, "nop", "");
5917 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5918 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5920 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5924 if (ex.X_add_number != 0)
5926 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5927 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5928 ex.X_op = O_constant;
5929 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5937 if (!mips_opts.at && *used_at == 1)
5938 as_bad (_("Macro used $at after \".set noat\""));
5941 /* Move the contents of register SOURCE into register DEST. */
5944 move_register (int dest, int source)
5946 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5947 instruction specifically requires a 32-bit one. */
5948 if (mips_opts.micromips
5949 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5950 macro_build (NULL, "move", "mp,mj", dest, source );
5952 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5956 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5957 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5958 The two alternatives are:
5960 Global symbol Local sybmol
5961 ------------- ------------
5962 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5964 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5966 load_got_offset emits the first instruction and add_got_offset
5967 emits the second for a 16-bit offset or add_got_offset_hilo emits
5968 a sequence to add a 32-bit offset using a scratch register. */
5971 load_got_offset (int dest, expressionS *local)
5976 global.X_add_number = 0;
5978 relax_start (local->X_add_symbol);
5979 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5980 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5982 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5983 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5988 add_got_offset (int dest, expressionS *local)
5992 global.X_op = O_constant;
5993 global.X_op_symbol = NULL;
5994 global.X_add_symbol = NULL;
5995 global.X_add_number = local->X_add_number;
5997 relax_start (local->X_add_symbol);
5998 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5999 dest, dest, BFD_RELOC_LO16);
6001 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6006 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6009 int hold_mips_optimize;
6011 global.X_op = O_constant;
6012 global.X_op_symbol = NULL;
6013 global.X_add_symbol = NULL;
6014 global.X_add_number = local->X_add_number;
6016 relax_start (local->X_add_symbol);
6017 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6019 /* Set mips_optimize around the lui instruction to avoid
6020 inserting an unnecessary nop after the lw. */
6021 hold_mips_optimize = mips_optimize;
6023 macro_build_lui (&global, tmp);
6024 mips_optimize = hold_mips_optimize;
6025 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6028 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6031 /* Emit a sequence of instructions to emulate a branch likely operation.
6032 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6033 is its complementing branch with the original condition negated.
6034 CALL is set if the original branch specified the link operation.
6035 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6037 Code like this is produced in the noreorder mode:
6042 delay slot (executed only if branch taken)
6050 delay slot (executed only if branch taken)
6053 In the reorder mode the delay slot would be filled with a nop anyway,
6054 so code produced is simply:
6059 This function is used when producing code for the microMIPS ASE that
6060 does not implement branch likely instructions in hardware. */
6063 macro_build_branch_likely (const char *br, const char *brneg,
6064 int call, expressionS *ep, const char *fmt,
6065 unsigned int sreg, unsigned int treg)
6067 int noreorder = mips_opts.noreorder;
6070 gas_assert (mips_opts.micromips);
6074 micromips_label_expr (&expr1);
6075 macro_build (&expr1, brneg, fmt, sreg, treg);
6076 macro_build (NULL, "nop", "");
6077 macro_build (ep, call ? "bal" : "b", "p");
6079 /* Set to true so that append_insn adds a label. */
6080 emit_branch_likely_macro = TRUE;
6084 macro_build (ep, br, fmt, sreg, treg);
6085 macro_build (NULL, "nop", "");
6090 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6091 the condition code tested. EP specifies the branch target. */
6094 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6121 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6124 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6125 the register tested. EP specifies the branch target. */
6128 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6130 const char *brneg = NULL;
6140 br = mips_opts.micromips ? "bgez" : "bgezl";
6144 gas_assert (mips_opts.micromips);
6153 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6160 br = mips_opts.micromips ? "blez" : "blezl";
6167 br = mips_opts.micromips ? "bltz" : "bltzl";
6171 gas_assert (mips_opts.micromips);
6179 if (mips_opts.micromips && brneg)
6180 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6182 macro_build (ep, br, "s,p", sreg);
6185 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6186 TREG as the registers tested. EP specifies the branch target. */
6189 macro_build_branch_rsrt (int type, expressionS *ep,
6190 unsigned int sreg, unsigned int treg)
6192 const char *brneg = NULL;
6204 br = mips_opts.micromips ? "beq" : "beql";
6213 br = mips_opts.micromips ? "bne" : "bnel";
6219 if (mips_opts.micromips && brneg)
6220 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6222 macro_build (ep, br, "s,t,p", sreg, treg);
6227 * This routine implements the seemingly endless macro or synthesized
6228 * instructions and addressing modes in the mips assembly language. Many
6229 * of these macros are simple and are similar to each other. These could
6230 * probably be handled by some kind of table or grammar approach instead of
6231 * this verbose method. Others are not simple macros but are more like
6232 * optimizing code generation.
6233 * One interesting optimization is when several store macros appear
6234 * consecutively that would load AT with the upper half of the same address.
6235 * The ensuing load upper instructions are ommited. This implies some kind
6236 * of global optimization. We currently only optimize within a single macro.
6237 * For many of the load and store macros if the address is specified as a
6238 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6239 * first load register 'at' with zero and use it as the base register. The
6240 * mips assembler simply uses register $zero. Just one tiny optimization
6244 macro (struct mips_cl_insn *ip)
6246 unsigned int treg, sreg, dreg, breg;
6247 unsigned int tempreg;
6250 expressionS label_expr;
6268 bfd_reloc_code_real_type r;
6269 int hold_mips_optimize;
6271 gas_assert (! mips_opts.mips16);
6273 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6274 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6275 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6276 mask = ip->insn_mo->mask;
6278 label_expr.X_op = O_constant;
6279 label_expr.X_op_symbol = NULL;
6280 label_expr.X_add_symbol = NULL;
6281 label_expr.X_add_number = 0;
6283 expr1.X_op = O_constant;
6284 expr1.X_op_symbol = NULL;
6285 expr1.X_add_symbol = NULL;
6286 expr1.X_add_number = 1;
6301 if (mips_opts.micromips)
6302 micromips_label_expr (&label_expr);
6304 label_expr.X_add_number = 8;
6305 macro_build (&label_expr, "bgez", "s,p", sreg);
6307 macro_build (NULL, "nop", "");
6309 move_register (dreg, sreg);
6310 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6311 if (mips_opts.micromips)
6312 micromips_add_label ();
6329 if (!mips_opts.micromips)
6331 if (imm_expr.X_op == O_constant
6332 && imm_expr.X_add_number >= -0x200
6333 && imm_expr.X_add_number < 0x200)
6335 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6344 if (imm_expr.X_op == O_constant
6345 && imm_expr.X_add_number >= -0x8000
6346 && imm_expr.X_add_number < 0x8000)
6348 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6353 load_register (AT, &imm_expr, dbl);
6354 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6373 if (imm_expr.X_op == O_constant
6374 && imm_expr.X_add_number >= 0
6375 && imm_expr.X_add_number < 0x10000)
6377 if (mask != M_NOR_I)
6378 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6381 macro_build (&imm_expr, "ori", "t,r,i",
6382 treg, sreg, BFD_RELOC_LO16);
6383 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6389 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6390 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6394 switch (imm_expr.X_add_number)
6397 macro_build (NULL, "nop", "");
6400 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6403 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6404 (int) imm_expr.X_add_number);
6413 gas_assert (mips_opts.micromips);
6414 macro_build_branch_ccl (mask, &offset_expr,
6415 EXTRACT_OPERAND (1, BCC, *ip));
6422 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6428 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6433 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6440 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6442 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6446 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6447 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6448 &offset_expr, AT, ZERO);
6458 macro_build_branch_rs (mask, &offset_expr, sreg);
6464 /* Check for > max integer. */
6465 maxnum = 0x7fffffff;
6466 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6473 if (imm_expr.X_op == O_constant
6474 && imm_expr.X_add_number >= maxnum
6475 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6478 /* Result is always false. */
6480 macro_build (NULL, "nop", "");
6482 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6485 if (imm_expr.X_op != O_constant)
6486 as_bad (_("Unsupported large constant"));
6487 ++imm_expr.X_add_number;
6491 if (mask == M_BGEL_I)
6493 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6495 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6496 &offset_expr, sreg);
6499 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6501 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6502 &offset_expr, sreg);
6505 maxnum = 0x7fffffff;
6506 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6513 maxnum = - maxnum - 1;
6514 if (imm_expr.X_op == O_constant
6515 && imm_expr.X_add_number <= maxnum
6516 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6519 /* result is always true */
6520 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6521 macro_build (&offset_expr, "b", "p");
6526 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6527 &offset_expr, AT, ZERO);
6536 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6537 &offset_expr, ZERO, treg);
6541 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6542 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6543 &offset_expr, AT, ZERO);
6552 && imm_expr.X_op == O_constant
6553 && imm_expr.X_add_number == -1))
6555 if (imm_expr.X_op != O_constant)
6556 as_bad (_("Unsupported large constant"));
6557 ++imm_expr.X_add_number;
6561 if (mask == M_BGEUL_I)
6563 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6565 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6566 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6567 &offset_expr, sreg, ZERO);
6572 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6573 &offset_expr, AT, ZERO);
6581 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6583 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6587 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6588 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6589 &offset_expr, AT, ZERO);
6597 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6598 &offset_expr, sreg, ZERO);
6604 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6605 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6606 &offset_expr, AT, ZERO);
6614 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6616 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6620 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6621 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6622 &offset_expr, AT, ZERO);
6629 maxnum = 0x7fffffff;
6630 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6637 if (imm_expr.X_op == O_constant
6638 && imm_expr.X_add_number >= maxnum
6639 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6641 if (imm_expr.X_op != O_constant)
6642 as_bad (_("Unsupported large constant"));
6643 ++imm_expr.X_add_number;
6647 if (mask == M_BLTL_I)
6649 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6650 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6651 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6652 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6657 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6658 &offset_expr, AT, ZERO);
6666 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6667 &offset_expr, sreg, ZERO);
6673 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6674 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6675 &offset_expr, AT, ZERO);
6684 && imm_expr.X_op == O_constant
6685 && imm_expr.X_add_number == -1))
6687 if (imm_expr.X_op != O_constant)
6688 as_bad (_("Unsupported large constant"));
6689 ++imm_expr.X_add_number;
6693 if (mask == M_BLTUL_I)
6695 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6697 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6698 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6699 &offset_expr, sreg, ZERO);
6704 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6705 &offset_expr, AT, ZERO);
6713 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6715 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6719 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6720 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6721 &offset_expr, AT, ZERO);
6731 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6732 &offset_expr, ZERO, treg);
6736 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6737 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6738 &offset_expr, AT, ZERO);
6744 /* Use unsigned arithmetic. */
6748 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6750 as_bad (_("Unsupported large constant"));
6755 pos = imm_expr.X_add_number;
6756 size = imm2_expr.X_add_number;
6761 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6764 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6766 as_bad (_("Improper extract size (%lu, position %lu)"),
6767 (unsigned long) size, (unsigned long) pos);
6771 if (size <= 32 && pos < 32)
6776 else if (size <= 32)
6786 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6793 /* Use unsigned arithmetic. */
6797 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6799 as_bad (_("Unsupported large constant"));
6804 pos = imm_expr.X_add_number;
6805 size = imm2_expr.X_add_number;
6810 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6813 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6815 as_bad (_("Improper insert size (%lu, position %lu)"),
6816 (unsigned long) size, (unsigned long) pos);
6820 if (pos < 32 && (pos + size - 1) < 32)
6835 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6836 (int) (pos + size - 1));
6852 as_warn (_("Divide by zero."));
6854 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6856 macro_build (NULL, "break", BRK_FMT, 7);
6863 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6864 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6868 if (mips_opts.micromips)
6869 micromips_label_expr (&label_expr);
6871 label_expr.X_add_number = 8;
6872 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6873 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6874 macro_build (NULL, "break", BRK_FMT, 7);
6875 if (mips_opts.micromips)
6876 micromips_add_label ();
6878 expr1.X_add_number = -1;
6880 load_register (AT, &expr1, dbl);
6881 if (mips_opts.micromips)
6882 micromips_label_expr (&label_expr);
6884 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6885 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6888 expr1.X_add_number = 1;
6889 load_register (AT, &expr1, dbl);
6890 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6894 expr1.X_add_number = 0x80000000;
6895 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6899 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6900 /* We want to close the noreorder block as soon as possible, so
6901 that later insns are available for delay slot filling. */
6906 if (mips_opts.micromips)
6907 micromips_label_expr (&label_expr);
6909 label_expr.X_add_number = 8;
6910 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6911 macro_build (NULL, "nop", "");
6913 /* We want to close the noreorder block as soon as possible, so
6914 that later insns are available for delay slot filling. */
6917 macro_build (NULL, "break", BRK_FMT, 6);
6919 if (mips_opts.micromips)
6920 micromips_add_label ();
6921 macro_build (NULL, s, MFHL_FMT, dreg);
6960 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6962 as_warn (_("Divide by zero."));
6964 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6966 macro_build (NULL, "break", BRK_FMT, 7);
6969 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6971 if (strcmp (s2, "mflo") == 0)
6972 move_register (dreg, sreg);
6974 move_register (dreg, ZERO);
6977 if (imm_expr.X_op == O_constant
6978 && imm_expr.X_add_number == -1
6979 && s[strlen (s) - 1] != 'u')
6981 if (strcmp (s2, "mflo") == 0)
6983 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
6986 move_register (dreg, ZERO);
6991 load_register (AT, &imm_expr, dbl);
6992 macro_build (NULL, s, "z,s,t", sreg, AT);
6993 macro_build (NULL, s2, MFHL_FMT, dreg);
7015 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7016 macro_build (NULL, s, "z,s,t", sreg, treg);
7017 /* We want to close the noreorder block as soon as possible, so
7018 that later insns are available for delay slot filling. */
7023 if (mips_opts.micromips)
7024 micromips_label_expr (&label_expr);
7026 label_expr.X_add_number = 8;
7027 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7028 macro_build (NULL, s, "z,s,t", sreg, treg);
7030 /* We want to close the noreorder block as soon as possible, so
7031 that later insns are available for delay slot filling. */
7033 macro_build (NULL, "break", BRK_FMT, 7);
7034 if (mips_opts.micromips)
7035 micromips_add_label ();
7037 macro_build (NULL, s2, MFHL_FMT, dreg);
7049 /* Load the address of a symbol into a register. If breg is not
7050 zero, we then add a base register to it. */
7052 if (dbl && HAVE_32BIT_GPRS)
7053 as_warn (_("dla used to load 32-bit register"));
7055 if (!dbl && HAVE_64BIT_OBJECTS)
7056 as_warn (_("la used to load 64-bit address"));
7058 if (offset_expr.X_op == O_constant
7059 && offset_expr.X_add_number >= -0x8000
7060 && offset_expr.X_add_number < 0x8000)
7062 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7063 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7067 if (mips_opts.at && (treg == breg))
7077 if (offset_expr.X_op != O_symbol
7078 && offset_expr.X_op != O_constant)
7080 as_bad (_("Expression too complex"));
7081 offset_expr.X_op = O_constant;
7084 if (offset_expr.X_op == O_constant)
7085 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7086 else if (mips_pic == NO_PIC)
7088 /* If this is a reference to a GP relative symbol, we want
7089 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7091 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7092 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7093 If we have a constant, we need two instructions anyhow,
7094 so we may as well always use the latter form.
7096 With 64bit address space and a usable $at we want
7097 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7098 lui $at,<sym> (BFD_RELOC_HI16_S)
7099 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7100 daddiu $at,<sym> (BFD_RELOC_LO16)
7102 daddu $tempreg,$tempreg,$at
7104 If $at is already in use, we use a path which is suboptimal
7105 on superscalar processors.
7106 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7107 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7109 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7111 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7113 For GP relative symbols in 64bit address space we can use
7114 the same sequence as in 32bit address space. */
7115 if (HAVE_64BIT_SYMBOLS)
7117 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7118 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7120 relax_start (offset_expr.X_add_symbol);
7121 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7122 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7126 if (used_at == 0 && mips_opts.at)
7128 macro_build (&offset_expr, "lui", LUI_FMT,
7129 tempreg, BFD_RELOC_MIPS_HIGHEST);
7130 macro_build (&offset_expr, "lui", LUI_FMT,
7131 AT, BFD_RELOC_HI16_S);
7132 macro_build (&offset_expr, "daddiu", "t,r,j",
7133 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7134 macro_build (&offset_expr, "daddiu", "t,r,j",
7135 AT, AT, BFD_RELOC_LO16);
7136 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7137 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7142 macro_build (&offset_expr, "lui", LUI_FMT,
7143 tempreg, BFD_RELOC_MIPS_HIGHEST);
7144 macro_build (&offset_expr, "daddiu", "t,r,j",
7145 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7146 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7147 macro_build (&offset_expr, "daddiu", "t,r,j",
7148 tempreg, tempreg, BFD_RELOC_HI16_S);
7149 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7150 macro_build (&offset_expr, "daddiu", "t,r,j",
7151 tempreg, tempreg, BFD_RELOC_LO16);
7154 if (mips_relax.sequence)
7159 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7160 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7162 relax_start (offset_expr.X_add_symbol);
7163 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7164 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7167 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7168 as_bad (_("Offset too large"));
7169 macro_build_lui (&offset_expr, tempreg);
7170 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7171 tempreg, tempreg, BFD_RELOC_LO16);
7172 if (mips_relax.sequence)
7176 else if (!mips_big_got && !HAVE_NEWABI)
7178 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7180 /* If this is a reference to an external symbol, and there
7181 is no constant, we want
7182 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7183 or for lca or if tempreg is PIC_CALL_REG
7184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7185 For a local symbol, we want
7186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7188 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7190 If we have a small constant, and this is a reference to
7191 an external symbol, we want
7192 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7194 addiu $tempreg,$tempreg,<constant>
7195 For a local symbol, we want the same instruction
7196 sequence, but we output a BFD_RELOC_LO16 reloc on the
7199 If we have a large constant, and this is a reference to
7200 an external symbol, we want
7201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7202 lui $at,<hiconstant>
7203 addiu $at,$at,<loconstant>
7204 addu $tempreg,$tempreg,$at
7205 For a local symbol, we want the same instruction
7206 sequence, but we output a BFD_RELOC_LO16 reloc on the
7210 if (offset_expr.X_add_number == 0)
7212 if (mips_pic == SVR4_PIC
7214 && (call || tempreg == PIC_CALL_REG))
7215 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7217 relax_start (offset_expr.X_add_symbol);
7218 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7219 lw_reloc_type, mips_gp_register);
7222 /* We're going to put in an addu instruction using
7223 tempreg, so we may as well insert the nop right
7228 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7229 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7231 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7232 tempreg, tempreg, BFD_RELOC_LO16);
7234 /* FIXME: If breg == 0, and the next instruction uses
7235 $tempreg, then if this variant case is used an extra
7236 nop will be generated. */
7238 else if (offset_expr.X_add_number >= -0x8000
7239 && offset_expr.X_add_number < 0x8000)
7241 load_got_offset (tempreg, &offset_expr);
7243 add_got_offset (tempreg, &offset_expr);
7247 expr1.X_add_number = offset_expr.X_add_number;
7248 offset_expr.X_add_number =
7249 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
7250 load_got_offset (tempreg, &offset_expr);
7251 offset_expr.X_add_number = expr1.X_add_number;
7252 /* If we are going to add in a base register, and the
7253 target register and the base register are the same,
7254 then we are using AT as a temporary register. Since
7255 we want to load the constant into AT, we add our
7256 current AT (from the global offset table) and the
7257 register into the register now, and pretend we were
7258 not using a base register. */
7262 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7267 add_got_offset_hilo (tempreg, &offset_expr, AT);
7271 else if (!mips_big_got && HAVE_NEWABI)
7273 int add_breg_early = 0;
7275 /* If this is a reference to an external, and there is no
7276 constant, or local symbol (*), with or without a
7278 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7279 or for lca or if tempreg is PIC_CALL_REG
7280 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7282 If we have a small constant, and this is a reference to
7283 an external symbol, we want
7284 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7285 addiu $tempreg,$tempreg,<constant>
7287 If we have a large constant, and this is a reference to
7288 an external symbol, we want
7289 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7290 lui $at,<hiconstant>
7291 addiu $at,$at,<loconstant>
7292 addu $tempreg,$tempreg,$at
7294 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7295 local symbols, even though it introduces an additional
7298 if (offset_expr.X_add_number)
7300 expr1.X_add_number = offset_expr.X_add_number;
7301 offset_expr.X_add_number = 0;
7303 relax_start (offset_expr.X_add_symbol);
7304 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7305 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7307 if (expr1.X_add_number >= -0x8000
7308 && expr1.X_add_number < 0x8000)
7310 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7311 tempreg, tempreg, BFD_RELOC_LO16);
7313 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7315 /* If we are going to add in a base register, and the
7316 target register and the base register are the same,
7317 then we are using AT as a temporary register. Since
7318 we want to load the constant into AT, we add our
7319 current AT (from the global offset table) and the
7320 register into the register now, and pretend we were
7321 not using a base register. */
7326 gas_assert (tempreg == AT);
7327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7333 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7334 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7340 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7343 offset_expr.X_add_number = expr1.X_add_number;
7345 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7346 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7349 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7350 treg, tempreg, breg);
7356 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7358 relax_start (offset_expr.X_add_symbol);
7359 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7360 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7362 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7363 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7368 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7369 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7372 else if (mips_big_got && !HAVE_NEWABI)
7375 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7376 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7377 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7379 /* This is the large GOT case. If this is a reference to an
7380 external symbol, and there is no constant, we want
7381 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7382 addu $tempreg,$tempreg,$gp
7383 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7384 or for lca or if tempreg is PIC_CALL_REG
7385 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7386 addu $tempreg,$tempreg,$gp
7387 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7388 For a local symbol, we want
7389 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7391 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7393 If we have a small constant, and this is a reference to
7394 an external symbol, we want
7395 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7396 addu $tempreg,$tempreg,$gp
7397 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7399 addiu $tempreg,$tempreg,<constant>
7400 For a local symbol, we want
7401 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7403 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7405 If we have a large constant, and this is a reference to
7406 an external symbol, we want
7407 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7408 addu $tempreg,$tempreg,$gp
7409 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7410 lui $at,<hiconstant>
7411 addiu $at,$at,<loconstant>
7412 addu $tempreg,$tempreg,$at
7413 For a local symbol, we want
7414 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7415 lui $at,<hiconstant>
7416 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7417 addu $tempreg,$tempreg,$at
7420 expr1.X_add_number = offset_expr.X_add_number;
7421 offset_expr.X_add_number = 0;
7422 relax_start (offset_expr.X_add_symbol);
7423 gpdelay = reg_needs_delay (mips_gp_register);
7424 if (expr1.X_add_number == 0 && breg == 0
7425 && (call || tempreg == PIC_CALL_REG))
7427 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7428 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7430 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7431 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7432 tempreg, tempreg, mips_gp_register);
7433 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7434 tempreg, lw_reloc_type, tempreg);
7435 if (expr1.X_add_number == 0)
7439 /* We're going to put in an addu instruction using
7440 tempreg, so we may as well insert the nop right
7445 else if (expr1.X_add_number >= -0x8000
7446 && expr1.X_add_number < 0x8000)
7449 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7450 tempreg, tempreg, BFD_RELOC_LO16);
7454 /* If we are going to add in a base register, and the
7455 target register and the base register are the same,
7456 then we are using AT as a temporary register. Since
7457 we want to load the constant into AT, we add our
7458 current AT (from the global offset table) and the
7459 register into the register now, and pretend we were
7460 not using a base register. */
7465 gas_assert (tempreg == AT);
7467 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7472 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7473 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7477 offset_expr.X_add_number =
7478 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
7483 /* This is needed because this instruction uses $gp, but
7484 the first instruction on the main stream does not. */
7485 macro_build (NULL, "nop", "");
7488 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7489 local_reloc_type, mips_gp_register);
7490 if (expr1.X_add_number >= -0x8000
7491 && expr1.X_add_number < 0x8000)
7494 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7495 tempreg, tempreg, BFD_RELOC_LO16);
7496 /* FIXME: If add_number is 0, and there was no base
7497 register, the external symbol case ended with a load,
7498 so if the symbol turns out to not be external, and
7499 the next instruction uses tempreg, an unnecessary nop
7500 will be inserted. */
7506 /* We must add in the base register now, as in the
7507 external symbol case. */
7508 gas_assert (tempreg == AT);
7510 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7513 /* We set breg to 0 because we have arranged to add
7514 it in in both cases. */
7518 macro_build_lui (&expr1, AT);
7519 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7520 AT, AT, BFD_RELOC_LO16);
7521 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7522 tempreg, tempreg, AT);
7527 else if (mips_big_got && HAVE_NEWABI)
7529 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7530 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7531 int add_breg_early = 0;
7533 /* This is the large GOT case. If this is a reference to an
7534 external symbol, and there is no constant, we want
7535 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7536 add $tempreg,$tempreg,$gp
7537 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7538 or for lca or if tempreg is PIC_CALL_REG
7539 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7540 add $tempreg,$tempreg,$gp
7541 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7543 If we have a small constant, and this is a reference to
7544 an external symbol, we want
7545 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7546 add $tempreg,$tempreg,$gp
7547 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7548 addi $tempreg,$tempreg,<constant>
7550 If we have a large constant, and this is a reference to
7551 an external symbol, we want
7552 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7553 addu $tempreg,$tempreg,$gp
7554 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7555 lui $at,<hiconstant>
7556 addi $at,$at,<loconstant>
7557 add $tempreg,$tempreg,$at
7559 If we have NewABI, and we know it's a local symbol, we want
7560 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7561 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7562 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7564 relax_start (offset_expr.X_add_symbol);
7566 expr1.X_add_number = offset_expr.X_add_number;
7567 offset_expr.X_add_number = 0;
7569 if (expr1.X_add_number == 0 && breg == 0
7570 && (call || tempreg == PIC_CALL_REG))
7572 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7573 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7575 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7576 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7577 tempreg, tempreg, mips_gp_register);
7578 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7579 tempreg, lw_reloc_type, tempreg);
7581 if (expr1.X_add_number == 0)
7583 else if (expr1.X_add_number >= -0x8000
7584 && expr1.X_add_number < 0x8000)
7586 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7587 tempreg, tempreg, BFD_RELOC_LO16);
7589 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7591 /* If we are going to add in a base register, and the
7592 target register and the base register are the same,
7593 then we are using AT as a temporary register. Since
7594 we want to load the constant into AT, we add our
7595 current AT (from the global offset table) and the
7596 register into the register now, and pretend we were
7597 not using a base register. */
7602 gas_assert (tempreg == AT);
7603 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7609 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7610 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7615 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7618 offset_expr.X_add_number = expr1.X_add_number;
7619 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7620 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7621 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7622 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7625 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7626 treg, tempreg, breg);
7636 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7640 gas_assert (!mips_opts.micromips);
7642 unsigned long temp = (treg << 16) | (0x01);
7643 macro_build (NULL, "c2", "C", temp);
7648 gas_assert (!mips_opts.micromips);
7650 unsigned long temp = (0x02);
7651 macro_build (NULL, "c2", "C", temp);
7656 gas_assert (!mips_opts.micromips);
7658 unsigned long temp = (treg << 16) | (0x02);
7659 macro_build (NULL, "c2", "C", temp);
7664 gas_assert (!mips_opts.micromips);
7665 macro_build (NULL, "c2", "C", 3);
7669 gas_assert (!mips_opts.micromips);
7671 unsigned long temp = (treg << 16) | 0x03;
7672 macro_build (NULL, "c2", "C", temp);
7677 /* The j instruction may not be used in PIC code, since it
7678 requires an absolute address. We convert it to a b
7680 if (mips_pic == NO_PIC)
7681 macro_build (&offset_expr, "j", "a");
7683 macro_build (&offset_expr, "b", "p");
7686 /* The jal instructions must be handled as macros because when
7687 generating PIC code they expand to multi-instruction
7688 sequences. Normally they are simple instructions. */
7693 gas_assert (mips_opts.micromips);
7701 if (mips_pic == NO_PIC)
7703 s = jals ? "jalrs" : "jalr";
7704 if (mips_opts.micromips && dreg == RA)
7705 macro_build (NULL, s, "mj", sreg);
7707 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7711 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7712 && mips_cprestore_offset >= 0);
7714 if (sreg != PIC_CALL_REG)
7715 as_warn (_("MIPS PIC call to register other than $25"));
7717 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7718 ? "jalrs" : "jalr");
7719 if (mips_opts.micromips && dreg == RA)
7720 macro_build (NULL, s, "mj", sreg);
7722 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7723 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7725 if (mips_cprestore_offset < 0)
7726 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7729 if (!mips_frame_reg_valid)
7731 as_warn (_("No .frame pseudo-op used in PIC code"));
7732 /* Quiet this warning. */
7733 mips_frame_reg_valid = 1;
7735 if (!mips_cprestore_valid)
7737 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7738 /* Quiet this warning. */
7739 mips_cprestore_valid = 1;
7741 if (mips_opts.noreorder)
7742 macro_build (NULL, "nop", "");
7743 expr1.X_add_number = mips_cprestore_offset;
7744 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7747 HAVE_64BIT_ADDRESSES);
7755 gas_assert (mips_opts.micromips);
7759 if (mips_pic == NO_PIC)
7760 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7761 else if (mips_pic == SVR4_PIC)
7763 /* If this is a reference to an external symbol, and we are
7764 using a small GOT, we want
7765 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7769 lw $gp,cprestore($sp)
7770 The cprestore value is set using the .cprestore
7771 pseudo-op. If we are using a big GOT, we want
7772 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7774 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7778 lw $gp,cprestore($sp)
7779 If the symbol is not external, we want
7780 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7782 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7785 lw $gp,cprestore($sp)
7787 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7788 sequences above, minus nops, unless the symbol is local,
7789 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7795 relax_start (offset_expr.X_add_symbol);
7796 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7797 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7800 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7801 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7807 relax_start (offset_expr.X_add_symbol);
7808 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7809 BFD_RELOC_MIPS_CALL_HI16);
7810 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7811 PIC_CALL_REG, mips_gp_register);
7812 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7813 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7816 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7817 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7819 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7820 PIC_CALL_REG, PIC_CALL_REG,
7821 BFD_RELOC_MIPS_GOT_OFST);
7825 macro_build_jalr (&offset_expr, 0);
7829 relax_start (offset_expr.X_add_symbol);
7832 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7833 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7842 gpdelay = reg_needs_delay (mips_gp_register);
7843 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7844 BFD_RELOC_MIPS_CALL_HI16);
7845 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7846 PIC_CALL_REG, mips_gp_register);
7847 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7848 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7853 macro_build (NULL, "nop", "");
7855 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7856 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7859 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7860 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7862 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7864 if (mips_cprestore_offset < 0)
7865 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7868 if (!mips_frame_reg_valid)
7870 as_warn (_("No .frame pseudo-op used in PIC code"));
7871 /* Quiet this warning. */
7872 mips_frame_reg_valid = 1;
7874 if (!mips_cprestore_valid)
7876 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7877 /* Quiet this warning. */
7878 mips_cprestore_valid = 1;
7880 if (mips_opts.noreorder)
7881 macro_build (NULL, "nop", "");
7882 expr1.X_add_number = mips_cprestore_offset;
7883 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7886 HAVE_64BIT_ADDRESSES);
7890 else if (mips_pic == VXWORKS_PIC)
7891 as_bad (_("Non-PIC jump used in PIC library"));
7901 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7909 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7940 gas_assert (!mips_opts.micromips);
7943 /* Itbl support may require additional care here. */
7950 /* Itbl support may require additional care here. */
7958 off12 = mips_opts.micromips;
7959 /* Itbl support may require additional care here. */
7964 gas_assert (!mips_opts.micromips);
7967 /* Itbl support may require additional care here. */
7975 off12 = mips_opts.micromips;
7982 off12 = mips_opts.micromips;
7988 /* Itbl support may require additional care here. */
7996 off12 = mips_opts.micromips;
7997 /* Itbl support may require additional care here. */
8004 /* Itbl support may require additional care here. */
8012 off12 = mips_opts.micromips;
8019 off12 = mips_opts.micromips;
8026 off12 = mips_opts.micromips;
8033 off12 = mips_opts.micromips;
8040 off12 = mips_opts.micromips;
8045 gas_assert (mips_opts.micromips);
8054 gas_assert (mips_opts.micromips);
8063 gas_assert (mips_opts.micromips);
8071 gas_assert (mips_opts.micromips);
8078 if (breg == treg + lp)
8081 tempreg = treg + lp;
8101 gas_assert (!mips_opts.micromips);
8104 /* Itbl support may require additional care here. */
8111 /* Itbl support may require additional care here. */
8119 off12 = mips_opts.micromips;
8120 /* Itbl support may require additional care here. */
8125 gas_assert (!mips_opts.micromips);
8128 /* Itbl support may require additional care here. */
8136 off12 = mips_opts.micromips;
8143 off12 = mips_opts.micromips;
8150 off12 = mips_opts.micromips;
8157 off12 = mips_opts.micromips;
8163 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8164 off12 = mips_opts.micromips;
8170 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8171 off12 = mips_opts.micromips;
8178 /* Itbl support may require additional care here. */
8185 off12 = mips_opts.micromips;
8186 /* Itbl support may require additional care here. */
8191 gas_assert (!mips_opts.micromips);
8194 /* Itbl support may require additional care here. */
8202 off12 = mips_opts.micromips;
8209 off12 = mips_opts.micromips;
8214 gas_assert (mips_opts.micromips);
8222 gas_assert (mips_opts.micromips);
8230 gas_assert (mips_opts.micromips);
8238 gas_assert (mips_opts.micromips);
8248 && NO_ISA_COP (mips_opts.arch)
8249 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
8251 as_bad (_("Opcode not supported on this processor: %s"),
8252 mips_cpu_info_from_arch (mips_opts.arch)->name);
8256 if (offset_expr.X_op != O_constant
8257 && offset_expr.X_op != O_symbol)
8259 as_bad (_("Expression too complex"));
8260 offset_expr.X_op = O_constant;
8263 if (HAVE_32BIT_ADDRESSES
8264 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8268 sprintf_vma (value, offset_expr.X_add_number);
8269 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8272 /* A constant expression in PIC code can be handled just as it
8273 is in non PIC code. */
8274 if (offset_expr.X_op == O_constant)
8278 expr1.X_add_number = offset_expr.X_add_number;
8279 normalize_address_expr (&expr1);
8280 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8282 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8283 & ~(bfd_vma) 0xffff);
8286 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8288 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8289 & ~(bfd_vma) 0xfff);
8294 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8296 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8297 tempreg, tempreg, breg);
8301 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8303 macro_build (NULL, s, fmt,
8304 treg, (unsigned long) offset_expr.X_add_number, breg);
8308 /* A 12-bit offset field is too narrow to be used for a low-part
8309 relocation, so load the whole address into the auxillary
8310 register. In the case of "A(b)" addresses, we first load
8311 absolute address "A" into the register and then add base
8312 register "b". In the case of "o(b)" addresses, we simply
8313 need to add 16-bit offset "o" to base register "b", and
8314 offset_reloc already contains the relocations associated
8318 load_address (tempreg, &offset_expr, &used_at);
8320 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8321 tempreg, tempreg, breg);
8324 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8326 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8327 expr1.X_add_number = 0;
8328 macro_build (NULL, s, fmt,
8329 treg, (unsigned long) expr1.X_add_number, tempreg);
8331 else if (mips_pic == NO_PIC)
8333 /* If this is a reference to a GP relative symbol, and there
8334 is no base register, we want
8335 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8336 Otherwise, if there is no base register, we want
8337 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8338 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8339 If we have a constant, we need two instructions anyhow,
8340 so we always use the latter form.
8342 If we have a base register, and this is a reference to a
8343 GP relative symbol, we want
8344 addu $tempreg,$breg,$gp
8345 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8347 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8348 addu $tempreg,$tempreg,$breg
8349 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8350 With a constant we always use the latter case.
8352 With 64bit address space and no base register and $at usable,
8354 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8355 lui $at,<sym> (BFD_RELOC_HI16_S)
8356 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8359 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8360 If we have a base register, we want
8361 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8362 lui $at,<sym> (BFD_RELOC_HI16_S)
8363 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8367 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8369 Without $at we can't generate the optimal path for superscalar
8370 processors here since this would require two temporary registers.
8371 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8372 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8374 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8376 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8377 If we have a base register, we want
8378 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8379 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8381 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8383 daddu $tempreg,$tempreg,$breg
8384 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8386 For GP relative symbols in 64bit address space we can use
8387 the same sequence as in 32bit address space. */
8388 if (HAVE_64BIT_SYMBOLS)
8390 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8391 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8393 relax_start (offset_expr.X_add_symbol);
8396 macro_build (&offset_expr, s, fmt, treg,
8397 BFD_RELOC_GPREL16, mips_gp_register);
8401 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8402 tempreg, breg, mips_gp_register);
8403 macro_build (&offset_expr, s, fmt, treg,
8404 BFD_RELOC_GPREL16, tempreg);
8409 if (used_at == 0 && mips_opts.at)
8411 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8412 BFD_RELOC_MIPS_HIGHEST);
8413 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8415 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8416 tempreg, BFD_RELOC_MIPS_HIGHER);
8418 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8419 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8420 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8421 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8427 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8428 BFD_RELOC_MIPS_HIGHEST);
8429 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8430 tempreg, BFD_RELOC_MIPS_HIGHER);
8431 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8432 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8433 tempreg, BFD_RELOC_HI16_S);
8434 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8436 macro_build (NULL, "daddu", "d,v,t",
8437 tempreg, tempreg, breg);
8438 macro_build (&offset_expr, s, fmt, treg,
8439 BFD_RELOC_LO16, tempreg);
8442 if (mips_relax.sequence)
8449 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8450 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8452 relax_start (offset_expr.X_add_symbol);
8453 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8457 macro_build_lui (&offset_expr, tempreg);
8458 macro_build (&offset_expr, s, fmt, treg,
8459 BFD_RELOC_LO16, tempreg);
8460 if (mips_relax.sequence)
8465 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8466 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8468 relax_start (offset_expr.X_add_symbol);
8469 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8470 tempreg, breg, mips_gp_register);
8471 macro_build (&offset_expr, s, fmt, treg,
8472 BFD_RELOC_GPREL16, tempreg);
8475 macro_build_lui (&offset_expr, tempreg);
8476 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8477 tempreg, tempreg, breg);
8478 macro_build (&offset_expr, s, fmt, treg,
8479 BFD_RELOC_LO16, tempreg);
8480 if (mips_relax.sequence)
8484 else if (!mips_big_got)
8486 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8488 /* If this is a reference to an external symbol, we want
8489 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8491 <op> $treg,0($tempreg)
8493 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8495 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8496 <op> $treg,0($tempreg)
8499 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8500 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8502 If there is a base register, we add it to $tempreg before
8503 the <op>. If there is a constant, we stick it in the
8504 <op> instruction. We don't handle constants larger than
8505 16 bits, because we have no way to load the upper 16 bits
8506 (actually, we could handle them for the subset of cases
8507 in which we are not using $at). */
8508 gas_assert (offset_expr.X_op == O_symbol);
8511 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8512 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8514 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8515 tempreg, tempreg, breg);
8516 macro_build (&offset_expr, s, fmt, treg,
8517 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8520 expr1.X_add_number = offset_expr.X_add_number;
8521 offset_expr.X_add_number = 0;
8522 if (expr1.X_add_number < -0x8000
8523 || expr1.X_add_number >= 0x8000)
8524 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8525 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8526 lw_reloc_type, mips_gp_register);
8528 relax_start (offset_expr.X_add_symbol);
8530 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8531 tempreg, BFD_RELOC_LO16);
8534 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8535 tempreg, tempreg, breg);
8536 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8538 else if (mips_big_got && !HAVE_NEWABI)
8542 /* If this is a reference to an external symbol, we want
8543 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8544 addu $tempreg,$tempreg,$gp
8545 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8546 <op> $treg,0($tempreg)
8548 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8550 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8551 <op> $treg,0($tempreg)
8552 If there is a base register, we add it to $tempreg before
8553 the <op>. If there is a constant, we stick it in the
8554 <op> instruction. We don't handle constants larger than
8555 16 bits, because we have no way to load the upper 16 bits
8556 (actually, we could handle them for the subset of cases
8557 in which we are not using $at). */
8558 gas_assert (offset_expr.X_op == O_symbol);
8559 expr1.X_add_number = offset_expr.X_add_number;
8560 offset_expr.X_add_number = 0;
8561 if (expr1.X_add_number < -0x8000
8562 || expr1.X_add_number >= 0x8000)
8563 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8564 gpdelay = reg_needs_delay (mips_gp_register);
8565 relax_start (offset_expr.X_add_symbol);
8566 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8567 BFD_RELOC_MIPS_GOT_HI16);
8568 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8570 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8571 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8574 macro_build (NULL, "nop", "");
8575 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8576 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8578 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8579 tempreg, BFD_RELOC_LO16);
8583 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8584 tempreg, tempreg, breg);
8585 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8587 else if (mips_big_got && HAVE_NEWABI)
8589 /* If this is a reference to an external symbol, we want
8590 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8591 add $tempreg,$tempreg,$gp
8592 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8593 <op> $treg,<ofst>($tempreg)
8594 Otherwise, for local symbols, we want:
8595 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8596 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8597 gas_assert (offset_expr.X_op == O_symbol);
8598 expr1.X_add_number = offset_expr.X_add_number;
8599 offset_expr.X_add_number = 0;
8600 if (expr1.X_add_number < -0x8000
8601 || expr1.X_add_number >= 0x8000)
8602 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8603 relax_start (offset_expr.X_add_symbol);
8604 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8605 BFD_RELOC_MIPS_GOT_HI16);
8606 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8608 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8609 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8611 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8612 tempreg, tempreg, breg);
8613 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8616 offset_expr.X_add_number = expr1.X_add_number;
8617 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8618 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8620 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8621 tempreg, tempreg, breg);
8622 macro_build (&offset_expr, s, fmt, treg,
8623 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8633 load_register (treg, &imm_expr, 0);
8637 load_register (treg, &imm_expr, 1);
8641 if (imm_expr.X_op == O_constant)
8644 load_register (AT, &imm_expr, 0);
8645 macro_build (NULL, "mtc1", "t,G", AT, treg);
8650 gas_assert (offset_expr.X_op == O_symbol
8651 && strcmp (segment_name (S_GET_SEGMENT
8652 (offset_expr.X_add_symbol)),
8654 && offset_expr.X_add_number == 0);
8655 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8656 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8661 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8662 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8663 order 32 bits of the value and the low order 32 bits are either
8664 zero or in OFFSET_EXPR. */
8665 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8667 if (HAVE_64BIT_GPRS)
8668 load_register (treg, &imm_expr, 1);
8673 if (target_big_endian)
8685 load_register (hreg, &imm_expr, 0);
8688 if (offset_expr.X_op == O_absent)
8689 move_register (lreg, 0);
8692 gas_assert (offset_expr.X_op == O_constant);
8693 load_register (lreg, &offset_expr, 0);
8700 /* We know that sym is in the .rdata section. First we get the
8701 upper 16 bits of the address. */
8702 if (mips_pic == NO_PIC)
8704 macro_build_lui (&offset_expr, AT);
8709 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8710 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8714 /* Now we load the register(s). */
8715 if (HAVE_64BIT_GPRS)
8718 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8723 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8726 /* FIXME: How in the world do we deal with the possible
8728 offset_expr.X_add_number += 4;
8729 macro_build (&offset_expr, "lw", "t,o(b)",
8730 treg + 1, BFD_RELOC_LO16, AT);
8736 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8737 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8738 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8739 the value and the low order 32 bits are either zero or in
8741 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8744 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8745 if (HAVE_64BIT_FPRS)
8747 gas_assert (HAVE_64BIT_GPRS);
8748 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8752 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8753 if (offset_expr.X_op == O_absent)
8754 macro_build (NULL, "mtc1", "t,G", 0, treg);
8757 gas_assert (offset_expr.X_op == O_constant);
8758 load_register (AT, &offset_expr, 0);
8759 macro_build (NULL, "mtc1", "t,G", AT, treg);
8765 gas_assert (offset_expr.X_op == O_symbol
8766 && offset_expr.X_add_number == 0);
8767 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8768 if (strcmp (s, ".lit8") == 0)
8770 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8772 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8773 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8776 breg = mips_gp_register;
8777 r = BFD_RELOC_MIPS_LITERAL;
8782 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8784 if (mips_pic != NO_PIC)
8785 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8786 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8789 /* FIXME: This won't work for a 64 bit address. */
8790 macro_build_lui (&offset_expr, AT);
8793 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8795 macro_build (&offset_expr, "ldc1", "T,o(b)",
8796 treg, BFD_RELOC_LO16, AT);
8805 /* Even on a big endian machine $fn comes before $fn+1. We have
8806 to adjust when loading from memory. */
8809 gas_assert (!mips_opts.micromips);
8810 gas_assert (mips_opts.isa == ISA_MIPS1);
8811 macro_build (&offset_expr, "lwc1", "T,o(b)",
8812 target_big_endian ? treg + 1 : treg, r, breg);
8813 /* FIXME: A possible overflow which I don't know how to deal
8815 offset_expr.X_add_number += 4;
8816 macro_build (&offset_expr, "lwc1", "T,o(b)",
8817 target_big_endian ? treg : treg + 1, r, breg);
8821 gas_assert (!mips_opts.micromips);
8822 gas_assert (mips_opts.isa == ISA_MIPS1);
8823 /* Even on a big endian machine $fn comes before $fn+1. We have
8824 to adjust when storing to memory. */
8825 macro_build (&offset_expr, "swc1", "T,o(b)",
8826 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8827 offset_expr.X_add_number += 4;
8828 macro_build (&offset_expr, "swc1", "T,o(b)",
8829 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8833 gas_assert (!mips_opts.micromips);
8835 * The MIPS assembler seems to check for X_add_number not
8836 * being double aligned and generating:
8839 * addiu at,at,%lo(foo+1)
8842 * But, the resulting address is the same after relocation so why
8843 * generate the extra instruction?
8845 /* Itbl support may require additional care here. */
8848 if (mips_opts.isa != ISA_MIPS1)
8857 gas_assert (!mips_opts.micromips);
8858 /* Itbl support may require additional care here. */
8861 if (mips_opts.isa != ISA_MIPS1)
8871 if (HAVE_64BIT_GPRS)
8881 if (HAVE_64BIT_GPRS)
8889 if (offset_expr.X_op != O_symbol
8890 && offset_expr.X_op != O_constant)
8892 as_bad (_("Expression too complex"));
8893 offset_expr.X_op = O_constant;
8896 if (HAVE_32BIT_ADDRESSES
8897 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8901 sprintf_vma (value, offset_expr.X_add_number);
8902 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8905 /* Even on a big endian machine $fn comes before $fn+1. We have
8906 to adjust when loading from memory. We set coproc if we must
8907 load $fn+1 first. */
8908 /* Itbl support may require additional care here. */
8909 if (!target_big_endian)
8912 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
8914 /* If this is a reference to a GP relative symbol, we want
8915 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8916 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8917 If we have a base register, we use this
8919 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8920 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8921 If this is not a GP relative symbol, we want
8922 lui $at,<sym> (BFD_RELOC_HI16_S)
8923 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8924 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8925 If there is a base register, we add it to $at after the
8926 lui instruction. If there is a constant, we always use
8928 if (offset_expr.X_op == O_symbol
8929 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8930 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8932 relax_start (offset_expr.X_add_symbol);
8935 tempreg = mips_gp_register;
8939 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8940 AT, breg, mips_gp_register);
8945 /* Itbl support may require additional care here. */
8946 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8947 BFD_RELOC_GPREL16, tempreg);
8948 offset_expr.X_add_number += 4;
8950 /* Set mips_optimize to 2 to avoid inserting an
8952 hold_mips_optimize = mips_optimize;
8954 /* Itbl support may require additional care here. */
8955 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8956 BFD_RELOC_GPREL16, tempreg);
8957 mips_optimize = hold_mips_optimize;
8961 offset_expr.X_add_number -= 4;
8964 macro_build_lui (&offset_expr, AT);
8966 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8967 /* Itbl support may require additional care here. */
8968 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8969 BFD_RELOC_LO16, AT);
8970 /* FIXME: How do we handle overflow here? */
8971 offset_expr.X_add_number += 4;
8972 /* Itbl support may require additional care here. */
8973 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8974 BFD_RELOC_LO16, AT);
8975 if (mips_relax.sequence)
8978 else if (!mips_big_got)
8980 /* If this is a reference to an external symbol, we want
8981 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8986 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8988 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8989 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8990 If there is a base register we add it to $at before the
8991 lwc1 instructions. If there is a constant we include it
8992 in the lwc1 instructions. */
8994 expr1.X_add_number = offset_expr.X_add_number;
8995 if (expr1.X_add_number < -0x8000
8996 || expr1.X_add_number >= 0x8000 - 4)
8997 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8998 load_got_offset (AT, &offset_expr);
9001 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9003 /* Set mips_optimize to 2 to avoid inserting an undesired
9005 hold_mips_optimize = mips_optimize;
9008 /* Itbl support may require additional care here. */
9009 relax_start (offset_expr.X_add_symbol);
9010 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9011 BFD_RELOC_LO16, AT);
9012 expr1.X_add_number += 4;
9013 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9014 BFD_RELOC_LO16, AT);
9016 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9017 BFD_RELOC_LO16, AT);
9018 offset_expr.X_add_number += 4;
9019 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9020 BFD_RELOC_LO16, AT);
9023 mips_optimize = hold_mips_optimize;
9025 else if (mips_big_got)
9029 /* If this is a reference to an external symbol, we want
9030 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9032 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9037 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9039 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9040 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9041 If there is a base register we add it to $at before the
9042 lwc1 instructions. If there is a constant we include it
9043 in the lwc1 instructions. */
9045 expr1.X_add_number = offset_expr.X_add_number;
9046 offset_expr.X_add_number = 0;
9047 if (expr1.X_add_number < -0x8000
9048 || expr1.X_add_number >= 0x8000 - 4)
9049 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9050 gpdelay = reg_needs_delay (mips_gp_register);
9051 relax_start (offset_expr.X_add_symbol);
9052 macro_build (&offset_expr, "lui", LUI_FMT,
9053 AT, BFD_RELOC_MIPS_GOT_HI16);
9054 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9055 AT, AT, mips_gp_register);
9056 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9057 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9060 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9061 /* Itbl support may require additional care here. */
9062 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9063 BFD_RELOC_LO16, AT);
9064 expr1.X_add_number += 4;
9066 /* Set mips_optimize to 2 to avoid inserting an undesired
9068 hold_mips_optimize = mips_optimize;
9070 /* Itbl support may require additional care here. */
9071 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9072 BFD_RELOC_LO16, AT);
9073 mips_optimize = hold_mips_optimize;
9074 expr1.X_add_number -= 4;
9077 offset_expr.X_add_number = expr1.X_add_number;
9079 macro_build (NULL, "nop", "");
9080 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9081 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9084 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9085 /* Itbl support may require additional care here. */
9086 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9087 BFD_RELOC_LO16, AT);
9088 offset_expr.X_add_number += 4;
9090 /* Set mips_optimize to 2 to avoid inserting an undesired
9092 hold_mips_optimize = mips_optimize;
9094 /* Itbl support may require additional care here. */
9095 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9096 BFD_RELOC_LO16, AT);
9097 mips_optimize = hold_mips_optimize;
9106 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9109 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9111 macro_build (&offset_expr, s, "t,o(b)", treg,
9112 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9114 if (!HAVE_64BIT_GPRS)
9116 offset_expr.X_add_number += 4;
9117 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9118 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9123 /* New code added to support COPZ instructions.
9124 This code builds table entries out of the macros in mip_opcodes.
9125 R4000 uses interlocks to handle coproc delays.
9126 Other chips (like the R3000) require nops to be inserted for delays.
9128 FIXME: Currently, we require that the user handle delays.
9129 In order to fill delay slots for non-interlocked chips,
9130 we must have a way to specify delays based on the coprocessor.
9131 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9132 What are the side-effects of the cop instruction?
9133 What cache support might we have and what are its effects?
9134 Both coprocessor & memory require delays. how long???
9135 What registers are read/set/modified?
9137 If an itbl is provided to interpret cop instructions,
9138 this knowledge can be encoded in the itbl spec. */
9152 gas_assert (!mips_opts.micromips);
9153 if (NO_ISA_COP (mips_opts.arch)
9154 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
9156 as_bad (_("opcode not supported on this processor: %s"),
9157 mips_cpu_info_from_arch (mips_opts.arch)->name);
9161 /* For now we just do C (same as Cz). The parameter will be
9162 stored in insn_opcode by mips_ip. */
9163 macro_build (NULL, s, "C", ip->insn_opcode);
9167 move_register (dreg, sreg);
9173 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9174 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9180 /* The MIPS assembler some times generates shifts and adds. I'm
9181 not trying to be that fancy. GCC should do this for us
9184 load_register (AT, &imm_expr, dbl);
9185 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9186 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9202 load_register (AT, &imm_expr, dbl);
9203 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9204 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9205 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9206 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9208 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9211 if (mips_opts.micromips)
9212 micromips_label_expr (&label_expr);
9214 label_expr.X_add_number = 8;
9215 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9216 macro_build (NULL, "nop", "");
9217 macro_build (NULL, "break", BRK_FMT, 6);
9218 if (mips_opts.micromips)
9219 micromips_add_label ();
9222 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9238 load_register (AT, &imm_expr, dbl);
9239 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9240 sreg, imm ? AT : treg);
9241 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9242 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9244 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9247 if (mips_opts.micromips)
9248 micromips_label_expr (&label_expr);
9250 label_expr.X_add_number = 8;
9251 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9252 macro_build (NULL, "nop", "");
9253 macro_build (NULL, "break", BRK_FMT, 6);
9254 if (mips_opts.micromips)
9255 micromips_add_label ();
9261 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9272 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9273 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9277 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9278 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9279 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9280 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9284 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9295 macro_build (NULL, "negu", "d,w", tempreg, treg);
9296 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9300 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9301 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9302 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9303 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9312 if (imm_expr.X_op != O_constant)
9313 as_bad (_("Improper rotate count"));
9314 rot = imm_expr.X_add_number & 0x3f;
9315 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9317 rot = (64 - rot) & 0x3f;
9319 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9321 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9326 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9329 l = (rot < 0x20) ? "dsll" : "dsll32";
9330 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9333 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9334 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9335 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9343 if (imm_expr.X_op != O_constant)
9344 as_bad (_("Improper rotate count"));
9345 rot = imm_expr.X_add_number & 0x1f;
9346 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9348 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9353 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9357 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9358 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9359 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9364 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9366 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9370 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9371 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9372 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9373 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9377 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9379 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9383 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9384 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9385 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9386 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9395 if (imm_expr.X_op != O_constant)
9396 as_bad (_("Improper rotate count"));
9397 rot = imm_expr.X_add_number & 0x3f;
9398 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9401 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9403 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9408 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9411 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9412 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9415 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9416 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9417 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9425 if (imm_expr.X_op != O_constant)
9426 as_bad (_("Improper rotate count"));
9427 rot = imm_expr.X_add_number & 0x1f;
9428 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9430 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9435 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9439 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9440 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9441 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9447 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9449 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9452 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9453 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9458 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9460 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9465 as_warn (_("Instruction %s: result is always false"),
9467 move_register (dreg, 0);
9470 if (CPU_HAS_SEQ (mips_opts.arch)
9471 && -512 <= imm_expr.X_add_number
9472 && imm_expr.X_add_number < 512)
9474 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9475 (int) imm_expr.X_add_number);
9478 if (imm_expr.X_op == O_constant
9479 && imm_expr.X_add_number >= 0
9480 && imm_expr.X_add_number < 0x10000)
9482 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9484 else if (imm_expr.X_op == O_constant
9485 && imm_expr.X_add_number > -0x8000
9486 && imm_expr.X_add_number < 0)
9488 imm_expr.X_add_number = -imm_expr.X_add_number;
9489 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9490 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9492 else if (CPU_HAS_SEQ (mips_opts.arch))
9495 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9496 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9501 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9502 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9505 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9508 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9514 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9515 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9518 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9520 if (imm_expr.X_op == O_constant
9521 && imm_expr.X_add_number >= -0x8000
9522 && imm_expr.X_add_number < 0x8000)
9524 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9525 dreg, sreg, BFD_RELOC_LO16);
9529 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9530 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9534 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9537 case M_SGT: /* sreg > treg <==> treg < sreg */
9543 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9546 case M_SGT_I: /* sreg > I <==> I < sreg */
9553 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9554 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9557 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9563 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9564 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9567 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9574 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9575 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9576 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9580 if (imm_expr.X_op == O_constant
9581 && imm_expr.X_add_number >= -0x8000
9582 && imm_expr.X_add_number < 0x8000)
9584 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9588 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9589 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9593 if (imm_expr.X_op == O_constant
9594 && imm_expr.X_add_number >= -0x8000
9595 && imm_expr.X_add_number < 0x8000)
9597 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9602 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9603 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9608 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9610 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9613 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9614 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9619 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9621 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9626 as_warn (_("Instruction %s: result is always true"),
9628 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9629 dreg, 0, BFD_RELOC_LO16);
9632 if (CPU_HAS_SEQ (mips_opts.arch)
9633 && -512 <= imm_expr.X_add_number
9634 && imm_expr.X_add_number < 512)
9636 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9637 (int) imm_expr.X_add_number);
9640 if (imm_expr.X_op == O_constant
9641 && imm_expr.X_add_number >= 0
9642 && imm_expr.X_add_number < 0x10000)
9644 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9646 else if (imm_expr.X_op == O_constant
9647 && imm_expr.X_add_number > -0x8000
9648 && imm_expr.X_add_number < 0)
9650 imm_expr.X_add_number = -imm_expr.X_add_number;
9651 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9652 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9654 else if (CPU_HAS_SEQ (mips_opts.arch))
9657 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9658 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9663 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9664 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9667 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9682 if (!mips_opts.micromips)
9684 if (imm_expr.X_op == O_constant
9685 && imm_expr.X_add_number > -0x200
9686 && imm_expr.X_add_number <= 0x200)
9688 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9697 if (imm_expr.X_op == O_constant
9698 && imm_expr.X_add_number > -0x8000
9699 && imm_expr.X_add_number <= 0x8000)
9701 imm_expr.X_add_number = -imm_expr.X_add_number;
9702 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9707 load_register (AT, &imm_expr, dbl);
9708 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9730 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9731 macro_build (NULL, s, "s,t", sreg, AT);
9736 gas_assert (!mips_opts.micromips);
9737 gas_assert (mips_opts.isa == ISA_MIPS1);
9739 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9740 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9743 * Is the double cfc1 instruction a bug in the mips assembler;
9744 * or is there a reason for it?
9747 macro_build (NULL, "cfc1", "t,G", treg, RA);
9748 macro_build (NULL, "cfc1", "t,G", treg, RA);
9749 macro_build (NULL, "nop", "");
9750 expr1.X_add_number = 3;
9751 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9752 expr1.X_add_number = 2;
9753 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9754 macro_build (NULL, "ctc1", "t,G", AT, RA);
9755 macro_build (NULL, "nop", "");
9756 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9758 macro_build (NULL, "ctc1", "t,G", treg, RA);
9759 macro_build (NULL, "nop", "");
9782 off12 = mips_opts.micromips;
9790 off12 = mips_opts.micromips;
9806 off12 = mips_opts.micromips;
9815 off12 = mips_opts.micromips;
9820 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9821 as_bad (_("Operand overflow"));
9824 expr1.X_add_number = 0;
9829 load_address (tempreg, ep, &used_at);
9831 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9832 tempreg, tempreg, breg);
9838 && (offset_expr.X_op != O_constant
9839 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9840 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9844 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9845 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9850 else if (!ust && treg == breg)
9861 if (!target_big_endian)
9862 ep->X_add_number += off;
9864 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9866 macro_build (NULL, s, "t,~(b)",
9867 tempreg, (unsigned long) ep->X_add_number, breg);
9869 if (!target_big_endian)
9870 ep->X_add_number -= off;
9872 ep->X_add_number += off;
9874 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9876 macro_build (NULL, s2, "t,~(b)",
9877 tempreg, (unsigned long) ep->X_add_number, breg);
9879 /* If necessary, move the result in tempreg to the final destination. */
9880 if (!ust && treg != tempreg)
9882 /* Protect second load's delay slot. */
9884 move_register (treg, tempreg);
9890 if (target_big_endian == ust)
9891 ep->X_add_number += off;
9892 tempreg = ust || ab ? treg : AT;
9893 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9895 /* For halfword transfers we need a temporary register to shuffle
9896 bytes. Unfortunately for M_USH_A we have none available before
9897 the next store as AT holds the base address. We deal with this
9898 case by clobbering TREG and then restoring it as with ULH. */
9899 tempreg = ust == ab ? treg : AT;
9901 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9903 if (target_big_endian == ust)
9904 ep->X_add_number -= off;
9906 ep->X_add_number += off;
9907 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9909 /* For M_USH_A re-retrieve the LSB. */
9912 if (target_big_endian)
9913 ep->X_add_number += off;
9915 ep->X_add_number -= off;
9916 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9918 /* For ULH and M_USH_A OR the LSB in. */
9921 tempreg = !ab ? AT : treg;
9922 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9923 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9928 /* FIXME: Check if this is one of the itbl macros, since they
9929 are added dynamically. */
9930 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9933 if (!mips_opts.at && used_at)
9934 as_bad (_("Macro used $at after \".set noat\""));
9937 /* Implement macros in mips16 mode. */
9940 mips16_macro (struct mips_cl_insn *ip)
9943 int xreg, yreg, zreg, tmp;
9946 const char *s, *s2, *s3;
9948 mask = ip->insn_mo->mask;
9950 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
9951 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
9952 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
9954 expr1.X_op = O_constant;
9955 expr1.X_op_symbol = NULL;
9956 expr1.X_add_symbol = NULL;
9957 expr1.X_add_number = 1;
9977 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
9978 expr1.X_add_number = 2;
9979 macro_build (&expr1, "bnez", "x,p", yreg);
9980 macro_build (NULL, "break", "6", 7);
9982 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9983 since that causes an overflow. We should do that as well,
9984 but I don't see how to do the comparisons without a temporary
9987 macro_build (NULL, s, "x", zreg);
10006 start_noreorder ();
10007 macro_build (NULL, s, "0,x,y", xreg, yreg);
10008 expr1.X_add_number = 2;
10009 macro_build (&expr1, "bnez", "x,p", yreg);
10010 macro_build (NULL, "break", "6", 7);
10012 macro_build (NULL, s2, "x", zreg);
10018 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10019 macro_build (NULL, "mflo", "x", zreg);
10027 if (imm_expr.X_op != O_constant)
10028 as_bad (_("Unsupported large constant"));
10029 imm_expr.X_add_number = -imm_expr.X_add_number;
10030 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10034 if (imm_expr.X_op != O_constant)
10035 as_bad (_("Unsupported large constant"));
10036 imm_expr.X_add_number = -imm_expr.X_add_number;
10037 macro_build (&imm_expr, "addiu", "x,k", xreg);
10041 if (imm_expr.X_op != O_constant)
10042 as_bad (_("Unsupported large constant"));
10043 imm_expr.X_add_number = -imm_expr.X_add_number;
10044 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10066 goto do_reverse_branch;
10070 goto do_reverse_branch;
10082 goto do_reverse_branch;
10093 macro_build (NULL, s, "x,y", xreg, yreg);
10094 macro_build (&offset_expr, s2, "p");
10121 goto do_addone_branch_i;
10126 goto do_addone_branch_i;
10141 goto do_addone_branch_i;
10147 do_addone_branch_i:
10148 if (imm_expr.X_op != O_constant)
10149 as_bad (_("Unsupported large constant"));
10150 ++imm_expr.X_add_number;
10153 macro_build (&imm_expr, s, s3, xreg);
10154 macro_build (&offset_expr, s2, "p");
10158 expr1.X_add_number = 0;
10159 macro_build (&expr1, "slti", "x,8", yreg);
10161 move_register (xreg, yreg);
10162 expr1.X_add_number = 2;
10163 macro_build (&expr1, "bteqz", "p");
10164 macro_build (NULL, "neg", "x,w", xreg, xreg);
10168 /* For consistency checking, verify that all bits are specified either
10169 by the match/mask part of the instruction definition, or by the
10172 validate_mips_insn (const struct mips_opcode *opc)
10174 const char *p = opc->args;
10176 unsigned long used_bits = opc->mask;
10178 if ((used_bits & opc->match) != opc->match)
10180 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10181 opc->name, opc->args);
10184 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10194 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10195 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10196 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10197 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10198 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10199 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10200 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10201 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10202 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10203 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10204 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10205 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10206 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10208 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10209 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10210 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10211 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10212 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10213 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10214 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10215 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10216 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10217 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10218 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10219 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10220 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10221 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10222 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10225 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10226 c, opc->name, opc->args);
10230 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10231 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10233 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10234 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10235 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10236 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10238 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10239 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10241 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10242 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10244 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10245 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10246 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10247 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10248 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10249 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10250 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10251 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10252 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10253 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10254 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10255 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10256 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10257 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10258 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10259 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10260 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10262 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10263 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10264 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10265 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10267 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10268 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10269 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10270 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10271 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10272 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10273 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10274 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10275 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10278 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10279 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10280 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10281 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10282 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10285 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10286 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10287 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10288 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10289 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10290 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10291 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10292 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10293 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10294 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10295 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10296 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10297 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10298 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10299 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10300 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10301 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10302 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10303 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10304 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10306 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10307 c, opc->name, opc->args);
10311 if (used_bits != 0xffffffff)
10313 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10314 ~used_bits & 0xffffffff, opc->name, opc->args);
10320 /* For consistency checking, verify that the length implied matches the
10321 major opcode and that all bits are specified either by the match/mask
10322 part of the instruction definition, or by the operand list. */
10325 validate_micromips_insn (const struct mips_opcode *opc)
10327 unsigned long match = opc->match;
10328 unsigned long mask = opc->mask;
10329 const char *p = opc->args;
10330 unsigned long insn_bits;
10331 unsigned long used_bits;
10332 unsigned long major;
10333 unsigned int length;
10337 if ((mask & match) != match)
10339 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10340 opc->name, opc->args);
10343 length = micromips_insn_length (opc);
10344 if (length != 2 && length != 4)
10346 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10347 "%s %s"), length, opc->name, opc->args);
10350 major = match >> (10 + 8 * (length - 2));
10351 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10352 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10354 as_bad (_("Internal error: bad microMIPS opcode "
10355 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10359 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10360 insn_bits = 1 << 4 * length;
10361 insn_bits <<= 4 * length;
10364 #define USE_BITS(field) \
10365 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10376 case 'A': USE_BITS (EXTLSB); break;
10377 case 'B': USE_BITS (INSMSB); break;
10378 case 'C': USE_BITS (EXTMSBD); break;
10379 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10380 case 'E': USE_BITS (EXTLSB); break;
10381 case 'F': USE_BITS (INSMSB); break;
10382 case 'G': USE_BITS (EXTMSBD); break;
10383 case 'H': USE_BITS (EXTMSBD); break;
10385 as_bad (_("Internal error: bad mips opcode "
10386 "(unknown extension operand type `%c%c'): %s %s"),
10387 e, c, opc->name, opc->args);
10395 case 'A': USE_BITS (IMMA); break;
10396 case 'B': USE_BITS (IMMB); break;
10397 case 'C': USE_BITS (IMMC); break;
10398 case 'D': USE_BITS (IMMD); break;
10399 case 'E': USE_BITS (IMME); break;
10400 case 'F': USE_BITS (IMMF); break;
10401 case 'G': USE_BITS (IMMG); break;
10402 case 'H': USE_BITS (IMMH); break;
10403 case 'I': USE_BITS (IMMI); break;
10404 case 'J': USE_BITS (IMMJ); break;
10405 case 'L': USE_BITS (IMML); break;
10406 case 'M': USE_BITS (IMMM); break;
10407 case 'N': USE_BITS (IMMN); break;
10408 case 'O': USE_BITS (IMMO); break;
10409 case 'P': USE_BITS (IMMP); break;
10410 case 'Q': USE_BITS (IMMQ); break;
10411 case 'U': USE_BITS (IMMU); break;
10412 case 'W': USE_BITS (IMMW); break;
10413 case 'X': USE_BITS (IMMX); break;
10414 case 'Y': USE_BITS (IMMY); break;
10417 case 'b': USE_BITS (MB); break;
10418 case 'c': USE_BITS (MC); break;
10419 case 'd': USE_BITS (MD); break;
10420 case 'e': USE_BITS (ME); break;
10421 case 'f': USE_BITS (MF); break;
10422 case 'g': USE_BITS (MG); break;
10423 case 'h': USE_BITS (MH); break;
10424 case 'i': USE_BITS (MI); break;
10425 case 'j': USE_BITS (MJ); break;
10426 case 'l': USE_BITS (ML); break;
10427 case 'm': USE_BITS (MM); break;
10428 case 'n': USE_BITS (MN); break;
10429 case 'p': USE_BITS (MP); break;
10430 case 'q': USE_BITS (MQ); break;
10438 as_bad (_("Internal error: bad mips opcode "
10439 "(unknown extension operand type `%c%c'): %s %s"),
10440 e, c, opc->name, opc->args);
10444 case '.': USE_BITS (OFFSET10); break;
10445 case '1': USE_BITS (STYPE); break;
10446 case '<': USE_BITS (SHAMT); break;
10447 case '>': USE_BITS (SHAMT); break;
10448 case 'B': USE_BITS (CODE10); break;
10449 case 'C': USE_BITS (COPZ); break;
10450 case 'D': USE_BITS (FD); break;
10451 case 'E': USE_BITS (RT); break;
10452 case 'G': USE_BITS (RS); break;
10453 case 'H': USE_BITS (SEL); break;
10454 case 'K': USE_BITS (RS); break;
10455 case 'M': USE_BITS (CCC); break;
10456 case 'N': USE_BITS (BCC); break;
10457 case 'R': USE_BITS (FR); break;
10458 case 'S': USE_BITS (FS); break;
10459 case 'T': USE_BITS (FT); break;
10460 case 'V': USE_BITS (FS); break;
10461 case '\\': USE_BITS (3BITPOS); break;
10462 case 'a': USE_BITS (TARGET); break;
10463 case 'b': USE_BITS (RS); break;
10464 case 'c': USE_BITS (CODE); break;
10465 case 'd': USE_BITS (RD); break;
10466 case 'h': USE_BITS (PREFX); break;
10467 case 'i': USE_BITS (IMMEDIATE); break;
10468 case 'j': USE_BITS (DELTA); break;
10469 case 'k': USE_BITS (CACHE); break;
10470 case 'n': USE_BITS (RT); break;
10471 case 'o': USE_BITS (DELTA); break;
10472 case 'p': USE_BITS (DELTA); break;
10473 case 'q': USE_BITS (CODE2); break;
10474 case 'r': USE_BITS (RS); break;
10475 case 's': USE_BITS (RS); break;
10476 case 't': USE_BITS (RT); break;
10477 case 'u': USE_BITS (IMMEDIATE); break;
10478 case 'v': USE_BITS (RS); break;
10479 case 'w': USE_BITS (RT); break;
10480 case 'y': USE_BITS (RS3); break;
10482 case '|': USE_BITS (TRAP); break;
10483 case '~': USE_BITS (OFFSET12); break;
10485 as_bad (_("Internal error: bad microMIPS opcode "
10486 "(unknown operand type `%c'): %s %s"),
10487 c, opc->name, opc->args);
10491 if (used_bits != insn_bits)
10493 if (~used_bits & insn_bits)
10494 as_bad (_("Internal error: bad microMIPS opcode "
10495 "(bits 0x%lx undefined): %s %s"),
10496 ~used_bits & insn_bits, opc->name, opc->args);
10497 if (used_bits & ~insn_bits)
10498 as_bad (_("Internal error: bad microMIPS opcode "
10499 "(bits 0x%lx defined): %s %s"),
10500 used_bits & ~insn_bits, opc->name, opc->args);
10506 /* UDI immediates. */
10507 struct mips_immed {
10509 unsigned int shift;
10510 unsigned long mask;
10514 static const struct mips_immed mips_immed[] = {
10515 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10516 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10517 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10518 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10522 /* Check whether an odd floating-point register is allowed. */
10524 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10526 const char *s = insn->name;
10528 if (insn->pinfo == INSN_MACRO)
10529 /* Let a macro pass, we'll catch it later when it is expanded. */
10532 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10534 /* Allow odd registers for single-precision ops. */
10535 switch (insn->pinfo & (FP_S | FP_D))
10539 return 1; /* both single precision - ok */
10541 return 0; /* both double precision - fail */
10546 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10547 s = strchr (insn->name, '.');
10549 s = s != NULL ? strchr (s + 1, '.') : NULL;
10550 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10553 /* Single-precision coprocessor loads and moves are OK too. */
10554 if ((insn->pinfo & FP_S)
10555 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10556 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10562 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10563 taking bits from BIT up. */
10565 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10567 return (ep->X_op == O_constant
10568 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10569 && ep->X_add_number >= min << bit
10570 && ep->X_add_number < max << bit);
10573 /* This routine assembles an instruction into its binary format. As a
10574 side effect, it sets one of the global variables imm_reloc or
10575 offset_reloc to the type of relocation to do if one of the operands
10576 is an address expression. */
10579 mips_ip (char *str, struct mips_cl_insn *ip)
10581 bfd_boolean wrong_delay_slot_insns = FALSE;
10582 bfd_boolean need_delay_slot_ok = TRUE;
10583 struct mips_opcode *firstinsn = NULL;
10584 const struct mips_opcode *past;
10585 struct hash_control *hash;
10589 struct mips_opcode *insn;
10591 unsigned int regno;
10592 unsigned int lastregno;
10593 unsigned int destregno = 0;
10594 unsigned int lastpos = 0;
10595 unsigned int limlo, limhi;
10597 offsetT min_range, max_range;
10601 unsigned int rtype;
10607 if (mips_opts.micromips)
10609 hash = micromips_op_hash;
10610 past = µmips_opcodes[bfd_micromips_num_opcodes];
10615 past = &mips_opcodes[NUMOPCODES];
10617 forced_insn_length = 0;
10620 /* We first try to match an instruction up to a space or to the end. */
10621 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10624 /* Make a copy of the instruction so that we can fiddle with it. */
10625 name = alloca (end + 1);
10626 memcpy (name, str, end);
10631 insn = (struct mips_opcode *) hash_find (hash, name);
10633 if (insn != NULL || !mips_opts.micromips)
10635 if (forced_insn_length)
10638 /* See if there's an instruction size override suffix,
10639 either `16' or `32', at the end of the mnemonic proper,
10640 that defines the operation, i.e. before the first `.'
10641 character if any. Strip it and retry. */
10642 dot = strchr (name, '.');
10643 opend = dot != NULL ? dot - name : end;
10646 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10647 forced_insn_length = 2;
10648 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10649 forced_insn_length = 4;
10652 memcpy (name + opend - 2, name + opend, end - opend + 1);
10656 insn_error = _("Unrecognized opcode");
10660 /* For microMIPS instructions placed in a fixed-length branch delay slot
10661 we make up to two passes over the relevant fragment of the opcode
10662 table. First we try instructions that meet the delay slot's length
10663 requirement. If none matched, then we retry with the remaining ones
10664 and if one matches, then we use it and then issue an appropriate
10665 warning later on. */
10666 argsStart = s = str + end;
10669 bfd_boolean delay_slot_ok;
10670 bfd_boolean size_ok;
10673 gas_assert (strcmp (insn->name, name) == 0);
10675 ok = is_opcode_valid (insn);
10676 size_ok = is_size_valid (insn);
10677 delay_slot_ok = is_delay_slot_valid (insn);
10678 if (!delay_slot_ok && !wrong_delay_slot_insns)
10681 wrong_delay_slot_insns = TRUE;
10683 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10685 static char buf[256];
10687 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10692 if (wrong_delay_slot_insns && need_delay_slot_ok)
10694 gas_assert (firstinsn);
10695 need_delay_slot_ok = FALSE;
10705 sprintf (buf, _("opcode not supported on this processor: %s (%s)"),
10706 mips_cpu_info_from_arch (mips_opts.arch)->name,
10707 mips_cpu_info_from_isa (mips_opts.isa)->name);
10709 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10710 8 * forced_insn_length);
10716 create_insn (ip, insn);
10719 lastregno = 0xffffffff;
10720 for (args = insn->args;; ++args)
10724 s += strspn (s, " \t");
10728 case '\0': /* end of args */
10733 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
10734 gas_assert (!mips_opts.micromips);
10735 my_getExpression (&imm_expr, s);
10736 check_absolute_expr (ip, &imm_expr);
10737 if ((unsigned long) imm_expr.X_add_number != 1
10738 && (unsigned long) imm_expr.X_add_number != 3)
10740 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10741 (unsigned long) imm_expr.X_add_number);
10743 INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number);
10744 imm_expr.X_op = O_absent;
10748 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
10749 gas_assert (!mips_opts.micromips);
10750 my_getExpression (&imm_expr, s);
10751 check_absolute_expr (ip, &imm_expr);
10752 if (imm_expr.X_add_number & ~OP_MASK_SA3)
10754 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10755 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
10757 INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number);
10758 imm_expr.X_op = O_absent;
10762 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
10763 gas_assert (!mips_opts.micromips);
10764 my_getExpression (&imm_expr, s);
10765 check_absolute_expr (ip, &imm_expr);
10766 if (imm_expr.X_add_number & ~OP_MASK_SA4)
10768 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10769 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
10771 INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number);
10772 imm_expr.X_op = O_absent;
10776 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
10777 gas_assert (!mips_opts.micromips);
10778 my_getExpression (&imm_expr, s);
10779 check_absolute_expr (ip, &imm_expr);
10780 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
10782 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10783 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
10785 INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number);
10786 imm_expr.X_op = O_absent;
10790 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
10791 gas_assert (!mips_opts.micromips);
10792 my_getExpression (&imm_expr, s);
10793 check_absolute_expr (ip, &imm_expr);
10794 if (imm_expr.X_add_number & ~OP_MASK_RS)
10796 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10797 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
10799 INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number);
10800 imm_expr.X_op = O_absent;
10804 case '7': /* Four DSP accumulators in bits 11,12. */
10805 gas_assert (!mips_opts.micromips);
10806 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10807 s[3] >= '0' && s[3] <= '3')
10809 regno = s[3] - '0';
10811 INSERT_OPERAND (0, DSPACC, *ip, regno);
10815 as_bad (_("Invalid dsp acc register"));
10818 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
10819 gas_assert (!mips_opts.micromips);
10820 my_getExpression (&imm_expr, s);
10821 check_absolute_expr (ip, &imm_expr);
10822 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
10824 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10826 (unsigned long) imm_expr.X_add_number);
10828 INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number);
10829 imm_expr.X_op = O_absent;
10833 case '9': /* Four DSP accumulators in bits 21,22. */
10834 gas_assert (!mips_opts.micromips);
10835 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10836 s[3] >= '0' && s[3] <= '3')
10838 regno = s[3] - '0';
10840 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10844 as_bad (_("Invalid dsp acc register"));
10847 case '0': /* DSP 6-bit signed immediate in bit 20. */
10848 gas_assert (!mips_opts.micromips);
10849 my_getExpression (&imm_expr, s);
10850 check_absolute_expr (ip, &imm_expr);
10851 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
10852 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
10853 if (imm_expr.X_add_number < min_range ||
10854 imm_expr.X_add_number > max_range)
10856 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10857 (long) min_range, (long) max_range,
10858 (long) imm_expr.X_add_number);
10860 INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number);
10861 imm_expr.X_op = O_absent;
10865 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10866 gas_assert (!mips_opts.micromips);
10867 my_getExpression (&imm_expr, s);
10868 check_absolute_expr (ip, &imm_expr);
10869 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10871 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10873 (unsigned long) imm_expr.X_add_number);
10875 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
10876 imm_expr.X_op = O_absent;
10880 case ':': /* DSP 7-bit signed immediate in bit 19. */
10881 gas_assert (!mips_opts.micromips);
10882 my_getExpression (&imm_expr, s);
10883 check_absolute_expr (ip, &imm_expr);
10884 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10885 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10886 if (imm_expr.X_add_number < min_range ||
10887 imm_expr.X_add_number > max_range)
10889 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10890 (long) min_range, (long) max_range,
10891 (long) imm_expr.X_add_number);
10893 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
10894 imm_expr.X_op = O_absent;
10898 case '@': /* DSP 10-bit signed immediate in bit 16. */
10899 gas_assert (!mips_opts.micromips);
10900 my_getExpression (&imm_expr, s);
10901 check_absolute_expr (ip, &imm_expr);
10902 min_range = -((OP_MASK_IMM10 + 1) >> 1);
10903 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
10904 if (imm_expr.X_add_number < min_range ||
10905 imm_expr.X_add_number > max_range)
10907 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10908 (long) min_range, (long) max_range,
10909 (long) imm_expr.X_add_number);
10911 INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number);
10912 imm_expr.X_op = O_absent;
10916 case '!': /* MT usermode flag bit. */
10917 gas_assert (!mips_opts.micromips);
10918 my_getExpression (&imm_expr, s);
10919 check_absolute_expr (ip, &imm_expr);
10920 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
10921 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10922 (unsigned long) imm_expr.X_add_number);
10923 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
10924 imm_expr.X_op = O_absent;
10928 case '$': /* MT load high flag bit. */
10929 gas_assert (!mips_opts.micromips);
10930 my_getExpression (&imm_expr, s);
10931 check_absolute_expr (ip, &imm_expr);
10932 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
10933 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10934 (unsigned long) imm_expr.X_add_number);
10935 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
10936 imm_expr.X_op = O_absent;
10940 case '*': /* Four DSP accumulators in bits 18,19. */
10941 gas_assert (!mips_opts.micromips);
10942 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10943 s[3] >= '0' && s[3] <= '3')
10945 regno = s[3] - '0';
10947 INSERT_OPERAND (0, MTACC_T, *ip, regno);
10951 as_bad (_("Invalid dsp/smartmips acc register"));
10954 case '&': /* Four DSP accumulators in bits 13,14. */
10955 gas_assert (!mips_opts.micromips);
10956 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10957 s[3] >= '0' && s[3] <= '3')
10959 regno = s[3] - '0';
10961 INSERT_OPERAND (0, MTACC_D, *ip, regno);
10965 as_bad (_("Invalid dsp/smartmips acc register"));
10968 case '\\': /* 3-bit bit position. */
10970 unsigned long mask = (!mips_opts.micromips
10972 : MICROMIPSOP_MASK_3BITPOS);
10974 my_getExpression (&imm_expr, s);
10975 check_absolute_expr (ip, &imm_expr);
10976 if ((unsigned long) imm_expr.X_add_number > mask)
10977 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
10979 mask, (unsigned long) imm_expr.X_add_number);
10980 INSERT_OPERAND (mips_opts.micromips,
10981 3BITPOS, *ip, imm_expr.X_add_number);
10982 imm_expr.X_op = O_absent;
10996 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11000 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11004 gas_assert (!mips_opts.micromips);
11005 INSERT_OPERAND (0, FT, *ip, lastregno);
11009 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11015 /* Handle optional base register.
11016 Either the base register is omitted or
11017 we must have a left paren. */
11018 /* This is dependent on the next operand specifier
11019 is a base register specification. */
11020 gas_assert (args[1] == 'b'
11021 || (mips_opts.micromips
11023 && (args[2] == 'l' || args[2] == 'n'
11024 || args[2] == 's' || args[2] == 'a')));
11025 if (*s == '\0' && args[1] == 'b')
11027 /* Fall through. */
11029 case ')': /* These must match exactly. */
11034 case '[': /* These must match exactly. */
11036 gas_assert (!mips_opts.micromips);
11041 case '+': /* Opcode extension character. */
11044 case '1': /* UDI immediates. */
11048 gas_assert (!mips_opts.micromips);
11050 const struct mips_immed *imm = mips_immed;
11052 while (imm->type && imm->type != *args)
11056 my_getExpression (&imm_expr, s);
11057 check_absolute_expr (ip, &imm_expr);
11058 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11060 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11061 imm->desc ? imm->desc : ip->insn_mo->name,
11062 (unsigned long) imm_expr.X_add_number,
11063 (unsigned long) imm_expr.X_add_number);
11064 imm_expr.X_add_number &= imm->mask;
11066 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11068 imm_expr.X_op = O_absent;
11073 case 'A': /* ins/ext position, becomes LSB. */
11082 my_getExpression (&imm_expr, s);
11083 check_absolute_expr (ip, &imm_expr);
11084 if ((unsigned long) imm_expr.X_add_number < limlo
11085 || (unsigned long) imm_expr.X_add_number > limhi)
11087 as_bad (_("Improper position (%lu)"),
11088 (unsigned long) imm_expr.X_add_number);
11089 imm_expr.X_add_number = limlo;
11091 lastpos = imm_expr.X_add_number;
11092 INSERT_OPERAND (mips_opts.micromips,
11093 EXTLSB, *ip, imm_expr.X_add_number);
11094 imm_expr.X_op = O_absent;
11098 case 'B': /* ins size, becomes MSB. */
11107 my_getExpression (&imm_expr, s);
11108 check_absolute_expr (ip, &imm_expr);
11109 /* Check for negative input so that small negative numbers
11110 will not succeed incorrectly. The checks against
11111 (pos+size) transitively check "size" itself,
11112 assuming that "pos" is reasonable. */
11113 if ((long) imm_expr.X_add_number < 0
11114 || ((unsigned long) imm_expr.X_add_number
11116 || ((unsigned long) imm_expr.X_add_number
11117 + lastpos) > limhi)
11119 as_bad (_("Improper insert size (%lu, position %lu)"),
11120 (unsigned long) imm_expr.X_add_number,
11121 (unsigned long) lastpos);
11122 imm_expr.X_add_number = limlo - lastpos;
11124 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11125 lastpos + imm_expr.X_add_number - 1);
11126 imm_expr.X_op = O_absent;
11130 case 'C': /* ext size, becomes MSBD. */
11143 my_getExpression (&imm_expr, s);
11144 check_absolute_expr (ip, &imm_expr);
11145 /* Check for negative input so that small negative numbers
11146 will not succeed incorrectly. The checks against
11147 (pos+size) transitively check "size" itself,
11148 assuming that "pos" is reasonable. */
11149 if ((long) imm_expr.X_add_number < 0
11150 || ((unsigned long) imm_expr.X_add_number
11152 || ((unsigned long) imm_expr.X_add_number
11153 + lastpos) > limhi)
11155 as_bad (_("Improper extract size (%lu, position %lu)"),
11156 (unsigned long) imm_expr.X_add_number,
11157 (unsigned long) lastpos);
11158 imm_expr.X_add_number = limlo - lastpos;
11160 INSERT_OPERAND (mips_opts.micromips,
11161 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11162 imm_expr.X_op = O_absent;
11167 /* +D is for disassembly only; never match. */
11171 /* "+I" is like "I", except that imm2_expr is used. */
11172 my_getExpression (&imm2_expr, s);
11173 if (imm2_expr.X_op != O_big
11174 && imm2_expr.X_op != O_constant)
11175 insn_error = _("absolute expression required");
11176 if (HAVE_32BIT_GPRS)
11177 normalize_constant_expr (&imm2_expr);
11181 case 'T': /* Coprocessor register. */
11182 gas_assert (!mips_opts.micromips);
11183 /* +T is for disassembly only; never match. */
11186 case 't': /* Coprocessor register number. */
11187 gas_assert (!mips_opts.micromips);
11188 if (s[0] == '$' && ISDIGIT (s[1]))
11198 while (ISDIGIT (*s));
11200 as_bad (_("Invalid register number (%d)"), regno);
11203 INSERT_OPERAND (0, RT, *ip, regno);
11208 as_bad (_("Invalid coprocessor 0 register number"));
11212 /* bbit[01] and bbit[01]32 bit index. Give error if index
11213 is not in the valid range. */
11214 gas_assert (!mips_opts.micromips);
11215 my_getExpression (&imm_expr, s);
11216 check_absolute_expr (ip, &imm_expr);
11217 if ((unsigned) imm_expr.X_add_number > 31)
11219 as_bad (_("Improper bit index (%lu)"),
11220 (unsigned long) imm_expr.X_add_number);
11221 imm_expr.X_add_number = 0;
11223 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11224 imm_expr.X_op = O_absent;
11229 /* bbit[01] bit index when bbit is used but we generate
11230 bbit[01]32 because the index is over 32. Move to the
11231 next candidate if index is not in the valid range. */
11232 gas_assert (!mips_opts.micromips);
11233 my_getExpression (&imm_expr, s);
11234 check_absolute_expr (ip, &imm_expr);
11235 if ((unsigned) imm_expr.X_add_number < 32
11236 || (unsigned) imm_expr.X_add_number > 63)
11238 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11239 imm_expr.X_op = O_absent;
11244 /* cins, cins32, exts and exts32 position field. Give error
11245 if it's not in the valid range. */
11246 gas_assert (!mips_opts.micromips);
11247 my_getExpression (&imm_expr, s);
11248 check_absolute_expr (ip, &imm_expr);
11249 if ((unsigned) imm_expr.X_add_number > 31)
11251 as_bad (_("Improper position (%lu)"),
11252 (unsigned long) imm_expr.X_add_number);
11253 imm_expr.X_add_number = 0;
11255 /* Make the pos explicit to simplify +S. */
11256 lastpos = imm_expr.X_add_number + 32;
11257 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11258 imm_expr.X_op = O_absent;
11263 /* cins, cins32, exts and exts32 position field. Move to
11264 the next candidate if it's not in the valid range. */
11265 gas_assert (!mips_opts.micromips);
11266 my_getExpression (&imm_expr, s);
11267 check_absolute_expr (ip, &imm_expr);
11268 if ((unsigned) imm_expr.X_add_number < 32
11269 || (unsigned) imm_expr.X_add_number > 63)
11271 lastpos = imm_expr.X_add_number;
11272 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11273 imm_expr.X_op = O_absent;
11278 /* cins and exts length-minus-one field. */
11279 gas_assert (!mips_opts.micromips);
11280 my_getExpression (&imm_expr, s);
11281 check_absolute_expr (ip, &imm_expr);
11282 if ((unsigned long) imm_expr.X_add_number > 31)
11284 as_bad (_("Improper size (%lu)"),
11285 (unsigned long) imm_expr.X_add_number);
11286 imm_expr.X_add_number = 0;
11288 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11289 imm_expr.X_op = O_absent;
11294 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11295 length-minus-one field. */
11296 gas_assert (!mips_opts.micromips);
11297 my_getExpression (&imm_expr, s);
11298 check_absolute_expr (ip, &imm_expr);
11299 if ((long) imm_expr.X_add_number < 0
11300 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11302 as_bad (_("Improper size (%lu)"),
11303 (unsigned long) imm_expr.X_add_number);
11304 imm_expr.X_add_number = 0;
11306 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11307 imm_expr.X_op = O_absent;
11312 /* seqi/snei immediate field. */
11313 gas_assert (!mips_opts.micromips);
11314 my_getExpression (&imm_expr, s);
11315 check_absolute_expr (ip, &imm_expr);
11316 if ((long) imm_expr.X_add_number < -512
11317 || (long) imm_expr.X_add_number >= 512)
11319 as_bad (_("Improper immediate (%ld)"),
11320 (long) imm_expr.X_add_number);
11321 imm_expr.X_add_number = 0;
11323 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11324 imm_expr.X_op = O_absent;
11328 case 'a': /* 8-bit signed offset in bit 6 */
11329 gas_assert (!mips_opts.micromips);
11330 my_getExpression (&imm_expr, s);
11331 check_absolute_expr (ip, &imm_expr);
11332 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11333 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11334 if (imm_expr.X_add_number < min_range
11335 || imm_expr.X_add_number > max_range)
11337 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11338 (long) min_range, (long) max_range,
11339 (long) imm_expr.X_add_number);
11341 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11342 imm_expr.X_op = O_absent;
11346 case 'b': /* 8-bit signed offset in bit 3 */
11347 gas_assert (!mips_opts.micromips);
11348 my_getExpression (&imm_expr, s);
11349 check_absolute_expr (ip, &imm_expr);
11350 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11351 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11352 if (imm_expr.X_add_number < min_range
11353 || imm_expr.X_add_number > max_range)
11355 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11356 (long) min_range, (long) max_range,
11357 (long) imm_expr.X_add_number);
11359 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11360 imm_expr.X_op = O_absent;
11364 case 'c': /* 9-bit signed offset in bit 6 */
11365 gas_assert (!mips_opts.micromips);
11366 my_getExpression (&imm_expr, s);
11367 check_absolute_expr (ip, &imm_expr);
11368 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11369 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11370 /* We check the offset range before adjusted. */
11373 if (imm_expr.X_add_number < min_range
11374 || imm_expr.X_add_number > max_range)
11376 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11377 (long) min_range, (long) max_range,
11378 (long) imm_expr.X_add_number);
11380 if (imm_expr.X_add_number & 0xf)
11382 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11383 (long) imm_expr.X_add_number);
11385 /* Right shift 4 bits to adjust the offset operand. */
11386 INSERT_OPERAND (0, OFFSET_C, *ip,
11387 imm_expr.X_add_number >> 4);
11388 imm_expr.X_op = O_absent;
11393 gas_assert (!mips_opts.micromips);
11394 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11396 if (regno == AT && mips_opts.at)
11398 if (mips_opts.at == ATREG)
11399 as_warn (_("used $at without \".set noat\""));
11401 as_warn (_("used $%u with \".set at=$%u\""),
11402 regno, mips_opts.at);
11404 INSERT_OPERAND (0, RZ, *ip, regno);
11408 gas_assert (!mips_opts.micromips);
11409 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11411 INSERT_OPERAND (0, FZ, *ip, regno);
11415 as_bad (_("Internal error: bad %s opcode "
11416 "(unknown extension operand type `+%c'): %s %s"),
11417 mips_opts.micromips ? "microMIPS" : "MIPS",
11418 *args, insn->name, insn->args);
11419 /* Further processing is fruitless. */
11424 case '.': /* 10-bit offset. */
11425 gas_assert (mips_opts.micromips);
11426 case '~': /* 12-bit offset. */
11428 int shift = *args == '.' ? 9 : 11;
11431 /* Check whether there is only a single bracketed expression
11432 left. If so, it must be the base register and the
11433 constant must be zero. */
11434 if (*s == '(' && strchr (s + 1, '(') == 0)
11437 /* If this value won't fit into the offset, then go find
11438 a macro that will generate a 16- or 32-bit offset code
11440 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11441 if ((i == 0 && (imm_expr.X_op != O_constant
11442 || imm_expr.X_add_number >= 1 << shift
11443 || imm_expr.X_add_number < -1 << shift))
11446 imm_expr.X_op = O_absent;
11450 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11452 INSERT_OPERAND (mips_opts.micromips,
11453 OFFSET12, *ip, imm_expr.X_add_number);
11454 imm_expr.X_op = O_absent;
11459 case '<': /* must be at least one digit */
11461 * According to the manual, if the shift amount is greater
11462 * than 31 or less than 0, then the shift amount should be
11463 * mod 32. In reality the mips assembler issues an error.
11464 * We issue a warning and mask out all but the low 5 bits.
11466 my_getExpression (&imm_expr, s);
11467 check_absolute_expr (ip, &imm_expr);
11468 if ((unsigned long) imm_expr.X_add_number > 31)
11469 as_warn (_("Improper shift amount (%lu)"),
11470 (unsigned long) imm_expr.X_add_number);
11471 INSERT_OPERAND (mips_opts.micromips,
11472 SHAMT, *ip, imm_expr.X_add_number);
11473 imm_expr.X_op = O_absent;
11477 case '>': /* shift amount minus 32 */
11478 my_getExpression (&imm_expr, s);
11479 check_absolute_expr (ip, &imm_expr);
11480 if ((unsigned long) imm_expr.X_add_number < 32
11481 || (unsigned long) imm_expr.X_add_number > 63)
11483 INSERT_OPERAND (mips_opts.micromips,
11484 SHAMT, *ip, imm_expr.X_add_number - 32);
11485 imm_expr.X_op = O_absent;
11489 case 'k': /* CACHE code. */
11490 case 'h': /* PREFX code. */
11491 case '1': /* SYNC type. */
11492 my_getExpression (&imm_expr, s);
11493 check_absolute_expr (ip, &imm_expr);
11494 if ((unsigned long) imm_expr.X_add_number > 31)
11495 as_warn (_("Invalid value for `%s' (%lu)"),
11497 (unsigned long) imm_expr.X_add_number);
11501 if (mips_fix_cn63xxp1
11502 && !mips_opts.micromips
11503 && strcmp ("pref", insn->name) == 0)
11504 switch (imm_expr.X_add_number)
11513 case 31: /* These are ok. */
11516 default: /* The rest must be changed to 28. */
11517 imm_expr.X_add_number = 28;
11520 INSERT_OPERAND (mips_opts.micromips,
11521 CACHE, *ip, imm_expr.X_add_number);
11524 INSERT_OPERAND (mips_opts.micromips,
11525 PREFX, *ip, imm_expr.X_add_number);
11528 INSERT_OPERAND (mips_opts.micromips,
11529 STYPE, *ip, imm_expr.X_add_number);
11532 imm_expr.X_op = O_absent;
11536 case 'c': /* BREAK code. */
11538 unsigned long mask = (mips_opts.micromips
11539 ? MICROMIPSOP_MASK_CODE
11542 my_getExpression (&imm_expr, s);
11543 check_absolute_expr (ip, &imm_expr);
11544 if ((unsigned long) imm_expr.X_add_number > mask)
11545 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11547 mask, (unsigned long) imm_expr.X_add_number);
11548 INSERT_OPERAND (mips_opts.micromips,
11549 CODE, *ip, imm_expr.X_add_number);
11550 imm_expr.X_op = O_absent;
11555 case 'q': /* Lower BREAK code. */
11557 unsigned long mask = (mips_opts.micromips
11558 ? MICROMIPSOP_MASK_CODE2
11561 my_getExpression (&imm_expr, s);
11562 check_absolute_expr (ip, &imm_expr);
11563 if ((unsigned long) imm_expr.X_add_number > mask)
11564 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11566 mask, (unsigned long) imm_expr.X_add_number);
11567 INSERT_OPERAND (mips_opts.micromips,
11568 CODE2, *ip, imm_expr.X_add_number);
11569 imm_expr.X_op = O_absent;
11574 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11576 unsigned long mask = (mips_opts.micromips
11577 ? MICROMIPSOP_MASK_CODE10
11580 my_getExpression (&imm_expr, s);
11581 check_absolute_expr (ip, &imm_expr);
11582 if ((unsigned long) imm_expr.X_add_number > mask)
11583 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11585 mask, (unsigned long) imm_expr.X_add_number);
11586 if (mips_opts.micromips)
11587 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11589 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11590 imm_expr.X_op = O_absent;
11595 case 'C': /* 25- or 23-bit coprocessor code. */
11597 unsigned long mask = (mips_opts.micromips
11598 ? MICROMIPSOP_MASK_COPZ
11601 my_getExpression (&imm_expr, s);
11602 check_absolute_expr (ip, &imm_expr);
11603 if ((unsigned long) imm_expr.X_add_number > mask)
11604 as_warn (_("Coproccesor code > %u bits (%lu)"),
11605 mips_opts.micromips ? 23U : 25U,
11606 (unsigned long) imm_expr.X_add_number);
11607 INSERT_OPERAND (mips_opts.micromips,
11608 COPZ, *ip, imm_expr.X_add_number);
11609 imm_expr.X_op = O_absent;
11614 case 'J': /* 19-bit WAIT code. */
11615 gas_assert (!mips_opts.micromips);
11616 my_getExpression (&imm_expr, s);
11617 check_absolute_expr (ip, &imm_expr);
11618 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11620 as_warn (_("Illegal 19-bit code (%lu)"),
11621 (unsigned long) imm_expr.X_add_number);
11622 imm_expr.X_add_number &= OP_MASK_CODE19;
11624 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11625 imm_expr.X_op = O_absent;
11629 case 'P': /* Performance register. */
11630 gas_assert (!mips_opts.micromips);
11631 my_getExpression (&imm_expr, s);
11632 check_absolute_expr (ip, &imm_expr);
11633 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11634 as_warn (_("Invalid performance register (%lu)"),
11635 (unsigned long) imm_expr.X_add_number);
11636 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11637 imm_expr.X_op = O_absent;
11641 case 'G': /* Coprocessor destination register. */
11643 unsigned long opcode = ip->insn_opcode;
11644 unsigned long mask;
11645 unsigned int types;
11648 if (mips_opts.micromips)
11650 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11651 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11652 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11656 case 0x000000fc: /* mfc0 */
11657 case 0x000002fc: /* mtc0 */
11658 case 0x580000fc: /* dmfc0 */
11659 case 0x580002fc: /* dmtc0 */
11669 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11670 cop0 = opcode == OP_OP_COP0;
11672 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11673 ok = reg_lookup (&s, types, ®no);
11674 if (mips_opts.micromips)
11675 INSERT_OPERAND (1, RS, *ip, regno);
11677 INSERT_OPERAND (0, RD, *ip, regno);
11686 case 'y': /* ALNV.PS source register. */
11687 gas_assert (mips_opts.micromips);
11689 case 'x': /* Ignore register name. */
11690 case 'U': /* Destination register (CLO/CLZ). */
11691 case 'g': /* Coprocessor destination register. */
11692 gas_assert (!mips_opts.micromips);
11693 case 'b': /* Base register. */
11694 case 'd': /* Destination register. */
11695 case 's': /* Source register. */
11696 case 't': /* Target register. */
11697 case 'r': /* Both target and source. */
11698 case 'v': /* Both dest and source. */
11699 case 'w': /* Both dest and target. */
11700 case 'E': /* Coprocessor target register. */
11701 case 'K': /* RDHWR destination register. */
11702 case 'z': /* Must be zero register. */
11705 if (*args == 'E' || *args == 'K')
11706 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11709 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11710 if (regno == AT && mips_opts.at)
11712 if (mips_opts.at == ATREG)
11713 as_warn (_("Used $at without \".set noat\""));
11715 as_warn (_("Used $%u with \".set at=$%u\""),
11716 regno, mips_opts.at);
11726 if (c == 'r' || c == 'v' || c == 'w')
11733 /* 'z' only matches $0. */
11734 if (c == 'z' && regno != 0)
11737 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11739 if (regno == lastregno)
11742 = _("Source and destination must be different");
11745 if (regno == 31 && lastregno == 0xffffffff)
11748 = _("A destination register must be supplied");
11752 /* Now that we have assembled one operand, we use the args
11753 string to figure out where it goes in the instruction. */
11760 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11764 if (mips_opts.micromips)
11765 INSERT_OPERAND (1, RS, *ip, regno);
11767 INSERT_OPERAND (0, RD, *ip, regno);
11772 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11776 gas_assert (!mips_opts.micromips);
11777 INSERT_OPERAND (0, RD, *ip, regno);
11778 INSERT_OPERAND (0, RT, *ip, regno);
11784 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11788 gas_assert (mips_opts.micromips);
11789 INSERT_OPERAND (1, RS3, *ip, regno);
11793 /* This case exists because on the r3000 trunc
11794 expands into a macro which requires a gp
11795 register. On the r6000 or r4000 it is
11796 assembled into a single instruction which
11797 ignores the register. Thus the insn version
11798 is MIPS_ISA2 and uses 'x', and the macro
11799 version is MIPS_ISA1 and uses 't'. */
11803 /* This case is for the div instruction, which
11804 acts differently if the destination argument
11805 is $0. This only matches $0, and is checked
11806 outside the switch. */
11816 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11820 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11825 case 'O': /* MDMX alignment immediate constant. */
11826 gas_assert (!mips_opts.micromips);
11827 my_getExpression (&imm_expr, s);
11828 check_absolute_expr (ip, &imm_expr);
11829 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11830 as_warn (_("Improper align amount (%ld), using low bits"),
11831 (long) imm_expr.X_add_number);
11832 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11833 imm_expr.X_op = O_absent;
11837 case 'Q': /* MDMX vector, element sel, or const. */
11840 /* MDMX Immediate. */
11841 gas_assert (!mips_opts.micromips);
11842 my_getExpression (&imm_expr, s);
11843 check_absolute_expr (ip, &imm_expr);
11844 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
11845 as_warn (_("Invalid MDMX Immediate (%ld)"),
11846 (long) imm_expr.X_add_number);
11847 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
11848 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11849 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11851 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
11852 imm_expr.X_op = O_absent;
11856 /* Not MDMX Immediate. Fall through. */
11857 case 'X': /* MDMX destination register. */
11858 case 'Y': /* MDMX source register. */
11859 case 'Z': /* MDMX target register. */
11862 gas_assert (!mips_opts.micromips);
11863 case 'D': /* Floating point destination register. */
11864 case 'S': /* Floating point source register. */
11865 case 'T': /* Floating point target register. */
11866 case 'R': /* Floating point source register. */
11870 || (mips_opts.ase_mdmx
11871 && (ip->insn_mo->pinfo & FP_D)
11872 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11873 | INSN_COPROC_MEMORY_DELAY
11874 | INSN_LOAD_COPROC_DELAY
11875 | INSN_LOAD_MEMORY_DELAY
11876 | INSN_STORE_MEMORY))))
11877 rtype |= RTYPE_VEC;
11879 if (reg_lookup (&s, rtype, ®no))
11881 if ((regno & 1) != 0
11883 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
11884 as_warn (_("Float register should be even, was %d"),
11892 if (c == 'V' || c == 'W')
11903 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
11909 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
11913 /* This is like 'Z', but also needs to fix the MDMX
11914 vector/scalar select bits. Note that the
11915 scalar immediate case is handled above. */
11918 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
11919 int max_el = (is_qh ? 3 : 7);
11921 my_getExpression(&imm_expr, s);
11922 check_absolute_expr (ip, &imm_expr);
11924 if (imm_expr.X_add_number > max_el)
11925 as_bad (_("Bad element selector %ld"),
11926 (long) imm_expr.X_add_number);
11927 imm_expr.X_add_number &= max_el;
11928 ip->insn_opcode |= (imm_expr.X_add_number
11931 imm_expr.X_op = O_absent;
11933 as_warn (_("Expecting ']' found '%s'"), s);
11939 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11940 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
11943 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
11946 /* Fall through. */
11950 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
11954 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
11964 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11968 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
11974 my_getExpression (&imm_expr, s);
11975 if (imm_expr.X_op != O_big
11976 && imm_expr.X_op != O_constant)
11977 insn_error = _("absolute expression required");
11978 if (HAVE_32BIT_GPRS)
11979 normalize_constant_expr (&imm_expr);
11984 my_getExpression (&offset_expr, s);
11985 normalize_address_expr (&offset_expr);
11986 *imm_reloc = BFD_RELOC_32;
11999 unsigned char temp[8];
12001 unsigned int length;
12006 /* These only appear as the last operand in an
12007 instruction, and every instruction that accepts
12008 them in any variant accepts them in all variants.
12009 This means we don't have to worry about backing out
12010 any changes if the instruction does not match.
12012 The difference between them is the size of the
12013 floating point constant and where it goes. For 'F'
12014 and 'L' the constant is 64 bits; for 'f' and 'l' it
12015 is 32 bits. Where the constant is placed is based
12016 on how the MIPS assembler does things:
12019 f -- immediate value
12022 The .lit4 and .lit8 sections are only used if
12023 permitted by the -G argument.
12025 The code below needs to know whether the target register
12026 is 32 or 64 bits wide. It relies on the fact 'f' and
12027 'F' are used with GPR-based instructions and 'l' and
12028 'L' are used with FPR-based instructions. */
12030 f64 = *args == 'F' || *args == 'L';
12031 using_gprs = *args == 'F' || *args == 'f';
12033 save_in = input_line_pointer;
12034 input_line_pointer = s;
12035 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12037 s = input_line_pointer;
12038 input_line_pointer = save_in;
12039 if (err != NULL && *err != '\0')
12041 as_bad (_("Bad floating point constant: %s"), err);
12042 memset (temp, '\0', sizeof temp);
12043 length = f64 ? 8 : 4;
12046 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12050 && (g_switch_value < 4
12051 || (temp[0] == 0 && temp[1] == 0)
12052 || (temp[2] == 0 && temp[3] == 0))))
12054 imm_expr.X_op = O_constant;
12055 if (!target_big_endian)
12056 imm_expr.X_add_number = bfd_getl32 (temp);
12058 imm_expr.X_add_number = bfd_getb32 (temp);
12060 else if (length > 4
12061 && !mips_disable_float_construction
12062 /* Constants can only be constructed in GPRs and
12063 copied to FPRs if the GPRs are at least as wide
12064 as the FPRs. Force the constant into memory if
12065 we are using 64-bit FPRs but the GPRs are only
12068 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12069 && ((temp[0] == 0 && temp[1] == 0)
12070 || (temp[2] == 0 && temp[3] == 0))
12071 && ((temp[4] == 0 && temp[5] == 0)
12072 || (temp[6] == 0 && temp[7] == 0)))
12074 /* The value is simple enough to load with a couple of
12075 instructions. If using 32-bit registers, set
12076 imm_expr to the high order 32 bits and offset_expr to
12077 the low order 32 bits. Otherwise, set imm_expr to
12078 the entire 64 bit constant. */
12079 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12081 imm_expr.X_op = O_constant;
12082 offset_expr.X_op = O_constant;
12083 if (!target_big_endian)
12085 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12086 offset_expr.X_add_number = bfd_getl32 (temp);
12090 imm_expr.X_add_number = bfd_getb32 (temp);
12091 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12093 if (offset_expr.X_add_number == 0)
12094 offset_expr.X_op = O_absent;
12096 else if (sizeof (imm_expr.X_add_number) > 4)
12098 imm_expr.X_op = O_constant;
12099 if (!target_big_endian)
12100 imm_expr.X_add_number = bfd_getl64 (temp);
12102 imm_expr.X_add_number = bfd_getb64 (temp);
12106 imm_expr.X_op = O_big;
12107 imm_expr.X_add_number = 4;
12108 if (!target_big_endian)
12110 generic_bignum[0] = bfd_getl16 (temp);
12111 generic_bignum[1] = bfd_getl16 (temp + 2);
12112 generic_bignum[2] = bfd_getl16 (temp + 4);
12113 generic_bignum[3] = bfd_getl16 (temp + 6);
12117 generic_bignum[0] = bfd_getb16 (temp + 6);
12118 generic_bignum[1] = bfd_getb16 (temp + 4);
12119 generic_bignum[2] = bfd_getb16 (temp + 2);
12120 generic_bignum[3] = bfd_getb16 (temp);
12126 const char *newname;
12129 /* Switch to the right section. */
12131 subseg = now_subseg;
12134 default: /* unused default case avoids warnings. */
12136 newname = RDATA_SECTION_NAME;
12137 if (g_switch_value >= 8)
12141 newname = RDATA_SECTION_NAME;
12144 gas_assert (g_switch_value >= 4);
12148 new_seg = subseg_new (newname, (subsegT) 0);
12150 bfd_set_section_flags (stdoutput, new_seg,
12155 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12156 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12157 record_alignment (new_seg, 4);
12159 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12160 if (seg == now_seg)
12161 as_bad (_("Can't use floating point insn in this section"));
12163 /* Set the argument to the current address in the
12165 offset_expr.X_op = O_symbol;
12166 offset_expr.X_add_symbol = symbol_temp_new_now ();
12167 offset_expr.X_add_number = 0;
12169 /* Put the floating point number into the section. */
12170 p = frag_more ((int) length);
12171 memcpy (p, temp, length);
12173 /* Switch back to the original section. */
12174 subseg_set (seg, subseg);
12179 case 'i': /* 16-bit unsigned immediate. */
12180 case 'j': /* 16-bit signed immediate. */
12181 *imm_reloc = BFD_RELOC_LO16;
12182 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12185 offsetT minval, maxval;
12187 more = (insn + 1 < past
12188 && strcmp (insn->name, insn[1].name) == 0);
12190 /* If the expression was written as an unsigned number,
12191 only treat it as signed if there are no more
12195 && sizeof (imm_expr.X_add_number) <= 4
12196 && imm_expr.X_op == O_constant
12197 && imm_expr.X_add_number < 0
12198 && imm_expr.X_unsigned
12199 && HAVE_64BIT_GPRS)
12202 /* For compatibility with older assemblers, we accept
12203 0x8000-0xffff as signed 16-bit numbers when only
12204 signed numbers are allowed. */
12206 minval = 0, maxval = 0xffff;
12208 minval = -0x8000, maxval = 0x7fff;
12210 minval = -0x8000, maxval = 0xffff;
12212 if (imm_expr.X_op != O_constant
12213 || imm_expr.X_add_number < minval
12214 || imm_expr.X_add_number > maxval)
12218 if (imm_expr.X_op == O_constant
12219 || imm_expr.X_op == O_big)
12220 as_bad (_("Expression out of range"));
12226 case 'o': /* 16-bit offset. */
12227 offset_reloc[0] = BFD_RELOC_LO16;
12228 offset_reloc[1] = BFD_RELOC_UNUSED;
12229 offset_reloc[2] = BFD_RELOC_UNUSED;
12231 /* Check whether there is only a single bracketed expression
12232 left. If so, it must be the base register and the
12233 constant must be zero. */
12234 if (*s == '(' && strchr (s + 1, '(') == 0)
12236 offset_expr.X_op = O_constant;
12237 offset_expr.X_add_number = 0;
12241 /* If this value won't fit into a 16 bit offset, then go
12242 find a macro that will generate the 32 bit offset
12244 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12245 && (offset_expr.X_op != O_constant
12246 || offset_expr.X_add_number >= 0x8000
12247 || offset_expr.X_add_number < -0x8000))
12253 case 'p': /* PC-relative offset. */
12254 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12255 my_getExpression (&offset_expr, s);
12259 case 'u': /* Upper 16 bits. */
12260 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12261 && imm_expr.X_op == O_constant
12262 && (imm_expr.X_add_number < 0
12263 || imm_expr.X_add_number >= 0x10000))
12264 as_bad (_("lui expression (%lu) not in range 0..65535"),
12265 (unsigned long) imm_expr.X_add_number);
12269 case 'a': /* 26-bit address. */
12270 *offset_reloc = BFD_RELOC_MIPS_JMP;
12271 my_getExpression (&offset_expr, s);
12275 case 'N': /* 3-bit branch condition code. */
12276 case 'M': /* 3-bit compare condition code. */
12278 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12279 rtype |= RTYPE_FCC;
12280 if (!reg_lookup (&s, rtype, ®no))
12282 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12283 || strcmp (str + strlen (str) - 5, "any2f") == 0
12284 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12285 && (regno & 1) != 0)
12286 as_warn (_("Condition code register should be even for %s, "
12289 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12290 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12291 && (regno & 3) != 0)
12292 as_warn (_("Condition code register should be 0 or 4 for %s, "
12296 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12298 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12302 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12313 while (ISDIGIT (*s));
12316 c = 8; /* Invalid sel value. */
12319 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12320 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12324 gas_assert (!mips_opts.micromips);
12325 /* Must be at least one digit. */
12326 my_getExpression (&imm_expr, s);
12327 check_absolute_expr (ip, &imm_expr);
12329 if ((unsigned long) imm_expr.X_add_number
12330 > (unsigned long) OP_MASK_VECBYTE)
12332 as_bad (_("bad byte vector index (%ld)"),
12333 (long) imm_expr.X_add_number);
12334 imm_expr.X_add_number = 0;
12337 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12338 imm_expr.X_op = O_absent;
12343 gas_assert (!mips_opts.micromips);
12344 my_getExpression (&imm_expr, s);
12345 check_absolute_expr (ip, &imm_expr);
12347 if ((unsigned long) imm_expr.X_add_number
12348 > (unsigned long) OP_MASK_VECALIGN)
12350 as_bad (_("bad byte vector index (%ld)"),
12351 (long) imm_expr.X_add_number);
12352 imm_expr.X_add_number = 0;
12355 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12356 imm_expr.X_op = O_absent;
12360 case 'm': /* Opcode extension character. */
12361 gas_assert (mips_opts.micromips);
12366 if (strncmp (s, "$pc", 3) == 0)
12394 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12395 if (regno == AT && mips_opts.at)
12397 if (mips_opts.at == ATREG)
12398 as_warn (_("Used $at without \".set noat\""));
12400 as_warn (_("Used $%u with \".set at=$%u\""),
12401 regno, mips_opts.at);
12407 gas_assert (args[1] == ',');
12413 gas_assert (args[1] == ',');
12415 continue; /* Nothing to do. */
12421 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12423 if (regno == lastregno)
12426 = _("Source and destination must be different");
12429 if (regno == 31 && lastregno == 0xffffffff)
12432 = _("A destination register must be supplied");
12443 gas_assert (args[1] == ',');
12450 gas_assert (args[1] == ',');
12453 continue; /* Nothing to do. */
12457 /* Make sure regno is the same as lastregno. */
12458 if (c == 't' && regno != lastregno)
12461 /* Make sure regno is the same as destregno. */
12462 if (c == 'x' && regno != destregno)
12465 /* We need to save regno, before regno maps to the
12466 microMIPS register encoding. */
12476 regno = ILLEGAL_REG;
12480 regno = mips32_to_micromips_reg_b_map[regno];
12484 regno = mips32_to_micromips_reg_c_map[regno];
12488 regno = mips32_to_micromips_reg_d_map[regno];
12492 regno = mips32_to_micromips_reg_e_map[regno];
12496 regno = mips32_to_micromips_reg_f_map[regno];
12500 regno = mips32_to_micromips_reg_g_map[regno];
12504 regno = mips32_to_micromips_reg_h_map[regno];
12508 switch (EXTRACT_OPERAND (1, MI, *ip))
12513 else if (regno == 22)
12515 else if (regno == 5)
12517 else if (regno == 6)
12519 else if (regno == 7)
12522 regno = ILLEGAL_REG;
12528 else if (regno == 7)
12531 regno = ILLEGAL_REG;
12538 regno = ILLEGAL_REG;
12542 regno = ILLEGAL_REG;
12548 regno = mips32_to_micromips_reg_l_map[regno];
12552 regno = mips32_to_micromips_reg_m_map[regno];
12556 regno = mips32_to_micromips_reg_n_map[regno];
12560 regno = mips32_to_micromips_reg_q_map[regno];
12565 regno = ILLEGAL_REG;
12570 regno = ILLEGAL_REG;
12575 regno = ILLEGAL_REG;
12578 case 'j': /* Do nothing. */
12588 if (regno == ILLEGAL_REG)
12594 INSERT_OPERAND (1, MB, *ip, regno);
12598 INSERT_OPERAND (1, MC, *ip, regno);
12602 INSERT_OPERAND (1, MD, *ip, regno);
12606 INSERT_OPERAND (1, ME, *ip, regno);
12610 INSERT_OPERAND (1, MF, *ip, regno);
12614 INSERT_OPERAND (1, MG, *ip, regno);
12618 INSERT_OPERAND (1, MH, *ip, regno);
12622 INSERT_OPERAND (1, MI, *ip, regno);
12626 INSERT_OPERAND (1, MJ, *ip, regno);
12630 INSERT_OPERAND (1, ML, *ip, regno);
12634 INSERT_OPERAND (1, MM, *ip, regno);
12638 INSERT_OPERAND (1, MN, *ip, regno);
12642 INSERT_OPERAND (1, MP, *ip, regno);
12646 INSERT_OPERAND (1, MQ, *ip, regno);
12649 case 'a': /* Do nothing. */
12650 case 's': /* Do nothing. */
12651 case 't': /* Do nothing. */
12652 case 'x': /* Do nothing. */
12653 case 'y': /* Do nothing. */
12654 case 'z': /* Do nothing. */
12664 bfd_reloc_code_real_type r[3];
12668 /* Check whether there is only a single bracketed
12669 expression left. If so, it must be the base register
12670 and the constant must be zero. */
12671 if (*s == '(' && strchr (s + 1, '(') == 0)
12673 INSERT_OPERAND (1, IMMA, *ip, 0);
12677 if (my_getSmallExpression (&ep, r, s) > 0
12678 || !expr_const_in_range (&ep, -64, 64, 2))
12681 imm = ep.X_add_number >> 2;
12682 INSERT_OPERAND (1, IMMA, *ip, imm);
12689 bfd_reloc_code_real_type r[3];
12693 if (my_getSmallExpression (&ep, r, s) > 0
12694 || ep.X_op != O_constant)
12697 for (imm = 0; imm < 8; imm++)
12698 if (micromips_imm_b_map[imm] == ep.X_add_number)
12703 INSERT_OPERAND (1, IMMB, *ip, imm);
12710 bfd_reloc_code_real_type r[3];
12714 if (my_getSmallExpression (&ep, r, s) > 0
12715 || ep.X_op != O_constant)
12718 for (imm = 0; imm < 16; imm++)
12719 if (micromips_imm_c_map[imm] == ep.X_add_number)
12724 INSERT_OPERAND (1, IMMC, *ip, imm);
12729 case 'D': /* pc relative offset */
12730 case 'E': /* pc relative offset */
12731 my_getExpression (&offset_expr, s);
12732 if (offset_expr.X_op == O_register)
12735 if (!forced_insn_length)
12736 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12738 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12740 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12746 bfd_reloc_code_real_type r[3];
12750 if (my_getSmallExpression (&ep, r, s) > 0
12751 || !expr_const_in_range (&ep, 0, 16, 0))
12754 imm = ep.X_add_number;
12755 INSERT_OPERAND (1, IMMF, *ip, imm);
12762 bfd_reloc_code_real_type r[3];
12766 /* Check whether there is only a single bracketed
12767 expression left. If so, it must be the base register
12768 and the constant must be zero. */
12769 if (*s == '(' && strchr (s + 1, '(') == 0)
12771 INSERT_OPERAND (1, IMMG, *ip, 0);
12775 if (my_getSmallExpression (&ep, r, s) > 0
12776 || !expr_const_in_range (&ep, -1, 15, 0))
12779 imm = ep.X_add_number & 15;
12780 INSERT_OPERAND (1, IMMG, *ip, imm);
12787 bfd_reloc_code_real_type r[3];
12791 /* Check whether there is only a single bracketed
12792 expression left. If so, it must be the base register
12793 and the constant must be zero. */
12794 if (*s == '(' && strchr (s + 1, '(') == 0)
12796 INSERT_OPERAND (1, IMMH, *ip, 0);
12800 if (my_getSmallExpression (&ep, r, s) > 0
12801 || !expr_const_in_range (&ep, 0, 16, 1))
12804 imm = ep.X_add_number >> 1;
12805 INSERT_OPERAND (1, IMMH, *ip, imm);
12812 bfd_reloc_code_real_type r[3];
12816 if (my_getSmallExpression (&ep, r, s) > 0
12817 || !expr_const_in_range (&ep, -1, 127, 0))
12820 imm = ep.X_add_number & 127;
12821 INSERT_OPERAND (1, IMMI, *ip, imm);
12828 bfd_reloc_code_real_type r[3];
12832 /* Check whether there is only a single bracketed
12833 expression left. If so, it must be the base register
12834 and the constant must be zero. */
12835 if (*s == '(' && strchr (s + 1, '(') == 0)
12837 INSERT_OPERAND (1, IMMJ, *ip, 0);
12841 if (my_getSmallExpression (&ep, r, s) > 0
12842 || !expr_const_in_range (&ep, 0, 16, 2))
12845 imm = ep.X_add_number >> 2;
12846 INSERT_OPERAND (1, IMMJ, *ip, imm);
12853 bfd_reloc_code_real_type r[3];
12857 /* Check whether there is only a single bracketed
12858 expression left. If so, it must be the base register
12859 and the constant must be zero. */
12860 if (*s == '(' && strchr (s + 1, '(') == 0)
12862 INSERT_OPERAND (1, IMML, *ip, 0);
12866 if (my_getSmallExpression (&ep, r, s) > 0
12867 || !expr_const_in_range (&ep, 0, 16, 0))
12870 imm = ep.X_add_number;
12871 INSERT_OPERAND (1, IMML, *ip, imm);
12878 bfd_reloc_code_real_type r[3];
12882 if (my_getSmallExpression (&ep, r, s) > 0
12883 || !expr_const_in_range (&ep, 1, 9, 0))
12886 imm = ep.X_add_number & 7;
12887 INSERT_OPERAND (1, IMMM, *ip, imm);
12892 case 'N': /* Register list for lwm and swm. */
12894 /* A comma-separated list of registers and/or
12895 dash-separated contiguous ranges including
12896 both ra and a set of one or more registers
12897 starting at s0 up to s3 which have to be
12904 and any permutations of these. */
12905 unsigned int reglist;
12908 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
12911 if ((reglist & 0xfff1ffff) != 0x80010000)
12914 reglist = (reglist >> 17) & 7;
12916 if ((reglist & -reglist) != reglist)
12919 imm = ffs (reglist) - 1;
12920 INSERT_OPERAND (1, IMMN, *ip, imm);
12924 case 'O': /* sdbbp 4-bit code. */
12926 bfd_reloc_code_real_type r[3];
12930 if (my_getSmallExpression (&ep, r, s) > 0
12931 || !expr_const_in_range (&ep, 0, 16, 0))
12934 imm = ep.X_add_number;
12935 INSERT_OPERAND (1, IMMO, *ip, imm);
12942 bfd_reloc_code_real_type r[3];
12946 if (my_getSmallExpression (&ep, r, s) > 0
12947 || !expr_const_in_range (&ep, 0, 32, 2))
12950 imm = ep.X_add_number >> 2;
12951 INSERT_OPERAND (1, IMMP, *ip, imm);
12958 bfd_reloc_code_real_type r[3];
12962 if (my_getSmallExpression (&ep, r, s) > 0
12963 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
12966 imm = ep.X_add_number >> 2;
12967 INSERT_OPERAND (1, IMMQ, *ip, imm);
12974 bfd_reloc_code_real_type r[3];
12978 /* Check whether there is only a single bracketed
12979 expression left. If so, it must be the base register
12980 and the constant must be zero. */
12981 if (*s == '(' && strchr (s + 1, '(') == 0)
12983 INSERT_OPERAND (1, IMMU, *ip, 0);
12987 if (my_getSmallExpression (&ep, r, s) > 0
12988 || !expr_const_in_range (&ep, 0, 32, 2))
12991 imm = ep.X_add_number >> 2;
12992 INSERT_OPERAND (1, IMMU, *ip, imm);
12999 bfd_reloc_code_real_type r[3];
13003 if (my_getSmallExpression (&ep, r, s) > 0
13004 || !expr_const_in_range (&ep, 0, 64, 2))
13007 imm = ep.X_add_number >> 2;
13008 INSERT_OPERAND (1, IMMW, *ip, imm);
13015 bfd_reloc_code_real_type r[3];
13019 if (my_getSmallExpression (&ep, r, s) > 0
13020 || !expr_const_in_range (&ep, -8, 8, 0))
13023 imm = ep.X_add_number;
13024 INSERT_OPERAND (1, IMMX, *ip, imm);
13031 bfd_reloc_code_real_type r[3];
13035 if (my_getSmallExpression (&ep, r, s) > 0
13036 || expr_const_in_range (&ep, -2, 2, 2)
13037 || !expr_const_in_range (&ep, -258, 258, 2))
13040 imm = ep.X_add_number >> 2;
13041 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13042 INSERT_OPERAND (1, IMMY, *ip, imm);
13049 bfd_reloc_code_real_type r[3];
13052 if (my_getSmallExpression (&ep, r, s) > 0
13053 || !expr_const_in_range (&ep, 0, 1, 0))
13060 as_bad (_("Internal error: bad microMIPS opcode "
13061 "(unknown extension operand type `m%c'): %s %s"),
13062 *args, insn->name, insn->args);
13063 /* Further processing is fruitless. */
13068 case 'n': /* Register list for 32-bit lwm and swm. */
13069 gas_assert (mips_opts.micromips);
13071 /* A comma-separated list of registers and/or
13072 dash-separated contiguous ranges including
13073 at least one of ra and a set of one or more
13074 registers starting at s0 up to s7 and then
13075 s8 which have to be consecutive, e.g.:
13083 and any permutations of these. */
13084 unsigned int reglist;
13088 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13091 if ((reglist & 0x3f00ffff) != 0)
13094 ra = (reglist >> 27) & 0x10;
13095 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13097 if ((reglist & -reglist) != reglist)
13100 imm = (ffs (reglist) - 1) | ra;
13101 INSERT_OPERAND (1, RT, *ip, imm);
13102 imm_expr.X_op = O_absent;
13106 case '|': /* 4-bit trap code. */
13107 gas_assert (mips_opts.micromips);
13108 my_getExpression (&imm_expr, s);
13109 check_absolute_expr (ip, &imm_expr);
13110 if ((unsigned long) imm_expr.X_add_number
13111 > MICROMIPSOP_MASK_TRAP)
13112 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13113 (unsigned long) imm_expr.X_add_number,
13114 ip->insn_mo->name);
13115 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13116 imm_expr.X_op = O_absent;
13121 as_bad (_("Bad char = '%c'\n"), *args);
13126 /* Args don't match. */
13128 insn_error = _("Illegal operands");
13129 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13134 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13136 gas_assert (firstinsn);
13137 need_delay_slot_ok = FALSE;
13146 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13148 /* This routine assembles an instruction into its binary format when
13149 assembling for the mips16. As a side effect, it sets one of the
13150 global variables imm_reloc or offset_reloc to the type of relocation
13151 to do if one of the operands is an address expression. It also sets
13152 forced_insn_length to the resulting instruction size in bytes if the
13153 user explicitly requested a small or extended instruction. */
13156 mips16_ip (char *str, struct mips_cl_insn *ip)
13160 struct mips_opcode *insn;
13162 unsigned int regno;
13163 unsigned int lastregno = 0;
13169 forced_insn_length = 0;
13171 for (s = str; ISLOWER (*s); ++s)
13183 if (s[1] == 't' && s[2] == ' ')
13186 forced_insn_length = 2;
13190 else if (s[1] == 'e' && s[2] == ' ')
13193 forced_insn_length = 4;
13197 /* Fall through. */
13199 insn_error = _("unknown opcode");
13203 if (mips_opts.noautoextend && !forced_insn_length)
13204 forced_insn_length = 2;
13206 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13208 insn_error = _("unrecognized opcode");
13217 gas_assert (strcmp (insn->name, str) == 0);
13219 ok = is_opcode_valid_16 (insn);
13222 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13223 && strcmp (insn->name, insn[1].name) == 0)
13232 static char buf[100];
13234 _("opcode not supported on this processor: %s (%s)"),
13235 mips_cpu_info_from_arch (mips_opts.arch)->name,
13236 mips_cpu_info_from_isa (mips_opts.isa)->name);
13243 create_insn (ip, insn);
13244 imm_expr.X_op = O_absent;
13245 imm_reloc[0] = BFD_RELOC_UNUSED;
13246 imm_reloc[1] = BFD_RELOC_UNUSED;
13247 imm_reloc[2] = BFD_RELOC_UNUSED;
13248 imm2_expr.X_op = O_absent;
13249 offset_expr.X_op = O_absent;
13250 offset_reloc[0] = BFD_RELOC_UNUSED;
13251 offset_reloc[1] = BFD_RELOC_UNUSED;
13252 offset_reloc[2] = BFD_RELOC_UNUSED;
13253 for (args = insn->args; 1; ++args)
13260 /* In this switch statement we call break if we did not find
13261 a match, continue if we did find a match, or return if we
13270 /* Stuff the immediate value in now, if we can. */
13271 if (imm_expr.X_op == O_constant
13272 && *imm_reloc > BFD_RELOC_UNUSED
13273 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13274 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
13275 && insn->pinfo != INSN_MACRO)
13279 switch (*offset_reloc)
13281 case BFD_RELOC_MIPS16_HI16_S:
13282 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13285 case BFD_RELOC_MIPS16_HI16:
13286 tmp = imm_expr.X_add_number >> 16;
13289 case BFD_RELOC_MIPS16_LO16:
13290 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13294 case BFD_RELOC_UNUSED:
13295 tmp = imm_expr.X_add_number;
13301 *offset_reloc = BFD_RELOC_UNUSED;
13303 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13304 tmp, TRUE, forced_insn_length == 2,
13305 forced_insn_length == 4, &ip->insn_opcode,
13306 &ip->use_extend, &ip->extend);
13307 imm_expr.X_op = O_absent;
13308 *imm_reloc = BFD_RELOC_UNUSED;
13322 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13325 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13341 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13343 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13347 /* Fall through. */
13358 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13360 if (c == 'v' || c == 'w')
13363 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13365 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13376 if (c == 'v' || c == 'w')
13378 regno = mips16_to_32_reg_map[lastregno];
13392 regno = mips32_to_16_reg_map[regno];
13397 regno = ILLEGAL_REG;
13402 regno = ILLEGAL_REG;
13407 regno = ILLEGAL_REG;
13412 if (regno == AT && mips_opts.at)
13414 if (mips_opts.at == ATREG)
13415 as_warn (_("used $at without \".set noat\""));
13417 as_warn (_("used $%u with \".set at=$%u\""),
13418 regno, mips_opts.at);
13426 if (regno == ILLEGAL_REG)
13433 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13437 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13440 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13443 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13449 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13452 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13453 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13463 if (strncmp (s, "$pc", 3) == 0)
13480 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13483 if (imm_expr.X_op != O_constant)
13485 forced_insn_length = 4;
13486 ip->use_extend = TRUE;
13491 /* We need to relax this instruction. */
13492 *offset_reloc = *imm_reloc;
13493 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13498 *imm_reloc = BFD_RELOC_UNUSED;
13499 /* Fall through. */
13506 my_getExpression (&imm_expr, s);
13507 if (imm_expr.X_op == O_register)
13509 /* What we thought was an expression turned out to
13512 if (s[0] == '(' && args[1] == '(')
13514 /* It looks like the expression was omitted
13515 before a register indirection, which means
13516 that the expression is implicitly zero. We
13517 still set up imm_expr, so that we handle
13518 explicit extensions correctly. */
13519 imm_expr.X_op = O_constant;
13520 imm_expr.X_add_number = 0;
13521 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13528 /* We need to relax this instruction. */
13529 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13538 /* We use offset_reloc rather than imm_reloc for the PC
13539 relative operands. This lets macros with both
13540 immediate and address operands work correctly. */
13541 my_getExpression (&offset_expr, s);
13543 if (offset_expr.X_op == O_register)
13546 /* We need to relax this instruction. */
13547 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13551 case '6': /* break code */
13552 my_getExpression (&imm_expr, s);
13553 check_absolute_expr (ip, &imm_expr);
13554 if ((unsigned long) imm_expr.X_add_number > 63)
13555 as_warn (_("Invalid value for `%s' (%lu)"),
13557 (unsigned long) imm_expr.X_add_number);
13558 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13559 imm_expr.X_op = O_absent;
13563 case 'a': /* 26 bit address */
13564 my_getExpression (&offset_expr, s);
13566 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13567 ip->insn_opcode <<= 16;
13570 case 'l': /* register list for entry macro */
13571 case 'L': /* register list for exit macro */
13581 unsigned int freg, reg1, reg2;
13583 while (*s == ' ' || *s == ',')
13585 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13587 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13591 as_bad (_("can't parse register list"));
13601 if (!reg_lookup (&s, freg ? RTYPE_FPU
13602 : (RTYPE_GP | RTYPE_NUM), ®2))
13604 as_bad (_("invalid register list"));
13608 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13610 mask &= ~ (7 << 3);
13613 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13615 mask &= ~ (7 << 3);
13618 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13619 mask |= (reg2 - 3) << 3;
13620 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13621 mask |= (reg2 - 15) << 1;
13622 else if (reg1 == RA && reg2 == RA)
13626 as_bad (_("invalid register list"));
13630 /* The mask is filled in in the opcode table for the
13631 benefit of the disassembler. We remove it before
13632 applying the actual mask. */
13633 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13634 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13638 case 'm': /* Register list for save insn. */
13639 case 'M': /* Register list for restore insn. */
13642 int framesz = 0, seen_framesz = 0;
13643 int nargs = 0, statics = 0, sregs = 0;
13647 unsigned int reg1, reg2;
13649 SKIP_SPACE_TABS (s);
13652 SKIP_SPACE_TABS (s);
13654 my_getExpression (&imm_expr, s);
13655 if (imm_expr.X_op == O_constant)
13657 /* Handle the frame size. */
13660 as_bad (_("more than one frame size in list"));
13664 framesz = imm_expr.X_add_number;
13665 imm_expr.X_op = O_absent;
13670 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13672 as_bad (_("can't parse register list"));
13684 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13687 as_bad (_("can't parse register list"));
13692 while (reg1 <= reg2)
13694 if (reg1 >= 4 && reg1 <= 7)
13698 nargs |= 1 << (reg1 - 4);
13700 /* statics $a0-$a3 */
13701 statics |= 1 << (reg1 - 4);
13703 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13706 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13708 else if (reg1 == 31)
13710 /* Add $ra to insn. */
13715 as_bad (_("unexpected register in list"));
13723 /* Encode args/statics combination. */
13724 if (nargs & statics)
13725 as_bad (_("arg/static registers overlap"));
13726 else if (nargs == 0xf)
13727 /* All $a0-$a3 are args. */
13728 opcode |= MIPS16_ALL_ARGS << 16;
13729 else if (statics == 0xf)
13730 /* All $a0-$a3 are statics. */
13731 opcode |= MIPS16_ALL_STATICS << 16;
13734 int narg = 0, nstat = 0;
13736 /* Count arg registers. */
13737 while (nargs & 0x1)
13743 as_bad (_("invalid arg register list"));
13745 /* Count static registers. */
13746 while (statics & 0x8)
13748 statics = (statics << 1) & 0xf;
13752 as_bad (_("invalid static register list"));
13754 /* Encode args/statics. */
13755 opcode |= ((narg << 2) | nstat) << 16;
13758 /* Encode $s0/$s1. */
13759 if (sregs & (1 << 0)) /* $s0 */
13761 if (sregs & (1 << 1)) /* $s1 */
13767 /* Count regs $s2-$s8. */
13775 as_bad (_("invalid static register list"));
13776 /* Encode $s2-$s8. */
13777 opcode |= nsreg << 24;
13780 /* Encode frame size. */
13782 as_bad (_("missing frame size"));
13783 else if ((framesz & 7) != 0 || framesz < 0
13784 || framesz > 0xff * 8)
13785 as_bad (_("invalid frame size"));
13786 else if (framesz != 128 || (opcode >> 16) != 0)
13789 opcode |= (((framesz & 0xf0) << 16)
13790 | (framesz & 0x0f));
13793 /* Finally build the instruction. */
13794 if ((opcode >> 16) != 0 || framesz == 0)
13796 ip->use_extend = TRUE;
13797 ip->extend = opcode >> 16;
13799 ip->insn_opcode |= opcode & 0x7f;
13803 case 'e': /* extend code */
13804 my_getExpression (&imm_expr, s);
13805 check_absolute_expr (ip, &imm_expr);
13806 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13808 as_warn (_("Invalid value for `%s' (%lu)"),
13810 (unsigned long) imm_expr.X_add_number);
13811 imm_expr.X_add_number &= 0x7ff;
13813 ip->insn_opcode |= imm_expr.X_add_number;
13814 imm_expr.X_op = O_absent;
13824 /* Args don't match. */
13825 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13826 strcmp (insn->name, insn[1].name) == 0)
13833 insn_error = _("illegal operands");
13839 /* This structure holds information we know about a mips16 immediate
13842 struct mips16_immed_operand
13844 /* The type code used in the argument string in the opcode table. */
13846 /* The number of bits in the short form of the opcode. */
13848 /* The number of bits in the extended form of the opcode. */
13850 /* The amount by which the short form is shifted when it is used;
13851 for example, the sw instruction has a shift count of 2. */
13853 /* The amount by which the short form is shifted when it is stored
13854 into the instruction code. */
13856 /* Non-zero if the short form is unsigned. */
13858 /* Non-zero if the extended form is unsigned. */
13860 /* Non-zero if the value is PC relative. */
13864 /* The mips16 immediate operand types. */
13866 static const struct mips16_immed_operand mips16_immed_operands[] =
13868 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13869 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13870 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13871 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13872 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13873 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13874 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13875 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13876 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13877 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13878 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13879 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13880 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13881 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13882 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13883 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13884 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13885 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13886 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13887 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13888 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13891 #define MIPS16_NUM_IMMED \
13892 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13894 /* Handle a mips16 instruction with an immediate value. This or's the
13895 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13896 whether an extended value is needed; if one is needed, it sets
13897 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13898 If SMALL is true, an unextended opcode was explicitly requested.
13899 If EXT is true, an extended opcode was explicitly requested. If
13900 WARN is true, warn if EXT does not match reality. */
13903 mips16_immed (char *file, unsigned int line, int type, offsetT val,
13904 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
13905 unsigned long *insn, bfd_boolean *use_extend,
13906 unsigned short *extend)
13908 const struct mips16_immed_operand *op;
13909 int mintiny, maxtiny;
13910 bfd_boolean needext;
13912 op = mips16_immed_operands;
13913 while (op->type != type)
13916 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13921 if (type == '<' || type == '>' || type == '[' || type == ']')
13924 maxtiny = 1 << op->nbits;
13929 maxtiny = (1 << op->nbits) - 1;
13934 mintiny = - (1 << (op->nbits - 1));
13935 maxtiny = (1 << (op->nbits - 1)) - 1;
13938 /* Branch offsets have an implicit 0 in the lowest bit. */
13939 if (type == 'p' || type == 'q')
13942 if ((val & ((1 << op->shift) - 1)) != 0
13943 || val < (mintiny << op->shift)
13944 || val > (maxtiny << op->shift))
13949 if (warn && ext && ! needext)
13950 as_warn_where (file, line,
13951 _("extended operand requested but not required"));
13952 if (small && needext)
13953 as_bad_where (file, line, _("invalid unextended operand value"));
13955 if (small || (! ext && ! needext))
13959 *use_extend = FALSE;
13960 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
13961 insnval <<= op->op_shift;
13966 long minext, maxext;
13972 maxext = (1 << op->extbits) - 1;
13976 minext = - (1 << (op->extbits - 1));
13977 maxext = (1 << (op->extbits - 1)) - 1;
13979 if (val < minext || val > maxext)
13980 as_bad_where (file, line,
13981 _("operand value out of range for instruction"));
13983 *use_extend = TRUE;
13984 if (op->extbits == 16)
13986 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13989 else if (op->extbits == 15)
13991 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13996 extval = ((val & 0x1f) << 6) | (val & 0x20);
14000 *extend = (unsigned short) extval;
14005 struct percent_op_match
14008 bfd_reloc_code_real_type reloc;
14011 static const struct percent_op_match mips_percent_op[] =
14013 {"%lo", BFD_RELOC_LO16},
14015 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14016 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14017 {"%call16", BFD_RELOC_MIPS_CALL16},
14018 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14019 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14020 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14021 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14022 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14023 {"%got", BFD_RELOC_MIPS_GOT16},
14024 {"%gp_rel", BFD_RELOC_GPREL16},
14025 {"%half", BFD_RELOC_16},
14026 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14027 {"%higher", BFD_RELOC_MIPS_HIGHER},
14028 {"%neg", BFD_RELOC_MIPS_SUB},
14029 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14030 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14031 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14032 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14033 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14034 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14035 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14037 {"%hi", BFD_RELOC_HI16_S}
14040 static const struct percent_op_match mips16_percent_op[] =
14042 {"%lo", BFD_RELOC_MIPS16_LO16},
14043 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14044 {"%got", BFD_RELOC_MIPS16_GOT16},
14045 {"%call16", BFD_RELOC_MIPS16_CALL16},
14046 {"%hi", BFD_RELOC_MIPS16_HI16_S}
14050 /* Return true if *STR points to a relocation operator. When returning true,
14051 move *STR over the operator and store its relocation code in *RELOC.
14052 Leave both *STR and *RELOC alone when returning false. */
14055 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14057 const struct percent_op_match *percent_op;
14060 if (mips_opts.mips16)
14062 percent_op = mips16_percent_op;
14063 limit = ARRAY_SIZE (mips16_percent_op);
14067 percent_op = mips_percent_op;
14068 limit = ARRAY_SIZE (mips_percent_op);
14071 for (i = 0; i < limit; i++)
14072 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14074 int len = strlen (percent_op[i].str);
14076 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14079 *str += strlen (percent_op[i].str);
14080 *reloc = percent_op[i].reloc;
14082 /* Check whether the output BFD supports this relocation.
14083 If not, issue an error and fall back on something safe. */
14084 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14086 as_bad (_("relocation %s isn't supported by the current ABI"),
14087 percent_op[i].str);
14088 *reloc = BFD_RELOC_UNUSED;
14096 /* Parse string STR as a 16-bit relocatable operand. Store the
14097 expression in *EP and the relocations in the array starting
14098 at RELOC. Return the number of relocation operators used.
14100 On exit, EXPR_END points to the first character after the expression. */
14103 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14106 bfd_reloc_code_real_type reversed_reloc[3];
14107 size_t reloc_index, i;
14108 int crux_depth, str_depth;
14111 /* Search for the start of the main expression, recoding relocations
14112 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14113 of the main expression and with CRUX_DEPTH containing the number
14114 of open brackets at that point. */
14121 crux_depth = str_depth;
14123 /* Skip over whitespace and brackets, keeping count of the number
14125 while (*str == ' ' || *str == '\t' || *str == '(')
14130 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14131 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14133 my_getExpression (ep, crux);
14136 /* Match every open bracket. */
14137 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14141 if (crux_depth > 0)
14142 as_bad (_("unclosed '('"));
14146 if (reloc_index != 0)
14148 prev_reloc_op_frag = frag_now;
14149 for (i = 0; i < reloc_index; i++)
14150 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14153 return reloc_index;
14157 my_getExpression (expressionS *ep, char *str)
14161 save_in = input_line_pointer;
14162 input_line_pointer = str;
14164 expr_end = input_line_pointer;
14165 input_line_pointer = save_in;
14169 md_atof (int type, char *litP, int *sizeP)
14171 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14175 md_number_to_chars (char *buf, valueT val, int n)
14177 if (target_big_endian)
14178 number_to_chars_bigendian (buf, val, n);
14180 number_to_chars_littleendian (buf, val, n);
14184 static int support_64bit_objects(void)
14186 const char **list, **l;
14189 list = bfd_target_list ();
14190 for (l = list; *l != NULL; l++)
14191 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14192 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14194 yes = (*l != NULL);
14198 #endif /* OBJ_ELF */
14200 const char *md_shortopts = "O::g::G:";
14204 OPTION_MARCH = OPTION_MD_BASE,
14226 OPTION_NO_SMARTMIPS,
14230 OPTION_NO_MICROMIPS,
14233 OPTION_COMPAT_ARCH_BASE,
14242 OPTION_M7000_HILO_FIX,
14243 OPTION_MNO_7000_HILO_FIX,
14246 OPTION_FIX_LOONGSON2F_JUMP,
14247 OPTION_NO_FIX_LOONGSON2F_JUMP,
14248 OPTION_FIX_LOONGSON2F_NOP,
14249 OPTION_NO_FIX_LOONGSON2F_NOP,
14251 OPTION_NO_FIX_VR4120,
14253 OPTION_NO_FIX_VR4130,
14254 OPTION_FIX_CN63XXP1,
14255 OPTION_NO_FIX_CN63XXP1,
14262 OPTION_CONSTRUCT_FLOATS,
14263 OPTION_NO_CONSTRUCT_FLOATS,
14266 OPTION_RELAX_BRANCH,
14267 OPTION_NO_RELAX_BRANCH,
14274 OPTION_SINGLE_FLOAT,
14275 OPTION_DOUBLE_FLOAT,
14278 OPTION_CALL_SHARED,
14279 OPTION_CALL_NONPIC,
14289 OPTION_MVXWORKS_PIC,
14290 #endif /* OBJ_ELF */
14294 struct option md_longopts[] =
14296 /* Options which specify architecture. */
14297 {"march", required_argument, NULL, OPTION_MARCH},
14298 {"mtune", required_argument, NULL, OPTION_MTUNE},
14299 {"mips0", no_argument, NULL, OPTION_MIPS1},
14300 {"mips1", no_argument, NULL, OPTION_MIPS1},
14301 {"mips2", no_argument, NULL, OPTION_MIPS2},
14302 {"mips3", no_argument, NULL, OPTION_MIPS3},
14303 {"mips4", no_argument, NULL, OPTION_MIPS4},
14304 {"mips5", no_argument, NULL, OPTION_MIPS5},
14305 {"mips32", no_argument, NULL, OPTION_MIPS32},
14306 {"mips64", no_argument, NULL, OPTION_MIPS64},
14307 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14308 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14310 /* Options which specify Application Specific Extensions (ASEs). */
14311 {"mips16", no_argument, NULL, OPTION_MIPS16},
14312 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14313 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14314 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14315 {"mdmx", no_argument, NULL, OPTION_MDMX},
14316 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14317 {"mdsp", no_argument, NULL, OPTION_DSP},
14318 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14319 {"mmt", no_argument, NULL, OPTION_MT},
14320 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14321 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14322 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14323 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14324 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14325 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14326 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14327 {"mmcu", no_argument, NULL, OPTION_MCU},
14328 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14330 /* Old-style architecture options. Don't add more of these. */
14331 {"m4650", no_argument, NULL, OPTION_M4650},
14332 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14333 {"m4010", no_argument, NULL, OPTION_M4010},
14334 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14335 {"m4100", no_argument, NULL, OPTION_M4100},
14336 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14337 {"m3900", no_argument, NULL, OPTION_M3900},
14338 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14340 /* Options which enable bug fixes. */
14341 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14342 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14343 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14344 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14345 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14346 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14347 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14348 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14349 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14350 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14351 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14352 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14353 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14354 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14355 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14357 /* Miscellaneous options. */
14358 {"trap", no_argument, NULL, OPTION_TRAP},
14359 {"no-break", no_argument, NULL, OPTION_TRAP},
14360 {"break", no_argument, NULL, OPTION_BREAK},
14361 {"no-trap", no_argument, NULL, OPTION_BREAK},
14362 {"EB", no_argument, NULL, OPTION_EB},
14363 {"EL", no_argument, NULL, OPTION_EL},
14364 {"mfp32", no_argument, NULL, OPTION_FP32},
14365 {"mgp32", no_argument, NULL, OPTION_GP32},
14366 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14367 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14368 {"mfp64", no_argument, NULL, OPTION_FP64},
14369 {"mgp64", no_argument, NULL, OPTION_GP64},
14370 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14371 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14372 {"mshared", no_argument, NULL, OPTION_MSHARED},
14373 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14374 {"msym32", no_argument, NULL, OPTION_MSYM32},
14375 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14376 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14377 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14378 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14379 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14381 /* Strictly speaking this next option is ELF specific,
14382 but we allow it for other ports as well in order to
14383 make testing easier. */
14384 {"32", no_argument, NULL, OPTION_32},
14386 /* ELF-specific options. */
14388 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14389 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14390 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14391 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14392 {"xgot", no_argument, NULL, OPTION_XGOT},
14393 {"mabi", required_argument, NULL, OPTION_MABI},
14394 {"n32", no_argument, NULL, OPTION_N32},
14395 {"64", no_argument, NULL, OPTION_64},
14396 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14397 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14398 {"mpdr", no_argument, NULL, OPTION_PDR},
14399 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14400 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14401 #endif /* OBJ_ELF */
14403 {NULL, no_argument, NULL, 0}
14405 size_t md_longopts_size = sizeof (md_longopts);
14407 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14408 NEW_VALUE. Warn if another value was already specified. Note:
14409 we have to defer parsing the -march and -mtune arguments in order
14410 to handle 'from-abi' correctly, since the ABI might be specified
14411 in a later argument. */
14414 mips_set_option_string (const char **string_ptr, const char *new_value)
14416 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14417 as_warn (_("A different %s was already specified, is now %s"),
14418 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14421 *string_ptr = new_value;
14425 md_parse_option (int c, char *arg)
14429 case OPTION_CONSTRUCT_FLOATS:
14430 mips_disable_float_construction = 0;
14433 case OPTION_NO_CONSTRUCT_FLOATS:
14434 mips_disable_float_construction = 1;
14446 target_big_endian = 1;
14450 target_big_endian = 0;
14456 else if (arg[0] == '0')
14458 else if (arg[0] == '1')
14468 mips_debug = atoi (arg);
14472 file_mips_isa = ISA_MIPS1;
14476 file_mips_isa = ISA_MIPS2;
14480 file_mips_isa = ISA_MIPS3;
14484 file_mips_isa = ISA_MIPS4;
14488 file_mips_isa = ISA_MIPS5;
14491 case OPTION_MIPS32:
14492 file_mips_isa = ISA_MIPS32;
14495 case OPTION_MIPS32R2:
14496 file_mips_isa = ISA_MIPS32R2;
14499 case OPTION_MIPS64R2:
14500 file_mips_isa = ISA_MIPS64R2;
14503 case OPTION_MIPS64:
14504 file_mips_isa = ISA_MIPS64;
14508 mips_set_option_string (&mips_tune_string, arg);
14512 mips_set_option_string (&mips_arch_string, arg);
14516 mips_set_option_string (&mips_arch_string, "4650");
14517 mips_set_option_string (&mips_tune_string, "4650");
14520 case OPTION_NO_M4650:
14524 mips_set_option_string (&mips_arch_string, "4010");
14525 mips_set_option_string (&mips_tune_string, "4010");
14528 case OPTION_NO_M4010:
14532 mips_set_option_string (&mips_arch_string, "4100");
14533 mips_set_option_string (&mips_tune_string, "4100");
14536 case OPTION_NO_M4100:
14540 mips_set_option_string (&mips_arch_string, "3900");
14541 mips_set_option_string (&mips_tune_string, "3900");
14544 case OPTION_NO_M3900:
14548 mips_opts.ase_mdmx = 1;
14551 case OPTION_NO_MDMX:
14552 mips_opts.ase_mdmx = 0;
14556 mips_opts.ase_dsp = 1;
14557 mips_opts.ase_dspr2 = 0;
14560 case OPTION_NO_DSP:
14561 mips_opts.ase_dsp = 0;
14562 mips_opts.ase_dspr2 = 0;
14566 mips_opts.ase_dspr2 = 1;
14567 mips_opts.ase_dsp = 1;
14570 case OPTION_NO_DSPR2:
14571 mips_opts.ase_dspr2 = 0;
14572 mips_opts.ase_dsp = 0;
14576 mips_opts.ase_mt = 1;
14580 mips_opts.ase_mt = 0;
14584 mips_opts.ase_mcu = 1;
14587 case OPTION_NO_MCU:
14588 mips_opts.ase_mcu = 0;
14591 case OPTION_MICROMIPS:
14592 if (mips_opts.mips16 == 1)
14594 as_bad (_("-mmicromips cannot be used with -mips16"));
14597 mips_opts.micromips = 1;
14598 mips_no_prev_insn ();
14601 case OPTION_NO_MICROMIPS:
14602 mips_opts.micromips = 0;
14603 mips_no_prev_insn ();
14606 case OPTION_MIPS16:
14607 if (mips_opts.micromips == 1)
14609 as_bad (_("-mips16 cannot be used with -micromips"));
14612 mips_opts.mips16 = 1;
14613 mips_no_prev_insn ();
14616 case OPTION_NO_MIPS16:
14617 mips_opts.mips16 = 0;
14618 mips_no_prev_insn ();
14621 case OPTION_MIPS3D:
14622 mips_opts.ase_mips3d = 1;
14625 case OPTION_NO_MIPS3D:
14626 mips_opts.ase_mips3d = 0;
14629 case OPTION_SMARTMIPS:
14630 mips_opts.ase_smartmips = 1;
14633 case OPTION_NO_SMARTMIPS:
14634 mips_opts.ase_smartmips = 0;
14637 case OPTION_FIX_24K:
14641 case OPTION_NO_FIX_24K:
14645 case OPTION_FIX_LOONGSON2F_JUMP:
14646 mips_fix_loongson2f_jump = TRUE;
14649 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14650 mips_fix_loongson2f_jump = FALSE;
14653 case OPTION_FIX_LOONGSON2F_NOP:
14654 mips_fix_loongson2f_nop = TRUE;
14657 case OPTION_NO_FIX_LOONGSON2F_NOP:
14658 mips_fix_loongson2f_nop = FALSE;
14661 case OPTION_FIX_VR4120:
14662 mips_fix_vr4120 = 1;
14665 case OPTION_NO_FIX_VR4120:
14666 mips_fix_vr4120 = 0;
14669 case OPTION_FIX_VR4130:
14670 mips_fix_vr4130 = 1;
14673 case OPTION_NO_FIX_VR4130:
14674 mips_fix_vr4130 = 0;
14677 case OPTION_FIX_CN63XXP1:
14678 mips_fix_cn63xxp1 = TRUE;
14681 case OPTION_NO_FIX_CN63XXP1:
14682 mips_fix_cn63xxp1 = FALSE;
14685 case OPTION_RELAX_BRANCH:
14686 mips_relax_branch = 1;
14689 case OPTION_NO_RELAX_BRANCH:
14690 mips_relax_branch = 0;
14693 case OPTION_MSHARED:
14694 mips_in_shared = TRUE;
14697 case OPTION_MNO_SHARED:
14698 mips_in_shared = FALSE;
14701 case OPTION_MSYM32:
14702 mips_opts.sym32 = TRUE;
14705 case OPTION_MNO_SYM32:
14706 mips_opts.sym32 = FALSE;
14710 /* When generating ELF code, we permit -KPIC and -call_shared to
14711 select SVR4_PIC, and -non_shared to select no PIC. This is
14712 intended to be compatible with Irix 5. */
14713 case OPTION_CALL_SHARED:
14716 as_bad (_("-call_shared is supported only for ELF format"));
14719 mips_pic = SVR4_PIC;
14720 mips_abicalls = TRUE;
14723 case OPTION_CALL_NONPIC:
14726 as_bad (_("-call_nonpic is supported only for ELF format"));
14730 mips_abicalls = TRUE;
14733 case OPTION_NON_SHARED:
14736 as_bad (_("-non_shared is supported only for ELF format"));
14740 mips_abicalls = FALSE;
14743 /* The -xgot option tells the assembler to use 32 bit offsets
14744 when accessing the got in SVR4_PIC mode. It is for Irix
14749 #endif /* OBJ_ELF */
14752 g_switch_value = atoi (arg);
14756 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14760 mips_abi = O32_ABI;
14761 /* We silently ignore -32 for non-ELF targets. This greatly
14762 simplifies the construction of the MIPS GAS test cases. */
14769 as_bad (_("-n32 is supported for ELF format only"));
14772 mips_abi = N32_ABI;
14778 as_bad (_("-64 is supported for ELF format only"));
14781 mips_abi = N64_ABI;
14782 if (!support_64bit_objects())
14783 as_fatal (_("No compiled in support for 64 bit object file format"));
14785 #endif /* OBJ_ELF */
14788 file_mips_gp32 = 1;
14792 file_mips_gp32 = 0;
14796 file_mips_fp32 = 1;
14800 file_mips_fp32 = 0;
14803 case OPTION_SINGLE_FLOAT:
14804 file_mips_single_float = 1;
14807 case OPTION_DOUBLE_FLOAT:
14808 file_mips_single_float = 0;
14811 case OPTION_SOFT_FLOAT:
14812 file_mips_soft_float = 1;
14815 case OPTION_HARD_FLOAT:
14816 file_mips_soft_float = 0;
14823 as_bad (_("-mabi is supported for ELF format only"));
14826 if (strcmp (arg, "32") == 0)
14827 mips_abi = O32_ABI;
14828 else if (strcmp (arg, "o64") == 0)
14829 mips_abi = O64_ABI;
14830 else if (strcmp (arg, "n32") == 0)
14831 mips_abi = N32_ABI;
14832 else if (strcmp (arg, "64") == 0)
14834 mips_abi = N64_ABI;
14835 if (! support_64bit_objects())
14836 as_fatal (_("No compiled in support for 64 bit object file "
14839 else if (strcmp (arg, "eabi") == 0)
14840 mips_abi = EABI_ABI;
14843 as_fatal (_("invalid abi -mabi=%s"), arg);
14847 #endif /* OBJ_ELF */
14849 case OPTION_M7000_HILO_FIX:
14850 mips_7000_hilo_fix = TRUE;
14853 case OPTION_MNO_7000_HILO_FIX:
14854 mips_7000_hilo_fix = FALSE;
14858 case OPTION_MDEBUG:
14859 mips_flag_mdebug = TRUE;
14862 case OPTION_NO_MDEBUG:
14863 mips_flag_mdebug = FALSE;
14867 mips_flag_pdr = TRUE;
14870 case OPTION_NO_PDR:
14871 mips_flag_pdr = FALSE;
14874 case OPTION_MVXWORKS_PIC:
14875 mips_pic = VXWORKS_PIC;
14877 #endif /* OBJ_ELF */
14883 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14888 /* Set up globals to generate code for the ISA or processor
14889 described by INFO. */
14892 mips_set_architecture (const struct mips_cpu_info *info)
14896 file_mips_arch = info->cpu;
14897 mips_opts.arch = info->cpu;
14898 mips_opts.isa = info->isa;
14903 /* Likewise for tuning. */
14906 mips_set_tune (const struct mips_cpu_info *info)
14909 mips_tune = info->cpu;
14914 mips_after_parse_args (void)
14916 const struct mips_cpu_info *arch_info = 0;
14917 const struct mips_cpu_info *tune_info = 0;
14919 /* GP relative stuff not working for PE */
14920 if (strncmp (TARGET_OS, "pe", 2) == 0)
14922 if (g_switch_seen && g_switch_value != 0)
14923 as_bad (_("-G not supported in this configuration."));
14924 g_switch_value = 0;
14927 if (mips_abi == NO_ABI)
14928 mips_abi = MIPS_DEFAULT_ABI;
14930 /* The following code determines the architecture and register size.
14931 Similar code was added to GCC 3.3 (see override_options() in
14932 config/mips/mips.c). The GAS and GCC code should be kept in sync
14933 as much as possible. */
14935 if (mips_arch_string != 0)
14936 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14938 if (file_mips_isa != ISA_UNKNOWN)
14940 /* Handle -mipsN. At this point, file_mips_isa contains the
14941 ISA level specified by -mipsN, while arch_info->isa contains
14942 the -march selection (if any). */
14943 if (arch_info != 0)
14945 /* -march takes precedence over -mipsN, since it is more descriptive.
14946 There's no harm in specifying both as long as the ISA levels
14948 if (file_mips_isa != arch_info->isa)
14949 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
14950 mips_cpu_info_from_isa (file_mips_isa)->name,
14951 mips_cpu_info_from_isa (arch_info->isa)->name);
14954 arch_info = mips_cpu_info_from_isa (file_mips_isa);
14957 if (arch_info == 0)
14958 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14960 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14961 as_bad (_("-march=%s is not compatible with the selected ABI"),
14964 mips_set_architecture (arch_info);
14966 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
14967 if (mips_tune_string != 0)
14968 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14970 if (tune_info == 0)
14971 mips_set_tune (arch_info);
14973 mips_set_tune (tune_info);
14975 if (file_mips_gp32 >= 0)
14977 /* The user specified the size of the integer registers. Make sure
14978 it agrees with the ABI and ISA. */
14979 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14980 as_bad (_("-mgp64 used with a 32-bit processor"));
14981 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14982 as_bad (_("-mgp32 used with a 64-bit ABI"));
14983 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14984 as_bad (_("-mgp64 used with a 32-bit ABI"));
14988 /* Infer the integer register size from the ABI and processor.
14989 Restrict ourselves to 32-bit registers if that's all the
14990 processor has, or if the ABI cannot handle 64-bit registers. */
14991 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14992 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
14995 switch (file_mips_fp32)
14999 /* No user specified float register size.
15000 ??? GAS treats single-float processors as though they had 64-bit
15001 float registers (although it complains when double-precision
15002 instructions are used). As things stand, saying they have 32-bit
15003 registers would lead to spurious "register must be even" messages.
15004 So here we assume float registers are never smaller than the
15006 if (file_mips_gp32 == 0)
15007 /* 64-bit integer registers implies 64-bit float registers. */
15008 file_mips_fp32 = 0;
15009 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15010 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15011 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15012 file_mips_fp32 = 0;
15014 /* 32-bit float registers. */
15015 file_mips_fp32 = 1;
15018 /* The user specified the size of the float registers. Check if it
15019 agrees with the ABI and ISA. */
15021 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15022 as_bad (_("-mfp64 used with a 32-bit fpu"));
15023 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15024 && !ISA_HAS_MXHC1 (mips_opts.isa))
15025 as_warn (_("-mfp64 used with a 32-bit ABI"));
15028 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15029 as_warn (_("-mfp32 used with a 64-bit ABI"));
15033 /* End of GCC-shared inference code. */
15035 /* This flag is set when we have a 64-bit capable CPU but use only
15036 32-bit wide registers. Note that EABI does not use it. */
15037 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15038 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15039 || mips_abi == O32_ABI))
15040 mips_32bitmode = 1;
15042 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15043 as_bad (_("trap exception not supported at ISA 1"));
15045 /* If the selected architecture includes support for ASEs, enable
15046 generation of code for them. */
15047 if (mips_opts.mips16 == -1)
15048 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15049 if (mips_opts.micromips == -1)
15050 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15051 if (mips_opts.ase_mips3d == -1)
15052 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15053 && file_mips_fp32 == 0) ? 1 : 0;
15054 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15055 as_bad (_("-mfp32 used with -mips3d"));
15057 if (mips_opts.ase_mdmx == -1)
15058 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15059 && file_mips_fp32 == 0) ? 1 : 0;
15060 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15061 as_bad (_("-mfp32 used with -mdmx"));
15063 if (mips_opts.ase_smartmips == -1)
15064 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15065 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15066 as_warn (_("%s ISA does not support SmartMIPS"),
15067 mips_cpu_info_from_isa (mips_opts.isa)->name);
15069 if (mips_opts.ase_dsp == -1)
15070 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15071 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15072 as_warn (_("%s ISA does not support DSP ASE"),
15073 mips_cpu_info_from_isa (mips_opts.isa)->name);
15075 if (mips_opts.ase_dspr2 == -1)
15077 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15078 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15080 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15081 as_warn (_("%s ISA does not support DSP R2 ASE"),
15082 mips_cpu_info_from_isa (mips_opts.isa)->name);
15084 if (mips_opts.ase_mt == -1)
15085 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15086 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15087 as_warn (_("%s ISA does not support MT ASE"),
15088 mips_cpu_info_from_isa (mips_opts.isa)->name);
15090 if (mips_opts.ase_mcu == -1)
15091 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15092 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15093 as_warn (_("%s ISA does not support MCU ASE"),
15094 mips_cpu_info_from_isa (mips_opts.isa)->name);
15096 file_mips_isa = mips_opts.isa;
15097 file_ase_mips3d = mips_opts.ase_mips3d;
15098 file_ase_mdmx = mips_opts.ase_mdmx;
15099 file_ase_smartmips = mips_opts.ase_smartmips;
15100 file_ase_dsp = mips_opts.ase_dsp;
15101 file_ase_dspr2 = mips_opts.ase_dspr2;
15102 file_ase_mt = mips_opts.ase_mt;
15103 mips_opts.gp32 = file_mips_gp32;
15104 mips_opts.fp32 = file_mips_fp32;
15105 mips_opts.soft_float = file_mips_soft_float;
15106 mips_opts.single_float = file_mips_single_float;
15108 if (mips_flag_mdebug < 0)
15110 #ifdef OBJ_MAYBE_ECOFF
15111 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15112 mips_flag_mdebug = 1;
15114 #endif /* OBJ_MAYBE_ECOFF */
15115 mips_flag_mdebug = 0;
15120 mips_init_after_args (void)
15122 /* initialize opcodes */
15123 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15124 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15128 md_pcrel_from (fixS *fixP)
15130 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15131 switch (fixP->fx_r_type)
15133 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15134 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15135 /* Return the address of the delay slot. */
15138 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15139 case BFD_RELOC_MICROMIPS_JMP:
15140 case BFD_RELOC_16_PCREL_S2:
15141 case BFD_RELOC_MIPS_JMP:
15142 /* Return the address of the delay slot. */
15146 /* We have no relocation type for PC relative MIPS16 instructions. */
15147 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15148 as_bad_where (fixP->fx_file, fixP->fx_line,
15149 _("PC relative MIPS16 instruction references a different section"));
15154 /* This is called before the symbol table is processed. In order to
15155 work with gcc when using mips-tfile, we must keep all local labels.
15156 However, in other cases, we want to discard them. If we were
15157 called with -g, but we didn't see any debugging information, it may
15158 mean that gcc is smuggling debugging information through to
15159 mips-tfile, in which case we must generate all local labels. */
15162 mips_frob_file_before_adjust (void)
15164 #ifndef NO_ECOFF_DEBUGGING
15165 if (ECOFF_DEBUGGING
15167 && ! ecoff_debugging_seen)
15168 flag_keep_locals = 1;
15172 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15173 the corresponding LO16 reloc. This is called before md_apply_fix and
15174 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15175 relocation operators.
15177 For our purposes, a %lo() expression matches a %got() or %hi()
15180 (a) it refers to the same symbol; and
15181 (b) the offset applied in the %lo() expression is no lower than
15182 the offset applied in the %got() or %hi().
15184 (b) allows us to cope with code like:
15187 lh $4,%lo(foo+2)($4)
15189 ...which is legal on RELA targets, and has a well-defined behaviour
15190 if the user knows that adding 2 to "foo" will not induce a carry to
15193 When several %lo()s match a particular %got() or %hi(), we use the
15194 following rules to distinguish them:
15196 (1) %lo()s with smaller offsets are a better match than %lo()s with
15199 (2) %lo()s with no matching %got() or %hi() are better than those
15200 that already have a matching %got() or %hi().
15202 (3) later %lo()s are better than earlier %lo()s.
15204 These rules are applied in order.
15206 (1) means, among other things, that %lo()s with identical offsets are
15207 chosen if they exist.
15209 (2) means that we won't associate several high-part relocations with
15210 the same low-part relocation unless there's no alternative. Having
15211 several high parts for the same low part is a GNU extension; this rule
15212 allows careful users to avoid it.
15214 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15215 with the last high-part relocation being at the front of the list.
15216 It therefore makes sense to choose the last matching low-part
15217 relocation, all other things being equal. It's also easier
15218 to code that way. */
15221 mips_frob_file (void)
15223 struct mips_hi_fixup *l;
15224 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15226 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15228 segment_info_type *seginfo;
15229 bfd_boolean matched_lo_p;
15230 fixS **hi_pos, **lo_pos, **pos;
15232 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15234 /* If a GOT16 relocation turns out to be against a global symbol,
15235 there isn't supposed to be a matching LO. */
15236 if (got16_reloc_p (l->fixp->fx_r_type)
15237 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15240 /* Check quickly whether the next fixup happens to be a matching %lo. */
15241 if (fixup_has_matching_lo_p (l->fixp))
15244 seginfo = seg_info (l->seg);
15246 /* Set HI_POS to the position of this relocation in the chain.
15247 Set LO_POS to the position of the chosen low-part relocation.
15248 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15249 relocation that matches an immediately-preceding high-part
15253 matched_lo_p = FALSE;
15254 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15256 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15258 if (*pos == l->fixp)
15261 if ((*pos)->fx_r_type == looking_for_rtype
15262 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15263 && (*pos)->fx_offset >= l->fixp->fx_offset
15265 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15267 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15270 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15271 && fixup_has_matching_lo_p (*pos));
15274 /* If we found a match, remove the high-part relocation from its
15275 current position and insert it before the low-part relocation.
15276 Make the offsets match so that fixup_has_matching_lo_p()
15279 We don't warn about unmatched high-part relocations since some
15280 versions of gcc have been known to emit dead "lui ...%hi(...)"
15282 if (lo_pos != NULL)
15284 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15285 if (l->fixp->fx_next != *lo_pos)
15287 *hi_pos = l->fixp->fx_next;
15288 l->fixp->fx_next = *lo_pos;
15295 /* We may have combined relocations without symbols in the N32/N64 ABI.
15296 We have to prevent gas from dropping them. */
15299 mips_force_relocation (fixS *fixp)
15301 if (generic_force_reloc (fixp))
15304 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15305 so that the linker relaxation can update targets. */
15306 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15307 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15308 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15312 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15313 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
15314 || hi16_reloc_p (fixp->fx_r_type)
15315 || lo16_reloc_p (fixp->fx_r_type)))
15321 /* Apply a fixup to the object file. */
15324 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15328 reloc_howto_type *howto;
15330 /* We ignore generic BFD relocations we don't know about. */
15331 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15335 gas_assert (fixP->fx_size == 2
15336 || fixP->fx_size == 4
15337 || fixP->fx_r_type == BFD_RELOC_16
15338 || fixP->fx_r_type == BFD_RELOC_64
15339 || fixP->fx_r_type == BFD_RELOC_CTOR
15340 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15341 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15342 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15343 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15344 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15346 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
15348 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15349 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15350 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15351 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15353 /* Don't treat parts of a composite relocation as done. There are two
15356 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15357 should nevertheless be emitted if the first part is.
15359 (2) In normal usage, composite relocations are never assembly-time
15360 constants. The easiest way of dealing with the pathological
15361 exceptions is to generate a relocation against STN_UNDEF and
15362 leave everything up to the linker. */
15363 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15366 switch (fixP->fx_r_type)
15368 case BFD_RELOC_MIPS_TLS_GD:
15369 case BFD_RELOC_MIPS_TLS_LDM:
15370 case BFD_RELOC_MIPS_TLS_DTPREL32:
15371 case BFD_RELOC_MIPS_TLS_DTPREL64:
15372 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15373 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15374 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15375 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15376 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15377 case BFD_RELOC_MICROMIPS_TLS_GD:
15378 case BFD_RELOC_MICROMIPS_TLS_LDM:
15379 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15380 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15381 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15382 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15383 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15384 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15387 case BFD_RELOC_MIPS_JMP:
15388 case BFD_RELOC_MIPS_SHIFT5:
15389 case BFD_RELOC_MIPS_SHIFT6:
15390 case BFD_RELOC_MIPS_GOT_DISP:
15391 case BFD_RELOC_MIPS_GOT_PAGE:
15392 case BFD_RELOC_MIPS_GOT_OFST:
15393 case BFD_RELOC_MIPS_SUB:
15394 case BFD_RELOC_MIPS_INSERT_A:
15395 case BFD_RELOC_MIPS_INSERT_B:
15396 case BFD_RELOC_MIPS_DELETE:
15397 case BFD_RELOC_MIPS_HIGHEST:
15398 case BFD_RELOC_MIPS_HIGHER:
15399 case BFD_RELOC_MIPS_SCN_DISP:
15400 case BFD_RELOC_MIPS_REL16:
15401 case BFD_RELOC_MIPS_RELGOT:
15402 case BFD_RELOC_MIPS_JALR:
15403 case BFD_RELOC_HI16:
15404 case BFD_RELOC_HI16_S:
15405 case BFD_RELOC_GPREL16:
15406 case BFD_RELOC_MIPS_LITERAL:
15407 case BFD_RELOC_MIPS_CALL16:
15408 case BFD_RELOC_MIPS_GOT16:
15409 case BFD_RELOC_GPREL32:
15410 case BFD_RELOC_MIPS_GOT_HI16:
15411 case BFD_RELOC_MIPS_GOT_LO16:
15412 case BFD_RELOC_MIPS_CALL_HI16:
15413 case BFD_RELOC_MIPS_CALL_LO16:
15414 case BFD_RELOC_MIPS16_GPREL:
15415 case BFD_RELOC_MIPS16_GOT16:
15416 case BFD_RELOC_MIPS16_CALL16:
15417 case BFD_RELOC_MIPS16_HI16:
15418 case BFD_RELOC_MIPS16_HI16_S:
15419 case BFD_RELOC_MIPS16_JMP:
15420 case BFD_RELOC_MICROMIPS_JMP:
15421 case BFD_RELOC_MICROMIPS_GOT_DISP:
15422 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15423 case BFD_RELOC_MICROMIPS_GOT_OFST:
15424 case BFD_RELOC_MICROMIPS_SUB:
15425 case BFD_RELOC_MICROMIPS_HIGHEST:
15426 case BFD_RELOC_MICROMIPS_HIGHER:
15427 case BFD_RELOC_MICROMIPS_SCN_DISP:
15428 case BFD_RELOC_MICROMIPS_JALR:
15429 case BFD_RELOC_MICROMIPS_HI16:
15430 case BFD_RELOC_MICROMIPS_HI16_S:
15431 case BFD_RELOC_MICROMIPS_GPREL16:
15432 case BFD_RELOC_MICROMIPS_LITERAL:
15433 case BFD_RELOC_MICROMIPS_CALL16:
15434 case BFD_RELOC_MICROMIPS_GOT16:
15435 case BFD_RELOC_MICROMIPS_GOT_HI16:
15436 case BFD_RELOC_MICROMIPS_GOT_LO16:
15437 case BFD_RELOC_MICROMIPS_CALL_HI16:
15438 case BFD_RELOC_MICROMIPS_CALL_LO16:
15439 /* Nothing needed to do. The value comes from the reloc entry. */
15443 /* This is handled like BFD_RELOC_32, but we output a sign
15444 extended value if we are only 32 bits. */
15447 if (8 <= sizeof (valueT))
15448 md_number_to_chars ((char *) buf, *valP, 8);
15453 if ((*valP & 0x80000000) != 0)
15457 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
15459 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
15465 case BFD_RELOC_RVA:
15468 /* If we are deleting this reloc entry, we must fill in the
15469 value now. This can happen if we have a .word which is not
15470 resolved when it appears but is later defined. */
15472 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
15475 case BFD_RELOC_LO16:
15476 case BFD_RELOC_MIPS16_LO16:
15477 case BFD_RELOC_MICROMIPS_LO16:
15478 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15479 may be safe to remove, but if so it's not obvious. */
15480 /* When handling an embedded PIC switch statement, we can wind
15481 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15484 if (*valP + 0x8000 > 0xffff)
15485 as_bad_where (fixP->fx_file, fixP->fx_line,
15486 _("relocation overflow"));
15487 /* 32-bit microMIPS instructions are divided into two halfwords.
15488 Relocations always refer to the second halfword, regardless
15490 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
15492 md_number_to_chars ((char *) buf, *valP, 2);
15496 case BFD_RELOC_16_PCREL_S2:
15497 if ((*valP & 0x3) != 0)
15498 as_bad_where (fixP->fx_file, fixP->fx_line,
15499 _("Branch to misaligned address (%lx)"), (long) *valP);
15501 /* We need to save the bits in the instruction since fixup_segment()
15502 might be deleting the relocation entry (i.e., a branch within
15503 the current segment). */
15504 if (! fixP->fx_done)
15507 /* Update old instruction data. */
15508 if (target_big_endian)
15509 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
15511 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
15513 if (*valP + 0x20000 <= 0x3ffff)
15515 insn |= (*valP >> 2) & 0xffff;
15516 md_number_to_chars ((char *) buf, insn, 4);
15518 else if (mips_pic == NO_PIC
15520 && fixP->fx_frag->fr_address >= text_section->vma
15521 && (fixP->fx_frag->fr_address
15522 < text_section->vma + bfd_get_section_size (text_section))
15523 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15524 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15525 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15527 /* The branch offset is too large. If this is an
15528 unconditional branch, and we are not generating PIC code,
15529 we can convert it to an absolute jump instruction. */
15530 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15531 insn = 0x0c000000; /* jal */
15533 insn = 0x08000000; /* j */
15534 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15536 fixP->fx_addsy = section_symbol (text_section);
15537 *valP += md_pcrel_from (fixP);
15538 md_number_to_chars ((char *) buf, insn, 4);
15542 /* If we got here, we have branch-relaxation disabled,
15543 and there's nothing we can do to fix this instruction
15544 without turning it into a longer sequence. */
15545 as_bad_where (fixP->fx_file, fixP->fx_line,
15546 _("Branch out of range"));
15550 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15551 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15552 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15553 /* We adjust the offset back to even. */
15554 if ((*valP & 0x1) != 0)
15557 if (! fixP->fx_done)
15560 /* Should never visit here, because we keep the relocation. */
15564 case BFD_RELOC_VTABLE_INHERIT:
15567 && !S_IS_DEFINED (fixP->fx_addsy)
15568 && !S_IS_WEAK (fixP->fx_addsy))
15569 S_SET_WEAK (fixP->fx_addsy);
15572 case BFD_RELOC_VTABLE_ENTRY:
15580 /* Remember value for tc_gen_reloc. */
15581 fixP->fx_addnumber = *valP;
15591 name = input_line_pointer;
15592 c = get_symbol_end ();
15593 p = (symbolS *) symbol_find_or_make (name);
15594 *input_line_pointer = c;
15598 /* Align the current frag to a given power of two. If a particular
15599 fill byte should be used, FILL points to an integer that contains
15600 that byte, otherwise FILL is null.
15602 The MIPS assembler also automatically adjusts any preceding
15606 mips_align (int to, int *fill, symbolS *label)
15608 mips_emit_delays ();
15609 mips_record_compressed_mode ();
15610 if (fill == NULL && subseg_text_p (now_seg))
15611 frag_align_code (to, 0);
15613 frag_align (to, fill ? *fill : 0, 0);
15614 record_alignment (now_seg, to);
15617 gas_assert (S_GET_SEGMENT (label) == now_seg);
15618 symbol_set_frag (label, frag_now);
15619 S_SET_VALUE (label, (valueT) frag_now_fix ());
15623 /* Align to a given power of two. .align 0 turns off the automatic
15624 alignment used by the data creating pseudo-ops. */
15627 s_align (int x ATTRIBUTE_UNUSED)
15629 int temp, fill_value, *fill_ptr;
15630 long max_alignment = 28;
15632 /* o Note that the assembler pulls down any immediately preceding label
15633 to the aligned address.
15634 o It's not documented but auto alignment is reinstated by
15635 a .align pseudo instruction.
15636 o Note also that after auto alignment is turned off the mips assembler
15637 issues an error on attempt to assemble an improperly aligned data item.
15640 temp = get_absolute_expression ();
15641 if (temp > max_alignment)
15642 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15645 as_warn (_("Alignment negative: 0 assumed."));
15648 if (*input_line_pointer == ',')
15650 ++input_line_pointer;
15651 fill_value = get_absolute_expression ();
15652 fill_ptr = &fill_value;
15658 segment_info_type *si = seg_info (now_seg);
15659 struct insn_label_list *l = si->label_list;
15660 /* Auto alignment should be switched on by next section change. */
15662 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
15669 demand_empty_rest_of_line ();
15673 s_change_sec (int sec)
15678 /* The ELF backend needs to know that we are changing sections, so
15679 that .previous works correctly. We could do something like check
15680 for an obj_section_change_hook macro, but that might be confusing
15681 as it would not be appropriate to use it in the section changing
15682 functions in read.c, since obj-elf.c intercepts those. FIXME:
15683 This should be cleaner, somehow. */
15685 obj_elf_section_change_hook ();
15688 mips_emit_delays ();
15699 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15700 demand_empty_rest_of_line ();
15704 seg = subseg_new (RDATA_SECTION_NAME,
15705 (subsegT) get_absolute_expression ());
15708 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15709 | SEC_READONLY | SEC_RELOC
15711 if (strncmp (TARGET_OS, "elf", 3) != 0)
15712 record_alignment (seg, 4);
15714 demand_empty_rest_of_line ();
15718 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15721 bfd_set_section_flags (stdoutput, seg,
15722 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15723 if (strncmp (TARGET_OS, "elf", 3) != 0)
15724 record_alignment (seg, 4);
15726 demand_empty_rest_of_line ();
15730 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15733 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15734 if (strncmp (TARGET_OS, "elf", 3) != 0)
15735 record_alignment (seg, 4);
15737 demand_empty_rest_of_line ();
15745 s_change_section (int ignore ATTRIBUTE_UNUSED)
15748 char *section_name;
15753 int section_entry_size;
15754 int section_alignment;
15759 section_name = input_line_pointer;
15760 c = get_symbol_end ();
15762 next_c = *(input_line_pointer + 1);
15764 /* Do we have .section Name<,"flags">? */
15765 if (c != ',' || (c == ',' && next_c == '"'))
15767 /* just after name is now '\0'. */
15768 *input_line_pointer = c;
15769 input_line_pointer = section_name;
15770 obj_elf_section (ignore);
15773 input_line_pointer++;
15775 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15777 section_type = get_absolute_expression ();
15780 if (*input_line_pointer++ == ',')
15781 section_flag = get_absolute_expression ();
15784 if (*input_line_pointer++ == ',')
15785 section_entry_size = get_absolute_expression ();
15787 section_entry_size = 0;
15788 if (*input_line_pointer++ == ',')
15789 section_alignment = get_absolute_expression ();
15791 section_alignment = 0;
15792 /* FIXME: really ignore? */
15793 (void) section_alignment;
15795 section_name = xstrdup (section_name);
15797 /* When using the generic form of .section (as implemented by obj-elf.c),
15798 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15799 traditionally had to fall back on the more common @progbits instead.
15801 There's nothing really harmful in this, since bfd will correct
15802 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15803 means that, for backwards compatibility, the special_section entries
15804 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15806 Even so, we shouldn't force users of the MIPS .section syntax to
15807 incorrectly label the sections as SHT_PROGBITS. The best compromise
15808 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15809 generic type-checking code. */
15810 if (section_type == SHT_MIPS_DWARF)
15811 section_type = SHT_PROGBITS;
15813 obj_elf_change_section (section_name, section_type, section_flag,
15814 section_entry_size, 0, 0, 0);
15816 if (now_seg->name != section_name)
15817 free (section_name);
15818 #endif /* OBJ_ELF */
15822 mips_enable_auto_align (void)
15828 s_cons (int log_size)
15830 segment_info_type *si = seg_info (now_seg);
15831 struct insn_label_list *l = si->label_list;
15834 label = l != NULL ? l->label : NULL;
15835 mips_emit_delays ();
15836 if (log_size > 0 && auto_align)
15837 mips_align (log_size, 0, label);
15838 cons (1 << log_size);
15839 mips_clear_insn_labels ();
15843 s_float_cons (int type)
15845 segment_info_type *si = seg_info (now_seg);
15846 struct insn_label_list *l = si->label_list;
15849 label = l != NULL ? l->label : NULL;
15851 mips_emit_delays ();
15856 mips_align (3, 0, label);
15858 mips_align (2, 0, label);
15862 mips_clear_insn_labels ();
15865 /* Handle .globl. We need to override it because on Irix 5 you are
15868 where foo is an undefined symbol, to mean that foo should be
15869 considered to be the address of a function. */
15872 s_mips_globl (int x ATTRIBUTE_UNUSED)
15881 name = input_line_pointer;
15882 c = get_symbol_end ();
15883 symbolP = symbol_find_or_make (name);
15884 S_SET_EXTERNAL (symbolP);
15886 *input_line_pointer = c;
15887 SKIP_WHITESPACE ();
15889 /* On Irix 5, every global symbol that is not explicitly labelled as
15890 being a function is apparently labelled as being an object. */
15893 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15894 && (*input_line_pointer != ','))
15899 secname = input_line_pointer;
15900 c = get_symbol_end ();
15901 sec = bfd_get_section_by_name (stdoutput, secname);
15903 as_bad (_("%s: no such section"), secname);
15904 *input_line_pointer = c;
15906 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15907 flag = BSF_FUNCTION;
15910 symbol_get_bfdsym (symbolP)->flags |= flag;
15912 c = *input_line_pointer;
15915 input_line_pointer++;
15916 SKIP_WHITESPACE ();
15917 if (is_end_of_line[(unsigned char) *input_line_pointer])
15923 demand_empty_rest_of_line ();
15927 s_option (int x ATTRIBUTE_UNUSED)
15932 opt = input_line_pointer;
15933 c = get_symbol_end ();
15937 /* FIXME: What does this mean? */
15939 else if (strncmp (opt, "pic", 3) == 0)
15943 i = atoi (opt + 3);
15948 mips_pic = SVR4_PIC;
15949 mips_abicalls = TRUE;
15952 as_bad (_(".option pic%d not supported"), i);
15954 if (mips_pic == SVR4_PIC)
15956 if (g_switch_seen && g_switch_value != 0)
15957 as_warn (_("-G may not be used with SVR4 PIC code"));
15958 g_switch_value = 0;
15959 bfd_set_gp_size (stdoutput, 0);
15963 as_warn (_("Unrecognized option \"%s\""), opt);
15965 *input_line_pointer = c;
15966 demand_empty_rest_of_line ();
15969 /* This structure is used to hold a stack of .set values. */
15971 struct mips_option_stack
15973 struct mips_option_stack *next;
15974 struct mips_set_options options;
15977 static struct mips_option_stack *mips_opts_stack;
15979 /* Handle the .set pseudo-op. */
15982 s_mipsset (int x ATTRIBUTE_UNUSED)
15984 char *name = input_line_pointer, ch;
15986 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15987 ++input_line_pointer;
15988 ch = *input_line_pointer;
15989 *input_line_pointer = '\0';
15991 if (strcmp (name, "reorder") == 0)
15993 if (mips_opts.noreorder)
15996 else if (strcmp (name, "noreorder") == 0)
15998 if (!mips_opts.noreorder)
15999 start_noreorder ();
16001 else if (strncmp (name, "at=", 3) == 0)
16003 char *s = name + 3;
16005 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16006 as_bad (_("Unrecognized register name `%s'"), s);
16008 else if (strcmp (name, "at") == 0)
16010 mips_opts.at = ATREG;
16012 else if (strcmp (name, "noat") == 0)
16014 mips_opts.at = ZERO;
16016 else if (strcmp (name, "macro") == 0)
16018 mips_opts.warn_about_macros = 0;
16020 else if (strcmp (name, "nomacro") == 0)
16022 if (mips_opts.noreorder == 0)
16023 as_bad (_("`noreorder' must be set before `nomacro'"));
16024 mips_opts.warn_about_macros = 1;
16026 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16028 mips_opts.nomove = 0;
16030 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16032 mips_opts.nomove = 1;
16034 else if (strcmp (name, "bopt") == 0)
16036 mips_opts.nobopt = 0;
16038 else if (strcmp (name, "nobopt") == 0)
16040 mips_opts.nobopt = 1;
16042 else if (strcmp (name, "gp=default") == 0)
16043 mips_opts.gp32 = file_mips_gp32;
16044 else if (strcmp (name, "gp=32") == 0)
16045 mips_opts.gp32 = 1;
16046 else if (strcmp (name, "gp=64") == 0)
16048 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16049 as_warn (_("%s isa does not support 64-bit registers"),
16050 mips_cpu_info_from_isa (mips_opts.isa)->name);
16051 mips_opts.gp32 = 0;
16053 else if (strcmp (name, "fp=default") == 0)
16054 mips_opts.fp32 = file_mips_fp32;
16055 else if (strcmp (name, "fp=32") == 0)
16056 mips_opts.fp32 = 1;
16057 else if (strcmp (name, "fp=64") == 0)
16059 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16060 as_warn (_("%s isa does not support 64-bit floating point registers"),
16061 mips_cpu_info_from_isa (mips_opts.isa)->name);
16062 mips_opts.fp32 = 0;
16064 else if (strcmp (name, "softfloat") == 0)
16065 mips_opts.soft_float = 1;
16066 else if (strcmp (name, "hardfloat") == 0)
16067 mips_opts.soft_float = 0;
16068 else if (strcmp (name, "singlefloat") == 0)
16069 mips_opts.single_float = 1;
16070 else if (strcmp (name, "doublefloat") == 0)
16071 mips_opts.single_float = 0;
16072 else if (strcmp (name, "mips16") == 0
16073 || strcmp (name, "MIPS-16") == 0)
16075 if (mips_opts.micromips == 1)
16076 as_fatal (_("`mips16' cannot be used with `micromips'"));
16077 mips_opts.mips16 = 1;
16079 else if (strcmp (name, "nomips16") == 0
16080 || strcmp (name, "noMIPS-16") == 0)
16081 mips_opts.mips16 = 0;
16082 else if (strcmp (name, "micromips") == 0)
16084 if (mips_opts.mips16 == 1)
16085 as_fatal (_("`micromips' cannot be used with `mips16'"));
16086 mips_opts.micromips = 1;
16088 else if (strcmp (name, "nomicromips") == 0)
16089 mips_opts.micromips = 0;
16090 else if (strcmp (name, "smartmips") == 0)
16092 if (!ISA_SUPPORTS_SMARTMIPS)
16093 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16094 mips_cpu_info_from_isa (mips_opts.isa)->name);
16095 mips_opts.ase_smartmips = 1;
16097 else if (strcmp (name, "nosmartmips") == 0)
16098 mips_opts.ase_smartmips = 0;
16099 else if (strcmp (name, "mips3d") == 0)
16100 mips_opts.ase_mips3d = 1;
16101 else if (strcmp (name, "nomips3d") == 0)
16102 mips_opts.ase_mips3d = 0;
16103 else if (strcmp (name, "mdmx") == 0)
16104 mips_opts.ase_mdmx = 1;
16105 else if (strcmp (name, "nomdmx") == 0)
16106 mips_opts.ase_mdmx = 0;
16107 else if (strcmp (name, "dsp") == 0)
16109 if (!ISA_SUPPORTS_DSP_ASE)
16110 as_warn (_("%s ISA does not support DSP ASE"),
16111 mips_cpu_info_from_isa (mips_opts.isa)->name);
16112 mips_opts.ase_dsp = 1;
16113 mips_opts.ase_dspr2 = 0;
16115 else if (strcmp (name, "nodsp") == 0)
16117 mips_opts.ase_dsp = 0;
16118 mips_opts.ase_dspr2 = 0;
16120 else if (strcmp (name, "dspr2") == 0)
16122 if (!ISA_SUPPORTS_DSPR2_ASE)
16123 as_warn (_("%s ISA does not support DSP R2 ASE"),
16124 mips_cpu_info_from_isa (mips_opts.isa)->name);
16125 mips_opts.ase_dspr2 = 1;
16126 mips_opts.ase_dsp = 1;
16128 else if (strcmp (name, "nodspr2") == 0)
16130 mips_opts.ase_dspr2 = 0;
16131 mips_opts.ase_dsp = 0;
16133 else if (strcmp (name, "mt") == 0)
16135 if (!ISA_SUPPORTS_MT_ASE)
16136 as_warn (_("%s ISA does not support MT ASE"),
16137 mips_cpu_info_from_isa (mips_opts.isa)->name);
16138 mips_opts.ase_mt = 1;
16140 else if (strcmp (name, "nomt") == 0)
16141 mips_opts.ase_mt = 0;
16142 else if (strcmp (name, "mcu") == 0)
16143 mips_opts.ase_mcu = 1;
16144 else if (strcmp (name, "nomcu") == 0)
16145 mips_opts.ase_mcu = 0;
16146 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16150 /* Permit the user to change the ISA and architecture on the fly.
16151 Needless to say, misuse can cause serious problems. */
16152 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16155 mips_opts.isa = file_mips_isa;
16156 mips_opts.arch = file_mips_arch;
16158 else if (strncmp (name, "arch=", 5) == 0)
16160 const struct mips_cpu_info *p;
16162 p = mips_parse_cpu("internal use", name + 5);
16164 as_bad (_("unknown architecture %s"), name + 5);
16167 mips_opts.arch = p->cpu;
16168 mips_opts.isa = p->isa;
16171 else if (strncmp (name, "mips", 4) == 0)
16173 const struct mips_cpu_info *p;
16175 p = mips_parse_cpu("internal use", name);
16177 as_bad (_("unknown ISA level %s"), name + 4);
16180 mips_opts.arch = p->cpu;
16181 mips_opts.isa = p->isa;
16185 as_bad (_("unknown ISA or architecture %s"), name);
16187 switch (mips_opts.isa)
16195 mips_opts.gp32 = 1;
16196 mips_opts.fp32 = 1;
16203 mips_opts.gp32 = 0;
16204 mips_opts.fp32 = 0;
16207 as_bad (_("unknown ISA level %s"), name + 4);
16212 mips_opts.gp32 = file_mips_gp32;
16213 mips_opts.fp32 = file_mips_fp32;
16216 else if (strcmp (name, "autoextend") == 0)
16217 mips_opts.noautoextend = 0;
16218 else if (strcmp (name, "noautoextend") == 0)
16219 mips_opts.noautoextend = 1;
16220 else if (strcmp (name, "push") == 0)
16222 struct mips_option_stack *s;
16224 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16225 s->next = mips_opts_stack;
16226 s->options = mips_opts;
16227 mips_opts_stack = s;
16229 else if (strcmp (name, "pop") == 0)
16231 struct mips_option_stack *s;
16233 s = mips_opts_stack;
16235 as_bad (_(".set pop with no .set push"));
16238 /* If we're changing the reorder mode we need to handle
16239 delay slots correctly. */
16240 if (s->options.noreorder && ! mips_opts.noreorder)
16241 start_noreorder ();
16242 else if (! s->options.noreorder && mips_opts.noreorder)
16245 mips_opts = s->options;
16246 mips_opts_stack = s->next;
16250 else if (strcmp (name, "sym32") == 0)
16251 mips_opts.sym32 = TRUE;
16252 else if (strcmp (name, "nosym32") == 0)
16253 mips_opts.sym32 = FALSE;
16254 else if (strchr (name, ','))
16256 /* Generic ".set" directive; use the generic handler. */
16257 *input_line_pointer = ch;
16258 input_line_pointer = name;
16264 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16266 *input_line_pointer = ch;
16267 demand_empty_rest_of_line ();
16270 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16271 .option pic2. It means to generate SVR4 PIC calls. */
16274 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16276 mips_pic = SVR4_PIC;
16277 mips_abicalls = TRUE;
16279 if (g_switch_seen && g_switch_value != 0)
16280 as_warn (_("-G may not be used with SVR4 PIC code"));
16281 g_switch_value = 0;
16283 bfd_set_gp_size (stdoutput, 0);
16284 demand_empty_rest_of_line ();
16287 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16288 PIC code. It sets the $gp register for the function based on the
16289 function address, which is in the register named in the argument.
16290 This uses a relocation against _gp_disp, which is handled specially
16291 by the linker. The result is:
16292 lui $gp,%hi(_gp_disp)
16293 addiu $gp,$gp,%lo(_gp_disp)
16294 addu $gp,$gp,.cpload argument
16295 The .cpload argument is normally $25 == $t9.
16297 The -mno-shared option changes this to:
16298 lui $gp,%hi(__gnu_local_gp)
16299 addiu $gp,$gp,%lo(__gnu_local_gp)
16300 and the argument is ignored. This saves an instruction, but the
16301 resulting code is not position independent; it uses an absolute
16302 address for __gnu_local_gp. Thus code assembled with -mno-shared
16303 can go into an ordinary executable, but not into a shared library. */
16306 s_cpload (int ignore ATTRIBUTE_UNUSED)
16312 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16313 .cpload is ignored. */
16314 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16320 /* .cpload should be in a .set noreorder section. */
16321 if (mips_opts.noreorder == 0)
16322 as_warn (_(".cpload not in noreorder section"));
16324 reg = tc_get_register (0);
16326 /* If we need to produce a 64-bit address, we are better off using
16327 the default instruction sequence. */
16328 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16330 ex.X_op = O_symbol;
16331 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16333 ex.X_op_symbol = NULL;
16334 ex.X_add_number = 0;
16336 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16337 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16340 macro_build_lui (&ex, mips_gp_register);
16341 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16342 mips_gp_register, BFD_RELOC_LO16);
16344 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16345 mips_gp_register, reg);
16348 demand_empty_rest_of_line ();
16351 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16352 .cpsetup $reg1, offset|$reg2, label
16354 If offset is given, this results in:
16355 sd $gp, offset($sp)
16356 lui $gp, %hi(%neg(%gp_rel(label)))
16357 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16358 daddu $gp, $gp, $reg1
16360 If $reg2 is given, this results in:
16361 daddu $reg2, $gp, $0
16362 lui $gp, %hi(%neg(%gp_rel(label)))
16363 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16364 daddu $gp, $gp, $reg1
16365 $reg1 is normally $25 == $t9.
16367 The -mno-shared option replaces the last three instructions with
16369 addiu $gp,$gp,%lo(_gp) */
16372 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16374 expressionS ex_off;
16375 expressionS ex_sym;
16378 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16379 We also need NewABI support. */
16380 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16386 reg1 = tc_get_register (0);
16387 SKIP_WHITESPACE ();
16388 if (*input_line_pointer != ',')
16390 as_bad (_("missing argument separator ',' for .cpsetup"));
16394 ++input_line_pointer;
16395 SKIP_WHITESPACE ();
16396 if (*input_line_pointer == '$')
16398 mips_cpreturn_register = tc_get_register (0);
16399 mips_cpreturn_offset = -1;
16403 mips_cpreturn_offset = get_absolute_expression ();
16404 mips_cpreturn_register = -1;
16406 SKIP_WHITESPACE ();
16407 if (*input_line_pointer != ',')
16409 as_bad (_("missing argument separator ',' for .cpsetup"));
16413 ++input_line_pointer;
16414 SKIP_WHITESPACE ();
16415 expression (&ex_sym);
16418 if (mips_cpreturn_register == -1)
16420 ex_off.X_op = O_constant;
16421 ex_off.X_add_symbol = NULL;
16422 ex_off.X_op_symbol = NULL;
16423 ex_off.X_add_number = mips_cpreturn_offset;
16425 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16426 BFD_RELOC_LO16, SP);
16429 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16430 mips_gp_register, 0);
16432 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16434 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16435 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16438 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16439 mips_gp_register, -1, BFD_RELOC_GPREL16,
16440 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16442 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16443 mips_gp_register, reg1);
16449 ex.X_op = O_symbol;
16450 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16451 ex.X_op_symbol = NULL;
16452 ex.X_add_number = 0;
16454 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16455 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16457 macro_build_lui (&ex, mips_gp_register);
16458 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16459 mips_gp_register, BFD_RELOC_LO16);
16464 demand_empty_rest_of_line ();
16468 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16470 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16471 .cplocal is ignored. */
16472 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16478 mips_gp_register = tc_get_register (0);
16479 demand_empty_rest_of_line ();
16482 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16483 offset from $sp. The offset is remembered, and after making a PIC
16484 call $gp is restored from that location. */
16487 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16491 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16492 .cprestore is ignored. */
16493 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16499 mips_cprestore_offset = get_absolute_expression ();
16500 mips_cprestore_valid = 1;
16502 ex.X_op = O_constant;
16503 ex.X_add_symbol = NULL;
16504 ex.X_op_symbol = NULL;
16505 ex.X_add_number = mips_cprestore_offset;
16508 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16509 SP, HAVE_64BIT_ADDRESSES);
16512 demand_empty_rest_of_line ();
16515 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16516 was given in the preceding .cpsetup, it results in:
16517 ld $gp, offset($sp)
16519 If a register $reg2 was given there, it results in:
16520 daddu $gp, $reg2, $0 */
16523 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16527 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16528 We also need NewABI support. */
16529 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16536 if (mips_cpreturn_register == -1)
16538 ex.X_op = O_constant;
16539 ex.X_add_symbol = NULL;
16540 ex.X_op_symbol = NULL;
16541 ex.X_add_number = mips_cpreturn_offset;
16543 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16546 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16547 mips_cpreturn_register, 0);
16550 demand_empty_rest_of_line ();
16553 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
16554 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
16555 use in DWARF debug information. */
16558 s_dtprel_internal (size_t bytes)
16565 if (ex.X_op != O_symbol)
16567 as_bad (_("Unsupported use of %s"), (bytes == 8
16570 ignore_rest_of_line ();
16573 p = frag_more (bytes);
16574 md_number_to_chars (p, 0, bytes);
16575 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
16577 ? BFD_RELOC_MIPS_TLS_DTPREL64
16578 : BFD_RELOC_MIPS_TLS_DTPREL32));
16580 demand_empty_rest_of_line ();
16583 /* Handle .dtprelword. */
16586 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16588 s_dtprel_internal (4);
16591 /* Handle .dtpreldword. */
16594 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16596 s_dtprel_internal (8);
16599 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16600 code. It sets the offset to use in gp_rel relocations. */
16603 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16605 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16606 We also need NewABI support. */
16607 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16613 mips_gprel_offset = get_absolute_expression ();
16615 demand_empty_rest_of_line ();
16618 /* Handle the .gpword pseudo-op. This is used when generating PIC
16619 code. It generates a 32 bit GP relative reloc. */
16622 s_gpword (int ignore ATTRIBUTE_UNUSED)
16624 segment_info_type *si;
16625 struct insn_label_list *l;
16630 /* When not generating PIC code, this is treated as .word. */
16631 if (mips_pic != SVR4_PIC)
16637 si = seg_info (now_seg);
16638 l = si->label_list;
16639 label = l != NULL ? l->label : NULL;
16640 mips_emit_delays ();
16642 mips_align (2, 0, label);
16645 mips_clear_insn_labels ();
16647 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16649 as_bad (_("Unsupported use of .gpword"));
16650 ignore_rest_of_line ();
16654 md_number_to_chars (p, 0, 4);
16655 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16656 BFD_RELOC_GPREL32);
16658 demand_empty_rest_of_line ();
16662 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16664 segment_info_type *si;
16665 struct insn_label_list *l;
16670 /* When not generating PIC code, this is treated as .dword. */
16671 if (mips_pic != SVR4_PIC)
16677 si = seg_info (now_seg);
16678 l = si->label_list;
16679 label = l != NULL ? l->label : NULL;
16680 mips_emit_delays ();
16682 mips_align (3, 0, label);
16685 mips_clear_insn_labels ();
16687 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16689 as_bad (_("Unsupported use of .gpdword"));
16690 ignore_rest_of_line ();
16694 md_number_to_chars (p, 0, 8);
16695 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16696 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16698 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16699 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16700 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16702 demand_empty_rest_of_line ();
16705 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16706 tables in SVR4 PIC code. */
16709 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16713 /* This is ignored when not generating SVR4 PIC code. */
16714 if (mips_pic != SVR4_PIC)
16720 /* Add $gp to the register named as an argument. */
16722 reg = tc_get_register (0);
16723 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16726 demand_empty_rest_of_line ();
16729 /* Handle the .insn pseudo-op. This marks instruction labels in
16730 mips16/micromips mode. This permits the linker to handle them specially,
16731 such as generating jalx instructions when needed. We also make
16732 them odd for the duration of the assembly, in order to generate the
16733 right sort of code. We will make them even in the adjust_symtab
16734 routine, while leaving them marked. This is convenient for the
16735 debugger and the disassembler. The linker knows to make them odd
16739 s_insn (int ignore ATTRIBUTE_UNUSED)
16741 mips_mark_labels ();
16743 demand_empty_rest_of_line ();
16746 /* Handle a .stabn directive. We need these in order to mark a label
16747 as being a mips16 text label correctly. Sometimes the compiler
16748 will emit a label, followed by a .stabn, and then switch sections.
16749 If the label and .stabn are in mips16 mode, then the label is
16750 really a mips16 text label. */
16753 s_mips_stab (int type)
16756 mips_mark_labels ();
16761 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16764 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16771 name = input_line_pointer;
16772 c = get_symbol_end ();
16773 symbolP = symbol_find_or_make (name);
16774 S_SET_WEAK (symbolP);
16775 *input_line_pointer = c;
16777 SKIP_WHITESPACE ();
16779 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16781 if (S_IS_DEFINED (symbolP))
16783 as_bad (_("ignoring attempt to redefine symbol %s"),
16784 S_GET_NAME (symbolP));
16785 ignore_rest_of_line ();
16789 if (*input_line_pointer == ',')
16791 ++input_line_pointer;
16792 SKIP_WHITESPACE ();
16796 if (exp.X_op != O_symbol)
16798 as_bad (_("bad .weakext directive"));
16799 ignore_rest_of_line ();
16802 symbol_set_value_expression (symbolP, &exp);
16805 demand_empty_rest_of_line ();
16808 /* Parse a register string into a number. Called from the ECOFF code
16809 to parse .frame. The argument is non-zero if this is the frame
16810 register, so that we can record it in mips_frame_reg. */
16813 tc_get_register (int frame)
16817 SKIP_WHITESPACE ();
16818 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16822 mips_frame_reg = reg != 0 ? reg : SP;
16823 mips_frame_reg_valid = 1;
16824 mips_cprestore_valid = 0;
16830 md_section_align (asection *seg, valueT addr)
16832 int align = bfd_get_section_alignment (stdoutput, seg);
16836 /* We don't need to align ELF sections to the full alignment.
16837 However, Irix 5 may prefer that we align them at least to a 16
16838 byte boundary. We don't bother to align the sections if we
16839 are targeted for an embedded system. */
16840 if (strncmp (TARGET_OS, "elf", 3) == 0)
16846 return ((addr + (1 << align) - 1) & (-1 << align));
16849 /* Utility routine, called from above as well. If called while the
16850 input file is still being read, it's only an approximation. (For
16851 example, a symbol may later become defined which appeared to be
16852 undefined earlier.) */
16855 nopic_need_relax (symbolS *sym, int before_relaxing)
16860 if (g_switch_value > 0)
16862 const char *symname;
16865 /* Find out whether this symbol can be referenced off the $gp
16866 register. It can be if it is smaller than the -G size or if
16867 it is in the .sdata or .sbss section. Certain symbols can
16868 not be referenced off the $gp, although it appears as though
16870 symname = S_GET_NAME (sym);
16871 if (symname != (const char *) NULL
16872 && (strcmp (symname, "eprol") == 0
16873 || strcmp (symname, "etext") == 0
16874 || strcmp (symname, "_gp") == 0
16875 || strcmp (symname, "edata") == 0
16876 || strcmp (symname, "_fbss") == 0
16877 || strcmp (symname, "_fdata") == 0
16878 || strcmp (symname, "_ftext") == 0
16879 || strcmp (symname, "end") == 0
16880 || strcmp (symname, "_gp_disp") == 0))
16882 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16884 #ifndef NO_ECOFF_DEBUGGING
16885 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16886 && (symbol_get_obj (sym)->ecoff_extern_size
16887 <= g_switch_value))
16889 /* We must defer this decision until after the whole
16890 file has been read, since there might be a .extern
16891 after the first use of this symbol. */
16892 || (before_relaxing
16893 #ifndef NO_ECOFF_DEBUGGING
16894 && symbol_get_obj (sym)->ecoff_extern_size == 0
16896 && S_GET_VALUE (sym) == 0)
16897 || (S_GET_VALUE (sym) != 0
16898 && S_GET_VALUE (sym) <= g_switch_value)))
16902 const char *segname;
16904 segname = segment_name (S_GET_SEGMENT (sym));
16905 gas_assert (strcmp (segname, ".lit8") != 0
16906 && strcmp (segname, ".lit4") != 0);
16907 change = (strcmp (segname, ".sdata") != 0
16908 && strcmp (segname, ".sbss") != 0
16909 && strncmp (segname, ".sdata.", 7) != 0
16910 && strncmp (segname, ".sbss.", 6) != 0
16911 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16912 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16917 /* We are not optimizing for the $gp register. */
16922 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16925 pic_need_relax (symbolS *sym, asection *segtype)
16929 /* Handle the case of a symbol equated to another symbol. */
16930 while (symbol_equated_reloc_p (sym))
16934 /* It's possible to get a loop here in a badly written program. */
16935 n = symbol_get_value_expression (sym)->X_add_symbol;
16941 if (symbol_section_p (sym))
16944 symsec = S_GET_SEGMENT (sym);
16946 /* This must duplicate the test in adjust_reloc_syms. */
16947 return (symsec != &bfd_und_section
16948 && symsec != &bfd_abs_section
16949 && !bfd_is_com_section (symsec)
16950 && !s_is_linkonce (sym, segtype)
16952 /* A global or weak symbol is treated as external. */
16953 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
16959 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16960 extended opcode. SEC is the section the frag is in. */
16963 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16966 const struct mips16_immed_operand *op;
16968 int mintiny, maxtiny;
16972 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16974 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16977 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16978 op = mips16_immed_operands;
16979 while (op->type != type)
16982 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
16987 if (type == '<' || type == '>' || type == '[' || type == ']')
16990 maxtiny = 1 << op->nbits;
16995 maxtiny = (1 << op->nbits) - 1;
17000 mintiny = - (1 << (op->nbits - 1));
17001 maxtiny = (1 << (op->nbits - 1)) - 1;
17004 sym_frag = symbol_get_frag (fragp->fr_symbol);
17005 val = S_GET_VALUE (fragp->fr_symbol);
17006 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17012 /* We won't have the section when we are called from
17013 mips_relax_frag. However, we will always have been called
17014 from md_estimate_size_before_relax first. If this is a
17015 branch to a different section, we mark it as such. If SEC is
17016 NULL, and the frag is not marked, then it must be a branch to
17017 the same section. */
17020 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17025 /* Must have been called from md_estimate_size_before_relax. */
17028 fragp->fr_subtype =
17029 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17031 /* FIXME: We should support this, and let the linker
17032 catch branches and loads that are out of range. */
17033 as_bad_where (fragp->fr_file, fragp->fr_line,
17034 _("unsupported PC relative reference to different section"));
17038 if (fragp != sym_frag && sym_frag->fr_address == 0)
17039 /* Assume non-extended on the first relaxation pass.
17040 The address we have calculated will be bogus if this is
17041 a forward branch to another frag, as the forward frag
17042 will have fr_address == 0. */
17046 /* In this case, we know for sure that the symbol fragment is in
17047 the same section. If the relax_marker of the symbol fragment
17048 differs from the relax_marker of this fragment, we have not
17049 yet adjusted the symbol fragment fr_address. We want to add
17050 in STRETCH in order to get a better estimate of the address.
17051 This particularly matters because of the shift bits. */
17053 && sym_frag->relax_marker != fragp->relax_marker)
17057 /* Adjust stretch for any alignment frag. Note that if have
17058 been expanding the earlier code, the symbol may be
17059 defined in what appears to be an earlier frag. FIXME:
17060 This doesn't handle the fr_subtype field, which specifies
17061 a maximum number of bytes to skip when doing an
17063 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17065 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17068 stretch = - ((- stretch)
17069 & ~ ((1 << (int) f->fr_offset) - 1));
17071 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17080 addr = fragp->fr_address + fragp->fr_fix;
17082 /* The base address rules are complicated. The base address of
17083 a branch is the following instruction. The base address of a
17084 PC relative load or add is the instruction itself, but if it
17085 is in a delay slot (in which case it can not be extended) use
17086 the address of the instruction whose delay slot it is in. */
17087 if (type == 'p' || type == 'q')
17091 /* If we are currently assuming that this frag should be
17092 extended, then, the current address is two bytes
17094 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17097 /* Ignore the low bit in the target, since it will be set
17098 for a text label. */
17099 if ((val & 1) != 0)
17102 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17104 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17107 val -= addr & ~ ((1 << op->shift) - 1);
17109 /* Branch offsets have an implicit 0 in the lowest bit. */
17110 if (type == 'p' || type == 'q')
17113 /* If any of the shifted bits are set, we must use an extended
17114 opcode. If the address depends on the size of this
17115 instruction, this can lead to a loop, so we arrange to always
17116 use an extended opcode. We only check this when we are in
17117 the main relaxation loop, when SEC is NULL. */
17118 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17120 fragp->fr_subtype =
17121 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17125 /* If we are about to mark a frag as extended because the value
17126 is precisely maxtiny + 1, then there is a chance of an
17127 infinite loop as in the following code:
17132 In this case when the la is extended, foo is 0x3fc bytes
17133 away, so the la can be shrunk, but then foo is 0x400 away, so
17134 the la must be extended. To avoid this loop, we mark the
17135 frag as extended if it was small, and is about to become
17136 extended with a value of maxtiny + 1. */
17137 if (val == ((maxtiny + 1) << op->shift)
17138 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17141 fragp->fr_subtype =
17142 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17146 else if (symsec != absolute_section && sec != NULL)
17147 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17149 if ((val & ((1 << op->shift) - 1)) != 0
17150 || val < (mintiny << op->shift)
17151 || val > (maxtiny << op->shift))
17157 /* Compute the length of a branch sequence, and adjust the
17158 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17159 worst-case length is computed, with UPDATE being used to indicate
17160 whether an unconditional (-1), branch-likely (+1) or regular (0)
17161 branch is to be computed. */
17163 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17165 bfd_boolean toofar;
17169 && S_IS_DEFINED (fragp->fr_symbol)
17170 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17175 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17177 addr = fragp->fr_address + fragp->fr_fix + 4;
17181 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17184 /* If the symbol is not defined or it's in a different segment,
17185 assume the user knows what's going on and emit a short
17191 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17193 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17194 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17195 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17196 RELAX_BRANCH_LINK (fragp->fr_subtype),
17202 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17205 if (mips_pic != NO_PIC)
17207 /* Additional space for PIC loading of target address. */
17209 if (mips_opts.isa == ISA_MIPS1)
17210 /* Additional space for $at-stabilizing nop. */
17214 /* If branch is conditional. */
17215 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17222 /* Compute the length of a branch sequence, and adjust the
17223 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17224 worst-case length is computed, with UPDATE being used to indicate
17225 whether an unconditional (-1), or regular (0) branch is to be
17229 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17231 bfd_boolean toofar;
17235 && S_IS_DEFINED (fragp->fr_symbol)
17236 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17241 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17242 /* Ignore the low bit in the target, since it will be set
17243 for a text label. */
17244 if ((val & 1) != 0)
17247 addr = fragp->fr_address + fragp->fr_fix + 4;
17251 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17254 /* If the symbol is not defined or it's in a different segment,
17255 assume the user knows what's going on and emit a short
17261 if (fragp && update
17262 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17263 fragp->fr_subtype = (toofar
17264 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17265 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17270 bfd_boolean compact_known = fragp != NULL;
17271 bfd_boolean compact = FALSE;
17272 bfd_boolean uncond;
17275 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17277 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17279 uncond = update < 0;
17281 /* If label is out of range, we turn branch <br>:
17283 <br> label # 4 bytes
17289 nop # 2 bytes if compact && !PIC
17292 if (mips_pic == NO_PIC && (!compact_known || compact))
17295 /* If assembling PIC code, we further turn:
17301 lw/ld at, %got(label)(gp) # 4 bytes
17302 d/addiu at, %lo(label) # 4 bytes
17305 if (mips_pic != NO_PIC)
17308 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17310 <brneg> 0f # 4 bytes
17311 nop # 2 bytes if !compact
17314 length += (compact_known && compact) ? 4 : 6;
17320 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17321 bit accordingly. */
17324 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17326 bfd_boolean toofar;
17329 && S_IS_DEFINED (fragp->fr_symbol)
17330 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17336 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17337 /* Ignore the low bit in the target, since it will be set
17338 for a text label. */
17339 if ((val & 1) != 0)
17342 /* Assume this is a 2-byte branch. */
17343 addr = fragp->fr_address + fragp->fr_fix + 2;
17345 /* We try to avoid the infinite loop by not adding 2 more bytes for
17350 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17352 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17353 else if (type == 'E')
17354 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17359 /* If the symbol is not defined or it's in a different segment,
17360 we emit a normal 32-bit branch. */
17363 if (fragp && update
17364 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17366 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17367 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17375 /* Estimate the size of a frag before relaxing. Unless this is the
17376 mips16, we are not really relaxing here, and the final size is
17377 encoded in the subtype information. For the mips16, we have to
17378 decide whether we are using an extended opcode or not. */
17381 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17385 if (RELAX_BRANCH_P (fragp->fr_subtype))
17388 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17390 return fragp->fr_var;
17393 if (RELAX_MIPS16_P (fragp->fr_subtype))
17394 /* We don't want to modify the EXTENDED bit here; it might get us
17395 into infinite loops. We change it only in mips_relax_frag(). */
17396 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17398 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17402 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17403 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17404 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17405 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17406 fragp->fr_var = length;
17411 if (mips_pic == NO_PIC)
17412 change = nopic_need_relax (fragp->fr_symbol, 0);
17413 else if (mips_pic == SVR4_PIC)
17414 change = pic_need_relax (fragp->fr_symbol, segtype);
17415 else if (mips_pic == VXWORKS_PIC)
17416 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17423 fragp->fr_subtype |= RELAX_USE_SECOND;
17424 return -RELAX_FIRST (fragp->fr_subtype);
17427 return -RELAX_SECOND (fragp->fr_subtype);
17430 /* This is called to see whether a reloc against a defined symbol
17431 should be converted into a reloc against a section. */
17434 mips_fix_adjustable (fixS *fixp)
17436 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17437 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17440 if (fixp->fx_addsy == NULL)
17443 /* If symbol SYM is in a mergeable section, relocations of the form
17444 SYM + 0 can usually be made section-relative. The mergeable data
17445 is then identified by the section offset rather than by the symbol.
17447 However, if we're generating REL LO16 relocations, the offset is split
17448 between the LO16 and parterning high part relocation. The linker will
17449 need to recalculate the complete offset in order to correctly identify
17452 The linker has traditionally not looked for the parterning high part
17453 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17454 placed anywhere. Rather than break backwards compatibility by changing
17455 this, it seems better not to force the issue, and instead keep the
17456 original symbol. This will work with either linker behavior. */
17457 if ((lo16_reloc_p (fixp->fx_r_type)
17458 || reloc_needs_lo_p (fixp->fx_r_type))
17459 && HAVE_IN_PLACE_ADDENDS
17460 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17463 /* There is no place to store an in-place offset for JALR relocations.
17464 Likewise an in-range offset of PC-relative relocations may overflow
17465 the in-place relocatable field if recalculated against the start
17466 address of the symbol's containing section. */
17467 if (HAVE_IN_PLACE_ADDENDS
17468 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17472 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17473 to a floating-point stub. The same is true for non-R_MIPS16_26
17474 relocations against MIPS16 functions; in this case, the stub becomes
17475 the function's canonical address.
17477 Floating-point stubs are stored in unique .mips16.call.* or
17478 .mips16.fn.* sections. If a stub T for function F is in section S,
17479 the first relocation in section S must be against F; this is how the
17480 linker determines the target function. All relocations that might
17481 resolve to T must also be against F. We therefore have the following
17482 restrictions, which are given in an intentionally-redundant way:
17484 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17487 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17488 if that stub might be used.
17490 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17493 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17494 that stub might be used.
17496 There is a further restriction:
17498 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17499 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17500 targets with in-place addends; the relocation field cannot
17501 encode the low bit.
17503 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17504 against a MIPS16 symbol. We deal with (5) by by not reducing any
17505 such relocations on REL targets.
17507 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17508 relocation against some symbol R, no relocation against R may be
17509 reduced. (Note that this deals with (2) as well as (1) because
17510 relocations against global symbols will never be reduced on ELF
17511 targets.) This approach is a little simpler than trying to detect
17512 stub sections, and gives the "all or nothing" per-symbol consistency
17513 that we have for MIPS16 symbols. */
17515 && fixp->fx_subsy == NULL
17516 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17517 || *symbol_get_tc (fixp->fx_addsy)
17518 || (HAVE_IN_PLACE_ADDENDS
17519 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17520 && jmp_reloc_p (fixp->fx_r_type))))
17527 /* Translate internal representation of relocation info to BFD target
17531 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17533 static arelent *retval[4];
17535 bfd_reloc_code_real_type code;
17537 memset (retval, 0, sizeof(retval));
17538 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17539 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17540 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17541 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17543 if (fixp->fx_pcrel)
17545 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17546 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17547 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17548 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17550 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17551 Relocations want only the symbol offset. */
17552 reloc->addend = fixp->fx_addnumber + reloc->address;
17555 /* A gruesome hack which is a result of the gruesome gas
17556 reloc handling. What's worse, for COFF (as opposed to
17557 ECOFF), we might need yet another copy of reloc->address.
17558 See bfd_install_relocation. */
17559 reloc->addend += reloc->address;
17563 reloc->addend = fixp->fx_addnumber;
17565 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17566 entry to be used in the relocation's section offset. */
17567 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17569 reloc->address = reloc->addend;
17573 code = fixp->fx_r_type;
17575 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17576 if (reloc->howto == NULL)
17578 as_bad_where (fixp->fx_file, fixp->fx_line,
17579 _("Can not represent %s relocation in this object file format"),
17580 bfd_get_reloc_code_name (code));
17587 /* Relax a machine dependent frag. This returns the amount by which
17588 the current size of the frag should change. */
17591 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17593 if (RELAX_BRANCH_P (fragp->fr_subtype))
17595 offsetT old_var = fragp->fr_var;
17597 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17599 return fragp->fr_var - old_var;
17602 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17604 offsetT old_var = fragp->fr_var;
17605 offsetT new_var = 4;
17607 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17608 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17609 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17610 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17611 fragp->fr_var = new_var;
17613 return new_var - old_var;
17616 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17619 if (mips16_extended_frag (fragp, NULL, stretch))
17621 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17623 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17628 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17630 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17637 /* Convert a machine dependent frag. */
17640 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17642 if (RELAX_BRANCH_P (fragp->fr_subtype))
17645 unsigned long insn;
17649 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
17651 if (target_big_endian)
17652 insn = bfd_getb32 (buf);
17654 insn = bfd_getl32 (buf);
17656 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17658 /* We generate a fixup instead of applying it right now
17659 because, if there are linker relaxations, we're going to
17660 need the relocations. */
17661 exp.X_op = O_symbol;
17662 exp.X_add_symbol = fragp->fr_symbol;
17663 exp.X_add_number = fragp->fr_offset;
17665 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17666 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
17667 fixp->fx_file = fragp->fr_file;
17668 fixp->fx_line = fragp->fr_line;
17670 md_number_to_chars ((char *) buf, insn, 4);
17677 as_warn_where (fragp->fr_file, fragp->fr_line,
17678 _("Relaxed out-of-range branch into a jump"));
17680 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17683 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17685 /* Reverse the branch. */
17686 switch ((insn >> 28) & 0xf)
17689 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17690 have the condition reversed by tweaking a single
17691 bit, and their opcodes all have 0x4???????. */
17692 gas_assert ((insn & 0xf1000000) == 0x41000000);
17693 insn ^= 0x00010000;
17697 /* bltz 0x04000000 bgez 0x04010000
17698 bltzal 0x04100000 bgezal 0x04110000 */
17699 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17700 insn ^= 0x00010000;
17704 /* beq 0x10000000 bne 0x14000000
17705 blez 0x18000000 bgtz 0x1c000000 */
17706 insn ^= 0x04000000;
17714 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17716 /* Clear the and-link bit. */
17717 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17719 /* bltzal 0x04100000 bgezal 0x04110000
17720 bltzall 0x04120000 bgezall 0x04130000 */
17721 insn &= ~0x00100000;
17724 /* Branch over the branch (if the branch was likely) or the
17725 full jump (not likely case). Compute the offset from the
17726 current instruction to branch to. */
17727 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17731 /* How many bytes in instructions we've already emitted? */
17732 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17733 /* How many bytes in instructions from here to the end? */
17734 i = fragp->fr_var - i;
17736 /* Convert to instruction count. */
17738 /* Branch counts from the next instruction. */
17741 /* Branch over the jump. */
17742 md_number_to_chars ((char *) buf, insn, 4);
17746 md_number_to_chars ((char *) buf, 0, 4);
17749 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17751 /* beql $0, $0, 2f */
17753 /* Compute the PC offset from the current instruction to
17754 the end of the variable frag. */
17755 /* How many bytes in instructions we've already emitted? */
17756 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17757 /* How many bytes in instructions from here to the end? */
17758 i = fragp->fr_var - i;
17759 /* Convert to instruction count. */
17761 /* Don't decrement i, because we want to branch over the
17765 md_number_to_chars ((char *) buf, insn, 4);
17768 md_number_to_chars ((char *) buf, 0, 4);
17773 if (mips_pic == NO_PIC)
17776 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17777 ? 0x0c000000 : 0x08000000);
17778 exp.X_op = O_symbol;
17779 exp.X_add_symbol = fragp->fr_symbol;
17780 exp.X_add_number = fragp->fr_offset;
17782 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17783 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
17784 fixp->fx_file = fragp->fr_file;
17785 fixp->fx_line = fragp->fr_line;
17787 md_number_to_chars ((char *) buf, insn, 4);
17792 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17794 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17795 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17796 insn |= at << OP_SH_RT;
17797 exp.X_op = O_symbol;
17798 exp.X_add_symbol = fragp->fr_symbol;
17799 exp.X_add_number = fragp->fr_offset;
17801 if (fragp->fr_offset)
17803 exp.X_add_symbol = make_expr_symbol (&exp);
17804 exp.X_add_number = 0;
17807 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17808 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
17809 fixp->fx_file = fragp->fr_file;
17810 fixp->fx_line = fragp->fr_line;
17812 md_number_to_chars ((char *) buf, insn, 4);
17815 if (mips_opts.isa == ISA_MIPS1)
17818 md_number_to_chars ((char *) buf, 0, 4);
17822 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17823 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17824 insn |= at << OP_SH_RS | at << OP_SH_RT;
17826 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17827 4, &exp, FALSE, BFD_RELOC_LO16);
17828 fixp->fx_file = fragp->fr_file;
17829 fixp->fx_line = fragp->fr_line;
17831 md_number_to_chars ((char *) buf, insn, 4);
17835 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17839 insn |= at << OP_SH_RS;
17841 md_number_to_chars ((char *) buf, insn, 4);
17846 gas_assert (buf == (bfd_byte *)fragp->fr_literal
17847 + fragp->fr_fix + fragp->fr_var);
17849 fragp->fr_fix += fragp->fr_var;
17854 /* Relax microMIPS branches. */
17855 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17857 bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
17858 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17859 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17860 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17861 bfd_boolean short_ds;
17862 unsigned long insn;
17866 exp.X_op = O_symbol;
17867 exp.X_add_symbol = fragp->fr_symbol;
17868 exp.X_add_number = fragp->fr_offset;
17870 fragp->fr_fix += fragp->fr_var;
17872 /* Handle 16-bit branches that fit or are forced to fit. */
17873 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17875 /* We generate a fixup instead of applying it right now,
17876 because if there is linker relaxation, we're going to
17877 need the relocations. */
17879 fixp = fix_new_exp (fragp,
17880 buf - (bfd_byte *) fragp->fr_literal,
17882 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17883 else if (type == 'E')
17884 fixp = fix_new_exp (fragp,
17885 buf - (bfd_byte *) fragp->fr_literal,
17887 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17891 fixp->fx_file = fragp->fr_file;
17892 fixp->fx_line = fragp->fr_line;
17894 /* These relocations can have an addend that won't fit in
17896 fixp->fx_no_overflow = 1;
17901 /* Handle 32-bit branches that fit or are forced to fit. */
17902 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17903 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17905 /* We generate a fixup instead of applying it right now,
17906 because if there is linker relaxation, we're going to
17907 need the relocations. */
17908 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17909 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17910 fixp->fx_file = fragp->fr_file;
17911 fixp->fx_line = fragp->fr_line;
17917 /* Relax 16-bit branches to 32-bit branches. */
17920 if (target_big_endian)
17921 insn = bfd_getb16 (buf);
17923 insn = bfd_getl16 (buf);
17925 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17926 insn = 0x94000000; /* beq */
17927 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17929 unsigned long regno;
17931 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17932 regno = micromips_to_32_reg_d_map [regno];
17933 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17934 insn |= regno << MICROMIPSOP_SH_RS;
17939 /* Nothing else to do, just write it out. */
17940 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17941 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17943 md_number_to_chars ((char *) buf, insn >> 16, 2);
17945 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17948 gas_assert (buf == ((bfd_byte *) fragp->fr_literal
17955 unsigned long next;
17957 if (target_big_endian)
17959 insn = bfd_getb16 (buf);
17960 next = bfd_getb16 (buf + 2);
17964 insn = bfd_getl16 (buf);
17965 next = bfd_getl16 (buf + 2);
17967 insn = (insn << 16) | next;
17970 /* Relax 32-bit branches to a sequence of instructions. */
17971 as_warn_where (fragp->fr_file, fragp->fr_line,
17972 _("Relaxed out-of-range branch into a jump"));
17974 /* Set the short-delay-slot bit. */
17975 short_ds = al && (insn & 0x02000000) != 0;
17977 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17981 /* Reverse the branch. */
17982 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17983 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17984 insn ^= 0x20000000;
17985 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17986 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17987 || (insn & 0xffe00000) == 0x40800000 /* blez */
17988 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17989 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17990 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17991 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17992 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17993 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17994 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17995 insn ^= 0x00400000;
17996 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17997 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17998 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17999 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18000 insn ^= 0x00200000;
18006 /* Clear the and-link and short-delay-slot bits. */
18007 gas_assert ((insn & 0xfda00000) == 0x40200000);
18009 /* bltzal 0x40200000 bgezal 0x40600000 */
18010 /* bltzals 0x42200000 bgezals 0x42600000 */
18011 insn &= ~0x02200000;
18014 /* Make a label at the end for use with the branch. */
18015 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18016 micromips_label_inc ();
18017 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18019 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18023 fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
18024 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18025 fixp->fx_file = fragp->fr_file;
18026 fixp->fx_line = fragp->fr_line;
18028 /* Branch over the jump. */
18029 md_number_to_chars ((char *) buf, insn >> 16, 2);
18031 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18038 md_number_to_chars ((char *) buf, insn, 2);
18043 if (mips_pic == NO_PIC)
18045 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18047 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18048 insn = al ? jal : 0xd4000000;
18050 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18051 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
18052 fixp->fx_file = fragp->fr_file;
18053 fixp->fx_line = fragp->fr_line;
18055 md_number_to_chars ((char *) buf, insn >> 16, 2);
18057 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18064 md_number_to_chars ((char *) buf, insn, 2);
18070 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18071 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18072 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18074 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18075 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18076 insn |= at << MICROMIPSOP_SH_RT;
18078 if (exp.X_add_number)
18080 exp.X_add_symbol = make_expr_symbol (&exp);
18081 exp.X_add_number = 0;
18084 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18085 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
18086 fixp->fx_file = fragp->fr_file;
18087 fixp->fx_line = fragp->fr_line;
18089 md_number_to_chars ((char *) buf, insn >> 16, 2);
18091 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18094 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18095 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18096 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18098 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18099 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
18100 fixp->fx_file = fragp->fr_file;
18101 fixp->fx_line = fragp->fr_line;
18103 md_number_to_chars ((char *) buf, insn >> 16, 2);
18105 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18108 /* jr/jrc/jalr/jalrs $at */
18109 insn = al ? jalr : jr;
18110 insn |= at << MICROMIPSOP_SH_MJ;
18112 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18116 gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
18120 if (RELAX_MIPS16_P (fragp->fr_subtype))
18123 const struct mips16_immed_operand *op;
18124 bfd_boolean small, ext;
18127 unsigned long insn;
18128 bfd_boolean use_extend;
18129 unsigned short extend;
18131 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18132 op = mips16_immed_operands;
18133 while (op->type != type)
18136 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18147 val = resolve_symbol_value (fragp->fr_symbol);
18152 addr = fragp->fr_address + fragp->fr_fix;
18154 /* The rules for the base address of a PC relative reloc are
18155 complicated; see mips16_extended_frag. */
18156 if (type == 'p' || type == 'q')
18161 /* Ignore the low bit in the target, since it will be
18162 set for a text label. */
18163 if ((val & 1) != 0)
18166 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18168 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18171 addr &= ~ (addressT) ((1 << op->shift) - 1);
18174 /* Make sure the section winds up with the alignment we have
18177 record_alignment (asec, op->shift);
18181 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18182 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18183 as_warn_where (fragp->fr_file, fragp->fr_line,
18184 _("extended instruction in delay slot"));
18186 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
18188 if (target_big_endian)
18189 insn = bfd_getb16 (buf);
18191 insn = bfd_getl16 (buf);
18193 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
18194 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
18195 small, ext, &insn, &use_extend, &extend);
18199 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
18200 fragp->fr_fix += 2;
18204 md_number_to_chars ((char *) buf, insn, 2);
18205 fragp->fr_fix += 2;
18210 relax_substateT subtype = fragp->fr_subtype;
18211 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18212 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18216 first = RELAX_FIRST (subtype);
18217 second = RELAX_SECOND (subtype);
18218 fixp = (fixS *) fragp->fr_opcode;
18220 /* If the delay slot chosen does not match the size of the instruction,
18221 then emit a warning. */
18222 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18223 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18228 s = subtype & (RELAX_DELAY_SLOT_16BIT
18229 | RELAX_DELAY_SLOT_SIZE_FIRST
18230 | RELAX_DELAY_SLOT_SIZE_SECOND);
18231 msg = macro_warning (s);
18233 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18237 /* Possibly emit a warning if we've chosen the longer option. */
18238 if (use_second == second_longer)
18244 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18245 msg = macro_warning (s);
18247 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18251 /* Go through all the fixups for the first sequence. Disable them
18252 (by marking them as done) if we're going to use the second
18253 sequence instead. */
18255 && fixp->fx_frag == fragp
18256 && fixp->fx_where < fragp->fr_fix - second)
18258 if (subtype & RELAX_USE_SECOND)
18260 fixp = fixp->fx_next;
18263 /* Go through the fixups for the second sequence. Disable them if
18264 we're going to use the first sequence, otherwise adjust their
18265 addresses to account for the relaxation. */
18266 while (fixp && fixp->fx_frag == fragp)
18268 if (subtype & RELAX_USE_SECOND)
18269 fixp->fx_where -= first;
18272 fixp = fixp->fx_next;
18275 /* Now modify the frag contents. */
18276 if (subtype & RELAX_USE_SECOND)
18280 start = fragp->fr_literal + fragp->fr_fix - first - second;
18281 memmove (start, start + first, second);
18282 fragp->fr_fix -= first;
18285 fragp->fr_fix -= second;
18291 /* This function is called after the relocs have been generated.
18292 We've been storing mips16 text labels as odd. Here we convert them
18293 back to even for the convenience of the debugger. */
18296 mips_frob_file_after_relocs (void)
18299 unsigned int count, i;
18304 syms = bfd_get_outsymbols (stdoutput);
18305 count = bfd_get_symcount (stdoutput);
18306 for (i = 0; i < count; i++, syms++)
18307 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18308 && ((*syms)->value & 1) != 0)
18310 (*syms)->value &= ~1;
18311 /* If the symbol has an odd size, it was probably computed
18312 incorrectly, so adjust that as well. */
18313 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18314 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18320 /* This function is called whenever a label is defined, including fake
18321 labels instantiated off the dot special symbol. It is used when
18322 handling branch delays; if a branch has a label, we assume we cannot
18323 move it. This also bumps the value of the symbol by 1 in compressed
18327 mips_record_label (symbolS *sym)
18329 segment_info_type *si = seg_info (now_seg);
18330 struct insn_label_list *l;
18332 if (free_insn_labels == NULL)
18333 l = (struct insn_label_list *) xmalloc (sizeof *l);
18336 l = free_insn_labels;
18337 free_insn_labels = l->next;
18341 l->next = si->label_list;
18342 si->label_list = l;
18345 /* This function is called as tc_frob_label() whenever a label is defined
18346 and adds a DWARF-2 record we only want for true labels. */
18349 mips_define_label (symbolS *sym)
18351 mips_record_label (sym);
18353 dwarf2_emit_label (sym);
18357 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18359 /* Some special processing for a MIPS ELF file. */
18362 mips_elf_final_processing (void)
18364 /* Write out the register information. */
18365 if (mips_abi != N64_ABI)
18369 s.ri_gprmask = mips_gprmask;
18370 s.ri_cprmask[0] = mips_cprmask[0];
18371 s.ri_cprmask[1] = mips_cprmask[1];
18372 s.ri_cprmask[2] = mips_cprmask[2];
18373 s.ri_cprmask[3] = mips_cprmask[3];
18374 /* The gp_value field is set by the MIPS ELF backend. */
18376 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18377 ((Elf32_External_RegInfo *)
18378 mips_regmask_frag));
18382 Elf64_Internal_RegInfo s;
18384 s.ri_gprmask = mips_gprmask;
18386 s.ri_cprmask[0] = mips_cprmask[0];
18387 s.ri_cprmask[1] = mips_cprmask[1];
18388 s.ri_cprmask[2] = mips_cprmask[2];
18389 s.ri_cprmask[3] = mips_cprmask[3];
18390 /* The gp_value field is set by the MIPS ELF backend. */
18392 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18393 ((Elf64_External_RegInfo *)
18394 mips_regmask_frag));
18397 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18398 sort of BFD interface for this. */
18399 if (mips_any_noreorder)
18400 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18401 if (mips_pic != NO_PIC)
18403 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18404 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18407 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18409 /* Set MIPS ELF flags for ASEs. */
18410 /* We may need to define a new flag for DSP ASE, and set this flag when
18411 file_ase_dsp is true. */
18412 /* Same for DSP R2. */
18413 /* We may need to define a new flag for MT ASE, and set this flag when
18414 file_ase_mt is true. */
18415 if (file_ase_mips16)
18416 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18417 if (file_ase_micromips)
18418 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18419 #if 0 /* XXX FIXME */
18420 if (file_ase_mips3d)
18421 elf_elfheader (stdoutput)->e_flags |= ???;
18424 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18426 /* Set the MIPS ELF ABI flags. */
18427 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18428 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18429 else if (mips_abi == O64_ABI)
18430 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18431 else if (mips_abi == EABI_ABI)
18433 if (!file_mips_gp32)
18434 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18436 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18438 else if (mips_abi == N32_ABI)
18439 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18441 /* Nothing to do for N64_ABI. */
18443 if (mips_32bitmode)
18444 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18446 #if 0 /* XXX FIXME */
18447 /* 32 bit code with 64 bit FP registers. */
18448 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18449 elf_elfheader (stdoutput)->e_flags |= ???;
18453 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18455 typedef struct proc {
18457 symbolS *func_end_sym;
18458 unsigned long reg_mask;
18459 unsigned long reg_offset;
18460 unsigned long fpreg_mask;
18461 unsigned long fpreg_offset;
18462 unsigned long frame_offset;
18463 unsigned long frame_reg;
18464 unsigned long pc_reg;
18467 static procS cur_proc;
18468 static procS *cur_proc_ptr;
18469 static int numprocs;
18471 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18472 as "2", and a normal nop as "0". */
18474 #define NOP_OPCODE_MIPS 0
18475 #define NOP_OPCODE_MIPS16 1
18476 #define NOP_OPCODE_MICROMIPS 2
18479 mips_nop_opcode (void)
18481 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18482 return NOP_OPCODE_MICROMIPS;
18483 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18484 return NOP_OPCODE_MIPS16;
18486 return NOP_OPCODE_MIPS;
18489 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18490 32-bit microMIPS NOPs here (if applicable). */
18493 mips_handle_align (fragS *fragp)
18497 int bytes, size, excess;
18500 if (fragp->fr_type != rs_align_code)
18503 p = fragp->fr_literal + fragp->fr_fix;
18505 switch (nop_opcode)
18507 case NOP_OPCODE_MICROMIPS:
18508 opcode = micromips_nop32_insn.insn_opcode;
18511 case NOP_OPCODE_MIPS16:
18512 opcode = mips16_nop_insn.insn_opcode;
18515 case NOP_OPCODE_MIPS:
18517 opcode = nop_insn.insn_opcode;
18522 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18523 excess = bytes % size;
18525 /* Handle the leading part if we're not inserting a whole number of
18526 instructions, and make it the end of the fixed part of the frag.
18527 Try to fit in a short microMIPS NOP if applicable and possible,
18528 and use zeroes otherwise. */
18529 gas_assert (excess < 4);
18530 fragp->fr_fix += excess;
18535 /* Fall through. */
18537 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18539 md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
18544 /* Fall through. */
18547 /* Fall through. */
18552 md_number_to_chars (p, opcode, size);
18553 fragp->fr_var = size;
18557 md_obj_begin (void)
18564 /* Check for premature end, nesting errors, etc. */
18566 as_warn (_("missing .end at end of assembly"));
18575 if (*input_line_pointer == '-')
18577 ++input_line_pointer;
18580 if (!ISDIGIT (*input_line_pointer))
18581 as_bad (_("expected simple number"));
18582 if (input_line_pointer[0] == '0')
18584 if (input_line_pointer[1] == 'x')
18586 input_line_pointer += 2;
18587 while (ISXDIGIT (*input_line_pointer))
18590 val |= hex_value (*input_line_pointer++);
18592 return negative ? -val : val;
18596 ++input_line_pointer;
18597 while (ISDIGIT (*input_line_pointer))
18600 val |= *input_line_pointer++ - '0';
18602 return negative ? -val : val;
18605 if (!ISDIGIT (*input_line_pointer))
18607 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18608 *input_line_pointer, *input_line_pointer);
18609 as_warn (_("invalid number"));
18612 while (ISDIGIT (*input_line_pointer))
18615 val += *input_line_pointer++ - '0';
18617 return negative ? -val : val;
18620 /* The .file directive; just like the usual .file directive, but there
18621 is an initial number which is the ECOFF file index. In the non-ECOFF
18622 case .file implies DWARF-2. */
18625 s_mips_file (int x ATTRIBUTE_UNUSED)
18627 static int first_file_directive = 0;
18629 if (ECOFF_DEBUGGING)
18638 filename = dwarf2_directive_file (0);
18640 /* Versions of GCC up to 3.1 start files with a ".file"
18641 directive even for stabs output. Make sure that this
18642 ".file" is handled. Note that you need a version of GCC
18643 after 3.1 in order to support DWARF-2 on MIPS. */
18644 if (filename != NULL && ! first_file_directive)
18646 (void) new_logical_line (filename, -1);
18647 s_app_file_string (filename, 0);
18649 first_file_directive = 1;
18653 /* The .loc directive, implying DWARF-2. */
18656 s_mips_loc (int x ATTRIBUTE_UNUSED)
18658 if (!ECOFF_DEBUGGING)
18659 dwarf2_directive_loc (0);
18662 /* The .end directive. */
18665 s_mips_end (int x ATTRIBUTE_UNUSED)
18669 /* Following functions need their own .frame and .cprestore directives. */
18670 mips_frame_reg_valid = 0;
18671 mips_cprestore_valid = 0;
18673 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18676 demand_empty_rest_of_line ();
18681 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18682 as_warn (_(".end not in text section"));
18686 as_warn (_(".end directive without a preceding .ent directive."));
18687 demand_empty_rest_of_line ();
18693 gas_assert (S_GET_NAME (p));
18694 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18695 as_warn (_(".end symbol does not match .ent symbol."));
18697 if (debug_type == DEBUG_STABS)
18698 stabs_generate_asm_endfunc (S_GET_NAME (p),
18702 as_warn (_(".end directive missing or unknown symbol"));
18705 /* Create an expression to calculate the size of the function. */
18706 if (p && cur_proc_ptr)
18708 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18709 expressionS *exp = xmalloc (sizeof (expressionS));
18712 exp->X_op = O_subtract;
18713 exp->X_add_symbol = symbol_temp_new_now ();
18714 exp->X_op_symbol = p;
18715 exp->X_add_number = 0;
18717 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18720 /* Generate a .pdr section. */
18721 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18723 segT saved_seg = now_seg;
18724 subsegT saved_subseg = now_subseg;
18728 #ifdef md_flush_pending_output
18729 md_flush_pending_output ();
18732 gas_assert (pdr_seg);
18733 subseg_set (pdr_seg, 0);
18735 /* Write the symbol. */
18736 exp.X_op = O_symbol;
18737 exp.X_add_symbol = p;
18738 exp.X_add_number = 0;
18739 emit_expr (&exp, 4);
18741 fragp = frag_more (7 * 4);
18743 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18744 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18745 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18746 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18747 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18748 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18749 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18751 subseg_set (saved_seg, saved_subseg);
18753 #endif /* OBJ_ELF */
18755 cur_proc_ptr = NULL;
18758 /* The .aent and .ent directives. */
18761 s_mips_ent (int aent)
18765 symbolP = get_symbol ();
18766 if (*input_line_pointer == ',')
18767 ++input_line_pointer;
18768 SKIP_WHITESPACE ();
18769 if (ISDIGIT (*input_line_pointer)
18770 || *input_line_pointer == '-')
18773 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18774 as_warn (_(".ent or .aent not in text section."));
18776 if (!aent && cur_proc_ptr)
18777 as_warn (_("missing .end"));
18781 /* This function needs its own .frame and .cprestore directives. */
18782 mips_frame_reg_valid = 0;
18783 mips_cprestore_valid = 0;
18785 cur_proc_ptr = &cur_proc;
18786 memset (cur_proc_ptr, '\0', sizeof (procS));
18788 cur_proc_ptr->func_sym = symbolP;
18792 if (debug_type == DEBUG_STABS)
18793 stabs_generate_asm_func (S_GET_NAME (symbolP),
18794 S_GET_NAME (symbolP));
18797 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18799 demand_empty_rest_of_line ();
18802 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18803 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18804 s_mips_frame is used so that we can set the PDR information correctly.
18805 We can't use the ecoff routines because they make reference to the ecoff
18806 symbol table (in the mdebug section). */
18809 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18812 if (IS_ELF && !ECOFF_DEBUGGING)
18816 if (cur_proc_ptr == (procS *) NULL)
18818 as_warn (_(".frame outside of .ent"));
18819 demand_empty_rest_of_line ();
18823 cur_proc_ptr->frame_reg = tc_get_register (1);
18825 SKIP_WHITESPACE ();
18826 if (*input_line_pointer++ != ','
18827 || get_absolute_expression_and_terminator (&val) != ',')
18829 as_warn (_("Bad .frame directive"));
18830 --input_line_pointer;
18831 demand_empty_rest_of_line ();
18835 cur_proc_ptr->frame_offset = val;
18836 cur_proc_ptr->pc_reg = tc_get_register (0);
18838 demand_empty_rest_of_line ();
18841 #endif /* OBJ_ELF */
18845 /* The .fmask and .mask directives. If the mdebug section is present
18846 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18847 embedded targets, s_mips_mask is used so that we can set the PDR
18848 information correctly. We can't use the ecoff routines because they
18849 make reference to the ecoff symbol table (in the mdebug section). */
18852 s_mips_mask (int reg_type)
18855 if (IS_ELF && !ECOFF_DEBUGGING)
18859 if (cur_proc_ptr == (procS *) NULL)
18861 as_warn (_(".mask/.fmask outside of .ent"));
18862 demand_empty_rest_of_line ();
18866 if (get_absolute_expression_and_terminator (&mask) != ',')
18868 as_warn (_("Bad .mask/.fmask directive"));
18869 --input_line_pointer;
18870 demand_empty_rest_of_line ();
18874 off = get_absolute_expression ();
18876 if (reg_type == 'F')
18878 cur_proc_ptr->fpreg_mask = mask;
18879 cur_proc_ptr->fpreg_offset = off;
18883 cur_proc_ptr->reg_mask = mask;
18884 cur_proc_ptr->reg_offset = off;
18887 demand_empty_rest_of_line ();
18890 #endif /* OBJ_ELF */
18891 s_ignore (reg_type);
18894 /* A table describing all the processors gas knows about. Names are
18895 matched in the order listed.
18897 To ease comparison, please keep this table in the same order as
18898 gcc's mips_cpu_info_table[]. */
18899 static const struct mips_cpu_info mips_cpu_info_table[] =
18901 /* Entries for generic ISAs */
18902 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
18903 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
18904 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
18905 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
18906 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
18907 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
18908 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
18909 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
18910 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
18913 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
18914 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
18915 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
18918 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
18921 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
18922 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
18923 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
18924 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
18925 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
18926 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
18927 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
18928 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
18929 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
18930 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
18931 { "orion", 0, ISA_MIPS3, CPU_R4600 },
18932 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
18933 /* ST Microelectronics Loongson 2E and 2F cores */
18934 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
18935 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
18938 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
18939 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
18940 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
18941 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
18942 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
18943 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
18944 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
18945 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
18946 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
18947 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
18948 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
18949 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
18950 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
18951 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
18952 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
18955 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
18956 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
18957 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
18958 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18960 /* MIPS 32 Release 2 */
18961 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18962 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18963 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18964 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18965 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18966 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18967 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18968 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18969 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18970 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18971 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18972 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18973 /* Deprecated forms of the above. */
18974 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18975 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18976 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18977 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18978 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18979 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18980 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18981 /* Deprecated forms of the above. */
18982 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18983 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18984 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18985 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18986 ISA_MIPS32R2, CPU_MIPS32R2 },
18987 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18988 ISA_MIPS32R2, CPU_MIPS32R2 },
18989 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18990 ISA_MIPS32R2, CPU_MIPS32R2 },
18991 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18992 ISA_MIPS32R2, CPU_MIPS32R2 },
18993 /* Deprecated forms of the above. */
18994 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18995 ISA_MIPS32R2, CPU_MIPS32R2 },
18996 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18997 ISA_MIPS32R2, CPU_MIPS32R2 },
18998 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18999 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19000 ISA_MIPS32R2, CPU_MIPS32R2 },
19001 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19002 ISA_MIPS32R2, CPU_MIPS32R2 },
19003 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19004 ISA_MIPS32R2, CPU_MIPS32R2 },
19005 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19006 ISA_MIPS32R2, CPU_MIPS32R2 },
19007 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19008 ISA_MIPS32R2, CPU_MIPS32R2 },
19009 /* Deprecated forms of the above. */
19010 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19011 ISA_MIPS32R2, CPU_MIPS32R2 },
19012 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19013 ISA_MIPS32R2, CPU_MIPS32R2 },
19014 /* 1004K cores are multiprocessor versions of the 34K. */
19015 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19016 ISA_MIPS32R2, CPU_MIPS32R2 },
19017 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19018 ISA_MIPS32R2, CPU_MIPS32R2 },
19019 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19020 ISA_MIPS32R2, CPU_MIPS32R2 },
19021 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19022 ISA_MIPS32R2, CPU_MIPS32R2 },
19025 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19026 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19027 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19028 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19030 /* Broadcom SB-1 CPU core */
19031 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19032 ISA_MIPS64, CPU_SB1 },
19033 /* Broadcom SB-1A CPU core */
19034 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19035 ISA_MIPS64, CPU_SB1 },
19037 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19039 /* MIPS 64 Release 2 */
19041 /* Cavium Networks Octeon CPU core */
19042 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19045 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19052 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19053 with a final "000" replaced by "k". Ignore case.
19055 Note: this function is shared between GCC and GAS. */
19058 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19060 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19061 given++, canonical++;
19063 return ((*given == 0 && *canonical == 0)
19064 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19068 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19069 CPU name. We've traditionally allowed a lot of variation here.
19071 Note: this function is shared between GCC and GAS. */
19074 mips_matching_cpu_name_p (const char *canonical, const char *given)
19076 /* First see if the name matches exactly, or with a final "000"
19077 turned into "k". */
19078 if (mips_strict_matching_cpu_name_p (canonical, given))
19081 /* If not, try comparing based on numerical designation alone.
19082 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19083 if (TOLOWER (*given) == 'r')
19085 if (!ISDIGIT (*given))
19088 /* Skip over some well-known prefixes in the canonical name,
19089 hoping to find a number there too. */
19090 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19092 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19094 else if (TOLOWER (canonical[0]) == 'r')
19097 return mips_strict_matching_cpu_name_p (canonical, given);
19101 /* Parse an option that takes the name of a processor as its argument.
19102 OPTION is the name of the option and CPU_STRING is the argument.
19103 Return the corresponding processor enumeration if the CPU_STRING is
19104 recognized, otherwise report an error and return null.
19106 A similar function exists in GCC. */
19108 static const struct mips_cpu_info *
19109 mips_parse_cpu (const char *option, const char *cpu_string)
19111 const struct mips_cpu_info *p;
19113 /* 'from-abi' selects the most compatible architecture for the given
19114 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19115 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19116 version. Look first at the -mgp options, if given, otherwise base
19117 the choice on MIPS_DEFAULT_64BIT.
19119 Treat NO_ABI like the EABIs. One reason to do this is that the
19120 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19121 architecture. This code picks MIPS I for 'mips' and MIPS III for
19122 'mips64', just as we did in the days before 'from-abi'. */
19123 if (strcasecmp (cpu_string, "from-abi") == 0)
19125 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19126 return mips_cpu_info_from_isa (ISA_MIPS1);
19128 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19129 return mips_cpu_info_from_isa (ISA_MIPS3);
19131 if (file_mips_gp32 >= 0)
19132 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19134 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19139 /* 'default' has traditionally been a no-op. Probably not very useful. */
19140 if (strcasecmp (cpu_string, "default") == 0)
19143 for (p = mips_cpu_info_table; p->name != 0; p++)
19144 if (mips_matching_cpu_name_p (p->name, cpu_string))
19147 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19151 /* Return the canonical processor information for ISA (a member of the
19152 ISA_MIPS* enumeration). */
19154 static const struct mips_cpu_info *
19155 mips_cpu_info_from_isa (int isa)
19159 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19160 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19161 && isa == mips_cpu_info_table[i].isa)
19162 return (&mips_cpu_info_table[i]);
19167 static const struct mips_cpu_info *
19168 mips_cpu_info_from_arch (int arch)
19172 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19173 if (arch == mips_cpu_info_table[i].cpu)
19174 return (&mips_cpu_info_table[i]);
19180 show (FILE *stream, const char *string, int *col_p, int *first_p)
19184 fprintf (stream, "%24s", "");
19189 fprintf (stream, ", ");
19193 if (*col_p + strlen (string) > 72)
19195 fprintf (stream, "\n%24s", "");
19199 fprintf (stream, "%s", string);
19200 *col_p += strlen (string);
19206 md_show_usage (FILE *stream)
19211 fprintf (stream, _("\
19213 -EB generate big endian output\n\
19214 -EL generate little endian output\n\
19215 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19216 -G NUM allow referencing objects up to NUM bytes\n\
19217 implicitly with the gp register [default 8]\n"));
19218 fprintf (stream, _("\
19219 -mips1 generate MIPS ISA I instructions\n\
19220 -mips2 generate MIPS ISA II instructions\n\
19221 -mips3 generate MIPS ISA III instructions\n\
19222 -mips4 generate MIPS ISA IV instructions\n\
19223 -mips5 generate MIPS ISA V instructions\n\
19224 -mips32 generate MIPS32 ISA instructions\n\
19225 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19226 -mips64 generate MIPS64 ISA instructions\n\
19227 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19228 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19232 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19233 show (stream, mips_cpu_info_table[i].name, &column, &first);
19234 show (stream, "from-abi", &column, &first);
19235 fputc ('\n', stream);
19237 fprintf (stream, _("\
19238 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19239 -no-mCPU don't generate code specific to CPU.\n\
19240 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19244 show (stream, "3900", &column, &first);
19245 show (stream, "4010", &column, &first);
19246 show (stream, "4100", &column, &first);
19247 show (stream, "4650", &column, &first);
19248 fputc ('\n', stream);
19250 fprintf (stream, _("\
19251 -mips16 generate mips16 instructions\n\
19252 -no-mips16 do not generate mips16 instructions\n"));
19253 fprintf (stream, _("\
19254 -mmicromips generate microMIPS instructions\n\
19255 -mno-micromips do not generate microMIPS instructions\n"));
19256 fprintf (stream, _("\
19257 -msmartmips generate smartmips instructions\n\
19258 -mno-smartmips do not generate smartmips instructions\n"));
19259 fprintf (stream, _("\
19260 -mdsp generate DSP instructions\n\
19261 -mno-dsp do not generate DSP instructions\n"));
19262 fprintf (stream, _("\
19263 -mdspr2 generate DSP R2 instructions\n\
19264 -mno-dspr2 do not generate DSP R2 instructions\n"));
19265 fprintf (stream, _("\
19266 -mmt generate MT instructions\n\
19267 -mno-mt do not generate MT instructions\n"));
19268 fprintf (stream, _("\
19269 -mmcu generate MCU instructions\n\
19270 -mno-mcu do not generate MCU instructions\n"));
19271 fprintf (stream, _("\
19272 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19273 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19274 -mfix-vr4120 work around certain VR4120 errata\n\
19275 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19276 -mfix-24k insert a nop after ERET and DERET instructions\n\
19277 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19278 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19279 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19280 -msym32 assume all symbols have 32-bit values\n\
19281 -O0 remove unneeded NOPs, do not swap branches\n\
19282 -O remove unneeded NOPs and swap branches\n\
19283 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19284 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19285 fprintf (stream, _("\
19286 -mhard-float allow floating-point instructions\n\
19287 -msoft-float do not allow floating-point instructions\n\
19288 -msingle-float only allow 32-bit floating-point operations\n\
19289 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19290 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19293 fprintf (stream, _("\
19294 -KPIC, -call_shared generate SVR4 position independent code\n\
19295 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19296 -mvxworks-pic generate VxWorks position independent code\n\
19297 -non_shared do not generate code that can operate with DSOs\n\
19298 -xgot assume a 32 bit GOT\n\
19299 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19300 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19301 position dependent (non shared) code\n\
19302 -mabi=ABI create ABI conformant object file for:\n"));
19306 show (stream, "32", &column, &first);
19307 show (stream, "o64", &column, &first);
19308 show (stream, "n32", &column, &first);
19309 show (stream, "64", &column, &first);
19310 show (stream, "eabi", &column, &first);
19312 fputc ('\n', stream);
19314 fprintf (stream, _("\
19315 -32 create o32 ABI object file (default)\n\
19316 -n32 create n32 ABI object file\n\
19317 -64 create 64 ABI object file\n"));
19323 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19325 if (HAVE_64BIT_SYMBOLS)
19326 return dwarf2_format_64bit_irix;
19328 return dwarf2_format_32bit;
19333 mips_dwarf2_addr_size (void)
19335 if (HAVE_64BIT_OBJECTS)
19341 /* Standard calling conventions leave the CFA at SP on entry. */
19343 mips_cfi_frame_initial_instructions (void)
19345 cfi_add_CFA_def_cfa_register (SP);
19349 tc_mips_regname_to_dw2regnum (char *regname)
19351 unsigned int regnum = -1;
19354 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))