1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi = NO_ABI;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls = FALSE;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared = TRUE;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). These are set to -1
208 if they have not been initialized. Changed by `.set <asename>', by
209 command line options, and based on the default architecture. */
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
222 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
223 1 if we are, and -1 if the value has not been initialized. Changed
224 by `.set micromips' and `.set nomicromips', and the -mmicromips
225 and -mno-micromips command line options, and the default CPU. */
227 /* Non-zero if we should not reorder instructions. Changed by `.set
228 reorder' and `.set noreorder'. */
230 /* Non-zero if we should not permit the register designated "assembler
231 temporary" to be used in instructions. The value is the register
232 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
233 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
235 /* Non-zero if we should warn when a macro instruction expands into
236 more than one machine instruction. Changed by `.set nomacro' and
238 int warn_about_macros;
239 /* Non-zero if we should not move instructions. Changed by `.set
240 move', `.set volatile', `.set nomove', and `.set novolatile'. */
242 /* Non-zero if we should not optimize branches by moving the target
243 of the branch into the delay slot. Actually, we don't perform
244 this optimization anyhow. Changed by `.set bopt' and `.set
247 /* Non-zero if we should not autoextend mips16 instructions.
248 Changed by `.set autoextend' and `.set noautoextend'. */
250 /* Restrict general purpose registers and floating point registers
251 to 32 bit. This is initially determined when -mgp32 or -mfp32
252 is passed but can changed if the assembler code uses .set mipsN. */
255 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
256 command line option, and the default CPU. */
258 /* True if ".set sym32" is in effect. */
260 /* True if floating-point operations are not allowed. Changed by .set
261 softfloat or .set hardfloat, by command line options -msoft-float or
262 -mhard-float. The default is false. */
263 bfd_boolean soft_float;
265 /* True if only single-precision floating-point operations are allowed.
266 Changed by .set singlefloat or .set doublefloat, command-line options
267 -msingle-float or -mdouble-float. The default is false. */
268 bfd_boolean single_float;
271 /* This is the struct we use to hold the current set of options. Note
272 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
273 -1 to indicate that they have not been initialized. */
275 /* True if -mgp32 was passed. */
276 static int file_mips_gp32 = -1;
278 /* True if -mfp32 was passed. */
279 static int file_mips_fp32 = -1;
281 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
282 static int file_mips_soft_float = 0;
284 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
285 static int file_mips_single_float = 0;
287 static struct mips_set_options mips_opts =
289 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
290 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
291 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
292 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
293 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
294 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* True if -mips3d was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_mips3d;
333 /* True if -mdmx was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mdmx;
337 /* True if -msmartmips was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_smartmips;
341 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
342 || mips_opts.isa == ISA_MIPS32R2)
344 /* True if -mdsp was passed or implied by arguments passed on the
345 command line (e.g., by -march). */
346 static int file_ase_dsp;
348 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
349 || mips_opts.isa == ISA_MIPS64R2 \
350 || mips_opts.micromips)
352 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mdspr2 was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_dspr2;
358 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2 \
360 || mips_opts.micromips)
362 /* True if -mmt was passed or implied by arguments passed on the
363 command line (e.g., by -march). */
364 static int file_ase_mt;
366 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
367 || mips_opts.isa == ISA_MIPS64R2)
369 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2 \
371 || mips_opts.micromips)
373 /* The argument of the -march= flag. The architecture we are assembling. */
374 static int file_mips_arch = CPU_UNKNOWN;
375 static const char *mips_arch_string;
377 /* The argument of the -mtune= flag. The architecture for which we
379 static int mips_tune = CPU_UNKNOWN;
380 static const char *mips_tune_string;
382 /* True when generating 32-bit code for a 64-bit processor. */
383 static int mips_32bitmode = 0;
385 /* True if the given ABI requires 32-bit registers. */
386 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
388 /* Likewise 64-bit registers. */
389 #define ABI_NEEDS_64BIT_REGS(ABI) \
391 || (ABI) == N64_ABI \
394 /* Return true if ISA supports 64 bit wide gp registers. */
395 #define ISA_HAS_64BIT_REGS(ISA) \
396 ((ISA) == ISA_MIPS3 \
397 || (ISA) == ISA_MIPS4 \
398 || (ISA) == ISA_MIPS5 \
399 || (ISA) == ISA_MIPS64 \
400 || (ISA) == ISA_MIPS64R2)
402 /* Return true if ISA supports 64 bit wide float registers. */
403 #define ISA_HAS_64BIT_FPRS(ISA) \
404 ((ISA) == ISA_MIPS3 \
405 || (ISA) == ISA_MIPS4 \
406 || (ISA) == ISA_MIPS5 \
407 || (ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64 \
409 || (ISA) == ISA_MIPS64R2)
411 /* Return true if ISA supports 64-bit right rotate (dror et al.)
413 #define ISA_HAS_DROR(ISA) \
414 ((ISA) == ISA_MIPS64R2 \
415 || (mips_opts.micromips \
416 && ISA_HAS_64BIT_REGS (ISA)) \
419 /* Return true if ISA supports 32-bit right rotate (ror et al.)
421 #define ISA_HAS_ROR(ISA) \
422 ((ISA) == ISA_MIPS32R2 \
423 || (ISA) == ISA_MIPS64R2 \
424 || mips_opts.ase_smartmips \
425 || mips_opts.micromips \
428 /* Return true if ISA supports single-precision floats in odd registers. */
429 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
430 ((ISA) == ISA_MIPS32 \
431 || (ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS64 \
433 || (ISA) == ISA_MIPS64R2)
435 /* Return true if ISA supports move to/from high part of a 64-bit
436 floating-point register. */
437 #define ISA_HAS_MXHC1(ISA) \
438 ((ISA) == ISA_MIPS32R2 \
439 || (ISA) == ISA_MIPS64R2)
441 #define HAVE_32BIT_GPRS \
442 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
444 #define HAVE_32BIT_FPRS \
445 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
447 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
448 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
450 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
452 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
454 /* True if relocations are stored in-place. */
455 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
457 /* The ABI-derived address size. */
458 #define HAVE_64BIT_ADDRESSES \
459 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
460 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
462 /* The size of symbolic constants (i.e., expressions of the form
463 "SYMBOL" or "SYMBOL + OFFSET"). */
464 #define HAVE_32BIT_SYMBOLS \
465 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
466 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
468 /* Addresses are loaded in different ways, depending on the address size
469 in use. The n32 ABI Documentation also mandates the use of additions
470 with overflow checking, but existing implementations don't follow it. */
471 #define ADDRESS_ADD_INSN \
472 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
474 #define ADDRESS_ADDI_INSN \
475 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
477 #define ADDRESS_LOAD_INSN \
478 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
480 #define ADDRESS_STORE_INSN \
481 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
483 /* Return true if the given CPU supports the MIPS16 ASE. */
484 #define CPU_HAS_MIPS16(cpu) \
485 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
486 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
488 /* Return true if the given CPU supports the microMIPS ASE. */
489 #define CPU_HAS_MICROMIPS(cpu) 0
491 /* True if CPU has a dror instruction. */
492 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
494 /* True if CPU has a ror instruction. */
495 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
497 /* True if CPU is in the Octeon family */
498 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
500 /* True if CPU has seq/sne and seqi/snei instructions. */
501 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
574 has been selected. This implies, in particular, that addresses of text
575 labels have their LSB set. */
576 #define HAVE_CODE_COMPRESSION \
577 ((mips_opts.mips16 | mips_opts.micromips) != 0)
579 /* MIPS PIC level. */
581 enum mips_pic_level mips_pic;
583 /* 1 if we should generate 32 bit offsets from the $gp register in
584 SVR4_PIC mode. Currently has no meaning in other modes. */
585 static int mips_big_got = 0;
587 /* 1 if trap instructions should used for overflow rather than break
589 static int mips_trap = 0;
591 /* 1 if double width floating point constants should not be constructed
592 by assembling two single width halves into two single width floating
593 point registers which just happen to alias the double width destination
594 register. On some architectures this aliasing can be disabled by a bit
595 in the status register, and the setting of this bit cannot be determined
596 automatically at assemble time. */
597 static int mips_disable_float_construction;
599 /* Non-zero if any .set noreorder directives were used. */
601 static int mips_any_noreorder;
603 /* Non-zero if nops should be inserted when the register referenced in
604 an mfhi/mflo instruction is read in the next two instructions. */
605 static int mips_7000_hilo_fix;
607 /* The size of objects in the small data section. */
608 static unsigned int g_switch_value = 8;
609 /* Whether the -G option was used. */
610 static int g_switch_seen = 0;
615 /* If we can determine in advance that GP optimization won't be
616 possible, we can skip the relaxation stuff that tries to produce
617 GP-relative references. This makes delay slot optimization work
620 This function can only provide a guess, but it seems to work for
621 gcc output. It needs to guess right for gcc, otherwise gcc
622 will put what it thinks is a GP-relative instruction in a branch
625 I don't know if a fix is needed for the SVR4_PIC mode. I've only
626 fixed it for the non-PIC mode. KR 95/04/07 */
627 static int nopic_need_relax (symbolS *, int);
629 /* handle of the OPCODE hash table */
630 static struct hash_control *op_hash = NULL;
632 /* The opcode hash table we use for the mips16. */
633 static struct hash_control *mips16_op_hash = NULL;
635 /* The opcode hash table we use for the microMIPS ASE. */
636 static struct hash_control *micromips_op_hash = NULL;
638 /* This array holds the chars that always start a comment. If the
639 pre-processor is disabled, these aren't very useful */
640 const char comment_chars[] = "#";
642 /* This array holds the chars that only start a comment at the beginning of
643 a line. If the line seems to have the form '# 123 filename'
644 .line and .file directives will appear in the pre-processed output */
645 /* Note that input_file.c hand checks for '#' at the beginning of the
646 first line of the input file. This is because the compiler outputs
647 #NO_APP at the beginning of its output. */
648 /* Also note that C style comments are always supported. */
649 const char line_comment_chars[] = "#";
651 /* This array holds machine specific line separator characters. */
652 const char line_separator_chars[] = ";";
654 /* Chars that can be used to separate mant from exp in floating point nums */
655 const char EXP_CHARS[] = "eE";
657 /* Chars that mean this number is a floating point constant */
660 const char FLT_CHARS[] = "rRsSfFdDxXpP";
662 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
663 changed in read.c . Ideally it shouldn't have to know about it at all,
664 but nothing is ideal around here.
667 static char *insn_error;
669 static int auto_align = 1;
671 /* When outputting SVR4 PIC code, the assembler needs to know the
672 offset in the stack frame from which to restore the $gp register.
673 This is set by the .cprestore pseudo-op, and saved in this
675 static offsetT mips_cprestore_offset = -1;
677 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
678 more optimizations, it can use a register value instead of a memory-saved
679 offset and even an other register than $gp as global pointer. */
680 static offsetT mips_cpreturn_offset = -1;
681 static int mips_cpreturn_register = -1;
682 static int mips_gp_register = GP;
683 static int mips_gprel_offset = 0;
685 /* Whether mips_cprestore_offset has been set in the current function
686 (or whether it has already been warned about, if not). */
687 static int mips_cprestore_valid = 0;
689 /* This is the register which holds the stack frame, as set by the
690 .frame pseudo-op. This is needed to implement .cprestore. */
691 static int mips_frame_reg = SP;
693 /* Whether mips_frame_reg has been set in the current function
694 (or whether it has already been warned about, if not). */
695 static int mips_frame_reg_valid = 0;
697 /* To output NOP instructions correctly, we need to keep information
698 about the previous two instructions. */
700 /* Whether we are optimizing. The default value of 2 means to remove
701 unneeded NOPs and swap branch instructions when possible. A value
702 of 1 means to not swap branches. A value of 0 means to always
704 static int mips_optimize = 2;
706 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
707 equivalent to seeing no -g option at all. */
708 static int mips_debug = 0;
710 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
711 #define MAX_VR4130_NOPS 4
713 /* The maximum number of NOPs needed to fill delay slots. */
714 #define MAX_DELAY_NOPS 2
716 /* The maximum number of NOPs needed for any purpose. */
719 /* A list of previous instructions, with index 0 being the most recent.
720 We need to look back MAX_NOPS instructions when filling delay slots
721 or working around processor errata. We need to look back one
722 instruction further if we're thinking about using history[0] to
723 fill a branch delay slot. */
724 static struct mips_cl_insn history[1 + MAX_NOPS];
726 /* Nop instructions used by emit_nop. */
727 static struct mips_cl_insn nop_insn;
728 static struct mips_cl_insn mips16_nop_insn;
729 static struct mips_cl_insn micromips_nop16_insn;
730 static struct mips_cl_insn micromips_nop32_insn;
732 /* The appropriate nop for the current mode. */
733 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
734 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
736 /* The size of NOP_INSN in bytes. */
737 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
739 /* If this is set, it points to a frag holding nop instructions which
740 were inserted before the start of a noreorder section. If those
741 nops turn out to be unnecessary, the size of the frag can be
743 static fragS *prev_nop_frag;
745 /* The number of nop instructions we created in prev_nop_frag. */
746 static int prev_nop_frag_holds;
748 /* The number of nop instructions that we know we need in
750 static int prev_nop_frag_required;
752 /* The number of instructions we've seen since prev_nop_frag. */
753 static int prev_nop_frag_since;
755 /* For ECOFF and ELF, relocations against symbols are done in two
756 parts, with a HI relocation and a LO relocation. Each relocation
757 has only 16 bits of space to store an addend. This means that in
758 order for the linker to handle carries correctly, it must be able
759 to locate both the HI and the LO relocation. This means that the
760 relocations must appear in order in the relocation table.
762 In order to implement this, we keep track of each unmatched HI
763 relocation. We then sort them so that they immediately precede the
764 corresponding LO relocation. */
769 struct mips_hi_fixup *next;
772 /* The section this fixup is in. */
776 /* The list of unmatched HI relocs. */
778 static struct mips_hi_fixup *mips_hi_fixup_list;
780 /* The frag containing the last explicit relocation operator.
781 Null if explicit relocations have not been used. */
783 static fragS *prev_reloc_op_frag;
785 /* Map normal MIPS register numbers to mips16 register numbers. */
787 #define X ILLEGAL_REG
788 static const int mips32_to_16_reg_map[] =
790 X, X, 2, 3, 4, 5, 6, 7,
791 X, X, X, X, X, X, X, X,
792 0, 1, X, X, X, X, X, X,
793 X, X, X, X, X, X, X, X
797 /* Map mips16 register numbers to normal MIPS register numbers. */
799 static const unsigned int mips16_to_32_reg_map[] =
801 16, 17, 2, 3, 4, 5, 6, 7
804 /* Map normal MIPS register numbers to microMIPS register numbers. */
806 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
807 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
808 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
809 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
810 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
811 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
812 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
814 #define X ILLEGAL_REG
815 /* reg type h: 4, 5, 6. */
816 static const int mips32_to_micromips_reg_h_map[] =
818 X, X, X, X, 4, 5, 6, X,
819 X, X, X, X, X, X, X, X,
820 X, X, X, X, X, X, X, X,
821 X, X, X, X, X, X, X, X
824 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
825 static const int mips32_to_micromips_reg_m_map[] =
827 0, X, 2, 3, X, X, X, X,
828 X, X, X, X, X, X, X, X,
829 4, 1, 5, 6, 7, X, X, X,
830 X, X, X, X, X, X, X, X
833 /* reg type q: 0, 2-7. 17. */
834 static const int mips32_to_micromips_reg_q_map[] =
836 0, X, 2, 3, 4, 5, 6, 7,
837 X, X, X, X, X, X, X, X,
838 X, 1, X, X, X, X, X, X,
839 X, X, X, X, X, X, X, X
842 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
845 /* Map microMIPS register numbers to normal MIPS register numbers. */
847 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
848 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
849 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
850 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
851 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
852 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
854 /* The microMIPS registers with type h. */
855 static const unsigned int micromips_to_32_reg_h_map[] =
857 5, 5, 6, 4, 4, 4, 4, 4
860 /* The microMIPS registers with type i. */
861 static const unsigned int micromips_to_32_reg_i_map[] =
863 6, 7, 7, 21, 22, 5, 6, 7
866 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
868 /* The microMIPS registers with type m. */
869 static const unsigned int micromips_to_32_reg_m_map[] =
871 0, 17, 2, 3, 16, 18, 19, 20
874 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
876 /* The microMIPS registers with type q. */
877 static const unsigned int micromips_to_32_reg_q_map[] =
879 0, 17, 2, 3, 4, 5, 6, 7
882 /* microMIPS imm type B. */
883 static const int micromips_imm_b_map[] =
885 1, 4, 8, 12, 16, 20, 24, -1
888 /* microMIPS imm type C. */
889 static const int micromips_imm_c_map[] =
891 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
894 /* Classifies the kind of instructions we're interested in when
895 implementing -mfix-vr4120. */
896 enum fix_vr4120_class
904 NUM_FIX_VR4120_CLASSES
907 /* ...likewise -mfix-loongson2f-jump. */
908 static bfd_boolean mips_fix_loongson2f_jump;
910 /* ...likewise -mfix-loongson2f-nop. */
911 static bfd_boolean mips_fix_loongson2f_nop;
913 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
914 static bfd_boolean mips_fix_loongson2f;
916 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
917 there must be at least one other instruction between an instruction
918 of type X and an instruction of type Y. */
919 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
921 /* True if -mfix-vr4120 is in force. */
922 static int mips_fix_vr4120;
924 /* ...likewise -mfix-vr4130. */
925 static int mips_fix_vr4130;
927 /* ...likewise -mfix-24k. */
928 static int mips_fix_24k;
930 /* ...likewise -mfix-cn63xxp1 */
931 static bfd_boolean mips_fix_cn63xxp1;
933 /* We don't relax branches by default, since this causes us to expand
934 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
935 fail to compute the offset before expanding the macro to the most
936 efficient expansion. */
938 static int mips_relax_branch;
940 /* The expansion of many macros depends on the type of symbol that
941 they refer to. For example, when generating position-dependent code,
942 a macro that refers to a symbol may have two different expansions,
943 one which uses GP-relative addresses and one which uses absolute
944 addresses. When generating SVR4-style PIC, a macro may have
945 different expansions for local and global symbols.
947 We handle these situations by generating both sequences and putting
948 them in variant frags. In position-dependent code, the first sequence
949 will be the GP-relative one and the second sequence will be the
950 absolute one. In SVR4 PIC, the first sequence will be for global
951 symbols and the second will be for local symbols.
953 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
954 SECOND are the lengths of the two sequences in bytes. These fields
955 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
956 the subtype has the following flags:
959 Set if it has been decided that we should use the second
960 sequence instead of the first.
963 Set in the first variant frag if the macro's second implementation
964 is longer than its first. This refers to the macro as a whole,
965 not an individual relaxation.
968 Set in the first variant frag if the macro appeared in a .set nomacro
969 block and if one alternative requires a warning but the other does not.
972 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
975 RELAX_DELAY_SLOT_16BIT
976 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
979 RELAX_DELAY_SLOT_SIZE_FIRST
980 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
981 the macro is of the wrong size for the branch delay slot.
983 RELAX_DELAY_SLOT_SIZE_SECOND
984 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
985 the macro is of the wrong size for the branch delay slot.
987 The frag's "opcode" points to the first fixup for relaxable code.
989 Relaxable macros are generated using a sequence such as:
991 relax_start (SYMBOL);
992 ... generate first expansion ...
994 ... generate second expansion ...
997 The code and fixups for the unwanted alternative are discarded
998 by md_convert_frag. */
999 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1001 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1002 #define RELAX_SECOND(X) ((X) & 0xff)
1003 #define RELAX_USE_SECOND 0x10000
1004 #define RELAX_SECOND_LONGER 0x20000
1005 #define RELAX_NOMACRO 0x40000
1006 #define RELAX_DELAY_SLOT 0x80000
1007 #define RELAX_DELAY_SLOT_16BIT 0x100000
1008 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1009 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1011 /* Branch without likely bit. If label is out of range, we turn:
1013 beq reg1, reg2, label
1023 with the following opcode replacements:
1030 bltzal <-> bgezal (with jal label instead of j label)
1032 Even though keeping the delay slot instruction in the delay slot of
1033 the branch would be more efficient, it would be very tricky to do
1034 correctly, because we'd have to introduce a variable frag *after*
1035 the delay slot instruction, and expand that instead. Let's do it
1036 the easy way for now, even if the branch-not-taken case now costs
1037 one additional instruction. Out-of-range branches are not supposed
1038 to be common, anyway.
1040 Branch likely. If label is out of range, we turn:
1042 beql reg1, reg2, label
1043 delay slot (annulled if branch not taken)
1052 delay slot (executed only if branch taken)
1055 It would be possible to generate a shorter sequence by losing the
1056 likely bit, generating something like:
1061 delay slot (executed only if branch taken)
1073 bltzall -> bgezal (with jal label instead of j label)
1074 bgezall -> bltzal (ditto)
1077 but it's not clear that it would actually improve performance. */
1078 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1079 ((relax_substateT) \
1082 | ((toofar) ? 0x20 : 0) \
1083 | ((link) ? 0x40 : 0) \
1084 | ((likely) ? 0x80 : 0) \
1085 | ((uncond) ? 0x100 : 0)))
1086 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1087 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1088 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1089 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1090 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1091 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1093 /* For mips16 code, we use an entirely different form of relaxation.
1094 mips16 supports two versions of most instructions which take
1095 immediate values: a small one which takes some small value, and a
1096 larger one which takes a 16 bit value. Since branches also follow
1097 this pattern, relaxing these values is required.
1099 We can assemble both mips16 and normal MIPS code in a single
1100 object. Therefore, we need to support this type of relaxation at
1101 the same time that we support the relaxation described above. We
1102 use the high bit of the subtype field to distinguish these cases.
1104 The information we store for this type of relaxation is the
1105 argument code found in the opcode file for this relocation, whether
1106 the user explicitly requested a small or extended form, and whether
1107 the relocation is in a jump or jal delay slot. That tells us the
1108 size of the value, and how it should be stored. We also store
1109 whether the fragment is considered to be extended or not. We also
1110 store whether this is known to be a branch to a different section,
1111 whether we have tried to relax this frag yet, and whether we have
1112 ever extended a PC relative fragment because of a shift count. */
1113 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1116 | ((small) ? 0x100 : 0) \
1117 | ((ext) ? 0x200 : 0) \
1118 | ((dslot) ? 0x400 : 0) \
1119 | ((jal_dslot) ? 0x800 : 0))
1120 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1121 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1123 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1124 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1125 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1126 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1127 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1128 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1129 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1130 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1131 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1133 /* For microMIPS code, we use relaxation similar to one we use for
1134 MIPS16 code. Some instructions that take immediate values support
1135 two encodings: a small one which takes some small value, and a
1136 larger one which takes a 16 bit value. As some branches also follow
1137 this pattern, relaxing these values is required.
1139 We can assemble both microMIPS and normal MIPS code in a single
1140 object. Therefore, we need to support this type of relaxation at
1141 the same time that we support the relaxation described above. We
1142 use one of the high bits of the subtype field to distinguish these
1145 The information we store for this type of relaxation is the argument
1146 code found in the opcode file for this relocation, the register
1147 selected as the assembler temporary, whether the branch is
1148 unconditional, whether it is compact, whether it stores the link
1149 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1150 branches to a sequence of instructions is enabled, and whether the
1151 displacement of a branch is too large to fit as an immediate argument
1152 of a 16-bit and a 32-bit branch, respectively. */
1153 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1154 relax32, toofar16, toofar32) \
1157 | (((at) & 0x1f) << 8) \
1158 | ((uncond) ? 0x2000 : 0) \
1159 | ((compact) ? 0x4000 : 0) \
1160 | ((link) ? 0x8000 : 0) \
1161 | ((relax32) ? 0x10000 : 0) \
1162 | ((toofar16) ? 0x20000 : 0) \
1163 | ((toofar32) ? 0x40000 : 0))
1164 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1165 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1166 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1167 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1168 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1169 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1170 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1172 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1173 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1174 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1175 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1176 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1177 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1179 /* Sign-extend 16-bit value X. */
1180 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1182 /* Is the given value a sign-extended 32-bit value? */
1183 #define IS_SEXT_32BIT_NUM(x) \
1184 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1185 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1187 /* Is the given value a sign-extended 16-bit value? */
1188 #define IS_SEXT_16BIT_NUM(x) \
1189 (((x) &~ (offsetT) 0x7fff) == 0 \
1190 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1192 /* Is the given value a sign-extended 12-bit value? */
1193 #define IS_SEXT_12BIT_NUM(x) \
1194 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1196 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1197 #define IS_ZEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0xffffffff) == 0 \
1199 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1201 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1202 VALUE << SHIFT. VALUE is evaluated exactly once. */
1203 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1204 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1205 | (((VALUE) & (MASK)) << (SHIFT)))
1207 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1209 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1210 (((STRUCT) >> (SHIFT)) & (MASK))
1212 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1213 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1215 include/opcode/mips.h specifies operand fields using the macros
1216 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1217 with "MIPS16OP" instead of "OP". */
1218 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1221 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1222 OP_MASK_##FIELD, OP_SH_##FIELD); \
1224 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1225 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1227 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1228 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1229 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1231 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1232 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1234 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1235 : EXTRACT_BITS ((INSN).insn_opcode, \
1236 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1237 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1238 EXTRACT_BITS ((INSN).insn_opcode, \
1239 MIPS16OP_MASK_##FIELD, \
1240 MIPS16OP_SH_##FIELD)
1242 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1243 #define MIPS16_EXTEND (0xf000U << 16)
1245 /* Whether or not we are emitting a branch-likely macro. */
1246 static bfd_boolean emit_branch_likely_macro = FALSE;
1248 /* Global variables used when generating relaxable macros. See the
1249 comment above RELAX_ENCODE for more details about how relaxation
1252 /* 0 if we're not emitting a relaxable macro.
1253 1 if we're emitting the first of the two relaxation alternatives.
1254 2 if we're emitting the second alternative. */
1257 /* The first relaxable fixup in the current frag. (In other words,
1258 the first fixup that refers to relaxable code.) */
1261 /* sizes[0] says how many bytes of the first alternative are stored in
1262 the current frag. Likewise sizes[1] for the second alternative. */
1263 unsigned int sizes[2];
1265 /* The symbol on which the choice of sequence depends. */
1269 /* Global variables used to decide whether a macro needs a warning. */
1271 /* True if the macro is in a branch delay slot. */
1272 bfd_boolean delay_slot_p;
1274 /* Set to the length in bytes required if the macro is in a delay slot
1275 that requires a specific length of instruction, otherwise zero. */
1276 unsigned int delay_slot_length;
1278 /* For relaxable macros, sizes[0] is the length of the first alternative
1279 in bytes and sizes[1] is the length of the second alternative.
1280 For non-relaxable macros, both elements give the length of the
1282 unsigned int sizes[2];
1284 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1285 instruction of the first alternative in bytes and first_insn_sizes[1]
1286 is the length of the first instruction of the second alternative.
1287 For non-relaxable macros, both elements give the length of the first
1288 instruction in bytes.
1290 Set to zero if we haven't yet seen the first instruction. */
1291 unsigned int first_insn_sizes[2];
1293 /* For relaxable macros, insns[0] is the number of instructions for the
1294 first alternative and insns[1] is the number of instructions for the
1297 For non-relaxable macros, both elements give the number of
1298 instructions for the macro. */
1299 unsigned int insns[2];
1301 /* The first variant frag for this macro. */
1303 } mips_macro_warning;
1305 /* Prototypes for static functions. */
1307 #define internalError() \
1308 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1310 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1312 static void append_insn
1313 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1314 bfd_boolean expansionp);
1315 static void mips_no_prev_insn (void);
1316 static void macro_build (expressionS *, const char *, const char *, ...);
1317 static void mips16_macro_build
1318 (expressionS *, const char *, const char *, va_list *);
1319 static void load_register (int, expressionS *, int);
1320 static void macro_start (void);
1321 static void macro_end (void);
1322 static void macro (struct mips_cl_insn * ip);
1323 static void mips16_macro (struct mips_cl_insn * ip);
1324 static void mips_ip (char *str, struct mips_cl_insn * ip);
1325 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1326 static void mips16_immed
1327 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1328 unsigned int, unsigned long *);
1329 static size_t my_getSmallExpression
1330 (expressionS *, bfd_reloc_code_real_type *, char *);
1331 static void my_getExpression (expressionS *, char *);
1332 static void s_align (int);
1333 static void s_change_sec (int);
1334 static void s_change_section (int);
1335 static void s_cons (int);
1336 static void s_float_cons (int);
1337 static void s_mips_globl (int);
1338 static void s_option (int);
1339 static void s_mipsset (int);
1340 static void s_abicalls (int);
1341 static void s_cpload (int);
1342 static void s_cpsetup (int);
1343 static void s_cplocal (int);
1344 static void s_cprestore (int);
1345 static void s_cpreturn (int);
1346 static void s_dtprelword (int);
1347 static void s_dtpreldword (int);
1348 static void s_tprelword (int);
1349 static void s_tpreldword (int);
1350 static void s_gpvalue (int);
1351 static void s_gpword (int);
1352 static void s_gpdword (int);
1353 static void s_cpadd (int);
1354 static void s_insn (int);
1355 static void md_obj_begin (void);
1356 static void md_obj_end (void);
1357 static void s_mips_ent (int);
1358 static void s_mips_end (int);
1359 static void s_mips_frame (int);
1360 static void s_mips_mask (int reg_type);
1361 static void s_mips_stab (int);
1362 static void s_mips_weakext (int);
1363 static void s_mips_file (int);
1364 static void s_mips_loc (int);
1365 static bfd_boolean pic_need_relax (symbolS *, asection *);
1366 static int relaxed_branch_length (fragS *, asection *, int);
1367 static int validate_mips_insn (const struct mips_opcode *);
1368 static int validate_micromips_insn (const struct mips_opcode *);
1369 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1370 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1372 /* Table and functions used to map between CPU/ISA names, and
1373 ISA levels, and CPU numbers. */
1375 struct mips_cpu_info
1377 const char *name; /* CPU or ISA name. */
1378 int flags; /* ASEs available, or ISA flag. */
1379 int isa; /* ISA level. */
1380 int cpu; /* CPU number (default CPU if ISA). */
1383 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1384 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1385 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1386 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1387 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1388 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1389 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1390 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1392 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1393 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1394 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1398 The following pseudo-ops from the Kane and Heinrich MIPS book
1399 should be defined here, but are currently unsupported: .alias,
1400 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1402 The following pseudo-ops from the Kane and Heinrich MIPS book are
1403 specific to the type of debugging information being generated, and
1404 should be defined by the object format: .aent, .begin, .bend,
1405 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1408 The following pseudo-ops from the Kane and Heinrich MIPS book are
1409 not MIPS CPU specific, but are also not specific to the object file
1410 format. This file is probably the best place to define them, but
1411 they are not currently supported: .asm0, .endr, .lab, .struct. */
1413 static const pseudo_typeS mips_pseudo_table[] =
1415 /* MIPS specific pseudo-ops. */
1416 {"option", s_option, 0},
1417 {"set", s_mipsset, 0},
1418 {"rdata", s_change_sec, 'r'},
1419 {"sdata", s_change_sec, 's'},
1420 {"livereg", s_ignore, 0},
1421 {"abicalls", s_abicalls, 0},
1422 {"cpload", s_cpload, 0},
1423 {"cpsetup", s_cpsetup, 0},
1424 {"cplocal", s_cplocal, 0},
1425 {"cprestore", s_cprestore, 0},
1426 {"cpreturn", s_cpreturn, 0},
1427 {"dtprelword", s_dtprelword, 0},
1428 {"dtpreldword", s_dtpreldword, 0},
1429 {"tprelword", s_tprelword, 0},
1430 {"tpreldword", s_tpreldword, 0},
1431 {"gpvalue", s_gpvalue, 0},
1432 {"gpword", s_gpword, 0},
1433 {"gpdword", s_gpdword, 0},
1434 {"cpadd", s_cpadd, 0},
1435 {"insn", s_insn, 0},
1437 /* Relatively generic pseudo-ops that happen to be used on MIPS
1439 {"asciiz", stringer, 8 + 1},
1440 {"bss", s_change_sec, 'b'},
1442 {"half", s_cons, 1},
1443 {"dword", s_cons, 3},
1444 {"weakext", s_mips_weakext, 0},
1445 {"origin", s_org, 0},
1446 {"repeat", s_rept, 0},
1448 /* For MIPS this is non-standard, but we define it for consistency. */
1449 {"sbss", s_change_sec, 'B'},
1451 /* These pseudo-ops are defined in read.c, but must be overridden
1452 here for one reason or another. */
1453 {"align", s_align, 0},
1454 {"byte", s_cons, 0},
1455 {"data", s_change_sec, 'd'},
1456 {"double", s_float_cons, 'd'},
1457 {"float", s_float_cons, 'f'},
1458 {"globl", s_mips_globl, 0},
1459 {"global", s_mips_globl, 0},
1460 {"hword", s_cons, 1},
1462 {"long", s_cons, 2},
1463 {"octa", s_cons, 4},
1464 {"quad", s_cons, 3},
1465 {"section", s_change_section, 0},
1466 {"short", s_cons, 1},
1467 {"single", s_float_cons, 'f'},
1468 {"stabn", s_mips_stab, 'n'},
1469 {"text", s_change_sec, 't'},
1470 {"word", s_cons, 2},
1472 { "extern", ecoff_directive_extern, 0},
1477 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1479 /* These pseudo-ops should be defined by the object file format.
1480 However, a.out doesn't support them, so we have versions here. */
1481 {"aent", s_mips_ent, 1},
1482 {"bgnb", s_ignore, 0},
1483 {"end", s_mips_end, 0},
1484 {"endb", s_ignore, 0},
1485 {"ent", s_mips_ent, 0},
1486 {"file", s_mips_file, 0},
1487 {"fmask", s_mips_mask, 'F'},
1488 {"frame", s_mips_frame, 0},
1489 {"loc", s_mips_loc, 0},
1490 {"mask", s_mips_mask, 'R'},
1491 {"verstamp", s_ignore, 0},
1495 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1496 purpose of the `.dc.a' internal pseudo-op. */
1499 mips_address_bytes (void)
1501 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1504 extern void pop_insert (const pseudo_typeS *);
1507 mips_pop_insert (void)
1509 pop_insert (mips_pseudo_table);
1510 if (! ECOFF_DEBUGGING)
1511 pop_insert (mips_nonecoff_pseudo_table);
1514 /* Symbols labelling the current insn. */
1516 struct insn_label_list
1518 struct insn_label_list *next;
1522 static struct insn_label_list *free_insn_labels;
1523 #define label_list tc_segment_info_data.labels
1525 static void mips_clear_insn_labels (void);
1526 static void mips_mark_labels (void);
1527 static void mips_compressed_mark_labels (void);
1530 mips_clear_insn_labels (void)
1532 register struct insn_label_list **pl;
1533 segment_info_type *si;
1537 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1540 si = seg_info (now_seg);
1541 *pl = si->label_list;
1542 si->label_list = NULL;
1546 /* Mark instruction labels in MIPS16/microMIPS mode. */
1549 mips_mark_labels (void)
1551 if (HAVE_CODE_COMPRESSION)
1552 mips_compressed_mark_labels ();
1555 static char *expr_end;
1557 /* Expressions which appear in instructions. These are set by
1560 static expressionS imm_expr;
1561 static expressionS imm2_expr;
1562 static expressionS offset_expr;
1564 /* Relocs associated with imm_expr and offset_expr. */
1566 static bfd_reloc_code_real_type imm_reloc[3]
1567 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1568 static bfd_reloc_code_real_type offset_reloc[3]
1569 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1571 /* This is set to the resulting size of the instruction to be produced
1572 by mips16_ip if an explicit extension is used or by mips_ip if an
1573 explicit size is supplied. */
1575 static unsigned int forced_insn_length;
1578 /* The pdr segment for per procedure frame/regmask info. Not used for
1581 static segT pdr_seg;
1584 /* The default target format to use. */
1586 #if defined (TE_FreeBSD)
1587 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1588 #elif defined (TE_TMIPS)
1589 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1591 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1595 mips_target_format (void)
1597 switch (OUTPUT_FLAVOR)
1599 case bfd_target_ecoff_flavour:
1600 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1601 case bfd_target_coff_flavour:
1603 case bfd_target_elf_flavour:
1605 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1606 return (target_big_endian
1607 ? "elf32-bigmips-vxworks"
1608 : "elf32-littlemips-vxworks");
1610 return (target_big_endian
1611 ? (HAVE_64BIT_OBJECTS
1612 ? ELF_TARGET ("elf64-", "big")
1614 ? ELF_TARGET ("elf32-n", "big")
1615 : ELF_TARGET ("elf32-", "big")))
1616 : (HAVE_64BIT_OBJECTS
1617 ? ELF_TARGET ("elf64-", "little")
1619 ? ELF_TARGET ("elf32-n", "little")
1620 : ELF_TARGET ("elf32-", "little"))));
1627 /* Return the length of a microMIPS instruction in bytes. If bits of
1628 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1629 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1630 major opcode) will require further modifications to the opcode
1633 static inline unsigned int
1634 micromips_insn_length (const struct mips_opcode *mo)
1636 return (mo->mask >> 16) == 0 ? 2 : 4;
1639 /* Return the length of MIPS16 instruction OPCODE. */
1641 static inline unsigned int
1642 mips16_opcode_length (unsigned long opcode)
1644 return (opcode >> 16) == 0 ? 2 : 4;
1647 /* Return the length of instruction INSN. */
1649 static inline unsigned int
1650 insn_length (const struct mips_cl_insn *insn)
1652 if (mips_opts.micromips)
1653 return micromips_insn_length (insn->insn_mo);
1654 else if (mips_opts.mips16)
1655 return mips16_opcode_length (insn->insn_opcode);
1660 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1663 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1668 insn->insn_opcode = mo->match;
1671 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1672 insn->fixp[i] = NULL;
1673 insn->fixed_p = (mips_opts.noreorder > 0);
1674 insn->noreorder_p = (mips_opts.noreorder > 0);
1675 insn->mips16_absolute_jump_p = 0;
1676 insn->complete_p = 0;
1679 /* Record the current MIPS16/microMIPS mode in now_seg. */
1682 mips_record_compressed_mode (void)
1684 segment_info_type *si;
1686 si = seg_info (now_seg);
1687 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1688 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1689 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1690 si->tc_segment_info_data.micromips = mips_opts.micromips;
1693 /* Read a standard MIPS instruction from BUF. */
1695 static unsigned long
1696 read_insn (char *buf)
1698 if (target_big_endian)
1699 return bfd_getb32 ((bfd_byte *) buf);
1701 return bfd_getl32 ((bfd_byte *) buf);
1704 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1708 write_insn (char *buf, unsigned int insn)
1710 md_number_to_chars (buf, insn, 4);
1714 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1715 has length LENGTH. */
1717 static unsigned long
1718 read_compressed_insn (char *buf, unsigned int length)
1724 for (i = 0; i < length; i += 2)
1727 if (target_big_endian)
1728 insn |= bfd_getb16 ((char *) buf);
1730 insn |= bfd_getl16 ((char *) buf);
1736 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1737 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1740 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1744 for (i = 0; i < length; i += 2)
1745 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1746 return buf + length;
1749 /* Install INSN at the location specified by its "frag" and "where" fields. */
1752 install_insn (const struct mips_cl_insn *insn)
1754 char *f = insn->frag->fr_literal + insn->where;
1755 if (HAVE_CODE_COMPRESSION)
1756 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1758 write_insn (f, insn->insn_opcode);
1759 mips_record_compressed_mode ();
1762 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1763 and install the opcode in the new location. */
1766 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1771 insn->where = where;
1772 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1773 if (insn->fixp[i] != NULL)
1775 insn->fixp[i]->fx_frag = frag;
1776 insn->fixp[i]->fx_where = where;
1778 install_insn (insn);
1781 /* Add INSN to the end of the output. */
1784 add_fixed_insn (struct mips_cl_insn *insn)
1786 char *f = frag_more (insn_length (insn));
1787 move_insn (insn, frag_now, f - frag_now->fr_literal);
1790 /* Start a variant frag and move INSN to the start of the variant part,
1791 marking it as fixed. The other arguments are as for frag_var. */
1794 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1795 relax_substateT subtype, symbolS *symbol, offsetT offset)
1797 frag_grow (max_chars);
1798 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1800 frag_var (rs_machine_dependent, max_chars, var,
1801 subtype, symbol, offset, NULL);
1804 /* Insert N copies of INSN into the history buffer, starting at
1805 position FIRST. Neither FIRST nor N need to be clipped. */
1808 insert_into_history (unsigned int first, unsigned int n,
1809 const struct mips_cl_insn *insn)
1811 if (mips_relax.sequence != 2)
1815 for (i = ARRAY_SIZE (history); i-- > first;)
1817 history[i] = history[i - n];
1823 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1824 the idea is to make it obvious at a glance that each errata is
1828 init_vr4120_conflicts (void)
1830 #define CONFLICT(FIRST, SECOND) \
1831 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1833 /* Errata 21 - [D]DIV[U] after [D]MACC */
1834 CONFLICT (MACC, DIV);
1835 CONFLICT (DMACC, DIV);
1837 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1838 CONFLICT (DMULT, DMULT);
1839 CONFLICT (DMULT, DMACC);
1840 CONFLICT (DMACC, DMULT);
1841 CONFLICT (DMACC, DMACC);
1843 /* Errata 24 - MT{LO,HI} after [D]MACC */
1844 CONFLICT (MACC, MTHILO);
1845 CONFLICT (DMACC, MTHILO);
1847 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1848 instruction is executed immediately after a MACC or DMACC
1849 instruction, the result of [either instruction] is incorrect." */
1850 CONFLICT (MACC, MULT);
1851 CONFLICT (MACC, DMULT);
1852 CONFLICT (DMACC, MULT);
1853 CONFLICT (DMACC, DMULT);
1855 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1856 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1857 DDIV or DDIVU instruction, the result of the MACC or
1858 DMACC instruction is incorrect.". */
1859 CONFLICT (DMULT, MACC);
1860 CONFLICT (DMULT, DMACC);
1861 CONFLICT (DIV, MACC);
1862 CONFLICT (DIV, DMACC);
1872 #define RTYPE_MASK 0x1ff00
1873 #define RTYPE_NUM 0x00100
1874 #define RTYPE_FPU 0x00200
1875 #define RTYPE_FCC 0x00400
1876 #define RTYPE_VEC 0x00800
1877 #define RTYPE_GP 0x01000
1878 #define RTYPE_CP0 0x02000
1879 #define RTYPE_PC 0x04000
1880 #define RTYPE_ACC 0x08000
1881 #define RTYPE_CCC 0x10000
1882 #define RNUM_MASK 0x000ff
1883 #define RWARN 0x80000
1885 #define GENERIC_REGISTER_NUMBERS \
1886 {"$0", RTYPE_NUM | 0}, \
1887 {"$1", RTYPE_NUM | 1}, \
1888 {"$2", RTYPE_NUM | 2}, \
1889 {"$3", RTYPE_NUM | 3}, \
1890 {"$4", RTYPE_NUM | 4}, \
1891 {"$5", RTYPE_NUM | 5}, \
1892 {"$6", RTYPE_NUM | 6}, \
1893 {"$7", RTYPE_NUM | 7}, \
1894 {"$8", RTYPE_NUM | 8}, \
1895 {"$9", RTYPE_NUM | 9}, \
1896 {"$10", RTYPE_NUM | 10}, \
1897 {"$11", RTYPE_NUM | 11}, \
1898 {"$12", RTYPE_NUM | 12}, \
1899 {"$13", RTYPE_NUM | 13}, \
1900 {"$14", RTYPE_NUM | 14}, \
1901 {"$15", RTYPE_NUM | 15}, \
1902 {"$16", RTYPE_NUM | 16}, \
1903 {"$17", RTYPE_NUM | 17}, \
1904 {"$18", RTYPE_NUM | 18}, \
1905 {"$19", RTYPE_NUM | 19}, \
1906 {"$20", RTYPE_NUM | 20}, \
1907 {"$21", RTYPE_NUM | 21}, \
1908 {"$22", RTYPE_NUM | 22}, \
1909 {"$23", RTYPE_NUM | 23}, \
1910 {"$24", RTYPE_NUM | 24}, \
1911 {"$25", RTYPE_NUM | 25}, \
1912 {"$26", RTYPE_NUM | 26}, \
1913 {"$27", RTYPE_NUM | 27}, \
1914 {"$28", RTYPE_NUM | 28}, \
1915 {"$29", RTYPE_NUM | 29}, \
1916 {"$30", RTYPE_NUM | 30}, \
1917 {"$31", RTYPE_NUM | 31}
1919 #define FPU_REGISTER_NAMES \
1920 {"$f0", RTYPE_FPU | 0}, \
1921 {"$f1", RTYPE_FPU | 1}, \
1922 {"$f2", RTYPE_FPU | 2}, \
1923 {"$f3", RTYPE_FPU | 3}, \
1924 {"$f4", RTYPE_FPU | 4}, \
1925 {"$f5", RTYPE_FPU | 5}, \
1926 {"$f6", RTYPE_FPU | 6}, \
1927 {"$f7", RTYPE_FPU | 7}, \
1928 {"$f8", RTYPE_FPU | 8}, \
1929 {"$f9", RTYPE_FPU | 9}, \
1930 {"$f10", RTYPE_FPU | 10}, \
1931 {"$f11", RTYPE_FPU | 11}, \
1932 {"$f12", RTYPE_FPU | 12}, \
1933 {"$f13", RTYPE_FPU | 13}, \
1934 {"$f14", RTYPE_FPU | 14}, \
1935 {"$f15", RTYPE_FPU | 15}, \
1936 {"$f16", RTYPE_FPU | 16}, \
1937 {"$f17", RTYPE_FPU | 17}, \
1938 {"$f18", RTYPE_FPU | 18}, \
1939 {"$f19", RTYPE_FPU | 19}, \
1940 {"$f20", RTYPE_FPU | 20}, \
1941 {"$f21", RTYPE_FPU | 21}, \
1942 {"$f22", RTYPE_FPU | 22}, \
1943 {"$f23", RTYPE_FPU | 23}, \
1944 {"$f24", RTYPE_FPU | 24}, \
1945 {"$f25", RTYPE_FPU | 25}, \
1946 {"$f26", RTYPE_FPU | 26}, \
1947 {"$f27", RTYPE_FPU | 27}, \
1948 {"$f28", RTYPE_FPU | 28}, \
1949 {"$f29", RTYPE_FPU | 29}, \
1950 {"$f30", RTYPE_FPU | 30}, \
1951 {"$f31", RTYPE_FPU | 31}
1953 #define FPU_CONDITION_CODE_NAMES \
1954 {"$fcc0", RTYPE_FCC | 0}, \
1955 {"$fcc1", RTYPE_FCC | 1}, \
1956 {"$fcc2", RTYPE_FCC | 2}, \
1957 {"$fcc3", RTYPE_FCC | 3}, \
1958 {"$fcc4", RTYPE_FCC | 4}, \
1959 {"$fcc5", RTYPE_FCC | 5}, \
1960 {"$fcc6", RTYPE_FCC | 6}, \
1961 {"$fcc7", RTYPE_FCC | 7}
1963 #define COPROC_CONDITION_CODE_NAMES \
1964 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1965 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1966 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1967 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1968 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1969 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1970 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1971 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1973 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1974 {"$a4", RTYPE_GP | 8}, \
1975 {"$a5", RTYPE_GP | 9}, \
1976 {"$a6", RTYPE_GP | 10}, \
1977 {"$a7", RTYPE_GP | 11}, \
1978 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1979 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1980 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1981 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1982 {"$t0", RTYPE_GP | 12}, \
1983 {"$t1", RTYPE_GP | 13}, \
1984 {"$t2", RTYPE_GP | 14}, \
1985 {"$t3", RTYPE_GP | 15}
1987 #define O32_SYMBOLIC_REGISTER_NAMES \
1988 {"$t0", RTYPE_GP | 8}, \
1989 {"$t1", RTYPE_GP | 9}, \
1990 {"$t2", RTYPE_GP | 10}, \
1991 {"$t3", RTYPE_GP | 11}, \
1992 {"$t4", RTYPE_GP | 12}, \
1993 {"$t5", RTYPE_GP | 13}, \
1994 {"$t6", RTYPE_GP | 14}, \
1995 {"$t7", RTYPE_GP | 15}, \
1996 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1997 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1998 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1999 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2001 /* Remaining symbolic register names */
2002 #define SYMBOLIC_REGISTER_NAMES \
2003 {"$zero", RTYPE_GP | 0}, \
2004 {"$at", RTYPE_GP | 1}, \
2005 {"$AT", RTYPE_GP | 1}, \
2006 {"$v0", RTYPE_GP | 2}, \
2007 {"$v1", RTYPE_GP | 3}, \
2008 {"$a0", RTYPE_GP | 4}, \
2009 {"$a1", RTYPE_GP | 5}, \
2010 {"$a2", RTYPE_GP | 6}, \
2011 {"$a3", RTYPE_GP | 7}, \
2012 {"$s0", RTYPE_GP | 16}, \
2013 {"$s1", RTYPE_GP | 17}, \
2014 {"$s2", RTYPE_GP | 18}, \
2015 {"$s3", RTYPE_GP | 19}, \
2016 {"$s4", RTYPE_GP | 20}, \
2017 {"$s5", RTYPE_GP | 21}, \
2018 {"$s6", RTYPE_GP | 22}, \
2019 {"$s7", RTYPE_GP | 23}, \
2020 {"$t8", RTYPE_GP | 24}, \
2021 {"$t9", RTYPE_GP | 25}, \
2022 {"$k0", RTYPE_GP | 26}, \
2023 {"$kt0", RTYPE_GP | 26}, \
2024 {"$k1", RTYPE_GP | 27}, \
2025 {"$kt1", RTYPE_GP | 27}, \
2026 {"$gp", RTYPE_GP | 28}, \
2027 {"$sp", RTYPE_GP | 29}, \
2028 {"$s8", RTYPE_GP | 30}, \
2029 {"$fp", RTYPE_GP | 30}, \
2030 {"$ra", RTYPE_GP | 31}
2032 #define MIPS16_SPECIAL_REGISTER_NAMES \
2033 {"$pc", RTYPE_PC | 0}
2035 #define MDMX_VECTOR_REGISTER_NAMES \
2036 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2037 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2038 {"$v2", RTYPE_VEC | 2}, \
2039 {"$v3", RTYPE_VEC | 3}, \
2040 {"$v4", RTYPE_VEC | 4}, \
2041 {"$v5", RTYPE_VEC | 5}, \
2042 {"$v6", RTYPE_VEC | 6}, \
2043 {"$v7", RTYPE_VEC | 7}, \
2044 {"$v8", RTYPE_VEC | 8}, \
2045 {"$v9", RTYPE_VEC | 9}, \
2046 {"$v10", RTYPE_VEC | 10}, \
2047 {"$v11", RTYPE_VEC | 11}, \
2048 {"$v12", RTYPE_VEC | 12}, \
2049 {"$v13", RTYPE_VEC | 13}, \
2050 {"$v14", RTYPE_VEC | 14}, \
2051 {"$v15", RTYPE_VEC | 15}, \
2052 {"$v16", RTYPE_VEC | 16}, \
2053 {"$v17", RTYPE_VEC | 17}, \
2054 {"$v18", RTYPE_VEC | 18}, \
2055 {"$v19", RTYPE_VEC | 19}, \
2056 {"$v20", RTYPE_VEC | 20}, \
2057 {"$v21", RTYPE_VEC | 21}, \
2058 {"$v22", RTYPE_VEC | 22}, \
2059 {"$v23", RTYPE_VEC | 23}, \
2060 {"$v24", RTYPE_VEC | 24}, \
2061 {"$v25", RTYPE_VEC | 25}, \
2062 {"$v26", RTYPE_VEC | 26}, \
2063 {"$v27", RTYPE_VEC | 27}, \
2064 {"$v28", RTYPE_VEC | 28}, \
2065 {"$v29", RTYPE_VEC | 29}, \
2066 {"$v30", RTYPE_VEC | 30}, \
2067 {"$v31", RTYPE_VEC | 31}
2069 #define MIPS_DSP_ACCUMULATOR_NAMES \
2070 {"$ac0", RTYPE_ACC | 0}, \
2071 {"$ac1", RTYPE_ACC | 1}, \
2072 {"$ac2", RTYPE_ACC | 2}, \
2073 {"$ac3", RTYPE_ACC | 3}
2075 static const struct regname reg_names[] = {
2076 GENERIC_REGISTER_NUMBERS,
2078 FPU_CONDITION_CODE_NAMES,
2079 COPROC_CONDITION_CODE_NAMES,
2081 /* The $txx registers depends on the abi,
2082 these will be added later into the symbol table from
2083 one of the tables below once mips_abi is set after
2084 parsing of arguments from the command line. */
2085 SYMBOLIC_REGISTER_NAMES,
2087 MIPS16_SPECIAL_REGISTER_NAMES,
2088 MDMX_VECTOR_REGISTER_NAMES,
2089 MIPS_DSP_ACCUMULATOR_NAMES,
2093 static const struct regname reg_names_o32[] = {
2094 O32_SYMBOLIC_REGISTER_NAMES,
2098 static const struct regname reg_names_n32n64[] = {
2099 N32N64_SYMBOLIC_REGISTER_NAMES,
2103 /* Check if S points at a valid register specifier according to TYPES.
2104 If so, then return 1, advance S to consume the specifier and store
2105 the register's number in REGNOP, otherwise return 0. */
2108 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2115 /* Find end of name. */
2117 if (is_name_beginner (*e))
2119 while (is_part_of_name (*e))
2122 /* Terminate name. */
2126 /* Look for a register symbol. */
2127 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2129 int r = S_GET_VALUE (symbolP);
2131 reg = r & RNUM_MASK;
2132 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2133 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2134 reg = (r & RNUM_MASK) - 2;
2136 /* Else see if this is a register defined in an itbl entry. */
2137 else if ((types & RTYPE_GP) && itbl_have_entries)
2144 if (itbl_get_reg_val (n, &r))
2145 reg = r & RNUM_MASK;
2148 /* Advance to next token if a register was recognised. */
2151 else if (types & RWARN)
2152 as_warn (_("Unrecognized register name `%s'"), *s);
2160 /* Check if S points at a valid register list according to TYPES.
2161 If so, then return 1, advance S to consume the list and store
2162 the registers present on the list as a bitmask of ones in REGLISTP,
2163 otherwise return 0. A valid list comprises a comma-separated
2164 enumeration of valid single registers and/or dash-separated
2165 contiguous register ranges as determined by their numbers.
2167 As a special exception if one of s0-s7 registers is specified as
2168 the range's lower delimiter and s8 (fp) is its upper one, then no
2169 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2170 are selected; they have to be listed separately if needed. */
2173 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2175 unsigned int reglist = 0;
2176 unsigned int lastregno;
2177 bfd_boolean ok = TRUE;
2178 unsigned int regmask;
2179 char *s_endlist = *s;
2183 while (reg_lookup (s, types, ®no))
2189 ok = reg_lookup (s, types, &lastregno);
2190 if (ok && lastregno < regno)
2196 if (lastregno == FP && regno >= S0 && regno <= S7)
2201 regmask = 1 << lastregno;
2202 regmask = (regmask << 1) - 1;
2203 regmask ^= (1 << regno) - 1;
2217 *reglistp = reglist;
2218 return ok && reglist != 0;
2221 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2222 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2225 is_opcode_valid (const struct mips_opcode *mo)
2227 int isa = mips_opts.isa;
2230 if (mips_opts.ase_mdmx)
2232 if (mips_opts.ase_dsp)
2234 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2236 if (mips_opts.ase_dspr2)
2238 if (mips_opts.ase_mt)
2240 if (mips_opts.ase_mips3d)
2242 if (mips_opts.ase_smartmips)
2243 isa |= INSN_SMARTMIPS;
2244 if (mips_opts.ase_mcu)
2247 if (!opcode_is_member (mo, isa, mips_opts.arch))
2250 /* Check whether the instruction or macro requires single-precision or
2251 double-precision floating-point support. Note that this information is
2252 stored differently in the opcode table for insns and macros. */
2253 if (mo->pinfo == INSN_MACRO)
2255 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2256 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2260 fp_s = mo->pinfo & FP_S;
2261 fp_d = mo->pinfo & FP_D;
2264 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2267 if (fp_s && mips_opts.soft_float)
2273 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2274 selected ISA and architecture. */
2277 is_opcode_valid_16 (const struct mips_opcode *mo)
2279 return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
2282 /* Return TRUE if the size of the microMIPS opcode MO matches one
2283 explicitly requested. Always TRUE in the standard MIPS mode. */
2286 is_size_valid (const struct mips_opcode *mo)
2288 if (!mips_opts.micromips)
2291 if (!forced_insn_length)
2293 if (mo->pinfo == INSN_MACRO)
2295 return forced_insn_length == micromips_insn_length (mo);
2298 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2299 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2302 is_delay_slot_valid (const struct mips_opcode *mo)
2304 if (!mips_opts.micromips)
2307 if (mo->pinfo == INSN_MACRO)
2309 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2310 && micromips_insn_length (mo) != 4)
2312 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2313 && micromips_insn_length (mo) != 2)
2319 /* This function is called once, at assembler startup time. It should set up
2320 all the tables, etc. that the MD part of the assembler will need. */
2325 const char *retval = NULL;
2329 if (mips_pic != NO_PIC)
2331 if (g_switch_seen && g_switch_value != 0)
2332 as_bad (_("-G may not be used in position-independent code"));
2336 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2337 as_warn (_("Could not set architecture and machine"));
2339 op_hash = hash_new ();
2341 for (i = 0; i < NUMOPCODES;)
2343 const char *name = mips_opcodes[i].name;
2345 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2348 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2349 mips_opcodes[i].name, retval);
2350 /* Probably a memory allocation problem? Give up now. */
2351 as_fatal (_("Broken assembler. No assembly attempted."));
2355 if (mips_opcodes[i].pinfo != INSN_MACRO)
2357 if (!validate_mips_insn (&mips_opcodes[i]))
2359 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2361 create_insn (&nop_insn, mips_opcodes + i);
2362 if (mips_fix_loongson2f_nop)
2363 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2364 nop_insn.fixed_p = 1;
2369 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2372 mips16_op_hash = hash_new ();
2375 while (i < bfd_mips16_num_opcodes)
2377 const char *name = mips16_opcodes[i].name;
2379 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2381 as_fatal (_("internal: can't hash `%s': %s"),
2382 mips16_opcodes[i].name, retval);
2385 if (mips16_opcodes[i].pinfo != INSN_MACRO
2386 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2387 != mips16_opcodes[i].match))
2389 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2390 mips16_opcodes[i].name, mips16_opcodes[i].args);
2393 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2395 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2396 mips16_nop_insn.fixed_p = 1;
2400 while (i < bfd_mips16_num_opcodes
2401 && strcmp (mips16_opcodes[i].name, name) == 0);
2404 micromips_op_hash = hash_new ();
2407 while (i < bfd_micromips_num_opcodes)
2409 const char *name = micromips_opcodes[i].name;
2411 retval = hash_insert (micromips_op_hash, name,
2412 (void *) µmips_opcodes[i]);
2414 as_fatal (_("internal: can't hash `%s': %s"),
2415 micromips_opcodes[i].name, retval);
2417 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2419 struct mips_cl_insn *micromips_nop_insn;
2421 if (!validate_micromips_insn (µmips_opcodes[i]))
2424 if (micromips_insn_length (micromips_opcodes + i) == 2)
2425 micromips_nop_insn = µmips_nop16_insn;
2426 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2427 micromips_nop_insn = µmips_nop32_insn;
2431 if (micromips_nop_insn->insn_mo == NULL
2432 && strcmp (name, "nop") == 0)
2434 create_insn (micromips_nop_insn, micromips_opcodes + i);
2435 micromips_nop_insn->fixed_p = 1;
2438 while (++i < bfd_micromips_num_opcodes
2439 && strcmp (micromips_opcodes[i].name, name) == 0);
2443 as_fatal (_("Broken assembler. No assembly attempted."));
2445 /* We add all the general register names to the symbol table. This
2446 helps us detect invalid uses of them. */
2447 for (i = 0; reg_names[i].name; i++)
2448 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2449 reg_names[i].num, /* & RNUM_MASK, */
2450 &zero_address_frag));
2452 for (i = 0; reg_names_n32n64[i].name; i++)
2453 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2454 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2455 &zero_address_frag));
2457 for (i = 0; reg_names_o32[i].name; i++)
2458 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2459 reg_names_o32[i].num, /* & RNUM_MASK, */
2460 &zero_address_frag));
2462 mips_no_prev_insn ();
2465 mips_cprmask[0] = 0;
2466 mips_cprmask[1] = 0;
2467 mips_cprmask[2] = 0;
2468 mips_cprmask[3] = 0;
2470 /* set the default alignment for the text section (2**2) */
2471 record_alignment (text_section, 2);
2473 bfd_set_gp_size (stdoutput, g_switch_value);
2478 /* On a native system other than VxWorks, sections must be aligned
2479 to 16 byte boundaries. When configured for an embedded ELF
2480 target, we don't bother. */
2481 if (strncmp (TARGET_OS, "elf", 3) != 0
2482 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2484 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2485 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2486 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2489 /* Create a .reginfo section for register masks and a .mdebug
2490 section for debugging information. */
2498 subseg = now_subseg;
2500 /* The ABI says this section should be loaded so that the
2501 running program can access it. However, we don't load it
2502 if we are configured for an embedded target */
2503 flags = SEC_READONLY | SEC_DATA;
2504 if (strncmp (TARGET_OS, "elf", 3) != 0)
2505 flags |= SEC_ALLOC | SEC_LOAD;
2507 if (mips_abi != N64_ABI)
2509 sec = subseg_new (".reginfo", (subsegT) 0);
2511 bfd_set_section_flags (stdoutput, sec, flags);
2512 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2514 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2518 /* The 64-bit ABI uses a .MIPS.options section rather than
2519 .reginfo section. */
2520 sec = subseg_new (".MIPS.options", (subsegT) 0);
2521 bfd_set_section_flags (stdoutput, sec, flags);
2522 bfd_set_section_alignment (stdoutput, sec, 3);
2524 /* Set up the option header. */
2526 Elf_Internal_Options opthdr;
2529 opthdr.kind = ODK_REGINFO;
2530 opthdr.size = (sizeof (Elf_External_Options)
2531 + sizeof (Elf64_External_RegInfo));
2534 f = frag_more (sizeof (Elf_External_Options));
2535 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2536 (Elf_External_Options *) f);
2538 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2542 if (ECOFF_DEBUGGING)
2544 sec = subseg_new (".mdebug", (subsegT) 0);
2545 (void) bfd_set_section_flags (stdoutput, sec,
2546 SEC_HAS_CONTENTS | SEC_READONLY);
2547 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2549 else if (mips_flag_pdr)
2551 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2552 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2553 SEC_READONLY | SEC_RELOC
2555 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2558 subseg_set (seg, subseg);
2561 #endif /* OBJ_ELF */
2563 if (! ECOFF_DEBUGGING)
2566 if (mips_fix_vr4120)
2567 init_vr4120_conflicts ();
2573 mips_emit_delays ();
2574 if (! ECOFF_DEBUGGING)
2579 md_assemble (char *str)
2581 struct mips_cl_insn insn;
2582 bfd_reloc_code_real_type unused_reloc[3]
2583 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2585 imm_expr.X_op = O_absent;
2586 imm2_expr.X_op = O_absent;
2587 offset_expr.X_op = O_absent;
2588 imm_reloc[0] = BFD_RELOC_UNUSED;
2589 imm_reloc[1] = BFD_RELOC_UNUSED;
2590 imm_reloc[2] = BFD_RELOC_UNUSED;
2591 offset_reloc[0] = BFD_RELOC_UNUSED;
2592 offset_reloc[1] = BFD_RELOC_UNUSED;
2593 offset_reloc[2] = BFD_RELOC_UNUSED;
2595 if (mips_opts.mips16)
2596 mips16_ip (str, &insn);
2599 mips_ip (str, &insn);
2600 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2601 str, insn.insn_opcode));
2606 as_bad ("%s `%s'", insn_error, str);
2610 if (insn.insn_mo->pinfo == INSN_MACRO)
2613 if (mips_opts.mips16)
2614 mips16_macro (&insn);
2621 if (imm_expr.X_op != O_absent)
2622 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2623 else if (offset_expr.X_op != O_absent)
2624 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2626 append_insn (&insn, NULL, unused_reloc, FALSE);
2630 /* Convenience functions for abstracting away the differences between
2631 MIPS16 and non-MIPS16 relocations. */
2633 static inline bfd_boolean
2634 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2638 case BFD_RELOC_MIPS16_JMP:
2639 case BFD_RELOC_MIPS16_GPREL:
2640 case BFD_RELOC_MIPS16_GOT16:
2641 case BFD_RELOC_MIPS16_CALL16:
2642 case BFD_RELOC_MIPS16_HI16_S:
2643 case BFD_RELOC_MIPS16_HI16:
2644 case BFD_RELOC_MIPS16_LO16:
2652 static inline bfd_boolean
2653 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2657 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2658 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2659 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2660 case BFD_RELOC_MICROMIPS_GPREL16:
2661 case BFD_RELOC_MICROMIPS_JMP:
2662 case BFD_RELOC_MICROMIPS_HI16:
2663 case BFD_RELOC_MICROMIPS_HI16_S:
2664 case BFD_RELOC_MICROMIPS_LO16:
2665 case BFD_RELOC_MICROMIPS_LITERAL:
2666 case BFD_RELOC_MICROMIPS_GOT16:
2667 case BFD_RELOC_MICROMIPS_CALL16:
2668 case BFD_RELOC_MICROMIPS_GOT_HI16:
2669 case BFD_RELOC_MICROMIPS_GOT_LO16:
2670 case BFD_RELOC_MICROMIPS_CALL_HI16:
2671 case BFD_RELOC_MICROMIPS_CALL_LO16:
2672 case BFD_RELOC_MICROMIPS_SUB:
2673 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2674 case BFD_RELOC_MICROMIPS_GOT_OFST:
2675 case BFD_RELOC_MICROMIPS_GOT_DISP:
2676 case BFD_RELOC_MICROMIPS_HIGHEST:
2677 case BFD_RELOC_MICROMIPS_HIGHER:
2678 case BFD_RELOC_MICROMIPS_SCN_DISP:
2679 case BFD_RELOC_MICROMIPS_JALR:
2687 static inline bfd_boolean
2688 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2690 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2693 static inline bfd_boolean
2694 got16_reloc_p (bfd_reloc_code_real_type reloc)
2696 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2697 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2700 static inline bfd_boolean
2701 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2703 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2704 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2707 static inline bfd_boolean
2708 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2710 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2711 || reloc == BFD_RELOC_MICROMIPS_LO16);
2714 static inline bfd_boolean
2715 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2717 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2720 /* Return true if the given relocation might need a matching %lo().
2721 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2722 need a matching %lo() when applied to local symbols. */
2724 static inline bfd_boolean
2725 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2727 return (HAVE_IN_PLACE_ADDENDS
2728 && (hi16_reloc_p (reloc)
2729 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2730 all GOT16 relocations evaluate to "G". */
2731 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2734 /* Return the type of %lo() reloc needed by RELOC, given that
2735 reloc_needs_lo_p. */
2737 static inline bfd_reloc_code_real_type
2738 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2740 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2741 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2745 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2748 static inline bfd_boolean
2749 fixup_has_matching_lo_p (fixS *fixp)
2751 return (fixp->fx_next != NULL
2752 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2753 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2754 && fixp->fx_offset == fixp->fx_next->fx_offset);
2757 /* This function returns true if modifying a register requires a
2761 reg_needs_delay (unsigned int reg)
2763 unsigned long prev_pinfo;
2765 prev_pinfo = history[0].insn_mo->pinfo;
2766 if (! mips_opts.noreorder
2767 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2768 && ! gpr_interlocks)
2769 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2770 && ! cop_interlocks)))
2772 /* A load from a coprocessor or from memory. All load delays
2773 delay the use of general register rt for one instruction. */
2774 /* Itbl support may require additional care here. */
2775 know (prev_pinfo & INSN_WRITE_GPR_T);
2776 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2783 /* Move all labels in LABELS to the current insertion point. TEXT_P
2784 says whether the labels refer to text or data. */
2787 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2789 struct insn_label_list *l;
2792 for (l = labels; l != NULL; l = l->next)
2794 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2795 symbol_set_frag (l->label, frag_now);
2796 val = (valueT) frag_now_fix ();
2797 /* MIPS16/microMIPS text labels are stored as odd. */
2798 if (text_p && HAVE_CODE_COMPRESSION)
2800 S_SET_VALUE (l->label, val);
2804 /* Move all labels in insn_labels to the current insertion point
2805 and treat them as text labels. */
2808 mips_move_text_labels (void)
2810 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2814 s_is_linkonce (symbolS *sym, segT from_seg)
2816 bfd_boolean linkonce = FALSE;
2817 segT symseg = S_GET_SEGMENT (sym);
2819 if (symseg != from_seg && !S_IS_LOCAL (sym))
2821 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2824 /* The GNU toolchain uses an extension for ELF: a section
2825 beginning with the magic string .gnu.linkonce is a
2826 linkonce section. */
2827 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2828 sizeof ".gnu.linkonce" - 1) == 0)
2835 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2836 linker to handle them specially, such as generating jalx instructions
2837 when needed. We also make them odd for the duration of the assembly,
2838 in order to generate the right sort of code. We will make them even
2839 in the adjust_symtab routine, while leaving them marked. This is
2840 convenient for the debugger and the disassembler. The linker knows
2841 to make them odd again. */
2844 mips_compressed_mark_labels (void)
2846 segment_info_type *si = seg_info (now_seg);
2847 struct insn_label_list *l;
2849 gas_assert (HAVE_CODE_COMPRESSION);
2851 for (l = si->label_list; l != NULL; l = l->next)
2853 symbolS *label = l->label;
2855 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2858 if (mips_opts.mips16)
2859 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2861 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2864 if ((S_GET_VALUE (label) & 1) == 0
2865 /* Don't adjust the address if the label is global or weak, or
2866 in a link-once section, since we'll be emitting symbol reloc
2867 references to it which will be patched up by the linker, and
2868 the final value of the symbol may or may not be MIPS16/microMIPS. */
2869 && ! S_IS_WEAK (label)
2870 && ! S_IS_EXTERNAL (label)
2871 && ! s_is_linkonce (label, now_seg))
2872 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2876 /* End the current frag. Make it a variant frag and record the
2880 relax_close_frag (void)
2882 mips_macro_warning.first_frag = frag_now;
2883 frag_var (rs_machine_dependent, 0, 0,
2884 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2885 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2887 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2888 mips_relax.first_fixup = 0;
2891 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2892 See the comment above RELAX_ENCODE for more details. */
2895 relax_start (symbolS *symbol)
2897 gas_assert (mips_relax.sequence == 0);
2898 mips_relax.sequence = 1;
2899 mips_relax.symbol = symbol;
2902 /* Start generating the second version of a relaxable sequence.
2903 See the comment above RELAX_ENCODE for more details. */
2908 gas_assert (mips_relax.sequence == 1);
2909 mips_relax.sequence = 2;
2912 /* End the current relaxable sequence. */
2917 gas_assert (mips_relax.sequence == 2);
2918 relax_close_frag ();
2919 mips_relax.sequence = 0;
2922 /* Return true if IP is a delayed branch or jump. */
2924 static inline bfd_boolean
2925 delayed_branch_p (const struct mips_cl_insn *ip)
2927 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2928 | INSN_COND_BRANCH_DELAY
2929 | INSN_COND_BRANCH_LIKELY)) != 0;
2932 /* Return true if IP is a compact branch or jump. */
2934 static inline bfd_boolean
2935 compact_branch_p (const struct mips_cl_insn *ip)
2937 if (mips_opts.mips16)
2938 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2939 | MIPS16_INSN_COND_BRANCH)) != 0;
2941 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2942 | INSN2_COND_BRANCH)) != 0;
2945 /* Return true if IP is an unconditional branch or jump. */
2947 static inline bfd_boolean
2948 uncond_branch_p (const struct mips_cl_insn *ip)
2950 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2951 || (mips_opts.mips16
2952 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2953 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2956 /* Return true if IP is a branch-likely instruction. */
2958 static inline bfd_boolean
2959 branch_likely_p (const struct mips_cl_insn *ip)
2961 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2964 /* Return the type of nop that should be used to fill the delay slot
2965 of delayed branch IP. */
2967 static struct mips_cl_insn *
2968 get_delay_slot_nop (const struct mips_cl_insn *ip)
2970 if (mips_opts.micromips
2971 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2972 return µmips_nop32_insn;
2976 /* Return the mask of core registers that IP reads or writes. */
2979 gpr_mod_mask (const struct mips_cl_insn *ip)
2981 unsigned long pinfo2;
2985 pinfo2 = ip->insn_mo->pinfo2;
2986 if (mips_opts.micromips)
2988 if (pinfo2 & INSN2_MOD_GPR_MD)
2989 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2990 if (pinfo2 & INSN2_MOD_GPR_MF)
2991 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2992 if (pinfo2 & INSN2_MOD_SP)
2998 /* Return the mask of core registers that IP reads. */
3001 gpr_read_mask (const struct mips_cl_insn *ip)
3003 unsigned long pinfo, pinfo2;
3006 mask = gpr_mod_mask (ip);
3007 pinfo = ip->insn_mo->pinfo;
3008 pinfo2 = ip->insn_mo->pinfo2;
3009 if (mips_opts.mips16)
3011 if (pinfo & MIPS16_INSN_READ_X)
3012 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3013 if (pinfo & MIPS16_INSN_READ_Y)
3014 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3015 if (pinfo & MIPS16_INSN_READ_T)
3017 if (pinfo & MIPS16_INSN_READ_SP)
3019 if (pinfo & MIPS16_INSN_READ_31)
3021 if (pinfo & MIPS16_INSN_READ_Z)
3022 mask |= 1 << (mips16_to_32_reg_map
3023 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3024 if (pinfo & MIPS16_INSN_READ_GPR_X)
3025 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3029 if (pinfo2 & INSN2_READ_GPR_D)
3030 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3031 if (pinfo & INSN_READ_GPR_T)
3032 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3033 if (pinfo & INSN_READ_GPR_S)
3034 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3035 if (pinfo2 & INSN2_READ_GP)
3037 if (pinfo2 & INSN2_READ_GPR_31)
3039 if (pinfo2 & INSN2_READ_GPR_Z)
3040 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3042 if (mips_opts.micromips)
3044 if (pinfo2 & INSN2_READ_GPR_MC)
3045 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3046 if (pinfo2 & INSN2_READ_GPR_ME)
3047 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3048 if (pinfo2 & INSN2_READ_GPR_MG)
3049 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3050 if (pinfo2 & INSN2_READ_GPR_MJ)
3051 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3052 if (pinfo2 & INSN2_READ_GPR_MMN)
3054 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3055 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3057 if (pinfo2 & INSN2_READ_GPR_MP)
3058 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3059 if (pinfo2 & INSN2_READ_GPR_MQ)
3060 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3062 /* Don't include register 0. */
3066 /* Return the mask of core registers that IP writes. */
3069 gpr_write_mask (const struct mips_cl_insn *ip)
3071 unsigned long pinfo, pinfo2;
3074 mask = gpr_mod_mask (ip);
3075 pinfo = ip->insn_mo->pinfo;
3076 pinfo2 = ip->insn_mo->pinfo2;
3077 if (mips_opts.mips16)
3079 if (pinfo & MIPS16_INSN_WRITE_X)
3080 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3081 if (pinfo & MIPS16_INSN_WRITE_Y)
3082 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3083 if (pinfo & MIPS16_INSN_WRITE_Z)
3084 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3085 if (pinfo & MIPS16_INSN_WRITE_T)
3087 if (pinfo & MIPS16_INSN_WRITE_SP)
3089 if (pinfo & MIPS16_INSN_WRITE_31)
3091 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3092 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3096 if (pinfo & INSN_WRITE_GPR_D)
3097 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3098 if (pinfo & INSN_WRITE_GPR_T)
3099 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3100 if (pinfo & INSN_WRITE_GPR_S)
3101 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3102 if (pinfo & INSN_WRITE_GPR_31)
3104 if (pinfo2 & INSN2_WRITE_GPR_Z)
3105 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3107 if (mips_opts.micromips)
3109 if (pinfo2 & INSN2_WRITE_GPR_MB)
3110 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3111 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3113 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3114 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3116 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3117 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3118 if (pinfo2 & INSN2_WRITE_GPR_MP)
3119 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3121 /* Don't include register 0. */
3125 /* Return the mask of floating-point registers that IP reads. */
3128 fpr_read_mask (const struct mips_cl_insn *ip)
3130 unsigned long pinfo, pinfo2;
3134 pinfo = ip->insn_mo->pinfo;
3135 pinfo2 = ip->insn_mo->pinfo2;
3136 if (!mips_opts.mips16)
3138 if (pinfo2 & INSN2_READ_FPR_D)
3139 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3140 if (pinfo & INSN_READ_FPR_S)
3141 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3142 if (pinfo & INSN_READ_FPR_T)
3143 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3144 if (pinfo & INSN_READ_FPR_R)
3145 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3146 if (pinfo2 & INSN2_READ_FPR_Z)
3147 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3149 /* Conservatively treat all operands to an FP_D instruction are doubles.
3150 (This is overly pessimistic for things like cvt.d.s.) */
3151 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3156 /* Return the mask of floating-point registers that IP writes. */
3159 fpr_write_mask (const struct mips_cl_insn *ip)
3161 unsigned long pinfo, pinfo2;
3165 pinfo = ip->insn_mo->pinfo;
3166 pinfo2 = ip->insn_mo->pinfo2;
3167 if (!mips_opts.mips16)
3169 if (pinfo & INSN_WRITE_FPR_D)
3170 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3171 if (pinfo & INSN_WRITE_FPR_S)
3172 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3173 if (pinfo & INSN_WRITE_FPR_T)
3174 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3175 if (pinfo2 & INSN2_WRITE_FPR_Z)
3176 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3178 /* Conservatively treat all operands to an FP_D instruction are doubles.
3179 (This is overly pessimistic for things like cvt.s.d.) */
3180 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3185 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3186 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3187 by VR4120 errata. */
3190 classify_vr4120_insn (const char *name)
3192 if (strncmp (name, "macc", 4) == 0)
3193 return FIX_VR4120_MACC;
3194 if (strncmp (name, "dmacc", 5) == 0)
3195 return FIX_VR4120_DMACC;
3196 if (strncmp (name, "mult", 4) == 0)
3197 return FIX_VR4120_MULT;
3198 if (strncmp (name, "dmult", 5) == 0)
3199 return FIX_VR4120_DMULT;
3200 if (strstr (name, "div"))
3201 return FIX_VR4120_DIV;
3202 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3203 return FIX_VR4120_MTHILO;
3204 return NUM_FIX_VR4120_CLASSES;
3207 #define INSN_ERET 0x42000018
3208 #define INSN_DERET 0x4200001f
3210 /* Return the number of instructions that must separate INSN1 and INSN2,
3211 where INSN1 is the earlier instruction. Return the worst-case value
3212 for any INSN2 if INSN2 is null. */
3215 insns_between (const struct mips_cl_insn *insn1,
3216 const struct mips_cl_insn *insn2)
3218 unsigned long pinfo1, pinfo2;
3221 /* This function needs to know which pinfo flags are set for INSN2
3222 and which registers INSN2 uses. The former is stored in PINFO2 and
3223 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3224 will have every flag set and INSN2_USES_GPR will always return true. */
3225 pinfo1 = insn1->insn_mo->pinfo;
3226 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3228 #define INSN2_USES_GPR(REG) \
3229 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3231 /* For most targets, write-after-read dependencies on the HI and LO
3232 registers must be separated by at least two instructions. */
3233 if (!hilo_interlocks)
3235 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3237 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3241 /* If we're working around r7000 errata, there must be two instructions
3242 between an mfhi or mflo and any instruction that uses the result. */
3243 if (mips_7000_hilo_fix
3244 && !mips_opts.micromips
3245 && MF_HILO_INSN (pinfo1)
3246 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3249 /* If we're working around 24K errata, one instruction is required
3250 if an ERET or DERET is followed by a branch instruction. */
3251 if (mips_fix_24k && !mips_opts.micromips)
3253 if (insn1->insn_opcode == INSN_ERET
3254 || insn1->insn_opcode == INSN_DERET)
3257 || insn2->insn_opcode == INSN_ERET
3258 || insn2->insn_opcode == INSN_DERET
3259 || delayed_branch_p (insn2))
3264 /* If working around VR4120 errata, check for combinations that need
3265 a single intervening instruction. */
3266 if (mips_fix_vr4120 && !mips_opts.micromips)
3268 unsigned int class1, class2;
3270 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3271 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3275 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3276 if (vr4120_conflicts[class1] & (1 << class2))
3281 if (!HAVE_CODE_COMPRESSION)
3283 /* Check for GPR or coprocessor load delays. All such delays
3284 are on the RT register. */
3285 /* Itbl support may require additional care here. */
3286 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3287 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3289 know (pinfo1 & INSN_WRITE_GPR_T);
3290 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3294 /* Check for generic coprocessor hazards.
3296 This case is not handled very well. There is no special
3297 knowledge of CP0 handling, and the coprocessors other than
3298 the floating point unit are not distinguished at all. */
3299 /* Itbl support may require additional care here. FIXME!
3300 Need to modify this to include knowledge about
3301 user specified delays! */
3302 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3303 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3305 /* Handle cases where INSN1 writes to a known general coprocessor
3306 register. There must be a one instruction delay before INSN2
3307 if INSN2 reads that register, otherwise no delay is needed. */
3308 mask = fpr_write_mask (insn1);
3311 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3316 /* Read-after-write dependencies on the control registers
3317 require a two-instruction gap. */
3318 if ((pinfo1 & INSN_WRITE_COND_CODE)
3319 && (pinfo2 & INSN_READ_COND_CODE))
3322 /* We don't know exactly what INSN1 does. If INSN2 is
3323 also a coprocessor instruction, assume there must be
3324 a one instruction gap. */
3325 if (pinfo2 & INSN_COP)
3330 /* Check for read-after-write dependencies on the coprocessor
3331 control registers in cases where INSN1 does not need a general
3332 coprocessor delay. This means that INSN1 is a floating point
3333 comparison instruction. */
3334 /* Itbl support may require additional care here. */
3335 else if (!cop_interlocks
3336 && (pinfo1 & INSN_WRITE_COND_CODE)
3337 && (pinfo2 & INSN_READ_COND_CODE))
3341 #undef INSN2_USES_GPR
3346 /* Return the number of nops that would be needed to work around the
3347 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3348 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3349 that are contained within the first IGNORE instructions of HIST. */
3352 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3353 const struct mips_cl_insn *insn)
3358 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3359 are not affected by the errata. */
3361 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3362 || strcmp (insn->insn_mo->name, "mtlo") == 0
3363 || strcmp (insn->insn_mo->name, "mthi") == 0))
3366 /* Search for the first MFLO or MFHI. */
3367 for (i = 0; i < MAX_VR4130_NOPS; i++)
3368 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3370 /* Extract the destination register. */
3371 mask = gpr_write_mask (&hist[i]);
3373 /* No nops are needed if INSN reads that register. */
3374 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3377 /* ...or if any of the intervening instructions do. */
3378 for (j = 0; j < i; j++)
3379 if (gpr_read_mask (&hist[j]) & mask)
3383 return MAX_VR4130_NOPS - i;
3388 #define BASE_REG_EQ(INSN1, INSN2) \
3389 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3390 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3392 /* Return the minimum alignment for this store instruction. */
3395 fix_24k_align_to (const struct mips_opcode *mo)
3397 if (strcmp (mo->name, "sh") == 0)
3400 if (strcmp (mo->name, "swc1") == 0
3401 || strcmp (mo->name, "swc2") == 0
3402 || strcmp (mo->name, "sw") == 0
3403 || strcmp (mo->name, "sc") == 0
3404 || strcmp (mo->name, "s.s") == 0)
3407 if (strcmp (mo->name, "sdc1") == 0
3408 || strcmp (mo->name, "sdc2") == 0
3409 || strcmp (mo->name, "s.d") == 0)
3416 struct fix_24k_store_info
3418 /* Immediate offset, if any, for this store instruction. */
3420 /* Alignment required by this store instruction. */
3422 /* True for register offsets. */
3423 int register_offset;
3426 /* Comparison function used by qsort. */
3429 fix_24k_sort (const void *a, const void *b)
3431 const struct fix_24k_store_info *pos1 = a;
3432 const struct fix_24k_store_info *pos2 = b;
3434 return (pos1->off - pos2->off);
3437 /* INSN is a store instruction. Try to record the store information
3438 in STINFO. Return false if the information isn't known. */
3441 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3442 const struct mips_cl_insn *insn)
3444 /* The instruction must have a known offset. */
3445 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3448 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3449 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3453 /* Return the number of nops that would be needed to work around the 24k
3454 "lost data on stores during refill" errata if instruction INSN
3455 immediately followed the 2 instructions described by HIST.
3456 Ignore hazards that are contained within the first IGNORE
3457 instructions of HIST.
3459 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3460 for the data cache refills and store data. The following describes
3461 the scenario where the store data could be lost.
3463 * A data cache miss, due to either a load or a store, causing fill
3464 data to be supplied by the memory subsystem
3465 * The first three doublewords of fill data are returned and written
3467 * A sequence of four stores occurs in consecutive cycles around the
3468 final doubleword of the fill:
3472 * Zero, One or more instructions
3475 The four stores A-D must be to different doublewords of the line that
3476 is being filled. The fourth instruction in the sequence above permits
3477 the fill of the final doubleword to be transferred from the FSB into
3478 the cache. In the sequence above, the stores may be either integer
3479 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3480 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3481 different doublewords on the line. If the floating point unit is
3482 running in 1:2 mode, it is not possible to create the sequence above
3483 using only floating point store instructions.
3485 In this case, the cache line being filled is incorrectly marked
3486 invalid, thereby losing the data from any store to the line that
3487 occurs between the original miss and the completion of the five
3488 cycle sequence shown above.
3490 The workarounds are:
3492 * Run the data cache in write-through mode.
3493 * Insert a non-store instruction between
3494 Store A and Store B or Store B and Store C. */
3497 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3498 const struct mips_cl_insn *insn)
3500 struct fix_24k_store_info pos[3];
3501 int align, i, base_offset;
3506 /* If the previous instruction wasn't a store, there's nothing to
3508 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3511 /* If the instructions after the previous one are unknown, we have
3512 to assume the worst. */
3516 /* Check whether we are dealing with three consecutive stores. */
3517 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3518 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3521 /* If we don't know the relationship between the store addresses,
3522 assume the worst. */
3523 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3524 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3527 if (!fix_24k_record_store_info (&pos[0], insn)
3528 || !fix_24k_record_store_info (&pos[1], &hist[0])
3529 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3532 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3534 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3535 X bytes and such that the base register + X is known to be aligned
3538 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3542 align = pos[0].align_to;
3543 base_offset = pos[0].off;
3544 for (i = 1; i < 3; i++)
3545 if (align < pos[i].align_to)
3547 align = pos[i].align_to;
3548 base_offset = pos[i].off;
3550 for (i = 0; i < 3; i++)
3551 pos[i].off -= base_offset;
3554 pos[0].off &= ~align + 1;
3555 pos[1].off &= ~align + 1;
3556 pos[2].off &= ~align + 1;
3558 /* If any two stores write to the same chunk, they also write to the
3559 same doubleword. The offsets are still sorted at this point. */
3560 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3563 /* A range of at least 9 bytes is needed for the stores to be in
3564 non-overlapping doublewords. */
3565 if (pos[2].off - pos[0].off <= 8)
3568 if (pos[2].off - pos[1].off >= 24
3569 || pos[1].off - pos[0].off >= 24
3570 || pos[2].off - pos[0].off >= 32)
3576 /* Return the number of nops that would be needed if instruction INSN
3577 immediately followed the MAX_NOPS instructions given by HIST,
3578 where HIST[0] is the most recent instruction. Ignore hazards
3579 between INSN and the first IGNORE instructions in HIST.
3581 If INSN is null, return the worse-case number of nops for any
3585 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3586 const struct mips_cl_insn *insn)
3588 int i, nops, tmp_nops;
3591 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3593 tmp_nops = insns_between (hist + i, insn) - i;
3594 if (tmp_nops > nops)
3598 if (mips_fix_vr4130 && !mips_opts.micromips)
3600 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3601 if (tmp_nops > nops)
3605 if (mips_fix_24k && !mips_opts.micromips)
3607 tmp_nops = nops_for_24k (ignore, hist, insn);
3608 if (tmp_nops > nops)
3615 /* The variable arguments provide NUM_INSNS extra instructions that
3616 might be added to HIST. Return the largest number of nops that
3617 would be needed after the extended sequence, ignoring hazards
3618 in the first IGNORE instructions. */
3621 nops_for_sequence (int num_insns, int ignore,
3622 const struct mips_cl_insn *hist, ...)
3625 struct mips_cl_insn buffer[MAX_NOPS];
3626 struct mips_cl_insn *cursor;
3629 va_start (args, hist);
3630 cursor = buffer + num_insns;
3631 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3632 while (cursor > buffer)
3633 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3635 nops = nops_for_insn (ignore, buffer, NULL);
3640 /* Like nops_for_insn, but if INSN is a branch, take into account the
3641 worst-case delay for the branch target. */
3644 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3645 const struct mips_cl_insn *insn)
3649 nops = nops_for_insn (ignore, hist, insn);
3650 if (delayed_branch_p (insn))
3652 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3653 hist, insn, get_delay_slot_nop (insn));
3654 if (tmp_nops > nops)
3657 else if (compact_branch_p (insn))
3659 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3660 if (tmp_nops > nops)
3666 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3669 fix_loongson2f_nop (struct mips_cl_insn * ip)
3671 gas_assert (!HAVE_CODE_COMPRESSION);
3672 if (strcmp (ip->insn_mo->name, "nop") == 0)
3673 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3676 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3677 jr target pc &= 'hffff_ffff_cfff_ffff. */
3680 fix_loongson2f_jump (struct mips_cl_insn * ip)
3682 gas_assert (!HAVE_CODE_COMPRESSION);
3683 if (strcmp (ip->insn_mo->name, "j") == 0
3684 || strcmp (ip->insn_mo->name, "jr") == 0
3685 || strcmp (ip->insn_mo->name, "jalr") == 0)
3693 sreg = EXTRACT_OPERAND (0, RS, *ip);
3694 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3697 ep.X_op = O_constant;
3698 ep.X_add_number = 0xcfff0000;
3699 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3700 ep.X_add_number = 0xffff;
3701 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3702 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3707 fix_loongson2f (struct mips_cl_insn * ip)
3709 if (mips_fix_loongson2f_nop)
3710 fix_loongson2f_nop (ip);
3712 if (mips_fix_loongson2f_jump)
3713 fix_loongson2f_jump (ip);
3716 /* IP is a branch that has a delay slot, and we need to fill it
3717 automatically. Return true if we can do that by swapping IP
3718 with the previous instruction. */
3721 can_swap_branch_p (struct mips_cl_insn *ip)
3723 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3724 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3726 /* -O2 and above is required for this optimization. */
3727 if (mips_optimize < 2)
3730 /* If we have seen .set volatile or .set nomove, don't optimize. */
3731 if (mips_opts.nomove)
3734 /* We can't swap if the previous instruction's position is fixed. */
3735 if (history[0].fixed_p)
3738 /* If the previous previous insn was in a .set noreorder, we can't
3739 swap. Actually, the MIPS assembler will swap in this situation.
3740 However, gcc configured -with-gnu-as will generate code like
3748 in which we can not swap the bne and INSN. If gcc is not configured
3749 -with-gnu-as, it does not output the .set pseudo-ops. */
3750 if (history[1].noreorder_p)
3753 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3754 This means that the previous instruction was a 4-byte one anyhow. */
3755 if (mips_opts.mips16 && history[0].fixp[0])
3758 /* If the branch is itself the target of a branch, we can not swap.
3759 We cheat on this; all we check for is whether there is a label on
3760 this instruction. If there are any branches to anything other than
3761 a label, users must use .set noreorder. */
3762 if (seg_info (now_seg)->label_list)
3765 /* If the previous instruction is in a variant frag other than this
3766 branch's one, we cannot do the swap. This does not apply to
3767 MIPS16 code, which uses variant frags for different purposes. */
3768 if (!mips_opts.mips16
3770 && history[0].frag->fr_type == rs_machine_dependent)
3773 /* We do not swap with instructions that cannot architecturally
3774 be placed in a branch delay slot, such as SYNC or ERET. We
3775 also refrain from swapping with a trap instruction, since it
3776 complicates trap handlers to have the trap instruction be in
3778 prev_pinfo = history[0].insn_mo->pinfo;
3779 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3782 /* Check for conflicts between the branch and the instructions
3783 before the candidate delay slot. */
3784 if (nops_for_insn (0, history + 1, ip) > 0)
3787 /* Check for conflicts between the swapped sequence and the
3788 target of the branch. */
3789 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3792 /* If the branch reads a register that the previous
3793 instruction sets, we can not swap. */
3794 gpr_read = gpr_read_mask (ip);
3795 prev_gpr_write = gpr_write_mask (&history[0]);
3796 if (gpr_read & prev_gpr_write)
3799 /* If the branch writes a register that the previous
3800 instruction sets, we can not swap. */
3801 gpr_write = gpr_write_mask (ip);
3802 if (gpr_write & prev_gpr_write)
3805 /* If the branch writes a register that the previous
3806 instruction reads, we can not swap. */
3807 prev_gpr_read = gpr_read_mask (&history[0]);
3808 if (gpr_write & prev_gpr_read)
3811 /* If one instruction sets a condition code and the
3812 other one uses a condition code, we can not swap. */
3813 pinfo = ip->insn_mo->pinfo;
3814 if ((pinfo & INSN_READ_COND_CODE)
3815 && (prev_pinfo & INSN_WRITE_COND_CODE))
3817 if ((pinfo & INSN_WRITE_COND_CODE)
3818 && (prev_pinfo & INSN_READ_COND_CODE))
3821 /* If the previous instruction uses the PC, we can not swap. */
3822 prev_pinfo2 = history[0].insn_mo->pinfo2;
3823 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3825 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3828 /* If the previous instruction has an incorrect size for a fixed
3829 branch delay slot in microMIPS mode, we cannot swap. */
3830 pinfo2 = ip->insn_mo->pinfo2;
3831 if (mips_opts.micromips
3832 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3833 && insn_length (history) != 2)
3835 if (mips_opts.micromips
3836 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3837 && insn_length (history) != 4)
3843 /* Decide how we should add IP to the instruction stream. */
3845 static enum append_method
3846 get_append_method (struct mips_cl_insn *ip)
3848 unsigned long pinfo;
3850 /* The relaxed version of a macro sequence must be inherently
3852 if (mips_relax.sequence == 2)
3855 /* We must not dabble with instructions in a ".set norerorder" block. */
3856 if (mips_opts.noreorder)
3859 /* Otherwise, it's our responsibility to fill branch delay slots. */
3860 if (delayed_branch_p (ip))
3862 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3865 pinfo = ip->insn_mo->pinfo;
3866 if (mips_opts.mips16
3867 && ISA_SUPPORTS_MIPS16E
3868 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3869 return APPEND_ADD_COMPACT;
3871 return APPEND_ADD_WITH_NOP;
3877 /* IP is a MIPS16 instruction whose opcode we have just changed.
3878 Point IP->insn_mo to the new opcode's definition. */
3881 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3883 const struct mips_opcode *mo, *end;
3885 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3886 for (mo = ip->insn_mo; mo < end; mo++)
3887 if ((ip->insn_opcode & mo->mask) == mo->match)
3895 /* For microMIPS macros, we need to generate a local number label
3896 as the target of branches. */
3897 #define MICROMIPS_LABEL_CHAR '\037'
3898 static unsigned long micromips_target_label;
3899 static char micromips_target_name[32];
3902 micromips_label_name (void)
3904 char *p = micromips_target_name;
3905 char symbol_name_temporary[24];
3913 l = micromips_target_label;
3914 #ifdef LOCAL_LABEL_PREFIX
3915 *p++ = LOCAL_LABEL_PREFIX;
3918 *p++ = MICROMIPS_LABEL_CHAR;
3921 symbol_name_temporary[i++] = l % 10 + '0';
3926 *p++ = symbol_name_temporary[--i];
3929 return micromips_target_name;
3933 micromips_label_expr (expressionS *label_expr)
3935 label_expr->X_op = O_symbol;
3936 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3937 label_expr->X_add_number = 0;
3941 micromips_label_inc (void)
3943 micromips_target_label++;
3944 *micromips_target_name = '\0';
3948 micromips_add_label (void)
3952 s = colon (micromips_label_name ());
3953 micromips_label_inc ();
3954 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3956 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3962 /* If assembling microMIPS code, then return the microMIPS reloc
3963 corresponding to the requested one if any. Otherwise return
3964 the reloc unchanged. */
3966 static bfd_reloc_code_real_type
3967 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3969 static const bfd_reloc_code_real_type relocs[][2] =
3971 /* Keep sorted incrementally by the left-hand key. */
3972 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3973 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3974 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3975 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3976 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3977 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3978 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3979 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3980 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3981 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3982 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3983 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3984 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3985 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3986 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3987 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3988 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3989 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3990 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3991 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3992 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3993 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3994 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3995 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3996 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3997 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3998 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4000 bfd_reloc_code_real_type r;
4003 if (!mips_opts.micromips)
4005 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4011 return relocs[i][1];
4016 /* Output an instruction. IP is the instruction information.
4017 ADDRESS_EXPR is an operand of the instruction to be used with
4018 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4019 a macro expansion. */
4022 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4023 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4025 unsigned long prev_pinfo2, pinfo;
4026 bfd_boolean relaxed_branch = FALSE;
4027 enum append_method method;
4028 bfd_boolean relax32;
4031 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4032 fix_loongson2f (ip);
4034 mips_mark_labels ();
4036 file_ase_mips16 |= mips_opts.mips16;
4037 file_ase_micromips |= mips_opts.micromips;
4039 prev_pinfo2 = history[0].insn_mo->pinfo2;
4040 pinfo = ip->insn_mo->pinfo;
4042 if (mips_opts.micromips
4044 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4045 && micromips_insn_length (ip->insn_mo) != 2)
4046 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4047 && micromips_insn_length (ip->insn_mo) != 4)))
4048 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4049 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4051 if (address_expr == NULL)
4053 else if (*reloc_type <= BFD_RELOC_UNUSED
4054 && address_expr->X_op == O_constant)
4059 switch (*reloc_type)
4062 ip->insn_opcode |= address_expr->X_add_number;
4065 case BFD_RELOC_MIPS_HIGHEST:
4066 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
4067 ip->insn_opcode |= tmp & 0xffff;
4070 case BFD_RELOC_MIPS_HIGHER:
4071 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
4072 ip->insn_opcode |= tmp & 0xffff;
4075 case BFD_RELOC_HI16_S:
4076 tmp = (address_expr->X_add_number + 0x8000) >> 16;
4077 ip->insn_opcode |= tmp & 0xffff;
4080 case BFD_RELOC_HI16:
4081 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4084 case BFD_RELOC_UNUSED:
4085 case BFD_RELOC_LO16:
4086 case BFD_RELOC_MIPS_GOT_DISP:
4087 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4090 case BFD_RELOC_MIPS_JMP:
4094 shift = mips_opts.micromips ? 1 : 2;
4095 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4096 as_bad (_("jump to misaligned address (0x%lx)"),
4097 (unsigned long) address_expr->X_add_number);
4098 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4104 case BFD_RELOC_MIPS16_JMP:
4105 if ((address_expr->X_add_number & 3) != 0)
4106 as_bad (_("jump to misaligned address (0x%lx)"),
4107 (unsigned long) address_expr->X_add_number);
4109 (((address_expr->X_add_number & 0x7c0000) << 3)
4110 | ((address_expr->X_add_number & 0xf800000) >> 7)
4111 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4115 case BFD_RELOC_16_PCREL_S2:
4119 shift = mips_opts.micromips ? 1 : 2;
4120 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4121 as_bad (_("branch to misaligned address (0x%lx)"),
4122 (unsigned long) address_expr->X_add_number);
4123 if (!mips_relax_branch)
4125 if ((address_expr->X_add_number + (1 << (shift + 15)))
4126 & ~((1 << (shift + 16)) - 1))
4127 as_bad (_("branch address range overflow (0x%lx)"),
4128 (unsigned long) address_expr->X_add_number);
4129 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4141 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4143 /* There are a lot of optimizations we could do that we don't.
4144 In particular, we do not, in general, reorder instructions.
4145 If you use gcc with optimization, it will reorder
4146 instructions and generally do much more optimization then we
4147 do here; repeating all that work in the assembler would only
4148 benefit hand written assembly code, and does not seem worth
4150 int nops = (mips_optimize == 0
4151 ? nops_for_insn (0, history, NULL)
4152 : nops_for_insn_or_target (0, history, ip));
4156 unsigned long old_frag_offset;
4159 old_frag = frag_now;
4160 old_frag_offset = frag_now_fix ();
4162 for (i = 0; i < nops; i++)
4163 add_fixed_insn (NOP_INSN);
4164 insert_into_history (0, nops, NOP_INSN);
4168 listing_prev_line ();
4169 /* We may be at the start of a variant frag. In case we
4170 are, make sure there is enough space for the frag
4171 after the frags created by listing_prev_line. The
4172 argument to frag_grow here must be at least as large
4173 as the argument to all other calls to frag_grow in
4174 this file. We don't have to worry about being in the
4175 middle of a variant frag, because the variants insert
4176 all needed nop instructions themselves. */
4180 mips_move_text_labels ();
4182 #ifndef NO_ECOFF_DEBUGGING
4183 if (ECOFF_DEBUGGING)
4184 ecoff_fix_loc (old_frag, old_frag_offset);
4188 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4192 /* Work out how many nops in prev_nop_frag are needed by IP,
4193 ignoring hazards generated by the first prev_nop_frag_since
4195 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4196 gas_assert (nops <= prev_nop_frag_holds);
4198 /* Enforce NOPS as a minimum. */
4199 if (nops > prev_nop_frag_required)
4200 prev_nop_frag_required = nops;
4202 if (prev_nop_frag_holds == prev_nop_frag_required)
4204 /* Settle for the current number of nops. Update the history
4205 accordingly (for the benefit of any future .set reorder code). */
4206 prev_nop_frag = NULL;
4207 insert_into_history (prev_nop_frag_since,
4208 prev_nop_frag_holds, NOP_INSN);
4212 /* Allow this instruction to replace one of the nops that was
4213 tentatively added to prev_nop_frag. */
4214 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4215 prev_nop_frag_holds--;
4216 prev_nop_frag_since++;
4220 method = get_append_method (ip);
4221 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4224 /* The value passed to dwarf2_emit_insn is the distance between
4225 the beginning of the current instruction and the address that
4226 should be recorded in the debug tables. This is normally the
4229 For MIPS16/microMIPS debug info we want to use ISA-encoded
4230 addresses, so we use -1 for an address higher by one than the
4233 If the instruction produced is a branch that we will swap with
4234 the preceding instruction, then we add the displacement by which
4235 the branch will be moved backwards. This is more appropriate
4236 and for MIPS16/microMIPS code also prevents a debugger from
4237 placing a breakpoint in the middle of the branch (and corrupting
4238 code if software breakpoints are used). */
4239 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4242 relax32 = (mips_relax_branch
4243 /* Don't try branch relaxation within .set nomacro, or within
4244 .set noat if we use $at for PIC computations. If it turns
4245 out that the branch was out-of-range, we'll get an error. */
4246 && !mips_opts.warn_about_macros
4247 && (mips_opts.at || mips_pic == NO_PIC)
4248 /* Don't relax BPOSGE32/64 as they have no complementing
4250 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4252 if (!HAVE_CODE_COMPRESSION
4255 && *reloc_type == BFD_RELOC_16_PCREL_S2
4256 && delayed_branch_p (ip))
4258 relaxed_branch = TRUE;
4259 add_relaxed_insn (ip, (relaxed_branch_length
4261 uncond_branch_p (ip) ? -1
4262 : branch_likely_p (ip) ? 1
4266 uncond_branch_p (ip),
4267 branch_likely_p (ip),
4268 pinfo & INSN_WRITE_GPR_31,
4270 address_expr->X_add_symbol,
4271 address_expr->X_add_number);
4272 *reloc_type = BFD_RELOC_UNUSED;
4274 else if (mips_opts.micromips
4276 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4277 || *reloc_type > BFD_RELOC_UNUSED)
4278 && (delayed_branch_p (ip) || compact_branch_p (ip))
4279 /* Don't try branch relaxation when users specify
4280 16-bit/32-bit instructions. */
4281 && !forced_insn_length)
4283 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4284 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4285 int uncond = uncond_branch_p (ip) ? -1 : 0;
4286 int compact = compact_branch_p (ip);
4287 int al = pinfo & INSN_WRITE_GPR_31;
4290 gas_assert (address_expr != NULL);
4291 gas_assert (!mips_relax.sequence);
4293 relaxed_branch = TRUE;
4294 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4295 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4296 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4298 address_expr->X_add_symbol,
4299 address_expr->X_add_number);
4300 *reloc_type = BFD_RELOC_UNUSED;
4302 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4304 /* We need to set up a variant frag. */
4305 gas_assert (address_expr != NULL);
4306 add_relaxed_insn (ip, 4, 0,
4308 (*reloc_type - BFD_RELOC_UNUSED,
4309 forced_insn_length == 2, forced_insn_length == 4,
4310 delayed_branch_p (&history[0]),
4311 history[0].mips16_absolute_jump_p),
4312 make_expr_symbol (address_expr), 0);
4314 else if (mips_opts.mips16 && insn_length (ip) == 2)
4316 if (!delayed_branch_p (ip))
4317 /* Make sure there is enough room to swap this instruction with
4318 a following jump instruction. */
4320 add_fixed_insn (ip);
4324 if (mips_opts.mips16
4325 && mips_opts.noreorder
4326 && delayed_branch_p (&history[0]))
4327 as_warn (_("extended instruction in delay slot"));
4329 if (mips_relax.sequence)
4331 /* If we've reached the end of this frag, turn it into a variant
4332 frag and record the information for the instructions we've
4334 if (frag_room () < 4)
4335 relax_close_frag ();
4336 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4339 if (mips_relax.sequence != 2)
4341 if (mips_macro_warning.first_insn_sizes[0] == 0)
4342 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4343 mips_macro_warning.sizes[0] += insn_length (ip);
4344 mips_macro_warning.insns[0]++;
4346 if (mips_relax.sequence != 1)
4348 if (mips_macro_warning.first_insn_sizes[1] == 0)
4349 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4350 mips_macro_warning.sizes[1] += insn_length (ip);
4351 mips_macro_warning.insns[1]++;
4354 if (mips_opts.mips16)
4357 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4359 add_fixed_insn (ip);
4362 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4364 bfd_reloc_code_real_type final_type[3];
4365 reloc_howto_type *howto0;
4366 reloc_howto_type *howto;
4369 /* Perform any necessary conversion to microMIPS relocations
4370 and find out how many relocations there actually are. */
4371 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4372 final_type[i] = micromips_map_reloc (reloc_type[i]);
4374 /* In a compound relocation, it is the final (outermost)
4375 operator that determines the relocated field. */
4376 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4380 /* To reproduce this failure try assembling gas/testsuites/
4381 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4383 as_bad (_("Unsupported MIPS relocation number %d"),
4385 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4389 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4390 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4391 bfd_get_reloc_size (howto),
4393 howto0 && howto0->pc_relative,
4396 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4397 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4398 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4400 /* These relocations can have an addend that won't fit in
4401 4 octets for 64bit assembly. */
4403 && ! howto->partial_inplace
4404 && (reloc_type[0] == BFD_RELOC_16
4405 || reloc_type[0] == BFD_RELOC_32
4406 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4407 || reloc_type[0] == BFD_RELOC_GPREL16
4408 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4409 || reloc_type[0] == BFD_RELOC_GPREL32
4410 || reloc_type[0] == BFD_RELOC_64
4411 || reloc_type[0] == BFD_RELOC_CTOR
4412 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4413 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4414 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4415 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4416 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4417 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4418 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4419 || hi16_reloc_p (reloc_type[0])
4420 || lo16_reloc_p (reloc_type[0])))
4421 ip->fixp[0]->fx_no_overflow = 1;
4423 if (mips_relax.sequence)
4425 if (mips_relax.first_fixup == 0)
4426 mips_relax.first_fixup = ip->fixp[0];
4428 else if (reloc_needs_lo_p (*reloc_type))
4430 struct mips_hi_fixup *hi_fixup;
4432 /* Reuse the last entry if it already has a matching %lo. */
4433 hi_fixup = mips_hi_fixup_list;
4435 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4437 hi_fixup = ((struct mips_hi_fixup *)
4438 xmalloc (sizeof (struct mips_hi_fixup)));
4439 hi_fixup->next = mips_hi_fixup_list;
4440 mips_hi_fixup_list = hi_fixup;
4442 hi_fixup->fixp = ip->fixp[0];
4443 hi_fixup->seg = now_seg;
4446 /* Add fixups for the second and third relocations, if given.
4447 Note that the ABI allows the second relocation to be
4448 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4449 moment we only use RSS_UNDEF, but we could add support
4450 for the others if it ever becomes necessary. */
4451 for (i = 1; i < 3; i++)
4452 if (reloc_type[i] != BFD_RELOC_UNUSED)
4454 ip->fixp[i] = fix_new (ip->frag, ip->where,
4455 ip->fixp[0]->fx_size, NULL, 0,
4456 FALSE, final_type[i]);
4458 /* Use fx_tcbit to mark compound relocs. */
4459 ip->fixp[0]->fx_tcbit = 1;
4460 ip->fixp[i]->fx_tcbit = 1;
4465 /* Update the register mask information. */
4466 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4467 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4472 insert_into_history (0, 1, ip);
4475 case APPEND_ADD_WITH_NOP:
4477 struct mips_cl_insn *nop;
4479 insert_into_history (0, 1, ip);
4480 nop = get_delay_slot_nop (ip);
4481 add_fixed_insn (nop);
4482 insert_into_history (0, 1, nop);
4483 if (mips_relax.sequence)
4484 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4488 case APPEND_ADD_COMPACT:
4489 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4490 gas_assert (mips_opts.mips16);
4491 ip->insn_opcode |= 0x0080;
4492 find_altered_mips16_opcode (ip);
4494 insert_into_history (0, 1, ip);
4499 struct mips_cl_insn delay = history[0];
4500 if (mips_opts.mips16)
4502 know (delay.frag == ip->frag);
4503 move_insn (ip, delay.frag, delay.where);
4504 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4506 else if (relaxed_branch || delay.frag != ip->frag)
4508 /* Add the delay slot instruction to the end of the
4509 current frag and shrink the fixed part of the
4510 original frag. If the branch occupies the tail of
4511 the latter, move it backwards to cover the gap. */
4512 delay.frag->fr_fix -= branch_disp;
4513 if (delay.frag == ip->frag)
4514 move_insn (ip, ip->frag, ip->where - branch_disp);
4515 add_fixed_insn (&delay);
4519 move_insn (&delay, ip->frag,
4520 ip->where - branch_disp + insn_length (ip));
4521 move_insn (ip, history[0].frag, history[0].where);
4525 insert_into_history (0, 1, &delay);
4530 /* If we have just completed an unconditional branch, clear the history. */
4531 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4532 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4533 mips_no_prev_insn ();
4535 /* We need to emit a label at the end of branch-likely macros. */
4536 if (emit_branch_likely_macro)
4538 emit_branch_likely_macro = FALSE;
4539 micromips_add_label ();
4542 /* We just output an insn, so the next one doesn't have a label. */
4543 mips_clear_insn_labels ();
4546 /* Forget that there was any previous instruction or label. */
4549 mips_no_prev_insn (void)
4551 prev_nop_frag = NULL;
4552 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4553 mips_clear_insn_labels ();
4556 /* This function must be called before we emit something other than
4557 instructions. It is like mips_no_prev_insn except that it inserts
4558 any NOPS that might be needed by previous instructions. */
4561 mips_emit_delays (void)
4563 if (! mips_opts.noreorder)
4565 int nops = nops_for_insn (0, history, NULL);
4569 add_fixed_insn (NOP_INSN);
4570 mips_move_text_labels ();
4573 mips_no_prev_insn ();
4576 /* Start a (possibly nested) noreorder block. */
4579 start_noreorder (void)
4581 if (mips_opts.noreorder == 0)
4586 /* None of the instructions before the .set noreorder can be moved. */
4587 for (i = 0; i < ARRAY_SIZE (history); i++)
4588 history[i].fixed_p = 1;
4590 /* Insert any nops that might be needed between the .set noreorder
4591 block and the previous instructions. We will later remove any
4592 nops that turn out not to be needed. */
4593 nops = nops_for_insn (0, history, NULL);
4596 if (mips_optimize != 0)
4598 /* Record the frag which holds the nop instructions, so
4599 that we can remove them if we don't need them. */
4600 frag_grow (nops * NOP_INSN_SIZE);
4601 prev_nop_frag = frag_now;
4602 prev_nop_frag_holds = nops;
4603 prev_nop_frag_required = 0;
4604 prev_nop_frag_since = 0;
4607 for (; nops > 0; --nops)
4608 add_fixed_insn (NOP_INSN);
4610 /* Move on to a new frag, so that it is safe to simply
4611 decrease the size of prev_nop_frag. */
4612 frag_wane (frag_now);
4614 mips_move_text_labels ();
4616 mips_mark_labels ();
4617 mips_clear_insn_labels ();
4619 mips_opts.noreorder++;
4620 mips_any_noreorder = 1;
4623 /* End a nested noreorder block. */
4626 end_noreorder (void)
4628 mips_opts.noreorder--;
4629 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4631 /* Commit to inserting prev_nop_frag_required nops and go back to
4632 handling nop insertion the .set reorder way. */
4633 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4635 insert_into_history (prev_nop_frag_since,
4636 prev_nop_frag_required, NOP_INSN);
4637 prev_nop_frag = NULL;
4641 /* Set up global variables for the start of a new macro. */
4646 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4647 memset (&mips_macro_warning.first_insn_sizes, 0,
4648 sizeof (mips_macro_warning.first_insn_sizes));
4649 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4650 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4651 && delayed_branch_p (&history[0]));
4652 switch (history[0].insn_mo->pinfo2
4653 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4655 case INSN2_BRANCH_DELAY_32BIT:
4656 mips_macro_warning.delay_slot_length = 4;
4658 case INSN2_BRANCH_DELAY_16BIT:
4659 mips_macro_warning.delay_slot_length = 2;
4662 mips_macro_warning.delay_slot_length = 0;
4665 mips_macro_warning.first_frag = NULL;
4668 /* Given that a macro is longer than one instruction or of the wrong size,
4669 return the appropriate warning for it. Return null if no warning is
4670 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4671 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4672 and RELAX_NOMACRO. */
4675 macro_warning (relax_substateT subtype)
4677 if (subtype & RELAX_DELAY_SLOT)
4678 return _("Macro instruction expanded into multiple instructions"
4679 " in a branch delay slot");
4680 else if (subtype & RELAX_NOMACRO)
4681 return _("Macro instruction expanded into multiple instructions");
4682 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4683 | RELAX_DELAY_SLOT_SIZE_SECOND))
4684 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4685 ? _("Macro instruction expanded into a wrong size instruction"
4686 " in a 16-bit branch delay slot")
4687 : _("Macro instruction expanded into a wrong size instruction"
4688 " in a 32-bit branch delay slot"));
4693 /* Finish up a macro. Emit warnings as appropriate. */
4698 /* Relaxation warning flags. */
4699 relax_substateT subtype = 0;
4701 /* Check delay slot size requirements. */
4702 if (mips_macro_warning.delay_slot_length == 2)
4703 subtype |= RELAX_DELAY_SLOT_16BIT;
4704 if (mips_macro_warning.delay_slot_length != 0)
4706 if (mips_macro_warning.delay_slot_length
4707 != mips_macro_warning.first_insn_sizes[0])
4708 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4709 if (mips_macro_warning.delay_slot_length
4710 != mips_macro_warning.first_insn_sizes[1])
4711 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4714 /* Check instruction count requirements. */
4715 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4717 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4718 subtype |= RELAX_SECOND_LONGER;
4719 if (mips_opts.warn_about_macros)
4720 subtype |= RELAX_NOMACRO;
4721 if (mips_macro_warning.delay_slot_p)
4722 subtype |= RELAX_DELAY_SLOT;
4725 /* If both alternatives fail to fill a delay slot correctly,
4726 emit the warning now. */
4727 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4728 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4733 s = subtype & (RELAX_DELAY_SLOT_16BIT
4734 | RELAX_DELAY_SLOT_SIZE_FIRST
4735 | RELAX_DELAY_SLOT_SIZE_SECOND);
4736 msg = macro_warning (s);
4738 as_warn ("%s", msg);
4742 /* If both implementations are longer than 1 instruction, then emit the
4744 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4749 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4750 msg = macro_warning (s);
4752 as_warn ("%s", msg);
4756 /* If any flags still set, then one implementation might need a warning
4757 and the other either will need one of a different kind or none at all.
4758 Pass any remaining flags over to relaxation. */
4759 if (mips_macro_warning.first_frag != NULL)
4760 mips_macro_warning.first_frag->fr_subtype |= subtype;
4763 /* Instruction operand formats used in macros that vary between
4764 standard MIPS and microMIPS code. */
4766 static const char * const brk_fmt[2] = { "c", "mF" };
4767 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4768 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4769 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4770 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4771 static const char * const mfhl_fmt[2] = { "d", "mj" };
4772 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4773 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4775 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4776 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4777 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4778 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4779 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4780 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4781 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4782 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4784 /* Read a macro's relocation codes from *ARGS and store them in *R.
4785 The first argument in *ARGS will be either the code for a single
4786 relocation or -1 followed by the three codes that make up a
4787 composite relocation. */
4790 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4794 next = va_arg (*args, int);
4796 r[0] = (bfd_reloc_code_real_type) next;
4798 for (i = 0; i < 3; i++)
4799 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4802 /* Build an instruction created by a macro expansion. This is passed
4803 a pointer to the count of instructions created so far, an
4804 expression, the name of the instruction to build, an operand format
4805 string, and corresponding arguments. */
4808 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4810 const struct mips_opcode *mo = NULL;
4811 bfd_reloc_code_real_type r[3];
4812 const struct mips_opcode *amo;
4813 struct hash_control *hash;
4814 struct mips_cl_insn insn;
4817 va_start (args, fmt);
4819 if (mips_opts.mips16)
4821 mips16_macro_build (ep, name, fmt, &args);
4826 r[0] = BFD_RELOC_UNUSED;
4827 r[1] = BFD_RELOC_UNUSED;
4828 r[2] = BFD_RELOC_UNUSED;
4829 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4830 amo = (struct mips_opcode *) hash_find (hash, name);
4832 gas_assert (strcmp (name, amo->name) == 0);
4836 /* Search until we get a match for NAME. It is assumed here that
4837 macros will never generate MDMX, MIPS-3D, or MT instructions.
4838 We try to match an instruction that fulfils the branch delay
4839 slot instruction length requirement (if any) of the previous
4840 instruction. While doing this we record the first instruction
4841 seen that matches all the other conditions and use it anyway
4842 if the requirement cannot be met; we will issue an appropriate
4843 warning later on. */
4844 if (strcmp (fmt, amo->args) == 0
4845 && amo->pinfo != INSN_MACRO
4846 && is_opcode_valid (amo)
4847 && is_size_valid (amo))
4849 if (is_delay_slot_valid (amo))
4859 gas_assert (amo->name);
4861 while (strcmp (name, amo->name) == 0);
4864 create_insn (&insn, mo);
4882 INSERT_OPERAND (mips_opts.micromips,
4883 EXTLSB, insn, va_arg (args, int));
4888 /* Note that in the macro case, these arguments are already
4889 in MSB form. (When handling the instruction in the
4890 non-macro case, these arguments are sizes from which
4891 MSB values must be calculated.) */
4892 INSERT_OPERAND (mips_opts.micromips,
4893 INSMSB, insn, va_arg (args, int));
4899 /* Note that in the macro case, these arguments are already
4900 in MSBD form. (When handling the instruction in the
4901 non-macro case, these arguments are sizes from which
4902 MSBD values must be calculated.) */
4903 INSERT_OPERAND (mips_opts.micromips,
4904 EXTMSBD, insn, va_arg (args, int));
4908 gas_assert (!mips_opts.micromips);
4909 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4918 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
4922 gas_assert (mips_opts.micromips);
4926 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4930 gas_assert (!mips_opts.micromips);
4931 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4935 gas_assert (!mips_opts.micromips);
4937 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4941 if (mips_opts.micromips)
4942 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4944 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4948 gas_assert (!mips_opts.micromips);
4950 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
4954 gas_assert (!mips_opts.micromips);
4956 int tmp = va_arg (args, int);
4958 INSERT_OPERAND (0, RT, insn, tmp);
4959 INSERT_OPERAND (0, RD, insn, tmp);
4965 gas_assert (!mips_opts.micromips);
4966 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
4973 INSERT_OPERAND (mips_opts.micromips,
4974 SHAMT, insn, va_arg (args, int));
4978 gas_assert (!mips_opts.micromips);
4979 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
4983 gas_assert (!mips_opts.micromips);
4984 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
4988 gas_assert (!mips_opts.micromips);
4989 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4993 gas_assert (!mips_opts.micromips);
4994 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5001 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5006 macro_read_relocs (&args, r);
5007 gas_assert (*r == BFD_RELOC_GPREL16
5008 || *r == BFD_RELOC_MIPS_HIGHER
5009 || *r == BFD_RELOC_HI16_S
5010 || *r == BFD_RELOC_LO16
5011 || *r == BFD_RELOC_MIPS_GOT_OFST);
5015 macro_read_relocs (&args, r);
5019 macro_read_relocs (&args, r);
5020 gas_assert (ep != NULL
5021 && (ep->X_op == O_constant
5022 || (ep->X_op == O_symbol
5023 && (*r == BFD_RELOC_MIPS_HIGHEST
5024 || *r == BFD_RELOC_HI16_S
5025 || *r == BFD_RELOC_HI16
5026 || *r == BFD_RELOC_GPREL16
5027 || *r == BFD_RELOC_MIPS_GOT_HI16
5028 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5032 gas_assert (ep != NULL);
5035 * This allows macro() to pass an immediate expression for
5036 * creating short branches without creating a symbol.
5038 * We don't allow branch relaxation for these branches, as
5039 * they should only appear in ".set nomacro" anyway.
5041 if (ep->X_op == O_constant)
5043 /* For microMIPS we always use relocations for branches.
5044 So we should not resolve immediate values. */
5045 gas_assert (!mips_opts.micromips);
5047 if ((ep->X_add_number & 3) != 0)
5048 as_bad (_("branch to misaligned address (0x%lx)"),
5049 (unsigned long) ep->X_add_number);
5050 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5051 as_bad (_("branch address range overflow (0x%lx)"),
5052 (unsigned long) ep->X_add_number);
5053 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5057 *r = BFD_RELOC_16_PCREL_S2;
5061 gas_assert (ep != NULL);
5062 *r = BFD_RELOC_MIPS_JMP;
5066 gas_assert (!mips_opts.micromips);
5067 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5071 INSERT_OPERAND (mips_opts.micromips,
5072 CACHE, insn, va_arg (args, unsigned long));
5076 gas_assert (mips_opts.micromips);
5077 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5081 gas_assert (mips_opts.micromips);
5082 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5086 INSERT_OPERAND (mips_opts.micromips,
5087 3BITPOS, insn, va_arg (args, unsigned int));
5091 INSERT_OPERAND (mips_opts.micromips,
5092 OFFSET12, insn, va_arg (args, unsigned long));
5096 gas_assert (mips_opts.micromips);
5097 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5100 case 'm': /* Opcode extension character. */
5101 gas_assert (mips_opts.micromips);
5105 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5109 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5113 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5127 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5129 append_insn (&insn, ep, r, TRUE);
5133 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5136 struct mips_opcode *mo;
5137 struct mips_cl_insn insn;
5138 bfd_reloc_code_real_type r[3]
5139 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5141 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5143 gas_assert (strcmp (name, mo->name) == 0);
5145 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5148 gas_assert (mo->name);
5149 gas_assert (strcmp (name, mo->name) == 0);
5152 create_insn (&insn, mo);
5170 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5175 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5179 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5183 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5193 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5200 regno = va_arg (*args, int);
5201 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5202 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5223 gas_assert (ep != NULL);
5225 if (ep->X_op != O_constant)
5226 *r = (int) BFD_RELOC_UNUSED + c;
5229 mips16_immed (NULL, 0, c, *r, ep->X_add_number,
5230 0, &insn.insn_opcode);
5232 *r = BFD_RELOC_UNUSED;
5238 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5245 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5247 append_insn (&insn, ep, r, TRUE);
5251 * Sign-extend 32-bit mode constants that have bit 31 set and all
5252 * higher bits unset.
5255 normalize_constant_expr (expressionS *ex)
5257 if (ex->X_op == O_constant
5258 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5259 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5264 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5265 * all higher bits unset.
5268 normalize_address_expr (expressionS *ex)
5270 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5271 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5272 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5273 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5278 * Generate a "jalr" instruction with a relocation hint to the called
5279 * function. This occurs in NewABI PIC code.
5282 macro_build_jalr (expressionS *ep, int cprestore)
5284 static const bfd_reloc_code_real_type jalr_relocs[2]
5285 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5286 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5290 if (MIPS_JALR_HINT_P (ep))
5295 if (mips_opts.micromips)
5297 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5298 if (MIPS_JALR_HINT_P (ep))
5299 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5301 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5304 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5305 if (MIPS_JALR_HINT_P (ep))
5306 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5310 * Generate a "lui" instruction.
5313 macro_build_lui (expressionS *ep, int regnum)
5315 gas_assert (! mips_opts.mips16);
5317 if (ep->X_op != O_constant)
5319 gas_assert (ep->X_op == O_symbol);
5320 /* _gp_disp is a special case, used from s_cpload.
5321 __gnu_local_gp is used if mips_no_shared. */
5322 gas_assert (mips_pic == NO_PIC
5324 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5325 || (! mips_in_shared
5326 && strcmp (S_GET_NAME (ep->X_add_symbol),
5327 "__gnu_local_gp") == 0));
5330 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5333 /* Generate a sequence of instructions to do a load or store from a constant
5334 offset off of a base register (breg) into/from a target register (treg),
5335 using AT if necessary. */
5337 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5338 int treg, int breg, int dbl)
5340 gas_assert (ep->X_op == O_constant);
5342 /* Sign-extending 32-bit constants makes their handling easier. */
5344 normalize_constant_expr (ep);
5346 /* Right now, this routine can only handle signed 32-bit constants. */
5347 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5348 as_warn (_("operand overflow"));
5350 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5352 /* Signed 16-bit offset will fit in the op. Easy! */
5353 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5357 /* 32-bit offset, need multiple instructions and AT, like:
5358 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5359 addu $tempreg,$tempreg,$breg
5360 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5361 to handle the complete offset. */
5362 macro_build_lui (ep, AT);
5363 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5364 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5367 as_bad (_("Macro used $at after \".set noat\""));
5372 * Generates code to set the $at register to true (one)
5373 * if reg is less than the immediate expression.
5376 set_at (int reg, int unsignedp)
5378 if (imm_expr.X_op == O_constant
5379 && imm_expr.X_add_number >= -0x8000
5380 && imm_expr.X_add_number < 0x8000)
5381 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5382 AT, reg, BFD_RELOC_LO16);
5385 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5386 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5390 /* Warn if an expression is not a constant. */
5393 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5395 if (ex->X_op == O_big)
5396 as_bad (_("unsupported large constant"));
5397 else if (ex->X_op != O_constant)
5398 as_bad (_("Instruction %s requires absolute expression"),
5401 if (HAVE_32BIT_GPRS)
5402 normalize_constant_expr (ex);
5405 /* Count the leading zeroes by performing a binary chop. This is a
5406 bulky bit of source, but performance is a LOT better for the
5407 majority of values than a simple loop to count the bits:
5408 for (lcnt = 0; (lcnt < 32); lcnt++)
5409 if ((v) & (1 << (31 - lcnt)))
5411 However it is not code size friendly, and the gain will drop a bit
5412 on certain cached systems.
5414 #define COUNT_TOP_ZEROES(v) \
5415 (((v) & ~0xffff) == 0 \
5416 ? ((v) & ~0xff) == 0 \
5417 ? ((v) & ~0xf) == 0 \
5418 ? ((v) & ~0x3) == 0 \
5419 ? ((v) & ~0x1) == 0 \
5424 : ((v) & ~0x7) == 0 \
5427 : ((v) & ~0x3f) == 0 \
5428 ? ((v) & ~0x1f) == 0 \
5431 : ((v) & ~0x7f) == 0 \
5434 : ((v) & ~0xfff) == 0 \
5435 ? ((v) & ~0x3ff) == 0 \
5436 ? ((v) & ~0x1ff) == 0 \
5439 : ((v) & ~0x7ff) == 0 \
5442 : ((v) & ~0x3fff) == 0 \
5443 ? ((v) & ~0x1fff) == 0 \
5446 : ((v) & ~0x7fff) == 0 \
5449 : ((v) & ~0xffffff) == 0 \
5450 ? ((v) & ~0xfffff) == 0 \
5451 ? ((v) & ~0x3ffff) == 0 \
5452 ? ((v) & ~0x1ffff) == 0 \
5455 : ((v) & ~0x7ffff) == 0 \
5458 : ((v) & ~0x3fffff) == 0 \
5459 ? ((v) & ~0x1fffff) == 0 \
5462 : ((v) & ~0x7fffff) == 0 \
5465 : ((v) & ~0xfffffff) == 0 \
5466 ? ((v) & ~0x3ffffff) == 0 \
5467 ? ((v) & ~0x1ffffff) == 0 \
5470 : ((v) & ~0x7ffffff) == 0 \
5473 : ((v) & ~0x3fffffff) == 0 \
5474 ? ((v) & ~0x1fffffff) == 0 \
5477 : ((v) & ~0x7fffffff) == 0 \
5482 * This routine generates the least number of instructions necessary to load
5483 * an absolute expression value into a register.
5486 load_register (int reg, expressionS *ep, int dbl)
5489 expressionS hi32, lo32;
5491 if (ep->X_op != O_big)
5493 gas_assert (ep->X_op == O_constant);
5495 /* Sign-extending 32-bit constants makes their handling easier. */
5497 normalize_constant_expr (ep);
5499 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5501 /* We can handle 16 bit signed values with an addiu to
5502 $zero. No need to ever use daddiu here, since $zero and
5503 the result are always correct in 32 bit mode. */
5504 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5507 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5509 /* We can handle 16 bit unsigned values with an ori to
5511 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5514 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5516 /* 32 bit values require an lui. */
5517 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5518 if ((ep->X_add_number & 0xffff) != 0)
5519 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5524 /* The value is larger than 32 bits. */
5526 if (!dbl || HAVE_32BIT_GPRS)
5530 sprintf_vma (value, ep->X_add_number);
5531 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5532 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5536 if (ep->X_op != O_big)
5539 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5540 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5541 hi32.X_add_number &= 0xffffffff;
5543 lo32.X_add_number &= 0xffffffff;
5547 gas_assert (ep->X_add_number > 2);
5548 if (ep->X_add_number == 3)
5549 generic_bignum[3] = 0;
5550 else if (ep->X_add_number > 4)
5551 as_bad (_("Number larger than 64 bits"));
5552 lo32.X_op = O_constant;
5553 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5554 hi32.X_op = O_constant;
5555 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5558 if (hi32.X_add_number == 0)
5563 unsigned long hi, lo;
5565 if (hi32.X_add_number == (offsetT) 0xffffffff)
5567 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5569 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5572 if (lo32.X_add_number & 0x80000000)
5574 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5575 if (lo32.X_add_number & 0xffff)
5576 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5581 /* Check for 16bit shifted constant. We know that hi32 is
5582 non-zero, so start the mask on the first bit of the hi32
5587 unsigned long himask, lomask;
5591 himask = 0xffff >> (32 - shift);
5592 lomask = (0xffff << shift) & 0xffffffff;
5596 himask = 0xffff << (shift - 32);
5599 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5600 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5604 tmp.X_op = O_constant;
5606 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5607 | (lo32.X_add_number >> shift));
5609 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5610 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5611 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5612 reg, reg, (shift >= 32) ? shift - 32 : shift);
5617 while (shift <= (64 - 16));
5619 /* Find the bit number of the lowest one bit, and store the
5620 shifted value in hi/lo. */
5621 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5622 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5626 while ((lo & 1) == 0)
5631 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5637 while ((hi & 1) == 0)
5646 /* Optimize if the shifted value is a (power of 2) - 1. */
5647 if ((hi == 0 && ((lo + 1) & lo) == 0)
5648 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5650 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5655 /* This instruction will set the register to be all
5657 tmp.X_op = O_constant;
5658 tmp.X_add_number = (offsetT) -1;
5659 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5663 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5664 reg, reg, (bit >= 32) ? bit - 32 : bit);
5666 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5667 reg, reg, (shift >= 32) ? shift - 32 : shift);
5672 /* Sign extend hi32 before calling load_register, because we can
5673 generally get better code when we load a sign extended value. */
5674 if ((hi32.X_add_number & 0x80000000) != 0)
5675 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5676 load_register (reg, &hi32, 0);
5679 if ((lo32.X_add_number & 0xffff0000) == 0)
5683 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5691 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5693 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5694 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5700 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5704 mid16.X_add_number >>= 16;
5705 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5706 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5709 if ((lo32.X_add_number & 0xffff) != 0)
5710 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5714 load_delay_nop (void)
5716 if (!gpr_interlocks)
5717 macro_build (NULL, "nop", "");
5720 /* Load an address into a register. */
5723 load_address (int reg, expressionS *ep, int *used_at)
5725 if (ep->X_op != O_constant
5726 && ep->X_op != O_symbol)
5728 as_bad (_("expression too complex"));
5729 ep->X_op = O_constant;
5732 if (ep->X_op == O_constant)
5734 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5738 if (mips_pic == NO_PIC)
5740 /* If this is a reference to a GP relative symbol, we want
5741 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5743 lui $reg,<sym> (BFD_RELOC_HI16_S)
5744 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5745 If we have an addend, we always use the latter form.
5747 With 64bit address space and a usable $at we want
5748 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5749 lui $at,<sym> (BFD_RELOC_HI16_S)
5750 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5751 daddiu $at,<sym> (BFD_RELOC_LO16)
5755 If $at is already in use, we use a path which is suboptimal
5756 on superscalar processors.
5757 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5758 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5760 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5762 daddiu $reg,<sym> (BFD_RELOC_LO16)
5764 For GP relative symbols in 64bit address space we can use
5765 the same sequence as in 32bit address space. */
5766 if (HAVE_64BIT_SYMBOLS)
5768 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5769 && !nopic_need_relax (ep->X_add_symbol, 1))
5771 relax_start (ep->X_add_symbol);
5772 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5773 mips_gp_register, BFD_RELOC_GPREL16);
5777 if (*used_at == 0 && mips_opts.at)
5779 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5780 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5781 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5782 BFD_RELOC_MIPS_HIGHER);
5783 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5784 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5785 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5790 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5791 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5792 BFD_RELOC_MIPS_HIGHER);
5793 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5794 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5795 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5796 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5799 if (mips_relax.sequence)
5804 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5805 && !nopic_need_relax (ep->X_add_symbol, 1))
5807 relax_start (ep->X_add_symbol);
5808 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5809 mips_gp_register, BFD_RELOC_GPREL16);
5812 macro_build_lui (ep, reg);
5813 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5814 reg, reg, BFD_RELOC_LO16);
5815 if (mips_relax.sequence)
5819 else if (!mips_big_got)
5823 /* If this is a reference to an external symbol, we want
5824 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5826 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5828 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5829 If there is a constant, it must be added in after.
5831 If we have NewABI, we want
5832 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5833 unless we're referencing a global symbol with a non-zero
5834 offset, in which case cst must be added separately. */
5837 if (ep->X_add_number)
5839 ex.X_add_number = ep->X_add_number;
5840 ep->X_add_number = 0;
5841 relax_start (ep->X_add_symbol);
5842 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5843 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5844 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5845 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5846 ex.X_op = O_constant;
5847 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5848 reg, reg, BFD_RELOC_LO16);
5849 ep->X_add_number = ex.X_add_number;
5852 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5853 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5854 if (mips_relax.sequence)
5859 ex.X_add_number = ep->X_add_number;
5860 ep->X_add_number = 0;
5861 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5862 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5864 relax_start (ep->X_add_symbol);
5866 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5870 if (ex.X_add_number != 0)
5872 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5873 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5874 ex.X_op = O_constant;
5875 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5876 reg, reg, BFD_RELOC_LO16);
5880 else if (mips_big_got)
5884 /* This is the large GOT case. If this is a reference to an
5885 external symbol, we want
5886 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5888 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5890 Otherwise, for a reference to a local symbol in old ABI, we want
5891 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5893 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5894 If there is a constant, it must be added in after.
5896 In the NewABI, for local symbols, with or without offsets, we want:
5897 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5898 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5902 ex.X_add_number = ep->X_add_number;
5903 ep->X_add_number = 0;
5904 relax_start (ep->X_add_symbol);
5905 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5906 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5907 reg, reg, mips_gp_register);
5908 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5909 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5910 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5911 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5912 else if (ex.X_add_number)
5914 ex.X_op = O_constant;
5915 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5919 ep->X_add_number = ex.X_add_number;
5921 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5922 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5923 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5924 BFD_RELOC_MIPS_GOT_OFST);
5929 ex.X_add_number = ep->X_add_number;
5930 ep->X_add_number = 0;
5931 relax_start (ep->X_add_symbol);
5932 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5933 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5934 reg, reg, mips_gp_register);
5935 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5936 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5938 if (reg_needs_delay (mips_gp_register))
5940 /* We need a nop before loading from $gp. This special
5941 check is required because the lui which starts the main
5942 instruction stream does not refer to $gp, and so will not
5943 insert the nop which may be required. */
5944 macro_build (NULL, "nop", "");
5946 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5947 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5949 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5953 if (ex.X_add_number != 0)
5955 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5956 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5957 ex.X_op = O_constant;
5958 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5966 if (!mips_opts.at && *used_at == 1)
5967 as_bad (_("Macro used $at after \".set noat\""));
5970 /* Move the contents of register SOURCE into register DEST. */
5973 move_register (int dest, int source)
5975 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5976 instruction specifically requires a 32-bit one. */
5977 if (mips_opts.micromips
5978 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5979 macro_build (NULL, "move", "mp,mj", dest, source);
5981 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5985 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5986 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5987 The two alternatives are:
5989 Global symbol Local sybmol
5990 ------------- ------------
5991 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5993 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5995 load_got_offset emits the first instruction and add_got_offset
5996 emits the second for a 16-bit offset or add_got_offset_hilo emits
5997 a sequence to add a 32-bit offset using a scratch register. */
6000 load_got_offset (int dest, expressionS *local)
6005 global.X_add_number = 0;
6007 relax_start (local->X_add_symbol);
6008 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6009 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6011 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6012 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6017 add_got_offset (int dest, expressionS *local)
6021 global.X_op = O_constant;
6022 global.X_op_symbol = NULL;
6023 global.X_add_symbol = NULL;
6024 global.X_add_number = local->X_add_number;
6026 relax_start (local->X_add_symbol);
6027 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6028 dest, dest, BFD_RELOC_LO16);
6030 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6035 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6038 int hold_mips_optimize;
6040 global.X_op = O_constant;
6041 global.X_op_symbol = NULL;
6042 global.X_add_symbol = NULL;
6043 global.X_add_number = local->X_add_number;
6045 relax_start (local->X_add_symbol);
6046 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6048 /* Set mips_optimize around the lui instruction to avoid
6049 inserting an unnecessary nop after the lw. */
6050 hold_mips_optimize = mips_optimize;
6052 macro_build_lui (&global, tmp);
6053 mips_optimize = hold_mips_optimize;
6054 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6057 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6060 /* Emit a sequence of instructions to emulate a branch likely operation.
6061 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6062 is its complementing branch with the original condition negated.
6063 CALL is set if the original branch specified the link operation.
6064 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6066 Code like this is produced in the noreorder mode:
6071 delay slot (executed only if branch taken)
6079 delay slot (executed only if branch taken)
6082 In the reorder mode the delay slot would be filled with a nop anyway,
6083 so code produced is simply:
6088 This function is used when producing code for the microMIPS ASE that
6089 does not implement branch likely instructions in hardware. */
6092 macro_build_branch_likely (const char *br, const char *brneg,
6093 int call, expressionS *ep, const char *fmt,
6094 unsigned int sreg, unsigned int treg)
6096 int noreorder = mips_opts.noreorder;
6099 gas_assert (mips_opts.micromips);
6103 micromips_label_expr (&expr1);
6104 macro_build (&expr1, brneg, fmt, sreg, treg);
6105 macro_build (NULL, "nop", "");
6106 macro_build (ep, call ? "bal" : "b", "p");
6108 /* Set to true so that append_insn adds a label. */
6109 emit_branch_likely_macro = TRUE;
6113 macro_build (ep, br, fmt, sreg, treg);
6114 macro_build (NULL, "nop", "");
6119 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6120 the condition code tested. EP specifies the branch target. */
6123 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6150 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6153 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6154 the register tested. EP specifies the branch target. */
6157 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6159 const char *brneg = NULL;
6169 br = mips_opts.micromips ? "bgez" : "bgezl";
6173 gas_assert (mips_opts.micromips);
6182 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6189 br = mips_opts.micromips ? "blez" : "blezl";
6196 br = mips_opts.micromips ? "bltz" : "bltzl";
6200 gas_assert (mips_opts.micromips);
6208 if (mips_opts.micromips && brneg)
6209 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6211 macro_build (ep, br, "s,p", sreg);
6214 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6215 TREG as the registers tested. EP specifies the branch target. */
6218 macro_build_branch_rsrt (int type, expressionS *ep,
6219 unsigned int sreg, unsigned int treg)
6221 const char *brneg = NULL;
6233 br = mips_opts.micromips ? "beq" : "beql";
6242 br = mips_opts.micromips ? "bne" : "bnel";
6248 if (mips_opts.micromips && brneg)
6249 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6251 macro_build (ep, br, "s,t,p", sreg, treg);
6256 * This routine implements the seemingly endless macro or synthesized
6257 * instructions and addressing modes in the mips assembly language. Many
6258 * of these macros are simple and are similar to each other. These could
6259 * probably be handled by some kind of table or grammar approach instead of
6260 * this verbose method. Others are not simple macros but are more like
6261 * optimizing code generation.
6262 * One interesting optimization is when several store macros appear
6263 * consecutively that would load AT with the upper half of the same address.
6264 * The ensuing load upper instructions are ommited. This implies some kind
6265 * of global optimization. We currently only optimize within a single macro.
6266 * For many of the load and store macros if the address is specified as a
6267 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6268 * first load register 'at' with zero and use it as the base register. The
6269 * mips assembler simply uses register $zero. Just one tiny optimization
6273 macro (struct mips_cl_insn *ip)
6275 unsigned int treg, sreg, dreg, breg;
6276 unsigned int tempreg;
6279 expressionS label_expr;
6298 bfd_reloc_code_real_type r;
6299 int hold_mips_optimize;
6301 gas_assert (! mips_opts.mips16);
6303 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6304 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6305 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6306 mask = ip->insn_mo->mask;
6308 label_expr.X_op = O_constant;
6309 label_expr.X_op_symbol = NULL;
6310 label_expr.X_add_symbol = NULL;
6311 label_expr.X_add_number = 0;
6313 expr1.X_op = O_constant;
6314 expr1.X_op_symbol = NULL;
6315 expr1.X_add_symbol = NULL;
6316 expr1.X_add_number = 1;
6331 if (mips_opts.micromips)
6332 micromips_label_expr (&label_expr);
6334 label_expr.X_add_number = 8;
6335 macro_build (&label_expr, "bgez", "s,p", sreg);
6337 macro_build (NULL, "nop", "");
6339 move_register (dreg, sreg);
6340 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6341 if (mips_opts.micromips)
6342 micromips_add_label ();
6359 if (!mips_opts.micromips)
6361 if (imm_expr.X_op == O_constant
6362 && imm_expr.X_add_number >= -0x200
6363 && imm_expr.X_add_number < 0x200)
6365 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6374 if (imm_expr.X_op == O_constant
6375 && imm_expr.X_add_number >= -0x8000
6376 && imm_expr.X_add_number < 0x8000)
6378 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6383 load_register (AT, &imm_expr, dbl);
6384 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6403 if (imm_expr.X_op == O_constant
6404 && imm_expr.X_add_number >= 0
6405 && imm_expr.X_add_number < 0x10000)
6407 if (mask != M_NOR_I)
6408 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6411 macro_build (&imm_expr, "ori", "t,r,i",
6412 treg, sreg, BFD_RELOC_LO16);
6413 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6419 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6420 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6424 switch (imm_expr.X_add_number)
6427 macro_build (NULL, "nop", "");
6430 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6434 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6435 (int) imm_expr.X_add_number);
6438 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6439 (unsigned long) imm_expr.X_add_number);
6448 gas_assert (mips_opts.micromips);
6449 macro_build_branch_ccl (mask, &offset_expr,
6450 EXTRACT_OPERAND (1, BCC, *ip));
6457 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6463 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6468 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6475 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6477 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6481 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6482 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6483 &offset_expr, AT, ZERO);
6493 macro_build_branch_rs (mask, &offset_expr, sreg);
6499 /* Check for > max integer. */
6500 maxnum = 0x7fffffff;
6501 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6508 if (imm_expr.X_op == O_constant
6509 && imm_expr.X_add_number >= maxnum
6510 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6513 /* Result is always false. */
6515 macro_build (NULL, "nop", "");
6517 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6520 if (imm_expr.X_op != O_constant)
6521 as_bad (_("Unsupported large constant"));
6522 ++imm_expr.X_add_number;
6526 if (mask == M_BGEL_I)
6528 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6530 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6531 &offset_expr, sreg);
6534 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6536 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6537 &offset_expr, sreg);
6540 maxnum = 0x7fffffff;
6541 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6548 maxnum = - maxnum - 1;
6549 if (imm_expr.X_op == O_constant
6550 && imm_expr.X_add_number <= maxnum
6551 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6554 /* result is always true */
6555 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6556 macro_build (&offset_expr, "b", "p");
6561 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6562 &offset_expr, AT, ZERO);
6571 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6572 &offset_expr, ZERO, treg);
6576 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6577 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6578 &offset_expr, AT, ZERO);
6587 && imm_expr.X_op == O_constant
6588 && imm_expr.X_add_number == -1))
6590 if (imm_expr.X_op != O_constant)
6591 as_bad (_("Unsupported large constant"));
6592 ++imm_expr.X_add_number;
6596 if (mask == M_BGEUL_I)
6598 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6600 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6601 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6602 &offset_expr, sreg, ZERO);
6607 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6608 &offset_expr, AT, ZERO);
6616 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6618 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6622 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6623 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6624 &offset_expr, AT, ZERO);
6632 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6633 &offset_expr, sreg, ZERO);
6639 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6640 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6641 &offset_expr, AT, ZERO);
6649 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6651 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6655 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6656 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6657 &offset_expr, AT, ZERO);
6664 maxnum = 0x7fffffff;
6665 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6672 if (imm_expr.X_op == O_constant
6673 && imm_expr.X_add_number >= maxnum
6674 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6676 if (imm_expr.X_op != O_constant)
6677 as_bad (_("Unsupported large constant"));
6678 ++imm_expr.X_add_number;
6682 if (mask == M_BLTL_I)
6684 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6685 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6686 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6687 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6692 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6693 &offset_expr, AT, ZERO);
6701 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6702 &offset_expr, sreg, ZERO);
6708 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6709 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6710 &offset_expr, AT, ZERO);
6719 && imm_expr.X_op == O_constant
6720 && imm_expr.X_add_number == -1))
6722 if (imm_expr.X_op != O_constant)
6723 as_bad (_("Unsupported large constant"));
6724 ++imm_expr.X_add_number;
6728 if (mask == M_BLTUL_I)
6730 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6732 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6733 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6734 &offset_expr, sreg, ZERO);
6739 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6740 &offset_expr, AT, ZERO);
6748 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6750 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6754 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6755 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6756 &offset_expr, AT, ZERO);
6766 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6767 &offset_expr, ZERO, treg);
6771 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6772 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6773 &offset_expr, AT, ZERO);
6779 /* Use unsigned arithmetic. */
6783 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6785 as_bad (_("Unsupported large constant"));
6790 pos = imm_expr.X_add_number;
6791 size = imm2_expr.X_add_number;
6796 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6799 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6801 as_bad (_("Improper extract size (%lu, position %lu)"),
6802 (unsigned long) size, (unsigned long) pos);
6806 if (size <= 32 && pos < 32)
6811 else if (size <= 32)
6821 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6828 /* Use unsigned arithmetic. */
6832 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6834 as_bad (_("Unsupported large constant"));
6839 pos = imm_expr.X_add_number;
6840 size = imm2_expr.X_add_number;
6845 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6848 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6850 as_bad (_("Improper insert size (%lu, position %lu)"),
6851 (unsigned long) size, (unsigned long) pos);
6855 if (pos < 32 && (pos + size - 1) < 32)
6870 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6871 (int) (pos + size - 1));
6887 as_warn (_("Divide by zero."));
6889 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6891 macro_build (NULL, "break", BRK_FMT, 7);
6898 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6899 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6903 if (mips_opts.micromips)
6904 micromips_label_expr (&label_expr);
6906 label_expr.X_add_number = 8;
6907 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6908 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6909 macro_build (NULL, "break", BRK_FMT, 7);
6910 if (mips_opts.micromips)
6911 micromips_add_label ();
6913 expr1.X_add_number = -1;
6915 load_register (AT, &expr1, dbl);
6916 if (mips_opts.micromips)
6917 micromips_label_expr (&label_expr);
6919 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6920 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6923 expr1.X_add_number = 1;
6924 load_register (AT, &expr1, dbl);
6925 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6929 expr1.X_add_number = 0x80000000;
6930 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6934 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6935 /* We want to close the noreorder block as soon as possible, so
6936 that later insns are available for delay slot filling. */
6941 if (mips_opts.micromips)
6942 micromips_label_expr (&label_expr);
6944 label_expr.X_add_number = 8;
6945 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6946 macro_build (NULL, "nop", "");
6948 /* We want to close the noreorder block as soon as possible, so
6949 that later insns are available for delay slot filling. */
6952 macro_build (NULL, "break", BRK_FMT, 6);
6954 if (mips_opts.micromips)
6955 micromips_add_label ();
6956 macro_build (NULL, s, MFHL_FMT, dreg);
6995 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6997 as_warn (_("Divide by zero."));
6999 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7001 macro_build (NULL, "break", BRK_FMT, 7);
7004 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7006 if (strcmp (s2, "mflo") == 0)
7007 move_register (dreg, sreg);
7009 move_register (dreg, ZERO);
7012 if (imm_expr.X_op == O_constant
7013 && imm_expr.X_add_number == -1
7014 && s[strlen (s) - 1] != 'u')
7016 if (strcmp (s2, "mflo") == 0)
7018 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7021 move_register (dreg, ZERO);
7026 load_register (AT, &imm_expr, dbl);
7027 macro_build (NULL, s, "z,s,t", sreg, AT);
7028 macro_build (NULL, s2, MFHL_FMT, dreg);
7050 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7051 macro_build (NULL, s, "z,s,t", sreg, treg);
7052 /* We want to close the noreorder block as soon as possible, so
7053 that later insns are available for delay slot filling. */
7058 if (mips_opts.micromips)
7059 micromips_label_expr (&label_expr);
7061 label_expr.X_add_number = 8;
7062 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7063 macro_build (NULL, s, "z,s,t", sreg, treg);
7065 /* We want to close the noreorder block as soon as possible, so
7066 that later insns are available for delay slot filling. */
7068 macro_build (NULL, "break", BRK_FMT, 7);
7069 if (mips_opts.micromips)
7070 micromips_add_label ();
7072 macro_build (NULL, s2, MFHL_FMT, dreg);
7084 /* Load the address of a symbol into a register. If breg is not
7085 zero, we then add a base register to it. */
7087 if (dbl && HAVE_32BIT_GPRS)
7088 as_warn (_("dla used to load 32-bit register"));
7090 if (!dbl && HAVE_64BIT_OBJECTS)
7091 as_warn (_("la used to load 64-bit address"));
7093 if (offset_expr.X_op == O_constant
7094 && offset_expr.X_add_number >= -0x8000
7095 && offset_expr.X_add_number < 0x8000)
7097 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7098 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7102 if (mips_opts.at && (treg == breg))
7112 if (offset_expr.X_op != O_symbol
7113 && offset_expr.X_op != O_constant)
7115 as_bad (_("Expression too complex"));
7116 offset_expr.X_op = O_constant;
7119 if (offset_expr.X_op == O_constant)
7120 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7121 else if (mips_pic == NO_PIC)
7123 /* If this is a reference to a GP relative symbol, we want
7124 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7126 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7127 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7128 If we have a constant, we need two instructions anyhow,
7129 so we may as well always use the latter form.
7131 With 64bit address space and a usable $at we want
7132 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7133 lui $at,<sym> (BFD_RELOC_HI16_S)
7134 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7135 daddiu $at,<sym> (BFD_RELOC_LO16)
7137 daddu $tempreg,$tempreg,$at
7139 If $at is already in use, we use a path which is suboptimal
7140 on superscalar processors.
7141 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7142 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7144 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7146 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7148 For GP relative symbols in 64bit address space we can use
7149 the same sequence as in 32bit address space. */
7150 if (HAVE_64BIT_SYMBOLS)
7152 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7153 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7155 relax_start (offset_expr.X_add_symbol);
7156 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7157 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7161 if (used_at == 0 && mips_opts.at)
7163 macro_build (&offset_expr, "lui", LUI_FMT,
7164 tempreg, BFD_RELOC_MIPS_HIGHEST);
7165 macro_build (&offset_expr, "lui", LUI_FMT,
7166 AT, BFD_RELOC_HI16_S);
7167 macro_build (&offset_expr, "daddiu", "t,r,j",
7168 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7169 macro_build (&offset_expr, "daddiu", "t,r,j",
7170 AT, AT, BFD_RELOC_LO16);
7171 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7172 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7177 macro_build (&offset_expr, "lui", LUI_FMT,
7178 tempreg, BFD_RELOC_MIPS_HIGHEST);
7179 macro_build (&offset_expr, "daddiu", "t,r,j",
7180 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7181 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7182 macro_build (&offset_expr, "daddiu", "t,r,j",
7183 tempreg, tempreg, BFD_RELOC_HI16_S);
7184 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7185 macro_build (&offset_expr, "daddiu", "t,r,j",
7186 tempreg, tempreg, BFD_RELOC_LO16);
7189 if (mips_relax.sequence)
7194 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7195 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7197 relax_start (offset_expr.X_add_symbol);
7198 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7199 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7202 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7203 as_bad (_("Offset too large"));
7204 macro_build_lui (&offset_expr, tempreg);
7205 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7206 tempreg, tempreg, BFD_RELOC_LO16);
7207 if (mips_relax.sequence)
7211 else if (!mips_big_got && !HAVE_NEWABI)
7213 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7215 /* If this is a reference to an external symbol, and there
7216 is no constant, we want
7217 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7218 or for lca or if tempreg is PIC_CALL_REG
7219 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7220 For a local symbol, we want
7221 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7223 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7225 If we have a small constant, and this is a reference to
7226 an external symbol, we want
7227 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7229 addiu $tempreg,$tempreg,<constant>
7230 For a local symbol, we want the same instruction
7231 sequence, but we output a BFD_RELOC_LO16 reloc on the
7234 If we have a large constant, and this is a reference to
7235 an external symbol, we want
7236 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7237 lui $at,<hiconstant>
7238 addiu $at,$at,<loconstant>
7239 addu $tempreg,$tempreg,$at
7240 For a local symbol, we want the same instruction
7241 sequence, but we output a BFD_RELOC_LO16 reloc on the
7245 if (offset_expr.X_add_number == 0)
7247 if (mips_pic == SVR4_PIC
7249 && (call || tempreg == PIC_CALL_REG))
7250 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7252 relax_start (offset_expr.X_add_symbol);
7253 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7254 lw_reloc_type, mips_gp_register);
7257 /* We're going to put in an addu instruction using
7258 tempreg, so we may as well insert the nop right
7263 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7264 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7266 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7267 tempreg, tempreg, BFD_RELOC_LO16);
7269 /* FIXME: If breg == 0, and the next instruction uses
7270 $tempreg, then if this variant case is used an extra
7271 nop will be generated. */
7273 else if (offset_expr.X_add_number >= -0x8000
7274 && offset_expr.X_add_number < 0x8000)
7276 load_got_offset (tempreg, &offset_expr);
7278 add_got_offset (tempreg, &offset_expr);
7282 expr1.X_add_number = offset_expr.X_add_number;
7283 offset_expr.X_add_number =
7284 SEXT_16BIT (offset_expr.X_add_number);
7285 load_got_offset (tempreg, &offset_expr);
7286 offset_expr.X_add_number = expr1.X_add_number;
7287 /* If we are going to add in a base register, and the
7288 target register and the base register are the same,
7289 then we are using AT as a temporary register. Since
7290 we want to load the constant into AT, we add our
7291 current AT (from the global offset table) and the
7292 register into the register now, and pretend we were
7293 not using a base register. */
7297 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7302 add_got_offset_hilo (tempreg, &offset_expr, AT);
7306 else if (!mips_big_got && HAVE_NEWABI)
7308 int add_breg_early = 0;
7310 /* If this is a reference to an external, and there is no
7311 constant, or local symbol (*), with or without a
7313 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7314 or for lca or if tempreg is PIC_CALL_REG
7315 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7317 If we have a small constant, and this is a reference to
7318 an external symbol, we want
7319 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7320 addiu $tempreg,$tempreg,<constant>
7322 If we have a large constant, and this is a reference to
7323 an external symbol, we want
7324 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7325 lui $at,<hiconstant>
7326 addiu $at,$at,<loconstant>
7327 addu $tempreg,$tempreg,$at
7329 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7330 local symbols, even though it introduces an additional
7333 if (offset_expr.X_add_number)
7335 expr1.X_add_number = offset_expr.X_add_number;
7336 offset_expr.X_add_number = 0;
7338 relax_start (offset_expr.X_add_symbol);
7339 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7340 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7342 if (expr1.X_add_number >= -0x8000
7343 && expr1.X_add_number < 0x8000)
7345 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7346 tempreg, tempreg, BFD_RELOC_LO16);
7348 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7350 /* If we are going to add in a base register, and the
7351 target register and the base register are the same,
7352 then we are using AT as a temporary register. Since
7353 we want to load the constant into AT, we add our
7354 current AT (from the global offset table) and the
7355 register into the register now, and pretend we were
7356 not using a base register. */
7361 gas_assert (tempreg == AT);
7362 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7368 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7369 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7375 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7378 offset_expr.X_add_number = expr1.X_add_number;
7380 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7381 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7384 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7385 treg, tempreg, breg);
7391 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7393 relax_start (offset_expr.X_add_symbol);
7394 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7395 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7397 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7398 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7403 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7404 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7407 else if (mips_big_got && !HAVE_NEWABI)
7410 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7411 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7412 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7414 /* This is the large GOT case. If this is a reference to an
7415 external symbol, and there is no constant, we want
7416 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7417 addu $tempreg,$tempreg,$gp
7418 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7419 or for lca or if tempreg is PIC_CALL_REG
7420 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7421 addu $tempreg,$tempreg,$gp
7422 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7423 For a local symbol, we want
7424 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7426 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7428 If we have a small constant, and this is a reference to
7429 an external symbol, we want
7430 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7431 addu $tempreg,$tempreg,$gp
7432 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7434 addiu $tempreg,$tempreg,<constant>
7435 For a local symbol, we want
7436 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7438 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7440 If we have a large constant, and this is a reference to
7441 an external symbol, we want
7442 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7443 addu $tempreg,$tempreg,$gp
7444 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7445 lui $at,<hiconstant>
7446 addiu $at,$at,<loconstant>
7447 addu $tempreg,$tempreg,$at
7448 For a local symbol, we want
7449 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7450 lui $at,<hiconstant>
7451 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7452 addu $tempreg,$tempreg,$at
7455 expr1.X_add_number = offset_expr.X_add_number;
7456 offset_expr.X_add_number = 0;
7457 relax_start (offset_expr.X_add_symbol);
7458 gpdelay = reg_needs_delay (mips_gp_register);
7459 if (expr1.X_add_number == 0 && breg == 0
7460 && (call || tempreg == PIC_CALL_REG))
7462 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7463 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7465 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7466 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7467 tempreg, tempreg, mips_gp_register);
7468 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7469 tempreg, lw_reloc_type, tempreg);
7470 if (expr1.X_add_number == 0)
7474 /* We're going to put in an addu instruction using
7475 tempreg, so we may as well insert the nop right
7480 else if (expr1.X_add_number >= -0x8000
7481 && expr1.X_add_number < 0x8000)
7484 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7485 tempreg, tempreg, BFD_RELOC_LO16);
7489 /* If we are going to add in a base register, and the
7490 target register and the base register are the same,
7491 then we are using AT as a temporary register. Since
7492 we want to load the constant into AT, we add our
7493 current AT (from the global offset table) and the
7494 register into the register now, and pretend we were
7495 not using a base register. */
7500 gas_assert (tempreg == AT);
7502 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7507 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7508 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7512 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7517 /* This is needed because this instruction uses $gp, but
7518 the first instruction on the main stream does not. */
7519 macro_build (NULL, "nop", "");
7522 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7523 local_reloc_type, mips_gp_register);
7524 if (expr1.X_add_number >= -0x8000
7525 && expr1.X_add_number < 0x8000)
7528 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7529 tempreg, tempreg, BFD_RELOC_LO16);
7530 /* FIXME: If add_number is 0, and there was no base
7531 register, the external symbol case ended with a load,
7532 so if the symbol turns out to not be external, and
7533 the next instruction uses tempreg, an unnecessary nop
7534 will be inserted. */
7540 /* We must add in the base register now, as in the
7541 external symbol case. */
7542 gas_assert (tempreg == AT);
7544 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7547 /* We set breg to 0 because we have arranged to add
7548 it in in both cases. */
7552 macro_build_lui (&expr1, AT);
7553 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7554 AT, AT, BFD_RELOC_LO16);
7555 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7556 tempreg, tempreg, AT);
7561 else if (mips_big_got && HAVE_NEWABI)
7563 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7564 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7565 int add_breg_early = 0;
7567 /* This is the large GOT case. If this is a reference to an
7568 external symbol, and there is no constant, we want
7569 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7570 add $tempreg,$tempreg,$gp
7571 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7572 or for lca or if tempreg is PIC_CALL_REG
7573 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7574 add $tempreg,$tempreg,$gp
7575 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7577 If we have a small constant, and this is a reference to
7578 an external symbol, we want
7579 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7580 add $tempreg,$tempreg,$gp
7581 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7582 addi $tempreg,$tempreg,<constant>
7584 If we have a large constant, and this is a reference to
7585 an external symbol, we want
7586 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7587 addu $tempreg,$tempreg,$gp
7588 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7589 lui $at,<hiconstant>
7590 addi $at,$at,<loconstant>
7591 add $tempreg,$tempreg,$at
7593 If we have NewABI, and we know it's a local symbol, we want
7594 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7595 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7596 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7598 relax_start (offset_expr.X_add_symbol);
7600 expr1.X_add_number = offset_expr.X_add_number;
7601 offset_expr.X_add_number = 0;
7603 if (expr1.X_add_number == 0 && breg == 0
7604 && (call || tempreg == PIC_CALL_REG))
7606 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7607 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7609 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7610 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7611 tempreg, tempreg, mips_gp_register);
7612 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7613 tempreg, lw_reloc_type, tempreg);
7615 if (expr1.X_add_number == 0)
7617 else if (expr1.X_add_number >= -0x8000
7618 && expr1.X_add_number < 0x8000)
7620 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7621 tempreg, tempreg, BFD_RELOC_LO16);
7623 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7625 /* If we are going to add in a base register, and the
7626 target register and the base register are the same,
7627 then we are using AT as a temporary register. Since
7628 we want to load the constant into AT, we add our
7629 current AT (from the global offset table) and the
7630 register into the register now, and pretend we were
7631 not using a base register. */
7636 gas_assert (tempreg == AT);
7637 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7643 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7644 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7649 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7652 offset_expr.X_add_number = expr1.X_add_number;
7653 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7654 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7655 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7656 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7660 treg, tempreg, breg);
7670 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7674 gas_assert (!mips_opts.micromips);
7676 unsigned long temp = (treg << 16) | (0x01);
7677 macro_build (NULL, "c2", "C", temp);
7682 gas_assert (!mips_opts.micromips);
7684 unsigned long temp = (0x02);
7685 macro_build (NULL, "c2", "C", temp);
7690 gas_assert (!mips_opts.micromips);
7692 unsigned long temp = (treg << 16) | (0x02);
7693 macro_build (NULL, "c2", "C", temp);
7698 gas_assert (!mips_opts.micromips);
7699 macro_build (NULL, "c2", "C", 3);
7703 gas_assert (!mips_opts.micromips);
7705 unsigned long temp = (treg << 16) | 0x03;
7706 macro_build (NULL, "c2", "C", temp);
7711 /* The j instruction may not be used in PIC code, since it
7712 requires an absolute address. We convert it to a b
7714 if (mips_pic == NO_PIC)
7715 macro_build (&offset_expr, "j", "a");
7717 macro_build (&offset_expr, "b", "p");
7720 /* The jal instructions must be handled as macros because when
7721 generating PIC code they expand to multi-instruction
7722 sequences. Normally they are simple instructions. */
7727 gas_assert (mips_opts.micromips);
7735 if (mips_pic == NO_PIC)
7737 s = jals ? "jalrs" : "jalr";
7738 if (mips_opts.micromips && dreg == RA)
7739 macro_build (NULL, s, "mj", sreg);
7741 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7745 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7746 && mips_cprestore_offset >= 0);
7748 if (sreg != PIC_CALL_REG)
7749 as_warn (_("MIPS PIC call to register other than $25"));
7751 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7752 ? "jalrs" : "jalr");
7753 if (mips_opts.micromips && dreg == RA)
7754 macro_build (NULL, s, "mj", sreg);
7756 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7757 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7759 if (mips_cprestore_offset < 0)
7760 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7763 if (!mips_frame_reg_valid)
7765 as_warn (_("No .frame pseudo-op used in PIC code"));
7766 /* Quiet this warning. */
7767 mips_frame_reg_valid = 1;
7769 if (!mips_cprestore_valid)
7771 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7772 /* Quiet this warning. */
7773 mips_cprestore_valid = 1;
7775 if (mips_opts.noreorder)
7776 macro_build (NULL, "nop", "");
7777 expr1.X_add_number = mips_cprestore_offset;
7778 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7781 HAVE_64BIT_ADDRESSES);
7789 gas_assert (mips_opts.micromips);
7793 if (mips_pic == NO_PIC)
7794 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7795 else if (mips_pic == SVR4_PIC)
7797 /* If this is a reference to an external symbol, and we are
7798 using a small GOT, we want
7799 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7803 lw $gp,cprestore($sp)
7804 The cprestore value is set using the .cprestore
7805 pseudo-op. If we are using a big GOT, we want
7806 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7808 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7812 lw $gp,cprestore($sp)
7813 If the symbol is not external, we want
7814 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7816 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7819 lw $gp,cprestore($sp)
7821 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7822 sequences above, minus nops, unless the symbol is local,
7823 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7829 relax_start (offset_expr.X_add_symbol);
7830 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7831 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7834 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7835 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7841 relax_start (offset_expr.X_add_symbol);
7842 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7843 BFD_RELOC_MIPS_CALL_HI16);
7844 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7845 PIC_CALL_REG, mips_gp_register);
7846 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7847 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7850 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7851 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7853 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7854 PIC_CALL_REG, PIC_CALL_REG,
7855 BFD_RELOC_MIPS_GOT_OFST);
7859 macro_build_jalr (&offset_expr, 0);
7863 relax_start (offset_expr.X_add_symbol);
7866 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7867 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7876 gpdelay = reg_needs_delay (mips_gp_register);
7877 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7878 BFD_RELOC_MIPS_CALL_HI16);
7879 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7880 PIC_CALL_REG, mips_gp_register);
7881 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7882 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7887 macro_build (NULL, "nop", "");
7889 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7890 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7893 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7894 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7896 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7898 if (mips_cprestore_offset < 0)
7899 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7902 if (!mips_frame_reg_valid)
7904 as_warn (_("No .frame pseudo-op used in PIC code"));
7905 /* Quiet this warning. */
7906 mips_frame_reg_valid = 1;
7908 if (!mips_cprestore_valid)
7910 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7911 /* Quiet this warning. */
7912 mips_cprestore_valid = 1;
7914 if (mips_opts.noreorder)
7915 macro_build (NULL, "nop", "");
7916 expr1.X_add_number = mips_cprestore_offset;
7917 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7920 HAVE_64BIT_ADDRESSES);
7924 else if (mips_pic == VXWORKS_PIC)
7925 as_bad (_("Non-PIC jump used in PIC library"));
7935 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7943 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7974 gas_assert (!mips_opts.micromips);
7977 /* Itbl support may require additional care here. */
7984 /* Itbl support may require additional care here. */
7992 off12 = mips_opts.micromips;
7993 /* Itbl support may require additional care here. */
7998 gas_assert (!mips_opts.micromips);
8001 /* Itbl support may require additional care here. */
8009 off12 = mips_opts.micromips;
8016 off12 = mips_opts.micromips;
8022 /* Itbl support may require additional care here. */
8030 off12 = mips_opts.micromips;
8031 /* Itbl support may require additional care here. */
8038 /* Itbl support may require additional care here. */
8046 off12 = mips_opts.micromips;
8053 off12 = mips_opts.micromips;
8060 off12 = mips_opts.micromips;
8067 off12 = mips_opts.micromips;
8074 off12 = mips_opts.micromips;
8079 gas_assert (mips_opts.micromips);
8088 gas_assert (mips_opts.micromips);
8097 gas_assert (mips_opts.micromips);
8105 gas_assert (mips_opts.micromips);
8112 if (breg == treg + lp)
8115 tempreg = treg + lp;
8135 gas_assert (!mips_opts.micromips);
8138 /* Itbl support may require additional care here. */
8145 /* Itbl support may require additional care here. */
8153 off12 = mips_opts.micromips;
8154 /* Itbl support may require additional care here. */
8159 gas_assert (!mips_opts.micromips);
8162 /* Itbl support may require additional care here. */
8170 off12 = mips_opts.micromips;
8177 off12 = mips_opts.micromips;
8184 off12 = mips_opts.micromips;
8191 off12 = mips_opts.micromips;
8197 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8198 off12 = mips_opts.micromips;
8204 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8205 off12 = mips_opts.micromips;
8212 /* Itbl support may require additional care here. */
8219 off12 = mips_opts.micromips;
8220 /* Itbl support may require additional care here. */
8225 gas_assert (!mips_opts.micromips);
8228 /* Itbl support may require additional care here. */
8236 off12 = mips_opts.micromips;
8243 off12 = mips_opts.micromips;
8248 gas_assert (mips_opts.micromips);
8256 gas_assert (mips_opts.micromips);
8264 gas_assert (mips_opts.micromips);
8272 gas_assert (mips_opts.micromips);
8281 if (offset_expr.X_op != O_constant
8282 && offset_expr.X_op != O_symbol)
8284 as_bad (_("Expression too complex"));
8285 offset_expr.X_op = O_constant;
8288 if (HAVE_32BIT_ADDRESSES
8289 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8293 sprintf_vma (value, offset_expr.X_add_number);
8294 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8297 /* A constant expression in PIC code can be handled just as it
8298 is in non PIC code. */
8299 if (offset_expr.X_op == O_constant)
8303 expr1.X_add_number = offset_expr.X_add_number;
8304 normalize_address_expr (&expr1);
8305 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8307 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8308 & ~(bfd_vma) 0xffff);
8311 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8313 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8314 & ~(bfd_vma) 0xfff);
8319 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8321 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8322 tempreg, tempreg, breg);
8327 if (offset_expr.X_add_number == 0)
8330 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8331 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8332 macro_build (NULL, s, fmt, treg, tempreg);
8335 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8337 macro_build (NULL, s, fmt,
8338 treg, (unsigned long) offset_expr.X_add_number, breg);
8340 else if (off12 || off0)
8342 /* A 12-bit or 0-bit offset field is too narrow to be used
8343 for a low-part relocation, so load the whole address into
8344 the auxillary register. In the case of "A(b)" addresses,
8345 we first load absolute address "A" into the register and
8346 then add base register "b". In the case of "o(b)" addresses,
8347 we simply need to add 16-bit offset "o" to base register "b", and
8348 offset_reloc already contains the relocations associated
8352 load_address (tempreg, &offset_expr, &used_at);
8354 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8355 tempreg, tempreg, breg);
8358 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8360 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8361 expr1.X_add_number = 0;
8363 macro_build (NULL, s, fmt, treg, tempreg);
8365 macro_build (NULL, s, fmt,
8366 treg, (unsigned long) expr1.X_add_number, tempreg);
8368 else if (mips_pic == NO_PIC)
8370 /* If this is a reference to a GP relative symbol, and there
8371 is no base register, we want
8372 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8373 Otherwise, if there is no base register, we want
8374 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8375 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8376 If we have a constant, we need two instructions anyhow,
8377 so we always use the latter form.
8379 If we have a base register, and this is a reference to a
8380 GP relative symbol, we want
8381 addu $tempreg,$breg,$gp
8382 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8384 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8385 addu $tempreg,$tempreg,$breg
8386 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8387 With a constant we always use the latter case.
8389 With 64bit address space and no base register and $at usable,
8391 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8392 lui $at,<sym> (BFD_RELOC_HI16_S)
8393 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8396 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8397 If we have a base register, we want
8398 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8399 lui $at,<sym> (BFD_RELOC_HI16_S)
8400 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8404 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8406 Without $at we can't generate the optimal path for superscalar
8407 processors here since this would require two temporary registers.
8408 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8409 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8411 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8413 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8414 If we have a base register, we want
8415 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8416 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8418 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8420 daddu $tempreg,$tempreg,$breg
8421 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8423 For GP relative symbols in 64bit address space we can use
8424 the same sequence as in 32bit address space. */
8425 if (HAVE_64BIT_SYMBOLS)
8427 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8428 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8430 relax_start (offset_expr.X_add_symbol);
8433 macro_build (&offset_expr, s, fmt, treg,
8434 BFD_RELOC_GPREL16, mips_gp_register);
8438 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8439 tempreg, breg, mips_gp_register);
8440 macro_build (&offset_expr, s, fmt, treg,
8441 BFD_RELOC_GPREL16, tempreg);
8446 if (used_at == 0 && mips_opts.at)
8448 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8449 BFD_RELOC_MIPS_HIGHEST);
8450 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8452 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8453 tempreg, BFD_RELOC_MIPS_HIGHER);
8455 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8456 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8457 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8458 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8464 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8465 BFD_RELOC_MIPS_HIGHEST);
8466 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8467 tempreg, BFD_RELOC_MIPS_HIGHER);
8468 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8469 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8470 tempreg, BFD_RELOC_HI16_S);
8471 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8473 macro_build (NULL, "daddu", "d,v,t",
8474 tempreg, tempreg, breg);
8475 macro_build (&offset_expr, s, fmt, treg,
8476 BFD_RELOC_LO16, tempreg);
8479 if (mips_relax.sequence)
8486 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8487 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8489 relax_start (offset_expr.X_add_symbol);
8490 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8494 macro_build_lui (&offset_expr, tempreg);
8495 macro_build (&offset_expr, s, fmt, treg,
8496 BFD_RELOC_LO16, tempreg);
8497 if (mips_relax.sequence)
8502 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8503 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8505 relax_start (offset_expr.X_add_symbol);
8506 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8507 tempreg, breg, mips_gp_register);
8508 macro_build (&offset_expr, s, fmt, treg,
8509 BFD_RELOC_GPREL16, tempreg);
8512 macro_build_lui (&offset_expr, tempreg);
8513 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8514 tempreg, tempreg, breg);
8515 macro_build (&offset_expr, s, fmt, treg,
8516 BFD_RELOC_LO16, tempreg);
8517 if (mips_relax.sequence)
8521 else if (!mips_big_got)
8523 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8525 /* If this is a reference to an external symbol, we want
8526 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8528 <op> $treg,0($tempreg)
8530 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8532 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8533 <op> $treg,0($tempreg)
8536 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8537 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8539 If there is a base register, we add it to $tempreg before
8540 the <op>. If there is a constant, we stick it in the
8541 <op> instruction. We don't handle constants larger than
8542 16 bits, because we have no way to load the upper 16 bits
8543 (actually, we could handle them for the subset of cases
8544 in which we are not using $at). */
8545 gas_assert (offset_expr.X_op == O_symbol);
8548 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8549 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8551 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8552 tempreg, tempreg, breg);
8553 macro_build (&offset_expr, s, fmt, treg,
8554 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8557 expr1.X_add_number = offset_expr.X_add_number;
8558 offset_expr.X_add_number = 0;
8559 if (expr1.X_add_number < -0x8000
8560 || expr1.X_add_number >= 0x8000)
8561 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8562 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8563 lw_reloc_type, mips_gp_register);
8565 relax_start (offset_expr.X_add_symbol);
8567 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8568 tempreg, BFD_RELOC_LO16);
8571 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8572 tempreg, tempreg, breg);
8573 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8575 else if (mips_big_got && !HAVE_NEWABI)
8579 /* If this is a reference to an external symbol, we want
8580 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8581 addu $tempreg,$tempreg,$gp
8582 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8583 <op> $treg,0($tempreg)
8585 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8587 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8588 <op> $treg,0($tempreg)
8589 If there is a base register, we add it to $tempreg before
8590 the <op>. If there is a constant, we stick it in the
8591 <op> instruction. We don't handle constants larger than
8592 16 bits, because we have no way to load the upper 16 bits
8593 (actually, we could handle them for the subset of cases
8594 in which we are not using $at). */
8595 gas_assert (offset_expr.X_op == O_symbol);
8596 expr1.X_add_number = offset_expr.X_add_number;
8597 offset_expr.X_add_number = 0;
8598 if (expr1.X_add_number < -0x8000
8599 || expr1.X_add_number >= 0x8000)
8600 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8601 gpdelay = reg_needs_delay (mips_gp_register);
8602 relax_start (offset_expr.X_add_symbol);
8603 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8604 BFD_RELOC_MIPS_GOT_HI16);
8605 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8607 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8608 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8611 macro_build (NULL, "nop", "");
8612 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8613 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8615 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8616 tempreg, BFD_RELOC_LO16);
8620 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8621 tempreg, tempreg, breg);
8622 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8624 else if (mips_big_got && HAVE_NEWABI)
8626 /* If this is a reference to an external symbol, we want
8627 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8628 add $tempreg,$tempreg,$gp
8629 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8630 <op> $treg,<ofst>($tempreg)
8631 Otherwise, for local symbols, we want:
8632 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8633 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8634 gas_assert (offset_expr.X_op == O_symbol);
8635 expr1.X_add_number = offset_expr.X_add_number;
8636 offset_expr.X_add_number = 0;
8637 if (expr1.X_add_number < -0x8000
8638 || expr1.X_add_number >= 0x8000)
8639 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8640 relax_start (offset_expr.X_add_symbol);
8641 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8642 BFD_RELOC_MIPS_GOT_HI16);
8643 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8645 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8646 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8648 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8649 tempreg, tempreg, breg);
8650 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8653 offset_expr.X_add_number = expr1.X_add_number;
8654 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8655 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8657 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8658 tempreg, tempreg, breg);
8659 macro_build (&offset_expr, s, fmt, treg,
8660 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8670 load_register (treg, &imm_expr, 0);
8674 load_register (treg, &imm_expr, 1);
8678 if (imm_expr.X_op == O_constant)
8681 load_register (AT, &imm_expr, 0);
8682 macro_build (NULL, "mtc1", "t,G", AT, treg);
8687 gas_assert (offset_expr.X_op == O_symbol
8688 && strcmp (segment_name (S_GET_SEGMENT
8689 (offset_expr.X_add_symbol)),
8691 && offset_expr.X_add_number == 0);
8692 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8693 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8698 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8699 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8700 order 32 bits of the value and the low order 32 bits are either
8701 zero or in OFFSET_EXPR. */
8702 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8704 if (HAVE_64BIT_GPRS)
8705 load_register (treg, &imm_expr, 1);
8710 if (target_big_endian)
8722 load_register (hreg, &imm_expr, 0);
8725 if (offset_expr.X_op == O_absent)
8726 move_register (lreg, 0);
8729 gas_assert (offset_expr.X_op == O_constant);
8730 load_register (lreg, &offset_expr, 0);
8737 /* We know that sym is in the .rdata section. First we get the
8738 upper 16 bits of the address. */
8739 if (mips_pic == NO_PIC)
8741 macro_build_lui (&offset_expr, AT);
8746 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8747 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8751 /* Now we load the register(s). */
8752 if (HAVE_64BIT_GPRS)
8755 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8760 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8763 /* FIXME: How in the world do we deal with the possible
8765 offset_expr.X_add_number += 4;
8766 macro_build (&offset_expr, "lw", "t,o(b)",
8767 treg + 1, BFD_RELOC_LO16, AT);
8773 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8774 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8775 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8776 the value and the low order 32 bits are either zero or in
8778 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8781 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8782 if (HAVE_64BIT_FPRS)
8784 gas_assert (HAVE_64BIT_GPRS);
8785 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8789 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8790 if (offset_expr.X_op == O_absent)
8791 macro_build (NULL, "mtc1", "t,G", 0, treg);
8794 gas_assert (offset_expr.X_op == O_constant);
8795 load_register (AT, &offset_expr, 0);
8796 macro_build (NULL, "mtc1", "t,G", AT, treg);
8802 gas_assert (offset_expr.X_op == O_symbol
8803 && offset_expr.X_add_number == 0);
8804 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8805 if (strcmp (s, ".lit8") == 0)
8807 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8809 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8810 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8813 breg = mips_gp_register;
8814 r = BFD_RELOC_MIPS_LITERAL;
8819 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8821 if (mips_pic != NO_PIC)
8822 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8823 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8826 /* FIXME: This won't work for a 64 bit address. */
8827 macro_build_lui (&offset_expr, AT);
8830 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8832 macro_build (&offset_expr, "ldc1", "T,o(b)",
8833 treg, BFD_RELOC_LO16, AT);
8842 /* Even on a big endian machine $fn comes before $fn+1. We have
8843 to adjust when loading from memory. */
8846 gas_assert (!mips_opts.micromips);
8847 gas_assert (mips_opts.isa == ISA_MIPS1);
8848 macro_build (&offset_expr, "lwc1", "T,o(b)",
8849 target_big_endian ? treg + 1 : treg, r, breg);
8850 /* FIXME: A possible overflow which I don't know how to deal
8852 offset_expr.X_add_number += 4;
8853 macro_build (&offset_expr, "lwc1", "T,o(b)",
8854 target_big_endian ? treg : treg + 1, r, breg);
8858 gas_assert (!mips_opts.micromips);
8859 gas_assert (mips_opts.isa == ISA_MIPS1);
8860 /* Even on a big endian machine $fn comes before $fn+1. We have
8861 to adjust when storing to memory. */
8862 macro_build (&offset_expr, "swc1", "T,o(b)",
8863 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8864 offset_expr.X_add_number += 4;
8865 macro_build (&offset_expr, "swc1", "T,o(b)",
8866 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8870 gas_assert (!mips_opts.micromips);
8872 * The MIPS assembler seems to check for X_add_number not
8873 * being double aligned and generating:
8876 * addiu at,at,%lo(foo+1)
8879 * But, the resulting address is the same after relocation so why
8880 * generate the extra instruction?
8882 /* Itbl support may require additional care here. */
8885 if (mips_opts.isa != ISA_MIPS1)
8894 gas_assert (!mips_opts.micromips);
8895 /* Itbl support may require additional care here. */
8898 if (mips_opts.isa != ISA_MIPS1)
8908 if (HAVE_64BIT_GPRS)
8918 if (HAVE_64BIT_GPRS)
8926 if (offset_expr.X_op != O_symbol
8927 && offset_expr.X_op != O_constant)
8929 as_bad (_("Expression too complex"));
8930 offset_expr.X_op = O_constant;
8933 if (HAVE_32BIT_ADDRESSES
8934 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8938 sprintf_vma (value, offset_expr.X_add_number);
8939 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8942 /* Even on a big endian machine $fn comes before $fn+1. We have
8943 to adjust when loading from memory. We set coproc if we must
8944 load $fn+1 first. */
8945 /* Itbl support may require additional care here. */
8946 if (!target_big_endian)
8949 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
8951 /* If this is a reference to a GP relative symbol, we want
8952 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8953 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8954 If we have a base register, we use this
8956 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8957 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8958 If this is not a GP relative symbol, we want
8959 lui $at,<sym> (BFD_RELOC_HI16_S)
8960 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8961 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8962 If there is a base register, we add it to $at after the
8963 lui instruction. If there is a constant, we always use
8965 if (offset_expr.X_op == O_symbol
8966 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8967 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8969 relax_start (offset_expr.X_add_symbol);
8972 tempreg = mips_gp_register;
8976 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8977 AT, breg, mips_gp_register);
8982 /* Itbl support may require additional care here. */
8983 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8984 BFD_RELOC_GPREL16, tempreg);
8985 offset_expr.X_add_number += 4;
8987 /* Set mips_optimize to 2 to avoid inserting an
8989 hold_mips_optimize = mips_optimize;
8991 /* Itbl support may require additional care here. */
8992 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8993 BFD_RELOC_GPREL16, tempreg);
8994 mips_optimize = hold_mips_optimize;
8998 offset_expr.X_add_number -= 4;
9001 macro_build_lui (&offset_expr, AT);
9003 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9004 /* Itbl support may require additional care here. */
9005 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9006 BFD_RELOC_LO16, AT);
9007 /* FIXME: How do we handle overflow here? */
9008 offset_expr.X_add_number += 4;
9009 /* Itbl support may require additional care here. */
9010 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9011 BFD_RELOC_LO16, AT);
9012 if (mips_relax.sequence)
9015 else if (!mips_big_got)
9017 /* If this is a reference to an external symbol, we want
9018 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9023 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9025 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9026 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9027 If there is a base register we add it to $at before the
9028 lwc1 instructions. If there is a constant we include it
9029 in the lwc1 instructions. */
9031 expr1.X_add_number = offset_expr.X_add_number;
9032 if (expr1.X_add_number < -0x8000
9033 || expr1.X_add_number >= 0x8000 - 4)
9034 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9035 load_got_offset (AT, &offset_expr);
9038 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9040 /* Set mips_optimize to 2 to avoid inserting an undesired
9042 hold_mips_optimize = mips_optimize;
9045 /* Itbl support may require additional care here. */
9046 relax_start (offset_expr.X_add_symbol);
9047 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9048 BFD_RELOC_LO16, AT);
9049 expr1.X_add_number += 4;
9050 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9051 BFD_RELOC_LO16, AT);
9053 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9054 BFD_RELOC_LO16, AT);
9055 offset_expr.X_add_number += 4;
9056 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9057 BFD_RELOC_LO16, AT);
9060 mips_optimize = hold_mips_optimize;
9062 else if (mips_big_got)
9066 /* If this is a reference to an external symbol, we want
9067 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9069 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9074 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9076 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9077 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9078 If there is a base register we add it to $at before the
9079 lwc1 instructions. If there is a constant we include it
9080 in the lwc1 instructions. */
9082 expr1.X_add_number = offset_expr.X_add_number;
9083 offset_expr.X_add_number = 0;
9084 if (expr1.X_add_number < -0x8000
9085 || expr1.X_add_number >= 0x8000 - 4)
9086 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9087 gpdelay = reg_needs_delay (mips_gp_register);
9088 relax_start (offset_expr.X_add_symbol);
9089 macro_build (&offset_expr, "lui", LUI_FMT,
9090 AT, BFD_RELOC_MIPS_GOT_HI16);
9091 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9092 AT, AT, mips_gp_register);
9093 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9094 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9097 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9098 /* Itbl support may require additional care here. */
9099 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9100 BFD_RELOC_LO16, AT);
9101 expr1.X_add_number += 4;
9103 /* Set mips_optimize to 2 to avoid inserting an undesired
9105 hold_mips_optimize = mips_optimize;
9107 /* Itbl support may require additional care here. */
9108 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9109 BFD_RELOC_LO16, AT);
9110 mips_optimize = hold_mips_optimize;
9111 expr1.X_add_number -= 4;
9114 offset_expr.X_add_number = expr1.X_add_number;
9116 macro_build (NULL, "nop", "");
9117 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9118 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9122 /* Itbl support may require additional care here. */
9123 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9124 BFD_RELOC_LO16, AT);
9125 offset_expr.X_add_number += 4;
9127 /* Set mips_optimize to 2 to avoid inserting an undesired
9129 hold_mips_optimize = mips_optimize;
9131 /* Itbl support may require additional care here. */
9132 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9133 BFD_RELOC_LO16, AT);
9134 mips_optimize = hold_mips_optimize;
9143 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9146 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9148 macro_build (&offset_expr, s, "t,o(b)", treg,
9149 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9151 if (!HAVE_64BIT_GPRS)
9153 offset_expr.X_add_number += 4;
9154 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9155 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9176 /* New code added to support COPZ instructions.
9177 This code builds table entries out of the macros in mip_opcodes.
9178 R4000 uses interlocks to handle coproc delays.
9179 Other chips (like the R3000) require nops to be inserted for delays.
9181 FIXME: Currently, we require that the user handle delays.
9182 In order to fill delay slots for non-interlocked chips,
9183 we must have a way to specify delays based on the coprocessor.
9184 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9185 What are the side-effects of the cop instruction?
9186 What cache support might we have and what are its effects?
9187 Both coprocessor & memory require delays. how long???
9188 What registers are read/set/modified?
9190 If an itbl is provided to interpret cop instructions,
9191 this knowledge can be encoded in the itbl spec. */
9205 gas_assert (!mips_opts.micromips);
9206 /* For now we just do C (same as Cz). The parameter will be
9207 stored in insn_opcode by mips_ip. */
9208 macro_build (NULL, s, "C", ip->insn_opcode);
9212 move_register (dreg, sreg);
9218 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9219 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9225 /* The MIPS assembler some times generates shifts and adds. I'm
9226 not trying to be that fancy. GCC should do this for us
9229 load_register (AT, &imm_expr, dbl);
9230 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9231 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9247 load_register (AT, &imm_expr, dbl);
9248 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9249 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9250 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9251 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9253 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9256 if (mips_opts.micromips)
9257 micromips_label_expr (&label_expr);
9259 label_expr.X_add_number = 8;
9260 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9261 macro_build (NULL, "nop", "");
9262 macro_build (NULL, "break", BRK_FMT, 6);
9263 if (mips_opts.micromips)
9264 micromips_add_label ();
9267 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9283 load_register (AT, &imm_expr, dbl);
9284 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9285 sreg, imm ? AT : treg);
9286 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9287 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9289 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9292 if (mips_opts.micromips)
9293 micromips_label_expr (&label_expr);
9295 label_expr.X_add_number = 8;
9296 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9297 macro_build (NULL, "nop", "");
9298 macro_build (NULL, "break", BRK_FMT, 6);
9299 if (mips_opts.micromips)
9300 micromips_add_label ();
9306 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9317 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9318 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9322 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9323 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9324 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9325 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9329 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9340 macro_build (NULL, "negu", "d,w", tempreg, treg);
9341 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9345 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9346 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9347 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9348 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9357 if (imm_expr.X_op != O_constant)
9358 as_bad (_("Improper rotate count"));
9359 rot = imm_expr.X_add_number & 0x3f;
9360 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9362 rot = (64 - rot) & 0x3f;
9364 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9366 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9371 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9374 l = (rot < 0x20) ? "dsll" : "dsll32";
9375 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9378 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9379 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9380 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9388 if (imm_expr.X_op != O_constant)
9389 as_bad (_("Improper rotate count"));
9390 rot = imm_expr.X_add_number & 0x1f;
9391 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9393 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9398 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9402 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9403 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9404 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9409 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9411 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9415 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9416 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9417 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9418 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9422 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9424 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9428 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9429 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9430 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9431 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9440 if (imm_expr.X_op != O_constant)
9441 as_bad (_("Improper rotate count"));
9442 rot = imm_expr.X_add_number & 0x3f;
9443 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9446 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9448 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9453 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9456 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9457 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9460 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9461 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9462 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9470 if (imm_expr.X_op != O_constant)
9471 as_bad (_("Improper rotate count"));
9472 rot = imm_expr.X_add_number & 0x1f;
9473 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9475 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9480 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9484 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9485 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9486 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9492 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9494 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9497 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9498 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9503 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9505 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9510 as_warn (_("Instruction %s: result is always false"),
9512 move_register (dreg, 0);
9515 if (CPU_HAS_SEQ (mips_opts.arch)
9516 && -512 <= imm_expr.X_add_number
9517 && imm_expr.X_add_number < 512)
9519 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9520 (int) imm_expr.X_add_number);
9523 if (imm_expr.X_op == O_constant
9524 && imm_expr.X_add_number >= 0
9525 && imm_expr.X_add_number < 0x10000)
9527 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9529 else if (imm_expr.X_op == O_constant
9530 && imm_expr.X_add_number > -0x8000
9531 && imm_expr.X_add_number < 0)
9533 imm_expr.X_add_number = -imm_expr.X_add_number;
9534 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9535 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9537 else if (CPU_HAS_SEQ (mips_opts.arch))
9540 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9541 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9546 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9547 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9550 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9553 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9559 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9560 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9563 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9565 if (imm_expr.X_op == O_constant
9566 && imm_expr.X_add_number >= -0x8000
9567 && imm_expr.X_add_number < 0x8000)
9569 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9570 dreg, sreg, BFD_RELOC_LO16);
9574 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9575 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9579 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9582 case M_SGT: /* sreg > treg <==> treg < sreg */
9588 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9591 case M_SGT_I: /* sreg > I <==> I < sreg */
9598 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9599 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9602 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9608 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9609 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9612 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9619 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9620 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9621 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9625 if (imm_expr.X_op == O_constant
9626 && imm_expr.X_add_number >= -0x8000
9627 && imm_expr.X_add_number < 0x8000)
9629 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9633 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9634 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9638 if (imm_expr.X_op == O_constant
9639 && imm_expr.X_add_number >= -0x8000
9640 && imm_expr.X_add_number < 0x8000)
9642 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9647 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9648 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9653 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9655 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9658 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9659 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9664 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9666 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9671 as_warn (_("Instruction %s: result is always true"),
9673 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9674 dreg, 0, BFD_RELOC_LO16);
9677 if (CPU_HAS_SEQ (mips_opts.arch)
9678 && -512 <= imm_expr.X_add_number
9679 && imm_expr.X_add_number < 512)
9681 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9682 (int) imm_expr.X_add_number);
9685 if (imm_expr.X_op == O_constant
9686 && imm_expr.X_add_number >= 0
9687 && imm_expr.X_add_number < 0x10000)
9689 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9691 else if (imm_expr.X_op == O_constant
9692 && imm_expr.X_add_number > -0x8000
9693 && imm_expr.X_add_number < 0)
9695 imm_expr.X_add_number = -imm_expr.X_add_number;
9696 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9697 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9699 else if (CPU_HAS_SEQ (mips_opts.arch))
9702 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9703 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9708 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9709 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9712 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9727 if (!mips_opts.micromips)
9729 if (imm_expr.X_op == O_constant
9730 && imm_expr.X_add_number > -0x200
9731 && imm_expr.X_add_number <= 0x200)
9733 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9742 if (imm_expr.X_op == O_constant
9743 && imm_expr.X_add_number > -0x8000
9744 && imm_expr.X_add_number <= 0x8000)
9746 imm_expr.X_add_number = -imm_expr.X_add_number;
9747 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9752 load_register (AT, &imm_expr, dbl);
9753 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9775 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9776 macro_build (NULL, s, "s,t", sreg, AT);
9781 gas_assert (!mips_opts.micromips);
9782 gas_assert (mips_opts.isa == ISA_MIPS1);
9784 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9785 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9788 * Is the double cfc1 instruction a bug in the mips assembler;
9789 * or is there a reason for it?
9792 macro_build (NULL, "cfc1", "t,G", treg, RA);
9793 macro_build (NULL, "cfc1", "t,G", treg, RA);
9794 macro_build (NULL, "nop", "");
9795 expr1.X_add_number = 3;
9796 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9797 expr1.X_add_number = 2;
9798 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9799 macro_build (NULL, "ctc1", "t,G", AT, RA);
9800 macro_build (NULL, "nop", "");
9801 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9803 macro_build (NULL, "ctc1", "t,G", treg, RA);
9804 macro_build (NULL, "nop", "");
9827 off12 = mips_opts.micromips;
9835 off12 = mips_opts.micromips;
9851 off12 = mips_opts.micromips;
9860 off12 = mips_opts.micromips;
9865 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9866 as_bad (_("Operand overflow"));
9869 expr1.X_add_number = 0;
9874 load_address (tempreg, ep, &used_at);
9876 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9877 tempreg, tempreg, breg);
9883 && (offset_expr.X_op != O_constant
9884 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9885 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9889 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9890 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9895 else if (!ust && treg == breg)
9906 if (!target_big_endian)
9907 ep->X_add_number += off;
9909 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9911 macro_build (NULL, s, "t,~(b)",
9912 tempreg, (unsigned long) ep->X_add_number, breg);
9914 if (!target_big_endian)
9915 ep->X_add_number -= off;
9917 ep->X_add_number += off;
9919 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9921 macro_build (NULL, s2, "t,~(b)",
9922 tempreg, (unsigned long) ep->X_add_number, breg);
9924 /* If necessary, move the result in tempreg to the final destination. */
9925 if (!ust && treg != tempreg)
9927 /* Protect second load's delay slot. */
9929 move_register (treg, tempreg);
9935 if (target_big_endian == ust)
9936 ep->X_add_number += off;
9937 tempreg = ust || ab ? treg : AT;
9938 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9940 /* For halfword transfers we need a temporary register to shuffle
9941 bytes. Unfortunately for M_USH_A we have none available before
9942 the next store as AT holds the base address. We deal with this
9943 case by clobbering TREG and then restoring it as with ULH. */
9944 tempreg = ust == ab ? treg : AT;
9946 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9948 if (target_big_endian == ust)
9949 ep->X_add_number -= off;
9951 ep->X_add_number += off;
9952 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9954 /* For M_USH_A re-retrieve the LSB. */
9957 if (target_big_endian)
9958 ep->X_add_number += off;
9960 ep->X_add_number -= off;
9961 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9963 /* For ULH and M_USH_A OR the LSB in. */
9966 tempreg = !ab ? AT : treg;
9967 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9968 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9973 /* FIXME: Check if this is one of the itbl macros, since they
9974 are added dynamically. */
9975 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9978 if (!mips_opts.at && used_at)
9979 as_bad (_("Macro used $at after \".set noat\""));
9982 /* Implement macros in mips16 mode. */
9985 mips16_macro (struct mips_cl_insn *ip)
9988 int xreg, yreg, zreg, tmp;
9991 const char *s, *s2, *s3;
9993 mask = ip->insn_mo->mask;
9995 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
9996 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
9997 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
9999 expr1.X_op = O_constant;
10000 expr1.X_op_symbol = NULL;
10001 expr1.X_add_symbol = NULL;
10002 expr1.X_add_number = 1;
10021 start_noreorder ();
10022 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10023 expr1.X_add_number = 2;
10024 macro_build (&expr1, "bnez", "x,p", yreg);
10025 macro_build (NULL, "break", "6", 7);
10027 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10028 since that causes an overflow. We should do that as well,
10029 but I don't see how to do the comparisons without a temporary
10032 macro_build (NULL, s, "x", zreg);
10051 start_noreorder ();
10052 macro_build (NULL, s, "0,x,y", xreg, yreg);
10053 expr1.X_add_number = 2;
10054 macro_build (&expr1, "bnez", "x,p", yreg);
10055 macro_build (NULL, "break", "6", 7);
10057 macro_build (NULL, s2, "x", zreg);
10063 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10064 macro_build (NULL, "mflo", "x", zreg);
10072 if (imm_expr.X_op != O_constant)
10073 as_bad (_("Unsupported large constant"));
10074 imm_expr.X_add_number = -imm_expr.X_add_number;
10075 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10079 if (imm_expr.X_op != O_constant)
10080 as_bad (_("Unsupported large constant"));
10081 imm_expr.X_add_number = -imm_expr.X_add_number;
10082 macro_build (&imm_expr, "addiu", "x,k", xreg);
10086 if (imm_expr.X_op != O_constant)
10087 as_bad (_("Unsupported large constant"));
10088 imm_expr.X_add_number = -imm_expr.X_add_number;
10089 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10111 goto do_reverse_branch;
10115 goto do_reverse_branch;
10127 goto do_reverse_branch;
10138 macro_build (NULL, s, "x,y", xreg, yreg);
10139 macro_build (&offset_expr, s2, "p");
10166 goto do_addone_branch_i;
10171 goto do_addone_branch_i;
10186 goto do_addone_branch_i;
10192 do_addone_branch_i:
10193 if (imm_expr.X_op != O_constant)
10194 as_bad (_("Unsupported large constant"));
10195 ++imm_expr.X_add_number;
10198 macro_build (&imm_expr, s, s3, xreg);
10199 macro_build (&offset_expr, s2, "p");
10203 expr1.X_add_number = 0;
10204 macro_build (&expr1, "slti", "x,8", yreg);
10206 move_register (xreg, yreg);
10207 expr1.X_add_number = 2;
10208 macro_build (&expr1, "bteqz", "p");
10209 macro_build (NULL, "neg", "x,w", xreg, xreg);
10213 /* For consistency checking, verify that all bits are specified either
10214 by the match/mask part of the instruction definition, or by the
10217 validate_mips_insn (const struct mips_opcode *opc)
10219 const char *p = opc->args;
10221 unsigned long used_bits = opc->mask;
10223 if ((used_bits & opc->match) != opc->match)
10225 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10226 opc->name, opc->args);
10229 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10239 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10240 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10241 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10242 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10243 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10244 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10245 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10246 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10247 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10248 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10249 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10250 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10251 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10253 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10254 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10255 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10256 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10257 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10258 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10259 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10260 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10261 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10262 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10263 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10264 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10265 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10266 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10267 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10270 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10271 c, opc->name, opc->args);
10275 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10276 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10278 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10279 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10280 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10281 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10283 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10284 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10286 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10287 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10289 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10290 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10291 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10292 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10293 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10294 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10295 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10296 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10297 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10298 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10299 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10300 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10301 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10302 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10303 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10304 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10305 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10307 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10308 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10309 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10310 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10312 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10313 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10314 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10315 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10316 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10317 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10318 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10319 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10320 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10323 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10324 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10325 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10326 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10327 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10330 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10331 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10332 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10333 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10334 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10335 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10336 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10337 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10338 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10339 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10340 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10341 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10342 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10343 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10344 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10345 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10346 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10347 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10348 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10349 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10351 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10352 c, opc->name, opc->args);
10356 if (used_bits != 0xffffffff)
10358 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10359 ~used_bits & 0xffffffff, opc->name, opc->args);
10365 /* For consistency checking, verify that the length implied matches the
10366 major opcode and that all bits are specified either by the match/mask
10367 part of the instruction definition, or by the operand list. */
10370 validate_micromips_insn (const struct mips_opcode *opc)
10372 unsigned long match = opc->match;
10373 unsigned long mask = opc->mask;
10374 const char *p = opc->args;
10375 unsigned long insn_bits;
10376 unsigned long used_bits;
10377 unsigned long major;
10378 unsigned int length;
10382 if ((mask & match) != match)
10384 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10385 opc->name, opc->args);
10388 length = micromips_insn_length (opc);
10389 if (length != 2 && length != 4)
10391 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10392 "%s %s"), length, opc->name, opc->args);
10395 major = match >> (10 + 8 * (length - 2));
10396 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10397 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10399 as_bad (_("Internal error: bad microMIPS opcode "
10400 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10404 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10405 insn_bits = 1 << 4 * length;
10406 insn_bits <<= 4 * length;
10409 #define USE_BITS(field) \
10410 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10421 case 'A': USE_BITS (EXTLSB); break;
10422 case 'B': USE_BITS (INSMSB); break;
10423 case 'C': USE_BITS (EXTMSBD); break;
10424 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10425 case 'E': USE_BITS (EXTLSB); break;
10426 case 'F': USE_BITS (INSMSB); break;
10427 case 'G': USE_BITS (EXTMSBD); break;
10428 case 'H': USE_BITS (EXTMSBD); break;
10430 as_bad (_("Internal error: bad mips opcode "
10431 "(unknown extension operand type `%c%c'): %s %s"),
10432 e, c, opc->name, opc->args);
10440 case 'A': USE_BITS (IMMA); break;
10441 case 'B': USE_BITS (IMMB); break;
10442 case 'C': USE_BITS (IMMC); break;
10443 case 'D': USE_BITS (IMMD); break;
10444 case 'E': USE_BITS (IMME); break;
10445 case 'F': USE_BITS (IMMF); break;
10446 case 'G': USE_BITS (IMMG); break;
10447 case 'H': USE_BITS (IMMH); break;
10448 case 'I': USE_BITS (IMMI); break;
10449 case 'J': USE_BITS (IMMJ); break;
10450 case 'L': USE_BITS (IMML); break;
10451 case 'M': USE_BITS (IMMM); break;
10452 case 'N': USE_BITS (IMMN); break;
10453 case 'O': USE_BITS (IMMO); break;
10454 case 'P': USE_BITS (IMMP); break;
10455 case 'Q': USE_BITS (IMMQ); break;
10456 case 'U': USE_BITS (IMMU); break;
10457 case 'W': USE_BITS (IMMW); break;
10458 case 'X': USE_BITS (IMMX); break;
10459 case 'Y': USE_BITS (IMMY); break;
10462 case 'b': USE_BITS (MB); break;
10463 case 'c': USE_BITS (MC); break;
10464 case 'd': USE_BITS (MD); break;
10465 case 'e': USE_BITS (ME); break;
10466 case 'f': USE_BITS (MF); break;
10467 case 'g': USE_BITS (MG); break;
10468 case 'h': USE_BITS (MH); break;
10469 case 'i': USE_BITS (MI); break;
10470 case 'j': USE_BITS (MJ); break;
10471 case 'l': USE_BITS (ML); break;
10472 case 'm': USE_BITS (MM); break;
10473 case 'n': USE_BITS (MN); break;
10474 case 'p': USE_BITS (MP); break;
10475 case 'q': USE_BITS (MQ); break;
10483 as_bad (_("Internal error: bad mips opcode "
10484 "(unknown extension operand type `%c%c'): %s %s"),
10485 e, c, opc->name, opc->args);
10489 case '.': USE_BITS (OFFSET10); break;
10490 case '1': USE_BITS (STYPE); break;
10491 case '2': USE_BITS (BP); break;
10492 case '3': USE_BITS (SA3); break;
10493 case '4': USE_BITS (SA4); break;
10494 case '5': USE_BITS (IMM8); break;
10495 case '6': USE_BITS (RS); break;
10496 case '7': USE_BITS (DSPACC); break;
10497 case '8': USE_BITS (WRDSP); break;
10498 case '0': USE_BITS (DSPSFT); break;
10499 case '<': USE_BITS (SHAMT); break;
10500 case '>': USE_BITS (SHAMT); break;
10501 case '@': USE_BITS (IMM10); break;
10502 case 'B': USE_BITS (CODE10); break;
10503 case 'C': USE_BITS (COPZ); break;
10504 case 'D': USE_BITS (FD); break;
10505 case 'E': USE_BITS (RT); break;
10506 case 'G': USE_BITS (RS); break;
10507 case 'H': USE_BITS (SEL); break;
10508 case 'K': USE_BITS (RS); break;
10509 case 'M': USE_BITS (CCC); break;
10510 case 'N': USE_BITS (BCC); break;
10511 case 'R': USE_BITS (FR); break;
10512 case 'S': USE_BITS (FS); break;
10513 case 'T': USE_BITS (FT); break;
10514 case 'V': USE_BITS (FS); break;
10515 case '\\': USE_BITS (3BITPOS); break;
10516 case '^': USE_BITS (RD); break;
10517 case 'a': USE_BITS (TARGET); break;
10518 case 'b': USE_BITS (RS); break;
10519 case 'c': USE_BITS (CODE); break;
10520 case 'd': USE_BITS (RD); break;
10521 case 'h': USE_BITS (PREFX); break;
10522 case 'i': USE_BITS (IMMEDIATE); break;
10523 case 'j': USE_BITS (DELTA); break;
10524 case 'k': USE_BITS (CACHE); break;
10525 case 'n': USE_BITS (RT); break;
10526 case 'o': USE_BITS (DELTA); break;
10527 case 'p': USE_BITS (DELTA); break;
10528 case 'q': USE_BITS (CODE2); break;
10529 case 'r': USE_BITS (RS); break;
10530 case 's': USE_BITS (RS); break;
10531 case 't': USE_BITS (RT); break;
10532 case 'u': USE_BITS (IMMEDIATE); break;
10533 case 'v': USE_BITS (RS); break;
10534 case 'w': USE_BITS (RT); break;
10535 case 'y': USE_BITS (RS3); break;
10537 case '|': USE_BITS (TRAP); break;
10538 case '~': USE_BITS (OFFSET12); break;
10540 as_bad (_("Internal error: bad microMIPS opcode "
10541 "(unknown operand type `%c'): %s %s"),
10542 c, opc->name, opc->args);
10546 if (used_bits != insn_bits)
10548 if (~used_bits & insn_bits)
10549 as_bad (_("Internal error: bad microMIPS opcode "
10550 "(bits 0x%lx undefined): %s %s"),
10551 ~used_bits & insn_bits, opc->name, opc->args);
10552 if (used_bits & ~insn_bits)
10553 as_bad (_("Internal error: bad microMIPS opcode "
10554 "(bits 0x%lx defined): %s %s"),
10555 used_bits & ~insn_bits, opc->name, opc->args);
10561 /* UDI immediates. */
10562 struct mips_immed {
10564 unsigned int shift;
10565 unsigned long mask;
10569 static const struct mips_immed mips_immed[] = {
10570 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10571 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10572 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10573 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10577 /* Check whether an odd floating-point register is allowed. */
10579 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10581 const char *s = insn->name;
10583 if (insn->pinfo == INSN_MACRO)
10584 /* Let a macro pass, we'll catch it later when it is expanded. */
10587 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10589 /* Allow odd registers for single-precision ops. */
10590 switch (insn->pinfo & (FP_S | FP_D))
10594 return 1; /* both single precision - ok */
10596 return 0; /* both double precision - fail */
10601 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10602 s = strchr (insn->name, '.');
10604 s = s != NULL ? strchr (s + 1, '.') : NULL;
10605 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10608 /* Single-precision coprocessor loads and moves are OK too. */
10609 if ((insn->pinfo & FP_S)
10610 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10611 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10617 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10618 taking bits from BIT up. */
10620 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10622 return (ep->X_op == O_constant
10623 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10624 && ep->X_add_number >= min << bit
10625 && ep->X_add_number < max << bit);
10628 /* This routine assembles an instruction into its binary format. As a
10629 side effect, it sets one of the global variables imm_reloc or
10630 offset_reloc to the type of relocation to do if one of the operands
10631 is an address expression. */
10634 mips_ip (char *str, struct mips_cl_insn *ip)
10636 bfd_boolean wrong_delay_slot_insns = FALSE;
10637 bfd_boolean need_delay_slot_ok = TRUE;
10638 struct mips_opcode *firstinsn = NULL;
10639 const struct mips_opcode *past;
10640 struct hash_control *hash;
10644 struct mips_opcode *insn;
10646 unsigned int regno;
10647 unsigned int lastregno;
10648 unsigned int destregno = 0;
10649 unsigned int lastpos = 0;
10650 unsigned int limlo, limhi;
10652 offsetT min_range, max_range;
10656 unsigned int rtype;
10662 if (mips_opts.micromips)
10664 hash = micromips_op_hash;
10665 past = µmips_opcodes[bfd_micromips_num_opcodes];
10670 past = &mips_opcodes[NUMOPCODES];
10672 forced_insn_length = 0;
10675 /* We first try to match an instruction up to a space or to the end. */
10676 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10679 /* Make a copy of the instruction so that we can fiddle with it. */
10680 name = alloca (end + 1);
10681 memcpy (name, str, end);
10686 insn = (struct mips_opcode *) hash_find (hash, name);
10688 if (insn != NULL || !mips_opts.micromips)
10690 if (forced_insn_length)
10693 /* See if there's an instruction size override suffix,
10694 either `16' or `32', at the end of the mnemonic proper,
10695 that defines the operation, i.e. before the first `.'
10696 character if any. Strip it and retry. */
10697 dot = strchr (name, '.');
10698 opend = dot != NULL ? dot - name : end;
10701 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10702 forced_insn_length = 2;
10703 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10704 forced_insn_length = 4;
10707 memcpy (name + opend - 2, name + opend, end - opend + 1);
10711 insn_error = _("Unrecognized opcode");
10715 /* For microMIPS instructions placed in a fixed-length branch delay slot
10716 we make up to two passes over the relevant fragment of the opcode
10717 table. First we try instructions that meet the delay slot's length
10718 requirement. If none matched, then we retry with the remaining ones
10719 and if one matches, then we use it and then issue an appropriate
10720 warning later on. */
10721 argsStart = s = str + end;
10724 bfd_boolean delay_slot_ok;
10725 bfd_boolean size_ok;
10728 gas_assert (strcmp (insn->name, name) == 0);
10730 ok = is_opcode_valid (insn);
10731 size_ok = is_size_valid (insn);
10732 delay_slot_ok = is_delay_slot_valid (insn);
10733 if (!delay_slot_ok && !wrong_delay_slot_insns)
10736 wrong_delay_slot_insns = TRUE;
10738 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10740 static char buf[256];
10742 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10747 if (wrong_delay_slot_insns && need_delay_slot_ok)
10749 gas_assert (firstinsn);
10750 need_delay_slot_ok = FALSE;
10760 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10761 mips_cpu_info_from_arch (mips_opts.arch)->name,
10762 mips_cpu_info_from_isa (mips_opts.isa)->name);
10764 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10765 8 * forced_insn_length);
10771 create_insn (ip, insn);
10774 lastregno = 0xffffffff;
10775 for (args = insn->args;; ++args)
10779 s += strspn (s, " \t");
10783 case '\0': /* end of args */
10789 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10790 code) or 14 (for microMIPS code). */
10791 my_getExpression (&imm_expr, s);
10792 check_absolute_expr (ip, &imm_expr);
10793 if ((unsigned long) imm_expr.X_add_number != 1
10794 && (unsigned long) imm_expr.X_add_number != 3)
10796 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10797 (unsigned long) imm_expr.X_add_number);
10799 INSERT_OPERAND (mips_opts.micromips,
10800 BP, *ip, imm_expr.X_add_number);
10801 imm_expr.X_op = O_absent;
10806 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10807 code) or 21 (for microMIPS code). */
10809 unsigned long mask = (mips_opts.micromips
10810 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
10812 my_getExpression (&imm_expr, s);
10813 check_absolute_expr (ip, &imm_expr);
10814 if ((unsigned long) imm_expr.X_add_number > mask)
10815 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10816 mask, (unsigned long) imm_expr.X_add_number);
10817 INSERT_OPERAND (mips_opts.micromips,
10818 SA3, *ip, imm_expr.X_add_number);
10819 imm_expr.X_op = O_absent;
10825 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10826 code) or 21 (for microMIPS code). */
10828 unsigned long mask = (mips_opts.micromips
10829 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
10831 my_getExpression (&imm_expr, s);
10832 check_absolute_expr (ip, &imm_expr);
10833 if ((unsigned long) imm_expr.X_add_number > mask)
10834 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10835 mask, (unsigned long) imm_expr.X_add_number);
10836 INSERT_OPERAND (mips_opts.micromips,
10837 SA4, *ip, imm_expr.X_add_number);
10838 imm_expr.X_op = O_absent;
10844 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10845 code) or 16 (for microMIPS code). */
10847 unsigned long mask = (mips_opts.micromips
10848 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
10850 my_getExpression (&imm_expr, s);
10851 check_absolute_expr (ip, &imm_expr);
10852 if ((unsigned long) imm_expr.X_add_number > mask)
10853 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10854 mask, (unsigned long) imm_expr.X_add_number);
10855 INSERT_OPERAND (mips_opts.micromips,
10856 IMM8, *ip, imm_expr.X_add_number);
10857 imm_expr.X_op = O_absent;
10863 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
10864 code) or 21 (for microMIPS code). */
10866 unsigned long mask = (mips_opts.micromips
10867 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
10869 my_getExpression (&imm_expr, s);
10870 check_absolute_expr (ip, &imm_expr);
10871 if ((unsigned long) imm_expr.X_add_number > mask)
10872 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10873 mask, (unsigned long) imm_expr.X_add_number);
10874 INSERT_OPERAND (mips_opts.micromips,
10875 RS, *ip, imm_expr.X_add_number);
10876 imm_expr.X_op = O_absent;
10881 case '7': /* Four DSP accumulators in bits 11,12. */
10882 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
10883 && s[3] >= '0' && s[3] <= '3')
10885 regno = s[3] - '0';
10887 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
10891 as_bad (_("Invalid dsp acc register"));
10895 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
10896 code) or 14 (for microMIPS code). */
10898 unsigned long mask = (mips_opts.micromips
10899 ? MICROMIPSOP_MASK_WRDSP
10902 my_getExpression (&imm_expr, s);
10903 check_absolute_expr (ip, &imm_expr);
10904 if ((unsigned long) imm_expr.X_add_number > mask)
10905 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10906 mask, (unsigned long) imm_expr.X_add_number);
10907 INSERT_OPERAND (mips_opts.micromips,
10908 WRDSP, *ip, imm_expr.X_add_number);
10909 imm_expr.X_op = O_absent;
10914 case '9': /* Four DSP accumulators in bits 21,22. */
10915 gas_assert (!mips_opts.micromips);
10916 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
10917 && s[3] >= '0' && s[3] <= '3')
10919 regno = s[3] - '0';
10921 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10925 as_bad (_("Invalid dsp acc register"));
10929 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
10930 code) or 20 (for microMIPS code). */
10932 long mask = (mips_opts.micromips
10933 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
10935 my_getExpression (&imm_expr, s);
10936 check_absolute_expr (ip, &imm_expr);
10937 min_range = -((mask + 1) >> 1);
10938 max_range = ((mask + 1) >> 1) - 1;
10939 if (imm_expr.X_add_number < min_range
10940 || imm_expr.X_add_number > max_range)
10941 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10942 (long) min_range, (long) max_range,
10943 (long) imm_expr.X_add_number);
10944 INSERT_OPERAND (mips_opts.micromips,
10945 DSPSFT, *ip, imm_expr.X_add_number);
10946 imm_expr.X_op = O_absent;
10951 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10952 gas_assert (!mips_opts.micromips);
10953 my_getExpression (&imm_expr, s);
10954 check_absolute_expr (ip, &imm_expr);
10955 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10957 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10959 (unsigned long) imm_expr.X_add_number);
10961 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
10962 imm_expr.X_op = O_absent;
10966 case ':': /* DSP 7-bit signed immediate in bit 19. */
10967 gas_assert (!mips_opts.micromips);
10968 my_getExpression (&imm_expr, s);
10969 check_absolute_expr (ip, &imm_expr);
10970 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10971 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10972 if (imm_expr.X_add_number < min_range ||
10973 imm_expr.X_add_number > max_range)
10975 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10976 (long) min_range, (long) max_range,
10977 (long) imm_expr.X_add_number);
10979 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
10980 imm_expr.X_op = O_absent;
10984 case '@': /* DSP 10-bit signed immediate in bit 16. */
10986 long mask = (mips_opts.micromips
10987 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
10989 my_getExpression (&imm_expr, s);
10990 check_absolute_expr (ip, &imm_expr);
10991 min_range = -((mask + 1) >> 1);
10992 max_range = ((mask + 1) >> 1) - 1;
10993 if (imm_expr.X_add_number < min_range
10994 || imm_expr.X_add_number > max_range)
10995 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10996 (long) min_range, (long) max_range,
10997 (long) imm_expr.X_add_number);
10998 INSERT_OPERAND (mips_opts.micromips,
10999 IMM10, *ip, imm_expr.X_add_number);
11000 imm_expr.X_op = O_absent;
11005 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11006 gas_assert (mips_opts.micromips);
11007 my_getExpression (&imm_expr, s);
11008 check_absolute_expr (ip, &imm_expr);
11009 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11010 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11011 MICROMIPSOP_MASK_RD,
11012 (unsigned long) imm_expr.X_add_number);
11013 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11014 imm_expr.X_op = O_absent;
11018 case '!': /* MT usermode flag bit. */
11019 gas_assert (!mips_opts.micromips);
11020 my_getExpression (&imm_expr, s);
11021 check_absolute_expr (ip, &imm_expr);
11022 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11023 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11024 (unsigned long) imm_expr.X_add_number);
11025 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11026 imm_expr.X_op = O_absent;
11030 case '$': /* MT load high flag bit. */
11031 gas_assert (!mips_opts.micromips);
11032 my_getExpression (&imm_expr, s);
11033 check_absolute_expr (ip, &imm_expr);
11034 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11035 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11036 (unsigned long) imm_expr.X_add_number);
11037 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11038 imm_expr.X_op = O_absent;
11042 case '*': /* Four DSP accumulators in bits 18,19. */
11043 gas_assert (!mips_opts.micromips);
11044 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11045 s[3] >= '0' && s[3] <= '3')
11047 regno = s[3] - '0';
11049 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11053 as_bad (_("Invalid dsp/smartmips acc register"));
11056 case '&': /* Four DSP accumulators in bits 13,14. */
11057 gas_assert (!mips_opts.micromips);
11058 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11059 s[3] >= '0' && s[3] <= '3')
11061 regno = s[3] - '0';
11063 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11067 as_bad (_("Invalid dsp/smartmips acc register"));
11070 case '\\': /* 3-bit bit position. */
11072 unsigned long mask = (mips_opts.micromips
11073 ? MICROMIPSOP_MASK_3BITPOS
11074 : OP_MASK_3BITPOS);
11076 my_getExpression (&imm_expr, s);
11077 check_absolute_expr (ip, &imm_expr);
11078 if ((unsigned long) imm_expr.X_add_number > mask)
11079 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11081 mask, (unsigned long) imm_expr.X_add_number);
11082 INSERT_OPERAND (mips_opts.micromips,
11083 3BITPOS, *ip, imm_expr.X_add_number);
11084 imm_expr.X_op = O_absent;
11098 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11102 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11106 gas_assert (!mips_opts.micromips);
11107 INSERT_OPERAND (0, FT, *ip, lastregno);
11111 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11117 /* Handle optional base register.
11118 Either the base register is omitted or
11119 we must have a left paren. */
11120 /* This is dependent on the next operand specifier
11121 is a base register specification. */
11122 gas_assert (args[1] == 'b'
11123 || (mips_opts.micromips
11125 && (args[2] == 'l' || args[2] == 'n'
11126 || args[2] == 's' || args[2] == 'a')));
11127 if (*s == '\0' && args[1] == 'b')
11129 /* Fall through. */
11131 case ')': /* These must match exactly. */
11136 case '[': /* These must match exactly. */
11138 gas_assert (!mips_opts.micromips);
11143 case '+': /* Opcode extension character. */
11146 case '1': /* UDI immediates. */
11150 gas_assert (!mips_opts.micromips);
11152 const struct mips_immed *imm = mips_immed;
11154 while (imm->type && imm->type != *args)
11158 my_getExpression (&imm_expr, s);
11159 check_absolute_expr (ip, &imm_expr);
11160 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11162 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11163 imm->desc ? imm->desc : ip->insn_mo->name,
11164 (unsigned long) imm_expr.X_add_number,
11165 (unsigned long) imm_expr.X_add_number);
11166 imm_expr.X_add_number &= imm->mask;
11168 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11170 imm_expr.X_op = O_absent;
11175 case 'A': /* ins/ext position, becomes LSB. */
11184 my_getExpression (&imm_expr, s);
11185 check_absolute_expr (ip, &imm_expr);
11186 if ((unsigned long) imm_expr.X_add_number < limlo
11187 || (unsigned long) imm_expr.X_add_number > limhi)
11189 as_bad (_("Improper position (%lu)"),
11190 (unsigned long) imm_expr.X_add_number);
11191 imm_expr.X_add_number = limlo;
11193 lastpos = imm_expr.X_add_number;
11194 INSERT_OPERAND (mips_opts.micromips,
11195 EXTLSB, *ip, imm_expr.X_add_number);
11196 imm_expr.X_op = O_absent;
11200 case 'B': /* ins size, becomes MSB. */
11209 my_getExpression (&imm_expr, s);
11210 check_absolute_expr (ip, &imm_expr);
11211 /* Check for negative input so that small negative numbers
11212 will not succeed incorrectly. The checks against
11213 (pos+size) transitively check "size" itself,
11214 assuming that "pos" is reasonable. */
11215 if ((long) imm_expr.X_add_number < 0
11216 || ((unsigned long) imm_expr.X_add_number
11218 || ((unsigned long) imm_expr.X_add_number
11219 + lastpos) > limhi)
11221 as_bad (_("Improper insert size (%lu, position %lu)"),
11222 (unsigned long) imm_expr.X_add_number,
11223 (unsigned long) lastpos);
11224 imm_expr.X_add_number = limlo - lastpos;
11226 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11227 lastpos + imm_expr.X_add_number - 1);
11228 imm_expr.X_op = O_absent;
11232 case 'C': /* ext size, becomes MSBD. */
11245 my_getExpression (&imm_expr, s);
11246 check_absolute_expr (ip, &imm_expr);
11247 /* Check for negative input so that small negative numbers
11248 will not succeed incorrectly. The checks against
11249 (pos+size) transitively check "size" itself,
11250 assuming that "pos" is reasonable. */
11251 if ((long) imm_expr.X_add_number < 0
11252 || ((unsigned long) imm_expr.X_add_number
11254 || ((unsigned long) imm_expr.X_add_number
11255 + lastpos) > limhi)
11257 as_bad (_("Improper extract size (%lu, position %lu)"),
11258 (unsigned long) imm_expr.X_add_number,
11259 (unsigned long) lastpos);
11260 imm_expr.X_add_number = limlo - lastpos;
11262 INSERT_OPERAND (mips_opts.micromips,
11263 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11264 imm_expr.X_op = O_absent;
11269 /* +D is for disassembly only; never match. */
11273 /* "+I" is like "I", except that imm2_expr is used. */
11274 my_getExpression (&imm2_expr, s);
11275 if (imm2_expr.X_op != O_big
11276 && imm2_expr.X_op != O_constant)
11277 insn_error = _("absolute expression required");
11278 if (HAVE_32BIT_GPRS)
11279 normalize_constant_expr (&imm2_expr);
11283 case 'T': /* Coprocessor register. */
11284 gas_assert (!mips_opts.micromips);
11285 /* +T is for disassembly only; never match. */
11288 case 't': /* Coprocessor register number. */
11289 gas_assert (!mips_opts.micromips);
11290 if (s[0] == '$' && ISDIGIT (s[1]))
11300 while (ISDIGIT (*s));
11302 as_bad (_("Invalid register number (%d)"), regno);
11305 INSERT_OPERAND (0, RT, *ip, regno);
11310 as_bad (_("Invalid coprocessor 0 register number"));
11314 /* bbit[01] and bbit[01]32 bit index. Give error if index
11315 is not in the valid range. */
11316 gas_assert (!mips_opts.micromips);
11317 my_getExpression (&imm_expr, s);
11318 check_absolute_expr (ip, &imm_expr);
11319 if ((unsigned) imm_expr.X_add_number > 31)
11321 as_bad (_("Improper bit index (%lu)"),
11322 (unsigned long) imm_expr.X_add_number);
11323 imm_expr.X_add_number = 0;
11325 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11326 imm_expr.X_op = O_absent;
11331 /* bbit[01] bit index when bbit is used but we generate
11332 bbit[01]32 because the index is over 32. Move to the
11333 next candidate if index is not in the valid range. */
11334 gas_assert (!mips_opts.micromips);
11335 my_getExpression (&imm_expr, s);
11336 check_absolute_expr (ip, &imm_expr);
11337 if ((unsigned) imm_expr.X_add_number < 32
11338 || (unsigned) imm_expr.X_add_number > 63)
11340 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11341 imm_expr.X_op = O_absent;
11346 /* cins, cins32, exts and exts32 position field. Give error
11347 if it's not in the valid range. */
11348 gas_assert (!mips_opts.micromips);
11349 my_getExpression (&imm_expr, s);
11350 check_absolute_expr (ip, &imm_expr);
11351 if ((unsigned) imm_expr.X_add_number > 31)
11353 as_bad (_("Improper position (%lu)"),
11354 (unsigned long) imm_expr.X_add_number);
11355 imm_expr.X_add_number = 0;
11357 /* Make the pos explicit to simplify +S. */
11358 lastpos = imm_expr.X_add_number + 32;
11359 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11360 imm_expr.X_op = O_absent;
11365 /* cins, cins32, exts and exts32 position field. Move to
11366 the next candidate if it's not in the valid range. */
11367 gas_assert (!mips_opts.micromips);
11368 my_getExpression (&imm_expr, s);
11369 check_absolute_expr (ip, &imm_expr);
11370 if ((unsigned) imm_expr.X_add_number < 32
11371 || (unsigned) imm_expr.X_add_number > 63)
11373 lastpos = imm_expr.X_add_number;
11374 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11375 imm_expr.X_op = O_absent;
11380 /* cins and exts length-minus-one field. */
11381 gas_assert (!mips_opts.micromips);
11382 my_getExpression (&imm_expr, s);
11383 check_absolute_expr (ip, &imm_expr);
11384 if ((unsigned long) imm_expr.X_add_number > 31)
11386 as_bad (_("Improper size (%lu)"),
11387 (unsigned long) imm_expr.X_add_number);
11388 imm_expr.X_add_number = 0;
11390 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11391 imm_expr.X_op = O_absent;
11396 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11397 length-minus-one field. */
11398 gas_assert (!mips_opts.micromips);
11399 my_getExpression (&imm_expr, s);
11400 check_absolute_expr (ip, &imm_expr);
11401 if ((long) imm_expr.X_add_number < 0
11402 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11404 as_bad (_("Improper size (%lu)"),
11405 (unsigned long) imm_expr.X_add_number);
11406 imm_expr.X_add_number = 0;
11408 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11409 imm_expr.X_op = O_absent;
11414 /* seqi/snei immediate field. */
11415 gas_assert (!mips_opts.micromips);
11416 my_getExpression (&imm_expr, s);
11417 check_absolute_expr (ip, &imm_expr);
11418 if ((long) imm_expr.X_add_number < -512
11419 || (long) imm_expr.X_add_number >= 512)
11421 as_bad (_("Improper immediate (%ld)"),
11422 (long) imm_expr.X_add_number);
11423 imm_expr.X_add_number = 0;
11425 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11426 imm_expr.X_op = O_absent;
11430 case 'a': /* 8-bit signed offset in bit 6 */
11431 gas_assert (!mips_opts.micromips);
11432 my_getExpression (&imm_expr, s);
11433 check_absolute_expr (ip, &imm_expr);
11434 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11435 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11436 if (imm_expr.X_add_number < min_range
11437 || imm_expr.X_add_number > max_range)
11439 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11440 (long) min_range, (long) max_range,
11441 (long) imm_expr.X_add_number);
11443 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11444 imm_expr.X_op = O_absent;
11448 case 'b': /* 8-bit signed offset in bit 3 */
11449 gas_assert (!mips_opts.micromips);
11450 my_getExpression (&imm_expr, s);
11451 check_absolute_expr (ip, &imm_expr);
11452 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11453 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11454 if (imm_expr.X_add_number < min_range
11455 || imm_expr.X_add_number > max_range)
11457 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11458 (long) min_range, (long) max_range,
11459 (long) imm_expr.X_add_number);
11461 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11462 imm_expr.X_op = O_absent;
11466 case 'c': /* 9-bit signed offset in bit 6 */
11467 gas_assert (!mips_opts.micromips);
11468 my_getExpression (&imm_expr, s);
11469 check_absolute_expr (ip, &imm_expr);
11470 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11471 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11472 /* We check the offset range before adjusted. */
11475 if (imm_expr.X_add_number < min_range
11476 || imm_expr.X_add_number > max_range)
11478 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11479 (long) min_range, (long) max_range,
11480 (long) imm_expr.X_add_number);
11482 if (imm_expr.X_add_number & 0xf)
11484 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11485 (long) imm_expr.X_add_number);
11487 /* Right shift 4 bits to adjust the offset operand. */
11488 INSERT_OPERAND (0, OFFSET_C, *ip,
11489 imm_expr.X_add_number >> 4);
11490 imm_expr.X_op = O_absent;
11495 gas_assert (!mips_opts.micromips);
11496 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11498 if (regno == AT && mips_opts.at)
11500 if (mips_opts.at == ATREG)
11501 as_warn (_("used $at without \".set noat\""));
11503 as_warn (_("used $%u with \".set at=$%u\""),
11504 regno, mips_opts.at);
11506 INSERT_OPERAND (0, RZ, *ip, regno);
11510 gas_assert (!mips_opts.micromips);
11511 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11513 INSERT_OPERAND (0, FZ, *ip, regno);
11517 as_bad (_("Internal error: bad %s opcode "
11518 "(unknown extension operand type `+%c'): %s %s"),
11519 mips_opts.micromips ? "microMIPS" : "MIPS",
11520 *args, insn->name, insn->args);
11521 /* Further processing is fruitless. */
11526 case '.': /* 10-bit offset. */
11527 gas_assert (mips_opts.micromips);
11528 case '~': /* 12-bit offset. */
11530 int shift = *args == '.' ? 9 : 11;
11533 /* Check whether there is only a single bracketed expression
11534 left. If so, it must be the base register and the
11535 constant must be zero. */
11536 if (*s == '(' && strchr (s + 1, '(') == 0)
11539 /* If this value won't fit into the offset, then go find
11540 a macro that will generate a 16- or 32-bit offset code
11542 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11543 if ((i == 0 && (imm_expr.X_op != O_constant
11544 || imm_expr.X_add_number >= 1 << shift
11545 || imm_expr.X_add_number < -1 << shift))
11548 imm_expr.X_op = O_absent;
11552 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11554 INSERT_OPERAND (mips_opts.micromips,
11555 OFFSET12, *ip, imm_expr.X_add_number);
11556 imm_expr.X_op = O_absent;
11561 case '<': /* must be at least one digit */
11563 * According to the manual, if the shift amount is greater
11564 * than 31 or less than 0, then the shift amount should be
11565 * mod 32. In reality the mips assembler issues an error.
11566 * We issue a warning and mask out all but the low 5 bits.
11568 my_getExpression (&imm_expr, s);
11569 check_absolute_expr (ip, &imm_expr);
11570 if ((unsigned long) imm_expr.X_add_number > 31)
11571 as_warn (_("Improper shift amount (%lu)"),
11572 (unsigned long) imm_expr.X_add_number);
11573 INSERT_OPERAND (mips_opts.micromips,
11574 SHAMT, *ip, imm_expr.X_add_number);
11575 imm_expr.X_op = O_absent;
11579 case '>': /* shift amount minus 32 */
11580 my_getExpression (&imm_expr, s);
11581 check_absolute_expr (ip, &imm_expr);
11582 if ((unsigned long) imm_expr.X_add_number < 32
11583 || (unsigned long) imm_expr.X_add_number > 63)
11585 INSERT_OPERAND (mips_opts.micromips,
11586 SHAMT, *ip, imm_expr.X_add_number - 32);
11587 imm_expr.X_op = O_absent;
11591 case 'k': /* CACHE code. */
11592 case 'h': /* PREFX code. */
11593 case '1': /* SYNC type. */
11594 my_getExpression (&imm_expr, s);
11595 check_absolute_expr (ip, &imm_expr);
11596 if ((unsigned long) imm_expr.X_add_number > 31)
11597 as_warn (_("Invalid value for `%s' (%lu)"),
11599 (unsigned long) imm_expr.X_add_number);
11603 if (mips_fix_cn63xxp1
11604 && !mips_opts.micromips
11605 && strcmp ("pref", insn->name) == 0)
11606 switch (imm_expr.X_add_number)
11615 case 31: /* These are ok. */
11618 default: /* The rest must be changed to 28. */
11619 imm_expr.X_add_number = 28;
11622 INSERT_OPERAND (mips_opts.micromips,
11623 CACHE, *ip, imm_expr.X_add_number);
11626 INSERT_OPERAND (mips_opts.micromips,
11627 PREFX, *ip, imm_expr.X_add_number);
11630 INSERT_OPERAND (mips_opts.micromips,
11631 STYPE, *ip, imm_expr.X_add_number);
11634 imm_expr.X_op = O_absent;
11638 case 'c': /* BREAK code. */
11640 unsigned long mask = (mips_opts.micromips
11641 ? MICROMIPSOP_MASK_CODE
11644 my_getExpression (&imm_expr, s);
11645 check_absolute_expr (ip, &imm_expr);
11646 if ((unsigned long) imm_expr.X_add_number > mask)
11647 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11649 mask, (unsigned long) imm_expr.X_add_number);
11650 INSERT_OPERAND (mips_opts.micromips,
11651 CODE, *ip, imm_expr.X_add_number);
11652 imm_expr.X_op = O_absent;
11657 case 'q': /* Lower BREAK code. */
11659 unsigned long mask = (mips_opts.micromips
11660 ? MICROMIPSOP_MASK_CODE2
11663 my_getExpression (&imm_expr, s);
11664 check_absolute_expr (ip, &imm_expr);
11665 if ((unsigned long) imm_expr.X_add_number > mask)
11666 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11668 mask, (unsigned long) imm_expr.X_add_number);
11669 INSERT_OPERAND (mips_opts.micromips,
11670 CODE2, *ip, imm_expr.X_add_number);
11671 imm_expr.X_op = O_absent;
11676 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11678 unsigned long mask = (mips_opts.micromips
11679 ? MICROMIPSOP_MASK_CODE10
11682 my_getExpression (&imm_expr, s);
11683 check_absolute_expr (ip, &imm_expr);
11684 if ((unsigned long) imm_expr.X_add_number > mask)
11685 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11687 mask, (unsigned long) imm_expr.X_add_number);
11688 if (mips_opts.micromips)
11689 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11691 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11692 imm_expr.X_op = O_absent;
11697 case 'C': /* 25- or 23-bit coprocessor code. */
11699 unsigned long mask = (mips_opts.micromips
11700 ? MICROMIPSOP_MASK_COPZ
11703 my_getExpression (&imm_expr, s);
11704 check_absolute_expr (ip, &imm_expr);
11705 if ((unsigned long) imm_expr.X_add_number > mask)
11706 as_warn (_("Coproccesor code > %u bits (%lu)"),
11707 mips_opts.micromips ? 23U : 25U,
11708 (unsigned long) imm_expr.X_add_number);
11709 INSERT_OPERAND (mips_opts.micromips,
11710 COPZ, *ip, imm_expr.X_add_number);
11711 imm_expr.X_op = O_absent;
11716 case 'J': /* 19-bit WAIT code. */
11717 gas_assert (!mips_opts.micromips);
11718 my_getExpression (&imm_expr, s);
11719 check_absolute_expr (ip, &imm_expr);
11720 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11722 as_warn (_("Illegal 19-bit code (%lu)"),
11723 (unsigned long) imm_expr.X_add_number);
11724 imm_expr.X_add_number &= OP_MASK_CODE19;
11726 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11727 imm_expr.X_op = O_absent;
11731 case 'P': /* Performance register. */
11732 gas_assert (!mips_opts.micromips);
11733 my_getExpression (&imm_expr, s);
11734 check_absolute_expr (ip, &imm_expr);
11735 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11736 as_warn (_("Invalid performance register (%lu)"),
11737 (unsigned long) imm_expr.X_add_number);
11738 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11739 imm_expr.X_op = O_absent;
11743 case 'G': /* Coprocessor destination register. */
11745 unsigned long opcode = ip->insn_opcode;
11746 unsigned long mask;
11747 unsigned int types;
11750 if (mips_opts.micromips)
11752 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11753 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11754 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11758 case 0x000000fc: /* mfc0 */
11759 case 0x000002fc: /* mtc0 */
11760 case 0x580000fc: /* dmfc0 */
11761 case 0x580002fc: /* dmtc0 */
11771 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11772 cop0 = opcode == OP_OP_COP0;
11774 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11775 ok = reg_lookup (&s, types, ®no);
11776 if (mips_opts.micromips)
11777 INSERT_OPERAND (1, RS, *ip, regno);
11779 INSERT_OPERAND (0, RD, *ip, regno);
11788 case 'y': /* ALNV.PS source register. */
11789 gas_assert (mips_opts.micromips);
11791 case 'x': /* Ignore register name. */
11792 case 'U': /* Destination register (CLO/CLZ). */
11793 case 'g': /* Coprocessor destination register. */
11794 gas_assert (!mips_opts.micromips);
11795 case 'b': /* Base register. */
11796 case 'd': /* Destination register. */
11797 case 's': /* Source register. */
11798 case 't': /* Target register. */
11799 case 'r': /* Both target and source. */
11800 case 'v': /* Both dest and source. */
11801 case 'w': /* Both dest and target. */
11802 case 'E': /* Coprocessor target register. */
11803 case 'K': /* RDHWR destination register. */
11804 case 'z': /* Must be zero register. */
11807 if (*args == 'E' || *args == 'K')
11808 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11811 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11812 if (regno == AT && mips_opts.at)
11814 if (mips_opts.at == ATREG)
11815 as_warn (_("Used $at without \".set noat\""));
11817 as_warn (_("Used $%u with \".set at=$%u\""),
11818 regno, mips_opts.at);
11828 if (c == 'r' || c == 'v' || c == 'w')
11835 /* 'z' only matches $0. */
11836 if (c == 'z' && regno != 0)
11839 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11841 if (regno == lastregno)
11844 = _("Source and destination must be different");
11847 if (regno == 31 && lastregno == 0xffffffff)
11850 = _("A destination register must be supplied");
11854 /* Now that we have assembled one operand, we use the args
11855 string to figure out where it goes in the instruction. */
11862 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11866 if (mips_opts.micromips)
11867 INSERT_OPERAND (1, RS, *ip, regno);
11869 INSERT_OPERAND (0, RD, *ip, regno);
11874 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11878 gas_assert (!mips_opts.micromips);
11879 INSERT_OPERAND (0, RD, *ip, regno);
11880 INSERT_OPERAND (0, RT, *ip, regno);
11886 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11890 gas_assert (mips_opts.micromips);
11891 INSERT_OPERAND (1, RS3, *ip, regno);
11895 /* This case exists because on the r3000 trunc
11896 expands into a macro which requires a gp
11897 register. On the r6000 or r4000 it is
11898 assembled into a single instruction which
11899 ignores the register. Thus the insn version
11900 is MIPS_ISA2 and uses 'x', and the macro
11901 version is MIPS_ISA1 and uses 't'. */
11905 /* This case is for the div instruction, which
11906 acts differently if the destination argument
11907 is $0. This only matches $0, and is checked
11908 outside the switch. */
11918 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11922 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11927 case 'O': /* MDMX alignment immediate constant. */
11928 gas_assert (!mips_opts.micromips);
11929 my_getExpression (&imm_expr, s);
11930 check_absolute_expr (ip, &imm_expr);
11931 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11932 as_warn (_("Improper align amount (%ld), using low bits"),
11933 (long) imm_expr.X_add_number);
11934 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11935 imm_expr.X_op = O_absent;
11939 case 'Q': /* MDMX vector, element sel, or const. */
11942 /* MDMX Immediate. */
11943 gas_assert (!mips_opts.micromips);
11944 my_getExpression (&imm_expr, s);
11945 check_absolute_expr (ip, &imm_expr);
11946 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
11947 as_warn (_("Invalid MDMX Immediate (%ld)"),
11948 (long) imm_expr.X_add_number);
11949 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
11950 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11951 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11953 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
11954 imm_expr.X_op = O_absent;
11958 /* Not MDMX Immediate. Fall through. */
11959 case 'X': /* MDMX destination register. */
11960 case 'Y': /* MDMX source register. */
11961 case 'Z': /* MDMX target register. */
11964 gas_assert (!mips_opts.micromips);
11965 case 'D': /* Floating point destination register. */
11966 case 'S': /* Floating point source register. */
11967 case 'T': /* Floating point target register. */
11968 case 'R': /* Floating point source register. */
11972 || (mips_opts.ase_mdmx
11973 && (ip->insn_mo->pinfo & FP_D)
11974 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11975 | INSN_COPROC_MEMORY_DELAY
11976 | INSN_LOAD_COPROC_DELAY
11977 | INSN_LOAD_MEMORY_DELAY
11978 | INSN_STORE_MEMORY))))
11979 rtype |= RTYPE_VEC;
11981 if (reg_lookup (&s, rtype, ®no))
11983 if ((regno & 1) != 0
11985 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
11986 as_warn (_("Float register should be even, was %d"),
11994 if (c == 'V' || c == 'W')
12005 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12011 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12015 /* This is like 'Z', but also needs to fix the MDMX
12016 vector/scalar select bits. Note that the
12017 scalar immediate case is handled above. */
12020 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12021 int max_el = (is_qh ? 3 : 7);
12023 my_getExpression(&imm_expr, s);
12024 check_absolute_expr (ip, &imm_expr);
12026 if (imm_expr.X_add_number > max_el)
12027 as_bad (_("Bad element selector %ld"),
12028 (long) imm_expr.X_add_number);
12029 imm_expr.X_add_number &= max_el;
12030 ip->insn_opcode |= (imm_expr.X_add_number
12033 imm_expr.X_op = O_absent;
12035 as_warn (_("Expecting ']' found '%s'"), s);
12041 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12042 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12045 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12048 /* Fall through. */
12052 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12056 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12066 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12070 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12076 my_getExpression (&imm_expr, s);
12077 if (imm_expr.X_op != O_big
12078 && imm_expr.X_op != O_constant)
12079 insn_error = _("absolute expression required");
12080 if (HAVE_32BIT_GPRS)
12081 normalize_constant_expr (&imm_expr);
12086 my_getExpression (&offset_expr, s);
12087 normalize_address_expr (&offset_expr);
12088 *imm_reloc = BFD_RELOC_32;
12101 unsigned char temp[8];
12103 unsigned int length;
12108 /* These only appear as the last operand in an
12109 instruction, and every instruction that accepts
12110 them in any variant accepts them in all variants.
12111 This means we don't have to worry about backing out
12112 any changes if the instruction does not match.
12114 The difference between them is the size of the
12115 floating point constant and where it goes. For 'F'
12116 and 'L' the constant is 64 bits; for 'f' and 'l' it
12117 is 32 bits. Where the constant is placed is based
12118 on how the MIPS assembler does things:
12121 f -- immediate value
12124 The .lit4 and .lit8 sections are only used if
12125 permitted by the -G argument.
12127 The code below needs to know whether the target register
12128 is 32 or 64 bits wide. It relies on the fact 'f' and
12129 'F' are used with GPR-based instructions and 'l' and
12130 'L' are used with FPR-based instructions. */
12132 f64 = *args == 'F' || *args == 'L';
12133 using_gprs = *args == 'F' || *args == 'f';
12135 save_in = input_line_pointer;
12136 input_line_pointer = s;
12137 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12139 s = input_line_pointer;
12140 input_line_pointer = save_in;
12141 if (err != NULL && *err != '\0')
12143 as_bad (_("Bad floating point constant: %s"), err);
12144 memset (temp, '\0', sizeof temp);
12145 length = f64 ? 8 : 4;
12148 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12152 && (g_switch_value < 4
12153 || (temp[0] == 0 && temp[1] == 0)
12154 || (temp[2] == 0 && temp[3] == 0))))
12156 imm_expr.X_op = O_constant;
12157 if (!target_big_endian)
12158 imm_expr.X_add_number = bfd_getl32 (temp);
12160 imm_expr.X_add_number = bfd_getb32 (temp);
12162 else if (length > 4
12163 && !mips_disable_float_construction
12164 /* Constants can only be constructed in GPRs and
12165 copied to FPRs if the GPRs are at least as wide
12166 as the FPRs. Force the constant into memory if
12167 we are using 64-bit FPRs but the GPRs are only
12170 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12171 && ((temp[0] == 0 && temp[1] == 0)
12172 || (temp[2] == 0 && temp[3] == 0))
12173 && ((temp[4] == 0 && temp[5] == 0)
12174 || (temp[6] == 0 && temp[7] == 0)))
12176 /* The value is simple enough to load with a couple of
12177 instructions. If using 32-bit registers, set
12178 imm_expr to the high order 32 bits and offset_expr to
12179 the low order 32 bits. Otherwise, set imm_expr to
12180 the entire 64 bit constant. */
12181 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12183 imm_expr.X_op = O_constant;
12184 offset_expr.X_op = O_constant;
12185 if (!target_big_endian)
12187 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12188 offset_expr.X_add_number = bfd_getl32 (temp);
12192 imm_expr.X_add_number = bfd_getb32 (temp);
12193 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12195 if (offset_expr.X_add_number == 0)
12196 offset_expr.X_op = O_absent;
12198 else if (sizeof (imm_expr.X_add_number) > 4)
12200 imm_expr.X_op = O_constant;
12201 if (!target_big_endian)
12202 imm_expr.X_add_number = bfd_getl64 (temp);
12204 imm_expr.X_add_number = bfd_getb64 (temp);
12208 imm_expr.X_op = O_big;
12209 imm_expr.X_add_number = 4;
12210 if (!target_big_endian)
12212 generic_bignum[0] = bfd_getl16 (temp);
12213 generic_bignum[1] = bfd_getl16 (temp + 2);
12214 generic_bignum[2] = bfd_getl16 (temp + 4);
12215 generic_bignum[3] = bfd_getl16 (temp + 6);
12219 generic_bignum[0] = bfd_getb16 (temp + 6);
12220 generic_bignum[1] = bfd_getb16 (temp + 4);
12221 generic_bignum[2] = bfd_getb16 (temp + 2);
12222 generic_bignum[3] = bfd_getb16 (temp);
12228 const char *newname;
12231 /* Switch to the right section. */
12233 subseg = now_subseg;
12236 default: /* unused default case avoids warnings. */
12238 newname = RDATA_SECTION_NAME;
12239 if (g_switch_value >= 8)
12243 newname = RDATA_SECTION_NAME;
12246 gas_assert (g_switch_value >= 4);
12250 new_seg = subseg_new (newname, (subsegT) 0);
12252 bfd_set_section_flags (stdoutput, new_seg,
12257 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12258 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12259 record_alignment (new_seg, 4);
12261 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12262 if (seg == now_seg)
12263 as_bad (_("Can't use floating point insn in this section"));
12265 /* Set the argument to the current address in the
12267 offset_expr.X_op = O_symbol;
12268 offset_expr.X_add_symbol = symbol_temp_new_now ();
12269 offset_expr.X_add_number = 0;
12271 /* Put the floating point number into the section. */
12272 p = frag_more ((int) length);
12273 memcpy (p, temp, length);
12275 /* Switch back to the original section. */
12276 subseg_set (seg, subseg);
12281 case 'i': /* 16-bit unsigned immediate. */
12282 case 'j': /* 16-bit signed immediate. */
12283 *imm_reloc = BFD_RELOC_LO16;
12284 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12287 offsetT minval, maxval;
12289 more = (insn + 1 < past
12290 && strcmp (insn->name, insn[1].name) == 0);
12292 /* If the expression was written as an unsigned number,
12293 only treat it as signed if there are no more
12297 && sizeof (imm_expr.X_add_number) <= 4
12298 && imm_expr.X_op == O_constant
12299 && imm_expr.X_add_number < 0
12300 && imm_expr.X_unsigned
12301 && HAVE_64BIT_GPRS)
12304 /* For compatibility with older assemblers, we accept
12305 0x8000-0xffff as signed 16-bit numbers when only
12306 signed numbers are allowed. */
12308 minval = 0, maxval = 0xffff;
12310 minval = -0x8000, maxval = 0x7fff;
12312 minval = -0x8000, maxval = 0xffff;
12314 if (imm_expr.X_op != O_constant
12315 || imm_expr.X_add_number < minval
12316 || imm_expr.X_add_number > maxval)
12320 if (imm_expr.X_op == O_constant
12321 || imm_expr.X_op == O_big)
12322 as_bad (_("Expression out of range"));
12328 case 'o': /* 16-bit offset. */
12329 offset_reloc[0] = BFD_RELOC_LO16;
12330 offset_reloc[1] = BFD_RELOC_UNUSED;
12331 offset_reloc[2] = BFD_RELOC_UNUSED;
12333 /* Check whether there is only a single bracketed expression
12334 left. If so, it must be the base register and the
12335 constant must be zero. */
12336 if (*s == '(' && strchr (s + 1, '(') == 0)
12338 offset_expr.X_op = O_constant;
12339 offset_expr.X_add_number = 0;
12343 /* If this value won't fit into a 16 bit offset, then go
12344 find a macro that will generate the 32 bit offset
12346 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12347 && (offset_expr.X_op != O_constant
12348 || offset_expr.X_add_number >= 0x8000
12349 || offset_expr.X_add_number < -0x8000))
12355 case 'p': /* PC-relative offset. */
12356 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12357 my_getExpression (&offset_expr, s);
12361 case 'u': /* Upper 16 bits. */
12362 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12363 && imm_expr.X_op == O_constant
12364 && (imm_expr.X_add_number < 0
12365 || imm_expr.X_add_number >= 0x10000))
12366 as_bad (_("lui expression (%lu) not in range 0..65535"),
12367 (unsigned long) imm_expr.X_add_number);
12371 case 'a': /* 26-bit address. */
12372 *offset_reloc = BFD_RELOC_MIPS_JMP;
12373 my_getExpression (&offset_expr, s);
12377 case 'N': /* 3-bit branch condition code. */
12378 case 'M': /* 3-bit compare condition code. */
12380 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12381 rtype |= RTYPE_FCC;
12382 if (!reg_lookup (&s, rtype, ®no))
12384 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12385 || strcmp (str + strlen (str) - 5, "any2f") == 0
12386 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12387 && (regno & 1) != 0)
12388 as_warn (_("Condition code register should be even for %s, "
12391 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12392 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12393 && (regno & 3) != 0)
12394 as_warn (_("Condition code register should be 0 or 4 for %s, "
12398 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12400 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12404 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12415 while (ISDIGIT (*s));
12418 c = 8; /* Invalid sel value. */
12421 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12422 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12426 gas_assert (!mips_opts.micromips);
12427 /* Must be at least one digit. */
12428 my_getExpression (&imm_expr, s);
12429 check_absolute_expr (ip, &imm_expr);
12431 if ((unsigned long) imm_expr.X_add_number
12432 > (unsigned long) OP_MASK_VECBYTE)
12434 as_bad (_("bad byte vector index (%ld)"),
12435 (long) imm_expr.X_add_number);
12436 imm_expr.X_add_number = 0;
12439 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12440 imm_expr.X_op = O_absent;
12445 gas_assert (!mips_opts.micromips);
12446 my_getExpression (&imm_expr, s);
12447 check_absolute_expr (ip, &imm_expr);
12449 if ((unsigned long) imm_expr.X_add_number
12450 > (unsigned long) OP_MASK_VECALIGN)
12452 as_bad (_("bad byte vector index (%ld)"),
12453 (long) imm_expr.X_add_number);
12454 imm_expr.X_add_number = 0;
12457 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12458 imm_expr.X_op = O_absent;
12462 case 'm': /* Opcode extension character. */
12463 gas_assert (mips_opts.micromips);
12468 if (strncmp (s, "$pc", 3) == 0)
12496 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12497 if (regno == AT && mips_opts.at)
12499 if (mips_opts.at == ATREG)
12500 as_warn (_("Used $at without \".set noat\""));
12502 as_warn (_("Used $%u with \".set at=$%u\""),
12503 regno, mips_opts.at);
12509 gas_assert (args[1] == ',');
12515 gas_assert (args[1] == ',');
12517 continue; /* Nothing to do. */
12523 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12525 if (regno == lastregno)
12528 = _("Source and destination must be different");
12531 if (regno == 31 && lastregno == 0xffffffff)
12534 = _("A destination register must be supplied");
12545 gas_assert (args[1] == ',');
12552 gas_assert (args[1] == ',');
12555 continue; /* Nothing to do. */
12559 /* Make sure regno is the same as lastregno. */
12560 if (c == 't' && regno != lastregno)
12563 /* Make sure regno is the same as destregno. */
12564 if (c == 'x' && regno != destregno)
12567 /* We need to save regno, before regno maps to the
12568 microMIPS register encoding. */
12578 regno = ILLEGAL_REG;
12582 regno = mips32_to_micromips_reg_b_map[regno];
12586 regno = mips32_to_micromips_reg_c_map[regno];
12590 regno = mips32_to_micromips_reg_d_map[regno];
12594 regno = mips32_to_micromips_reg_e_map[regno];
12598 regno = mips32_to_micromips_reg_f_map[regno];
12602 regno = mips32_to_micromips_reg_g_map[regno];
12606 regno = mips32_to_micromips_reg_h_map[regno];
12610 switch (EXTRACT_OPERAND (1, MI, *ip))
12615 else if (regno == 22)
12617 else if (regno == 5)
12619 else if (regno == 6)
12621 else if (regno == 7)
12624 regno = ILLEGAL_REG;
12630 else if (regno == 7)
12633 regno = ILLEGAL_REG;
12640 regno = ILLEGAL_REG;
12644 regno = ILLEGAL_REG;
12650 regno = mips32_to_micromips_reg_l_map[regno];
12654 regno = mips32_to_micromips_reg_m_map[regno];
12658 regno = mips32_to_micromips_reg_n_map[regno];
12662 regno = mips32_to_micromips_reg_q_map[regno];
12667 regno = ILLEGAL_REG;
12672 regno = ILLEGAL_REG;
12677 regno = ILLEGAL_REG;
12680 case 'j': /* Do nothing. */
12690 if (regno == ILLEGAL_REG)
12696 INSERT_OPERAND (1, MB, *ip, regno);
12700 INSERT_OPERAND (1, MC, *ip, regno);
12704 INSERT_OPERAND (1, MD, *ip, regno);
12708 INSERT_OPERAND (1, ME, *ip, regno);
12712 INSERT_OPERAND (1, MF, *ip, regno);
12716 INSERT_OPERAND (1, MG, *ip, regno);
12720 INSERT_OPERAND (1, MH, *ip, regno);
12724 INSERT_OPERAND (1, MI, *ip, regno);
12728 INSERT_OPERAND (1, MJ, *ip, regno);
12732 INSERT_OPERAND (1, ML, *ip, regno);
12736 INSERT_OPERAND (1, MM, *ip, regno);
12740 INSERT_OPERAND (1, MN, *ip, regno);
12744 INSERT_OPERAND (1, MP, *ip, regno);
12748 INSERT_OPERAND (1, MQ, *ip, regno);
12751 case 'a': /* Do nothing. */
12752 case 's': /* Do nothing. */
12753 case 't': /* Do nothing. */
12754 case 'x': /* Do nothing. */
12755 case 'y': /* Do nothing. */
12756 case 'z': /* Do nothing. */
12766 bfd_reloc_code_real_type r[3];
12770 /* Check whether there is only a single bracketed
12771 expression left. If so, it must be the base register
12772 and the constant must be zero. */
12773 if (*s == '(' && strchr (s + 1, '(') == 0)
12775 INSERT_OPERAND (1, IMMA, *ip, 0);
12779 if (my_getSmallExpression (&ep, r, s) > 0
12780 || !expr_const_in_range (&ep, -64, 64, 2))
12783 imm = ep.X_add_number >> 2;
12784 INSERT_OPERAND (1, IMMA, *ip, imm);
12791 bfd_reloc_code_real_type r[3];
12795 if (my_getSmallExpression (&ep, r, s) > 0
12796 || ep.X_op != O_constant)
12799 for (imm = 0; imm < 8; imm++)
12800 if (micromips_imm_b_map[imm] == ep.X_add_number)
12805 INSERT_OPERAND (1, IMMB, *ip, imm);
12812 bfd_reloc_code_real_type r[3];
12816 if (my_getSmallExpression (&ep, r, s) > 0
12817 || ep.X_op != O_constant)
12820 for (imm = 0; imm < 16; imm++)
12821 if (micromips_imm_c_map[imm] == ep.X_add_number)
12826 INSERT_OPERAND (1, IMMC, *ip, imm);
12831 case 'D': /* pc relative offset */
12832 case 'E': /* pc relative offset */
12833 my_getExpression (&offset_expr, s);
12834 if (offset_expr.X_op == O_register)
12837 if (!forced_insn_length)
12838 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12840 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12842 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12848 bfd_reloc_code_real_type r[3];
12852 if (my_getSmallExpression (&ep, r, s) > 0
12853 || !expr_const_in_range (&ep, 0, 16, 0))
12856 imm = ep.X_add_number;
12857 INSERT_OPERAND (1, IMMF, *ip, imm);
12864 bfd_reloc_code_real_type r[3];
12868 /* Check whether there is only a single bracketed
12869 expression left. If so, it must be the base register
12870 and the constant must be zero. */
12871 if (*s == '(' && strchr (s + 1, '(') == 0)
12873 INSERT_OPERAND (1, IMMG, *ip, 0);
12877 if (my_getSmallExpression (&ep, r, s) > 0
12878 || !expr_const_in_range (&ep, -1, 15, 0))
12881 imm = ep.X_add_number & 15;
12882 INSERT_OPERAND (1, IMMG, *ip, imm);
12889 bfd_reloc_code_real_type r[3];
12893 /* Check whether there is only a single bracketed
12894 expression left. If so, it must be the base register
12895 and the constant must be zero. */
12896 if (*s == '(' && strchr (s + 1, '(') == 0)
12898 INSERT_OPERAND (1, IMMH, *ip, 0);
12902 if (my_getSmallExpression (&ep, r, s) > 0
12903 || !expr_const_in_range (&ep, 0, 16, 1))
12906 imm = ep.X_add_number >> 1;
12907 INSERT_OPERAND (1, IMMH, *ip, imm);
12914 bfd_reloc_code_real_type r[3];
12918 if (my_getSmallExpression (&ep, r, s) > 0
12919 || !expr_const_in_range (&ep, -1, 127, 0))
12922 imm = ep.X_add_number & 127;
12923 INSERT_OPERAND (1, IMMI, *ip, imm);
12930 bfd_reloc_code_real_type r[3];
12934 /* Check whether there is only a single bracketed
12935 expression left. If so, it must be the base register
12936 and the constant must be zero. */
12937 if (*s == '(' && strchr (s + 1, '(') == 0)
12939 INSERT_OPERAND (1, IMMJ, *ip, 0);
12943 if (my_getSmallExpression (&ep, r, s) > 0
12944 || !expr_const_in_range (&ep, 0, 16, 2))
12947 imm = ep.X_add_number >> 2;
12948 INSERT_OPERAND (1, IMMJ, *ip, imm);
12955 bfd_reloc_code_real_type r[3];
12959 /* Check whether there is only a single bracketed
12960 expression left. If so, it must be the base register
12961 and the constant must be zero. */
12962 if (*s == '(' && strchr (s + 1, '(') == 0)
12964 INSERT_OPERAND (1, IMML, *ip, 0);
12968 if (my_getSmallExpression (&ep, r, s) > 0
12969 || !expr_const_in_range (&ep, 0, 16, 0))
12972 imm = ep.X_add_number;
12973 INSERT_OPERAND (1, IMML, *ip, imm);
12980 bfd_reloc_code_real_type r[3];
12984 if (my_getSmallExpression (&ep, r, s) > 0
12985 || !expr_const_in_range (&ep, 1, 9, 0))
12988 imm = ep.X_add_number & 7;
12989 INSERT_OPERAND (1, IMMM, *ip, imm);
12994 case 'N': /* Register list for lwm and swm. */
12996 /* A comma-separated list of registers and/or
12997 dash-separated contiguous ranges including
12998 both ra and a set of one or more registers
12999 starting at s0 up to s3 which have to be
13006 and any permutations of these. */
13007 unsigned int reglist;
13010 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13013 if ((reglist & 0xfff1ffff) != 0x80010000)
13016 reglist = (reglist >> 17) & 7;
13018 if ((reglist & -reglist) != reglist)
13021 imm = ffs (reglist) - 1;
13022 INSERT_OPERAND (1, IMMN, *ip, imm);
13026 case 'O': /* sdbbp 4-bit code. */
13028 bfd_reloc_code_real_type r[3];
13032 if (my_getSmallExpression (&ep, r, s) > 0
13033 || !expr_const_in_range (&ep, 0, 16, 0))
13036 imm = ep.X_add_number;
13037 INSERT_OPERAND (1, IMMO, *ip, imm);
13044 bfd_reloc_code_real_type r[3];
13048 if (my_getSmallExpression (&ep, r, s) > 0
13049 || !expr_const_in_range (&ep, 0, 32, 2))
13052 imm = ep.X_add_number >> 2;
13053 INSERT_OPERAND (1, IMMP, *ip, imm);
13060 bfd_reloc_code_real_type r[3];
13064 if (my_getSmallExpression (&ep, r, s) > 0
13065 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13068 imm = ep.X_add_number >> 2;
13069 INSERT_OPERAND (1, IMMQ, *ip, imm);
13076 bfd_reloc_code_real_type r[3];
13080 /* Check whether there is only a single bracketed
13081 expression left. If so, it must be the base register
13082 and the constant must be zero. */
13083 if (*s == '(' && strchr (s + 1, '(') == 0)
13085 INSERT_OPERAND (1, IMMU, *ip, 0);
13089 if (my_getSmallExpression (&ep, r, s) > 0
13090 || !expr_const_in_range (&ep, 0, 32, 2))
13093 imm = ep.X_add_number >> 2;
13094 INSERT_OPERAND (1, IMMU, *ip, imm);
13101 bfd_reloc_code_real_type r[3];
13105 if (my_getSmallExpression (&ep, r, s) > 0
13106 || !expr_const_in_range (&ep, 0, 64, 2))
13109 imm = ep.X_add_number >> 2;
13110 INSERT_OPERAND (1, IMMW, *ip, imm);
13117 bfd_reloc_code_real_type r[3];
13121 if (my_getSmallExpression (&ep, r, s) > 0
13122 || !expr_const_in_range (&ep, -8, 8, 0))
13125 imm = ep.X_add_number;
13126 INSERT_OPERAND (1, IMMX, *ip, imm);
13133 bfd_reloc_code_real_type r[3];
13137 if (my_getSmallExpression (&ep, r, s) > 0
13138 || expr_const_in_range (&ep, -2, 2, 2)
13139 || !expr_const_in_range (&ep, -258, 258, 2))
13142 imm = ep.X_add_number >> 2;
13143 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13144 INSERT_OPERAND (1, IMMY, *ip, imm);
13151 bfd_reloc_code_real_type r[3];
13154 if (my_getSmallExpression (&ep, r, s) > 0
13155 || !expr_const_in_range (&ep, 0, 1, 0))
13162 as_bad (_("Internal error: bad microMIPS opcode "
13163 "(unknown extension operand type `m%c'): %s %s"),
13164 *args, insn->name, insn->args);
13165 /* Further processing is fruitless. */
13170 case 'n': /* Register list for 32-bit lwm and swm. */
13171 gas_assert (mips_opts.micromips);
13173 /* A comma-separated list of registers and/or
13174 dash-separated contiguous ranges including
13175 at least one of ra and a set of one or more
13176 registers starting at s0 up to s7 and then
13177 s8 which have to be consecutive, e.g.:
13185 and any permutations of these. */
13186 unsigned int reglist;
13190 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13193 if ((reglist & 0x3f00ffff) != 0)
13196 ra = (reglist >> 27) & 0x10;
13197 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13199 if ((reglist & -reglist) != reglist)
13202 imm = (ffs (reglist) - 1) | ra;
13203 INSERT_OPERAND (1, RT, *ip, imm);
13204 imm_expr.X_op = O_absent;
13208 case '|': /* 4-bit trap code. */
13209 gas_assert (mips_opts.micromips);
13210 my_getExpression (&imm_expr, s);
13211 check_absolute_expr (ip, &imm_expr);
13212 if ((unsigned long) imm_expr.X_add_number
13213 > MICROMIPSOP_MASK_TRAP)
13214 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13215 (unsigned long) imm_expr.X_add_number,
13216 ip->insn_mo->name);
13217 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13218 imm_expr.X_op = O_absent;
13223 as_bad (_("Bad char = '%c'\n"), *args);
13228 /* Args don't match. */
13230 insn_error = _("Illegal operands");
13231 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13236 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13238 gas_assert (firstinsn);
13239 need_delay_slot_ok = FALSE;
13248 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13250 /* This routine assembles an instruction into its binary format when
13251 assembling for the mips16. As a side effect, it sets one of the
13252 global variables imm_reloc or offset_reloc to the type of relocation
13253 to do if one of the operands is an address expression. It also sets
13254 forced_insn_length to the resulting instruction size in bytes if the
13255 user explicitly requested a small or extended instruction. */
13258 mips16_ip (char *str, struct mips_cl_insn *ip)
13262 struct mips_opcode *insn;
13264 unsigned int regno;
13265 unsigned int lastregno = 0;
13271 forced_insn_length = 0;
13273 for (s = str; ISLOWER (*s); ++s)
13285 if (s[1] == 't' && s[2] == ' ')
13288 forced_insn_length = 2;
13292 else if (s[1] == 'e' && s[2] == ' ')
13295 forced_insn_length = 4;
13299 /* Fall through. */
13301 insn_error = _("unknown opcode");
13305 if (mips_opts.noautoextend && !forced_insn_length)
13306 forced_insn_length = 2;
13308 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13310 insn_error = _("unrecognized opcode");
13319 gas_assert (strcmp (insn->name, str) == 0);
13321 ok = is_opcode_valid_16 (insn);
13324 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13325 && strcmp (insn->name, insn[1].name) == 0)
13334 static char buf[100];
13336 _("Opcode not supported on this processor: %s (%s)"),
13337 mips_cpu_info_from_arch (mips_opts.arch)->name,
13338 mips_cpu_info_from_isa (mips_opts.isa)->name);
13345 create_insn (ip, insn);
13346 imm_expr.X_op = O_absent;
13347 imm_reloc[0] = BFD_RELOC_UNUSED;
13348 imm_reloc[1] = BFD_RELOC_UNUSED;
13349 imm_reloc[2] = BFD_RELOC_UNUSED;
13350 imm2_expr.X_op = O_absent;
13351 offset_expr.X_op = O_absent;
13352 offset_reloc[0] = BFD_RELOC_UNUSED;
13353 offset_reloc[1] = BFD_RELOC_UNUSED;
13354 offset_reloc[2] = BFD_RELOC_UNUSED;
13355 for (args = insn->args; 1; ++args)
13362 /* In this switch statement we call break if we did not find
13363 a match, continue if we did find a match, or return if we
13372 /* Stuff the immediate value in now, if we can. */
13373 if (imm_expr.X_op == O_constant
13374 && *imm_reloc > BFD_RELOC_UNUSED
13375 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13376 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
13377 && insn->pinfo != INSN_MACRO)
13381 switch (*offset_reloc)
13383 case BFD_RELOC_MIPS16_HI16_S:
13384 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13387 case BFD_RELOC_MIPS16_HI16:
13388 tmp = imm_expr.X_add_number >> 16;
13391 case BFD_RELOC_MIPS16_LO16:
13392 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13396 case BFD_RELOC_UNUSED:
13397 tmp = imm_expr.X_add_number;
13404 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13405 *offset_reloc, tmp, forced_insn_length,
13407 imm_expr.X_op = O_absent;
13408 *imm_reloc = BFD_RELOC_UNUSED;
13409 *offset_reloc = BFD_RELOC_UNUSED;
13423 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13426 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13442 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13444 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13448 /* Fall through. */
13459 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13461 if (c == 'v' || c == 'w')
13464 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13466 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13477 if (c == 'v' || c == 'w')
13479 regno = mips16_to_32_reg_map[lastregno];
13493 regno = mips32_to_16_reg_map[regno];
13498 regno = ILLEGAL_REG;
13503 regno = ILLEGAL_REG;
13508 regno = ILLEGAL_REG;
13513 if (regno == AT && mips_opts.at)
13515 if (mips_opts.at == ATREG)
13516 as_warn (_("used $at without \".set noat\""));
13518 as_warn (_("used $%u with \".set at=$%u\""),
13519 regno, mips_opts.at);
13527 if (regno == ILLEGAL_REG)
13534 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13538 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13541 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13544 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13550 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13553 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13554 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13564 if (strncmp (s, "$pc", 3) == 0)
13581 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13584 if (imm_expr.X_op != O_constant)
13586 forced_insn_length = 4;
13587 ip->insn_opcode |= MIPS16_EXTEND;
13591 /* We need to relax this instruction. */
13592 *offset_reloc = *imm_reloc;
13593 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13598 *imm_reloc = BFD_RELOC_UNUSED;
13599 /* Fall through. */
13606 my_getExpression (&imm_expr, s);
13607 if (imm_expr.X_op == O_register)
13609 /* What we thought was an expression turned out to
13612 if (s[0] == '(' && args[1] == '(')
13614 /* It looks like the expression was omitted
13615 before a register indirection, which means
13616 that the expression is implicitly zero. We
13617 still set up imm_expr, so that we handle
13618 explicit extensions correctly. */
13619 imm_expr.X_op = O_constant;
13620 imm_expr.X_add_number = 0;
13621 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13628 /* We need to relax this instruction. */
13629 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13638 /* We use offset_reloc rather than imm_reloc for the PC
13639 relative operands. This lets macros with both
13640 immediate and address operands work correctly. */
13641 my_getExpression (&offset_expr, s);
13643 if (offset_expr.X_op == O_register)
13646 /* We need to relax this instruction. */
13647 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13651 case '6': /* break code */
13652 my_getExpression (&imm_expr, s);
13653 check_absolute_expr (ip, &imm_expr);
13654 if ((unsigned long) imm_expr.X_add_number > 63)
13655 as_warn (_("Invalid value for `%s' (%lu)"),
13657 (unsigned long) imm_expr.X_add_number);
13658 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13659 imm_expr.X_op = O_absent;
13663 case 'a': /* 26 bit address */
13664 my_getExpression (&offset_expr, s);
13666 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13667 ip->insn_opcode <<= 16;
13670 case 'l': /* register list for entry macro */
13671 case 'L': /* register list for exit macro */
13681 unsigned int freg, reg1, reg2;
13683 while (*s == ' ' || *s == ',')
13685 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13687 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13691 as_bad (_("can't parse register list"));
13701 if (!reg_lookup (&s, freg ? RTYPE_FPU
13702 : (RTYPE_GP | RTYPE_NUM), ®2))
13704 as_bad (_("invalid register list"));
13708 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13710 mask &= ~ (7 << 3);
13713 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13715 mask &= ~ (7 << 3);
13718 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13719 mask |= (reg2 - 3) << 3;
13720 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13721 mask |= (reg2 - 15) << 1;
13722 else if (reg1 == RA && reg2 == RA)
13726 as_bad (_("invalid register list"));
13730 /* The mask is filled in in the opcode table for the
13731 benefit of the disassembler. We remove it before
13732 applying the actual mask. */
13733 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13734 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13738 case 'm': /* Register list for save insn. */
13739 case 'M': /* Register list for restore insn. */
13741 int opcode = ip->insn_opcode;
13742 int framesz = 0, seen_framesz = 0;
13743 int nargs = 0, statics = 0, sregs = 0;
13747 unsigned int reg1, reg2;
13749 SKIP_SPACE_TABS (s);
13752 SKIP_SPACE_TABS (s);
13754 my_getExpression (&imm_expr, s);
13755 if (imm_expr.X_op == O_constant)
13757 /* Handle the frame size. */
13760 as_bad (_("more than one frame size in list"));
13764 framesz = imm_expr.X_add_number;
13765 imm_expr.X_op = O_absent;
13770 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13772 as_bad (_("can't parse register list"));
13784 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13787 as_bad (_("can't parse register list"));
13792 while (reg1 <= reg2)
13794 if (reg1 >= 4 && reg1 <= 7)
13798 nargs |= 1 << (reg1 - 4);
13800 /* statics $a0-$a3 */
13801 statics |= 1 << (reg1 - 4);
13803 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13806 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13808 else if (reg1 == 31)
13810 /* Add $ra to insn. */
13815 as_bad (_("unexpected register in list"));
13823 /* Encode args/statics combination. */
13824 if (nargs & statics)
13825 as_bad (_("arg/static registers overlap"));
13826 else if (nargs == 0xf)
13827 /* All $a0-$a3 are args. */
13828 opcode |= MIPS16_ALL_ARGS << 16;
13829 else if (statics == 0xf)
13830 /* All $a0-$a3 are statics. */
13831 opcode |= MIPS16_ALL_STATICS << 16;
13834 int narg = 0, nstat = 0;
13836 /* Count arg registers. */
13837 while (nargs & 0x1)
13843 as_bad (_("invalid arg register list"));
13845 /* Count static registers. */
13846 while (statics & 0x8)
13848 statics = (statics << 1) & 0xf;
13852 as_bad (_("invalid static register list"));
13854 /* Encode args/statics. */
13855 opcode |= ((narg << 2) | nstat) << 16;
13858 /* Encode $s0/$s1. */
13859 if (sregs & (1 << 0)) /* $s0 */
13861 if (sregs & (1 << 1)) /* $s1 */
13867 /* Count regs $s2-$s8. */
13875 as_bad (_("invalid static register list"));
13876 /* Encode $s2-$s8. */
13877 opcode |= nsreg << 24;
13880 /* Encode frame size. */
13882 as_bad (_("missing frame size"));
13883 else if ((framesz & 7) != 0 || framesz < 0
13884 || framesz > 0xff * 8)
13885 as_bad (_("invalid frame size"));
13886 else if (framesz != 128 || (opcode >> 16) != 0)
13889 opcode |= (((framesz & 0xf0) << 16)
13890 | (framesz & 0x0f));
13893 /* Finally build the instruction. */
13894 if ((opcode >> 16) != 0 || framesz == 0)
13895 opcode |= MIPS16_EXTEND;
13896 ip->insn_opcode = opcode;
13900 case 'e': /* extend code */
13901 my_getExpression (&imm_expr, s);
13902 check_absolute_expr (ip, &imm_expr);
13903 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13905 as_warn (_("Invalid value for `%s' (%lu)"),
13907 (unsigned long) imm_expr.X_add_number);
13908 imm_expr.X_add_number &= 0x7ff;
13910 ip->insn_opcode |= imm_expr.X_add_number;
13911 imm_expr.X_op = O_absent;
13921 /* Args don't match. */
13922 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13923 strcmp (insn->name, insn[1].name) == 0)
13930 insn_error = _("illegal operands");
13936 /* This structure holds information we know about a mips16 immediate
13939 struct mips16_immed_operand
13941 /* The type code used in the argument string in the opcode table. */
13943 /* The number of bits in the short form of the opcode. */
13945 /* The number of bits in the extended form of the opcode. */
13947 /* The amount by which the short form is shifted when it is used;
13948 for example, the sw instruction has a shift count of 2. */
13950 /* The amount by which the short form is shifted when it is stored
13951 into the instruction code. */
13953 /* Non-zero if the short form is unsigned. */
13955 /* Non-zero if the extended form is unsigned. */
13957 /* Non-zero if the value is PC relative. */
13961 /* The mips16 immediate operand types. */
13963 static const struct mips16_immed_operand mips16_immed_operands[] =
13965 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13966 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13967 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13968 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13969 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13970 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13971 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13972 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13973 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13974 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13975 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13976 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13977 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13978 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13979 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13980 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13981 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13982 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13983 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13984 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13985 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13988 #define MIPS16_NUM_IMMED \
13989 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13991 /* Install immediate value VAL into MIPS16 instruction *INSN,
13992 extending it if necessary. The instruction in *INSN may
13993 already be extended.
13995 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13996 if none. In the former case, VAL is a 16-bit number with no
13997 defined signedness.
13999 TYPE is the type of the immediate field. USER_INSN_LENGTH
14000 is the length that the user requested, or 0 if none. */
14003 mips16_immed (char *file, unsigned int line, int type,
14004 bfd_reloc_code_real_type reloc, offsetT val,
14005 unsigned int user_insn_length, unsigned long *insn)
14007 const struct mips16_immed_operand *op;
14008 int mintiny, maxtiny;
14010 op = mips16_immed_operands;
14011 while (op->type != type)
14014 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14019 if (type == '<' || type == '>' || type == '[' || type == ']')
14022 maxtiny = 1 << op->nbits;
14027 maxtiny = (1 << op->nbits) - 1;
14029 if (reloc != BFD_RELOC_UNUSED)
14034 mintiny = - (1 << (op->nbits - 1));
14035 maxtiny = (1 << (op->nbits - 1)) - 1;
14036 if (reloc != BFD_RELOC_UNUSED)
14037 val = SEXT_16BIT (val);
14040 /* Branch offsets have an implicit 0 in the lowest bit. */
14041 if (type == 'p' || type == 'q')
14044 if ((val & ((1 << op->shift) - 1)) != 0
14045 || val < (mintiny << op->shift)
14046 || val > (maxtiny << op->shift))
14048 /* We need an extended instruction. */
14049 if (user_insn_length == 2)
14050 as_bad_where (file, line, _("invalid unextended operand value"));
14052 *insn |= MIPS16_EXTEND;
14054 else if (user_insn_length == 4)
14056 /* The operand doesn't force an unextended instruction to be extended.
14057 Warn if the user wanted an extended instruction anyway. */
14058 *insn |= MIPS16_EXTEND;
14059 as_warn_where (file, line,
14060 _("extended operand requested but not required"));
14063 if (mips16_opcode_length (*insn) == 2)
14067 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14068 insnval <<= op->op_shift;
14073 long minext, maxext;
14076 if (reloc == BFD_RELOC_UNUSED)
14081 maxext = (1 << op->extbits) - 1;
14085 minext = - (1 << (op->extbits - 1));
14086 maxext = (1 << (op->extbits - 1)) - 1;
14088 if (val < minext || val > maxext)
14089 as_bad_where (file, line,
14090 _("operand value out of range for instruction"));
14093 if (op->extbits == 16)
14095 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14098 else if (op->extbits == 15)
14100 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14105 extval = ((val & 0x1f) << 6) | (val & 0x20);
14109 *insn |= (extval << 16) | val;
14113 struct percent_op_match
14116 bfd_reloc_code_real_type reloc;
14119 static const struct percent_op_match mips_percent_op[] =
14121 {"%lo", BFD_RELOC_LO16},
14123 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14124 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14125 {"%call16", BFD_RELOC_MIPS_CALL16},
14126 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14127 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14128 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14129 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14130 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14131 {"%got", BFD_RELOC_MIPS_GOT16},
14132 {"%gp_rel", BFD_RELOC_GPREL16},
14133 {"%half", BFD_RELOC_16},
14134 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14135 {"%higher", BFD_RELOC_MIPS_HIGHER},
14136 {"%neg", BFD_RELOC_MIPS_SUB},
14137 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14138 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14139 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14140 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14141 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14142 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14143 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14145 {"%hi", BFD_RELOC_HI16_S}
14148 static const struct percent_op_match mips16_percent_op[] =
14150 {"%lo", BFD_RELOC_MIPS16_LO16},
14151 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14152 {"%got", BFD_RELOC_MIPS16_GOT16},
14153 {"%call16", BFD_RELOC_MIPS16_CALL16},
14154 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14155 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14156 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14157 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14158 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14159 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14160 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14161 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14165 /* Return true if *STR points to a relocation operator. When returning true,
14166 move *STR over the operator and store its relocation code in *RELOC.
14167 Leave both *STR and *RELOC alone when returning false. */
14170 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14172 const struct percent_op_match *percent_op;
14175 if (mips_opts.mips16)
14177 percent_op = mips16_percent_op;
14178 limit = ARRAY_SIZE (mips16_percent_op);
14182 percent_op = mips_percent_op;
14183 limit = ARRAY_SIZE (mips_percent_op);
14186 for (i = 0; i < limit; i++)
14187 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14189 int len = strlen (percent_op[i].str);
14191 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14194 *str += strlen (percent_op[i].str);
14195 *reloc = percent_op[i].reloc;
14197 /* Check whether the output BFD supports this relocation.
14198 If not, issue an error and fall back on something safe. */
14199 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14201 as_bad (_("relocation %s isn't supported by the current ABI"),
14202 percent_op[i].str);
14203 *reloc = BFD_RELOC_UNUSED;
14211 /* Parse string STR as a 16-bit relocatable operand. Store the
14212 expression in *EP and the relocations in the array starting
14213 at RELOC. Return the number of relocation operators used.
14215 On exit, EXPR_END points to the first character after the expression. */
14218 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14221 bfd_reloc_code_real_type reversed_reloc[3];
14222 size_t reloc_index, i;
14223 int crux_depth, str_depth;
14226 /* Search for the start of the main expression, recoding relocations
14227 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14228 of the main expression and with CRUX_DEPTH containing the number
14229 of open brackets at that point. */
14236 crux_depth = str_depth;
14238 /* Skip over whitespace and brackets, keeping count of the number
14240 while (*str == ' ' || *str == '\t' || *str == '(')
14245 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14246 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14248 my_getExpression (ep, crux);
14251 /* Match every open bracket. */
14252 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14256 if (crux_depth > 0)
14257 as_bad (_("unclosed '('"));
14261 if (reloc_index != 0)
14263 prev_reloc_op_frag = frag_now;
14264 for (i = 0; i < reloc_index; i++)
14265 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14268 return reloc_index;
14272 my_getExpression (expressionS *ep, char *str)
14276 save_in = input_line_pointer;
14277 input_line_pointer = str;
14279 expr_end = input_line_pointer;
14280 input_line_pointer = save_in;
14284 md_atof (int type, char *litP, int *sizeP)
14286 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14290 md_number_to_chars (char *buf, valueT val, int n)
14292 if (target_big_endian)
14293 number_to_chars_bigendian (buf, val, n);
14295 number_to_chars_littleendian (buf, val, n);
14299 static int support_64bit_objects(void)
14301 const char **list, **l;
14304 list = bfd_target_list ();
14305 for (l = list; *l != NULL; l++)
14306 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14307 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14309 yes = (*l != NULL);
14313 #endif /* OBJ_ELF */
14315 const char *md_shortopts = "O::g::G:";
14319 OPTION_MARCH = OPTION_MD_BASE,
14341 OPTION_NO_SMARTMIPS,
14345 OPTION_NO_MICROMIPS,
14348 OPTION_COMPAT_ARCH_BASE,
14357 OPTION_M7000_HILO_FIX,
14358 OPTION_MNO_7000_HILO_FIX,
14361 OPTION_FIX_LOONGSON2F_JUMP,
14362 OPTION_NO_FIX_LOONGSON2F_JUMP,
14363 OPTION_FIX_LOONGSON2F_NOP,
14364 OPTION_NO_FIX_LOONGSON2F_NOP,
14366 OPTION_NO_FIX_VR4120,
14368 OPTION_NO_FIX_VR4130,
14369 OPTION_FIX_CN63XXP1,
14370 OPTION_NO_FIX_CN63XXP1,
14377 OPTION_CONSTRUCT_FLOATS,
14378 OPTION_NO_CONSTRUCT_FLOATS,
14381 OPTION_RELAX_BRANCH,
14382 OPTION_NO_RELAX_BRANCH,
14389 OPTION_SINGLE_FLOAT,
14390 OPTION_DOUBLE_FLOAT,
14393 OPTION_CALL_SHARED,
14394 OPTION_CALL_NONPIC,
14404 OPTION_MVXWORKS_PIC,
14405 #endif /* OBJ_ELF */
14409 struct option md_longopts[] =
14411 /* Options which specify architecture. */
14412 {"march", required_argument, NULL, OPTION_MARCH},
14413 {"mtune", required_argument, NULL, OPTION_MTUNE},
14414 {"mips0", no_argument, NULL, OPTION_MIPS1},
14415 {"mips1", no_argument, NULL, OPTION_MIPS1},
14416 {"mips2", no_argument, NULL, OPTION_MIPS2},
14417 {"mips3", no_argument, NULL, OPTION_MIPS3},
14418 {"mips4", no_argument, NULL, OPTION_MIPS4},
14419 {"mips5", no_argument, NULL, OPTION_MIPS5},
14420 {"mips32", no_argument, NULL, OPTION_MIPS32},
14421 {"mips64", no_argument, NULL, OPTION_MIPS64},
14422 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14423 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14425 /* Options which specify Application Specific Extensions (ASEs). */
14426 {"mips16", no_argument, NULL, OPTION_MIPS16},
14427 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14428 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14429 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14430 {"mdmx", no_argument, NULL, OPTION_MDMX},
14431 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14432 {"mdsp", no_argument, NULL, OPTION_DSP},
14433 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14434 {"mmt", no_argument, NULL, OPTION_MT},
14435 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14436 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14437 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14438 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14439 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14440 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14441 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14442 {"mmcu", no_argument, NULL, OPTION_MCU},
14443 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14445 /* Old-style architecture options. Don't add more of these. */
14446 {"m4650", no_argument, NULL, OPTION_M4650},
14447 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14448 {"m4010", no_argument, NULL, OPTION_M4010},
14449 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14450 {"m4100", no_argument, NULL, OPTION_M4100},
14451 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14452 {"m3900", no_argument, NULL, OPTION_M3900},
14453 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14455 /* Options which enable bug fixes. */
14456 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14457 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14458 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14459 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14460 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14461 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14462 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14463 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14464 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14465 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14466 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14467 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14468 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14469 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14470 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14472 /* Miscellaneous options. */
14473 {"trap", no_argument, NULL, OPTION_TRAP},
14474 {"no-break", no_argument, NULL, OPTION_TRAP},
14475 {"break", no_argument, NULL, OPTION_BREAK},
14476 {"no-trap", no_argument, NULL, OPTION_BREAK},
14477 {"EB", no_argument, NULL, OPTION_EB},
14478 {"EL", no_argument, NULL, OPTION_EL},
14479 {"mfp32", no_argument, NULL, OPTION_FP32},
14480 {"mgp32", no_argument, NULL, OPTION_GP32},
14481 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14482 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14483 {"mfp64", no_argument, NULL, OPTION_FP64},
14484 {"mgp64", no_argument, NULL, OPTION_GP64},
14485 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14486 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14487 {"mshared", no_argument, NULL, OPTION_MSHARED},
14488 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14489 {"msym32", no_argument, NULL, OPTION_MSYM32},
14490 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14491 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14492 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14493 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14494 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14496 /* Strictly speaking this next option is ELF specific,
14497 but we allow it for other ports as well in order to
14498 make testing easier. */
14499 {"32", no_argument, NULL, OPTION_32},
14501 /* ELF-specific options. */
14503 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14504 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14505 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14506 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14507 {"xgot", no_argument, NULL, OPTION_XGOT},
14508 {"mabi", required_argument, NULL, OPTION_MABI},
14509 {"n32", no_argument, NULL, OPTION_N32},
14510 {"64", no_argument, NULL, OPTION_64},
14511 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14512 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14513 {"mpdr", no_argument, NULL, OPTION_PDR},
14514 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14515 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14516 #endif /* OBJ_ELF */
14518 {NULL, no_argument, NULL, 0}
14520 size_t md_longopts_size = sizeof (md_longopts);
14522 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14523 NEW_VALUE. Warn if another value was already specified. Note:
14524 we have to defer parsing the -march and -mtune arguments in order
14525 to handle 'from-abi' correctly, since the ABI might be specified
14526 in a later argument. */
14529 mips_set_option_string (const char **string_ptr, const char *new_value)
14531 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14532 as_warn (_("A different %s was already specified, is now %s"),
14533 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14536 *string_ptr = new_value;
14540 md_parse_option (int c, char *arg)
14544 case OPTION_CONSTRUCT_FLOATS:
14545 mips_disable_float_construction = 0;
14548 case OPTION_NO_CONSTRUCT_FLOATS:
14549 mips_disable_float_construction = 1;
14561 target_big_endian = 1;
14565 target_big_endian = 0;
14571 else if (arg[0] == '0')
14573 else if (arg[0] == '1')
14583 mips_debug = atoi (arg);
14587 file_mips_isa = ISA_MIPS1;
14591 file_mips_isa = ISA_MIPS2;
14595 file_mips_isa = ISA_MIPS3;
14599 file_mips_isa = ISA_MIPS4;
14603 file_mips_isa = ISA_MIPS5;
14606 case OPTION_MIPS32:
14607 file_mips_isa = ISA_MIPS32;
14610 case OPTION_MIPS32R2:
14611 file_mips_isa = ISA_MIPS32R2;
14614 case OPTION_MIPS64R2:
14615 file_mips_isa = ISA_MIPS64R2;
14618 case OPTION_MIPS64:
14619 file_mips_isa = ISA_MIPS64;
14623 mips_set_option_string (&mips_tune_string, arg);
14627 mips_set_option_string (&mips_arch_string, arg);
14631 mips_set_option_string (&mips_arch_string, "4650");
14632 mips_set_option_string (&mips_tune_string, "4650");
14635 case OPTION_NO_M4650:
14639 mips_set_option_string (&mips_arch_string, "4010");
14640 mips_set_option_string (&mips_tune_string, "4010");
14643 case OPTION_NO_M4010:
14647 mips_set_option_string (&mips_arch_string, "4100");
14648 mips_set_option_string (&mips_tune_string, "4100");
14651 case OPTION_NO_M4100:
14655 mips_set_option_string (&mips_arch_string, "3900");
14656 mips_set_option_string (&mips_tune_string, "3900");
14659 case OPTION_NO_M3900:
14663 mips_opts.ase_mdmx = 1;
14666 case OPTION_NO_MDMX:
14667 mips_opts.ase_mdmx = 0;
14671 mips_opts.ase_dsp = 1;
14672 mips_opts.ase_dspr2 = 0;
14675 case OPTION_NO_DSP:
14676 mips_opts.ase_dsp = 0;
14677 mips_opts.ase_dspr2 = 0;
14681 mips_opts.ase_dspr2 = 1;
14682 mips_opts.ase_dsp = 1;
14685 case OPTION_NO_DSPR2:
14686 mips_opts.ase_dspr2 = 0;
14687 mips_opts.ase_dsp = 0;
14691 mips_opts.ase_mt = 1;
14695 mips_opts.ase_mt = 0;
14699 mips_opts.ase_mcu = 1;
14702 case OPTION_NO_MCU:
14703 mips_opts.ase_mcu = 0;
14706 case OPTION_MICROMIPS:
14707 if (mips_opts.mips16 == 1)
14709 as_bad (_("-mmicromips cannot be used with -mips16"));
14712 mips_opts.micromips = 1;
14713 mips_no_prev_insn ();
14716 case OPTION_NO_MICROMIPS:
14717 mips_opts.micromips = 0;
14718 mips_no_prev_insn ();
14721 case OPTION_MIPS16:
14722 if (mips_opts.micromips == 1)
14724 as_bad (_("-mips16 cannot be used with -micromips"));
14727 mips_opts.mips16 = 1;
14728 mips_no_prev_insn ();
14731 case OPTION_NO_MIPS16:
14732 mips_opts.mips16 = 0;
14733 mips_no_prev_insn ();
14736 case OPTION_MIPS3D:
14737 mips_opts.ase_mips3d = 1;
14740 case OPTION_NO_MIPS3D:
14741 mips_opts.ase_mips3d = 0;
14744 case OPTION_SMARTMIPS:
14745 mips_opts.ase_smartmips = 1;
14748 case OPTION_NO_SMARTMIPS:
14749 mips_opts.ase_smartmips = 0;
14752 case OPTION_FIX_24K:
14756 case OPTION_NO_FIX_24K:
14760 case OPTION_FIX_LOONGSON2F_JUMP:
14761 mips_fix_loongson2f_jump = TRUE;
14764 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14765 mips_fix_loongson2f_jump = FALSE;
14768 case OPTION_FIX_LOONGSON2F_NOP:
14769 mips_fix_loongson2f_nop = TRUE;
14772 case OPTION_NO_FIX_LOONGSON2F_NOP:
14773 mips_fix_loongson2f_nop = FALSE;
14776 case OPTION_FIX_VR4120:
14777 mips_fix_vr4120 = 1;
14780 case OPTION_NO_FIX_VR4120:
14781 mips_fix_vr4120 = 0;
14784 case OPTION_FIX_VR4130:
14785 mips_fix_vr4130 = 1;
14788 case OPTION_NO_FIX_VR4130:
14789 mips_fix_vr4130 = 0;
14792 case OPTION_FIX_CN63XXP1:
14793 mips_fix_cn63xxp1 = TRUE;
14796 case OPTION_NO_FIX_CN63XXP1:
14797 mips_fix_cn63xxp1 = FALSE;
14800 case OPTION_RELAX_BRANCH:
14801 mips_relax_branch = 1;
14804 case OPTION_NO_RELAX_BRANCH:
14805 mips_relax_branch = 0;
14808 case OPTION_MSHARED:
14809 mips_in_shared = TRUE;
14812 case OPTION_MNO_SHARED:
14813 mips_in_shared = FALSE;
14816 case OPTION_MSYM32:
14817 mips_opts.sym32 = TRUE;
14820 case OPTION_MNO_SYM32:
14821 mips_opts.sym32 = FALSE;
14825 /* When generating ELF code, we permit -KPIC and -call_shared to
14826 select SVR4_PIC, and -non_shared to select no PIC. This is
14827 intended to be compatible with Irix 5. */
14828 case OPTION_CALL_SHARED:
14831 as_bad (_("-call_shared is supported only for ELF format"));
14834 mips_pic = SVR4_PIC;
14835 mips_abicalls = TRUE;
14838 case OPTION_CALL_NONPIC:
14841 as_bad (_("-call_nonpic is supported only for ELF format"));
14845 mips_abicalls = TRUE;
14848 case OPTION_NON_SHARED:
14851 as_bad (_("-non_shared is supported only for ELF format"));
14855 mips_abicalls = FALSE;
14858 /* The -xgot option tells the assembler to use 32 bit offsets
14859 when accessing the got in SVR4_PIC mode. It is for Irix
14864 #endif /* OBJ_ELF */
14867 g_switch_value = atoi (arg);
14871 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14875 mips_abi = O32_ABI;
14876 /* We silently ignore -32 for non-ELF targets. This greatly
14877 simplifies the construction of the MIPS GAS test cases. */
14884 as_bad (_("-n32 is supported for ELF format only"));
14887 mips_abi = N32_ABI;
14893 as_bad (_("-64 is supported for ELF format only"));
14896 mips_abi = N64_ABI;
14897 if (!support_64bit_objects())
14898 as_fatal (_("No compiled in support for 64 bit object file format"));
14900 #endif /* OBJ_ELF */
14903 file_mips_gp32 = 1;
14907 file_mips_gp32 = 0;
14911 file_mips_fp32 = 1;
14915 file_mips_fp32 = 0;
14918 case OPTION_SINGLE_FLOAT:
14919 file_mips_single_float = 1;
14922 case OPTION_DOUBLE_FLOAT:
14923 file_mips_single_float = 0;
14926 case OPTION_SOFT_FLOAT:
14927 file_mips_soft_float = 1;
14930 case OPTION_HARD_FLOAT:
14931 file_mips_soft_float = 0;
14938 as_bad (_("-mabi is supported for ELF format only"));
14941 if (strcmp (arg, "32") == 0)
14942 mips_abi = O32_ABI;
14943 else if (strcmp (arg, "o64") == 0)
14944 mips_abi = O64_ABI;
14945 else if (strcmp (arg, "n32") == 0)
14946 mips_abi = N32_ABI;
14947 else if (strcmp (arg, "64") == 0)
14949 mips_abi = N64_ABI;
14950 if (! support_64bit_objects())
14951 as_fatal (_("No compiled in support for 64 bit object file "
14954 else if (strcmp (arg, "eabi") == 0)
14955 mips_abi = EABI_ABI;
14958 as_fatal (_("invalid abi -mabi=%s"), arg);
14962 #endif /* OBJ_ELF */
14964 case OPTION_M7000_HILO_FIX:
14965 mips_7000_hilo_fix = TRUE;
14968 case OPTION_MNO_7000_HILO_FIX:
14969 mips_7000_hilo_fix = FALSE;
14973 case OPTION_MDEBUG:
14974 mips_flag_mdebug = TRUE;
14977 case OPTION_NO_MDEBUG:
14978 mips_flag_mdebug = FALSE;
14982 mips_flag_pdr = TRUE;
14985 case OPTION_NO_PDR:
14986 mips_flag_pdr = FALSE;
14989 case OPTION_MVXWORKS_PIC:
14990 mips_pic = VXWORKS_PIC;
14992 #endif /* OBJ_ELF */
14998 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15003 /* Set up globals to generate code for the ISA or processor
15004 described by INFO. */
15007 mips_set_architecture (const struct mips_cpu_info *info)
15011 file_mips_arch = info->cpu;
15012 mips_opts.arch = info->cpu;
15013 mips_opts.isa = info->isa;
15018 /* Likewise for tuning. */
15021 mips_set_tune (const struct mips_cpu_info *info)
15024 mips_tune = info->cpu;
15029 mips_after_parse_args (void)
15031 const struct mips_cpu_info *arch_info = 0;
15032 const struct mips_cpu_info *tune_info = 0;
15034 /* GP relative stuff not working for PE */
15035 if (strncmp (TARGET_OS, "pe", 2) == 0)
15037 if (g_switch_seen && g_switch_value != 0)
15038 as_bad (_("-G not supported in this configuration."));
15039 g_switch_value = 0;
15042 if (mips_abi == NO_ABI)
15043 mips_abi = MIPS_DEFAULT_ABI;
15045 /* The following code determines the architecture and register size.
15046 Similar code was added to GCC 3.3 (see override_options() in
15047 config/mips/mips.c). The GAS and GCC code should be kept in sync
15048 as much as possible. */
15050 if (mips_arch_string != 0)
15051 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15053 if (file_mips_isa != ISA_UNKNOWN)
15055 /* Handle -mipsN. At this point, file_mips_isa contains the
15056 ISA level specified by -mipsN, while arch_info->isa contains
15057 the -march selection (if any). */
15058 if (arch_info != 0)
15060 /* -march takes precedence over -mipsN, since it is more descriptive.
15061 There's no harm in specifying both as long as the ISA levels
15063 if (file_mips_isa != arch_info->isa)
15064 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15065 mips_cpu_info_from_isa (file_mips_isa)->name,
15066 mips_cpu_info_from_isa (arch_info->isa)->name);
15069 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15072 if (arch_info == 0)
15074 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15075 gas_assert (arch_info);
15078 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15079 as_bad (_("-march=%s is not compatible with the selected ABI"),
15082 mips_set_architecture (arch_info);
15084 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15085 if (mips_tune_string != 0)
15086 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15088 if (tune_info == 0)
15089 mips_set_tune (arch_info);
15091 mips_set_tune (tune_info);
15093 if (file_mips_gp32 >= 0)
15095 /* The user specified the size of the integer registers. Make sure
15096 it agrees with the ABI and ISA. */
15097 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15098 as_bad (_("-mgp64 used with a 32-bit processor"));
15099 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15100 as_bad (_("-mgp32 used with a 64-bit ABI"));
15101 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15102 as_bad (_("-mgp64 used with a 32-bit ABI"));
15106 /* Infer the integer register size from the ABI and processor.
15107 Restrict ourselves to 32-bit registers if that's all the
15108 processor has, or if the ABI cannot handle 64-bit registers. */
15109 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15110 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15113 switch (file_mips_fp32)
15117 /* No user specified float register size.
15118 ??? GAS treats single-float processors as though they had 64-bit
15119 float registers (although it complains when double-precision
15120 instructions are used). As things stand, saying they have 32-bit
15121 registers would lead to spurious "register must be even" messages.
15122 So here we assume float registers are never smaller than the
15124 if (file_mips_gp32 == 0)
15125 /* 64-bit integer registers implies 64-bit float registers. */
15126 file_mips_fp32 = 0;
15127 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15128 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15129 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15130 file_mips_fp32 = 0;
15132 /* 32-bit float registers. */
15133 file_mips_fp32 = 1;
15136 /* The user specified the size of the float registers. Check if it
15137 agrees with the ABI and ISA. */
15139 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15140 as_bad (_("-mfp64 used with a 32-bit fpu"));
15141 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15142 && !ISA_HAS_MXHC1 (mips_opts.isa))
15143 as_warn (_("-mfp64 used with a 32-bit ABI"));
15146 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15147 as_warn (_("-mfp32 used with a 64-bit ABI"));
15151 /* End of GCC-shared inference code. */
15153 /* This flag is set when we have a 64-bit capable CPU but use only
15154 32-bit wide registers. Note that EABI does not use it. */
15155 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15156 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15157 || mips_abi == O32_ABI))
15158 mips_32bitmode = 1;
15160 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15161 as_bad (_("trap exception not supported at ISA 1"));
15163 /* If the selected architecture includes support for ASEs, enable
15164 generation of code for them. */
15165 if (mips_opts.mips16 == -1)
15166 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15167 if (mips_opts.micromips == -1)
15168 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15169 if (mips_opts.ase_mips3d == -1)
15170 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15171 && file_mips_fp32 == 0) ? 1 : 0;
15172 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15173 as_bad (_("-mfp32 used with -mips3d"));
15175 if (mips_opts.ase_mdmx == -1)
15176 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15177 && file_mips_fp32 == 0) ? 1 : 0;
15178 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15179 as_bad (_("-mfp32 used with -mdmx"));
15181 if (mips_opts.ase_smartmips == -1)
15182 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15183 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15184 as_warn (_("%s ISA does not support SmartMIPS"),
15185 mips_cpu_info_from_isa (mips_opts.isa)->name);
15187 if (mips_opts.ase_dsp == -1)
15188 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15189 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15190 as_warn (_("%s ISA does not support DSP ASE"),
15191 mips_cpu_info_from_isa (mips_opts.isa)->name);
15193 if (mips_opts.ase_dspr2 == -1)
15195 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15196 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15198 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15199 as_warn (_("%s ISA does not support DSP R2 ASE"),
15200 mips_cpu_info_from_isa (mips_opts.isa)->name);
15202 if (mips_opts.ase_mt == -1)
15203 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15204 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15205 as_warn (_("%s ISA does not support MT ASE"),
15206 mips_cpu_info_from_isa (mips_opts.isa)->name);
15208 if (mips_opts.ase_mcu == -1)
15209 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15210 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15211 as_warn (_("%s ISA does not support MCU ASE"),
15212 mips_cpu_info_from_isa (mips_opts.isa)->name);
15214 file_mips_isa = mips_opts.isa;
15215 file_ase_mips3d = mips_opts.ase_mips3d;
15216 file_ase_mdmx = mips_opts.ase_mdmx;
15217 file_ase_smartmips = mips_opts.ase_smartmips;
15218 file_ase_dsp = mips_opts.ase_dsp;
15219 file_ase_dspr2 = mips_opts.ase_dspr2;
15220 file_ase_mt = mips_opts.ase_mt;
15221 mips_opts.gp32 = file_mips_gp32;
15222 mips_opts.fp32 = file_mips_fp32;
15223 mips_opts.soft_float = file_mips_soft_float;
15224 mips_opts.single_float = file_mips_single_float;
15226 if (mips_flag_mdebug < 0)
15228 #ifdef OBJ_MAYBE_ECOFF
15229 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15230 mips_flag_mdebug = 1;
15232 #endif /* OBJ_MAYBE_ECOFF */
15233 mips_flag_mdebug = 0;
15238 mips_init_after_args (void)
15240 /* initialize opcodes */
15241 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15242 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15246 md_pcrel_from (fixS *fixP)
15248 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15249 switch (fixP->fx_r_type)
15251 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15252 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15253 /* Return the address of the delay slot. */
15256 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15257 case BFD_RELOC_MICROMIPS_JMP:
15258 case BFD_RELOC_16_PCREL_S2:
15259 case BFD_RELOC_MIPS_JMP:
15260 /* Return the address of the delay slot. */
15264 /* We have no relocation type for PC relative MIPS16 instructions. */
15265 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15266 as_bad_where (fixP->fx_file, fixP->fx_line,
15267 _("PC relative MIPS16 instruction references a different section"));
15272 /* This is called before the symbol table is processed. In order to
15273 work with gcc when using mips-tfile, we must keep all local labels.
15274 However, in other cases, we want to discard them. If we were
15275 called with -g, but we didn't see any debugging information, it may
15276 mean that gcc is smuggling debugging information through to
15277 mips-tfile, in which case we must generate all local labels. */
15280 mips_frob_file_before_adjust (void)
15282 #ifndef NO_ECOFF_DEBUGGING
15283 if (ECOFF_DEBUGGING
15285 && ! ecoff_debugging_seen)
15286 flag_keep_locals = 1;
15290 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15291 the corresponding LO16 reloc. This is called before md_apply_fix and
15292 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15293 relocation operators.
15295 For our purposes, a %lo() expression matches a %got() or %hi()
15298 (a) it refers to the same symbol; and
15299 (b) the offset applied in the %lo() expression is no lower than
15300 the offset applied in the %got() or %hi().
15302 (b) allows us to cope with code like:
15305 lh $4,%lo(foo+2)($4)
15307 ...which is legal on RELA targets, and has a well-defined behaviour
15308 if the user knows that adding 2 to "foo" will not induce a carry to
15311 When several %lo()s match a particular %got() or %hi(), we use the
15312 following rules to distinguish them:
15314 (1) %lo()s with smaller offsets are a better match than %lo()s with
15317 (2) %lo()s with no matching %got() or %hi() are better than those
15318 that already have a matching %got() or %hi().
15320 (3) later %lo()s are better than earlier %lo()s.
15322 These rules are applied in order.
15324 (1) means, among other things, that %lo()s with identical offsets are
15325 chosen if they exist.
15327 (2) means that we won't associate several high-part relocations with
15328 the same low-part relocation unless there's no alternative. Having
15329 several high parts for the same low part is a GNU extension; this rule
15330 allows careful users to avoid it.
15332 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15333 with the last high-part relocation being at the front of the list.
15334 It therefore makes sense to choose the last matching low-part
15335 relocation, all other things being equal. It's also easier
15336 to code that way. */
15339 mips_frob_file (void)
15341 struct mips_hi_fixup *l;
15342 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15344 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15346 segment_info_type *seginfo;
15347 bfd_boolean matched_lo_p;
15348 fixS **hi_pos, **lo_pos, **pos;
15350 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15352 /* If a GOT16 relocation turns out to be against a global symbol,
15353 there isn't supposed to be a matching LO. */
15354 if (got16_reloc_p (l->fixp->fx_r_type)
15355 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15358 /* Check quickly whether the next fixup happens to be a matching %lo. */
15359 if (fixup_has_matching_lo_p (l->fixp))
15362 seginfo = seg_info (l->seg);
15364 /* Set HI_POS to the position of this relocation in the chain.
15365 Set LO_POS to the position of the chosen low-part relocation.
15366 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15367 relocation that matches an immediately-preceding high-part
15371 matched_lo_p = FALSE;
15372 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15374 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15376 if (*pos == l->fixp)
15379 if ((*pos)->fx_r_type == looking_for_rtype
15380 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15381 && (*pos)->fx_offset >= l->fixp->fx_offset
15383 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15385 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15388 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15389 && fixup_has_matching_lo_p (*pos));
15392 /* If we found a match, remove the high-part relocation from its
15393 current position and insert it before the low-part relocation.
15394 Make the offsets match so that fixup_has_matching_lo_p()
15397 We don't warn about unmatched high-part relocations since some
15398 versions of gcc have been known to emit dead "lui ...%hi(...)"
15400 if (lo_pos != NULL)
15402 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15403 if (l->fixp->fx_next != *lo_pos)
15405 *hi_pos = l->fixp->fx_next;
15406 l->fixp->fx_next = *lo_pos;
15413 /* We may have combined relocations without symbols in the N32/N64 ABI.
15414 We have to prevent gas from dropping them. */
15417 mips_force_relocation (fixS *fixp)
15419 if (generic_force_reloc (fixp))
15422 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15423 so that the linker relaxation can update targets. */
15424 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15425 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15426 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15430 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15431 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
15432 || hi16_reloc_p (fixp->fx_r_type)
15433 || lo16_reloc_p (fixp->fx_r_type)))
15439 /* Apply a fixup to the object file. */
15442 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15446 reloc_howto_type *howto;
15448 /* We ignore generic BFD relocations we don't know about. */
15449 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15453 gas_assert (fixP->fx_size == 2
15454 || fixP->fx_size == 4
15455 || fixP->fx_r_type == BFD_RELOC_16
15456 || fixP->fx_r_type == BFD_RELOC_64
15457 || fixP->fx_r_type == BFD_RELOC_CTOR
15458 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15459 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15460 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15461 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15462 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15464 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15466 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15467 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15468 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15469 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15471 /* Don't treat parts of a composite relocation as done. There are two
15474 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15475 should nevertheless be emitted if the first part is.
15477 (2) In normal usage, composite relocations are never assembly-time
15478 constants. The easiest way of dealing with the pathological
15479 exceptions is to generate a relocation against STN_UNDEF and
15480 leave everything up to the linker. */
15481 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15484 switch (fixP->fx_r_type)
15486 case BFD_RELOC_MIPS_TLS_GD:
15487 case BFD_RELOC_MIPS_TLS_LDM:
15488 case BFD_RELOC_MIPS_TLS_DTPREL32:
15489 case BFD_RELOC_MIPS_TLS_DTPREL64:
15490 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15491 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15492 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15493 case BFD_RELOC_MIPS_TLS_TPREL32:
15494 case BFD_RELOC_MIPS_TLS_TPREL64:
15495 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15496 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15497 case BFD_RELOC_MICROMIPS_TLS_GD:
15498 case BFD_RELOC_MICROMIPS_TLS_LDM:
15499 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15500 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15501 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15502 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15503 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15504 case BFD_RELOC_MIPS16_TLS_GD:
15505 case BFD_RELOC_MIPS16_TLS_LDM:
15506 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15507 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15508 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15509 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15510 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15511 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15514 case BFD_RELOC_MIPS_JMP:
15515 case BFD_RELOC_MIPS_SHIFT5:
15516 case BFD_RELOC_MIPS_SHIFT6:
15517 case BFD_RELOC_MIPS_GOT_DISP:
15518 case BFD_RELOC_MIPS_GOT_PAGE:
15519 case BFD_RELOC_MIPS_GOT_OFST:
15520 case BFD_RELOC_MIPS_SUB:
15521 case BFD_RELOC_MIPS_INSERT_A:
15522 case BFD_RELOC_MIPS_INSERT_B:
15523 case BFD_RELOC_MIPS_DELETE:
15524 case BFD_RELOC_MIPS_HIGHEST:
15525 case BFD_RELOC_MIPS_HIGHER:
15526 case BFD_RELOC_MIPS_SCN_DISP:
15527 case BFD_RELOC_MIPS_REL16:
15528 case BFD_RELOC_MIPS_RELGOT:
15529 case BFD_RELOC_MIPS_JALR:
15530 case BFD_RELOC_HI16:
15531 case BFD_RELOC_HI16_S:
15532 case BFD_RELOC_GPREL16:
15533 case BFD_RELOC_MIPS_LITERAL:
15534 case BFD_RELOC_MIPS_CALL16:
15535 case BFD_RELOC_MIPS_GOT16:
15536 case BFD_RELOC_GPREL32:
15537 case BFD_RELOC_MIPS_GOT_HI16:
15538 case BFD_RELOC_MIPS_GOT_LO16:
15539 case BFD_RELOC_MIPS_CALL_HI16:
15540 case BFD_RELOC_MIPS_CALL_LO16:
15541 case BFD_RELOC_MIPS16_GPREL:
15542 case BFD_RELOC_MIPS16_GOT16:
15543 case BFD_RELOC_MIPS16_CALL16:
15544 case BFD_RELOC_MIPS16_HI16:
15545 case BFD_RELOC_MIPS16_HI16_S:
15546 case BFD_RELOC_MIPS16_JMP:
15547 case BFD_RELOC_MICROMIPS_JMP:
15548 case BFD_RELOC_MICROMIPS_GOT_DISP:
15549 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15550 case BFD_RELOC_MICROMIPS_GOT_OFST:
15551 case BFD_RELOC_MICROMIPS_SUB:
15552 case BFD_RELOC_MICROMIPS_HIGHEST:
15553 case BFD_RELOC_MICROMIPS_HIGHER:
15554 case BFD_RELOC_MICROMIPS_SCN_DISP:
15555 case BFD_RELOC_MICROMIPS_JALR:
15556 case BFD_RELOC_MICROMIPS_HI16:
15557 case BFD_RELOC_MICROMIPS_HI16_S:
15558 case BFD_RELOC_MICROMIPS_GPREL16:
15559 case BFD_RELOC_MICROMIPS_LITERAL:
15560 case BFD_RELOC_MICROMIPS_CALL16:
15561 case BFD_RELOC_MICROMIPS_GOT16:
15562 case BFD_RELOC_MICROMIPS_GOT_HI16:
15563 case BFD_RELOC_MICROMIPS_GOT_LO16:
15564 case BFD_RELOC_MICROMIPS_CALL_HI16:
15565 case BFD_RELOC_MICROMIPS_CALL_LO16:
15566 /* Nothing needed to do. The value comes from the reloc entry. */
15570 /* This is handled like BFD_RELOC_32, but we output a sign
15571 extended value if we are only 32 bits. */
15574 if (8 <= sizeof (valueT))
15575 md_number_to_chars (buf, *valP, 8);
15580 if ((*valP & 0x80000000) != 0)
15584 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15585 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15590 case BFD_RELOC_RVA:
15593 /* If we are deleting this reloc entry, we must fill in the
15594 value now. This can happen if we have a .word which is not
15595 resolved when it appears but is later defined. */
15597 md_number_to_chars (buf, *valP, fixP->fx_size);
15600 case BFD_RELOC_LO16:
15601 case BFD_RELOC_MIPS16_LO16:
15602 case BFD_RELOC_MICROMIPS_LO16:
15603 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15604 may be safe to remove, but if so it's not obvious. */
15605 /* When handling an embedded PIC switch statement, we can wind
15606 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15609 if (*valP + 0x8000 > 0xffff)
15610 as_bad_where (fixP->fx_file, fixP->fx_line,
15611 _("relocation overflow"));
15612 /* 32-bit microMIPS instructions are divided into two halfwords.
15613 Relocations always refer to the second halfword, regardless
15615 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
15617 md_number_to_chars (buf, *valP, 2);
15621 case BFD_RELOC_16_PCREL_S2:
15622 if ((*valP & 0x3) != 0)
15623 as_bad_where (fixP->fx_file, fixP->fx_line,
15624 _("Branch to misaligned address (%lx)"), (long) *valP);
15626 /* We need to save the bits in the instruction since fixup_segment()
15627 might be deleting the relocation entry (i.e., a branch within
15628 the current segment). */
15629 if (! fixP->fx_done)
15632 /* Update old instruction data. */
15633 insn = read_insn (buf);
15635 if (*valP + 0x20000 <= 0x3ffff)
15637 insn |= (*valP >> 2) & 0xffff;
15638 write_insn (buf, insn);
15640 else if (mips_pic == NO_PIC
15642 && fixP->fx_frag->fr_address >= text_section->vma
15643 && (fixP->fx_frag->fr_address
15644 < text_section->vma + bfd_get_section_size (text_section))
15645 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15646 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15647 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15649 /* The branch offset is too large. If this is an
15650 unconditional branch, and we are not generating PIC code,
15651 we can convert it to an absolute jump instruction. */
15652 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15653 insn = 0x0c000000; /* jal */
15655 insn = 0x08000000; /* j */
15656 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15658 fixP->fx_addsy = section_symbol (text_section);
15659 *valP += md_pcrel_from (fixP);
15660 write_insn (buf, insn);
15664 /* If we got here, we have branch-relaxation disabled,
15665 and there's nothing we can do to fix this instruction
15666 without turning it into a longer sequence. */
15667 as_bad_where (fixP->fx_file, fixP->fx_line,
15668 _("Branch out of range"));
15672 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15673 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15674 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15675 /* We adjust the offset back to even. */
15676 if ((*valP & 0x1) != 0)
15679 if (! fixP->fx_done)
15682 /* Should never visit here, because we keep the relocation. */
15686 case BFD_RELOC_VTABLE_INHERIT:
15689 && !S_IS_DEFINED (fixP->fx_addsy)
15690 && !S_IS_WEAK (fixP->fx_addsy))
15691 S_SET_WEAK (fixP->fx_addsy);
15694 case BFD_RELOC_VTABLE_ENTRY:
15702 /* Remember value for tc_gen_reloc. */
15703 fixP->fx_addnumber = *valP;
15713 name = input_line_pointer;
15714 c = get_symbol_end ();
15715 p = (symbolS *) symbol_find_or_make (name);
15716 *input_line_pointer = c;
15720 /* Align the current frag to a given power of two. If a particular
15721 fill byte should be used, FILL points to an integer that contains
15722 that byte, otherwise FILL is null.
15724 This function used to have the comment:
15726 The MIPS assembler also automatically adjusts any preceding label.
15728 The implementation therefore applied the adjustment to a maximum of
15729 one label. However, other label adjustments are applied to batches
15730 of labels, and adjusting just one caused problems when new labels
15731 were added for the sake of debugging or unwind information.
15732 We therefore adjust all preceding labels (given as LABELS) instead. */
15735 mips_align (int to, int *fill, struct insn_label_list *labels)
15737 mips_emit_delays ();
15738 mips_record_compressed_mode ();
15739 if (fill == NULL && subseg_text_p (now_seg))
15740 frag_align_code (to, 0);
15742 frag_align (to, fill ? *fill : 0, 0);
15743 record_alignment (now_seg, to);
15744 mips_move_labels (labels, FALSE);
15747 /* Align to a given power of two. .align 0 turns off the automatic
15748 alignment used by the data creating pseudo-ops. */
15751 s_align (int x ATTRIBUTE_UNUSED)
15753 int temp, fill_value, *fill_ptr;
15754 long max_alignment = 28;
15756 /* o Note that the assembler pulls down any immediately preceding label
15757 to the aligned address.
15758 o It's not documented but auto alignment is reinstated by
15759 a .align pseudo instruction.
15760 o Note also that after auto alignment is turned off the mips assembler
15761 issues an error on attempt to assemble an improperly aligned data item.
15764 temp = get_absolute_expression ();
15765 if (temp > max_alignment)
15766 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15769 as_warn (_("Alignment negative: 0 assumed."));
15772 if (*input_line_pointer == ',')
15774 ++input_line_pointer;
15775 fill_value = get_absolute_expression ();
15776 fill_ptr = &fill_value;
15782 segment_info_type *si = seg_info (now_seg);
15783 struct insn_label_list *l = si->label_list;
15784 /* Auto alignment should be switched on by next section change. */
15786 mips_align (temp, fill_ptr, l);
15793 demand_empty_rest_of_line ();
15797 s_change_sec (int sec)
15802 /* The ELF backend needs to know that we are changing sections, so
15803 that .previous works correctly. We could do something like check
15804 for an obj_section_change_hook macro, but that might be confusing
15805 as it would not be appropriate to use it in the section changing
15806 functions in read.c, since obj-elf.c intercepts those. FIXME:
15807 This should be cleaner, somehow. */
15809 obj_elf_section_change_hook ();
15812 mips_emit_delays ();
15823 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15824 demand_empty_rest_of_line ();
15828 seg = subseg_new (RDATA_SECTION_NAME,
15829 (subsegT) get_absolute_expression ());
15832 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15833 | SEC_READONLY | SEC_RELOC
15835 if (strncmp (TARGET_OS, "elf", 3) != 0)
15836 record_alignment (seg, 4);
15838 demand_empty_rest_of_line ();
15842 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15845 bfd_set_section_flags (stdoutput, seg,
15846 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15847 if (strncmp (TARGET_OS, "elf", 3) != 0)
15848 record_alignment (seg, 4);
15850 demand_empty_rest_of_line ();
15854 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15857 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15858 if (strncmp (TARGET_OS, "elf", 3) != 0)
15859 record_alignment (seg, 4);
15861 demand_empty_rest_of_line ();
15869 s_change_section (int ignore ATTRIBUTE_UNUSED)
15872 char *section_name;
15877 int section_entry_size;
15878 int section_alignment;
15883 section_name = input_line_pointer;
15884 c = get_symbol_end ();
15886 next_c = *(input_line_pointer + 1);
15888 /* Do we have .section Name<,"flags">? */
15889 if (c != ',' || (c == ',' && next_c == '"'))
15891 /* just after name is now '\0'. */
15892 *input_line_pointer = c;
15893 input_line_pointer = section_name;
15894 obj_elf_section (ignore);
15897 input_line_pointer++;
15899 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15901 section_type = get_absolute_expression ();
15904 if (*input_line_pointer++ == ',')
15905 section_flag = get_absolute_expression ();
15908 if (*input_line_pointer++ == ',')
15909 section_entry_size = get_absolute_expression ();
15911 section_entry_size = 0;
15912 if (*input_line_pointer++ == ',')
15913 section_alignment = get_absolute_expression ();
15915 section_alignment = 0;
15916 /* FIXME: really ignore? */
15917 (void) section_alignment;
15919 section_name = xstrdup (section_name);
15921 /* When using the generic form of .section (as implemented by obj-elf.c),
15922 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15923 traditionally had to fall back on the more common @progbits instead.
15925 There's nothing really harmful in this, since bfd will correct
15926 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15927 means that, for backwards compatibility, the special_section entries
15928 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15930 Even so, we shouldn't force users of the MIPS .section syntax to
15931 incorrectly label the sections as SHT_PROGBITS. The best compromise
15932 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15933 generic type-checking code. */
15934 if (section_type == SHT_MIPS_DWARF)
15935 section_type = SHT_PROGBITS;
15937 obj_elf_change_section (section_name, section_type, section_flag,
15938 section_entry_size, 0, 0, 0);
15940 if (now_seg->name != section_name)
15941 free (section_name);
15942 #endif /* OBJ_ELF */
15946 mips_enable_auto_align (void)
15952 s_cons (int log_size)
15954 segment_info_type *si = seg_info (now_seg);
15955 struct insn_label_list *l = si->label_list;
15957 mips_emit_delays ();
15958 if (log_size > 0 && auto_align)
15959 mips_align (log_size, 0, l);
15960 cons (1 << log_size);
15961 mips_clear_insn_labels ();
15965 s_float_cons (int type)
15967 segment_info_type *si = seg_info (now_seg);
15968 struct insn_label_list *l = si->label_list;
15970 mips_emit_delays ();
15975 mips_align (3, 0, l);
15977 mips_align (2, 0, l);
15981 mips_clear_insn_labels ();
15984 /* Handle .globl. We need to override it because on Irix 5 you are
15987 where foo is an undefined symbol, to mean that foo should be
15988 considered to be the address of a function. */
15991 s_mips_globl (int x ATTRIBUTE_UNUSED)
16000 name = input_line_pointer;
16001 c = get_symbol_end ();
16002 symbolP = symbol_find_or_make (name);
16003 S_SET_EXTERNAL (symbolP);
16005 *input_line_pointer = c;
16006 SKIP_WHITESPACE ();
16008 /* On Irix 5, every global symbol that is not explicitly labelled as
16009 being a function is apparently labelled as being an object. */
16012 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16013 && (*input_line_pointer != ','))
16018 secname = input_line_pointer;
16019 c = get_symbol_end ();
16020 sec = bfd_get_section_by_name (stdoutput, secname);
16022 as_bad (_("%s: no such section"), secname);
16023 *input_line_pointer = c;
16025 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16026 flag = BSF_FUNCTION;
16029 symbol_get_bfdsym (symbolP)->flags |= flag;
16031 c = *input_line_pointer;
16034 input_line_pointer++;
16035 SKIP_WHITESPACE ();
16036 if (is_end_of_line[(unsigned char) *input_line_pointer])
16042 demand_empty_rest_of_line ();
16046 s_option (int x ATTRIBUTE_UNUSED)
16051 opt = input_line_pointer;
16052 c = get_symbol_end ();
16056 /* FIXME: What does this mean? */
16058 else if (strncmp (opt, "pic", 3) == 0)
16062 i = atoi (opt + 3);
16067 mips_pic = SVR4_PIC;
16068 mips_abicalls = TRUE;
16071 as_bad (_(".option pic%d not supported"), i);
16073 if (mips_pic == SVR4_PIC)
16075 if (g_switch_seen && g_switch_value != 0)
16076 as_warn (_("-G may not be used with SVR4 PIC code"));
16077 g_switch_value = 0;
16078 bfd_set_gp_size (stdoutput, 0);
16082 as_warn (_("Unrecognized option \"%s\""), opt);
16084 *input_line_pointer = c;
16085 demand_empty_rest_of_line ();
16088 /* This structure is used to hold a stack of .set values. */
16090 struct mips_option_stack
16092 struct mips_option_stack *next;
16093 struct mips_set_options options;
16096 static struct mips_option_stack *mips_opts_stack;
16098 /* Handle the .set pseudo-op. */
16101 s_mipsset (int x ATTRIBUTE_UNUSED)
16103 char *name = input_line_pointer, ch;
16105 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16106 ++input_line_pointer;
16107 ch = *input_line_pointer;
16108 *input_line_pointer = '\0';
16110 if (strcmp (name, "reorder") == 0)
16112 if (mips_opts.noreorder)
16115 else if (strcmp (name, "noreorder") == 0)
16117 if (!mips_opts.noreorder)
16118 start_noreorder ();
16120 else if (strncmp (name, "at=", 3) == 0)
16122 char *s = name + 3;
16124 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16125 as_bad (_("Unrecognized register name `%s'"), s);
16127 else if (strcmp (name, "at") == 0)
16129 mips_opts.at = ATREG;
16131 else if (strcmp (name, "noat") == 0)
16133 mips_opts.at = ZERO;
16135 else if (strcmp (name, "macro") == 0)
16137 mips_opts.warn_about_macros = 0;
16139 else if (strcmp (name, "nomacro") == 0)
16141 if (mips_opts.noreorder == 0)
16142 as_bad (_("`noreorder' must be set before `nomacro'"));
16143 mips_opts.warn_about_macros = 1;
16145 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16147 mips_opts.nomove = 0;
16149 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16151 mips_opts.nomove = 1;
16153 else if (strcmp (name, "bopt") == 0)
16155 mips_opts.nobopt = 0;
16157 else if (strcmp (name, "nobopt") == 0)
16159 mips_opts.nobopt = 1;
16161 else if (strcmp (name, "gp=default") == 0)
16162 mips_opts.gp32 = file_mips_gp32;
16163 else if (strcmp (name, "gp=32") == 0)
16164 mips_opts.gp32 = 1;
16165 else if (strcmp (name, "gp=64") == 0)
16167 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16168 as_warn (_("%s isa does not support 64-bit registers"),
16169 mips_cpu_info_from_isa (mips_opts.isa)->name);
16170 mips_opts.gp32 = 0;
16172 else if (strcmp (name, "fp=default") == 0)
16173 mips_opts.fp32 = file_mips_fp32;
16174 else if (strcmp (name, "fp=32") == 0)
16175 mips_opts.fp32 = 1;
16176 else if (strcmp (name, "fp=64") == 0)
16178 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16179 as_warn (_("%s isa does not support 64-bit floating point registers"),
16180 mips_cpu_info_from_isa (mips_opts.isa)->name);
16181 mips_opts.fp32 = 0;
16183 else if (strcmp (name, "softfloat") == 0)
16184 mips_opts.soft_float = 1;
16185 else if (strcmp (name, "hardfloat") == 0)
16186 mips_opts.soft_float = 0;
16187 else if (strcmp (name, "singlefloat") == 0)
16188 mips_opts.single_float = 1;
16189 else if (strcmp (name, "doublefloat") == 0)
16190 mips_opts.single_float = 0;
16191 else if (strcmp (name, "mips16") == 0
16192 || strcmp (name, "MIPS-16") == 0)
16194 if (mips_opts.micromips == 1)
16195 as_fatal (_("`mips16' cannot be used with `micromips'"));
16196 mips_opts.mips16 = 1;
16198 else if (strcmp (name, "nomips16") == 0
16199 || strcmp (name, "noMIPS-16") == 0)
16200 mips_opts.mips16 = 0;
16201 else if (strcmp (name, "micromips") == 0)
16203 if (mips_opts.mips16 == 1)
16204 as_fatal (_("`micromips' cannot be used with `mips16'"));
16205 mips_opts.micromips = 1;
16207 else if (strcmp (name, "nomicromips") == 0)
16208 mips_opts.micromips = 0;
16209 else if (strcmp (name, "smartmips") == 0)
16211 if (!ISA_SUPPORTS_SMARTMIPS)
16212 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16213 mips_cpu_info_from_isa (mips_opts.isa)->name);
16214 mips_opts.ase_smartmips = 1;
16216 else if (strcmp (name, "nosmartmips") == 0)
16217 mips_opts.ase_smartmips = 0;
16218 else if (strcmp (name, "mips3d") == 0)
16219 mips_opts.ase_mips3d = 1;
16220 else if (strcmp (name, "nomips3d") == 0)
16221 mips_opts.ase_mips3d = 0;
16222 else if (strcmp (name, "mdmx") == 0)
16223 mips_opts.ase_mdmx = 1;
16224 else if (strcmp (name, "nomdmx") == 0)
16225 mips_opts.ase_mdmx = 0;
16226 else if (strcmp (name, "dsp") == 0)
16228 if (!ISA_SUPPORTS_DSP_ASE)
16229 as_warn (_("%s ISA does not support DSP ASE"),
16230 mips_cpu_info_from_isa (mips_opts.isa)->name);
16231 mips_opts.ase_dsp = 1;
16232 mips_opts.ase_dspr2 = 0;
16234 else if (strcmp (name, "nodsp") == 0)
16236 mips_opts.ase_dsp = 0;
16237 mips_opts.ase_dspr2 = 0;
16239 else if (strcmp (name, "dspr2") == 0)
16241 if (!ISA_SUPPORTS_DSPR2_ASE)
16242 as_warn (_("%s ISA does not support DSP R2 ASE"),
16243 mips_cpu_info_from_isa (mips_opts.isa)->name);
16244 mips_opts.ase_dspr2 = 1;
16245 mips_opts.ase_dsp = 1;
16247 else if (strcmp (name, "nodspr2") == 0)
16249 mips_opts.ase_dspr2 = 0;
16250 mips_opts.ase_dsp = 0;
16252 else if (strcmp (name, "mt") == 0)
16254 if (!ISA_SUPPORTS_MT_ASE)
16255 as_warn (_("%s ISA does not support MT ASE"),
16256 mips_cpu_info_from_isa (mips_opts.isa)->name);
16257 mips_opts.ase_mt = 1;
16259 else if (strcmp (name, "nomt") == 0)
16260 mips_opts.ase_mt = 0;
16261 else if (strcmp (name, "mcu") == 0)
16262 mips_opts.ase_mcu = 1;
16263 else if (strcmp (name, "nomcu") == 0)
16264 mips_opts.ase_mcu = 0;
16265 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16269 /* Permit the user to change the ISA and architecture on the fly.
16270 Needless to say, misuse can cause serious problems. */
16271 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16274 mips_opts.isa = file_mips_isa;
16275 mips_opts.arch = file_mips_arch;
16277 else if (strncmp (name, "arch=", 5) == 0)
16279 const struct mips_cpu_info *p;
16281 p = mips_parse_cpu("internal use", name + 5);
16283 as_bad (_("unknown architecture %s"), name + 5);
16286 mips_opts.arch = p->cpu;
16287 mips_opts.isa = p->isa;
16290 else if (strncmp (name, "mips", 4) == 0)
16292 const struct mips_cpu_info *p;
16294 p = mips_parse_cpu("internal use", name);
16296 as_bad (_("unknown ISA level %s"), name + 4);
16299 mips_opts.arch = p->cpu;
16300 mips_opts.isa = p->isa;
16304 as_bad (_("unknown ISA or architecture %s"), name);
16306 switch (mips_opts.isa)
16314 mips_opts.gp32 = 1;
16315 mips_opts.fp32 = 1;
16322 mips_opts.gp32 = 0;
16323 mips_opts.fp32 = 0;
16326 as_bad (_("unknown ISA level %s"), name + 4);
16331 mips_opts.gp32 = file_mips_gp32;
16332 mips_opts.fp32 = file_mips_fp32;
16335 else if (strcmp (name, "autoextend") == 0)
16336 mips_opts.noautoextend = 0;
16337 else if (strcmp (name, "noautoextend") == 0)
16338 mips_opts.noautoextend = 1;
16339 else if (strcmp (name, "push") == 0)
16341 struct mips_option_stack *s;
16343 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16344 s->next = mips_opts_stack;
16345 s->options = mips_opts;
16346 mips_opts_stack = s;
16348 else if (strcmp (name, "pop") == 0)
16350 struct mips_option_stack *s;
16352 s = mips_opts_stack;
16354 as_bad (_(".set pop with no .set push"));
16357 /* If we're changing the reorder mode we need to handle
16358 delay slots correctly. */
16359 if (s->options.noreorder && ! mips_opts.noreorder)
16360 start_noreorder ();
16361 else if (! s->options.noreorder && mips_opts.noreorder)
16364 mips_opts = s->options;
16365 mips_opts_stack = s->next;
16369 else if (strcmp (name, "sym32") == 0)
16370 mips_opts.sym32 = TRUE;
16371 else if (strcmp (name, "nosym32") == 0)
16372 mips_opts.sym32 = FALSE;
16373 else if (strchr (name, ','))
16375 /* Generic ".set" directive; use the generic handler. */
16376 *input_line_pointer = ch;
16377 input_line_pointer = name;
16383 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16385 *input_line_pointer = ch;
16386 demand_empty_rest_of_line ();
16389 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16390 .option pic2. It means to generate SVR4 PIC calls. */
16393 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16395 mips_pic = SVR4_PIC;
16396 mips_abicalls = TRUE;
16398 if (g_switch_seen && g_switch_value != 0)
16399 as_warn (_("-G may not be used with SVR4 PIC code"));
16400 g_switch_value = 0;
16402 bfd_set_gp_size (stdoutput, 0);
16403 demand_empty_rest_of_line ();
16406 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16407 PIC code. It sets the $gp register for the function based on the
16408 function address, which is in the register named in the argument.
16409 This uses a relocation against _gp_disp, which is handled specially
16410 by the linker. The result is:
16411 lui $gp,%hi(_gp_disp)
16412 addiu $gp,$gp,%lo(_gp_disp)
16413 addu $gp,$gp,.cpload argument
16414 The .cpload argument is normally $25 == $t9.
16416 The -mno-shared option changes this to:
16417 lui $gp,%hi(__gnu_local_gp)
16418 addiu $gp,$gp,%lo(__gnu_local_gp)
16419 and the argument is ignored. This saves an instruction, but the
16420 resulting code is not position independent; it uses an absolute
16421 address for __gnu_local_gp. Thus code assembled with -mno-shared
16422 can go into an ordinary executable, but not into a shared library. */
16425 s_cpload (int ignore ATTRIBUTE_UNUSED)
16431 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16432 .cpload is ignored. */
16433 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16439 if (mips_opts.mips16)
16441 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16442 ignore_rest_of_line ();
16446 /* .cpload should be in a .set noreorder section. */
16447 if (mips_opts.noreorder == 0)
16448 as_warn (_(".cpload not in noreorder section"));
16450 reg = tc_get_register (0);
16452 /* If we need to produce a 64-bit address, we are better off using
16453 the default instruction sequence. */
16454 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16456 ex.X_op = O_symbol;
16457 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16459 ex.X_op_symbol = NULL;
16460 ex.X_add_number = 0;
16462 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16463 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16466 macro_build_lui (&ex, mips_gp_register);
16467 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16468 mips_gp_register, BFD_RELOC_LO16);
16470 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16471 mips_gp_register, reg);
16474 demand_empty_rest_of_line ();
16477 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16478 .cpsetup $reg1, offset|$reg2, label
16480 If offset is given, this results in:
16481 sd $gp, offset($sp)
16482 lui $gp, %hi(%neg(%gp_rel(label)))
16483 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16484 daddu $gp, $gp, $reg1
16486 If $reg2 is given, this results in:
16487 daddu $reg2, $gp, $0
16488 lui $gp, %hi(%neg(%gp_rel(label)))
16489 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16490 daddu $gp, $gp, $reg1
16491 $reg1 is normally $25 == $t9.
16493 The -mno-shared option replaces the last three instructions with
16495 addiu $gp,$gp,%lo(_gp) */
16498 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16500 expressionS ex_off;
16501 expressionS ex_sym;
16504 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16505 We also need NewABI support. */
16506 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16512 if (mips_opts.mips16)
16514 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16515 ignore_rest_of_line ();
16519 reg1 = tc_get_register (0);
16520 SKIP_WHITESPACE ();
16521 if (*input_line_pointer != ',')
16523 as_bad (_("missing argument separator ',' for .cpsetup"));
16527 ++input_line_pointer;
16528 SKIP_WHITESPACE ();
16529 if (*input_line_pointer == '$')
16531 mips_cpreturn_register = tc_get_register (0);
16532 mips_cpreturn_offset = -1;
16536 mips_cpreturn_offset = get_absolute_expression ();
16537 mips_cpreturn_register = -1;
16539 SKIP_WHITESPACE ();
16540 if (*input_line_pointer != ',')
16542 as_bad (_("missing argument separator ',' for .cpsetup"));
16546 ++input_line_pointer;
16547 SKIP_WHITESPACE ();
16548 expression (&ex_sym);
16551 if (mips_cpreturn_register == -1)
16553 ex_off.X_op = O_constant;
16554 ex_off.X_add_symbol = NULL;
16555 ex_off.X_op_symbol = NULL;
16556 ex_off.X_add_number = mips_cpreturn_offset;
16558 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16559 BFD_RELOC_LO16, SP);
16562 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16563 mips_gp_register, 0);
16565 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16567 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16568 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16571 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16572 mips_gp_register, -1, BFD_RELOC_GPREL16,
16573 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16575 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16576 mips_gp_register, reg1);
16582 ex.X_op = O_symbol;
16583 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16584 ex.X_op_symbol = NULL;
16585 ex.X_add_number = 0;
16587 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16588 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16590 macro_build_lui (&ex, mips_gp_register);
16591 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16592 mips_gp_register, BFD_RELOC_LO16);
16597 demand_empty_rest_of_line ();
16601 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16603 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16604 .cplocal is ignored. */
16605 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16611 if (mips_opts.mips16)
16613 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16614 ignore_rest_of_line ();
16618 mips_gp_register = tc_get_register (0);
16619 demand_empty_rest_of_line ();
16622 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16623 offset from $sp. The offset is remembered, and after making a PIC
16624 call $gp is restored from that location. */
16627 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16631 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16632 .cprestore is ignored. */
16633 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16639 if (mips_opts.mips16)
16641 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16642 ignore_rest_of_line ();
16646 mips_cprestore_offset = get_absolute_expression ();
16647 mips_cprestore_valid = 1;
16649 ex.X_op = O_constant;
16650 ex.X_add_symbol = NULL;
16651 ex.X_op_symbol = NULL;
16652 ex.X_add_number = mips_cprestore_offset;
16655 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16656 SP, HAVE_64BIT_ADDRESSES);
16659 demand_empty_rest_of_line ();
16662 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16663 was given in the preceding .cpsetup, it results in:
16664 ld $gp, offset($sp)
16666 If a register $reg2 was given there, it results in:
16667 daddu $gp, $reg2, $0 */
16670 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16674 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16675 We also need NewABI support. */
16676 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16682 if (mips_opts.mips16)
16684 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16685 ignore_rest_of_line ();
16690 if (mips_cpreturn_register == -1)
16692 ex.X_op = O_constant;
16693 ex.X_add_symbol = NULL;
16694 ex.X_op_symbol = NULL;
16695 ex.X_add_number = mips_cpreturn_offset;
16697 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16700 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16701 mips_cpreturn_register, 0);
16704 demand_empty_rest_of_line ();
16707 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16708 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16709 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16710 debug information or MIPS16 TLS. */
16713 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16714 bfd_reloc_code_real_type rtype)
16721 if (ex.X_op != O_symbol)
16723 as_bad (_("Unsupported use of %s"), dirstr);
16724 ignore_rest_of_line ();
16727 p = frag_more (bytes);
16728 md_number_to_chars (p, 0, bytes);
16729 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16730 demand_empty_rest_of_line ();
16731 mips_clear_insn_labels ();
16734 /* Handle .dtprelword. */
16737 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16739 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16742 /* Handle .dtpreldword. */
16745 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16747 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16750 /* Handle .tprelword. */
16753 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16755 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16758 /* Handle .tpreldword. */
16761 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16763 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16766 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16767 code. It sets the offset to use in gp_rel relocations. */
16770 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16772 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16773 We also need NewABI support. */
16774 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16780 mips_gprel_offset = get_absolute_expression ();
16782 demand_empty_rest_of_line ();
16785 /* Handle the .gpword pseudo-op. This is used when generating PIC
16786 code. It generates a 32 bit GP relative reloc. */
16789 s_gpword (int ignore ATTRIBUTE_UNUSED)
16791 segment_info_type *si;
16792 struct insn_label_list *l;
16796 /* When not generating PIC code, this is treated as .word. */
16797 if (mips_pic != SVR4_PIC)
16803 si = seg_info (now_seg);
16804 l = si->label_list;
16805 mips_emit_delays ();
16807 mips_align (2, 0, l);
16810 mips_clear_insn_labels ();
16812 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16814 as_bad (_("Unsupported use of .gpword"));
16815 ignore_rest_of_line ();
16819 md_number_to_chars (p, 0, 4);
16820 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16821 BFD_RELOC_GPREL32);
16823 demand_empty_rest_of_line ();
16827 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16829 segment_info_type *si;
16830 struct insn_label_list *l;
16834 /* When not generating PIC code, this is treated as .dword. */
16835 if (mips_pic != SVR4_PIC)
16841 si = seg_info (now_seg);
16842 l = si->label_list;
16843 mips_emit_delays ();
16845 mips_align (3, 0, l);
16848 mips_clear_insn_labels ();
16850 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16852 as_bad (_("Unsupported use of .gpdword"));
16853 ignore_rest_of_line ();
16857 md_number_to_chars (p, 0, 8);
16858 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16859 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16861 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16862 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16863 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16865 demand_empty_rest_of_line ();
16868 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16869 tables in SVR4 PIC code. */
16872 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16876 /* This is ignored when not generating SVR4 PIC code. */
16877 if (mips_pic != SVR4_PIC)
16883 /* Add $gp to the register named as an argument. */
16885 reg = tc_get_register (0);
16886 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16889 demand_empty_rest_of_line ();
16892 /* Handle the .insn pseudo-op. This marks instruction labels in
16893 mips16/micromips mode. This permits the linker to handle them specially,
16894 such as generating jalx instructions when needed. We also make
16895 them odd for the duration of the assembly, in order to generate the
16896 right sort of code. We will make them even in the adjust_symtab
16897 routine, while leaving them marked. This is convenient for the
16898 debugger and the disassembler. The linker knows to make them odd
16902 s_insn (int ignore ATTRIBUTE_UNUSED)
16904 mips_mark_labels ();
16906 demand_empty_rest_of_line ();
16909 /* Handle a .stabn directive. We need these in order to mark a label
16910 as being a mips16 text label correctly. Sometimes the compiler
16911 will emit a label, followed by a .stabn, and then switch sections.
16912 If the label and .stabn are in mips16 mode, then the label is
16913 really a mips16 text label. */
16916 s_mips_stab (int type)
16919 mips_mark_labels ();
16924 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16927 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16934 name = input_line_pointer;
16935 c = get_symbol_end ();
16936 symbolP = symbol_find_or_make (name);
16937 S_SET_WEAK (symbolP);
16938 *input_line_pointer = c;
16940 SKIP_WHITESPACE ();
16942 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16944 if (S_IS_DEFINED (symbolP))
16946 as_bad (_("ignoring attempt to redefine symbol %s"),
16947 S_GET_NAME (symbolP));
16948 ignore_rest_of_line ();
16952 if (*input_line_pointer == ',')
16954 ++input_line_pointer;
16955 SKIP_WHITESPACE ();
16959 if (exp.X_op != O_symbol)
16961 as_bad (_("bad .weakext directive"));
16962 ignore_rest_of_line ();
16965 symbol_set_value_expression (symbolP, &exp);
16968 demand_empty_rest_of_line ();
16971 /* Parse a register string into a number. Called from the ECOFF code
16972 to parse .frame. The argument is non-zero if this is the frame
16973 register, so that we can record it in mips_frame_reg. */
16976 tc_get_register (int frame)
16980 SKIP_WHITESPACE ();
16981 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16985 mips_frame_reg = reg != 0 ? reg : SP;
16986 mips_frame_reg_valid = 1;
16987 mips_cprestore_valid = 0;
16993 md_section_align (asection *seg, valueT addr)
16995 int align = bfd_get_section_alignment (stdoutput, seg);
16999 /* We don't need to align ELF sections to the full alignment.
17000 However, Irix 5 may prefer that we align them at least to a 16
17001 byte boundary. We don't bother to align the sections if we
17002 are targeted for an embedded system. */
17003 if (strncmp (TARGET_OS, "elf", 3) == 0)
17009 return ((addr + (1 << align) - 1) & (-1 << align));
17012 /* Utility routine, called from above as well. If called while the
17013 input file is still being read, it's only an approximation. (For
17014 example, a symbol may later become defined which appeared to be
17015 undefined earlier.) */
17018 nopic_need_relax (symbolS *sym, int before_relaxing)
17023 if (g_switch_value > 0)
17025 const char *symname;
17028 /* Find out whether this symbol can be referenced off the $gp
17029 register. It can be if it is smaller than the -G size or if
17030 it is in the .sdata or .sbss section. Certain symbols can
17031 not be referenced off the $gp, although it appears as though
17033 symname = S_GET_NAME (sym);
17034 if (symname != (const char *) NULL
17035 && (strcmp (symname, "eprol") == 0
17036 || strcmp (symname, "etext") == 0
17037 || strcmp (symname, "_gp") == 0
17038 || strcmp (symname, "edata") == 0
17039 || strcmp (symname, "_fbss") == 0
17040 || strcmp (symname, "_fdata") == 0
17041 || strcmp (symname, "_ftext") == 0
17042 || strcmp (symname, "end") == 0
17043 || strcmp (symname, "_gp_disp") == 0))
17045 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17047 #ifndef NO_ECOFF_DEBUGGING
17048 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17049 && (symbol_get_obj (sym)->ecoff_extern_size
17050 <= g_switch_value))
17052 /* We must defer this decision until after the whole
17053 file has been read, since there might be a .extern
17054 after the first use of this symbol. */
17055 || (before_relaxing
17056 #ifndef NO_ECOFF_DEBUGGING
17057 && symbol_get_obj (sym)->ecoff_extern_size == 0
17059 && S_GET_VALUE (sym) == 0)
17060 || (S_GET_VALUE (sym) != 0
17061 && S_GET_VALUE (sym) <= g_switch_value)))
17065 const char *segname;
17067 segname = segment_name (S_GET_SEGMENT (sym));
17068 gas_assert (strcmp (segname, ".lit8") != 0
17069 && strcmp (segname, ".lit4") != 0);
17070 change = (strcmp (segname, ".sdata") != 0
17071 && strcmp (segname, ".sbss") != 0
17072 && strncmp (segname, ".sdata.", 7) != 0
17073 && strncmp (segname, ".sbss.", 6) != 0
17074 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17075 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17080 /* We are not optimizing for the $gp register. */
17085 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17088 pic_need_relax (symbolS *sym, asection *segtype)
17092 /* Handle the case of a symbol equated to another symbol. */
17093 while (symbol_equated_reloc_p (sym))
17097 /* It's possible to get a loop here in a badly written program. */
17098 n = symbol_get_value_expression (sym)->X_add_symbol;
17104 if (symbol_section_p (sym))
17107 symsec = S_GET_SEGMENT (sym);
17109 /* This must duplicate the test in adjust_reloc_syms. */
17110 return (!bfd_is_und_section (symsec)
17111 && !bfd_is_abs_section (symsec)
17112 && !bfd_is_com_section (symsec)
17113 && !s_is_linkonce (sym, segtype)
17115 /* A global or weak symbol is treated as external. */
17116 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17122 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17123 extended opcode. SEC is the section the frag is in. */
17126 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17129 const struct mips16_immed_operand *op;
17131 int mintiny, maxtiny;
17135 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17137 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17140 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17141 op = mips16_immed_operands;
17142 while (op->type != type)
17145 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17150 if (type == '<' || type == '>' || type == '[' || type == ']')
17153 maxtiny = 1 << op->nbits;
17158 maxtiny = (1 << op->nbits) - 1;
17163 mintiny = - (1 << (op->nbits - 1));
17164 maxtiny = (1 << (op->nbits - 1)) - 1;
17167 sym_frag = symbol_get_frag (fragp->fr_symbol);
17168 val = S_GET_VALUE (fragp->fr_symbol);
17169 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17175 /* We won't have the section when we are called from
17176 mips_relax_frag. However, we will always have been called
17177 from md_estimate_size_before_relax first. If this is a
17178 branch to a different section, we mark it as such. If SEC is
17179 NULL, and the frag is not marked, then it must be a branch to
17180 the same section. */
17183 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17188 /* Must have been called from md_estimate_size_before_relax. */
17191 fragp->fr_subtype =
17192 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17194 /* FIXME: We should support this, and let the linker
17195 catch branches and loads that are out of range. */
17196 as_bad_where (fragp->fr_file, fragp->fr_line,
17197 _("unsupported PC relative reference to different section"));
17201 if (fragp != sym_frag && sym_frag->fr_address == 0)
17202 /* Assume non-extended on the first relaxation pass.
17203 The address we have calculated will be bogus if this is
17204 a forward branch to another frag, as the forward frag
17205 will have fr_address == 0. */
17209 /* In this case, we know for sure that the symbol fragment is in
17210 the same section. If the relax_marker of the symbol fragment
17211 differs from the relax_marker of this fragment, we have not
17212 yet adjusted the symbol fragment fr_address. We want to add
17213 in STRETCH in order to get a better estimate of the address.
17214 This particularly matters because of the shift bits. */
17216 && sym_frag->relax_marker != fragp->relax_marker)
17220 /* Adjust stretch for any alignment frag. Note that if have
17221 been expanding the earlier code, the symbol may be
17222 defined in what appears to be an earlier frag. FIXME:
17223 This doesn't handle the fr_subtype field, which specifies
17224 a maximum number of bytes to skip when doing an
17226 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17228 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17231 stretch = - ((- stretch)
17232 & ~ ((1 << (int) f->fr_offset) - 1));
17234 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17243 addr = fragp->fr_address + fragp->fr_fix;
17245 /* The base address rules are complicated. The base address of
17246 a branch is the following instruction. The base address of a
17247 PC relative load or add is the instruction itself, but if it
17248 is in a delay slot (in which case it can not be extended) use
17249 the address of the instruction whose delay slot it is in. */
17250 if (type == 'p' || type == 'q')
17254 /* If we are currently assuming that this frag should be
17255 extended, then, the current address is two bytes
17257 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17260 /* Ignore the low bit in the target, since it will be set
17261 for a text label. */
17262 if ((val & 1) != 0)
17265 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17267 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17270 val -= addr & ~ ((1 << op->shift) - 1);
17272 /* Branch offsets have an implicit 0 in the lowest bit. */
17273 if (type == 'p' || type == 'q')
17276 /* If any of the shifted bits are set, we must use an extended
17277 opcode. If the address depends on the size of this
17278 instruction, this can lead to a loop, so we arrange to always
17279 use an extended opcode. We only check this when we are in
17280 the main relaxation loop, when SEC is NULL. */
17281 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17283 fragp->fr_subtype =
17284 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17288 /* If we are about to mark a frag as extended because the value
17289 is precisely maxtiny + 1, then there is a chance of an
17290 infinite loop as in the following code:
17295 In this case when the la is extended, foo is 0x3fc bytes
17296 away, so the la can be shrunk, but then foo is 0x400 away, so
17297 the la must be extended. To avoid this loop, we mark the
17298 frag as extended if it was small, and is about to become
17299 extended with a value of maxtiny + 1. */
17300 if (val == ((maxtiny + 1) << op->shift)
17301 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17304 fragp->fr_subtype =
17305 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17309 else if (symsec != absolute_section && sec != NULL)
17310 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17312 if ((val & ((1 << op->shift) - 1)) != 0
17313 || val < (mintiny << op->shift)
17314 || val > (maxtiny << op->shift))
17320 /* Compute the length of a branch sequence, and adjust the
17321 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17322 worst-case length is computed, with UPDATE being used to indicate
17323 whether an unconditional (-1), branch-likely (+1) or regular (0)
17324 branch is to be computed. */
17326 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17328 bfd_boolean toofar;
17332 && S_IS_DEFINED (fragp->fr_symbol)
17333 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17338 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17340 addr = fragp->fr_address + fragp->fr_fix + 4;
17344 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17347 /* If the symbol is not defined or it's in a different segment,
17348 assume the user knows what's going on and emit a short
17354 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17356 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17357 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17358 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17359 RELAX_BRANCH_LINK (fragp->fr_subtype),
17365 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17368 if (mips_pic != NO_PIC)
17370 /* Additional space for PIC loading of target address. */
17372 if (mips_opts.isa == ISA_MIPS1)
17373 /* Additional space for $at-stabilizing nop. */
17377 /* If branch is conditional. */
17378 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17385 /* Compute the length of a branch sequence, and adjust the
17386 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17387 worst-case length is computed, with UPDATE being used to indicate
17388 whether an unconditional (-1), or regular (0) branch is to be
17392 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17394 bfd_boolean toofar;
17398 && S_IS_DEFINED (fragp->fr_symbol)
17399 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17404 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17405 /* Ignore the low bit in the target, since it will be set
17406 for a text label. */
17407 if ((val & 1) != 0)
17410 addr = fragp->fr_address + fragp->fr_fix + 4;
17414 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17417 /* If the symbol is not defined or it's in a different segment,
17418 assume the user knows what's going on and emit a short
17424 if (fragp && update
17425 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17426 fragp->fr_subtype = (toofar
17427 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17428 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17433 bfd_boolean compact_known = fragp != NULL;
17434 bfd_boolean compact = FALSE;
17435 bfd_boolean uncond;
17438 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17440 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17442 uncond = update < 0;
17444 /* If label is out of range, we turn branch <br>:
17446 <br> label # 4 bytes
17452 nop # 2 bytes if compact && !PIC
17455 if (mips_pic == NO_PIC && (!compact_known || compact))
17458 /* If assembling PIC code, we further turn:
17464 lw/ld at, %got(label)(gp) # 4 bytes
17465 d/addiu at, %lo(label) # 4 bytes
17468 if (mips_pic != NO_PIC)
17471 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17473 <brneg> 0f # 4 bytes
17474 nop # 2 bytes if !compact
17477 length += (compact_known && compact) ? 4 : 6;
17483 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17484 bit accordingly. */
17487 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17489 bfd_boolean toofar;
17492 && S_IS_DEFINED (fragp->fr_symbol)
17493 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17499 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17500 /* Ignore the low bit in the target, since it will be set
17501 for a text label. */
17502 if ((val & 1) != 0)
17505 /* Assume this is a 2-byte branch. */
17506 addr = fragp->fr_address + fragp->fr_fix + 2;
17508 /* We try to avoid the infinite loop by not adding 2 more bytes for
17513 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17515 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17516 else if (type == 'E')
17517 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17522 /* If the symbol is not defined or it's in a different segment,
17523 we emit a normal 32-bit branch. */
17526 if (fragp && update
17527 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17529 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17530 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17538 /* Estimate the size of a frag before relaxing. Unless this is the
17539 mips16, we are not really relaxing here, and the final size is
17540 encoded in the subtype information. For the mips16, we have to
17541 decide whether we are using an extended opcode or not. */
17544 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17548 if (RELAX_BRANCH_P (fragp->fr_subtype))
17551 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17553 return fragp->fr_var;
17556 if (RELAX_MIPS16_P (fragp->fr_subtype))
17557 /* We don't want to modify the EXTENDED bit here; it might get us
17558 into infinite loops. We change it only in mips_relax_frag(). */
17559 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17561 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17565 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17566 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17567 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17568 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17569 fragp->fr_var = length;
17574 if (mips_pic == NO_PIC)
17575 change = nopic_need_relax (fragp->fr_symbol, 0);
17576 else if (mips_pic == SVR4_PIC)
17577 change = pic_need_relax (fragp->fr_symbol, segtype);
17578 else if (mips_pic == VXWORKS_PIC)
17579 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17586 fragp->fr_subtype |= RELAX_USE_SECOND;
17587 return -RELAX_FIRST (fragp->fr_subtype);
17590 return -RELAX_SECOND (fragp->fr_subtype);
17593 /* This is called to see whether a reloc against a defined symbol
17594 should be converted into a reloc against a section. */
17597 mips_fix_adjustable (fixS *fixp)
17599 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17600 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17603 if (fixp->fx_addsy == NULL)
17606 /* If symbol SYM is in a mergeable section, relocations of the form
17607 SYM + 0 can usually be made section-relative. The mergeable data
17608 is then identified by the section offset rather than by the symbol.
17610 However, if we're generating REL LO16 relocations, the offset is split
17611 between the LO16 and parterning high part relocation. The linker will
17612 need to recalculate the complete offset in order to correctly identify
17615 The linker has traditionally not looked for the parterning high part
17616 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17617 placed anywhere. Rather than break backwards compatibility by changing
17618 this, it seems better not to force the issue, and instead keep the
17619 original symbol. This will work with either linker behavior. */
17620 if ((lo16_reloc_p (fixp->fx_r_type)
17621 || reloc_needs_lo_p (fixp->fx_r_type))
17622 && HAVE_IN_PLACE_ADDENDS
17623 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17626 /* There is no place to store an in-place offset for JALR relocations.
17627 Likewise an in-range offset of PC-relative relocations may overflow
17628 the in-place relocatable field if recalculated against the start
17629 address of the symbol's containing section. */
17630 if (HAVE_IN_PLACE_ADDENDS
17631 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17635 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17636 to a floating-point stub. The same is true for non-R_MIPS16_26
17637 relocations against MIPS16 functions; in this case, the stub becomes
17638 the function's canonical address.
17640 Floating-point stubs are stored in unique .mips16.call.* or
17641 .mips16.fn.* sections. If a stub T for function F is in section S,
17642 the first relocation in section S must be against F; this is how the
17643 linker determines the target function. All relocations that might
17644 resolve to T must also be against F. We therefore have the following
17645 restrictions, which are given in an intentionally-redundant way:
17647 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17650 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17651 if that stub might be used.
17653 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17656 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17657 that stub might be used.
17659 There is a further restriction:
17661 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17662 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17663 targets with in-place addends; the relocation field cannot
17664 encode the low bit.
17666 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17667 against a MIPS16 symbol. We deal with (5) by by not reducing any
17668 such relocations on REL targets.
17670 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17671 relocation against some symbol R, no relocation against R may be
17672 reduced. (Note that this deals with (2) as well as (1) because
17673 relocations against global symbols will never be reduced on ELF
17674 targets.) This approach is a little simpler than trying to detect
17675 stub sections, and gives the "all or nothing" per-symbol consistency
17676 that we have for MIPS16 symbols. */
17678 && fixp->fx_subsy == NULL
17679 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17680 || *symbol_get_tc (fixp->fx_addsy)
17681 || (HAVE_IN_PLACE_ADDENDS
17682 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17683 && jmp_reloc_p (fixp->fx_r_type))))
17690 /* Translate internal representation of relocation info to BFD target
17694 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17696 static arelent *retval[4];
17698 bfd_reloc_code_real_type code;
17700 memset (retval, 0, sizeof(retval));
17701 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17702 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17703 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17704 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17706 if (fixp->fx_pcrel)
17708 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17709 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17710 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17711 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17713 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17714 Relocations want only the symbol offset. */
17715 reloc->addend = fixp->fx_addnumber + reloc->address;
17718 /* A gruesome hack which is a result of the gruesome gas
17719 reloc handling. What's worse, for COFF (as opposed to
17720 ECOFF), we might need yet another copy of reloc->address.
17721 See bfd_install_relocation. */
17722 reloc->addend += reloc->address;
17726 reloc->addend = fixp->fx_addnumber;
17728 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17729 entry to be used in the relocation's section offset. */
17730 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17732 reloc->address = reloc->addend;
17736 code = fixp->fx_r_type;
17738 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17739 if (reloc->howto == NULL)
17741 as_bad_where (fixp->fx_file, fixp->fx_line,
17742 _("Can not represent %s relocation in this object file format"),
17743 bfd_get_reloc_code_name (code));
17750 /* Relax a machine dependent frag. This returns the amount by which
17751 the current size of the frag should change. */
17754 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17756 if (RELAX_BRANCH_P (fragp->fr_subtype))
17758 offsetT old_var = fragp->fr_var;
17760 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17762 return fragp->fr_var - old_var;
17765 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17767 offsetT old_var = fragp->fr_var;
17768 offsetT new_var = 4;
17770 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17771 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17772 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17773 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17774 fragp->fr_var = new_var;
17776 return new_var - old_var;
17779 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17782 if (mips16_extended_frag (fragp, NULL, stretch))
17784 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17786 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17791 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17793 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17800 /* Convert a machine dependent frag. */
17803 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17805 if (RELAX_BRANCH_P (fragp->fr_subtype))
17808 unsigned long insn;
17812 buf = fragp->fr_literal + fragp->fr_fix;
17813 insn = read_insn (buf);
17815 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17817 /* We generate a fixup instead of applying it right now
17818 because, if there are linker relaxations, we're going to
17819 need the relocations. */
17820 exp.X_op = O_symbol;
17821 exp.X_add_symbol = fragp->fr_symbol;
17822 exp.X_add_number = fragp->fr_offset;
17824 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17825 BFD_RELOC_16_PCREL_S2);
17826 fixp->fx_file = fragp->fr_file;
17827 fixp->fx_line = fragp->fr_line;
17829 buf = write_insn (buf, insn);
17835 as_warn_where (fragp->fr_file, fragp->fr_line,
17836 _("Relaxed out-of-range branch into a jump"));
17838 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17841 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17843 /* Reverse the branch. */
17844 switch ((insn >> 28) & 0xf)
17847 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17848 have the condition reversed by tweaking a single
17849 bit, and their opcodes all have 0x4???????. */
17850 gas_assert ((insn & 0xf1000000) == 0x41000000);
17851 insn ^= 0x00010000;
17855 /* bltz 0x04000000 bgez 0x04010000
17856 bltzal 0x04100000 bgezal 0x04110000 */
17857 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17858 insn ^= 0x00010000;
17862 /* beq 0x10000000 bne 0x14000000
17863 blez 0x18000000 bgtz 0x1c000000 */
17864 insn ^= 0x04000000;
17872 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17874 /* Clear the and-link bit. */
17875 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17877 /* bltzal 0x04100000 bgezal 0x04110000
17878 bltzall 0x04120000 bgezall 0x04130000 */
17879 insn &= ~0x00100000;
17882 /* Branch over the branch (if the branch was likely) or the
17883 full jump (not likely case). Compute the offset from the
17884 current instruction to branch to. */
17885 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17889 /* How many bytes in instructions we've already emitted? */
17890 i = buf - fragp->fr_literal - fragp->fr_fix;
17891 /* How many bytes in instructions from here to the end? */
17892 i = fragp->fr_var - i;
17894 /* Convert to instruction count. */
17896 /* Branch counts from the next instruction. */
17899 /* Branch over the jump. */
17900 buf = write_insn (buf, insn);
17903 buf = write_insn (buf, 0);
17905 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17907 /* beql $0, $0, 2f */
17909 /* Compute the PC offset from the current instruction to
17910 the end of the variable frag. */
17911 /* How many bytes in instructions we've already emitted? */
17912 i = buf - fragp->fr_literal - fragp->fr_fix;
17913 /* How many bytes in instructions from here to the end? */
17914 i = fragp->fr_var - i;
17915 /* Convert to instruction count. */
17917 /* Don't decrement i, because we want to branch over the
17921 buf = write_insn (buf, insn);
17922 buf = write_insn (buf, 0);
17926 if (mips_pic == NO_PIC)
17929 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17930 ? 0x0c000000 : 0x08000000);
17931 exp.X_op = O_symbol;
17932 exp.X_add_symbol = fragp->fr_symbol;
17933 exp.X_add_number = fragp->fr_offset;
17935 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17936 FALSE, BFD_RELOC_MIPS_JMP);
17937 fixp->fx_file = fragp->fr_file;
17938 fixp->fx_line = fragp->fr_line;
17940 buf = write_insn (buf, insn);
17944 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17946 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17947 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17948 insn |= at << OP_SH_RT;
17949 exp.X_op = O_symbol;
17950 exp.X_add_symbol = fragp->fr_symbol;
17951 exp.X_add_number = fragp->fr_offset;
17953 if (fragp->fr_offset)
17955 exp.X_add_symbol = make_expr_symbol (&exp);
17956 exp.X_add_number = 0;
17959 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17960 FALSE, BFD_RELOC_MIPS_GOT16);
17961 fixp->fx_file = fragp->fr_file;
17962 fixp->fx_line = fragp->fr_line;
17964 buf = write_insn (buf, insn);
17966 if (mips_opts.isa == ISA_MIPS1)
17968 buf = write_insn (buf, 0);
17970 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17971 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17972 insn |= at << OP_SH_RS | at << OP_SH_RT;
17974 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17975 FALSE, BFD_RELOC_LO16);
17976 fixp->fx_file = fragp->fr_file;
17977 fixp->fx_line = fragp->fr_line;
17979 buf = write_insn (buf, insn);
17982 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17986 insn |= at << OP_SH_RS;
17988 buf = write_insn (buf, insn);
17992 fragp->fr_fix += fragp->fr_var;
17993 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17997 /* Relax microMIPS branches. */
17998 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18000 char *buf = fragp->fr_literal + fragp->fr_fix;
18001 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18002 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18003 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18004 bfd_boolean short_ds;
18005 unsigned long insn;
18009 exp.X_op = O_symbol;
18010 exp.X_add_symbol = fragp->fr_symbol;
18011 exp.X_add_number = fragp->fr_offset;
18013 fragp->fr_fix += fragp->fr_var;
18015 /* Handle 16-bit branches that fit or are forced to fit. */
18016 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18018 /* We generate a fixup instead of applying it right now,
18019 because if there is linker relaxation, we're going to
18020 need the relocations. */
18022 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18023 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18024 else if (type == 'E')
18025 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18026 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18030 fixp->fx_file = fragp->fr_file;
18031 fixp->fx_line = fragp->fr_line;
18033 /* These relocations can have an addend that won't fit in
18035 fixp->fx_no_overflow = 1;
18040 /* Handle 32-bit branches that fit or are forced to fit. */
18041 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18042 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18044 /* We generate a fixup instead of applying it right now,
18045 because if there is linker relaxation, we're going to
18046 need the relocations. */
18047 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18048 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18049 fixp->fx_file = fragp->fr_file;
18050 fixp->fx_line = fragp->fr_line;
18056 /* Relax 16-bit branches to 32-bit branches. */
18059 insn = read_compressed_insn (buf, 2);
18061 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18062 insn = 0x94000000; /* beq */
18063 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18065 unsigned long regno;
18067 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18068 regno = micromips_to_32_reg_d_map [regno];
18069 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18070 insn |= regno << MICROMIPSOP_SH_RS;
18075 /* Nothing else to do, just write it out. */
18076 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18077 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18079 buf = write_compressed_insn (buf, insn, 4);
18080 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18085 insn = read_compressed_insn (buf, 4);
18087 /* Relax 32-bit branches to a sequence of instructions. */
18088 as_warn_where (fragp->fr_file, fragp->fr_line,
18089 _("Relaxed out-of-range branch into a jump"));
18091 /* Set the short-delay-slot bit. */
18092 short_ds = al && (insn & 0x02000000) != 0;
18094 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18098 /* Reverse the branch. */
18099 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18100 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18101 insn ^= 0x20000000;
18102 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18103 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18104 || (insn & 0xffe00000) == 0x40800000 /* blez */
18105 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18106 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18107 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18108 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18109 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18110 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18111 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18112 insn ^= 0x00400000;
18113 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18114 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18115 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18116 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18117 insn ^= 0x00200000;
18123 /* Clear the and-link and short-delay-slot bits. */
18124 gas_assert ((insn & 0xfda00000) == 0x40200000);
18126 /* bltzal 0x40200000 bgezal 0x40600000 */
18127 /* bltzals 0x42200000 bgezals 0x42600000 */
18128 insn &= ~0x02200000;
18131 /* Make a label at the end for use with the branch. */
18132 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18133 micromips_label_inc ();
18134 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18136 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18140 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18141 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18142 fixp->fx_file = fragp->fr_file;
18143 fixp->fx_line = fragp->fr_line;
18145 /* Branch over the jump. */
18146 buf = write_compressed_insn (buf, insn, 4);
18149 buf = write_compressed_insn (buf, 0x0c00, 2);
18152 if (mips_pic == NO_PIC)
18154 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18156 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18157 insn = al ? jal : 0xd4000000;
18159 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18160 BFD_RELOC_MICROMIPS_JMP);
18161 fixp->fx_file = fragp->fr_file;
18162 fixp->fx_line = fragp->fr_line;
18164 buf = write_compressed_insn (buf, insn, 4);
18167 buf = write_compressed_insn (buf, 0x0c00, 2);
18171 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18172 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18173 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18175 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18176 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18177 insn |= at << MICROMIPSOP_SH_RT;
18179 if (exp.X_add_number)
18181 exp.X_add_symbol = make_expr_symbol (&exp);
18182 exp.X_add_number = 0;
18185 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18186 BFD_RELOC_MICROMIPS_GOT16);
18187 fixp->fx_file = fragp->fr_file;
18188 fixp->fx_line = fragp->fr_line;
18190 buf = write_compressed_insn (buf, insn, 4);
18192 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18193 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18194 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18196 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18197 BFD_RELOC_MICROMIPS_LO16);
18198 fixp->fx_file = fragp->fr_file;
18199 fixp->fx_line = fragp->fr_line;
18201 buf = write_compressed_insn (buf, insn, 4);
18203 /* jr/jrc/jalr/jalrs $at */
18204 insn = al ? jalr : jr;
18205 insn |= at << MICROMIPSOP_SH_MJ;
18207 buf = write_compressed_insn (buf, insn, 2);
18210 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18214 if (RELAX_MIPS16_P (fragp->fr_subtype))
18217 const struct mips16_immed_operand *op;
18220 unsigned int user_length, length;
18221 unsigned long insn;
18224 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18225 op = mips16_immed_operands;
18226 while (op->type != type)
18229 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18230 val = resolve_symbol_value (fragp->fr_symbol);
18235 addr = fragp->fr_address + fragp->fr_fix;
18237 /* The rules for the base address of a PC relative reloc are
18238 complicated; see mips16_extended_frag. */
18239 if (type == 'p' || type == 'q')
18244 /* Ignore the low bit in the target, since it will be
18245 set for a text label. */
18246 if ((val & 1) != 0)
18249 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18251 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18254 addr &= ~ (addressT) ((1 << op->shift) - 1);
18257 /* Make sure the section winds up with the alignment we have
18260 record_alignment (asec, op->shift);
18264 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18265 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18266 as_warn_where (fragp->fr_file, fragp->fr_line,
18267 _("extended instruction in delay slot"));
18269 buf = fragp->fr_literal + fragp->fr_fix;
18271 insn = read_compressed_insn (buf, 2);
18273 insn |= MIPS16_EXTEND;
18275 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18277 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18282 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18283 BFD_RELOC_NONE, val, user_length, &insn);
18285 length = (ext ? 4 : 2);
18286 gas_assert (mips16_opcode_length (insn) == length);
18287 write_compressed_insn (buf, insn, length);
18288 fragp->fr_fix += length;
18292 relax_substateT subtype = fragp->fr_subtype;
18293 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18294 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18298 first = RELAX_FIRST (subtype);
18299 second = RELAX_SECOND (subtype);
18300 fixp = (fixS *) fragp->fr_opcode;
18302 /* If the delay slot chosen does not match the size of the instruction,
18303 then emit a warning. */
18304 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18305 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18310 s = subtype & (RELAX_DELAY_SLOT_16BIT
18311 | RELAX_DELAY_SLOT_SIZE_FIRST
18312 | RELAX_DELAY_SLOT_SIZE_SECOND);
18313 msg = macro_warning (s);
18315 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18319 /* Possibly emit a warning if we've chosen the longer option. */
18320 if (use_second == second_longer)
18326 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18327 msg = macro_warning (s);
18329 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18333 /* Go through all the fixups for the first sequence. Disable them
18334 (by marking them as done) if we're going to use the second
18335 sequence instead. */
18337 && fixp->fx_frag == fragp
18338 && fixp->fx_where < fragp->fr_fix - second)
18340 if (subtype & RELAX_USE_SECOND)
18342 fixp = fixp->fx_next;
18345 /* Go through the fixups for the second sequence. Disable them if
18346 we're going to use the first sequence, otherwise adjust their
18347 addresses to account for the relaxation. */
18348 while (fixp && fixp->fx_frag == fragp)
18350 if (subtype & RELAX_USE_SECOND)
18351 fixp->fx_where -= first;
18354 fixp = fixp->fx_next;
18357 /* Now modify the frag contents. */
18358 if (subtype & RELAX_USE_SECOND)
18362 start = fragp->fr_literal + fragp->fr_fix - first - second;
18363 memmove (start, start + first, second);
18364 fragp->fr_fix -= first;
18367 fragp->fr_fix -= second;
18373 /* This function is called after the relocs have been generated.
18374 We've been storing mips16 text labels as odd. Here we convert them
18375 back to even for the convenience of the debugger. */
18378 mips_frob_file_after_relocs (void)
18381 unsigned int count, i;
18386 syms = bfd_get_outsymbols (stdoutput);
18387 count = bfd_get_symcount (stdoutput);
18388 for (i = 0; i < count; i++, syms++)
18389 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18390 && ((*syms)->value & 1) != 0)
18392 (*syms)->value &= ~1;
18393 /* If the symbol has an odd size, it was probably computed
18394 incorrectly, so adjust that as well. */
18395 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18396 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18402 /* This function is called whenever a label is defined, including fake
18403 labels instantiated off the dot special symbol. It is used when
18404 handling branch delays; if a branch has a label, we assume we cannot
18405 move it. This also bumps the value of the symbol by 1 in compressed
18409 mips_record_label (symbolS *sym)
18411 segment_info_type *si = seg_info (now_seg);
18412 struct insn_label_list *l;
18414 if (free_insn_labels == NULL)
18415 l = (struct insn_label_list *) xmalloc (sizeof *l);
18418 l = free_insn_labels;
18419 free_insn_labels = l->next;
18423 l->next = si->label_list;
18424 si->label_list = l;
18427 /* This function is called as tc_frob_label() whenever a label is defined
18428 and adds a DWARF-2 record we only want for true labels. */
18431 mips_define_label (symbolS *sym)
18433 mips_record_label (sym);
18435 dwarf2_emit_label (sym);
18439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18441 /* Some special processing for a MIPS ELF file. */
18444 mips_elf_final_processing (void)
18446 /* Write out the register information. */
18447 if (mips_abi != N64_ABI)
18451 s.ri_gprmask = mips_gprmask;
18452 s.ri_cprmask[0] = mips_cprmask[0];
18453 s.ri_cprmask[1] = mips_cprmask[1];
18454 s.ri_cprmask[2] = mips_cprmask[2];
18455 s.ri_cprmask[3] = mips_cprmask[3];
18456 /* The gp_value field is set by the MIPS ELF backend. */
18458 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18459 ((Elf32_External_RegInfo *)
18460 mips_regmask_frag));
18464 Elf64_Internal_RegInfo s;
18466 s.ri_gprmask = mips_gprmask;
18468 s.ri_cprmask[0] = mips_cprmask[0];
18469 s.ri_cprmask[1] = mips_cprmask[1];
18470 s.ri_cprmask[2] = mips_cprmask[2];
18471 s.ri_cprmask[3] = mips_cprmask[3];
18472 /* The gp_value field is set by the MIPS ELF backend. */
18474 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18475 ((Elf64_External_RegInfo *)
18476 mips_regmask_frag));
18479 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18480 sort of BFD interface for this. */
18481 if (mips_any_noreorder)
18482 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18483 if (mips_pic != NO_PIC)
18485 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18486 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18489 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18491 /* Set MIPS ELF flags for ASEs. */
18492 /* We may need to define a new flag for DSP ASE, and set this flag when
18493 file_ase_dsp is true. */
18494 /* Same for DSP R2. */
18495 /* We may need to define a new flag for MT ASE, and set this flag when
18496 file_ase_mt is true. */
18497 if (file_ase_mips16)
18498 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18499 if (file_ase_micromips)
18500 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18501 #if 0 /* XXX FIXME */
18502 if (file_ase_mips3d)
18503 elf_elfheader (stdoutput)->e_flags |= ???;
18506 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18508 /* Set the MIPS ELF ABI flags. */
18509 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18510 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18511 else if (mips_abi == O64_ABI)
18512 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18513 else if (mips_abi == EABI_ABI)
18515 if (!file_mips_gp32)
18516 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18518 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18520 else if (mips_abi == N32_ABI)
18521 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18523 /* Nothing to do for N64_ABI. */
18525 if (mips_32bitmode)
18526 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18528 #if 0 /* XXX FIXME */
18529 /* 32 bit code with 64 bit FP registers. */
18530 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18531 elf_elfheader (stdoutput)->e_flags |= ???;
18535 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18537 typedef struct proc {
18539 symbolS *func_end_sym;
18540 unsigned long reg_mask;
18541 unsigned long reg_offset;
18542 unsigned long fpreg_mask;
18543 unsigned long fpreg_offset;
18544 unsigned long frame_offset;
18545 unsigned long frame_reg;
18546 unsigned long pc_reg;
18549 static procS cur_proc;
18550 static procS *cur_proc_ptr;
18551 static int numprocs;
18553 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18554 as "2", and a normal nop as "0". */
18556 #define NOP_OPCODE_MIPS 0
18557 #define NOP_OPCODE_MIPS16 1
18558 #define NOP_OPCODE_MICROMIPS 2
18561 mips_nop_opcode (void)
18563 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18564 return NOP_OPCODE_MICROMIPS;
18565 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18566 return NOP_OPCODE_MIPS16;
18568 return NOP_OPCODE_MIPS;
18571 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18572 32-bit microMIPS NOPs here (if applicable). */
18575 mips_handle_align (fragS *fragp)
18579 int bytes, size, excess;
18582 if (fragp->fr_type != rs_align_code)
18585 p = fragp->fr_literal + fragp->fr_fix;
18587 switch (nop_opcode)
18589 case NOP_OPCODE_MICROMIPS:
18590 opcode = micromips_nop32_insn.insn_opcode;
18593 case NOP_OPCODE_MIPS16:
18594 opcode = mips16_nop_insn.insn_opcode;
18597 case NOP_OPCODE_MIPS:
18599 opcode = nop_insn.insn_opcode;
18604 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18605 excess = bytes % size;
18607 /* Handle the leading part if we're not inserting a whole number of
18608 instructions, and make it the end of the fixed part of the frag.
18609 Try to fit in a short microMIPS NOP if applicable and possible,
18610 and use zeroes otherwise. */
18611 gas_assert (excess < 4);
18612 fragp->fr_fix += excess;
18617 /* Fall through. */
18619 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18621 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18625 /* Fall through. */
18628 /* Fall through. */
18633 md_number_to_chars (p, opcode, size);
18634 fragp->fr_var = size;
18638 md_obj_begin (void)
18645 /* Check for premature end, nesting errors, etc. */
18647 as_warn (_("missing .end at end of assembly"));
18656 if (*input_line_pointer == '-')
18658 ++input_line_pointer;
18661 if (!ISDIGIT (*input_line_pointer))
18662 as_bad (_("expected simple number"));
18663 if (input_line_pointer[0] == '0')
18665 if (input_line_pointer[1] == 'x')
18667 input_line_pointer += 2;
18668 while (ISXDIGIT (*input_line_pointer))
18671 val |= hex_value (*input_line_pointer++);
18673 return negative ? -val : val;
18677 ++input_line_pointer;
18678 while (ISDIGIT (*input_line_pointer))
18681 val |= *input_line_pointer++ - '0';
18683 return negative ? -val : val;
18686 if (!ISDIGIT (*input_line_pointer))
18688 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18689 *input_line_pointer, *input_line_pointer);
18690 as_warn (_("invalid number"));
18693 while (ISDIGIT (*input_line_pointer))
18696 val += *input_line_pointer++ - '0';
18698 return negative ? -val : val;
18701 /* The .file directive; just like the usual .file directive, but there
18702 is an initial number which is the ECOFF file index. In the non-ECOFF
18703 case .file implies DWARF-2. */
18706 s_mips_file (int x ATTRIBUTE_UNUSED)
18708 static int first_file_directive = 0;
18710 if (ECOFF_DEBUGGING)
18719 filename = dwarf2_directive_file (0);
18721 /* Versions of GCC up to 3.1 start files with a ".file"
18722 directive even for stabs output. Make sure that this
18723 ".file" is handled. Note that you need a version of GCC
18724 after 3.1 in order to support DWARF-2 on MIPS. */
18725 if (filename != NULL && ! first_file_directive)
18727 (void) new_logical_line (filename, -1);
18728 s_app_file_string (filename, 0);
18730 first_file_directive = 1;
18734 /* The .loc directive, implying DWARF-2. */
18737 s_mips_loc (int x ATTRIBUTE_UNUSED)
18739 if (!ECOFF_DEBUGGING)
18740 dwarf2_directive_loc (0);
18743 /* The .end directive. */
18746 s_mips_end (int x ATTRIBUTE_UNUSED)
18750 /* Following functions need their own .frame and .cprestore directives. */
18751 mips_frame_reg_valid = 0;
18752 mips_cprestore_valid = 0;
18754 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18757 demand_empty_rest_of_line ();
18762 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18763 as_warn (_(".end not in text section"));
18767 as_warn (_(".end directive without a preceding .ent directive."));
18768 demand_empty_rest_of_line ();
18774 gas_assert (S_GET_NAME (p));
18775 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18776 as_warn (_(".end symbol does not match .ent symbol."));
18778 if (debug_type == DEBUG_STABS)
18779 stabs_generate_asm_endfunc (S_GET_NAME (p),
18783 as_warn (_(".end directive missing or unknown symbol"));
18786 /* Create an expression to calculate the size of the function. */
18787 if (p && cur_proc_ptr)
18789 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18790 expressionS *exp = xmalloc (sizeof (expressionS));
18793 exp->X_op = O_subtract;
18794 exp->X_add_symbol = symbol_temp_new_now ();
18795 exp->X_op_symbol = p;
18796 exp->X_add_number = 0;
18798 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18801 /* Generate a .pdr section. */
18802 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18804 segT saved_seg = now_seg;
18805 subsegT saved_subseg = now_subseg;
18809 #ifdef md_flush_pending_output
18810 md_flush_pending_output ();
18813 gas_assert (pdr_seg);
18814 subseg_set (pdr_seg, 0);
18816 /* Write the symbol. */
18817 exp.X_op = O_symbol;
18818 exp.X_add_symbol = p;
18819 exp.X_add_number = 0;
18820 emit_expr (&exp, 4);
18822 fragp = frag_more (7 * 4);
18824 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18825 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18826 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18827 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18828 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18829 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18830 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18832 subseg_set (saved_seg, saved_subseg);
18834 #endif /* OBJ_ELF */
18836 cur_proc_ptr = NULL;
18839 /* The .aent and .ent directives. */
18842 s_mips_ent (int aent)
18846 symbolP = get_symbol ();
18847 if (*input_line_pointer == ',')
18848 ++input_line_pointer;
18849 SKIP_WHITESPACE ();
18850 if (ISDIGIT (*input_line_pointer)
18851 || *input_line_pointer == '-')
18854 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18855 as_warn (_(".ent or .aent not in text section."));
18857 if (!aent && cur_proc_ptr)
18858 as_warn (_("missing .end"));
18862 /* This function needs its own .frame and .cprestore directives. */
18863 mips_frame_reg_valid = 0;
18864 mips_cprestore_valid = 0;
18866 cur_proc_ptr = &cur_proc;
18867 memset (cur_proc_ptr, '\0', sizeof (procS));
18869 cur_proc_ptr->func_sym = symbolP;
18873 if (debug_type == DEBUG_STABS)
18874 stabs_generate_asm_func (S_GET_NAME (symbolP),
18875 S_GET_NAME (symbolP));
18878 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18880 demand_empty_rest_of_line ();
18883 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18884 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18885 s_mips_frame is used so that we can set the PDR information correctly.
18886 We can't use the ecoff routines because they make reference to the ecoff
18887 symbol table (in the mdebug section). */
18890 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18893 if (IS_ELF && !ECOFF_DEBUGGING)
18897 if (cur_proc_ptr == (procS *) NULL)
18899 as_warn (_(".frame outside of .ent"));
18900 demand_empty_rest_of_line ();
18904 cur_proc_ptr->frame_reg = tc_get_register (1);
18906 SKIP_WHITESPACE ();
18907 if (*input_line_pointer++ != ','
18908 || get_absolute_expression_and_terminator (&val) != ',')
18910 as_warn (_("Bad .frame directive"));
18911 --input_line_pointer;
18912 demand_empty_rest_of_line ();
18916 cur_proc_ptr->frame_offset = val;
18917 cur_proc_ptr->pc_reg = tc_get_register (0);
18919 demand_empty_rest_of_line ();
18922 #endif /* OBJ_ELF */
18926 /* The .fmask and .mask directives. If the mdebug section is present
18927 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18928 embedded targets, s_mips_mask is used so that we can set the PDR
18929 information correctly. We can't use the ecoff routines because they
18930 make reference to the ecoff symbol table (in the mdebug section). */
18933 s_mips_mask (int reg_type)
18936 if (IS_ELF && !ECOFF_DEBUGGING)
18940 if (cur_proc_ptr == (procS *) NULL)
18942 as_warn (_(".mask/.fmask outside of .ent"));
18943 demand_empty_rest_of_line ();
18947 if (get_absolute_expression_and_terminator (&mask) != ',')
18949 as_warn (_("Bad .mask/.fmask directive"));
18950 --input_line_pointer;
18951 demand_empty_rest_of_line ();
18955 off = get_absolute_expression ();
18957 if (reg_type == 'F')
18959 cur_proc_ptr->fpreg_mask = mask;
18960 cur_proc_ptr->fpreg_offset = off;
18964 cur_proc_ptr->reg_mask = mask;
18965 cur_proc_ptr->reg_offset = off;
18968 demand_empty_rest_of_line ();
18971 #endif /* OBJ_ELF */
18972 s_ignore (reg_type);
18975 /* A table describing all the processors gas knows about. Names are
18976 matched in the order listed.
18978 To ease comparison, please keep this table in the same order as
18979 gcc's mips_cpu_info_table[]. */
18980 static const struct mips_cpu_info mips_cpu_info_table[] =
18982 /* Entries for generic ISAs */
18983 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
18984 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
18985 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
18986 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
18987 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
18988 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
18989 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
18990 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
18991 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
18994 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
18995 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
18996 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
18999 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19002 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19003 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19004 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19005 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19006 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19007 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19008 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19009 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19010 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19011 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19012 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19013 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19014 /* ST Microelectronics Loongson 2E and 2F cores */
19015 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19016 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19019 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19020 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19021 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19022 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19023 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19024 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19025 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19026 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19027 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19028 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19029 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19030 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19031 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19032 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19033 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19036 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19037 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19038 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19039 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19041 /* MIPS 32 Release 2 */
19042 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19043 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19044 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19045 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19046 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19047 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19048 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19049 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19050 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19051 ISA_MIPS32R2, CPU_MIPS32R2 },
19052 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19053 ISA_MIPS32R2, CPU_MIPS32R2 },
19054 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19055 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19056 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19057 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19058 /* Deprecated forms of the above. */
19059 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19060 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19061 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19062 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19063 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19064 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19065 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19066 /* Deprecated forms of the above. */
19067 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19068 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19069 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19070 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19071 ISA_MIPS32R2, CPU_MIPS32R2 },
19072 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19073 ISA_MIPS32R2, CPU_MIPS32R2 },
19074 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19075 ISA_MIPS32R2, CPU_MIPS32R2 },
19076 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19077 ISA_MIPS32R2, CPU_MIPS32R2 },
19078 /* Deprecated forms of the above. */
19079 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19080 ISA_MIPS32R2, CPU_MIPS32R2 },
19081 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19082 ISA_MIPS32R2, CPU_MIPS32R2 },
19083 /* 34Kn is a 34kc without DSP. */
19084 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19085 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19086 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19087 ISA_MIPS32R2, CPU_MIPS32R2 },
19088 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19089 ISA_MIPS32R2, CPU_MIPS32R2 },
19090 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19091 ISA_MIPS32R2, CPU_MIPS32R2 },
19092 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19093 ISA_MIPS32R2, CPU_MIPS32R2 },
19094 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19095 ISA_MIPS32R2, CPU_MIPS32R2 },
19096 /* Deprecated forms of the above. */
19097 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19098 ISA_MIPS32R2, CPU_MIPS32R2 },
19099 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19100 ISA_MIPS32R2, CPU_MIPS32R2 },
19101 /* 1004K cores are multiprocessor versions of the 34K. */
19102 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19103 ISA_MIPS32R2, CPU_MIPS32R2 },
19104 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19105 ISA_MIPS32R2, CPU_MIPS32R2 },
19106 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19107 ISA_MIPS32R2, CPU_MIPS32R2 },
19108 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19109 ISA_MIPS32R2, CPU_MIPS32R2 },
19112 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19113 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19114 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19115 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19117 /* Broadcom SB-1 CPU core */
19118 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19119 ISA_MIPS64, CPU_SB1 },
19120 /* Broadcom SB-1A CPU core */
19121 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19122 ISA_MIPS64, CPU_SB1 },
19124 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19126 /* MIPS 64 Release 2 */
19128 /* Cavium Networks Octeon CPU core */
19129 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19130 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19131 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19134 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19137 XLP is mostly like XLR, with the prominent exception that it is
19138 MIPS64R2 rather than MIPS64. */
19139 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19146 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19147 with a final "000" replaced by "k". Ignore case.
19149 Note: this function is shared between GCC and GAS. */
19152 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19154 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19155 given++, canonical++;
19157 return ((*given == 0 && *canonical == 0)
19158 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19162 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19163 CPU name. We've traditionally allowed a lot of variation here.
19165 Note: this function is shared between GCC and GAS. */
19168 mips_matching_cpu_name_p (const char *canonical, const char *given)
19170 /* First see if the name matches exactly, or with a final "000"
19171 turned into "k". */
19172 if (mips_strict_matching_cpu_name_p (canonical, given))
19175 /* If not, try comparing based on numerical designation alone.
19176 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19177 if (TOLOWER (*given) == 'r')
19179 if (!ISDIGIT (*given))
19182 /* Skip over some well-known prefixes in the canonical name,
19183 hoping to find a number there too. */
19184 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19186 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19188 else if (TOLOWER (canonical[0]) == 'r')
19191 return mips_strict_matching_cpu_name_p (canonical, given);
19195 /* Parse an option that takes the name of a processor as its argument.
19196 OPTION is the name of the option and CPU_STRING is the argument.
19197 Return the corresponding processor enumeration if the CPU_STRING is
19198 recognized, otherwise report an error and return null.
19200 A similar function exists in GCC. */
19202 static const struct mips_cpu_info *
19203 mips_parse_cpu (const char *option, const char *cpu_string)
19205 const struct mips_cpu_info *p;
19207 /* 'from-abi' selects the most compatible architecture for the given
19208 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19209 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19210 version. Look first at the -mgp options, if given, otherwise base
19211 the choice on MIPS_DEFAULT_64BIT.
19213 Treat NO_ABI like the EABIs. One reason to do this is that the
19214 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19215 architecture. This code picks MIPS I for 'mips' and MIPS III for
19216 'mips64', just as we did in the days before 'from-abi'. */
19217 if (strcasecmp (cpu_string, "from-abi") == 0)
19219 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19220 return mips_cpu_info_from_isa (ISA_MIPS1);
19222 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19223 return mips_cpu_info_from_isa (ISA_MIPS3);
19225 if (file_mips_gp32 >= 0)
19226 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19228 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19233 /* 'default' has traditionally been a no-op. Probably not very useful. */
19234 if (strcasecmp (cpu_string, "default") == 0)
19237 for (p = mips_cpu_info_table; p->name != 0; p++)
19238 if (mips_matching_cpu_name_p (p->name, cpu_string))
19241 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19245 /* Return the canonical processor information for ISA (a member of the
19246 ISA_MIPS* enumeration). */
19248 static const struct mips_cpu_info *
19249 mips_cpu_info_from_isa (int isa)
19253 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19254 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19255 && isa == mips_cpu_info_table[i].isa)
19256 return (&mips_cpu_info_table[i]);
19261 static const struct mips_cpu_info *
19262 mips_cpu_info_from_arch (int arch)
19266 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19267 if (arch == mips_cpu_info_table[i].cpu)
19268 return (&mips_cpu_info_table[i]);
19274 show (FILE *stream, const char *string, int *col_p, int *first_p)
19278 fprintf (stream, "%24s", "");
19283 fprintf (stream, ", ");
19287 if (*col_p + strlen (string) > 72)
19289 fprintf (stream, "\n%24s", "");
19293 fprintf (stream, "%s", string);
19294 *col_p += strlen (string);
19300 md_show_usage (FILE *stream)
19305 fprintf (stream, _("\
19307 -EB generate big endian output\n\
19308 -EL generate little endian output\n\
19309 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19310 -G NUM allow referencing objects up to NUM bytes\n\
19311 implicitly with the gp register [default 8]\n"));
19312 fprintf (stream, _("\
19313 -mips1 generate MIPS ISA I instructions\n\
19314 -mips2 generate MIPS ISA II instructions\n\
19315 -mips3 generate MIPS ISA III instructions\n\
19316 -mips4 generate MIPS ISA IV instructions\n\
19317 -mips5 generate MIPS ISA V instructions\n\
19318 -mips32 generate MIPS32 ISA instructions\n\
19319 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19320 -mips64 generate MIPS64 ISA instructions\n\
19321 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19322 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19326 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19327 show (stream, mips_cpu_info_table[i].name, &column, &first);
19328 show (stream, "from-abi", &column, &first);
19329 fputc ('\n', stream);
19331 fprintf (stream, _("\
19332 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19333 -no-mCPU don't generate code specific to CPU.\n\
19334 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19338 show (stream, "3900", &column, &first);
19339 show (stream, "4010", &column, &first);
19340 show (stream, "4100", &column, &first);
19341 show (stream, "4650", &column, &first);
19342 fputc ('\n', stream);
19344 fprintf (stream, _("\
19345 -mips16 generate mips16 instructions\n\
19346 -no-mips16 do not generate mips16 instructions\n"));
19347 fprintf (stream, _("\
19348 -mmicromips generate microMIPS instructions\n\
19349 -mno-micromips do not generate microMIPS instructions\n"));
19350 fprintf (stream, _("\
19351 -msmartmips generate smartmips instructions\n\
19352 -mno-smartmips do not generate smartmips instructions\n"));
19353 fprintf (stream, _("\
19354 -mdsp generate DSP instructions\n\
19355 -mno-dsp do not generate DSP instructions\n"));
19356 fprintf (stream, _("\
19357 -mdspr2 generate DSP R2 instructions\n\
19358 -mno-dspr2 do not generate DSP R2 instructions\n"));
19359 fprintf (stream, _("\
19360 -mmt generate MT instructions\n\
19361 -mno-mt do not generate MT instructions\n"));
19362 fprintf (stream, _("\
19363 -mmcu generate MCU instructions\n\
19364 -mno-mcu do not generate MCU instructions\n"));
19365 fprintf (stream, _("\
19366 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19367 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19368 -mfix-vr4120 work around certain VR4120 errata\n\
19369 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19370 -mfix-24k insert a nop after ERET and DERET instructions\n\
19371 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19372 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19373 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19374 -msym32 assume all symbols have 32-bit values\n\
19375 -O0 remove unneeded NOPs, do not swap branches\n\
19376 -O remove unneeded NOPs and swap branches\n\
19377 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19378 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19379 fprintf (stream, _("\
19380 -mhard-float allow floating-point instructions\n\
19381 -msoft-float do not allow floating-point instructions\n\
19382 -msingle-float only allow 32-bit floating-point operations\n\
19383 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19384 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19387 fprintf (stream, _("\
19388 -KPIC, -call_shared generate SVR4 position independent code\n\
19389 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19390 -mvxworks-pic generate VxWorks position independent code\n\
19391 -non_shared do not generate code that can operate with DSOs\n\
19392 -xgot assume a 32 bit GOT\n\
19393 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19394 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19395 position dependent (non shared) code\n\
19396 -mabi=ABI create ABI conformant object file for:\n"));
19400 show (stream, "32", &column, &first);
19401 show (stream, "o64", &column, &first);
19402 show (stream, "n32", &column, &first);
19403 show (stream, "64", &column, &first);
19404 show (stream, "eabi", &column, &first);
19406 fputc ('\n', stream);
19408 fprintf (stream, _("\
19409 -32 create o32 ABI object file (default)\n\
19410 -n32 create n32 ABI object file\n\
19411 -64 create 64 ABI object file\n"));
19417 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19419 if (HAVE_64BIT_SYMBOLS)
19420 return dwarf2_format_64bit_irix;
19422 return dwarf2_format_32bit;
19427 mips_dwarf2_addr_size (void)
19429 if (HAVE_64BIT_OBJECTS)
19435 /* Standard calling conventions leave the CFA at SP on entry. */
19437 mips_cfi_frame_initial_instructions (void)
19439 cfi_add_CFA_def_cfa_register (SP);
19443 tc_mips_regname_to_dw2regnum (char *regname)
19445 unsigned int regnum = -1;
19448 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))