1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p : 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p : 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi = NO_ABI;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls = FALSE;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared = TRUE;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32 = -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32 = -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float = 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float = 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008 = FALSE;
281 static struct mips_set_options mips_opts =
283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
287 /* soft_float */ FALSE, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch = CPU_UNKNOWN;
331 static const char *mips_arch_string;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune = CPU_UNKNOWN;
336 static const char *mips_tune_string;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode = 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got = 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap = 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value = 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen = 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS *, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control *op_hash = NULL;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control *mips16_op_hash = NULL;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control *micromips_op_hash = NULL;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error;
635 static int auto_align = 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset = -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset = -1;
647 static int mips_cpreturn_register = -1;
648 static int mips_gp_register = GP;
649 static int mips_gprel_offset = 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid = 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg = SP;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid = 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize = 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug = 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history[1 + MAX_NOPS];
692 /* Arrays of operands for each instruction. */
693 #define MAX_OPERANDS 5
694 struct mips_operand_array {
695 const struct mips_operand *operand[MAX_OPERANDS];
697 static struct mips_operand_array *mips_operands;
698 static struct mips_operand_array *mips16_operands;
699 static struct mips_operand_array *micromips_operands;
701 /* Nop instructions used by emit_nop. */
702 static struct mips_cl_insn nop_insn;
703 static struct mips_cl_insn mips16_nop_insn;
704 static struct mips_cl_insn micromips_nop16_insn;
705 static struct mips_cl_insn micromips_nop32_insn;
707 /* The appropriate nop for the current mode. */
708 #define NOP_INSN (mips_opts.mips16 \
710 : (mips_opts.micromips \
711 ? (mips_opts.insn32 \
712 ? µmips_nop32_insn \
713 : µmips_nop16_insn) \
716 /* The size of NOP_INSN in bytes. */
717 #define NOP_INSN_SIZE ((mips_opts.mips16 \
718 || (mips_opts.micromips && !mips_opts.insn32)) \
721 /* If this is set, it points to a frag holding nop instructions which
722 were inserted before the start of a noreorder section. If those
723 nops turn out to be unnecessary, the size of the frag can be
725 static fragS *prev_nop_frag;
727 /* The number of nop instructions we created in prev_nop_frag. */
728 static int prev_nop_frag_holds;
730 /* The number of nop instructions that we know we need in
732 static int prev_nop_frag_required;
734 /* The number of instructions we've seen since prev_nop_frag. */
735 static int prev_nop_frag_since;
737 /* Relocations against symbols are sometimes done in two parts, with a HI
738 relocation and a LO relocation. Each relocation has only 16 bits of
739 space to store an addend. This means that in order for the linker to
740 handle carries correctly, it must be able to locate both the HI and
741 the LO relocation. This means that the relocations must appear in
742 order in the relocation table.
744 In order to implement this, we keep track of each unmatched HI
745 relocation. We then sort them so that they immediately precede the
746 corresponding LO relocation. */
751 struct mips_hi_fixup *next;
754 /* The section this fixup is in. */
758 /* The list of unmatched HI relocs. */
760 static struct mips_hi_fixup *mips_hi_fixup_list;
762 /* The frag containing the last explicit relocation operator.
763 Null if explicit relocations have not been used. */
765 static fragS *prev_reloc_op_frag;
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map microMIPS register numbers to normal MIPS register numbers. */
776 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
778 /* The microMIPS registers with type h. */
779 static const unsigned int micromips_to_32_reg_h_map1[] =
781 5, 5, 6, 4, 4, 4, 4, 4
783 static const unsigned int micromips_to_32_reg_h_map2[] =
785 6, 7, 7, 21, 22, 5, 6, 7
788 /* The microMIPS registers with type m. */
789 static const unsigned int micromips_to_32_reg_m_map[] =
791 0, 17, 2, 3, 16, 18, 19, 20
794 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
796 /* Classifies the kind of instructions we're interested in when
797 implementing -mfix-vr4120. */
798 enum fix_vr4120_class
806 NUM_FIX_VR4120_CLASSES
809 /* ...likewise -mfix-loongson2f-jump. */
810 static bfd_boolean mips_fix_loongson2f_jump;
812 /* ...likewise -mfix-loongson2f-nop. */
813 static bfd_boolean mips_fix_loongson2f_nop;
815 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
816 static bfd_boolean mips_fix_loongson2f;
818 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
819 there must be at least one other instruction between an instruction
820 of type X and an instruction of type Y. */
821 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
823 /* True if -mfix-vr4120 is in force. */
824 static int mips_fix_vr4120;
826 /* ...likewise -mfix-vr4130. */
827 static int mips_fix_vr4130;
829 /* ...likewise -mfix-24k. */
830 static int mips_fix_24k;
832 /* ...likewise -mfix-cn63xxp1 */
833 static bfd_boolean mips_fix_cn63xxp1;
835 /* We don't relax branches by default, since this causes us to expand
836 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
837 fail to compute the offset before expanding the macro to the most
838 efficient expansion. */
840 static int mips_relax_branch;
842 /* The expansion of many macros depends on the type of symbol that
843 they refer to. For example, when generating position-dependent code,
844 a macro that refers to a symbol may have two different expansions,
845 one which uses GP-relative addresses and one which uses absolute
846 addresses. When generating SVR4-style PIC, a macro may have
847 different expansions for local and global symbols.
849 We handle these situations by generating both sequences and putting
850 them in variant frags. In position-dependent code, the first sequence
851 will be the GP-relative one and the second sequence will be the
852 absolute one. In SVR4 PIC, the first sequence will be for global
853 symbols and the second will be for local symbols.
855 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
856 SECOND are the lengths of the two sequences in bytes. These fields
857 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
858 the subtype has the following flags:
861 Set if it has been decided that we should use the second
862 sequence instead of the first.
865 Set in the first variant frag if the macro's second implementation
866 is longer than its first. This refers to the macro as a whole,
867 not an individual relaxation.
870 Set in the first variant frag if the macro appeared in a .set nomacro
871 block and if one alternative requires a warning but the other does not.
874 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
877 RELAX_DELAY_SLOT_16BIT
878 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
881 RELAX_DELAY_SLOT_SIZE_FIRST
882 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
883 the macro is of the wrong size for the branch delay slot.
885 RELAX_DELAY_SLOT_SIZE_SECOND
886 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
887 the macro is of the wrong size for the branch delay slot.
889 The frag's "opcode" points to the first fixup for relaxable code.
891 Relaxable macros are generated using a sequence such as:
893 relax_start (SYMBOL);
894 ... generate first expansion ...
896 ... generate second expansion ...
899 The code and fixups for the unwanted alternative are discarded
900 by md_convert_frag. */
901 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
903 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
904 #define RELAX_SECOND(X) ((X) & 0xff)
905 #define RELAX_USE_SECOND 0x10000
906 #define RELAX_SECOND_LONGER 0x20000
907 #define RELAX_NOMACRO 0x40000
908 #define RELAX_DELAY_SLOT 0x80000
909 #define RELAX_DELAY_SLOT_16BIT 0x100000
910 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
911 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
913 /* Branch without likely bit. If label is out of range, we turn:
915 beq reg1, reg2, label
925 with the following opcode replacements:
932 bltzal <-> bgezal (with jal label instead of j label)
934 Even though keeping the delay slot instruction in the delay slot of
935 the branch would be more efficient, it would be very tricky to do
936 correctly, because we'd have to introduce a variable frag *after*
937 the delay slot instruction, and expand that instead. Let's do it
938 the easy way for now, even if the branch-not-taken case now costs
939 one additional instruction. Out-of-range branches are not supposed
940 to be common, anyway.
942 Branch likely. If label is out of range, we turn:
944 beql reg1, reg2, label
945 delay slot (annulled if branch not taken)
954 delay slot (executed only if branch taken)
957 It would be possible to generate a shorter sequence by losing the
958 likely bit, generating something like:
963 delay slot (executed only if branch taken)
975 bltzall -> bgezal (with jal label instead of j label)
976 bgezall -> bltzal (ditto)
979 but it's not clear that it would actually improve performance. */
980 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
984 | ((toofar) ? 0x20 : 0) \
985 | ((link) ? 0x40 : 0) \
986 | ((likely) ? 0x80 : 0) \
987 | ((uncond) ? 0x100 : 0)))
988 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
989 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
990 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
991 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
992 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
993 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
995 /* For mips16 code, we use an entirely different form of relaxation.
996 mips16 supports two versions of most instructions which take
997 immediate values: a small one which takes some small value, and a
998 larger one which takes a 16 bit value. Since branches also follow
999 this pattern, relaxing these values is required.
1001 We can assemble both mips16 and normal MIPS code in a single
1002 object. Therefore, we need to support this type of relaxation at
1003 the same time that we support the relaxation described above. We
1004 use the high bit of the subtype field to distinguish these cases.
1006 The information we store for this type of relaxation is the
1007 argument code found in the opcode file for this relocation, whether
1008 the user explicitly requested a small or extended form, and whether
1009 the relocation is in a jump or jal delay slot. That tells us the
1010 size of the value, and how it should be stored. We also store
1011 whether the fragment is considered to be extended or not. We also
1012 store whether this is known to be a branch to a different section,
1013 whether we have tried to relax this frag yet, and whether we have
1014 ever extended a PC relative fragment because of a shift count. */
1015 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1018 | ((small) ? 0x100 : 0) \
1019 | ((ext) ? 0x200 : 0) \
1020 | ((dslot) ? 0x400 : 0) \
1021 | ((jal_dslot) ? 0x800 : 0))
1022 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1023 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1024 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1025 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1026 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1027 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1028 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1029 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1030 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1031 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1032 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1033 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1035 /* For microMIPS code, we use relaxation similar to one we use for
1036 MIPS16 code. Some instructions that take immediate values support
1037 two encodings: a small one which takes some small value, and a
1038 larger one which takes a 16 bit value. As some branches also follow
1039 this pattern, relaxing these values is required.
1041 We can assemble both microMIPS and normal MIPS code in a single
1042 object. Therefore, we need to support this type of relaxation at
1043 the same time that we support the relaxation described above. We
1044 use one of the high bits of the subtype field to distinguish these
1047 The information we store for this type of relaxation is the argument
1048 code found in the opcode file for this relocation, the register
1049 selected as the assembler temporary, whether the branch is
1050 unconditional, whether it is compact, whether it stores the link
1051 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1052 branches to a sequence of instructions is enabled, and whether the
1053 displacement of a branch is too large to fit as an immediate argument
1054 of a 16-bit and a 32-bit branch, respectively. */
1055 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1056 relax32, toofar16, toofar32) \
1059 | (((at) & 0x1f) << 8) \
1060 | ((uncond) ? 0x2000 : 0) \
1061 | ((compact) ? 0x4000 : 0) \
1062 | ((link) ? 0x8000 : 0) \
1063 | ((relax32) ? 0x10000 : 0) \
1064 | ((toofar16) ? 0x20000 : 0) \
1065 | ((toofar32) ? 0x40000 : 0))
1066 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1067 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1068 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1069 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1070 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1071 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1072 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1074 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1075 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1076 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1077 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1078 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1079 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1081 /* Sign-extend 16-bit value X. */
1082 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1084 /* Is the given value a sign-extended 32-bit value? */
1085 #define IS_SEXT_32BIT_NUM(x) \
1086 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1087 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1089 /* Is the given value a sign-extended 16-bit value? */
1090 #define IS_SEXT_16BIT_NUM(x) \
1091 (((x) &~ (offsetT) 0x7fff) == 0 \
1092 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1094 /* Is the given value a sign-extended 12-bit value? */
1095 #define IS_SEXT_12BIT_NUM(x) \
1096 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1098 /* Is the given value a sign-extended 9-bit value? */
1099 #define IS_SEXT_9BIT_NUM(x) \
1100 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1102 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1103 #define IS_ZEXT_32BIT_NUM(x) \
1104 (((x) &~ (offsetT) 0xffffffff) == 0 \
1105 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1107 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1109 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1110 (((STRUCT) >> (SHIFT)) & (MASK))
1112 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1113 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1115 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1116 : EXTRACT_BITS ((INSN).insn_opcode, \
1117 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1118 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1119 EXTRACT_BITS ((INSN).insn_opcode, \
1120 MIPS16OP_MASK_##FIELD, \
1121 MIPS16OP_SH_##FIELD)
1123 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1124 #define MIPS16_EXTEND (0xf000U << 16)
1126 /* Whether or not we are emitting a branch-likely macro. */
1127 static bfd_boolean emit_branch_likely_macro = FALSE;
1129 /* Global variables used when generating relaxable macros. See the
1130 comment above RELAX_ENCODE for more details about how relaxation
1133 /* 0 if we're not emitting a relaxable macro.
1134 1 if we're emitting the first of the two relaxation alternatives.
1135 2 if we're emitting the second alternative. */
1138 /* The first relaxable fixup in the current frag. (In other words,
1139 the first fixup that refers to relaxable code.) */
1142 /* sizes[0] says how many bytes of the first alternative are stored in
1143 the current frag. Likewise sizes[1] for the second alternative. */
1144 unsigned int sizes[2];
1146 /* The symbol on which the choice of sequence depends. */
1150 /* Global variables used to decide whether a macro needs a warning. */
1152 /* True if the macro is in a branch delay slot. */
1153 bfd_boolean delay_slot_p;
1155 /* Set to the length in bytes required if the macro is in a delay slot
1156 that requires a specific length of instruction, otherwise zero. */
1157 unsigned int delay_slot_length;
1159 /* For relaxable macros, sizes[0] is the length of the first alternative
1160 in bytes and sizes[1] is the length of the second alternative.
1161 For non-relaxable macros, both elements give the length of the
1163 unsigned int sizes[2];
1165 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1166 instruction of the first alternative in bytes and first_insn_sizes[1]
1167 is the length of the first instruction of the second alternative.
1168 For non-relaxable macros, both elements give the length of the first
1169 instruction in bytes.
1171 Set to zero if we haven't yet seen the first instruction. */
1172 unsigned int first_insn_sizes[2];
1174 /* For relaxable macros, insns[0] is the number of instructions for the
1175 first alternative and insns[1] is the number of instructions for the
1178 For non-relaxable macros, both elements give the number of
1179 instructions for the macro. */
1180 unsigned int insns[2];
1182 /* The first variant frag for this macro. */
1184 } mips_macro_warning;
1186 /* Prototypes for static functions. */
1188 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1190 static void append_insn
1191 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1192 bfd_boolean expansionp);
1193 static void mips_no_prev_insn (void);
1194 static void macro_build (expressionS *, const char *, const char *, ...);
1195 static void mips16_macro_build
1196 (expressionS *, const char *, const char *, va_list *);
1197 static void load_register (int, expressionS *, int);
1198 static void macro_start (void);
1199 static void macro_end (void);
1200 static void macro (struct mips_cl_insn *ip, char *str);
1201 static void mips16_macro (struct mips_cl_insn * ip);
1202 static void mips_ip (char *str, struct mips_cl_insn * ip);
1203 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1204 static void mips16_immed
1205 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1206 unsigned int, unsigned long *);
1207 static size_t my_getSmallExpression
1208 (expressionS *, bfd_reloc_code_real_type *, char *);
1209 static void my_getExpression (expressionS *, char *);
1210 static void s_align (int);
1211 static void s_change_sec (int);
1212 static void s_change_section (int);
1213 static void s_cons (int);
1214 static void s_float_cons (int);
1215 static void s_mips_globl (int);
1216 static void s_option (int);
1217 static void s_mipsset (int);
1218 static void s_abicalls (int);
1219 static void s_cpload (int);
1220 static void s_cpsetup (int);
1221 static void s_cplocal (int);
1222 static void s_cprestore (int);
1223 static void s_cpreturn (int);
1224 static void s_dtprelword (int);
1225 static void s_dtpreldword (int);
1226 static void s_tprelword (int);
1227 static void s_tpreldword (int);
1228 static void s_gpvalue (int);
1229 static void s_gpword (int);
1230 static void s_gpdword (int);
1231 static void s_ehword (int);
1232 static void s_cpadd (int);
1233 static void s_insn (int);
1234 static void s_nan (int);
1235 static void md_obj_begin (void);
1236 static void md_obj_end (void);
1237 static void s_mips_ent (int);
1238 static void s_mips_end (int);
1239 static void s_mips_frame (int);
1240 static void s_mips_mask (int reg_type);
1241 static void s_mips_stab (int);
1242 static void s_mips_weakext (int);
1243 static void s_mips_file (int);
1244 static void s_mips_loc (int);
1245 static bfd_boolean pic_need_relax (symbolS *, asection *);
1246 static int relaxed_branch_length (fragS *, asection *, int);
1247 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1248 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1250 /* Table and functions used to map between CPU/ISA names, and
1251 ISA levels, and CPU numbers. */
1253 struct mips_cpu_info
1255 const char *name; /* CPU or ISA name. */
1256 int flags; /* MIPS_CPU_* flags. */
1257 int ase; /* Set of ASEs implemented by the CPU. */
1258 int isa; /* ISA level. */
1259 int cpu; /* CPU number (default CPU if ISA). */
1262 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1264 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1265 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1266 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1268 /* Command-line options. */
1269 const char *md_shortopts = "O::g::G:";
1273 OPTION_MARCH = OPTION_MD_BASE,
1297 OPTION_NO_SMARTMIPS,
1303 OPTION_NO_MICROMIPS,
1306 OPTION_COMPAT_ARCH_BASE,
1315 OPTION_M7000_HILO_FIX,
1316 OPTION_MNO_7000_HILO_FIX,
1319 OPTION_FIX_LOONGSON2F_JUMP,
1320 OPTION_NO_FIX_LOONGSON2F_JUMP,
1321 OPTION_FIX_LOONGSON2F_NOP,
1322 OPTION_NO_FIX_LOONGSON2F_NOP,
1324 OPTION_NO_FIX_VR4120,
1326 OPTION_NO_FIX_VR4130,
1327 OPTION_FIX_CN63XXP1,
1328 OPTION_NO_FIX_CN63XXP1,
1335 OPTION_CONSTRUCT_FLOATS,
1336 OPTION_NO_CONSTRUCT_FLOATS,
1339 OPTION_RELAX_BRANCH,
1340 OPTION_NO_RELAX_BRANCH,
1349 OPTION_SINGLE_FLOAT,
1350 OPTION_DOUBLE_FLOAT,
1363 OPTION_MVXWORKS_PIC,
1368 struct option md_longopts[] =
1370 /* Options which specify architecture. */
1371 {"march", required_argument, NULL, OPTION_MARCH},
1372 {"mtune", required_argument, NULL, OPTION_MTUNE},
1373 {"mips0", no_argument, NULL, OPTION_MIPS1},
1374 {"mips1", no_argument, NULL, OPTION_MIPS1},
1375 {"mips2", no_argument, NULL, OPTION_MIPS2},
1376 {"mips3", no_argument, NULL, OPTION_MIPS3},
1377 {"mips4", no_argument, NULL, OPTION_MIPS4},
1378 {"mips5", no_argument, NULL, OPTION_MIPS5},
1379 {"mips32", no_argument, NULL, OPTION_MIPS32},
1380 {"mips64", no_argument, NULL, OPTION_MIPS64},
1381 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1382 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1384 /* Options which specify Application Specific Extensions (ASEs). */
1385 {"mips16", no_argument, NULL, OPTION_MIPS16},
1386 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1387 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1388 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1389 {"mdmx", no_argument, NULL, OPTION_MDMX},
1390 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1391 {"mdsp", no_argument, NULL, OPTION_DSP},
1392 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1393 {"mmt", no_argument, NULL, OPTION_MT},
1394 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1395 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1396 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1397 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1398 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1399 {"meva", no_argument, NULL, OPTION_EVA},
1400 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1401 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1402 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1403 {"mmcu", no_argument, NULL, OPTION_MCU},
1404 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1405 {"mvirt", no_argument, NULL, OPTION_VIRT},
1406 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1408 /* Old-style architecture options. Don't add more of these. */
1409 {"m4650", no_argument, NULL, OPTION_M4650},
1410 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1411 {"m4010", no_argument, NULL, OPTION_M4010},
1412 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1413 {"m4100", no_argument, NULL, OPTION_M4100},
1414 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1415 {"m3900", no_argument, NULL, OPTION_M3900},
1416 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1418 /* Options which enable bug fixes. */
1419 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1420 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1421 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1422 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1423 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1424 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1425 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1426 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1427 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1428 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1429 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1430 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1431 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1432 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1433 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1435 /* Miscellaneous options. */
1436 {"trap", no_argument, NULL, OPTION_TRAP},
1437 {"no-break", no_argument, NULL, OPTION_TRAP},
1438 {"break", no_argument, NULL, OPTION_BREAK},
1439 {"no-trap", no_argument, NULL, OPTION_BREAK},
1440 {"EB", no_argument, NULL, OPTION_EB},
1441 {"EL", no_argument, NULL, OPTION_EL},
1442 {"mfp32", no_argument, NULL, OPTION_FP32},
1443 {"mgp32", no_argument, NULL, OPTION_GP32},
1444 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1445 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1446 {"mfp64", no_argument, NULL, OPTION_FP64},
1447 {"mgp64", no_argument, NULL, OPTION_GP64},
1448 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1449 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1450 {"minsn32", no_argument, NULL, OPTION_INSN32},
1451 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1452 {"mshared", no_argument, NULL, OPTION_MSHARED},
1453 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1454 {"msym32", no_argument, NULL, OPTION_MSYM32},
1455 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1456 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1457 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1458 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1459 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1461 /* Strictly speaking this next option is ELF specific,
1462 but we allow it for other ports as well in order to
1463 make testing easier. */
1464 {"32", no_argument, NULL, OPTION_32},
1466 /* ELF-specific options. */
1467 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1468 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1469 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1470 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1471 {"xgot", no_argument, NULL, OPTION_XGOT},
1472 {"mabi", required_argument, NULL, OPTION_MABI},
1473 {"n32", no_argument, NULL, OPTION_N32},
1474 {"64", no_argument, NULL, OPTION_64},
1475 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1476 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1477 {"mpdr", no_argument, NULL, OPTION_PDR},
1478 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1479 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1480 {"mnan", required_argument, NULL, OPTION_NAN},
1482 {NULL, no_argument, NULL, 0}
1484 size_t md_longopts_size = sizeof (md_longopts);
1486 /* Information about either an Application Specific Extension or an
1487 optional architecture feature that, for simplicity, we treat in the
1488 same way as an ASE. */
1491 /* The name of the ASE, used in both the command-line and .set options. */
1494 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1495 and 64-bit architectures, the flags here refer to the subset that
1496 is available on both. */
1499 /* The ASE_* flag used for instructions that are available on 64-bit
1500 architectures but that are not included in FLAGS. */
1501 unsigned int flags64;
1503 /* The command-line options that turn the ASE on and off. */
1507 /* The minimum required architecture revisions for MIPS32, MIPS64,
1508 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1511 int micromips32_rev;
1512 int micromips64_rev;
1515 /* A table of all supported ASEs. */
1516 static const struct mips_ase mips_ases[] = {
1517 { "dsp", ASE_DSP, ASE_DSP64,
1518 OPTION_DSP, OPTION_NO_DSP,
1521 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1522 OPTION_DSPR2, OPTION_NO_DSPR2,
1525 { "eva", ASE_EVA, 0,
1526 OPTION_EVA, OPTION_NO_EVA,
1529 { "mcu", ASE_MCU, 0,
1530 OPTION_MCU, OPTION_NO_MCU,
1533 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1534 { "mdmx", ASE_MDMX, 0,
1535 OPTION_MDMX, OPTION_NO_MDMX,
1538 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1539 { "mips3d", ASE_MIPS3D, 0,
1540 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1544 OPTION_MT, OPTION_NO_MT,
1547 { "smartmips", ASE_SMARTMIPS, 0,
1548 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1551 { "virt", ASE_VIRT, ASE_VIRT64,
1552 OPTION_VIRT, OPTION_NO_VIRT,
1556 /* The set of ASEs that require -mfp64. */
1557 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1559 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1560 static const unsigned int mips_ase_groups[] = {
1566 The following pseudo-ops from the Kane and Heinrich MIPS book
1567 should be defined here, but are currently unsupported: .alias,
1568 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1570 The following pseudo-ops from the Kane and Heinrich MIPS book are
1571 specific to the type of debugging information being generated, and
1572 should be defined by the object format: .aent, .begin, .bend,
1573 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1576 The following pseudo-ops from the Kane and Heinrich MIPS book are
1577 not MIPS CPU specific, but are also not specific to the object file
1578 format. This file is probably the best place to define them, but
1579 they are not currently supported: .asm0, .endr, .lab, .struct. */
1581 static const pseudo_typeS mips_pseudo_table[] =
1583 /* MIPS specific pseudo-ops. */
1584 {"option", s_option, 0},
1585 {"set", s_mipsset, 0},
1586 {"rdata", s_change_sec, 'r'},
1587 {"sdata", s_change_sec, 's'},
1588 {"livereg", s_ignore, 0},
1589 {"abicalls", s_abicalls, 0},
1590 {"cpload", s_cpload, 0},
1591 {"cpsetup", s_cpsetup, 0},
1592 {"cplocal", s_cplocal, 0},
1593 {"cprestore", s_cprestore, 0},
1594 {"cpreturn", s_cpreturn, 0},
1595 {"dtprelword", s_dtprelword, 0},
1596 {"dtpreldword", s_dtpreldword, 0},
1597 {"tprelword", s_tprelword, 0},
1598 {"tpreldword", s_tpreldword, 0},
1599 {"gpvalue", s_gpvalue, 0},
1600 {"gpword", s_gpword, 0},
1601 {"gpdword", s_gpdword, 0},
1602 {"ehword", s_ehword, 0},
1603 {"cpadd", s_cpadd, 0},
1604 {"insn", s_insn, 0},
1607 /* Relatively generic pseudo-ops that happen to be used on MIPS
1609 {"asciiz", stringer, 8 + 1},
1610 {"bss", s_change_sec, 'b'},
1612 {"half", s_cons, 1},
1613 {"dword", s_cons, 3},
1614 {"weakext", s_mips_weakext, 0},
1615 {"origin", s_org, 0},
1616 {"repeat", s_rept, 0},
1618 /* For MIPS this is non-standard, but we define it for consistency. */
1619 {"sbss", s_change_sec, 'B'},
1621 /* These pseudo-ops are defined in read.c, but must be overridden
1622 here for one reason or another. */
1623 {"align", s_align, 0},
1624 {"byte", s_cons, 0},
1625 {"data", s_change_sec, 'd'},
1626 {"double", s_float_cons, 'd'},
1627 {"float", s_float_cons, 'f'},
1628 {"globl", s_mips_globl, 0},
1629 {"global", s_mips_globl, 0},
1630 {"hword", s_cons, 1},
1632 {"long", s_cons, 2},
1633 {"octa", s_cons, 4},
1634 {"quad", s_cons, 3},
1635 {"section", s_change_section, 0},
1636 {"short", s_cons, 1},
1637 {"single", s_float_cons, 'f'},
1638 {"stabd", s_mips_stab, 'd'},
1639 {"stabn", s_mips_stab, 'n'},
1640 {"stabs", s_mips_stab, 's'},
1641 {"text", s_change_sec, 't'},
1642 {"word", s_cons, 2},
1644 { "extern", ecoff_directive_extern, 0},
1649 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1651 /* These pseudo-ops should be defined by the object file format.
1652 However, a.out doesn't support them, so we have versions here. */
1653 {"aent", s_mips_ent, 1},
1654 {"bgnb", s_ignore, 0},
1655 {"end", s_mips_end, 0},
1656 {"endb", s_ignore, 0},
1657 {"ent", s_mips_ent, 0},
1658 {"file", s_mips_file, 0},
1659 {"fmask", s_mips_mask, 'F'},
1660 {"frame", s_mips_frame, 0},
1661 {"loc", s_mips_loc, 0},
1662 {"mask", s_mips_mask, 'R'},
1663 {"verstamp", s_ignore, 0},
1667 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1668 purpose of the `.dc.a' internal pseudo-op. */
1671 mips_address_bytes (void)
1673 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1676 extern void pop_insert (const pseudo_typeS *);
1679 mips_pop_insert (void)
1681 pop_insert (mips_pseudo_table);
1682 if (! ECOFF_DEBUGGING)
1683 pop_insert (mips_nonecoff_pseudo_table);
1686 /* Symbols labelling the current insn. */
1688 struct insn_label_list
1690 struct insn_label_list *next;
1694 static struct insn_label_list *free_insn_labels;
1695 #define label_list tc_segment_info_data.labels
1697 static void mips_clear_insn_labels (void);
1698 static void mips_mark_labels (void);
1699 static void mips_compressed_mark_labels (void);
1702 mips_clear_insn_labels (void)
1704 register struct insn_label_list **pl;
1705 segment_info_type *si;
1709 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1712 si = seg_info (now_seg);
1713 *pl = si->label_list;
1714 si->label_list = NULL;
1718 /* Mark instruction labels in MIPS16/microMIPS mode. */
1721 mips_mark_labels (void)
1723 if (HAVE_CODE_COMPRESSION)
1724 mips_compressed_mark_labels ();
1727 static char *expr_end;
1729 /* Expressions which appear in macro instructions. These are set by
1730 mips_ip and read by macro. */
1732 static expressionS imm_expr;
1733 static expressionS imm2_expr;
1735 /* The relocatable field in an instruction and the relocs associated
1736 with it. These variables are used for instructions like LUI and
1737 JAL as well as true offsets. They are also used for address
1738 operands in macros. */
1740 static expressionS offset_expr;
1741 static bfd_reloc_code_real_type offset_reloc[3]
1742 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1744 /* This is set to the resulting size of the instruction to be produced
1745 by mips16_ip if an explicit extension is used or by mips_ip if an
1746 explicit size is supplied. */
1748 static unsigned int forced_insn_length;
1750 /* True if we are assembling an instruction. All dot symbols defined during
1751 this time should be treated as code labels. */
1753 static bfd_boolean mips_assembling_insn;
1755 /* The pdr segment for per procedure frame/regmask info. Not used for
1758 static segT pdr_seg;
1760 /* The default target format to use. */
1762 #if defined (TE_FreeBSD)
1763 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1764 #elif defined (TE_TMIPS)
1765 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1771 mips_target_format (void)
1773 switch (OUTPUT_FLAVOR)
1775 case bfd_target_elf_flavour:
1777 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1778 return (target_big_endian
1779 ? "elf32-bigmips-vxworks"
1780 : "elf32-littlemips-vxworks");
1782 return (target_big_endian
1783 ? (HAVE_64BIT_OBJECTS
1784 ? ELF_TARGET ("elf64-", "big")
1786 ? ELF_TARGET ("elf32-n", "big")
1787 : ELF_TARGET ("elf32-", "big")))
1788 : (HAVE_64BIT_OBJECTS
1789 ? ELF_TARGET ("elf64-", "little")
1791 ? ELF_TARGET ("elf32-n", "little")
1792 : ELF_TARGET ("elf32-", "little"))));
1799 /* Return the ISA revision that is currently in use, or 0 if we are
1800 generating code for MIPS V or below. */
1805 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1808 /* microMIPS implies revision 2 or above. */
1809 if (mips_opts.micromips)
1812 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1818 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1821 mips_ase_mask (unsigned int flags)
1825 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1826 if (flags & mips_ase_groups[i])
1827 flags |= mips_ase_groups[i];
1831 /* Check whether the current ISA supports ASE. Issue a warning if
1835 mips_check_isa_supports_ase (const struct mips_ase *ase)
1839 static unsigned int warned_isa;
1840 static unsigned int warned_fp32;
1842 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1843 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1845 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1846 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1847 && (warned_isa & ase->flags) != ase->flags)
1849 warned_isa |= ase->flags;
1850 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1851 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1853 as_warn (_("The %d-bit %s architecture does not support the"
1854 " `%s' extension"), size, base, ase->name);
1856 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1857 ase->name, base, size, min_rev);
1859 if ((ase->flags & FP64_ASES)
1861 && (warned_fp32 & ase->flags) != ase->flags)
1863 warned_fp32 |= ase->flags;
1864 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1868 /* Check all enabled ASEs to see whether they are supported by the
1869 chosen architecture. */
1872 mips_check_isa_supports_ases (void)
1874 unsigned int i, mask;
1876 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1878 mask = mips_ase_mask (mips_ases[i].flags);
1879 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1880 mips_check_isa_supports_ase (&mips_ases[i]);
1884 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1885 that were affected. */
1888 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1892 mask = mips_ase_mask (ase->flags);
1893 mips_opts.ase &= ~mask;
1895 mips_opts.ase |= ase->flags;
1899 /* Return the ASE called NAME, or null if none. */
1901 static const struct mips_ase *
1902 mips_lookup_ase (const char *name)
1906 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1907 if (strcmp (name, mips_ases[i].name) == 0)
1908 return &mips_ases[i];
1912 /* Return the length of a microMIPS instruction in bytes. If bits of
1913 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1914 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1915 major opcode) will require further modifications to the opcode
1918 static inline unsigned int
1919 micromips_insn_length (const struct mips_opcode *mo)
1921 return (mo->mask >> 16) == 0 ? 2 : 4;
1924 /* Return the length of MIPS16 instruction OPCODE. */
1926 static inline unsigned int
1927 mips16_opcode_length (unsigned long opcode)
1929 return (opcode >> 16) == 0 ? 2 : 4;
1932 /* Return the length of instruction INSN. */
1934 static inline unsigned int
1935 insn_length (const struct mips_cl_insn *insn)
1937 if (mips_opts.micromips)
1938 return micromips_insn_length (insn->insn_mo);
1939 else if (mips_opts.mips16)
1940 return mips16_opcode_length (insn->insn_opcode);
1945 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1948 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1953 insn->insn_opcode = mo->match;
1956 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1957 insn->fixp[i] = NULL;
1958 insn->fixed_p = (mips_opts.noreorder > 0);
1959 insn->noreorder_p = (mips_opts.noreorder > 0);
1960 insn->mips16_absolute_jump_p = 0;
1961 insn->complete_p = 0;
1962 insn->cleared_p = 0;
1965 /* Get a list of all the operands in INSN. */
1967 static const struct mips_operand_array *
1968 insn_operands (const struct mips_cl_insn *insn)
1970 if (insn->insn_mo >= &mips_opcodes[0]
1971 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
1972 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
1974 if (insn->insn_mo >= &mips16_opcodes[0]
1975 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
1976 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
1978 if (insn->insn_mo >= µmips_opcodes[0]
1979 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
1980 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
1985 /* Get a description of operand OPNO of INSN. */
1987 static const struct mips_operand *
1988 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
1990 const struct mips_operand_array *operands;
1992 operands = insn_operands (insn);
1993 if (opno >= MAX_OPERANDS || !operands->operand[opno])
1995 return operands->operand[opno];
1998 /* Install UVAL as the value of OPERAND in INSN. */
2001 insn_insert_operand (struct mips_cl_insn *insn,
2002 const struct mips_operand *operand, unsigned int uval)
2004 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2007 /* Extract the value of OPERAND from INSN. */
2009 static inline unsigned
2010 insn_extract_operand (const struct mips_cl_insn *insn,
2011 const struct mips_operand *operand)
2013 return mips_extract_operand (operand, insn->insn_opcode);
2016 /* Record the current MIPS16/microMIPS mode in now_seg. */
2019 mips_record_compressed_mode (void)
2021 segment_info_type *si;
2023 si = seg_info (now_seg);
2024 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2025 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2026 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2027 si->tc_segment_info_data.micromips = mips_opts.micromips;
2030 /* Read a standard MIPS instruction from BUF. */
2032 static unsigned long
2033 read_insn (char *buf)
2035 if (target_big_endian)
2036 return bfd_getb32 ((bfd_byte *) buf);
2038 return bfd_getl32 ((bfd_byte *) buf);
2041 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2045 write_insn (char *buf, unsigned int insn)
2047 md_number_to_chars (buf, insn, 4);
2051 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2052 has length LENGTH. */
2054 static unsigned long
2055 read_compressed_insn (char *buf, unsigned int length)
2061 for (i = 0; i < length; i += 2)
2064 if (target_big_endian)
2065 insn |= bfd_getb16 ((char *) buf);
2067 insn |= bfd_getl16 ((char *) buf);
2073 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2074 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2077 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2081 for (i = 0; i < length; i += 2)
2082 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2083 return buf + length;
2086 /* Install INSN at the location specified by its "frag" and "where" fields. */
2089 install_insn (const struct mips_cl_insn *insn)
2091 char *f = insn->frag->fr_literal + insn->where;
2092 if (HAVE_CODE_COMPRESSION)
2093 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2095 write_insn (f, insn->insn_opcode);
2096 mips_record_compressed_mode ();
2099 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2100 and install the opcode in the new location. */
2103 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2108 insn->where = where;
2109 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2110 if (insn->fixp[i] != NULL)
2112 insn->fixp[i]->fx_frag = frag;
2113 insn->fixp[i]->fx_where = where;
2115 install_insn (insn);
2118 /* Add INSN to the end of the output. */
2121 add_fixed_insn (struct mips_cl_insn *insn)
2123 char *f = frag_more (insn_length (insn));
2124 move_insn (insn, frag_now, f - frag_now->fr_literal);
2127 /* Start a variant frag and move INSN to the start of the variant part,
2128 marking it as fixed. The other arguments are as for frag_var. */
2131 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2132 relax_substateT subtype, symbolS *symbol, offsetT offset)
2134 frag_grow (max_chars);
2135 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2137 frag_var (rs_machine_dependent, max_chars, var,
2138 subtype, symbol, offset, NULL);
2141 /* Insert N copies of INSN into the history buffer, starting at
2142 position FIRST. Neither FIRST nor N need to be clipped. */
2145 insert_into_history (unsigned int first, unsigned int n,
2146 const struct mips_cl_insn *insn)
2148 if (mips_relax.sequence != 2)
2152 for (i = ARRAY_SIZE (history); i-- > first;)
2154 history[i] = history[i - n];
2160 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2161 the idea is to make it obvious at a glance that each errata is
2165 init_vr4120_conflicts (void)
2167 #define CONFLICT(FIRST, SECOND) \
2168 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2170 /* Errata 21 - [D]DIV[U] after [D]MACC */
2171 CONFLICT (MACC, DIV);
2172 CONFLICT (DMACC, DIV);
2174 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2175 CONFLICT (DMULT, DMULT);
2176 CONFLICT (DMULT, DMACC);
2177 CONFLICT (DMACC, DMULT);
2178 CONFLICT (DMACC, DMACC);
2180 /* Errata 24 - MT{LO,HI} after [D]MACC */
2181 CONFLICT (MACC, MTHILO);
2182 CONFLICT (DMACC, MTHILO);
2184 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2185 instruction is executed immediately after a MACC or DMACC
2186 instruction, the result of [either instruction] is incorrect." */
2187 CONFLICT (MACC, MULT);
2188 CONFLICT (MACC, DMULT);
2189 CONFLICT (DMACC, MULT);
2190 CONFLICT (DMACC, DMULT);
2192 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2193 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2194 DDIV or DDIVU instruction, the result of the MACC or
2195 DMACC instruction is incorrect.". */
2196 CONFLICT (DMULT, MACC);
2197 CONFLICT (DMULT, DMACC);
2198 CONFLICT (DIV, MACC);
2199 CONFLICT (DIV, DMACC);
2209 #define RTYPE_MASK 0x1ff00
2210 #define RTYPE_NUM 0x00100
2211 #define RTYPE_FPU 0x00200
2212 #define RTYPE_FCC 0x00400
2213 #define RTYPE_VEC 0x00800
2214 #define RTYPE_GP 0x01000
2215 #define RTYPE_CP0 0x02000
2216 #define RTYPE_PC 0x04000
2217 #define RTYPE_ACC 0x08000
2218 #define RTYPE_CCC 0x10000
2219 #define RNUM_MASK 0x000ff
2220 #define RWARN 0x80000
2222 #define GENERIC_REGISTER_NUMBERS \
2223 {"$0", RTYPE_NUM | 0}, \
2224 {"$1", RTYPE_NUM | 1}, \
2225 {"$2", RTYPE_NUM | 2}, \
2226 {"$3", RTYPE_NUM | 3}, \
2227 {"$4", RTYPE_NUM | 4}, \
2228 {"$5", RTYPE_NUM | 5}, \
2229 {"$6", RTYPE_NUM | 6}, \
2230 {"$7", RTYPE_NUM | 7}, \
2231 {"$8", RTYPE_NUM | 8}, \
2232 {"$9", RTYPE_NUM | 9}, \
2233 {"$10", RTYPE_NUM | 10}, \
2234 {"$11", RTYPE_NUM | 11}, \
2235 {"$12", RTYPE_NUM | 12}, \
2236 {"$13", RTYPE_NUM | 13}, \
2237 {"$14", RTYPE_NUM | 14}, \
2238 {"$15", RTYPE_NUM | 15}, \
2239 {"$16", RTYPE_NUM | 16}, \
2240 {"$17", RTYPE_NUM | 17}, \
2241 {"$18", RTYPE_NUM | 18}, \
2242 {"$19", RTYPE_NUM | 19}, \
2243 {"$20", RTYPE_NUM | 20}, \
2244 {"$21", RTYPE_NUM | 21}, \
2245 {"$22", RTYPE_NUM | 22}, \
2246 {"$23", RTYPE_NUM | 23}, \
2247 {"$24", RTYPE_NUM | 24}, \
2248 {"$25", RTYPE_NUM | 25}, \
2249 {"$26", RTYPE_NUM | 26}, \
2250 {"$27", RTYPE_NUM | 27}, \
2251 {"$28", RTYPE_NUM | 28}, \
2252 {"$29", RTYPE_NUM | 29}, \
2253 {"$30", RTYPE_NUM | 30}, \
2254 {"$31", RTYPE_NUM | 31}
2256 #define FPU_REGISTER_NAMES \
2257 {"$f0", RTYPE_FPU | 0}, \
2258 {"$f1", RTYPE_FPU | 1}, \
2259 {"$f2", RTYPE_FPU | 2}, \
2260 {"$f3", RTYPE_FPU | 3}, \
2261 {"$f4", RTYPE_FPU | 4}, \
2262 {"$f5", RTYPE_FPU | 5}, \
2263 {"$f6", RTYPE_FPU | 6}, \
2264 {"$f7", RTYPE_FPU | 7}, \
2265 {"$f8", RTYPE_FPU | 8}, \
2266 {"$f9", RTYPE_FPU | 9}, \
2267 {"$f10", RTYPE_FPU | 10}, \
2268 {"$f11", RTYPE_FPU | 11}, \
2269 {"$f12", RTYPE_FPU | 12}, \
2270 {"$f13", RTYPE_FPU | 13}, \
2271 {"$f14", RTYPE_FPU | 14}, \
2272 {"$f15", RTYPE_FPU | 15}, \
2273 {"$f16", RTYPE_FPU | 16}, \
2274 {"$f17", RTYPE_FPU | 17}, \
2275 {"$f18", RTYPE_FPU | 18}, \
2276 {"$f19", RTYPE_FPU | 19}, \
2277 {"$f20", RTYPE_FPU | 20}, \
2278 {"$f21", RTYPE_FPU | 21}, \
2279 {"$f22", RTYPE_FPU | 22}, \
2280 {"$f23", RTYPE_FPU | 23}, \
2281 {"$f24", RTYPE_FPU | 24}, \
2282 {"$f25", RTYPE_FPU | 25}, \
2283 {"$f26", RTYPE_FPU | 26}, \
2284 {"$f27", RTYPE_FPU | 27}, \
2285 {"$f28", RTYPE_FPU | 28}, \
2286 {"$f29", RTYPE_FPU | 29}, \
2287 {"$f30", RTYPE_FPU | 30}, \
2288 {"$f31", RTYPE_FPU | 31}
2290 #define FPU_CONDITION_CODE_NAMES \
2291 {"$fcc0", RTYPE_FCC | 0}, \
2292 {"$fcc1", RTYPE_FCC | 1}, \
2293 {"$fcc2", RTYPE_FCC | 2}, \
2294 {"$fcc3", RTYPE_FCC | 3}, \
2295 {"$fcc4", RTYPE_FCC | 4}, \
2296 {"$fcc5", RTYPE_FCC | 5}, \
2297 {"$fcc6", RTYPE_FCC | 6}, \
2298 {"$fcc7", RTYPE_FCC | 7}
2300 #define COPROC_CONDITION_CODE_NAMES \
2301 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2302 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2303 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2304 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2305 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2306 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2307 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2308 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2310 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2311 {"$a4", RTYPE_GP | 8}, \
2312 {"$a5", RTYPE_GP | 9}, \
2313 {"$a6", RTYPE_GP | 10}, \
2314 {"$a7", RTYPE_GP | 11}, \
2315 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2316 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2317 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2318 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2319 {"$t0", RTYPE_GP | 12}, \
2320 {"$t1", RTYPE_GP | 13}, \
2321 {"$t2", RTYPE_GP | 14}, \
2322 {"$t3", RTYPE_GP | 15}
2324 #define O32_SYMBOLIC_REGISTER_NAMES \
2325 {"$t0", RTYPE_GP | 8}, \
2326 {"$t1", RTYPE_GP | 9}, \
2327 {"$t2", RTYPE_GP | 10}, \
2328 {"$t3", RTYPE_GP | 11}, \
2329 {"$t4", RTYPE_GP | 12}, \
2330 {"$t5", RTYPE_GP | 13}, \
2331 {"$t6", RTYPE_GP | 14}, \
2332 {"$t7", RTYPE_GP | 15}, \
2333 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2334 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2335 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2336 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2338 /* Remaining symbolic register names */
2339 #define SYMBOLIC_REGISTER_NAMES \
2340 {"$zero", RTYPE_GP | 0}, \
2341 {"$at", RTYPE_GP | 1}, \
2342 {"$AT", RTYPE_GP | 1}, \
2343 {"$v0", RTYPE_GP | 2}, \
2344 {"$v1", RTYPE_GP | 3}, \
2345 {"$a0", RTYPE_GP | 4}, \
2346 {"$a1", RTYPE_GP | 5}, \
2347 {"$a2", RTYPE_GP | 6}, \
2348 {"$a3", RTYPE_GP | 7}, \
2349 {"$s0", RTYPE_GP | 16}, \
2350 {"$s1", RTYPE_GP | 17}, \
2351 {"$s2", RTYPE_GP | 18}, \
2352 {"$s3", RTYPE_GP | 19}, \
2353 {"$s4", RTYPE_GP | 20}, \
2354 {"$s5", RTYPE_GP | 21}, \
2355 {"$s6", RTYPE_GP | 22}, \
2356 {"$s7", RTYPE_GP | 23}, \
2357 {"$t8", RTYPE_GP | 24}, \
2358 {"$t9", RTYPE_GP | 25}, \
2359 {"$k0", RTYPE_GP | 26}, \
2360 {"$kt0", RTYPE_GP | 26}, \
2361 {"$k1", RTYPE_GP | 27}, \
2362 {"$kt1", RTYPE_GP | 27}, \
2363 {"$gp", RTYPE_GP | 28}, \
2364 {"$sp", RTYPE_GP | 29}, \
2365 {"$s8", RTYPE_GP | 30}, \
2366 {"$fp", RTYPE_GP | 30}, \
2367 {"$ra", RTYPE_GP | 31}
2369 #define MIPS16_SPECIAL_REGISTER_NAMES \
2370 {"$pc", RTYPE_PC | 0}
2372 #define MDMX_VECTOR_REGISTER_NAMES \
2373 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2374 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2375 {"$v2", RTYPE_VEC | 2}, \
2376 {"$v3", RTYPE_VEC | 3}, \
2377 {"$v4", RTYPE_VEC | 4}, \
2378 {"$v5", RTYPE_VEC | 5}, \
2379 {"$v6", RTYPE_VEC | 6}, \
2380 {"$v7", RTYPE_VEC | 7}, \
2381 {"$v8", RTYPE_VEC | 8}, \
2382 {"$v9", RTYPE_VEC | 9}, \
2383 {"$v10", RTYPE_VEC | 10}, \
2384 {"$v11", RTYPE_VEC | 11}, \
2385 {"$v12", RTYPE_VEC | 12}, \
2386 {"$v13", RTYPE_VEC | 13}, \
2387 {"$v14", RTYPE_VEC | 14}, \
2388 {"$v15", RTYPE_VEC | 15}, \
2389 {"$v16", RTYPE_VEC | 16}, \
2390 {"$v17", RTYPE_VEC | 17}, \
2391 {"$v18", RTYPE_VEC | 18}, \
2392 {"$v19", RTYPE_VEC | 19}, \
2393 {"$v20", RTYPE_VEC | 20}, \
2394 {"$v21", RTYPE_VEC | 21}, \
2395 {"$v22", RTYPE_VEC | 22}, \
2396 {"$v23", RTYPE_VEC | 23}, \
2397 {"$v24", RTYPE_VEC | 24}, \
2398 {"$v25", RTYPE_VEC | 25}, \
2399 {"$v26", RTYPE_VEC | 26}, \
2400 {"$v27", RTYPE_VEC | 27}, \
2401 {"$v28", RTYPE_VEC | 28}, \
2402 {"$v29", RTYPE_VEC | 29}, \
2403 {"$v30", RTYPE_VEC | 30}, \
2404 {"$v31", RTYPE_VEC | 31}
2406 #define MIPS_DSP_ACCUMULATOR_NAMES \
2407 {"$ac0", RTYPE_ACC | 0}, \
2408 {"$ac1", RTYPE_ACC | 1}, \
2409 {"$ac2", RTYPE_ACC | 2}, \
2410 {"$ac3", RTYPE_ACC | 3}
2412 static const struct regname reg_names[] = {
2413 GENERIC_REGISTER_NUMBERS,
2415 FPU_CONDITION_CODE_NAMES,
2416 COPROC_CONDITION_CODE_NAMES,
2418 /* The $txx registers depends on the abi,
2419 these will be added later into the symbol table from
2420 one of the tables below once mips_abi is set after
2421 parsing of arguments from the command line. */
2422 SYMBOLIC_REGISTER_NAMES,
2424 MIPS16_SPECIAL_REGISTER_NAMES,
2425 MDMX_VECTOR_REGISTER_NAMES,
2426 MIPS_DSP_ACCUMULATOR_NAMES,
2430 static const struct regname reg_names_o32[] = {
2431 O32_SYMBOLIC_REGISTER_NAMES,
2435 static const struct regname reg_names_n32n64[] = {
2436 N32N64_SYMBOLIC_REGISTER_NAMES,
2440 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2441 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2442 of these register symbols, return the associated vector register,
2443 otherwise return SYMVAL itself. */
2446 mips_prefer_vec_regno (unsigned int symval)
2448 if ((symval & -2) == (RTYPE_GP | 2))
2449 return RTYPE_VEC | (symval & 1);
2453 /* Return true if the string at *SPTR is a valid register name. If so,
2454 move *SPTR past the register and store the register's symbol value
2455 in *SYMVAL. This symbol value includes the register number
2456 (RNUM_MASK) and register type (RTYPE_MASK). */
2459 mips_parse_register (char **sptr, unsigned int *symval)
2465 /* Find end of name. */
2467 if (is_name_beginner (*e))
2469 while (is_part_of_name (*e))
2472 /* Terminate name. */
2476 /* Look up the name. */
2477 symbol = symbol_find (s);
2480 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2484 *symval = S_GET_VALUE (symbol);
2488 /* Check if SPTR points at a valid register specifier according to TYPES.
2489 If so, then return 1, advance S to consume the specifier and store
2490 the register's number in REGNOP, otherwise return 0. */
2493 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2497 if (mips_parse_register (s, ®no))
2499 if (types & RTYPE_VEC)
2500 regno = mips_prefer_vec_regno (regno);
2509 as_warn (_("Unrecognized register name `%s'"), *s);
2514 return regno <= RNUM_MASK;
2517 /* Token types for parsed operand lists. */
2518 enum mips_operand_token_type {
2519 /* A plain register, e.g. $f2. */
2522 /* An element of a vector, e.g. $v0[1]. */
2525 /* A continuous range of registers, e.g. $s0-$s4. */
2528 /* A (possibly relocated) expression. */
2531 /* A floating-point value. */
2534 /* A single character. This can be '(', ')' or ',', but '(' only appears
2538 /* The end of the operand list. */
2542 /* A parsed operand token. */
2543 struct mips_operand_token
2545 /* The type of token. */
2546 enum mips_operand_token_type type;
2549 /* The register symbol value for an OT_REG. */
2552 /* The register symbol value and index for an OT_REG_ELEMENT. */
2558 /* The two register symbol values involved in an OT_REG_RANGE. */
2560 unsigned int regno1;
2561 unsigned int regno2;
2564 /* The value of an OT_INTEGER. The value is represented as an
2565 expression and the relocation operators that were applied to
2566 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2567 relocation operators were used. */
2570 bfd_reloc_code_real_type relocs[3];
2573 /* The binary data for an OT_FLOAT constant, and the number of bytes
2576 unsigned char data[8];
2580 /* The character represented by an OT_CHAR. */
2585 /* An obstack used to construct lists of mips_operand_tokens. */
2586 static struct obstack mips_operand_tokens;
2588 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2591 mips_add_token (struct mips_operand_token *token,
2592 enum mips_operand_token_type type)
2595 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2598 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2599 and OT_REG tokens for them if so, and return a pointer to the first
2600 unconsumed character. Return null otherwise. */
2603 mips_parse_base_start (char *s)
2605 struct mips_operand_token token;
2612 SKIP_SPACE_TABS (s);
2613 if (!mips_parse_register (&s, ®no))
2617 mips_add_token (&token, OT_CHAR);
2619 token.u.regno = regno;
2620 mips_add_token (&token, OT_REG);
2625 /* Parse one or more tokens from S. Return a pointer to the first
2626 unconsumed character on success. Return null if an error was found
2627 and store the error text in insn_error. FLOAT_FORMAT is as for
2628 mips_parse_arguments. */
2631 mips_parse_argument_token (char *s, char float_format)
2633 char *end, *save_in, *err;
2634 unsigned int regno1, regno2;
2635 struct mips_operand_token token;
2637 /* First look for "($reg", since we want to treat that as an
2638 OT_CHAR and OT_REG rather than an expression. */
2639 end = mips_parse_base_start (s);
2643 /* Handle other characters that end up as OT_CHARs. */
2644 if (*s == ')' || *s == ',')
2647 mips_add_token (&token, OT_CHAR);
2652 /* Handle tokens that start with a register. */
2653 if (mips_parse_register (&s, ®no1))
2655 SKIP_SPACE_TABS (s);
2658 /* A register range. */
2660 SKIP_SPACE_TABS (s);
2661 if (!mips_parse_register (&s, ®no2))
2663 insn_error = _("Invalid register range");
2667 token.u.reg_range.regno1 = regno1;
2668 token.u.reg_range.regno2 = regno2;
2669 mips_add_token (&token, OT_REG_RANGE);
2674 /* A vector element. */
2675 expressionS element;
2678 SKIP_SPACE_TABS (s);
2679 my_getExpression (&element, s);
2680 if (element.X_op != O_constant)
2682 insn_error = _("Vector element must be constant");
2686 SKIP_SPACE_TABS (s);
2689 insn_error = _("Missing `]'");
2694 token.u.reg_element.regno = regno1;
2695 token.u.reg_element.index = element.X_add_number;
2696 mips_add_token (&token, OT_REG_ELEMENT);
2700 /* Looks like just a plain register. */
2701 token.u.regno = regno1;
2702 mips_add_token (&token, OT_REG);
2708 /* First try to treat expressions as floats. */
2709 save_in = input_line_pointer;
2710 input_line_pointer = s;
2711 err = md_atof (float_format, (char *) token.u.flt.data,
2712 &token.u.flt.length);
2713 end = input_line_pointer;
2714 input_line_pointer = save_in;
2722 mips_add_token (&token, OT_FLOAT);
2727 /* Treat everything else as an integer expression. */
2728 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
2729 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
2730 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
2731 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
2733 mips_add_token (&token, OT_INTEGER);
2737 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2738 if expressions should be treated as 32-bit floating-point constants,
2739 'd' if they should be treated as 64-bit floating-point constants,
2740 or 0 if they should be treated as integer expressions (the usual case).
2742 Return a list of tokens on success, otherwise return 0. The caller
2743 must obstack_free the list after use. */
2745 static struct mips_operand_token *
2746 mips_parse_arguments (char *s, char float_format)
2748 struct mips_operand_token token;
2750 SKIP_SPACE_TABS (s);
2753 s = mips_parse_argument_token (s, float_format);
2756 obstack_free (&mips_operand_tokens,
2757 obstack_finish (&mips_operand_tokens));
2760 SKIP_SPACE_TABS (s);
2762 mips_add_token (&token, OT_END);
2763 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
2766 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2767 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2770 is_opcode_valid (const struct mips_opcode *mo)
2772 int isa = mips_opts.isa;
2773 int ase = mips_opts.ase;
2777 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2778 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2779 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2780 ase |= mips_ases[i].flags64;
2782 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2785 /* Check whether the instruction or macro requires single-precision or
2786 double-precision floating-point support. Note that this information is
2787 stored differently in the opcode table for insns and macros. */
2788 if (mo->pinfo == INSN_MACRO)
2790 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2791 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2795 fp_s = mo->pinfo & FP_S;
2796 fp_d = mo->pinfo & FP_D;
2799 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2802 if (fp_s && mips_opts.soft_float)
2808 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2809 selected ISA and architecture. */
2812 is_opcode_valid_16 (const struct mips_opcode *mo)
2814 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2817 /* Return TRUE if the size of the microMIPS opcode MO matches one
2818 explicitly requested. Always TRUE in the standard MIPS mode. */
2821 is_size_valid (const struct mips_opcode *mo)
2823 if (!mips_opts.micromips)
2826 if (mips_opts.insn32)
2828 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2830 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2833 if (!forced_insn_length)
2835 if (mo->pinfo == INSN_MACRO)
2837 return forced_insn_length == micromips_insn_length (mo);
2840 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2841 of the preceding instruction. Always TRUE in the standard MIPS mode.
2843 We don't accept macros in 16-bit delay slots to avoid a case where
2844 a macro expansion fails because it relies on a preceding 32-bit real
2845 instruction to have matched and does not handle the operands correctly.
2846 The only macros that may expand to 16-bit instructions are JAL that
2847 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2848 and BGT (that likewise cannot be placed in a delay slot) that decay to
2849 a NOP. In all these cases the macros precede any corresponding real
2850 instruction definitions in the opcode table, so they will match in the
2851 second pass where the size of the delay slot is ignored and therefore
2852 produce correct code. */
2855 is_delay_slot_valid (const struct mips_opcode *mo)
2857 if (!mips_opts.micromips)
2860 if (mo->pinfo == INSN_MACRO)
2861 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2862 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2863 && micromips_insn_length (mo) != 4)
2865 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2866 && micromips_insn_length (mo) != 2)
2872 /* For consistency checking, verify that all bits of OPCODE are specified
2873 either by the match/mask part of the instruction definition, or by the
2874 operand list. Also build up a list of operands in OPERANDS.
2876 INSN_BITS says which bits of the instruction are significant.
2877 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
2878 provides the mips_operand description of each operand. DECODE_OPERAND
2879 is null for MIPS16 instructions. */
2882 validate_mips_insn (const struct mips_opcode *opcode,
2883 unsigned long insn_bits,
2884 const struct mips_operand *(*decode_operand) (const char *),
2885 struct mips_operand_array *operands)
2888 unsigned long used_bits, doubled, undefined, opno, mask;
2889 const struct mips_operand *operand;
2891 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
2892 if ((mask & opcode->match) != opcode->match)
2894 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
2895 opcode->name, opcode->args);
2900 for (s = opcode->args; *s; ++s)
2909 if (!decode_operand)
2910 operand = decode_mips16_operand (*s, FALSE);
2912 operand = decode_operand (s);
2913 if (!operand && opcode->pinfo != INSN_MACRO)
2915 as_bad (_("internal: unknown operand type: %s %s"),
2916 opcode->name, opcode->args);
2919 gas_assert (opno < MAX_OPERANDS);
2920 operands->operand[opno] = operand;
2923 used_bits |= ((1 << operand->size) - 1) << operand->lsb;
2924 if (operand->type == OP_MDMX_IMM_REG)
2925 /* Bit 5 is the format selector (OB vs QH). The opcode table
2926 has separate entries for each format. */
2927 used_bits &= ~(1 << (operand->lsb + 5));
2928 if (operand->type == OP_ENTRY_EXIT_LIST)
2929 used_bits &= ~(mask & 0x700);
2931 /* Skip prefix characters. */
2932 if (decode_operand && (*s == '+' || *s == 'm'))
2937 doubled = used_bits & mask & insn_bits;
2940 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
2941 " %s %s"), doubled, opcode->name, opcode->args);
2945 undefined = ~used_bits & insn_bits;
2946 if (opcode->pinfo != INSN_MACRO && undefined)
2948 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
2949 undefined, opcode->name, opcode->args);
2952 used_bits &= ~insn_bits;
2955 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
2956 used_bits, opcode->name, opcode->args);
2962 /* The MIPS16 version of validate_mips_insn. */
2965 validate_mips16_insn (const struct mips_opcode *opcode,
2966 struct mips_operand_array *operands)
2968 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
2970 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
2971 instruction. Use TMP to describe the full instruction. */
2972 struct mips_opcode tmp;
2977 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
2979 return validate_mips_insn (opcode, 0xffff, 0, operands);
2982 /* The microMIPS version of validate_mips_insn. */
2985 validate_micromips_insn (const struct mips_opcode *opc,
2986 struct mips_operand_array *operands)
2988 unsigned long insn_bits;
2989 unsigned long major;
2990 unsigned int length;
2992 if (opc->pinfo == INSN_MACRO)
2993 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
2996 length = micromips_insn_length (opc);
2997 if (length != 2 && length != 4)
2999 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3000 "%s %s"), length, opc->name, opc->args);
3003 major = opc->match >> (10 + 8 * (length - 2));
3004 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3005 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3007 as_bad (_("Internal error: bad microMIPS opcode "
3008 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3012 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3013 insn_bits = 1 << 4 * length;
3014 insn_bits <<= 4 * length;
3016 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3020 /* This function is called once, at assembler startup time. It should set up
3021 all the tables, etc. that the MD part of the assembler will need. */
3026 const char *retval = NULL;
3030 if (mips_pic != NO_PIC)
3032 if (g_switch_seen && g_switch_value != 0)
3033 as_bad (_("-G may not be used in position-independent code"));
3037 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
3038 as_warn (_("Could not set architecture and machine"));
3040 op_hash = hash_new ();
3042 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3043 for (i = 0; i < NUMOPCODES;)
3045 const char *name = mips_opcodes[i].name;
3047 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3050 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3051 mips_opcodes[i].name, retval);
3052 /* Probably a memory allocation problem? Give up now. */
3053 as_fatal (_("Broken assembler. No assembly attempted."));
3057 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3058 decode_mips_operand, &mips_operands[i]))
3060 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3062 create_insn (&nop_insn, mips_opcodes + i);
3063 if (mips_fix_loongson2f_nop)
3064 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3065 nop_insn.fixed_p = 1;
3069 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3072 mips16_op_hash = hash_new ();
3073 mips16_operands = XCNEWVEC (struct mips_operand_array,
3074 bfd_mips16_num_opcodes);
3077 while (i < bfd_mips16_num_opcodes)
3079 const char *name = mips16_opcodes[i].name;
3081 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3083 as_fatal (_("internal: can't hash `%s': %s"),
3084 mips16_opcodes[i].name, retval);
3087 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3089 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3091 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3092 mips16_nop_insn.fixed_p = 1;
3096 while (i < bfd_mips16_num_opcodes
3097 && strcmp (mips16_opcodes[i].name, name) == 0);
3100 micromips_op_hash = hash_new ();
3101 micromips_operands = XCNEWVEC (struct mips_operand_array,
3102 bfd_micromips_num_opcodes);
3105 while (i < bfd_micromips_num_opcodes)
3107 const char *name = micromips_opcodes[i].name;
3109 retval = hash_insert (micromips_op_hash, name,
3110 (void *) µmips_opcodes[i]);
3112 as_fatal (_("internal: can't hash `%s': %s"),
3113 micromips_opcodes[i].name, retval);
3116 struct mips_cl_insn *micromips_nop_insn;
3118 if (!validate_micromips_insn (µmips_opcodes[i],
3119 µmips_operands[i]))
3122 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3124 if (micromips_insn_length (micromips_opcodes + i) == 2)
3125 micromips_nop_insn = µmips_nop16_insn;
3126 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3127 micromips_nop_insn = µmips_nop32_insn;
3131 if (micromips_nop_insn->insn_mo == NULL
3132 && strcmp (name, "nop") == 0)
3134 create_insn (micromips_nop_insn, micromips_opcodes + i);
3135 micromips_nop_insn->fixed_p = 1;
3139 while (++i < bfd_micromips_num_opcodes
3140 && strcmp (micromips_opcodes[i].name, name) == 0);
3144 as_fatal (_("Broken assembler. No assembly attempted."));
3146 /* We add all the general register names to the symbol table. This
3147 helps us detect invalid uses of them. */
3148 for (i = 0; reg_names[i].name; i++)
3149 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3150 reg_names[i].num, /* & RNUM_MASK, */
3151 &zero_address_frag));
3153 for (i = 0; reg_names_n32n64[i].name; i++)
3154 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3155 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3156 &zero_address_frag));
3158 for (i = 0; reg_names_o32[i].name; i++)
3159 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3160 reg_names_o32[i].num, /* & RNUM_MASK, */
3161 &zero_address_frag));
3163 obstack_init (&mips_operand_tokens);
3165 mips_no_prev_insn ();
3168 mips_cprmask[0] = 0;
3169 mips_cprmask[1] = 0;
3170 mips_cprmask[2] = 0;
3171 mips_cprmask[3] = 0;
3173 /* set the default alignment for the text section (2**2) */
3174 record_alignment (text_section, 2);
3176 bfd_set_gp_size (stdoutput, g_switch_value);
3178 /* On a native system other than VxWorks, sections must be aligned
3179 to 16 byte boundaries. When configured for an embedded ELF
3180 target, we don't bother. */
3181 if (strncmp (TARGET_OS, "elf", 3) != 0
3182 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3184 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3185 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3186 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3189 /* Create a .reginfo section for register masks and a .mdebug
3190 section for debugging information. */
3198 subseg = now_subseg;
3200 /* The ABI says this section should be loaded so that the
3201 running program can access it. However, we don't load it
3202 if we are configured for an embedded target */
3203 flags = SEC_READONLY | SEC_DATA;
3204 if (strncmp (TARGET_OS, "elf", 3) != 0)
3205 flags |= SEC_ALLOC | SEC_LOAD;
3207 if (mips_abi != N64_ABI)
3209 sec = subseg_new (".reginfo", (subsegT) 0);
3211 bfd_set_section_flags (stdoutput, sec, flags);
3212 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3214 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3218 /* The 64-bit ABI uses a .MIPS.options section rather than
3219 .reginfo section. */
3220 sec = subseg_new (".MIPS.options", (subsegT) 0);
3221 bfd_set_section_flags (stdoutput, sec, flags);
3222 bfd_set_section_alignment (stdoutput, sec, 3);
3224 /* Set up the option header. */
3226 Elf_Internal_Options opthdr;
3229 opthdr.kind = ODK_REGINFO;
3230 opthdr.size = (sizeof (Elf_External_Options)
3231 + sizeof (Elf64_External_RegInfo));
3234 f = frag_more (sizeof (Elf_External_Options));
3235 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3236 (Elf_External_Options *) f);
3238 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3242 if (ECOFF_DEBUGGING)
3244 sec = subseg_new (".mdebug", (subsegT) 0);
3245 (void) bfd_set_section_flags (stdoutput, sec,
3246 SEC_HAS_CONTENTS | SEC_READONLY);
3247 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3249 else if (mips_flag_pdr)
3251 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3252 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3253 SEC_READONLY | SEC_RELOC
3255 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3258 subseg_set (seg, subseg);
3261 if (! ECOFF_DEBUGGING)
3264 if (mips_fix_vr4120)
3265 init_vr4120_conflicts ();
3271 mips_emit_delays ();
3272 if (! ECOFF_DEBUGGING)
3277 md_assemble (char *str)
3279 struct mips_cl_insn insn;
3280 bfd_reloc_code_real_type unused_reloc[3]
3281 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3283 imm_expr.X_op = O_absent;
3284 imm2_expr.X_op = O_absent;
3285 offset_expr.X_op = O_absent;
3286 offset_reloc[0] = BFD_RELOC_UNUSED;
3287 offset_reloc[1] = BFD_RELOC_UNUSED;
3288 offset_reloc[2] = BFD_RELOC_UNUSED;
3290 mips_mark_labels ();
3291 mips_assembling_insn = TRUE;
3293 if (mips_opts.mips16)
3294 mips16_ip (str, &insn);
3297 mips_ip (str, &insn);
3298 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3299 str, insn.insn_opcode));
3303 as_bad ("%s `%s'", insn_error, str);
3304 else if (insn.insn_mo->pinfo == INSN_MACRO)
3307 if (mips_opts.mips16)
3308 mips16_macro (&insn);
3315 if (offset_expr.X_op != O_absent)
3316 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3318 append_insn (&insn, NULL, unused_reloc, FALSE);
3321 mips_assembling_insn = FALSE;
3324 /* Convenience functions for abstracting away the differences between
3325 MIPS16 and non-MIPS16 relocations. */
3327 static inline bfd_boolean
3328 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3332 case BFD_RELOC_MIPS16_JMP:
3333 case BFD_RELOC_MIPS16_GPREL:
3334 case BFD_RELOC_MIPS16_GOT16:
3335 case BFD_RELOC_MIPS16_CALL16:
3336 case BFD_RELOC_MIPS16_HI16_S:
3337 case BFD_RELOC_MIPS16_HI16:
3338 case BFD_RELOC_MIPS16_LO16:
3346 static inline bfd_boolean
3347 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3351 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3352 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3353 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3354 case BFD_RELOC_MICROMIPS_GPREL16:
3355 case BFD_RELOC_MICROMIPS_JMP:
3356 case BFD_RELOC_MICROMIPS_HI16:
3357 case BFD_RELOC_MICROMIPS_HI16_S:
3358 case BFD_RELOC_MICROMIPS_LO16:
3359 case BFD_RELOC_MICROMIPS_LITERAL:
3360 case BFD_RELOC_MICROMIPS_GOT16:
3361 case BFD_RELOC_MICROMIPS_CALL16:
3362 case BFD_RELOC_MICROMIPS_GOT_HI16:
3363 case BFD_RELOC_MICROMIPS_GOT_LO16:
3364 case BFD_RELOC_MICROMIPS_CALL_HI16:
3365 case BFD_RELOC_MICROMIPS_CALL_LO16:
3366 case BFD_RELOC_MICROMIPS_SUB:
3367 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3368 case BFD_RELOC_MICROMIPS_GOT_OFST:
3369 case BFD_RELOC_MICROMIPS_GOT_DISP:
3370 case BFD_RELOC_MICROMIPS_HIGHEST:
3371 case BFD_RELOC_MICROMIPS_HIGHER:
3372 case BFD_RELOC_MICROMIPS_SCN_DISP:
3373 case BFD_RELOC_MICROMIPS_JALR:
3381 static inline bfd_boolean
3382 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3384 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3387 static inline bfd_boolean
3388 got16_reloc_p (bfd_reloc_code_real_type reloc)
3390 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3391 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3394 static inline bfd_boolean
3395 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3397 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3398 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3401 static inline bfd_boolean
3402 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3404 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3405 || reloc == BFD_RELOC_MICROMIPS_LO16);
3408 static inline bfd_boolean
3409 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3411 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3414 static inline bfd_boolean
3415 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3417 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3418 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3421 /* Return true if RELOC is a PC-relative relocation that does not have
3422 full address range. */
3424 static inline bfd_boolean
3425 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3429 case BFD_RELOC_16_PCREL_S2:
3430 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3431 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3432 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3435 case BFD_RELOC_32_PCREL:
3436 return HAVE_64BIT_ADDRESSES;
3443 /* Return true if the given relocation might need a matching %lo().
3444 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3445 need a matching %lo() when applied to local symbols. */
3447 static inline bfd_boolean
3448 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3450 return (HAVE_IN_PLACE_ADDENDS
3451 && (hi16_reloc_p (reloc)
3452 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3453 all GOT16 relocations evaluate to "G". */
3454 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3457 /* Return the type of %lo() reloc needed by RELOC, given that
3458 reloc_needs_lo_p. */
3460 static inline bfd_reloc_code_real_type
3461 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3463 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3464 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3468 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3471 static inline bfd_boolean
3472 fixup_has_matching_lo_p (fixS *fixp)
3474 return (fixp->fx_next != NULL
3475 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3476 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3477 && fixp->fx_offset == fixp->fx_next->fx_offset);
3480 /* Move all labels in LABELS to the current insertion point. TEXT_P
3481 says whether the labels refer to text or data. */
3484 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3486 struct insn_label_list *l;
3489 for (l = labels; l != NULL; l = l->next)
3491 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3492 symbol_set_frag (l->label, frag_now);
3493 val = (valueT) frag_now_fix ();
3494 /* MIPS16/microMIPS text labels are stored as odd. */
3495 if (text_p && HAVE_CODE_COMPRESSION)
3497 S_SET_VALUE (l->label, val);
3501 /* Move all labels in insn_labels to the current insertion point
3502 and treat them as text labels. */
3505 mips_move_text_labels (void)
3507 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3511 s_is_linkonce (symbolS *sym, segT from_seg)
3513 bfd_boolean linkonce = FALSE;
3514 segT symseg = S_GET_SEGMENT (sym);
3516 if (symseg != from_seg && !S_IS_LOCAL (sym))
3518 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3520 /* The GNU toolchain uses an extension for ELF: a section
3521 beginning with the magic string .gnu.linkonce is a
3522 linkonce section. */
3523 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3524 sizeof ".gnu.linkonce" - 1) == 0)
3530 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3531 linker to handle them specially, such as generating jalx instructions
3532 when needed. We also make them odd for the duration of the assembly,
3533 in order to generate the right sort of code. We will make them even
3534 in the adjust_symtab routine, while leaving them marked. This is
3535 convenient for the debugger and the disassembler. The linker knows
3536 to make them odd again. */
3539 mips_compressed_mark_label (symbolS *label)
3541 gas_assert (HAVE_CODE_COMPRESSION);
3543 if (mips_opts.mips16)
3544 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3546 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3547 if ((S_GET_VALUE (label) & 1) == 0
3548 /* Don't adjust the address if the label is global or weak, or
3549 in a link-once section, since we'll be emitting symbol reloc
3550 references to it which will be patched up by the linker, and
3551 the final value of the symbol may or may not be MIPS16/microMIPS. */
3552 && !S_IS_WEAK (label)
3553 && !S_IS_EXTERNAL (label)
3554 && !s_is_linkonce (label, now_seg))
3555 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3558 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3561 mips_compressed_mark_labels (void)
3563 struct insn_label_list *l;
3565 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3566 mips_compressed_mark_label (l->label);
3569 /* End the current frag. Make it a variant frag and record the
3573 relax_close_frag (void)
3575 mips_macro_warning.first_frag = frag_now;
3576 frag_var (rs_machine_dependent, 0, 0,
3577 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3578 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3580 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3581 mips_relax.first_fixup = 0;
3584 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3585 See the comment above RELAX_ENCODE for more details. */
3588 relax_start (symbolS *symbol)
3590 gas_assert (mips_relax.sequence == 0);
3591 mips_relax.sequence = 1;
3592 mips_relax.symbol = symbol;
3595 /* Start generating the second version of a relaxable sequence.
3596 See the comment above RELAX_ENCODE for more details. */
3601 gas_assert (mips_relax.sequence == 1);
3602 mips_relax.sequence = 2;
3605 /* End the current relaxable sequence. */
3610 gas_assert (mips_relax.sequence == 2);
3611 relax_close_frag ();
3612 mips_relax.sequence = 0;
3615 /* Return true if IP is a delayed branch or jump. */
3617 static inline bfd_boolean
3618 delayed_branch_p (const struct mips_cl_insn *ip)
3620 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3621 | INSN_COND_BRANCH_DELAY
3622 | INSN_COND_BRANCH_LIKELY)) != 0;
3625 /* Return true if IP is a compact branch or jump. */
3627 static inline bfd_boolean
3628 compact_branch_p (const struct mips_cl_insn *ip)
3630 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3631 | INSN2_COND_BRANCH)) != 0;
3634 /* Return true if IP is an unconditional branch or jump. */
3636 static inline bfd_boolean
3637 uncond_branch_p (const struct mips_cl_insn *ip)
3639 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3640 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
3643 /* Return true if IP is a branch-likely instruction. */
3645 static inline bfd_boolean
3646 branch_likely_p (const struct mips_cl_insn *ip)
3648 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3651 /* Return the type of nop that should be used to fill the delay slot
3652 of delayed branch IP. */
3654 static struct mips_cl_insn *
3655 get_delay_slot_nop (const struct mips_cl_insn *ip)
3657 if (mips_opts.micromips
3658 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3659 return µmips_nop32_insn;
3663 /* Return a mask that has bit N set if OPCODE reads the register(s)
3667 insn_read_mask (const struct mips_opcode *opcode)
3669 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
3672 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3676 insn_write_mask (const struct mips_opcode *opcode)
3678 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
3681 /* Return a mask of the registers specified by operand OPERAND of INSN.
3682 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3686 operand_reg_mask (const struct mips_cl_insn *insn,
3687 const struct mips_operand *operand,
3688 unsigned int type_mask)
3690 unsigned int uval, vsel;
3692 switch (operand->type)
3699 case OP_ADDIUSP_INT:
3700 case OP_ENTRY_EXIT_LIST:
3701 case OP_REPEAT_DEST_REG:
3702 case OP_REPEAT_PREV_REG:
3708 const struct mips_reg_operand *reg_op;
3710 reg_op = (const struct mips_reg_operand *) operand;
3711 if (!(type_mask & (1 << reg_op->reg_type)))
3713 uval = insn_extract_operand (insn, operand);
3714 return 1 << mips_decode_reg_operand (reg_op, uval);
3719 const struct mips_reg_pair_operand *pair_op;
3721 pair_op = (const struct mips_reg_pair_operand *) operand;
3722 if (!(type_mask & (1 << pair_op->reg_type)))
3724 uval = insn_extract_operand (insn, operand);
3725 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
3728 case OP_CLO_CLZ_DEST:
3729 if (!(type_mask & (1 << OP_REG_GP)))
3731 uval = insn_extract_operand (insn, operand);
3732 return (1 << (uval & 31)) | (1 << (uval >> 5));
3734 case OP_LWM_SWM_LIST:
3737 case OP_SAVE_RESTORE_LIST:
3740 case OP_MDMX_IMM_REG:
3741 if (!(type_mask & (1 << OP_REG_VEC)))
3743 uval = insn_extract_operand (insn, operand);
3745 if ((vsel & 0x18) == 0x18)
3747 return 1 << (uval & 31);
3752 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
3753 where bit N of OPNO_MASK is set if operand N should be included.
3754 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3758 insn_reg_mask (const struct mips_cl_insn *insn,
3759 unsigned int type_mask, unsigned int opno_mask)
3761 unsigned int opno, reg_mask;
3765 while (opno_mask != 0)
3768 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
3775 /* Return the mask of core registers that IP reads. */
3778 gpr_read_mask (const struct mips_cl_insn *ip)
3780 unsigned long pinfo, pinfo2;
3783 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
3784 pinfo = ip->insn_mo->pinfo;
3785 pinfo2 = ip->insn_mo->pinfo2;
3786 if (pinfo & INSN_UDI)
3788 /* UDI instructions have traditionally been assumed to read RS
3790 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3791 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3793 if (pinfo & INSN_READ_GPR_24)
3795 if (pinfo2 & INSN2_READ_GPR_16)
3797 if (pinfo2 & INSN2_READ_SP)
3799 if (pinfo2 & INSN2_READ_GPR_31)
3801 /* Don't include register 0. */
3805 /* Return the mask of core registers that IP writes. */
3808 gpr_write_mask (const struct mips_cl_insn *ip)
3810 unsigned long pinfo, pinfo2;
3813 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
3814 pinfo = ip->insn_mo->pinfo;
3815 pinfo2 = ip->insn_mo->pinfo2;
3816 if (pinfo & INSN_WRITE_GPR_24)
3818 if (pinfo & INSN_WRITE_GPR_31)
3820 if (pinfo & INSN_UDI)
3821 /* UDI instructions have traditionally been assumed to write to RD. */
3822 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3823 if (pinfo2 & INSN2_WRITE_SP)
3825 /* Don't include register 0. */
3829 /* Return the mask of floating-point registers that IP reads. */
3832 fpr_read_mask (const struct mips_cl_insn *ip)
3834 unsigned long pinfo;
3837 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
3838 insn_read_mask (ip->insn_mo));
3839 pinfo = ip->insn_mo->pinfo;
3840 /* Conservatively treat all operands to an FP_D instruction are doubles.
3841 (This is overly pessimistic for things like cvt.d.s.) */
3842 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3847 /* Return the mask of floating-point registers that IP writes. */
3850 fpr_write_mask (const struct mips_cl_insn *ip)
3852 unsigned long pinfo;
3855 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
3856 insn_write_mask (ip->insn_mo));
3857 pinfo = ip->insn_mo->pinfo;
3858 /* Conservatively treat all operands to an FP_D instruction are doubles.
3859 (This is overly pessimistic for things like cvt.s.d.) */
3860 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3865 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
3866 Check whether that is allowed. */
3869 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
3871 const char *s = insn->name;
3873 if (insn->pinfo == INSN_MACRO)
3874 /* Let a macro pass, we'll catch it later when it is expanded. */
3877 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
3879 /* Allow odd registers for single-precision ops. */
3880 switch (insn->pinfo & (FP_S | FP_D))
3891 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
3892 s = strchr (insn->name, '.');
3893 if (s != NULL && opnum == 2)
3894 s = strchr (s + 1, '.');
3895 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
3898 /* Single-precision coprocessor loads and moves are OK too. */
3899 if ((insn->pinfo & FP_S)
3900 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
3901 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
3907 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
3908 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
3909 this operand is normally printed in hex or decimal. */
3912 report_bad_range (struct mips_cl_insn *insn, int argnum,
3913 offsetT val, int min_val, int max_val,
3914 bfd_boolean print_hex)
3916 if (print_hex && val >= 0)
3917 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3919 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3921 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
3923 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3925 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
3927 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
3930 /* Report an invalid combination of position and size operands for a bitfield
3931 operation. POS and SIZE are the values that were given. */
3934 report_bad_field (offsetT pos, offsetT size)
3936 as_bad (_("Invalid field specification (position %ld, size %ld)"),
3937 (unsigned long) pos, (unsigned long) size);
3940 /* Information about an instruction argument that we're trying to match. */
3941 struct mips_arg_info
3943 /* The instruction so far. */
3944 struct mips_cl_insn *insn;
3946 /* The first unconsumed operand token. */
3947 struct mips_operand_token *token;
3949 /* The 1-based operand number, in terms of insn->insn_mo->args. */
3952 /* The 1-based argument number, for error reporting. This does not
3953 count elided optional registers, etc.. */
3956 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
3957 unsigned int last_regno;
3959 /* If the first operand was an OP_REG, this is the register that it
3960 specified, otherwise it is ILLEGAL_REG. */
3961 unsigned int dest_regno;
3963 /* The value of the last OP_INT operand. Only used for OP_MSB,
3964 where it gives the lsb position. */
3965 unsigned int last_op_int;
3967 /* If true, match routines should silently reject invalid arguments.
3968 If false, match routines can accept invalid arguments as long as
3969 they report an appropriate error. They still have the option of
3970 silently rejecting arguments, in which case a generic "Invalid operands"
3971 style of error will be used instead. */
3972 bfd_boolean soft_match;
3974 /* If true, the OP_INT match routine should treat plain symbolic operands
3975 as if a relocation operator like %lo(...) had been used. This is only
3976 ever true if the operand can be relocated. */
3977 bfd_boolean allow_nonconst;
3979 /* When true, the OP_INT match routine should allow unsigned N-bit
3980 arguments to be used where a signed N-bit operand is expected. */
3981 bfd_boolean lax_max;
3983 /* True if a reference to the current AT register was seen. */
3984 bfd_boolean seen_at;
3987 /* Try to match an OT_CHAR token for character CH. Consume the token
3988 and return true on success, otherwise return false. */
3991 match_char (struct mips_arg_info *arg, char ch)
3993 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4003 /* Try to get an expression from the next tokens in ARG. Consume the
4004 tokens and return true on success, storing the expression value in
4005 VALUE and relocation types in R. */
4008 match_expression (struct mips_arg_info *arg, expressionS *value,
4009 bfd_reloc_code_real_type *r)
4011 if (arg->token->type == OT_INTEGER)
4013 *value = arg->token->u.integer.value;
4014 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4019 /* Error-reporting is more consistent if we treat registers as O_register
4020 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4021 then handled in the same way. */
4022 if (arg->token->type == OT_REG)
4024 value->X_add_number = arg->token->u.regno;
4027 else if (arg->token[0].type == OT_CHAR
4028 && arg->token[0].u.ch == '('
4029 && arg->token[1].type == OT_REG
4030 && arg->token[2].type == OT_CHAR
4031 && arg->token[2].u.ch == ')')
4033 value->X_add_number = arg->token[1].u.regno;
4039 value->X_op = O_register;
4040 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4044 /* Try to get a constant expression from the next tokens in ARG. Consume
4045 the tokens and return return true on success, storing the constant value
4046 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4050 match_const_int (struct mips_arg_info *arg, offsetT *value, offsetT fallback)
4053 bfd_reloc_code_real_type r[3];
4055 if (!match_expression (arg, &ex, r))
4058 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4059 *value = ex.X_add_number;
4062 if (arg->soft_match)
4064 as_bad (_("Operand %d of `%s' must be constant"),
4065 arg->argnum, arg->insn->insn_mo->name);
4071 /* Return the RTYPE_* flags for a register operand of type TYPE that
4072 appears in instruction OPCODE. */
4075 convert_reg_type (const struct mips_opcode *opcode,
4076 enum mips_reg_operand_type type)
4081 return RTYPE_NUM | RTYPE_GP;
4084 /* Allow vector register names for MDMX if the instruction is a 64-bit
4085 FPR load, store or move (including moves to and from GPRs). */
4086 if ((mips_opts.ase & ASE_MDMX)
4087 && (opcode->pinfo & FP_D)
4088 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4089 | INSN_COPROC_MEMORY_DELAY
4090 | INSN_LOAD_COPROC_DELAY
4091 | INSN_LOAD_MEMORY_DELAY
4092 | INSN_STORE_MEMORY)))
4093 return RTYPE_FPU | RTYPE_VEC;
4097 if (opcode->pinfo & (FP_D | FP_S))
4098 return RTYPE_CCC | RTYPE_FCC;
4102 if (opcode->membership & INSN_5400)
4104 return RTYPE_FPU | RTYPE_VEC;
4110 if (opcode->name[strlen (opcode->name) - 1] == '0')
4111 return RTYPE_NUM | RTYPE_CP0;
4120 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4123 check_regno (struct mips_arg_info *arg,
4124 enum mips_reg_operand_type type, unsigned int regno)
4126 if (AT && type == OP_REG_GP && regno == AT)
4127 arg->seen_at = TRUE;
4129 if (type == OP_REG_FP
4132 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4133 as_warn (_("Float register should be even, was %d"), regno);
4135 if (type == OP_REG_CCC)
4140 name = arg->insn->insn_mo->name;
4141 length = strlen (name);
4142 if ((regno & 1) != 0
4143 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4144 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4145 as_warn (_("Condition code register should be even for %s, was %d"),
4148 if ((regno & 3) != 0
4149 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4150 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4155 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4156 a register of type TYPE. Return true on success, storing the register
4157 number in *REGNO and warning about any dubious uses. */
4160 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4161 unsigned int symval, unsigned int *regno)
4163 if (type == OP_REG_VEC)
4164 symval = mips_prefer_vec_regno (symval);
4165 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4168 *regno = symval & RNUM_MASK;
4169 check_regno (arg, type, *regno);
4173 /* Try to interpret the next token in ARG as a register of type TYPE.
4174 Consume the token and return true on success, storing the register
4175 number in *REGNO. Return false on failure. */
4178 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4179 unsigned int *regno)
4181 if (arg->token->type == OT_REG
4182 && match_regno (arg, type, arg->token->u.regno, regno))
4190 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4191 Consume the token and return true on success, storing the register numbers
4192 in *REGNO1 and *REGNO2. Return false on failure. */
4195 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4196 unsigned int *regno1, unsigned int *regno2)
4198 if (match_reg (arg, type, regno1))
4203 if (arg->token->type == OT_REG_RANGE
4204 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4205 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4206 && *regno1 <= *regno2)
4214 /* OP_INT matcher. */
4217 match_int_operand (struct mips_arg_info *arg,
4218 const struct mips_operand *operand_base)
4220 const struct mips_int_operand *operand;
4222 int min_val, max_val, factor;
4224 bfd_boolean print_hex;
4226 operand = (const struct mips_int_operand *) operand_base;
4227 factor = 1 << operand->shift;
4228 min_val = mips_int_operand_min (operand);
4229 max_val = mips_int_operand_max (operand);
4231 max_val = ((1 << operand_base->size) - 1) << operand->shift;
4233 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4234 /* Assume we have an elided offset. The later match will fail
4235 if this turns out to be wrong. */
4237 else if (operand_base->lsb == 0
4238 && operand_base->size == 16
4239 && operand->shift == 0
4240 && operand->bias == 0
4241 && (operand->max_val == 32767 || operand->max_val == 65535))
4243 /* The operand can be relocated. */
4244 if (!match_expression (arg, &offset_expr, offset_reloc))
4247 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4248 /* Relocation operators were used. Accept the arguent and
4249 leave the relocation value in offset_expr and offset_relocs
4250 for the caller to process. */
4253 if (offset_expr.X_op != O_constant)
4255 /* If non-constant operands are allowed then leave them for
4256 the caller to process, otherwise fail the match. */
4257 if (!arg->allow_nonconst)
4259 offset_reloc[0] = BFD_RELOC_LO16;
4263 /* Clear the global state; we're going to install the operand
4265 sval = offset_expr.X_add_number;
4266 offset_expr.X_op = O_absent;
4270 if (!match_const_int (arg, &sval, min_val))
4274 arg->last_op_int = sval;
4276 /* Check the range. If there's a problem, record the lowest acceptable
4277 value in arg->last_op_int in order to prevent an unhelpful error
4280 Bit counts have traditionally been printed in hex by the disassembler
4281 but printed as decimal in error messages. Only resort to hex if
4282 the operand is bigger than 6 bits. */
4283 print_hex = operand->print_hex && operand_base->size > 6;
4284 if (sval < min_val || sval > max_val)
4286 if (arg->soft_match)
4288 report_bad_range (arg->insn, arg->argnum, sval, min_val, max_val,
4290 arg->last_op_int = min_val;
4292 else if (sval % factor)
4294 if (arg->soft_match)
4296 as_bad (print_hex && sval >= 0
4297 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4298 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4299 arg->argnum, arg->insn->insn_mo->name, factor,
4300 (unsigned long) sval);
4301 arg->last_op_int = min_val;
4304 uval = (unsigned int) sval >> operand->shift;
4305 uval -= operand->bias;
4307 /* Handle -mfix-cn63xxp1. */
4309 && mips_fix_cn63xxp1
4310 && !mips_opts.micromips
4311 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4326 /* The rest must be changed to 28. */
4331 insn_insert_operand (arg->insn, operand_base, uval);
4335 /* OP_MAPPED_INT matcher. */
4338 match_mapped_int_operand (struct mips_arg_info *arg,
4339 const struct mips_operand *operand_base)
4341 const struct mips_mapped_int_operand *operand;
4342 unsigned int uval, num_vals;
4345 operand = (const struct mips_mapped_int_operand *) operand_base;
4346 if (!match_const_int (arg, &sval, operand->int_map[0]))
4349 num_vals = 1 << operand_base->size;
4350 for (uval = 0; uval < num_vals; uval++)
4351 if (operand->int_map[uval] == sval)
4353 if (uval == num_vals)
4356 insn_insert_operand (arg->insn, operand_base, uval);
4360 /* OP_MSB matcher. */
4363 match_msb_operand (struct mips_arg_info *arg,
4364 const struct mips_operand *operand_base)
4366 const struct mips_msb_operand *operand;
4367 int min_val, max_val, max_high;
4368 offsetT size, sval, high;
4370 operand = (const struct mips_msb_operand *) operand_base;
4371 min_val = operand->bias;
4372 max_val = min_val + (1 << operand_base->size) - 1;
4373 max_high = operand->opsize;
4375 if (!match_const_int (arg, &size, 1))
4378 high = size + arg->last_op_int;
4379 sval = operand->add_lsb ? high : size;
4381 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4383 if (arg->soft_match)
4385 report_bad_field (arg->last_op_int, size);
4388 insn_insert_operand (arg->insn, operand_base, sval - min_val);
4392 /* OP_REG matcher. */
4395 match_reg_operand (struct mips_arg_info *arg,
4396 const struct mips_operand *operand_base)
4398 const struct mips_reg_operand *operand;
4399 unsigned int regno, uval, num_vals;
4401 operand = (const struct mips_reg_operand *) operand_base;
4402 if (!match_reg (arg, operand->reg_type, ®no))
4405 if (operand->reg_map)
4407 num_vals = 1 << operand->root.size;
4408 for (uval = 0; uval < num_vals; uval++)
4409 if (operand->reg_map[uval] == regno)
4411 if (num_vals == uval)
4417 arg->last_regno = regno;
4418 if (arg->opnum == 1)
4419 arg->dest_regno = regno;
4420 insn_insert_operand (arg->insn, operand_base, uval);
4424 /* OP_REG_PAIR matcher. */
4427 match_reg_pair_operand (struct mips_arg_info *arg,
4428 const struct mips_operand *operand_base)
4430 const struct mips_reg_pair_operand *operand;
4431 unsigned int regno1, regno2, uval, num_vals;
4433 operand = (const struct mips_reg_pair_operand *) operand_base;
4434 if (!match_reg (arg, operand->reg_type, ®no1)
4435 || !match_char (arg, ',')
4436 || !match_reg (arg, operand->reg_type, ®no2))
4439 num_vals = 1 << operand_base->size;
4440 for (uval = 0; uval < num_vals; uval++)
4441 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4443 if (uval == num_vals)
4446 insn_insert_operand (arg->insn, operand_base, uval);
4450 /* OP_PCREL matcher. The caller chooses the relocation type. */
4453 match_pcrel_operand (struct mips_arg_info *arg)
4455 bfd_reloc_code_real_type r[3];
4457 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
4460 /* OP_PERF_REG matcher. */
4463 match_perf_reg_operand (struct mips_arg_info *arg,
4464 const struct mips_operand *operand)
4468 if (!match_const_int (arg, &sval, 0))
4473 || (mips_opts.arch == CPU_R5900
4474 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4475 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4477 if (arg->soft_match)
4479 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval);
4482 insn_insert_operand (arg->insn, operand, sval);
4486 /* OP_ADDIUSP matcher. */
4489 match_addiusp_operand (struct mips_arg_info *arg,
4490 const struct mips_operand *operand)
4495 if (!match_const_int (arg, &sval, -256))
4502 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
4505 uval = (unsigned int) sval;
4506 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4507 insn_insert_operand (arg->insn, operand, uval);
4511 /* OP_CLO_CLZ_DEST matcher. */
4514 match_clo_clz_dest_operand (struct mips_arg_info *arg,
4515 const struct mips_operand *operand)
4519 if (!match_reg (arg, OP_REG_GP, ®no))
4522 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
4526 /* OP_LWM_SWM_LIST matcher. */
4529 match_lwm_swm_list_operand (struct mips_arg_info *arg,
4530 const struct mips_operand *operand)
4532 unsigned int reglist, sregs, ra, regno1, regno2;
4533 struct mips_arg_info reset;
4536 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4540 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4545 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4548 while (match_char (arg, ',')
4549 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
4552 if (operand->size == 2)
4554 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4560 and any permutations of these. */
4561 if ((reglist & 0xfff1ffff) != 0x80010000)
4564 sregs = (reglist >> 17) & 7;
4569 /* The list must include at least one of ra and s0-sN,
4570 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4571 which are $23 and $30 respectively.) E.g.:
4579 and any permutations of these. */
4580 if ((reglist & 0x3f00ffff) != 0)
4583 ra = (reglist >> 27) & 0x10;
4584 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4587 if ((sregs & -sregs) != sregs)
4590 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
4594 /* OP_ENTRY_EXIT_LIST matcher. */
4597 match_entry_exit_operand (struct mips_arg_info *arg,
4598 const struct mips_operand *operand)
4601 bfd_boolean is_exit;
4603 /* The format is the same for both ENTRY and EXIT, but the constraints
4605 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4606 mask = (is_exit ? 7 << 3 : 0);
4609 unsigned int regno1, regno2;
4610 bfd_boolean is_freg;
4612 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4614 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
4619 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4622 mask |= (5 + regno2) << 3;
4624 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4625 mask |= (regno2 - 3) << 3;
4626 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4627 mask |= (regno2 - 15) << 1;
4628 else if (regno1 == RA && regno2 == RA)
4633 while (match_char (arg, ','));
4635 insn_insert_operand (arg->insn, operand, mask);
4639 /* OP_SAVE_RESTORE_LIST matcher. */
4642 match_save_restore_list_operand (struct mips_arg_info *arg)
4644 unsigned int opcode, args, statics, sregs;
4645 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
4650 opcode = arg->insn->insn_opcode;
4652 num_frame_sizes = 0;
4658 unsigned int regno1, regno2;
4660 if (arg->token->type == OT_INTEGER)
4662 /* Handle the frame size. */
4663 if (!match_const_int (arg, &frame_size, 0))
4665 num_frame_sizes += 1;
4669 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4672 while (regno1 <= regno2)
4674 if (regno1 >= 4 && regno1 <= 7)
4676 if (num_frame_sizes == 0)
4678 args |= 1 << (regno1 - 4);
4680 /* statics $a0-$a3 */
4681 statics |= 1 << (regno1 - 4);
4683 else if (regno1 >= 16 && regno1 <= 23)
4685 sregs |= 1 << (regno1 - 16);
4686 else if (regno1 == 30)
4689 else if (regno1 == 31)
4690 /* Add $ra to insn. */
4700 while (match_char (arg, ','));
4702 /* Encode args/statics combination. */
4705 else if (args == 0xf)
4706 /* All $a0-$a3 are args. */
4707 opcode |= MIPS16_ALL_ARGS << 16;
4708 else if (statics == 0xf)
4709 /* All $a0-$a3 are statics. */
4710 opcode |= MIPS16_ALL_STATICS << 16;
4713 /* Count arg registers. */
4723 /* Count static registers. */
4725 while (statics & 0x8)
4727 statics = (statics << 1) & 0xf;
4733 /* Encode args/statics. */
4734 opcode |= ((num_args << 2) | num_statics) << 16;
4737 /* Encode $s0/$s1. */
4738 if (sregs & (1 << 0)) /* $s0 */
4740 if (sregs & (1 << 1)) /* $s1 */
4744 /* Encode $s2-$s8. */
4753 opcode |= num_sregs << 24;
4755 /* Encode frame size. */
4756 if (num_frame_sizes == 0)
4757 error = _("Missing frame size");
4758 else if (num_frame_sizes > 1)
4759 error = _("Frame size specified twice");
4760 else if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
4761 error = _("Invalid frame size");
4762 else if (frame_size != 128 || (opcode >> 16) != 0)
4765 opcode |= (((frame_size & 0xf0) << 16)
4766 | (frame_size & 0x0f));
4771 if (arg->soft_match)
4773 as_bad ("%s", error);
4776 /* Finally build the instruction. */
4777 if ((opcode >> 16) != 0 || frame_size == 0)
4778 opcode |= MIPS16_EXTEND;
4779 arg->insn->insn_opcode = opcode;
4783 /* OP_MDMX_IMM_REG matcher. */
4786 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
4787 const struct mips_operand *operand)
4789 unsigned int regno, uval;
4791 const struct mips_opcode *opcode;
4793 /* The mips_opcode records whether this is an octobyte or quadhalf
4794 instruction. Start out with that bit in place. */
4795 opcode = arg->insn->insn_mo;
4796 uval = mips_extract_operand (operand, opcode->match);
4797 is_qh = (uval != 0);
4799 if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
4801 if ((opcode->membership & INSN_5400)
4802 && strcmp (opcode->name, "rzu.ob") == 0)
4804 if (arg->soft_match)
4806 as_bad (_("Operand %d of `%s' must be an immediate"),
4807 arg->argnum, opcode->name);
4810 /* Check whether this is a vector register or a broadcast of
4811 a single element. */
4812 if (arg->token->type == OT_REG_ELEMENT)
4814 if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
4817 if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
4819 if (arg->soft_match)
4821 as_bad (_("Invalid element selector"));
4824 uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
4828 /* A full vector. */
4829 if ((opcode->membership & INSN_5400)
4830 && (strcmp (opcode->name, "sll.ob") == 0
4831 || strcmp (opcode->name, "srl.ob") == 0))
4833 if (arg->soft_match)
4835 as_bad (_("Operand %d of `%s' must be scalar"),
4836 arg->argnum, opcode->name);
4839 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
4842 uval |= MDMX_FMTSEL_VEC_QH << 5;
4844 uval |= MDMX_FMTSEL_VEC_OB << 5;
4853 if (!match_const_int (arg, &sval, 0))
4855 if (sval < 0 || sval > 31)
4857 if (arg->soft_match)
4859 report_bad_range (arg->insn, arg->argnum, sval, 0, 31, FALSE);
4861 uval |= (sval & 31);
4863 uval |= MDMX_FMTSEL_IMM_QH << 5;
4865 uval |= MDMX_FMTSEL_IMM_OB << 5;
4867 insn_insert_operand (arg->insn, operand, uval);
4871 /* OP_PC matcher. */
4874 match_pc_operand (struct mips_arg_info *arg)
4876 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
4884 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
4885 register that we need to match. */
4888 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
4892 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
4895 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
4896 the length of the value in bytes (4 for float, 8 for double) and
4897 USING_GPRS says whether the destination is a GPR rather than an FPR.
4899 Return the constant in IMM and OFFSET as follows:
4901 - If the constant should be loaded via memory, set IMM to O_absent and
4902 OFFSET to the memory address.
4904 - Otherwise, if the constant should be loaded into two 32-bit registers,
4905 set IMM to the O_constant to load into the high register and OFFSET
4906 to the corresponding value for the low register.
4908 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
4910 These constants only appear as the last operand in an instruction,
4911 and every instruction that accepts them in any variant accepts them
4912 in all variants. This means we don't have to worry about backing out
4913 any changes if the instruction does not match. We just match
4914 unconditionally and report an error if the constant is invalid. */
4917 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
4918 expressionS *offset, int length, bfd_boolean using_gprs)
4923 const char *newname;
4924 unsigned char *data;
4926 /* Where the constant is placed is based on how the MIPS assembler
4929 length == 4 && using_gprs -- immediate value only
4930 length == 8 && using_gprs -- .rdata or immediate value
4931 length == 4 && !using_gprs -- .lit4 or immediate value
4932 length == 8 && !using_gprs -- .lit8 or immediate value
4934 The .lit4 and .lit8 sections are only used if permitted by the
4936 if (arg->token->type != OT_FLOAT)
4939 gas_assert (arg->token->u.flt.length == length);
4940 data = arg->token->u.flt.data;
4943 /* Handle 32-bit constants for which an immediate value is best. */
4946 || g_switch_value < 4
4947 || (data[0] == 0 && data[1] == 0)
4948 || (data[2] == 0 && data[3] == 0)))
4950 imm->X_op = O_constant;
4951 if (!target_big_endian)
4952 imm->X_add_number = bfd_getl32 (data);
4954 imm->X_add_number = bfd_getb32 (data);
4955 offset->X_op = O_absent;
4959 /* Handle 64-bit constants for which an immediate value is best. */
4961 && !mips_disable_float_construction
4962 /* Constants can only be constructed in GPRs and copied
4963 to FPRs if the GPRs are at least as wide as the FPRs.
4964 Force the constant into memory if we are using 64-bit FPRs
4965 but the GPRs are only 32 bits wide. */
4966 /* ??? No longer true with the addition of MTHC1, but this
4967 is legacy code... */
4968 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
4969 && ((data[0] == 0 && data[1] == 0)
4970 || (data[2] == 0 && data[3] == 0))
4971 && ((data[4] == 0 && data[5] == 0)
4972 || (data[6] == 0 && data[7] == 0)))
4974 /* The value is simple enough to load with a couple of instructions.
4975 If using 32-bit registers, set IMM to the high order 32 bits and
4976 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
4978 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
4980 imm->X_op = O_constant;
4981 offset->X_op = O_constant;
4982 if (!target_big_endian)
4984 imm->X_add_number = bfd_getl32 (data + 4);
4985 offset->X_add_number = bfd_getl32 (data);
4989 imm->X_add_number = bfd_getb32 (data);
4990 offset->X_add_number = bfd_getb32 (data + 4);
4992 if (offset->X_add_number == 0)
4993 offset->X_op = O_absent;
4997 imm->X_op = O_constant;
4998 if (!target_big_endian)
4999 imm->X_add_number = bfd_getl64 (data);
5001 imm->X_add_number = bfd_getb64 (data);
5002 offset->X_op = O_absent;
5007 /* Switch to the right section. */
5009 subseg = now_subseg;
5012 gas_assert (!using_gprs && g_switch_value >= 4);
5017 if (using_gprs || g_switch_value < 8)
5018 newname = RDATA_SECTION_NAME;
5023 new_seg = subseg_new (newname, (subsegT) 0);
5024 bfd_set_section_flags (stdoutput, new_seg,
5025 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5026 frag_align (length == 4 ? 2 : 3, 0, 0);
5027 if (strncmp (TARGET_OS, "elf", 3) != 0)
5028 record_alignment (new_seg, 4);
5030 record_alignment (new_seg, length == 4 ? 2 : 3);
5032 as_bad (_("Can't use floating point insn in this section"));
5034 /* Set the argument to the current address in the section. */
5035 imm->X_op = O_absent;
5036 offset->X_op = O_symbol;
5037 offset->X_add_symbol = symbol_temp_new_now ();
5038 offset->X_add_number = 0;
5040 /* Put the floating point number into the section. */
5041 p = frag_more (length);
5042 memcpy (p, data, length);
5044 /* Switch back to the original section. */
5045 subseg_set (seg, subseg);
5049 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5050 of the argument text if the match is successful, otherwise return null. */
5053 match_operand (struct mips_arg_info *arg,
5054 const struct mips_operand *operand)
5056 switch (operand->type)
5059 return match_int_operand (arg, operand);
5062 return match_mapped_int_operand (arg, operand);
5065 return match_msb_operand (arg, operand);
5068 return match_reg_operand (arg, operand);
5071 return match_reg_pair_operand (arg, operand);
5074 return match_pcrel_operand (arg);
5077 return match_perf_reg_operand (arg, operand);
5079 case OP_ADDIUSP_INT:
5080 return match_addiusp_operand (arg, operand);
5082 case OP_CLO_CLZ_DEST:
5083 return match_clo_clz_dest_operand (arg, operand);
5085 case OP_LWM_SWM_LIST:
5086 return match_lwm_swm_list_operand (arg, operand);
5088 case OP_ENTRY_EXIT_LIST:
5089 return match_entry_exit_operand (arg, operand);
5091 case OP_SAVE_RESTORE_LIST:
5092 return match_save_restore_list_operand (arg);
5094 case OP_MDMX_IMM_REG:
5095 return match_mdmx_imm_reg_operand (arg, operand);
5097 case OP_REPEAT_DEST_REG:
5098 return match_tied_reg_operand (arg, arg->dest_regno);
5100 case OP_REPEAT_PREV_REG:
5101 return match_tied_reg_operand (arg, arg->last_regno);
5104 return match_pc_operand (arg);
5109 /* ARG is the state after successfully matching an instruction.
5110 Issue any queued-up warnings. */
5113 check_completed_insn (struct mips_arg_info *arg)
5118 as_warn (_("Used $at without \".set noat\""));
5120 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
5124 /* Return true if modifying general-purpose register REG needs a delay. */
5127 reg_needs_delay (unsigned int reg)
5129 unsigned long prev_pinfo;
5131 prev_pinfo = history[0].insn_mo->pinfo;
5132 if (!mips_opts.noreorder
5133 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5134 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5135 && (gpr_write_mask (&history[0]) & (1 << reg)))
5141 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5142 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5143 by VR4120 errata. */
5146 classify_vr4120_insn (const char *name)
5148 if (strncmp (name, "macc", 4) == 0)
5149 return FIX_VR4120_MACC;
5150 if (strncmp (name, "dmacc", 5) == 0)
5151 return FIX_VR4120_DMACC;
5152 if (strncmp (name, "mult", 4) == 0)
5153 return FIX_VR4120_MULT;
5154 if (strncmp (name, "dmult", 5) == 0)
5155 return FIX_VR4120_DMULT;
5156 if (strstr (name, "div"))
5157 return FIX_VR4120_DIV;
5158 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5159 return FIX_VR4120_MTHILO;
5160 return NUM_FIX_VR4120_CLASSES;
5163 #define INSN_ERET 0x42000018
5164 #define INSN_DERET 0x4200001f
5166 /* Return the number of instructions that must separate INSN1 and INSN2,
5167 where INSN1 is the earlier instruction. Return the worst-case value
5168 for any INSN2 if INSN2 is null. */
5171 insns_between (const struct mips_cl_insn *insn1,
5172 const struct mips_cl_insn *insn2)
5174 unsigned long pinfo1, pinfo2;
5177 /* If INFO2 is null, pessimistically assume that all flags are set for
5178 the second instruction. */
5179 pinfo1 = insn1->insn_mo->pinfo;
5180 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
5182 /* For most targets, write-after-read dependencies on the HI and LO
5183 registers must be separated by at least two instructions. */
5184 if (!hilo_interlocks)
5186 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5188 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5192 /* If we're working around r7000 errata, there must be two instructions
5193 between an mfhi or mflo and any instruction that uses the result. */
5194 if (mips_7000_hilo_fix
5195 && !mips_opts.micromips
5196 && MF_HILO_INSN (pinfo1)
5197 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
5200 /* If we're working around 24K errata, one instruction is required
5201 if an ERET or DERET is followed by a branch instruction. */
5202 if (mips_fix_24k && !mips_opts.micromips)
5204 if (insn1->insn_opcode == INSN_ERET
5205 || insn1->insn_opcode == INSN_DERET)
5208 || insn2->insn_opcode == INSN_ERET
5209 || insn2->insn_opcode == INSN_DERET
5210 || delayed_branch_p (insn2))
5215 /* If working around VR4120 errata, check for combinations that need
5216 a single intervening instruction. */
5217 if (mips_fix_vr4120 && !mips_opts.micromips)
5219 unsigned int class1, class2;
5221 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5222 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
5226 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5227 if (vr4120_conflicts[class1] & (1 << class2))
5232 if (!HAVE_CODE_COMPRESSION)
5234 /* Check for GPR or coprocessor load delays. All such delays
5235 are on the RT register. */
5236 /* Itbl support may require additional care here. */
5237 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5238 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
5240 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
5244 /* Check for generic coprocessor hazards.
5246 This case is not handled very well. There is no special
5247 knowledge of CP0 handling, and the coprocessors other than
5248 the floating point unit are not distinguished at all. */
5249 /* Itbl support may require additional care here. FIXME!
5250 Need to modify this to include knowledge about
5251 user specified delays! */
5252 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5253 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5255 /* Handle cases where INSN1 writes to a known general coprocessor
5256 register. There must be a one instruction delay before INSN2
5257 if INSN2 reads that register, otherwise no delay is needed. */
5258 mask = fpr_write_mask (insn1);
5261 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
5266 /* Read-after-write dependencies on the control registers
5267 require a two-instruction gap. */
5268 if ((pinfo1 & INSN_WRITE_COND_CODE)
5269 && (pinfo2 & INSN_READ_COND_CODE))
5272 /* We don't know exactly what INSN1 does. If INSN2 is
5273 also a coprocessor instruction, assume there must be
5274 a one instruction gap. */
5275 if (pinfo2 & INSN_COP)
5280 /* Check for read-after-write dependencies on the coprocessor
5281 control registers in cases where INSN1 does not need a general
5282 coprocessor delay. This means that INSN1 is a floating point
5283 comparison instruction. */
5284 /* Itbl support may require additional care here. */
5285 else if (!cop_interlocks
5286 && (pinfo1 & INSN_WRITE_COND_CODE)
5287 && (pinfo2 & INSN_READ_COND_CODE))
5294 /* Return the number of nops that would be needed to work around the
5295 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5296 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5297 that are contained within the first IGNORE instructions of HIST. */
5300 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
5301 const struct mips_cl_insn *insn)
5306 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5307 are not affected by the errata. */
5309 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5310 || strcmp (insn->insn_mo->name, "mtlo") == 0
5311 || strcmp (insn->insn_mo->name, "mthi") == 0))
5314 /* Search for the first MFLO or MFHI. */
5315 for (i = 0; i < MAX_VR4130_NOPS; i++)
5316 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
5318 /* Extract the destination register. */
5319 mask = gpr_write_mask (&hist[i]);
5321 /* No nops are needed if INSN reads that register. */
5322 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
5325 /* ...or if any of the intervening instructions do. */
5326 for (j = 0; j < i; j++)
5327 if (gpr_read_mask (&hist[j]) & mask)
5331 return MAX_VR4130_NOPS - i;
5336 #define BASE_REG_EQ(INSN1, INSN2) \
5337 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5338 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5340 /* Return the minimum alignment for this store instruction. */
5343 fix_24k_align_to (const struct mips_opcode *mo)
5345 if (strcmp (mo->name, "sh") == 0)
5348 if (strcmp (mo->name, "swc1") == 0
5349 || strcmp (mo->name, "swc2") == 0
5350 || strcmp (mo->name, "sw") == 0
5351 || strcmp (mo->name, "sc") == 0
5352 || strcmp (mo->name, "s.s") == 0)
5355 if (strcmp (mo->name, "sdc1") == 0
5356 || strcmp (mo->name, "sdc2") == 0
5357 || strcmp (mo->name, "s.d") == 0)
5364 struct fix_24k_store_info
5366 /* Immediate offset, if any, for this store instruction. */
5368 /* Alignment required by this store instruction. */
5370 /* True for register offsets. */
5371 int register_offset;
5374 /* Comparison function used by qsort. */
5377 fix_24k_sort (const void *a, const void *b)
5379 const struct fix_24k_store_info *pos1 = a;
5380 const struct fix_24k_store_info *pos2 = b;
5382 return (pos1->off - pos2->off);
5385 /* INSN is a store instruction. Try to record the store information
5386 in STINFO. Return false if the information isn't known. */
5389 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
5390 const struct mips_cl_insn *insn)
5392 /* The instruction must have a known offset. */
5393 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5396 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5397 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5401 /* Return the number of nops that would be needed to work around the 24k
5402 "lost data on stores during refill" errata if instruction INSN
5403 immediately followed the 2 instructions described by HIST.
5404 Ignore hazards that are contained within the first IGNORE
5405 instructions of HIST.
5407 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5408 for the data cache refills and store data. The following describes
5409 the scenario where the store data could be lost.
5411 * A data cache miss, due to either a load or a store, causing fill
5412 data to be supplied by the memory subsystem
5413 * The first three doublewords of fill data are returned and written
5415 * A sequence of four stores occurs in consecutive cycles around the
5416 final doubleword of the fill:
5420 * Zero, One or more instructions
5423 The four stores A-D must be to different doublewords of the line that
5424 is being filled. The fourth instruction in the sequence above permits
5425 the fill of the final doubleword to be transferred from the FSB into
5426 the cache. In the sequence above, the stores may be either integer
5427 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5428 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5429 different doublewords on the line. If the floating point unit is
5430 running in 1:2 mode, it is not possible to create the sequence above
5431 using only floating point store instructions.
5433 In this case, the cache line being filled is incorrectly marked
5434 invalid, thereby losing the data from any store to the line that
5435 occurs between the original miss and the completion of the five
5436 cycle sequence shown above.
5438 The workarounds are:
5440 * Run the data cache in write-through mode.
5441 * Insert a non-store instruction between
5442 Store A and Store B or Store B and Store C. */
5445 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
5446 const struct mips_cl_insn *insn)
5448 struct fix_24k_store_info pos[3];
5449 int align, i, base_offset;
5454 /* If the previous instruction wasn't a store, there's nothing to
5456 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5459 /* If the instructions after the previous one are unknown, we have
5460 to assume the worst. */
5464 /* Check whether we are dealing with three consecutive stores. */
5465 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5466 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5469 /* If we don't know the relationship between the store addresses,
5470 assume the worst. */
5471 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
5472 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5475 if (!fix_24k_record_store_info (&pos[0], insn)
5476 || !fix_24k_record_store_info (&pos[1], &hist[0])
5477 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5480 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5482 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5483 X bytes and such that the base register + X is known to be aligned
5486 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5490 align = pos[0].align_to;
5491 base_offset = pos[0].off;
5492 for (i = 1; i < 3; i++)
5493 if (align < pos[i].align_to)
5495 align = pos[i].align_to;
5496 base_offset = pos[i].off;
5498 for (i = 0; i < 3; i++)
5499 pos[i].off -= base_offset;
5502 pos[0].off &= ~align + 1;
5503 pos[1].off &= ~align + 1;
5504 pos[2].off &= ~align + 1;
5506 /* If any two stores write to the same chunk, they also write to the
5507 same doubleword. The offsets are still sorted at this point. */
5508 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5511 /* A range of at least 9 bytes is needed for the stores to be in
5512 non-overlapping doublewords. */
5513 if (pos[2].off - pos[0].off <= 8)
5516 if (pos[2].off - pos[1].off >= 24
5517 || pos[1].off - pos[0].off >= 24
5518 || pos[2].off - pos[0].off >= 32)
5524 /* Return the number of nops that would be needed if instruction INSN
5525 immediately followed the MAX_NOPS instructions given by HIST,
5526 where HIST[0] is the most recent instruction. Ignore hazards
5527 between INSN and the first IGNORE instructions in HIST.
5529 If INSN is null, return the worse-case number of nops for any
5533 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
5534 const struct mips_cl_insn *insn)
5536 int i, nops, tmp_nops;
5539 for (i = ignore; i < MAX_DELAY_NOPS; i++)
5541 tmp_nops = insns_between (hist + i, insn) - i;
5542 if (tmp_nops > nops)
5546 if (mips_fix_vr4130 && !mips_opts.micromips)
5548 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
5549 if (tmp_nops > nops)
5553 if (mips_fix_24k && !mips_opts.micromips)
5555 tmp_nops = nops_for_24k (ignore, hist, insn);
5556 if (tmp_nops > nops)
5563 /* The variable arguments provide NUM_INSNS extra instructions that
5564 might be added to HIST. Return the largest number of nops that
5565 would be needed after the extended sequence, ignoring hazards
5566 in the first IGNORE instructions. */
5569 nops_for_sequence (int num_insns, int ignore,
5570 const struct mips_cl_insn *hist, ...)
5573 struct mips_cl_insn buffer[MAX_NOPS];
5574 struct mips_cl_insn *cursor;
5577 va_start (args, hist);
5578 cursor = buffer + num_insns;
5579 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
5580 while (cursor > buffer)
5581 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5583 nops = nops_for_insn (ignore, buffer, NULL);
5588 /* Like nops_for_insn, but if INSN is a branch, take into account the
5589 worst-case delay for the branch target. */
5592 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
5593 const struct mips_cl_insn *insn)
5597 nops = nops_for_insn (ignore, hist, insn);
5598 if (delayed_branch_p (insn))
5600 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
5601 hist, insn, get_delay_slot_nop (insn));
5602 if (tmp_nops > nops)
5605 else if (compact_branch_p (insn))
5607 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
5608 if (tmp_nops > nops)
5614 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5617 fix_loongson2f_nop (struct mips_cl_insn * ip)
5619 gas_assert (!HAVE_CODE_COMPRESSION);
5620 if (strcmp (ip->insn_mo->name, "nop") == 0)
5621 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5624 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5625 jr target pc &= 'hffff_ffff_cfff_ffff. */
5628 fix_loongson2f_jump (struct mips_cl_insn * ip)
5630 gas_assert (!HAVE_CODE_COMPRESSION);
5631 if (strcmp (ip->insn_mo->name, "j") == 0
5632 || strcmp (ip->insn_mo->name, "jr") == 0
5633 || strcmp (ip->insn_mo->name, "jalr") == 0)
5641 sreg = EXTRACT_OPERAND (0, RS, *ip);
5642 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
5645 ep.X_op = O_constant;
5646 ep.X_add_number = 0xcfff0000;
5647 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
5648 ep.X_add_number = 0xffff;
5649 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
5650 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
5655 fix_loongson2f (struct mips_cl_insn * ip)
5657 if (mips_fix_loongson2f_nop)
5658 fix_loongson2f_nop (ip);
5660 if (mips_fix_loongson2f_jump)
5661 fix_loongson2f_jump (ip);
5664 /* IP is a branch that has a delay slot, and we need to fill it
5665 automatically. Return true if we can do that by swapping IP
5666 with the previous instruction.
5667 ADDRESS_EXPR is an operand of the instruction to be used with
5671 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
5672 bfd_reloc_code_real_type *reloc_type)
5674 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
5675 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
5677 /* -O2 and above is required for this optimization. */
5678 if (mips_optimize < 2)
5681 /* If we have seen .set volatile or .set nomove, don't optimize. */
5682 if (mips_opts.nomove)
5685 /* We can't swap if the previous instruction's position is fixed. */
5686 if (history[0].fixed_p)
5689 /* If the previous previous insn was in a .set noreorder, we can't
5690 swap. Actually, the MIPS assembler will swap in this situation.
5691 However, gcc configured -with-gnu-as will generate code like
5699 in which we can not swap the bne and INSN. If gcc is not configured
5700 -with-gnu-as, it does not output the .set pseudo-ops. */
5701 if (history[1].noreorder_p)
5704 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5705 This means that the previous instruction was a 4-byte one anyhow. */
5706 if (mips_opts.mips16 && history[0].fixp[0])
5709 /* If the branch is itself the target of a branch, we can not swap.
5710 We cheat on this; all we check for is whether there is a label on
5711 this instruction. If there are any branches to anything other than
5712 a label, users must use .set noreorder. */
5713 if (seg_info (now_seg)->label_list)
5716 /* If the previous instruction is in a variant frag other than this
5717 branch's one, we cannot do the swap. This does not apply to
5718 MIPS16 code, which uses variant frags for different purposes. */
5719 if (!mips_opts.mips16
5721 && history[0].frag->fr_type == rs_machine_dependent)
5724 /* We do not swap with instructions that cannot architecturally
5725 be placed in a branch delay slot, such as SYNC or ERET. We
5726 also refrain from swapping with a trap instruction, since it
5727 complicates trap handlers to have the trap instruction be in
5729 prev_pinfo = history[0].insn_mo->pinfo;
5730 if (prev_pinfo & INSN_NO_DELAY_SLOT)
5733 /* Check for conflicts between the branch and the instructions
5734 before the candidate delay slot. */
5735 if (nops_for_insn (0, history + 1, ip) > 0)
5738 /* Check for conflicts between the swapped sequence and the
5739 target of the branch. */
5740 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
5743 /* If the branch reads a register that the previous
5744 instruction sets, we can not swap. */
5745 gpr_read = gpr_read_mask (ip);
5746 prev_gpr_write = gpr_write_mask (&history[0]);
5747 if (gpr_read & prev_gpr_write)
5750 /* If the branch writes a register that the previous
5751 instruction sets, we can not swap. */
5752 gpr_write = gpr_write_mask (ip);
5753 if (gpr_write & prev_gpr_write)
5756 /* If the branch writes a register that the previous
5757 instruction reads, we can not swap. */
5758 prev_gpr_read = gpr_read_mask (&history[0]);
5759 if (gpr_write & prev_gpr_read)
5762 /* If one instruction sets a condition code and the
5763 other one uses a condition code, we can not swap. */
5764 pinfo = ip->insn_mo->pinfo;
5765 if ((pinfo & INSN_READ_COND_CODE)
5766 && (prev_pinfo & INSN_WRITE_COND_CODE))
5768 if ((pinfo & INSN_WRITE_COND_CODE)
5769 && (prev_pinfo & INSN_READ_COND_CODE))
5772 /* If the previous instruction uses the PC, we can not swap. */
5773 prev_pinfo2 = history[0].insn_mo->pinfo2;
5774 if (prev_pinfo2 & INSN2_READ_PC)
5777 /* If the previous instruction has an incorrect size for a fixed
5778 branch delay slot in microMIPS mode, we cannot swap. */
5779 pinfo2 = ip->insn_mo->pinfo2;
5780 if (mips_opts.micromips
5781 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
5782 && insn_length (history) != 2)
5784 if (mips_opts.micromips
5785 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
5786 && insn_length (history) != 4)
5789 /* On R5900 short loops need to be fixed by inserting a nop in
5790 the branch delay slots.
5791 A short loop can be terminated too early. */
5792 if (mips_opts.arch == CPU_R5900
5793 /* Check if instruction has a parameter, ignore "j $31". */
5794 && (address_expr != NULL)
5795 /* Parameter must be 16 bit. */
5796 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
5797 /* Branch to same segment. */
5798 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
5799 /* Branch to same code fragment. */
5800 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
5801 /* Can only calculate branch offset if value is known. */
5802 && symbol_constant_p(address_expr->X_add_symbol)
5803 /* Check if branch is really conditional. */
5804 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
5805 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
5806 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
5809 /* Check if loop is shorter than 6 instructions including
5810 branch and delay slot. */
5811 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
5818 /* When the loop includes branches or jumps,
5819 it is not a short loop. */
5820 for (i = 0; i < (distance / 4); i++)
5822 if ((history[i].cleared_p)
5823 || delayed_branch_p(&history[i]))
5831 /* Insert nop after branch to fix short loop. */
5840 /* Decide how we should add IP to the instruction stream.
5841 ADDRESS_EXPR is an operand of the instruction to be used with
5844 static enum append_method
5845 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
5846 bfd_reloc_code_real_type *reloc_type)
5848 /* The relaxed version of a macro sequence must be inherently
5850 if (mips_relax.sequence == 2)
5853 /* We must not dabble with instructions in a ".set norerorder" block. */
5854 if (mips_opts.noreorder)
5857 /* Otherwise, it's our responsibility to fill branch delay slots. */
5858 if (delayed_branch_p (ip))
5860 if (!branch_likely_p (ip)
5861 && can_swap_branch_p (ip, address_expr, reloc_type))
5864 if (mips_opts.mips16
5865 && ISA_SUPPORTS_MIPS16E
5866 && gpr_read_mask (ip) != 0)
5867 return APPEND_ADD_COMPACT;
5869 return APPEND_ADD_WITH_NOP;
5875 /* IP is a MIPS16 instruction whose opcode we have just changed.
5876 Point IP->insn_mo to the new opcode's definition. */
5879 find_altered_mips16_opcode (struct mips_cl_insn *ip)
5881 const struct mips_opcode *mo, *end;
5883 end = &mips16_opcodes[bfd_mips16_num_opcodes];
5884 for (mo = ip->insn_mo; mo < end; mo++)
5885 if ((ip->insn_opcode & mo->mask) == mo->match)
5893 /* For microMIPS macros, we need to generate a local number label
5894 as the target of branches. */
5895 #define MICROMIPS_LABEL_CHAR '\037'
5896 static unsigned long micromips_target_label;
5897 static char micromips_target_name[32];
5900 micromips_label_name (void)
5902 char *p = micromips_target_name;
5903 char symbol_name_temporary[24];
5911 l = micromips_target_label;
5912 #ifdef LOCAL_LABEL_PREFIX
5913 *p++ = LOCAL_LABEL_PREFIX;
5916 *p++ = MICROMIPS_LABEL_CHAR;
5919 symbol_name_temporary[i++] = l % 10 + '0';
5924 *p++ = symbol_name_temporary[--i];
5927 return micromips_target_name;
5931 micromips_label_expr (expressionS *label_expr)
5933 label_expr->X_op = O_symbol;
5934 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
5935 label_expr->X_add_number = 0;
5939 micromips_label_inc (void)
5941 micromips_target_label++;
5942 *micromips_target_name = '\0';
5946 micromips_add_label (void)
5950 s = colon (micromips_label_name ());
5951 micromips_label_inc ();
5952 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
5955 /* If assembling microMIPS code, then return the microMIPS reloc
5956 corresponding to the requested one if any. Otherwise return
5957 the reloc unchanged. */
5959 static bfd_reloc_code_real_type
5960 micromips_map_reloc (bfd_reloc_code_real_type reloc)
5962 static const bfd_reloc_code_real_type relocs[][2] =
5964 /* Keep sorted incrementally by the left-hand key. */
5965 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
5966 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
5967 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
5968 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
5969 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
5970 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
5971 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
5972 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
5973 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
5974 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
5975 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
5976 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
5977 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
5978 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
5979 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
5980 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
5981 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
5982 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
5983 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
5984 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
5985 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
5986 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
5987 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
5988 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
5989 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
5990 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
5991 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
5993 bfd_reloc_code_real_type r;
5996 if (!mips_opts.micromips)
5998 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6004 return relocs[i][1];
6009 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6010 Return true on success, storing the resolved value in RESULT. */
6013 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6018 case BFD_RELOC_MIPS_HIGHEST:
6019 case BFD_RELOC_MICROMIPS_HIGHEST:
6020 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6023 case BFD_RELOC_MIPS_HIGHER:
6024 case BFD_RELOC_MICROMIPS_HIGHER:
6025 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6028 case BFD_RELOC_HI16_S:
6029 case BFD_RELOC_MICROMIPS_HI16_S:
6030 case BFD_RELOC_MIPS16_HI16_S:
6031 *result = ((operand + 0x8000) >> 16) & 0xffff;
6034 case BFD_RELOC_HI16:
6035 case BFD_RELOC_MICROMIPS_HI16:
6036 case BFD_RELOC_MIPS16_HI16:
6037 *result = (operand >> 16) & 0xffff;
6040 case BFD_RELOC_LO16:
6041 case BFD_RELOC_MICROMIPS_LO16:
6042 case BFD_RELOC_MIPS16_LO16:
6043 *result = operand & 0xffff;
6046 case BFD_RELOC_UNUSED:
6055 /* Output an instruction. IP is the instruction information.
6056 ADDRESS_EXPR is an operand of the instruction to be used with
6057 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6058 a macro expansion. */
6061 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
6062 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
6064 unsigned long prev_pinfo2, pinfo;
6065 bfd_boolean relaxed_branch = FALSE;
6066 enum append_method method;
6067 bfd_boolean relax32;
6070 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
6071 fix_loongson2f (ip);
6073 file_ase_mips16 |= mips_opts.mips16;
6074 file_ase_micromips |= mips_opts.micromips;
6076 prev_pinfo2 = history[0].insn_mo->pinfo2;
6077 pinfo = ip->insn_mo->pinfo;
6079 if (mips_opts.micromips
6081 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6082 && micromips_insn_length (ip->insn_mo) != 2)
6083 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6084 && micromips_insn_length (ip->insn_mo) != 4)))
6085 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6086 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
6088 if (address_expr == NULL)
6090 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6091 && reloc_type[1] == BFD_RELOC_UNUSED
6092 && reloc_type[2] == BFD_RELOC_UNUSED
6093 && address_expr->X_op == O_constant)
6095 switch (*reloc_type)
6097 case BFD_RELOC_MIPS_JMP:
6101 shift = mips_opts.micromips ? 1 : 2;
6102 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6103 as_bad (_("jump to misaligned address (0x%lx)"),
6104 (unsigned long) address_expr->X_add_number);
6105 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6111 case BFD_RELOC_MIPS16_JMP:
6112 if ((address_expr->X_add_number & 3) != 0)
6113 as_bad (_("jump to misaligned address (0x%lx)"),
6114 (unsigned long) address_expr->X_add_number);
6116 (((address_expr->X_add_number & 0x7c0000) << 3)
6117 | ((address_expr->X_add_number & 0xf800000) >> 7)
6118 | ((address_expr->X_add_number & 0x3fffc) >> 2));
6122 case BFD_RELOC_16_PCREL_S2:
6126 shift = mips_opts.micromips ? 1 : 2;
6127 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6128 as_bad (_("branch to misaligned address (0x%lx)"),
6129 (unsigned long) address_expr->X_add_number);
6130 if (!mips_relax_branch)
6132 if ((address_expr->X_add_number + (1 << (shift + 15)))
6133 & ~((1 << (shift + 16)) - 1))
6134 as_bad (_("branch address range overflow (0x%lx)"),
6135 (unsigned long) address_expr->X_add_number);
6136 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6146 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6149 ip->insn_opcode |= value & 0xffff;
6157 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6159 /* There are a lot of optimizations we could do that we don't.
6160 In particular, we do not, in general, reorder instructions.
6161 If you use gcc with optimization, it will reorder
6162 instructions and generally do much more optimization then we
6163 do here; repeating all that work in the assembler would only
6164 benefit hand written assembly code, and does not seem worth
6166 int nops = (mips_optimize == 0
6167 ? nops_for_insn (0, history, NULL)
6168 : nops_for_insn_or_target (0, history, ip));
6172 unsigned long old_frag_offset;
6175 old_frag = frag_now;
6176 old_frag_offset = frag_now_fix ();
6178 for (i = 0; i < nops; i++)
6179 add_fixed_insn (NOP_INSN);
6180 insert_into_history (0, nops, NOP_INSN);
6184 listing_prev_line ();
6185 /* We may be at the start of a variant frag. In case we
6186 are, make sure there is enough space for the frag
6187 after the frags created by listing_prev_line. The
6188 argument to frag_grow here must be at least as large
6189 as the argument to all other calls to frag_grow in
6190 this file. We don't have to worry about being in the
6191 middle of a variant frag, because the variants insert
6192 all needed nop instructions themselves. */
6196 mips_move_text_labels ();
6198 #ifndef NO_ECOFF_DEBUGGING
6199 if (ECOFF_DEBUGGING)
6200 ecoff_fix_loc (old_frag, old_frag_offset);
6204 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6208 /* Work out how many nops in prev_nop_frag are needed by IP,
6209 ignoring hazards generated by the first prev_nop_frag_since
6211 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
6212 gas_assert (nops <= prev_nop_frag_holds);
6214 /* Enforce NOPS as a minimum. */
6215 if (nops > prev_nop_frag_required)
6216 prev_nop_frag_required = nops;
6218 if (prev_nop_frag_holds == prev_nop_frag_required)
6220 /* Settle for the current number of nops. Update the history
6221 accordingly (for the benefit of any future .set reorder code). */
6222 prev_nop_frag = NULL;
6223 insert_into_history (prev_nop_frag_since,
6224 prev_nop_frag_holds, NOP_INSN);
6228 /* Allow this instruction to replace one of the nops that was
6229 tentatively added to prev_nop_frag. */
6230 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
6231 prev_nop_frag_holds--;
6232 prev_nop_frag_since++;
6236 method = get_append_method (ip, address_expr, reloc_type);
6237 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
6239 dwarf2_emit_insn (0);
6240 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6241 so "move" the instruction address accordingly.
6243 Also, it doesn't seem appropriate for the assembler to reorder .loc
6244 entries. If this instruction is a branch that we are going to swap
6245 with the previous instruction, the two instructions should be
6246 treated as a unit, and the debug information for both instructions
6247 should refer to the start of the branch sequence. Using the
6248 current position is certainly wrong when swapping a 32-bit branch
6249 and a 16-bit delay slot, since the current position would then be
6250 in the middle of a branch. */
6251 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
6253 relax32 = (mips_relax_branch
6254 /* Don't try branch relaxation within .set nomacro, or within
6255 .set noat if we use $at for PIC computations. If it turns
6256 out that the branch was out-of-range, we'll get an error. */
6257 && !mips_opts.warn_about_macros
6258 && (mips_opts.at || mips_pic == NO_PIC)
6259 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6260 as they have no complementing branches. */
6261 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
6263 if (!HAVE_CODE_COMPRESSION
6266 && *reloc_type == BFD_RELOC_16_PCREL_S2
6267 && delayed_branch_p (ip))
6269 relaxed_branch = TRUE;
6270 add_relaxed_insn (ip, (relaxed_branch_length
6272 uncond_branch_p (ip) ? -1
6273 : branch_likely_p (ip) ? 1
6277 uncond_branch_p (ip),
6278 branch_likely_p (ip),
6279 pinfo & INSN_WRITE_GPR_31,
6281 address_expr->X_add_symbol,
6282 address_expr->X_add_number);
6283 *reloc_type = BFD_RELOC_UNUSED;
6285 else if (mips_opts.micromips
6287 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6288 || *reloc_type > BFD_RELOC_UNUSED)
6289 && (delayed_branch_p (ip) || compact_branch_p (ip))
6290 /* Don't try branch relaxation when users specify
6291 16-bit/32-bit instructions. */
6292 && !forced_insn_length)
6294 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6295 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
6296 int uncond = uncond_branch_p (ip) ? -1 : 0;
6297 int compact = compact_branch_p (ip);
6298 int al = pinfo & INSN_WRITE_GPR_31;
6301 gas_assert (address_expr != NULL);
6302 gas_assert (!mips_relax.sequence);
6304 relaxed_branch = TRUE;
6305 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6306 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
6307 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6309 address_expr->X_add_symbol,
6310 address_expr->X_add_number);
6311 *reloc_type = BFD_RELOC_UNUSED;
6313 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
6315 /* We need to set up a variant frag. */
6316 gas_assert (address_expr != NULL);
6317 add_relaxed_insn (ip, 4, 0,
6319 (*reloc_type - BFD_RELOC_UNUSED,
6320 forced_insn_length == 2, forced_insn_length == 4,
6321 delayed_branch_p (&history[0]),
6322 history[0].mips16_absolute_jump_p),
6323 make_expr_symbol (address_expr), 0);
6325 else if (mips_opts.mips16 && insn_length (ip) == 2)
6327 if (!delayed_branch_p (ip))
6328 /* Make sure there is enough room to swap this instruction with
6329 a following jump instruction. */
6331 add_fixed_insn (ip);
6335 if (mips_opts.mips16
6336 && mips_opts.noreorder
6337 && delayed_branch_p (&history[0]))
6338 as_warn (_("extended instruction in delay slot"));
6340 if (mips_relax.sequence)
6342 /* If we've reached the end of this frag, turn it into a variant
6343 frag and record the information for the instructions we've
6345 if (frag_room () < 4)
6346 relax_close_frag ();
6347 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
6350 if (mips_relax.sequence != 2)
6352 if (mips_macro_warning.first_insn_sizes[0] == 0)
6353 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6354 mips_macro_warning.sizes[0] += insn_length (ip);
6355 mips_macro_warning.insns[0]++;
6357 if (mips_relax.sequence != 1)
6359 if (mips_macro_warning.first_insn_sizes[1] == 0)
6360 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6361 mips_macro_warning.sizes[1] += insn_length (ip);
6362 mips_macro_warning.insns[1]++;
6365 if (mips_opts.mips16)
6368 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6370 add_fixed_insn (ip);
6373 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
6375 bfd_reloc_code_real_type final_type[3];
6376 reloc_howto_type *howto0;
6377 reloc_howto_type *howto;
6380 /* Perform any necessary conversion to microMIPS relocations
6381 and find out how many relocations there actually are. */
6382 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6383 final_type[i] = micromips_map_reloc (reloc_type[i]);
6385 /* In a compound relocation, it is the final (outermost)
6386 operator that determines the relocated field. */
6387 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
6392 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
6393 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6394 bfd_get_reloc_size (howto),
6396 howto0 && howto0->pc_relative,
6399 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6400 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
6401 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6403 /* These relocations can have an addend that won't fit in
6404 4 octets for 64bit assembly. */
6406 && ! howto->partial_inplace
6407 && (reloc_type[0] == BFD_RELOC_16
6408 || reloc_type[0] == BFD_RELOC_32
6409 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6410 || reloc_type[0] == BFD_RELOC_GPREL16
6411 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6412 || reloc_type[0] == BFD_RELOC_GPREL32
6413 || reloc_type[0] == BFD_RELOC_64
6414 || reloc_type[0] == BFD_RELOC_CTOR
6415 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6416 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6417 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6418 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6419 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6420 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6421 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6422 || hi16_reloc_p (reloc_type[0])
6423 || lo16_reloc_p (reloc_type[0])))
6424 ip->fixp[0]->fx_no_overflow = 1;
6426 /* These relocations can have an addend that won't fit in 2 octets. */
6427 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6428 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6429 ip->fixp[0]->fx_no_overflow = 1;
6431 if (mips_relax.sequence)
6433 if (mips_relax.first_fixup == 0)
6434 mips_relax.first_fixup = ip->fixp[0];
6436 else if (reloc_needs_lo_p (*reloc_type))
6438 struct mips_hi_fixup *hi_fixup;
6440 /* Reuse the last entry if it already has a matching %lo. */
6441 hi_fixup = mips_hi_fixup_list;
6443 || !fixup_has_matching_lo_p (hi_fixup->fixp))
6445 hi_fixup = ((struct mips_hi_fixup *)
6446 xmalloc (sizeof (struct mips_hi_fixup)));
6447 hi_fixup->next = mips_hi_fixup_list;
6448 mips_hi_fixup_list = hi_fixup;
6450 hi_fixup->fixp = ip->fixp[0];
6451 hi_fixup->seg = now_seg;
6454 /* Add fixups for the second and third relocations, if given.
6455 Note that the ABI allows the second relocation to be
6456 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6457 moment we only use RSS_UNDEF, but we could add support
6458 for the others if it ever becomes necessary. */
6459 for (i = 1; i < 3; i++)
6460 if (reloc_type[i] != BFD_RELOC_UNUSED)
6462 ip->fixp[i] = fix_new (ip->frag, ip->where,
6463 ip->fixp[0]->fx_size, NULL, 0,
6464 FALSE, final_type[i]);
6466 /* Use fx_tcbit to mark compound relocs. */
6467 ip->fixp[0]->fx_tcbit = 1;
6468 ip->fixp[i]->fx_tcbit = 1;
6473 /* Update the register mask information. */
6474 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6475 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
6480 insert_into_history (0, 1, ip);
6483 case APPEND_ADD_WITH_NOP:
6485 struct mips_cl_insn *nop;
6487 insert_into_history (0, 1, ip);
6488 nop = get_delay_slot_nop (ip);
6489 add_fixed_insn (nop);
6490 insert_into_history (0, 1, nop);
6491 if (mips_relax.sequence)
6492 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6496 case APPEND_ADD_COMPACT:
6497 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6498 gas_assert (mips_opts.mips16);
6499 ip->insn_opcode |= 0x0080;
6500 find_altered_mips16_opcode (ip);
6502 insert_into_history (0, 1, ip);
6507 struct mips_cl_insn delay = history[0];
6508 if (mips_opts.mips16)
6510 know (delay.frag == ip->frag);
6511 move_insn (ip, delay.frag, delay.where);
6512 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6514 else if (relaxed_branch || delay.frag != ip->frag)
6516 /* Add the delay slot instruction to the end of the
6517 current frag and shrink the fixed part of the
6518 original frag. If the branch occupies the tail of
6519 the latter, move it backwards to cover the gap. */
6520 delay.frag->fr_fix -= branch_disp;
6521 if (delay.frag == ip->frag)
6522 move_insn (ip, ip->frag, ip->where - branch_disp);
6523 add_fixed_insn (&delay);
6527 move_insn (&delay, ip->frag,
6528 ip->where - branch_disp + insn_length (ip));
6529 move_insn (ip, history[0].frag, history[0].where);
6533 insert_into_history (0, 1, &delay);
6538 /* If we have just completed an unconditional branch, clear the history. */
6539 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6540 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
6544 mips_no_prev_insn ();
6546 for (i = 0; i < ARRAY_SIZE (history); i++)
6547 history[i].cleared_p = 1;
6550 /* We need to emit a label at the end of branch-likely macros. */
6551 if (emit_branch_likely_macro)
6553 emit_branch_likely_macro = FALSE;
6554 micromips_add_label ();
6557 /* We just output an insn, so the next one doesn't have a label. */
6558 mips_clear_insn_labels ();
6561 /* Forget that there was any previous instruction or label.
6562 When BRANCH is true, the branch history is also flushed. */
6565 mips_no_prev_insn (void)
6567 prev_nop_frag = NULL;
6568 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
6569 mips_clear_insn_labels ();
6572 /* This function must be called before we emit something other than
6573 instructions. It is like mips_no_prev_insn except that it inserts
6574 any NOPS that might be needed by previous instructions. */
6577 mips_emit_delays (void)
6579 if (! mips_opts.noreorder)
6581 int nops = nops_for_insn (0, history, NULL);
6585 add_fixed_insn (NOP_INSN);
6586 mips_move_text_labels ();
6589 mips_no_prev_insn ();
6592 /* Start a (possibly nested) noreorder block. */
6595 start_noreorder (void)
6597 if (mips_opts.noreorder == 0)
6602 /* None of the instructions before the .set noreorder can be moved. */
6603 for (i = 0; i < ARRAY_SIZE (history); i++)
6604 history[i].fixed_p = 1;
6606 /* Insert any nops that might be needed between the .set noreorder
6607 block and the previous instructions. We will later remove any
6608 nops that turn out not to be needed. */
6609 nops = nops_for_insn (0, history, NULL);
6612 if (mips_optimize != 0)
6614 /* Record the frag which holds the nop instructions, so
6615 that we can remove them if we don't need them. */
6616 frag_grow (nops * NOP_INSN_SIZE);
6617 prev_nop_frag = frag_now;
6618 prev_nop_frag_holds = nops;
6619 prev_nop_frag_required = 0;
6620 prev_nop_frag_since = 0;
6623 for (; nops > 0; --nops)
6624 add_fixed_insn (NOP_INSN);
6626 /* Move on to a new frag, so that it is safe to simply
6627 decrease the size of prev_nop_frag. */
6628 frag_wane (frag_now);
6630 mips_move_text_labels ();
6632 mips_mark_labels ();
6633 mips_clear_insn_labels ();
6635 mips_opts.noreorder++;
6636 mips_any_noreorder = 1;
6639 /* End a nested noreorder block. */
6642 end_noreorder (void)
6644 mips_opts.noreorder--;
6645 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
6647 /* Commit to inserting prev_nop_frag_required nops and go back to
6648 handling nop insertion the .set reorder way. */
6649 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
6651 insert_into_history (prev_nop_frag_since,
6652 prev_nop_frag_required, NOP_INSN);
6653 prev_nop_frag = NULL;
6657 /* Set up global variables for the start of a new macro. */
6662 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
6663 memset (&mips_macro_warning.first_insn_sizes, 0,
6664 sizeof (mips_macro_warning.first_insn_sizes));
6665 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
6666 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
6667 && delayed_branch_p (&history[0]));
6668 switch (history[0].insn_mo->pinfo2
6669 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
6671 case INSN2_BRANCH_DELAY_32BIT:
6672 mips_macro_warning.delay_slot_length = 4;
6674 case INSN2_BRANCH_DELAY_16BIT:
6675 mips_macro_warning.delay_slot_length = 2;
6678 mips_macro_warning.delay_slot_length = 0;
6681 mips_macro_warning.first_frag = NULL;
6684 /* Given that a macro is longer than one instruction or of the wrong size,
6685 return the appropriate warning for it. Return null if no warning is
6686 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6687 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6688 and RELAX_NOMACRO. */
6691 macro_warning (relax_substateT subtype)
6693 if (subtype & RELAX_DELAY_SLOT)
6694 return _("Macro instruction expanded into multiple instructions"
6695 " in a branch delay slot");
6696 else if (subtype & RELAX_NOMACRO)
6697 return _("Macro instruction expanded into multiple instructions");
6698 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
6699 | RELAX_DELAY_SLOT_SIZE_SECOND))
6700 return ((subtype & RELAX_DELAY_SLOT_16BIT)
6701 ? _("Macro instruction expanded into a wrong size instruction"
6702 " in a 16-bit branch delay slot")
6703 : _("Macro instruction expanded into a wrong size instruction"
6704 " in a 32-bit branch delay slot"));
6709 /* Finish up a macro. Emit warnings as appropriate. */
6714 /* Relaxation warning flags. */
6715 relax_substateT subtype = 0;
6717 /* Check delay slot size requirements. */
6718 if (mips_macro_warning.delay_slot_length == 2)
6719 subtype |= RELAX_DELAY_SLOT_16BIT;
6720 if (mips_macro_warning.delay_slot_length != 0)
6722 if (mips_macro_warning.delay_slot_length
6723 != mips_macro_warning.first_insn_sizes[0])
6724 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
6725 if (mips_macro_warning.delay_slot_length
6726 != mips_macro_warning.first_insn_sizes[1])
6727 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
6730 /* Check instruction count requirements. */
6731 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
6733 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
6734 subtype |= RELAX_SECOND_LONGER;
6735 if (mips_opts.warn_about_macros)
6736 subtype |= RELAX_NOMACRO;
6737 if (mips_macro_warning.delay_slot_p)
6738 subtype |= RELAX_DELAY_SLOT;
6741 /* If both alternatives fail to fill a delay slot correctly,
6742 emit the warning now. */
6743 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
6744 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
6749 s = subtype & (RELAX_DELAY_SLOT_16BIT
6750 | RELAX_DELAY_SLOT_SIZE_FIRST
6751 | RELAX_DELAY_SLOT_SIZE_SECOND);
6752 msg = macro_warning (s);
6754 as_warn ("%s", msg);
6758 /* If both implementations are longer than 1 instruction, then emit the
6760 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
6765 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
6766 msg = macro_warning (s);
6768 as_warn ("%s", msg);
6772 /* If any flags still set, then one implementation might need a warning
6773 and the other either will need one of a different kind or none at all.
6774 Pass any remaining flags over to relaxation. */
6775 if (mips_macro_warning.first_frag != NULL)
6776 mips_macro_warning.first_frag->fr_subtype |= subtype;
6779 /* Instruction operand formats used in macros that vary between
6780 standard MIPS and microMIPS code. */
6782 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
6783 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
6784 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
6785 static const char * const lui_fmt[2] = { "t,u", "s,u" };
6786 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
6787 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
6788 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
6789 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
6791 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
6792 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
6793 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
6794 #define LUI_FMT (lui_fmt[mips_opts.micromips])
6795 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
6796 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
6797 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
6798 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
6800 /* Read a macro's relocation codes from *ARGS and store them in *R.
6801 The first argument in *ARGS will be either the code for a single
6802 relocation or -1 followed by the three codes that make up a
6803 composite relocation. */
6806 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
6810 next = va_arg (*args, int);
6812 r[0] = (bfd_reloc_code_real_type) next;
6815 for (i = 0; i < 3; i++)
6816 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
6817 /* This function is only used for 16-bit relocation fields.
6818 To make the macro code simpler, treat an unrelocated value
6819 in the same way as BFD_RELOC_LO16. */
6820 if (r[0] == BFD_RELOC_UNUSED)
6821 r[0] = BFD_RELOC_LO16;
6825 /* Build an instruction created by a macro expansion. This is passed
6826 a pointer to the count of instructions created so far, an
6827 expression, the name of the instruction to build, an operand format
6828 string, and corresponding arguments. */
6831 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
6833 const struct mips_opcode *mo = NULL;
6834 bfd_reloc_code_real_type r[3];
6835 const struct mips_opcode *amo;
6836 const struct mips_operand *operand;
6837 struct hash_control *hash;
6838 struct mips_cl_insn insn;
6842 va_start (args, fmt);
6844 if (mips_opts.mips16)
6846 mips16_macro_build (ep, name, fmt, &args);
6851 r[0] = BFD_RELOC_UNUSED;
6852 r[1] = BFD_RELOC_UNUSED;
6853 r[2] = BFD_RELOC_UNUSED;
6854 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
6855 amo = (struct mips_opcode *) hash_find (hash, name);
6857 gas_assert (strcmp (name, amo->name) == 0);
6861 /* Search until we get a match for NAME. It is assumed here that
6862 macros will never generate MDMX, MIPS-3D, or MT instructions.
6863 We try to match an instruction that fulfils the branch delay
6864 slot instruction length requirement (if any) of the previous
6865 instruction. While doing this we record the first instruction
6866 seen that matches all the other conditions and use it anyway
6867 if the requirement cannot be met; we will issue an appropriate
6868 warning later on. */
6869 if (strcmp (fmt, amo->args) == 0
6870 && amo->pinfo != INSN_MACRO
6871 && is_opcode_valid (amo)
6872 && is_size_valid (amo))
6874 if (is_delay_slot_valid (amo))
6884 gas_assert (amo->name);
6886 while (strcmp (name, amo->name) == 0);
6889 create_insn (&insn, mo);
6902 macro_read_relocs (&args, r);
6903 gas_assert (*r == BFD_RELOC_GPREL16
6904 || *r == BFD_RELOC_MIPS_HIGHER
6905 || *r == BFD_RELOC_HI16_S
6906 || *r == BFD_RELOC_LO16
6907 || *r == BFD_RELOC_MIPS_GOT_OFST);
6911 macro_read_relocs (&args, r);
6915 macro_read_relocs (&args, r);
6916 gas_assert (ep != NULL
6917 && (ep->X_op == O_constant
6918 || (ep->X_op == O_symbol
6919 && (*r == BFD_RELOC_MIPS_HIGHEST
6920 || *r == BFD_RELOC_HI16_S
6921 || *r == BFD_RELOC_HI16
6922 || *r == BFD_RELOC_GPREL16
6923 || *r == BFD_RELOC_MIPS_GOT_HI16
6924 || *r == BFD_RELOC_MIPS_CALL_HI16))));
6928 gas_assert (ep != NULL);
6931 * This allows macro() to pass an immediate expression for
6932 * creating short branches without creating a symbol.
6934 * We don't allow branch relaxation for these branches, as
6935 * they should only appear in ".set nomacro" anyway.
6937 if (ep->X_op == O_constant)
6939 /* For microMIPS we always use relocations for branches.
6940 So we should not resolve immediate values. */
6941 gas_assert (!mips_opts.micromips);
6943 if ((ep->X_add_number & 3) != 0)
6944 as_bad (_("branch to misaligned address (0x%lx)"),
6945 (unsigned long) ep->X_add_number);
6946 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
6947 as_bad (_("branch address range overflow (0x%lx)"),
6948 (unsigned long) ep->X_add_number);
6949 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
6953 *r = BFD_RELOC_16_PCREL_S2;
6957 gas_assert (ep != NULL);
6958 *r = BFD_RELOC_MIPS_JMP;
6962 operand = (mips_opts.micromips
6963 ? decode_micromips_operand (fmt)
6964 : decode_mips_operand (fmt));
6968 uval = va_arg (args, int);
6969 if (operand->type == OP_CLO_CLZ_DEST)
6970 uval |= (uval << 5);
6971 insn_insert_operand (&insn, operand, uval);
6973 if (*fmt == '+' || *fmt == 'm')
6979 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
6981 append_insn (&insn, ep, r, TRUE);
6985 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
6988 struct mips_opcode *mo;
6989 struct mips_cl_insn insn;
6990 const struct mips_operand *operand;
6991 bfd_reloc_code_real_type r[3]
6992 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
6994 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
6996 gas_assert (strcmp (name, mo->name) == 0);
6998 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
7001 gas_assert (mo->name);
7002 gas_assert (strcmp (name, mo->name) == 0);
7005 create_insn (&insn, mo);
7043 gas_assert (ep != NULL);
7045 if (ep->X_op != O_constant)
7046 *r = (int) BFD_RELOC_UNUSED + c;
7047 else if (calculate_reloc (*r, ep->X_add_number, &value))
7049 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
7051 *r = BFD_RELOC_UNUSED;
7057 operand = decode_mips16_operand (c, FALSE);
7061 insn_insert_operand (&insn, operand, va_arg (*args, int));
7066 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7068 append_insn (&insn, ep, r, TRUE);
7072 * Sign-extend 32-bit mode constants that have bit 31 set and all
7073 * higher bits unset.
7076 normalize_constant_expr (expressionS *ex)
7078 if (ex->X_op == O_constant
7079 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7080 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7085 * Sign-extend 32-bit mode address offsets that have bit 31 set and
7086 * all higher bits unset.
7089 normalize_address_expr (expressionS *ex)
7091 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7092 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7093 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7094 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7099 * Generate a "jalr" instruction with a relocation hint to the called
7100 * function. This occurs in NewABI PIC code.
7103 macro_build_jalr (expressionS *ep, int cprestore)
7105 static const bfd_reloc_code_real_type jalr_relocs[2]
7106 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
7107 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
7111 if (MIPS_JALR_HINT_P (ep))
7116 if (mips_opts.micromips)
7118 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
7119 ? "jalr" : "jalrs");
7120 if (MIPS_JALR_HINT_P (ep)
7122 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7123 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
7125 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
7128 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
7129 if (MIPS_JALR_HINT_P (ep))
7130 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
7134 * Generate a "lui" instruction.
7137 macro_build_lui (expressionS *ep, int regnum)
7139 gas_assert (! mips_opts.mips16);
7141 if (ep->X_op != O_constant)
7143 gas_assert (ep->X_op == O_symbol);
7144 /* _gp_disp is a special case, used from s_cpload.
7145 __gnu_local_gp is used if mips_no_shared. */
7146 gas_assert (mips_pic == NO_PIC
7148 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
7149 || (! mips_in_shared
7150 && strcmp (S_GET_NAME (ep->X_add_symbol),
7151 "__gnu_local_gp") == 0));
7154 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
7157 /* Generate a sequence of instructions to do a load or store from a constant
7158 offset off of a base register (breg) into/from a target register (treg),
7159 using AT if necessary. */
7161 macro_build_ldst_constoffset (expressionS *ep, const char *op,
7162 int treg, int breg, int dbl)
7164 gas_assert (ep->X_op == O_constant);
7166 /* Sign-extending 32-bit constants makes their handling easier. */
7168 normalize_constant_expr (ep);
7170 /* Right now, this routine can only handle signed 32-bit constants. */
7171 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
7172 as_warn (_("operand overflow"));
7174 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
7176 /* Signed 16-bit offset will fit in the op. Easy! */
7177 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7181 /* 32-bit offset, need multiple instructions and AT, like:
7182 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7183 addu $tempreg,$tempreg,$breg
7184 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7185 to handle the complete offset. */
7186 macro_build_lui (ep, AT);
7187 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7188 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7191 as_bad (_("Macro used $at after \".set noat\""));
7196 * Generates code to set the $at register to true (one)
7197 * if reg is less than the immediate expression.
7200 set_at (int reg, int unsignedp)
7202 if (imm_expr.X_op == O_constant
7203 && imm_expr.X_add_number >= -0x8000
7204 && imm_expr.X_add_number < 0x8000)
7205 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
7206 AT, reg, BFD_RELOC_LO16);
7209 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7210 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
7214 /* Count the leading zeroes by performing a binary chop. This is a
7215 bulky bit of source, but performance is a LOT better for the
7216 majority of values than a simple loop to count the bits:
7217 for (lcnt = 0; (lcnt < 32); lcnt++)
7218 if ((v) & (1 << (31 - lcnt)))
7220 However it is not code size friendly, and the gain will drop a bit
7221 on certain cached systems.
7223 #define COUNT_TOP_ZEROES(v) \
7224 (((v) & ~0xffff) == 0 \
7225 ? ((v) & ~0xff) == 0 \
7226 ? ((v) & ~0xf) == 0 \
7227 ? ((v) & ~0x3) == 0 \
7228 ? ((v) & ~0x1) == 0 \
7233 : ((v) & ~0x7) == 0 \
7236 : ((v) & ~0x3f) == 0 \
7237 ? ((v) & ~0x1f) == 0 \
7240 : ((v) & ~0x7f) == 0 \
7243 : ((v) & ~0xfff) == 0 \
7244 ? ((v) & ~0x3ff) == 0 \
7245 ? ((v) & ~0x1ff) == 0 \
7248 : ((v) & ~0x7ff) == 0 \
7251 : ((v) & ~0x3fff) == 0 \
7252 ? ((v) & ~0x1fff) == 0 \
7255 : ((v) & ~0x7fff) == 0 \
7258 : ((v) & ~0xffffff) == 0 \
7259 ? ((v) & ~0xfffff) == 0 \
7260 ? ((v) & ~0x3ffff) == 0 \
7261 ? ((v) & ~0x1ffff) == 0 \
7264 : ((v) & ~0x7ffff) == 0 \
7267 : ((v) & ~0x3fffff) == 0 \
7268 ? ((v) & ~0x1fffff) == 0 \
7271 : ((v) & ~0x7fffff) == 0 \
7274 : ((v) & ~0xfffffff) == 0 \
7275 ? ((v) & ~0x3ffffff) == 0 \
7276 ? ((v) & ~0x1ffffff) == 0 \
7279 : ((v) & ~0x7ffffff) == 0 \
7282 : ((v) & ~0x3fffffff) == 0 \
7283 ? ((v) & ~0x1fffffff) == 0 \
7286 : ((v) & ~0x7fffffff) == 0 \
7291 * This routine generates the least number of instructions necessary to load
7292 * an absolute expression value into a register.
7295 load_register (int reg, expressionS *ep, int dbl)
7298 expressionS hi32, lo32;
7300 if (ep->X_op != O_big)
7302 gas_assert (ep->X_op == O_constant);
7304 /* Sign-extending 32-bit constants makes their handling easier. */
7306 normalize_constant_expr (ep);
7308 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
7310 /* We can handle 16 bit signed values with an addiu to
7311 $zero. No need to ever use daddiu here, since $zero and
7312 the result are always correct in 32 bit mode. */
7313 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7316 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
7318 /* We can handle 16 bit unsigned values with an ori to
7320 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
7323 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
7325 /* 32 bit values require an lui. */
7326 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7327 if ((ep->X_add_number & 0xffff) != 0)
7328 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
7333 /* The value is larger than 32 bits. */
7335 if (!dbl || HAVE_32BIT_GPRS)
7339 sprintf_vma (value, ep->X_add_number);
7340 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7341 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7345 if (ep->X_op != O_big)
7348 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7349 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
7350 hi32.X_add_number &= 0xffffffff;
7352 lo32.X_add_number &= 0xffffffff;
7356 gas_assert (ep->X_add_number > 2);
7357 if (ep->X_add_number == 3)
7358 generic_bignum[3] = 0;
7359 else if (ep->X_add_number > 4)
7360 as_bad (_("Number larger than 64 bits"));
7361 lo32.X_op = O_constant;
7362 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
7363 hi32.X_op = O_constant;
7364 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
7367 if (hi32.X_add_number == 0)
7372 unsigned long hi, lo;
7374 if (hi32.X_add_number == (offsetT) 0xffffffff)
7376 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
7378 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7381 if (lo32.X_add_number & 0x80000000)
7383 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7384 if (lo32.X_add_number & 0xffff)
7385 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
7390 /* Check for 16bit shifted constant. We know that hi32 is
7391 non-zero, so start the mask on the first bit of the hi32
7396 unsigned long himask, lomask;
7400 himask = 0xffff >> (32 - shift);
7401 lomask = (0xffff << shift) & 0xffffffff;
7405 himask = 0xffff << (shift - 32);
7408 if ((hi32.X_add_number & ~(offsetT) himask) == 0
7409 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
7413 tmp.X_op = O_constant;
7415 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
7416 | (lo32.X_add_number >> shift));
7418 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
7419 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
7420 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
7421 reg, reg, (shift >= 32) ? shift - 32 : shift);
7426 while (shift <= (64 - 16));
7428 /* Find the bit number of the lowest one bit, and store the
7429 shifted value in hi/lo. */
7430 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
7431 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
7435 while ((lo & 1) == 0)
7440 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
7446 while ((hi & 1) == 0)
7455 /* Optimize if the shifted value is a (power of 2) - 1. */
7456 if ((hi == 0 && ((lo + 1) & lo) == 0)
7457 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
7459 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
7464 /* This instruction will set the register to be all
7466 tmp.X_op = O_constant;
7467 tmp.X_add_number = (offsetT) -1;
7468 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
7472 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
7473 reg, reg, (bit >= 32) ? bit - 32 : bit);
7475 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
7476 reg, reg, (shift >= 32) ? shift - 32 : shift);
7481 /* Sign extend hi32 before calling load_register, because we can
7482 generally get better code when we load a sign extended value. */
7483 if ((hi32.X_add_number & 0x80000000) != 0)
7484 hi32.X_add_number |= ~(offsetT) 0xffffffff;
7485 load_register (reg, &hi32, 0);
7488 if ((lo32.X_add_number & 0xffff0000) == 0)
7492 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
7500 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
7502 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
7503 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
7509 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
7513 mid16.X_add_number >>= 16;
7514 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
7515 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7518 if ((lo32.X_add_number & 0xffff) != 0)
7519 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
7523 load_delay_nop (void)
7525 if (!gpr_interlocks)
7526 macro_build (NULL, "nop", "");
7529 /* Load an address into a register. */
7532 load_address (int reg, expressionS *ep, int *used_at)
7534 if (ep->X_op != O_constant
7535 && ep->X_op != O_symbol)
7537 as_bad (_("expression too complex"));
7538 ep->X_op = O_constant;
7541 if (ep->X_op == O_constant)
7543 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
7547 if (mips_pic == NO_PIC)
7549 /* If this is a reference to a GP relative symbol, we want
7550 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7552 lui $reg,<sym> (BFD_RELOC_HI16_S)
7553 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7554 If we have an addend, we always use the latter form.
7556 With 64bit address space and a usable $at we want
7557 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7558 lui $at,<sym> (BFD_RELOC_HI16_S)
7559 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7560 daddiu $at,<sym> (BFD_RELOC_LO16)
7564 If $at is already in use, we use a path which is suboptimal
7565 on superscalar processors.
7566 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7567 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7569 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7571 daddiu $reg,<sym> (BFD_RELOC_LO16)
7573 For GP relative symbols in 64bit address space we can use
7574 the same sequence as in 32bit address space. */
7575 if (HAVE_64BIT_SYMBOLS)
7577 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7578 && !nopic_need_relax (ep->X_add_symbol, 1))
7580 relax_start (ep->X_add_symbol);
7581 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7582 mips_gp_register, BFD_RELOC_GPREL16);
7586 if (*used_at == 0 && mips_opts.at)
7588 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7589 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
7590 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7591 BFD_RELOC_MIPS_HIGHER);
7592 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
7593 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
7594 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
7599 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
7600 macro_build (ep, "daddiu", "t,r,j", reg, reg,
7601 BFD_RELOC_MIPS_HIGHER);
7602 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7603 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
7604 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
7605 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
7608 if (mips_relax.sequence)
7613 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
7614 && !nopic_need_relax (ep->X_add_symbol, 1))
7616 relax_start (ep->X_add_symbol);
7617 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
7618 mips_gp_register, BFD_RELOC_GPREL16);
7621 macro_build_lui (ep, reg);
7622 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
7623 reg, reg, BFD_RELOC_LO16);
7624 if (mips_relax.sequence)
7628 else if (!mips_big_got)
7632 /* If this is a reference to an external symbol, we want
7633 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7635 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7637 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7638 If there is a constant, it must be added in after.
7640 If we have NewABI, we want
7641 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7642 unless we're referencing a global symbol with a non-zero
7643 offset, in which case cst must be added separately. */
7646 if (ep->X_add_number)
7648 ex.X_add_number = ep->X_add_number;
7649 ep->X_add_number = 0;
7650 relax_start (ep->X_add_symbol);
7651 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7652 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7653 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7654 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7655 ex.X_op = O_constant;
7656 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
7657 reg, reg, BFD_RELOC_LO16);
7658 ep->X_add_number = ex.X_add_number;
7661 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7662 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7663 if (mips_relax.sequence)
7668 ex.X_add_number = ep->X_add_number;
7669 ep->X_add_number = 0;
7670 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7671 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7673 relax_start (ep->X_add_symbol);
7675 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7679 if (ex.X_add_number != 0)
7681 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7682 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7683 ex.X_op = O_constant;
7684 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
7685 reg, reg, BFD_RELOC_LO16);
7689 else if (mips_big_got)
7693 /* This is the large GOT case. If this is a reference to an
7694 external symbol, we want
7695 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7697 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7699 Otherwise, for a reference to a local symbol in old ABI, we want
7700 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7702 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7703 If there is a constant, it must be added in after.
7705 In the NewABI, for local symbols, with or without offsets, we want:
7706 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7707 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7711 ex.X_add_number = ep->X_add_number;
7712 ep->X_add_number = 0;
7713 relax_start (ep->X_add_symbol);
7714 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
7715 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7716 reg, reg, mips_gp_register);
7717 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7718 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
7719 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7720 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7721 else if (ex.X_add_number)
7723 ex.X_op = O_constant;
7724 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7728 ep->X_add_number = ex.X_add_number;
7730 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7731 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7732 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7733 BFD_RELOC_MIPS_GOT_OFST);
7738 ex.X_add_number = ep->X_add_number;
7739 ep->X_add_number = 0;
7740 relax_start (ep->X_add_symbol);
7741 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
7742 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7743 reg, reg, mips_gp_register);
7744 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
7745 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
7747 if (reg_needs_delay (mips_gp_register))
7749 /* We need a nop before loading from $gp. This special
7750 check is required because the lui which starts the main
7751 instruction stream does not refer to $gp, and so will not
7752 insert the nop which may be required. */
7753 macro_build (NULL, "nop", "");
7755 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
7756 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7758 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7762 if (ex.X_add_number != 0)
7764 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
7765 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7766 ex.X_op = O_constant;
7767 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
7775 if (!mips_opts.at && *used_at == 1)
7776 as_bad (_("Macro used $at after \".set noat\""));
7779 /* Move the contents of register SOURCE into register DEST. */
7782 move_register (int dest, int source)
7784 /* Prefer to use a 16-bit microMIPS instruction unless the previous
7785 instruction specifically requires a 32-bit one. */
7786 if (mips_opts.micromips
7787 && !mips_opts.insn32
7788 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7789 macro_build (NULL, "move", "mp,mj", dest, source);
7791 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
7795 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
7796 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
7797 The two alternatives are:
7799 Global symbol Local sybmol
7800 ------------- ------------
7801 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
7803 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
7805 load_got_offset emits the first instruction and add_got_offset
7806 emits the second for a 16-bit offset or add_got_offset_hilo emits
7807 a sequence to add a 32-bit offset using a scratch register. */
7810 load_got_offset (int dest, expressionS *local)
7815 global.X_add_number = 0;
7817 relax_start (local->X_add_symbol);
7818 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7819 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7821 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
7822 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7827 add_got_offset (int dest, expressionS *local)
7831 global.X_op = O_constant;
7832 global.X_op_symbol = NULL;
7833 global.X_add_symbol = NULL;
7834 global.X_add_number = local->X_add_number;
7836 relax_start (local->X_add_symbol);
7837 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
7838 dest, dest, BFD_RELOC_LO16);
7840 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
7845 add_got_offset_hilo (int dest, expressionS *local, int tmp)
7848 int hold_mips_optimize;
7850 global.X_op = O_constant;
7851 global.X_op_symbol = NULL;
7852 global.X_add_symbol = NULL;
7853 global.X_add_number = local->X_add_number;
7855 relax_start (local->X_add_symbol);
7856 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
7858 /* Set mips_optimize around the lui instruction to avoid
7859 inserting an unnecessary nop after the lw. */
7860 hold_mips_optimize = mips_optimize;
7862 macro_build_lui (&global, tmp);
7863 mips_optimize = hold_mips_optimize;
7864 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
7867 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
7870 /* Emit a sequence of instructions to emulate a branch likely operation.
7871 BR is an ordinary branch corresponding to one to be emulated. BRNEG
7872 is its complementing branch with the original condition negated.
7873 CALL is set if the original branch specified the link operation.
7874 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
7876 Code like this is produced in the noreorder mode:
7881 delay slot (executed only if branch taken)
7889 delay slot (executed only if branch taken)
7892 In the reorder mode the delay slot would be filled with a nop anyway,
7893 so code produced is simply:
7898 This function is used when producing code for the microMIPS ASE that
7899 does not implement branch likely instructions in hardware. */
7902 macro_build_branch_likely (const char *br, const char *brneg,
7903 int call, expressionS *ep, const char *fmt,
7904 unsigned int sreg, unsigned int treg)
7906 int noreorder = mips_opts.noreorder;
7909 gas_assert (mips_opts.micromips);
7913 micromips_label_expr (&expr1);
7914 macro_build (&expr1, brneg, fmt, sreg, treg);
7915 macro_build (NULL, "nop", "");
7916 macro_build (ep, call ? "bal" : "b", "p");
7918 /* Set to true so that append_insn adds a label. */
7919 emit_branch_likely_macro = TRUE;
7923 macro_build (ep, br, fmt, sreg, treg);
7924 macro_build (NULL, "nop", "");
7929 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
7930 the condition code tested. EP specifies the branch target. */
7933 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
7960 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
7963 /* Emit a two-argument branch macro specified by TYPE, using SREG as
7964 the register tested. EP specifies the branch target. */
7967 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
7969 const char *brneg = NULL;
7979 br = mips_opts.micromips ? "bgez" : "bgezl";
7983 gas_assert (mips_opts.micromips);
7984 br = mips_opts.insn32 ? "bgezal" : "bgezals";
7992 br = mips_opts.micromips ? "bgtz" : "bgtzl";
7999 br = mips_opts.micromips ? "blez" : "blezl";
8006 br = mips_opts.micromips ? "bltz" : "bltzl";
8010 gas_assert (mips_opts.micromips);
8011 br = mips_opts.insn32 ? "bltzal" : "bltzals";
8018 if (mips_opts.micromips && brneg)
8019 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
8021 macro_build (ep, br, "s,p", sreg);
8024 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8025 TREG as the registers tested. EP specifies the branch target. */
8028 macro_build_branch_rsrt (int type, expressionS *ep,
8029 unsigned int sreg, unsigned int treg)
8031 const char *brneg = NULL;
8043 br = mips_opts.micromips ? "beq" : "beql";
8052 br = mips_opts.micromips ? "bne" : "bnel";
8058 if (mips_opts.micromips && brneg)
8059 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
8061 macro_build (ep, br, "s,t,p", sreg, treg);
8064 /* Return the high part that should be loaded in order to make the low
8065 part of VALUE accessible using an offset of OFFBITS bits. */
8068 offset_high_part (offsetT value, unsigned int offbits)
8075 bias = 1 << (offbits - 1);
8076 low_mask = bias * 2 - 1;
8077 return (value + bias) & ~low_mask;
8080 /* Return true if the value stored in offset_expr and offset_reloc
8081 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8082 amount that the caller wants to add without inducing overflow
8083 and ALIGN is the known alignment of the value in bytes. */
8086 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
8090 /* Accept any relocation operator if overflow isn't a concern. */
8091 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
8094 /* These relocations are guaranteed not to overflow in correct links. */
8095 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
8096 || gprel16_reloc_p (*offset_reloc))
8099 if (offset_expr.X_op == O_constant
8100 && offset_high_part (offset_expr.X_add_number, offbits) == 0
8101 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
8108 * This routine implements the seemingly endless macro or synthesized
8109 * instructions and addressing modes in the mips assembly language. Many
8110 * of these macros are simple and are similar to each other. These could
8111 * probably be handled by some kind of table or grammar approach instead of
8112 * this verbose method. Others are not simple macros but are more like
8113 * optimizing code generation.
8114 * One interesting optimization is when several store macros appear
8115 * consecutively that would load AT with the upper half of the same address.
8116 * The ensuing load upper instructions are ommited. This implies some kind
8117 * of global optimization. We currently only optimize within a single macro.
8118 * For many of the load and store macros if the address is specified as a
8119 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8120 * first load register 'at' with zero and use it as the base register. The
8121 * mips assembler simply uses register $zero. Just one tiny optimization
8125 macro (struct mips_cl_insn *ip, char *str)
8127 unsigned int treg, sreg, dreg, breg;
8128 unsigned int tempreg;
8131 expressionS label_expr;
8146 bfd_boolean large_offset;
8148 int hold_mips_optimize;
8151 gas_assert (! mips_opts.mips16);
8153 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
8154 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
8155 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
8156 mask = ip->insn_mo->mask;
8158 label_expr.X_op = O_constant;
8159 label_expr.X_op_symbol = NULL;
8160 label_expr.X_add_symbol = NULL;
8161 label_expr.X_add_number = 0;
8163 expr1.X_op = O_constant;
8164 expr1.X_op_symbol = NULL;
8165 expr1.X_add_symbol = NULL;
8166 expr1.X_add_number = 1;
8182 if (mips_opts.micromips)
8183 micromips_label_expr (&label_expr);
8185 label_expr.X_add_number = 8;
8186 macro_build (&label_expr, "bgez", "s,p", sreg);
8188 macro_build (NULL, "nop", "");
8190 move_register (dreg, sreg);
8191 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
8192 if (mips_opts.micromips)
8193 micromips_add_label ();
8210 if (!mips_opts.micromips)
8212 if (imm_expr.X_op == O_constant
8213 && imm_expr.X_add_number >= -0x200
8214 && imm_expr.X_add_number < 0x200)
8216 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
8225 if (imm_expr.X_op == O_constant
8226 && imm_expr.X_add_number >= -0x8000
8227 && imm_expr.X_add_number < 0x8000)
8229 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
8234 load_register (AT, &imm_expr, dbl);
8235 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
8254 if (imm_expr.X_op == O_constant
8255 && imm_expr.X_add_number >= 0
8256 && imm_expr.X_add_number < 0x10000)
8258 if (mask != M_NOR_I)
8259 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
8262 macro_build (&imm_expr, "ori", "t,r,i",
8263 treg, sreg, BFD_RELOC_LO16);
8264 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
8270 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8271 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
8275 switch (imm_expr.X_add_number)
8278 macro_build (NULL, "nop", "");
8281 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
8285 macro_build (NULL, "balign", "t,s,2", treg, sreg,
8286 (int) imm_expr.X_add_number);
8289 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8290 (unsigned long) imm_expr.X_add_number);
8299 gas_assert (mips_opts.micromips);
8300 macro_build_branch_ccl (mask, &offset_expr,
8301 EXTRACT_OPERAND (1, BCC, *ip));
8308 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8314 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
8319 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
8326 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
8328 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
8332 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
8333 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8334 &offset_expr, AT, ZERO);
8344 macro_build_branch_rs (mask, &offset_expr, sreg);
8350 /* Check for > max integer. */
8351 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
8354 /* Result is always false. */
8356 macro_build (NULL, "nop", "");
8358 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
8361 if (imm_expr.X_op != O_constant)
8362 as_bad (_("Unsupported large constant"));
8363 ++imm_expr.X_add_number;
8367 if (mask == M_BGEL_I)
8369 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8371 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
8372 &offset_expr, sreg);
8375 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8377 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
8378 &offset_expr, sreg);
8381 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
8384 /* result is always true */
8385 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
8386 macro_build (&offset_expr, "b", "p");
8391 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8392 &offset_expr, AT, ZERO);
8401 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8402 &offset_expr, ZERO, treg);
8406 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
8407 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8408 &offset_expr, AT, ZERO);
8417 && imm_expr.X_op == O_constant
8418 && imm_expr.X_add_number == -1))
8420 if (imm_expr.X_op != O_constant)
8421 as_bad (_("Unsupported large constant"));
8422 ++imm_expr.X_add_number;
8426 if (mask == M_BGEUL_I)
8428 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8430 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8431 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8432 &offset_expr, sreg, ZERO);
8437 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8438 &offset_expr, AT, ZERO);
8446 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
8448 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
8452 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
8453 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8454 &offset_expr, AT, ZERO);
8462 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8463 &offset_expr, sreg, ZERO);
8469 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
8470 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8471 &offset_expr, AT, ZERO);
8479 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
8481 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
8485 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
8486 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8487 &offset_expr, AT, ZERO);
8494 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
8496 if (imm_expr.X_op != O_constant)
8497 as_bad (_("Unsupported large constant"));
8498 ++imm_expr.X_add_number;
8502 if (mask == M_BLTL_I)
8504 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8505 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
8506 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8507 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
8512 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8513 &offset_expr, AT, ZERO);
8521 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8522 &offset_expr, sreg, ZERO);
8528 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
8529 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8530 &offset_expr, AT, ZERO);
8539 && imm_expr.X_op == O_constant
8540 && imm_expr.X_add_number == -1))
8542 if (imm_expr.X_op != O_constant)
8543 as_bad (_("Unsupported large constant"));
8544 ++imm_expr.X_add_number;
8548 if (mask == M_BLTUL_I)
8550 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8552 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8553 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
8554 &offset_expr, sreg, ZERO);
8559 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8560 &offset_expr, AT, ZERO);
8568 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
8570 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
8574 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
8575 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8576 &offset_expr, AT, ZERO);
8586 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8587 &offset_expr, ZERO, treg);
8591 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
8592 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
8593 &offset_expr, AT, ZERO);
8599 /* Use unsigned arithmetic. */
8603 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
8605 as_bad (_("Unsupported large constant"));
8610 pos = imm_expr.X_add_number;
8611 size = imm2_expr.X_add_number;
8616 report_bad_range (ip, 3, pos, 0, 63, FALSE);
8619 if (size == 0 || size > 64 || (pos + size - 1) > 63)
8621 report_bad_field (pos, size);
8625 if (size <= 32 && pos < 32)
8630 else if (size <= 32)
8640 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
8647 /* Use unsigned arithmetic. */
8651 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
8653 as_bad (_("Unsupported large constant"));
8658 pos = imm_expr.X_add_number;
8659 size = imm2_expr.X_add_number;
8664 report_bad_range (ip, 3, pos, 0, 63, FALSE);
8667 if (size == 0 || size > 64 || (pos + size - 1) > 63)
8669 report_bad_field (pos, size);
8673 if (pos < 32 && (pos + size - 1) < 32)
8688 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
8689 (int) (pos + size - 1));
8705 as_warn (_("Divide by zero."));
8707 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
8709 macro_build (NULL, "break", BRK_FMT, 7);
8716 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
8717 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
8721 if (mips_opts.micromips)
8722 micromips_label_expr (&label_expr);
8724 label_expr.X_add_number = 8;
8725 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
8726 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
8727 macro_build (NULL, "break", BRK_FMT, 7);
8728 if (mips_opts.micromips)
8729 micromips_add_label ();
8731 expr1.X_add_number = -1;
8733 load_register (AT, &expr1, dbl);
8734 if (mips_opts.micromips)
8735 micromips_label_expr (&label_expr);
8737 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
8738 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
8741 expr1.X_add_number = 1;
8742 load_register (AT, &expr1, dbl);
8743 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
8747 expr1.X_add_number = 0x80000000;
8748 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
8752 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
8753 /* We want to close the noreorder block as soon as possible, so
8754 that later insns are available for delay slot filling. */
8759 if (mips_opts.micromips)
8760 micromips_label_expr (&label_expr);
8762 label_expr.X_add_number = 8;
8763 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
8764 macro_build (NULL, "nop", "");
8766 /* We want to close the noreorder block as soon as possible, so
8767 that later insns are available for delay slot filling. */
8770 macro_build (NULL, "break", BRK_FMT, 6);
8772 if (mips_opts.micromips)
8773 micromips_add_label ();
8774 macro_build (NULL, s, MFHL_FMT, dreg);
8813 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8815 as_warn (_("Divide by zero."));
8817 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
8819 macro_build (NULL, "break", BRK_FMT, 7);
8822 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
8824 if (strcmp (s2, "mflo") == 0)
8825 move_register (dreg, sreg);
8827 move_register (dreg, ZERO);
8830 if (imm_expr.X_op == O_constant
8831 && imm_expr.X_add_number == -1
8832 && s[strlen (s) - 1] != 'u')
8834 if (strcmp (s2, "mflo") == 0)
8836 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
8839 move_register (dreg, ZERO);
8844 load_register (AT, &imm_expr, dbl);
8845 macro_build (NULL, s, "z,s,t", sreg, AT);
8846 macro_build (NULL, s2, MFHL_FMT, dreg);
8868 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
8869 macro_build (NULL, s, "z,s,t", sreg, treg);
8870 /* We want to close the noreorder block as soon as possible, so
8871 that later insns are available for delay slot filling. */
8876 if (mips_opts.micromips)
8877 micromips_label_expr (&label_expr);
8879 label_expr.X_add_number = 8;
8880 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
8881 macro_build (NULL, s, "z,s,t", sreg, treg);
8883 /* We want to close the noreorder block as soon as possible, so
8884 that later insns are available for delay slot filling. */
8886 macro_build (NULL, "break", BRK_FMT, 7);
8887 if (mips_opts.micromips)
8888 micromips_add_label ();
8890 macro_build (NULL, s2, MFHL_FMT, dreg);
8902 /* Load the address of a symbol into a register. If breg is not
8903 zero, we then add a base register to it. */
8905 if (dbl && HAVE_32BIT_GPRS)
8906 as_warn (_("dla used to load 32-bit register"));
8908 if (!dbl && HAVE_64BIT_OBJECTS)
8909 as_warn (_("la used to load 64-bit address"));
8911 if (small_offset_p (0, align, 16))
8913 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
8914 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8918 if (mips_opts.at && (treg == breg))
8928 if (offset_expr.X_op != O_symbol
8929 && offset_expr.X_op != O_constant)
8931 as_bad (_("Expression too complex"));
8932 offset_expr.X_op = O_constant;
8935 if (offset_expr.X_op == O_constant)
8936 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
8937 else if (mips_pic == NO_PIC)
8939 /* If this is a reference to a GP relative symbol, we want
8940 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
8942 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8943 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8944 If we have a constant, we need two instructions anyhow,
8945 so we may as well always use the latter form.
8947 With 64bit address space and a usable $at we want
8948 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8949 lui $at,<sym> (BFD_RELOC_HI16_S)
8950 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8951 daddiu $at,<sym> (BFD_RELOC_LO16)
8953 daddu $tempreg,$tempreg,$at
8955 If $at is already in use, we use a path which is suboptimal
8956 on superscalar processors.
8957 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8958 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8960 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8962 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
8964 For GP relative symbols in 64bit address space we can use
8965 the same sequence as in 32bit address space. */
8966 if (HAVE_64BIT_SYMBOLS)
8968 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8969 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8971 relax_start (offset_expr.X_add_symbol);
8972 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8973 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
8977 if (used_at == 0 && mips_opts.at)
8979 macro_build (&offset_expr, "lui", LUI_FMT,
8980 tempreg, BFD_RELOC_MIPS_HIGHEST);
8981 macro_build (&offset_expr, "lui", LUI_FMT,
8982 AT, BFD_RELOC_HI16_S);
8983 macro_build (&offset_expr, "daddiu", "t,r,j",
8984 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
8985 macro_build (&offset_expr, "daddiu", "t,r,j",
8986 AT, AT, BFD_RELOC_LO16);
8987 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8988 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8993 macro_build (&offset_expr, "lui", LUI_FMT,
8994 tempreg, BFD_RELOC_MIPS_HIGHEST);
8995 macro_build (&offset_expr, "daddiu", "t,r,j",
8996 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
8997 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8998 macro_build (&offset_expr, "daddiu", "t,r,j",
8999 tempreg, tempreg, BFD_RELOC_HI16_S);
9000 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9001 macro_build (&offset_expr, "daddiu", "t,r,j",
9002 tempreg, tempreg, BFD_RELOC_LO16);
9005 if (mips_relax.sequence)
9010 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9011 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9013 relax_start (offset_expr.X_add_symbol);
9014 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9015 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9018 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9019 as_bad (_("Offset too large"));
9020 macro_build_lui (&offset_expr, tempreg);
9021 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9022 tempreg, tempreg, BFD_RELOC_LO16);
9023 if (mips_relax.sequence)
9027 else if (!mips_big_got && !HAVE_NEWABI)
9029 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9031 /* If this is a reference to an external symbol, and there
9032 is no constant, we want
9033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9034 or for lca or if tempreg is PIC_CALL_REG
9035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9036 For a local symbol, we want
9037 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9039 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9041 If we have a small constant, and this is a reference to
9042 an external symbol, we want
9043 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9045 addiu $tempreg,$tempreg,<constant>
9046 For a local symbol, we want the same instruction
9047 sequence, but we output a BFD_RELOC_LO16 reloc on the
9050 If we have a large constant, and this is a reference to
9051 an external symbol, we want
9052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9053 lui $at,<hiconstant>
9054 addiu $at,$at,<loconstant>
9055 addu $tempreg,$tempreg,$at
9056 For a local symbol, we want the same instruction
9057 sequence, but we output a BFD_RELOC_LO16 reloc on the
9061 if (offset_expr.X_add_number == 0)
9063 if (mips_pic == SVR4_PIC
9065 && (call || tempreg == PIC_CALL_REG))
9066 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9068 relax_start (offset_expr.X_add_symbol);
9069 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9070 lw_reloc_type, mips_gp_register);
9073 /* We're going to put in an addu instruction using
9074 tempreg, so we may as well insert the nop right
9079 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9080 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
9082 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9083 tempreg, tempreg, BFD_RELOC_LO16);
9085 /* FIXME: If breg == 0, and the next instruction uses
9086 $tempreg, then if this variant case is used an extra
9087 nop will be generated. */
9089 else if (offset_expr.X_add_number >= -0x8000
9090 && offset_expr.X_add_number < 0x8000)
9092 load_got_offset (tempreg, &offset_expr);
9094 add_got_offset (tempreg, &offset_expr);
9098 expr1.X_add_number = offset_expr.X_add_number;
9099 offset_expr.X_add_number =
9100 SEXT_16BIT (offset_expr.X_add_number);
9101 load_got_offset (tempreg, &offset_expr);
9102 offset_expr.X_add_number = expr1.X_add_number;
9103 /* If we are going to add in a base register, and the
9104 target register and the base register are the same,
9105 then we are using AT as a temporary register. Since
9106 we want to load the constant into AT, we add our
9107 current AT (from the global offset table) and the
9108 register into the register now, and pretend we were
9109 not using a base register. */
9113 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9118 add_got_offset_hilo (tempreg, &offset_expr, AT);
9122 else if (!mips_big_got && HAVE_NEWABI)
9124 int add_breg_early = 0;
9126 /* If this is a reference to an external, and there is no
9127 constant, or local symbol (*), with or without a
9129 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9130 or for lca or if tempreg is PIC_CALL_REG
9131 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9133 If we have a small constant, and this is a reference to
9134 an external symbol, we want
9135 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9136 addiu $tempreg,$tempreg,<constant>
9138 If we have a large constant, and this is a reference to
9139 an external symbol, we want
9140 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9141 lui $at,<hiconstant>
9142 addiu $at,$at,<loconstant>
9143 addu $tempreg,$tempreg,$at
9145 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9146 local symbols, even though it introduces an additional
9149 if (offset_expr.X_add_number)
9151 expr1.X_add_number = offset_expr.X_add_number;
9152 offset_expr.X_add_number = 0;
9154 relax_start (offset_expr.X_add_symbol);
9155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9156 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9158 if (expr1.X_add_number >= -0x8000
9159 && expr1.X_add_number < 0x8000)
9161 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9162 tempreg, tempreg, BFD_RELOC_LO16);
9164 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9166 /* If we are going to add in a base register, and the
9167 target register and the base register are the same,
9168 then we are using AT as a temporary register. Since
9169 we want to load the constant into AT, we add our
9170 current AT (from the global offset table) and the
9171 register into the register now, and pretend we were
9172 not using a base register. */
9177 gas_assert (tempreg == AT);
9178 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9184 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9185 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9191 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9194 offset_expr.X_add_number = expr1.X_add_number;
9196 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9197 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9200 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9201 treg, tempreg, breg);
9207 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
9209 relax_start (offset_expr.X_add_symbol);
9210 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9211 BFD_RELOC_MIPS_CALL16, mips_gp_register);
9213 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9214 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9219 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9220 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9223 else if (mips_big_got && !HAVE_NEWABI)
9226 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9227 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
9228 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9230 /* This is the large GOT case. If this is a reference to an
9231 external symbol, and there is no constant, we want
9232 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9233 addu $tempreg,$tempreg,$gp
9234 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9235 or for lca or if tempreg is PIC_CALL_REG
9236 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9237 addu $tempreg,$tempreg,$gp
9238 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9239 For a local symbol, we want
9240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9242 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9244 If we have a small constant, and this is a reference to
9245 an external symbol, we want
9246 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9247 addu $tempreg,$tempreg,$gp
9248 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9250 addiu $tempreg,$tempreg,<constant>
9251 For a local symbol, we want
9252 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9254 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9256 If we have a large constant, and this is a reference to
9257 an external symbol, we want
9258 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9259 addu $tempreg,$tempreg,$gp
9260 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9261 lui $at,<hiconstant>
9262 addiu $at,$at,<loconstant>
9263 addu $tempreg,$tempreg,$at
9264 For a local symbol, we want
9265 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9266 lui $at,<hiconstant>
9267 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9268 addu $tempreg,$tempreg,$at
9271 expr1.X_add_number = offset_expr.X_add_number;
9272 offset_expr.X_add_number = 0;
9273 relax_start (offset_expr.X_add_symbol);
9274 gpdelay = reg_needs_delay (mips_gp_register);
9275 if (expr1.X_add_number == 0 && breg == 0
9276 && (call || tempreg == PIC_CALL_REG))
9278 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9279 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9281 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
9282 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9283 tempreg, tempreg, mips_gp_register);
9284 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9285 tempreg, lw_reloc_type, tempreg);
9286 if (expr1.X_add_number == 0)
9290 /* We're going to put in an addu instruction using
9291 tempreg, so we may as well insert the nop right
9296 else if (expr1.X_add_number >= -0x8000
9297 && expr1.X_add_number < 0x8000)
9300 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9301 tempreg, tempreg, BFD_RELOC_LO16);
9305 /* If we are going to add in a base register, and the
9306 target register and the base register are the same,
9307 then we are using AT as a temporary register. Since
9308 we want to load the constant into AT, we add our
9309 current AT (from the global offset table) and the
9310 register into the register now, and pretend we were
9311 not using a base register. */
9316 gas_assert (tempreg == AT);
9318 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9323 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9324 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
9328 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
9333 /* This is needed because this instruction uses $gp, but
9334 the first instruction on the main stream does not. */
9335 macro_build (NULL, "nop", "");
9338 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9339 local_reloc_type, mips_gp_register);
9340 if (expr1.X_add_number >= -0x8000
9341 && expr1.X_add_number < 0x8000)
9344 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9345 tempreg, tempreg, BFD_RELOC_LO16);
9346 /* FIXME: If add_number is 0, and there was no base
9347 register, the external symbol case ended with a load,
9348 so if the symbol turns out to not be external, and
9349 the next instruction uses tempreg, an unnecessary nop
9350 will be inserted. */
9356 /* We must add in the base register now, as in the
9357 external symbol case. */
9358 gas_assert (tempreg == AT);
9360 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9363 /* We set breg to 0 because we have arranged to add
9364 it in in both cases. */
9368 macro_build_lui (&expr1, AT);
9369 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9370 AT, AT, BFD_RELOC_LO16);
9371 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9372 tempreg, tempreg, AT);
9377 else if (mips_big_got && HAVE_NEWABI)
9379 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
9380 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
9381 int add_breg_early = 0;
9383 /* This is the large GOT case. If this is a reference to an
9384 external symbol, and there is no constant, we want
9385 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9386 add $tempreg,$tempreg,$gp
9387 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9388 or for lca or if tempreg is PIC_CALL_REG
9389 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9390 add $tempreg,$tempreg,$gp
9391 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9393 If we have a small constant, and this is a reference to
9394 an external symbol, we want
9395 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9396 add $tempreg,$tempreg,$gp
9397 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9398 addi $tempreg,$tempreg,<constant>
9400 If we have a large constant, and this is a reference to
9401 an external symbol, we want
9402 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9403 addu $tempreg,$tempreg,$gp
9404 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9405 lui $at,<hiconstant>
9406 addi $at,$at,<loconstant>
9407 add $tempreg,$tempreg,$at
9409 If we have NewABI, and we know it's a local symbol, we want
9410 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9411 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9412 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9414 relax_start (offset_expr.X_add_symbol);
9416 expr1.X_add_number = offset_expr.X_add_number;
9417 offset_expr.X_add_number = 0;
9419 if (expr1.X_add_number == 0 && breg == 0
9420 && (call || tempreg == PIC_CALL_REG))
9422 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
9423 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
9425 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
9426 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9427 tempreg, tempreg, mips_gp_register);
9428 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9429 tempreg, lw_reloc_type, tempreg);
9431 if (expr1.X_add_number == 0)
9433 else if (expr1.X_add_number >= -0x8000
9434 && expr1.X_add_number < 0x8000)
9436 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9437 tempreg, tempreg, BFD_RELOC_LO16);
9439 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9441 /* If we are going to add in a base register, and the
9442 target register and the base register are the same,
9443 then we are using AT as a temporary register. Since
9444 we want to load the constant into AT, we add our
9445 current AT (from the global offset table) and the
9446 register into the register now, and pretend we were
9447 not using a base register. */
9452 gas_assert (tempreg == AT);
9453 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9459 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9460 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
9465 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9468 offset_expr.X_add_number = expr1.X_add_number;
9469 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9470 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9471 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9472 tempreg, BFD_RELOC_MIPS_GOT_OFST);
9475 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9476 treg, tempreg, breg);
9486 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
9490 gas_assert (!mips_opts.micromips);
9491 macro_build (NULL, "c2", "C", (treg << 16) | 0x01);
9495 gas_assert (!mips_opts.micromips);
9496 macro_build (NULL, "c2", "C", 0x02);
9500 gas_assert (!mips_opts.micromips);
9501 macro_build (NULL, "c2", "C", (treg << 16) | 0x02);
9505 gas_assert (!mips_opts.micromips);
9506 macro_build (NULL, "c2", "C", 3);
9510 gas_assert (!mips_opts.micromips);
9511 macro_build (NULL, "c2", "C", (treg << 16) | 0x03);
9515 /* The j instruction may not be used in PIC code, since it
9516 requires an absolute address. We convert it to a b
9518 if (mips_pic == NO_PIC)
9519 macro_build (&offset_expr, "j", "a");
9521 macro_build (&offset_expr, "b", "p");
9524 /* The jal instructions must be handled as macros because when
9525 generating PIC code they expand to multi-instruction
9526 sequences. Normally they are simple instructions. */
9531 gas_assert (mips_opts.micromips);
9532 if (mips_opts.insn32)
9534 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9544 if (mips_pic == NO_PIC)
9546 s = jals ? "jalrs" : "jalr";
9547 if (mips_opts.micromips
9548 && !mips_opts.insn32
9550 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9551 macro_build (NULL, s, "mj", sreg);
9553 macro_build (NULL, s, JALR_FMT, dreg, sreg);
9557 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
9558 && mips_cprestore_offset >= 0);
9560 if (sreg != PIC_CALL_REG)
9561 as_warn (_("MIPS PIC call to register other than $25"));
9563 s = ((mips_opts.micromips
9564 && !mips_opts.insn32
9565 && (!mips_opts.noreorder || cprestore))
9566 ? "jalrs" : "jalr");
9567 if (mips_opts.micromips
9568 && !mips_opts.insn32
9570 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9571 macro_build (NULL, s, "mj", sreg);
9573 macro_build (NULL, s, JALR_FMT, dreg, sreg);
9574 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
9576 if (mips_cprestore_offset < 0)
9577 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9580 if (!mips_frame_reg_valid)
9582 as_warn (_("No .frame pseudo-op used in PIC code"));
9583 /* Quiet this warning. */
9584 mips_frame_reg_valid = 1;
9586 if (!mips_cprestore_valid)
9588 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9589 /* Quiet this warning. */
9590 mips_cprestore_valid = 1;
9592 if (mips_opts.noreorder)
9593 macro_build (NULL, "nop", "");
9594 expr1.X_add_number = mips_cprestore_offset;
9595 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
9598 HAVE_64BIT_ADDRESSES);
9606 gas_assert (mips_opts.micromips);
9607 if (mips_opts.insn32)
9609 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
9615 if (mips_pic == NO_PIC)
9616 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
9617 else if (mips_pic == SVR4_PIC)
9619 /* If this is a reference to an external symbol, and we are
9620 using a small GOT, we want
9621 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9625 lw $gp,cprestore($sp)
9626 The cprestore value is set using the .cprestore
9627 pseudo-op. If we are using a big GOT, we want
9628 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9630 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9634 lw $gp,cprestore($sp)
9635 If the symbol is not external, we want
9636 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9638 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9641 lw $gp,cprestore($sp)
9643 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9644 sequences above, minus nops, unless the symbol is local,
9645 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9651 relax_start (offset_expr.X_add_symbol);
9652 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9653 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
9656 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9657 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
9663 relax_start (offset_expr.X_add_symbol);
9664 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
9665 BFD_RELOC_MIPS_CALL_HI16);
9666 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9667 PIC_CALL_REG, mips_gp_register);
9668 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9669 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9672 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9673 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
9675 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9676 PIC_CALL_REG, PIC_CALL_REG,
9677 BFD_RELOC_MIPS_GOT_OFST);
9681 macro_build_jalr (&offset_expr, 0);
9685 relax_start (offset_expr.X_add_symbol);
9688 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9689 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
9698 gpdelay = reg_needs_delay (mips_gp_register);
9699 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
9700 BFD_RELOC_MIPS_CALL_HI16);
9701 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
9702 PIC_CALL_REG, mips_gp_register);
9703 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9704 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
9709 macro_build (NULL, "nop", "");
9711 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9712 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
9715 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9716 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
9718 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
9720 if (mips_cprestore_offset < 0)
9721 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9724 if (!mips_frame_reg_valid)
9726 as_warn (_("No .frame pseudo-op used in PIC code"));
9727 /* Quiet this warning. */
9728 mips_frame_reg_valid = 1;
9730 if (!mips_cprestore_valid)
9732 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9733 /* Quiet this warning. */
9734 mips_cprestore_valid = 1;
9736 if (mips_opts.noreorder)
9737 macro_build (NULL, "nop", "");
9738 expr1.X_add_number = mips_cprestore_offset;
9739 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
9742 HAVE_64BIT_ADDRESSES);
9746 else if (mips_pic == VXWORKS_PIC)
9747 as_bad (_("Non-PIC jump used in PIC library"));
9825 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
9831 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
9856 gas_assert (!mips_opts.micromips);
9859 /* Itbl support may require additional care here. */
9865 /* Itbl support may require additional care here. */
9871 offbits = (mips_opts.micromips ? 12 : 16);
9872 /* Itbl support may require additional care here. */
9876 gas_assert (!mips_opts.micromips);
9879 /* Itbl support may require additional care here. */
9885 offbits = (mips_opts.micromips ? 12 : 16);
9890 offbits = (mips_opts.micromips ? 12 : 16);
9895 /* Itbl support may require additional care here. */
9901 offbits = (mips_opts.micromips ? 12 : 16);
9902 /* Itbl support may require additional care here. */
9908 /* Itbl support may require additional care here. */
9914 /* Itbl support may require additional care here. */
9920 offbits = (mips_opts.micromips ? 12 : 16);
9925 offbits = (mips_opts.micromips ? 12 : 16);
9930 offbits = (mips_opts.micromips ? 12 : 16);
9935 offbits = (mips_opts.micromips ? 12 : 16);
9940 offbits = (mips_opts.micromips ? 12 : 16);
9943 gas_assert (mips_opts.micromips);
9950 gas_assert (mips_opts.micromips);
9957 gas_assert (mips_opts.micromips);
9963 gas_assert (mips_opts.micromips);
9970 /* We don't want to use $0 as tempreg. */
9971 if (breg == treg + lp || treg + lp == ZERO)
9974 tempreg = treg + lp;
9990 gas_assert (!mips_opts.micromips);
9993 /* Itbl support may require additional care here. */
9999 /* Itbl support may require additional care here. */
10005 offbits = (mips_opts.micromips ? 12 : 16);
10006 /* Itbl support may require additional care here. */
10010 gas_assert (!mips_opts.micromips);
10013 /* Itbl support may require additional care here. */
10019 offbits = (mips_opts.micromips ? 12 : 16);
10024 offbits = (mips_opts.micromips ? 12 : 16);
10029 offbits = (mips_opts.micromips ? 12 : 16);
10034 offbits = (mips_opts.micromips ? 12 : 16);
10038 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
10039 offbits = (mips_opts.micromips ? 12 : 16);
10048 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
10049 offbits = (mips_opts.micromips ? 12 : 16);
10060 /* Itbl support may require additional care here. */
10065 offbits = (mips_opts.micromips ? 12 : 16);
10066 /* Itbl support may require additional care here. */
10072 /* Itbl support may require additional care here. */
10076 gas_assert (!mips_opts.micromips);
10079 /* Itbl support may require additional care here. */
10085 offbits = (mips_opts.micromips ? 12 : 16);
10090 offbits = (mips_opts.micromips ? 12 : 16);
10093 gas_assert (mips_opts.micromips);
10099 gas_assert (mips_opts.micromips);
10105 gas_assert (mips_opts.micromips);
10111 gas_assert (mips_opts.micromips);
10119 if (small_offset_p (0, align, 16))
10121 /* The first case exists for M_LD_AB and M_SD_AB, which are
10122 macros for o32 but which should act like normal instructions
10125 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
10126 offset_reloc[1], offset_reloc[2], breg);
10127 else if (small_offset_p (0, align, offbits))
10130 macro_build (NULL, s, fmt, treg, breg);
10132 macro_build (NULL, s, fmt, treg,
10133 (int) offset_expr.X_add_number, breg);
10139 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10140 tempreg, breg, -1, offset_reloc[0],
10141 offset_reloc[1], offset_reloc[2]);
10143 macro_build (NULL, s, fmt, treg, tempreg);
10145 macro_build (NULL, s, fmt, treg, 0, tempreg);
10153 if (offset_expr.X_op != O_constant
10154 && offset_expr.X_op != O_symbol)
10156 as_bad (_("Expression too complex"));
10157 offset_expr.X_op = O_constant;
10160 if (HAVE_32BIT_ADDRESSES
10161 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10165 sprintf_vma (value, offset_expr.X_add_number);
10166 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10169 /* A constant expression in PIC code can be handled just as it
10170 is in non PIC code. */
10171 if (offset_expr.X_op == O_constant)
10173 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
10174 offbits == 0 ? 16 : offbits);
10175 offset_expr.X_add_number -= expr1.X_add_number;
10177 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
10179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10180 tempreg, tempreg, breg);
10183 if (offset_expr.X_add_number != 0)
10184 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
10185 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
10186 macro_build (NULL, s, fmt, treg, tempreg);
10188 else if (offbits == 16)
10189 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10191 macro_build (NULL, s, fmt, treg,
10192 (int) offset_expr.X_add_number, tempreg);
10194 else if (offbits != 16)
10196 /* The offset field is too narrow to be used for a low-part
10197 relocation, so load the whole address into the auxillary
10199 load_address (tempreg, &offset_expr, &used_at);
10201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10202 tempreg, tempreg, breg);
10204 macro_build (NULL, s, fmt, treg, tempreg);
10206 macro_build (NULL, s, fmt, treg, 0, tempreg);
10208 else if (mips_pic == NO_PIC)
10210 /* If this is a reference to a GP relative symbol, and there
10211 is no base register, we want
10212 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10213 Otherwise, if there is no base register, we want
10214 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10215 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10216 If we have a constant, we need two instructions anyhow,
10217 so we always use the latter form.
10219 If we have a base register, and this is a reference to a
10220 GP relative symbol, we want
10221 addu $tempreg,$breg,$gp
10222 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
10224 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10225 addu $tempreg,$tempreg,$breg
10226 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10227 With a constant we always use the latter case.
10229 With 64bit address space and no base register and $at usable,
10231 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10232 lui $at,<sym> (BFD_RELOC_HI16_S)
10233 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10236 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10237 If we have a base register, we want
10238 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10239 lui $at,<sym> (BFD_RELOC_HI16_S)
10240 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10244 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10246 Without $at we can't generate the optimal path for superscalar
10247 processors here since this would require two temporary registers.
10248 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10249 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10251 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10253 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10254 If we have a base register, we want
10255 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10256 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10258 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10260 daddu $tempreg,$tempreg,$breg
10261 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
10263 For GP relative symbols in 64bit address space we can use
10264 the same sequence as in 32bit address space. */
10265 if (HAVE_64BIT_SYMBOLS)
10267 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10268 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10270 relax_start (offset_expr.X_add_symbol);
10273 macro_build (&offset_expr, s, fmt, treg,
10274 BFD_RELOC_GPREL16, mips_gp_register);
10278 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10279 tempreg, breg, mips_gp_register);
10280 macro_build (&offset_expr, s, fmt, treg,
10281 BFD_RELOC_GPREL16, tempreg);
10286 if (used_at == 0 && mips_opts.at)
10288 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10289 BFD_RELOC_MIPS_HIGHEST);
10290 macro_build (&offset_expr, "lui", LUI_FMT, AT,
10292 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10293 tempreg, BFD_RELOC_MIPS_HIGHER);
10295 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
10296 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10297 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10298 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
10304 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10305 BFD_RELOC_MIPS_HIGHEST);
10306 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10307 tempreg, BFD_RELOC_MIPS_HIGHER);
10308 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10309 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
10310 tempreg, BFD_RELOC_HI16_S);
10311 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10313 macro_build (NULL, "daddu", "d,v,t",
10314 tempreg, tempreg, breg);
10315 macro_build (&offset_expr, s, fmt, treg,
10316 BFD_RELOC_LO16, tempreg);
10319 if (mips_relax.sequence)
10326 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10327 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10329 relax_start (offset_expr.X_add_symbol);
10330 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
10334 macro_build_lui (&offset_expr, tempreg);
10335 macro_build (&offset_expr, s, fmt, treg,
10336 BFD_RELOC_LO16, tempreg);
10337 if (mips_relax.sequence)
10342 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10343 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10345 relax_start (offset_expr.X_add_symbol);
10346 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10347 tempreg, breg, mips_gp_register);
10348 macro_build (&offset_expr, s, fmt, treg,
10349 BFD_RELOC_GPREL16, tempreg);
10352 macro_build_lui (&offset_expr, tempreg);
10353 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10354 tempreg, tempreg, breg);
10355 macro_build (&offset_expr, s, fmt, treg,
10356 BFD_RELOC_LO16, tempreg);
10357 if (mips_relax.sequence)
10361 else if (!mips_big_got)
10363 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10365 /* If this is a reference to an external symbol, we want
10366 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10368 <op> $treg,0($tempreg)
10370 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10372 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10373 <op> $treg,0($tempreg)
10375 For NewABI, we want
10376 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10377 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10379 If there is a base register, we add it to $tempreg before
10380 the <op>. If there is a constant, we stick it in the
10381 <op> instruction. We don't handle constants larger than
10382 16 bits, because we have no way to load the upper 16 bits
10383 (actually, we could handle them for the subset of cases
10384 in which we are not using $at). */
10385 gas_assert (offset_expr.X_op == O_symbol);
10388 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10389 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10391 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10392 tempreg, tempreg, breg);
10393 macro_build (&offset_expr, s, fmt, treg,
10394 BFD_RELOC_MIPS_GOT_OFST, tempreg);
10397 expr1.X_add_number = offset_expr.X_add_number;
10398 offset_expr.X_add_number = 0;
10399 if (expr1.X_add_number < -0x8000
10400 || expr1.X_add_number >= 0x8000)
10401 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10402 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10403 lw_reloc_type, mips_gp_register);
10405 relax_start (offset_expr.X_add_symbol);
10407 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10408 tempreg, BFD_RELOC_LO16);
10411 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10412 tempreg, tempreg, breg);
10413 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10415 else if (mips_big_got && !HAVE_NEWABI)
10419 /* If this is a reference to an external symbol, we want
10420 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10421 addu $tempreg,$tempreg,$gp
10422 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10423 <op> $treg,0($tempreg)
10425 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10427 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10428 <op> $treg,0($tempreg)
10429 If there is a base register, we add it to $tempreg before
10430 the <op>. If there is a constant, we stick it in the
10431 <op> instruction. We don't handle constants larger than
10432 16 bits, because we have no way to load the upper 16 bits
10433 (actually, we could handle them for the subset of cases
10434 in which we are not using $at). */
10435 gas_assert (offset_expr.X_op == O_symbol);
10436 expr1.X_add_number = offset_expr.X_add_number;
10437 offset_expr.X_add_number = 0;
10438 if (expr1.X_add_number < -0x8000
10439 || expr1.X_add_number >= 0x8000)
10440 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10441 gpdelay = reg_needs_delay (mips_gp_register);
10442 relax_start (offset_expr.X_add_symbol);
10443 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10444 BFD_RELOC_MIPS_GOT_HI16);
10445 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10447 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10448 BFD_RELOC_MIPS_GOT_LO16, tempreg);
10451 macro_build (NULL, "nop", "");
10452 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10453 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10455 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10456 tempreg, BFD_RELOC_LO16);
10460 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10461 tempreg, tempreg, breg);
10462 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10464 else if (mips_big_got && HAVE_NEWABI)
10466 /* If this is a reference to an external symbol, we want
10467 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10468 add $tempreg,$tempreg,$gp
10469 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10470 <op> $treg,<ofst>($tempreg)
10471 Otherwise, for local symbols, we want:
10472 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10473 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10474 gas_assert (offset_expr.X_op == O_symbol);
10475 expr1.X_add_number = offset_expr.X_add_number;
10476 offset_expr.X_add_number = 0;
10477 if (expr1.X_add_number < -0x8000
10478 || expr1.X_add_number >= 0x8000)
10479 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10480 relax_start (offset_expr.X_add_symbol);
10481 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
10482 BFD_RELOC_MIPS_GOT_HI16);
10483 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
10485 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10486 BFD_RELOC_MIPS_GOT_LO16, tempreg);
10488 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10489 tempreg, tempreg, breg);
10490 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
10493 offset_expr.X_add_number = expr1.X_add_number;
10494 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10495 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10497 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10498 tempreg, tempreg, breg);
10499 macro_build (&offset_expr, s, fmt, treg,
10500 BFD_RELOC_MIPS_GOT_OFST, tempreg);
10509 gas_assert (mips_opts.micromips);
10510 gas_assert (mips_opts.insn32);
10511 start_noreorder ();
10512 macro_build (NULL, "jr", "s", RA);
10513 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
10514 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
10519 gas_assert (mips_opts.micromips);
10520 gas_assert (mips_opts.insn32);
10521 macro_build (NULL, "jr", "s", sreg);
10522 if (mips_opts.noreorder)
10523 macro_build (NULL, "nop", "");
10528 load_register (treg, &imm_expr, 0);
10532 load_register (treg, &imm_expr, 1);
10536 if (imm_expr.X_op == O_constant)
10539 load_register (AT, &imm_expr, 0);
10540 macro_build (NULL, "mtc1", "t,G", AT, treg);
10545 gas_assert (offset_expr.X_op == O_symbol
10546 && strcmp (segment_name (S_GET_SEGMENT
10547 (offset_expr.X_add_symbol)),
10549 && offset_expr.X_add_number == 0);
10550 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
10551 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
10556 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10557 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10558 order 32 bits of the value and the low order 32 bits are either
10559 zero or in OFFSET_EXPR. */
10560 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10562 if (HAVE_64BIT_GPRS)
10563 load_register (treg, &imm_expr, 1);
10568 if (target_big_endian)
10580 load_register (hreg, &imm_expr, 0);
10583 if (offset_expr.X_op == O_absent)
10584 move_register (lreg, 0);
10587 gas_assert (offset_expr.X_op == O_constant);
10588 load_register (lreg, &offset_expr, 0);
10595 /* We know that sym is in the .rdata section. First we get the
10596 upper 16 bits of the address. */
10597 if (mips_pic == NO_PIC)
10599 macro_build_lui (&offset_expr, AT);
10604 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10605 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10609 /* Now we load the register(s). */
10610 if (HAVE_64BIT_GPRS)
10613 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
10618 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
10621 /* FIXME: How in the world do we deal with the possible
10623 offset_expr.X_add_number += 4;
10624 macro_build (&offset_expr, "lw", "t,o(b)",
10625 treg + 1, BFD_RELOC_LO16, AT);
10631 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10632 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10633 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10634 the value and the low order 32 bits are either zero or in
10636 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
10639 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
10640 if (HAVE_64BIT_FPRS)
10642 gas_assert (HAVE_64BIT_GPRS);
10643 macro_build (NULL, "dmtc1", "t,S", AT, treg);
10647 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
10648 if (offset_expr.X_op == O_absent)
10649 macro_build (NULL, "mtc1", "t,G", 0, treg);
10652 gas_assert (offset_expr.X_op == O_constant);
10653 load_register (AT, &offset_expr, 0);
10654 macro_build (NULL, "mtc1", "t,G", AT, treg);
10660 gas_assert (offset_expr.X_op == O_symbol
10661 && offset_expr.X_add_number == 0);
10662 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
10663 if (strcmp (s, ".lit8") == 0)
10665 breg = mips_gp_register;
10666 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
10667 offset_reloc[1] = BFD_RELOC_UNUSED;
10668 offset_reloc[2] = BFD_RELOC_UNUSED;
10672 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
10674 if (mips_pic != NO_PIC)
10675 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10676 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10679 /* FIXME: This won't work for a 64 bit address. */
10680 macro_build_lui (&offset_expr, AT);
10684 offset_reloc[0] = BFD_RELOC_LO16;
10685 offset_reloc[1] = BFD_RELOC_UNUSED;
10686 offset_reloc[2] = BFD_RELOC_UNUSED;
10693 * The MIPS assembler seems to check for X_add_number not
10694 * being double aligned and generating:
10695 * lui at,%hi(foo+1)
10697 * addiu at,at,%lo(foo+1)
10700 * But, the resulting address is the same after relocation so why
10701 * generate the extra instruction?
10703 /* Itbl support may require additional care here. */
10706 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
10715 gas_assert (!mips_opts.micromips);
10716 /* Itbl support may require additional care here. */
10719 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
10739 if (HAVE_64BIT_GPRS)
10749 if (HAVE_64BIT_GPRS)
10757 /* Even on a big endian machine $fn comes before $fn+1. We have
10758 to adjust when loading from memory. We set coproc if we must
10759 load $fn+1 first. */
10760 /* Itbl support may require additional care here. */
10761 if (!target_big_endian)
10764 if (small_offset_p (0, align, 16))
10767 if (!small_offset_p (4, align, 16))
10769 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
10770 -1, offset_reloc[0], offset_reloc[1],
10772 expr1.X_add_number = 0;
10776 offset_reloc[0] = BFD_RELOC_LO16;
10777 offset_reloc[1] = BFD_RELOC_UNUSED;
10778 offset_reloc[2] = BFD_RELOC_UNUSED;
10780 if (strcmp (s, "lw") == 0 && treg == breg)
10782 ep->X_add_number += 4;
10783 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
10784 offset_reloc[1], offset_reloc[2], breg);
10785 ep->X_add_number -= 4;
10786 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
10787 offset_reloc[1], offset_reloc[2], breg);
10791 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
10792 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10794 ep->X_add_number += 4;
10795 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
10796 offset_reloc[0], offset_reloc[1], offset_reloc[2],
10802 if (offset_expr.X_op != O_symbol
10803 && offset_expr.X_op != O_constant)
10805 as_bad (_("Expression too complex"));
10806 offset_expr.X_op = O_constant;
10809 if (HAVE_32BIT_ADDRESSES
10810 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10814 sprintf_vma (value, offset_expr.X_add_number);
10815 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10818 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
10820 /* If this is a reference to a GP relative symbol, we want
10821 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
10822 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
10823 If we have a base register, we use this
10825 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
10826 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
10827 If this is not a GP relative symbol, we want
10828 lui $at,<sym> (BFD_RELOC_HI16_S)
10829 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10830 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10831 If there is a base register, we add it to $at after the
10832 lui instruction. If there is a constant, we always use
10834 if (offset_expr.X_op == O_symbol
10835 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10836 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10838 relax_start (offset_expr.X_add_symbol);
10841 tempreg = mips_gp_register;
10845 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10846 AT, breg, mips_gp_register);
10851 /* Itbl support may require additional care here. */
10852 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10853 BFD_RELOC_GPREL16, tempreg);
10854 offset_expr.X_add_number += 4;
10856 /* Set mips_optimize to 2 to avoid inserting an
10858 hold_mips_optimize = mips_optimize;
10860 /* Itbl support may require additional care here. */
10861 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10862 BFD_RELOC_GPREL16, tempreg);
10863 mips_optimize = hold_mips_optimize;
10867 offset_expr.X_add_number -= 4;
10870 if (offset_high_part (offset_expr.X_add_number, 16)
10871 != offset_high_part (offset_expr.X_add_number + 4, 16))
10873 load_address (AT, &offset_expr, &used_at);
10874 offset_expr.X_op = O_constant;
10875 offset_expr.X_add_number = 0;
10878 macro_build_lui (&offset_expr, AT);
10880 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10881 /* Itbl support may require additional care here. */
10882 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10883 BFD_RELOC_LO16, AT);
10884 /* FIXME: How do we handle overflow here? */
10885 offset_expr.X_add_number += 4;
10886 /* Itbl support may require additional care here. */
10887 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10888 BFD_RELOC_LO16, AT);
10889 if (mips_relax.sequence)
10892 else if (!mips_big_got)
10894 /* If this is a reference to an external symbol, we want
10895 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10898 <op> $treg+1,4($at)
10900 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10902 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10903 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10904 If there is a base register we add it to $at before the
10905 lwc1 instructions. If there is a constant we include it
10906 in the lwc1 instructions. */
10908 expr1.X_add_number = offset_expr.X_add_number;
10909 if (expr1.X_add_number < -0x8000
10910 || expr1.X_add_number >= 0x8000 - 4)
10911 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10912 load_got_offset (AT, &offset_expr);
10915 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10917 /* Set mips_optimize to 2 to avoid inserting an undesired
10919 hold_mips_optimize = mips_optimize;
10922 /* Itbl support may require additional care here. */
10923 relax_start (offset_expr.X_add_symbol);
10924 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
10925 BFD_RELOC_LO16, AT);
10926 expr1.X_add_number += 4;
10927 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
10928 BFD_RELOC_LO16, AT);
10930 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
10931 BFD_RELOC_LO16, AT);
10932 offset_expr.X_add_number += 4;
10933 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
10934 BFD_RELOC_LO16, AT);
10937 mips_optimize = hold_mips_optimize;
10939 else if (mips_big_got)
10943 /* If this is a reference to an external symbol, we want
10944 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10946 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
10949 <op> $treg+1,4($at)
10951 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10953 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
10954 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
10955 If there is a base register we add it to $at before the
10956 lwc1 instructions. If there is a constant we include it
10957 in the lwc1 instructions. */
10959 expr1.X_add_number = offset_expr.X_add_number;
10960 offset_expr.X_add_number = 0;
10961 if (expr1.X_add_number < -0x8000
10962 || expr1.X_add_number >= 0x8000 - 4)
10963 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10964 gpdelay = reg_needs_delay (mips_gp_register);
10965 relax_start (offset_expr.X_add_symbol);
10966 macro_build (&offset_expr, "lui", LUI_FMT,
10967 AT, BFD_RELOC_MIPS_GOT_HI16);
10968 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10969 AT, AT, mips_gp_register);
10970 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10971 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
10974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10975 /* Itbl support may require additional care here. */
10976 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
10977 BFD_RELOC_LO16, AT);
10978 expr1.X_add_number += 4;
10980 /* Set mips_optimize to 2 to avoid inserting an undesired
10982 hold_mips_optimize = mips_optimize;
10984 /* Itbl support may require additional care here. */
10985 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
10986 BFD_RELOC_LO16, AT);
10987 mips_optimize = hold_mips_optimize;
10988 expr1.X_add_number -= 4;
10991 offset_expr.X_add_number = expr1.X_add_number;
10993 macro_build (NULL, "nop", "");
10994 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
10995 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10998 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
10999 /* Itbl support may require additional care here. */
11000 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
11001 BFD_RELOC_LO16, AT);
11002 offset_expr.X_add_number += 4;
11004 /* Set mips_optimize to 2 to avoid inserting an undesired
11006 hold_mips_optimize = mips_optimize;
11008 /* Itbl support may require additional care here. */
11009 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
11010 BFD_RELOC_LO16, AT);
11011 mips_optimize = hold_mips_optimize;
11030 /* New code added to support COPZ instructions.
11031 This code builds table entries out of the macros in mip_opcodes.
11032 R4000 uses interlocks to handle coproc delays.
11033 Other chips (like the R3000) require nops to be inserted for delays.
11035 FIXME: Currently, we require that the user handle delays.
11036 In order to fill delay slots for non-interlocked chips,
11037 we must have a way to specify delays based on the coprocessor.
11038 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11039 What are the side-effects of the cop instruction?
11040 What cache support might we have and what are its effects?
11041 Both coprocessor & memory require delays. how long???
11042 What registers are read/set/modified?
11044 If an itbl is provided to interpret cop instructions,
11045 this knowledge can be encoded in the itbl spec. */
11059 gas_assert (!mips_opts.micromips);
11060 /* For now we just do C (same as Cz). The parameter will be
11061 stored in insn_opcode by mips_ip. */
11062 macro_build (NULL, s, "C", (int) ip->insn_opcode);
11066 move_register (dreg, sreg);
11070 gas_assert (mips_opts.micromips);
11071 gas_assert (mips_opts.insn32);
11072 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
11073 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
11074 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
11075 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
11076 move_register (dreg, sreg);
11077 move_register (breg, treg);
11083 if (mips_opts.arch == CPU_R5900)
11085 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
11089 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
11090 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11097 /* The MIPS assembler some times generates shifts and adds. I'm
11098 not trying to be that fancy. GCC should do this for us
11101 load_register (AT, &imm_expr, dbl);
11102 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
11103 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11116 start_noreorder ();
11119 load_register (AT, &imm_expr, dbl);
11120 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
11121 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11122 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
11123 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11125 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
11128 if (mips_opts.micromips)
11129 micromips_label_expr (&label_expr);
11131 label_expr.X_add_number = 8;
11132 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
11133 macro_build (NULL, "nop", "");
11134 macro_build (NULL, "break", BRK_FMT, 6);
11135 if (mips_opts.micromips)
11136 micromips_add_label ();
11139 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11152 start_noreorder ();
11155 load_register (AT, &imm_expr, dbl);
11156 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
11157 sreg, imm ? AT : treg);
11158 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11159 macro_build (NULL, "mflo", MFHL_FMT, dreg);
11161 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
11164 if (mips_opts.micromips)
11165 micromips_label_expr (&label_expr);
11167 label_expr.X_add_number = 8;
11168 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
11169 macro_build (NULL, "nop", "");
11170 macro_build (NULL, "break", BRK_FMT, 6);
11171 if (mips_opts.micromips)
11172 micromips_add_label ();
11178 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11189 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
11190 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
11194 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
11195 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
11196 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
11197 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11201 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11212 macro_build (NULL, "negu", "d,w", tempreg, treg);
11213 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
11217 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
11218 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
11219 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
11220 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11229 if (imm_expr.X_op != O_constant)
11230 as_bad (_("Improper rotate count"));
11231 rot = imm_expr.X_add_number & 0x3f;
11232 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11234 rot = (64 - rot) & 0x3f;
11236 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
11238 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
11243 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
11246 l = (rot < 0x20) ? "dsll" : "dsll32";
11247 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
11250 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
11251 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11252 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11260 if (imm_expr.X_op != O_constant)
11261 as_bad (_("Improper rotate count"));
11262 rot = imm_expr.X_add_number & 0x1f;
11263 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11265 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
11270 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
11274 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
11275 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11276 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11281 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11283 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
11287 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
11288 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
11289 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
11290 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11294 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11296 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
11300 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
11301 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
11302 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
11303 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11312 if (imm_expr.X_op != O_constant)
11313 as_bad (_("Improper rotate count"));
11314 rot = imm_expr.X_add_number & 0x3f;
11315 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11318 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
11320 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
11325 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
11328 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
11329 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
11332 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
11333 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11334 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11342 if (imm_expr.X_op != O_constant)
11343 as_bad (_("Improper rotate count"));
11344 rot = imm_expr.X_add_number & 0x1f;
11345 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
11347 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
11352 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
11356 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
11357 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
11358 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
11364 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
11365 else if (treg == 0)
11366 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11369 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
11370 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
11375 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11377 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11382 as_warn (_("Instruction %s: result is always false"),
11383 ip->insn_mo->name);
11384 move_register (dreg, 0);
11387 if (CPU_HAS_SEQ (mips_opts.arch)
11388 && -512 <= imm_expr.X_add_number
11389 && imm_expr.X_add_number < 512)
11391 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
11392 (int) imm_expr.X_add_number);
11395 if (imm_expr.X_op == O_constant
11396 && imm_expr.X_add_number >= 0
11397 && imm_expr.X_add_number < 0x10000)
11399 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
11401 else if (imm_expr.X_op == O_constant
11402 && imm_expr.X_add_number > -0x8000
11403 && imm_expr.X_add_number < 0)
11405 imm_expr.X_add_number = -imm_expr.X_add_number;
11406 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
11407 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11409 else if (CPU_HAS_SEQ (mips_opts.arch))
11412 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11413 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
11418 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11419 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
11422 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
11425 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
11431 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
11432 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11435 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
11437 if (imm_expr.X_op == O_constant
11438 && imm_expr.X_add_number >= -0x8000
11439 && imm_expr.X_add_number < 0x8000)
11441 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
11442 dreg, sreg, BFD_RELOC_LO16);
11446 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11447 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
11451 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11454 case M_SGT: /* sreg > treg <==> treg < sreg */
11460 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
11463 case M_SGT_I: /* sreg > I <==> I < sreg */
11470 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11471 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
11474 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
11480 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
11481 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11484 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
11491 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11492 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
11493 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
11497 if (imm_expr.X_op == O_constant
11498 && imm_expr.X_add_number >= -0x8000
11499 && imm_expr.X_add_number < 0x8000)
11501 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11505 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11506 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
11510 if (imm_expr.X_op == O_constant
11511 && imm_expr.X_add_number >= -0x8000
11512 && imm_expr.X_add_number < 0x8000)
11514 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
11519 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11520 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
11525 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
11526 else if (treg == 0)
11527 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
11530 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
11531 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
11536 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
11538 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
11543 as_warn (_("Instruction %s: result is always true"),
11544 ip->insn_mo->name);
11545 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
11546 dreg, 0, BFD_RELOC_LO16);
11549 if (CPU_HAS_SEQ (mips_opts.arch)
11550 && -512 <= imm_expr.X_add_number
11551 && imm_expr.X_add_number < 512)
11553 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
11554 (int) imm_expr.X_add_number);
11557 if (imm_expr.X_op == O_constant
11558 && imm_expr.X_add_number >= 0
11559 && imm_expr.X_add_number < 0x10000)
11561 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
11563 else if (imm_expr.X_op == O_constant
11564 && imm_expr.X_add_number > -0x8000
11565 && imm_expr.X_add_number < 0)
11567 imm_expr.X_add_number = -imm_expr.X_add_number;
11568 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
11569 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11571 else if (CPU_HAS_SEQ (mips_opts.arch))
11574 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11575 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
11580 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11581 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
11584 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
11599 if (!mips_opts.micromips)
11601 if (imm_expr.X_op == O_constant
11602 && imm_expr.X_add_number > -0x200
11603 && imm_expr.X_add_number <= 0x200)
11605 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
11614 if (imm_expr.X_op == O_constant
11615 && imm_expr.X_add_number > -0x8000
11616 && imm_expr.X_add_number <= 0x8000)
11618 imm_expr.X_add_number = -imm_expr.X_add_number;
11619 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
11624 load_register (AT, &imm_expr, dbl);
11625 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
11647 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
11648 macro_build (NULL, s, "s,t", sreg, AT);
11653 gas_assert (!mips_opts.micromips);
11654 gas_assert (mips_opts.isa == ISA_MIPS1);
11656 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
11657 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
11660 * Is the double cfc1 instruction a bug in the mips assembler;
11661 * or is there a reason for it?
11663 start_noreorder ();
11664 macro_build (NULL, "cfc1", "t,G", treg, RA);
11665 macro_build (NULL, "cfc1", "t,G", treg, RA);
11666 macro_build (NULL, "nop", "");
11667 expr1.X_add_number = 3;
11668 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
11669 expr1.X_add_number = 2;
11670 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
11671 macro_build (NULL, "ctc1", "t,G", AT, RA);
11672 macro_build (NULL, "nop", "");
11673 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
11675 macro_build (NULL, "ctc1", "t,G", treg, RA);
11676 macro_build (NULL, "nop", "");
11693 offbits = (mips_opts.micromips ? 12 : 16);
11699 offbits = (mips_opts.micromips ? 12 : 16);
11711 offbits = (mips_opts.micromips ? 12 : 16);
11718 offbits = (mips_opts.micromips ? 12 : 16);
11723 large_offset = !small_offset_p (off, align, offbits);
11725 expr1.X_add_number = 0;
11730 if (small_offset_p (0, align, 16))
11731 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
11732 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
11735 load_address (tempreg, ep, &used_at);
11737 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11738 tempreg, tempreg, breg);
11740 offset_reloc[0] = BFD_RELOC_LO16;
11741 offset_reloc[1] = BFD_RELOC_UNUSED;
11742 offset_reloc[2] = BFD_RELOC_UNUSED;
11747 else if (!ust && treg == breg)
11758 if (!target_big_endian)
11759 ep->X_add_number += off;
11761 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
11763 macro_build (ep, s, "t,o(b)", tempreg, -1,
11764 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11766 if (!target_big_endian)
11767 ep->X_add_number -= off;
11769 ep->X_add_number += off;
11771 macro_build (NULL, s2, "t,~(b)",
11772 tempreg, (int) ep->X_add_number, breg);
11774 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11775 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11777 /* If necessary, move the result in tempreg to the final destination. */
11778 if (!ust && treg != tempreg)
11780 /* Protect second load's delay slot. */
11782 move_register (treg, tempreg);
11788 if (target_big_endian == ust)
11789 ep->X_add_number += off;
11790 tempreg = ust || large_offset ? treg : AT;
11791 macro_build (ep, s, "t,o(b)", tempreg, -1,
11792 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11794 /* For halfword transfers we need a temporary register to shuffle
11795 bytes. Unfortunately for M_USH_A we have none available before
11796 the next store as AT holds the base address. We deal with this
11797 case by clobbering TREG and then restoring it as with ULH. */
11798 tempreg = ust == large_offset ? treg : AT;
11800 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
11802 if (target_big_endian == ust)
11803 ep->X_add_number -= off;
11805 ep->X_add_number += off;
11806 macro_build (ep, s2, "t,o(b)", tempreg, -1,
11807 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
11809 /* For M_USH_A re-retrieve the LSB. */
11810 if (ust && large_offset)
11812 if (target_big_endian)
11813 ep->X_add_number += off;
11815 ep->X_add_number -= off;
11816 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
11817 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
11819 /* For ULH and M_USH_A OR the LSB in. */
11820 if (!ust || large_offset)
11822 tempreg = !large_offset ? AT : treg;
11823 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
11824 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
11829 /* FIXME: Check if this is one of the itbl macros, since they
11830 are added dynamically. */
11831 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
11834 if (!mips_opts.at && used_at)
11835 as_bad (_("Macro used $at after \".set noat\""));
11838 /* Implement macros in mips16 mode. */
11841 mips16_macro (struct mips_cl_insn *ip)
11844 int xreg, yreg, zreg, tmp;
11847 const char *s, *s2, *s3;
11849 mask = ip->insn_mo->mask;
11851 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
11852 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
11853 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
11855 expr1.X_op = O_constant;
11856 expr1.X_op_symbol = NULL;
11857 expr1.X_add_symbol = NULL;
11858 expr1.X_add_number = 1;
11877 start_noreorder ();
11878 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
11879 expr1.X_add_number = 2;
11880 macro_build (&expr1, "bnez", "x,p", yreg);
11881 macro_build (NULL, "break", "6", 7);
11883 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
11884 since that causes an overflow. We should do that as well,
11885 but I don't see how to do the comparisons without a temporary
11888 macro_build (NULL, s, "x", zreg);
11907 start_noreorder ();
11908 macro_build (NULL, s, "0,x,y", xreg, yreg);
11909 expr1.X_add_number = 2;
11910 macro_build (&expr1, "bnez", "x,p", yreg);
11911 macro_build (NULL, "break", "6", 7);
11913 macro_build (NULL, s2, "x", zreg);
11919 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
11920 macro_build (NULL, "mflo", "x", zreg);
11928 if (imm_expr.X_op != O_constant)
11929 as_bad (_("Unsupported large constant"));
11930 imm_expr.X_add_number = -imm_expr.X_add_number;
11931 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
11935 if (imm_expr.X_op != O_constant)
11936 as_bad (_("Unsupported large constant"));
11937 imm_expr.X_add_number = -imm_expr.X_add_number;
11938 macro_build (&imm_expr, "addiu", "x,k", xreg);
11942 if (imm_expr.X_op != O_constant)
11943 as_bad (_("Unsupported large constant"));
11944 imm_expr.X_add_number = -imm_expr.X_add_number;
11945 macro_build (&imm_expr, "daddiu", "y,j", yreg);
11967 goto do_reverse_branch;
11971 goto do_reverse_branch;
11983 goto do_reverse_branch;
11994 macro_build (NULL, s, "x,y", xreg, yreg);
11995 macro_build (&offset_expr, s2, "p");
12022 goto do_addone_branch_i;
12027 goto do_addone_branch_i;
12042 goto do_addone_branch_i;
12048 do_addone_branch_i:
12049 if (imm_expr.X_op != O_constant)
12050 as_bad (_("Unsupported large constant"));
12051 ++imm_expr.X_add_number;
12054 macro_build (&imm_expr, s, s3, xreg);
12055 macro_build (&offset_expr, s2, "p");
12059 expr1.X_add_number = 0;
12060 macro_build (&expr1, "slti", "x,8", yreg);
12062 macro_build (NULL, "move", "y,X", xreg, mips16_to_32_reg_map[yreg]);
12063 expr1.X_add_number = 2;
12064 macro_build (&expr1, "bteqz", "p");
12065 macro_build (NULL, "neg", "x,w", xreg, xreg);
12070 /* Assemble an instruction into its binary format. If the instruction
12071 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12072 associated with "I", "+I" and "A" operands respectively. Otherwise
12073 store the value of the relocatable field (if any) in offset_expr.
12074 In both cases set offset_reloc to the relocation operators applied
12078 mips_ip (char *str, struct mips_cl_insn *ip)
12080 bfd_boolean wrong_delay_slot_insns = FALSE;
12081 bfd_boolean need_delay_slot_ok = TRUE;
12082 struct mips_opcode *firstinsn = NULL;
12083 const struct mips_opcode *past;
12084 struct hash_control *hash;
12087 struct mips_opcode *insn;
12093 const struct mips_operand *operand;
12094 struct mips_arg_info arg;
12095 struct mips_operand_token *tokens;
12096 bfd_boolean optional_reg;
12100 if (mips_opts.micromips)
12102 hash = micromips_op_hash;
12103 past = µmips_opcodes[bfd_micromips_num_opcodes];
12108 past = &mips_opcodes[NUMOPCODES];
12110 forced_insn_length = 0;
12113 /* We first try to match an instruction up to a space or to the end. */
12114 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12117 /* Make a copy of the instruction so that we can fiddle with it. */
12118 name = alloca (end + 1);
12119 memcpy (name, str, end);
12124 insn = (struct mips_opcode *) hash_find (hash, name);
12126 if (insn != NULL || !mips_opts.micromips)
12128 if (forced_insn_length)
12131 /* See if there's an instruction size override suffix,
12132 either `16' or `32', at the end of the mnemonic proper,
12133 that defines the operation, i.e. before the first `.'
12134 character if any. Strip it and retry. */
12135 dot = strchr (name, '.');
12136 opend = dot != NULL ? dot - name : end;
12139 if (name[opend - 2] == '1' && name[opend - 1] == '6')
12140 forced_insn_length = 2;
12141 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12142 forced_insn_length = 4;
12145 memcpy (name + opend - 2, name + opend, end - opend + 1);
12149 insn_error = _("Unrecognized opcode");
12153 if (strcmp (name, "li.s") == 0)
12155 else if (strcmp (name, "li.d") == 0)
12159 tokens = mips_parse_arguments (str + end, format);
12163 /* For microMIPS instructions placed in a fixed-length branch delay slot
12164 we make up to two passes over the relevant fragment of the opcode
12165 table. First we try instructions that meet the delay slot's length
12166 requirement. If none matched, then we retry with the remaining ones
12167 and if one matches, then we use it and then issue an appropriate
12168 warning later on. */
12171 bfd_boolean delay_slot_ok;
12172 bfd_boolean size_ok;
12174 bfd_boolean more_alts;
12176 gas_assert (strcmp (insn->name, name) == 0);
12178 ok = is_opcode_valid (insn);
12179 size_ok = is_size_valid (insn);
12180 delay_slot_ok = is_delay_slot_valid (insn);
12181 if (!delay_slot_ok && !wrong_delay_slot_insns)
12184 wrong_delay_slot_insns = TRUE;
12186 more_alts = (insn + 1 < past
12187 && strcmp (insn[0].name, insn[1].name) == 0);
12188 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
12190 static char buf[256];
12197 if (wrong_delay_slot_insns && need_delay_slot_ok)
12199 gas_assert (firstinsn);
12200 need_delay_slot_ok = FALSE;
12206 obstack_free (&mips_operand_tokens, tokens);
12211 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
12212 mips_cpu_info_from_arch (mips_opts.arch)->name,
12213 mips_cpu_info_from_isa (mips_opts.isa)->name);
12214 else if (mips_opts.insn32)
12215 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
12217 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
12218 8 * forced_insn_length);
12224 imm_expr.X_op = O_absent;
12225 imm2_expr.X_op = O_absent;
12226 offset_expr.X_op = O_absent;
12227 offset_reloc[0] = BFD_RELOC_UNUSED;
12228 offset_reloc[1] = BFD_RELOC_UNUSED;
12229 offset_reloc[2] = BFD_RELOC_UNUSED;
12231 create_insn (ip, insn);
12233 memset (&arg, 0, sizeof (arg));
12235 arg.token = tokens;
12237 arg.last_regno = ILLEGAL_REG;
12238 arg.dest_regno = ILLEGAL_REG;
12239 arg.soft_match = (more_alts
12240 || (wrong_delay_slot_insns && need_delay_slot_ok));
12241 for (args = insn->args;; ++args)
12243 if (arg.token->type == OT_END)
12245 /* Handle unary instructions in which only one operand is given.
12246 The source is then the same as the destination. */
12247 if (arg.opnum == 1 && *args == ',')
12255 arg.token = tokens;
12260 /* Treat elided base registers as $0. */
12261 if (strcmp (args, "(b)") == 0)
12264 /* Fail the match if there were too few operands. */
12268 /* Successful match. */
12269 if (arg.dest_regno == arg.last_regno
12270 && strncmp (ip->insn_mo->name, "jalr", 4) == 0)
12272 if (arg.opnum == 2)
12273 as_bad (_("Source and destination must be different"));
12274 else if (arg.last_regno == 31)
12275 as_bad (_("A destination register must be supplied"));
12277 check_completed_insn (&arg);
12278 obstack_free (&mips_operand_tokens, tokens);
12282 /* Fail the match if the line has too many operands. */
12286 /* Handle characters that need to match exactly. */
12287 if (*args == '(' || *args == ')' || *args == ',')
12289 if (match_char (&arg, *args))
12294 /* Handle special macro operands. Work out the properties of
12297 arg.lax_max = FALSE;
12298 optional_reg = FALSE;
12317 /* If these integer forms come last, there is no other
12318 form of the instruction that could match. Prefer to
12319 give detailed error messages where possible. */
12321 arg.soft_match = FALSE;
12325 /* "+I" is like "I", except that imm2_expr is used. */
12326 if (match_const_int (&arg, &imm2_expr.X_add_number, 0))
12327 imm2_expr.X_op = O_constant;
12329 insn_error = _("absolute expression required");
12330 if (HAVE_32BIT_GPRS)
12331 normalize_constant_expr (&imm2_expr);
12336 *offset_reloc = BFD_RELOC_MIPS_JMP;
12366 /* If these integer forms come last, there is no other
12367 form of the instruction that could match. Prefer to
12368 give detailed error messages where possible. */
12370 arg.soft_match = FALSE;
12378 /* We have already matched a comma by this point, so the register
12379 is only optional if there is another operand to come. */
12380 gas_assert (arg.opnum == 2);
12381 optional_reg = (args[1] == ',');
12385 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
12386 imm_expr.X_op = O_constant;
12388 insn_error = _("absolute expression required");
12389 if (HAVE_32BIT_GPRS)
12390 normalize_constant_expr (&imm_expr);
12394 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
12396 /* Assume that the offset has been elided and that what
12397 we saw was a base register. The match will fail later
12398 if that assumption turns out to be wrong. */
12399 offset_expr.X_op = O_constant;
12400 offset_expr.X_add_number = 0;
12402 else if (match_expression (&arg, &offset_expr, offset_reloc))
12403 normalize_address_expr (&offset_expr);
12405 insn_error = _("absolute expression required");
12409 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12411 insn_error = _("floating-point expression required");
12415 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12417 insn_error = _("floating-point expression required");
12421 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12423 insn_error = _("floating-point expression required");
12427 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
12429 insn_error = _("floating-point expression required");
12432 /* ??? This is the traditional behavior, but is flaky if
12433 there are alternative versions of the same instruction
12434 for different subarchitectures. The next alternative
12435 might not be suitable. */
12437 /* For compatibility with older assemblers, we accept
12438 0x8000-0xffff as signed 16-bit numbers when only
12439 signed numbers are allowed. */
12440 arg.lax_max = !more_alts;
12442 /* Only accept non-constant operands if this is the
12443 final alternative. Later alternatives might include
12444 a macro implementation. */
12445 arg.allow_nonconst = !more_alts;
12449 /* There are no macro implementations for out-of-range values. */
12450 arg.allow_nonconst = TRUE;
12454 /* There should always be a macro implementation. */
12455 arg.allow_nonconst = FALSE;
12459 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12463 *offset_reloc = BFD_RELOC_MIPS_JMP;
12467 gas_assert (mips_opts.micromips);
12474 /* We have already matched a comma by this point,
12475 so the register is only optional if there is another
12476 operand to come. */
12477 gas_assert (arg.opnum == 2);
12478 optional_reg = (args[2] == ',');
12483 if (!forced_insn_length)
12484 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12486 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12488 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12494 operand = (mips_opts.micromips
12495 ? decode_micromips_operand (args)
12496 : decode_mips_operand (args));
12501 && (arg.token[0].type != OT_REG
12502 || arg.token[1].type == OT_END))
12504 /* Assume that the register has been elided and is the
12505 same as the first operand. */
12506 arg.token = tokens;
12510 if (!match_operand (&arg, operand))
12513 /* Skip prefixes. */
12514 if (*args == '+' || *args == 'm')
12519 /* Args don't match. */
12520 insn_error = _("Illegal operands");
12526 if (wrong_delay_slot_insns && need_delay_slot_ok)
12528 gas_assert (firstinsn);
12529 need_delay_slot_ok = FALSE;
12534 obstack_free (&mips_operand_tokens, tokens);
12539 /* As for mips_ip, but used when assembling MIPS16 code.
12540 Also set forced_insn_length to the resulting instruction size in
12541 bytes if the user explicitly requested a small or extended instruction. */
12544 mips16_ip (char *str, struct mips_cl_insn *ip)
12548 struct mips_opcode *insn;
12549 const struct mips_operand *operand;
12550 const struct mips_operand *ext_operand;
12551 struct mips_arg_info arg;
12552 struct mips_operand_token *tokens;
12553 bfd_boolean optional_reg;
12557 forced_insn_length = 0;
12559 for (s = str; ISLOWER (*s); ++s)
12571 if (s[1] == 't' && s[2] == ' ')
12574 forced_insn_length = 2;
12578 else if (s[1] == 'e' && s[2] == ' ')
12581 forced_insn_length = 4;
12585 /* Fall through. */
12587 insn_error = _("unknown opcode");
12591 if (mips_opts.noautoextend && !forced_insn_length)
12592 forced_insn_length = 2;
12594 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
12596 insn_error = _("unrecognized opcode");
12600 tokens = mips_parse_arguments (s, 0);
12607 bfd_boolean more_alts;
12610 gas_assert (strcmp (insn->name, str) == 0);
12612 ok = is_opcode_valid_16 (insn);
12613 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
12614 && strcmp (insn[0].name, insn[1].name) == 0);
12626 static char buf[100];
12628 _("Opcode not supported on this processor: %s (%s)"),
12629 mips_cpu_info_from_arch (mips_opts.arch)->name,
12630 mips_cpu_info_from_isa (mips_opts.isa)->name);
12633 obstack_free (&mips_operand_tokens, tokens);
12638 create_insn (ip, insn);
12639 imm_expr.X_op = O_absent;
12640 imm2_expr.X_op = O_absent;
12641 offset_expr.X_op = O_absent;
12642 offset_reloc[0] = BFD_RELOC_UNUSED;
12643 offset_reloc[1] = BFD_RELOC_UNUSED;
12644 offset_reloc[2] = BFD_RELOC_UNUSED;
12647 memset (&arg, 0, sizeof (arg));
12649 arg.token = tokens;
12651 arg.last_regno = ILLEGAL_REG;
12652 arg.dest_regno = ILLEGAL_REG;
12653 arg.soft_match = more_alts;
12655 for (args = insn->args; 1; ++args)
12659 if (arg.token->type == OT_END)
12663 /* Handle unary instructions in which only one operand is given.
12664 The source is then the same as the destination. */
12665 if (arg.opnum == 1 && *args == ',')
12670 arg.token = tokens;
12675 /* Fail the match if there were too few operands. */
12679 /* Successful match. Stuff the immediate value in now, if
12681 if (insn->pinfo == INSN_MACRO)
12683 gas_assert (relax_char == 0 || relax_char == 'p');
12684 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
12686 else if (relax_char
12687 && offset_expr.X_op == O_constant
12688 && calculate_reloc (*offset_reloc,
12689 offset_expr.X_add_number,
12692 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
12693 forced_insn_length, &ip->insn_opcode);
12694 offset_expr.X_op = O_absent;
12695 *offset_reloc = BFD_RELOC_UNUSED;
12697 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
12699 if (forced_insn_length == 2)
12700 as_bad (_("invalid unextended operand value"));
12701 forced_insn_length = 4;
12702 ip->insn_opcode |= MIPS16_EXTEND;
12704 else if (relax_char)
12705 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
12707 check_completed_insn (&arg);
12708 obstack_free (&mips_operand_tokens, tokens);
12712 /* Fail the match if the line has too many operands. */
12716 /* Handle characters that need to match exactly. */
12717 if (*args == '(' || *args == ')' || *args == ',')
12719 if (match_char (&arg, *args))
12725 optional_reg = FALSE;
12731 optional_reg = (args[1] == ',');
12743 if (match_const_int (&arg, &imm_expr.X_add_number, 0))
12744 imm_expr.X_op = O_constant;
12746 insn_error = _("absolute expression required");
12747 if (HAVE_32BIT_GPRS)
12748 normalize_constant_expr (&imm_expr);
12753 *offset_reloc = BFD_RELOC_MIPS16_JMP;
12754 ip->insn_opcode <<= 16;
12758 operand = decode_mips16_operand (c, FALSE);
12762 /* '6' is a special case. It is used for BREAK and SDBBP,
12763 whose operands are only meaningful to the software that decodes
12764 them. This means that there is no architectural reason why
12765 they cannot be prefixed by EXTEND, but in practice,
12766 exception handlers will only look at the instruction
12767 itself. We therefore allow '6' to be extended when
12768 disassembling but not when assembling. */
12769 if (operand->type != OP_PCREL && c != '6')
12771 ext_operand = decode_mips16_operand (c, TRUE);
12772 if (operand != ext_operand)
12774 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
12776 offset_expr.X_op = O_constant;
12777 offset_expr.X_add_number = 0;
12782 /* We need the OT_INTEGER check because some MIPS16
12783 immediate variants are listed before the register ones. */
12784 if (arg.token->type != OT_INTEGER
12785 || !match_expression (&arg, &offset_expr, offset_reloc))
12788 /* '8' is used for SLTI(U) and has traditionally not
12789 been allowed to take relocation operators. */
12790 if (offset_reloc[0] != BFD_RELOC_UNUSED
12791 && (ext_operand->size != 16 || c == '8'))
12800 && (arg.token[0].type != OT_REG
12801 || arg.token[1].type == OT_END))
12803 /* Assume that the register has been elided and is the
12804 same as the first operand. */
12805 arg.token = tokens;
12809 if (!match_operand (&arg, operand))
12814 /* Args don't match. */
12821 insn_error = _("illegal operands");
12823 obstack_free (&mips_operand_tokens, tokens);
12828 /* Marshal immediate value VAL for an extended MIPS16 instruction.
12829 NBITS is the number of significant bits in VAL. */
12831 static unsigned long
12832 mips16_immed_extend (offsetT val, unsigned int nbits)
12837 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
12840 else if (nbits == 15)
12842 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
12847 extval = ((val & 0x1f) << 6) | (val & 0x20);
12850 return (extval << 16) | val;
12853 /* Like decode_mips16_operand, but require the operand to be defined and
12854 require it to be an integer. */
12856 static const struct mips_int_operand *
12857 mips16_immed_operand (int type, bfd_boolean extended_p)
12859 const struct mips_operand *operand;
12861 operand = decode_mips16_operand (type, extended_p);
12862 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
12864 return (const struct mips_int_operand *) operand;
12867 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
12870 mips16_immed_in_range_p (const struct mips_int_operand *operand,
12871 bfd_reloc_code_real_type reloc, offsetT sval)
12873 int min_val, max_val;
12875 min_val = mips_int_operand_min (operand);
12876 max_val = mips_int_operand_max (operand);
12877 if (reloc != BFD_RELOC_UNUSED)
12880 sval = SEXT_16BIT (sval);
12885 return (sval >= min_val
12887 && (sval & ((1 << operand->shift) - 1)) == 0);
12890 /* Install immediate value VAL into MIPS16 instruction *INSN,
12891 extending it if necessary. The instruction in *INSN may
12892 already be extended.
12894 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
12895 if none. In the former case, VAL is a 16-bit number with no
12896 defined signedness.
12898 TYPE is the type of the immediate field. USER_INSN_LENGTH
12899 is the length that the user requested, or 0 if none. */
12902 mips16_immed (char *file, unsigned int line, int type,
12903 bfd_reloc_code_real_type reloc, offsetT val,
12904 unsigned int user_insn_length, unsigned long *insn)
12906 const struct mips_int_operand *operand;
12907 unsigned int uval, length;
12909 operand = mips16_immed_operand (type, FALSE);
12910 if (!mips16_immed_in_range_p (operand, reloc, val))
12912 /* We need an extended instruction. */
12913 if (user_insn_length == 2)
12914 as_bad_where (file, line, _("invalid unextended operand value"));
12916 *insn |= MIPS16_EXTEND;
12918 else if (user_insn_length == 4)
12920 /* The operand doesn't force an unextended instruction to be extended.
12921 Warn if the user wanted an extended instruction anyway. */
12922 *insn |= MIPS16_EXTEND;
12923 as_warn_where (file, line,
12924 _("extended operand requested but not required"));
12927 length = mips16_opcode_length (*insn);
12930 operand = mips16_immed_operand (type, TRUE);
12931 if (!mips16_immed_in_range_p (operand, reloc, val))
12932 as_bad_where (file, line,
12933 _("operand value out of range for instruction"));
12935 uval = ((unsigned int) val >> operand->shift) - operand->bias;
12937 *insn = mips_insert_operand (&operand->root, *insn, uval);
12939 *insn |= mips16_immed_extend (uval, operand->root.size);
12942 struct percent_op_match
12945 bfd_reloc_code_real_type reloc;
12948 static const struct percent_op_match mips_percent_op[] =
12950 {"%lo", BFD_RELOC_LO16},
12951 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
12952 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
12953 {"%call16", BFD_RELOC_MIPS_CALL16},
12954 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
12955 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
12956 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
12957 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
12958 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
12959 {"%got", BFD_RELOC_MIPS_GOT16},
12960 {"%gp_rel", BFD_RELOC_GPREL16},
12961 {"%half", BFD_RELOC_16},
12962 {"%highest", BFD_RELOC_MIPS_HIGHEST},
12963 {"%higher", BFD_RELOC_MIPS_HIGHER},
12964 {"%neg", BFD_RELOC_MIPS_SUB},
12965 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
12966 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
12967 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
12968 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
12969 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
12970 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
12971 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
12972 {"%hi", BFD_RELOC_HI16_S}
12975 static const struct percent_op_match mips16_percent_op[] =
12977 {"%lo", BFD_RELOC_MIPS16_LO16},
12978 {"%gprel", BFD_RELOC_MIPS16_GPREL},
12979 {"%got", BFD_RELOC_MIPS16_GOT16},
12980 {"%call16", BFD_RELOC_MIPS16_CALL16},
12981 {"%hi", BFD_RELOC_MIPS16_HI16_S},
12982 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
12983 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
12984 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
12985 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
12986 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
12987 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
12988 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
12992 /* Return true if *STR points to a relocation operator. When returning true,
12993 move *STR over the operator and store its relocation code in *RELOC.
12994 Leave both *STR and *RELOC alone when returning false. */
12997 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
12999 const struct percent_op_match *percent_op;
13002 if (mips_opts.mips16)
13004 percent_op = mips16_percent_op;
13005 limit = ARRAY_SIZE (mips16_percent_op);
13009 percent_op = mips_percent_op;
13010 limit = ARRAY_SIZE (mips_percent_op);
13013 for (i = 0; i < limit; i++)
13014 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13016 int len = strlen (percent_op[i].str);
13018 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13021 *str += strlen (percent_op[i].str);
13022 *reloc = percent_op[i].reloc;
13024 /* Check whether the output BFD supports this relocation.
13025 If not, issue an error and fall back on something safe. */
13026 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13028 as_bad (_("relocation %s isn't supported by the current ABI"),
13029 percent_op[i].str);
13030 *reloc = BFD_RELOC_UNUSED;
13038 /* Parse string STR as a 16-bit relocatable operand. Store the
13039 expression in *EP and the relocations in the array starting
13040 at RELOC. Return the number of relocation operators used.
13042 On exit, EXPR_END points to the first character after the expression. */
13045 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13048 bfd_reloc_code_real_type reversed_reloc[3];
13049 size_t reloc_index, i;
13050 int crux_depth, str_depth;
13053 /* Search for the start of the main expression, recoding relocations
13054 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13055 of the main expression and with CRUX_DEPTH containing the number
13056 of open brackets at that point. */
13063 crux_depth = str_depth;
13065 /* Skip over whitespace and brackets, keeping count of the number
13067 while (*str == ' ' || *str == '\t' || *str == '(')
13072 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13073 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13075 my_getExpression (ep, crux);
13078 /* Match every open bracket. */
13079 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13083 if (crux_depth > 0)
13084 as_bad (_("unclosed '('"));
13088 if (reloc_index != 0)
13090 prev_reloc_op_frag = frag_now;
13091 for (i = 0; i < reloc_index; i++)
13092 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13095 return reloc_index;
13099 my_getExpression (expressionS *ep, char *str)
13103 save_in = input_line_pointer;
13104 input_line_pointer = str;
13106 expr_end = input_line_pointer;
13107 input_line_pointer = save_in;
13111 md_atof (int type, char *litP, int *sizeP)
13113 return ieee_md_atof (type, litP, sizeP, target_big_endian);
13117 md_number_to_chars (char *buf, valueT val, int n)
13119 if (target_big_endian)
13120 number_to_chars_bigendian (buf, val, n);
13122 number_to_chars_littleendian (buf, val, n);
13125 static int support_64bit_objects(void)
13127 const char **list, **l;
13130 list = bfd_target_list ();
13131 for (l = list; *l != NULL; l++)
13132 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13133 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
13135 yes = (*l != NULL);
13140 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13141 NEW_VALUE. Warn if another value was already specified. Note:
13142 we have to defer parsing the -march and -mtune arguments in order
13143 to handle 'from-abi' correctly, since the ABI might be specified
13144 in a later argument. */
13147 mips_set_option_string (const char **string_ptr, const char *new_value)
13149 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13150 as_warn (_("A different %s was already specified, is now %s"),
13151 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13154 *string_ptr = new_value;
13158 md_parse_option (int c, char *arg)
13162 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13163 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13165 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13166 c == mips_ases[i].option_on);
13172 case OPTION_CONSTRUCT_FLOATS:
13173 mips_disable_float_construction = 0;
13176 case OPTION_NO_CONSTRUCT_FLOATS:
13177 mips_disable_float_construction = 1;
13189 target_big_endian = 1;
13193 target_big_endian = 0;
13199 else if (arg[0] == '0')
13201 else if (arg[0] == '1')
13211 mips_debug = atoi (arg);
13215 file_mips_isa = ISA_MIPS1;
13219 file_mips_isa = ISA_MIPS2;
13223 file_mips_isa = ISA_MIPS3;
13227 file_mips_isa = ISA_MIPS4;
13231 file_mips_isa = ISA_MIPS5;
13234 case OPTION_MIPS32:
13235 file_mips_isa = ISA_MIPS32;
13238 case OPTION_MIPS32R2:
13239 file_mips_isa = ISA_MIPS32R2;
13242 case OPTION_MIPS64R2:
13243 file_mips_isa = ISA_MIPS64R2;
13246 case OPTION_MIPS64:
13247 file_mips_isa = ISA_MIPS64;
13251 mips_set_option_string (&mips_tune_string, arg);
13255 mips_set_option_string (&mips_arch_string, arg);
13259 mips_set_option_string (&mips_arch_string, "4650");
13260 mips_set_option_string (&mips_tune_string, "4650");
13263 case OPTION_NO_M4650:
13267 mips_set_option_string (&mips_arch_string, "4010");
13268 mips_set_option_string (&mips_tune_string, "4010");
13271 case OPTION_NO_M4010:
13275 mips_set_option_string (&mips_arch_string, "4100");
13276 mips_set_option_string (&mips_tune_string, "4100");
13279 case OPTION_NO_M4100:
13283 mips_set_option_string (&mips_arch_string, "3900");
13284 mips_set_option_string (&mips_tune_string, "3900");
13287 case OPTION_NO_M3900:
13290 case OPTION_MICROMIPS:
13291 if (mips_opts.mips16 == 1)
13293 as_bad (_("-mmicromips cannot be used with -mips16"));
13296 mips_opts.micromips = 1;
13297 mips_no_prev_insn ();
13300 case OPTION_NO_MICROMIPS:
13301 mips_opts.micromips = 0;
13302 mips_no_prev_insn ();
13305 case OPTION_MIPS16:
13306 if (mips_opts.micromips == 1)
13308 as_bad (_("-mips16 cannot be used with -micromips"));
13311 mips_opts.mips16 = 1;
13312 mips_no_prev_insn ();
13315 case OPTION_NO_MIPS16:
13316 mips_opts.mips16 = 0;
13317 mips_no_prev_insn ();
13320 case OPTION_FIX_24K:
13324 case OPTION_NO_FIX_24K:
13328 case OPTION_FIX_LOONGSON2F_JUMP:
13329 mips_fix_loongson2f_jump = TRUE;
13332 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13333 mips_fix_loongson2f_jump = FALSE;
13336 case OPTION_FIX_LOONGSON2F_NOP:
13337 mips_fix_loongson2f_nop = TRUE;
13340 case OPTION_NO_FIX_LOONGSON2F_NOP:
13341 mips_fix_loongson2f_nop = FALSE;
13344 case OPTION_FIX_VR4120:
13345 mips_fix_vr4120 = 1;
13348 case OPTION_NO_FIX_VR4120:
13349 mips_fix_vr4120 = 0;
13352 case OPTION_FIX_VR4130:
13353 mips_fix_vr4130 = 1;
13356 case OPTION_NO_FIX_VR4130:
13357 mips_fix_vr4130 = 0;
13360 case OPTION_FIX_CN63XXP1:
13361 mips_fix_cn63xxp1 = TRUE;
13364 case OPTION_NO_FIX_CN63XXP1:
13365 mips_fix_cn63xxp1 = FALSE;
13368 case OPTION_RELAX_BRANCH:
13369 mips_relax_branch = 1;
13372 case OPTION_NO_RELAX_BRANCH:
13373 mips_relax_branch = 0;
13376 case OPTION_INSN32:
13377 mips_opts.insn32 = TRUE;
13380 case OPTION_NO_INSN32:
13381 mips_opts.insn32 = FALSE;
13384 case OPTION_MSHARED:
13385 mips_in_shared = TRUE;
13388 case OPTION_MNO_SHARED:
13389 mips_in_shared = FALSE;
13392 case OPTION_MSYM32:
13393 mips_opts.sym32 = TRUE;
13396 case OPTION_MNO_SYM32:
13397 mips_opts.sym32 = FALSE;
13400 /* When generating ELF code, we permit -KPIC and -call_shared to
13401 select SVR4_PIC, and -non_shared to select no PIC. This is
13402 intended to be compatible with Irix 5. */
13403 case OPTION_CALL_SHARED:
13404 mips_pic = SVR4_PIC;
13405 mips_abicalls = TRUE;
13408 case OPTION_CALL_NONPIC:
13410 mips_abicalls = TRUE;
13413 case OPTION_NON_SHARED:
13415 mips_abicalls = FALSE;
13418 /* The -xgot option tells the assembler to use 32 bit offsets
13419 when accessing the got in SVR4_PIC mode. It is for Irix
13426 g_switch_value = atoi (arg);
13430 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13433 mips_abi = O32_ABI;
13437 mips_abi = N32_ABI;
13441 mips_abi = N64_ABI;
13442 if (!support_64bit_objects())
13443 as_fatal (_("No compiled in support for 64 bit object file format"));
13447 file_mips_gp32 = 1;
13451 file_mips_gp32 = 0;
13455 file_mips_fp32 = 1;
13459 file_mips_fp32 = 0;
13462 case OPTION_SINGLE_FLOAT:
13463 file_mips_single_float = 1;
13466 case OPTION_DOUBLE_FLOAT:
13467 file_mips_single_float = 0;
13470 case OPTION_SOFT_FLOAT:
13471 file_mips_soft_float = 1;
13474 case OPTION_HARD_FLOAT:
13475 file_mips_soft_float = 0;
13479 if (strcmp (arg, "32") == 0)
13480 mips_abi = O32_ABI;
13481 else if (strcmp (arg, "o64") == 0)
13482 mips_abi = O64_ABI;
13483 else if (strcmp (arg, "n32") == 0)
13484 mips_abi = N32_ABI;
13485 else if (strcmp (arg, "64") == 0)
13487 mips_abi = N64_ABI;
13488 if (! support_64bit_objects())
13489 as_fatal (_("No compiled in support for 64 bit object file "
13492 else if (strcmp (arg, "eabi") == 0)
13493 mips_abi = EABI_ABI;
13496 as_fatal (_("invalid abi -mabi=%s"), arg);
13501 case OPTION_M7000_HILO_FIX:
13502 mips_7000_hilo_fix = TRUE;
13505 case OPTION_MNO_7000_HILO_FIX:
13506 mips_7000_hilo_fix = FALSE;
13509 case OPTION_MDEBUG:
13510 mips_flag_mdebug = TRUE;
13513 case OPTION_NO_MDEBUG:
13514 mips_flag_mdebug = FALSE;
13518 mips_flag_pdr = TRUE;
13521 case OPTION_NO_PDR:
13522 mips_flag_pdr = FALSE;
13525 case OPTION_MVXWORKS_PIC:
13526 mips_pic = VXWORKS_PIC;
13530 if (strcmp (arg, "2008") == 0)
13531 mips_flag_nan2008 = TRUE;
13532 else if (strcmp (arg, "legacy") == 0)
13533 mips_flag_nan2008 = FALSE;
13536 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13545 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13550 /* Set up globals to generate code for the ISA or processor
13551 described by INFO. */
13554 mips_set_architecture (const struct mips_cpu_info *info)
13558 file_mips_arch = info->cpu;
13559 mips_opts.arch = info->cpu;
13560 mips_opts.isa = info->isa;
13565 /* Likewise for tuning. */
13568 mips_set_tune (const struct mips_cpu_info *info)
13571 mips_tune = info->cpu;
13576 mips_after_parse_args (void)
13578 const struct mips_cpu_info *arch_info = 0;
13579 const struct mips_cpu_info *tune_info = 0;
13581 /* GP relative stuff not working for PE */
13582 if (strncmp (TARGET_OS, "pe", 2) == 0)
13584 if (g_switch_seen && g_switch_value != 0)
13585 as_bad (_("-G not supported in this configuration."));
13586 g_switch_value = 0;
13589 if (mips_abi == NO_ABI)
13590 mips_abi = MIPS_DEFAULT_ABI;
13592 /* The following code determines the architecture and register size.
13593 Similar code was added to GCC 3.3 (see override_options() in
13594 config/mips/mips.c). The GAS and GCC code should be kept in sync
13595 as much as possible. */
13597 if (mips_arch_string != 0)
13598 arch_info = mips_parse_cpu ("-march", mips_arch_string);
13600 if (file_mips_isa != ISA_UNKNOWN)
13602 /* Handle -mipsN. At this point, file_mips_isa contains the
13603 ISA level specified by -mipsN, while arch_info->isa contains
13604 the -march selection (if any). */
13605 if (arch_info != 0)
13607 /* -march takes precedence over -mipsN, since it is more descriptive.
13608 There's no harm in specifying both as long as the ISA levels
13610 if (file_mips_isa != arch_info->isa)
13611 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13612 mips_cpu_info_from_isa (file_mips_isa)->name,
13613 mips_cpu_info_from_isa (arch_info->isa)->name);
13616 arch_info = mips_cpu_info_from_isa (file_mips_isa);
13619 if (arch_info == 0)
13621 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13622 gas_assert (arch_info);
13625 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
13626 as_bad (_("-march=%s is not compatible with the selected ABI"),
13629 mips_set_architecture (arch_info);
13631 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13632 if (mips_tune_string != 0)
13633 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
13635 if (tune_info == 0)
13636 mips_set_tune (arch_info);
13638 mips_set_tune (tune_info);
13640 if (file_mips_gp32 >= 0)
13642 /* The user specified the size of the integer registers. Make sure
13643 it agrees with the ABI and ISA. */
13644 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
13645 as_bad (_("-mgp64 used with a 32-bit processor"));
13646 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
13647 as_bad (_("-mgp32 used with a 64-bit ABI"));
13648 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
13649 as_bad (_("-mgp64 used with a 32-bit ABI"));
13653 /* Infer the integer register size from the ABI and processor.
13654 Restrict ourselves to 32-bit registers if that's all the
13655 processor has, or if the ABI cannot handle 64-bit registers. */
13656 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
13657 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
13660 switch (file_mips_fp32)
13664 /* No user specified float register size.
13665 ??? GAS treats single-float processors as though they had 64-bit
13666 float registers (although it complains when double-precision
13667 instructions are used). As things stand, saying they have 32-bit
13668 registers would lead to spurious "register must be even" messages.
13669 So here we assume float registers are never smaller than the
13671 if (file_mips_gp32 == 0)
13672 /* 64-bit integer registers implies 64-bit float registers. */
13673 file_mips_fp32 = 0;
13674 else if ((mips_opts.ase & FP64_ASES)
13675 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
13676 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13677 file_mips_fp32 = 0;
13679 /* 32-bit float registers. */
13680 file_mips_fp32 = 1;
13683 /* The user specified the size of the float registers. Check if it
13684 agrees with the ABI and ISA. */
13686 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13687 as_bad (_("-mfp64 used with a 32-bit fpu"));
13688 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
13689 && !ISA_HAS_MXHC1 (mips_opts.isa))
13690 as_warn (_("-mfp64 used with a 32-bit ABI"));
13693 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13694 as_warn (_("-mfp32 used with a 64-bit ABI"));
13698 /* End of GCC-shared inference code. */
13700 /* This flag is set when we have a 64-bit capable CPU but use only
13701 32-bit wide registers. Note that EABI does not use it. */
13702 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
13703 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
13704 || mips_abi == O32_ABI))
13705 mips_32bitmode = 1;
13707 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
13708 as_bad (_("trap exception not supported at ISA 1"));
13710 /* If the selected architecture includes support for ASEs, enable
13711 generation of code for them. */
13712 if (mips_opts.mips16 == -1)
13713 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
13714 if (mips_opts.micromips == -1)
13715 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
13717 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
13718 ASEs from being selected implicitly. */
13719 if (file_mips_fp32 == 1)
13720 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
13722 /* If the user didn't explicitly select or deselect a particular ASE,
13723 use the default setting for the CPU. */
13724 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
13726 file_mips_isa = mips_opts.isa;
13727 file_ase = mips_opts.ase;
13728 mips_opts.gp32 = file_mips_gp32;
13729 mips_opts.fp32 = file_mips_fp32;
13730 mips_opts.soft_float = file_mips_soft_float;
13731 mips_opts.single_float = file_mips_single_float;
13733 mips_check_isa_supports_ases ();
13735 if (mips_flag_mdebug < 0)
13736 mips_flag_mdebug = 0;
13740 mips_init_after_args (void)
13742 /* initialize opcodes */
13743 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
13744 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
13748 md_pcrel_from (fixS *fixP)
13750 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
13751 switch (fixP->fx_r_type)
13753 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
13754 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
13755 /* Return the address of the delay slot. */
13758 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
13759 case BFD_RELOC_MICROMIPS_JMP:
13760 case BFD_RELOC_16_PCREL_S2:
13761 case BFD_RELOC_MIPS_JMP:
13762 /* Return the address of the delay slot. */
13765 case BFD_RELOC_32_PCREL:
13769 /* We have no relocation type for PC relative MIPS16 instructions. */
13770 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
13771 as_bad_where (fixP->fx_file, fixP->fx_line,
13772 _("PC relative MIPS16 instruction references a different section"));
13777 /* This is called before the symbol table is processed. In order to
13778 work with gcc when using mips-tfile, we must keep all local labels.
13779 However, in other cases, we want to discard them. If we were
13780 called with -g, but we didn't see any debugging information, it may
13781 mean that gcc is smuggling debugging information through to
13782 mips-tfile, in which case we must generate all local labels. */
13785 mips_frob_file_before_adjust (void)
13787 #ifndef NO_ECOFF_DEBUGGING
13788 if (ECOFF_DEBUGGING
13790 && ! ecoff_debugging_seen)
13791 flag_keep_locals = 1;
13795 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
13796 the corresponding LO16 reloc. This is called before md_apply_fix and
13797 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
13798 relocation operators.
13800 For our purposes, a %lo() expression matches a %got() or %hi()
13803 (a) it refers to the same symbol; and
13804 (b) the offset applied in the %lo() expression is no lower than
13805 the offset applied in the %got() or %hi().
13807 (b) allows us to cope with code like:
13810 lh $4,%lo(foo+2)($4)
13812 ...which is legal on RELA targets, and has a well-defined behaviour
13813 if the user knows that adding 2 to "foo" will not induce a carry to
13816 When several %lo()s match a particular %got() or %hi(), we use the
13817 following rules to distinguish them:
13819 (1) %lo()s with smaller offsets are a better match than %lo()s with
13822 (2) %lo()s with no matching %got() or %hi() are better than those
13823 that already have a matching %got() or %hi().
13825 (3) later %lo()s are better than earlier %lo()s.
13827 These rules are applied in order.
13829 (1) means, among other things, that %lo()s with identical offsets are
13830 chosen if they exist.
13832 (2) means that we won't associate several high-part relocations with
13833 the same low-part relocation unless there's no alternative. Having
13834 several high parts for the same low part is a GNU extension; this rule
13835 allows careful users to avoid it.
13837 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
13838 with the last high-part relocation being at the front of the list.
13839 It therefore makes sense to choose the last matching low-part
13840 relocation, all other things being equal. It's also easier
13841 to code that way. */
13844 mips_frob_file (void)
13846 struct mips_hi_fixup *l;
13847 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
13849 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
13851 segment_info_type *seginfo;
13852 bfd_boolean matched_lo_p;
13853 fixS **hi_pos, **lo_pos, **pos;
13855 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
13857 /* If a GOT16 relocation turns out to be against a global symbol,
13858 there isn't supposed to be a matching LO. Ignore %gots against
13859 constants; we'll report an error for those later. */
13860 if (got16_reloc_p (l->fixp->fx_r_type)
13861 && !(l->fixp->fx_addsy
13862 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
13865 /* Check quickly whether the next fixup happens to be a matching %lo. */
13866 if (fixup_has_matching_lo_p (l->fixp))
13869 seginfo = seg_info (l->seg);
13871 /* Set HI_POS to the position of this relocation in the chain.
13872 Set LO_POS to the position of the chosen low-part relocation.
13873 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
13874 relocation that matches an immediately-preceding high-part
13878 matched_lo_p = FALSE;
13879 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
13881 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
13883 if (*pos == l->fixp)
13886 if ((*pos)->fx_r_type == looking_for_rtype
13887 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
13888 && (*pos)->fx_offset >= l->fixp->fx_offset
13890 || (*pos)->fx_offset < (*lo_pos)->fx_offset
13892 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
13895 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
13896 && fixup_has_matching_lo_p (*pos));
13899 /* If we found a match, remove the high-part relocation from its
13900 current position and insert it before the low-part relocation.
13901 Make the offsets match so that fixup_has_matching_lo_p()
13904 We don't warn about unmatched high-part relocations since some
13905 versions of gcc have been known to emit dead "lui ...%hi(...)"
13907 if (lo_pos != NULL)
13909 l->fixp->fx_offset = (*lo_pos)->fx_offset;
13910 if (l->fixp->fx_next != *lo_pos)
13912 *hi_pos = l->fixp->fx_next;
13913 l->fixp->fx_next = *lo_pos;
13921 mips_force_relocation (fixS *fixp)
13923 if (generic_force_reloc (fixp))
13926 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
13927 so that the linker relaxation can update targets. */
13928 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13929 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
13930 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
13936 /* Read the instruction associated with RELOC from BUF. */
13938 static unsigned int
13939 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
13941 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13942 return read_compressed_insn (buf, 4);
13944 return read_insn (buf);
13947 /* Write instruction INSN to BUF, given that it has been relocated
13951 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
13952 unsigned long insn)
13954 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
13955 write_compressed_insn (buf, insn, 4);
13957 write_insn (buf, insn);
13960 /* Apply a fixup to the object file. */
13963 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
13966 unsigned long insn;
13967 reloc_howto_type *howto;
13969 /* We ignore generic BFD relocations we don't know about. */
13970 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
13974 gas_assert (fixP->fx_size == 2
13975 || fixP->fx_size == 4
13976 || fixP->fx_r_type == BFD_RELOC_16
13977 || fixP->fx_r_type == BFD_RELOC_64
13978 || fixP->fx_r_type == BFD_RELOC_CTOR
13979 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
13980 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
13981 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13982 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
13983 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
13985 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
13987 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
13988 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
13989 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
13990 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
13991 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
13993 /* Don't treat parts of a composite relocation as done. There are two
13996 (1) The second and third parts will be against 0 (RSS_UNDEF) but
13997 should nevertheless be emitted if the first part is.
13999 (2) In normal usage, composite relocations are never assembly-time
14000 constants. The easiest way of dealing with the pathological
14001 exceptions is to generate a relocation against STN_UNDEF and
14002 leave everything up to the linker. */
14003 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14006 switch (fixP->fx_r_type)
14008 case BFD_RELOC_MIPS_TLS_GD:
14009 case BFD_RELOC_MIPS_TLS_LDM:
14010 case BFD_RELOC_MIPS_TLS_DTPREL32:
14011 case BFD_RELOC_MIPS_TLS_DTPREL64:
14012 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14013 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14014 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14015 case BFD_RELOC_MIPS_TLS_TPREL32:
14016 case BFD_RELOC_MIPS_TLS_TPREL64:
14017 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14018 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14019 case BFD_RELOC_MICROMIPS_TLS_GD:
14020 case BFD_RELOC_MICROMIPS_TLS_LDM:
14021 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14022 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14023 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14024 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14025 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14026 case BFD_RELOC_MIPS16_TLS_GD:
14027 case BFD_RELOC_MIPS16_TLS_LDM:
14028 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14029 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14030 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14031 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14032 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14033 if (!fixP->fx_addsy)
14035 as_bad_where (fixP->fx_file, fixP->fx_line,
14036 _("TLS relocation against a constant"));
14039 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14042 case BFD_RELOC_MIPS_JMP:
14043 case BFD_RELOC_MIPS_SHIFT5:
14044 case BFD_RELOC_MIPS_SHIFT6:
14045 case BFD_RELOC_MIPS_GOT_DISP:
14046 case BFD_RELOC_MIPS_GOT_PAGE:
14047 case BFD_RELOC_MIPS_GOT_OFST:
14048 case BFD_RELOC_MIPS_SUB:
14049 case BFD_RELOC_MIPS_INSERT_A:
14050 case BFD_RELOC_MIPS_INSERT_B:
14051 case BFD_RELOC_MIPS_DELETE:
14052 case BFD_RELOC_MIPS_HIGHEST:
14053 case BFD_RELOC_MIPS_HIGHER:
14054 case BFD_RELOC_MIPS_SCN_DISP:
14055 case BFD_RELOC_MIPS_REL16:
14056 case BFD_RELOC_MIPS_RELGOT:
14057 case BFD_RELOC_MIPS_JALR:
14058 case BFD_RELOC_HI16:
14059 case BFD_RELOC_HI16_S:
14060 case BFD_RELOC_LO16:
14061 case BFD_RELOC_GPREL16:
14062 case BFD_RELOC_MIPS_LITERAL:
14063 case BFD_RELOC_MIPS_CALL16:
14064 case BFD_RELOC_MIPS_GOT16:
14065 case BFD_RELOC_GPREL32:
14066 case BFD_RELOC_MIPS_GOT_HI16:
14067 case BFD_RELOC_MIPS_GOT_LO16:
14068 case BFD_RELOC_MIPS_CALL_HI16:
14069 case BFD_RELOC_MIPS_CALL_LO16:
14070 case BFD_RELOC_MIPS16_GPREL:
14071 case BFD_RELOC_MIPS16_GOT16:
14072 case BFD_RELOC_MIPS16_CALL16:
14073 case BFD_RELOC_MIPS16_HI16:
14074 case BFD_RELOC_MIPS16_HI16_S:
14075 case BFD_RELOC_MIPS16_LO16:
14076 case BFD_RELOC_MIPS16_JMP:
14077 case BFD_RELOC_MICROMIPS_JMP:
14078 case BFD_RELOC_MICROMIPS_GOT_DISP:
14079 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14080 case BFD_RELOC_MICROMIPS_GOT_OFST:
14081 case BFD_RELOC_MICROMIPS_SUB:
14082 case BFD_RELOC_MICROMIPS_HIGHEST:
14083 case BFD_RELOC_MICROMIPS_HIGHER:
14084 case BFD_RELOC_MICROMIPS_SCN_DISP:
14085 case BFD_RELOC_MICROMIPS_JALR:
14086 case BFD_RELOC_MICROMIPS_HI16:
14087 case BFD_RELOC_MICROMIPS_HI16_S:
14088 case BFD_RELOC_MICROMIPS_LO16:
14089 case BFD_RELOC_MICROMIPS_GPREL16:
14090 case BFD_RELOC_MICROMIPS_LITERAL:
14091 case BFD_RELOC_MICROMIPS_CALL16:
14092 case BFD_RELOC_MICROMIPS_GOT16:
14093 case BFD_RELOC_MICROMIPS_GOT_HI16:
14094 case BFD_RELOC_MICROMIPS_GOT_LO16:
14095 case BFD_RELOC_MICROMIPS_CALL_HI16:
14096 case BFD_RELOC_MICROMIPS_CALL_LO16:
14097 case BFD_RELOC_MIPS_EH:
14102 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14104 insn = read_reloc_insn (buf, fixP->fx_r_type);
14105 if (mips16_reloc_p (fixP->fx_r_type))
14106 insn |= mips16_immed_extend (value, 16);
14108 insn |= (value & 0xffff);
14109 write_reloc_insn (buf, fixP->fx_r_type, insn);
14112 as_bad_where (fixP->fx_file, fixP->fx_line,
14113 _("Unsupported constant in relocation"));
14118 /* This is handled like BFD_RELOC_32, but we output a sign
14119 extended value if we are only 32 bits. */
14122 if (8 <= sizeof (valueT))
14123 md_number_to_chars (buf, *valP, 8);
14128 if ((*valP & 0x80000000) != 0)
14132 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14133 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
14138 case BFD_RELOC_RVA:
14140 case BFD_RELOC_32_PCREL:
14142 /* If we are deleting this reloc entry, we must fill in the
14143 value now. This can happen if we have a .word which is not
14144 resolved when it appears but is later defined. */
14146 md_number_to_chars (buf, *valP, fixP->fx_size);
14149 case BFD_RELOC_16_PCREL_S2:
14150 if ((*valP & 0x3) != 0)
14151 as_bad_where (fixP->fx_file, fixP->fx_line,
14152 _("Branch to misaligned address (%lx)"), (long) *valP);
14154 /* We need to save the bits in the instruction since fixup_segment()
14155 might be deleting the relocation entry (i.e., a branch within
14156 the current segment). */
14157 if (! fixP->fx_done)
14160 /* Update old instruction data. */
14161 insn = read_insn (buf);
14163 if (*valP + 0x20000 <= 0x3ffff)
14165 insn |= (*valP >> 2) & 0xffff;
14166 write_insn (buf, insn);
14168 else if (mips_pic == NO_PIC
14170 && fixP->fx_frag->fr_address >= text_section->vma
14171 && (fixP->fx_frag->fr_address
14172 < text_section->vma + bfd_get_section_size (text_section))
14173 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14174 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14175 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
14177 /* The branch offset is too large. If this is an
14178 unconditional branch, and we are not generating PIC code,
14179 we can convert it to an absolute jump instruction. */
14180 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14181 insn = 0x0c000000; /* jal */
14183 insn = 0x08000000; /* j */
14184 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14186 fixP->fx_addsy = section_symbol (text_section);
14187 *valP += md_pcrel_from (fixP);
14188 write_insn (buf, insn);
14192 /* If we got here, we have branch-relaxation disabled,
14193 and there's nothing we can do to fix this instruction
14194 without turning it into a longer sequence. */
14195 as_bad_where (fixP->fx_file, fixP->fx_line,
14196 _("Branch out of range"));
14200 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14201 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14202 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14203 /* We adjust the offset back to even. */
14204 if ((*valP & 0x1) != 0)
14207 if (! fixP->fx_done)
14210 /* Should never visit here, because we keep the relocation. */
14214 case BFD_RELOC_VTABLE_INHERIT:
14217 && !S_IS_DEFINED (fixP->fx_addsy)
14218 && !S_IS_WEAK (fixP->fx_addsy))
14219 S_SET_WEAK (fixP->fx_addsy);
14222 case BFD_RELOC_VTABLE_ENTRY:
14230 /* Remember value for tc_gen_reloc. */
14231 fixP->fx_addnumber = *valP;
14241 name = input_line_pointer;
14242 c = get_symbol_end ();
14243 p = (symbolS *) symbol_find_or_make (name);
14244 *input_line_pointer = c;
14248 /* Align the current frag to a given power of two. If a particular
14249 fill byte should be used, FILL points to an integer that contains
14250 that byte, otherwise FILL is null.
14252 This function used to have the comment:
14254 The MIPS assembler also automatically adjusts any preceding label.
14256 The implementation therefore applied the adjustment to a maximum of
14257 one label. However, other label adjustments are applied to batches
14258 of labels, and adjusting just one caused problems when new labels
14259 were added for the sake of debugging or unwind information.
14260 We therefore adjust all preceding labels (given as LABELS) instead. */
14263 mips_align (int to, int *fill, struct insn_label_list *labels)
14265 mips_emit_delays ();
14266 mips_record_compressed_mode ();
14267 if (fill == NULL && subseg_text_p (now_seg))
14268 frag_align_code (to, 0);
14270 frag_align (to, fill ? *fill : 0, 0);
14271 record_alignment (now_seg, to);
14272 mips_move_labels (labels, FALSE);
14275 /* Align to a given power of two. .align 0 turns off the automatic
14276 alignment used by the data creating pseudo-ops. */
14279 s_align (int x ATTRIBUTE_UNUSED)
14281 int temp, fill_value, *fill_ptr;
14282 long max_alignment = 28;
14284 /* o Note that the assembler pulls down any immediately preceding label
14285 to the aligned address.
14286 o It's not documented but auto alignment is reinstated by
14287 a .align pseudo instruction.
14288 o Note also that after auto alignment is turned off the mips assembler
14289 issues an error on attempt to assemble an improperly aligned data item.
14292 temp = get_absolute_expression ();
14293 if (temp > max_alignment)
14294 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14297 as_warn (_("Alignment negative: 0 assumed."));
14300 if (*input_line_pointer == ',')
14302 ++input_line_pointer;
14303 fill_value = get_absolute_expression ();
14304 fill_ptr = &fill_value;
14310 segment_info_type *si = seg_info (now_seg);
14311 struct insn_label_list *l = si->label_list;
14312 /* Auto alignment should be switched on by next section change. */
14314 mips_align (temp, fill_ptr, l);
14321 demand_empty_rest_of_line ();
14325 s_change_sec (int sec)
14329 /* The ELF backend needs to know that we are changing sections, so
14330 that .previous works correctly. We could do something like check
14331 for an obj_section_change_hook macro, but that might be confusing
14332 as it would not be appropriate to use it in the section changing
14333 functions in read.c, since obj-elf.c intercepts those. FIXME:
14334 This should be cleaner, somehow. */
14335 obj_elf_section_change_hook ();
14337 mips_emit_delays ();
14348 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14349 demand_empty_rest_of_line ();
14353 seg = subseg_new (RDATA_SECTION_NAME,
14354 (subsegT) get_absolute_expression ());
14355 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14356 | SEC_READONLY | SEC_RELOC
14358 if (strncmp (TARGET_OS, "elf", 3) != 0)
14359 record_alignment (seg, 4);
14360 demand_empty_rest_of_line ();
14364 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
14365 bfd_set_section_flags (stdoutput, seg,
14366 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14367 if (strncmp (TARGET_OS, "elf", 3) != 0)
14368 record_alignment (seg, 4);
14369 demand_empty_rest_of_line ();
14373 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
14374 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14375 if (strncmp (TARGET_OS, "elf", 3) != 0)
14376 record_alignment (seg, 4);
14377 demand_empty_rest_of_line ();
14385 s_change_section (int ignore ATTRIBUTE_UNUSED)
14387 char *section_name;
14392 int section_entry_size;
14393 int section_alignment;
14395 section_name = input_line_pointer;
14396 c = get_symbol_end ();
14398 next_c = *(input_line_pointer + 1);
14400 /* Do we have .section Name<,"flags">? */
14401 if (c != ',' || (c == ',' && next_c == '"'))
14403 /* just after name is now '\0'. */
14404 *input_line_pointer = c;
14405 input_line_pointer = section_name;
14406 obj_elf_section (ignore);
14409 input_line_pointer++;
14411 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14413 section_type = get_absolute_expression ();
14416 if (*input_line_pointer++ == ',')
14417 section_flag = get_absolute_expression ();
14420 if (*input_line_pointer++ == ',')
14421 section_entry_size = get_absolute_expression ();
14423 section_entry_size = 0;
14424 if (*input_line_pointer++ == ',')
14425 section_alignment = get_absolute_expression ();
14427 section_alignment = 0;
14428 /* FIXME: really ignore? */
14429 (void) section_alignment;
14431 section_name = xstrdup (section_name);
14433 /* When using the generic form of .section (as implemented by obj-elf.c),
14434 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14435 traditionally had to fall back on the more common @progbits instead.
14437 There's nothing really harmful in this, since bfd will correct
14438 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14439 means that, for backwards compatibility, the special_section entries
14440 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14442 Even so, we shouldn't force users of the MIPS .section syntax to
14443 incorrectly label the sections as SHT_PROGBITS. The best compromise
14444 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14445 generic type-checking code. */
14446 if (section_type == SHT_MIPS_DWARF)
14447 section_type = SHT_PROGBITS;
14449 obj_elf_change_section (section_name, section_type, section_flag,
14450 section_entry_size, 0, 0, 0);
14452 if (now_seg->name != section_name)
14453 free (section_name);
14457 mips_enable_auto_align (void)
14463 s_cons (int log_size)
14465 segment_info_type *si = seg_info (now_seg);
14466 struct insn_label_list *l = si->label_list;
14468 mips_emit_delays ();
14469 if (log_size > 0 && auto_align)
14470 mips_align (log_size, 0, l);
14471 cons (1 << log_size);
14472 mips_clear_insn_labels ();
14476 s_float_cons (int type)
14478 segment_info_type *si = seg_info (now_seg);
14479 struct insn_label_list *l = si->label_list;
14481 mips_emit_delays ();
14486 mips_align (3, 0, l);
14488 mips_align (2, 0, l);
14492 mips_clear_insn_labels ();
14495 /* Handle .globl. We need to override it because on Irix 5 you are
14498 where foo is an undefined symbol, to mean that foo should be
14499 considered to be the address of a function. */
14502 s_mips_globl (int x ATTRIBUTE_UNUSED)
14511 name = input_line_pointer;
14512 c = get_symbol_end ();
14513 symbolP = symbol_find_or_make (name);
14514 S_SET_EXTERNAL (symbolP);
14516 *input_line_pointer = c;
14517 SKIP_WHITESPACE ();
14519 /* On Irix 5, every global symbol that is not explicitly labelled as
14520 being a function is apparently labelled as being an object. */
14523 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14524 && (*input_line_pointer != ','))
14529 secname = input_line_pointer;
14530 c = get_symbol_end ();
14531 sec = bfd_get_section_by_name (stdoutput, secname);
14533 as_bad (_("%s: no such section"), secname);
14534 *input_line_pointer = c;
14536 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14537 flag = BSF_FUNCTION;
14540 symbol_get_bfdsym (symbolP)->flags |= flag;
14542 c = *input_line_pointer;
14545 input_line_pointer++;
14546 SKIP_WHITESPACE ();
14547 if (is_end_of_line[(unsigned char) *input_line_pointer])
14553 demand_empty_rest_of_line ();
14557 s_option (int x ATTRIBUTE_UNUSED)
14562 opt = input_line_pointer;
14563 c = get_symbol_end ();
14567 /* FIXME: What does this mean? */
14569 else if (strncmp (opt, "pic", 3) == 0)
14573 i = atoi (opt + 3);
14578 mips_pic = SVR4_PIC;
14579 mips_abicalls = TRUE;
14582 as_bad (_(".option pic%d not supported"), i);
14584 if (mips_pic == SVR4_PIC)
14586 if (g_switch_seen && g_switch_value != 0)
14587 as_warn (_("-G may not be used with SVR4 PIC code"));
14588 g_switch_value = 0;
14589 bfd_set_gp_size (stdoutput, 0);
14593 as_warn (_("Unrecognized option \"%s\""), opt);
14595 *input_line_pointer = c;
14596 demand_empty_rest_of_line ();
14599 /* This structure is used to hold a stack of .set values. */
14601 struct mips_option_stack
14603 struct mips_option_stack *next;
14604 struct mips_set_options options;
14607 static struct mips_option_stack *mips_opts_stack;
14609 /* Handle the .set pseudo-op. */
14612 s_mipsset (int x ATTRIBUTE_UNUSED)
14614 char *name = input_line_pointer, ch;
14615 const struct mips_ase *ase;
14617 while (!is_end_of_line[(unsigned char) *input_line_pointer])
14618 ++input_line_pointer;
14619 ch = *input_line_pointer;
14620 *input_line_pointer = '\0';
14622 if (strcmp (name, "reorder") == 0)
14624 if (mips_opts.noreorder)
14627 else if (strcmp (name, "noreorder") == 0)
14629 if (!mips_opts.noreorder)
14630 start_noreorder ();
14632 else if (strncmp (name, "at=", 3) == 0)
14634 char *s = name + 3;
14636 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
14637 as_bad (_("Unrecognized register name `%s'"), s);
14639 else if (strcmp (name, "at") == 0)
14641 mips_opts.at = ATREG;
14643 else if (strcmp (name, "noat") == 0)
14645 mips_opts.at = ZERO;
14647 else if (strcmp (name, "macro") == 0)
14649 mips_opts.warn_about_macros = 0;
14651 else if (strcmp (name, "nomacro") == 0)
14653 if (mips_opts.noreorder == 0)
14654 as_bad (_("`noreorder' must be set before `nomacro'"));
14655 mips_opts.warn_about_macros = 1;
14657 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
14659 mips_opts.nomove = 0;
14661 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
14663 mips_opts.nomove = 1;
14665 else if (strcmp (name, "bopt") == 0)
14667 mips_opts.nobopt = 0;
14669 else if (strcmp (name, "nobopt") == 0)
14671 mips_opts.nobopt = 1;
14673 else if (strcmp (name, "gp=default") == 0)
14674 mips_opts.gp32 = file_mips_gp32;
14675 else if (strcmp (name, "gp=32") == 0)
14676 mips_opts.gp32 = 1;
14677 else if (strcmp (name, "gp=64") == 0)
14679 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
14680 as_warn (_("%s isa does not support 64-bit registers"),
14681 mips_cpu_info_from_isa (mips_opts.isa)->name);
14682 mips_opts.gp32 = 0;
14684 else if (strcmp (name, "fp=default") == 0)
14685 mips_opts.fp32 = file_mips_fp32;
14686 else if (strcmp (name, "fp=32") == 0)
14687 mips_opts.fp32 = 1;
14688 else if (strcmp (name, "fp=64") == 0)
14690 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14691 as_warn (_("%s isa does not support 64-bit floating point registers"),
14692 mips_cpu_info_from_isa (mips_opts.isa)->name);
14693 mips_opts.fp32 = 0;
14695 else if (strcmp (name, "softfloat") == 0)
14696 mips_opts.soft_float = 1;
14697 else if (strcmp (name, "hardfloat") == 0)
14698 mips_opts.soft_float = 0;
14699 else if (strcmp (name, "singlefloat") == 0)
14700 mips_opts.single_float = 1;
14701 else if (strcmp (name, "doublefloat") == 0)
14702 mips_opts.single_float = 0;
14703 else if (strcmp (name, "mips16") == 0
14704 || strcmp (name, "MIPS-16") == 0)
14706 if (mips_opts.micromips == 1)
14707 as_fatal (_("`mips16' cannot be used with `micromips'"));
14708 mips_opts.mips16 = 1;
14710 else if (strcmp (name, "nomips16") == 0
14711 || strcmp (name, "noMIPS-16") == 0)
14712 mips_opts.mips16 = 0;
14713 else if (strcmp (name, "micromips") == 0)
14715 if (mips_opts.mips16 == 1)
14716 as_fatal (_("`micromips' cannot be used with `mips16'"));
14717 mips_opts.micromips = 1;
14719 else if (strcmp (name, "nomicromips") == 0)
14720 mips_opts.micromips = 0;
14721 else if (name[0] == 'n'
14723 && (ase = mips_lookup_ase (name + 2)))
14724 mips_set_ase (ase, FALSE);
14725 else if ((ase = mips_lookup_ase (name)))
14726 mips_set_ase (ase, TRUE);
14727 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
14731 /* Permit the user to change the ISA and architecture on the fly.
14732 Needless to say, misuse can cause serious problems. */
14733 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
14736 mips_opts.isa = file_mips_isa;
14737 mips_opts.arch = file_mips_arch;
14739 else if (strncmp (name, "arch=", 5) == 0)
14741 const struct mips_cpu_info *p;
14743 p = mips_parse_cpu("internal use", name + 5);
14745 as_bad (_("unknown architecture %s"), name + 5);
14748 mips_opts.arch = p->cpu;
14749 mips_opts.isa = p->isa;
14752 else if (strncmp (name, "mips", 4) == 0)
14754 const struct mips_cpu_info *p;
14756 p = mips_parse_cpu("internal use", name);
14758 as_bad (_("unknown ISA level %s"), name + 4);
14761 mips_opts.arch = p->cpu;
14762 mips_opts.isa = p->isa;
14766 as_bad (_("unknown ISA or architecture %s"), name);
14768 switch (mips_opts.isa)
14776 mips_opts.gp32 = 1;
14777 mips_opts.fp32 = 1;
14784 mips_opts.gp32 = 0;
14785 if (mips_opts.arch == CPU_R5900)
14787 mips_opts.fp32 = 1;
14791 mips_opts.fp32 = 0;
14795 as_bad (_("unknown ISA level %s"), name + 4);
14800 mips_opts.gp32 = file_mips_gp32;
14801 mips_opts.fp32 = file_mips_fp32;
14804 else if (strcmp (name, "autoextend") == 0)
14805 mips_opts.noautoextend = 0;
14806 else if (strcmp (name, "noautoextend") == 0)
14807 mips_opts.noautoextend = 1;
14808 else if (strcmp (name, "insn32") == 0)
14809 mips_opts.insn32 = TRUE;
14810 else if (strcmp (name, "noinsn32") == 0)
14811 mips_opts.insn32 = FALSE;
14812 else if (strcmp (name, "push") == 0)
14814 struct mips_option_stack *s;
14816 s = (struct mips_option_stack *) xmalloc (sizeof *s);
14817 s->next = mips_opts_stack;
14818 s->options = mips_opts;
14819 mips_opts_stack = s;
14821 else if (strcmp (name, "pop") == 0)
14823 struct mips_option_stack *s;
14825 s = mips_opts_stack;
14827 as_bad (_(".set pop with no .set push"));
14830 /* If we're changing the reorder mode we need to handle
14831 delay slots correctly. */
14832 if (s->options.noreorder && ! mips_opts.noreorder)
14833 start_noreorder ();
14834 else if (! s->options.noreorder && mips_opts.noreorder)
14837 mips_opts = s->options;
14838 mips_opts_stack = s->next;
14842 else if (strcmp (name, "sym32") == 0)
14843 mips_opts.sym32 = TRUE;
14844 else if (strcmp (name, "nosym32") == 0)
14845 mips_opts.sym32 = FALSE;
14846 else if (strchr (name, ','))
14848 /* Generic ".set" directive; use the generic handler. */
14849 *input_line_pointer = ch;
14850 input_line_pointer = name;
14856 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
14858 mips_check_isa_supports_ases ();
14859 *input_line_pointer = ch;
14860 demand_empty_rest_of_line ();
14863 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
14864 .option pic2. It means to generate SVR4 PIC calls. */
14867 s_abicalls (int ignore ATTRIBUTE_UNUSED)
14869 mips_pic = SVR4_PIC;
14870 mips_abicalls = TRUE;
14872 if (g_switch_seen && g_switch_value != 0)
14873 as_warn (_("-G may not be used with SVR4 PIC code"));
14874 g_switch_value = 0;
14876 bfd_set_gp_size (stdoutput, 0);
14877 demand_empty_rest_of_line ();
14880 /* Handle the .cpload pseudo-op. This is used when generating SVR4
14881 PIC code. It sets the $gp register for the function based on the
14882 function address, which is in the register named in the argument.
14883 This uses a relocation against _gp_disp, which is handled specially
14884 by the linker. The result is:
14885 lui $gp,%hi(_gp_disp)
14886 addiu $gp,$gp,%lo(_gp_disp)
14887 addu $gp,$gp,.cpload argument
14888 The .cpload argument is normally $25 == $t9.
14890 The -mno-shared option changes this to:
14891 lui $gp,%hi(__gnu_local_gp)
14892 addiu $gp,$gp,%lo(__gnu_local_gp)
14893 and the argument is ignored. This saves an instruction, but the
14894 resulting code is not position independent; it uses an absolute
14895 address for __gnu_local_gp. Thus code assembled with -mno-shared
14896 can go into an ordinary executable, but not into a shared library. */
14899 s_cpload (int ignore ATTRIBUTE_UNUSED)
14905 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
14906 .cpload is ignored. */
14907 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
14913 if (mips_opts.mips16)
14915 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
14916 ignore_rest_of_line ();
14920 /* .cpload should be in a .set noreorder section. */
14921 if (mips_opts.noreorder == 0)
14922 as_warn (_(".cpload not in noreorder section"));
14924 reg = tc_get_register (0);
14926 /* If we need to produce a 64-bit address, we are better off using
14927 the default instruction sequence. */
14928 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
14930 ex.X_op = O_symbol;
14931 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
14933 ex.X_op_symbol = NULL;
14934 ex.X_add_number = 0;
14936 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
14937 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
14939 mips_mark_labels ();
14940 mips_assembling_insn = TRUE;
14943 macro_build_lui (&ex, mips_gp_register);
14944 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
14945 mips_gp_register, BFD_RELOC_LO16);
14947 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
14948 mips_gp_register, reg);
14951 mips_assembling_insn = FALSE;
14952 demand_empty_rest_of_line ();
14955 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
14956 .cpsetup $reg1, offset|$reg2, label
14958 If offset is given, this results in:
14959 sd $gp, offset($sp)
14960 lui $gp, %hi(%neg(%gp_rel(label)))
14961 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14962 daddu $gp, $gp, $reg1
14964 If $reg2 is given, this results in:
14965 daddu $reg2, $gp, $0
14966 lui $gp, %hi(%neg(%gp_rel(label)))
14967 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
14968 daddu $gp, $gp, $reg1
14969 $reg1 is normally $25 == $t9.
14971 The -mno-shared option replaces the last three instructions with
14973 addiu $gp,$gp,%lo(_gp) */
14976 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
14978 expressionS ex_off;
14979 expressionS ex_sym;
14982 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
14983 We also need NewABI support. */
14984 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
14990 if (mips_opts.mips16)
14992 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
14993 ignore_rest_of_line ();
14997 reg1 = tc_get_register (0);
14998 SKIP_WHITESPACE ();
14999 if (*input_line_pointer != ',')
15001 as_bad (_("missing argument separator ',' for .cpsetup"));
15005 ++input_line_pointer;
15006 SKIP_WHITESPACE ();
15007 if (*input_line_pointer == '$')
15009 mips_cpreturn_register = tc_get_register (0);
15010 mips_cpreturn_offset = -1;
15014 mips_cpreturn_offset = get_absolute_expression ();
15015 mips_cpreturn_register = -1;
15017 SKIP_WHITESPACE ();
15018 if (*input_line_pointer != ',')
15020 as_bad (_("missing argument separator ',' for .cpsetup"));
15024 ++input_line_pointer;
15025 SKIP_WHITESPACE ();
15026 expression (&ex_sym);
15028 mips_mark_labels ();
15029 mips_assembling_insn = TRUE;
15032 if (mips_cpreturn_register == -1)
15034 ex_off.X_op = O_constant;
15035 ex_off.X_add_symbol = NULL;
15036 ex_off.X_op_symbol = NULL;
15037 ex_off.X_add_number = mips_cpreturn_offset;
15039 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15040 BFD_RELOC_LO16, SP);
15043 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
15044 mips_gp_register, 0);
15046 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15048 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15049 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15052 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15053 mips_gp_register, -1, BFD_RELOC_GPREL16,
15054 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15056 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15057 mips_gp_register, reg1);
15063 ex.X_op = O_symbol;
15064 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15065 ex.X_op_symbol = NULL;
15066 ex.X_add_number = 0;
15068 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15069 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15071 macro_build_lui (&ex, mips_gp_register);
15072 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15073 mips_gp_register, BFD_RELOC_LO16);
15078 mips_assembling_insn = FALSE;
15079 demand_empty_rest_of_line ();
15083 s_cplocal (int ignore ATTRIBUTE_UNUSED)
15085 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15086 .cplocal is ignored. */
15087 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15093 if (mips_opts.mips16)
15095 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15096 ignore_rest_of_line ();
15100 mips_gp_register = tc_get_register (0);
15101 demand_empty_rest_of_line ();
15104 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15105 offset from $sp. The offset is remembered, and after making a PIC
15106 call $gp is restored from that location. */
15109 s_cprestore (int ignore ATTRIBUTE_UNUSED)
15113 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15114 .cprestore is ignored. */
15115 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15121 if (mips_opts.mips16)
15123 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15124 ignore_rest_of_line ();
15128 mips_cprestore_offset = get_absolute_expression ();
15129 mips_cprestore_valid = 1;
15131 ex.X_op = O_constant;
15132 ex.X_add_symbol = NULL;
15133 ex.X_op_symbol = NULL;
15134 ex.X_add_number = mips_cprestore_offset;
15136 mips_mark_labels ();
15137 mips_assembling_insn = TRUE;
15140 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15141 SP, HAVE_64BIT_ADDRESSES);
15144 mips_assembling_insn = FALSE;
15145 demand_empty_rest_of_line ();
15148 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15149 was given in the preceding .cpsetup, it results in:
15150 ld $gp, offset($sp)
15152 If a register $reg2 was given there, it results in:
15153 daddu $gp, $reg2, $0 */
15156 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
15160 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15161 We also need NewABI support. */
15162 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15168 if (mips_opts.mips16)
15170 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15171 ignore_rest_of_line ();
15175 mips_mark_labels ();
15176 mips_assembling_insn = TRUE;
15179 if (mips_cpreturn_register == -1)
15181 ex.X_op = O_constant;
15182 ex.X_add_symbol = NULL;
15183 ex.X_op_symbol = NULL;
15184 ex.X_add_number = mips_cpreturn_offset;
15186 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
15189 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
15190 mips_cpreturn_register, 0);
15193 mips_assembling_insn = FALSE;
15194 demand_empty_rest_of_line ();
15197 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15198 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15199 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15200 debug information or MIPS16 TLS. */
15203 s_tls_rel_directive (const size_t bytes, const char *dirstr,
15204 bfd_reloc_code_real_type rtype)
15211 if (ex.X_op != O_symbol)
15213 as_bad (_("Unsupported use of %s"), dirstr);
15214 ignore_rest_of_line ();
15217 p = frag_more (bytes);
15218 md_number_to_chars (p, 0, bytes);
15219 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
15220 demand_empty_rest_of_line ();
15221 mips_clear_insn_labels ();
15224 /* Handle .dtprelword. */
15227 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15229 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
15232 /* Handle .dtpreldword. */
15235 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15237 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15240 /* Handle .tprelword. */
15243 s_tprelword (int ignore ATTRIBUTE_UNUSED)
15245 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15248 /* Handle .tpreldword. */
15251 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15253 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
15256 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15257 code. It sets the offset to use in gp_rel relocations. */
15260 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
15262 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15263 We also need NewABI support. */
15264 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15270 mips_gprel_offset = get_absolute_expression ();
15272 demand_empty_rest_of_line ();
15275 /* Handle the .gpword pseudo-op. This is used when generating PIC
15276 code. It generates a 32 bit GP relative reloc. */
15279 s_gpword (int ignore ATTRIBUTE_UNUSED)
15281 segment_info_type *si;
15282 struct insn_label_list *l;
15286 /* When not generating PIC code, this is treated as .word. */
15287 if (mips_pic != SVR4_PIC)
15293 si = seg_info (now_seg);
15294 l = si->label_list;
15295 mips_emit_delays ();
15297 mips_align (2, 0, l);
15300 mips_clear_insn_labels ();
15302 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15304 as_bad (_("Unsupported use of .gpword"));
15305 ignore_rest_of_line ();
15309 md_number_to_chars (p, 0, 4);
15310 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15311 BFD_RELOC_GPREL32);
15313 demand_empty_rest_of_line ();
15317 s_gpdword (int ignore ATTRIBUTE_UNUSED)
15319 segment_info_type *si;
15320 struct insn_label_list *l;
15324 /* When not generating PIC code, this is treated as .dword. */
15325 if (mips_pic != SVR4_PIC)
15331 si = seg_info (now_seg);
15332 l = si->label_list;
15333 mips_emit_delays ();
15335 mips_align (3, 0, l);
15338 mips_clear_insn_labels ();
15340 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15342 as_bad (_("Unsupported use of .gpdword"));
15343 ignore_rest_of_line ();
15347 md_number_to_chars (p, 0, 8);
15348 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15349 BFD_RELOC_GPREL32)->fx_tcbit = 1;
15351 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15352 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15353 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
15355 demand_empty_rest_of_line ();
15358 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15359 tables. It generates a R_MIPS_EH reloc. */
15362 s_ehword (int ignore ATTRIBUTE_UNUSED)
15367 mips_emit_delays ();
15370 mips_clear_insn_labels ();
15372 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15374 as_bad (_("Unsupported use of .ehword"));
15375 ignore_rest_of_line ();
15379 md_number_to_chars (p, 0, 4);
15380 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15381 BFD_RELOC_MIPS_EH);
15383 demand_empty_rest_of_line ();
15386 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15387 tables in SVR4 PIC code. */
15390 s_cpadd (int ignore ATTRIBUTE_UNUSED)
15394 /* This is ignored when not generating SVR4 PIC code. */
15395 if (mips_pic != SVR4_PIC)
15401 mips_mark_labels ();
15402 mips_assembling_insn = TRUE;
15404 /* Add $gp to the register named as an argument. */
15406 reg = tc_get_register (0);
15407 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
15410 mips_assembling_insn = FALSE;
15411 demand_empty_rest_of_line ();
15414 /* Handle the .insn pseudo-op. This marks instruction labels in
15415 mips16/micromips mode. This permits the linker to handle them specially,
15416 such as generating jalx instructions when needed. We also make
15417 them odd for the duration of the assembly, in order to generate the
15418 right sort of code. We will make them even in the adjust_symtab
15419 routine, while leaving them marked. This is convenient for the
15420 debugger and the disassembler. The linker knows to make them odd
15424 s_insn (int ignore ATTRIBUTE_UNUSED)
15426 mips_mark_labels ();
15428 demand_empty_rest_of_line ();
15431 /* Handle the .nan pseudo-op. */
15434 s_nan (int ignore ATTRIBUTE_UNUSED)
15436 static const char str_legacy[] = "legacy";
15437 static const char str_2008[] = "2008";
15440 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15442 if (i == sizeof (str_2008) - 1
15443 && memcmp (input_line_pointer, str_2008, i) == 0)
15444 mips_flag_nan2008 = TRUE;
15445 else if (i == sizeof (str_legacy) - 1
15446 && memcmp (input_line_pointer, str_legacy, i) == 0)
15447 mips_flag_nan2008 = FALSE;
15449 as_bad (_("Bad .nan directive"));
15451 input_line_pointer += i;
15452 demand_empty_rest_of_line ();
15455 /* Handle a .stab[snd] directive. Ideally these directives would be
15456 implemented in a transparent way, so that removing them would not
15457 have any effect on the generated instructions. However, s_stab
15458 internally changes the section, so in practice we need to decide
15459 now whether the preceding label marks compressed code. We do not
15460 support changing the compression mode of a label after a .stab*
15461 directive, such as in:
15467 so the current mode wins. */
15470 s_mips_stab (int type)
15472 mips_mark_labels ();
15476 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15479 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
15486 name = input_line_pointer;
15487 c = get_symbol_end ();
15488 symbolP = symbol_find_or_make (name);
15489 S_SET_WEAK (symbolP);
15490 *input_line_pointer = c;
15492 SKIP_WHITESPACE ();
15494 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15496 if (S_IS_DEFINED (symbolP))
15498 as_bad (_("ignoring attempt to redefine symbol %s"),
15499 S_GET_NAME (symbolP));
15500 ignore_rest_of_line ();
15504 if (*input_line_pointer == ',')
15506 ++input_line_pointer;
15507 SKIP_WHITESPACE ();
15511 if (exp.X_op != O_symbol)
15513 as_bad (_("bad .weakext directive"));
15514 ignore_rest_of_line ();
15517 symbol_set_value_expression (symbolP, &exp);
15520 demand_empty_rest_of_line ();
15523 /* Parse a register string into a number. Called from the ECOFF code
15524 to parse .frame. The argument is non-zero if this is the frame
15525 register, so that we can record it in mips_frame_reg. */
15528 tc_get_register (int frame)
15532 SKIP_WHITESPACE ();
15533 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
15537 mips_frame_reg = reg != 0 ? reg : SP;
15538 mips_frame_reg_valid = 1;
15539 mips_cprestore_valid = 0;
15545 md_section_align (asection *seg, valueT addr)
15547 int align = bfd_get_section_alignment (stdoutput, seg);
15549 /* We don't need to align ELF sections to the full alignment.
15550 However, Irix 5 may prefer that we align them at least to a 16
15551 byte boundary. We don't bother to align the sections if we
15552 are targeted for an embedded system. */
15553 if (strncmp (TARGET_OS, "elf", 3) == 0)
15558 return ((addr + (1 << align) - 1) & (-1 << align));
15561 /* Utility routine, called from above as well. If called while the
15562 input file is still being read, it's only an approximation. (For
15563 example, a symbol may later become defined which appeared to be
15564 undefined earlier.) */
15567 nopic_need_relax (symbolS *sym, int before_relaxing)
15572 if (g_switch_value > 0)
15574 const char *symname;
15577 /* Find out whether this symbol can be referenced off the $gp
15578 register. It can be if it is smaller than the -G size or if
15579 it is in the .sdata or .sbss section. Certain symbols can
15580 not be referenced off the $gp, although it appears as though
15582 symname = S_GET_NAME (sym);
15583 if (symname != (const char *) NULL
15584 && (strcmp (symname, "eprol") == 0
15585 || strcmp (symname, "etext") == 0
15586 || strcmp (symname, "_gp") == 0
15587 || strcmp (symname, "edata") == 0
15588 || strcmp (symname, "_fbss") == 0
15589 || strcmp (symname, "_fdata") == 0
15590 || strcmp (symname, "_ftext") == 0
15591 || strcmp (symname, "end") == 0
15592 || strcmp (symname, "_gp_disp") == 0))
15594 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15596 #ifndef NO_ECOFF_DEBUGGING
15597 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15598 && (symbol_get_obj (sym)->ecoff_extern_size
15599 <= g_switch_value))
15601 /* We must defer this decision until after the whole
15602 file has been read, since there might be a .extern
15603 after the first use of this symbol. */
15604 || (before_relaxing
15605 #ifndef NO_ECOFF_DEBUGGING
15606 && symbol_get_obj (sym)->ecoff_extern_size == 0
15608 && S_GET_VALUE (sym) == 0)
15609 || (S_GET_VALUE (sym) != 0
15610 && S_GET_VALUE (sym) <= g_switch_value)))
15614 const char *segname;
15616 segname = segment_name (S_GET_SEGMENT (sym));
15617 gas_assert (strcmp (segname, ".lit8") != 0
15618 && strcmp (segname, ".lit4") != 0);
15619 change = (strcmp (segname, ".sdata") != 0
15620 && strcmp (segname, ".sbss") != 0
15621 && strncmp (segname, ".sdata.", 7) != 0
15622 && strncmp (segname, ".sbss.", 6) != 0
15623 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
15624 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
15629 /* We are not optimizing for the $gp register. */
15634 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15637 pic_need_relax (symbolS *sym, asection *segtype)
15641 /* Handle the case of a symbol equated to another symbol. */
15642 while (symbol_equated_reloc_p (sym))
15646 /* It's possible to get a loop here in a badly written program. */
15647 n = symbol_get_value_expression (sym)->X_add_symbol;
15653 if (symbol_section_p (sym))
15656 symsec = S_GET_SEGMENT (sym);
15658 /* This must duplicate the test in adjust_reloc_syms. */
15659 return (!bfd_is_und_section (symsec)
15660 && !bfd_is_abs_section (symsec)
15661 && !bfd_is_com_section (symsec)
15662 && !s_is_linkonce (sym, segtype)
15663 /* A global or weak symbol is treated as external. */
15664 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
15668 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15669 extended opcode. SEC is the section the frag is in. */
15672 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
15675 const struct mips_int_operand *operand;
15680 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
15682 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
15685 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
15686 operand = mips16_immed_operand (type, FALSE);
15688 sym_frag = symbol_get_frag (fragp->fr_symbol);
15689 val = S_GET_VALUE (fragp->fr_symbol);
15690 symsec = S_GET_SEGMENT (fragp->fr_symbol);
15692 if (operand->root.type == OP_PCREL)
15694 const struct mips_pcrel_operand *pcrel_op;
15698 /* We won't have the section when we are called from
15699 mips_relax_frag. However, we will always have been called
15700 from md_estimate_size_before_relax first. If this is a
15701 branch to a different section, we mark it as such. If SEC is
15702 NULL, and the frag is not marked, then it must be a branch to
15703 the same section. */
15704 pcrel_op = (const struct mips_pcrel_operand *) operand;
15707 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
15712 /* Must have been called from md_estimate_size_before_relax. */
15715 fragp->fr_subtype =
15716 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15718 /* FIXME: We should support this, and let the linker
15719 catch branches and loads that are out of range. */
15720 as_bad_where (fragp->fr_file, fragp->fr_line,
15721 _("unsupported PC relative reference to different section"));
15725 if (fragp != sym_frag && sym_frag->fr_address == 0)
15726 /* Assume non-extended on the first relaxation pass.
15727 The address we have calculated will be bogus if this is
15728 a forward branch to another frag, as the forward frag
15729 will have fr_address == 0. */
15733 /* In this case, we know for sure that the symbol fragment is in
15734 the same section. If the relax_marker of the symbol fragment
15735 differs from the relax_marker of this fragment, we have not
15736 yet adjusted the symbol fragment fr_address. We want to add
15737 in STRETCH in order to get a better estimate of the address.
15738 This particularly matters because of the shift bits. */
15740 && sym_frag->relax_marker != fragp->relax_marker)
15744 /* Adjust stretch for any alignment frag. Note that if have
15745 been expanding the earlier code, the symbol may be
15746 defined in what appears to be an earlier frag. FIXME:
15747 This doesn't handle the fr_subtype field, which specifies
15748 a maximum number of bytes to skip when doing an
15750 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
15752 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
15755 stretch = - ((- stretch)
15756 & ~ ((1 << (int) f->fr_offset) - 1));
15758 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
15767 addr = fragp->fr_address + fragp->fr_fix;
15769 /* The base address rules are complicated. The base address of
15770 a branch is the following instruction. The base address of a
15771 PC relative load or add is the instruction itself, but if it
15772 is in a delay slot (in which case it can not be extended) use
15773 the address of the instruction whose delay slot it is in. */
15774 if (pcrel_op->include_isa_bit)
15778 /* If we are currently assuming that this frag should be
15779 extended, then, the current address is two bytes
15781 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
15784 /* Ignore the low bit in the target, since it will be set
15785 for a text label. */
15788 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
15790 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
15793 val -= addr & -(1 << pcrel_op->align_log2);
15795 /* If any of the shifted bits are set, we must use an extended
15796 opcode. If the address depends on the size of this
15797 instruction, this can lead to a loop, so we arrange to always
15798 use an extended opcode. We only check this when we are in
15799 the main relaxation loop, when SEC is NULL. */
15800 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
15802 fragp->fr_subtype =
15803 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15807 /* If we are about to mark a frag as extended because the value
15808 is precisely the next value above maxtiny, then there is a
15809 chance of an infinite loop as in the following code:
15814 In this case when the la is extended, foo is 0x3fc bytes
15815 away, so the la can be shrunk, but then foo is 0x400 away, so
15816 the la must be extended. To avoid this loop, we mark the
15817 frag as extended if it was small, and is about to become
15818 extended with the next value above maxtiny. */
15819 maxtiny = mips_int_operand_max (operand);
15820 if (val == maxtiny + (1 << operand->shift)
15821 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
15824 fragp->fr_subtype =
15825 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
15829 else if (symsec != absolute_section && sec != NULL)
15830 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
15832 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
15835 /* Compute the length of a branch sequence, and adjust the
15836 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
15837 worst-case length is computed, with UPDATE being used to indicate
15838 whether an unconditional (-1), branch-likely (+1) or regular (0)
15839 branch is to be computed. */
15841 relaxed_branch_length (fragS *fragp, asection *sec, int update)
15843 bfd_boolean toofar;
15847 && S_IS_DEFINED (fragp->fr_symbol)
15848 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15853 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15855 addr = fragp->fr_address + fragp->fr_fix + 4;
15859 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
15862 /* If the symbol is not defined or it's in a different segment,
15863 assume the user knows what's going on and emit a short
15869 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
15871 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
15872 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
15873 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
15874 RELAX_BRANCH_LINK (fragp->fr_subtype),
15880 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
15883 if (mips_pic != NO_PIC)
15885 /* Additional space for PIC loading of target address. */
15887 if (mips_opts.isa == ISA_MIPS1)
15888 /* Additional space for $at-stabilizing nop. */
15892 /* If branch is conditional. */
15893 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
15900 /* Compute the length of a branch sequence, and adjust the
15901 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
15902 worst-case length is computed, with UPDATE being used to indicate
15903 whether an unconditional (-1), or regular (0) branch is to be
15907 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
15909 bfd_boolean toofar;
15913 && S_IS_DEFINED (fragp->fr_symbol)
15914 && sec == S_GET_SEGMENT (fragp->fr_symbol))
15919 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
15920 /* Ignore the low bit in the target, since it will be set
15921 for a text label. */
15922 if ((val & 1) != 0)
15925 addr = fragp->fr_address + fragp->fr_fix + 4;
15929 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
15932 /* If the symbol is not defined or it's in a different segment,
15933 assume the user knows what's going on and emit a short
15939 if (fragp && update
15940 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
15941 fragp->fr_subtype = (toofar
15942 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
15943 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
15948 bfd_boolean compact_known = fragp != NULL;
15949 bfd_boolean compact = FALSE;
15950 bfd_boolean uncond;
15953 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
15955 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
15957 uncond = update < 0;
15959 /* If label is out of range, we turn branch <br>:
15961 <br> label # 4 bytes
15967 nop # 2 bytes if compact && !PIC
15970 if (mips_pic == NO_PIC && (!compact_known || compact))
15973 /* If assembling PIC code, we further turn:
15979 lw/ld at, %got(label)(gp) # 4 bytes
15980 d/addiu at, %lo(label) # 4 bytes
15983 if (mips_pic != NO_PIC)
15986 /* If branch <br> is conditional, we prepend negated branch <brneg>:
15988 <brneg> 0f # 4 bytes
15989 nop # 2 bytes if !compact
15992 length += (compact_known && compact) ? 4 : 6;
15998 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
15999 bit accordingly. */
16002 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16004 bfd_boolean toofar;
16007 && S_IS_DEFINED (fragp->fr_symbol)
16008 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16014 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16015 /* Ignore the low bit in the target, since it will be set
16016 for a text label. */
16017 if ((val & 1) != 0)
16020 /* Assume this is a 2-byte branch. */
16021 addr = fragp->fr_address + fragp->fr_fix + 2;
16023 /* We try to avoid the infinite loop by not adding 2 more bytes for
16028 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16030 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16031 else if (type == 'E')
16032 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16037 /* If the symbol is not defined or it's in a different segment,
16038 we emit a normal 32-bit branch. */
16041 if (fragp && update
16042 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16044 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16045 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16053 /* Estimate the size of a frag before relaxing. Unless this is the
16054 mips16, we are not really relaxing here, and the final size is
16055 encoded in the subtype information. For the mips16, we have to
16056 decide whether we are using an extended opcode or not. */
16059 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
16063 if (RELAX_BRANCH_P (fragp->fr_subtype))
16066 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16068 return fragp->fr_var;
16071 if (RELAX_MIPS16_P (fragp->fr_subtype))
16072 /* We don't want to modify the EXTENDED bit here; it might get us
16073 into infinite loops. We change it only in mips_relax_frag(). */
16074 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
16076 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16080 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16081 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16082 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16083 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16084 fragp->fr_var = length;
16089 if (mips_pic == NO_PIC)
16090 change = nopic_need_relax (fragp->fr_symbol, 0);
16091 else if (mips_pic == SVR4_PIC)
16092 change = pic_need_relax (fragp->fr_symbol, segtype);
16093 else if (mips_pic == VXWORKS_PIC)
16094 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16101 fragp->fr_subtype |= RELAX_USE_SECOND;
16102 return -RELAX_FIRST (fragp->fr_subtype);
16105 return -RELAX_SECOND (fragp->fr_subtype);
16108 /* This is called to see whether a reloc against a defined symbol
16109 should be converted into a reloc against a section. */
16112 mips_fix_adjustable (fixS *fixp)
16114 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16115 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16118 if (fixp->fx_addsy == NULL)
16121 /* If symbol SYM is in a mergeable section, relocations of the form
16122 SYM + 0 can usually be made section-relative. The mergeable data
16123 is then identified by the section offset rather than by the symbol.
16125 However, if we're generating REL LO16 relocations, the offset is split
16126 between the LO16 and parterning high part relocation. The linker will
16127 need to recalculate the complete offset in order to correctly identify
16130 The linker has traditionally not looked for the parterning high part
16131 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16132 placed anywhere. Rather than break backwards compatibility by changing
16133 this, it seems better not to force the issue, and instead keep the
16134 original symbol. This will work with either linker behavior. */
16135 if ((lo16_reloc_p (fixp->fx_r_type)
16136 || reloc_needs_lo_p (fixp->fx_r_type))
16137 && HAVE_IN_PLACE_ADDENDS
16138 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16141 /* There is no place to store an in-place offset for JALR relocations.
16142 Likewise an in-range offset of limited PC-relative relocations may
16143 overflow the in-place relocatable field if recalculated against the
16144 start address of the symbol's containing section. */
16145 if (HAVE_IN_PLACE_ADDENDS
16146 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16147 || jalr_reloc_p (fixp->fx_r_type)))
16150 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16151 to a floating-point stub. The same is true for non-R_MIPS16_26
16152 relocations against MIPS16 functions; in this case, the stub becomes
16153 the function's canonical address.
16155 Floating-point stubs are stored in unique .mips16.call.* or
16156 .mips16.fn.* sections. If a stub T for function F is in section S,
16157 the first relocation in section S must be against F; this is how the
16158 linker determines the target function. All relocations that might
16159 resolve to T must also be against F. We therefore have the following
16160 restrictions, which are given in an intentionally-redundant way:
16162 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16165 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16166 if that stub might be used.
16168 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16171 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16172 that stub might be used.
16174 There is a further restriction:
16176 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16177 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16178 targets with in-place addends; the relocation field cannot
16179 encode the low bit.
16181 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16182 against a MIPS16 symbol. We deal with (5) by by not reducing any
16183 such relocations on REL targets.
16185 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16186 relocation against some symbol R, no relocation against R may be
16187 reduced. (Note that this deals with (2) as well as (1) because
16188 relocations against global symbols will never be reduced on ELF
16189 targets.) This approach is a little simpler than trying to detect
16190 stub sections, and gives the "all or nothing" per-symbol consistency
16191 that we have for MIPS16 symbols. */
16192 if (fixp->fx_subsy == NULL
16193 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
16194 || *symbol_get_tc (fixp->fx_addsy)
16195 || (HAVE_IN_PLACE_ADDENDS
16196 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16197 && jmp_reloc_p (fixp->fx_r_type))))
16203 /* Translate internal representation of relocation info to BFD target
16207 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
16209 static arelent *retval[4];
16211 bfd_reloc_code_real_type code;
16213 memset (retval, 0, sizeof(retval));
16214 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
16215 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16216 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
16217 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16219 if (fixp->fx_pcrel)
16221 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16222 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16223 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
16224 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16225 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
16227 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16228 Relocations want only the symbol offset. */
16229 reloc->addend = fixp->fx_addnumber + reloc->address;
16232 reloc->addend = fixp->fx_addnumber;
16234 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16235 entry to be used in the relocation's section offset. */
16236 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16238 reloc->address = reloc->addend;
16242 code = fixp->fx_r_type;
16244 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
16245 if (reloc->howto == NULL)
16247 as_bad_where (fixp->fx_file, fixp->fx_line,
16248 _("Can not represent %s relocation in this object file format"),
16249 bfd_get_reloc_code_name (code));
16256 /* Relax a machine dependent frag. This returns the amount by which
16257 the current size of the frag should change. */
16260 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
16262 if (RELAX_BRANCH_P (fragp->fr_subtype))
16264 offsetT old_var = fragp->fr_var;
16266 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
16268 return fragp->fr_var - old_var;
16271 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16273 offsetT old_var = fragp->fr_var;
16274 offsetT new_var = 4;
16276 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16277 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16278 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16279 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16280 fragp->fr_var = new_var;
16282 return new_var - old_var;
16285 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16288 if (mips16_extended_frag (fragp, NULL, stretch))
16290 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16292 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16297 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16299 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16306 /* Convert a machine dependent frag. */
16309 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
16311 if (RELAX_BRANCH_P (fragp->fr_subtype))
16314 unsigned long insn;
16318 buf = fragp->fr_literal + fragp->fr_fix;
16319 insn = read_insn (buf);
16321 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16323 /* We generate a fixup instead of applying it right now
16324 because, if there are linker relaxations, we're going to
16325 need the relocations. */
16326 exp.X_op = O_symbol;
16327 exp.X_add_symbol = fragp->fr_symbol;
16328 exp.X_add_number = fragp->fr_offset;
16330 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16331 BFD_RELOC_16_PCREL_S2);
16332 fixp->fx_file = fragp->fr_file;
16333 fixp->fx_line = fragp->fr_line;
16335 buf = write_insn (buf, insn);
16341 as_warn_where (fragp->fr_file, fragp->fr_line,
16342 _("Relaxed out-of-range branch into a jump"));
16344 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16347 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16349 /* Reverse the branch. */
16350 switch ((insn >> 28) & 0xf)
16353 /* bc[0-3][tf]l? instructions can have the condition
16354 reversed by tweaking a single TF bit, and their
16355 opcodes all have 0x4???????. */
16356 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16357 insn ^= 0x00010000;
16361 /* bltz 0x04000000 bgez 0x04010000
16362 bltzal 0x04100000 bgezal 0x04110000 */
16363 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
16364 insn ^= 0x00010000;
16368 /* beq 0x10000000 bne 0x14000000
16369 blez 0x18000000 bgtz 0x1c000000 */
16370 insn ^= 0x04000000;
16378 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16380 /* Clear the and-link bit. */
16381 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
16383 /* bltzal 0x04100000 bgezal 0x04110000
16384 bltzall 0x04120000 bgezall 0x04130000 */
16385 insn &= ~0x00100000;
16388 /* Branch over the branch (if the branch was likely) or the
16389 full jump (not likely case). Compute the offset from the
16390 current instruction to branch to. */
16391 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16395 /* How many bytes in instructions we've already emitted? */
16396 i = buf - fragp->fr_literal - fragp->fr_fix;
16397 /* How many bytes in instructions from here to the end? */
16398 i = fragp->fr_var - i;
16400 /* Convert to instruction count. */
16402 /* Branch counts from the next instruction. */
16405 /* Branch over the jump. */
16406 buf = write_insn (buf, insn);
16409 buf = write_insn (buf, 0);
16411 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16413 /* beql $0, $0, 2f */
16415 /* Compute the PC offset from the current instruction to
16416 the end of the variable frag. */
16417 /* How many bytes in instructions we've already emitted? */
16418 i = buf - fragp->fr_literal - fragp->fr_fix;
16419 /* How many bytes in instructions from here to the end? */
16420 i = fragp->fr_var - i;
16421 /* Convert to instruction count. */
16423 /* Don't decrement i, because we want to branch over the
16427 buf = write_insn (buf, insn);
16428 buf = write_insn (buf, 0);
16432 if (mips_pic == NO_PIC)
16435 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16436 ? 0x0c000000 : 0x08000000);
16437 exp.X_op = O_symbol;
16438 exp.X_add_symbol = fragp->fr_symbol;
16439 exp.X_add_number = fragp->fr_offset;
16441 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16442 FALSE, BFD_RELOC_MIPS_JMP);
16443 fixp->fx_file = fragp->fr_file;
16444 fixp->fx_line = fragp->fr_line;
16446 buf = write_insn (buf, insn);
16450 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16452 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16453 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16454 insn |= at << OP_SH_RT;
16455 exp.X_op = O_symbol;
16456 exp.X_add_symbol = fragp->fr_symbol;
16457 exp.X_add_number = fragp->fr_offset;
16459 if (fragp->fr_offset)
16461 exp.X_add_symbol = make_expr_symbol (&exp);
16462 exp.X_add_number = 0;
16465 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16466 FALSE, BFD_RELOC_MIPS_GOT16);
16467 fixp->fx_file = fragp->fr_file;
16468 fixp->fx_line = fragp->fr_line;
16470 buf = write_insn (buf, insn);
16472 if (mips_opts.isa == ISA_MIPS1)
16474 buf = write_insn (buf, 0);
16476 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16477 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16478 insn |= at << OP_SH_RS | at << OP_SH_RT;
16480 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16481 FALSE, BFD_RELOC_LO16);
16482 fixp->fx_file = fragp->fr_file;
16483 fixp->fx_line = fragp->fr_line;
16485 buf = write_insn (buf, insn);
16488 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16492 insn |= at << OP_SH_RS;
16494 buf = write_insn (buf, insn);
16498 fragp->fr_fix += fragp->fr_var;
16499 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16503 /* Relax microMIPS branches. */
16504 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16506 char *buf = fragp->fr_literal + fragp->fr_fix;
16507 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16508 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16509 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16510 bfd_boolean short_ds;
16511 unsigned long insn;
16515 exp.X_op = O_symbol;
16516 exp.X_add_symbol = fragp->fr_symbol;
16517 exp.X_add_number = fragp->fr_offset;
16519 fragp->fr_fix += fragp->fr_var;
16521 /* Handle 16-bit branches that fit or are forced to fit. */
16522 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16524 /* We generate a fixup instead of applying it right now,
16525 because if there is linker relaxation, we're going to
16526 need the relocations. */
16528 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16529 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16530 else if (type == 'E')
16531 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16532 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16536 fixp->fx_file = fragp->fr_file;
16537 fixp->fx_line = fragp->fr_line;
16539 /* These relocations can have an addend that won't fit in
16541 fixp->fx_no_overflow = 1;
16546 /* Handle 32-bit branches that fit or are forced to fit. */
16547 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16548 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16550 /* We generate a fixup instead of applying it right now,
16551 because if there is linker relaxation, we're going to
16552 need the relocations. */
16553 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16554 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16555 fixp->fx_file = fragp->fr_file;
16556 fixp->fx_line = fragp->fr_line;
16562 /* Relax 16-bit branches to 32-bit branches. */
16565 insn = read_compressed_insn (buf, 2);
16567 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16568 insn = 0x94000000; /* beq */
16569 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16571 unsigned long regno;
16573 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16574 regno = micromips_to_32_reg_d_map [regno];
16575 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16576 insn |= regno << MICROMIPSOP_SH_RS;
16581 /* Nothing else to do, just write it out. */
16582 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16583 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16585 buf = write_compressed_insn (buf, insn, 4);
16586 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16591 insn = read_compressed_insn (buf, 4);
16593 /* Relax 32-bit branches to a sequence of instructions. */
16594 as_warn_where (fragp->fr_file, fragp->fr_line,
16595 _("Relaxed out-of-range branch into a jump"));
16597 /* Set the short-delay-slot bit. */
16598 short_ds = al && (insn & 0x02000000) != 0;
16600 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16604 /* Reverse the branch. */
16605 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16606 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16607 insn ^= 0x20000000;
16608 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16609 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16610 || (insn & 0xffe00000) == 0x40800000 /* blez */
16611 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16612 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16613 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16614 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16615 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16616 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16617 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16618 insn ^= 0x00400000;
16619 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16620 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16621 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16622 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16623 insn ^= 0x00200000;
16629 /* Clear the and-link and short-delay-slot bits. */
16630 gas_assert ((insn & 0xfda00000) == 0x40200000);
16632 /* bltzal 0x40200000 bgezal 0x40600000 */
16633 /* bltzals 0x42200000 bgezals 0x42600000 */
16634 insn &= ~0x02200000;
16637 /* Make a label at the end for use with the branch. */
16638 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
16639 micromips_label_inc ();
16640 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
16643 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
16644 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16645 fixp->fx_file = fragp->fr_file;
16646 fixp->fx_line = fragp->fr_line;
16648 /* Branch over the jump. */
16649 buf = write_compressed_insn (buf, insn, 4);
16652 buf = write_compressed_insn (buf, 0x0c00, 2);
16655 if (mips_pic == NO_PIC)
16657 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
16659 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16660 insn = al ? jal : 0xd4000000;
16662 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16663 BFD_RELOC_MICROMIPS_JMP);
16664 fixp->fx_file = fragp->fr_file;
16665 fixp->fx_line = fragp->fr_line;
16667 buf = write_compressed_insn (buf, insn, 4);
16670 buf = write_compressed_insn (buf, 0x0c00, 2);
16674 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
16675 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
16676 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
16678 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16679 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
16680 insn |= at << MICROMIPSOP_SH_RT;
16682 if (exp.X_add_number)
16684 exp.X_add_symbol = make_expr_symbol (&exp);
16685 exp.X_add_number = 0;
16688 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16689 BFD_RELOC_MICROMIPS_GOT16);
16690 fixp->fx_file = fragp->fr_file;
16691 fixp->fx_line = fragp->fr_line;
16693 buf = write_compressed_insn (buf, insn, 4);
16695 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16696 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
16697 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
16699 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
16700 BFD_RELOC_MICROMIPS_LO16);
16701 fixp->fx_file = fragp->fr_file;
16702 fixp->fx_line = fragp->fr_line;
16704 buf = write_compressed_insn (buf, insn, 4);
16706 /* jr/jrc/jalr/jalrs $at */
16707 insn = al ? jalr : jr;
16708 insn |= at << MICROMIPSOP_SH_MJ;
16710 buf = write_compressed_insn (buf, insn, 2);
16713 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16717 if (RELAX_MIPS16_P (fragp->fr_subtype))
16720 const struct mips_int_operand *operand;
16723 unsigned int user_length, length;
16724 unsigned long insn;
16727 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16728 operand = mips16_immed_operand (type, FALSE);
16730 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
16731 val = resolve_symbol_value (fragp->fr_symbol);
16732 if (operand->root.type == OP_PCREL)
16734 const struct mips_pcrel_operand *pcrel_op;
16737 pcrel_op = (const struct mips_pcrel_operand *) operand;
16738 addr = fragp->fr_address + fragp->fr_fix;
16740 /* The rules for the base address of a PC relative reloc are
16741 complicated; see mips16_extended_frag. */
16742 if (pcrel_op->include_isa_bit)
16747 /* Ignore the low bit in the target, since it will be
16748 set for a text label. */
16751 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16753 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16756 addr &= -(1 << pcrel_op->align_log2);
16759 /* Make sure the section winds up with the alignment we have
16761 if (operand->shift > 0)
16762 record_alignment (asec, operand->shift);
16766 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
16767 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
16768 as_warn_where (fragp->fr_file, fragp->fr_line,
16769 _("extended instruction in delay slot"));
16771 buf = fragp->fr_literal + fragp->fr_fix;
16773 insn = read_compressed_insn (buf, 2);
16775 insn |= MIPS16_EXTEND;
16777 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16779 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16784 mips16_immed (fragp->fr_file, fragp->fr_line, type,
16785 BFD_RELOC_UNUSED, val, user_length, &insn);
16787 length = (ext ? 4 : 2);
16788 gas_assert (mips16_opcode_length (insn) == length);
16789 write_compressed_insn (buf, insn, length);
16790 fragp->fr_fix += length;
16794 relax_substateT subtype = fragp->fr_subtype;
16795 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
16796 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
16800 first = RELAX_FIRST (subtype);
16801 second = RELAX_SECOND (subtype);
16802 fixp = (fixS *) fragp->fr_opcode;
16804 /* If the delay slot chosen does not match the size of the instruction,
16805 then emit a warning. */
16806 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
16807 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
16812 s = subtype & (RELAX_DELAY_SLOT_16BIT
16813 | RELAX_DELAY_SLOT_SIZE_FIRST
16814 | RELAX_DELAY_SLOT_SIZE_SECOND);
16815 msg = macro_warning (s);
16817 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
16821 /* Possibly emit a warning if we've chosen the longer option. */
16822 if (use_second == second_longer)
16828 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
16829 msg = macro_warning (s);
16831 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
16835 /* Go through all the fixups for the first sequence. Disable them
16836 (by marking them as done) if we're going to use the second
16837 sequence instead. */
16839 && fixp->fx_frag == fragp
16840 && fixp->fx_where < fragp->fr_fix - second)
16842 if (subtype & RELAX_USE_SECOND)
16844 fixp = fixp->fx_next;
16847 /* Go through the fixups for the second sequence. Disable them if
16848 we're going to use the first sequence, otherwise adjust their
16849 addresses to account for the relaxation. */
16850 while (fixp && fixp->fx_frag == fragp)
16852 if (subtype & RELAX_USE_SECOND)
16853 fixp->fx_where -= first;
16856 fixp = fixp->fx_next;
16859 /* Now modify the frag contents. */
16860 if (subtype & RELAX_USE_SECOND)
16864 start = fragp->fr_literal + fragp->fr_fix - first - second;
16865 memmove (start, start + first, second);
16866 fragp->fr_fix -= first;
16869 fragp->fr_fix -= second;
16873 /* This function is called after the relocs have been generated.
16874 We've been storing mips16 text labels as odd. Here we convert them
16875 back to even for the convenience of the debugger. */
16878 mips_frob_file_after_relocs (void)
16881 unsigned int count, i;
16883 syms = bfd_get_outsymbols (stdoutput);
16884 count = bfd_get_symcount (stdoutput);
16885 for (i = 0; i < count; i++, syms++)
16886 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
16887 && ((*syms)->value & 1) != 0)
16889 (*syms)->value &= ~1;
16890 /* If the symbol has an odd size, it was probably computed
16891 incorrectly, so adjust that as well. */
16892 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
16893 ++elf_symbol (*syms)->internal_elf_sym.st_size;
16897 /* This function is called whenever a label is defined, including fake
16898 labels instantiated off the dot special symbol. It is used when
16899 handling branch delays; if a branch has a label, we assume we cannot
16900 move it. This also bumps the value of the symbol by 1 in compressed
16904 mips_record_label (symbolS *sym)
16906 segment_info_type *si = seg_info (now_seg);
16907 struct insn_label_list *l;
16909 if (free_insn_labels == NULL)
16910 l = (struct insn_label_list *) xmalloc (sizeof *l);
16913 l = free_insn_labels;
16914 free_insn_labels = l->next;
16918 l->next = si->label_list;
16919 si->label_list = l;
16922 /* This function is called as tc_frob_label() whenever a label is defined
16923 and adds a DWARF-2 record we only want for true labels. */
16926 mips_define_label (symbolS *sym)
16928 mips_record_label (sym);
16929 dwarf2_emit_label (sym);
16932 /* This function is called by tc_new_dot_label whenever a new dot symbol
16936 mips_add_dot_label (symbolS *sym)
16938 mips_record_label (sym);
16939 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
16940 mips_compressed_mark_label (sym);
16943 /* Some special processing for a MIPS ELF file. */
16946 mips_elf_final_processing (void)
16948 /* Write out the register information. */
16949 if (mips_abi != N64_ABI)
16953 s.ri_gprmask = mips_gprmask;
16954 s.ri_cprmask[0] = mips_cprmask[0];
16955 s.ri_cprmask[1] = mips_cprmask[1];
16956 s.ri_cprmask[2] = mips_cprmask[2];
16957 s.ri_cprmask[3] = mips_cprmask[3];
16958 /* The gp_value field is set by the MIPS ELF backend. */
16960 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
16961 ((Elf32_External_RegInfo *)
16962 mips_regmask_frag));
16966 Elf64_Internal_RegInfo s;
16968 s.ri_gprmask = mips_gprmask;
16970 s.ri_cprmask[0] = mips_cprmask[0];
16971 s.ri_cprmask[1] = mips_cprmask[1];
16972 s.ri_cprmask[2] = mips_cprmask[2];
16973 s.ri_cprmask[3] = mips_cprmask[3];
16974 /* The gp_value field is set by the MIPS ELF backend. */
16976 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
16977 ((Elf64_External_RegInfo *)
16978 mips_regmask_frag));
16981 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
16982 sort of BFD interface for this. */
16983 if (mips_any_noreorder)
16984 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
16985 if (mips_pic != NO_PIC)
16987 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
16988 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
16991 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
16993 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
16994 defined at present; this might need to change in future. */
16995 if (file_ase_mips16)
16996 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
16997 if (file_ase_micromips)
16998 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
16999 if (file_ase & ASE_MDMX)
17000 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
17002 /* Set the MIPS ELF ABI flags. */
17003 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
17004 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
17005 else if (mips_abi == O64_ABI)
17006 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
17007 else if (mips_abi == EABI_ABI)
17009 if (!file_mips_gp32)
17010 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17012 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17014 else if (mips_abi == N32_ABI)
17015 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17017 /* Nothing to do for N64_ABI. */
17019 if (mips_32bitmode)
17020 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
17022 if (mips_flag_nan2008)
17023 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17025 #if 0 /* XXX FIXME */
17026 /* 32 bit code with 64 bit FP registers. */
17027 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17028 elf_elfheader (stdoutput)->e_flags |= ???;
17032 typedef struct proc {
17034 symbolS *func_end_sym;
17035 unsigned long reg_mask;
17036 unsigned long reg_offset;
17037 unsigned long fpreg_mask;
17038 unsigned long fpreg_offset;
17039 unsigned long frame_offset;
17040 unsigned long frame_reg;
17041 unsigned long pc_reg;
17044 static procS cur_proc;
17045 static procS *cur_proc_ptr;
17046 static int numprocs;
17048 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17049 as "2", and a normal nop as "0". */
17051 #define NOP_OPCODE_MIPS 0
17052 #define NOP_OPCODE_MIPS16 1
17053 #define NOP_OPCODE_MICROMIPS 2
17056 mips_nop_opcode (void)
17058 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17059 return NOP_OPCODE_MICROMIPS;
17060 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17061 return NOP_OPCODE_MIPS16;
17063 return NOP_OPCODE_MIPS;
17066 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17067 32-bit microMIPS NOPs here (if applicable). */
17070 mips_handle_align (fragS *fragp)
17074 int bytes, size, excess;
17077 if (fragp->fr_type != rs_align_code)
17080 p = fragp->fr_literal + fragp->fr_fix;
17082 switch (nop_opcode)
17084 case NOP_OPCODE_MICROMIPS:
17085 opcode = micromips_nop32_insn.insn_opcode;
17088 case NOP_OPCODE_MIPS16:
17089 opcode = mips16_nop_insn.insn_opcode;
17092 case NOP_OPCODE_MIPS:
17094 opcode = nop_insn.insn_opcode;
17099 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17100 excess = bytes % size;
17102 /* Handle the leading part if we're not inserting a whole number of
17103 instructions, and make it the end of the fixed part of the frag.
17104 Try to fit in a short microMIPS NOP if applicable and possible,
17105 and use zeroes otherwise. */
17106 gas_assert (excess < 4);
17107 fragp->fr_fix += excess;
17112 /* Fall through. */
17114 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
17116 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
17120 /* Fall through. */
17123 /* Fall through. */
17128 md_number_to_chars (p, opcode, size);
17129 fragp->fr_var = size;
17133 md_obj_begin (void)
17140 /* Check for premature end, nesting errors, etc. */
17142 as_warn (_("missing .end at end of assembly"));
17151 if (*input_line_pointer == '-')
17153 ++input_line_pointer;
17156 if (!ISDIGIT (*input_line_pointer))
17157 as_bad (_("expected simple number"));
17158 if (input_line_pointer[0] == '0')
17160 if (input_line_pointer[1] == 'x')
17162 input_line_pointer += 2;
17163 while (ISXDIGIT (*input_line_pointer))
17166 val |= hex_value (*input_line_pointer++);
17168 return negative ? -val : val;
17172 ++input_line_pointer;
17173 while (ISDIGIT (*input_line_pointer))
17176 val |= *input_line_pointer++ - '0';
17178 return negative ? -val : val;
17181 if (!ISDIGIT (*input_line_pointer))
17183 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17184 *input_line_pointer, *input_line_pointer);
17185 as_warn (_("invalid number"));
17188 while (ISDIGIT (*input_line_pointer))
17191 val += *input_line_pointer++ - '0';
17193 return negative ? -val : val;
17196 /* The .file directive; just like the usual .file directive, but there
17197 is an initial number which is the ECOFF file index. In the non-ECOFF
17198 case .file implies DWARF-2. */
17201 s_mips_file (int x ATTRIBUTE_UNUSED)
17203 static int first_file_directive = 0;
17205 if (ECOFF_DEBUGGING)
17214 filename = dwarf2_directive_file (0);
17216 /* Versions of GCC up to 3.1 start files with a ".file"
17217 directive even for stabs output. Make sure that this
17218 ".file" is handled. Note that you need a version of GCC
17219 after 3.1 in order to support DWARF-2 on MIPS. */
17220 if (filename != NULL && ! first_file_directive)
17222 (void) new_logical_line (filename, -1);
17223 s_app_file_string (filename, 0);
17225 first_file_directive = 1;
17229 /* The .loc directive, implying DWARF-2. */
17232 s_mips_loc (int x ATTRIBUTE_UNUSED)
17234 if (!ECOFF_DEBUGGING)
17235 dwarf2_directive_loc (0);
17238 /* The .end directive. */
17241 s_mips_end (int x ATTRIBUTE_UNUSED)
17245 /* Following functions need their own .frame and .cprestore directives. */
17246 mips_frame_reg_valid = 0;
17247 mips_cprestore_valid = 0;
17249 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17252 demand_empty_rest_of_line ();
17257 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17258 as_warn (_(".end not in text section"));
17262 as_warn (_(".end directive without a preceding .ent directive."));
17263 demand_empty_rest_of_line ();
17269 gas_assert (S_GET_NAME (p));
17270 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
17271 as_warn (_(".end symbol does not match .ent symbol."));
17273 if (debug_type == DEBUG_STABS)
17274 stabs_generate_asm_endfunc (S_GET_NAME (p),
17278 as_warn (_(".end directive missing or unknown symbol"));
17280 /* Create an expression to calculate the size of the function. */
17281 if (p && cur_proc_ptr)
17283 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17284 expressionS *exp = xmalloc (sizeof (expressionS));
17287 exp->X_op = O_subtract;
17288 exp->X_add_symbol = symbol_temp_new_now ();
17289 exp->X_op_symbol = p;
17290 exp->X_add_number = 0;
17292 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17295 /* Generate a .pdr section. */
17296 if (!ECOFF_DEBUGGING && mips_flag_pdr)
17298 segT saved_seg = now_seg;
17299 subsegT saved_subseg = now_subseg;
17303 #ifdef md_flush_pending_output
17304 md_flush_pending_output ();
17307 gas_assert (pdr_seg);
17308 subseg_set (pdr_seg, 0);
17310 /* Write the symbol. */
17311 exp.X_op = O_symbol;
17312 exp.X_add_symbol = p;
17313 exp.X_add_number = 0;
17314 emit_expr (&exp, 4);
17316 fragp = frag_more (7 * 4);
17318 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17319 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17320 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17321 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17322 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17323 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17324 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
17326 subseg_set (saved_seg, saved_subseg);
17329 cur_proc_ptr = NULL;
17332 /* The .aent and .ent directives. */
17335 s_mips_ent (int aent)
17339 symbolP = get_symbol ();
17340 if (*input_line_pointer == ',')
17341 ++input_line_pointer;
17342 SKIP_WHITESPACE ();
17343 if (ISDIGIT (*input_line_pointer)
17344 || *input_line_pointer == '-')
17347 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17348 as_warn (_(".ent or .aent not in text section."));
17350 if (!aent && cur_proc_ptr)
17351 as_warn (_("missing .end"));
17355 /* This function needs its own .frame and .cprestore directives. */
17356 mips_frame_reg_valid = 0;
17357 mips_cprestore_valid = 0;
17359 cur_proc_ptr = &cur_proc;
17360 memset (cur_proc_ptr, '\0', sizeof (procS));
17362 cur_proc_ptr->func_sym = symbolP;
17366 if (debug_type == DEBUG_STABS)
17367 stabs_generate_asm_func (S_GET_NAME (symbolP),
17368 S_GET_NAME (symbolP));
17371 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17373 demand_empty_rest_of_line ();
17376 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17377 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17378 s_mips_frame is used so that we can set the PDR information correctly.
17379 We can't use the ecoff routines because they make reference to the ecoff
17380 symbol table (in the mdebug section). */
17383 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
17385 if (ECOFF_DEBUGGING)
17391 if (cur_proc_ptr == (procS *) NULL)
17393 as_warn (_(".frame outside of .ent"));
17394 demand_empty_rest_of_line ();
17398 cur_proc_ptr->frame_reg = tc_get_register (1);
17400 SKIP_WHITESPACE ();
17401 if (*input_line_pointer++ != ','
17402 || get_absolute_expression_and_terminator (&val) != ',')
17404 as_warn (_("Bad .frame directive"));
17405 --input_line_pointer;
17406 demand_empty_rest_of_line ();
17410 cur_proc_ptr->frame_offset = val;
17411 cur_proc_ptr->pc_reg = tc_get_register (0);
17413 demand_empty_rest_of_line ();
17417 /* The .fmask and .mask directives. If the mdebug section is present
17418 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17419 embedded targets, s_mips_mask is used so that we can set the PDR
17420 information correctly. We can't use the ecoff routines because they
17421 make reference to the ecoff symbol table (in the mdebug section). */
17424 s_mips_mask (int reg_type)
17426 if (ECOFF_DEBUGGING)
17427 s_ignore (reg_type);
17432 if (cur_proc_ptr == (procS *) NULL)
17434 as_warn (_(".mask/.fmask outside of .ent"));
17435 demand_empty_rest_of_line ();
17439 if (get_absolute_expression_and_terminator (&mask) != ',')
17441 as_warn (_("Bad .mask/.fmask directive"));
17442 --input_line_pointer;
17443 demand_empty_rest_of_line ();
17447 off = get_absolute_expression ();
17449 if (reg_type == 'F')
17451 cur_proc_ptr->fpreg_mask = mask;
17452 cur_proc_ptr->fpreg_offset = off;
17456 cur_proc_ptr->reg_mask = mask;
17457 cur_proc_ptr->reg_offset = off;
17460 demand_empty_rest_of_line ();
17464 /* A table describing all the processors gas knows about. Names are
17465 matched in the order listed.
17467 To ease comparison, please keep this table in the same order as
17468 gcc's mips_cpu_info_table[]. */
17469 static const struct mips_cpu_info mips_cpu_info_table[] =
17471 /* Entries for generic ISAs */
17472 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17473 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17474 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17475 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17476 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17477 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17478 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17479 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17480 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
17483 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17484 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17485 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
17488 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
17491 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17492 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17493 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17494 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17495 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17496 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17497 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17498 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17499 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17500 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17501 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17502 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17503 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
17504 /* ST Microelectronics Loongson 2E and 2F cores */
17505 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17506 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
17509 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17510 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17511 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17512 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17513 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17514 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17515 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17516 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17517 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17518 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17519 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17520 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17521 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17522 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17523 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
17526 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17527 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17528 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17529 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
17531 /* MIPS 32 Release 2 */
17532 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17533 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17534 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17535 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17536 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17537 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17538 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17539 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17540 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17541 ISA_MIPS32R2, CPU_MIPS32R2 },
17542 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17543 ISA_MIPS32R2, CPU_MIPS32R2 },
17544 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17545 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17546 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17547 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17548 /* Deprecated forms of the above. */
17549 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17550 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17551 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17552 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17553 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17554 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17555 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17556 /* Deprecated forms of the above. */
17557 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17558 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17559 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17560 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17561 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17562 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17563 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17564 /* Deprecated forms of the above. */
17565 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17566 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17567 /* 34Kn is a 34kc without DSP. */
17568 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17569 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17570 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17571 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17572 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17573 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17574 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17575 /* Deprecated forms of the above. */
17576 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17577 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17578 /* 1004K cores are multiprocessor versions of the 34K. */
17579 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17580 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17581 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17582 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17585 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17586 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17587 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17588 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17590 /* Broadcom SB-1 CPU core */
17591 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17592 /* Broadcom SB-1A CPU core */
17593 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17595 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
17597 /* MIPS 64 Release 2 */
17599 /* Cavium Networks Octeon CPU core */
17600 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17601 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17602 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
17605 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
17608 XLP is mostly like XLR, with the prominent exception that it is
17609 MIPS64R2 rather than MIPS64. */
17610 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
17613 { NULL, 0, 0, 0, 0 }
17617 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17618 with a final "000" replaced by "k". Ignore case.
17620 Note: this function is shared between GCC and GAS. */
17623 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
17625 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17626 given++, canonical++;
17628 return ((*given == 0 && *canonical == 0)
17629 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17633 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17634 CPU name. We've traditionally allowed a lot of variation here.
17636 Note: this function is shared between GCC and GAS. */
17639 mips_matching_cpu_name_p (const char *canonical, const char *given)
17641 /* First see if the name matches exactly, or with a final "000"
17642 turned into "k". */
17643 if (mips_strict_matching_cpu_name_p (canonical, given))
17646 /* If not, try comparing based on numerical designation alone.
17647 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17648 if (TOLOWER (*given) == 'r')
17650 if (!ISDIGIT (*given))
17653 /* Skip over some well-known prefixes in the canonical name,
17654 hoping to find a number there too. */
17655 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
17657 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
17659 else if (TOLOWER (canonical[0]) == 'r')
17662 return mips_strict_matching_cpu_name_p (canonical, given);
17666 /* Parse an option that takes the name of a processor as its argument.
17667 OPTION is the name of the option and CPU_STRING is the argument.
17668 Return the corresponding processor enumeration if the CPU_STRING is
17669 recognized, otherwise report an error and return null.
17671 A similar function exists in GCC. */
17673 static const struct mips_cpu_info *
17674 mips_parse_cpu (const char *option, const char *cpu_string)
17676 const struct mips_cpu_info *p;
17678 /* 'from-abi' selects the most compatible architecture for the given
17679 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17680 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17681 version. Look first at the -mgp options, if given, otherwise base
17682 the choice on MIPS_DEFAULT_64BIT.
17684 Treat NO_ABI like the EABIs. One reason to do this is that the
17685 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17686 architecture. This code picks MIPS I for 'mips' and MIPS III for
17687 'mips64', just as we did in the days before 'from-abi'. */
17688 if (strcasecmp (cpu_string, "from-abi") == 0)
17690 if (ABI_NEEDS_32BIT_REGS (mips_abi))
17691 return mips_cpu_info_from_isa (ISA_MIPS1);
17693 if (ABI_NEEDS_64BIT_REGS (mips_abi))
17694 return mips_cpu_info_from_isa (ISA_MIPS3);
17696 if (file_mips_gp32 >= 0)
17697 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
17699 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
17704 /* 'default' has traditionally been a no-op. Probably not very useful. */
17705 if (strcasecmp (cpu_string, "default") == 0)
17708 for (p = mips_cpu_info_table; p->name != 0; p++)
17709 if (mips_matching_cpu_name_p (p->name, cpu_string))
17712 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
17716 /* Return the canonical processor information for ISA (a member of the
17717 ISA_MIPS* enumeration). */
17719 static const struct mips_cpu_info *
17720 mips_cpu_info_from_isa (int isa)
17724 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17725 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
17726 && isa == mips_cpu_info_table[i].isa)
17727 return (&mips_cpu_info_table[i]);
17732 static const struct mips_cpu_info *
17733 mips_cpu_info_from_arch (int arch)
17737 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17738 if (arch == mips_cpu_info_table[i].cpu)
17739 return (&mips_cpu_info_table[i]);
17745 show (FILE *stream, const char *string, int *col_p, int *first_p)
17749 fprintf (stream, "%24s", "");
17754 fprintf (stream, ", ");
17758 if (*col_p + strlen (string) > 72)
17760 fprintf (stream, "\n%24s", "");
17764 fprintf (stream, "%s", string);
17765 *col_p += strlen (string);
17771 md_show_usage (FILE *stream)
17776 fprintf (stream, _("\
17778 -EB generate big endian output\n\
17779 -EL generate little endian output\n\
17780 -g, -g2 do not remove unneeded NOPs or swap branches\n\
17781 -G NUM allow referencing objects up to NUM bytes\n\
17782 implicitly with the gp register [default 8]\n"));
17783 fprintf (stream, _("\
17784 -mips1 generate MIPS ISA I instructions\n\
17785 -mips2 generate MIPS ISA II instructions\n\
17786 -mips3 generate MIPS ISA III instructions\n\
17787 -mips4 generate MIPS ISA IV instructions\n\
17788 -mips5 generate MIPS ISA V instructions\n\
17789 -mips32 generate MIPS32 ISA instructions\n\
17790 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
17791 -mips64 generate MIPS64 ISA instructions\n\
17792 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
17793 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
17797 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
17798 show (stream, mips_cpu_info_table[i].name, &column, &first);
17799 show (stream, "from-abi", &column, &first);
17800 fputc ('\n', stream);
17802 fprintf (stream, _("\
17803 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
17804 -no-mCPU don't generate code specific to CPU.\n\
17805 For -mCPU and -no-mCPU, CPU must be one of:\n"));
17809 show (stream, "3900", &column, &first);
17810 show (stream, "4010", &column, &first);
17811 show (stream, "4100", &column, &first);
17812 show (stream, "4650", &column, &first);
17813 fputc ('\n', stream);
17815 fprintf (stream, _("\
17816 -mips16 generate mips16 instructions\n\
17817 -no-mips16 do not generate mips16 instructions\n"));
17818 fprintf (stream, _("\
17819 -mmicromips generate microMIPS instructions\n\
17820 -mno-micromips do not generate microMIPS instructions\n"));
17821 fprintf (stream, _("\
17822 -msmartmips generate smartmips instructions\n\
17823 -mno-smartmips do not generate smartmips instructions\n"));
17824 fprintf (stream, _("\
17825 -mdsp generate DSP instructions\n\
17826 -mno-dsp do not generate DSP instructions\n"));
17827 fprintf (stream, _("\
17828 -mdspr2 generate DSP R2 instructions\n\
17829 -mno-dspr2 do not generate DSP R2 instructions\n"));
17830 fprintf (stream, _("\
17831 -mmt generate MT instructions\n\
17832 -mno-mt do not generate MT instructions\n"));
17833 fprintf (stream, _("\
17834 -mmcu generate MCU instructions\n\
17835 -mno-mcu do not generate MCU instructions\n"));
17836 fprintf (stream, _("\
17837 -mvirt generate Virtualization instructions\n\
17838 -mno-virt do not generate Virtualization instructions\n"));
17839 fprintf (stream, _("\
17840 -minsn32 only generate 32-bit microMIPS instructions\n\
17841 -mno-insn32 generate all microMIPS instructions\n"));
17842 fprintf (stream, _("\
17843 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
17844 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
17845 -mfix-vr4120 work around certain VR4120 errata\n\
17846 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
17847 -mfix-24k insert a nop after ERET and DERET instructions\n\
17848 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
17849 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
17850 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
17851 -msym32 assume all symbols have 32-bit values\n\
17852 -O0 remove unneeded NOPs, do not swap branches\n\
17853 -O remove unneeded NOPs and swap branches\n\
17854 --trap, --no-break trap exception on div by 0 and mult overflow\n\
17855 --break, --no-trap break exception on div by 0 and mult overflow\n"));
17856 fprintf (stream, _("\
17857 -mhard-float allow floating-point instructions\n\
17858 -msoft-float do not allow floating-point instructions\n\
17859 -msingle-float only allow 32-bit floating-point operations\n\
17860 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
17861 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
17862 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
17863 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
17867 show (stream, "legacy", &column, &first);
17868 show (stream, "2008", &column, &first);
17870 fputc ('\n', stream);
17872 fprintf (stream, _("\
17873 -KPIC, -call_shared generate SVR4 position independent code\n\
17874 -call_nonpic generate non-PIC code that can operate with DSOs\n\
17875 -mvxworks-pic generate VxWorks position independent code\n\
17876 -non_shared do not generate code that can operate with DSOs\n\
17877 -xgot assume a 32 bit GOT\n\
17878 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
17879 -mshared, -mno-shared disable/enable .cpload optimization for\n\
17880 position dependent (non shared) code\n\
17881 -mabi=ABI create ABI conformant object file for:\n"));
17885 show (stream, "32", &column, &first);
17886 show (stream, "o64", &column, &first);
17887 show (stream, "n32", &column, &first);
17888 show (stream, "64", &column, &first);
17889 show (stream, "eabi", &column, &first);
17891 fputc ('\n', stream);
17893 fprintf (stream, _("\
17894 -32 create o32 ABI object file (default)\n\
17895 -n32 create n32 ABI object file\n\
17896 -64 create 64 ABI object file\n"));
17901 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
17903 if (HAVE_64BIT_SYMBOLS)
17904 return dwarf2_format_64bit_irix;
17906 return dwarf2_format_32bit;
17911 mips_dwarf2_addr_size (void)
17913 if (HAVE_64BIT_OBJECTS)
17919 /* Standard calling conventions leave the CFA at SP on entry. */
17921 mips_cfi_frame_initial_instructions (void)
17923 cfi_add_CFA_def_cfa_register (SP);
17927 tc_mips_regname_to_dw2regnum (char *regname)
17929 unsigned int regnum = -1;
17932 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))