1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
161 /* The ABI to use. */
172 /* MIPS ABI we are using for this output file. */
173 static enum mips_abi_level mips_abi = NO_ABI;
175 /* Whether or not we have code that can call pic code. */
176 int mips_abicalls = FALSE;
178 /* Whether or not we have code which can be put into a shared
180 static bfd_boolean mips_in_shared = TRUE;
182 /* This is the set of options which may be modified by the .set
183 pseudo-op. We use a struct so that .set push and .set pop are more
186 struct mips_set_options
188 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
189 if it has not been initialized. Changed by `.set mipsN', and the
190 -mipsN command line option, and the default CPU. */
192 /* Enabled Application Specific Extensions (ASEs). These are set to -1
193 if they have not been initialized. Changed by `.set <asename>', by
194 command line options, and based on the default architecture. */
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Non-zero if we should not reorder instructions. Changed by `.set
207 reorder' and `.set noreorder'. */
209 /* Non-zero if we should not permit the register designated "assembler
210 temporary" to be used in instructions. The value is the register
211 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
212 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
214 /* Non-zero if we should warn when a macro instruction expands into
215 more than one machine instruction. Changed by `.set nomacro' and
217 int warn_about_macros;
218 /* Non-zero if we should not move instructions. Changed by `.set
219 move', `.set volatile', `.set nomove', and `.set novolatile'. */
221 /* Non-zero if we should not optimize branches by moving the target
222 of the branch into the delay slot. Actually, we don't perform
223 this optimization anyhow. Changed by `.set bopt' and `.set
226 /* Non-zero if we should not autoextend mips16 instructions.
227 Changed by `.set autoextend' and `.set noautoextend'. */
229 /* Restrict general purpose registers and floating point registers
230 to 32 bit. This is initially determined when -mgp32 or -mfp32
231 is passed but can changed if the assembler code uses .set mipsN. */
234 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
235 command line option, and the default CPU. */
237 /* True if ".set sym32" is in effect. */
239 /* True if floating-point operations are not allowed. Changed by .set
240 softfloat or .set hardfloat, by command line options -msoft-float or
241 -mhard-float. The default is false. */
242 bfd_boolean soft_float;
244 /* True if only single-precision floating-point operations are allowed.
245 Changed by .set singlefloat or .set doublefloat, command-line options
246 -msingle-float or -mdouble-float. The default is false. */
247 bfd_boolean single_float;
250 /* This is the struct we use to hold the current set of options. Note
251 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
252 -1 to indicate that they have not been initialized. */
254 /* True if -mgp32 was passed. */
255 static int file_mips_gp32 = -1;
257 /* True if -mfp32 was passed. */
258 static int file_mips_fp32 = -1;
260 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
261 static int file_mips_soft_float = 0;
263 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
264 static int file_mips_single_float = 0;
266 static struct mips_set_options mips_opts =
268 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
269 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
270 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
271 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
272 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
273 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
276 /* These variables are filled in with the masks of registers used.
277 The object format code reads them and puts them in the appropriate
279 unsigned long mips_gprmask;
280 unsigned long mips_cprmask[4];
282 /* MIPS ISA we are using for this output file. */
283 static int file_mips_isa = ISA_UNKNOWN;
285 /* True if any MIPS16 code was produced. */
286 static int file_ase_mips16;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if we want to create R_MIPS_JALR for jalr $25. */
295 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
297 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
298 because there's no place for any addend, the only acceptable
299 expression is a bare symbol. */
300 #define MIPS_JALR_HINT_P(EXPR) \
301 (!HAVE_IN_PLACE_ADDENDS \
302 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
305 /* True if -mips3d was passed or implied by arguments passed on the
306 command line (e.g., by -march). */
307 static int file_ase_mips3d;
309 /* True if -mdmx was passed or implied by arguments passed on the
310 command line (e.g., by -march). */
311 static int file_ase_mdmx;
313 /* True if -msmartmips was passed or implied by arguments passed on the
314 command line (e.g., by -march). */
315 static int file_ase_smartmips;
317 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
318 || mips_opts.isa == ISA_MIPS32R2)
320 /* True if -mdsp was passed or implied by arguments passed on the
321 command line (e.g., by -march). */
322 static int file_ase_dsp;
324 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
325 || mips_opts.isa == ISA_MIPS64R2)
327 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
329 /* True if -mdspr2 was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_dspr2;
333 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
334 || mips_opts.isa == ISA_MIPS64R2)
336 /* True if -mmt was passed or implied by arguments passed on the
337 command line (e.g., by -march). */
338 static int file_ase_mt;
340 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
341 || mips_opts.isa == ISA_MIPS64R2)
343 /* The argument of the -march= flag. The architecture we are assembling. */
344 static int file_mips_arch = CPU_UNKNOWN;
345 static const char *mips_arch_string;
347 /* The argument of the -mtune= flag. The architecture for which we
349 static int mips_tune = CPU_UNKNOWN;
350 static const char *mips_tune_string;
352 /* True when generating 32-bit code for a 64-bit processor. */
353 static int mips_32bitmode = 0;
355 /* True if the given ABI requires 32-bit registers. */
356 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
358 /* Likewise 64-bit registers. */
359 #define ABI_NEEDS_64BIT_REGS(ABI) \
361 || (ABI) == N64_ABI \
364 /* Return true if ISA supports 64 bit wide gp registers. */
365 #define ISA_HAS_64BIT_REGS(ISA) \
366 ((ISA) == ISA_MIPS3 \
367 || (ISA) == ISA_MIPS4 \
368 || (ISA) == ISA_MIPS5 \
369 || (ISA) == ISA_MIPS64 \
370 || (ISA) == ISA_MIPS64R2)
372 /* Return true if ISA supports 64 bit wide float registers. */
373 #define ISA_HAS_64BIT_FPRS(ISA) \
374 ((ISA) == ISA_MIPS3 \
375 || (ISA) == ISA_MIPS4 \
376 || (ISA) == ISA_MIPS5 \
377 || (ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64 \
379 || (ISA) == ISA_MIPS64R2)
381 /* Return true if ISA supports 64-bit right rotate (dror et al.)
383 #define ISA_HAS_DROR(ISA) \
384 ((ISA) == ISA_MIPS64R2)
386 /* Return true if ISA supports 32-bit right rotate (ror et al.)
388 #define ISA_HAS_ROR(ISA) \
389 ((ISA) == ISA_MIPS32R2 \
390 || (ISA) == ISA_MIPS64R2 \
391 || mips_opts.ase_smartmips)
393 /* Return true if ISA supports single-precision floats in odd registers. */
394 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
395 ((ISA) == ISA_MIPS32 \
396 || (ISA) == ISA_MIPS32R2 \
397 || (ISA) == ISA_MIPS64 \
398 || (ISA) == ISA_MIPS64R2)
400 /* Return true if ISA supports move to/from high part of a 64-bit
401 floating-point register. */
402 #define ISA_HAS_MXHC1(ISA) \
403 ((ISA) == ISA_MIPS32R2 \
404 || (ISA) == ISA_MIPS64R2)
406 #define HAVE_32BIT_GPRS \
407 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
409 #define HAVE_32BIT_FPRS \
410 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
412 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
413 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
415 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
417 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
419 /* True if relocations are stored in-place. */
420 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
422 /* The ABI-derived address size. */
423 #define HAVE_64BIT_ADDRESSES \
424 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
425 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
427 /* The size of symbolic constants (i.e., expressions of the form
428 "SYMBOL" or "SYMBOL + OFFSET"). */
429 #define HAVE_32BIT_SYMBOLS \
430 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
431 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
433 /* Addresses are loaded in different ways, depending on the address size
434 in use. The n32 ABI Documentation also mandates the use of additions
435 with overflow checking, but existing implementations don't follow it. */
436 #define ADDRESS_ADD_INSN \
437 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
439 #define ADDRESS_ADDI_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
442 #define ADDRESS_LOAD_INSN \
443 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
445 #define ADDRESS_STORE_INSN \
446 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
448 /* Return true if the given CPU supports the MIPS16 ASE. */
449 #define CPU_HAS_MIPS16(cpu) \
450 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
451 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
453 /* True if CPU has a dror instruction. */
454 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
456 /* True if CPU has a ror instruction. */
457 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
459 /* True if CPU has seq/sne and seqi/snei instructions. */
460 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
462 /* True if CPU does not implement the all the coprocessor insns. For these
463 CPUs only those COP insns are accepted that are explicitly marked to be
464 available on the CPU. ISA membership for COP insns is ignored. */
465 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
467 /* True if mflo and mfhi can be immediately followed by instructions
468 which write to the HI and LO registers.
470 According to MIPS specifications, MIPS ISAs I, II, and III need
471 (at least) two instructions between the reads of HI/LO and
472 instructions which write them, and later ISAs do not. Contradicting
473 the MIPS specifications, some MIPS IV processor user manuals (e.g.
474 the UM for the NEC Vr5000) document needing the instructions between
475 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
476 MIPS64 and later ISAs to have the interlocks, plus any specific
477 earlier-ISA CPUs for which CPU documentation declares that the
478 instructions are really interlocked. */
479 #define hilo_interlocks \
480 (mips_opts.isa == ISA_MIPS32 \
481 || mips_opts.isa == ISA_MIPS32R2 \
482 || mips_opts.isa == ISA_MIPS64 \
483 || mips_opts.isa == ISA_MIPS64R2 \
484 || mips_opts.arch == CPU_R4010 \
485 || mips_opts.arch == CPU_R10000 \
486 || mips_opts.arch == CPU_R12000 \
487 || mips_opts.arch == CPU_R14000 \
488 || mips_opts.arch == CPU_R16000 \
489 || mips_opts.arch == CPU_RM7000 \
490 || mips_opts.arch == CPU_VR5500 \
493 /* Whether the processor uses hardware interlocks to protect reads
494 from the GPRs after they are loaded from memory, and thus does not
495 require nops to be inserted. This applies to instructions marked
496 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
498 #define gpr_interlocks \
499 (mips_opts.isa != ISA_MIPS1 \
500 || mips_opts.arch == CPU_R3900)
502 /* Whether the processor uses hardware interlocks to avoid delays
503 required by coprocessor instructions, and thus does not require
504 nops to be inserted. This applies to instructions marked
505 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
506 between instructions marked INSN_WRITE_COND_CODE and ones marked
507 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
508 levels I, II, and III. */
509 /* Itbl support may require additional care here. */
510 #define cop_interlocks \
511 ((mips_opts.isa != ISA_MIPS1 \
512 && mips_opts.isa != ISA_MIPS2 \
513 && mips_opts.isa != ISA_MIPS3) \
514 || mips_opts.arch == CPU_R4300 \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I. */
522 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
524 /* Is this a mfhi or mflo instruction? */
525 #define MF_HILO_INSN(PINFO) \
526 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
528 /* Returns true for a (non floating-point) coprocessor instruction. Reading
529 or writing the condition code is only possible on the coprocessors and
530 these insns are not marked with INSN_COP. Thus for these insns use the
531 condition-code flags. */
532 #define COP_INSN(PINFO) \
533 (PINFO != INSN_MACRO \
534 && ((PINFO) & (FP_S | FP_D)) == 0 \
535 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
537 /* MIPS PIC level. */
539 enum mips_pic_level mips_pic;
541 /* 1 if we should generate 32 bit offsets from the $gp register in
542 SVR4_PIC mode. Currently has no meaning in other modes. */
543 static int mips_big_got = 0;
545 /* 1 if trap instructions should used for overflow rather than break
547 static int mips_trap = 0;
549 /* 1 if double width floating point constants should not be constructed
550 by assembling two single width halves into two single width floating
551 point registers which just happen to alias the double width destination
552 register. On some architectures this aliasing can be disabled by a bit
553 in the status register, and the setting of this bit cannot be determined
554 automatically at assemble time. */
555 static int mips_disable_float_construction;
557 /* Non-zero if any .set noreorder directives were used. */
559 static int mips_any_noreorder;
561 /* Non-zero if nops should be inserted when the register referenced in
562 an mfhi/mflo instruction is read in the next two instructions. */
563 static int mips_7000_hilo_fix;
565 /* The size of objects in the small data section. */
566 static unsigned int g_switch_value = 8;
567 /* Whether the -G option was used. */
568 static int g_switch_seen = 0;
573 /* If we can determine in advance that GP optimization won't be
574 possible, we can skip the relaxation stuff that tries to produce
575 GP-relative references. This makes delay slot optimization work
578 This function can only provide a guess, but it seems to work for
579 gcc output. It needs to guess right for gcc, otherwise gcc
580 will put what it thinks is a GP-relative instruction in a branch
583 I don't know if a fix is needed for the SVR4_PIC mode. I've only
584 fixed it for the non-PIC mode. KR 95/04/07 */
585 static int nopic_need_relax (symbolS *, int);
587 /* handle of the OPCODE hash table */
588 static struct hash_control *op_hash = NULL;
590 /* The opcode hash table we use for the mips16. */
591 static struct hash_control *mips16_op_hash = NULL;
593 /* This array holds the chars that always start a comment. If the
594 pre-processor is disabled, these aren't very useful */
595 const char comment_chars[] = "#";
597 /* This array holds the chars that only start a comment at the beginning of
598 a line. If the line seems to have the form '# 123 filename'
599 .line and .file directives will appear in the pre-processed output */
600 /* Note that input_file.c hand checks for '#' at the beginning of the
601 first line of the input file. This is because the compiler outputs
602 #NO_APP at the beginning of its output. */
603 /* Also note that C style comments are always supported. */
604 const char line_comment_chars[] = "#";
606 /* This array holds machine specific line separator characters. */
607 const char line_separator_chars[] = ";";
609 /* Chars that can be used to separate mant from exp in floating point nums */
610 const char EXP_CHARS[] = "eE";
612 /* Chars that mean this number is a floating point constant */
615 const char FLT_CHARS[] = "rRsSfFdDxXpP";
617 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
618 changed in read.c . Ideally it shouldn't have to know about it at all,
619 but nothing is ideal around here.
622 static char *insn_error;
624 static int auto_align = 1;
626 /* When outputting SVR4 PIC code, the assembler needs to know the
627 offset in the stack frame from which to restore the $gp register.
628 This is set by the .cprestore pseudo-op, and saved in this
630 static offsetT mips_cprestore_offset = -1;
632 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
633 more optimizations, it can use a register value instead of a memory-saved
634 offset and even an other register than $gp as global pointer. */
635 static offsetT mips_cpreturn_offset = -1;
636 static int mips_cpreturn_register = -1;
637 static int mips_gp_register = GP;
638 static int mips_gprel_offset = 0;
640 /* Whether mips_cprestore_offset has been set in the current function
641 (or whether it has already been warned about, if not). */
642 static int mips_cprestore_valid = 0;
644 /* This is the register which holds the stack frame, as set by the
645 .frame pseudo-op. This is needed to implement .cprestore. */
646 static int mips_frame_reg = SP;
648 /* Whether mips_frame_reg has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_frame_reg_valid = 0;
652 /* To output NOP instructions correctly, we need to keep information
653 about the previous two instructions. */
655 /* Whether we are optimizing. The default value of 2 means to remove
656 unneeded NOPs and swap branch instructions when possible. A value
657 of 1 means to not swap branches. A value of 0 means to always
659 static int mips_optimize = 2;
661 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
662 equivalent to seeing no -g option at all. */
663 static int mips_debug = 0;
665 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
666 #define MAX_VR4130_NOPS 4
668 /* The maximum number of NOPs needed to fill delay slots. */
669 #define MAX_DELAY_NOPS 2
671 /* The maximum number of NOPs needed for any purpose. */
674 /* A list of previous instructions, with index 0 being the most recent.
675 We need to look back MAX_NOPS instructions when filling delay slots
676 or working around processor errata. We need to look back one
677 instruction further if we're thinking about using history[0] to
678 fill a branch delay slot. */
679 static struct mips_cl_insn history[1 + MAX_NOPS];
681 /* Nop instructions used by emit_nop. */
682 static struct mips_cl_insn nop_insn, mips16_nop_insn;
684 /* The appropriate nop for the current mode. */
685 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
687 /* If this is set, it points to a frag holding nop instructions which
688 were inserted before the start of a noreorder section. If those
689 nops turn out to be unnecessary, the size of the frag can be
691 static fragS *prev_nop_frag;
693 /* The number of nop instructions we created in prev_nop_frag. */
694 static int prev_nop_frag_holds;
696 /* The number of nop instructions that we know we need in
698 static int prev_nop_frag_required;
700 /* The number of instructions we've seen since prev_nop_frag. */
701 static int prev_nop_frag_since;
703 /* For ECOFF and ELF, relocations against symbols are done in two
704 parts, with a HI relocation and a LO relocation. Each relocation
705 has only 16 bits of space to store an addend. This means that in
706 order for the linker to handle carries correctly, it must be able
707 to locate both the HI and the LO relocation. This means that the
708 relocations must appear in order in the relocation table.
710 In order to implement this, we keep track of each unmatched HI
711 relocation. We then sort them so that they immediately precede the
712 corresponding LO relocation. */
717 struct mips_hi_fixup *next;
720 /* The section this fixup is in. */
724 /* The list of unmatched HI relocs. */
726 static struct mips_hi_fixup *mips_hi_fixup_list;
728 /* The frag containing the last explicit relocation operator.
729 Null if explicit relocations have not been used. */
731 static fragS *prev_reloc_op_frag;
733 /* Map normal MIPS register numbers to mips16 register numbers. */
735 #define X ILLEGAL_REG
736 static const int mips32_to_16_reg_map[] =
738 X, X, 2, 3, 4, 5, 6, 7,
739 X, X, X, X, X, X, X, X,
740 0, 1, X, X, X, X, X, X,
741 X, X, X, X, X, X, X, X
745 /* Map mips16 register numbers to normal MIPS register numbers. */
747 static const unsigned int mips16_to_32_reg_map[] =
749 16, 17, 2, 3, 4, 5, 6, 7
752 /* Classifies the kind of instructions we're interested in when
753 implementing -mfix-vr4120. */
754 enum fix_vr4120_class
762 NUM_FIX_VR4120_CLASSES
765 /* ...likewise -mfix-loongson2f-jump. */
766 static bfd_boolean mips_fix_loongson2f_jump;
768 /* ...likewise -mfix-loongson2f-nop. */
769 static bfd_boolean mips_fix_loongson2f_nop;
771 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
772 static bfd_boolean mips_fix_loongson2f;
774 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
775 there must be at least one other instruction between an instruction
776 of type X and an instruction of type Y. */
777 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
779 /* True if -mfix-vr4120 is in force. */
780 static int mips_fix_vr4120;
782 /* ...likewise -mfix-vr4130. */
783 static int mips_fix_vr4130;
785 /* ...likewise -mfix-24k. */
786 static int mips_fix_24k;
788 /* ...likewise -mfix-cn63xxp1 */
789 static bfd_boolean mips_fix_cn63xxp1;
791 /* We don't relax branches by default, since this causes us to expand
792 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
793 fail to compute the offset before expanding the macro to the most
794 efficient expansion. */
796 static int mips_relax_branch;
798 /* The expansion of many macros depends on the type of symbol that
799 they refer to. For example, when generating position-dependent code,
800 a macro that refers to a symbol may have two different expansions,
801 one which uses GP-relative addresses and one which uses absolute
802 addresses. When generating SVR4-style PIC, a macro may have
803 different expansions for local and global symbols.
805 We handle these situations by generating both sequences and putting
806 them in variant frags. In position-dependent code, the first sequence
807 will be the GP-relative one and the second sequence will be the
808 absolute one. In SVR4 PIC, the first sequence will be for global
809 symbols and the second will be for local symbols.
811 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
812 SECOND are the lengths of the two sequences in bytes. These fields
813 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
814 the subtype has the following flags:
817 Set if it has been decided that we should use the second
818 sequence instead of the first.
821 Set in the first variant frag if the macro's second implementation
822 is longer than its first. This refers to the macro as a whole,
823 not an individual relaxation.
826 Set in the first variant frag if the macro appeared in a .set nomacro
827 block and if one alternative requires a warning but the other does not.
830 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
833 The frag's "opcode" points to the first fixup for relaxable code.
835 Relaxable macros are generated using a sequence such as:
837 relax_start (SYMBOL);
838 ... generate first expansion ...
840 ... generate second expansion ...
843 The code and fixups for the unwanted alternative are discarded
844 by md_convert_frag. */
845 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
847 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
848 #define RELAX_SECOND(X) ((X) & 0xff)
849 #define RELAX_USE_SECOND 0x10000
850 #define RELAX_SECOND_LONGER 0x20000
851 #define RELAX_NOMACRO 0x40000
852 #define RELAX_DELAY_SLOT 0x80000
854 /* Branch without likely bit. If label is out of range, we turn:
856 beq reg1, reg2, label
866 with the following opcode replacements:
873 bltzal <-> bgezal (with jal label instead of j label)
875 Even though keeping the delay slot instruction in the delay slot of
876 the branch would be more efficient, it would be very tricky to do
877 correctly, because we'd have to introduce a variable frag *after*
878 the delay slot instruction, and expand that instead. Let's do it
879 the easy way for now, even if the branch-not-taken case now costs
880 one additional instruction. Out-of-range branches are not supposed
881 to be common, anyway.
883 Branch likely. If label is out of range, we turn:
885 beql reg1, reg2, label
886 delay slot (annulled if branch not taken)
895 delay slot (executed only if branch taken)
898 It would be possible to generate a shorter sequence by losing the
899 likely bit, generating something like:
904 delay slot (executed only if branch taken)
916 bltzall -> bgezal (with jal label instead of j label)
917 bgezall -> bltzal (ditto)
920 but it's not clear that it would actually improve performance. */
921 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
924 | ((toofar) ? 1 : 0) \
926 | ((likely) ? 4 : 0) \
927 | ((uncond) ? 8 : 0)))
928 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
929 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
930 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
931 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
932 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
934 /* For mips16 code, we use an entirely different form of relaxation.
935 mips16 supports two versions of most instructions which take
936 immediate values: a small one which takes some small value, and a
937 larger one which takes a 16 bit value. Since branches also follow
938 this pattern, relaxing these values is required.
940 We can assemble both mips16 and normal MIPS code in a single
941 object. Therefore, we need to support this type of relaxation at
942 the same time that we support the relaxation described above. We
943 use the high bit of the subtype field to distinguish these cases.
945 The information we store for this type of relaxation is the
946 argument code found in the opcode file for this relocation, whether
947 the user explicitly requested a small or extended form, and whether
948 the relocation is in a jump or jal delay slot. That tells us the
949 size of the value, and how it should be stored. We also store
950 whether the fragment is considered to be extended or not. We also
951 store whether this is known to be a branch to a different section,
952 whether we have tried to relax this frag yet, and whether we have
953 ever extended a PC relative fragment because of a shift count. */
954 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
957 | ((small) ? 0x100 : 0) \
958 | ((ext) ? 0x200 : 0) \
959 | ((dslot) ? 0x400 : 0) \
960 | ((jal_dslot) ? 0x800 : 0))
961 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
962 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
963 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
964 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
965 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
966 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
967 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
968 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
969 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
970 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
971 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
972 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
974 /* Is the given value a sign-extended 32-bit value? */
975 #define IS_SEXT_32BIT_NUM(x) \
976 (((x) &~ (offsetT) 0x7fffffff) == 0 \
977 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
979 /* Is the given value a sign-extended 16-bit value? */
980 #define IS_SEXT_16BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fff) == 0 \
982 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
984 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
985 #define IS_ZEXT_32BIT_NUM(x) \
986 (((x) &~ (offsetT) 0xffffffff) == 0 \
987 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
989 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
990 VALUE << SHIFT. VALUE is evaluated exactly once. */
991 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
992 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
993 | (((VALUE) & (MASK)) << (SHIFT)))
995 /* Extract bits MASK << SHIFT from STRUCT and shift them right
997 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
998 (((STRUCT) >> (SHIFT)) & (MASK))
1000 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1001 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1003 include/opcode/mips.h specifies operand fields using the macros
1004 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1005 with "MIPS16OP" instead of "OP". */
1006 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1007 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1008 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1009 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1010 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1012 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1013 #define EXTRACT_OPERAND(FIELD, INSN) \
1014 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1015 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1016 EXTRACT_BITS ((INSN).insn_opcode, \
1017 MIPS16OP_MASK_##FIELD, \
1018 MIPS16OP_SH_##FIELD)
1020 /* Global variables used when generating relaxable macros. See the
1021 comment above RELAX_ENCODE for more details about how relaxation
1024 /* 0 if we're not emitting a relaxable macro.
1025 1 if we're emitting the first of the two relaxation alternatives.
1026 2 if we're emitting the second alternative. */
1029 /* The first relaxable fixup in the current frag. (In other words,
1030 the first fixup that refers to relaxable code.) */
1033 /* sizes[0] says how many bytes of the first alternative are stored in
1034 the current frag. Likewise sizes[1] for the second alternative. */
1035 unsigned int sizes[2];
1037 /* The symbol on which the choice of sequence depends. */
1041 /* Global variables used to decide whether a macro needs a warning. */
1043 /* True if the macro is in a branch delay slot. */
1044 bfd_boolean delay_slot_p;
1046 /* For relaxable macros, sizes[0] is the length of the first alternative
1047 in bytes and sizes[1] is the length of the second alternative.
1048 For non-relaxable macros, both elements give the length of the
1050 unsigned int sizes[2];
1052 /* The first variant frag for this macro. */
1054 } mips_macro_warning;
1056 /* Prototypes for static functions. */
1058 #define internalError() \
1059 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1061 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1063 static void append_insn
1064 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1065 static void mips_no_prev_insn (void);
1066 static void macro_build (expressionS *, const char *, const char *, ...);
1067 static void mips16_macro_build
1068 (expressionS *, const char *, const char *, va_list *);
1069 static void load_register (int, expressionS *, int);
1070 static void macro_start (void);
1071 static void macro_end (void);
1072 static void macro (struct mips_cl_insn * ip);
1073 static void mips16_macro (struct mips_cl_insn * ip);
1074 static void mips_ip (char *str, struct mips_cl_insn * ip);
1075 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1076 static void mips16_immed
1077 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1078 unsigned long *, bfd_boolean *, unsigned short *);
1079 static size_t my_getSmallExpression
1080 (expressionS *, bfd_reloc_code_real_type *, char *);
1081 static void my_getExpression (expressionS *, char *);
1082 static void s_align (int);
1083 static void s_change_sec (int);
1084 static void s_change_section (int);
1085 static void s_cons (int);
1086 static void s_float_cons (int);
1087 static void s_mips_globl (int);
1088 static void s_option (int);
1089 static void s_mipsset (int);
1090 static void s_abicalls (int);
1091 static void s_cpload (int);
1092 static void s_cpsetup (int);
1093 static void s_cplocal (int);
1094 static void s_cprestore (int);
1095 static void s_cpreturn (int);
1096 static void s_dtprelword (int);
1097 static void s_dtpreldword (int);
1098 static void s_gpvalue (int);
1099 static void s_gpword (int);
1100 static void s_gpdword (int);
1101 static void s_cpadd (int);
1102 static void s_insn (int);
1103 static void md_obj_begin (void);
1104 static void md_obj_end (void);
1105 static void s_mips_ent (int);
1106 static void s_mips_end (int);
1107 static void s_mips_frame (int);
1108 static void s_mips_mask (int reg_type);
1109 static void s_mips_stab (int);
1110 static void s_mips_weakext (int);
1111 static void s_mips_file (int);
1112 static void s_mips_loc (int);
1113 static bfd_boolean pic_need_relax (symbolS *, asection *);
1114 static int relaxed_branch_length (fragS *, asection *, int);
1115 static int validate_mips_insn (const struct mips_opcode *);
1117 /* Table and functions used to map between CPU/ISA names, and
1118 ISA levels, and CPU numbers. */
1120 struct mips_cpu_info
1122 const char *name; /* CPU or ISA name. */
1123 int flags; /* ASEs available, or ISA flag. */
1124 int isa; /* ISA level. */
1125 int cpu; /* CPU number (default CPU if ISA). */
1128 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1129 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1130 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1131 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1132 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1133 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1134 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1136 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1137 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1138 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1142 The following pseudo-ops from the Kane and Heinrich MIPS book
1143 should be defined here, but are currently unsupported: .alias,
1144 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1146 The following pseudo-ops from the Kane and Heinrich MIPS book are
1147 specific to the type of debugging information being generated, and
1148 should be defined by the object format: .aent, .begin, .bend,
1149 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1152 The following pseudo-ops from the Kane and Heinrich MIPS book are
1153 not MIPS CPU specific, but are also not specific to the object file
1154 format. This file is probably the best place to define them, but
1155 they are not currently supported: .asm0, .endr, .lab, .struct. */
1157 static const pseudo_typeS mips_pseudo_table[] =
1159 /* MIPS specific pseudo-ops. */
1160 {"option", s_option, 0},
1161 {"set", s_mipsset, 0},
1162 {"rdata", s_change_sec, 'r'},
1163 {"sdata", s_change_sec, 's'},
1164 {"livereg", s_ignore, 0},
1165 {"abicalls", s_abicalls, 0},
1166 {"cpload", s_cpload, 0},
1167 {"cpsetup", s_cpsetup, 0},
1168 {"cplocal", s_cplocal, 0},
1169 {"cprestore", s_cprestore, 0},
1170 {"cpreturn", s_cpreturn, 0},
1171 {"dtprelword", s_dtprelword, 0},
1172 {"dtpreldword", s_dtpreldword, 0},
1173 {"gpvalue", s_gpvalue, 0},
1174 {"gpword", s_gpword, 0},
1175 {"gpdword", s_gpdword, 0},
1176 {"cpadd", s_cpadd, 0},
1177 {"insn", s_insn, 0},
1179 /* Relatively generic pseudo-ops that happen to be used on MIPS
1181 {"asciiz", stringer, 8 + 1},
1182 {"bss", s_change_sec, 'b'},
1184 {"half", s_cons, 1},
1185 {"dword", s_cons, 3},
1186 {"weakext", s_mips_weakext, 0},
1187 {"origin", s_org, 0},
1188 {"repeat", s_rept, 0},
1190 /* For MIPS this is non-standard, but we define it for consistency. */
1191 {"sbss", s_change_sec, 'B'},
1193 /* These pseudo-ops are defined in read.c, but must be overridden
1194 here for one reason or another. */
1195 {"align", s_align, 0},
1196 {"byte", s_cons, 0},
1197 {"data", s_change_sec, 'd'},
1198 {"double", s_float_cons, 'd'},
1199 {"float", s_float_cons, 'f'},
1200 {"globl", s_mips_globl, 0},
1201 {"global", s_mips_globl, 0},
1202 {"hword", s_cons, 1},
1204 {"long", s_cons, 2},
1205 {"octa", s_cons, 4},
1206 {"quad", s_cons, 3},
1207 {"section", s_change_section, 0},
1208 {"short", s_cons, 1},
1209 {"single", s_float_cons, 'f'},
1210 {"stabn", s_mips_stab, 'n'},
1211 {"text", s_change_sec, 't'},
1212 {"word", s_cons, 2},
1214 { "extern", ecoff_directive_extern, 0},
1219 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1221 /* These pseudo-ops should be defined by the object file format.
1222 However, a.out doesn't support them, so we have versions here. */
1223 {"aent", s_mips_ent, 1},
1224 {"bgnb", s_ignore, 0},
1225 {"end", s_mips_end, 0},
1226 {"endb", s_ignore, 0},
1227 {"ent", s_mips_ent, 0},
1228 {"file", s_mips_file, 0},
1229 {"fmask", s_mips_mask, 'F'},
1230 {"frame", s_mips_frame, 0},
1231 {"loc", s_mips_loc, 0},
1232 {"mask", s_mips_mask, 'R'},
1233 {"verstamp", s_ignore, 0},
1237 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1238 purpose of the `.dc.a' internal pseudo-op. */
1241 mips_address_bytes (void)
1243 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1246 extern void pop_insert (const pseudo_typeS *);
1249 mips_pop_insert (void)
1251 pop_insert (mips_pseudo_table);
1252 if (! ECOFF_DEBUGGING)
1253 pop_insert (mips_nonecoff_pseudo_table);
1256 /* Symbols labelling the current insn. */
1258 struct insn_label_list
1260 struct insn_label_list *next;
1264 static struct insn_label_list *free_insn_labels;
1265 #define label_list tc_segment_info_data.labels
1267 static void mips_clear_insn_labels (void);
1270 mips_clear_insn_labels (void)
1272 register struct insn_label_list **pl;
1273 segment_info_type *si;
1277 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1280 si = seg_info (now_seg);
1281 *pl = si->label_list;
1282 si->label_list = NULL;
1287 static char *expr_end;
1289 /* Expressions which appear in instructions. These are set by
1292 static expressionS imm_expr;
1293 static expressionS imm2_expr;
1294 static expressionS offset_expr;
1296 /* Relocs associated with imm_expr and offset_expr. */
1298 static bfd_reloc_code_real_type imm_reloc[3]
1299 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1300 static bfd_reloc_code_real_type offset_reloc[3]
1301 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1303 /* These are set by mips16_ip if an explicit extension is used. */
1305 static bfd_boolean mips16_small, mips16_ext;
1308 /* The pdr segment for per procedure frame/regmask info. Not used for
1311 static segT pdr_seg;
1314 /* The default target format to use. */
1317 mips_target_format (void)
1319 switch (OUTPUT_FLAVOR)
1321 case bfd_target_ecoff_flavour:
1322 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1323 case bfd_target_coff_flavour:
1325 case bfd_target_elf_flavour:
1327 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1328 return (target_big_endian
1329 ? "elf32-bigmips-vxworks"
1330 : "elf32-littlemips-vxworks");
1333 /* This is traditional mips. */
1334 return (target_big_endian
1335 ? (HAVE_64BIT_OBJECTS
1336 ? "elf64-tradbigmips"
1338 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1339 : (HAVE_64BIT_OBJECTS
1340 ? "elf64-tradlittlemips"
1342 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1344 return (target_big_endian
1345 ? (HAVE_64BIT_OBJECTS
1348 ? "elf32-nbigmips" : "elf32-bigmips"))
1349 : (HAVE_64BIT_OBJECTS
1350 ? "elf64-littlemips"
1352 ? "elf32-nlittlemips" : "elf32-littlemips")));
1360 /* Return the length of instruction INSN. */
1362 static inline unsigned int
1363 insn_length (const struct mips_cl_insn *insn)
1365 if (!mips_opts.mips16)
1367 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1370 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1373 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1378 insn->use_extend = FALSE;
1380 insn->insn_opcode = mo->match;
1383 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1384 insn->fixp[i] = NULL;
1385 insn->fixed_p = (mips_opts.noreorder > 0);
1386 insn->noreorder_p = (mips_opts.noreorder > 0);
1387 insn->mips16_absolute_jump_p = 0;
1390 /* Record the current MIPS16 mode in now_seg. */
1393 mips_record_mips16_mode (void)
1395 segment_info_type *si;
1397 si = seg_info (now_seg);
1398 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1399 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1402 /* Install INSN at the location specified by its "frag" and "where" fields. */
1405 install_insn (const struct mips_cl_insn *insn)
1407 char *f = insn->frag->fr_literal + insn->where;
1408 if (!mips_opts.mips16)
1409 md_number_to_chars (f, insn->insn_opcode, 4);
1410 else if (insn->mips16_absolute_jump_p)
1412 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1413 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1417 if (insn->use_extend)
1419 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1422 md_number_to_chars (f, insn->insn_opcode, 2);
1424 mips_record_mips16_mode ();
1427 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1428 and install the opcode in the new location. */
1431 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1436 insn->where = where;
1437 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1438 if (insn->fixp[i] != NULL)
1440 insn->fixp[i]->fx_frag = frag;
1441 insn->fixp[i]->fx_where = where;
1443 install_insn (insn);
1446 /* Add INSN to the end of the output. */
1449 add_fixed_insn (struct mips_cl_insn *insn)
1451 char *f = frag_more (insn_length (insn));
1452 move_insn (insn, frag_now, f - frag_now->fr_literal);
1455 /* Start a variant frag and move INSN to the start of the variant part,
1456 marking it as fixed. The other arguments are as for frag_var. */
1459 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1460 relax_substateT subtype, symbolS *symbol, offsetT offset)
1462 frag_grow (max_chars);
1463 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1465 frag_var (rs_machine_dependent, max_chars, var,
1466 subtype, symbol, offset, NULL);
1469 /* Insert N copies of INSN into the history buffer, starting at
1470 position FIRST. Neither FIRST nor N need to be clipped. */
1473 insert_into_history (unsigned int first, unsigned int n,
1474 const struct mips_cl_insn *insn)
1476 if (mips_relax.sequence != 2)
1480 for (i = ARRAY_SIZE (history); i-- > first;)
1482 history[i] = history[i - n];
1488 /* Emit a nop instruction, recording it in the history buffer. */
1493 add_fixed_insn (NOP_INSN);
1494 insert_into_history (0, 1, NOP_INSN);
1497 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1498 the idea is to make it obvious at a glance that each errata is
1502 init_vr4120_conflicts (void)
1504 #define CONFLICT(FIRST, SECOND) \
1505 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1507 /* Errata 21 - [D]DIV[U] after [D]MACC */
1508 CONFLICT (MACC, DIV);
1509 CONFLICT (DMACC, DIV);
1511 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1512 CONFLICT (DMULT, DMULT);
1513 CONFLICT (DMULT, DMACC);
1514 CONFLICT (DMACC, DMULT);
1515 CONFLICT (DMACC, DMACC);
1517 /* Errata 24 - MT{LO,HI} after [D]MACC */
1518 CONFLICT (MACC, MTHILO);
1519 CONFLICT (DMACC, MTHILO);
1521 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1522 instruction is executed immediately after a MACC or DMACC
1523 instruction, the result of [either instruction] is incorrect." */
1524 CONFLICT (MACC, MULT);
1525 CONFLICT (MACC, DMULT);
1526 CONFLICT (DMACC, MULT);
1527 CONFLICT (DMACC, DMULT);
1529 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1530 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1531 DDIV or DDIVU instruction, the result of the MACC or
1532 DMACC instruction is incorrect.". */
1533 CONFLICT (DMULT, MACC);
1534 CONFLICT (DMULT, DMACC);
1535 CONFLICT (DIV, MACC);
1536 CONFLICT (DIV, DMACC);
1546 #define RTYPE_MASK 0x1ff00
1547 #define RTYPE_NUM 0x00100
1548 #define RTYPE_FPU 0x00200
1549 #define RTYPE_FCC 0x00400
1550 #define RTYPE_VEC 0x00800
1551 #define RTYPE_GP 0x01000
1552 #define RTYPE_CP0 0x02000
1553 #define RTYPE_PC 0x04000
1554 #define RTYPE_ACC 0x08000
1555 #define RTYPE_CCC 0x10000
1556 #define RNUM_MASK 0x000ff
1557 #define RWARN 0x80000
1559 #define GENERIC_REGISTER_NUMBERS \
1560 {"$0", RTYPE_NUM | 0}, \
1561 {"$1", RTYPE_NUM | 1}, \
1562 {"$2", RTYPE_NUM | 2}, \
1563 {"$3", RTYPE_NUM | 3}, \
1564 {"$4", RTYPE_NUM | 4}, \
1565 {"$5", RTYPE_NUM | 5}, \
1566 {"$6", RTYPE_NUM | 6}, \
1567 {"$7", RTYPE_NUM | 7}, \
1568 {"$8", RTYPE_NUM | 8}, \
1569 {"$9", RTYPE_NUM | 9}, \
1570 {"$10", RTYPE_NUM | 10}, \
1571 {"$11", RTYPE_NUM | 11}, \
1572 {"$12", RTYPE_NUM | 12}, \
1573 {"$13", RTYPE_NUM | 13}, \
1574 {"$14", RTYPE_NUM | 14}, \
1575 {"$15", RTYPE_NUM | 15}, \
1576 {"$16", RTYPE_NUM | 16}, \
1577 {"$17", RTYPE_NUM | 17}, \
1578 {"$18", RTYPE_NUM | 18}, \
1579 {"$19", RTYPE_NUM | 19}, \
1580 {"$20", RTYPE_NUM | 20}, \
1581 {"$21", RTYPE_NUM | 21}, \
1582 {"$22", RTYPE_NUM | 22}, \
1583 {"$23", RTYPE_NUM | 23}, \
1584 {"$24", RTYPE_NUM | 24}, \
1585 {"$25", RTYPE_NUM | 25}, \
1586 {"$26", RTYPE_NUM | 26}, \
1587 {"$27", RTYPE_NUM | 27}, \
1588 {"$28", RTYPE_NUM | 28}, \
1589 {"$29", RTYPE_NUM | 29}, \
1590 {"$30", RTYPE_NUM | 30}, \
1591 {"$31", RTYPE_NUM | 31}
1593 #define FPU_REGISTER_NAMES \
1594 {"$f0", RTYPE_FPU | 0}, \
1595 {"$f1", RTYPE_FPU | 1}, \
1596 {"$f2", RTYPE_FPU | 2}, \
1597 {"$f3", RTYPE_FPU | 3}, \
1598 {"$f4", RTYPE_FPU | 4}, \
1599 {"$f5", RTYPE_FPU | 5}, \
1600 {"$f6", RTYPE_FPU | 6}, \
1601 {"$f7", RTYPE_FPU | 7}, \
1602 {"$f8", RTYPE_FPU | 8}, \
1603 {"$f9", RTYPE_FPU | 9}, \
1604 {"$f10", RTYPE_FPU | 10}, \
1605 {"$f11", RTYPE_FPU | 11}, \
1606 {"$f12", RTYPE_FPU | 12}, \
1607 {"$f13", RTYPE_FPU | 13}, \
1608 {"$f14", RTYPE_FPU | 14}, \
1609 {"$f15", RTYPE_FPU | 15}, \
1610 {"$f16", RTYPE_FPU | 16}, \
1611 {"$f17", RTYPE_FPU | 17}, \
1612 {"$f18", RTYPE_FPU | 18}, \
1613 {"$f19", RTYPE_FPU | 19}, \
1614 {"$f20", RTYPE_FPU | 20}, \
1615 {"$f21", RTYPE_FPU | 21}, \
1616 {"$f22", RTYPE_FPU | 22}, \
1617 {"$f23", RTYPE_FPU | 23}, \
1618 {"$f24", RTYPE_FPU | 24}, \
1619 {"$f25", RTYPE_FPU | 25}, \
1620 {"$f26", RTYPE_FPU | 26}, \
1621 {"$f27", RTYPE_FPU | 27}, \
1622 {"$f28", RTYPE_FPU | 28}, \
1623 {"$f29", RTYPE_FPU | 29}, \
1624 {"$f30", RTYPE_FPU | 30}, \
1625 {"$f31", RTYPE_FPU | 31}
1627 #define FPU_CONDITION_CODE_NAMES \
1628 {"$fcc0", RTYPE_FCC | 0}, \
1629 {"$fcc1", RTYPE_FCC | 1}, \
1630 {"$fcc2", RTYPE_FCC | 2}, \
1631 {"$fcc3", RTYPE_FCC | 3}, \
1632 {"$fcc4", RTYPE_FCC | 4}, \
1633 {"$fcc5", RTYPE_FCC | 5}, \
1634 {"$fcc6", RTYPE_FCC | 6}, \
1635 {"$fcc7", RTYPE_FCC | 7}
1637 #define COPROC_CONDITION_CODE_NAMES \
1638 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1639 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1640 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1641 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1642 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1643 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1644 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1645 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1647 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1648 {"$a4", RTYPE_GP | 8}, \
1649 {"$a5", RTYPE_GP | 9}, \
1650 {"$a6", RTYPE_GP | 10}, \
1651 {"$a7", RTYPE_GP | 11}, \
1652 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1653 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1654 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1655 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1656 {"$t0", RTYPE_GP | 12}, \
1657 {"$t1", RTYPE_GP | 13}, \
1658 {"$t2", RTYPE_GP | 14}, \
1659 {"$t3", RTYPE_GP | 15}
1661 #define O32_SYMBOLIC_REGISTER_NAMES \
1662 {"$t0", RTYPE_GP | 8}, \
1663 {"$t1", RTYPE_GP | 9}, \
1664 {"$t2", RTYPE_GP | 10}, \
1665 {"$t3", RTYPE_GP | 11}, \
1666 {"$t4", RTYPE_GP | 12}, \
1667 {"$t5", RTYPE_GP | 13}, \
1668 {"$t6", RTYPE_GP | 14}, \
1669 {"$t7", RTYPE_GP | 15}, \
1670 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1671 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1672 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1673 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1675 /* Remaining symbolic register names */
1676 #define SYMBOLIC_REGISTER_NAMES \
1677 {"$zero", RTYPE_GP | 0}, \
1678 {"$at", RTYPE_GP | 1}, \
1679 {"$AT", RTYPE_GP | 1}, \
1680 {"$v0", RTYPE_GP | 2}, \
1681 {"$v1", RTYPE_GP | 3}, \
1682 {"$a0", RTYPE_GP | 4}, \
1683 {"$a1", RTYPE_GP | 5}, \
1684 {"$a2", RTYPE_GP | 6}, \
1685 {"$a3", RTYPE_GP | 7}, \
1686 {"$s0", RTYPE_GP | 16}, \
1687 {"$s1", RTYPE_GP | 17}, \
1688 {"$s2", RTYPE_GP | 18}, \
1689 {"$s3", RTYPE_GP | 19}, \
1690 {"$s4", RTYPE_GP | 20}, \
1691 {"$s5", RTYPE_GP | 21}, \
1692 {"$s6", RTYPE_GP | 22}, \
1693 {"$s7", RTYPE_GP | 23}, \
1694 {"$t8", RTYPE_GP | 24}, \
1695 {"$t9", RTYPE_GP | 25}, \
1696 {"$k0", RTYPE_GP | 26}, \
1697 {"$kt0", RTYPE_GP | 26}, \
1698 {"$k1", RTYPE_GP | 27}, \
1699 {"$kt1", RTYPE_GP | 27}, \
1700 {"$gp", RTYPE_GP | 28}, \
1701 {"$sp", RTYPE_GP | 29}, \
1702 {"$s8", RTYPE_GP | 30}, \
1703 {"$fp", RTYPE_GP | 30}, \
1704 {"$ra", RTYPE_GP | 31}
1706 #define MIPS16_SPECIAL_REGISTER_NAMES \
1707 {"$pc", RTYPE_PC | 0}
1709 #define MDMX_VECTOR_REGISTER_NAMES \
1710 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1711 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1712 {"$v2", RTYPE_VEC | 2}, \
1713 {"$v3", RTYPE_VEC | 3}, \
1714 {"$v4", RTYPE_VEC | 4}, \
1715 {"$v5", RTYPE_VEC | 5}, \
1716 {"$v6", RTYPE_VEC | 6}, \
1717 {"$v7", RTYPE_VEC | 7}, \
1718 {"$v8", RTYPE_VEC | 8}, \
1719 {"$v9", RTYPE_VEC | 9}, \
1720 {"$v10", RTYPE_VEC | 10}, \
1721 {"$v11", RTYPE_VEC | 11}, \
1722 {"$v12", RTYPE_VEC | 12}, \
1723 {"$v13", RTYPE_VEC | 13}, \
1724 {"$v14", RTYPE_VEC | 14}, \
1725 {"$v15", RTYPE_VEC | 15}, \
1726 {"$v16", RTYPE_VEC | 16}, \
1727 {"$v17", RTYPE_VEC | 17}, \
1728 {"$v18", RTYPE_VEC | 18}, \
1729 {"$v19", RTYPE_VEC | 19}, \
1730 {"$v20", RTYPE_VEC | 20}, \
1731 {"$v21", RTYPE_VEC | 21}, \
1732 {"$v22", RTYPE_VEC | 22}, \
1733 {"$v23", RTYPE_VEC | 23}, \
1734 {"$v24", RTYPE_VEC | 24}, \
1735 {"$v25", RTYPE_VEC | 25}, \
1736 {"$v26", RTYPE_VEC | 26}, \
1737 {"$v27", RTYPE_VEC | 27}, \
1738 {"$v28", RTYPE_VEC | 28}, \
1739 {"$v29", RTYPE_VEC | 29}, \
1740 {"$v30", RTYPE_VEC | 30}, \
1741 {"$v31", RTYPE_VEC | 31}
1743 #define MIPS_DSP_ACCUMULATOR_NAMES \
1744 {"$ac0", RTYPE_ACC | 0}, \
1745 {"$ac1", RTYPE_ACC | 1}, \
1746 {"$ac2", RTYPE_ACC | 2}, \
1747 {"$ac3", RTYPE_ACC | 3}
1749 static const struct regname reg_names[] = {
1750 GENERIC_REGISTER_NUMBERS,
1752 FPU_CONDITION_CODE_NAMES,
1753 COPROC_CONDITION_CODE_NAMES,
1755 /* The $txx registers depends on the abi,
1756 these will be added later into the symbol table from
1757 one of the tables below once mips_abi is set after
1758 parsing of arguments from the command line. */
1759 SYMBOLIC_REGISTER_NAMES,
1761 MIPS16_SPECIAL_REGISTER_NAMES,
1762 MDMX_VECTOR_REGISTER_NAMES,
1763 MIPS_DSP_ACCUMULATOR_NAMES,
1767 static const struct regname reg_names_o32[] = {
1768 O32_SYMBOLIC_REGISTER_NAMES,
1772 static const struct regname reg_names_n32n64[] = {
1773 N32N64_SYMBOLIC_REGISTER_NAMES,
1778 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1785 /* Find end of name. */
1787 if (is_name_beginner (*e))
1789 while (is_part_of_name (*e))
1792 /* Terminate name. */
1796 /* Look for a register symbol. */
1797 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1799 int r = S_GET_VALUE (symbolP);
1801 reg = r & RNUM_MASK;
1802 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1803 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1804 reg = (r & RNUM_MASK) - 2;
1806 /* Else see if this is a register defined in an itbl entry. */
1807 else if ((types & RTYPE_GP) && itbl_have_entries)
1814 if (itbl_get_reg_val (n, &r))
1815 reg = r & RNUM_MASK;
1818 /* Advance to next token if a register was recognised. */
1821 else if (types & RWARN)
1822 as_warn (_("Unrecognized register name `%s'"), *s);
1830 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1831 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1834 is_opcode_valid (const struct mips_opcode *mo)
1836 int isa = mips_opts.isa;
1839 if (mips_opts.ase_mdmx)
1841 if (mips_opts.ase_dsp)
1843 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1845 if (mips_opts.ase_dspr2)
1847 if (mips_opts.ase_mt)
1849 if (mips_opts.ase_mips3d)
1851 if (mips_opts.ase_smartmips)
1852 isa |= INSN_SMARTMIPS;
1854 /* Don't accept instructions based on the ISA if the CPU does not implement
1855 all the coprocessor insns. */
1856 if (NO_ISA_COP (mips_opts.arch)
1857 && COP_INSN (mo->pinfo))
1860 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1863 /* Check whether the instruction or macro requires single-precision or
1864 double-precision floating-point support. Note that this information is
1865 stored differently in the opcode table for insns and macros. */
1866 if (mo->pinfo == INSN_MACRO)
1868 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1869 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1873 fp_s = mo->pinfo & FP_S;
1874 fp_d = mo->pinfo & FP_D;
1877 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1880 if (fp_s && mips_opts.soft_float)
1886 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1887 selected ISA and architecture. */
1890 is_opcode_valid_16 (const struct mips_opcode *mo)
1892 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1895 /* This function is called once, at assembler startup time. It should set up
1896 all the tables, etc. that the MD part of the assembler will need. */
1901 const char *retval = NULL;
1905 if (mips_pic != NO_PIC)
1907 if (g_switch_seen && g_switch_value != 0)
1908 as_bad (_("-G may not be used in position-independent code"));
1912 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1913 as_warn (_("Could not set architecture and machine"));
1915 op_hash = hash_new ();
1917 for (i = 0; i < NUMOPCODES;)
1919 const char *name = mips_opcodes[i].name;
1921 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1924 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1925 mips_opcodes[i].name, retval);
1926 /* Probably a memory allocation problem? Give up now. */
1927 as_fatal (_("Broken assembler. No assembly attempted."));
1931 if (mips_opcodes[i].pinfo != INSN_MACRO)
1933 if (!validate_mips_insn (&mips_opcodes[i]))
1935 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1937 create_insn (&nop_insn, mips_opcodes + i);
1938 if (mips_fix_loongson2f_nop)
1939 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1940 nop_insn.fixed_p = 1;
1945 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1948 mips16_op_hash = hash_new ();
1951 while (i < bfd_mips16_num_opcodes)
1953 const char *name = mips16_opcodes[i].name;
1955 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1957 as_fatal (_("internal: can't hash `%s': %s"),
1958 mips16_opcodes[i].name, retval);
1961 if (mips16_opcodes[i].pinfo != INSN_MACRO
1962 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1963 != mips16_opcodes[i].match))
1965 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1966 mips16_opcodes[i].name, mips16_opcodes[i].args);
1969 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1971 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1972 mips16_nop_insn.fixed_p = 1;
1976 while (i < bfd_mips16_num_opcodes
1977 && strcmp (mips16_opcodes[i].name, name) == 0);
1981 as_fatal (_("Broken assembler. No assembly attempted."));
1983 /* We add all the general register names to the symbol table. This
1984 helps us detect invalid uses of them. */
1985 for (i = 0; reg_names[i].name; i++)
1986 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1987 reg_names[i].num, /* & RNUM_MASK, */
1988 &zero_address_frag));
1990 for (i = 0; reg_names_n32n64[i].name; i++)
1991 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1992 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1993 &zero_address_frag));
1995 for (i = 0; reg_names_o32[i].name; i++)
1996 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
1997 reg_names_o32[i].num, /* & RNUM_MASK, */
1998 &zero_address_frag));
2000 mips_no_prev_insn ();
2003 mips_cprmask[0] = 0;
2004 mips_cprmask[1] = 0;
2005 mips_cprmask[2] = 0;
2006 mips_cprmask[3] = 0;
2008 /* set the default alignment for the text section (2**2) */
2009 record_alignment (text_section, 2);
2011 bfd_set_gp_size (stdoutput, g_switch_value);
2016 /* On a native system other than VxWorks, sections must be aligned
2017 to 16 byte boundaries. When configured for an embedded ELF
2018 target, we don't bother. */
2019 if (strncmp (TARGET_OS, "elf", 3) != 0
2020 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2022 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2023 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2024 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2027 /* Create a .reginfo section for register masks and a .mdebug
2028 section for debugging information. */
2036 subseg = now_subseg;
2038 /* The ABI says this section should be loaded so that the
2039 running program can access it. However, we don't load it
2040 if we are configured for an embedded target */
2041 flags = SEC_READONLY | SEC_DATA;
2042 if (strncmp (TARGET_OS, "elf", 3) != 0)
2043 flags |= SEC_ALLOC | SEC_LOAD;
2045 if (mips_abi != N64_ABI)
2047 sec = subseg_new (".reginfo", (subsegT) 0);
2049 bfd_set_section_flags (stdoutput, sec, flags);
2050 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2052 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2056 /* The 64-bit ABI uses a .MIPS.options section rather than
2057 .reginfo section. */
2058 sec = subseg_new (".MIPS.options", (subsegT) 0);
2059 bfd_set_section_flags (stdoutput, sec, flags);
2060 bfd_set_section_alignment (stdoutput, sec, 3);
2062 /* Set up the option header. */
2064 Elf_Internal_Options opthdr;
2067 opthdr.kind = ODK_REGINFO;
2068 opthdr.size = (sizeof (Elf_External_Options)
2069 + sizeof (Elf64_External_RegInfo));
2072 f = frag_more (sizeof (Elf_External_Options));
2073 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2074 (Elf_External_Options *) f);
2076 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2080 if (ECOFF_DEBUGGING)
2082 sec = subseg_new (".mdebug", (subsegT) 0);
2083 (void) bfd_set_section_flags (stdoutput, sec,
2084 SEC_HAS_CONTENTS | SEC_READONLY);
2085 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2087 else if (mips_flag_pdr)
2089 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2090 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2091 SEC_READONLY | SEC_RELOC
2093 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2096 subseg_set (seg, subseg);
2099 #endif /* OBJ_ELF */
2101 if (! ECOFF_DEBUGGING)
2104 if (mips_fix_vr4120)
2105 init_vr4120_conflicts ();
2111 if (! ECOFF_DEBUGGING)
2116 md_assemble (char *str)
2118 struct mips_cl_insn insn;
2119 bfd_reloc_code_real_type unused_reloc[3]
2120 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2122 imm_expr.X_op = O_absent;
2123 imm2_expr.X_op = O_absent;
2124 offset_expr.X_op = O_absent;
2125 imm_reloc[0] = BFD_RELOC_UNUSED;
2126 imm_reloc[1] = BFD_RELOC_UNUSED;
2127 imm_reloc[2] = BFD_RELOC_UNUSED;
2128 offset_reloc[0] = BFD_RELOC_UNUSED;
2129 offset_reloc[1] = BFD_RELOC_UNUSED;
2130 offset_reloc[2] = BFD_RELOC_UNUSED;
2132 if (mips_opts.mips16)
2133 mips16_ip (str, &insn);
2136 mips_ip (str, &insn);
2137 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2138 str, insn.insn_opcode));
2143 as_bad ("%s `%s'", insn_error, str);
2147 if (insn.insn_mo->pinfo == INSN_MACRO)
2150 if (mips_opts.mips16)
2151 mips16_macro (&insn);
2158 if (imm_expr.X_op != O_absent)
2159 append_insn (&insn, &imm_expr, imm_reloc);
2160 else if (offset_expr.X_op != O_absent)
2161 append_insn (&insn, &offset_expr, offset_reloc);
2163 append_insn (&insn, NULL, unused_reloc);
2167 /* Convenience functions for abstracting away the differences between
2168 MIPS16 and non-MIPS16 relocations. */
2170 static inline bfd_boolean
2171 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2175 case BFD_RELOC_MIPS16_JMP:
2176 case BFD_RELOC_MIPS16_GPREL:
2177 case BFD_RELOC_MIPS16_GOT16:
2178 case BFD_RELOC_MIPS16_CALL16:
2179 case BFD_RELOC_MIPS16_HI16_S:
2180 case BFD_RELOC_MIPS16_HI16:
2181 case BFD_RELOC_MIPS16_LO16:
2189 static inline bfd_boolean
2190 got16_reloc_p (bfd_reloc_code_real_type reloc)
2192 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2195 static inline bfd_boolean
2196 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2198 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2201 static inline bfd_boolean
2202 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2204 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2207 /* Return true if the given relocation might need a matching %lo().
2208 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2209 need a matching %lo() when applied to local symbols. */
2211 static inline bfd_boolean
2212 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2214 return (HAVE_IN_PLACE_ADDENDS
2215 && (hi16_reloc_p (reloc)
2216 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2217 all GOT16 relocations evaluate to "G". */
2218 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2221 /* Return the type of %lo() reloc needed by RELOC, given that
2222 reloc_needs_lo_p. */
2224 static inline bfd_reloc_code_real_type
2225 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2227 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2230 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2233 static inline bfd_boolean
2234 fixup_has_matching_lo_p (fixS *fixp)
2236 return (fixp->fx_next != NULL
2237 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2238 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2239 && fixp->fx_offset == fixp->fx_next->fx_offset);
2242 /* See whether instruction IP reads register REG. CLASS is the type
2246 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2247 enum mips_regclass regclass)
2249 if (regclass == MIPS16_REG)
2251 gas_assert (mips_opts.mips16);
2252 reg = mips16_to_32_reg_map[reg];
2253 regclass = MIPS_GR_REG;
2256 /* Don't report on general register ZERO, since it never changes. */
2257 if (regclass == MIPS_GR_REG && reg == ZERO)
2260 if (regclass == MIPS_FP_REG)
2262 gas_assert (! mips_opts.mips16);
2263 /* If we are called with either $f0 or $f1, we must check $f0.
2264 This is not optimal, because it will introduce an unnecessary
2265 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2266 need to distinguish reading both $f0 and $f1 or just one of
2267 them. Note that we don't have to check the other way,
2268 because there is no instruction that sets both $f0 and $f1
2269 and requires a delay. */
2270 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2271 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2272 == (reg &~ (unsigned) 1)))
2274 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2275 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2276 == (reg &~ (unsigned) 1)))
2279 else if (! mips_opts.mips16)
2281 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2282 && EXTRACT_OPERAND (RS, *ip) == reg)
2284 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2285 && EXTRACT_OPERAND (RT, *ip) == reg)
2290 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2291 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2293 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2294 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2296 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2297 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2300 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2302 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2304 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2306 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2307 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2314 /* This function returns true if modifying a register requires a
2318 reg_needs_delay (unsigned int reg)
2320 unsigned long prev_pinfo;
2322 prev_pinfo = history[0].insn_mo->pinfo;
2323 if (! mips_opts.noreorder
2324 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2325 && ! gpr_interlocks)
2326 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2327 && ! cop_interlocks)))
2329 /* A load from a coprocessor or from memory. All load delays
2330 delay the use of general register rt for one instruction. */
2331 /* Itbl support may require additional care here. */
2332 know (prev_pinfo & INSN_WRITE_GPR_T);
2333 if (reg == EXTRACT_OPERAND (RT, history[0]))
2340 /* Move all labels in insn_labels to the current insertion point. */
2343 mips_move_labels (void)
2345 segment_info_type *si = seg_info (now_seg);
2346 struct insn_label_list *l;
2349 for (l = si->label_list; l != NULL; l = l->next)
2351 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2352 symbol_set_frag (l->label, frag_now);
2353 val = (valueT) frag_now_fix ();
2354 /* mips16 text labels are stored as odd. */
2355 if (mips_opts.mips16)
2357 S_SET_VALUE (l->label, val);
2362 s_is_linkonce (symbolS *sym, segT from_seg)
2364 bfd_boolean linkonce = FALSE;
2365 segT symseg = S_GET_SEGMENT (sym);
2367 if (symseg != from_seg && !S_IS_LOCAL (sym))
2369 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2372 /* The GNU toolchain uses an extension for ELF: a section
2373 beginning with the magic string .gnu.linkonce is a
2374 linkonce section. */
2375 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2376 sizeof ".gnu.linkonce" - 1) == 0)
2383 /* Mark instruction labels in mips16 mode. This permits the linker to
2384 handle them specially, such as generating jalx instructions when
2385 needed. We also make them odd for the duration of the assembly, in
2386 order to generate the right sort of code. We will make them even
2387 in the adjust_symtab routine, while leaving them marked. This is
2388 convenient for the debugger and the disassembler. The linker knows
2389 to make them odd again. */
2392 mips16_mark_labels (void)
2394 segment_info_type *si = seg_info (now_seg);
2395 struct insn_label_list *l;
2397 if (!mips_opts.mips16)
2400 for (l = si->label_list; l != NULL; l = l->next)
2402 symbolS *label = l->label;
2404 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2406 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2408 if ((S_GET_VALUE (label) & 1) == 0
2409 /* Don't adjust the address if the label is global or weak, or
2410 in a link-once section, since we'll be emitting symbol reloc
2411 references to it which will be patched up by the linker, and
2412 the final value of the symbol may or may not be MIPS16. */
2413 && ! S_IS_WEAK (label)
2414 && ! S_IS_EXTERNAL (label)
2415 && ! s_is_linkonce (label, now_seg))
2416 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2420 /* End the current frag. Make it a variant frag and record the
2424 relax_close_frag (void)
2426 mips_macro_warning.first_frag = frag_now;
2427 frag_var (rs_machine_dependent, 0, 0,
2428 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2429 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2431 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2432 mips_relax.first_fixup = 0;
2435 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2436 See the comment above RELAX_ENCODE for more details. */
2439 relax_start (symbolS *symbol)
2441 gas_assert (mips_relax.sequence == 0);
2442 mips_relax.sequence = 1;
2443 mips_relax.symbol = symbol;
2446 /* Start generating the second version of a relaxable sequence.
2447 See the comment above RELAX_ENCODE for more details. */
2452 gas_assert (mips_relax.sequence == 1);
2453 mips_relax.sequence = 2;
2456 /* End the current relaxable sequence. */
2461 gas_assert (mips_relax.sequence == 2);
2462 relax_close_frag ();
2463 mips_relax.sequence = 0;
2466 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2467 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2468 by VR4120 errata. */
2471 classify_vr4120_insn (const char *name)
2473 if (strncmp (name, "macc", 4) == 0)
2474 return FIX_VR4120_MACC;
2475 if (strncmp (name, "dmacc", 5) == 0)
2476 return FIX_VR4120_DMACC;
2477 if (strncmp (name, "mult", 4) == 0)
2478 return FIX_VR4120_MULT;
2479 if (strncmp (name, "dmult", 5) == 0)
2480 return FIX_VR4120_DMULT;
2481 if (strstr (name, "div"))
2482 return FIX_VR4120_DIV;
2483 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2484 return FIX_VR4120_MTHILO;
2485 return NUM_FIX_VR4120_CLASSES;
2488 #define INSN_ERET 0x42000018
2489 #define INSN_DERET 0x4200001f
2491 /* Return the number of instructions that must separate INSN1 and INSN2,
2492 where INSN1 is the earlier instruction. Return the worst-case value
2493 for any INSN2 if INSN2 is null. */
2496 insns_between (const struct mips_cl_insn *insn1,
2497 const struct mips_cl_insn *insn2)
2499 unsigned long pinfo1, pinfo2;
2501 /* This function needs to know which pinfo flags are set for INSN2
2502 and which registers INSN2 uses. The former is stored in PINFO2 and
2503 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2504 will have every flag set and INSN2_USES_REG will always return true. */
2505 pinfo1 = insn1->insn_mo->pinfo;
2506 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2508 #define INSN2_USES_REG(REG, CLASS) \
2509 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2511 /* For most targets, write-after-read dependencies on the HI and LO
2512 registers must be separated by at least two instructions. */
2513 if (!hilo_interlocks)
2515 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2517 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2521 /* If we're working around r7000 errata, there must be two instructions
2522 between an mfhi or mflo and any instruction that uses the result. */
2523 if (mips_7000_hilo_fix
2524 && MF_HILO_INSN (pinfo1)
2525 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2528 /* If we're working around 24K errata, one instruction is required
2529 if an ERET or DERET is followed by a branch instruction. */
2532 if (insn1->insn_opcode == INSN_ERET
2533 || insn1->insn_opcode == INSN_DERET)
2536 || insn2->insn_opcode == INSN_ERET
2537 || insn2->insn_opcode == INSN_DERET
2538 || (insn2->insn_mo->pinfo
2539 & (INSN_UNCOND_BRANCH_DELAY
2540 | INSN_COND_BRANCH_DELAY
2541 | INSN_COND_BRANCH_LIKELY)) != 0)
2546 /* If working around VR4120 errata, check for combinations that need
2547 a single intervening instruction. */
2548 if (mips_fix_vr4120)
2550 unsigned int class1, class2;
2552 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2553 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2557 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2558 if (vr4120_conflicts[class1] & (1 << class2))
2563 if (!mips_opts.mips16)
2565 /* Check for GPR or coprocessor load delays. All such delays
2566 are on the RT register. */
2567 /* Itbl support may require additional care here. */
2568 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2569 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2571 know (pinfo1 & INSN_WRITE_GPR_T);
2572 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2576 /* Check for generic coprocessor hazards.
2578 This case is not handled very well. There is no special
2579 knowledge of CP0 handling, and the coprocessors other than
2580 the floating point unit are not distinguished at all. */
2581 /* Itbl support may require additional care here. FIXME!
2582 Need to modify this to include knowledge about
2583 user specified delays! */
2584 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2585 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2587 /* Handle cases where INSN1 writes to a known general coprocessor
2588 register. There must be a one instruction delay before INSN2
2589 if INSN2 reads that register, otherwise no delay is needed. */
2590 if (pinfo1 & INSN_WRITE_FPR_T)
2592 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2595 else if (pinfo1 & INSN_WRITE_FPR_S)
2597 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2602 /* Read-after-write dependencies on the control registers
2603 require a two-instruction gap. */
2604 if ((pinfo1 & INSN_WRITE_COND_CODE)
2605 && (pinfo2 & INSN_READ_COND_CODE))
2608 /* We don't know exactly what INSN1 does. If INSN2 is
2609 also a coprocessor instruction, assume there must be
2610 a one instruction gap. */
2611 if (pinfo2 & INSN_COP)
2616 /* Check for read-after-write dependencies on the coprocessor
2617 control registers in cases where INSN1 does not need a general
2618 coprocessor delay. This means that INSN1 is a floating point
2619 comparison instruction. */
2620 /* Itbl support may require additional care here. */
2621 else if (!cop_interlocks
2622 && (pinfo1 & INSN_WRITE_COND_CODE)
2623 && (pinfo2 & INSN_READ_COND_CODE))
2627 #undef INSN2_USES_REG
2632 /* Return the number of nops that would be needed to work around the
2633 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2634 the MAX_VR4130_NOPS instructions described by HIST. */
2637 nops_for_vr4130 (const struct mips_cl_insn *hist,
2638 const struct mips_cl_insn *insn)
2642 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2643 are not affected by the errata. */
2645 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2646 || strcmp (insn->insn_mo->name, "mtlo") == 0
2647 || strcmp (insn->insn_mo->name, "mthi") == 0))
2650 /* Search for the first MFLO or MFHI. */
2651 for (i = 0; i < MAX_VR4130_NOPS; i++)
2652 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2654 /* Extract the destination register. */
2655 if (mips_opts.mips16)
2656 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])];
2658 reg = EXTRACT_OPERAND (RD, hist[i]);
2660 /* No nops are needed if INSN reads that register. */
2661 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2664 /* ...or if any of the intervening instructions do. */
2665 for (j = 0; j < i; j++)
2666 if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG))
2669 return MAX_VR4130_NOPS - i;
2674 /* Return the number of nops that would be needed if instruction INSN
2675 immediately followed the MAX_NOPS instructions given by HIST,
2676 where HIST[0] is the most recent instruction. If INSN is null,
2677 return the worse-case number of nops for any instruction. */
2680 nops_for_insn (const struct mips_cl_insn *hist,
2681 const struct mips_cl_insn *insn)
2683 int i, nops, tmp_nops;
2686 for (i = 0; i < MAX_DELAY_NOPS; i++)
2688 tmp_nops = insns_between (hist + i, insn) - i;
2689 if (tmp_nops > nops)
2693 if (mips_fix_vr4130)
2695 tmp_nops = nops_for_vr4130 (hist, insn);
2696 if (tmp_nops > nops)
2703 /* The variable arguments provide NUM_INSNS extra instructions that
2704 might be added to HIST. Return the largest number of nops that
2705 would be needed after the extended sequence. */
2708 nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...)
2711 struct mips_cl_insn buffer[MAX_NOPS];
2712 struct mips_cl_insn *cursor;
2715 va_start (args, hist);
2716 cursor = buffer + num_insns;
2717 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2718 while (cursor > buffer)
2719 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2721 nops = nops_for_insn (buffer, NULL);
2726 /* Like nops_for_insn, but if INSN is a branch, take into account the
2727 worst-case delay for the branch target. */
2730 nops_for_insn_or_target (const struct mips_cl_insn *hist,
2731 const struct mips_cl_insn *insn)
2735 nops = nops_for_insn (hist, insn);
2736 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2737 | INSN_COND_BRANCH_DELAY
2738 | INSN_COND_BRANCH_LIKELY))
2740 tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN);
2741 if (tmp_nops > nops)
2744 else if (mips_opts.mips16
2745 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2746 | MIPS16_INSN_COND_BRANCH)))
2748 tmp_nops = nops_for_sequence (1, hist, insn);
2749 if (tmp_nops > nops)
2755 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2758 fix_loongson2f_nop (struct mips_cl_insn * ip)
2760 if (strcmp (ip->insn_mo->name, "nop") == 0)
2761 ip->insn_opcode = LOONGSON2F_NOP_INSN;
2764 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2765 jr target pc &= 'hffff_ffff_cfff_ffff. */
2768 fix_loongson2f_jump (struct mips_cl_insn * ip)
2770 if (strcmp (ip->insn_mo->name, "j") == 0
2771 || strcmp (ip->insn_mo->name, "jr") == 0
2772 || strcmp (ip->insn_mo->name, "jalr") == 0)
2780 sreg = EXTRACT_OPERAND (RS, *ip);
2781 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
2784 ep.X_op = O_constant;
2785 ep.X_add_number = 0xcfff0000;
2786 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
2787 ep.X_add_number = 0xffff;
2788 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
2789 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
2794 fix_loongson2f (struct mips_cl_insn * ip)
2796 if (mips_fix_loongson2f_nop)
2797 fix_loongson2f_nop (ip);
2799 if (mips_fix_loongson2f_jump)
2800 fix_loongson2f_jump (ip);
2803 /* Output an instruction. IP is the instruction information.
2804 ADDRESS_EXPR is an operand of the instruction to be used with
2808 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2809 bfd_reloc_code_real_type *reloc_type)
2811 unsigned long prev_pinfo, pinfo;
2812 relax_stateT prev_insn_frag_type = 0;
2813 bfd_boolean relaxed_branch = FALSE;
2814 segment_info_type *si = seg_info (now_seg);
2816 if (mips_fix_loongson2f)
2817 fix_loongson2f (ip);
2819 /* Mark instruction labels in mips16 mode. */
2820 mips16_mark_labels ();
2822 file_ase_mips16 |= mips_opts.mips16;
2824 prev_pinfo = history[0].insn_mo->pinfo;
2825 pinfo = ip->insn_mo->pinfo;
2827 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2829 /* There are a lot of optimizations we could do that we don't.
2830 In particular, we do not, in general, reorder instructions.
2831 If you use gcc with optimization, it will reorder
2832 instructions and generally do much more optimization then we
2833 do here; repeating all that work in the assembler would only
2834 benefit hand written assembly code, and does not seem worth
2836 int nops = (mips_optimize == 0
2837 ? nops_for_insn (history, NULL)
2838 : nops_for_insn_or_target (history, ip));
2842 unsigned long old_frag_offset;
2845 old_frag = frag_now;
2846 old_frag_offset = frag_now_fix ();
2848 for (i = 0; i < nops; i++)
2853 listing_prev_line ();
2854 /* We may be at the start of a variant frag. In case we
2855 are, make sure there is enough space for the frag
2856 after the frags created by listing_prev_line. The
2857 argument to frag_grow here must be at least as large
2858 as the argument to all other calls to frag_grow in
2859 this file. We don't have to worry about being in the
2860 middle of a variant frag, because the variants insert
2861 all needed nop instructions themselves. */
2865 mips_move_labels ();
2867 #ifndef NO_ECOFF_DEBUGGING
2868 if (ECOFF_DEBUGGING)
2869 ecoff_fix_loc (old_frag, old_frag_offset);
2873 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2875 /* Work out how many nops in prev_nop_frag are needed by IP. */
2876 int nops = nops_for_insn_or_target (history, ip);
2877 gas_assert (nops <= prev_nop_frag_holds);
2879 /* Enforce NOPS as a minimum. */
2880 if (nops > prev_nop_frag_required)
2881 prev_nop_frag_required = nops;
2883 if (prev_nop_frag_holds == prev_nop_frag_required)
2885 /* Settle for the current number of nops. Update the history
2886 accordingly (for the benefit of any future .set reorder code). */
2887 prev_nop_frag = NULL;
2888 insert_into_history (prev_nop_frag_since,
2889 prev_nop_frag_holds, NOP_INSN);
2893 /* Allow this instruction to replace one of the nops that was
2894 tentatively added to prev_nop_frag. */
2895 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2896 prev_nop_frag_holds--;
2897 prev_nop_frag_since++;
2902 /* The value passed to dwarf2_emit_insn is the distance between
2903 the beginning of the current instruction and the address that
2904 should be recorded in the debug tables. For MIPS16 debug info
2905 we want to use ISA-encoded addresses, so we pass -1 for an
2906 address higher by one than the current. */
2907 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2910 /* Record the frag type before frag_var. */
2911 if (history[0].frag)
2912 prev_insn_frag_type = history[0].frag->fr_type;
2915 && *reloc_type == BFD_RELOC_16_PCREL_S2
2916 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2917 || pinfo & INSN_COND_BRANCH_LIKELY)
2918 && mips_relax_branch
2919 /* Don't try branch relaxation within .set nomacro, or within
2920 .set noat if we use $at for PIC computations. If it turns
2921 out that the branch was out-of-range, we'll get an error. */
2922 && !mips_opts.warn_about_macros
2923 && (mips_opts.at || mips_pic == NO_PIC)
2924 && !mips_opts.mips16)
2926 relaxed_branch = TRUE;
2927 add_relaxed_insn (ip, (relaxed_branch_length
2929 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2930 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2933 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2934 pinfo & INSN_COND_BRANCH_LIKELY,
2935 pinfo & INSN_WRITE_GPR_31,
2937 address_expr->X_add_symbol,
2938 address_expr->X_add_number);
2939 *reloc_type = BFD_RELOC_UNUSED;
2941 else if (*reloc_type > BFD_RELOC_UNUSED)
2943 /* We need to set up a variant frag. */
2944 gas_assert (mips_opts.mips16 && address_expr != NULL);
2945 add_relaxed_insn (ip, 4, 0,
2947 (*reloc_type - BFD_RELOC_UNUSED,
2948 mips16_small, mips16_ext,
2949 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2950 history[0].mips16_absolute_jump_p),
2951 make_expr_symbol (address_expr), 0);
2953 else if (mips_opts.mips16
2955 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2957 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2958 /* Make sure there is enough room to swap this instruction with
2959 a following jump instruction. */
2961 add_fixed_insn (ip);
2965 if (mips_opts.mips16
2966 && mips_opts.noreorder
2967 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2968 as_warn (_("extended instruction in delay slot"));
2970 if (mips_relax.sequence)
2972 /* If we've reached the end of this frag, turn it into a variant
2973 frag and record the information for the instructions we've
2975 if (frag_room () < 4)
2976 relax_close_frag ();
2977 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2980 if (mips_relax.sequence != 2)
2981 mips_macro_warning.sizes[0] += 4;
2982 if (mips_relax.sequence != 1)
2983 mips_macro_warning.sizes[1] += 4;
2985 if (mips_opts.mips16)
2988 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2990 add_fixed_insn (ip);
2993 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2995 if (address_expr->X_op == O_constant)
2999 switch (*reloc_type)
3002 ip->insn_opcode |= address_expr->X_add_number;
3005 case BFD_RELOC_MIPS_HIGHEST:
3006 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3007 ip->insn_opcode |= tmp & 0xffff;
3010 case BFD_RELOC_MIPS_HIGHER:
3011 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3012 ip->insn_opcode |= tmp & 0xffff;
3015 case BFD_RELOC_HI16_S:
3016 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3017 ip->insn_opcode |= tmp & 0xffff;
3020 case BFD_RELOC_HI16:
3021 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3024 case BFD_RELOC_UNUSED:
3025 case BFD_RELOC_LO16:
3026 case BFD_RELOC_MIPS_GOT_DISP:
3027 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3030 case BFD_RELOC_MIPS_JMP:
3031 if ((address_expr->X_add_number & 3) != 0)
3032 as_bad (_("jump to misaligned address (0x%lx)"),
3033 (unsigned long) address_expr->X_add_number);
3034 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3037 case BFD_RELOC_MIPS16_JMP:
3038 if ((address_expr->X_add_number & 3) != 0)
3039 as_bad (_("jump to misaligned address (0x%lx)"),
3040 (unsigned long) address_expr->X_add_number);
3042 (((address_expr->X_add_number & 0x7c0000) << 3)
3043 | ((address_expr->X_add_number & 0xf800000) >> 7)
3044 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3047 case BFD_RELOC_16_PCREL_S2:
3048 if ((address_expr->X_add_number & 3) != 0)
3049 as_bad (_("branch to misaligned address (0x%lx)"),
3050 (unsigned long) address_expr->X_add_number);
3051 if (mips_relax_branch)
3053 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3054 as_bad (_("branch address range overflow (0x%lx)"),
3055 (unsigned long) address_expr->X_add_number);
3056 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3063 else if (*reloc_type < BFD_RELOC_UNUSED)
3066 reloc_howto_type *howto;
3069 /* In a compound relocation, it is the final (outermost)
3070 operator that determines the relocated field. */
3071 for (i = 1; i < 3; i++)
3072 if (reloc_type[i] == BFD_RELOC_UNUSED)
3075 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3078 /* To reproduce this failure try assembling gas/testsuites/
3079 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3081 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3082 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3085 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3086 bfd_get_reloc_size (howto),
3088 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3091 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3092 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3093 && ip->fixp[0]->fx_addsy)
3094 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3096 /* These relocations can have an addend that won't fit in
3097 4 octets for 64bit assembly. */
3099 && ! howto->partial_inplace
3100 && (reloc_type[0] == BFD_RELOC_16
3101 || reloc_type[0] == BFD_RELOC_32
3102 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3103 || reloc_type[0] == BFD_RELOC_GPREL16
3104 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3105 || reloc_type[0] == BFD_RELOC_GPREL32
3106 || reloc_type[0] == BFD_RELOC_64
3107 || reloc_type[0] == BFD_RELOC_CTOR
3108 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3109 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3110 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3111 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3112 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3113 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3114 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3115 || hi16_reloc_p (reloc_type[0])
3116 || lo16_reloc_p (reloc_type[0])))
3117 ip->fixp[0]->fx_no_overflow = 1;
3119 if (mips_relax.sequence)
3121 if (mips_relax.first_fixup == 0)
3122 mips_relax.first_fixup = ip->fixp[0];
3124 else if (reloc_needs_lo_p (*reloc_type))
3126 struct mips_hi_fixup *hi_fixup;
3128 /* Reuse the last entry if it already has a matching %lo. */
3129 hi_fixup = mips_hi_fixup_list;
3131 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3133 hi_fixup = ((struct mips_hi_fixup *)
3134 xmalloc (sizeof (struct mips_hi_fixup)));
3135 hi_fixup->next = mips_hi_fixup_list;
3136 mips_hi_fixup_list = hi_fixup;
3138 hi_fixup->fixp = ip->fixp[0];
3139 hi_fixup->seg = now_seg;
3142 /* Add fixups for the second and third relocations, if given.
3143 Note that the ABI allows the second relocation to be
3144 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3145 moment we only use RSS_UNDEF, but we could add support
3146 for the others if it ever becomes necessary. */
3147 for (i = 1; i < 3; i++)
3148 if (reloc_type[i] != BFD_RELOC_UNUSED)
3150 ip->fixp[i] = fix_new (ip->frag, ip->where,
3151 ip->fixp[0]->fx_size, NULL, 0,
3152 FALSE, reloc_type[i]);
3154 /* Use fx_tcbit to mark compound relocs. */
3155 ip->fixp[0]->fx_tcbit = 1;
3156 ip->fixp[i]->fx_tcbit = 1;
3162 /* Update the register mask information. */
3163 if (! mips_opts.mips16)
3165 if (pinfo & INSN_WRITE_GPR_D)
3166 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3167 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3168 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3169 if (pinfo & INSN_READ_GPR_S)
3170 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3171 if (pinfo & INSN_WRITE_GPR_31)
3172 mips_gprmask |= 1 << RA;
3173 if (pinfo & INSN_WRITE_FPR_D)
3174 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3175 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3176 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3177 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3178 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3179 if ((pinfo & INSN_READ_FPR_R) != 0)
3180 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3181 if (pinfo & INSN_COP)
3183 /* We don't keep enough information to sort these cases out.
3184 The itbl support does keep this information however, although
3185 we currently don't support itbl fprmats as part of the cop
3186 instruction. May want to add this support in the future. */
3188 /* Never set the bit for $0, which is always zero. */
3189 mips_gprmask &= ~1 << 0;
3193 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3194 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3195 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3196 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3197 if (pinfo & MIPS16_INSN_WRITE_Z)
3198 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3199 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3200 mips_gprmask |= 1 << TREG;
3201 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3202 mips_gprmask |= 1 << SP;
3203 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3204 mips_gprmask |= 1 << RA;
3205 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3206 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3207 if (pinfo & MIPS16_INSN_READ_Z)
3208 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3209 if (pinfo & MIPS16_INSN_READ_GPR_X)
3210 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3213 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3215 /* Filling the branch delay slot is more complex. We try to
3216 switch the branch with the previous instruction, which we can
3217 do if the previous instruction does not set up a condition
3218 that the branch tests and if the branch is not itself the
3219 target of any branch. */
3220 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3221 || (pinfo & INSN_COND_BRANCH_DELAY))
3223 if (mips_optimize < 2
3224 /* If we have seen .set volatile or .set nomove, don't
3226 || mips_opts.nomove != 0
3227 /* We can't swap if the previous instruction's position
3229 || history[0].fixed_p
3230 /* If the previous previous insn was in a .set
3231 noreorder, we can't swap. Actually, the MIPS
3232 assembler will swap in this situation. However, gcc
3233 configured -with-gnu-as will generate code like
3239 in which we can not swap the bne and INSN. If gcc is
3240 not configured -with-gnu-as, it does not output the
3242 || history[1].noreorder_p
3243 /* If the branch is itself the target of a branch, we
3244 can not swap. We cheat on this; all we check for is
3245 whether there is a label on this instruction. If
3246 there are any branches to anything other than a
3247 label, users must use .set noreorder. */
3248 || si->label_list != NULL
3249 /* If the previous instruction is in a variant frag
3250 other than this branch's one, we cannot do the swap.
3251 This does not apply to the mips16, which uses variant
3252 frags for different purposes. */
3253 || (! mips_opts.mips16
3254 && prev_insn_frag_type == rs_machine_dependent)
3255 /* Check for conflicts between the branch and the instructions
3256 before the candidate delay slot. */
3257 || nops_for_insn (history + 1, ip) > 0
3258 /* Check for conflicts between the swapped sequence and the
3259 target of the branch. */
3260 || nops_for_sequence (2, history + 1, ip, history) > 0
3261 /* We do not swap with a trap instruction, since it
3262 complicates trap handlers to have the trap
3263 instruction be in a delay slot. */
3264 || (prev_pinfo & INSN_TRAP)
3265 /* If the branch reads a register that the previous
3266 instruction sets, we can not swap. */
3267 || (! mips_opts.mips16
3268 && (prev_pinfo & INSN_WRITE_GPR_T)
3269 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3271 || (! mips_opts.mips16
3272 && (prev_pinfo & INSN_WRITE_GPR_D)
3273 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3275 || (mips_opts.mips16
3276 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3278 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3280 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3282 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3284 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3286 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3288 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3289 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3290 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3291 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3292 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3293 && insn_uses_reg (ip,
3294 MIPS16OP_EXTRACT_REG32R
3295 (history[0].insn_opcode),
3297 /* If the branch writes a register that the previous
3298 instruction sets, we can not swap (we know that
3299 branches write only to RD or to $31). */
3300 || (! mips_opts.mips16
3301 && (prev_pinfo & INSN_WRITE_GPR_T)
3302 && (((pinfo & INSN_WRITE_GPR_D)
3303 && (EXTRACT_OPERAND (RT, history[0])
3304 == EXTRACT_OPERAND (RD, *ip)))
3305 || ((pinfo & INSN_WRITE_GPR_31)
3306 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3307 || (! mips_opts.mips16
3308 && (prev_pinfo & INSN_WRITE_GPR_D)
3309 && (((pinfo & INSN_WRITE_GPR_D)
3310 && (EXTRACT_OPERAND (RD, history[0])
3311 == EXTRACT_OPERAND (RD, *ip)))
3312 || ((pinfo & INSN_WRITE_GPR_31)
3313 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3314 || (mips_opts.mips16
3315 && (pinfo & MIPS16_INSN_WRITE_31)
3316 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3317 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3318 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3320 /* If the branch writes a register that the previous
3321 instruction reads, we can not swap (we know that
3322 branches only write to RD or to $31). */
3323 || (! mips_opts.mips16
3324 && (pinfo & INSN_WRITE_GPR_D)
3325 && insn_uses_reg (&history[0],
3326 EXTRACT_OPERAND (RD, *ip),
3328 || (! mips_opts.mips16
3329 && (pinfo & INSN_WRITE_GPR_31)
3330 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3331 || (mips_opts.mips16
3332 && (pinfo & MIPS16_INSN_WRITE_31)
3333 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3334 /* If one instruction sets a condition code and the
3335 other one uses a condition code, we can not swap. */
3336 || ((pinfo & INSN_READ_COND_CODE)
3337 && (prev_pinfo & INSN_WRITE_COND_CODE))
3338 || ((pinfo & INSN_WRITE_COND_CODE)
3339 && (prev_pinfo & INSN_READ_COND_CODE))
3340 /* If the previous instruction uses the PC, we can not
3342 || (mips_opts.mips16
3343 && (prev_pinfo & MIPS16_INSN_READ_PC))
3344 /* If the previous instruction had a fixup in mips16
3345 mode, we can not swap. This normally means that the
3346 previous instruction was a 4 byte branch anyhow. */
3347 || (mips_opts.mips16 && history[0].fixp[0])
3348 /* If the previous instruction is a sync, sync.l, or
3349 sync.p, we can not swap. */
3350 || (prev_pinfo & INSN_SYNC)
3351 /* If the previous instruction is an ERET or
3352 DERET, avoid the swap. */
3353 || (history[0].insn_opcode == INSN_ERET)
3354 || (history[0].insn_opcode == INSN_DERET))
3356 if (mips_opts.mips16
3357 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3358 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3359 && ISA_SUPPORTS_MIPS16E)
3361 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3362 ip->insn_opcode |= 0x0080;
3364 insert_into_history (0, 1, ip);
3368 /* We could do even better for unconditional branches to
3369 portions of this object file; we could pick up the
3370 instruction at the destination, put it in the delay
3371 slot, and bump the destination address. */
3372 insert_into_history (0, 1, ip);
3376 if (mips_relax.sequence)
3377 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3381 /* It looks like we can actually do the swap. */
3382 struct mips_cl_insn delay = history[0];
3383 if (mips_opts.mips16)
3385 know (delay.frag == ip->frag);
3386 move_insn (ip, delay.frag, delay.where);
3387 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3389 else if (relaxed_branch)
3391 /* Add the delay slot instruction to the end of the
3392 current frag and shrink the fixed part of the
3393 original frag. If the branch occupies the tail of
3394 the latter, move it backwards to cover the gap. */
3395 delay.frag->fr_fix -= 4;
3396 if (delay.frag == ip->frag)
3397 move_insn (ip, ip->frag, ip->where - 4);
3398 add_fixed_insn (&delay);
3402 move_insn (&delay, ip->frag, ip->where);
3403 move_insn (ip, history[0].frag, history[0].where);
3407 insert_into_history (0, 1, &delay);
3410 /* If that was an unconditional branch, forget the previous
3411 insn information. */
3412 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3414 mips_no_prev_insn ();
3417 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3419 /* We don't yet optimize a branch likely. What we should do
3420 is look at the target, copy the instruction found there
3421 into the delay slot, and increment the branch to jump to
3422 the next instruction. */
3423 insert_into_history (0, 1, ip);
3427 insert_into_history (0, 1, ip);
3430 insert_into_history (0, 1, ip);
3432 /* We just output an insn, so the next one doesn't have a label. */
3433 mips_clear_insn_labels ();
3436 /* Forget that there was any previous instruction or label. */
3439 mips_no_prev_insn (void)
3441 prev_nop_frag = NULL;
3442 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3443 mips_clear_insn_labels ();
3446 /* This function must be called before we emit something other than
3447 instructions. It is like mips_no_prev_insn except that it inserts
3448 any NOPS that might be needed by previous instructions. */
3451 mips_emit_delays (void)
3453 if (! mips_opts.noreorder)
3455 int nops = nops_for_insn (history, NULL);
3459 add_fixed_insn (NOP_INSN);
3460 mips_move_labels ();
3463 mips_no_prev_insn ();
3466 /* Start a (possibly nested) noreorder block. */
3469 start_noreorder (void)
3471 if (mips_opts.noreorder == 0)
3476 /* None of the instructions before the .set noreorder can be moved. */
3477 for (i = 0; i < ARRAY_SIZE (history); i++)
3478 history[i].fixed_p = 1;
3480 /* Insert any nops that might be needed between the .set noreorder
3481 block and the previous instructions. We will later remove any
3482 nops that turn out not to be needed. */
3483 nops = nops_for_insn (history, NULL);
3486 if (mips_optimize != 0)
3488 /* Record the frag which holds the nop instructions, so
3489 that we can remove them if we don't need them. */
3490 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3491 prev_nop_frag = frag_now;
3492 prev_nop_frag_holds = nops;
3493 prev_nop_frag_required = 0;
3494 prev_nop_frag_since = 0;
3497 for (; nops > 0; --nops)
3498 add_fixed_insn (NOP_INSN);
3500 /* Move on to a new frag, so that it is safe to simply
3501 decrease the size of prev_nop_frag. */
3502 frag_wane (frag_now);
3504 mips_move_labels ();
3506 mips16_mark_labels ();
3507 mips_clear_insn_labels ();
3509 mips_opts.noreorder++;
3510 mips_any_noreorder = 1;
3513 /* End a nested noreorder block. */
3516 end_noreorder (void)
3519 mips_opts.noreorder--;
3520 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3522 /* Commit to inserting prev_nop_frag_required nops and go back to
3523 handling nop insertion the .set reorder way. */
3524 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3525 * (mips_opts.mips16 ? 2 : 4));
3526 insert_into_history (prev_nop_frag_since,
3527 prev_nop_frag_required, NOP_INSN);
3528 prev_nop_frag = NULL;
3532 /* Set up global variables for the start of a new macro. */
3537 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3538 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3539 && (history[0].insn_mo->pinfo
3540 & (INSN_UNCOND_BRANCH_DELAY
3541 | INSN_COND_BRANCH_DELAY
3542 | INSN_COND_BRANCH_LIKELY)) != 0);
3545 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3546 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3547 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3550 macro_warning (relax_substateT subtype)
3552 if (subtype & RELAX_DELAY_SLOT)
3553 return _("Macro instruction expanded into multiple instructions"
3554 " in a branch delay slot");
3555 else if (subtype & RELAX_NOMACRO)
3556 return _("Macro instruction expanded into multiple instructions");
3561 /* Finish up a macro. Emit warnings as appropriate. */
3566 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3568 relax_substateT subtype;
3570 /* Set up the relaxation warning flags. */
3572 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3573 subtype |= RELAX_SECOND_LONGER;
3574 if (mips_opts.warn_about_macros)
3575 subtype |= RELAX_NOMACRO;
3576 if (mips_macro_warning.delay_slot_p)
3577 subtype |= RELAX_DELAY_SLOT;
3579 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3581 /* Either the macro has a single implementation or both
3582 implementations are longer than 4 bytes. Emit the
3584 const char *msg = macro_warning (subtype);
3586 as_warn ("%s", msg);
3590 /* One implementation might need a warning but the other
3591 definitely doesn't. */
3592 mips_macro_warning.first_frag->fr_subtype |= subtype;
3597 /* Read a macro's relocation codes from *ARGS and store them in *R.
3598 The first argument in *ARGS will be either the code for a single
3599 relocation or -1 followed by the three codes that make up a
3600 composite relocation. */
3603 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3607 next = va_arg (*args, int);
3609 r[0] = (bfd_reloc_code_real_type) next;
3611 for (i = 0; i < 3; i++)
3612 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3615 /* Build an instruction created by a macro expansion. This is passed
3616 a pointer to the count of instructions created so far, an
3617 expression, the name of the instruction to build, an operand format
3618 string, and corresponding arguments. */
3621 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3623 const struct mips_opcode *mo;
3624 struct mips_cl_insn insn;
3625 bfd_reloc_code_real_type r[3];
3628 va_start (args, fmt);
3630 if (mips_opts.mips16)
3632 mips16_macro_build (ep, name, fmt, &args);
3637 r[0] = BFD_RELOC_UNUSED;
3638 r[1] = BFD_RELOC_UNUSED;
3639 r[2] = BFD_RELOC_UNUSED;
3640 mo = (struct mips_opcode *) hash_find (op_hash, name);
3642 gas_assert (strcmp (name, mo->name) == 0);
3646 /* Search until we get a match for NAME. It is assumed here that
3647 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3648 if (strcmp (fmt, mo->args) == 0
3649 && mo->pinfo != INSN_MACRO
3650 && is_opcode_valid (mo))
3654 gas_assert (mo->name);
3655 gas_assert (strcmp (name, mo->name) == 0);
3658 create_insn (&insn, mo);
3676 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3681 /* Note that in the macro case, these arguments are already
3682 in MSB form. (When handling the instruction in the
3683 non-macro case, these arguments are sizes from which
3684 MSB values must be calculated.) */
3685 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3691 /* Note that in the macro case, these arguments are already
3692 in MSBD form. (When handling the instruction in the
3693 non-macro case, these arguments are sizes from which
3694 MSBD values must be calculated.) */
3695 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3699 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3708 INSERT_OPERAND (BP, insn, va_arg (args, int));
3714 INSERT_OPERAND (RT, insn, va_arg (args, int));
3718 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3723 INSERT_OPERAND (FT, insn, va_arg (args, int));
3729 INSERT_OPERAND (RD, insn, va_arg (args, int));
3734 int tmp = va_arg (args, int);
3736 INSERT_OPERAND (RT, insn, tmp);
3737 INSERT_OPERAND (RD, insn, tmp);
3743 INSERT_OPERAND (FS, insn, va_arg (args, int));
3750 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3754 INSERT_OPERAND (FD, insn, va_arg (args, int));
3758 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3762 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3766 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3773 INSERT_OPERAND (RS, insn, va_arg (args, int));
3778 macro_read_relocs (&args, r);
3779 gas_assert (*r == BFD_RELOC_GPREL16
3780 || *r == BFD_RELOC_MIPS_HIGHER
3781 || *r == BFD_RELOC_HI16_S
3782 || *r == BFD_RELOC_LO16
3783 || *r == BFD_RELOC_MIPS_GOT_OFST);
3787 macro_read_relocs (&args, r);
3791 macro_read_relocs (&args, r);
3792 gas_assert (ep != NULL
3793 && (ep->X_op == O_constant
3794 || (ep->X_op == O_symbol
3795 && (*r == BFD_RELOC_MIPS_HIGHEST
3796 || *r == BFD_RELOC_HI16_S
3797 || *r == BFD_RELOC_HI16
3798 || *r == BFD_RELOC_GPREL16
3799 || *r == BFD_RELOC_MIPS_GOT_HI16
3800 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3804 gas_assert (ep != NULL);
3807 * This allows macro() to pass an immediate expression for
3808 * creating short branches without creating a symbol.
3810 * We don't allow branch relaxation for these branches, as
3811 * they should only appear in ".set nomacro" anyway.
3813 if (ep->X_op == O_constant)
3815 if ((ep->X_add_number & 3) != 0)
3816 as_bad (_("branch to misaligned address (0x%lx)"),
3817 (unsigned long) ep->X_add_number);
3818 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3819 as_bad (_("branch address range overflow (0x%lx)"),
3820 (unsigned long) ep->X_add_number);
3821 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3825 *r = BFD_RELOC_16_PCREL_S2;
3829 gas_assert (ep != NULL);
3830 *r = BFD_RELOC_MIPS_JMP;
3834 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3838 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3847 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3849 append_insn (&insn, ep, r);
3853 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3856 struct mips_opcode *mo;
3857 struct mips_cl_insn insn;
3858 bfd_reloc_code_real_type r[3]
3859 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3861 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3863 gas_assert (strcmp (name, mo->name) == 0);
3865 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3868 gas_assert (mo->name);
3869 gas_assert (strcmp (name, mo->name) == 0);
3872 create_insn (&insn, mo);
3890 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
3895 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
3899 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
3903 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
3913 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
3920 regno = va_arg (*args, int);
3921 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3922 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3943 gas_assert (ep != NULL);
3945 if (ep->X_op != O_constant)
3946 *r = (int) BFD_RELOC_UNUSED + c;
3949 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3950 FALSE, &insn.insn_opcode, &insn.use_extend,
3953 *r = BFD_RELOC_UNUSED;
3959 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
3966 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3968 append_insn (&insn, ep, r);
3972 * Sign-extend 32-bit mode constants that have bit 31 set and all
3973 * higher bits unset.
3976 normalize_constant_expr (expressionS *ex)
3978 if (ex->X_op == O_constant
3979 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3980 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3985 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3986 * all higher bits unset.
3989 normalize_address_expr (expressionS *ex)
3991 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3992 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3993 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3994 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3999 * Generate a "jalr" instruction with a relocation hint to the called
4000 * function. This occurs in NewABI PIC code.
4003 macro_build_jalr (expressionS *ep)
4007 if (MIPS_JALR_HINT_P (ep))
4012 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4013 if (MIPS_JALR_HINT_P (ep))
4014 fix_new_exp (frag_now, f - frag_now->fr_literal,
4015 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4019 * Generate a "lui" instruction.
4022 macro_build_lui (expressionS *ep, int regnum)
4024 expressionS high_expr;
4025 const struct mips_opcode *mo;
4026 struct mips_cl_insn insn;
4027 bfd_reloc_code_real_type r[3]
4028 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4029 const char *name = "lui";
4030 const char *fmt = "t,u";
4032 gas_assert (! mips_opts.mips16);
4036 if (high_expr.X_op == O_constant)
4038 /* We can compute the instruction now without a relocation entry. */
4039 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4041 *r = BFD_RELOC_UNUSED;
4045 gas_assert (ep->X_op == O_symbol);
4046 /* _gp_disp is a special case, used from s_cpload.
4047 __gnu_local_gp is used if mips_no_shared. */
4048 gas_assert (mips_pic == NO_PIC
4050 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4051 || (! mips_in_shared
4052 && strcmp (S_GET_NAME (ep->X_add_symbol),
4053 "__gnu_local_gp") == 0));
4054 *r = BFD_RELOC_HI16_S;
4057 mo = hash_find (op_hash, name);
4058 gas_assert (strcmp (name, mo->name) == 0);
4059 gas_assert (strcmp (fmt, mo->args) == 0);
4060 create_insn (&insn, mo);
4062 insn.insn_opcode = insn.insn_mo->match;
4063 INSERT_OPERAND (RT, insn, regnum);
4064 if (*r == BFD_RELOC_UNUSED)
4066 insn.insn_opcode |= high_expr.X_add_number;
4067 append_insn (&insn, NULL, r);
4070 append_insn (&insn, &high_expr, r);
4073 /* Generate a sequence of instructions to do a load or store from a constant
4074 offset off of a base register (breg) into/from a target register (treg),
4075 using AT if necessary. */
4077 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4078 int treg, int breg, int dbl)
4080 gas_assert (ep->X_op == O_constant);
4082 /* Sign-extending 32-bit constants makes their handling easier. */
4084 normalize_constant_expr (ep);
4086 /* Right now, this routine can only handle signed 32-bit constants. */
4087 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4088 as_warn (_("operand overflow"));
4090 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4092 /* Signed 16-bit offset will fit in the op. Easy! */
4093 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4097 /* 32-bit offset, need multiple instructions and AT, like:
4098 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4099 addu $tempreg,$tempreg,$breg
4100 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4101 to handle the complete offset. */
4102 macro_build_lui (ep, AT);
4103 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4104 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4107 as_bad (_("Macro used $at after \".set noat\""));
4112 * Generates code to set the $at register to true (one)
4113 * if reg is less than the immediate expression.
4116 set_at (int reg, int unsignedp)
4118 if (imm_expr.X_op == O_constant
4119 && imm_expr.X_add_number >= -0x8000
4120 && imm_expr.X_add_number < 0x8000)
4121 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4122 AT, reg, BFD_RELOC_LO16);
4125 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4126 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4130 /* Warn if an expression is not a constant. */
4133 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4135 if (ex->X_op == O_big)
4136 as_bad (_("unsupported large constant"));
4137 else if (ex->X_op != O_constant)
4138 as_bad (_("Instruction %s requires absolute expression"),
4141 if (HAVE_32BIT_GPRS)
4142 normalize_constant_expr (ex);
4145 /* Count the leading zeroes by performing a binary chop. This is a
4146 bulky bit of source, but performance is a LOT better for the
4147 majority of values than a simple loop to count the bits:
4148 for (lcnt = 0; (lcnt < 32); lcnt++)
4149 if ((v) & (1 << (31 - lcnt)))
4151 However it is not code size friendly, and the gain will drop a bit
4152 on certain cached systems.
4154 #define COUNT_TOP_ZEROES(v) \
4155 (((v) & ~0xffff) == 0 \
4156 ? ((v) & ~0xff) == 0 \
4157 ? ((v) & ~0xf) == 0 \
4158 ? ((v) & ~0x3) == 0 \
4159 ? ((v) & ~0x1) == 0 \
4164 : ((v) & ~0x7) == 0 \
4167 : ((v) & ~0x3f) == 0 \
4168 ? ((v) & ~0x1f) == 0 \
4171 : ((v) & ~0x7f) == 0 \
4174 : ((v) & ~0xfff) == 0 \
4175 ? ((v) & ~0x3ff) == 0 \
4176 ? ((v) & ~0x1ff) == 0 \
4179 : ((v) & ~0x7ff) == 0 \
4182 : ((v) & ~0x3fff) == 0 \
4183 ? ((v) & ~0x1fff) == 0 \
4186 : ((v) & ~0x7fff) == 0 \
4189 : ((v) & ~0xffffff) == 0 \
4190 ? ((v) & ~0xfffff) == 0 \
4191 ? ((v) & ~0x3ffff) == 0 \
4192 ? ((v) & ~0x1ffff) == 0 \
4195 : ((v) & ~0x7ffff) == 0 \
4198 : ((v) & ~0x3fffff) == 0 \
4199 ? ((v) & ~0x1fffff) == 0 \
4202 : ((v) & ~0x7fffff) == 0 \
4205 : ((v) & ~0xfffffff) == 0 \
4206 ? ((v) & ~0x3ffffff) == 0 \
4207 ? ((v) & ~0x1ffffff) == 0 \
4210 : ((v) & ~0x7ffffff) == 0 \
4213 : ((v) & ~0x3fffffff) == 0 \
4214 ? ((v) & ~0x1fffffff) == 0 \
4217 : ((v) & ~0x7fffffff) == 0 \
4222 * This routine generates the least number of instructions necessary to load
4223 * an absolute expression value into a register.
4226 load_register (int reg, expressionS *ep, int dbl)
4229 expressionS hi32, lo32;
4231 if (ep->X_op != O_big)
4233 gas_assert (ep->X_op == O_constant);
4235 /* Sign-extending 32-bit constants makes their handling easier. */
4237 normalize_constant_expr (ep);
4239 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4241 /* We can handle 16 bit signed values with an addiu to
4242 $zero. No need to ever use daddiu here, since $zero and
4243 the result are always correct in 32 bit mode. */
4244 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4247 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4249 /* We can handle 16 bit unsigned values with an ori to
4251 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4254 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4256 /* 32 bit values require an lui. */
4257 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4258 if ((ep->X_add_number & 0xffff) != 0)
4259 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4264 /* The value is larger than 32 bits. */
4266 if (!dbl || HAVE_32BIT_GPRS)
4270 sprintf_vma (value, ep->X_add_number);
4271 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4272 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4276 if (ep->X_op != O_big)
4279 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4280 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4281 hi32.X_add_number &= 0xffffffff;
4283 lo32.X_add_number &= 0xffffffff;
4287 gas_assert (ep->X_add_number > 2);
4288 if (ep->X_add_number == 3)
4289 generic_bignum[3] = 0;
4290 else if (ep->X_add_number > 4)
4291 as_bad (_("Number larger than 64 bits"));
4292 lo32.X_op = O_constant;
4293 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4294 hi32.X_op = O_constant;
4295 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4298 if (hi32.X_add_number == 0)
4303 unsigned long hi, lo;
4305 if (hi32.X_add_number == (offsetT) 0xffffffff)
4307 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4309 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4312 if (lo32.X_add_number & 0x80000000)
4314 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4315 if (lo32.X_add_number & 0xffff)
4316 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4321 /* Check for 16bit shifted constant. We know that hi32 is
4322 non-zero, so start the mask on the first bit of the hi32
4327 unsigned long himask, lomask;
4331 himask = 0xffff >> (32 - shift);
4332 lomask = (0xffff << shift) & 0xffffffff;
4336 himask = 0xffff << (shift - 32);
4339 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4340 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4344 tmp.X_op = O_constant;
4346 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4347 | (lo32.X_add_number >> shift));
4349 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4350 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4351 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4352 reg, reg, (shift >= 32) ? shift - 32 : shift);
4357 while (shift <= (64 - 16));
4359 /* Find the bit number of the lowest one bit, and store the
4360 shifted value in hi/lo. */
4361 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4362 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4366 while ((lo & 1) == 0)
4371 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4377 while ((hi & 1) == 0)
4386 /* Optimize if the shifted value is a (power of 2) - 1. */
4387 if ((hi == 0 && ((lo + 1) & lo) == 0)
4388 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4390 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4395 /* This instruction will set the register to be all
4397 tmp.X_op = O_constant;
4398 tmp.X_add_number = (offsetT) -1;
4399 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4403 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4404 reg, reg, (bit >= 32) ? bit - 32 : bit);
4406 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4407 reg, reg, (shift >= 32) ? shift - 32 : shift);
4412 /* Sign extend hi32 before calling load_register, because we can
4413 generally get better code when we load a sign extended value. */
4414 if ((hi32.X_add_number & 0x80000000) != 0)
4415 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4416 load_register (reg, &hi32, 0);
4419 if ((lo32.X_add_number & 0xffff0000) == 0)
4423 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4431 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4433 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4434 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4440 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4444 mid16.X_add_number >>= 16;
4445 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4446 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4449 if ((lo32.X_add_number & 0xffff) != 0)
4450 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4454 load_delay_nop (void)
4456 if (!gpr_interlocks)
4457 macro_build (NULL, "nop", "");
4460 /* Load an address into a register. */
4463 load_address (int reg, expressionS *ep, int *used_at)
4465 if (ep->X_op != O_constant
4466 && ep->X_op != O_symbol)
4468 as_bad (_("expression too complex"));
4469 ep->X_op = O_constant;
4472 if (ep->X_op == O_constant)
4474 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4478 if (mips_pic == NO_PIC)
4480 /* If this is a reference to a GP relative symbol, we want
4481 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4483 lui $reg,<sym> (BFD_RELOC_HI16_S)
4484 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4485 If we have an addend, we always use the latter form.
4487 With 64bit address space and a usable $at we want
4488 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4489 lui $at,<sym> (BFD_RELOC_HI16_S)
4490 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4491 daddiu $at,<sym> (BFD_RELOC_LO16)
4495 If $at is already in use, we use a path which is suboptimal
4496 on superscalar processors.
4497 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4498 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4500 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4502 daddiu $reg,<sym> (BFD_RELOC_LO16)
4504 For GP relative symbols in 64bit address space we can use
4505 the same sequence as in 32bit address space. */
4506 if (HAVE_64BIT_SYMBOLS)
4508 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4509 && !nopic_need_relax (ep->X_add_symbol, 1))
4511 relax_start (ep->X_add_symbol);
4512 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4513 mips_gp_register, BFD_RELOC_GPREL16);
4517 if (*used_at == 0 && mips_opts.at)
4519 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4520 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4521 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4522 BFD_RELOC_MIPS_HIGHER);
4523 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4524 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4525 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4530 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4531 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4532 BFD_RELOC_MIPS_HIGHER);
4533 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4534 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4535 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4536 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4539 if (mips_relax.sequence)
4544 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4545 && !nopic_need_relax (ep->X_add_symbol, 1))
4547 relax_start (ep->X_add_symbol);
4548 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4549 mips_gp_register, BFD_RELOC_GPREL16);
4552 macro_build_lui (ep, reg);
4553 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4554 reg, reg, BFD_RELOC_LO16);
4555 if (mips_relax.sequence)
4559 else if (!mips_big_got)
4563 /* If this is a reference to an external symbol, we want
4564 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4566 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4568 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4569 If there is a constant, it must be added in after.
4571 If we have NewABI, we want
4572 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4573 unless we're referencing a global symbol with a non-zero
4574 offset, in which case cst must be added separately. */
4577 if (ep->X_add_number)
4579 ex.X_add_number = ep->X_add_number;
4580 ep->X_add_number = 0;
4581 relax_start (ep->X_add_symbol);
4582 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4583 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4584 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4585 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4586 ex.X_op = O_constant;
4587 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4588 reg, reg, BFD_RELOC_LO16);
4589 ep->X_add_number = ex.X_add_number;
4592 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4593 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4594 if (mips_relax.sequence)
4599 ex.X_add_number = ep->X_add_number;
4600 ep->X_add_number = 0;
4601 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4602 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4604 relax_start (ep->X_add_symbol);
4606 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4610 if (ex.X_add_number != 0)
4612 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4613 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4614 ex.X_op = O_constant;
4615 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4616 reg, reg, BFD_RELOC_LO16);
4620 else if (mips_big_got)
4624 /* This is the large GOT case. If this is a reference to an
4625 external symbol, we want
4626 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4628 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4630 Otherwise, for a reference to a local symbol in old ABI, we want
4631 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4633 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4634 If there is a constant, it must be added in after.
4636 In the NewABI, for local symbols, with or without offsets, we want:
4637 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4638 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4642 ex.X_add_number = ep->X_add_number;
4643 ep->X_add_number = 0;
4644 relax_start (ep->X_add_symbol);
4645 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4646 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4647 reg, reg, mips_gp_register);
4648 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4649 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4650 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4651 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4652 else if (ex.X_add_number)
4654 ex.X_op = O_constant;
4655 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4659 ep->X_add_number = ex.X_add_number;
4661 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4662 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4663 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4664 BFD_RELOC_MIPS_GOT_OFST);
4669 ex.X_add_number = ep->X_add_number;
4670 ep->X_add_number = 0;
4671 relax_start (ep->X_add_symbol);
4672 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4673 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4674 reg, reg, mips_gp_register);
4675 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4676 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4678 if (reg_needs_delay (mips_gp_register))
4680 /* We need a nop before loading from $gp. This special
4681 check is required because the lui which starts the main
4682 instruction stream does not refer to $gp, and so will not
4683 insert the nop which may be required. */
4684 macro_build (NULL, "nop", "");
4686 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4687 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4689 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4693 if (ex.X_add_number != 0)
4695 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4696 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4697 ex.X_op = O_constant;
4698 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4706 if (!mips_opts.at && *used_at == 1)
4707 as_bad (_("Macro used $at after \".set noat\""));
4710 /* Move the contents of register SOURCE into register DEST. */
4713 move_register (int dest, int source)
4715 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4719 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4720 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4721 The two alternatives are:
4723 Global symbol Local sybmol
4724 ------------- ------------
4725 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4727 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4729 load_got_offset emits the first instruction and add_got_offset
4730 emits the second for a 16-bit offset or add_got_offset_hilo emits
4731 a sequence to add a 32-bit offset using a scratch register. */
4734 load_got_offset (int dest, expressionS *local)
4739 global.X_add_number = 0;
4741 relax_start (local->X_add_symbol);
4742 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4743 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4745 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4746 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4751 add_got_offset (int dest, expressionS *local)
4755 global.X_op = O_constant;
4756 global.X_op_symbol = NULL;
4757 global.X_add_symbol = NULL;
4758 global.X_add_number = local->X_add_number;
4760 relax_start (local->X_add_symbol);
4761 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4762 dest, dest, BFD_RELOC_LO16);
4764 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4769 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4772 int hold_mips_optimize;
4774 global.X_op = O_constant;
4775 global.X_op_symbol = NULL;
4776 global.X_add_symbol = NULL;
4777 global.X_add_number = local->X_add_number;
4779 relax_start (local->X_add_symbol);
4780 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4782 /* Set mips_optimize around the lui instruction to avoid
4783 inserting an unnecessary nop after the lw. */
4784 hold_mips_optimize = mips_optimize;
4786 macro_build_lui (&global, tmp);
4787 mips_optimize = hold_mips_optimize;
4788 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4791 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4796 * This routine implements the seemingly endless macro or synthesized
4797 * instructions and addressing modes in the mips assembly language. Many
4798 * of these macros are simple and are similar to each other. These could
4799 * probably be handled by some kind of table or grammar approach instead of
4800 * this verbose method. Others are not simple macros but are more like
4801 * optimizing code generation.
4802 * One interesting optimization is when several store macros appear
4803 * consecutively that would load AT with the upper half of the same address.
4804 * The ensuing load upper instructions are ommited. This implies some kind
4805 * of global optimization. We currently only optimize within a single macro.
4806 * For many of the load and store macros if the address is specified as a
4807 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4808 * first load register 'at' with zero and use it as the base register. The
4809 * mips assembler simply uses register $zero. Just one tiny optimization
4813 macro (struct mips_cl_insn *ip)
4815 unsigned int treg, sreg, dreg, breg;
4816 unsigned int tempreg;
4831 bfd_reloc_code_real_type r;
4832 int hold_mips_optimize;
4834 gas_assert (! mips_opts.mips16);
4836 treg = EXTRACT_OPERAND (RT, *ip);
4837 dreg = EXTRACT_OPERAND (RD, *ip);
4838 sreg = breg = EXTRACT_OPERAND (RS, *ip);
4839 mask = ip->insn_mo->mask;
4841 expr1.X_op = O_constant;
4842 expr1.X_op_symbol = NULL;
4843 expr1.X_add_symbol = NULL;
4844 expr1.X_add_number = 1;
4858 expr1.X_add_number = 8;
4859 macro_build (&expr1, "bgez", "s,p", sreg);
4861 macro_build (NULL, "nop", "");
4863 move_register (dreg, sreg);
4864 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4887 if (imm_expr.X_op == O_constant
4888 && imm_expr.X_add_number >= -0x8000
4889 && imm_expr.X_add_number < 0x8000)
4891 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4895 load_register (AT, &imm_expr, dbl);
4896 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4915 if (imm_expr.X_op == O_constant
4916 && imm_expr.X_add_number >= 0
4917 && imm_expr.X_add_number < 0x10000)
4919 if (mask != M_NOR_I)
4920 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4923 macro_build (&imm_expr, "ori", "t,r,i",
4924 treg, sreg, BFD_RELOC_LO16);
4925 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4931 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4932 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4936 switch (imm_expr.X_add_number)
4939 macro_build (NULL, "nop", "");
4942 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4945 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4946 (int) imm_expr.X_add_number);
4965 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4967 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
4971 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4972 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4980 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4985 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4989 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4990 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
4996 /* Check for > max integer. */
4997 maxnum = 0x7fffffff;
4998 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5005 if (imm_expr.X_op == O_constant
5006 && imm_expr.X_add_number >= maxnum
5007 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5010 /* Result is always false. */
5012 macro_build (NULL, "nop", "");
5014 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5017 if (imm_expr.X_op != O_constant)
5018 as_bad (_("Unsupported large constant"));
5019 ++imm_expr.X_add_number;
5023 if (mask == M_BGEL_I)
5025 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5027 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5030 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5032 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5035 maxnum = 0x7fffffff;
5036 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5043 maxnum = - maxnum - 1;
5044 if (imm_expr.X_op == O_constant
5045 && imm_expr.X_add_number <= maxnum
5046 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5049 /* result is always true */
5050 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5051 macro_build (&offset_expr, "b", "p");
5056 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5066 macro_build (&offset_expr, likely ? "beql" : "beq",
5067 "s,t,p", ZERO, treg);
5071 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5072 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5080 && imm_expr.X_op == O_constant
5081 && imm_expr.X_add_number == -1))
5083 if (imm_expr.X_op != O_constant)
5084 as_bad (_("Unsupported large constant"));
5085 ++imm_expr.X_add_number;
5089 if (mask == M_BGEUL_I)
5091 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5093 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5095 macro_build (&offset_expr, likely ? "bnel" : "bne",
5096 "s,t,p", sreg, ZERO);
5101 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5109 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5114 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5118 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5119 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5127 macro_build (&offset_expr, likely ? "bnel" : "bne",
5128 "s,t,p", sreg, ZERO);
5134 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5135 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5143 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5148 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5152 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5153 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5159 maxnum = 0x7fffffff;
5160 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5167 if (imm_expr.X_op == O_constant
5168 && imm_expr.X_add_number >= maxnum
5169 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5171 if (imm_expr.X_op != O_constant)
5172 as_bad (_("Unsupported large constant"));
5173 ++imm_expr.X_add_number;
5177 if (mask == M_BLTL_I)
5179 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5181 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5184 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5186 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5191 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5199 macro_build (&offset_expr, likely ? "beql" : "beq",
5200 "s,t,p", sreg, ZERO);
5206 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5207 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5215 && imm_expr.X_op == O_constant
5216 && imm_expr.X_add_number == -1))
5218 if (imm_expr.X_op != O_constant)
5219 as_bad (_("Unsupported large constant"));
5220 ++imm_expr.X_add_number;
5224 if (mask == M_BLTUL_I)
5226 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5228 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5230 macro_build (&offset_expr, likely ? "beql" : "beq",
5231 "s,t,p", sreg, ZERO);
5236 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5244 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5249 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5253 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5254 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5264 macro_build (&offset_expr, likely ? "bnel" : "bne",
5265 "s,t,p", ZERO, treg);
5269 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5270 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5275 /* Use unsigned arithmetic. */
5279 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5281 as_bad (_("Unsupported large constant"));
5286 pos = imm_expr.X_add_number;
5287 size = imm2_expr.X_add_number;
5292 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5295 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5297 as_bad (_("Improper extract size (%lu, position %lu)"),
5298 (unsigned long) size, (unsigned long) pos);
5302 if (size <= 32 && pos < 32)
5307 else if (size <= 32)
5317 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5324 /* Use unsigned arithmetic. */
5328 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5330 as_bad (_("Unsupported large constant"));
5335 pos = imm_expr.X_add_number;
5336 size = imm2_expr.X_add_number;
5341 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5344 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5346 as_bad (_("Improper insert size (%lu, position %lu)"),
5347 (unsigned long) size, (unsigned long) pos);
5351 if (pos < 32 && (pos + size - 1) < 32)
5366 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5367 (int) (pos + size - 1));
5383 as_warn (_("Divide by zero."));
5385 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5387 macro_build (NULL, "break", "c", 7);
5394 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5395 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5399 expr1.X_add_number = 8;
5400 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5401 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5402 macro_build (NULL, "break", "c", 7);
5404 expr1.X_add_number = -1;
5406 load_register (AT, &expr1, dbl);
5407 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5408 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5411 expr1.X_add_number = 1;
5412 load_register (AT, &expr1, dbl);
5413 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5417 expr1.X_add_number = 0x80000000;
5418 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5422 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5423 /* We want to close the noreorder block as soon as possible, so
5424 that later insns are available for delay slot filling. */
5429 expr1.X_add_number = 8;
5430 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5431 macro_build (NULL, "nop", "");
5433 /* We want to close the noreorder block as soon as possible, so
5434 that later insns are available for delay slot filling. */
5437 macro_build (NULL, "break", "c", 6);
5439 macro_build (NULL, s, "d", dreg);
5478 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5480 as_warn (_("Divide by zero."));
5482 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5484 macro_build (NULL, "break", "c", 7);
5487 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5489 if (strcmp (s2, "mflo") == 0)
5490 move_register (dreg, sreg);
5492 move_register (dreg, ZERO);
5495 if (imm_expr.X_op == O_constant
5496 && imm_expr.X_add_number == -1
5497 && s[strlen (s) - 1] != 'u')
5499 if (strcmp (s2, "mflo") == 0)
5501 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5504 move_register (dreg, ZERO);
5509 load_register (AT, &imm_expr, dbl);
5510 macro_build (NULL, s, "z,s,t", sreg, AT);
5511 macro_build (NULL, s2, "d", dreg);
5533 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5534 macro_build (NULL, s, "z,s,t", sreg, treg);
5535 /* We want to close the noreorder block as soon as possible, so
5536 that later insns are available for delay slot filling. */
5541 expr1.X_add_number = 8;
5542 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5543 macro_build (NULL, s, "z,s,t", sreg, treg);
5545 /* We want to close the noreorder block as soon as possible, so
5546 that later insns are available for delay slot filling. */
5548 macro_build (NULL, "break", "c", 7);
5550 macro_build (NULL, s2, "d", dreg);
5562 /* Load the address of a symbol into a register. If breg is not
5563 zero, we then add a base register to it. */
5565 if (dbl && HAVE_32BIT_GPRS)
5566 as_warn (_("dla used to load 32-bit register"));
5568 if (!dbl && HAVE_64BIT_OBJECTS)
5569 as_warn (_("la used to load 64-bit address"));
5571 if (offset_expr.X_op == O_constant
5572 && offset_expr.X_add_number >= -0x8000
5573 && offset_expr.X_add_number < 0x8000)
5575 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5576 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5580 if (mips_opts.at && (treg == breg))
5590 if (offset_expr.X_op != O_symbol
5591 && offset_expr.X_op != O_constant)
5593 as_bad (_("Expression too complex"));
5594 offset_expr.X_op = O_constant;
5597 if (offset_expr.X_op == O_constant)
5598 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5599 else if (mips_pic == NO_PIC)
5601 /* If this is a reference to a GP relative symbol, we want
5602 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5604 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5605 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5606 If we have a constant, we need two instructions anyhow,
5607 so we may as well always use the latter form.
5609 With 64bit address space and a usable $at we want
5610 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5611 lui $at,<sym> (BFD_RELOC_HI16_S)
5612 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5613 daddiu $at,<sym> (BFD_RELOC_LO16)
5615 daddu $tempreg,$tempreg,$at
5617 If $at is already in use, we use a path which is suboptimal
5618 on superscalar processors.
5619 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5620 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5622 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5624 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5626 For GP relative symbols in 64bit address space we can use
5627 the same sequence as in 32bit address space. */
5628 if (HAVE_64BIT_SYMBOLS)
5630 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5631 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5633 relax_start (offset_expr.X_add_symbol);
5634 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5635 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5639 if (used_at == 0 && mips_opts.at)
5641 macro_build (&offset_expr, "lui", "t,u",
5642 tempreg, BFD_RELOC_MIPS_HIGHEST);
5643 macro_build (&offset_expr, "lui", "t,u",
5644 AT, BFD_RELOC_HI16_S);
5645 macro_build (&offset_expr, "daddiu", "t,r,j",
5646 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5647 macro_build (&offset_expr, "daddiu", "t,r,j",
5648 AT, AT, BFD_RELOC_LO16);
5649 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5650 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5655 macro_build (&offset_expr, "lui", "t,u",
5656 tempreg, BFD_RELOC_MIPS_HIGHEST);
5657 macro_build (&offset_expr, "daddiu", "t,r,j",
5658 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5659 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5660 macro_build (&offset_expr, "daddiu", "t,r,j",
5661 tempreg, tempreg, BFD_RELOC_HI16_S);
5662 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5663 macro_build (&offset_expr, "daddiu", "t,r,j",
5664 tempreg, tempreg, BFD_RELOC_LO16);
5667 if (mips_relax.sequence)
5672 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5673 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5675 relax_start (offset_expr.X_add_symbol);
5676 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5677 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5680 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5681 as_bad (_("Offset too large"));
5682 macro_build_lui (&offset_expr, tempreg);
5683 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5684 tempreg, tempreg, BFD_RELOC_LO16);
5685 if (mips_relax.sequence)
5689 else if (!mips_big_got && !HAVE_NEWABI)
5691 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5693 /* If this is a reference to an external symbol, and there
5694 is no constant, we want
5695 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5696 or for lca or if tempreg is PIC_CALL_REG
5697 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5698 For a local symbol, we want
5699 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5701 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5703 If we have a small constant, and this is a reference to
5704 an external symbol, we want
5705 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5707 addiu $tempreg,$tempreg,<constant>
5708 For a local symbol, we want the same instruction
5709 sequence, but we output a BFD_RELOC_LO16 reloc on the
5712 If we have a large constant, and this is a reference to
5713 an external symbol, we want
5714 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5715 lui $at,<hiconstant>
5716 addiu $at,$at,<loconstant>
5717 addu $tempreg,$tempreg,$at
5718 For a local symbol, we want the same instruction
5719 sequence, but we output a BFD_RELOC_LO16 reloc on the
5723 if (offset_expr.X_add_number == 0)
5725 if (mips_pic == SVR4_PIC
5727 && (call || tempreg == PIC_CALL_REG))
5728 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5730 relax_start (offset_expr.X_add_symbol);
5731 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5732 lw_reloc_type, mips_gp_register);
5735 /* We're going to put in an addu instruction using
5736 tempreg, so we may as well insert the nop right
5741 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5742 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5744 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5745 tempreg, tempreg, BFD_RELOC_LO16);
5747 /* FIXME: If breg == 0, and the next instruction uses
5748 $tempreg, then if this variant case is used an extra
5749 nop will be generated. */
5751 else if (offset_expr.X_add_number >= -0x8000
5752 && offset_expr.X_add_number < 0x8000)
5754 load_got_offset (tempreg, &offset_expr);
5756 add_got_offset (tempreg, &offset_expr);
5760 expr1.X_add_number = offset_expr.X_add_number;
5761 offset_expr.X_add_number =
5762 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5763 load_got_offset (tempreg, &offset_expr);
5764 offset_expr.X_add_number = expr1.X_add_number;
5765 /* If we are going to add in a base register, and the
5766 target register and the base register are the same,
5767 then we are using AT as a temporary register. Since
5768 we want to load the constant into AT, we add our
5769 current AT (from the global offset table) and the
5770 register into the register now, and pretend we were
5771 not using a base register. */
5775 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5780 add_got_offset_hilo (tempreg, &offset_expr, AT);
5784 else if (!mips_big_got && HAVE_NEWABI)
5786 int add_breg_early = 0;
5788 /* If this is a reference to an external, and there is no
5789 constant, or local symbol (*), with or without a
5791 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5792 or for lca or if tempreg is PIC_CALL_REG
5793 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5795 If we have a small constant, and this is a reference to
5796 an external symbol, we want
5797 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5798 addiu $tempreg,$tempreg,<constant>
5800 If we have a large constant, and this is a reference to
5801 an external symbol, we want
5802 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5803 lui $at,<hiconstant>
5804 addiu $at,$at,<loconstant>
5805 addu $tempreg,$tempreg,$at
5807 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5808 local symbols, even though it introduces an additional
5811 if (offset_expr.X_add_number)
5813 expr1.X_add_number = offset_expr.X_add_number;
5814 offset_expr.X_add_number = 0;
5816 relax_start (offset_expr.X_add_symbol);
5817 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5818 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5820 if (expr1.X_add_number >= -0x8000
5821 && expr1.X_add_number < 0x8000)
5823 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5824 tempreg, tempreg, BFD_RELOC_LO16);
5826 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5828 /* If we are going to add in a base register, and the
5829 target register and the base register are the same,
5830 then we are using AT as a temporary register. Since
5831 we want to load the constant into AT, we add our
5832 current AT (from the global offset table) and the
5833 register into the register now, and pretend we were
5834 not using a base register. */
5839 gas_assert (tempreg == AT);
5840 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5846 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5847 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5853 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5856 offset_expr.X_add_number = expr1.X_add_number;
5858 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5859 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5862 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5863 treg, tempreg, breg);
5869 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5871 relax_start (offset_expr.X_add_symbol);
5872 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5873 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5875 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5876 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5881 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5882 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5885 else if (mips_big_got && !HAVE_NEWABI)
5888 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5889 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5890 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5892 /* This is the large GOT case. If this is a reference to an
5893 external symbol, and there is no constant, we want
5894 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5895 addu $tempreg,$tempreg,$gp
5896 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5897 or for lca or if tempreg is PIC_CALL_REG
5898 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5899 addu $tempreg,$tempreg,$gp
5900 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5901 For a local symbol, we want
5902 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5904 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5906 If we have a small constant, and this is a reference to
5907 an external symbol, we want
5908 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5909 addu $tempreg,$tempreg,$gp
5910 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5912 addiu $tempreg,$tempreg,<constant>
5913 For a local symbol, we want
5914 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5916 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5918 If we have a large constant, and this is a reference to
5919 an external symbol, we want
5920 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5921 addu $tempreg,$tempreg,$gp
5922 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5923 lui $at,<hiconstant>
5924 addiu $at,$at,<loconstant>
5925 addu $tempreg,$tempreg,$at
5926 For a local symbol, we want
5927 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5928 lui $at,<hiconstant>
5929 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5930 addu $tempreg,$tempreg,$at
5933 expr1.X_add_number = offset_expr.X_add_number;
5934 offset_expr.X_add_number = 0;
5935 relax_start (offset_expr.X_add_symbol);
5936 gpdelay = reg_needs_delay (mips_gp_register);
5937 if (expr1.X_add_number == 0 && breg == 0
5938 && (call || tempreg == PIC_CALL_REG))
5940 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5941 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5943 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5944 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5945 tempreg, tempreg, mips_gp_register);
5946 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5947 tempreg, lw_reloc_type, tempreg);
5948 if (expr1.X_add_number == 0)
5952 /* We're going to put in an addu instruction using
5953 tempreg, so we may as well insert the nop right
5958 else if (expr1.X_add_number >= -0x8000
5959 && expr1.X_add_number < 0x8000)
5962 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5963 tempreg, tempreg, BFD_RELOC_LO16);
5967 /* If we are going to add in a base register, and the
5968 target register and the base register are the same,
5969 then we are using AT as a temporary register. Since
5970 we want to load the constant into AT, we add our
5971 current AT (from the global offset table) and the
5972 register into the register now, and pretend we were
5973 not using a base register. */
5978 gas_assert (tempreg == AT);
5980 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5985 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5986 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5990 offset_expr.X_add_number =
5991 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5996 /* This is needed because this instruction uses $gp, but
5997 the first instruction on the main stream does not. */
5998 macro_build (NULL, "nop", "");
6001 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6002 local_reloc_type, mips_gp_register);
6003 if (expr1.X_add_number >= -0x8000
6004 && expr1.X_add_number < 0x8000)
6007 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6008 tempreg, tempreg, BFD_RELOC_LO16);
6009 /* FIXME: If add_number is 0, and there was no base
6010 register, the external symbol case ended with a load,
6011 so if the symbol turns out to not be external, and
6012 the next instruction uses tempreg, an unnecessary nop
6013 will be inserted. */
6019 /* We must add in the base register now, as in the
6020 external symbol case. */
6021 gas_assert (tempreg == AT);
6023 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6026 /* We set breg to 0 because we have arranged to add
6027 it in in both cases. */
6031 macro_build_lui (&expr1, AT);
6032 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6033 AT, AT, BFD_RELOC_LO16);
6034 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6035 tempreg, tempreg, AT);
6040 else if (mips_big_got && HAVE_NEWABI)
6042 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6043 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6044 int add_breg_early = 0;
6046 /* This is the large GOT case. If this is a reference to an
6047 external symbol, and there is no constant, we want
6048 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6049 add $tempreg,$tempreg,$gp
6050 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6051 or for lca or if tempreg is PIC_CALL_REG
6052 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6053 add $tempreg,$tempreg,$gp
6054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6056 If we have a small constant, and this is a reference to
6057 an external symbol, we want
6058 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6059 add $tempreg,$tempreg,$gp
6060 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6061 addi $tempreg,$tempreg,<constant>
6063 If we have a large constant, and this is a reference to
6064 an external symbol, we want
6065 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6066 addu $tempreg,$tempreg,$gp
6067 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6068 lui $at,<hiconstant>
6069 addi $at,$at,<loconstant>
6070 add $tempreg,$tempreg,$at
6072 If we have NewABI, and we know it's a local symbol, we want
6073 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6074 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6075 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6077 relax_start (offset_expr.X_add_symbol);
6079 expr1.X_add_number = offset_expr.X_add_number;
6080 offset_expr.X_add_number = 0;
6082 if (expr1.X_add_number == 0 && breg == 0
6083 && (call || tempreg == PIC_CALL_REG))
6085 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6086 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6088 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6089 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6090 tempreg, tempreg, mips_gp_register);
6091 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6092 tempreg, lw_reloc_type, tempreg);
6094 if (expr1.X_add_number == 0)
6096 else if (expr1.X_add_number >= -0x8000
6097 && expr1.X_add_number < 0x8000)
6099 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6100 tempreg, tempreg, BFD_RELOC_LO16);
6102 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6104 /* If we are going to add in a base register, and the
6105 target register and the base register are the same,
6106 then we are using AT as a temporary register. Since
6107 we want to load the constant into AT, we add our
6108 current AT (from the global offset table) and the
6109 register into the register now, and pretend we were
6110 not using a base register. */
6115 gas_assert (tempreg == AT);
6116 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6122 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6123 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6128 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6131 offset_expr.X_add_number = expr1.X_add_number;
6132 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6133 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6134 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6135 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6138 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6139 treg, tempreg, breg);
6149 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6154 unsigned long temp = (treg << 16) | (0x01);
6155 macro_build (NULL, "c2", "C", temp);
6161 unsigned long temp = (0x02);
6162 macro_build (NULL, "c2", "C", temp);
6168 unsigned long temp = (treg << 16) | (0x02);
6169 macro_build (NULL, "c2", "C", temp);
6174 macro_build (NULL, "c2", "C", 3);
6179 unsigned long temp = (treg << 16) | 0x03;
6180 macro_build (NULL, "c2", "C", temp);
6185 /* The j instruction may not be used in PIC code, since it
6186 requires an absolute address. We convert it to a b
6188 if (mips_pic == NO_PIC)
6189 macro_build (&offset_expr, "j", "a");
6191 macro_build (&offset_expr, "b", "p");
6194 /* The jal instructions must be handled as macros because when
6195 generating PIC code they expand to multi-instruction
6196 sequences. Normally they are simple instructions. */
6201 if (mips_pic == NO_PIC)
6202 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6205 if (sreg != PIC_CALL_REG)
6206 as_warn (_("MIPS PIC call to register other than $25"));
6208 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6209 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6211 if (mips_cprestore_offset < 0)
6212 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6215 if (!mips_frame_reg_valid)
6217 as_warn (_("No .frame pseudo-op used in PIC code"));
6218 /* Quiet this warning. */
6219 mips_frame_reg_valid = 1;
6221 if (!mips_cprestore_valid)
6223 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6224 /* Quiet this warning. */
6225 mips_cprestore_valid = 1;
6227 if (mips_opts.noreorder)
6228 macro_build (NULL, "nop", "");
6229 expr1.X_add_number = mips_cprestore_offset;
6230 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6233 HAVE_64BIT_ADDRESSES);
6241 if (mips_pic == NO_PIC)
6242 macro_build (&offset_expr, "jal", "a");
6243 else if (mips_pic == SVR4_PIC)
6245 /* If this is a reference to an external symbol, and we are
6246 using a small GOT, we want
6247 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6251 lw $gp,cprestore($sp)
6252 The cprestore value is set using the .cprestore
6253 pseudo-op. If we are using a big GOT, we want
6254 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6256 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6260 lw $gp,cprestore($sp)
6261 If the symbol is not external, we want
6262 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6264 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6267 lw $gp,cprestore($sp)
6269 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6270 sequences above, minus nops, unless the symbol is local,
6271 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6277 relax_start (offset_expr.X_add_symbol);
6278 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6279 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6282 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6283 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6289 relax_start (offset_expr.X_add_symbol);
6290 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6291 BFD_RELOC_MIPS_CALL_HI16);
6292 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6293 PIC_CALL_REG, mips_gp_register);
6294 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6295 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6298 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6299 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6301 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6302 PIC_CALL_REG, PIC_CALL_REG,
6303 BFD_RELOC_MIPS_GOT_OFST);
6307 macro_build_jalr (&offset_expr);
6311 relax_start (offset_expr.X_add_symbol);
6314 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6315 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6324 gpdelay = reg_needs_delay (mips_gp_register);
6325 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6326 BFD_RELOC_MIPS_CALL_HI16);
6327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6328 PIC_CALL_REG, mips_gp_register);
6329 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6330 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6335 macro_build (NULL, "nop", "");
6337 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6338 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6341 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6342 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6344 macro_build_jalr (&offset_expr);
6346 if (mips_cprestore_offset < 0)
6347 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6350 if (!mips_frame_reg_valid)
6352 as_warn (_("No .frame pseudo-op used in PIC code"));
6353 /* Quiet this warning. */
6354 mips_frame_reg_valid = 1;
6356 if (!mips_cprestore_valid)
6358 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6359 /* Quiet this warning. */
6360 mips_cprestore_valid = 1;
6362 if (mips_opts.noreorder)
6363 macro_build (NULL, "nop", "");
6364 expr1.X_add_number = mips_cprestore_offset;
6365 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6368 HAVE_64BIT_ADDRESSES);
6372 else if (mips_pic == VXWORKS_PIC)
6373 as_bad (_("Non-PIC jump used in PIC library"));
6396 /* Itbl support may require additional care here. */
6401 /* Itbl support may require additional care here. */
6406 /* Itbl support may require additional care here. */
6411 /* Itbl support may require additional care here. */
6424 /* Itbl support may require additional care here. */
6429 /* Itbl support may require additional care here. */
6434 /* Itbl support may require additional care here. */
6454 if (breg == treg || coproc || lr)
6475 /* Itbl support may require additional care here. */
6480 /* Itbl support may require additional care here. */
6485 /* Itbl support may require additional care here. */
6490 /* Itbl support may require additional care here. */
6511 /* Itbl support may require additional care here. */
6515 /* Itbl support may require additional care here. */
6520 /* Itbl support may require additional care here. */
6533 && NO_ISA_COP (mips_opts.arch)
6534 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6536 as_bad (_("Opcode not supported on this processor: %s"),
6537 mips_cpu_info_from_arch (mips_opts.arch)->name);
6541 /* Itbl support may require additional care here. */
6542 if (mask == M_LWC1_AB
6543 || mask == M_SWC1_AB
6544 || mask == M_LDC1_AB
6545 || mask == M_SDC1_AB
6549 else if (mask == M_CACHE_AB)
6556 if (offset_expr.X_op != O_constant
6557 && offset_expr.X_op != O_symbol)
6559 as_bad (_("Expression too complex"));
6560 offset_expr.X_op = O_constant;
6563 if (HAVE_32BIT_ADDRESSES
6564 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6568 sprintf_vma (value, offset_expr.X_add_number);
6569 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6572 /* A constant expression in PIC code can be handled just as it
6573 is in non PIC code. */
6574 if (offset_expr.X_op == O_constant)
6576 expr1.X_add_number = offset_expr.X_add_number;
6577 normalize_address_expr (&expr1);
6578 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6580 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6581 & ~(bfd_vma) 0xffff);
6582 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6584 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6585 tempreg, tempreg, breg);
6588 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6590 else if (mips_pic == NO_PIC)
6592 /* If this is a reference to a GP relative symbol, and there
6593 is no base register, we want
6594 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6595 Otherwise, if there is no base register, we want
6596 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6597 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6598 If we have a constant, we need two instructions anyhow,
6599 so we always use the latter form.
6601 If we have a base register, and this is a reference to a
6602 GP relative symbol, we want
6603 addu $tempreg,$breg,$gp
6604 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6606 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6607 addu $tempreg,$tempreg,$breg
6608 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6609 With a constant we always use the latter case.
6611 With 64bit address space and no base register and $at usable,
6613 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6614 lui $at,<sym> (BFD_RELOC_HI16_S)
6615 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6618 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6619 If we have a base register, we want
6620 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6621 lui $at,<sym> (BFD_RELOC_HI16_S)
6622 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6626 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6628 Without $at we can't generate the optimal path for superscalar
6629 processors here since this would require two temporary registers.
6630 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6631 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6633 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6635 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6636 If we have a base register, we want
6637 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6638 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6640 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6642 daddu $tempreg,$tempreg,$breg
6643 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6645 For GP relative symbols in 64bit address space we can use
6646 the same sequence as in 32bit address space. */
6647 if (HAVE_64BIT_SYMBOLS)
6649 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6650 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6652 relax_start (offset_expr.X_add_symbol);
6655 macro_build (&offset_expr, s, fmt, treg,
6656 BFD_RELOC_GPREL16, mips_gp_register);
6660 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6661 tempreg, breg, mips_gp_register);
6662 macro_build (&offset_expr, s, fmt, treg,
6663 BFD_RELOC_GPREL16, tempreg);
6668 if (used_at == 0 && mips_opts.at)
6670 macro_build (&offset_expr, "lui", "t,u", tempreg,
6671 BFD_RELOC_MIPS_HIGHEST);
6672 macro_build (&offset_expr, "lui", "t,u", AT,
6674 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6675 tempreg, BFD_RELOC_MIPS_HIGHER);
6677 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6678 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6679 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6680 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6686 macro_build (&offset_expr, "lui", "t,u", tempreg,
6687 BFD_RELOC_MIPS_HIGHEST);
6688 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6689 tempreg, BFD_RELOC_MIPS_HIGHER);
6690 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6691 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6692 tempreg, BFD_RELOC_HI16_S);
6693 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6695 macro_build (NULL, "daddu", "d,v,t",
6696 tempreg, tempreg, breg);
6697 macro_build (&offset_expr, s, fmt, treg,
6698 BFD_RELOC_LO16, tempreg);
6701 if (mips_relax.sequence)
6708 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6709 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6711 relax_start (offset_expr.X_add_symbol);
6712 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6716 macro_build_lui (&offset_expr, tempreg);
6717 macro_build (&offset_expr, s, fmt, treg,
6718 BFD_RELOC_LO16, tempreg);
6719 if (mips_relax.sequence)
6724 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6725 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6727 relax_start (offset_expr.X_add_symbol);
6728 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6729 tempreg, breg, mips_gp_register);
6730 macro_build (&offset_expr, s, fmt, treg,
6731 BFD_RELOC_GPREL16, tempreg);
6734 macro_build_lui (&offset_expr, tempreg);
6735 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6736 tempreg, tempreg, breg);
6737 macro_build (&offset_expr, s, fmt, treg,
6738 BFD_RELOC_LO16, tempreg);
6739 if (mips_relax.sequence)
6743 else if (!mips_big_got)
6745 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6747 /* If this is a reference to an external symbol, we want
6748 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6750 <op> $treg,0($tempreg)
6752 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6754 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6755 <op> $treg,0($tempreg)
6758 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6759 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6761 If there is a base register, we add it to $tempreg before
6762 the <op>. If there is a constant, we stick it in the
6763 <op> instruction. We don't handle constants larger than
6764 16 bits, because we have no way to load the upper 16 bits
6765 (actually, we could handle them for the subset of cases
6766 in which we are not using $at). */
6767 gas_assert (offset_expr.X_op == O_symbol);
6770 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6771 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6773 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6774 tempreg, tempreg, breg);
6775 macro_build (&offset_expr, s, fmt, treg,
6776 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6779 expr1.X_add_number = offset_expr.X_add_number;
6780 offset_expr.X_add_number = 0;
6781 if (expr1.X_add_number < -0x8000
6782 || expr1.X_add_number >= 0x8000)
6783 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6784 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6785 lw_reloc_type, mips_gp_register);
6787 relax_start (offset_expr.X_add_symbol);
6789 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6790 tempreg, BFD_RELOC_LO16);
6793 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6794 tempreg, tempreg, breg);
6795 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6797 else if (mips_big_got && !HAVE_NEWABI)
6801 /* If this is a reference to an external symbol, we want
6802 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6803 addu $tempreg,$tempreg,$gp
6804 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6805 <op> $treg,0($tempreg)
6807 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6809 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6810 <op> $treg,0($tempreg)
6811 If there is a base register, we add it to $tempreg before
6812 the <op>. If there is a constant, we stick it in the
6813 <op> instruction. We don't handle constants larger than
6814 16 bits, because we have no way to load the upper 16 bits
6815 (actually, we could handle them for the subset of cases
6816 in which we are not using $at). */
6817 gas_assert (offset_expr.X_op == O_symbol);
6818 expr1.X_add_number = offset_expr.X_add_number;
6819 offset_expr.X_add_number = 0;
6820 if (expr1.X_add_number < -0x8000
6821 || expr1.X_add_number >= 0x8000)
6822 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6823 gpdelay = reg_needs_delay (mips_gp_register);
6824 relax_start (offset_expr.X_add_symbol);
6825 macro_build (&offset_expr, "lui", "t,u", tempreg,
6826 BFD_RELOC_MIPS_GOT_HI16);
6827 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6829 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6830 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6833 macro_build (NULL, "nop", "");
6834 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6835 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6837 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6838 tempreg, BFD_RELOC_LO16);
6842 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6843 tempreg, tempreg, breg);
6844 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6846 else if (mips_big_got && HAVE_NEWABI)
6848 /* If this is a reference to an external symbol, we want
6849 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6850 add $tempreg,$tempreg,$gp
6851 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6852 <op> $treg,<ofst>($tempreg)
6853 Otherwise, for local symbols, we want:
6854 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6855 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6856 gas_assert (offset_expr.X_op == O_symbol);
6857 expr1.X_add_number = offset_expr.X_add_number;
6858 offset_expr.X_add_number = 0;
6859 if (expr1.X_add_number < -0x8000
6860 || expr1.X_add_number >= 0x8000)
6861 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6862 relax_start (offset_expr.X_add_symbol);
6863 macro_build (&offset_expr, "lui", "t,u", tempreg,
6864 BFD_RELOC_MIPS_GOT_HI16);
6865 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6867 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6868 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6870 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6871 tempreg, tempreg, breg);
6872 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6875 offset_expr.X_add_number = expr1.X_add_number;
6876 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6877 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6879 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6880 tempreg, tempreg, breg);
6881 macro_build (&offset_expr, s, fmt, treg,
6882 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6892 load_register (treg, &imm_expr, 0);
6896 load_register (treg, &imm_expr, 1);
6900 if (imm_expr.X_op == O_constant)
6903 load_register (AT, &imm_expr, 0);
6904 macro_build (NULL, "mtc1", "t,G", AT, treg);
6909 gas_assert (offset_expr.X_op == O_symbol
6910 && strcmp (segment_name (S_GET_SEGMENT
6911 (offset_expr.X_add_symbol)),
6913 && offset_expr.X_add_number == 0);
6914 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6915 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6920 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6921 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6922 order 32 bits of the value and the low order 32 bits are either
6923 zero or in OFFSET_EXPR. */
6924 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6926 if (HAVE_64BIT_GPRS)
6927 load_register (treg, &imm_expr, 1);
6932 if (target_big_endian)
6944 load_register (hreg, &imm_expr, 0);
6947 if (offset_expr.X_op == O_absent)
6948 move_register (lreg, 0);
6951 gas_assert (offset_expr.X_op == O_constant);
6952 load_register (lreg, &offset_expr, 0);
6959 /* We know that sym is in the .rdata section. First we get the
6960 upper 16 bits of the address. */
6961 if (mips_pic == NO_PIC)
6963 macro_build_lui (&offset_expr, AT);
6968 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6969 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6973 /* Now we load the register(s). */
6974 if (HAVE_64BIT_GPRS)
6977 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6982 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6985 /* FIXME: How in the world do we deal with the possible
6987 offset_expr.X_add_number += 4;
6988 macro_build (&offset_expr, "lw", "t,o(b)",
6989 treg + 1, BFD_RELOC_LO16, AT);
6995 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6996 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6997 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6998 the value and the low order 32 bits are either zero or in
7000 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7003 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7004 if (HAVE_64BIT_FPRS)
7006 gas_assert (HAVE_64BIT_GPRS);
7007 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7011 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7012 if (offset_expr.X_op == O_absent)
7013 macro_build (NULL, "mtc1", "t,G", 0, treg);
7016 gas_assert (offset_expr.X_op == O_constant);
7017 load_register (AT, &offset_expr, 0);
7018 macro_build (NULL, "mtc1", "t,G", AT, treg);
7024 gas_assert (offset_expr.X_op == O_symbol
7025 && offset_expr.X_add_number == 0);
7026 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7027 if (strcmp (s, ".lit8") == 0)
7029 if (mips_opts.isa != ISA_MIPS1)
7031 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7032 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7035 breg = mips_gp_register;
7036 r = BFD_RELOC_MIPS_LITERAL;
7041 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7043 if (mips_pic != NO_PIC)
7044 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7045 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7048 /* FIXME: This won't work for a 64 bit address. */
7049 macro_build_lui (&offset_expr, AT);
7052 if (mips_opts.isa != ISA_MIPS1)
7054 macro_build (&offset_expr, "ldc1", "T,o(b)",
7055 treg, BFD_RELOC_LO16, AT);
7064 /* Even on a big endian machine $fn comes before $fn+1. We have
7065 to adjust when loading from memory. */
7068 gas_assert (mips_opts.isa == ISA_MIPS1);
7069 macro_build (&offset_expr, "lwc1", "T,o(b)",
7070 target_big_endian ? treg + 1 : treg, r, breg);
7071 /* FIXME: A possible overflow which I don't know how to deal
7073 offset_expr.X_add_number += 4;
7074 macro_build (&offset_expr, "lwc1", "T,o(b)",
7075 target_big_endian ? treg : treg + 1, r, breg);
7079 gas_assert (mips_opts.isa == ISA_MIPS1);
7080 /* Even on a big endian machine $fn comes before $fn+1. We have
7081 to adjust when storing to memory. */
7082 macro_build (&offset_expr, "swc1", "T,o(b)",
7083 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7084 offset_expr.X_add_number += 4;
7085 macro_build (&offset_expr, "swc1", "T,o(b)",
7086 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7091 * The MIPS assembler seems to check for X_add_number not
7092 * being double aligned and generating:
7095 * addiu at,at,%lo(foo+1)
7098 * But, the resulting address is the same after relocation so why
7099 * generate the extra instruction?
7101 /* Itbl support may require additional care here. */
7103 if (mips_opts.isa != ISA_MIPS1)
7114 if (mips_opts.isa != ISA_MIPS1)
7122 /* Itbl support may require additional care here. */
7127 if (HAVE_64BIT_GPRS)
7138 if (HAVE_64BIT_GPRS)
7148 if (offset_expr.X_op != O_symbol
7149 && offset_expr.X_op != O_constant)
7151 as_bad (_("Expression too complex"));
7152 offset_expr.X_op = O_constant;
7155 if (HAVE_32BIT_ADDRESSES
7156 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7160 sprintf_vma (value, offset_expr.X_add_number);
7161 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7164 /* Even on a big endian machine $fn comes before $fn+1. We have
7165 to adjust when loading from memory. We set coproc if we must
7166 load $fn+1 first. */
7167 /* Itbl support may require additional care here. */
7168 if (!target_big_endian)
7171 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7173 /* If this is a reference to a GP relative symbol, we want
7174 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7175 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7176 If we have a base register, we use this
7178 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7179 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7180 If this is not a GP relative symbol, we want
7181 lui $at,<sym> (BFD_RELOC_HI16_S)
7182 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7183 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7184 If there is a base register, we add it to $at after the
7185 lui instruction. If there is a constant, we always use
7187 if (offset_expr.X_op == O_symbol
7188 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7189 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7191 relax_start (offset_expr.X_add_symbol);
7194 tempreg = mips_gp_register;
7198 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7199 AT, breg, mips_gp_register);
7204 /* Itbl support may require additional care here. */
7205 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7206 BFD_RELOC_GPREL16, tempreg);
7207 offset_expr.X_add_number += 4;
7209 /* Set mips_optimize to 2 to avoid inserting an
7211 hold_mips_optimize = mips_optimize;
7213 /* Itbl support may require additional care here. */
7214 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7215 BFD_RELOC_GPREL16, tempreg);
7216 mips_optimize = hold_mips_optimize;
7220 offset_expr.X_add_number -= 4;
7223 macro_build_lui (&offset_expr, AT);
7225 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7226 /* Itbl support may require additional care here. */
7227 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7228 BFD_RELOC_LO16, AT);
7229 /* FIXME: How do we handle overflow here? */
7230 offset_expr.X_add_number += 4;
7231 /* Itbl support may require additional care here. */
7232 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7233 BFD_RELOC_LO16, AT);
7234 if (mips_relax.sequence)
7237 else if (!mips_big_got)
7239 /* If this is a reference to an external symbol, we want
7240 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7245 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7247 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7248 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7249 If there is a base register we add it to $at before the
7250 lwc1 instructions. If there is a constant we include it
7251 in the lwc1 instructions. */
7253 expr1.X_add_number = offset_expr.X_add_number;
7254 if (expr1.X_add_number < -0x8000
7255 || expr1.X_add_number >= 0x8000 - 4)
7256 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7257 load_got_offset (AT, &offset_expr);
7260 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7262 /* Set mips_optimize to 2 to avoid inserting an undesired
7264 hold_mips_optimize = mips_optimize;
7267 /* Itbl support may require additional care here. */
7268 relax_start (offset_expr.X_add_symbol);
7269 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7270 BFD_RELOC_LO16, AT);
7271 expr1.X_add_number += 4;
7272 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7273 BFD_RELOC_LO16, AT);
7275 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7276 BFD_RELOC_LO16, AT);
7277 offset_expr.X_add_number += 4;
7278 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7279 BFD_RELOC_LO16, AT);
7282 mips_optimize = hold_mips_optimize;
7284 else if (mips_big_got)
7288 /* If this is a reference to an external symbol, we want
7289 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7291 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7296 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7298 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7299 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7300 If there is a base register we add it to $at before the
7301 lwc1 instructions. If there is a constant we include it
7302 in the lwc1 instructions. */
7304 expr1.X_add_number = offset_expr.X_add_number;
7305 offset_expr.X_add_number = 0;
7306 if (expr1.X_add_number < -0x8000
7307 || expr1.X_add_number >= 0x8000 - 4)
7308 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7309 gpdelay = reg_needs_delay (mips_gp_register);
7310 relax_start (offset_expr.X_add_symbol);
7311 macro_build (&offset_expr, "lui", "t,u",
7312 AT, BFD_RELOC_MIPS_GOT_HI16);
7313 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7314 AT, AT, mips_gp_register);
7315 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7316 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7320 /* Itbl support may require additional care here. */
7321 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7322 BFD_RELOC_LO16, AT);
7323 expr1.X_add_number += 4;
7325 /* Set mips_optimize to 2 to avoid inserting an undesired
7327 hold_mips_optimize = mips_optimize;
7329 /* Itbl support may require additional care here. */
7330 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7331 BFD_RELOC_LO16, AT);
7332 mips_optimize = hold_mips_optimize;
7333 expr1.X_add_number -= 4;
7336 offset_expr.X_add_number = expr1.X_add_number;
7338 macro_build (NULL, "nop", "");
7339 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7340 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7343 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7344 /* Itbl support may require additional care here. */
7345 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7346 BFD_RELOC_LO16, AT);
7347 offset_expr.X_add_number += 4;
7349 /* Set mips_optimize to 2 to avoid inserting an undesired
7351 hold_mips_optimize = mips_optimize;
7353 /* Itbl support may require additional care here. */
7354 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7355 BFD_RELOC_LO16, AT);
7356 mips_optimize = hold_mips_optimize;
7365 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7368 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7370 macro_build (&offset_expr, s, "t,o(b)", treg,
7371 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7373 if (!HAVE_64BIT_GPRS)
7375 offset_expr.X_add_number += 4;
7376 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7377 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7382 /* New code added to support COPZ instructions.
7383 This code builds table entries out of the macros in mip_opcodes.
7384 R4000 uses interlocks to handle coproc delays.
7385 Other chips (like the R3000) require nops to be inserted for delays.
7387 FIXME: Currently, we require that the user handle delays.
7388 In order to fill delay slots for non-interlocked chips,
7389 we must have a way to specify delays based on the coprocessor.
7390 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7391 What are the side-effects of the cop instruction?
7392 What cache support might we have and what are its effects?
7393 Both coprocessor & memory require delays. how long???
7394 What registers are read/set/modified?
7396 If an itbl is provided to interpret cop instructions,
7397 this knowledge can be encoded in the itbl spec. */
7411 if (NO_ISA_COP (mips_opts.arch)
7412 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7414 as_bad (_("opcode not supported on this processor: %s"),
7415 mips_cpu_info_from_arch (mips_opts.arch)->name);
7419 /* For now we just do C (same as Cz). The parameter will be
7420 stored in insn_opcode by mips_ip. */
7421 macro_build (NULL, s, "C", ip->insn_opcode);
7425 move_register (dreg, sreg);
7431 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7432 macro_build (NULL, "mflo", "d", dreg);
7438 /* The MIPS assembler some times generates shifts and adds. I'm
7439 not trying to be that fancy. GCC should do this for us
7442 load_register (AT, &imm_expr, dbl);
7443 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7444 macro_build (NULL, "mflo", "d", dreg);
7460 load_register (AT, &imm_expr, dbl);
7461 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7462 macro_build (NULL, "mflo", "d", dreg);
7463 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7464 macro_build (NULL, "mfhi", "d", AT);
7466 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7469 expr1.X_add_number = 8;
7470 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7471 macro_build (NULL, "nop", "");
7472 macro_build (NULL, "break", "c", 6);
7475 macro_build (NULL, "mflo", "d", dreg);
7491 load_register (AT, &imm_expr, dbl);
7492 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7493 sreg, imm ? AT : treg);
7494 macro_build (NULL, "mfhi", "d", AT);
7495 macro_build (NULL, "mflo", "d", dreg);
7497 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7500 expr1.X_add_number = 8;
7501 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7502 macro_build (NULL, "nop", "");
7503 macro_build (NULL, "break", "c", 6);
7509 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7520 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7521 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7525 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7526 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7527 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7528 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7532 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7543 macro_build (NULL, "negu", "d,w", tempreg, treg);
7544 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7548 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7549 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7550 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7551 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7560 if (imm_expr.X_op != O_constant)
7561 as_bad (_("Improper rotate count"));
7562 rot = imm_expr.X_add_number & 0x3f;
7563 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7565 rot = (64 - rot) & 0x3f;
7567 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7569 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7574 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7577 l = (rot < 0x20) ? "dsll" : "dsll32";
7578 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7581 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7582 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7583 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7591 if (imm_expr.X_op != O_constant)
7592 as_bad (_("Improper rotate count"));
7593 rot = imm_expr.X_add_number & 0x1f;
7594 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7596 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7601 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7605 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7606 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7607 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7612 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7614 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7618 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7619 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7620 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7621 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7625 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7627 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7631 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7632 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7633 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7634 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7643 if (imm_expr.X_op != O_constant)
7644 as_bad (_("Improper rotate count"));
7645 rot = imm_expr.X_add_number & 0x3f;
7646 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7649 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7651 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7656 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7659 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7660 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7663 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7664 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7665 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7673 if (imm_expr.X_op != O_constant)
7674 as_bad (_("Improper rotate count"));
7675 rot = imm_expr.X_add_number & 0x1f;
7676 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7678 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7683 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7687 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7688 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7689 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7695 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7697 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7700 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7701 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7706 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7708 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7713 as_warn (_("Instruction %s: result is always false"),
7715 move_register (dreg, 0);
7718 if (CPU_HAS_SEQ (mips_opts.arch)
7719 && -512 <= imm_expr.X_add_number
7720 && imm_expr.X_add_number < 512)
7722 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7723 (int) imm_expr.X_add_number);
7726 if (imm_expr.X_op == O_constant
7727 && imm_expr.X_add_number >= 0
7728 && imm_expr.X_add_number < 0x10000)
7730 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7732 else if (imm_expr.X_op == O_constant
7733 && imm_expr.X_add_number > -0x8000
7734 && imm_expr.X_add_number < 0)
7736 imm_expr.X_add_number = -imm_expr.X_add_number;
7737 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7738 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7740 else if (CPU_HAS_SEQ (mips_opts.arch))
7743 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7744 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7749 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7750 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7753 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7756 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7762 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7763 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7766 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7768 if (imm_expr.X_op == O_constant
7769 && imm_expr.X_add_number >= -0x8000
7770 && imm_expr.X_add_number < 0x8000)
7772 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7773 dreg, sreg, BFD_RELOC_LO16);
7777 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7778 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7782 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7785 case M_SGT: /* sreg > treg <==> treg < sreg */
7791 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7794 case M_SGT_I: /* sreg > I <==> I < sreg */
7801 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7802 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7805 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7811 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7812 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7815 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7822 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7823 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7824 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7828 if (imm_expr.X_op == O_constant
7829 && imm_expr.X_add_number >= -0x8000
7830 && imm_expr.X_add_number < 0x8000)
7832 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7836 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7837 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7841 if (imm_expr.X_op == O_constant
7842 && imm_expr.X_add_number >= -0x8000
7843 && imm_expr.X_add_number < 0x8000)
7845 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7850 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7851 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7856 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7858 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7861 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7862 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7867 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7869 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7874 as_warn (_("Instruction %s: result is always true"),
7876 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7877 dreg, 0, BFD_RELOC_LO16);
7880 if (CPU_HAS_SEQ (mips_opts.arch)
7881 && -512 <= imm_expr.X_add_number
7882 && imm_expr.X_add_number < 512)
7884 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
7885 (int) imm_expr.X_add_number);
7888 if (imm_expr.X_op == O_constant
7889 && imm_expr.X_add_number >= 0
7890 && imm_expr.X_add_number < 0x10000)
7892 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7894 else if (imm_expr.X_op == O_constant
7895 && imm_expr.X_add_number > -0x8000
7896 && imm_expr.X_add_number < 0)
7898 imm_expr.X_add_number = -imm_expr.X_add_number;
7899 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7900 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7902 else if (CPU_HAS_SEQ (mips_opts.arch))
7905 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7906 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
7911 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7912 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7915 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7921 if (imm_expr.X_op == O_constant
7922 && imm_expr.X_add_number > -0x8000
7923 && imm_expr.X_add_number <= 0x8000)
7925 imm_expr.X_add_number = -imm_expr.X_add_number;
7926 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7927 dreg, sreg, BFD_RELOC_LO16);
7931 load_register (AT, &imm_expr, dbl);
7932 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7938 if (imm_expr.X_op == O_constant
7939 && imm_expr.X_add_number > -0x8000
7940 && imm_expr.X_add_number <= 0x8000)
7942 imm_expr.X_add_number = -imm_expr.X_add_number;
7943 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7944 dreg, sreg, BFD_RELOC_LO16);
7948 load_register (AT, &imm_expr, dbl);
7949 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7971 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7972 macro_build (NULL, s, "s,t", sreg, AT);
7977 gas_assert (mips_opts.isa == ISA_MIPS1);
7979 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7980 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7983 * Is the double cfc1 instruction a bug in the mips assembler;
7984 * or is there a reason for it?
7987 macro_build (NULL, "cfc1", "t,G", treg, RA);
7988 macro_build (NULL, "cfc1", "t,G", treg, RA);
7989 macro_build (NULL, "nop", "");
7990 expr1.X_add_number = 3;
7991 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7992 expr1.X_add_number = 2;
7993 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7994 macro_build (NULL, "ctc1", "t,G", AT, RA);
7995 macro_build (NULL, "nop", "");
7996 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7998 macro_build (NULL, "ctc1", "t,G", treg, RA);
7999 macro_build (NULL, "nop", "");
8010 if (offset_expr.X_add_number >= 0x7fff)
8011 as_bad (_("Operand overflow"));
8012 if (!target_big_endian)
8013 ++offset_expr.X_add_number;
8014 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8015 if (!target_big_endian)
8016 --offset_expr.X_add_number;
8018 ++offset_expr.X_add_number;
8019 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8020 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8021 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8034 if (offset_expr.X_add_number >= 0x8000 - off)
8035 as_bad (_("Operand overflow"));
8043 if (!target_big_endian)
8044 offset_expr.X_add_number += off;
8045 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8046 if (!target_big_endian)
8047 offset_expr.X_add_number -= off;
8049 offset_expr.X_add_number += off;
8050 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8052 /* If necessary, move the result in tempreg to the final destination. */
8053 if (treg == tempreg)
8055 /* Protect second load's delay slot. */
8057 move_register (treg, tempreg);
8071 load_address (AT, &offset_expr, &used_at);
8073 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8074 if (!target_big_endian)
8075 expr1.X_add_number = off;
8077 expr1.X_add_number = 0;
8078 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8079 if (!target_big_endian)
8080 expr1.X_add_number = 0;
8082 expr1.X_add_number = off;
8083 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8089 load_address (AT, &offset_expr, &used_at);
8091 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8092 if (target_big_endian)
8093 expr1.X_add_number = 0;
8094 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8095 treg, BFD_RELOC_LO16, AT);
8096 if (target_big_endian)
8097 expr1.X_add_number = 1;
8099 expr1.X_add_number = 0;
8100 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8101 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8102 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8107 if (offset_expr.X_add_number >= 0x7fff)
8108 as_bad (_("Operand overflow"));
8109 if (target_big_endian)
8110 ++offset_expr.X_add_number;
8111 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8112 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8113 if (target_big_endian)
8114 --offset_expr.X_add_number;
8116 ++offset_expr.X_add_number;
8117 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8130 if (offset_expr.X_add_number >= 0x8000 - off)
8131 as_bad (_("Operand overflow"));
8132 if (!target_big_endian)
8133 offset_expr.X_add_number += off;
8134 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8135 if (!target_big_endian)
8136 offset_expr.X_add_number -= off;
8138 offset_expr.X_add_number += off;
8139 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8153 load_address (AT, &offset_expr, &used_at);
8155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8156 if (!target_big_endian)
8157 expr1.X_add_number = off;
8159 expr1.X_add_number = 0;
8160 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8161 if (!target_big_endian)
8162 expr1.X_add_number = 0;
8164 expr1.X_add_number = off;
8165 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8170 load_address (AT, &offset_expr, &used_at);
8172 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8173 if (!target_big_endian)
8174 expr1.X_add_number = 0;
8175 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8176 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8177 if (!target_big_endian)
8178 expr1.X_add_number = 1;
8180 expr1.X_add_number = 0;
8181 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8182 if (!target_big_endian)
8183 expr1.X_add_number = 0;
8185 expr1.X_add_number = 1;
8186 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8187 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8188 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8192 /* FIXME: Check if this is one of the itbl macros, since they
8193 are added dynamically. */
8194 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8197 if (!mips_opts.at && used_at)
8198 as_bad (_("Macro used $at after \".set noat\""));
8201 /* Implement macros in mips16 mode. */
8204 mips16_macro (struct mips_cl_insn *ip)
8207 int xreg, yreg, zreg, tmp;
8210 const char *s, *s2, *s3;
8212 mask = ip->insn_mo->mask;
8214 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8215 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8216 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8218 expr1.X_op = O_constant;
8219 expr1.X_op_symbol = NULL;
8220 expr1.X_add_symbol = NULL;
8221 expr1.X_add_number = 1;
8241 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8242 expr1.X_add_number = 2;
8243 macro_build (&expr1, "bnez", "x,p", yreg);
8244 macro_build (NULL, "break", "6", 7);
8246 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8247 since that causes an overflow. We should do that as well,
8248 but I don't see how to do the comparisons without a temporary
8251 macro_build (NULL, s, "x", zreg);
8271 macro_build (NULL, s, "0,x,y", xreg, yreg);
8272 expr1.X_add_number = 2;
8273 macro_build (&expr1, "bnez", "x,p", yreg);
8274 macro_build (NULL, "break", "6", 7);
8276 macro_build (NULL, s2, "x", zreg);
8282 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8283 macro_build (NULL, "mflo", "x", zreg);
8291 if (imm_expr.X_op != O_constant)
8292 as_bad (_("Unsupported large constant"));
8293 imm_expr.X_add_number = -imm_expr.X_add_number;
8294 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8298 if (imm_expr.X_op != O_constant)
8299 as_bad (_("Unsupported large constant"));
8300 imm_expr.X_add_number = -imm_expr.X_add_number;
8301 macro_build (&imm_expr, "addiu", "x,k", xreg);
8305 if (imm_expr.X_op != O_constant)
8306 as_bad (_("Unsupported large constant"));
8307 imm_expr.X_add_number = -imm_expr.X_add_number;
8308 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8330 goto do_reverse_branch;
8334 goto do_reverse_branch;
8346 goto do_reverse_branch;
8357 macro_build (NULL, s, "x,y", xreg, yreg);
8358 macro_build (&offset_expr, s2, "p");
8385 goto do_addone_branch_i;
8390 goto do_addone_branch_i;
8405 goto do_addone_branch_i;
8412 if (imm_expr.X_op != O_constant)
8413 as_bad (_("Unsupported large constant"));
8414 ++imm_expr.X_add_number;
8417 macro_build (&imm_expr, s, s3, xreg);
8418 macro_build (&offset_expr, s2, "p");
8422 expr1.X_add_number = 0;
8423 macro_build (&expr1, "slti", "x,8", yreg);
8425 move_register (xreg, yreg);
8426 expr1.X_add_number = 2;
8427 macro_build (&expr1, "bteqz", "p");
8428 macro_build (NULL, "neg", "x,w", xreg, xreg);
8432 /* For consistency checking, verify that all bits are specified either
8433 by the match/mask part of the instruction definition, or by the
8436 validate_mips_insn (const struct mips_opcode *opc)
8438 const char *p = opc->args;
8440 unsigned long used_bits = opc->mask;
8442 if ((used_bits & opc->match) != opc->match)
8444 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8445 opc->name, opc->args);
8448 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8458 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8459 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8460 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8461 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8462 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8463 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8464 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8465 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8466 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8467 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8468 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8469 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8470 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8472 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8473 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8474 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8475 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8476 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8477 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8478 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8479 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8480 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8481 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8484 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8485 c, opc->name, opc->args);
8489 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8490 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8492 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8493 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8494 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8495 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8497 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8498 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8500 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8501 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8503 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8504 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8505 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8506 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8507 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8508 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8509 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8510 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8511 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8512 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8513 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8514 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8515 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8516 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8517 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8518 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8519 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8521 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8522 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8523 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8524 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8526 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8527 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8528 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8529 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8530 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8531 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8532 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8533 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8534 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8537 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8538 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8539 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8540 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8541 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8544 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8545 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8546 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8547 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8548 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8549 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8550 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8551 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8552 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8553 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8554 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8555 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8556 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8557 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8558 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8559 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8560 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8561 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8563 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8564 c, opc->name, opc->args);
8568 if (used_bits != 0xffffffff)
8570 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8571 ~used_bits & 0xffffffff, opc->name, opc->args);
8577 /* UDI immediates. */
8585 static const struct mips_immed mips_immed[] = {
8586 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8587 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8588 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8589 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8593 /* Check whether an odd floating-point register is allowed. */
8595 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8597 const char *s = insn->name;
8599 if (insn->pinfo == INSN_MACRO)
8600 /* Let a macro pass, we'll catch it later when it is expanded. */
8603 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8605 /* Allow odd registers for single-precision ops. */
8606 switch (insn->pinfo & (FP_S | FP_D))
8610 return 1; /* both single precision - ok */
8612 return 0; /* both double precision - fail */
8617 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8618 s = strchr (insn->name, '.');
8620 s = s != NULL ? strchr (s + 1, '.') : NULL;
8621 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8624 /* Single-precision coprocessor loads and moves are OK too. */
8625 if ((insn->pinfo & FP_S)
8626 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8627 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8633 /* This routine assembles an instruction into its binary format. As a
8634 side effect, it sets one of the global variables imm_reloc or
8635 offset_reloc to the type of relocation to do if one of the operands
8636 is an address expression. */
8639 mips_ip (char *str, struct mips_cl_insn *ip)
8644 struct mips_opcode *insn;
8647 unsigned int lastregno;
8648 unsigned int lastpos = 0;
8649 unsigned int limlo, limhi;
8652 offsetT min_range, max_range;
8658 /* If the instruction contains a '.', we first try to match an instruction
8659 including the '.'. Then we try again without the '.'. */
8661 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8664 /* If we stopped on whitespace, then replace the whitespace with null for
8665 the call to hash_find. Save the character we replaced just in case we
8666 have to re-parse the instruction. */
8673 insn = (struct mips_opcode *) hash_find (op_hash, str);
8675 /* If we didn't find the instruction in the opcode table, try again, but
8676 this time with just the instruction up to, but not including the
8680 /* Restore the character we overwrite above (if any). */
8684 /* Scan up to the first '.' or whitespace. */
8686 *s != '\0' && *s != '.' && !ISSPACE (*s);
8690 /* If we did not find a '.', then we can quit now. */
8693 insn_error = _("Unrecognized opcode");
8697 /* Lookup the instruction in the hash table. */
8699 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8701 insn_error = _("Unrecognized opcode");
8711 gas_assert (strcmp (insn->name, str) == 0);
8713 ok = is_opcode_valid (insn);
8716 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8717 && strcmp (insn->name, insn[1].name) == 0)
8726 static char buf[100];
8728 _("opcode not supported on this processor: %s (%s)"),
8729 mips_cpu_info_from_arch (mips_opts.arch)->name,
8730 mips_cpu_info_from_isa (mips_opts.isa)->name);
8739 create_insn (ip, insn);
8742 lastregno = 0xffffffff;
8743 for (args = insn->args;; ++args)
8747 s += strspn (s, " \t");
8751 case '\0': /* end of args */
8756 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
8757 my_getExpression (&imm_expr, s);
8758 check_absolute_expr (ip, &imm_expr);
8759 if ((unsigned long) imm_expr.X_add_number != 1
8760 && (unsigned long) imm_expr.X_add_number != 3)
8762 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8763 (unsigned long) imm_expr.X_add_number);
8765 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8766 imm_expr.X_op = O_absent;
8770 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
8771 my_getExpression (&imm_expr, s);
8772 check_absolute_expr (ip, &imm_expr);
8773 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8775 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8776 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8778 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8779 imm_expr.X_op = O_absent;
8783 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
8784 my_getExpression (&imm_expr, s);
8785 check_absolute_expr (ip, &imm_expr);
8786 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8788 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8789 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8791 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8792 imm_expr.X_op = O_absent;
8796 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
8797 my_getExpression (&imm_expr, s);
8798 check_absolute_expr (ip, &imm_expr);
8799 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8801 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8802 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8804 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8805 imm_expr.X_op = O_absent;
8809 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
8810 my_getExpression (&imm_expr, s);
8811 check_absolute_expr (ip, &imm_expr);
8812 if (imm_expr.X_add_number & ~OP_MASK_RS)
8814 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8815 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8817 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8818 imm_expr.X_op = O_absent;
8822 case '7': /* Four DSP accumulators in bits 11,12. */
8823 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8824 s[3] >= '0' && s[3] <= '3')
8828 INSERT_OPERAND (DSPACC, *ip, regno);
8832 as_bad (_("Invalid dsp acc register"));
8835 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
8836 my_getExpression (&imm_expr, s);
8837 check_absolute_expr (ip, &imm_expr);
8838 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8840 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8842 (unsigned long) imm_expr.X_add_number);
8844 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8845 imm_expr.X_op = O_absent;
8849 case '9': /* Four DSP accumulators in bits 21,22. */
8850 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8851 s[3] >= '0' && s[3] <= '3')
8855 INSERT_OPERAND (DSPACC_S, *ip, regno);
8859 as_bad (_("Invalid dsp acc register"));
8862 case '0': /* DSP 6-bit signed immediate in bit 20. */
8863 my_getExpression (&imm_expr, s);
8864 check_absolute_expr (ip, &imm_expr);
8865 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8866 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8867 if (imm_expr.X_add_number < min_range ||
8868 imm_expr.X_add_number > max_range)
8870 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8871 (long) min_range, (long) max_range,
8872 (long) imm_expr.X_add_number);
8874 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8875 imm_expr.X_op = O_absent;
8879 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
8880 my_getExpression (&imm_expr, s);
8881 check_absolute_expr (ip, &imm_expr);
8882 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8884 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8886 (unsigned long) imm_expr.X_add_number);
8888 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8889 imm_expr.X_op = O_absent;
8893 case ':': /* DSP 7-bit signed immediate in bit 19. */
8894 my_getExpression (&imm_expr, s);
8895 check_absolute_expr (ip, &imm_expr);
8896 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8897 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8898 if (imm_expr.X_add_number < min_range ||
8899 imm_expr.X_add_number > max_range)
8901 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8902 (long) min_range, (long) max_range,
8903 (long) imm_expr.X_add_number);
8905 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8906 imm_expr.X_op = O_absent;
8910 case '@': /* DSP 10-bit signed immediate in bit 16. */
8911 my_getExpression (&imm_expr, s);
8912 check_absolute_expr (ip, &imm_expr);
8913 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8914 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8915 if (imm_expr.X_add_number < min_range ||
8916 imm_expr.X_add_number > max_range)
8918 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8919 (long) min_range, (long) max_range,
8920 (long) imm_expr.X_add_number);
8922 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8923 imm_expr.X_op = O_absent;
8927 case '!': /* MT usermode flag bit. */
8928 my_getExpression (&imm_expr, s);
8929 check_absolute_expr (ip, &imm_expr);
8930 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8931 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8932 (unsigned long) imm_expr.X_add_number);
8933 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
8934 imm_expr.X_op = O_absent;
8938 case '$': /* MT load high flag bit. */
8939 my_getExpression (&imm_expr, s);
8940 check_absolute_expr (ip, &imm_expr);
8941 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
8942 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8943 (unsigned long) imm_expr.X_add_number);
8944 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
8945 imm_expr.X_op = O_absent;
8949 case '*': /* Four DSP accumulators in bits 18,19. */
8950 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8951 s[3] >= '0' && s[3] <= '3')
8955 INSERT_OPERAND (MTACC_T, *ip, regno);
8959 as_bad (_("Invalid dsp/smartmips acc register"));
8962 case '&': /* Four DSP accumulators in bits 13,14. */
8963 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8964 s[3] >= '0' && s[3] <= '3')
8968 INSERT_OPERAND (MTACC_D, *ip, regno);
8972 as_bad (_("Invalid dsp/smartmips acc register"));
8984 INSERT_OPERAND (RS, *ip, lastregno);
8988 INSERT_OPERAND (RT, *ip, lastregno);
8992 INSERT_OPERAND (FT, *ip, lastregno);
8996 INSERT_OPERAND (FS, *ip, lastregno);
9002 /* Handle optional base register.
9003 Either the base register is omitted or
9004 we must have a left paren. */
9005 /* This is dependent on the next operand specifier
9006 is a base register specification. */
9007 gas_assert (args[1] == 'b');
9011 case ')': /* These must match exactly. */
9018 case '+': /* Opcode extension character. */
9021 case '1': /* UDI immediates. */
9026 const struct mips_immed *imm = mips_immed;
9028 while (imm->type && imm->type != *args)
9032 my_getExpression (&imm_expr, s);
9033 check_absolute_expr (ip, &imm_expr);
9034 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9036 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9037 imm->desc ? imm->desc : ip->insn_mo->name,
9038 (unsigned long) imm_expr.X_add_number,
9039 (unsigned long) imm_expr.X_add_number);
9040 imm_expr.X_add_number &= imm->mask;
9042 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9044 imm_expr.X_op = O_absent;
9049 case 'A': /* ins/ext position, becomes LSB. */
9058 my_getExpression (&imm_expr, s);
9059 check_absolute_expr (ip, &imm_expr);
9060 if ((unsigned long) imm_expr.X_add_number < limlo
9061 || (unsigned long) imm_expr.X_add_number > limhi)
9063 as_bad (_("Improper position (%lu)"),
9064 (unsigned long) imm_expr.X_add_number);
9065 imm_expr.X_add_number = limlo;
9067 lastpos = imm_expr.X_add_number;
9068 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9069 imm_expr.X_op = O_absent;
9073 case 'B': /* ins size, becomes MSB. */
9082 my_getExpression (&imm_expr, s);
9083 check_absolute_expr (ip, &imm_expr);
9084 /* Check for negative input so that small negative numbers
9085 will not succeed incorrectly. The checks against
9086 (pos+size) transitively check "size" itself,
9087 assuming that "pos" is reasonable. */
9088 if ((long) imm_expr.X_add_number < 0
9089 || ((unsigned long) imm_expr.X_add_number
9091 || ((unsigned long) imm_expr.X_add_number
9094 as_bad (_("Improper insert size (%lu, position %lu)"),
9095 (unsigned long) imm_expr.X_add_number,
9096 (unsigned long) lastpos);
9097 imm_expr.X_add_number = limlo - lastpos;
9099 INSERT_OPERAND (INSMSB, *ip,
9100 lastpos + imm_expr.X_add_number - 1);
9101 imm_expr.X_op = O_absent;
9105 case 'C': /* ext size, becomes MSBD. */
9118 my_getExpression (&imm_expr, s);
9119 check_absolute_expr (ip, &imm_expr);
9120 /* Check for negative input so that small negative numbers
9121 will not succeed incorrectly. The checks against
9122 (pos+size) transitively check "size" itself,
9123 assuming that "pos" is reasonable. */
9124 if ((long) imm_expr.X_add_number < 0
9125 || ((unsigned long) imm_expr.X_add_number
9127 || ((unsigned long) imm_expr.X_add_number
9130 as_bad (_("Improper extract size (%lu, position %lu)"),
9131 (unsigned long) imm_expr.X_add_number,
9132 (unsigned long) lastpos);
9133 imm_expr.X_add_number = limlo - lastpos;
9135 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9136 imm_expr.X_op = O_absent;
9141 /* +D is for disassembly only; never match. */
9145 /* "+I" is like "I", except that imm2_expr is used. */
9146 my_getExpression (&imm2_expr, s);
9147 if (imm2_expr.X_op != O_big
9148 && imm2_expr.X_op != O_constant)
9149 insn_error = _("absolute expression required");
9150 if (HAVE_32BIT_GPRS)
9151 normalize_constant_expr (&imm2_expr);
9155 case 'T': /* Coprocessor register. */
9156 /* +T is for disassembly only; never match. */
9159 case 't': /* Coprocessor register number. */
9160 if (s[0] == '$' && ISDIGIT (s[1]))
9170 while (ISDIGIT (*s));
9172 as_bad (_("Invalid register number (%d)"), regno);
9175 INSERT_OPERAND (RT, *ip, regno);
9180 as_bad (_("Invalid coprocessor 0 register number"));
9184 /* bbit[01] and bbit[01]32 bit index. Give error if index
9185 is not in the valid range. */
9186 my_getExpression (&imm_expr, s);
9187 check_absolute_expr (ip, &imm_expr);
9188 if ((unsigned) imm_expr.X_add_number > 31)
9190 as_bad (_("Improper bit index (%lu)"),
9191 (unsigned long) imm_expr.X_add_number);
9192 imm_expr.X_add_number = 0;
9194 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9195 imm_expr.X_op = O_absent;
9200 /* bbit[01] bit index when bbit is used but we generate
9201 bbit[01]32 because the index is over 32. Move to the
9202 next candidate if index is not in the valid range. */
9203 my_getExpression (&imm_expr, s);
9204 check_absolute_expr (ip, &imm_expr);
9205 if ((unsigned) imm_expr.X_add_number < 32
9206 || (unsigned) imm_expr.X_add_number > 63)
9208 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9209 imm_expr.X_op = O_absent;
9214 /* cins, cins32, exts and exts32 position field. Give error
9215 if it's not in the valid range. */
9216 my_getExpression (&imm_expr, s);
9217 check_absolute_expr (ip, &imm_expr);
9218 if ((unsigned) imm_expr.X_add_number > 31)
9220 as_bad (_("Improper position (%lu)"),
9221 (unsigned long) imm_expr.X_add_number);
9222 imm_expr.X_add_number = 0;
9224 /* Make the pos explicit to simplify +S. */
9225 lastpos = imm_expr.X_add_number + 32;
9226 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9227 imm_expr.X_op = O_absent;
9232 /* cins, cins32, exts and exts32 position field. Move to
9233 the next candidate if it's not in the valid range. */
9234 my_getExpression (&imm_expr, s);
9235 check_absolute_expr (ip, &imm_expr);
9236 if ((unsigned) imm_expr.X_add_number < 32
9237 || (unsigned) imm_expr.X_add_number > 63)
9239 lastpos = imm_expr.X_add_number;
9240 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9241 imm_expr.X_op = O_absent;
9246 /* cins and exts length-minus-one field. */
9247 my_getExpression (&imm_expr, s);
9248 check_absolute_expr (ip, &imm_expr);
9249 if ((unsigned long) imm_expr.X_add_number > 31)
9251 as_bad (_("Improper size (%lu)"),
9252 (unsigned long) imm_expr.X_add_number);
9253 imm_expr.X_add_number = 0;
9255 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9256 imm_expr.X_op = O_absent;
9261 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9262 length-minus-one field. */
9263 my_getExpression (&imm_expr, s);
9264 check_absolute_expr (ip, &imm_expr);
9265 if ((long) imm_expr.X_add_number < 0
9266 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9268 as_bad (_("Improper size (%lu)"),
9269 (unsigned long) imm_expr.X_add_number);
9270 imm_expr.X_add_number = 0;
9272 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9273 imm_expr.X_op = O_absent;
9278 /* seqi/snei immediate field. */
9279 my_getExpression (&imm_expr, s);
9280 check_absolute_expr (ip, &imm_expr);
9281 if ((long) imm_expr.X_add_number < -512
9282 || (long) imm_expr.X_add_number >= 512)
9284 as_bad (_("Improper immediate (%ld)"),
9285 (long) imm_expr.X_add_number);
9286 imm_expr.X_add_number = 0;
9288 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9289 imm_expr.X_op = O_absent;
9294 as_bad (_("Internal error: bad mips opcode "
9295 "(unknown extension operand type `+%c'): %s %s"),
9296 *args, insn->name, insn->args);
9297 /* Further processing is fruitless. */
9302 case '<': /* must be at least one digit */
9304 * According to the manual, if the shift amount is greater
9305 * than 31 or less than 0, then the shift amount should be
9306 * mod 32. In reality the mips assembler issues an error.
9307 * We issue a warning and mask out all but the low 5 bits.
9309 my_getExpression (&imm_expr, s);
9310 check_absolute_expr (ip, &imm_expr);
9311 if ((unsigned long) imm_expr.X_add_number > 31)
9312 as_warn (_("Improper shift amount (%lu)"),
9313 (unsigned long) imm_expr.X_add_number);
9314 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9315 imm_expr.X_op = O_absent;
9319 case '>': /* shift amount minus 32 */
9320 my_getExpression (&imm_expr, s);
9321 check_absolute_expr (ip, &imm_expr);
9322 if ((unsigned long) imm_expr.X_add_number < 32
9323 || (unsigned long) imm_expr.X_add_number > 63)
9325 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9326 imm_expr.X_op = O_absent;
9330 case 'k': /* CACHE code. */
9331 case 'h': /* PREFX code. */
9332 case '1': /* SYNC type. */
9333 my_getExpression (&imm_expr, s);
9334 check_absolute_expr (ip, &imm_expr);
9335 if ((unsigned long) imm_expr.X_add_number > 31)
9336 as_warn (_("Invalid value for `%s' (%lu)"),
9338 (unsigned long) imm_expr.X_add_number);
9341 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9342 switch (imm_expr.X_add_number)
9351 case 31: /* These are ok. */
9354 default: /* The rest must be changed to 28. */
9355 imm_expr.X_add_number = 28;
9358 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9360 else if (*args == 'h')
9361 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9363 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9364 imm_expr.X_op = O_absent;
9368 case 'c': /* BREAK code. */
9369 my_getExpression (&imm_expr, s);
9370 check_absolute_expr (ip, &imm_expr);
9371 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9372 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9374 (unsigned long) imm_expr.X_add_number);
9375 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9376 imm_expr.X_op = O_absent;
9380 case 'q': /* Lower BREAK code. */
9381 my_getExpression (&imm_expr, s);
9382 check_absolute_expr (ip, &imm_expr);
9383 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9384 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9386 (unsigned long) imm_expr.X_add_number);
9387 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9388 imm_expr.X_op = O_absent;
9392 case 'B': /* 20-bit SYSCALL/BREAK code. */
9393 my_getExpression (&imm_expr, s);
9394 check_absolute_expr (ip, &imm_expr);
9395 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9396 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9398 (unsigned long) imm_expr.X_add_number);
9399 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9400 imm_expr.X_op = O_absent;
9404 case 'C': /* Coprocessor code. */
9405 my_getExpression (&imm_expr, s);
9406 check_absolute_expr (ip, &imm_expr);
9407 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9409 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9410 (unsigned long) imm_expr.X_add_number);
9411 imm_expr.X_add_number &= OP_MASK_COPZ;
9413 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9414 imm_expr.X_op = O_absent;
9418 case 'J': /* 19-bit WAIT code. */
9419 my_getExpression (&imm_expr, s);
9420 check_absolute_expr (ip, &imm_expr);
9421 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9423 as_warn (_("Illegal 19-bit code (%lu)"),
9424 (unsigned long) imm_expr.X_add_number);
9425 imm_expr.X_add_number &= OP_MASK_CODE19;
9427 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9428 imm_expr.X_op = O_absent;
9432 case 'P': /* Performance register. */
9433 my_getExpression (&imm_expr, s);
9434 check_absolute_expr (ip, &imm_expr);
9435 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9436 as_warn (_("Invalid performance register (%lu)"),
9437 (unsigned long) imm_expr.X_add_number);
9438 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9439 imm_expr.X_op = O_absent;
9443 case 'G': /* Coprocessor destination register. */
9444 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9445 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9447 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9448 INSERT_OPERAND (RD, *ip, regno);
9457 case 'b': /* Base register. */
9458 case 'd': /* Destination register. */
9459 case 's': /* Source register. */
9460 case 't': /* Target register. */
9461 case 'r': /* Both target and source. */
9462 case 'v': /* Both dest and source. */
9463 case 'w': /* Both dest and target. */
9464 case 'E': /* Coprocessor target register. */
9465 case 'K': /* RDHWR destination register. */
9466 case 'x': /* Ignore register name. */
9467 case 'z': /* Must be zero register. */
9468 case 'U': /* Destination register (CLO/CLZ). */
9469 case 'g': /* Coprocessor destination register. */
9471 if (*args == 'E' || *args == 'K')
9472 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9475 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9476 if (regno == AT && mips_opts.at)
9478 if (mips_opts.at == ATREG)
9479 as_warn (_("Used $at without \".set noat\""));
9481 as_warn (_("Used $%u with \".set at=$%u\""),
9482 regno, mips_opts.at);
9492 if (c == 'r' || c == 'v' || c == 'w')
9499 /* 'z' only matches $0. */
9500 if (c == 'z' && regno != 0)
9503 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9505 if (regno == lastregno)
9508 = _("Source and destination must be different");
9511 if (regno == 31 && lastregno == 0xffffffff)
9514 = _("A destination register must be supplied");
9518 /* Now that we have assembled one operand, we use the args
9519 string to figure out where it goes in the instruction. */
9526 INSERT_OPERAND (RS, *ip, regno);
9531 INSERT_OPERAND (RD, *ip, regno);
9534 INSERT_OPERAND (RD, *ip, regno);
9535 INSERT_OPERAND (RT, *ip, regno);
9540 INSERT_OPERAND (RT, *ip, regno);
9543 /* This case exists because on the r3000 trunc
9544 expands into a macro which requires a gp
9545 register. On the r6000 or r4000 it is
9546 assembled into a single instruction which
9547 ignores the register. Thus the insn version
9548 is MIPS_ISA2 and uses 'x', and the macro
9549 version is MIPS_ISA1 and uses 't'. */
9552 /* This case is for the div instruction, which
9553 acts differently if the destination argument
9554 is $0. This only matches $0, and is checked
9555 outside the switch. */
9565 INSERT_OPERAND (RS, *ip, lastregno);
9568 INSERT_OPERAND (RT, *ip, lastregno);
9573 case 'O': /* MDMX alignment immediate constant. */
9574 my_getExpression (&imm_expr, s);
9575 check_absolute_expr (ip, &imm_expr);
9576 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9577 as_warn (_("Improper align amount (%ld), using low bits"),
9578 (long) imm_expr.X_add_number);
9579 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9580 imm_expr.X_op = O_absent;
9584 case 'Q': /* MDMX vector, element sel, or const. */
9587 /* MDMX Immediate. */
9588 my_getExpression (&imm_expr, s);
9589 check_absolute_expr (ip, &imm_expr);
9590 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9591 as_warn (_("Invalid MDMX Immediate (%ld)"),
9592 (long) imm_expr.X_add_number);
9593 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9594 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9595 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9597 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9598 imm_expr.X_op = O_absent;
9602 /* Not MDMX Immediate. Fall through. */
9603 case 'X': /* MDMX destination register. */
9604 case 'Y': /* MDMX source register. */
9605 case 'Z': /* MDMX target register. */
9607 case 'D': /* Floating point destination register. */
9608 case 'S': /* Floating point source register. */
9609 case 'T': /* Floating point target register. */
9610 case 'R': /* Floating point source register. */
9615 || (mips_opts.ase_mdmx
9616 && (ip->insn_mo->pinfo & FP_D)
9617 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9618 | INSN_COPROC_MEMORY_DELAY
9619 | INSN_LOAD_COPROC_DELAY
9620 | INSN_LOAD_MEMORY_DELAY
9621 | INSN_STORE_MEMORY))))
9624 if (reg_lookup (&s, rtype, ®no))
9626 if ((regno & 1) != 0
9628 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9629 as_warn (_("Float register should be even, was %d"),
9637 if (c == 'V' || c == 'W')
9648 INSERT_OPERAND (FD, *ip, regno);
9653 INSERT_OPERAND (FS, *ip, regno);
9656 /* This is like 'Z', but also needs to fix the MDMX
9657 vector/scalar select bits. Note that the
9658 scalar immediate case is handled above. */
9661 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9662 int max_el = (is_qh ? 3 : 7);
9664 my_getExpression(&imm_expr, s);
9665 check_absolute_expr (ip, &imm_expr);
9667 if (imm_expr.X_add_number > max_el)
9668 as_bad (_("Bad element selector %ld"),
9669 (long) imm_expr.X_add_number);
9670 imm_expr.X_add_number &= max_el;
9671 ip->insn_opcode |= (imm_expr.X_add_number
9674 imm_expr.X_op = O_absent;
9676 as_warn (_("Expecting ']' found '%s'"), s);
9682 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9683 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9686 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9693 INSERT_OPERAND (FT, *ip, regno);
9696 INSERT_OPERAND (FR, *ip, regno);
9706 INSERT_OPERAND (FS, *ip, lastregno);
9709 INSERT_OPERAND (FT, *ip, lastregno);
9715 my_getExpression (&imm_expr, s);
9716 if (imm_expr.X_op != O_big
9717 && imm_expr.X_op != O_constant)
9718 insn_error = _("absolute expression required");
9719 if (HAVE_32BIT_GPRS)
9720 normalize_constant_expr (&imm_expr);
9725 my_getExpression (&offset_expr, s);
9726 normalize_address_expr (&offset_expr);
9727 *imm_reloc = BFD_RELOC_32;
9740 unsigned char temp[8];
9742 unsigned int length;
9747 /* These only appear as the last operand in an
9748 instruction, and every instruction that accepts
9749 them in any variant accepts them in all variants.
9750 This means we don't have to worry about backing out
9751 any changes if the instruction does not match.
9753 The difference between them is the size of the
9754 floating point constant and where it goes. For 'F'
9755 and 'L' the constant is 64 bits; for 'f' and 'l' it
9756 is 32 bits. Where the constant is placed is based
9757 on how the MIPS assembler does things:
9760 f -- immediate value
9763 The .lit4 and .lit8 sections are only used if
9764 permitted by the -G argument.
9766 The code below needs to know whether the target register
9767 is 32 or 64 bits wide. It relies on the fact 'f' and
9768 'F' are used with GPR-based instructions and 'l' and
9769 'L' are used with FPR-based instructions. */
9771 f64 = *args == 'F' || *args == 'L';
9772 using_gprs = *args == 'F' || *args == 'f';
9774 save_in = input_line_pointer;
9775 input_line_pointer = s;
9776 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9778 s = input_line_pointer;
9779 input_line_pointer = save_in;
9780 if (err != NULL && *err != '\0')
9782 as_bad (_("Bad floating point constant: %s"), err);
9783 memset (temp, '\0', sizeof temp);
9784 length = f64 ? 8 : 4;
9787 gas_assert (length == (unsigned) (f64 ? 8 : 4));
9791 && (g_switch_value < 4
9792 || (temp[0] == 0 && temp[1] == 0)
9793 || (temp[2] == 0 && temp[3] == 0))))
9795 imm_expr.X_op = O_constant;
9796 if (!target_big_endian)
9797 imm_expr.X_add_number = bfd_getl32 (temp);
9799 imm_expr.X_add_number = bfd_getb32 (temp);
9802 && !mips_disable_float_construction
9803 /* Constants can only be constructed in GPRs and
9804 copied to FPRs if the GPRs are at least as wide
9805 as the FPRs. Force the constant into memory if
9806 we are using 64-bit FPRs but the GPRs are only
9809 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9810 && ((temp[0] == 0 && temp[1] == 0)
9811 || (temp[2] == 0 && temp[3] == 0))
9812 && ((temp[4] == 0 && temp[5] == 0)
9813 || (temp[6] == 0 && temp[7] == 0)))
9815 /* The value is simple enough to load with a couple of
9816 instructions. If using 32-bit registers, set
9817 imm_expr to the high order 32 bits and offset_expr to
9818 the low order 32 bits. Otherwise, set imm_expr to
9819 the entire 64 bit constant. */
9820 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9822 imm_expr.X_op = O_constant;
9823 offset_expr.X_op = O_constant;
9824 if (!target_big_endian)
9826 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9827 offset_expr.X_add_number = bfd_getl32 (temp);
9831 imm_expr.X_add_number = bfd_getb32 (temp);
9832 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9834 if (offset_expr.X_add_number == 0)
9835 offset_expr.X_op = O_absent;
9837 else if (sizeof (imm_expr.X_add_number) > 4)
9839 imm_expr.X_op = O_constant;
9840 if (!target_big_endian)
9841 imm_expr.X_add_number = bfd_getl64 (temp);
9843 imm_expr.X_add_number = bfd_getb64 (temp);
9847 imm_expr.X_op = O_big;
9848 imm_expr.X_add_number = 4;
9849 if (!target_big_endian)
9851 generic_bignum[0] = bfd_getl16 (temp);
9852 generic_bignum[1] = bfd_getl16 (temp + 2);
9853 generic_bignum[2] = bfd_getl16 (temp + 4);
9854 generic_bignum[3] = bfd_getl16 (temp + 6);
9858 generic_bignum[0] = bfd_getb16 (temp + 6);
9859 generic_bignum[1] = bfd_getb16 (temp + 4);
9860 generic_bignum[2] = bfd_getb16 (temp + 2);
9861 generic_bignum[3] = bfd_getb16 (temp);
9867 const char *newname;
9870 /* Switch to the right section. */
9872 subseg = now_subseg;
9875 default: /* unused default case avoids warnings. */
9877 newname = RDATA_SECTION_NAME;
9878 if (g_switch_value >= 8)
9882 newname = RDATA_SECTION_NAME;
9885 gas_assert (g_switch_value >= 4);
9889 new_seg = subseg_new (newname, (subsegT) 0);
9891 bfd_set_section_flags (stdoutput, new_seg,
9896 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9897 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
9898 record_alignment (new_seg, 4);
9900 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9902 as_bad (_("Can't use floating point insn in this section"));
9904 /* Set the argument to the current address in the
9906 offset_expr.X_op = O_symbol;
9907 offset_expr.X_add_symbol = symbol_temp_new_now ();
9908 offset_expr.X_add_number = 0;
9910 /* Put the floating point number into the section. */
9911 p = frag_more ((int) length);
9912 memcpy (p, temp, length);
9914 /* Switch back to the original section. */
9915 subseg_set (seg, subseg);
9920 case 'i': /* 16-bit unsigned immediate. */
9921 case 'j': /* 16-bit signed immediate. */
9922 *imm_reloc = BFD_RELOC_LO16;
9923 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9926 offsetT minval, maxval;
9928 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9929 && strcmp (insn->name, insn[1].name) == 0);
9931 /* If the expression was written as an unsigned number,
9932 only treat it as signed if there are no more
9936 && sizeof (imm_expr.X_add_number) <= 4
9937 && imm_expr.X_op == O_constant
9938 && imm_expr.X_add_number < 0
9939 && imm_expr.X_unsigned
9943 /* For compatibility with older assemblers, we accept
9944 0x8000-0xffff as signed 16-bit numbers when only
9945 signed numbers are allowed. */
9947 minval = 0, maxval = 0xffff;
9949 minval = -0x8000, maxval = 0x7fff;
9951 minval = -0x8000, maxval = 0xffff;
9953 if (imm_expr.X_op != O_constant
9954 || imm_expr.X_add_number < minval
9955 || imm_expr.X_add_number > maxval)
9959 if (imm_expr.X_op == O_constant
9960 || imm_expr.X_op == O_big)
9961 as_bad (_("Expression out of range"));
9967 case 'o': /* 16-bit offset. */
9968 offset_reloc[0] = BFD_RELOC_LO16;
9969 offset_reloc[1] = BFD_RELOC_UNUSED;
9970 offset_reloc[2] = BFD_RELOC_UNUSED;
9972 /* Check whether there is only a single bracketed expression
9973 left. If so, it must be the base register and the
9974 constant must be zero. */
9975 offset_reloc[0] = BFD_RELOC_LO16;
9976 offset_reloc[1] = BFD_RELOC_UNUSED;
9977 offset_reloc[2] = BFD_RELOC_UNUSED;
9978 if (*s == '(' && strchr (s + 1, '(') == 0)
9980 offset_expr.X_op = O_constant;
9981 offset_expr.X_add_number = 0;
9985 /* If this value won't fit into a 16 bit offset, then go
9986 find a macro that will generate the 32 bit offset
9988 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9989 && (offset_expr.X_op != O_constant
9990 || offset_expr.X_add_number >= 0x8000
9991 || offset_expr.X_add_number < -0x8000))
9997 case 'p': /* PC-relative offset. */
9998 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9999 my_getExpression (&offset_expr, s);
10003 case 'u': /* Upper 16 bits. */
10004 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10005 && imm_expr.X_op == O_constant
10006 && (imm_expr.X_add_number < 0
10007 || imm_expr.X_add_number >= 0x10000))
10008 as_bad (_("lui expression (%lu) not in range 0..65535"),
10009 (unsigned long) imm_expr.X_add_number);
10013 case 'a': /* 26-bit address. */
10014 my_getExpression (&offset_expr, s);
10016 *offset_reloc = BFD_RELOC_MIPS_JMP;
10019 case 'N': /* 3-bit branch condition code. */
10020 case 'M': /* 3-bit compare condition code. */
10022 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10023 rtype |= RTYPE_FCC;
10024 if (!reg_lookup (&s, rtype, ®no))
10026 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10027 || strcmp (str + strlen (str) - 5, "any2f") == 0
10028 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10029 && (regno & 1) != 0)
10030 as_warn (_("Condition code register should be even for %s, "
10033 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10034 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10035 && (regno & 3) != 0)
10036 as_warn (_("Condition code register should be 0 or 4 for %s, "
10040 INSERT_OPERAND (BCC, *ip, regno);
10042 INSERT_OPERAND (CCC, *ip, regno);
10046 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10057 while (ISDIGIT (*s));
10060 c = 8; /* Invalid sel value. */
10063 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10064 ip->insn_opcode |= c;
10068 /* Must be at least one digit. */
10069 my_getExpression (&imm_expr, s);
10070 check_absolute_expr (ip, &imm_expr);
10072 if ((unsigned long) imm_expr.X_add_number
10073 > (unsigned long) OP_MASK_VECBYTE)
10075 as_bad (_("bad byte vector index (%ld)"),
10076 (long) imm_expr.X_add_number);
10077 imm_expr.X_add_number = 0;
10080 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10081 imm_expr.X_op = O_absent;
10086 my_getExpression (&imm_expr, s);
10087 check_absolute_expr (ip, &imm_expr);
10089 if ((unsigned long) imm_expr.X_add_number
10090 > (unsigned long) OP_MASK_VECALIGN)
10092 as_bad (_("bad byte vector index (%ld)"),
10093 (long) imm_expr.X_add_number);
10094 imm_expr.X_add_number = 0;
10097 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10098 imm_expr.X_op = O_absent;
10103 as_bad (_("Bad char = '%c'\n"), *args);
10108 /* Args don't match. */
10109 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10110 !strcmp (insn->name, insn[1].name))
10114 insn_error = _("Illegal operands");
10118 *(--argsStart) = save_c;
10119 insn_error = _("Illegal operands");
10124 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10126 /* This routine assembles an instruction into its binary format when
10127 assembling for the mips16. As a side effect, it sets one of the
10128 global variables imm_reloc or offset_reloc to the type of
10129 relocation to do if one of the operands is an address expression.
10130 It also sets mips16_small and mips16_ext if the user explicitly
10131 requested a small or extended instruction. */
10134 mips16_ip (char *str, struct mips_cl_insn *ip)
10138 struct mips_opcode *insn;
10140 unsigned int regno;
10141 unsigned int lastregno = 0;
10147 mips16_small = FALSE;
10148 mips16_ext = FALSE;
10150 for (s = str; ISLOWER (*s); ++s)
10162 if (s[1] == 't' && s[2] == ' ')
10165 mips16_small = TRUE;
10169 else if (s[1] == 'e' && s[2] == ' ')
10176 /* Fall through. */
10178 insn_error = _("unknown opcode");
10182 if (mips_opts.noautoextend && ! mips16_ext)
10183 mips16_small = TRUE;
10185 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10187 insn_error = _("unrecognized opcode");
10196 gas_assert (strcmp (insn->name, str) == 0);
10198 ok = is_opcode_valid_16 (insn);
10201 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10202 && strcmp (insn->name, insn[1].name) == 0)
10211 static char buf[100];
10213 _("opcode not supported on this processor: %s (%s)"),
10214 mips_cpu_info_from_arch (mips_opts.arch)->name,
10215 mips_cpu_info_from_isa (mips_opts.isa)->name);
10222 create_insn (ip, insn);
10223 imm_expr.X_op = O_absent;
10224 imm_reloc[0] = BFD_RELOC_UNUSED;
10225 imm_reloc[1] = BFD_RELOC_UNUSED;
10226 imm_reloc[2] = BFD_RELOC_UNUSED;
10227 imm2_expr.X_op = O_absent;
10228 offset_expr.X_op = O_absent;
10229 offset_reloc[0] = BFD_RELOC_UNUSED;
10230 offset_reloc[1] = BFD_RELOC_UNUSED;
10231 offset_reloc[2] = BFD_RELOC_UNUSED;
10232 for (args = insn->args; 1; ++args)
10239 /* In this switch statement we call break if we did not find
10240 a match, continue if we did find a match, or return if we
10249 /* Stuff the immediate value in now, if we can. */
10250 if (imm_expr.X_op == O_constant
10251 && *imm_reloc > BFD_RELOC_UNUSED
10252 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10253 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10254 && insn->pinfo != INSN_MACRO)
10258 switch (*offset_reloc)
10260 case BFD_RELOC_MIPS16_HI16_S:
10261 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10264 case BFD_RELOC_MIPS16_HI16:
10265 tmp = imm_expr.X_add_number >> 16;
10268 case BFD_RELOC_MIPS16_LO16:
10269 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10273 case BFD_RELOC_UNUSED:
10274 tmp = imm_expr.X_add_number;
10280 *offset_reloc = BFD_RELOC_UNUSED;
10282 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10283 tmp, TRUE, mips16_small,
10284 mips16_ext, &ip->insn_opcode,
10285 &ip->use_extend, &ip->extend);
10286 imm_expr.X_op = O_absent;
10287 *imm_reloc = BFD_RELOC_UNUSED;
10301 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10304 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10320 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10322 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10326 /* Fall through. */
10337 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10339 if (c == 'v' || c == 'w')
10342 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10344 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10355 if (c == 'v' || c == 'w')
10357 regno = mips16_to_32_reg_map[lastregno];
10371 regno = mips32_to_16_reg_map[regno];
10376 regno = ILLEGAL_REG;
10381 regno = ILLEGAL_REG;
10386 regno = ILLEGAL_REG;
10391 if (regno == AT && mips_opts.at)
10393 if (mips_opts.at == ATREG)
10394 as_warn (_("used $at without \".set noat\""));
10396 as_warn (_("used $%u with \".set at=$%u\""),
10397 regno, mips_opts.at);
10405 if (regno == ILLEGAL_REG)
10412 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10416 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10419 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10422 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10428 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10431 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10432 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10442 if (strncmp (s, "$pc", 3) == 0)
10459 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10462 if (imm_expr.X_op != O_constant)
10465 ip->use_extend = TRUE;
10470 /* We need to relax this instruction. */
10471 *offset_reloc = *imm_reloc;
10472 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10477 *imm_reloc = BFD_RELOC_UNUSED;
10478 /* Fall through. */
10485 my_getExpression (&imm_expr, s);
10486 if (imm_expr.X_op == O_register)
10488 /* What we thought was an expression turned out to
10491 if (s[0] == '(' && args[1] == '(')
10493 /* It looks like the expression was omitted
10494 before a register indirection, which means
10495 that the expression is implicitly zero. We
10496 still set up imm_expr, so that we handle
10497 explicit extensions correctly. */
10498 imm_expr.X_op = O_constant;
10499 imm_expr.X_add_number = 0;
10500 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10507 /* We need to relax this instruction. */
10508 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10517 /* We use offset_reloc rather than imm_reloc for the PC
10518 relative operands. This lets macros with both
10519 immediate and address operands work correctly. */
10520 my_getExpression (&offset_expr, s);
10522 if (offset_expr.X_op == O_register)
10525 /* We need to relax this instruction. */
10526 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10530 case '6': /* break code */
10531 my_getExpression (&imm_expr, s);
10532 check_absolute_expr (ip, &imm_expr);
10533 if ((unsigned long) imm_expr.X_add_number > 63)
10534 as_warn (_("Invalid value for `%s' (%lu)"),
10536 (unsigned long) imm_expr.X_add_number);
10537 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10538 imm_expr.X_op = O_absent;
10542 case 'a': /* 26 bit address */
10543 my_getExpression (&offset_expr, s);
10545 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10546 ip->insn_opcode <<= 16;
10549 case 'l': /* register list for entry macro */
10550 case 'L': /* register list for exit macro */
10560 unsigned int freg, reg1, reg2;
10562 while (*s == ' ' || *s == ',')
10564 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10566 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10570 as_bad (_("can't parse register list"));
10580 if (!reg_lookup (&s, freg ? RTYPE_FPU
10581 : (RTYPE_GP | RTYPE_NUM), ®2))
10583 as_bad (_("invalid register list"));
10587 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10589 mask &= ~ (7 << 3);
10592 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10594 mask &= ~ (7 << 3);
10597 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10598 mask |= (reg2 - 3) << 3;
10599 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10600 mask |= (reg2 - 15) << 1;
10601 else if (reg1 == RA && reg2 == RA)
10605 as_bad (_("invalid register list"));
10609 /* The mask is filled in in the opcode table for the
10610 benefit of the disassembler. We remove it before
10611 applying the actual mask. */
10612 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10613 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10617 case 'm': /* Register list for save insn. */
10618 case 'M': /* Register list for restore insn. */
10621 int framesz = 0, seen_framesz = 0;
10622 int nargs = 0, statics = 0, sregs = 0;
10626 unsigned int reg1, reg2;
10628 SKIP_SPACE_TABS (s);
10631 SKIP_SPACE_TABS (s);
10633 my_getExpression (&imm_expr, s);
10634 if (imm_expr.X_op == O_constant)
10636 /* Handle the frame size. */
10639 as_bad (_("more than one frame size in list"));
10643 framesz = imm_expr.X_add_number;
10644 imm_expr.X_op = O_absent;
10649 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10651 as_bad (_("can't parse register list"));
10663 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10666 as_bad (_("can't parse register list"));
10671 while (reg1 <= reg2)
10673 if (reg1 >= 4 && reg1 <= 7)
10677 nargs |= 1 << (reg1 - 4);
10679 /* statics $a0-$a3 */
10680 statics |= 1 << (reg1 - 4);
10682 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10685 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10687 else if (reg1 == 31)
10689 /* Add $ra to insn. */
10694 as_bad (_("unexpected register in list"));
10702 /* Encode args/statics combination. */
10703 if (nargs & statics)
10704 as_bad (_("arg/static registers overlap"));
10705 else if (nargs == 0xf)
10706 /* All $a0-$a3 are args. */
10707 opcode |= MIPS16_ALL_ARGS << 16;
10708 else if (statics == 0xf)
10709 /* All $a0-$a3 are statics. */
10710 opcode |= MIPS16_ALL_STATICS << 16;
10713 int narg = 0, nstat = 0;
10715 /* Count arg registers. */
10716 while (nargs & 0x1)
10722 as_bad (_("invalid arg register list"));
10724 /* Count static registers. */
10725 while (statics & 0x8)
10727 statics = (statics << 1) & 0xf;
10731 as_bad (_("invalid static register list"));
10733 /* Encode args/statics. */
10734 opcode |= ((narg << 2) | nstat) << 16;
10737 /* Encode $s0/$s1. */
10738 if (sregs & (1 << 0)) /* $s0 */
10740 if (sregs & (1 << 1)) /* $s1 */
10746 /* Count regs $s2-$s8. */
10754 as_bad (_("invalid static register list"));
10755 /* Encode $s2-$s8. */
10756 opcode |= nsreg << 24;
10759 /* Encode frame size. */
10761 as_bad (_("missing frame size"));
10762 else if ((framesz & 7) != 0 || framesz < 0
10763 || framesz > 0xff * 8)
10764 as_bad (_("invalid frame size"));
10765 else if (framesz != 128 || (opcode >> 16) != 0)
10768 opcode |= (((framesz & 0xf0) << 16)
10769 | (framesz & 0x0f));
10772 /* Finally build the instruction. */
10773 if ((opcode >> 16) != 0 || framesz == 0)
10775 ip->use_extend = TRUE;
10776 ip->extend = opcode >> 16;
10778 ip->insn_opcode |= opcode & 0x7f;
10782 case 'e': /* extend code */
10783 my_getExpression (&imm_expr, s);
10784 check_absolute_expr (ip, &imm_expr);
10785 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10787 as_warn (_("Invalid value for `%s' (%lu)"),
10789 (unsigned long) imm_expr.X_add_number);
10790 imm_expr.X_add_number &= 0x7ff;
10792 ip->insn_opcode |= imm_expr.X_add_number;
10793 imm_expr.X_op = O_absent;
10803 /* Args don't match. */
10804 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10805 strcmp (insn->name, insn[1].name) == 0)
10812 insn_error = _("illegal operands");
10818 /* This structure holds information we know about a mips16 immediate
10821 struct mips16_immed_operand
10823 /* The type code used in the argument string in the opcode table. */
10825 /* The number of bits in the short form of the opcode. */
10827 /* The number of bits in the extended form of the opcode. */
10829 /* The amount by which the short form is shifted when it is used;
10830 for example, the sw instruction has a shift count of 2. */
10832 /* The amount by which the short form is shifted when it is stored
10833 into the instruction code. */
10835 /* Non-zero if the short form is unsigned. */
10837 /* Non-zero if the extended form is unsigned. */
10839 /* Non-zero if the value is PC relative. */
10843 /* The mips16 immediate operand types. */
10845 static const struct mips16_immed_operand mips16_immed_operands[] =
10847 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10848 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10849 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10850 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10851 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10852 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10853 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10854 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10855 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10856 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10857 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10858 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10859 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10860 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10861 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10862 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10863 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10864 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10865 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10866 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10867 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10870 #define MIPS16_NUM_IMMED \
10871 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10873 /* Handle a mips16 instruction with an immediate value. This or's the
10874 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10875 whether an extended value is needed; if one is needed, it sets
10876 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10877 If SMALL is true, an unextended opcode was explicitly requested.
10878 If EXT is true, an extended opcode was explicitly requested. If
10879 WARN is true, warn if EXT does not match reality. */
10882 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10883 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10884 unsigned long *insn, bfd_boolean *use_extend,
10885 unsigned short *extend)
10887 const struct mips16_immed_operand *op;
10888 int mintiny, maxtiny;
10889 bfd_boolean needext;
10891 op = mips16_immed_operands;
10892 while (op->type != type)
10895 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10900 if (type == '<' || type == '>' || type == '[' || type == ']')
10903 maxtiny = 1 << op->nbits;
10908 maxtiny = (1 << op->nbits) - 1;
10913 mintiny = - (1 << (op->nbits - 1));
10914 maxtiny = (1 << (op->nbits - 1)) - 1;
10917 /* Branch offsets have an implicit 0 in the lowest bit. */
10918 if (type == 'p' || type == 'q')
10921 if ((val & ((1 << op->shift) - 1)) != 0
10922 || val < (mintiny << op->shift)
10923 || val > (maxtiny << op->shift))
10928 if (warn && ext && ! needext)
10929 as_warn_where (file, line,
10930 _("extended operand requested but not required"));
10931 if (small && needext)
10932 as_bad_where (file, line, _("invalid unextended operand value"));
10934 if (small || (! ext && ! needext))
10938 *use_extend = FALSE;
10939 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10940 insnval <<= op->op_shift;
10945 long minext, maxext;
10951 maxext = (1 << op->extbits) - 1;
10955 minext = - (1 << (op->extbits - 1));
10956 maxext = (1 << (op->extbits - 1)) - 1;
10958 if (val < minext || val > maxext)
10959 as_bad_where (file, line,
10960 _("operand value out of range for instruction"));
10962 *use_extend = TRUE;
10963 if (op->extbits == 16)
10965 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10968 else if (op->extbits == 15)
10970 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10975 extval = ((val & 0x1f) << 6) | (val & 0x20);
10979 *extend = (unsigned short) extval;
10984 struct percent_op_match
10987 bfd_reloc_code_real_type reloc;
10990 static const struct percent_op_match mips_percent_op[] =
10992 {"%lo", BFD_RELOC_LO16},
10994 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10995 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10996 {"%call16", BFD_RELOC_MIPS_CALL16},
10997 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10998 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10999 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11000 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11001 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11002 {"%got", BFD_RELOC_MIPS_GOT16},
11003 {"%gp_rel", BFD_RELOC_GPREL16},
11004 {"%half", BFD_RELOC_16},
11005 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11006 {"%higher", BFD_RELOC_MIPS_HIGHER},
11007 {"%neg", BFD_RELOC_MIPS_SUB},
11008 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11009 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11010 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11011 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11012 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11013 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11014 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11016 {"%hi", BFD_RELOC_HI16_S}
11019 static const struct percent_op_match mips16_percent_op[] =
11021 {"%lo", BFD_RELOC_MIPS16_LO16},
11022 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11023 {"%got", BFD_RELOC_MIPS16_GOT16},
11024 {"%call16", BFD_RELOC_MIPS16_CALL16},
11025 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11029 /* Return true if *STR points to a relocation operator. When returning true,
11030 move *STR over the operator and store its relocation code in *RELOC.
11031 Leave both *STR and *RELOC alone when returning false. */
11034 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11036 const struct percent_op_match *percent_op;
11039 if (mips_opts.mips16)
11041 percent_op = mips16_percent_op;
11042 limit = ARRAY_SIZE (mips16_percent_op);
11046 percent_op = mips_percent_op;
11047 limit = ARRAY_SIZE (mips_percent_op);
11050 for (i = 0; i < limit; i++)
11051 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11053 int len = strlen (percent_op[i].str);
11055 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11058 *str += strlen (percent_op[i].str);
11059 *reloc = percent_op[i].reloc;
11061 /* Check whether the output BFD supports this relocation.
11062 If not, issue an error and fall back on something safe. */
11063 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11065 as_bad (_("relocation %s isn't supported by the current ABI"),
11066 percent_op[i].str);
11067 *reloc = BFD_RELOC_UNUSED;
11075 /* Parse string STR as a 16-bit relocatable operand. Store the
11076 expression in *EP and the relocations in the array starting
11077 at RELOC. Return the number of relocation operators used.
11079 On exit, EXPR_END points to the first character after the expression. */
11082 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11085 bfd_reloc_code_real_type reversed_reloc[3];
11086 size_t reloc_index, i;
11087 int crux_depth, str_depth;
11090 /* Search for the start of the main expression, recoding relocations
11091 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11092 of the main expression and with CRUX_DEPTH containing the number
11093 of open brackets at that point. */
11100 crux_depth = str_depth;
11102 /* Skip over whitespace and brackets, keeping count of the number
11104 while (*str == ' ' || *str == '\t' || *str == '(')
11109 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11110 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11112 my_getExpression (ep, crux);
11115 /* Match every open bracket. */
11116 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11120 if (crux_depth > 0)
11121 as_bad (_("unclosed '('"));
11125 if (reloc_index != 0)
11127 prev_reloc_op_frag = frag_now;
11128 for (i = 0; i < reloc_index; i++)
11129 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11132 return reloc_index;
11136 my_getExpression (expressionS *ep, char *str)
11141 save_in = input_line_pointer;
11142 input_line_pointer = str;
11144 expr_end = input_line_pointer;
11145 input_line_pointer = save_in;
11147 /* If we are in mips16 mode, and this is an expression based on `.',
11148 then we bump the value of the symbol by 1 since that is how other
11149 text symbols are handled. We don't bother to handle complex
11150 expressions, just `.' plus or minus a constant. */
11151 if (mips_opts.mips16
11152 && ep->X_op == O_symbol
11153 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
11154 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
11155 && symbol_get_frag (ep->X_add_symbol) == frag_now
11156 && symbol_constant_p (ep->X_add_symbol)
11157 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
11158 S_SET_VALUE (ep->X_add_symbol, val + 1);
11162 md_atof (int type, char *litP, int *sizeP)
11164 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11168 md_number_to_chars (char *buf, valueT val, int n)
11170 if (target_big_endian)
11171 number_to_chars_bigendian (buf, val, n);
11173 number_to_chars_littleendian (buf, val, n);
11177 static int support_64bit_objects(void)
11179 const char **list, **l;
11182 list = bfd_target_list ();
11183 for (l = list; *l != NULL; l++)
11185 /* This is traditional mips */
11186 if (strcmp (*l, "elf64-tradbigmips") == 0
11187 || strcmp (*l, "elf64-tradlittlemips") == 0)
11189 if (strcmp (*l, "elf64-bigmips") == 0
11190 || strcmp (*l, "elf64-littlemips") == 0)
11193 yes = (*l != NULL);
11197 #endif /* OBJ_ELF */
11199 const char *md_shortopts = "O::g::G:";
11203 OPTION_MARCH = OPTION_MD_BASE,
11225 OPTION_NO_SMARTMIPS,
11228 OPTION_COMPAT_ARCH_BASE,
11237 OPTION_M7000_HILO_FIX,
11238 OPTION_MNO_7000_HILO_FIX,
11241 OPTION_FIX_LOONGSON2F_JUMP,
11242 OPTION_NO_FIX_LOONGSON2F_JUMP,
11243 OPTION_FIX_LOONGSON2F_NOP,
11244 OPTION_NO_FIX_LOONGSON2F_NOP,
11246 OPTION_NO_FIX_VR4120,
11248 OPTION_NO_FIX_VR4130,
11249 OPTION_FIX_CN63XXP1,
11250 OPTION_NO_FIX_CN63XXP1,
11257 OPTION_CONSTRUCT_FLOATS,
11258 OPTION_NO_CONSTRUCT_FLOATS,
11261 OPTION_RELAX_BRANCH,
11262 OPTION_NO_RELAX_BRANCH,
11269 OPTION_SINGLE_FLOAT,
11270 OPTION_DOUBLE_FLOAT,
11273 OPTION_CALL_SHARED,
11274 OPTION_CALL_NONPIC,
11284 OPTION_MVXWORKS_PIC,
11285 #endif /* OBJ_ELF */
11289 struct option md_longopts[] =
11291 /* Options which specify architecture. */
11292 {"march", required_argument, NULL, OPTION_MARCH},
11293 {"mtune", required_argument, NULL, OPTION_MTUNE},
11294 {"mips0", no_argument, NULL, OPTION_MIPS1},
11295 {"mips1", no_argument, NULL, OPTION_MIPS1},
11296 {"mips2", no_argument, NULL, OPTION_MIPS2},
11297 {"mips3", no_argument, NULL, OPTION_MIPS3},
11298 {"mips4", no_argument, NULL, OPTION_MIPS4},
11299 {"mips5", no_argument, NULL, OPTION_MIPS5},
11300 {"mips32", no_argument, NULL, OPTION_MIPS32},
11301 {"mips64", no_argument, NULL, OPTION_MIPS64},
11302 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11303 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11305 /* Options which specify Application Specific Extensions (ASEs). */
11306 {"mips16", no_argument, NULL, OPTION_MIPS16},
11307 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11308 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11309 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11310 {"mdmx", no_argument, NULL, OPTION_MDMX},
11311 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11312 {"mdsp", no_argument, NULL, OPTION_DSP},
11313 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11314 {"mmt", no_argument, NULL, OPTION_MT},
11315 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11316 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11317 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11318 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11319 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11321 /* Old-style architecture options. Don't add more of these. */
11322 {"m4650", no_argument, NULL, OPTION_M4650},
11323 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11324 {"m4010", no_argument, NULL, OPTION_M4010},
11325 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11326 {"m4100", no_argument, NULL, OPTION_M4100},
11327 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11328 {"m3900", no_argument, NULL, OPTION_M3900},
11329 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11331 /* Options which enable bug fixes. */
11332 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11333 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11334 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11335 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11336 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11337 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11338 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11339 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11340 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11341 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11342 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11343 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11344 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11345 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11346 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11348 /* Miscellaneous options. */
11349 {"trap", no_argument, NULL, OPTION_TRAP},
11350 {"no-break", no_argument, NULL, OPTION_TRAP},
11351 {"break", no_argument, NULL, OPTION_BREAK},
11352 {"no-trap", no_argument, NULL, OPTION_BREAK},
11353 {"EB", no_argument, NULL, OPTION_EB},
11354 {"EL", no_argument, NULL, OPTION_EL},
11355 {"mfp32", no_argument, NULL, OPTION_FP32},
11356 {"mgp32", no_argument, NULL, OPTION_GP32},
11357 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11358 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11359 {"mfp64", no_argument, NULL, OPTION_FP64},
11360 {"mgp64", no_argument, NULL, OPTION_GP64},
11361 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11362 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11363 {"mshared", no_argument, NULL, OPTION_MSHARED},
11364 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11365 {"msym32", no_argument, NULL, OPTION_MSYM32},
11366 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11367 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11368 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11369 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11370 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11372 /* Strictly speaking this next option is ELF specific,
11373 but we allow it for other ports as well in order to
11374 make testing easier. */
11375 {"32", no_argument, NULL, OPTION_32},
11377 /* ELF-specific options. */
11379 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11380 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11381 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11382 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11383 {"xgot", no_argument, NULL, OPTION_XGOT},
11384 {"mabi", required_argument, NULL, OPTION_MABI},
11385 {"n32", no_argument, NULL, OPTION_N32},
11386 {"64", no_argument, NULL, OPTION_64},
11387 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11388 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11389 {"mpdr", no_argument, NULL, OPTION_PDR},
11390 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11391 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11392 #endif /* OBJ_ELF */
11394 {NULL, no_argument, NULL, 0}
11396 size_t md_longopts_size = sizeof (md_longopts);
11398 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11399 NEW_VALUE. Warn if another value was already specified. Note:
11400 we have to defer parsing the -march and -mtune arguments in order
11401 to handle 'from-abi' correctly, since the ABI might be specified
11402 in a later argument. */
11405 mips_set_option_string (const char **string_ptr, const char *new_value)
11407 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11408 as_warn (_("A different %s was already specified, is now %s"),
11409 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11412 *string_ptr = new_value;
11416 md_parse_option (int c, char *arg)
11420 case OPTION_CONSTRUCT_FLOATS:
11421 mips_disable_float_construction = 0;
11424 case OPTION_NO_CONSTRUCT_FLOATS:
11425 mips_disable_float_construction = 1;
11437 target_big_endian = 1;
11441 target_big_endian = 0;
11447 else if (arg[0] == '0')
11449 else if (arg[0] == '1')
11459 mips_debug = atoi (arg);
11463 file_mips_isa = ISA_MIPS1;
11467 file_mips_isa = ISA_MIPS2;
11471 file_mips_isa = ISA_MIPS3;
11475 file_mips_isa = ISA_MIPS4;
11479 file_mips_isa = ISA_MIPS5;
11482 case OPTION_MIPS32:
11483 file_mips_isa = ISA_MIPS32;
11486 case OPTION_MIPS32R2:
11487 file_mips_isa = ISA_MIPS32R2;
11490 case OPTION_MIPS64R2:
11491 file_mips_isa = ISA_MIPS64R2;
11494 case OPTION_MIPS64:
11495 file_mips_isa = ISA_MIPS64;
11499 mips_set_option_string (&mips_tune_string, arg);
11503 mips_set_option_string (&mips_arch_string, arg);
11507 mips_set_option_string (&mips_arch_string, "4650");
11508 mips_set_option_string (&mips_tune_string, "4650");
11511 case OPTION_NO_M4650:
11515 mips_set_option_string (&mips_arch_string, "4010");
11516 mips_set_option_string (&mips_tune_string, "4010");
11519 case OPTION_NO_M4010:
11523 mips_set_option_string (&mips_arch_string, "4100");
11524 mips_set_option_string (&mips_tune_string, "4100");
11527 case OPTION_NO_M4100:
11531 mips_set_option_string (&mips_arch_string, "3900");
11532 mips_set_option_string (&mips_tune_string, "3900");
11535 case OPTION_NO_M3900:
11539 mips_opts.ase_mdmx = 1;
11542 case OPTION_NO_MDMX:
11543 mips_opts.ase_mdmx = 0;
11547 mips_opts.ase_dsp = 1;
11548 mips_opts.ase_dspr2 = 0;
11551 case OPTION_NO_DSP:
11552 mips_opts.ase_dsp = 0;
11553 mips_opts.ase_dspr2 = 0;
11557 mips_opts.ase_dspr2 = 1;
11558 mips_opts.ase_dsp = 1;
11561 case OPTION_NO_DSPR2:
11562 mips_opts.ase_dspr2 = 0;
11563 mips_opts.ase_dsp = 0;
11567 mips_opts.ase_mt = 1;
11571 mips_opts.ase_mt = 0;
11574 case OPTION_MIPS16:
11575 mips_opts.mips16 = 1;
11576 mips_no_prev_insn ();
11579 case OPTION_NO_MIPS16:
11580 mips_opts.mips16 = 0;
11581 mips_no_prev_insn ();
11584 case OPTION_MIPS3D:
11585 mips_opts.ase_mips3d = 1;
11588 case OPTION_NO_MIPS3D:
11589 mips_opts.ase_mips3d = 0;
11592 case OPTION_SMARTMIPS:
11593 mips_opts.ase_smartmips = 1;
11596 case OPTION_NO_SMARTMIPS:
11597 mips_opts.ase_smartmips = 0;
11600 case OPTION_FIX_24K:
11604 case OPTION_NO_FIX_24K:
11608 case OPTION_FIX_LOONGSON2F_JUMP:
11609 mips_fix_loongson2f_jump = TRUE;
11612 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11613 mips_fix_loongson2f_jump = FALSE;
11616 case OPTION_FIX_LOONGSON2F_NOP:
11617 mips_fix_loongson2f_nop = TRUE;
11620 case OPTION_NO_FIX_LOONGSON2F_NOP:
11621 mips_fix_loongson2f_nop = FALSE;
11624 case OPTION_FIX_VR4120:
11625 mips_fix_vr4120 = 1;
11628 case OPTION_NO_FIX_VR4120:
11629 mips_fix_vr4120 = 0;
11632 case OPTION_FIX_VR4130:
11633 mips_fix_vr4130 = 1;
11636 case OPTION_NO_FIX_VR4130:
11637 mips_fix_vr4130 = 0;
11640 case OPTION_FIX_CN63XXP1:
11641 mips_fix_cn63xxp1 = TRUE;
11644 case OPTION_NO_FIX_CN63XXP1:
11645 mips_fix_cn63xxp1 = FALSE;
11648 case OPTION_RELAX_BRANCH:
11649 mips_relax_branch = 1;
11652 case OPTION_NO_RELAX_BRANCH:
11653 mips_relax_branch = 0;
11656 case OPTION_MSHARED:
11657 mips_in_shared = TRUE;
11660 case OPTION_MNO_SHARED:
11661 mips_in_shared = FALSE;
11664 case OPTION_MSYM32:
11665 mips_opts.sym32 = TRUE;
11668 case OPTION_MNO_SYM32:
11669 mips_opts.sym32 = FALSE;
11673 /* When generating ELF code, we permit -KPIC and -call_shared to
11674 select SVR4_PIC, and -non_shared to select no PIC. This is
11675 intended to be compatible with Irix 5. */
11676 case OPTION_CALL_SHARED:
11679 as_bad (_("-call_shared is supported only for ELF format"));
11682 mips_pic = SVR4_PIC;
11683 mips_abicalls = TRUE;
11686 case OPTION_CALL_NONPIC:
11689 as_bad (_("-call_nonpic is supported only for ELF format"));
11693 mips_abicalls = TRUE;
11696 case OPTION_NON_SHARED:
11699 as_bad (_("-non_shared is supported only for ELF format"));
11703 mips_abicalls = FALSE;
11706 /* The -xgot option tells the assembler to use 32 bit offsets
11707 when accessing the got in SVR4_PIC mode. It is for Irix
11712 #endif /* OBJ_ELF */
11715 g_switch_value = atoi (arg);
11719 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11723 mips_abi = O32_ABI;
11724 /* We silently ignore -32 for non-ELF targets. This greatly
11725 simplifies the construction of the MIPS GAS test cases. */
11732 as_bad (_("-n32 is supported for ELF format only"));
11735 mips_abi = N32_ABI;
11741 as_bad (_("-64 is supported for ELF format only"));
11744 mips_abi = N64_ABI;
11745 if (!support_64bit_objects())
11746 as_fatal (_("No compiled in support for 64 bit object file format"));
11748 #endif /* OBJ_ELF */
11751 file_mips_gp32 = 1;
11755 file_mips_gp32 = 0;
11759 file_mips_fp32 = 1;
11763 file_mips_fp32 = 0;
11766 case OPTION_SINGLE_FLOAT:
11767 file_mips_single_float = 1;
11770 case OPTION_DOUBLE_FLOAT:
11771 file_mips_single_float = 0;
11774 case OPTION_SOFT_FLOAT:
11775 file_mips_soft_float = 1;
11778 case OPTION_HARD_FLOAT:
11779 file_mips_soft_float = 0;
11786 as_bad (_("-mabi is supported for ELF format only"));
11789 if (strcmp (arg, "32") == 0)
11790 mips_abi = O32_ABI;
11791 else if (strcmp (arg, "o64") == 0)
11792 mips_abi = O64_ABI;
11793 else if (strcmp (arg, "n32") == 0)
11794 mips_abi = N32_ABI;
11795 else if (strcmp (arg, "64") == 0)
11797 mips_abi = N64_ABI;
11798 if (! support_64bit_objects())
11799 as_fatal (_("No compiled in support for 64 bit object file "
11802 else if (strcmp (arg, "eabi") == 0)
11803 mips_abi = EABI_ABI;
11806 as_fatal (_("invalid abi -mabi=%s"), arg);
11810 #endif /* OBJ_ELF */
11812 case OPTION_M7000_HILO_FIX:
11813 mips_7000_hilo_fix = TRUE;
11816 case OPTION_MNO_7000_HILO_FIX:
11817 mips_7000_hilo_fix = FALSE;
11821 case OPTION_MDEBUG:
11822 mips_flag_mdebug = TRUE;
11825 case OPTION_NO_MDEBUG:
11826 mips_flag_mdebug = FALSE;
11830 mips_flag_pdr = TRUE;
11833 case OPTION_NO_PDR:
11834 mips_flag_pdr = FALSE;
11837 case OPTION_MVXWORKS_PIC:
11838 mips_pic = VXWORKS_PIC;
11840 #endif /* OBJ_ELF */
11846 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
11851 /* Set up globals to generate code for the ISA or processor
11852 described by INFO. */
11855 mips_set_architecture (const struct mips_cpu_info *info)
11859 file_mips_arch = info->cpu;
11860 mips_opts.arch = info->cpu;
11861 mips_opts.isa = info->isa;
11866 /* Likewise for tuning. */
11869 mips_set_tune (const struct mips_cpu_info *info)
11872 mips_tune = info->cpu;
11877 mips_after_parse_args (void)
11879 const struct mips_cpu_info *arch_info = 0;
11880 const struct mips_cpu_info *tune_info = 0;
11882 /* GP relative stuff not working for PE */
11883 if (strncmp (TARGET_OS, "pe", 2) == 0)
11885 if (g_switch_seen && g_switch_value != 0)
11886 as_bad (_("-G not supported in this configuration."));
11887 g_switch_value = 0;
11890 if (mips_abi == NO_ABI)
11891 mips_abi = MIPS_DEFAULT_ABI;
11893 /* The following code determines the architecture and register size.
11894 Similar code was added to GCC 3.3 (see override_options() in
11895 config/mips/mips.c). The GAS and GCC code should be kept in sync
11896 as much as possible. */
11898 if (mips_arch_string != 0)
11899 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11901 if (file_mips_isa != ISA_UNKNOWN)
11903 /* Handle -mipsN. At this point, file_mips_isa contains the
11904 ISA level specified by -mipsN, while arch_info->isa contains
11905 the -march selection (if any). */
11906 if (arch_info != 0)
11908 /* -march takes precedence over -mipsN, since it is more descriptive.
11909 There's no harm in specifying both as long as the ISA levels
11911 if (file_mips_isa != arch_info->isa)
11912 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11913 mips_cpu_info_from_isa (file_mips_isa)->name,
11914 mips_cpu_info_from_isa (arch_info->isa)->name);
11917 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11920 if (arch_info == 0)
11921 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11923 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11924 as_bad (_("-march=%s is not compatible with the selected ABI"),
11927 mips_set_architecture (arch_info);
11929 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11930 if (mips_tune_string != 0)
11931 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11933 if (tune_info == 0)
11934 mips_set_tune (arch_info);
11936 mips_set_tune (tune_info);
11938 if (file_mips_gp32 >= 0)
11940 /* The user specified the size of the integer registers. Make sure
11941 it agrees with the ABI and ISA. */
11942 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11943 as_bad (_("-mgp64 used with a 32-bit processor"));
11944 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11945 as_bad (_("-mgp32 used with a 64-bit ABI"));
11946 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11947 as_bad (_("-mgp64 used with a 32-bit ABI"));
11951 /* Infer the integer register size from the ABI and processor.
11952 Restrict ourselves to 32-bit registers if that's all the
11953 processor has, or if the ABI cannot handle 64-bit registers. */
11954 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11955 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11958 switch (file_mips_fp32)
11962 /* No user specified float register size.
11963 ??? GAS treats single-float processors as though they had 64-bit
11964 float registers (although it complains when double-precision
11965 instructions are used). As things stand, saying they have 32-bit
11966 registers would lead to spurious "register must be even" messages.
11967 So here we assume float registers are never smaller than the
11969 if (file_mips_gp32 == 0)
11970 /* 64-bit integer registers implies 64-bit float registers. */
11971 file_mips_fp32 = 0;
11972 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11973 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11974 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11975 file_mips_fp32 = 0;
11977 /* 32-bit float registers. */
11978 file_mips_fp32 = 1;
11981 /* The user specified the size of the float registers. Check if it
11982 agrees with the ABI and ISA. */
11984 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
11985 as_bad (_("-mfp64 used with a 32-bit fpu"));
11986 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
11987 && !ISA_HAS_MXHC1 (mips_opts.isa))
11988 as_warn (_("-mfp64 used with a 32-bit ABI"));
11991 if (ABI_NEEDS_64BIT_REGS (mips_abi))
11992 as_warn (_("-mfp32 used with a 64-bit ABI"));
11996 /* End of GCC-shared inference code. */
11998 /* This flag is set when we have a 64-bit capable CPU but use only
11999 32-bit wide registers. Note that EABI does not use it. */
12000 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12001 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12002 || mips_abi == O32_ABI))
12003 mips_32bitmode = 1;
12005 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12006 as_bad (_("trap exception not supported at ISA 1"));
12008 /* If the selected architecture includes support for ASEs, enable
12009 generation of code for them. */
12010 if (mips_opts.mips16 == -1)
12011 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12012 if (mips_opts.ase_mips3d == -1)
12013 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12014 && file_mips_fp32 == 0) ? 1 : 0;
12015 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12016 as_bad (_("-mfp32 used with -mips3d"));
12018 if (mips_opts.ase_mdmx == -1)
12019 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12020 && file_mips_fp32 == 0) ? 1 : 0;
12021 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12022 as_bad (_("-mfp32 used with -mdmx"));
12024 if (mips_opts.ase_smartmips == -1)
12025 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12026 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12027 as_warn (_("%s ISA does not support SmartMIPS"),
12028 mips_cpu_info_from_isa (mips_opts.isa)->name);
12030 if (mips_opts.ase_dsp == -1)
12031 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12032 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12033 as_warn (_("%s ISA does not support DSP ASE"),
12034 mips_cpu_info_from_isa (mips_opts.isa)->name);
12036 if (mips_opts.ase_dspr2 == -1)
12038 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12039 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12041 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12042 as_warn (_("%s ISA does not support DSP R2 ASE"),
12043 mips_cpu_info_from_isa (mips_opts.isa)->name);
12045 if (mips_opts.ase_mt == -1)
12046 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12047 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12048 as_warn (_("%s ISA does not support MT ASE"),
12049 mips_cpu_info_from_isa (mips_opts.isa)->name);
12051 file_mips_isa = mips_opts.isa;
12052 file_ase_mips3d = mips_opts.ase_mips3d;
12053 file_ase_mdmx = mips_opts.ase_mdmx;
12054 file_ase_smartmips = mips_opts.ase_smartmips;
12055 file_ase_dsp = mips_opts.ase_dsp;
12056 file_ase_dspr2 = mips_opts.ase_dspr2;
12057 file_ase_mt = mips_opts.ase_mt;
12058 mips_opts.gp32 = file_mips_gp32;
12059 mips_opts.fp32 = file_mips_fp32;
12060 mips_opts.soft_float = file_mips_soft_float;
12061 mips_opts.single_float = file_mips_single_float;
12063 if (mips_flag_mdebug < 0)
12065 #ifdef OBJ_MAYBE_ECOFF
12066 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12067 mips_flag_mdebug = 1;
12069 #endif /* OBJ_MAYBE_ECOFF */
12070 mips_flag_mdebug = 0;
12075 mips_init_after_args (void)
12077 /* initialize opcodes */
12078 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12079 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12083 md_pcrel_from (fixS *fixP)
12085 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12086 switch (fixP->fx_r_type)
12088 case BFD_RELOC_16_PCREL_S2:
12089 case BFD_RELOC_MIPS_JMP:
12090 /* Return the address of the delay slot. */
12093 /* We have no relocation type for PC relative MIPS16 instructions. */
12094 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12095 as_bad_where (fixP->fx_file, fixP->fx_line,
12096 _("PC relative MIPS16 instruction references a different section"));
12101 /* This is called before the symbol table is processed. In order to
12102 work with gcc when using mips-tfile, we must keep all local labels.
12103 However, in other cases, we want to discard them. If we were
12104 called with -g, but we didn't see any debugging information, it may
12105 mean that gcc is smuggling debugging information through to
12106 mips-tfile, in which case we must generate all local labels. */
12109 mips_frob_file_before_adjust (void)
12111 #ifndef NO_ECOFF_DEBUGGING
12112 if (ECOFF_DEBUGGING
12114 && ! ecoff_debugging_seen)
12115 flag_keep_locals = 1;
12119 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12120 the corresponding LO16 reloc. This is called before md_apply_fix and
12121 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12122 relocation operators.
12124 For our purposes, a %lo() expression matches a %got() or %hi()
12127 (a) it refers to the same symbol; and
12128 (b) the offset applied in the %lo() expression is no lower than
12129 the offset applied in the %got() or %hi().
12131 (b) allows us to cope with code like:
12134 lh $4,%lo(foo+2)($4)
12136 ...which is legal on RELA targets, and has a well-defined behaviour
12137 if the user knows that adding 2 to "foo" will not induce a carry to
12140 When several %lo()s match a particular %got() or %hi(), we use the
12141 following rules to distinguish them:
12143 (1) %lo()s with smaller offsets are a better match than %lo()s with
12146 (2) %lo()s with no matching %got() or %hi() are better than those
12147 that already have a matching %got() or %hi().
12149 (3) later %lo()s are better than earlier %lo()s.
12151 These rules are applied in order.
12153 (1) means, among other things, that %lo()s with identical offsets are
12154 chosen if they exist.
12156 (2) means that we won't associate several high-part relocations with
12157 the same low-part relocation unless there's no alternative. Having
12158 several high parts for the same low part is a GNU extension; this rule
12159 allows careful users to avoid it.
12161 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12162 with the last high-part relocation being at the front of the list.
12163 It therefore makes sense to choose the last matching low-part
12164 relocation, all other things being equal. It's also easier
12165 to code that way. */
12168 mips_frob_file (void)
12170 struct mips_hi_fixup *l;
12171 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12173 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12175 segment_info_type *seginfo;
12176 bfd_boolean matched_lo_p;
12177 fixS **hi_pos, **lo_pos, **pos;
12179 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12181 /* If a GOT16 relocation turns out to be against a global symbol,
12182 there isn't supposed to be a matching LO. */
12183 if (got16_reloc_p (l->fixp->fx_r_type)
12184 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12187 /* Check quickly whether the next fixup happens to be a matching %lo. */
12188 if (fixup_has_matching_lo_p (l->fixp))
12191 seginfo = seg_info (l->seg);
12193 /* Set HI_POS to the position of this relocation in the chain.
12194 Set LO_POS to the position of the chosen low-part relocation.
12195 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12196 relocation that matches an immediately-preceding high-part
12200 matched_lo_p = FALSE;
12201 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12203 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12205 if (*pos == l->fixp)
12208 if ((*pos)->fx_r_type == looking_for_rtype
12209 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12210 && (*pos)->fx_offset >= l->fixp->fx_offset
12212 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12214 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12217 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12218 && fixup_has_matching_lo_p (*pos));
12221 /* If we found a match, remove the high-part relocation from its
12222 current position and insert it before the low-part relocation.
12223 Make the offsets match so that fixup_has_matching_lo_p()
12226 We don't warn about unmatched high-part relocations since some
12227 versions of gcc have been known to emit dead "lui ...%hi(...)"
12229 if (lo_pos != NULL)
12231 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12232 if (l->fixp->fx_next != *lo_pos)
12234 *hi_pos = l->fixp->fx_next;
12235 l->fixp->fx_next = *lo_pos;
12242 /* We may have combined relocations without symbols in the N32/N64 ABI.
12243 We have to prevent gas from dropping them. */
12246 mips_force_relocation (fixS *fixp)
12248 if (generic_force_reloc (fixp))
12252 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12253 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12254 || hi16_reloc_p (fixp->fx_r_type)
12255 || lo16_reloc_p (fixp->fx_r_type)))
12261 /* Apply a fixup to the object file. */
12264 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12268 reloc_howto_type *howto;
12270 /* We ignore generic BFD relocations we don't know about. */
12271 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12275 gas_assert (fixP->fx_size == 4
12276 || fixP->fx_r_type == BFD_RELOC_16
12277 || fixP->fx_r_type == BFD_RELOC_64
12278 || fixP->fx_r_type == BFD_RELOC_CTOR
12279 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12280 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12281 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12282 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12284 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12286 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12288 /* Don't treat parts of a composite relocation as done. There are two
12291 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12292 should nevertheless be emitted if the first part is.
12294 (2) In normal usage, composite relocations are never assembly-time
12295 constants. The easiest way of dealing with the pathological
12296 exceptions is to generate a relocation against STN_UNDEF and
12297 leave everything up to the linker. */
12298 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12301 switch (fixP->fx_r_type)
12303 case BFD_RELOC_MIPS_TLS_GD:
12304 case BFD_RELOC_MIPS_TLS_LDM:
12305 case BFD_RELOC_MIPS_TLS_DTPREL32:
12306 case BFD_RELOC_MIPS_TLS_DTPREL64:
12307 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12308 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12309 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12310 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12311 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12312 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12315 case BFD_RELOC_MIPS_JMP:
12316 case BFD_RELOC_MIPS_SHIFT5:
12317 case BFD_RELOC_MIPS_SHIFT6:
12318 case BFD_RELOC_MIPS_GOT_DISP:
12319 case BFD_RELOC_MIPS_GOT_PAGE:
12320 case BFD_RELOC_MIPS_GOT_OFST:
12321 case BFD_RELOC_MIPS_SUB:
12322 case BFD_RELOC_MIPS_INSERT_A:
12323 case BFD_RELOC_MIPS_INSERT_B:
12324 case BFD_RELOC_MIPS_DELETE:
12325 case BFD_RELOC_MIPS_HIGHEST:
12326 case BFD_RELOC_MIPS_HIGHER:
12327 case BFD_RELOC_MIPS_SCN_DISP:
12328 case BFD_RELOC_MIPS_REL16:
12329 case BFD_RELOC_MIPS_RELGOT:
12330 case BFD_RELOC_MIPS_JALR:
12331 case BFD_RELOC_HI16:
12332 case BFD_RELOC_HI16_S:
12333 case BFD_RELOC_GPREL16:
12334 case BFD_RELOC_MIPS_LITERAL:
12335 case BFD_RELOC_MIPS_CALL16:
12336 case BFD_RELOC_MIPS_GOT16:
12337 case BFD_RELOC_GPREL32:
12338 case BFD_RELOC_MIPS_GOT_HI16:
12339 case BFD_RELOC_MIPS_GOT_LO16:
12340 case BFD_RELOC_MIPS_CALL_HI16:
12341 case BFD_RELOC_MIPS_CALL_LO16:
12342 case BFD_RELOC_MIPS16_GPREL:
12343 case BFD_RELOC_MIPS16_GOT16:
12344 case BFD_RELOC_MIPS16_CALL16:
12345 case BFD_RELOC_MIPS16_HI16:
12346 case BFD_RELOC_MIPS16_HI16_S:
12347 case BFD_RELOC_MIPS16_JMP:
12348 /* Nothing needed to do. The value comes from the reloc entry. */
12352 /* This is handled like BFD_RELOC_32, but we output a sign
12353 extended value if we are only 32 bits. */
12356 if (8 <= sizeof (valueT))
12357 md_number_to_chars ((char *) buf, *valP, 8);
12362 if ((*valP & 0x80000000) != 0)
12366 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12368 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12374 case BFD_RELOC_RVA:
12377 /* If we are deleting this reloc entry, we must fill in the
12378 value now. This can happen if we have a .word which is not
12379 resolved when it appears but is later defined. */
12381 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12384 case BFD_RELOC_LO16:
12385 case BFD_RELOC_MIPS16_LO16:
12386 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12387 may be safe to remove, but if so it's not obvious. */
12388 /* When handling an embedded PIC switch statement, we can wind
12389 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12392 if (*valP + 0x8000 > 0xffff)
12393 as_bad_where (fixP->fx_file, fixP->fx_line,
12394 _("relocation overflow"));
12395 if (target_big_endian)
12397 md_number_to_chars ((char *) buf, *valP, 2);
12401 case BFD_RELOC_16_PCREL_S2:
12402 if ((*valP & 0x3) != 0)
12403 as_bad_where (fixP->fx_file, fixP->fx_line,
12404 _("Branch to misaligned address (%lx)"), (long) *valP);
12406 /* We need to save the bits in the instruction since fixup_segment()
12407 might be deleting the relocation entry (i.e., a branch within
12408 the current segment). */
12409 if (! fixP->fx_done)
12412 /* Update old instruction data. */
12413 if (target_big_endian)
12414 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12416 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12418 if (*valP + 0x20000 <= 0x3ffff)
12420 insn |= (*valP >> 2) & 0xffff;
12421 md_number_to_chars ((char *) buf, insn, 4);
12423 else if (mips_pic == NO_PIC
12425 && fixP->fx_frag->fr_address >= text_section->vma
12426 && (fixP->fx_frag->fr_address
12427 < text_section->vma + bfd_get_section_size (text_section))
12428 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12429 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12430 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12432 /* The branch offset is too large. If this is an
12433 unconditional branch, and we are not generating PIC code,
12434 we can convert it to an absolute jump instruction. */
12435 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12436 insn = 0x0c000000; /* jal */
12438 insn = 0x08000000; /* j */
12439 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12441 fixP->fx_addsy = section_symbol (text_section);
12442 *valP += md_pcrel_from (fixP);
12443 md_number_to_chars ((char *) buf, insn, 4);
12447 /* If we got here, we have branch-relaxation disabled,
12448 and there's nothing we can do to fix this instruction
12449 without turning it into a longer sequence. */
12450 as_bad_where (fixP->fx_file, fixP->fx_line,
12451 _("Branch out of range"));
12455 case BFD_RELOC_VTABLE_INHERIT:
12458 && !S_IS_DEFINED (fixP->fx_addsy)
12459 && !S_IS_WEAK (fixP->fx_addsy))
12460 S_SET_WEAK (fixP->fx_addsy);
12463 case BFD_RELOC_VTABLE_ENTRY:
12471 /* Remember value for tc_gen_reloc. */
12472 fixP->fx_addnumber = *valP;
12482 name = input_line_pointer;
12483 c = get_symbol_end ();
12484 p = (symbolS *) symbol_find_or_make (name);
12485 *input_line_pointer = c;
12489 /* Align the current frag to a given power of two. If a particular
12490 fill byte should be used, FILL points to an integer that contains
12491 that byte, otherwise FILL is null.
12493 The MIPS assembler also automatically adjusts any preceding
12497 mips_align (int to, int *fill, symbolS *label)
12499 mips_emit_delays ();
12500 mips_record_mips16_mode ();
12501 if (fill == NULL && subseg_text_p (now_seg))
12502 frag_align_code (to, 0);
12504 frag_align (to, fill ? *fill : 0, 0);
12505 record_alignment (now_seg, to);
12508 gas_assert (S_GET_SEGMENT (label) == now_seg);
12509 symbol_set_frag (label, frag_now);
12510 S_SET_VALUE (label, (valueT) frag_now_fix ());
12514 /* Align to a given power of two. .align 0 turns off the automatic
12515 alignment used by the data creating pseudo-ops. */
12518 s_align (int x ATTRIBUTE_UNUSED)
12520 int temp, fill_value, *fill_ptr;
12521 long max_alignment = 28;
12523 /* o Note that the assembler pulls down any immediately preceding label
12524 to the aligned address.
12525 o It's not documented but auto alignment is reinstated by
12526 a .align pseudo instruction.
12527 o Note also that after auto alignment is turned off the mips assembler
12528 issues an error on attempt to assemble an improperly aligned data item.
12531 temp = get_absolute_expression ();
12532 if (temp > max_alignment)
12533 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12536 as_warn (_("Alignment negative: 0 assumed."));
12539 if (*input_line_pointer == ',')
12541 ++input_line_pointer;
12542 fill_value = get_absolute_expression ();
12543 fill_ptr = &fill_value;
12549 segment_info_type *si = seg_info (now_seg);
12550 struct insn_label_list *l = si->label_list;
12551 /* Auto alignment should be switched on by next section change. */
12553 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12560 demand_empty_rest_of_line ();
12564 s_change_sec (int sec)
12569 /* The ELF backend needs to know that we are changing sections, so
12570 that .previous works correctly. We could do something like check
12571 for an obj_section_change_hook macro, but that might be confusing
12572 as it would not be appropriate to use it in the section changing
12573 functions in read.c, since obj-elf.c intercepts those. FIXME:
12574 This should be cleaner, somehow. */
12576 obj_elf_section_change_hook ();
12579 mips_emit_delays ();
12590 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12591 demand_empty_rest_of_line ();
12595 seg = subseg_new (RDATA_SECTION_NAME,
12596 (subsegT) get_absolute_expression ());
12599 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12600 | SEC_READONLY | SEC_RELOC
12602 if (strncmp (TARGET_OS, "elf", 3) != 0)
12603 record_alignment (seg, 4);
12605 demand_empty_rest_of_line ();
12609 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12612 bfd_set_section_flags (stdoutput, seg,
12613 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12614 if (strncmp (TARGET_OS, "elf", 3) != 0)
12615 record_alignment (seg, 4);
12617 demand_empty_rest_of_line ();
12621 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12624 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12625 if (strncmp (TARGET_OS, "elf", 3) != 0)
12626 record_alignment (seg, 4);
12628 demand_empty_rest_of_line ();
12636 s_change_section (int ignore ATTRIBUTE_UNUSED)
12639 char *section_name;
12644 int section_entry_size;
12645 int section_alignment;
12650 section_name = input_line_pointer;
12651 c = get_symbol_end ();
12653 next_c = *(input_line_pointer + 1);
12655 /* Do we have .section Name<,"flags">? */
12656 if (c != ',' || (c == ',' && next_c == '"'))
12658 /* just after name is now '\0'. */
12659 *input_line_pointer = c;
12660 input_line_pointer = section_name;
12661 obj_elf_section (ignore);
12664 input_line_pointer++;
12666 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12668 section_type = get_absolute_expression ();
12671 if (*input_line_pointer++ == ',')
12672 section_flag = get_absolute_expression ();
12675 if (*input_line_pointer++ == ',')
12676 section_entry_size = get_absolute_expression ();
12678 section_entry_size = 0;
12679 if (*input_line_pointer++ == ',')
12680 section_alignment = get_absolute_expression ();
12682 section_alignment = 0;
12683 /* FIXME: really ignore? */
12684 (void) section_alignment;
12686 section_name = xstrdup (section_name);
12688 /* When using the generic form of .section (as implemented by obj-elf.c),
12689 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12690 traditionally had to fall back on the more common @progbits instead.
12692 There's nothing really harmful in this, since bfd will correct
12693 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12694 means that, for backwards compatibility, the special_section entries
12695 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12697 Even so, we shouldn't force users of the MIPS .section syntax to
12698 incorrectly label the sections as SHT_PROGBITS. The best compromise
12699 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12700 generic type-checking code. */
12701 if (section_type == SHT_MIPS_DWARF)
12702 section_type = SHT_PROGBITS;
12704 obj_elf_change_section (section_name, section_type, section_flag,
12705 section_entry_size, 0, 0, 0);
12707 if (now_seg->name != section_name)
12708 free (section_name);
12709 #endif /* OBJ_ELF */
12713 mips_enable_auto_align (void)
12719 s_cons (int log_size)
12721 segment_info_type *si = seg_info (now_seg);
12722 struct insn_label_list *l = si->label_list;
12725 label = l != NULL ? l->label : NULL;
12726 mips_emit_delays ();
12727 if (log_size > 0 && auto_align)
12728 mips_align (log_size, 0, label);
12729 mips_clear_insn_labels ();
12730 cons (1 << log_size);
12734 s_float_cons (int type)
12736 segment_info_type *si = seg_info (now_seg);
12737 struct insn_label_list *l = si->label_list;
12740 label = l != NULL ? l->label : NULL;
12742 mips_emit_delays ();
12747 mips_align (3, 0, label);
12749 mips_align (2, 0, label);
12752 mips_clear_insn_labels ();
12757 /* Handle .globl. We need to override it because on Irix 5 you are
12760 where foo is an undefined symbol, to mean that foo should be
12761 considered to be the address of a function. */
12764 s_mips_globl (int x ATTRIBUTE_UNUSED)
12773 name = input_line_pointer;
12774 c = get_symbol_end ();
12775 symbolP = symbol_find_or_make (name);
12776 S_SET_EXTERNAL (symbolP);
12778 *input_line_pointer = c;
12779 SKIP_WHITESPACE ();
12781 /* On Irix 5, every global symbol that is not explicitly labelled as
12782 being a function is apparently labelled as being an object. */
12785 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12786 && (*input_line_pointer != ','))
12791 secname = input_line_pointer;
12792 c = get_symbol_end ();
12793 sec = bfd_get_section_by_name (stdoutput, secname);
12795 as_bad (_("%s: no such section"), secname);
12796 *input_line_pointer = c;
12798 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12799 flag = BSF_FUNCTION;
12802 symbol_get_bfdsym (symbolP)->flags |= flag;
12804 c = *input_line_pointer;
12807 input_line_pointer++;
12808 SKIP_WHITESPACE ();
12809 if (is_end_of_line[(unsigned char) *input_line_pointer])
12815 demand_empty_rest_of_line ();
12819 s_option (int x ATTRIBUTE_UNUSED)
12824 opt = input_line_pointer;
12825 c = get_symbol_end ();
12829 /* FIXME: What does this mean? */
12831 else if (strncmp (opt, "pic", 3) == 0)
12835 i = atoi (opt + 3);
12840 mips_pic = SVR4_PIC;
12841 mips_abicalls = TRUE;
12844 as_bad (_(".option pic%d not supported"), i);
12846 if (mips_pic == SVR4_PIC)
12848 if (g_switch_seen && g_switch_value != 0)
12849 as_warn (_("-G may not be used with SVR4 PIC code"));
12850 g_switch_value = 0;
12851 bfd_set_gp_size (stdoutput, 0);
12855 as_warn (_("Unrecognized option \"%s\""), opt);
12857 *input_line_pointer = c;
12858 demand_empty_rest_of_line ();
12861 /* This structure is used to hold a stack of .set values. */
12863 struct mips_option_stack
12865 struct mips_option_stack *next;
12866 struct mips_set_options options;
12869 static struct mips_option_stack *mips_opts_stack;
12871 /* Handle the .set pseudo-op. */
12874 s_mipsset (int x ATTRIBUTE_UNUSED)
12876 char *name = input_line_pointer, ch;
12878 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12879 ++input_line_pointer;
12880 ch = *input_line_pointer;
12881 *input_line_pointer = '\0';
12883 if (strcmp (name, "reorder") == 0)
12885 if (mips_opts.noreorder)
12888 else if (strcmp (name, "noreorder") == 0)
12890 if (!mips_opts.noreorder)
12891 start_noreorder ();
12893 else if (strncmp (name, "at=", 3) == 0)
12895 char *s = name + 3;
12897 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
12898 as_bad (_("Unrecognized register name `%s'"), s);
12900 else if (strcmp (name, "at") == 0)
12902 mips_opts.at = ATREG;
12904 else if (strcmp (name, "noat") == 0)
12906 mips_opts.at = ZERO;
12908 else if (strcmp (name, "macro") == 0)
12910 mips_opts.warn_about_macros = 0;
12912 else if (strcmp (name, "nomacro") == 0)
12914 if (mips_opts.noreorder == 0)
12915 as_bad (_("`noreorder' must be set before `nomacro'"));
12916 mips_opts.warn_about_macros = 1;
12918 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12920 mips_opts.nomove = 0;
12922 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12924 mips_opts.nomove = 1;
12926 else if (strcmp (name, "bopt") == 0)
12928 mips_opts.nobopt = 0;
12930 else if (strcmp (name, "nobopt") == 0)
12932 mips_opts.nobopt = 1;
12934 else if (strcmp (name, "gp=default") == 0)
12935 mips_opts.gp32 = file_mips_gp32;
12936 else if (strcmp (name, "gp=32") == 0)
12937 mips_opts.gp32 = 1;
12938 else if (strcmp (name, "gp=64") == 0)
12940 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12941 as_warn (_("%s isa does not support 64-bit registers"),
12942 mips_cpu_info_from_isa (mips_opts.isa)->name);
12943 mips_opts.gp32 = 0;
12945 else if (strcmp (name, "fp=default") == 0)
12946 mips_opts.fp32 = file_mips_fp32;
12947 else if (strcmp (name, "fp=32") == 0)
12948 mips_opts.fp32 = 1;
12949 else if (strcmp (name, "fp=64") == 0)
12951 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12952 as_warn (_("%s isa does not support 64-bit floating point registers"),
12953 mips_cpu_info_from_isa (mips_opts.isa)->name);
12954 mips_opts.fp32 = 0;
12956 else if (strcmp (name, "softfloat") == 0)
12957 mips_opts.soft_float = 1;
12958 else if (strcmp (name, "hardfloat") == 0)
12959 mips_opts.soft_float = 0;
12960 else if (strcmp (name, "singlefloat") == 0)
12961 mips_opts.single_float = 1;
12962 else if (strcmp (name, "doublefloat") == 0)
12963 mips_opts.single_float = 0;
12964 else if (strcmp (name, "mips16") == 0
12965 || strcmp (name, "MIPS-16") == 0)
12966 mips_opts.mips16 = 1;
12967 else if (strcmp (name, "nomips16") == 0
12968 || strcmp (name, "noMIPS-16") == 0)
12969 mips_opts.mips16 = 0;
12970 else if (strcmp (name, "smartmips") == 0)
12972 if (!ISA_SUPPORTS_SMARTMIPS)
12973 as_warn (_("%s ISA does not support SmartMIPS ASE"),
12974 mips_cpu_info_from_isa (mips_opts.isa)->name);
12975 mips_opts.ase_smartmips = 1;
12977 else if (strcmp (name, "nosmartmips") == 0)
12978 mips_opts.ase_smartmips = 0;
12979 else if (strcmp (name, "mips3d") == 0)
12980 mips_opts.ase_mips3d = 1;
12981 else if (strcmp (name, "nomips3d") == 0)
12982 mips_opts.ase_mips3d = 0;
12983 else if (strcmp (name, "mdmx") == 0)
12984 mips_opts.ase_mdmx = 1;
12985 else if (strcmp (name, "nomdmx") == 0)
12986 mips_opts.ase_mdmx = 0;
12987 else if (strcmp (name, "dsp") == 0)
12989 if (!ISA_SUPPORTS_DSP_ASE)
12990 as_warn (_("%s ISA does not support DSP ASE"),
12991 mips_cpu_info_from_isa (mips_opts.isa)->name);
12992 mips_opts.ase_dsp = 1;
12993 mips_opts.ase_dspr2 = 0;
12995 else if (strcmp (name, "nodsp") == 0)
12997 mips_opts.ase_dsp = 0;
12998 mips_opts.ase_dspr2 = 0;
13000 else if (strcmp (name, "dspr2") == 0)
13002 if (!ISA_SUPPORTS_DSPR2_ASE)
13003 as_warn (_("%s ISA does not support DSP R2 ASE"),
13004 mips_cpu_info_from_isa (mips_opts.isa)->name);
13005 mips_opts.ase_dspr2 = 1;
13006 mips_opts.ase_dsp = 1;
13008 else if (strcmp (name, "nodspr2") == 0)
13010 mips_opts.ase_dspr2 = 0;
13011 mips_opts.ase_dsp = 0;
13013 else if (strcmp (name, "mt") == 0)
13015 if (!ISA_SUPPORTS_MT_ASE)
13016 as_warn (_("%s ISA does not support MT ASE"),
13017 mips_cpu_info_from_isa (mips_opts.isa)->name);
13018 mips_opts.ase_mt = 1;
13020 else if (strcmp (name, "nomt") == 0)
13021 mips_opts.ase_mt = 0;
13022 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13026 /* Permit the user to change the ISA and architecture on the fly.
13027 Needless to say, misuse can cause serious problems. */
13028 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13031 mips_opts.isa = file_mips_isa;
13032 mips_opts.arch = file_mips_arch;
13034 else if (strncmp (name, "arch=", 5) == 0)
13036 const struct mips_cpu_info *p;
13038 p = mips_parse_cpu("internal use", name + 5);
13040 as_bad (_("unknown architecture %s"), name + 5);
13043 mips_opts.arch = p->cpu;
13044 mips_opts.isa = p->isa;
13047 else if (strncmp (name, "mips", 4) == 0)
13049 const struct mips_cpu_info *p;
13051 p = mips_parse_cpu("internal use", name);
13053 as_bad (_("unknown ISA level %s"), name + 4);
13056 mips_opts.arch = p->cpu;
13057 mips_opts.isa = p->isa;
13061 as_bad (_("unknown ISA or architecture %s"), name);
13063 switch (mips_opts.isa)
13071 mips_opts.gp32 = 1;
13072 mips_opts.fp32 = 1;
13079 mips_opts.gp32 = 0;
13080 mips_opts.fp32 = 0;
13083 as_bad (_("unknown ISA level %s"), name + 4);
13088 mips_opts.gp32 = file_mips_gp32;
13089 mips_opts.fp32 = file_mips_fp32;
13092 else if (strcmp (name, "autoextend") == 0)
13093 mips_opts.noautoextend = 0;
13094 else if (strcmp (name, "noautoextend") == 0)
13095 mips_opts.noautoextend = 1;
13096 else if (strcmp (name, "push") == 0)
13098 struct mips_option_stack *s;
13100 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13101 s->next = mips_opts_stack;
13102 s->options = mips_opts;
13103 mips_opts_stack = s;
13105 else if (strcmp (name, "pop") == 0)
13107 struct mips_option_stack *s;
13109 s = mips_opts_stack;
13111 as_bad (_(".set pop with no .set push"));
13114 /* If we're changing the reorder mode we need to handle
13115 delay slots correctly. */
13116 if (s->options.noreorder && ! mips_opts.noreorder)
13117 start_noreorder ();
13118 else if (! s->options.noreorder && mips_opts.noreorder)
13121 mips_opts = s->options;
13122 mips_opts_stack = s->next;
13126 else if (strcmp (name, "sym32") == 0)
13127 mips_opts.sym32 = TRUE;
13128 else if (strcmp (name, "nosym32") == 0)
13129 mips_opts.sym32 = FALSE;
13130 else if (strchr (name, ','))
13132 /* Generic ".set" directive; use the generic handler. */
13133 *input_line_pointer = ch;
13134 input_line_pointer = name;
13140 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13142 *input_line_pointer = ch;
13143 demand_empty_rest_of_line ();
13146 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13147 .option pic2. It means to generate SVR4 PIC calls. */
13150 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13152 mips_pic = SVR4_PIC;
13153 mips_abicalls = TRUE;
13155 if (g_switch_seen && g_switch_value != 0)
13156 as_warn (_("-G may not be used with SVR4 PIC code"));
13157 g_switch_value = 0;
13159 bfd_set_gp_size (stdoutput, 0);
13160 demand_empty_rest_of_line ();
13163 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13164 PIC code. It sets the $gp register for the function based on the
13165 function address, which is in the register named in the argument.
13166 This uses a relocation against _gp_disp, which is handled specially
13167 by the linker. The result is:
13168 lui $gp,%hi(_gp_disp)
13169 addiu $gp,$gp,%lo(_gp_disp)
13170 addu $gp,$gp,.cpload argument
13171 The .cpload argument is normally $25 == $t9.
13173 The -mno-shared option changes this to:
13174 lui $gp,%hi(__gnu_local_gp)
13175 addiu $gp,$gp,%lo(__gnu_local_gp)
13176 and the argument is ignored. This saves an instruction, but the
13177 resulting code is not position independent; it uses an absolute
13178 address for __gnu_local_gp. Thus code assembled with -mno-shared
13179 can go into an ordinary executable, but not into a shared library. */
13182 s_cpload (int ignore ATTRIBUTE_UNUSED)
13188 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13189 .cpload is ignored. */
13190 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13196 /* .cpload should be in a .set noreorder section. */
13197 if (mips_opts.noreorder == 0)
13198 as_warn (_(".cpload not in noreorder section"));
13200 reg = tc_get_register (0);
13202 /* If we need to produce a 64-bit address, we are better off using
13203 the default instruction sequence. */
13204 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13206 ex.X_op = O_symbol;
13207 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13209 ex.X_op_symbol = NULL;
13210 ex.X_add_number = 0;
13212 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13213 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13216 macro_build_lui (&ex, mips_gp_register);
13217 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13218 mips_gp_register, BFD_RELOC_LO16);
13220 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13221 mips_gp_register, reg);
13224 demand_empty_rest_of_line ();
13227 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13228 .cpsetup $reg1, offset|$reg2, label
13230 If offset is given, this results in:
13231 sd $gp, offset($sp)
13232 lui $gp, %hi(%neg(%gp_rel(label)))
13233 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13234 daddu $gp, $gp, $reg1
13236 If $reg2 is given, this results in:
13237 daddu $reg2, $gp, $0
13238 lui $gp, %hi(%neg(%gp_rel(label)))
13239 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13240 daddu $gp, $gp, $reg1
13241 $reg1 is normally $25 == $t9.
13243 The -mno-shared option replaces the last three instructions with
13245 addiu $gp,$gp,%lo(_gp) */
13248 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13250 expressionS ex_off;
13251 expressionS ex_sym;
13254 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13255 We also need NewABI support. */
13256 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13262 reg1 = tc_get_register (0);
13263 SKIP_WHITESPACE ();
13264 if (*input_line_pointer != ',')
13266 as_bad (_("missing argument separator ',' for .cpsetup"));
13270 ++input_line_pointer;
13271 SKIP_WHITESPACE ();
13272 if (*input_line_pointer == '$')
13274 mips_cpreturn_register = tc_get_register (0);
13275 mips_cpreturn_offset = -1;
13279 mips_cpreturn_offset = get_absolute_expression ();
13280 mips_cpreturn_register = -1;
13282 SKIP_WHITESPACE ();
13283 if (*input_line_pointer != ',')
13285 as_bad (_("missing argument separator ',' for .cpsetup"));
13289 ++input_line_pointer;
13290 SKIP_WHITESPACE ();
13291 expression (&ex_sym);
13294 if (mips_cpreturn_register == -1)
13296 ex_off.X_op = O_constant;
13297 ex_off.X_add_symbol = NULL;
13298 ex_off.X_op_symbol = NULL;
13299 ex_off.X_add_number = mips_cpreturn_offset;
13301 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13302 BFD_RELOC_LO16, SP);
13305 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13306 mips_gp_register, 0);
13308 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13310 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13311 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13314 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13315 mips_gp_register, -1, BFD_RELOC_GPREL16,
13316 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13318 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13319 mips_gp_register, reg1);
13325 ex.X_op = O_symbol;
13326 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13327 ex.X_op_symbol = NULL;
13328 ex.X_add_number = 0;
13330 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13331 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13333 macro_build_lui (&ex, mips_gp_register);
13334 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13335 mips_gp_register, BFD_RELOC_LO16);
13340 demand_empty_rest_of_line ();
13344 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13346 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13347 .cplocal is ignored. */
13348 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13354 mips_gp_register = tc_get_register (0);
13355 demand_empty_rest_of_line ();
13358 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13359 offset from $sp. The offset is remembered, and after making a PIC
13360 call $gp is restored from that location. */
13363 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13367 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13368 .cprestore is ignored. */
13369 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13375 mips_cprestore_offset = get_absolute_expression ();
13376 mips_cprestore_valid = 1;
13378 ex.X_op = O_constant;
13379 ex.X_add_symbol = NULL;
13380 ex.X_op_symbol = NULL;
13381 ex.X_add_number = mips_cprestore_offset;
13384 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13385 SP, HAVE_64BIT_ADDRESSES);
13388 demand_empty_rest_of_line ();
13391 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13392 was given in the preceding .cpsetup, it results in:
13393 ld $gp, offset($sp)
13395 If a register $reg2 was given there, it results in:
13396 daddu $gp, $reg2, $0 */
13399 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13403 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13404 We also need NewABI support. */
13405 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13412 if (mips_cpreturn_register == -1)
13414 ex.X_op = O_constant;
13415 ex.X_add_symbol = NULL;
13416 ex.X_op_symbol = NULL;
13417 ex.X_add_number = mips_cpreturn_offset;
13419 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13422 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13423 mips_cpreturn_register, 0);
13426 demand_empty_rest_of_line ();
13429 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13430 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13431 use in DWARF debug information. */
13434 s_dtprel_internal (size_t bytes)
13441 if (ex.X_op != O_symbol)
13443 as_bad (_("Unsupported use of %s"), (bytes == 8
13446 ignore_rest_of_line ();
13449 p = frag_more (bytes);
13450 md_number_to_chars (p, 0, bytes);
13451 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13453 ? BFD_RELOC_MIPS_TLS_DTPREL64
13454 : BFD_RELOC_MIPS_TLS_DTPREL32));
13456 demand_empty_rest_of_line ();
13459 /* Handle .dtprelword. */
13462 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13464 s_dtprel_internal (4);
13467 /* Handle .dtpreldword. */
13470 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13472 s_dtprel_internal (8);
13475 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13476 code. It sets the offset to use in gp_rel relocations. */
13479 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13481 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13482 We also need NewABI support. */
13483 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13489 mips_gprel_offset = get_absolute_expression ();
13491 demand_empty_rest_of_line ();
13494 /* Handle the .gpword pseudo-op. This is used when generating PIC
13495 code. It generates a 32 bit GP relative reloc. */
13498 s_gpword (int ignore ATTRIBUTE_UNUSED)
13500 segment_info_type *si;
13501 struct insn_label_list *l;
13506 /* When not generating PIC code, this is treated as .word. */
13507 if (mips_pic != SVR4_PIC)
13513 si = seg_info (now_seg);
13514 l = si->label_list;
13515 label = l != NULL ? l->label : NULL;
13516 mips_emit_delays ();
13518 mips_align (2, 0, label);
13519 mips_clear_insn_labels ();
13523 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13525 as_bad (_("Unsupported use of .gpword"));
13526 ignore_rest_of_line ();
13530 md_number_to_chars (p, 0, 4);
13531 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13532 BFD_RELOC_GPREL32);
13534 demand_empty_rest_of_line ();
13538 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13540 segment_info_type *si;
13541 struct insn_label_list *l;
13546 /* When not generating PIC code, this is treated as .dword. */
13547 if (mips_pic != SVR4_PIC)
13553 si = seg_info (now_seg);
13554 l = si->label_list;
13555 label = l != NULL ? l->label : NULL;
13556 mips_emit_delays ();
13558 mips_align (3, 0, label);
13559 mips_clear_insn_labels ();
13563 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13565 as_bad (_("Unsupported use of .gpdword"));
13566 ignore_rest_of_line ();
13570 md_number_to_chars (p, 0, 8);
13571 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13572 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13574 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13575 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13576 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13578 demand_empty_rest_of_line ();
13581 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13582 tables in SVR4 PIC code. */
13585 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13589 /* This is ignored when not generating SVR4 PIC code. */
13590 if (mips_pic != SVR4_PIC)
13596 /* Add $gp to the register named as an argument. */
13598 reg = tc_get_register (0);
13599 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13602 demand_empty_rest_of_line ();
13605 /* Handle the .insn pseudo-op. This marks instruction labels in
13606 mips16 mode. This permits the linker to handle them specially,
13607 such as generating jalx instructions when needed. We also make
13608 them odd for the duration of the assembly, in order to generate the
13609 right sort of code. We will make them even in the adjust_symtab
13610 routine, while leaving them marked. This is convenient for the
13611 debugger and the disassembler. The linker knows to make them odd
13615 s_insn (int ignore ATTRIBUTE_UNUSED)
13617 mips16_mark_labels ();
13619 demand_empty_rest_of_line ();
13622 /* Handle a .stabn directive. We need these in order to mark a label
13623 as being a mips16 text label correctly. Sometimes the compiler
13624 will emit a label, followed by a .stabn, and then switch sections.
13625 If the label and .stabn are in mips16 mode, then the label is
13626 really a mips16 text label. */
13629 s_mips_stab (int type)
13632 mips16_mark_labels ();
13637 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13640 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13647 name = input_line_pointer;
13648 c = get_symbol_end ();
13649 symbolP = symbol_find_or_make (name);
13650 S_SET_WEAK (symbolP);
13651 *input_line_pointer = c;
13653 SKIP_WHITESPACE ();
13655 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13657 if (S_IS_DEFINED (symbolP))
13659 as_bad (_("ignoring attempt to redefine symbol %s"),
13660 S_GET_NAME (symbolP));
13661 ignore_rest_of_line ();
13665 if (*input_line_pointer == ',')
13667 ++input_line_pointer;
13668 SKIP_WHITESPACE ();
13672 if (exp.X_op != O_symbol)
13674 as_bad (_("bad .weakext directive"));
13675 ignore_rest_of_line ();
13678 symbol_set_value_expression (symbolP, &exp);
13681 demand_empty_rest_of_line ();
13684 /* Parse a register string into a number. Called from the ECOFF code
13685 to parse .frame. The argument is non-zero if this is the frame
13686 register, so that we can record it in mips_frame_reg. */
13689 tc_get_register (int frame)
13693 SKIP_WHITESPACE ();
13694 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13698 mips_frame_reg = reg != 0 ? reg : SP;
13699 mips_frame_reg_valid = 1;
13700 mips_cprestore_valid = 0;
13706 md_section_align (asection *seg, valueT addr)
13708 int align = bfd_get_section_alignment (stdoutput, seg);
13712 /* We don't need to align ELF sections to the full alignment.
13713 However, Irix 5 may prefer that we align them at least to a 16
13714 byte boundary. We don't bother to align the sections if we
13715 are targeted for an embedded system. */
13716 if (strncmp (TARGET_OS, "elf", 3) == 0)
13722 return ((addr + (1 << align) - 1) & (-1 << align));
13725 /* Utility routine, called from above as well. If called while the
13726 input file is still being read, it's only an approximation. (For
13727 example, a symbol may later become defined which appeared to be
13728 undefined earlier.) */
13731 nopic_need_relax (symbolS *sym, int before_relaxing)
13736 if (g_switch_value > 0)
13738 const char *symname;
13741 /* Find out whether this symbol can be referenced off the $gp
13742 register. It can be if it is smaller than the -G size or if
13743 it is in the .sdata or .sbss section. Certain symbols can
13744 not be referenced off the $gp, although it appears as though
13746 symname = S_GET_NAME (sym);
13747 if (symname != (const char *) NULL
13748 && (strcmp (symname, "eprol") == 0
13749 || strcmp (symname, "etext") == 0
13750 || strcmp (symname, "_gp") == 0
13751 || strcmp (symname, "edata") == 0
13752 || strcmp (symname, "_fbss") == 0
13753 || strcmp (symname, "_fdata") == 0
13754 || strcmp (symname, "_ftext") == 0
13755 || strcmp (symname, "end") == 0
13756 || strcmp (symname, "_gp_disp") == 0))
13758 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13760 #ifndef NO_ECOFF_DEBUGGING
13761 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13762 && (symbol_get_obj (sym)->ecoff_extern_size
13763 <= g_switch_value))
13765 /* We must defer this decision until after the whole
13766 file has been read, since there might be a .extern
13767 after the first use of this symbol. */
13768 || (before_relaxing
13769 #ifndef NO_ECOFF_DEBUGGING
13770 && symbol_get_obj (sym)->ecoff_extern_size == 0
13772 && S_GET_VALUE (sym) == 0)
13773 || (S_GET_VALUE (sym) != 0
13774 && S_GET_VALUE (sym) <= g_switch_value)))
13778 const char *segname;
13780 segname = segment_name (S_GET_SEGMENT (sym));
13781 gas_assert (strcmp (segname, ".lit8") != 0
13782 && strcmp (segname, ".lit4") != 0);
13783 change = (strcmp (segname, ".sdata") != 0
13784 && strcmp (segname, ".sbss") != 0
13785 && strncmp (segname, ".sdata.", 7) != 0
13786 && strncmp (segname, ".sbss.", 6) != 0
13787 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13788 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13793 /* We are not optimizing for the $gp register. */
13798 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13801 pic_need_relax (symbolS *sym, asection *segtype)
13805 /* Handle the case of a symbol equated to another symbol. */
13806 while (symbol_equated_reloc_p (sym))
13810 /* It's possible to get a loop here in a badly written program. */
13811 n = symbol_get_value_expression (sym)->X_add_symbol;
13817 if (symbol_section_p (sym))
13820 symsec = S_GET_SEGMENT (sym);
13822 /* This must duplicate the test in adjust_reloc_syms. */
13823 return (symsec != &bfd_und_section
13824 && symsec != &bfd_abs_section
13825 && !bfd_is_com_section (symsec)
13826 && !s_is_linkonce (sym, segtype)
13828 /* A global or weak symbol is treated as external. */
13829 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13835 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13836 extended opcode. SEC is the section the frag is in. */
13839 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13842 const struct mips16_immed_operand *op;
13844 int mintiny, maxtiny;
13848 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13850 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13853 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13854 op = mips16_immed_operands;
13855 while (op->type != type)
13858 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13863 if (type == '<' || type == '>' || type == '[' || type == ']')
13866 maxtiny = 1 << op->nbits;
13871 maxtiny = (1 << op->nbits) - 1;
13876 mintiny = - (1 << (op->nbits - 1));
13877 maxtiny = (1 << (op->nbits - 1)) - 1;
13880 sym_frag = symbol_get_frag (fragp->fr_symbol);
13881 val = S_GET_VALUE (fragp->fr_symbol);
13882 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13888 /* We won't have the section when we are called from
13889 mips_relax_frag. However, we will always have been called
13890 from md_estimate_size_before_relax first. If this is a
13891 branch to a different section, we mark it as such. If SEC is
13892 NULL, and the frag is not marked, then it must be a branch to
13893 the same section. */
13896 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13901 /* Must have been called from md_estimate_size_before_relax. */
13904 fragp->fr_subtype =
13905 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13907 /* FIXME: We should support this, and let the linker
13908 catch branches and loads that are out of range. */
13909 as_bad_where (fragp->fr_file, fragp->fr_line,
13910 _("unsupported PC relative reference to different section"));
13914 if (fragp != sym_frag && sym_frag->fr_address == 0)
13915 /* Assume non-extended on the first relaxation pass.
13916 The address we have calculated will be bogus if this is
13917 a forward branch to another frag, as the forward frag
13918 will have fr_address == 0. */
13922 /* In this case, we know for sure that the symbol fragment is in
13923 the same section. If the relax_marker of the symbol fragment
13924 differs from the relax_marker of this fragment, we have not
13925 yet adjusted the symbol fragment fr_address. We want to add
13926 in STRETCH in order to get a better estimate of the address.
13927 This particularly matters because of the shift bits. */
13929 && sym_frag->relax_marker != fragp->relax_marker)
13933 /* Adjust stretch for any alignment frag. Note that if have
13934 been expanding the earlier code, the symbol may be
13935 defined in what appears to be an earlier frag. FIXME:
13936 This doesn't handle the fr_subtype field, which specifies
13937 a maximum number of bytes to skip when doing an
13939 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13941 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13944 stretch = - ((- stretch)
13945 & ~ ((1 << (int) f->fr_offset) - 1));
13947 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13956 addr = fragp->fr_address + fragp->fr_fix;
13958 /* The base address rules are complicated. The base address of
13959 a branch is the following instruction. The base address of a
13960 PC relative load or add is the instruction itself, but if it
13961 is in a delay slot (in which case it can not be extended) use
13962 the address of the instruction whose delay slot it is in. */
13963 if (type == 'p' || type == 'q')
13967 /* If we are currently assuming that this frag should be
13968 extended, then, the current address is two bytes
13970 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13973 /* Ignore the low bit in the target, since it will be set
13974 for a text label. */
13975 if ((val & 1) != 0)
13978 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13980 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13983 val -= addr & ~ ((1 << op->shift) - 1);
13985 /* Branch offsets have an implicit 0 in the lowest bit. */
13986 if (type == 'p' || type == 'q')
13989 /* If any of the shifted bits are set, we must use an extended
13990 opcode. If the address depends on the size of this
13991 instruction, this can lead to a loop, so we arrange to always
13992 use an extended opcode. We only check this when we are in
13993 the main relaxation loop, when SEC is NULL. */
13994 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13996 fragp->fr_subtype =
13997 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14001 /* If we are about to mark a frag as extended because the value
14002 is precisely maxtiny + 1, then there is a chance of an
14003 infinite loop as in the following code:
14008 In this case when the la is extended, foo is 0x3fc bytes
14009 away, so the la can be shrunk, but then foo is 0x400 away, so
14010 the la must be extended. To avoid this loop, we mark the
14011 frag as extended if it was small, and is about to become
14012 extended with a value of maxtiny + 1. */
14013 if (val == ((maxtiny + 1) << op->shift)
14014 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14017 fragp->fr_subtype =
14018 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14022 else if (symsec != absolute_section && sec != NULL)
14023 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14025 if ((val & ((1 << op->shift) - 1)) != 0
14026 || val < (mintiny << op->shift)
14027 || val > (maxtiny << op->shift))
14033 /* Compute the length of a branch sequence, and adjust the
14034 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14035 worst-case length is computed, with UPDATE being used to indicate
14036 whether an unconditional (-1), branch-likely (+1) or regular (0)
14037 branch is to be computed. */
14039 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14041 bfd_boolean toofar;
14045 && S_IS_DEFINED (fragp->fr_symbol)
14046 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14051 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14053 addr = fragp->fr_address + fragp->fr_fix + 4;
14057 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14060 /* If the symbol is not defined or it's in a different segment,
14061 assume the user knows what's going on and emit a short
14067 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14069 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14070 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14071 RELAX_BRANCH_LINK (fragp->fr_subtype),
14077 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14080 if (mips_pic != NO_PIC)
14082 /* Additional space for PIC loading of target address. */
14084 if (mips_opts.isa == ISA_MIPS1)
14085 /* Additional space for $at-stabilizing nop. */
14089 /* If branch is conditional. */
14090 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14097 /* Estimate the size of a frag before relaxing. Unless this is the
14098 mips16, we are not really relaxing here, and the final size is
14099 encoded in the subtype information. For the mips16, we have to
14100 decide whether we are using an extended opcode or not. */
14103 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14107 if (RELAX_BRANCH_P (fragp->fr_subtype))
14110 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14112 return fragp->fr_var;
14115 if (RELAX_MIPS16_P (fragp->fr_subtype))
14116 /* We don't want to modify the EXTENDED bit here; it might get us
14117 into infinite loops. We change it only in mips_relax_frag(). */
14118 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14120 if (mips_pic == NO_PIC)
14121 change = nopic_need_relax (fragp->fr_symbol, 0);
14122 else if (mips_pic == SVR4_PIC)
14123 change = pic_need_relax (fragp->fr_symbol, segtype);
14124 else if (mips_pic == VXWORKS_PIC)
14125 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14132 fragp->fr_subtype |= RELAX_USE_SECOND;
14133 return -RELAX_FIRST (fragp->fr_subtype);
14136 return -RELAX_SECOND (fragp->fr_subtype);
14139 /* This is called to see whether a reloc against a defined symbol
14140 should be converted into a reloc against a section. */
14143 mips_fix_adjustable (fixS *fixp)
14145 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14146 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14149 if (fixp->fx_addsy == NULL)
14152 /* If symbol SYM is in a mergeable section, relocations of the form
14153 SYM + 0 can usually be made section-relative. The mergeable data
14154 is then identified by the section offset rather than by the symbol.
14156 However, if we're generating REL LO16 relocations, the offset is split
14157 between the LO16 and parterning high part relocation. The linker will
14158 need to recalculate the complete offset in order to correctly identify
14161 The linker has traditionally not looked for the parterning high part
14162 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14163 placed anywhere. Rather than break backwards compatibility by changing
14164 this, it seems better not to force the issue, and instead keep the
14165 original symbol. This will work with either linker behavior. */
14166 if ((lo16_reloc_p (fixp->fx_r_type)
14167 || reloc_needs_lo_p (fixp->fx_r_type))
14168 && HAVE_IN_PLACE_ADDENDS
14169 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14172 /* There is no place to store an in-place offset for JALR relocations. */
14173 if (fixp->fx_r_type == BFD_RELOC_MIPS_JALR && HAVE_IN_PLACE_ADDENDS)
14177 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14178 to a floating-point stub. The same is true for non-R_MIPS16_26
14179 relocations against MIPS16 functions; in this case, the stub becomes
14180 the function's canonical address.
14182 Floating-point stubs are stored in unique .mips16.call.* or
14183 .mips16.fn.* sections. If a stub T for function F is in section S,
14184 the first relocation in section S must be against F; this is how the
14185 linker determines the target function. All relocations that might
14186 resolve to T must also be against F. We therefore have the following
14187 restrictions, which are given in an intentionally-redundant way:
14189 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14192 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14193 if that stub might be used.
14195 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14198 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14199 that stub might be used.
14201 There is a further restriction:
14203 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14204 on targets with in-place addends; the relocation field cannot
14205 encode the low bit.
14207 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14208 against a MIPS16 symbol.
14210 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14211 relocation against some symbol R, no relocation against R may be
14212 reduced. (Note that this deals with (2) as well as (1) because
14213 relocations against global symbols will never be reduced on ELF
14214 targets.) This approach is a little simpler than trying to detect
14215 stub sections, and gives the "all or nothing" per-symbol consistency
14216 that we have for MIPS16 symbols. */
14218 && fixp->fx_subsy == NULL
14219 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14220 || *symbol_get_tc (fixp->fx_addsy)))
14227 /* Translate internal representation of relocation info to BFD target
14231 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14233 static arelent *retval[4];
14235 bfd_reloc_code_real_type code;
14237 memset (retval, 0, sizeof(retval));
14238 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14239 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14240 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14241 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14243 if (fixp->fx_pcrel)
14245 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14247 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14248 Relocations want only the symbol offset. */
14249 reloc->addend = fixp->fx_addnumber + reloc->address;
14252 /* A gruesome hack which is a result of the gruesome gas
14253 reloc handling. What's worse, for COFF (as opposed to
14254 ECOFF), we might need yet another copy of reloc->address.
14255 See bfd_install_relocation. */
14256 reloc->addend += reloc->address;
14260 reloc->addend = fixp->fx_addnumber;
14262 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14263 entry to be used in the relocation's section offset. */
14264 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14266 reloc->address = reloc->addend;
14270 code = fixp->fx_r_type;
14272 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14273 if (reloc->howto == NULL)
14275 as_bad_where (fixp->fx_file, fixp->fx_line,
14276 _("Can not represent %s relocation in this object file format"),
14277 bfd_get_reloc_code_name (code));
14284 /* Relax a machine dependent frag. This returns the amount by which
14285 the current size of the frag should change. */
14288 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14290 if (RELAX_BRANCH_P (fragp->fr_subtype))
14292 offsetT old_var = fragp->fr_var;
14294 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14296 return fragp->fr_var - old_var;
14299 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14302 if (mips16_extended_frag (fragp, NULL, stretch))
14304 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14306 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14311 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14313 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14320 /* Convert a machine dependent frag. */
14323 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14325 if (RELAX_BRANCH_P (fragp->fr_subtype))
14328 unsigned long insn;
14332 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14334 if (target_big_endian)
14335 insn = bfd_getb32 (buf);
14337 insn = bfd_getl32 (buf);
14339 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14341 /* We generate a fixup instead of applying it right now
14342 because, if there are linker relaxations, we're going to
14343 need the relocations. */
14344 exp.X_op = O_symbol;
14345 exp.X_add_symbol = fragp->fr_symbol;
14346 exp.X_add_number = fragp->fr_offset;
14348 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14349 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14350 fixp->fx_file = fragp->fr_file;
14351 fixp->fx_line = fragp->fr_line;
14353 md_number_to_chars ((char *) buf, insn, 4);
14360 as_warn_where (fragp->fr_file, fragp->fr_line,
14361 _("relaxed out-of-range branch into a jump"));
14363 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14366 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14368 /* Reverse the branch. */
14369 switch ((insn >> 28) & 0xf)
14372 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14373 have the condition reversed by tweaking a single
14374 bit, and their opcodes all have 0x4???????. */
14375 gas_assert ((insn & 0xf1000000) == 0x41000000);
14376 insn ^= 0x00010000;
14380 /* bltz 0x04000000 bgez 0x04010000
14381 bltzal 0x04100000 bgezal 0x04110000 */
14382 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14383 insn ^= 0x00010000;
14387 /* beq 0x10000000 bne 0x14000000
14388 blez 0x18000000 bgtz 0x1c000000 */
14389 insn ^= 0x04000000;
14397 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14399 /* Clear the and-link bit. */
14400 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14402 /* bltzal 0x04100000 bgezal 0x04110000
14403 bltzall 0x04120000 bgezall 0x04130000 */
14404 insn &= ~0x00100000;
14407 /* Branch over the branch (if the branch was likely) or the
14408 full jump (not likely case). Compute the offset from the
14409 current instruction to branch to. */
14410 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14414 /* How many bytes in instructions we've already emitted? */
14415 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14416 /* How many bytes in instructions from here to the end? */
14417 i = fragp->fr_var - i;
14419 /* Convert to instruction count. */
14421 /* Branch counts from the next instruction. */
14424 /* Branch over the jump. */
14425 md_number_to_chars ((char *) buf, insn, 4);
14429 md_number_to_chars ((char *) buf, 0, 4);
14432 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14434 /* beql $0, $0, 2f */
14436 /* Compute the PC offset from the current instruction to
14437 the end of the variable frag. */
14438 /* How many bytes in instructions we've already emitted? */
14439 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14440 /* How many bytes in instructions from here to the end? */
14441 i = fragp->fr_var - i;
14442 /* Convert to instruction count. */
14444 /* Don't decrement i, because we want to branch over the
14448 md_number_to_chars ((char *) buf, insn, 4);
14451 md_number_to_chars ((char *) buf, 0, 4);
14456 if (mips_pic == NO_PIC)
14459 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14460 ? 0x0c000000 : 0x08000000);
14461 exp.X_op = O_symbol;
14462 exp.X_add_symbol = fragp->fr_symbol;
14463 exp.X_add_number = fragp->fr_offset;
14465 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14466 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14467 fixp->fx_file = fragp->fr_file;
14468 fixp->fx_line = fragp->fr_line;
14470 md_number_to_chars ((char *) buf, insn, 4);
14475 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14476 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
14477 exp.X_op = O_symbol;
14478 exp.X_add_symbol = fragp->fr_symbol;
14479 exp.X_add_number = fragp->fr_offset;
14481 if (fragp->fr_offset)
14483 exp.X_add_symbol = make_expr_symbol (&exp);
14484 exp.X_add_number = 0;
14487 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14488 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14489 fixp->fx_file = fragp->fr_file;
14490 fixp->fx_line = fragp->fr_line;
14492 md_number_to_chars ((char *) buf, insn, 4);
14495 if (mips_opts.isa == ISA_MIPS1)
14498 md_number_to_chars ((char *) buf, 0, 4);
14502 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14503 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14505 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14506 4, &exp, FALSE, BFD_RELOC_LO16);
14507 fixp->fx_file = fragp->fr_file;
14508 fixp->fx_line = fragp->fr_line;
14510 md_number_to_chars ((char *) buf, insn, 4);
14514 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14519 md_number_to_chars ((char *) buf, insn, 4);
14524 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14525 + fragp->fr_fix + fragp->fr_var);
14527 fragp->fr_fix += fragp->fr_var;
14532 if (RELAX_MIPS16_P (fragp->fr_subtype))
14535 const struct mips16_immed_operand *op;
14536 bfd_boolean small, ext;
14539 unsigned long insn;
14540 bfd_boolean use_extend;
14541 unsigned short extend;
14543 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14544 op = mips16_immed_operands;
14545 while (op->type != type)
14548 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14559 val = resolve_symbol_value (fragp->fr_symbol);
14564 addr = fragp->fr_address + fragp->fr_fix;
14566 /* The rules for the base address of a PC relative reloc are
14567 complicated; see mips16_extended_frag. */
14568 if (type == 'p' || type == 'q')
14573 /* Ignore the low bit in the target, since it will be
14574 set for a text label. */
14575 if ((val & 1) != 0)
14578 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14580 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14583 addr &= ~ (addressT) ((1 << op->shift) - 1);
14586 /* Make sure the section winds up with the alignment we have
14589 record_alignment (asec, op->shift);
14593 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14594 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14595 as_warn_where (fragp->fr_file, fragp->fr_line,
14596 _("extended instruction in delay slot"));
14598 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14600 if (target_big_endian)
14601 insn = bfd_getb16 (buf);
14603 insn = bfd_getl16 (buf);
14605 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14606 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14607 small, ext, &insn, &use_extend, &extend);
14611 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14612 fragp->fr_fix += 2;
14616 md_number_to_chars ((char *) buf, insn, 2);
14617 fragp->fr_fix += 2;
14625 first = RELAX_FIRST (fragp->fr_subtype);
14626 second = RELAX_SECOND (fragp->fr_subtype);
14627 fixp = (fixS *) fragp->fr_opcode;
14629 /* Possibly emit a warning if we've chosen the longer option. */
14630 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14631 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14633 const char *msg = macro_warning (fragp->fr_subtype);
14635 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14638 /* Go through all the fixups for the first sequence. Disable them
14639 (by marking them as done) if we're going to use the second
14640 sequence instead. */
14642 && fixp->fx_frag == fragp
14643 && fixp->fx_where < fragp->fr_fix - second)
14645 if (fragp->fr_subtype & RELAX_USE_SECOND)
14647 fixp = fixp->fx_next;
14650 /* Go through the fixups for the second sequence. Disable them if
14651 we're going to use the first sequence, otherwise adjust their
14652 addresses to account for the relaxation. */
14653 while (fixp && fixp->fx_frag == fragp)
14655 if (fragp->fr_subtype & RELAX_USE_SECOND)
14656 fixp->fx_where -= first;
14659 fixp = fixp->fx_next;
14662 /* Now modify the frag contents. */
14663 if (fragp->fr_subtype & RELAX_USE_SECOND)
14667 start = fragp->fr_literal + fragp->fr_fix - first - second;
14668 memmove (start, start + first, second);
14669 fragp->fr_fix -= first;
14672 fragp->fr_fix -= second;
14678 /* This function is called after the relocs have been generated.
14679 We've been storing mips16 text labels as odd. Here we convert them
14680 back to even for the convenience of the debugger. */
14683 mips_frob_file_after_relocs (void)
14686 unsigned int count, i;
14691 syms = bfd_get_outsymbols (stdoutput);
14692 count = bfd_get_symcount (stdoutput);
14693 for (i = 0; i < count; i++, syms++)
14695 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14696 && ((*syms)->value & 1) != 0)
14698 (*syms)->value &= ~1;
14699 /* If the symbol has an odd size, it was probably computed
14700 incorrectly, so adjust that as well. */
14701 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14702 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14709 /* This function is called whenever a label is defined. It is used
14710 when handling branch delays; if a branch has a label, we assume we
14711 can not move it. */
14714 mips_define_label (symbolS *sym)
14716 segment_info_type *si = seg_info (now_seg);
14717 struct insn_label_list *l;
14719 if (free_insn_labels == NULL)
14720 l = (struct insn_label_list *) xmalloc (sizeof *l);
14723 l = free_insn_labels;
14724 free_insn_labels = l->next;
14728 l->next = si->label_list;
14729 si->label_list = l;
14732 dwarf2_emit_label (sym);
14736 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14738 /* Some special processing for a MIPS ELF file. */
14741 mips_elf_final_processing (void)
14743 /* Write out the register information. */
14744 if (mips_abi != N64_ABI)
14748 s.ri_gprmask = mips_gprmask;
14749 s.ri_cprmask[0] = mips_cprmask[0];
14750 s.ri_cprmask[1] = mips_cprmask[1];
14751 s.ri_cprmask[2] = mips_cprmask[2];
14752 s.ri_cprmask[3] = mips_cprmask[3];
14753 /* The gp_value field is set by the MIPS ELF backend. */
14755 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14756 ((Elf32_External_RegInfo *)
14757 mips_regmask_frag));
14761 Elf64_Internal_RegInfo s;
14763 s.ri_gprmask = mips_gprmask;
14765 s.ri_cprmask[0] = mips_cprmask[0];
14766 s.ri_cprmask[1] = mips_cprmask[1];
14767 s.ri_cprmask[2] = mips_cprmask[2];
14768 s.ri_cprmask[3] = mips_cprmask[3];
14769 /* The gp_value field is set by the MIPS ELF backend. */
14771 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14772 ((Elf64_External_RegInfo *)
14773 mips_regmask_frag));
14776 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14777 sort of BFD interface for this. */
14778 if (mips_any_noreorder)
14779 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14780 if (mips_pic != NO_PIC)
14782 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14783 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14786 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14788 /* Set MIPS ELF flags for ASEs. */
14789 /* We may need to define a new flag for DSP ASE, and set this flag when
14790 file_ase_dsp is true. */
14791 /* Same for DSP R2. */
14792 /* We may need to define a new flag for MT ASE, and set this flag when
14793 file_ase_mt is true. */
14794 if (file_ase_mips16)
14795 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14796 #if 0 /* XXX FIXME */
14797 if (file_ase_mips3d)
14798 elf_elfheader (stdoutput)->e_flags |= ???;
14801 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14803 /* Set the MIPS ELF ABI flags. */
14804 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14805 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14806 else if (mips_abi == O64_ABI)
14807 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14808 else if (mips_abi == EABI_ABI)
14810 if (!file_mips_gp32)
14811 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14813 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14815 else if (mips_abi == N32_ABI)
14816 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14818 /* Nothing to do for N64_ABI. */
14820 if (mips_32bitmode)
14821 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14823 #if 0 /* XXX FIXME */
14824 /* 32 bit code with 64 bit FP registers. */
14825 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14826 elf_elfheader (stdoutput)->e_flags |= ???;
14830 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14832 typedef struct proc {
14834 symbolS *func_end_sym;
14835 unsigned long reg_mask;
14836 unsigned long reg_offset;
14837 unsigned long fpreg_mask;
14838 unsigned long fpreg_offset;
14839 unsigned long frame_offset;
14840 unsigned long frame_reg;
14841 unsigned long pc_reg;
14844 static procS cur_proc;
14845 static procS *cur_proc_ptr;
14846 static int numprocs;
14848 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14852 mips_nop_opcode (void)
14854 return seg_info (now_seg)->tc_segment_info_data.mips16;
14857 /* Fill in an rs_align_code fragment. This only needs to do something
14858 for MIPS16 code, where 0 is not a nop. */
14861 mips_handle_align (fragS *fragp)
14864 int bytes, size, excess;
14867 if (fragp->fr_type != rs_align_code)
14870 p = fragp->fr_literal + fragp->fr_fix;
14873 opcode = mips16_nop_insn.insn_opcode;
14878 opcode = nop_insn.insn_opcode;
14882 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14883 excess = bytes % size;
14886 /* If we're not inserting a whole number of instructions,
14887 pad the end of the fixed part of the frag with zeros. */
14888 memset (p, 0, excess);
14890 fragp->fr_fix += excess;
14893 md_number_to_chars (p, opcode, size);
14894 fragp->fr_var = size;
14898 md_obj_begin (void)
14905 /* Check for premature end, nesting errors, etc. */
14907 as_warn (_("missing .end at end of assembly"));
14916 if (*input_line_pointer == '-')
14918 ++input_line_pointer;
14921 if (!ISDIGIT (*input_line_pointer))
14922 as_bad (_("expected simple number"));
14923 if (input_line_pointer[0] == '0')
14925 if (input_line_pointer[1] == 'x')
14927 input_line_pointer += 2;
14928 while (ISXDIGIT (*input_line_pointer))
14931 val |= hex_value (*input_line_pointer++);
14933 return negative ? -val : val;
14937 ++input_line_pointer;
14938 while (ISDIGIT (*input_line_pointer))
14941 val |= *input_line_pointer++ - '0';
14943 return negative ? -val : val;
14946 if (!ISDIGIT (*input_line_pointer))
14948 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14949 *input_line_pointer, *input_line_pointer);
14950 as_warn (_("invalid number"));
14953 while (ISDIGIT (*input_line_pointer))
14956 val += *input_line_pointer++ - '0';
14958 return negative ? -val : val;
14961 /* The .file directive; just like the usual .file directive, but there
14962 is an initial number which is the ECOFF file index. In the non-ECOFF
14963 case .file implies DWARF-2. */
14966 s_mips_file (int x ATTRIBUTE_UNUSED)
14968 static int first_file_directive = 0;
14970 if (ECOFF_DEBUGGING)
14979 filename = dwarf2_directive_file (0);
14981 /* Versions of GCC up to 3.1 start files with a ".file"
14982 directive even for stabs output. Make sure that this
14983 ".file" is handled. Note that you need a version of GCC
14984 after 3.1 in order to support DWARF-2 on MIPS. */
14985 if (filename != NULL && ! first_file_directive)
14987 (void) new_logical_line (filename, -1);
14988 s_app_file_string (filename, 0);
14990 first_file_directive = 1;
14994 /* The .loc directive, implying DWARF-2. */
14997 s_mips_loc (int x ATTRIBUTE_UNUSED)
14999 if (!ECOFF_DEBUGGING)
15000 dwarf2_directive_loc (0);
15003 /* The .end directive. */
15006 s_mips_end (int x ATTRIBUTE_UNUSED)
15010 /* Following functions need their own .frame and .cprestore directives. */
15011 mips_frame_reg_valid = 0;
15012 mips_cprestore_valid = 0;
15014 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15017 demand_empty_rest_of_line ();
15022 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15023 as_warn (_(".end not in text section"));
15027 as_warn (_(".end directive without a preceding .ent directive."));
15028 demand_empty_rest_of_line ();
15034 gas_assert (S_GET_NAME (p));
15035 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15036 as_warn (_(".end symbol does not match .ent symbol."));
15038 if (debug_type == DEBUG_STABS)
15039 stabs_generate_asm_endfunc (S_GET_NAME (p),
15043 as_warn (_(".end directive missing or unknown symbol"));
15046 /* Create an expression to calculate the size of the function. */
15047 if (p && cur_proc_ptr)
15049 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15050 expressionS *exp = xmalloc (sizeof (expressionS));
15053 exp->X_op = O_subtract;
15054 exp->X_add_symbol = symbol_temp_new_now ();
15055 exp->X_op_symbol = p;
15056 exp->X_add_number = 0;
15058 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15061 /* Generate a .pdr section. */
15062 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15064 segT saved_seg = now_seg;
15065 subsegT saved_subseg = now_subseg;
15069 #ifdef md_flush_pending_output
15070 md_flush_pending_output ();
15073 gas_assert (pdr_seg);
15074 subseg_set (pdr_seg, 0);
15076 /* Write the symbol. */
15077 exp.X_op = O_symbol;
15078 exp.X_add_symbol = p;
15079 exp.X_add_number = 0;
15080 emit_expr (&exp, 4);
15082 fragp = frag_more (7 * 4);
15084 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15085 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15086 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15087 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15088 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15089 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15090 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15092 subseg_set (saved_seg, saved_subseg);
15094 #endif /* OBJ_ELF */
15096 cur_proc_ptr = NULL;
15099 /* The .aent and .ent directives. */
15102 s_mips_ent (int aent)
15106 symbolP = get_symbol ();
15107 if (*input_line_pointer == ',')
15108 ++input_line_pointer;
15109 SKIP_WHITESPACE ();
15110 if (ISDIGIT (*input_line_pointer)
15111 || *input_line_pointer == '-')
15114 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15115 as_warn (_(".ent or .aent not in text section."));
15117 if (!aent && cur_proc_ptr)
15118 as_warn (_("missing .end"));
15122 /* This function needs its own .frame and .cprestore directives. */
15123 mips_frame_reg_valid = 0;
15124 mips_cprestore_valid = 0;
15126 cur_proc_ptr = &cur_proc;
15127 memset (cur_proc_ptr, '\0', sizeof (procS));
15129 cur_proc_ptr->func_sym = symbolP;
15133 if (debug_type == DEBUG_STABS)
15134 stabs_generate_asm_func (S_GET_NAME (symbolP),
15135 S_GET_NAME (symbolP));
15138 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15140 demand_empty_rest_of_line ();
15143 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15144 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15145 s_mips_frame is used so that we can set the PDR information correctly.
15146 We can't use the ecoff routines because they make reference to the ecoff
15147 symbol table (in the mdebug section). */
15150 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15153 if (IS_ELF && !ECOFF_DEBUGGING)
15157 if (cur_proc_ptr == (procS *) NULL)
15159 as_warn (_(".frame outside of .ent"));
15160 demand_empty_rest_of_line ();
15164 cur_proc_ptr->frame_reg = tc_get_register (1);
15166 SKIP_WHITESPACE ();
15167 if (*input_line_pointer++ != ','
15168 || get_absolute_expression_and_terminator (&val) != ',')
15170 as_warn (_("Bad .frame directive"));
15171 --input_line_pointer;
15172 demand_empty_rest_of_line ();
15176 cur_proc_ptr->frame_offset = val;
15177 cur_proc_ptr->pc_reg = tc_get_register (0);
15179 demand_empty_rest_of_line ();
15182 #endif /* OBJ_ELF */
15186 /* The .fmask and .mask directives. If the mdebug section is present
15187 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15188 embedded targets, s_mips_mask is used so that we can set the PDR
15189 information correctly. We can't use the ecoff routines because they
15190 make reference to the ecoff symbol table (in the mdebug section). */
15193 s_mips_mask (int reg_type)
15196 if (IS_ELF && !ECOFF_DEBUGGING)
15200 if (cur_proc_ptr == (procS *) NULL)
15202 as_warn (_(".mask/.fmask outside of .ent"));
15203 demand_empty_rest_of_line ();
15207 if (get_absolute_expression_and_terminator (&mask) != ',')
15209 as_warn (_("Bad .mask/.fmask directive"));
15210 --input_line_pointer;
15211 demand_empty_rest_of_line ();
15215 off = get_absolute_expression ();
15217 if (reg_type == 'F')
15219 cur_proc_ptr->fpreg_mask = mask;
15220 cur_proc_ptr->fpreg_offset = off;
15224 cur_proc_ptr->reg_mask = mask;
15225 cur_proc_ptr->reg_offset = off;
15228 demand_empty_rest_of_line ();
15231 #endif /* OBJ_ELF */
15232 s_ignore (reg_type);
15235 /* A table describing all the processors gas knows about. Names are
15236 matched in the order listed.
15238 To ease comparison, please keep this table in the same order as
15239 gcc's mips_cpu_info_table[]. */
15240 static const struct mips_cpu_info mips_cpu_info_table[] =
15242 /* Entries for generic ISAs */
15243 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15244 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15245 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15246 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15247 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15248 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15249 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15250 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15251 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15254 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15255 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15256 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15259 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15262 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15263 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15264 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15265 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15266 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15267 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15268 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15269 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15270 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15271 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15272 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15273 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15274 /* ST Microelectronics Loongson 2E and 2F cores */
15275 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15276 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15279 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15280 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15281 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15282 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15283 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15284 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15285 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15286 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15287 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15288 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15289 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15290 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15291 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15292 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15293 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15296 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15297 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15298 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15299 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15301 /* MIPS 32 Release 2 */
15302 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15303 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15304 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15305 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15306 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15307 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15308 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15309 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15310 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15311 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15312 /* Deprecated forms of the above. */
15313 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15314 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15315 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15316 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15317 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15318 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15319 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15320 /* Deprecated forms of the above. */
15321 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15322 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15323 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15324 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15325 ISA_MIPS32R2, CPU_MIPS32R2 },
15326 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15327 ISA_MIPS32R2, CPU_MIPS32R2 },
15328 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15329 ISA_MIPS32R2, CPU_MIPS32R2 },
15330 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15331 ISA_MIPS32R2, CPU_MIPS32R2 },
15332 /* Deprecated forms of the above. */
15333 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15334 ISA_MIPS32R2, CPU_MIPS32R2 },
15335 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15336 ISA_MIPS32R2, CPU_MIPS32R2 },
15337 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15338 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15339 ISA_MIPS32R2, CPU_MIPS32R2 },
15340 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15341 ISA_MIPS32R2, CPU_MIPS32R2 },
15342 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15343 ISA_MIPS32R2, CPU_MIPS32R2 },
15344 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15345 ISA_MIPS32R2, CPU_MIPS32R2 },
15346 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15347 ISA_MIPS32R2, CPU_MIPS32R2 },
15348 /* Deprecated forms of the above. */
15349 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15350 ISA_MIPS32R2, CPU_MIPS32R2 },
15351 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15352 ISA_MIPS32R2, CPU_MIPS32R2 },
15353 /* 1004K cores are multiprocessor versions of the 34K. */
15354 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15355 ISA_MIPS32R2, CPU_MIPS32R2 },
15356 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15357 ISA_MIPS32R2, CPU_MIPS32R2 },
15358 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15359 ISA_MIPS32R2, CPU_MIPS32R2 },
15360 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15361 ISA_MIPS32R2, CPU_MIPS32R2 },
15364 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15365 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15366 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15367 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15369 /* Broadcom SB-1 CPU core */
15370 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15371 ISA_MIPS64, CPU_SB1 },
15372 /* Broadcom SB-1A CPU core */
15373 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15374 ISA_MIPS64, CPU_SB1 },
15376 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15378 /* MIPS 64 Release 2 */
15380 /* Cavium Networks Octeon CPU core */
15381 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15384 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15391 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15392 with a final "000" replaced by "k". Ignore case.
15394 Note: this function is shared between GCC and GAS. */
15397 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15399 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15400 given++, canonical++;
15402 return ((*given == 0 && *canonical == 0)
15403 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15407 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15408 CPU name. We've traditionally allowed a lot of variation here.
15410 Note: this function is shared between GCC and GAS. */
15413 mips_matching_cpu_name_p (const char *canonical, const char *given)
15415 /* First see if the name matches exactly, or with a final "000"
15416 turned into "k". */
15417 if (mips_strict_matching_cpu_name_p (canonical, given))
15420 /* If not, try comparing based on numerical designation alone.
15421 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15422 if (TOLOWER (*given) == 'r')
15424 if (!ISDIGIT (*given))
15427 /* Skip over some well-known prefixes in the canonical name,
15428 hoping to find a number there too. */
15429 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15431 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15433 else if (TOLOWER (canonical[0]) == 'r')
15436 return mips_strict_matching_cpu_name_p (canonical, given);
15440 /* Parse an option that takes the name of a processor as its argument.
15441 OPTION is the name of the option and CPU_STRING is the argument.
15442 Return the corresponding processor enumeration if the CPU_STRING is
15443 recognized, otherwise report an error and return null.
15445 A similar function exists in GCC. */
15447 static const struct mips_cpu_info *
15448 mips_parse_cpu (const char *option, const char *cpu_string)
15450 const struct mips_cpu_info *p;
15452 /* 'from-abi' selects the most compatible architecture for the given
15453 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15454 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15455 version. Look first at the -mgp options, if given, otherwise base
15456 the choice on MIPS_DEFAULT_64BIT.
15458 Treat NO_ABI like the EABIs. One reason to do this is that the
15459 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15460 architecture. This code picks MIPS I for 'mips' and MIPS III for
15461 'mips64', just as we did in the days before 'from-abi'. */
15462 if (strcasecmp (cpu_string, "from-abi") == 0)
15464 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15465 return mips_cpu_info_from_isa (ISA_MIPS1);
15467 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15468 return mips_cpu_info_from_isa (ISA_MIPS3);
15470 if (file_mips_gp32 >= 0)
15471 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15473 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15478 /* 'default' has traditionally been a no-op. Probably not very useful. */
15479 if (strcasecmp (cpu_string, "default") == 0)
15482 for (p = mips_cpu_info_table; p->name != 0; p++)
15483 if (mips_matching_cpu_name_p (p->name, cpu_string))
15486 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15490 /* Return the canonical processor information for ISA (a member of the
15491 ISA_MIPS* enumeration). */
15493 static const struct mips_cpu_info *
15494 mips_cpu_info_from_isa (int isa)
15498 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15499 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15500 && isa == mips_cpu_info_table[i].isa)
15501 return (&mips_cpu_info_table[i]);
15506 static const struct mips_cpu_info *
15507 mips_cpu_info_from_arch (int arch)
15511 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15512 if (arch == mips_cpu_info_table[i].cpu)
15513 return (&mips_cpu_info_table[i]);
15519 show (FILE *stream, const char *string, int *col_p, int *first_p)
15523 fprintf (stream, "%24s", "");
15528 fprintf (stream, ", ");
15532 if (*col_p + strlen (string) > 72)
15534 fprintf (stream, "\n%24s", "");
15538 fprintf (stream, "%s", string);
15539 *col_p += strlen (string);
15545 md_show_usage (FILE *stream)
15550 fprintf (stream, _("\
15552 -EB generate big endian output\n\
15553 -EL generate little endian output\n\
15554 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15555 -G NUM allow referencing objects up to NUM bytes\n\
15556 implicitly with the gp register [default 8]\n"));
15557 fprintf (stream, _("\
15558 -mips1 generate MIPS ISA I instructions\n\
15559 -mips2 generate MIPS ISA II instructions\n\
15560 -mips3 generate MIPS ISA III instructions\n\
15561 -mips4 generate MIPS ISA IV instructions\n\
15562 -mips5 generate MIPS ISA V instructions\n\
15563 -mips32 generate MIPS32 ISA instructions\n\
15564 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15565 -mips64 generate MIPS64 ISA instructions\n\
15566 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15567 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15571 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15572 show (stream, mips_cpu_info_table[i].name, &column, &first);
15573 show (stream, "from-abi", &column, &first);
15574 fputc ('\n', stream);
15576 fprintf (stream, _("\
15577 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15578 -no-mCPU don't generate code specific to CPU.\n\
15579 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15583 show (stream, "3900", &column, &first);
15584 show (stream, "4010", &column, &first);
15585 show (stream, "4100", &column, &first);
15586 show (stream, "4650", &column, &first);
15587 fputc ('\n', stream);
15589 fprintf (stream, _("\
15590 -mips16 generate mips16 instructions\n\
15591 -no-mips16 do not generate mips16 instructions\n"));
15592 fprintf (stream, _("\
15593 -msmartmips generate smartmips instructions\n\
15594 -mno-smartmips do not generate smartmips instructions\n"));
15595 fprintf (stream, _("\
15596 -mdsp generate DSP instructions\n\
15597 -mno-dsp do not generate DSP instructions\n"));
15598 fprintf (stream, _("\
15599 -mdspr2 generate DSP R2 instructions\n\
15600 -mno-dspr2 do not generate DSP R2 instructions\n"));
15601 fprintf (stream, _("\
15602 -mmt generate MT instructions\n\
15603 -mno-mt do not generate MT instructions\n"));
15604 fprintf (stream, _("\
15605 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15606 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15607 -mfix-vr4120 work around certain VR4120 errata\n\
15608 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15609 -mfix-24k insert a nop after ERET and DERET instructions\n\
15610 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15611 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15612 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15613 -msym32 assume all symbols have 32-bit values\n\
15614 -O0 remove unneeded NOPs, do not swap branches\n\
15615 -O remove unneeded NOPs and swap branches\n\
15616 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15617 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15618 fprintf (stream, _("\
15619 -mhard-float allow floating-point instructions\n\
15620 -msoft-float do not allow floating-point instructions\n\
15621 -msingle-float only allow 32-bit floating-point operations\n\
15622 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15623 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15626 fprintf (stream, _("\
15627 -KPIC, -call_shared generate SVR4 position independent code\n\
15628 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15629 -mvxworks-pic generate VxWorks position independent code\n\
15630 -non_shared do not generate code that can operate with DSOs\n\
15631 -xgot assume a 32 bit GOT\n\
15632 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15633 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15634 position dependent (non shared) code\n\
15635 -mabi=ABI create ABI conformant object file for:\n"));
15639 show (stream, "32", &column, &first);
15640 show (stream, "o64", &column, &first);
15641 show (stream, "n32", &column, &first);
15642 show (stream, "64", &column, &first);
15643 show (stream, "eabi", &column, &first);
15645 fputc ('\n', stream);
15647 fprintf (stream, _("\
15648 -32 create o32 ABI object file (default)\n\
15649 -n32 create n32 ABI object file\n\
15650 -64 create 64 ABI object file\n"));
15656 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15658 if (HAVE_64BIT_SYMBOLS)
15659 return dwarf2_format_64bit_irix;
15661 return dwarf2_format_32bit;
15666 mips_dwarf2_addr_size (void)
15668 if (HAVE_64BIT_OBJECTS)
15674 /* Standard calling conventions leave the CFA at SP on entry. */
15676 mips_cfi_frame_initial_instructions (void)
15678 cfi_add_CFA_def_cfa_register (SP);
15682 tc_mips_regname_to_dw2regnum (char *regname)
15684 unsigned int regnum = -1;
15687 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))