1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi = NO_ABI;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Whether we are assembling for the mips16 processor. 0 if we are
141 not, 1 if we are, and -1 if the value has not been initialized.
142 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
143 -nomips16 command line options, and the default CPU. */
145 /* Non-zero if we should not reorder instructions. Changed by `.set
146 reorder' and `.set noreorder'. */
148 /* Non-zero if we should not permit the $at ($1) register to be used
149 in instructions. Changed by `.set at' and `.set noat'. */
151 /* Non-zero if we should warn when a macro instruction expands into
152 more than one machine instruction. Changed by `.set nomacro' and
154 int warn_about_macros;
155 /* Non-zero if we should not move instructions. Changed by `.set
156 move', `.set volatile', `.set nomove', and `.set novolatile'. */
158 /* Non-zero if we should not optimize branches by moving the target
159 of the branch into the delay slot. Actually, we don't perform
160 this optimization anyhow. Changed by `.set bopt' and `.set
163 /* Non-zero if we should not autoextend mips16 instructions.
164 Changed by `.set autoextend' and `.set noautoextend'. */
166 /* Restrict general purpose registers and floating point registers
167 to 32 bit. This is initially determined when -mgp32 or -mfp32
168 is passed but can changed if the assembler code uses .set mipsN. */
171 /* The ABI currently in use. This is changed by .set mipsN to loosen
172 restrictions and doesn't affect the whole file. */
173 enum mips_abi_level abi;
176 /* True if -mgp32 was passed. */
177 static int file_mips_gp32 = -1;
179 /* True if -mfp32 was passed. */
180 static int file_mips_fp32 = -1;
182 /* This is the struct we use to hold the current set of options. Note
183 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
184 -1 to indicate that they have not been initialized. */
186 static struct mips_set_options mips_opts =
188 ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
191 /* These variables are filled in with the masks of registers used.
192 The object format code reads them and puts them in the appropriate
194 unsigned long mips_gprmask;
195 unsigned long mips_cprmask[4];
197 /* MIPS ISA we are using for this output file. */
198 static int file_mips_isa = ISA_UNKNOWN;
200 /* The argument of the -mcpu= flag. Historical for code generation. */
201 static int mips_cpu = CPU_UNKNOWN;
203 /* The argument of the -march= flag. The architecture we are assembling. */
204 static int mips_arch = CPU_UNKNOWN;
206 /* The argument of the -mtune= flag. The architecture for which we
208 static int mips_tune = CPU_UNKNOWN;
210 /* Whether we should mark the file EABI64 or EABI32. */
211 static int mips_eabi64 = 0;
213 /* If they asked for mips1 or mips2 and a cpu that is
214 mips3 or greater, then mark the object file 32BITMODE. */
215 static int mips_32bitmode = 0;
217 /* Some ISA's have delay slots for instructions which read or write
218 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
219 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
220 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
221 delay slot in this ISA. The uses of this macro assume that any
222 ISA that has delay slots for one of these, has them for all. They
223 also assume that ISAs which don't have delays for these insns, don't
224 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
225 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
227 || (ISA) == ISA_MIPS2 \
228 || (ISA) == ISA_MIPS3 \
231 /* Return true if ISA supports 64 bit gp register instructions. */
232 #define ISA_HAS_64BIT_REGS(ISA) ( \
234 || (ISA) == ISA_MIPS4 \
235 || (ISA) == ISA_MIPS5 \
236 || (ISA) == ISA_MIPS64 \
239 #define HAVE_32BIT_GPRS \
241 || mips_opts.abi == O32_ABI \
242 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
244 #define HAVE_32BIT_FPRS \
246 || mips_opts.abi == O32_ABI \
247 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
249 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
250 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
252 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
254 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
256 /* We can only have 64bit addresses if the object file format
258 #define HAVE_32BIT_ADDRESSES \
260 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
261 || ! HAVE_64BIT_OBJECTS) \
262 && mips_pic != EMBEDDED_PIC))
264 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
266 /* Whether the processor uses hardware interlocks to protect
267 reads from the HI and LO registers, and thus does not
268 require nops to be inserted. */
270 #define hilo_interlocks (mips_arch == CPU_R4010 \
271 || mips_arch == CPU_SB1 \
274 /* Whether the processor uses hardware interlocks to protect reads
275 from the GPRs, and thus does not require nops to be inserted. */
276 #define gpr_interlocks \
277 (mips_opts.isa != ISA_MIPS1 \
278 || mips_arch == CPU_R3900)
280 /* As with other "interlocks" this is used by hardware that has FP
281 (co-processor) interlocks. */
282 /* Itbl support may require additional care here. */
283 #define cop_interlocks (mips_arch == CPU_R4300 \
284 || mips_arch == CPU_SB1 \
287 /* Is this a mfhi or mflo instruction? */
288 #define MF_HILO_INSN(PINFO) \
289 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
291 /* MIPS PIC level. */
295 /* Do not generate PIC code. */
298 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
299 not sure what it is supposed to do. */
302 /* Generate PIC code as in the SVR4 MIPS ABI. */
305 /* Generate PIC code without using a global offset table: the data
306 segment has a maximum size of 64K, all data references are off
307 the $gp register, and all text references are PC relative. This
308 is used on some embedded systems. */
312 static enum mips_pic_level mips_pic;
314 /* Warn about all NOPS that the assembler generates. */
315 static int warn_nops = 0;
317 /* 1 if we should generate 32 bit offsets from the GP register in
318 SVR4_PIC mode. Currently has no meaning in other modes. */
319 static int mips_big_got;
321 /* 1 if trap instructions should used for overflow rather than break
323 static int mips_trap;
325 /* 1 if double width floating point constants should not be constructed
326 by assembling two single width halves into two single width floating
327 point registers which just happen to alias the double width destination
328 register. On some architectures this aliasing can be disabled by a bit
329 in the status register, and the setting of this bit cannot be determined
330 automatically at assemble time. */
331 static int mips_disable_float_construction;
333 /* Non-zero if any .set noreorder directives were used. */
335 static int mips_any_noreorder;
337 /* Non-zero if nops should be inserted when the register referenced in
338 an mfhi/mflo instruction is read in the next two instructions. */
339 static int mips_7000_hilo_fix;
341 /* The size of the small data section. */
342 static unsigned int g_switch_value = 8;
343 /* Whether the -G option was used. */
344 static int g_switch_seen = 0;
349 /* If we can determine in advance that GP optimization won't be
350 possible, we can skip the relaxation stuff that tries to produce
351 GP-relative references. This makes delay slot optimization work
354 This function can only provide a guess, but it seems to work for
355 gcc output. It needs to guess right for gcc, otherwise gcc
356 will put what it thinks is a GP-relative instruction in a branch
359 I don't know if a fix is needed for the SVR4_PIC mode. I've only
360 fixed it for the non-PIC mode. KR 95/04/07 */
361 static int nopic_need_relax PARAMS ((symbolS *, int));
363 /* handle of the OPCODE hash table */
364 static struct hash_control *op_hash = NULL;
366 /* The opcode hash table we use for the mips16. */
367 static struct hash_control *mips16_op_hash = NULL;
369 /* This array holds the chars that always start a comment. If the
370 pre-processor is disabled, these aren't very useful */
371 const char comment_chars[] = "#";
373 /* This array holds the chars that only start a comment at the beginning of
374 a line. If the line seems to have the form '# 123 filename'
375 .line and .file directives will appear in the pre-processed output */
376 /* Note that input_file.c hand checks for '#' at the beginning of the
377 first line of the input file. This is because the compiler outputs
378 #NO_APP at the beginning of its output. */
379 /* Also note that C style comments are always supported. */
380 const char line_comment_chars[] = "#";
382 /* This array holds machine specific line separator characters. */
383 const char line_separator_chars[] = ";";
385 /* Chars that can be used to separate mant from exp in floating point nums */
386 const char EXP_CHARS[] = "eE";
388 /* Chars that mean this number is a floating point constant */
391 const char FLT_CHARS[] = "rRsSfFdDxXpP";
393 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
394 changed in read.c . Ideally it shouldn't have to know about it at all,
395 but nothing is ideal around here.
398 static char *insn_error;
400 static int auto_align = 1;
402 /* When outputting SVR4 PIC code, the assembler needs to know the
403 offset in the stack frame from which to restore the $gp register.
404 This is set by the .cprestore pseudo-op, and saved in this
406 static offsetT mips_cprestore_offset = -1;
408 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
409 more optimizations, it can use a register value instead of a memory-saved
410 offset and even an other register than $gp as global pointer. */
411 static offsetT mips_cpreturn_offset = -1;
412 static int mips_cpreturn_register = -1;
413 static int mips_gp_register = GP;
415 /* Whether mips_cprestore_offset has been set in the current function
416 (or whether it has already been warned about, if not). */
417 static int mips_cprestore_valid = 0;
419 /* This is the register which holds the stack frame, as set by the
420 .frame pseudo-op. This is needed to implement .cprestore. */
421 static int mips_frame_reg = SP;
423 /* Whether mips_frame_reg has been set in the current function
424 (or whether it has already been warned about, if not). */
425 static int mips_frame_reg_valid = 0;
427 /* To output NOP instructions correctly, we need to keep information
428 about the previous two instructions. */
430 /* Whether we are optimizing. The default value of 2 means to remove
431 unneeded NOPs and swap branch instructions when possible. A value
432 of 1 means to not swap branches. A value of 0 means to always
434 static int mips_optimize = 2;
436 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
437 equivalent to seeing no -g option at all. */
438 static int mips_debug = 0;
440 /* The previous instruction. */
441 static struct mips_cl_insn prev_insn;
443 /* The instruction before prev_insn. */
444 static struct mips_cl_insn prev_prev_insn;
446 /* If we don't want information for prev_insn or prev_prev_insn, we
447 point the insn_mo field at this dummy integer. */
448 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
450 /* Non-zero if prev_insn is valid. */
451 static int prev_insn_valid;
453 /* The frag for the previous instruction. */
454 static struct frag *prev_insn_frag;
456 /* The offset into prev_insn_frag for the previous instruction. */
457 static long prev_insn_where;
459 /* The reloc type for the previous instruction, if any. */
460 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
462 /* The reloc for the previous instruction, if any. */
463 static fixS *prev_insn_fixp[3];
465 /* Non-zero if the previous instruction was in a delay slot. */
466 static int prev_insn_is_delay_slot;
468 /* Non-zero if the previous instruction was in a .set noreorder. */
469 static int prev_insn_unreordered;
471 /* Non-zero if the previous instruction uses an extend opcode (if
473 static int prev_insn_extended;
475 /* Non-zero if the previous previous instruction was in a .set
477 static int prev_prev_insn_unreordered;
479 /* If this is set, it points to a frag holding nop instructions which
480 were inserted before the start of a noreorder section. If those
481 nops turn out to be unnecessary, the size of the frag can be
483 static fragS *prev_nop_frag;
485 /* The number of nop instructions we created in prev_nop_frag. */
486 static int prev_nop_frag_holds;
488 /* The number of nop instructions that we know we need in
490 static int prev_nop_frag_required;
492 /* The number of instructions we've seen since prev_nop_frag. */
493 static int prev_nop_frag_since;
495 /* For ECOFF and ELF, relocations against symbols are done in two
496 parts, with a HI relocation and a LO relocation. Each relocation
497 has only 16 bits of space to store an addend. This means that in
498 order for the linker to handle carries correctly, it must be able
499 to locate both the HI and the LO relocation. This means that the
500 relocations must appear in order in the relocation table.
502 In order to implement this, we keep track of each unmatched HI
503 relocation. We then sort them so that they immediately precede the
504 corresponding LO relocation. */
509 struct mips_hi_fixup *next;
512 /* The section this fixup is in. */
516 /* The list of unmatched HI relocs. */
518 static struct mips_hi_fixup *mips_hi_fixup_list;
520 /* Map normal MIPS register numbers to mips16 register numbers. */
522 #define X ILLEGAL_REG
523 static const int mips32_to_16_reg_map[] =
525 X, X, 2, 3, 4, 5, 6, 7,
526 X, X, X, X, X, X, X, X,
527 0, 1, X, X, X, X, X, X,
528 X, X, X, X, X, X, X, X
532 /* Map mips16 register numbers to normal MIPS register numbers. */
534 static const unsigned int mips16_to_32_reg_map[] =
536 16, 17, 2, 3, 4, 5, 6, 7
539 /* Since the MIPS does not have multiple forms of PC relative
540 instructions, we do not have to do relaxing as is done on other
541 platforms. However, we do have to handle GP relative addressing
542 correctly, which turns out to be a similar problem.
544 Every macro that refers to a symbol can occur in (at least) two
545 forms, one with GP relative addressing and one without. For
546 example, loading a global variable into a register generally uses
547 a macro instruction like this:
549 If i can be addressed off the GP register (this is true if it is in
550 the .sbss or .sdata section, or if it is known to be smaller than
551 the -G argument) this will generate the following instruction:
553 This instruction will use a GPREL reloc. If i can not be addressed
554 off the GP register, the following instruction sequence will be used:
557 In this case the first instruction will have a HI16 reloc, and the
558 second reloc will have a LO16 reloc. Both relocs will be against
561 The issue here is that we may not know whether i is GP addressable
562 until after we see the instruction that uses it. Therefore, we
563 want to be able to choose the final instruction sequence only at
564 the end of the assembly. This is similar to the way other
565 platforms choose the size of a PC relative instruction only at the
568 When generating position independent code we do not use GP
569 addressing in quite the same way, but the issue still arises as
570 external symbols and local symbols must be handled differently.
572 We handle these issues by actually generating both possible
573 instruction sequences. The longer one is put in a frag_var with
574 type rs_machine_dependent. We encode what to do with the frag in
575 the subtype field. We encode (1) the number of existing bytes to
576 replace, (2) the number of new bytes to use, (3) the offset from
577 the start of the existing bytes to the first reloc we must generate
578 (that is, the offset is applied from the start of the existing
579 bytes after they are replaced by the new bytes, if any), (4) the
580 offset from the start of the existing bytes to the second reloc,
581 (5) whether a third reloc is needed (the third reloc is always four
582 bytes after the second reloc), and (6) whether to warn if this
583 variant is used (this is sometimes needed if .set nomacro or .set
584 noat is in effect). All these numbers are reasonably small.
586 Generating two instruction sequences must be handled carefully to
587 ensure that delay slots are handled correctly. Fortunately, there
588 are a limited number of cases. When the second instruction
589 sequence is generated, append_insn is directed to maintain the
590 existing delay slot information, so it continues to apply to any
591 code after the second instruction sequence. This means that the
592 second instruction sequence must not impose any requirements not
593 required by the first instruction sequence.
595 These variant frags are then handled in functions called by the
596 machine independent code. md_estimate_size_before_relax returns
597 the final size of the frag. md_convert_frag sets up the final form
598 of the frag. tc_gen_reloc adjust the first reloc and adds a second
600 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
604 | (((reloc1) + 64) << 9) \
605 | (((reloc2) + 64) << 2) \
606 | ((reloc3) ? (1 << 1) : 0) \
608 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
609 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
610 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
611 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
612 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
613 #define RELAX_WARN(i) ((i) & 1)
615 /* For mips16 code, we use an entirely different form of relaxation.
616 mips16 supports two versions of most instructions which take
617 immediate values: a small one which takes some small value, and a
618 larger one which takes a 16 bit value. Since branches also follow
619 this pattern, relaxing these values is required.
621 We can assemble both mips16 and normal MIPS code in a single
622 object. Therefore, we need to support this type of relaxation at
623 the same time that we support the relaxation described above. We
624 use the high bit of the subtype field to distinguish these cases.
626 The information we store for this type of relaxation is the
627 argument code found in the opcode file for this relocation, whether
628 the user explicitly requested a small or extended form, and whether
629 the relocation is in a jump or jal delay slot. That tells us the
630 size of the value, and how it should be stored. We also store
631 whether the fragment is considered to be extended or not. We also
632 store whether this is known to be a branch to a different section,
633 whether we have tried to relax this frag yet, and whether we have
634 ever extended a PC relative fragment because of a shift count. */
635 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
638 | ((small) ? 0x100 : 0) \
639 | ((ext) ? 0x200 : 0) \
640 | ((dslot) ? 0x400 : 0) \
641 | ((jal_dslot) ? 0x800 : 0))
642 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
643 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
644 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
645 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
646 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
647 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
648 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
649 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
650 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
651 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
652 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
653 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
655 /* Prototypes for static functions. */
658 #define internalError() \
659 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
661 #define internalError() as_fatal (_("MIPS internal Error"));
664 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
666 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
667 unsigned int reg, enum mips_regclass class));
668 static int reg_needs_delay PARAMS ((unsigned int));
669 static void mips16_mark_labels PARAMS ((void));
670 static void append_insn PARAMS ((char *place,
671 struct mips_cl_insn * ip,
673 bfd_reloc_code_real_type *r,
675 static void mips_no_prev_insn PARAMS ((int));
676 static void mips_emit_delays PARAMS ((boolean));
678 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
679 const char *name, const char *fmt,
682 static void macro_build ();
684 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
685 const char *, const char *,
687 static void macro_build_lui PARAMS ((char *place, int *counter,
688 expressionS * ep, int regnum));
689 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
690 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
692 static void load_register PARAMS ((int *, int, expressionS *, int));
693 static void load_address PARAMS ((int *, int, expressionS *, int, int *));
694 static void move_register PARAMS ((int *, int, int));
695 static void macro PARAMS ((struct mips_cl_insn * ip));
696 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
697 #ifdef LOSING_COMPILER
698 static void macro2 PARAMS ((struct mips_cl_insn * ip));
700 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
701 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
702 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
703 boolean, boolean, unsigned long *,
704 boolean *, unsigned short *));
705 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
706 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
707 static int my_getSmallExpression PARAMS ((expressionS *, char *));
708 static void my_getExpression PARAMS ((expressionS *, char *));
710 static int support_64bit_objects PARAMS((void));
712 static symbolS *get_symbol PARAMS ((void));
713 static void mips_align PARAMS ((int to, int fill, symbolS *label));
714 static void s_align PARAMS ((int));
715 static void s_change_sec PARAMS ((int));
716 static void s_cons PARAMS ((int));
717 static void s_float_cons PARAMS ((int));
718 static void s_mips_globl PARAMS ((int));
719 static void s_option PARAMS ((int));
720 static void s_mipsset PARAMS ((int));
721 static void s_abicalls PARAMS ((int));
722 static void s_cpload PARAMS ((int));
723 static void s_cpsetup PARAMS ((int));
724 static void s_cplocal PARAMS ((int));
725 static void s_cprestore PARAMS ((int));
726 static void s_cpreturn PARAMS ((int));
727 static void s_gpvalue PARAMS ((int));
728 static void s_gpword PARAMS ((int));
729 static void s_cpadd PARAMS ((int));
730 static void s_insn PARAMS ((int));
731 static void md_obj_begin PARAMS ((void));
732 static void md_obj_end PARAMS ((void));
733 static long get_number PARAMS ((void));
734 static void s_mips_ent PARAMS ((int));
735 static void s_mips_end PARAMS ((int));
736 static void s_mips_frame PARAMS ((int));
737 static void s_mips_mask PARAMS ((int));
738 static void s_mips_stab PARAMS ((int));
739 static void s_mips_weakext PARAMS ((int));
740 static void s_file PARAMS ((int));
741 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
742 static const char *mips_isa_to_str PARAMS ((int));
743 static const char *mips_cpu_to_str PARAMS ((int));
744 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
745 static void show PARAMS ((FILE *, char *, int *, int *));
747 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
750 /* Return values of my_getSmallExpression(). */
757 /* Direct relocation creation by %percent_op(). */
776 /* Table and functions used to map between CPU/ISA names, and
777 ISA levels, and CPU numbers. */
781 const char *name; /* CPU or ISA name. */
782 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
783 int isa; /* ISA level. */
784 int cpu; /* CPU number (default CPU if ISA). */
787 static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *));
788 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
789 static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
793 The following pseudo-ops from the Kane and Heinrich MIPS book
794 should be defined here, but are currently unsupported: .alias,
795 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
797 The following pseudo-ops from the Kane and Heinrich MIPS book are
798 specific to the type of debugging information being generated, and
799 should be defined by the object format: .aent, .begin, .bend,
800 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
803 The following pseudo-ops from the Kane and Heinrich MIPS book are
804 not MIPS CPU specific, but are also not specific to the object file
805 format. This file is probably the best place to define them, but
806 they are not currently supported: .asm0, .endr, .lab, .repeat,
809 static const pseudo_typeS mips_pseudo_table[] =
811 /* MIPS specific pseudo-ops. */
812 {"option", s_option, 0},
813 {"set", s_mipsset, 0},
814 {"rdata", s_change_sec, 'r'},
815 {"sdata", s_change_sec, 's'},
816 {"livereg", s_ignore, 0},
817 {"abicalls", s_abicalls, 0},
818 {"cpload", s_cpload, 0},
819 {"cpsetup", s_cpsetup, 0},
820 {"cplocal", s_cplocal, 0},
821 {"cprestore", s_cprestore, 0},
822 {"cpreturn", s_cpreturn, 0},
823 {"gpvalue", s_gpvalue, 0},
824 {"gpword", s_gpword, 0},
825 {"cpadd", s_cpadd, 0},
828 /* Relatively generic pseudo-ops that happen to be used on MIPS
830 {"asciiz", stringer, 1},
831 {"bss", s_change_sec, 'b'},
834 {"dword", s_cons, 3},
835 {"weakext", s_mips_weakext, 0},
837 /* These pseudo-ops are defined in read.c, but must be overridden
838 here for one reason or another. */
839 {"align", s_align, 0},
841 {"data", s_change_sec, 'd'},
842 {"double", s_float_cons, 'd'},
843 {"float", s_float_cons, 'f'},
844 {"globl", s_mips_globl, 0},
845 {"global", s_mips_globl, 0},
846 {"hword", s_cons, 1},
851 {"short", s_cons, 1},
852 {"single", s_float_cons, 'f'},
853 {"stabn", s_mips_stab, 'n'},
854 {"text", s_change_sec, 't'},
857 #ifdef MIPS_STABS_ELF
858 { "extern", ecoff_directive_extern, 0},
864 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
866 /* These pseudo-ops should be defined by the object file format.
867 However, a.out doesn't support them, so we have versions here. */
868 {"aent", s_mips_ent, 1},
869 {"bgnb", s_ignore, 0},
870 {"end", s_mips_end, 0},
871 {"endb", s_ignore, 0},
872 {"ent", s_mips_ent, 0},
874 {"fmask", s_mips_mask, 'F'},
875 {"frame", s_mips_frame, 0},
876 {"loc", s_ignore, 0},
877 {"mask", s_mips_mask, 'R'},
878 {"verstamp", s_ignore, 0},
882 extern void pop_insert PARAMS ((const pseudo_typeS *));
887 pop_insert (mips_pseudo_table);
888 if (! ECOFF_DEBUGGING)
889 pop_insert (mips_nonecoff_pseudo_table);
892 /* Symbols labelling the current insn. */
894 struct insn_label_list
896 struct insn_label_list *next;
900 static struct insn_label_list *insn_labels;
901 static struct insn_label_list *free_insn_labels;
903 static void mips_clear_insn_labels PARAMS ((void));
906 mips_clear_insn_labels ()
908 register struct insn_label_list **pl;
910 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
916 static char *expr_end;
918 /* Expressions which appear in instructions. These are set by
921 static expressionS imm_expr;
922 static expressionS offset_expr;
924 /* Relocs associated with imm_expr and offset_expr. */
926 static bfd_reloc_code_real_type imm_reloc[3]
927 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
928 static bfd_reloc_code_real_type offset_reloc[3]
929 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
931 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
933 static boolean imm_unmatched_hi;
935 /* These are set by mips16_ip if an explicit extension is used. */
937 static boolean mips16_small, mips16_ext;
939 #ifdef MIPS_STABS_ELF
940 /* The pdr segment for per procedure frame/regmask info */
946 mips_isa_to_str (isa)
949 const struct mips_cpu_info *ci;
952 ci = mips_cpu_info_from_isa (isa);
956 sprintf (s, "ISA#%d", isa);
961 mips_cpu_to_str (cpu)
964 const struct mips_cpu_info *ci;
967 ci = mips_cpu_info_from_cpu (cpu);
971 sprintf (s, "CPU#%d", cpu);
975 /* The default target format to use. */
978 mips_target_format ()
980 switch (OUTPUT_FLAVOR)
982 case bfd_target_aout_flavour:
983 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
984 case bfd_target_ecoff_flavour:
985 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
986 case bfd_target_coff_flavour:
988 case bfd_target_elf_flavour:
990 /* This is traditional mips */
991 return (target_big_endian
992 ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips"
993 : "elf32-tradbigmips")
994 : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips"
995 : "elf32-tradlittlemips"));
997 return (target_big_endian
998 ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips")
999 : (HAVE_64BIT_OBJECTS ? "elf64-littlemips"
1000 : "elf32-littlemips"));
1008 /* This function is called once, at assembler startup time. It should
1009 set up all the tables, etc. that the MD part of the assembler will need. */
1014 register const char *retval = NULL;
1019 int mips_isa_from_cpu;
1020 int target_cpu_had_mips16 = 0;
1021 const struct mips_cpu_info *ci;
1023 /* GP relative stuff not working for PE */
1024 if (strncmp (TARGET_OS, "pe", 2) == 0
1025 && g_switch_value != 0)
1028 as_bad (_("-G not supported in this configuration."));
1033 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
1035 a = xmalloc (sizeof TARGET_CPU);
1036 strcpy (a, TARGET_CPU);
1037 a[(sizeof TARGET_CPU) - 3] = '\0';
1041 if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0)
1043 target_cpu_had_mips16 = 1;
1044 cpu += sizeof "mips16" - 1;
1047 if (mips_opts.mips16 < 0)
1048 mips_opts.mips16 = target_cpu_had_mips16;
1050 /* Backward compatibility for historic -mcpu= option. Check for
1051 incompatible options, warn if -mcpu is used. */
1052 if (mips_cpu != CPU_UNKNOWN
1053 && mips_arch != CPU_UNKNOWN
1054 && mips_cpu != mips_arch)
1056 as_fatal (_("The -mcpu option can't be used together with -march. "
1057 "Use -mtune instead of -mcpu."));
1060 if (mips_cpu != CPU_UNKNOWN
1061 && mips_tune != CPU_UNKNOWN
1062 && mips_cpu != mips_tune)
1064 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1065 "Use -march instead of -mcpu."));
1069 /* For backward compatibility, let -mipsN set various defaults. */
1070 /* This code should go away, to be replaced with something rather more
1071 draconian. Until GCC 3.1 has been released for some reasonable
1072 amount of time, however, we need to support this. */
1073 if (mips_opts.isa != ISA_UNKNOWN)
1075 /* Translate -mipsN to the appropriate settings of file_mips_gp32
1076 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
1077 if (file_mips_gp32 < 0)
1079 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1084 if (file_mips_fp32 < 0)
1086 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1092 ci = mips_cpu_info_from_isa (mips_opts.isa);
1093 assert (ci != NULL);
1094 /* -mipsN has higher priority than -mcpu but lower than -march. */
1095 if (mips_arch == CPU_UNKNOWN)
1096 mips_arch = ci->cpu;
1098 /* Default mips_abi. */
1099 if (mips_opts.abi == NO_ABI)
1101 if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2)
1102 mips_opts.abi = O32_ABI;
1103 else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4)
1104 mips_opts.abi = O64_ABI;
1108 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1110 ci = mips_cpu_info_from_cpu (mips_cpu);
1111 assert (ci != NULL);
1112 mips_arch = ci->cpu;
1113 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1114 "-mtune instead."));
1117 /* Set tune from -mcpu, not from -mipsN. */
1118 if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1120 ci = mips_cpu_info_from_cpu (mips_cpu);
1121 assert (ci != NULL);
1122 mips_tune = ci->cpu;
1125 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1126 specified on the command line, or some other value if one was.
1127 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1128 the command line, or will be set otherwise if one was. */
1130 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1131 /* Handled above. */;
1133 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1135 ci = mips_cpu_info_from_cpu (mips_cpu);
1136 assert (ci != NULL);
1137 mips_arch = ci->cpu;
1138 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1139 "-mtune instead."));
1142 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1143 specified on the command line, or some other value if one was.
1144 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1145 the command line, or will be set otherwise if one was. */
1147 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1149 /* We have to check if the isa is the default isa of arch. Otherwise
1150 we'll get invalid object file headers. */
1151 ci = mips_cpu_info_from_cpu (mips_arch);
1152 assert (ci != NULL);
1153 if (mips_opts.isa != ci->isa)
1155 /* This really should be an error instead of a warning, but old
1156 compilers only have -mcpu which sets both arch and tune. For
1157 now, we discard arch and preserve tune. */
1158 as_warn (_("The -march option is incompatible to -mipsN and "
1159 "therefore ignored."));
1160 if (mips_tune == CPU_UNKNOWN)
1161 mips_tune = mips_arch;
1162 ci = mips_cpu_info_from_isa (mips_opts.isa);
1163 assert (ci != NULL);
1164 mips_arch = ci->cpu;
1168 else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
1170 /* We have ARCH, we need ISA. */
1171 ci = mips_cpu_info_from_cpu (mips_arch);
1172 assert (ci != NULL);
1173 mips_opts.isa = ci->isa;
1175 else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1177 /* We have ISA, we need default ARCH. */
1178 ci = mips_cpu_info_from_isa (mips_opts.isa);
1179 assert (ci != NULL);
1180 mips_arch = ci->cpu;
1184 /* We need to set both ISA and ARCH from target cpu. */
1185 ci = mips_cpu_info_from_name (cpu);
1187 ci = mips_cpu_info_from_cpu (CPU_R3000);
1188 assert (ci != NULL);
1189 mips_opts.isa = ci->isa;
1190 mips_arch = ci->cpu;
1193 if (mips_tune == CPU_UNKNOWN)
1194 mips_tune = mips_arch;
1196 ci = mips_cpu_info_from_cpu (mips_arch);
1197 assert (ci != NULL);
1198 mips_isa_from_cpu = ci->isa;
1200 /* End of TARGET_CPU processing, get rid of malloced memory
1209 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
1210 as_bad (_("trap exception not supported at ISA 1"));
1212 /* Set the EABI kind based on the ISA before the user gets
1213 to change the ISA with directives. This isn't really
1214 the best, but then neither is basing the abi on the isa. */
1215 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
1216 && mips_opts.abi == EABI_ABI)
1219 /* If they asked for mips1 or mips2 and a cpu that is
1220 mips3 or greater, then mark the object file 32BITMODE. */
1221 if (mips_isa_from_cpu != ISA_UNKNOWN
1222 && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
1223 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
1226 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1227 as_warn (_("Could not set architecture and machine"));
1229 if (file_mips_gp32 < 0)
1231 if (file_mips_fp32 < 0)
1234 file_mips_isa = mips_opts.isa;
1235 file_mips_abi = mips_opts.abi;
1236 mips_opts.gp32 = file_mips_gp32;
1237 mips_opts.fp32 = file_mips_fp32;
1239 op_hash = hash_new ();
1241 for (i = 0; i < NUMOPCODES;)
1243 const char *name = mips_opcodes[i].name;
1245 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1248 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1249 mips_opcodes[i].name, retval);
1250 /* Probably a memory allocation problem? Give up now. */
1251 as_fatal (_("Broken assembler. No assembly attempted."));
1255 if (mips_opcodes[i].pinfo != INSN_MACRO)
1257 if (!validate_mips_insn (&mips_opcodes[i]))
1262 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1265 mips16_op_hash = hash_new ();
1268 while (i < bfd_mips16_num_opcodes)
1270 const char *name = mips16_opcodes[i].name;
1272 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1274 as_fatal (_("internal: can't hash `%s': %s"),
1275 mips16_opcodes[i].name, retval);
1278 if (mips16_opcodes[i].pinfo != INSN_MACRO
1279 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1280 != mips16_opcodes[i].match))
1282 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1283 mips16_opcodes[i].name, mips16_opcodes[i].args);
1288 while (i < bfd_mips16_num_opcodes
1289 && strcmp (mips16_opcodes[i].name, name) == 0);
1293 as_fatal (_("Broken assembler. No assembly attempted."));
1295 /* We add all the general register names to the symbol table. This
1296 helps us detect invalid uses of them. */
1297 for (i = 0; i < 32; i++)
1301 sprintf (buf, "$%d", i);
1302 symbol_table_insert (symbol_new (buf, reg_section, i,
1303 &zero_address_frag));
1305 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1306 &zero_address_frag));
1307 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1308 &zero_address_frag));
1309 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1310 &zero_address_frag));
1311 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1312 &zero_address_frag));
1313 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1314 &zero_address_frag));
1315 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1316 &zero_address_frag));
1317 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1318 &zero_address_frag));
1320 mips_no_prev_insn (false);
1323 mips_cprmask[0] = 0;
1324 mips_cprmask[1] = 0;
1325 mips_cprmask[2] = 0;
1326 mips_cprmask[3] = 0;
1328 /* set the default alignment for the text section (2**2) */
1329 record_alignment (text_section, 2);
1331 if (USE_GLOBAL_POINTER_OPT)
1332 bfd_set_gp_size (stdoutput, g_switch_value);
1334 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1336 /* On a native system, sections must be aligned to 16 byte
1337 boundaries. When configured for an embedded ELF target, we
1339 if (strcmp (TARGET_OS, "elf") != 0)
1341 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1342 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1343 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1346 /* Create a .reginfo section for register masks and a .mdebug
1347 section for debugging information. */
1355 subseg = now_subseg;
1357 /* The ABI says this section should be loaded so that the
1358 running program can access it. However, we don't load it
1359 if we are configured for an embedded target */
1360 flags = SEC_READONLY | SEC_DATA;
1361 if (strcmp (TARGET_OS, "elf") != 0)
1362 flags |= SEC_ALLOC | SEC_LOAD;
1366 sec = subseg_new (".reginfo", (subsegT) 0);
1368 (void) bfd_set_section_flags (stdoutput, sec, flags);
1369 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1372 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1377 /* The 64-bit ABI uses a .MIPS.options section rather than
1378 .reginfo section. */
1379 sec = subseg_new (".MIPS.options", (subsegT) 0);
1380 (void) bfd_set_section_flags (stdoutput, sec, flags);
1381 (void) bfd_set_section_alignment (stdoutput, sec, 3);
1384 /* Set up the option header. */
1386 Elf_Internal_Options opthdr;
1389 opthdr.kind = ODK_REGINFO;
1390 opthdr.size = (sizeof (Elf_External_Options)
1391 + sizeof (Elf64_External_RegInfo));
1394 f = frag_more (sizeof (Elf_External_Options));
1395 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1396 (Elf_External_Options *) f);
1398 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1403 if (ECOFF_DEBUGGING)
1405 sec = subseg_new (".mdebug", (subsegT) 0);
1406 (void) bfd_set_section_flags (stdoutput, sec,
1407 SEC_HAS_CONTENTS | SEC_READONLY);
1408 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1411 #ifdef MIPS_STABS_ELF
1412 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1413 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1414 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
1415 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1418 subseg_set (seg, subseg);
1422 if (! ECOFF_DEBUGGING)
1429 if (! ECOFF_DEBUGGING)
1437 struct mips_cl_insn insn;
1438 bfd_reloc_code_real_type unused_reloc[3]
1439 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1441 imm_expr.X_op = O_absent;
1442 imm_unmatched_hi = false;
1443 offset_expr.X_op = O_absent;
1444 imm_reloc[0] = BFD_RELOC_UNUSED;
1445 imm_reloc[1] = BFD_RELOC_UNUSED;
1446 imm_reloc[2] = BFD_RELOC_UNUSED;
1447 offset_reloc[0] = BFD_RELOC_UNUSED;
1448 offset_reloc[1] = BFD_RELOC_UNUSED;
1449 offset_reloc[2] = BFD_RELOC_UNUSED;
1451 if (mips_opts.mips16)
1452 mips16_ip (str, &insn);
1455 mips_ip (str, &insn);
1456 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1457 str, insn.insn_opcode));
1462 as_bad ("%s `%s'", insn_error, str);
1466 if (insn.insn_mo->pinfo == INSN_MACRO)
1468 if (mips_opts.mips16)
1469 mips16_macro (&insn);
1475 if (imm_expr.X_op != O_absent)
1476 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1477 else if (offset_expr.X_op != O_absent)
1478 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1480 append_insn (NULL, &insn, NULL, unused_reloc, false);
1484 /* See whether instruction IP reads register REG. CLASS is the type
1488 insn_uses_reg (ip, reg, class)
1489 struct mips_cl_insn *ip;
1491 enum mips_regclass class;
1493 if (class == MIPS16_REG)
1495 assert (mips_opts.mips16);
1496 reg = mips16_to_32_reg_map[reg];
1497 class = MIPS_GR_REG;
1500 /* Don't report on general register 0, since it never changes. */
1501 if (class == MIPS_GR_REG && reg == 0)
1504 if (class == MIPS_FP_REG)
1506 assert (! mips_opts.mips16);
1507 /* If we are called with either $f0 or $f1, we must check $f0.
1508 This is not optimal, because it will introduce an unnecessary
1509 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1510 need to distinguish reading both $f0 and $f1 or just one of
1511 them. Note that we don't have to check the other way,
1512 because there is no instruction that sets both $f0 and $f1
1513 and requires a delay. */
1514 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1515 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1516 == (reg &~ (unsigned) 1)))
1518 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1519 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1520 == (reg &~ (unsigned) 1)))
1523 else if (! mips_opts.mips16)
1525 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1526 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1528 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1529 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1534 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1535 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1536 & MIPS16OP_MASK_RX)]
1539 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1540 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1541 & MIPS16OP_MASK_RY)]
1544 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1545 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1546 & MIPS16OP_MASK_MOVE32Z)]
1549 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1551 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1553 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1555 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1556 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1557 & MIPS16OP_MASK_REGR32) == reg)
1564 /* This function returns true if modifying a register requires a
1568 reg_needs_delay (reg)
1571 unsigned long prev_pinfo;
1573 prev_pinfo = prev_insn.insn_mo->pinfo;
1574 if (! mips_opts.noreorder
1575 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1576 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1577 || (! gpr_interlocks
1578 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1580 /* A load from a coprocessor or from memory. All load
1581 delays delay the use of general register rt for one
1582 instruction on the r3000. The r6000 and r4000 use
1584 /* Itbl support may require additional care here. */
1585 know (prev_pinfo & INSN_WRITE_GPR_T);
1586 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1593 /* Mark instruction labels in mips16 mode. This permits the linker to
1594 handle them specially, such as generating jalx instructions when
1595 needed. We also make them odd for the duration of the assembly, in
1596 order to generate the right sort of code. We will make them even
1597 in the adjust_symtab routine, while leaving them marked. This is
1598 convenient for the debugger and the disassembler. The linker knows
1599 to make them odd again. */
1602 mips16_mark_labels ()
1604 if (mips_opts.mips16)
1606 struct insn_label_list *l;
1609 for (l = insn_labels; l != NULL; l = l->next)
1612 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1613 S_SET_OTHER (l->label, STO_MIPS16);
1615 val = S_GET_VALUE (l->label);
1617 S_SET_VALUE (l->label, val + 1);
1622 /* Output an instruction. PLACE is where to put the instruction; if
1623 it is NULL, this uses frag_more to get room. IP is the instruction
1624 information. ADDRESS_EXPR is an operand of the instruction to be
1625 used with RELOC_TYPE. */
1628 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1630 struct mips_cl_insn *ip;
1631 expressionS *address_expr;
1632 bfd_reloc_code_real_type *reloc_type;
1633 boolean unmatched_hi;
1635 register unsigned long prev_pinfo, pinfo;
1640 /* Mark instruction labels in mips16 mode. */
1641 if (mips_opts.mips16)
1642 mips16_mark_labels ();
1644 prev_pinfo = prev_insn.insn_mo->pinfo;
1645 pinfo = ip->insn_mo->pinfo;
1647 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1651 /* If the previous insn required any delay slots, see if we need
1652 to insert a NOP or two. There are eight kinds of possible
1653 hazards, of which an instruction can have at most one type.
1654 (1) a load from memory delay
1655 (2) a load from a coprocessor delay
1656 (3) an unconditional branch delay
1657 (4) a conditional branch delay
1658 (5) a move to coprocessor register delay
1659 (6) a load coprocessor register from memory delay
1660 (7) a coprocessor condition code delay
1661 (8) a HI/LO special register delay
1663 There are a lot of optimizations we could do that we don't.
1664 In particular, we do not, in general, reorder instructions.
1665 If you use gcc with optimization, it will reorder
1666 instructions and generally do much more optimization then we
1667 do here; repeating all that work in the assembler would only
1668 benefit hand written assembly code, and does not seem worth
1671 /* This is how a NOP is emitted. */
1672 #define emit_nop() \
1674 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1675 : md_number_to_chars (frag_more (4), 0, 4))
1677 /* The previous insn might require a delay slot, depending upon
1678 the contents of the current insn. */
1679 if (! mips_opts.mips16
1680 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1681 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1682 && ! cop_interlocks)
1683 || (! gpr_interlocks
1684 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1686 /* A load from a coprocessor or from memory. All load
1687 delays delay the use of general register rt for one
1688 instruction on the r3000. The r6000 and r4000 use
1690 /* Itbl support may require additional care here. */
1691 know (prev_pinfo & INSN_WRITE_GPR_T);
1692 if (mips_optimize == 0
1693 || insn_uses_reg (ip,
1694 ((prev_insn.insn_opcode >> OP_SH_RT)
1699 else if (! mips_opts.mips16
1700 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1701 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1702 && ! cop_interlocks)
1703 || (mips_opts.isa == ISA_MIPS1
1704 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1706 /* A generic coprocessor delay. The previous instruction
1707 modified a coprocessor general or control register. If
1708 it modified a control register, we need to avoid any
1709 coprocessor instruction (this is probably not always
1710 required, but it sometimes is). If it modified a general
1711 register, we avoid using that register.
1713 On the r6000 and r4000 loading a coprocessor register
1714 from memory is interlocked, and does not require a delay.
1716 This case is not handled very well. There is no special
1717 knowledge of CP0 handling, and the coprocessors other
1718 than the floating point unit are not distinguished at
1720 /* Itbl support may require additional care here. FIXME!
1721 Need to modify this to include knowledge about
1722 user specified delays! */
1723 if (prev_pinfo & INSN_WRITE_FPR_T)
1725 if (mips_optimize == 0
1726 || insn_uses_reg (ip,
1727 ((prev_insn.insn_opcode >> OP_SH_FT)
1732 else if (prev_pinfo & INSN_WRITE_FPR_S)
1734 if (mips_optimize == 0
1735 || insn_uses_reg (ip,
1736 ((prev_insn.insn_opcode >> OP_SH_FS)
1743 /* We don't know exactly what the previous instruction
1744 does. If the current instruction uses a coprocessor
1745 register, we must insert a NOP. If previous
1746 instruction may set the condition codes, and the
1747 current instruction uses them, we must insert two
1749 /* Itbl support may require additional care here. */
1750 if (mips_optimize == 0
1751 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1752 && (pinfo & INSN_READ_COND_CODE)))
1754 else if (pinfo & INSN_COP)
1758 else if (! mips_opts.mips16
1759 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1760 && (prev_pinfo & INSN_WRITE_COND_CODE)
1761 && ! cop_interlocks)
1763 /* The previous instruction sets the coprocessor condition
1764 codes, but does not require a general coprocessor delay
1765 (this means it is a floating point comparison
1766 instruction). If this instruction uses the condition
1767 codes, we need to insert a single NOP. */
1768 /* Itbl support may require additional care here. */
1769 if (mips_optimize == 0
1770 || (pinfo & INSN_READ_COND_CODE))
1774 /* If we're fixing up mfhi/mflo for the r7000 and the
1775 previous insn was an mfhi/mflo and the current insn
1776 reads the register that the mfhi/mflo wrote to, then
1779 else if (mips_7000_hilo_fix
1780 && MF_HILO_INSN (prev_pinfo)
1781 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1788 /* If we're fixing up mfhi/mflo for the r7000 and the
1789 2nd previous insn was an mfhi/mflo and the current insn
1790 reads the register that the mfhi/mflo wrote to, then
1793 else if (mips_7000_hilo_fix
1794 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1795 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1803 else if (prev_pinfo & INSN_READ_LO)
1805 /* The previous instruction reads the LO register; if the
1806 current instruction writes to the LO register, we must
1807 insert two NOPS. Some newer processors have interlocks.
1808 Also the tx39's multiply instructions can be exectuted
1809 immediatly after a read from HI/LO (without the delay),
1810 though the tx39's divide insns still do require the
1812 if (! (hilo_interlocks
1813 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1814 && (mips_optimize == 0
1815 || (pinfo & INSN_WRITE_LO)))
1817 /* Most mips16 branch insns don't have a delay slot.
1818 If a read from LO is immediately followed by a branch
1819 to a write to LO we have a read followed by a write
1820 less than 2 insns away. We assume the target of
1821 a branch might be a write to LO, and insert a nop
1822 between a read and an immediately following branch. */
1823 else if (mips_opts.mips16
1824 && (mips_optimize == 0
1825 || (pinfo & MIPS16_INSN_BRANCH)))
1828 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1830 /* The previous instruction reads the HI register; if the
1831 current instruction writes to the HI register, we must
1832 insert a NOP. Some newer processors have interlocks.
1833 Also the note tx39's multiply above. */
1834 if (! (hilo_interlocks
1835 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1836 && (mips_optimize == 0
1837 || (pinfo & INSN_WRITE_HI)))
1839 /* Most mips16 branch insns don't have a delay slot.
1840 If a read from HI is immediately followed by a branch
1841 to a write to HI we have a read followed by a write
1842 less than 2 insns away. We assume the target of
1843 a branch might be a write to HI, and insert a nop
1844 between a read and an immediately following branch. */
1845 else if (mips_opts.mips16
1846 && (mips_optimize == 0
1847 || (pinfo & MIPS16_INSN_BRANCH)))
1851 /* If the previous instruction was in a noreorder section, then
1852 we don't want to insert the nop after all. */
1853 /* Itbl support may require additional care here. */
1854 if (prev_insn_unreordered)
1857 /* There are two cases which require two intervening
1858 instructions: 1) setting the condition codes using a move to
1859 coprocessor instruction which requires a general coprocessor
1860 delay and then reading the condition codes 2) reading the HI
1861 or LO register and then writing to it (except on processors
1862 which have interlocks). If we are not already emitting a NOP
1863 instruction, we must check for these cases compared to the
1864 instruction previous to the previous instruction. */
1865 if ((! mips_opts.mips16
1866 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1867 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1868 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1869 && (pinfo & INSN_READ_COND_CODE)
1870 && ! cop_interlocks)
1871 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1872 && (pinfo & INSN_WRITE_LO)
1873 && ! (hilo_interlocks
1874 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1875 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1876 && (pinfo & INSN_WRITE_HI)
1877 && ! (hilo_interlocks
1878 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1883 if (prev_prev_insn_unreordered)
1886 if (prev_prev_nop && nops == 0)
1889 /* If we are being given a nop instruction, don't bother with
1890 one of the nops we would otherwise output. This will only
1891 happen when a nop instruction is used with mips_optimize set
1894 && ! mips_opts.noreorder
1895 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1898 /* Now emit the right number of NOP instructions. */
1899 if (nops > 0 && ! mips_opts.noreorder)
1902 unsigned long old_frag_offset;
1904 struct insn_label_list *l;
1906 old_frag = frag_now;
1907 old_frag_offset = frag_now_fix ();
1909 for (i = 0; i < nops; i++)
1914 listing_prev_line ();
1915 /* We may be at the start of a variant frag. In case we
1916 are, make sure there is enough space for the frag
1917 after the frags created by listing_prev_line. The
1918 argument to frag_grow here must be at least as large
1919 as the argument to all other calls to frag_grow in
1920 this file. We don't have to worry about being in the
1921 middle of a variant frag, because the variants insert
1922 all needed nop instructions themselves. */
1926 for (l = insn_labels; l != NULL; l = l->next)
1930 assert (S_GET_SEGMENT (l->label) == now_seg);
1931 symbol_set_frag (l->label, frag_now);
1932 val = (valueT) frag_now_fix ();
1933 /* mips16 text labels are stored as odd. */
1934 if (mips_opts.mips16)
1936 S_SET_VALUE (l->label, val);
1939 #ifndef NO_ECOFF_DEBUGGING
1940 if (ECOFF_DEBUGGING)
1941 ecoff_fix_loc (old_frag, old_frag_offset);
1944 else if (prev_nop_frag != NULL)
1946 /* We have a frag holding nops we may be able to remove. If
1947 we don't need any nops, we can decrease the size of
1948 prev_nop_frag by the size of one instruction. If we do
1949 need some nops, we count them in prev_nops_required. */
1950 if (prev_nop_frag_since == 0)
1954 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1955 --prev_nop_frag_holds;
1958 prev_nop_frag_required += nops;
1962 if (prev_prev_nop == 0)
1964 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1965 --prev_nop_frag_holds;
1968 ++prev_nop_frag_required;
1971 if (prev_nop_frag_holds <= prev_nop_frag_required)
1972 prev_nop_frag = NULL;
1974 ++prev_nop_frag_since;
1976 /* Sanity check: by the time we reach the second instruction
1977 after prev_nop_frag, we should have used up all the nops
1978 one way or another. */
1979 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1983 if (*reloc_type > BFD_RELOC_UNUSED)
1985 /* We need to set up a variant frag. */
1986 assert (mips_opts.mips16 && address_expr != NULL);
1987 f = frag_var (rs_machine_dependent, 4, 0,
1988 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1989 mips16_small, mips16_ext,
1991 & INSN_UNCOND_BRANCH_DELAY),
1992 (*prev_insn_reloc_type
1993 == BFD_RELOC_MIPS16_JMP)),
1994 make_expr_symbol (address_expr), 0, NULL);
1996 else if (place != NULL)
1998 else if (mips_opts.mips16
2000 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2002 /* Make sure there is enough room to swap this instruction with
2003 a following jump instruction. */
2009 if (mips_opts.mips16
2010 && mips_opts.noreorder
2011 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2012 as_warn (_("extended instruction in delay slot"));
2017 fixp[0] = fixp[1] = fixp[2] = NULL;
2018 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2020 if (address_expr->X_op == O_constant)
2024 switch (*reloc_type)
2027 ip->insn_opcode |= address_expr->X_add_number;
2030 case BFD_RELOC_MIPS_HIGHEST:
2031 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
2033 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2036 case BFD_RELOC_MIPS_HIGHER:
2037 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2038 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2041 case BFD_RELOC_HI16_S:
2042 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2046 case BFD_RELOC_HI16:
2047 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2050 case BFD_RELOC_LO16:
2051 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2054 case BFD_RELOC_MIPS_JMP:
2055 if ((address_expr->X_add_number & 3) != 0)
2056 as_bad (_("jump to misaligned address (0x%lx)"),
2057 (unsigned long) address_expr->X_add_number);
2058 if (address_expr->X_add_number & ~0xfffffff
2059 || address_expr->X_add_number > 0x7fffffc)
2060 as_bad (_("jump address range overflow (0x%lx)"),
2061 (unsigned long) address_expr->X_add_number);
2062 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2065 case BFD_RELOC_MIPS16_JMP:
2066 if ((address_expr->X_add_number & 3) != 0)
2067 as_bad (_("jump to misaligned address (0x%lx)"),
2068 (unsigned long) address_expr->X_add_number);
2069 if (address_expr->X_add_number & ~0xfffffff
2070 || address_expr->X_add_number > 0x7fffffc)
2071 as_bad (_("jump address range overflow (0x%lx)"),
2072 (unsigned long) address_expr->X_add_number);
2074 (((address_expr->X_add_number & 0x7c0000) << 3)
2075 | ((address_expr->X_add_number & 0xf800000) >> 7)
2076 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2079 case BFD_RELOC_16_PCREL:
2080 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2083 case BFD_RELOC_16_PCREL_S2:
2093 /* Don't generate a reloc if we are writing into a variant frag. */
2096 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
2098 (*reloc_type == BFD_RELOC_16_PCREL
2099 || *reloc_type == BFD_RELOC_16_PCREL_S2),
2102 /* These relocations can have an addend that won't fit in
2103 4 octets for 64bit assembly. */
2104 if (HAVE_64BIT_GPRS &&
2105 (*reloc_type == BFD_RELOC_16
2106 || *reloc_type == BFD_RELOC_32
2107 || *reloc_type == BFD_RELOC_MIPS_JMP
2108 || *reloc_type == BFD_RELOC_HI16_S
2109 || *reloc_type == BFD_RELOC_LO16
2110 || *reloc_type == BFD_RELOC_GPREL16
2111 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2112 || *reloc_type == BFD_RELOC_GPREL32
2113 || *reloc_type == BFD_RELOC_64
2114 || *reloc_type == BFD_RELOC_CTOR
2115 || *reloc_type == BFD_RELOC_MIPS_SUB
2116 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2117 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2118 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2119 || *reloc_type == BFD_RELOC_MIPS_REL16
2120 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2121 fixp[0]->fx_no_overflow = 1;
2125 struct mips_hi_fixup *hi_fixup;
2127 assert (*reloc_type == BFD_RELOC_HI16_S);
2128 hi_fixup = ((struct mips_hi_fixup *)
2129 xmalloc (sizeof (struct mips_hi_fixup)));
2130 hi_fixup->fixp = fixp[0];
2131 hi_fixup->seg = now_seg;
2132 hi_fixup->next = mips_hi_fixup_list;
2133 mips_hi_fixup_list = hi_fixup;
2136 if (reloc_type[1] != BFD_RELOC_UNUSED)
2138 /* FIXME: This symbol can be one of
2139 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2140 address_expr->X_op = O_absent;
2141 address_expr->X_add_symbol = 0;
2142 address_expr->X_add_number = 0;
2144 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2145 4, address_expr, false,
2148 /* These relocations can have an addend that won't fit in
2149 4 octets for 64bit assembly. */
2150 if (HAVE_64BIT_GPRS &&
2151 (*reloc_type == BFD_RELOC_16
2152 || *reloc_type == BFD_RELOC_32
2153 || *reloc_type == BFD_RELOC_MIPS_JMP
2154 || *reloc_type == BFD_RELOC_HI16_S
2155 || *reloc_type == BFD_RELOC_LO16
2156 || *reloc_type == BFD_RELOC_GPREL16
2157 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2158 || *reloc_type == BFD_RELOC_GPREL32
2159 || *reloc_type == BFD_RELOC_64
2160 || *reloc_type == BFD_RELOC_CTOR
2161 || *reloc_type == BFD_RELOC_MIPS_SUB
2162 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2163 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2164 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2165 || *reloc_type == BFD_RELOC_MIPS_REL16
2166 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2167 fixp[1]->fx_no_overflow = 1;
2169 if (reloc_type[2] != BFD_RELOC_UNUSED)
2171 address_expr->X_op = O_absent;
2172 address_expr->X_add_symbol = 0;
2173 address_expr->X_add_number = 0;
2175 fixp[2] = fix_new_exp (frag_now,
2176 f - frag_now->fr_literal, 4,
2177 address_expr, false,
2180 /* These relocations can have an addend that won't fit in
2181 4 octets for 64bit assembly. */
2182 if (HAVE_64BIT_GPRS &&
2183 (*reloc_type == BFD_RELOC_16
2184 || *reloc_type == BFD_RELOC_32
2185 || *reloc_type == BFD_RELOC_MIPS_JMP
2186 || *reloc_type == BFD_RELOC_HI16_S
2187 || *reloc_type == BFD_RELOC_LO16
2188 || *reloc_type == BFD_RELOC_GPREL16
2189 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2190 || *reloc_type == BFD_RELOC_GPREL32
2191 || *reloc_type == BFD_RELOC_64
2192 || *reloc_type == BFD_RELOC_CTOR
2193 || *reloc_type == BFD_RELOC_MIPS_SUB
2194 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2195 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2196 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2197 || *reloc_type == BFD_RELOC_MIPS_REL16
2198 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2199 fixp[2]->fx_no_overflow = 1;
2206 if (! mips_opts.mips16)
2207 md_number_to_chars (f, ip->insn_opcode, 4);
2208 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2210 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2211 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2217 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2220 md_number_to_chars (f, ip->insn_opcode, 2);
2223 /* Update the register mask information. */
2224 if (! mips_opts.mips16)
2226 if (pinfo & INSN_WRITE_GPR_D)
2227 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2228 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2229 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2230 if (pinfo & INSN_READ_GPR_S)
2231 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2232 if (pinfo & INSN_WRITE_GPR_31)
2233 mips_gprmask |= 1 << 31;
2234 if (pinfo & INSN_WRITE_FPR_D)
2235 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2236 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2237 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2238 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2239 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2240 if ((pinfo & INSN_READ_FPR_R) != 0)
2241 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2242 if (pinfo & INSN_COP)
2244 /* We don't keep enough information to sort these cases out.
2245 The itbl support does keep this information however, although
2246 we currently don't support itbl fprmats as part of the cop
2247 instruction. May want to add this support in the future. */
2249 /* Never set the bit for $0, which is always zero. */
2250 mips_gprmask &= ~1 << 0;
2254 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2255 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2256 & MIPS16OP_MASK_RX);
2257 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2258 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2259 & MIPS16OP_MASK_RY);
2260 if (pinfo & MIPS16_INSN_WRITE_Z)
2261 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2262 & MIPS16OP_MASK_RZ);
2263 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2264 mips_gprmask |= 1 << TREG;
2265 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2266 mips_gprmask |= 1 << SP;
2267 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2268 mips_gprmask |= 1 << RA;
2269 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2270 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2271 if (pinfo & MIPS16_INSN_READ_Z)
2272 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2273 & MIPS16OP_MASK_MOVE32Z);
2274 if (pinfo & MIPS16_INSN_READ_GPR_X)
2275 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2276 & MIPS16OP_MASK_REGR32);
2279 if (place == NULL && ! mips_opts.noreorder)
2281 /* Filling the branch delay slot is more complex. We try to
2282 switch the branch with the previous instruction, which we can
2283 do if the previous instruction does not set up a condition
2284 that the branch tests and if the branch is not itself the
2285 target of any branch. */
2286 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2287 || (pinfo & INSN_COND_BRANCH_DELAY))
2289 if (mips_optimize < 2
2290 /* If we have seen .set volatile or .set nomove, don't
2292 || mips_opts.nomove != 0
2293 /* If we had to emit any NOP instructions, then we
2294 already know we can not swap. */
2296 /* If we don't even know the previous insn, we can not
2298 || ! prev_insn_valid
2299 /* If the previous insn is already in a branch delay
2300 slot, then we can not swap. */
2301 || prev_insn_is_delay_slot
2302 /* If the previous previous insn was in a .set
2303 noreorder, we can't swap. Actually, the MIPS
2304 assembler will swap in this situation. However, gcc
2305 configured -with-gnu-as will generate code like
2311 in which we can not swap the bne and INSN. If gcc is
2312 not configured -with-gnu-as, it does not output the
2313 .set pseudo-ops. We don't have to check
2314 prev_insn_unreordered, because prev_insn_valid will
2315 be 0 in that case. We don't want to use
2316 prev_prev_insn_valid, because we do want to be able
2317 to swap at the start of a function. */
2318 || prev_prev_insn_unreordered
2319 /* If the branch is itself the target of a branch, we
2320 can not swap. We cheat on this; all we check for is
2321 whether there is a label on this instruction. If
2322 there are any branches to anything other than a
2323 label, users must use .set noreorder. */
2324 || insn_labels != NULL
2325 /* If the previous instruction is in a variant frag, we
2326 can not do the swap. This does not apply to the
2327 mips16, which uses variant frags for different
2329 || (! mips_opts.mips16
2330 && prev_insn_frag->fr_type == rs_machine_dependent)
2331 /* If the branch reads the condition codes, we don't
2332 even try to swap, because in the sequence
2337 we can not swap, and I don't feel like handling that
2339 || (! mips_opts.mips16
2340 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2341 && (pinfo & INSN_READ_COND_CODE))
2342 /* We can not swap with an instruction that requires a
2343 delay slot, becase the target of the branch might
2344 interfere with that instruction. */
2345 || (! mips_opts.mips16
2346 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2348 /* Itbl support may require additional care here. */
2349 & (INSN_LOAD_COPROC_DELAY
2350 | INSN_COPROC_MOVE_DELAY
2351 | INSN_WRITE_COND_CODE)))
2352 || (! (hilo_interlocks
2353 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2357 || (! mips_opts.mips16
2359 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2360 || (! mips_opts.mips16
2361 && mips_opts.isa == ISA_MIPS1
2362 /* Itbl support may require additional care here. */
2363 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2364 /* We can not swap with a branch instruction. */
2366 & (INSN_UNCOND_BRANCH_DELAY
2367 | INSN_COND_BRANCH_DELAY
2368 | INSN_COND_BRANCH_LIKELY))
2369 /* We do not swap with a trap instruction, since it
2370 complicates trap handlers to have the trap
2371 instruction be in a delay slot. */
2372 || (prev_pinfo & INSN_TRAP)
2373 /* If the branch reads a register that the previous
2374 instruction sets, we can not swap. */
2375 || (! mips_opts.mips16
2376 && (prev_pinfo & INSN_WRITE_GPR_T)
2377 && insn_uses_reg (ip,
2378 ((prev_insn.insn_opcode >> OP_SH_RT)
2381 || (! mips_opts.mips16
2382 && (prev_pinfo & INSN_WRITE_GPR_D)
2383 && insn_uses_reg (ip,
2384 ((prev_insn.insn_opcode >> OP_SH_RD)
2387 || (mips_opts.mips16
2388 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2389 && insn_uses_reg (ip,
2390 ((prev_insn.insn_opcode
2392 & MIPS16OP_MASK_RX),
2394 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2395 && insn_uses_reg (ip,
2396 ((prev_insn.insn_opcode
2398 & MIPS16OP_MASK_RY),
2400 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2401 && insn_uses_reg (ip,
2402 ((prev_insn.insn_opcode
2404 & MIPS16OP_MASK_RZ),
2406 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2407 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2408 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2409 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2410 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2411 && insn_uses_reg (ip,
2412 MIPS16OP_EXTRACT_REG32R (prev_insn.
2415 /* If the branch writes a register that the previous
2416 instruction sets, we can not swap (we know that
2417 branches write only to RD or to $31). */
2418 || (! mips_opts.mips16
2419 && (prev_pinfo & INSN_WRITE_GPR_T)
2420 && (((pinfo & INSN_WRITE_GPR_D)
2421 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2422 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2423 || ((pinfo & INSN_WRITE_GPR_31)
2424 && (((prev_insn.insn_opcode >> OP_SH_RT)
2427 || (! mips_opts.mips16
2428 && (prev_pinfo & INSN_WRITE_GPR_D)
2429 && (((pinfo & INSN_WRITE_GPR_D)
2430 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2431 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2432 || ((pinfo & INSN_WRITE_GPR_31)
2433 && (((prev_insn.insn_opcode >> OP_SH_RD)
2436 || (mips_opts.mips16
2437 && (pinfo & MIPS16_INSN_WRITE_31)
2438 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2439 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2440 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2442 /* If the branch writes a register that the previous
2443 instruction reads, we can not swap (we know that
2444 branches only write to RD or to $31). */
2445 || (! mips_opts.mips16
2446 && (pinfo & INSN_WRITE_GPR_D)
2447 && insn_uses_reg (&prev_insn,
2448 ((ip->insn_opcode >> OP_SH_RD)
2451 || (! mips_opts.mips16
2452 && (pinfo & INSN_WRITE_GPR_31)
2453 && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG))
2454 || (mips_opts.mips16
2455 && (pinfo & MIPS16_INSN_WRITE_31)
2456 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2457 /* If we are generating embedded PIC code, the branch
2458 might be expanded into a sequence which uses $at, so
2459 we can't swap with an instruction which reads it. */
2460 || (mips_pic == EMBEDDED_PIC
2461 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2462 /* If the previous previous instruction has a load
2463 delay, and sets a register that the branch reads, we
2465 || (! mips_opts.mips16
2466 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2467 /* Itbl support may require additional care here. */
2468 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2469 || (! gpr_interlocks
2470 && (prev_prev_insn.insn_mo->pinfo
2471 & INSN_LOAD_MEMORY_DELAY)))
2472 && insn_uses_reg (ip,
2473 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2476 /* If one instruction sets a condition code and the
2477 other one uses a condition code, we can not swap. */
2478 || ((pinfo & INSN_READ_COND_CODE)
2479 && (prev_pinfo & INSN_WRITE_COND_CODE))
2480 || ((pinfo & INSN_WRITE_COND_CODE)
2481 && (prev_pinfo & INSN_READ_COND_CODE))
2482 /* If the previous instruction uses the PC, we can not
2484 || (mips_opts.mips16
2485 && (prev_pinfo & MIPS16_INSN_READ_PC))
2486 /* If the previous instruction was extended, we can not
2488 || (mips_opts.mips16 && prev_insn_extended)
2489 /* If the previous instruction had a fixup in mips16
2490 mode, we can not swap. This normally means that the
2491 previous instruction was a 4 byte branch anyhow. */
2492 || (mips_opts.mips16 && prev_insn_fixp[0])
2493 /* If the previous instruction is a sync, sync.l, or
2494 sync.p, we can not swap. */
2495 || (prev_pinfo & INSN_SYNC))
2497 /* We could do even better for unconditional branches to
2498 portions of this object file; we could pick up the
2499 instruction at the destination, put it in the delay
2500 slot, and bump the destination address. */
2502 /* Update the previous insn information. */
2503 prev_prev_insn = *ip;
2504 prev_insn.insn_mo = &dummy_opcode;
2508 /* It looks like we can actually do the swap. */
2509 if (! mips_opts.mips16)
2514 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2515 memcpy (temp, prev_f, 4);
2516 memcpy (prev_f, f, 4);
2517 memcpy (f, temp, 4);
2518 if (prev_insn_fixp[0])
2520 prev_insn_fixp[0]->fx_frag = frag_now;
2521 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2523 if (prev_insn_fixp[1])
2525 prev_insn_fixp[1]->fx_frag = frag_now;
2526 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2528 if (prev_insn_fixp[2])
2530 prev_insn_fixp[2]->fx_frag = frag_now;
2531 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2535 fixp[0]->fx_frag = prev_insn_frag;
2536 fixp[0]->fx_where = prev_insn_where;
2540 fixp[1]->fx_frag = prev_insn_frag;
2541 fixp[1]->fx_where = prev_insn_where;
2545 fixp[2]->fx_frag = prev_insn_frag;
2546 fixp[2]->fx_where = prev_insn_where;
2554 assert (prev_insn_fixp[0] == NULL);
2555 assert (prev_insn_fixp[1] == NULL);
2556 assert (prev_insn_fixp[2] == NULL);
2557 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2558 memcpy (temp, prev_f, 2);
2559 memcpy (prev_f, f, 2);
2560 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2562 assert (*reloc_type == BFD_RELOC_UNUSED);
2563 memcpy (f, temp, 2);
2567 memcpy (f, f + 2, 2);
2568 memcpy (f + 2, temp, 2);
2572 fixp[0]->fx_frag = prev_insn_frag;
2573 fixp[0]->fx_where = prev_insn_where;
2577 fixp[1]->fx_frag = prev_insn_frag;
2578 fixp[1]->fx_where = prev_insn_where;
2582 fixp[2]->fx_frag = prev_insn_frag;
2583 fixp[2]->fx_where = prev_insn_where;
2587 /* Update the previous insn information; leave prev_insn
2589 prev_prev_insn = *ip;
2591 prev_insn_is_delay_slot = 1;
2593 /* If that was an unconditional branch, forget the previous
2594 insn information. */
2595 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2597 prev_prev_insn.insn_mo = &dummy_opcode;
2598 prev_insn.insn_mo = &dummy_opcode;
2601 prev_insn_fixp[0] = NULL;
2602 prev_insn_fixp[1] = NULL;
2603 prev_insn_fixp[2] = NULL;
2604 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2605 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2606 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2607 prev_insn_extended = 0;
2609 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2611 /* We don't yet optimize a branch likely. What we should do
2612 is look at the target, copy the instruction found there
2613 into the delay slot, and increment the branch to jump to
2614 the next instruction. */
2616 /* Update the previous insn information. */
2617 prev_prev_insn = *ip;
2618 prev_insn.insn_mo = &dummy_opcode;
2619 prev_insn_fixp[0] = NULL;
2620 prev_insn_fixp[1] = NULL;
2621 prev_insn_fixp[2] = NULL;
2622 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2623 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2624 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2625 prev_insn_extended = 0;
2629 /* Update the previous insn information. */
2631 prev_prev_insn.insn_mo = &dummy_opcode;
2633 prev_prev_insn = prev_insn;
2636 /* Any time we see a branch, we always fill the delay slot
2637 immediately; since this insn is not a branch, we know it
2638 is not in a delay slot. */
2639 prev_insn_is_delay_slot = 0;
2641 prev_insn_fixp[0] = fixp[0];
2642 prev_insn_fixp[1] = fixp[1];
2643 prev_insn_fixp[2] = fixp[2];
2644 prev_insn_reloc_type[0] = reloc_type[0];
2645 prev_insn_reloc_type[1] = reloc_type[1];
2646 prev_insn_reloc_type[2] = reloc_type[2];
2647 if (mips_opts.mips16)
2648 prev_insn_extended = (ip->use_extend
2649 || *reloc_type > BFD_RELOC_UNUSED);
2652 prev_prev_insn_unreordered = prev_insn_unreordered;
2653 prev_insn_unreordered = 0;
2654 prev_insn_frag = frag_now;
2655 prev_insn_where = f - frag_now->fr_literal;
2656 prev_insn_valid = 1;
2658 else if (place == NULL)
2660 /* We need to record a bit of information even when we are not
2661 reordering, in order to determine the base address for mips16
2662 PC relative relocs. */
2663 prev_prev_insn = prev_insn;
2665 prev_insn_reloc_type[0] = reloc_type[0];
2666 prev_insn_reloc_type[1] = reloc_type[1];
2667 prev_insn_reloc_type[2] = reloc_type[2];
2668 prev_prev_insn_unreordered = prev_insn_unreordered;
2669 prev_insn_unreordered = 1;
2672 /* We just output an insn, so the next one doesn't have a label. */
2673 mips_clear_insn_labels ();
2675 /* We must ensure that a fixup associated with an unmatched %hi
2676 reloc does not become a variant frag. Otherwise, the
2677 rearrangement of %hi relocs in frob_file may confuse
2681 frag_wane (frag_now);
2686 /* This function forgets that there was any previous instruction or
2687 label. If PRESERVE is non-zero, it remembers enough information to
2688 know whether nops are needed before a noreorder section. */
2691 mips_no_prev_insn (preserve)
2696 prev_insn.insn_mo = &dummy_opcode;
2697 prev_prev_insn.insn_mo = &dummy_opcode;
2698 prev_nop_frag = NULL;
2699 prev_nop_frag_holds = 0;
2700 prev_nop_frag_required = 0;
2701 prev_nop_frag_since = 0;
2703 prev_insn_valid = 0;
2704 prev_insn_is_delay_slot = 0;
2705 prev_insn_unreordered = 0;
2706 prev_insn_extended = 0;
2707 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2708 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2709 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2710 prev_prev_insn_unreordered = 0;
2711 mips_clear_insn_labels ();
2714 /* This function must be called whenever we turn on noreorder or emit
2715 something other than instructions. It inserts any NOPS which might
2716 be needed by the previous instruction, and clears the information
2717 kept for the previous instructions. The INSNS parameter is true if
2718 instructions are to follow. */
2721 mips_emit_delays (insns)
2724 if (! mips_opts.noreorder)
2729 if ((! mips_opts.mips16
2730 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2731 && (! cop_interlocks
2732 && (prev_insn.insn_mo->pinfo
2733 & (INSN_LOAD_COPROC_DELAY
2734 | INSN_COPROC_MOVE_DELAY
2735 | INSN_WRITE_COND_CODE))))
2736 || (! hilo_interlocks
2737 && (prev_insn.insn_mo->pinfo
2740 || (! mips_opts.mips16
2742 && (prev_insn.insn_mo->pinfo
2743 & INSN_LOAD_MEMORY_DELAY))
2744 || (! mips_opts.mips16
2745 && mips_opts.isa == ISA_MIPS1
2746 && (prev_insn.insn_mo->pinfo
2747 & INSN_COPROC_MEMORY_DELAY)))
2749 /* Itbl support may require additional care here. */
2751 if ((! mips_opts.mips16
2752 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2753 && (! cop_interlocks
2754 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2755 || (! hilo_interlocks
2756 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2757 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2760 if (prev_insn_unreordered)
2763 else if ((! mips_opts.mips16
2764 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2765 && (! cop_interlocks
2766 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2767 || (! hilo_interlocks
2768 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2769 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2771 /* Itbl support may require additional care here. */
2772 if (! prev_prev_insn_unreordered)
2778 struct insn_label_list *l;
2782 /* Record the frag which holds the nop instructions, so
2783 that we can remove them if we don't need them. */
2784 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2785 prev_nop_frag = frag_now;
2786 prev_nop_frag_holds = nops;
2787 prev_nop_frag_required = 0;
2788 prev_nop_frag_since = 0;
2791 for (; nops > 0; --nops)
2796 /* Move on to a new frag, so that it is safe to simply
2797 decrease the size of prev_nop_frag. */
2798 frag_wane (frag_now);
2802 for (l = insn_labels; l != NULL; l = l->next)
2806 assert (S_GET_SEGMENT (l->label) == now_seg);
2807 symbol_set_frag (l->label, frag_now);
2808 val = (valueT) frag_now_fix ();
2809 /* mips16 text labels are stored as odd. */
2810 if (mips_opts.mips16)
2812 S_SET_VALUE (l->label, val);
2817 /* Mark instruction labels in mips16 mode. */
2818 if (mips_opts.mips16 && insns)
2819 mips16_mark_labels ();
2821 mips_no_prev_insn (insns);
2824 /* Build an instruction created by a macro expansion. This is passed
2825 a pointer to the count of instructions created so far, an
2826 expression, the name of the instruction to build, an operand format
2827 string, and corresponding arguments. */
2831 macro_build (char *place,
2839 macro_build (place, counter, ep, name, fmt, va_alist)
2848 struct mips_cl_insn insn;
2849 bfd_reloc_code_real_type r[3];
2853 va_start (args, fmt);
2859 * If the macro is about to expand into a second instruction,
2860 * print a warning if needed. We need to pass ip as a parameter
2861 * to generate a better warning message here...
2863 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2864 as_warn (_("Macro instruction expanded into multiple instructions"));
2867 *counter += 1; /* bump instruction counter */
2869 if (mips_opts.mips16)
2871 mips16_macro_build (place, counter, ep, name, fmt, args);
2876 r[0] = BFD_RELOC_UNUSED;
2877 r[1] = BFD_RELOC_UNUSED;
2878 r[2] = BFD_RELOC_UNUSED;
2879 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2880 assert (insn.insn_mo);
2881 assert (strcmp (name, insn.insn_mo->name) == 0);
2883 /* Search until we get a match for NAME. */
2886 if (strcmp (fmt, insn.insn_mo->args) == 0
2887 && insn.insn_mo->pinfo != INSN_MACRO
2888 && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
2889 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2893 assert (insn.insn_mo->name);
2894 assert (strcmp (name, insn.insn_mo->name) == 0);
2897 insn.insn_opcode = insn.insn_mo->match;
2913 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2917 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2922 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2927 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2932 int tmp = va_arg (args, int);
2934 insn.insn_opcode |= tmp << OP_SH_RT;
2935 insn.insn_opcode |= tmp << OP_SH_RD;
2941 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2948 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2952 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2956 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2960 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2964 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2971 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2977 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2978 assert (*r == BFD_RELOC_GPREL16
2979 || *r == BFD_RELOC_MIPS_LITERAL
2980 || *r == BFD_RELOC_MIPS_HIGHER
2981 || *r == BFD_RELOC_HI16_S
2982 || *r == BFD_RELOC_LO16
2983 || *r == BFD_RELOC_MIPS_GOT16
2984 || *r == BFD_RELOC_MIPS_CALL16
2985 || *r == BFD_RELOC_MIPS_GOT_LO16
2986 || *r == BFD_RELOC_MIPS_CALL_LO16
2987 || (ep->X_op == O_subtract
2988 && *r == BFD_RELOC_PCREL_LO16));
2992 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2994 && (ep->X_op == O_constant
2995 || (ep->X_op == O_symbol
2996 && (*r == BFD_RELOC_MIPS_HIGHEST
2997 || *r == BFD_RELOC_HI16_S
2998 || *r == BFD_RELOC_HI16
2999 || *r == BFD_RELOC_GPREL16
3000 || *r == BFD_RELOC_MIPS_GOT_HI16
3001 || *r == BFD_RELOC_MIPS_CALL_HI16))
3002 || (ep->X_op == O_subtract
3003 && *r == BFD_RELOC_PCREL_HI16_S)));
3007 assert (ep != NULL);
3009 * This allows macro() to pass an immediate expression for
3010 * creating short branches without creating a symbol.
3011 * Note that the expression still might come from the assembly
3012 * input, in which case the value is not checked for range nor
3013 * is a relocation entry generated (yuck).
3015 if (ep->X_op == O_constant)
3017 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3021 if (mips_pic == EMBEDDED_PIC)
3022 *r = BFD_RELOC_16_PCREL_S2;
3024 *r = BFD_RELOC_16_PCREL;
3028 assert (ep != NULL);
3029 *r = BFD_RELOC_MIPS_JMP;
3033 insn.insn_opcode |= va_arg (args, unsigned long);
3042 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3044 append_insn (place, &insn, ep, r, false);
3048 mips16_macro_build (place, counter, ep, name, fmt, args)
3050 int *counter ATTRIBUTE_UNUSED;
3056 struct mips_cl_insn insn;
3057 bfd_reloc_code_real_type r[3]
3058 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3060 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3061 assert (insn.insn_mo);
3062 assert (strcmp (name, insn.insn_mo->name) == 0);
3064 while (strcmp (fmt, insn.insn_mo->args) != 0
3065 || insn.insn_mo->pinfo == INSN_MACRO)
3068 assert (insn.insn_mo->name);
3069 assert (strcmp (name, insn.insn_mo->name) == 0);
3072 insn.insn_opcode = insn.insn_mo->match;
3073 insn.use_extend = false;
3092 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3097 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3101 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3105 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3115 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3122 regno = va_arg (args, int);
3123 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3124 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3145 assert (ep != NULL);
3147 if (ep->X_op != O_constant)
3148 *r = BFD_RELOC_UNUSED + c;
3151 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
3152 false, &insn.insn_opcode, &insn.use_extend,
3155 *r = BFD_RELOC_UNUSED;
3161 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3168 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3170 append_insn (place, &insn, ep, r, false);
3174 * Generate a "lui" instruction.
3177 macro_build_lui (place, counter, ep, regnum)
3183 expressionS high_expr;
3184 struct mips_cl_insn insn;
3185 bfd_reloc_code_real_type r[3]
3186 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3187 CONST char *name = "lui";
3188 CONST char *fmt = "t,u";
3190 assert (! mips_opts.mips16);
3196 high_expr.X_op = O_constant;
3197 high_expr.X_add_number = ep->X_add_number;
3200 if (high_expr.X_op == O_constant)
3202 /* we can compute the instruction now without a relocation entry */
3203 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3205 *r = BFD_RELOC_UNUSED;
3207 else if (! HAVE_NEWABI)
3209 assert (ep->X_op == O_symbol);
3210 /* _gp_disp is a special case, used from s_cpload. */
3211 assert (mips_pic == NO_PIC
3212 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3213 *r = BFD_RELOC_HI16_S;
3217 * If the macro is about to expand into a second instruction,
3218 * print a warning if needed. We need to pass ip as a parameter
3219 * to generate a better warning message here...
3221 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3222 as_warn (_("Macro instruction expanded into multiple instructions"));
3225 *counter += 1; /* bump instruction counter */
3227 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3228 assert (insn.insn_mo);
3229 assert (strcmp (name, insn.insn_mo->name) == 0);
3230 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3232 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3233 if (*r == BFD_RELOC_UNUSED)
3235 insn.insn_opcode |= high_expr.X_add_number;
3236 append_insn (place, &insn, NULL, r, false);
3239 append_insn (place, &insn, &high_expr, r, false);
3243 * Generates code to set the $at register to true (one)
3244 * if reg is less than the immediate expression.
3247 set_at (counter, reg, unsignedp)
3252 if (imm_expr.X_op == O_constant
3253 && imm_expr.X_add_number >= -0x8000
3254 && imm_expr.X_add_number < 0x8000)
3255 macro_build ((char *) NULL, counter, &imm_expr,
3256 unsignedp ? "sltiu" : "slti",
3257 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3260 load_register (counter, AT, &imm_expr, 0);
3261 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3262 unsignedp ? "sltu" : "slt",
3263 "d,v,t", AT, reg, AT);
3267 /* Warn if an expression is not a constant. */
3270 check_absolute_expr (ip, ex)
3271 struct mips_cl_insn *ip;
3274 if (ex->X_op == O_big)
3275 as_bad (_("unsupported large constant"));
3276 else if (ex->X_op != O_constant)
3277 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3280 /* Count the leading zeroes by performing a binary chop. This is a
3281 bulky bit of source, but performance is a LOT better for the
3282 majority of values than a simple loop to count the bits:
3283 for (lcnt = 0; (lcnt < 32); lcnt++)
3284 if ((v) & (1 << (31 - lcnt)))
3286 However it is not code size friendly, and the gain will drop a bit
3287 on certain cached systems.
3289 #define COUNT_TOP_ZEROES(v) \
3290 (((v) & ~0xffff) == 0 \
3291 ? ((v) & ~0xff) == 0 \
3292 ? ((v) & ~0xf) == 0 \
3293 ? ((v) & ~0x3) == 0 \
3294 ? ((v) & ~0x1) == 0 \
3299 : ((v) & ~0x7) == 0 \
3302 : ((v) & ~0x3f) == 0 \
3303 ? ((v) & ~0x1f) == 0 \
3306 : ((v) & ~0x7f) == 0 \
3309 : ((v) & ~0xfff) == 0 \
3310 ? ((v) & ~0x3ff) == 0 \
3311 ? ((v) & ~0x1ff) == 0 \
3314 : ((v) & ~0x7ff) == 0 \
3317 : ((v) & ~0x3fff) == 0 \
3318 ? ((v) & ~0x1fff) == 0 \
3321 : ((v) & ~0x7fff) == 0 \
3324 : ((v) & ~0xffffff) == 0 \
3325 ? ((v) & ~0xfffff) == 0 \
3326 ? ((v) & ~0x3ffff) == 0 \
3327 ? ((v) & ~0x1ffff) == 0 \
3330 : ((v) & ~0x7ffff) == 0 \
3333 : ((v) & ~0x3fffff) == 0 \
3334 ? ((v) & ~0x1fffff) == 0 \
3337 : ((v) & ~0x7fffff) == 0 \
3340 : ((v) & ~0xfffffff) == 0 \
3341 ? ((v) & ~0x3ffffff) == 0 \
3342 ? ((v) & ~0x1ffffff) == 0 \
3345 : ((v) & ~0x7ffffff) == 0 \
3348 : ((v) & ~0x3fffffff) == 0 \
3349 ? ((v) & ~0x1fffffff) == 0 \
3352 : ((v) & ~0x7fffffff) == 0 \
3357 * This routine generates the least number of instructions neccessary to load
3358 * an absolute expression value into a register.
3361 load_register (counter, reg, ep, dbl)
3368 expressionS hi32, lo32;
3370 if (ep->X_op != O_big)
3372 assert (ep->X_op == O_constant);
3373 if (ep->X_add_number < 0x8000
3374 && (ep->X_add_number >= 0
3375 || (ep->X_add_number >= -0x8000
3378 || sizeof (ep->X_add_number) > 4))))
3380 /* We can handle 16 bit signed values with an addiu to
3381 $zero. No need to ever use daddiu here, since $zero and
3382 the result are always correct in 32 bit mode. */
3383 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3384 (int) BFD_RELOC_LO16);
3387 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3389 /* We can handle 16 bit unsigned values with an ori to
3391 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3392 (int) BFD_RELOC_LO16);
3395 else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0
3396 || ((ep->X_add_number &~ (offsetT) 0x7fffffff)
3397 == ~ (offsetT) 0x7fffffff))
3400 || sizeof (ep->X_add_number) > 4
3401 || (ep->X_add_number & 0x80000000) == 0))
3402 || ((HAVE_32BIT_GPRS || ! dbl)
3403 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3406 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3407 == ~ (offsetT) 0xffffffff)))
3409 /* 32 bit values require an lui. */
3410 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3411 (int) BFD_RELOC_HI16);
3412 if ((ep->X_add_number & 0xffff) != 0)
3413 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3414 (int) BFD_RELOC_LO16);
3419 /* The value is larger than 32 bits. */
3421 if (HAVE_32BIT_GPRS)
3423 as_bad (_("Number (0x%lx) larger than 32 bits"),
3424 (unsigned long) ep->X_add_number);
3425 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3426 (int) BFD_RELOC_LO16);
3430 if (ep->X_op != O_big)
3433 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3434 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3435 hi32.X_add_number &= 0xffffffff;
3437 lo32.X_add_number &= 0xffffffff;
3441 assert (ep->X_add_number > 2);
3442 if (ep->X_add_number == 3)
3443 generic_bignum[3] = 0;
3444 else if (ep->X_add_number > 4)
3445 as_bad (_("Number larger than 64 bits"));
3446 lo32.X_op = O_constant;
3447 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3448 hi32.X_op = O_constant;
3449 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3452 if (hi32.X_add_number == 0)
3457 unsigned long hi, lo;
3459 if (hi32.X_add_number == (offsetT) 0xffffffff)
3461 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3463 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3464 reg, 0, (int) BFD_RELOC_LO16);
3467 if (lo32.X_add_number & 0x80000000)
3469 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3470 (int) BFD_RELOC_HI16);
3471 if (lo32.X_add_number & 0xffff)
3472 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3473 reg, reg, (int) BFD_RELOC_LO16);
3478 /* Check for 16bit shifted constant. We know that hi32 is
3479 non-zero, so start the mask on the first bit of the hi32
3484 unsigned long himask, lomask;
3488 himask = 0xffff >> (32 - shift);
3489 lomask = (0xffff << shift) & 0xffffffff;
3493 himask = 0xffff << (shift - 32);
3496 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3497 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3501 tmp.X_op = O_constant;
3503 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3504 | (lo32.X_add_number >> shift));
3506 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3507 macro_build ((char *) NULL, counter, &tmp,
3508 "ori", "t,r,i", reg, 0,
3509 (int) BFD_RELOC_LO16);
3510 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3511 (shift >= 32) ? "dsll32" : "dsll",
3513 (shift >= 32) ? shift - 32 : shift);
3518 while (shift <= (64 - 16));
3520 /* Find the bit number of the lowest one bit, and store the
3521 shifted value in hi/lo. */
3522 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3523 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3527 while ((lo & 1) == 0)
3532 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3538 while ((hi & 1) == 0)
3547 /* Optimize if the shifted value is a (power of 2) - 1. */
3548 if ((hi == 0 && ((lo + 1) & lo) == 0)
3549 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3551 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3556 /* This instruction will set the register to be all
3558 tmp.X_op = O_constant;
3559 tmp.X_add_number = (offsetT) -1;
3560 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3561 reg, 0, (int) BFD_RELOC_LO16);
3565 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3566 (bit >= 32) ? "dsll32" : "dsll",
3568 (bit >= 32) ? bit - 32 : bit);
3570 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3571 (shift >= 32) ? "dsrl32" : "dsrl",
3573 (shift >= 32) ? shift - 32 : shift);
3578 /* Sign extend hi32 before calling load_register, because we can
3579 generally get better code when we load a sign extended value. */
3580 if ((hi32.X_add_number & 0x80000000) != 0)
3581 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3582 load_register (counter, reg, &hi32, 0);
3585 if ((lo32.X_add_number & 0xffff0000) == 0)
3589 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3590 "dsll32", "d,w,<", reg, freg, 0);
3598 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3600 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3601 (int) BFD_RELOC_HI16);
3602 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3603 "dsrl32", "d,w,<", reg, reg, 0);
3609 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3610 "d,w,<", reg, freg, 16);
3614 mid16.X_add_number >>= 16;
3615 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3616 freg, (int) BFD_RELOC_LO16);
3617 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3618 "d,w,<", reg, reg, 16);
3621 if ((lo32.X_add_number & 0xffff) != 0)
3622 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3623 (int) BFD_RELOC_LO16);
3626 /* Load an address into a register. */
3629 load_address (counter, reg, ep, dbl, used_at)
3638 if (ep->X_op != O_constant
3639 && ep->X_op != O_symbol)
3641 as_bad (_("expression too complex"));
3642 ep->X_op = O_constant;
3645 if (ep->X_op == O_constant)
3647 load_register (counter, reg, ep, dbl);
3651 if (mips_pic == NO_PIC)
3653 /* If this is a reference to a GP relative symbol, we want
3654 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3656 lui $reg,<sym> (BFD_RELOC_HI16_S)
3657 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3658 If we have an addend, we always use the latter form.
3660 With 64bit address space and a usable $at we want
3661 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3662 lui $at,<sym> (BFD_RELOC_HI16_S)
3663 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3664 daddiu $at,<sym> (BFD_RELOC_LO16)
3668 If $at is already in use, we use an path which is suboptimal
3669 on superscalar processors.
3670 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3671 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3673 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3675 daddiu $reg,<sym> (BFD_RELOC_LO16)
3681 /* We don't do GP optimization for now because RELAX_ENCODE can't
3682 hold the data for such large chunks. */
3686 macro_build (p, counter, ep, "lui", "t,u",
3687 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3688 macro_build (p, counter, ep, "lui", "t,u",
3689 AT, (int) BFD_RELOC_HI16_S);
3690 macro_build (p, counter, ep, "daddiu", "t,r,j",
3691 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3692 macro_build (p, counter, ep, "daddiu", "t,r,j",
3693 AT, AT, (int) BFD_RELOC_LO16);
3694 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3695 "d,w,<", reg, reg, 0);
3696 macro_build (p, counter, (expressionS *) NULL, "dadd",
3697 "d,v,t", reg, reg, AT);
3702 macro_build (p, counter, ep, "lui", "t,u",
3703 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3704 macro_build (p, counter, ep, "daddiu", "t,r,j",
3705 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3706 macro_build (p, counter, (expressionS *) NULL, "dsll",
3707 "d,w,<", reg, reg, 16);
3708 macro_build (p, counter, ep, "daddiu", "t,r,j",
3709 reg, reg, (int) BFD_RELOC_HI16_S);
3710 macro_build (p, counter, (expressionS *) NULL, "dsll",
3711 "d,w,<", reg, reg, 16);
3712 macro_build (p, counter, ep, "daddiu", "t,r,j",
3713 reg, reg, (int) BFD_RELOC_LO16);
3719 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3720 && ! nopic_need_relax (ep->X_add_symbol, 1))
3723 macro_build ((char *) NULL, counter, ep,
3724 dbl ? "daddiu" : "addiu", "t,r,j", reg, GP,
3725 (int) BFD_RELOC_GPREL16);
3726 p = frag_var (rs_machine_dependent, 8, 0,
3727 RELAX_ENCODE (4, 8, 0, 4, 0,
3728 mips_opts.warn_about_macros),
3729 ep->X_add_symbol, 0, NULL);
3731 macro_build_lui (p, counter, ep, reg);
3734 macro_build (p, counter, ep, dbl ? "daddiu" : "addiu",
3735 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3738 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3742 /* If this is a reference to an external symbol, we want
3743 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3745 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3747 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3748 If there is a constant, it must be added in after. */
3749 ex.X_add_number = ep->X_add_number;
3750 ep->X_add_number = 0;
3752 macro_build ((char *) NULL, counter, ep,
3753 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3754 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
3755 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3756 p = frag_var (rs_machine_dependent, 4, 0,
3757 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3758 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3759 macro_build (p, counter, ep,
3760 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3761 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3762 if (ex.X_add_number != 0)
3764 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3765 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3766 ex.X_op = O_constant;
3767 macro_build ((char *) NULL, counter, &ex,
3768 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3769 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3772 else if (mips_pic == SVR4_PIC)
3777 /* This is the large GOT case. If this is a reference to an
3778 external symbol, we want
3779 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3781 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3782 Otherwise, for a reference to a local symbol, we want
3783 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3785 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3786 If there is a constant, it must be added in after. */
3787 ex.X_add_number = ep->X_add_number;
3788 ep->X_add_number = 0;
3789 if (reg_needs_delay (GP))
3794 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3795 (int) BFD_RELOC_MIPS_GOT_HI16);
3796 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3797 dbl ? "daddu" : "addu", "d,v,t", reg, reg, GP);
3798 macro_build ((char *) NULL, counter, ep, dbl ? "ld" : "lw",
3799 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3800 p = frag_var (rs_machine_dependent, 12 + off, 0,
3801 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3802 mips_opts.warn_about_macros),
3803 ep->X_add_symbol, 0, NULL);
3806 /* We need a nop before loading from $gp. This special
3807 check is required because the lui which starts the main
3808 instruction stream does not refer to $gp, and so will not
3809 insert the nop which may be required. */
3810 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3813 macro_build (p, counter, ep, dbl ? "ld" : "lw",
3814 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
3816 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3818 macro_build (p, counter, ep, dbl ? "daddiu" : "addiu",
3819 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3820 if (ex.X_add_number != 0)
3822 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3823 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3824 ex.X_op = O_constant;
3825 macro_build ((char *) NULL, counter, &ex, dbl ? "daddiu" : "addiu",
3826 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3829 else if (mips_pic == EMBEDDED_PIC)
3832 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3834 macro_build ((char *) NULL, counter, ep, dbl ? "daddiu" : "addiu",
3835 "t,r,j", reg, GP, (int) BFD_RELOC_GPREL16);
3841 /* Move the contents of register SOURCE into register DEST. */
3844 move_register (counter, dest, source)
3849 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3850 HAVE_32BIT_GPRS ? "addu" : "daddu",
3851 "d,v,t", dest, source, 0);
3856 * This routine implements the seemingly endless macro or synthesized
3857 * instructions and addressing modes in the mips assembly language. Many
3858 * of these macros are simple and are similar to each other. These could
3859 * probably be handled by some kind of table or grammer aproach instead of
3860 * this verbose method. Others are not simple macros but are more like
3861 * optimizing code generation.
3862 * One interesting optimization is when several store macros appear
3863 * consecutivly that would load AT with the upper half of the same address.
3864 * The ensuing load upper instructions are ommited. This implies some kind
3865 * of global optimization. We currently only optimize within a single macro.
3866 * For many of the load and store macros if the address is specified as a
3867 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3868 * first load register 'at' with zero and use it as the base register. The
3869 * mips assembler simply uses register $zero. Just one tiny optimization
3874 struct mips_cl_insn *ip;
3876 register int treg, sreg, dreg, breg;
3892 bfd_reloc_code_real_type r;
3894 int hold_mips_optimize;
3896 assert (! mips_opts.mips16);
3898 treg = (ip->insn_opcode >> 16) & 0x1f;
3899 dreg = (ip->insn_opcode >> 11) & 0x1f;
3900 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3901 mask = ip->insn_mo->mask;
3903 expr1.X_op = O_constant;
3904 expr1.X_op_symbol = NULL;
3905 expr1.X_add_symbol = NULL;
3906 expr1.X_add_number = 1;
3918 mips_emit_delays (true);
3919 ++mips_opts.noreorder;
3920 mips_any_noreorder = 1;
3922 expr1.X_add_number = 8;
3923 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3925 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3928 move_register (&icnt, dreg, sreg);
3929 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3930 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3932 --mips_opts.noreorder;
3953 if (imm_expr.X_op == O_constant
3954 && imm_expr.X_add_number >= -0x8000
3955 && imm_expr.X_add_number < 0x8000)
3957 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3958 (int) BFD_RELOC_LO16);
3961 load_register (&icnt, AT, &imm_expr, dbl);
3962 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3982 if (imm_expr.X_op == O_constant
3983 && imm_expr.X_add_number >= 0
3984 && imm_expr.X_add_number < 0x10000)
3986 if (mask != M_NOR_I)
3987 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3988 sreg, (int) BFD_RELOC_LO16);
3991 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3992 treg, sreg, (int) BFD_RELOC_LO16);
3993 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
3994 "d,v,t", treg, treg, 0);
3999 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4000 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4018 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4020 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
4024 load_register (&icnt, AT, &imm_expr, 0);
4025 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4033 macro_build ((char *) NULL, &icnt, &offset_expr,
4034 likely ? "bgezl" : "bgez", "s,p", sreg);
4039 macro_build ((char *) NULL, &icnt, &offset_expr,
4040 likely ? "blezl" : "blez", "s,p", treg);
4043 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4045 macro_build ((char *) NULL, &icnt, &offset_expr,
4046 likely ? "beql" : "beq", "s,t,p", AT, 0);
4052 /* check for > max integer */
4053 maxnum = 0x7fffffff;
4054 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4061 if (imm_expr.X_op == O_constant
4062 && imm_expr.X_add_number >= maxnum
4063 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4066 /* result is always false */
4070 as_warn (_("Branch %s is always false (nop)"),
4072 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
4078 as_warn (_("Branch likely %s is always false"),
4080 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
4085 if (imm_expr.X_op != O_constant)
4086 as_bad (_("Unsupported large constant"));
4087 imm_expr.X_add_number++;
4091 if (mask == M_BGEL_I)
4093 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4095 macro_build ((char *) NULL, &icnt, &offset_expr,
4096 likely ? "bgezl" : "bgez", "s,p", sreg);
4099 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4101 macro_build ((char *) NULL, &icnt, &offset_expr,
4102 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4105 maxnum = 0x7fffffff;
4106 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4113 maxnum = - maxnum - 1;
4114 if (imm_expr.X_op == O_constant
4115 && imm_expr.X_add_number <= maxnum
4116 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4119 /* result is always true */
4120 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4121 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4124 set_at (&icnt, sreg, 0);
4125 macro_build ((char *) NULL, &icnt, &offset_expr,
4126 likely ? "beql" : "beq", "s,t,p", AT, 0);
4136 macro_build ((char *) NULL, &icnt, &offset_expr,
4137 likely ? "beql" : "beq", "s,t,p", 0, treg);
4140 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4141 "d,v,t", AT, sreg, treg);
4142 macro_build ((char *) NULL, &icnt, &offset_expr,
4143 likely ? "beql" : "beq", "s,t,p", AT, 0);
4151 && imm_expr.X_op == O_constant
4152 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4154 if (imm_expr.X_op != O_constant)
4155 as_bad (_("Unsupported large constant"));
4156 imm_expr.X_add_number++;
4160 if (mask == M_BGEUL_I)
4162 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4164 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4166 macro_build ((char *) NULL, &icnt, &offset_expr,
4167 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4170 set_at (&icnt, sreg, 1);
4171 macro_build ((char *) NULL, &icnt, &offset_expr,
4172 likely ? "beql" : "beq", "s,t,p", AT, 0);
4180 macro_build ((char *) NULL, &icnt, &offset_expr,
4181 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4186 macro_build ((char *) NULL, &icnt, &offset_expr,
4187 likely ? "bltzl" : "bltz", "s,p", treg);
4190 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4192 macro_build ((char *) NULL, &icnt, &offset_expr,
4193 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4201 macro_build ((char *) NULL, &icnt, &offset_expr,
4202 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4207 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4208 "d,v,t", AT, treg, sreg);
4209 macro_build ((char *) NULL, &icnt, &offset_expr,
4210 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4218 macro_build ((char *) NULL, &icnt, &offset_expr,
4219 likely ? "blezl" : "blez", "s,p", sreg);
4224 macro_build ((char *) NULL, &icnt, &offset_expr,
4225 likely ? "bgezl" : "bgez", "s,p", treg);
4228 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4230 macro_build ((char *) NULL, &icnt, &offset_expr,
4231 likely ? "beql" : "beq", "s,t,p", AT, 0);
4237 maxnum = 0x7fffffff;
4238 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4245 if (imm_expr.X_op == O_constant
4246 && imm_expr.X_add_number >= maxnum
4247 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4249 if (imm_expr.X_op != O_constant)
4250 as_bad (_("Unsupported large constant"));
4251 imm_expr.X_add_number++;
4255 if (mask == M_BLTL_I)
4257 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4259 macro_build ((char *) NULL, &icnt, &offset_expr,
4260 likely ? "bltzl" : "bltz", "s,p", sreg);
4263 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4265 macro_build ((char *) NULL, &icnt, &offset_expr,
4266 likely ? "blezl" : "blez", "s,p", sreg);
4269 set_at (&icnt, sreg, 0);
4270 macro_build ((char *) NULL, &icnt, &offset_expr,
4271 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4279 macro_build ((char *) NULL, &icnt, &offset_expr,
4280 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4285 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4286 "d,v,t", AT, treg, sreg);
4287 macro_build ((char *) NULL, &icnt, &offset_expr,
4288 likely ? "beql" : "beq", "s,t,p", AT, 0);
4296 && imm_expr.X_op == O_constant
4297 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4299 if (imm_expr.X_op != O_constant)
4300 as_bad (_("Unsupported large constant"));
4301 imm_expr.X_add_number++;
4305 if (mask == M_BLTUL_I)
4307 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4309 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4311 macro_build ((char *) NULL, &icnt, &offset_expr,
4312 likely ? "beql" : "beq",
4316 set_at (&icnt, sreg, 1);
4317 macro_build ((char *) NULL, &icnt, &offset_expr,
4318 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4326 macro_build ((char *) NULL, &icnt, &offset_expr,
4327 likely ? "bltzl" : "bltz", "s,p", sreg);
4332 macro_build ((char *) NULL, &icnt, &offset_expr,
4333 likely ? "bgtzl" : "bgtz", "s,p", treg);
4336 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4338 macro_build ((char *) NULL, &icnt, &offset_expr,
4339 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4349 macro_build ((char *) NULL, &icnt, &offset_expr,
4350 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4353 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4356 macro_build ((char *) NULL, &icnt, &offset_expr,
4357 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4372 as_warn (_("Divide by zero."));
4374 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4377 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4382 mips_emit_delays (true);
4383 ++mips_opts.noreorder;
4384 mips_any_noreorder = 1;
4387 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4389 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4390 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4394 expr1.X_add_number = 8;
4395 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4396 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4397 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4398 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4401 expr1.X_add_number = -1;
4402 macro_build ((char *) NULL, &icnt, &expr1,
4403 dbl ? "daddiu" : "addiu",
4404 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4405 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4406 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4409 expr1.X_add_number = 1;
4410 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4411 (int) BFD_RELOC_LO16);
4412 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4413 "d,w,<", AT, AT, 31);
4417 expr1.X_add_number = 0x80000000;
4418 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4419 (int) BFD_RELOC_HI16);
4423 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4425 /* We want to close the noreorder block as soon as possible, so
4426 that later insns are available for delay slot filling. */
4427 --mips_opts.noreorder;
4431 expr1.X_add_number = 8;
4432 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4433 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4436 /* We want to close the noreorder block as soon as possible, so
4437 that later insns are available for delay slot filling. */
4438 --mips_opts.noreorder;
4440 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4443 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4482 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4484 as_warn (_("Divide by zero."));
4486 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4489 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4493 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4495 if (strcmp (s2, "mflo") == 0)
4496 move_register (&icnt, dreg, sreg);
4498 move_register (&icnt, dreg, 0);
4501 if (imm_expr.X_op == O_constant
4502 && imm_expr.X_add_number == -1
4503 && s[strlen (s) - 1] != 'u')
4505 if (strcmp (s2, "mflo") == 0)
4507 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4508 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4511 move_register (&icnt, dreg, 0);
4515 load_register (&icnt, AT, &imm_expr, dbl);
4516 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4518 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4537 mips_emit_delays (true);
4538 ++mips_opts.noreorder;
4539 mips_any_noreorder = 1;
4542 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4544 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4546 /* We want to close the noreorder block as soon as possible, so
4547 that later insns are available for delay slot filling. */
4548 --mips_opts.noreorder;
4552 expr1.X_add_number = 8;
4553 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4554 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4557 /* We want to close the noreorder block as soon as possible, so
4558 that later insns are available for delay slot filling. */
4559 --mips_opts.noreorder;
4560 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4563 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4569 /* Load the address of a symbol into a register. If breg is not
4570 zero, we then add a base register to it. */
4583 /* When generating embedded PIC code, we permit expressions of
4586 la $treg,foo-bar($breg)
4587 where bar is an address in the current section. These are used
4588 when getting the addresses of functions. We don't permit
4589 X_add_number to be non-zero, because if the symbol is
4590 external the relaxing code needs to know that any addend is
4591 purely the offset to X_op_symbol. */
4592 if (mips_pic == EMBEDDED_PIC
4593 && offset_expr.X_op == O_subtract
4594 && (symbol_constant_p (offset_expr.X_op_symbol)
4595 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4596 : (symbol_equated_p (offset_expr.X_op_symbol)
4598 (symbol_get_value_expression (offset_expr.X_op_symbol)
4601 && (offset_expr.X_add_number == 0
4602 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4608 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4609 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4613 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4614 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4615 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4616 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4617 "d,v,t", tempreg, tempreg, breg);
4619 macro_build ((char *) NULL, &icnt, &offset_expr,
4620 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4621 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4627 if (offset_expr.X_op != O_symbol
4628 && offset_expr.X_op != O_constant)
4630 as_bad (_("expression too complex"));
4631 offset_expr.X_op = O_constant;
4634 if (offset_expr.X_op == O_constant)
4635 load_register (&icnt, tempreg, &offset_expr, dbl);
4636 else if (mips_pic == NO_PIC)
4638 /* If this is a reference to a GP relative symbol, we want
4639 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4641 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4642 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4643 If we have a constant, we need two instructions anyhow,
4644 so we may as well always use the latter form.
4646 With 64bit address space and a usable $at we want
4647 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4648 lui $at,<sym> (BFD_RELOC_HI16_S)
4649 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4650 daddiu $at,<sym> (BFD_RELOC_LO16)
4652 dadd $tempreg,$tempreg,$at
4654 If $at is already in use, we use an path which is suboptimal
4655 on superscalar processors.
4656 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4657 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4659 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4661 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4664 if (HAVE_64BIT_ADDRESSES)
4666 /* We don't do GP optimization for now because RELAX_ENCODE can't
4667 hold the data for such large chunks. */
4671 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4672 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4673 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4674 AT, (int) BFD_RELOC_HI16_S);
4675 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4676 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4677 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4678 AT, AT, (int) BFD_RELOC_LO16);
4679 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4680 "d,w,<", tempreg, tempreg, 0);
4681 macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t",
4682 tempreg, tempreg, AT);
4687 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4688 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4689 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4690 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4691 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4692 tempreg, tempreg, 16);
4693 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4694 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4695 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4696 tempreg, tempreg, 16);
4697 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4698 tempreg, tempreg, (int) BFD_RELOC_LO16);
4703 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4704 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4707 macro_build ((char *) NULL, &icnt, &offset_expr,
4708 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4709 "t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16);
4710 p = frag_var (rs_machine_dependent, 8, 0,
4711 RELAX_ENCODE (4, 8, 0, 4, 0,
4712 mips_opts.warn_about_macros),
4713 offset_expr.X_add_symbol, 0, NULL);
4715 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4718 macro_build (p, &icnt, &offset_expr,
4719 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4720 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4723 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4725 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4727 /* If this is a reference to an external symbol, and there
4728 is no constant, we want
4729 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4730 or if tempreg is PIC_CALL_REG
4731 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4732 For a local symbol, we want
4733 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4735 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4737 If we have a small constant, and this is a reference to
4738 an external symbol, we want
4739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4741 addiu $tempreg,$tempreg,<constant>
4742 For a local symbol, we want the same instruction
4743 sequence, but we output a BFD_RELOC_LO16 reloc on the
4746 If we have a large constant, and this is a reference to
4747 an external symbol, we want
4748 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4749 lui $at,<hiconstant>
4750 addiu $at,$at,<loconstant>
4751 addu $tempreg,$tempreg,$at
4752 For a local symbol, we want the same instruction
4753 sequence, but we output a BFD_RELOC_LO16 reloc on the
4754 addiu instruction. */
4755 expr1.X_add_number = offset_expr.X_add_number;
4756 offset_expr.X_add_number = 0;
4758 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4759 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4760 macro_build ((char *) NULL, &icnt, &offset_expr, dbl ? "ld" : "lw",
4761 "t,o(b)", tempreg, lw_reloc_type, GP);
4762 if (expr1.X_add_number == 0)
4770 /* We're going to put in an addu instruction using
4771 tempreg, so we may as well insert the nop right
4773 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4777 p = frag_var (rs_machine_dependent, 8 - off, 0,
4778 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4780 ? mips_opts.warn_about_macros
4782 offset_expr.X_add_symbol, 0, NULL);
4785 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4788 macro_build (p, &icnt, &expr1,
4789 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4790 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4791 /* FIXME: If breg == 0, and the next instruction uses
4792 $tempreg, then if this variant case is used an extra
4793 nop will be generated. */
4795 else if (expr1.X_add_number >= -0x8000
4796 && expr1.X_add_number < 0x8000)
4798 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4800 macro_build ((char *) NULL, &icnt, &expr1,
4801 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4802 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4803 frag_var (rs_machine_dependent, 0, 0,
4804 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4805 offset_expr.X_add_symbol, 0, NULL);
4811 /* If we are going to add in a base register, and the
4812 target register and the base register are the same,
4813 then we are using AT as a temporary register. Since
4814 we want to load the constant into AT, we add our
4815 current AT (from the global offset table) and the
4816 register into the register now, and pretend we were
4817 not using a base register. */
4822 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4824 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4825 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4826 "d,v,t", treg, AT, breg);
4832 /* Set mips_optimize around the lui instruction to avoid
4833 inserting an unnecessary nop after the lw. */
4834 hold_mips_optimize = mips_optimize;
4836 macro_build_lui (NULL, &icnt, &expr1, AT);
4837 mips_optimize = hold_mips_optimize;
4839 macro_build ((char *) NULL, &icnt, &expr1,
4840 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4841 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4842 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4843 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4844 "d,v,t", tempreg, tempreg, AT);
4845 frag_var (rs_machine_dependent, 0, 0,
4846 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4847 offset_expr.X_add_symbol, 0, NULL);
4851 else if (mips_pic == SVR4_PIC)
4854 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4855 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4857 /* This is the large GOT case. If this is a reference to an
4858 external symbol, and there is no constant, we want
4859 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4860 addu $tempreg,$tempreg,$gp
4861 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4862 or if tempreg is PIC_CALL_REG
4863 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4864 addu $tempreg,$tempreg,$gp
4865 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4866 For a local symbol, we want
4867 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4869 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4871 If we have a small constant, and this is a reference to
4872 an external symbol, we want
4873 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4874 addu $tempreg,$tempreg,$gp
4875 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4877 addiu $tempreg,$tempreg,<constant>
4878 For a local symbol, we want
4879 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4881 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4883 If we have a large constant, and this is a reference to
4884 an external symbol, we want
4885 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4886 addu $tempreg,$tempreg,$gp
4887 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4888 lui $at,<hiconstant>
4889 addiu $at,$at,<loconstant>
4890 addu $tempreg,$tempreg,$at
4891 For a local symbol, we want
4892 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4893 lui $at,<hiconstant>
4894 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4895 addu $tempreg,$tempreg,$at
4897 expr1.X_add_number = offset_expr.X_add_number;
4898 offset_expr.X_add_number = 0;
4900 if (reg_needs_delay (GP))
4904 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4906 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4907 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4909 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4910 tempreg, lui_reloc_type);
4911 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4912 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4913 "d,v,t", tempreg, tempreg, GP);
4914 macro_build ((char *) NULL, &icnt, &offset_expr,
4916 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4917 if (expr1.X_add_number == 0)
4925 /* We're going to put in an addu instruction using
4926 tempreg, so we may as well insert the nop right
4928 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4933 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4934 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4937 ? mips_opts.warn_about_macros
4939 offset_expr.X_add_symbol, 0, NULL);
4941 else if (expr1.X_add_number >= -0x8000
4942 && expr1.X_add_number < 0x8000)
4944 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4946 macro_build ((char *) NULL, &icnt, &expr1,
4947 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4948 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4950 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4951 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4953 ? mips_opts.warn_about_macros
4955 offset_expr.X_add_symbol, 0, NULL);
4961 /* If we are going to add in a base register, and the
4962 target register and the base register are the same,
4963 then we are using AT as a temporary register. Since
4964 we want to load the constant into AT, we add our
4965 current AT (from the global offset table) and the
4966 register into the register now, and pretend we were
4967 not using a base register. */
4975 assert (tempreg == AT);
4976 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4978 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4979 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4980 "d,v,t", treg, AT, breg);
4985 /* Set mips_optimize around the lui instruction to avoid
4986 inserting an unnecessary nop after the lw. */
4987 hold_mips_optimize = mips_optimize;
4989 macro_build_lui (NULL, &icnt, &expr1, AT);
4990 mips_optimize = hold_mips_optimize;
4992 macro_build ((char *) NULL, &icnt, &expr1,
4993 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4994 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4995 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4996 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4997 "d,v,t", dreg, dreg, AT);
4999 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5000 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5003 ? mips_opts.warn_about_macros
5005 offset_expr.X_add_symbol, 0, NULL);
5012 /* This is needed because this instruction uses $gp, but
5013 the first instruction on the main stream does not. */
5014 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5017 macro_build (p, &icnt, &offset_expr,
5019 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
5021 if (expr1.X_add_number >= -0x8000
5022 && expr1.X_add_number < 0x8000)
5024 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5026 macro_build (p, &icnt, &expr1,
5027 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5028 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5029 /* FIXME: If add_number is 0, and there was no base
5030 register, the external symbol case ended with a load,
5031 so if the symbol turns out to not be external, and
5032 the next instruction uses tempreg, an unnecessary nop
5033 will be inserted. */
5039 /* We must add in the base register now, as in the
5040 external symbol case. */
5041 assert (tempreg == AT);
5042 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5044 macro_build (p, &icnt, (expressionS *) NULL,
5045 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5046 "d,v,t", treg, AT, breg);
5049 /* We set breg to 0 because we have arranged to add
5050 it in in both cases. */
5054 macro_build_lui (p, &icnt, &expr1, AT);
5056 macro_build (p, &icnt, &expr1,
5057 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5058 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5060 macro_build (p, &icnt, (expressionS *) NULL,
5061 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5062 "d,v,t", tempreg, tempreg, AT);
5066 else if (mips_pic == EMBEDDED_PIC)
5069 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5071 macro_build ((char *) NULL, &icnt, &offset_expr,
5072 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5073 "t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16);
5079 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5080 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5081 "d,v,t", treg, tempreg, breg);
5089 /* The j instruction may not be used in PIC code, since it
5090 requires an absolute address. We convert it to a b
5092 if (mips_pic == NO_PIC)
5093 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5095 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5098 /* The jal instructions must be handled as macros because when
5099 generating PIC code they expand to multi-instruction
5100 sequences. Normally they are simple instructions. */
5105 if (mips_pic == NO_PIC
5106 || mips_pic == EMBEDDED_PIC)
5107 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5109 else if (mips_pic == SVR4_PIC)
5111 if (sreg != PIC_CALL_REG)
5112 as_warn (_("MIPS PIC call to register other than $25"));
5114 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5118 if (mips_cprestore_offset < 0)
5119 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5122 if (! mips_frame_reg_valid)
5124 as_warn (_("No .frame pseudo-op used in PIC code"));
5125 /* Quiet this warning. */
5126 mips_frame_reg_valid = 1;
5128 if (! mips_cprestore_valid)
5130 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5131 /* Quiet this warning. */
5132 mips_cprestore_valid = 1;
5134 expr1.X_add_number = mips_cprestore_offset;
5135 macro_build ((char *) NULL, &icnt, &expr1,
5136 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5137 GP, (int) BFD_RELOC_LO16, mips_frame_reg);
5147 if (mips_pic == NO_PIC)
5148 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5149 else if (mips_pic == SVR4_PIC)
5151 /* If this is a reference to an external symbol, and we are
5152 using a small GOT, we want
5153 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5157 lw $gp,cprestore($sp)
5158 The cprestore value is set using the .cprestore
5159 pseudo-op. If we are using a big GOT, we want
5160 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5162 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5166 lw $gp,cprestore($sp)
5167 If the symbol is not external, we want
5168 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5170 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5173 lw $gp,cprestore($sp) */
5177 macro_build ((char *) NULL, &icnt, &offset_expr,
5178 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5179 "t,o(b)", PIC_CALL_REG,
5180 (int) BFD_RELOC_MIPS_CALL16, GP);
5181 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5183 p = frag_var (rs_machine_dependent, 4, 0,
5184 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5185 offset_expr.X_add_symbol, 0, NULL);
5191 if (reg_needs_delay (GP))
5195 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5196 PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
5197 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5198 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5199 "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
5200 macro_build ((char *) NULL, &icnt, &offset_expr,
5201 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5202 "t,o(b)", PIC_CALL_REG,
5203 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5204 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5206 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5207 RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel,
5209 offset_expr.X_add_symbol, 0, NULL);
5212 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5215 macro_build (p, &icnt, &offset_expr,
5216 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5217 "t,o(b)", PIC_CALL_REG,
5218 (int) BFD_RELOC_MIPS_GOT16, GP);
5220 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5223 macro_build (p, &icnt, &offset_expr,
5224 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5225 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5226 (int) BFD_RELOC_LO16);
5227 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5228 "jalr", "s", PIC_CALL_REG);
5231 if (mips_cprestore_offset < 0)
5232 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5235 if (! mips_frame_reg_valid)
5237 as_warn (_("No .frame pseudo-op used in PIC code"));
5238 /* Quiet this warning. */
5239 mips_frame_reg_valid = 1;
5241 if (! mips_cprestore_valid)
5243 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5244 /* Quiet this warning. */
5245 mips_cprestore_valid = 1;
5247 if (mips_opts.noreorder)
5248 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5250 expr1.X_add_number = mips_cprestore_offset;
5251 macro_build ((char *) NULL, &icnt, &expr1,
5252 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5253 GP, (int) BFD_RELOC_LO16, mips_frame_reg);
5257 else if (mips_pic == EMBEDDED_PIC)
5259 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5260 /* The linker may expand the call to a longer sequence which
5261 uses $at, so we must break rather than return. */
5286 /* Itbl support may require additional care here. */
5291 /* Itbl support may require additional care here. */
5296 /* Itbl support may require additional care here. */
5301 /* Itbl support may require additional care here. */
5313 if (mips_arch == CPU_R4650)
5315 as_bad (_("opcode not supported on this processor"));
5319 /* Itbl support may require additional care here. */
5324 /* Itbl support may require additional care here. */
5329 /* Itbl support may require additional care here. */
5349 if (breg == treg || coproc || lr)
5371 /* Itbl support may require additional care here. */
5376 /* Itbl support may require additional care here. */
5381 /* Itbl support may require additional care here. */
5386 /* Itbl support may require additional care here. */
5402 if (mips_arch == CPU_R4650)
5404 as_bad (_("opcode not supported on this processor"));
5409 /* Itbl support may require additional care here. */
5413 /* Itbl support may require additional care here. */
5418 /* Itbl support may require additional care here. */
5430 /* Itbl support may require additional care here. */
5431 if (mask == M_LWC1_AB
5432 || mask == M_SWC1_AB
5433 || mask == M_LDC1_AB
5434 || mask == M_SDC1_AB
5443 /* For embedded PIC, we allow loads where the offset is calculated
5444 by subtracting a symbol in the current segment from an unknown
5445 symbol, relative to a base register, e.g.:
5446 <op> $treg, <sym>-<localsym>($breg)
5447 This is used by the compiler for switch statements. */
5448 if (mips_pic == EMBEDDED_PIC
5449 && offset_expr.X_op == O_subtract
5450 && (symbol_constant_p (offset_expr.X_op_symbol)
5451 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5452 : (symbol_equated_p (offset_expr.X_op_symbol)
5454 (symbol_get_value_expression (offset_expr.X_op_symbol)
5458 && (offset_expr.X_add_number == 0
5459 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5461 /* For this case, we output the instructions:
5462 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5463 addiu $tempreg,$tempreg,$breg
5464 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5465 If the relocation would fit entirely in 16 bits, it would be
5467 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5468 instead, but that seems quite difficult. */
5469 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5470 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5471 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5472 ((bfd_arch_bits_per_address (stdoutput) == 32
5473 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5474 ? "addu" : "daddu"),
5475 "d,v,t", tempreg, tempreg, breg);
5476 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5477 (int) BFD_RELOC_PCREL_LO16, tempreg);
5483 if (offset_expr.X_op != O_constant
5484 && offset_expr.X_op != O_symbol)
5486 as_bad (_("expression too complex"));
5487 offset_expr.X_op = O_constant;
5490 /* A constant expression in PIC code can be handled just as it
5491 is in non PIC code. */
5492 if (mips_pic == NO_PIC
5493 || offset_expr.X_op == O_constant)
5495 /* If this is a reference to a GP relative symbol, and there
5496 is no base register, we want
5497 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5498 Otherwise, if there is no base register, we want
5499 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5500 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5501 If we have a constant, we need two instructions anyhow,
5502 so we always use the latter form.
5504 If we have a base register, and this is a reference to a
5505 GP relative symbol, we want
5506 addu $tempreg,$breg,$gp
5507 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5509 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5510 addu $tempreg,$tempreg,$breg
5511 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5512 With a constant we always use the latter case.
5514 With 64bit address space and no base register and $at usable,
5516 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5517 lui $at,<sym> (BFD_RELOC_HI16_S)
5518 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5521 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5522 If we have a base register, we want
5523 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5524 lui $at,<sym> (BFD_RELOC_HI16_S)
5525 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5529 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5531 Without $at we can't generate the optimal path for superscalar
5532 processors here since this would require two temporary registers.
5533 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5534 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5536 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5538 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5539 If we have a base register, we want
5540 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5541 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5543 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5545 daddu $tempreg,$tempreg,$breg
5546 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5548 if (HAVE_64BIT_ADDRESSES)
5552 /* We don't do GP optimization for now because RELAX_ENCODE can't
5553 hold the data for such large chunks. */
5557 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5558 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5559 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5560 AT, (int) BFD_RELOC_HI16_S);
5561 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5562 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5564 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5565 "d,v,t", AT, AT, breg);
5566 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5567 "d,w,<", tempreg, tempreg, 0);
5568 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5569 "d,v,t", tempreg, tempreg, AT);
5570 macro_build (p, &icnt, &offset_expr, s,
5571 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5576 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5577 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5578 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5579 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5580 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5581 "d,w,<", tempreg, tempreg, 16);
5582 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5583 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5584 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5585 "d,w,<", tempreg, tempreg, 16);
5587 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5588 "d,v,t", tempreg, tempreg, breg);
5589 macro_build (p, &icnt, &offset_expr, s,
5590 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5598 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5599 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5604 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5605 treg, (int) BFD_RELOC_GPREL16, GP);
5606 p = frag_var (rs_machine_dependent, 8, 0,
5607 RELAX_ENCODE (4, 8, 0, 4, 0,
5608 (mips_opts.warn_about_macros
5610 && mips_opts.noat))),
5611 offset_expr.X_add_symbol, 0, NULL);
5614 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5617 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5618 (int) BFD_RELOC_LO16, tempreg);
5622 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5623 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5628 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5629 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5630 "d,v,t", tempreg, breg, GP);
5631 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5632 treg, (int) BFD_RELOC_GPREL16, tempreg);
5633 p = frag_var (rs_machine_dependent, 12, 0,
5634 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5635 offset_expr.X_add_symbol, 0, NULL);
5637 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5640 macro_build (p, &icnt, (expressionS *) NULL,
5641 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5642 "d,v,t", tempreg, tempreg, breg);
5645 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5646 (int) BFD_RELOC_LO16, tempreg);
5649 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5651 /* If this is a reference to an external symbol, we want
5652 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5654 <op> $treg,0($tempreg)
5656 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5658 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5659 <op> $treg,0($tempreg)
5660 If there is a base register, we add it to $tempreg before
5661 the <op>. If there is a constant, we stick it in the
5662 <op> instruction. We don't handle constants larger than
5663 16 bits, because we have no way to load the upper 16 bits
5664 (actually, we could handle them for the subset of cases
5665 in which we are not using $at). */
5666 assert (offset_expr.X_op == O_symbol);
5667 expr1.X_add_number = offset_expr.X_add_number;
5668 offset_expr.X_add_number = 0;
5669 if (expr1.X_add_number < -0x8000
5670 || expr1.X_add_number >= 0x8000)
5671 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5673 macro_build ((char *) NULL, &icnt, &offset_expr,
5674 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5675 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
5676 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5677 p = frag_var (rs_machine_dependent, 4, 0,
5678 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5679 offset_expr.X_add_symbol, 0, NULL);
5680 macro_build (p, &icnt, &offset_expr,
5681 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5682 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5684 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5685 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5686 "d,v,t", tempreg, tempreg, breg);
5687 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5688 (int) BFD_RELOC_LO16, tempreg);
5690 else if (mips_pic == SVR4_PIC)
5694 /* If this is a reference to an external symbol, we want
5695 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5696 addu $tempreg,$tempreg,$gp
5697 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5698 <op> $treg,0($tempreg)
5700 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5702 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5703 <op> $treg,0($tempreg)
5704 If there is a base register, we add it to $tempreg before
5705 the <op>. If there is a constant, we stick it in the
5706 <op> instruction. We don't handle constants larger than
5707 16 bits, because we have no way to load the upper 16 bits
5708 (actually, we could handle them for the subset of cases
5709 in which we are not using $at). */
5710 assert (offset_expr.X_op == O_symbol);
5711 expr1.X_add_number = offset_expr.X_add_number;
5712 offset_expr.X_add_number = 0;
5713 if (expr1.X_add_number < -0x8000
5714 || expr1.X_add_number >= 0x8000)
5715 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5716 if (reg_needs_delay (GP))
5721 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5722 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5723 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5724 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5725 "d,v,t", tempreg, tempreg, GP);
5726 macro_build ((char *) NULL, &icnt, &offset_expr,
5727 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5728 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5730 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5731 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5732 offset_expr.X_add_symbol, 0, NULL);
5735 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5738 macro_build (p, &icnt, &offset_expr,
5739 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5740 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
5742 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5744 macro_build (p, &icnt, &offset_expr,
5745 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5746 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5748 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5749 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5750 "d,v,t", tempreg, tempreg, breg);
5751 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5752 (int) BFD_RELOC_LO16, tempreg);
5754 else if (mips_pic == EMBEDDED_PIC)
5756 /* If there is no base register, we want
5757 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5758 If there is a base register, we want
5759 addu $tempreg,$breg,$gp
5760 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5762 assert (offset_expr.X_op == O_symbol);
5765 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5766 treg, (int) BFD_RELOC_GPREL16, GP);
5771 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5772 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5773 "d,v,t", tempreg, breg, GP);
5774 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5775 treg, (int) BFD_RELOC_GPREL16, tempreg);
5788 load_register (&icnt, treg, &imm_expr, 0);
5792 load_register (&icnt, treg, &imm_expr, 1);
5796 if (imm_expr.X_op == O_constant)
5798 load_register (&icnt, AT, &imm_expr, 0);
5799 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5800 "mtc1", "t,G", AT, treg);
5805 assert (offset_expr.X_op == O_symbol
5806 && strcmp (segment_name (S_GET_SEGMENT
5807 (offset_expr.X_add_symbol)),
5809 && offset_expr.X_add_number == 0);
5810 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5811 treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
5816 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5817 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5818 order 32 bits of the value and the low order 32 bits are either
5819 zero or in OFFSET_EXPR. */
5820 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5822 if (HAVE_64BIT_GPRS)
5823 load_register (&icnt, treg, &imm_expr, 1);
5828 if (target_big_endian)
5840 load_register (&icnt, hreg, &imm_expr, 0);
5843 if (offset_expr.X_op == O_absent)
5844 move_register (&icnt, lreg, 0);
5847 assert (offset_expr.X_op == O_constant);
5848 load_register (&icnt, lreg, &offset_expr, 0);
5855 /* We know that sym is in the .rdata section. First we get the
5856 upper 16 bits of the address. */
5857 if (mips_pic == NO_PIC)
5859 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5861 else if (mips_pic == SVR4_PIC)
5863 macro_build ((char *) NULL, &icnt, &offset_expr,
5864 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5865 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
5867 else if (mips_pic == EMBEDDED_PIC)
5869 /* For embedded PIC we pick up the entire address off $gp in
5870 a single instruction. */
5871 macro_build ((char *) NULL, &icnt, &offset_expr,
5872 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5873 "t,r,j", AT, GP, (int) BFD_RELOC_GPREL16);
5874 offset_expr.X_op = O_constant;
5875 offset_expr.X_add_number = 0;
5880 /* Now we load the register(s). */
5881 if (HAVE_64BIT_GPRS)
5882 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5883 treg, (int) BFD_RELOC_LO16, AT);
5886 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5887 treg, (int) BFD_RELOC_LO16, AT);
5890 /* FIXME: How in the world do we deal with the possible
5892 offset_expr.X_add_number += 4;
5893 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5894 treg + 1, (int) BFD_RELOC_LO16, AT);
5898 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5899 does not become a variant frag. */
5900 frag_wane (frag_now);
5906 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5907 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5908 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5909 the value and the low order 32 bits are either zero or in
5911 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5913 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5914 if (HAVE_64BIT_FPRS)
5916 assert (HAVE_64BIT_GPRS);
5917 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5918 "dmtc1", "t,S", AT, treg);
5922 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5923 "mtc1", "t,G", AT, treg + 1);
5924 if (offset_expr.X_op == O_absent)
5925 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5926 "mtc1", "t,G", 0, treg);
5929 assert (offset_expr.X_op == O_constant);
5930 load_register (&icnt, AT, &offset_expr, 0);
5931 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5932 "mtc1", "t,G", AT, treg);
5938 assert (offset_expr.X_op == O_symbol
5939 && offset_expr.X_add_number == 0);
5940 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5941 if (strcmp (s, ".lit8") == 0)
5943 if (mips_opts.isa != ISA_MIPS1)
5945 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5946 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
5950 r = BFD_RELOC_MIPS_LITERAL;
5955 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
5956 if (mips_pic == SVR4_PIC)
5957 macro_build ((char *) NULL, &icnt, &offset_expr,
5958 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5959 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
5962 /* FIXME: This won't work for a 64 bit address. */
5963 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5966 if (mips_opts.isa != ISA_MIPS1)
5968 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5969 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
5971 /* To avoid confusion in tc_gen_reloc, we must ensure
5972 that this does not become a variant frag. */
5973 frag_wane (frag_now);
5984 if (mips_arch == CPU_R4650)
5986 as_bad (_("opcode not supported on this processor"));
5989 /* Even on a big endian machine $fn comes before $fn+1. We have
5990 to adjust when loading from memory. */
5993 assert (mips_opts.isa == ISA_MIPS1);
5994 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5995 target_big_endian ? treg + 1 : treg,
5997 /* FIXME: A possible overflow which I don't know how to deal
5999 offset_expr.X_add_number += 4;
6000 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6001 target_big_endian ? treg : treg + 1,
6004 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6005 does not become a variant frag. */
6006 frag_wane (frag_now);
6015 * The MIPS assembler seems to check for X_add_number not
6016 * being double aligned and generating:
6019 * addiu at,at,%lo(foo+1)
6022 * But, the resulting address is the same after relocation so why
6023 * generate the extra instruction?
6025 if (mips_arch == CPU_R4650)
6027 as_bad (_("opcode not supported on this processor"));
6030 /* Itbl support may require additional care here. */
6032 if (mips_opts.isa != ISA_MIPS1)
6043 if (mips_arch == CPU_R4650)
6045 as_bad (_("opcode not supported on this processor"));
6049 if (mips_opts.isa != ISA_MIPS1)
6057 /* Itbl support may require additional care here. */
6062 if (HAVE_64BIT_GPRS)
6073 if (HAVE_64BIT_GPRS)
6083 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6084 loads for the case of doing a pair of loads to simulate an 'ld'.
6085 This is not currently done by the compiler, and assembly coders
6086 writing embedded-pic code can cope. */
6088 if (offset_expr.X_op != O_symbol
6089 && offset_expr.X_op != O_constant)
6091 as_bad (_("expression too complex"));
6092 offset_expr.X_op = O_constant;
6095 /* Even on a big endian machine $fn comes before $fn+1. We have
6096 to adjust when loading from memory. We set coproc if we must
6097 load $fn+1 first. */
6098 /* Itbl support may require additional care here. */
6099 if (! target_big_endian)
6102 if (mips_pic == NO_PIC
6103 || offset_expr.X_op == O_constant)
6105 /* If this is a reference to a GP relative symbol, we want
6106 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6107 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6108 If we have a base register, we use this
6110 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6111 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6112 If this is not a GP relative symbol, we want
6113 lui $at,<sym> (BFD_RELOC_HI16_S)
6114 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6115 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6116 If there is a base register, we add it to $at after the
6117 lui instruction. If there is a constant, we always use
6119 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6120 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6139 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6140 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6141 "d,v,t", AT, breg, GP);
6147 /* Itbl support may require additional care here. */
6148 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6149 coproc ? treg + 1 : treg,
6150 (int) BFD_RELOC_GPREL16, tempreg);
6151 offset_expr.X_add_number += 4;
6153 /* Set mips_optimize to 2 to avoid inserting an
6155 hold_mips_optimize = mips_optimize;
6157 /* Itbl support may require additional care here. */
6158 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6159 coproc ? treg : treg + 1,
6160 (int) BFD_RELOC_GPREL16, tempreg);
6161 mips_optimize = hold_mips_optimize;
6163 p = frag_var (rs_machine_dependent, 12 + off, 0,
6164 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6165 used_at && mips_opts.noat),
6166 offset_expr.X_add_symbol, 0, NULL);
6168 /* We just generated two relocs. When tc_gen_reloc
6169 handles this case, it will skip the first reloc and
6170 handle the second. The second reloc already has an
6171 extra addend of 4, which we added above. We must
6172 subtract it out, and then subtract another 4 to make
6173 the first reloc come out right. The second reloc
6174 will come out right because we are going to add 4 to
6175 offset_expr when we build its instruction below.
6177 If we have a symbol, then we don't want to include
6178 the offset, because it will wind up being included
6179 when we generate the reloc. */
6181 if (offset_expr.X_op == O_constant)
6182 offset_expr.X_add_number -= 8;
6185 offset_expr.X_add_number = -4;
6186 offset_expr.X_op = O_constant;
6189 macro_build_lui (p, &icnt, &offset_expr, AT);
6194 macro_build (p, &icnt, (expressionS *) NULL,
6195 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6196 "d,v,t", AT, breg, AT);
6200 /* Itbl support may require additional care here. */
6201 macro_build (p, &icnt, &offset_expr, s, fmt,
6202 coproc ? treg + 1 : treg,
6203 (int) BFD_RELOC_LO16, AT);
6206 /* FIXME: How do we handle overflow here? */
6207 offset_expr.X_add_number += 4;
6208 /* Itbl support may require additional care here. */
6209 macro_build (p, &icnt, &offset_expr, s, fmt,
6210 coproc ? treg : treg + 1,
6211 (int) BFD_RELOC_LO16, AT);
6213 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6217 /* If this is a reference to an external symbol, we want
6218 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6223 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6225 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6226 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6227 If there is a base register we add it to $at before the
6228 lwc1 instructions. If there is a constant we include it
6229 in the lwc1 instructions. */
6231 expr1.X_add_number = offset_expr.X_add_number;
6232 offset_expr.X_add_number = 0;
6233 if (expr1.X_add_number < -0x8000
6234 || expr1.X_add_number >= 0x8000 - 4)
6235 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6240 frag_grow (24 + off);
6241 macro_build ((char *) NULL, &icnt, &offset_expr,
6242 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6243 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
6244 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6246 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6247 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6248 "d,v,t", AT, breg, AT);
6249 /* Itbl support may require additional care here. */
6250 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6251 coproc ? treg + 1 : treg,
6252 (int) BFD_RELOC_LO16, AT);
6253 expr1.X_add_number += 4;
6255 /* Set mips_optimize to 2 to avoid inserting an undesired
6257 hold_mips_optimize = mips_optimize;
6259 /* Itbl support may require additional care here. */
6260 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6261 coproc ? treg : treg + 1,
6262 (int) BFD_RELOC_LO16, AT);
6263 mips_optimize = hold_mips_optimize;
6265 (void) frag_var (rs_machine_dependent, 0, 0,
6266 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6267 offset_expr.X_add_symbol, 0, NULL);
6269 else if (mips_pic == SVR4_PIC)
6273 /* If this is a reference to an external symbol, we want
6274 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6276 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6281 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6283 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6284 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6285 If there is a base register we add it to $at before the
6286 lwc1 instructions. If there is a constant we include it
6287 in the lwc1 instructions. */
6289 expr1.X_add_number = offset_expr.X_add_number;
6290 offset_expr.X_add_number = 0;
6291 if (expr1.X_add_number < -0x8000
6292 || expr1.X_add_number >= 0x8000 - 4)
6293 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6294 if (reg_needs_delay (GP))
6303 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6304 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6305 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6306 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6307 "d,v,t", AT, AT, GP);
6308 macro_build ((char *) NULL, &icnt, &offset_expr,
6309 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6310 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6311 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6313 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6314 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6315 "d,v,t", AT, breg, AT);
6316 /* Itbl support may require additional care here. */
6317 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6318 coproc ? treg + 1 : treg,
6319 (int) BFD_RELOC_LO16, AT);
6320 expr1.X_add_number += 4;
6322 /* Set mips_optimize to 2 to avoid inserting an undesired
6324 hold_mips_optimize = mips_optimize;
6326 /* Itbl support may require additional care here. */
6327 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6328 coproc ? treg : treg + 1,
6329 (int) BFD_RELOC_LO16, AT);
6330 mips_optimize = hold_mips_optimize;
6331 expr1.X_add_number -= 4;
6333 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6334 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6335 8 + gpdel + off, 1, 0),
6336 offset_expr.X_add_symbol, 0, NULL);
6339 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6342 macro_build (p, &icnt, &offset_expr,
6343 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6344 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
6346 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6350 macro_build (p, &icnt, (expressionS *) NULL,
6351 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6352 "d,v,t", AT, breg, AT);
6355 /* Itbl support may require additional care here. */
6356 macro_build (p, &icnt, &expr1, s, fmt,
6357 coproc ? treg + 1 : treg,
6358 (int) BFD_RELOC_LO16, AT);
6360 expr1.X_add_number += 4;
6362 /* Set mips_optimize to 2 to avoid inserting an undesired
6364 hold_mips_optimize = mips_optimize;
6366 /* Itbl support may require additional care here. */
6367 macro_build (p, &icnt, &expr1, s, fmt,
6368 coproc ? treg : treg + 1,
6369 (int) BFD_RELOC_LO16, AT);
6370 mips_optimize = hold_mips_optimize;
6372 else if (mips_pic == EMBEDDED_PIC)
6374 /* If there is no base register, we use
6375 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6376 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6377 If we have a base register, we use
6379 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6380 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6389 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6390 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6391 "d,v,t", AT, breg, GP);
6396 /* Itbl support may require additional care here. */
6397 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6398 coproc ? treg + 1 : treg,
6399 (int) BFD_RELOC_GPREL16, tempreg);
6400 offset_expr.X_add_number += 4;
6401 /* Itbl support may require additional care here. */
6402 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6403 coproc ? treg : treg + 1,
6404 (int) BFD_RELOC_GPREL16, tempreg);
6420 assert (HAVE_32BIT_ADDRESSES);
6421 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6422 (int) BFD_RELOC_LO16, breg);
6423 offset_expr.X_add_number += 4;
6424 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6425 (int) BFD_RELOC_LO16, breg);
6428 /* New code added to support COPZ instructions.
6429 This code builds table entries out of the macros in mip_opcodes.
6430 R4000 uses interlocks to handle coproc delays.
6431 Other chips (like the R3000) require nops to be inserted for delays.
6433 FIXME: Currently, we require that the user handle delays.
6434 In order to fill delay slots for non-interlocked chips,
6435 we must have a way to specify delays based on the coprocessor.
6436 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6437 What are the side-effects of the cop instruction?
6438 What cache support might we have and what are its effects?
6439 Both coprocessor & memory require delays. how long???
6440 What registers are read/set/modified?
6442 If an itbl is provided to interpret cop instructions,
6443 this knowledge can be encoded in the itbl spec. */
6457 /* For now we just do C (same as Cz). The parameter will be
6458 stored in insn_opcode by mips_ip. */
6459 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6464 move_register (&icnt, dreg, sreg);
6467 #ifdef LOSING_COMPILER
6469 /* Try and see if this is a new itbl instruction.
6470 This code builds table entries out of the macros in mip_opcodes.
6471 FIXME: For now we just assemble the expression and pass it's
6472 value along as a 32-bit immediate.
6473 We may want to have the assembler assemble this value,
6474 so that we gain the assembler's knowledge of delay slots,
6476 Would it be more efficient to use mask (id) here? */
6477 if (itbl_have_entries
6478 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6480 s = ip->insn_mo->name;
6482 coproc = ITBL_DECODE_PNUM (immed_expr);;
6483 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6490 as_warn (_("Macro used $at after \".set noat\""));
6495 struct mips_cl_insn *ip;
6497 register int treg, sreg, dreg, breg;
6513 bfd_reloc_code_real_type r;
6516 treg = (ip->insn_opcode >> 16) & 0x1f;
6517 dreg = (ip->insn_opcode >> 11) & 0x1f;
6518 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6519 mask = ip->insn_mo->mask;
6521 expr1.X_op = O_constant;
6522 expr1.X_op_symbol = NULL;
6523 expr1.X_add_symbol = NULL;
6524 expr1.X_add_number = 1;
6528 #endif /* LOSING_COMPILER */
6533 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6534 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6535 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6542 /* The MIPS assembler some times generates shifts and adds. I'm
6543 not trying to be that fancy. GCC should do this for us
6545 load_register (&icnt, AT, &imm_expr, dbl);
6546 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6547 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6548 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6562 mips_emit_delays (true);
6563 ++mips_opts.noreorder;
6564 mips_any_noreorder = 1;
6566 load_register (&icnt, AT, &imm_expr, dbl);
6567 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6568 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6569 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6571 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6572 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, 31);
6573 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6576 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6580 expr1.X_add_number = 8;
6581 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6583 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6585 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6588 --mips_opts.noreorder;
6589 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6602 mips_emit_delays (true);
6603 ++mips_opts.noreorder;
6604 mips_any_noreorder = 1;
6606 load_register (&icnt, AT, &imm_expr, dbl);
6607 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6608 dbl ? "dmultu" : "multu",
6609 "s,t", sreg, imm ? AT : treg);
6610 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6612 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6615 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6619 expr1.X_add_number = 8;
6620 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6621 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6623 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6626 --mips_opts.noreorder;
6630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6631 "d,v,t", AT, 0, treg);
6632 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6633 "d,t,s", AT, sreg, AT);
6634 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6635 "d,t,s", dreg, sreg, treg);
6636 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6637 "d,v,t", dreg, dreg, AT);
6641 if (imm_expr.X_op != O_constant)
6642 as_bad (_("rotate count too large"));
6643 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
6644 AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
6645 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
6646 dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
6647 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
6652 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6653 "d,v,t", AT, 0, treg);
6654 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6655 "d,t,s", AT, sreg, AT);
6656 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6657 "d,t,s", dreg, sreg, treg);
6658 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6659 "d,v,t", dreg, dreg, AT);
6663 if (imm_expr.X_op != O_constant)
6664 as_bad (_("rotate count too large"));
6665 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
6666 AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
6667 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
6668 dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
6669 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
6674 if (mips_arch == CPU_R4650)
6676 as_bad (_("opcode not supported on this processor"));
6679 assert (mips_opts.isa == ISA_MIPS1);
6680 /* Even on a big endian machine $fn comes before $fn+1. We have
6681 to adjust when storing to memory. */
6682 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6683 target_big_endian ? treg + 1 : treg,
6684 (int) BFD_RELOC_LO16, breg);
6685 offset_expr.X_add_number += 4;
6686 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6687 target_big_endian ? treg : treg + 1,
6688 (int) BFD_RELOC_LO16, breg);
6693 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6694 treg, (int) BFD_RELOC_LO16);
6696 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6697 sreg, (int) BFD_RELOC_LO16);
6700 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6701 "d,v,t", dreg, sreg, treg);
6702 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6703 dreg, (int) BFD_RELOC_LO16);
6708 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6710 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6711 sreg, (int) BFD_RELOC_LO16);
6716 as_warn (_("Instruction %s: result is always false"),
6718 move_register (&icnt, dreg, 0);
6721 if (imm_expr.X_op == O_constant
6722 && imm_expr.X_add_number >= 0
6723 && imm_expr.X_add_number < 0x10000)
6725 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6726 sreg, (int) BFD_RELOC_LO16);
6729 else if (imm_expr.X_op == O_constant
6730 && imm_expr.X_add_number > -0x8000
6731 && imm_expr.X_add_number < 0)
6733 imm_expr.X_add_number = -imm_expr.X_add_number;
6734 macro_build ((char *) NULL, &icnt, &imm_expr,
6735 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6736 "t,r,j", dreg, sreg,
6737 (int) BFD_RELOC_LO16);
6742 load_register (&icnt, AT, &imm_expr, 0);
6743 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6744 "d,v,t", dreg, sreg, AT);
6747 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6748 (int) BFD_RELOC_LO16);
6753 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6759 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6761 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6762 (int) BFD_RELOC_LO16);
6765 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6767 if (imm_expr.X_op == O_constant
6768 && imm_expr.X_add_number >= -0x8000
6769 && imm_expr.X_add_number < 0x8000)
6771 macro_build ((char *) NULL, &icnt, &imm_expr,
6772 mask == M_SGE_I ? "slti" : "sltiu",
6773 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6778 load_register (&icnt, AT, &imm_expr, 0);
6779 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6780 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6784 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6785 (int) BFD_RELOC_LO16);
6790 case M_SGT: /* sreg > treg <==> treg < sreg */
6796 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6800 case M_SGT_I: /* sreg > I <==> I < sreg */
6806 load_register (&icnt, AT, &imm_expr, 0);
6807 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6811 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6817 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6819 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6820 (int) BFD_RELOC_LO16);
6823 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6829 load_register (&icnt, AT, &imm_expr, 0);
6830 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6832 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6833 (int) BFD_RELOC_LO16);
6837 if (imm_expr.X_op == O_constant
6838 && imm_expr.X_add_number >= -0x8000
6839 && imm_expr.X_add_number < 0x8000)
6841 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6842 dreg, sreg, (int) BFD_RELOC_LO16);
6845 load_register (&icnt, AT, &imm_expr, 0);
6846 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
6851 if (imm_expr.X_op == O_constant
6852 && imm_expr.X_add_number >= -0x8000
6853 && imm_expr.X_add_number < 0x8000)
6855 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6856 dreg, sreg, (int) BFD_RELOC_LO16);
6859 load_register (&icnt, AT, &imm_expr, 0);
6860 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6861 "d,v,t", dreg, sreg, AT);
6866 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6867 "d,v,t", dreg, 0, treg);
6869 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6870 "d,v,t", dreg, 0, sreg);
6873 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6874 "d,v,t", dreg, sreg, treg);
6875 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6876 "d,v,t", dreg, 0, dreg);
6881 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6883 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6884 "d,v,t", dreg, 0, sreg);
6889 as_warn (_("Instruction %s: result is always true"),
6891 macro_build ((char *) NULL, &icnt, &expr1,
6892 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6893 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
6896 if (imm_expr.X_op == O_constant
6897 && imm_expr.X_add_number >= 0
6898 && imm_expr.X_add_number < 0x10000)
6900 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
6901 dreg, sreg, (int) BFD_RELOC_LO16);
6904 else if (imm_expr.X_op == O_constant
6905 && imm_expr.X_add_number > -0x8000
6906 && imm_expr.X_add_number < 0)
6908 imm_expr.X_add_number = -imm_expr.X_add_number;
6909 macro_build ((char *) NULL, &icnt, &imm_expr,
6910 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6911 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6916 load_register (&icnt, AT, &imm_expr, 0);
6917 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6918 "d,v,t", dreg, sreg, AT);
6921 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6922 "d,v,t", dreg, 0, dreg);
6930 if (imm_expr.X_op == O_constant
6931 && imm_expr.X_add_number > -0x8000
6932 && imm_expr.X_add_number <= 0x8000)
6934 imm_expr.X_add_number = -imm_expr.X_add_number;
6935 macro_build ((char *) NULL, &icnt, &imm_expr,
6936 dbl ? "daddi" : "addi",
6937 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6940 load_register (&icnt, AT, &imm_expr, dbl);
6941 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6942 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
6948 if (imm_expr.X_op == O_constant
6949 && imm_expr.X_add_number > -0x8000
6950 && imm_expr.X_add_number <= 0x8000)
6952 imm_expr.X_add_number = -imm_expr.X_add_number;
6953 macro_build ((char *) NULL, &icnt, &imm_expr,
6954 dbl ? "daddiu" : "addiu",
6955 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6958 load_register (&icnt, AT, &imm_expr, dbl);
6959 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6960 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
6981 load_register (&icnt, AT, &imm_expr, 0);
6982 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
6988 assert (mips_opts.isa == ISA_MIPS1);
6989 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
6990 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
6993 * Is the double cfc1 instruction a bug in the mips assembler;
6994 * or is there a reason for it?
6996 mips_emit_delays (true);
6997 ++mips_opts.noreorder;
6998 mips_any_noreorder = 1;
6999 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7001 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7003 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7004 expr1.X_add_number = 3;
7005 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7006 (int) BFD_RELOC_LO16);
7007 expr1.X_add_number = 2;
7008 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7009 (int) BFD_RELOC_LO16);
7010 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7012 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7013 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7014 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7015 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7017 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7018 --mips_opts.noreorder;
7027 if (offset_expr.X_add_number >= 0x7fff)
7028 as_bad (_("operand overflow"));
7029 /* avoid load delay */
7030 if (! target_big_endian)
7031 offset_expr.X_add_number += 1;
7032 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7033 (int) BFD_RELOC_LO16, breg);
7034 if (! target_big_endian)
7035 offset_expr.X_add_number -= 1;
7037 offset_expr.X_add_number += 1;
7038 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7039 (int) BFD_RELOC_LO16, breg);
7040 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7042 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7056 if (offset_expr.X_add_number >= 0x8000 - off)
7057 as_bad (_("operand overflow"));
7058 if (! target_big_endian)
7059 offset_expr.X_add_number += off;
7060 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7061 (int) BFD_RELOC_LO16, breg);
7062 if (! target_big_endian)
7063 offset_expr.X_add_number -= off;
7065 offset_expr.X_add_number += off;
7066 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7067 (int) BFD_RELOC_LO16, breg);
7081 load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at);
7083 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7084 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7085 "d,v,t", AT, AT, breg);
7086 if (! target_big_endian)
7087 expr1.X_add_number = off;
7089 expr1.X_add_number = 0;
7090 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7091 (int) BFD_RELOC_LO16, AT);
7092 if (! target_big_endian)
7093 expr1.X_add_number = 0;
7095 expr1.X_add_number = off;
7096 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7097 (int) BFD_RELOC_LO16, AT);
7103 load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at);
7105 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7106 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7107 "d,v,t", AT, AT, breg);
7108 if (target_big_endian)
7109 expr1.X_add_number = 0;
7110 macro_build ((char *) NULL, &icnt, &expr1,
7111 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7112 (int) BFD_RELOC_LO16, AT);
7113 if (target_big_endian)
7114 expr1.X_add_number = 1;
7116 expr1.X_add_number = 0;
7117 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7118 (int) BFD_RELOC_LO16, AT);
7119 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7121 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7126 if (offset_expr.X_add_number >= 0x7fff)
7127 as_bad (_("operand overflow"));
7128 if (target_big_endian)
7129 offset_expr.X_add_number += 1;
7130 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7131 (int) BFD_RELOC_LO16, breg);
7132 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7134 if (target_big_endian)
7135 offset_expr.X_add_number -= 1;
7137 offset_expr.X_add_number += 1;
7138 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7139 (int) BFD_RELOC_LO16, breg);
7152 if (offset_expr.X_add_number >= 0x8000 - off)
7153 as_bad (_("operand overflow"));
7154 if (! target_big_endian)
7155 offset_expr.X_add_number += off;
7156 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7157 (int) BFD_RELOC_LO16, breg);
7158 if (! target_big_endian)
7159 offset_expr.X_add_number -= off;
7161 offset_expr.X_add_number += off;
7162 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7163 (int) BFD_RELOC_LO16, breg);
7177 load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at);
7179 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7180 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7181 "d,v,t", AT, AT, breg);
7182 if (! target_big_endian)
7183 expr1.X_add_number = off;
7185 expr1.X_add_number = 0;
7186 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7187 (int) BFD_RELOC_LO16, AT);
7188 if (! target_big_endian)
7189 expr1.X_add_number = 0;
7191 expr1.X_add_number = off;
7192 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7193 (int) BFD_RELOC_LO16, AT);
7198 load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at);
7200 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7201 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7202 "d,v,t", AT, AT, breg);
7203 if (! target_big_endian)
7204 expr1.X_add_number = 0;
7205 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7206 (int) BFD_RELOC_LO16, AT);
7207 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7209 if (! target_big_endian)
7210 expr1.X_add_number = 1;
7212 expr1.X_add_number = 0;
7213 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7214 (int) BFD_RELOC_LO16, AT);
7215 if (! target_big_endian)
7216 expr1.X_add_number = 0;
7218 expr1.X_add_number = 1;
7219 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7220 (int) BFD_RELOC_LO16, AT);
7221 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7223 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7228 /* FIXME: Check if this is one of the itbl macros, since they
7229 are added dynamically. */
7230 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7234 as_warn (_("Macro used $at after \".set noat\""));
7237 /* Implement macros in mips16 mode. */
7241 struct mips_cl_insn *ip;
7244 int xreg, yreg, zreg, tmp;
7248 const char *s, *s2, *s3;
7250 mask = ip->insn_mo->mask;
7252 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7253 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7254 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7258 expr1.X_op = O_constant;
7259 expr1.X_op_symbol = NULL;
7260 expr1.X_add_symbol = NULL;
7261 expr1.X_add_number = 1;
7280 mips_emit_delays (true);
7281 ++mips_opts.noreorder;
7282 mips_any_noreorder = 1;
7283 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7284 dbl ? "ddiv" : "div",
7285 "0,x,y", xreg, yreg);
7286 expr1.X_add_number = 2;
7287 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7288 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7291 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7292 since that causes an overflow. We should do that as well,
7293 but I don't see how to do the comparisons without a temporary
7295 --mips_opts.noreorder;
7296 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7315 mips_emit_delays (true);
7316 ++mips_opts.noreorder;
7317 mips_any_noreorder = 1;
7318 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7320 expr1.X_add_number = 2;
7321 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7322 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7324 --mips_opts.noreorder;
7325 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7331 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7332 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7333 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7342 if (imm_expr.X_op != O_constant)
7343 as_bad (_("Unsupported large constant"));
7344 imm_expr.X_add_number = -imm_expr.X_add_number;
7345 macro_build ((char *) NULL, &icnt, &imm_expr,
7346 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7350 if (imm_expr.X_op != O_constant)
7351 as_bad (_("Unsupported large constant"));
7352 imm_expr.X_add_number = -imm_expr.X_add_number;
7353 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7358 if (imm_expr.X_op != O_constant)
7359 as_bad (_("Unsupported large constant"));
7360 imm_expr.X_add_number = -imm_expr.X_add_number;
7361 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7384 goto do_reverse_branch;
7388 goto do_reverse_branch;
7400 goto do_reverse_branch;
7411 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7413 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7440 goto do_addone_branch_i;
7445 goto do_addone_branch_i;
7460 goto do_addone_branch_i;
7467 if (imm_expr.X_op != O_constant)
7468 as_bad (_("Unsupported large constant"));
7469 ++imm_expr.X_add_number;
7472 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7473 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7477 expr1.X_add_number = 0;
7478 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7480 move_register (&icnt, xreg, yreg);
7481 expr1.X_add_number = 2;
7482 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7483 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7484 "neg", "x,w", xreg, xreg);
7488 /* For consistency checking, verify that all bits are specified either
7489 by the match/mask part of the instruction definition, or by the
7492 validate_mips_insn (opc)
7493 const struct mips_opcode *opc;
7495 const char *p = opc->args;
7497 unsigned long used_bits = opc->mask;
7499 if ((used_bits & opc->match) != opc->match)
7501 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7502 opc->name, opc->args);
7505 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7512 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7513 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7515 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7516 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7517 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7518 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7520 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7521 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7523 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7525 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7526 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7527 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7528 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7529 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7530 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7531 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7532 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7533 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7534 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7535 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7537 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7538 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7539 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7540 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7542 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7543 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7544 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7545 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7546 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7547 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7548 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7549 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7550 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7553 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7554 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7555 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7557 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7558 c, opc->name, opc->args);
7562 if (used_bits != 0xffffffff)
7564 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7565 ~used_bits & 0xffffffff, opc->name, opc->args);
7571 /* This routine assembles an instruction into its binary format. As a
7572 side effect, it sets one of the global variables imm_reloc or
7573 offset_reloc to the type of relocation to do if one of the operands
7574 is an address expression. */
7579 struct mips_cl_insn *ip;
7584 struct mips_opcode *insn;
7587 unsigned int lastregno = 0;
7590 int full_opcode_match = 1;
7594 /* If the instruction contains a '.', we first try to match an instruction
7595 including the '.'. Then we try again without the '.'. */
7597 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7600 /* If we stopped on whitespace, then replace the whitespace with null for
7601 the call to hash_find. Save the character we replaced just in case we
7602 have to re-parse the instruction. */
7609 insn = (struct mips_opcode *) hash_find (op_hash, str);
7611 /* If we didn't find the instruction in the opcode table, try again, but
7612 this time with just the instruction up to, but not including the
7616 /* Restore the character we overwrite above (if any). */
7620 /* Scan up to the first '.' or whitespace. */
7622 *s != '\0' && *s != '.' && !ISSPACE (*s);
7626 /* If we did not find a '.', then we can quit now. */
7629 insn_error = "unrecognized opcode";
7633 /* Lookup the instruction in the hash table. */
7635 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7637 insn_error = "unrecognized opcode";
7641 full_opcode_match = 0;
7649 assert (strcmp (insn->name, str) == 0);
7651 if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch))
7656 if (insn->pinfo != INSN_MACRO)
7658 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7664 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7665 && strcmp (insn->name, insn[1].name) == 0)
7674 static char buf[100];
7676 _("opcode not supported on this processor: %s (%s)"),
7677 mips_cpu_to_str (mips_arch),
7678 mips_isa_to_str (mips_opts.isa));
7689 ip->insn_opcode = insn->match;
7691 for (args = insn->args;; ++args)
7693 s += strspn (s, " \t");
7696 case '\0': /* end of args */
7709 ip->insn_opcode |= lastregno << OP_SH_RS;
7713 ip->insn_opcode |= lastregno << OP_SH_RT;
7717 ip->insn_opcode |= lastregno << OP_SH_FT;
7721 ip->insn_opcode |= lastregno << OP_SH_FS;
7727 /* Handle optional base register.
7728 Either the base register is omitted or
7729 we must have a left paren. */
7730 /* This is dependent on the next operand specifier
7731 is a base register specification. */
7732 assert (args[1] == 'b' || args[1] == '5'
7733 || args[1] == '-' || args[1] == '4');
7737 case ')': /* these must match exactly */
7742 case '<': /* must be at least one digit */
7744 * According to the manual, if the shift amount is greater
7745 * than 31 or less than 0, then the shift amount should be
7746 * mod 32. In reality the mips assembler issues an error.
7747 * We issue a warning and mask out all but the low 5 bits.
7749 my_getExpression (&imm_expr, s);
7750 check_absolute_expr (ip, &imm_expr);
7751 if ((unsigned long) imm_expr.X_add_number > 31)
7753 as_warn (_("Improper shift amount (%ld)"),
7754 (long) imm_expr.X_add_number);
7755 imm_expr.X_add_number &= OP_MASK_SHAMT;
7757 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7758 imm_expr.X_op = O_absent;
7762 case '>': /* shift amount minus 32 */
7763 my_getExpression (&imm_expr, s);
7764 check_absolute_expr (ip, &imm_expr);
7765 if ((unsigned long) imm_expr.X_add_number < 32
7766 || (unsigned long) imm_expr.X_add_number > 63)
7768 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7769 imm_expr.X_op = O_absent;
7773 case 'k': /* cache code */
7774 case 'h': /* prefx code */
7775 my_getExpression (&imm_expr, s);
7776 check_absolute_expr (ip, &imm_expr);
7777 if ((unsigned long) imm_expr.X_add_number > 31)
7779 as_warn (_("Invalid value for `%s' (%lu)"),
7781 (unsigned long) imm_expr.X_add_number);
7782 imm_expr.X_add_number &= 0x1f;
7785 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7787 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7788 imm_expr.X_op = O_absent;
7792 case 'c': /* break code */
7793 my_getExpression (&imm_expr, s);
7794 check_absolute_expr (ip, &imm_expr);
7795 if ((unsigned) imm_expr.X_add_number > 1023)
7797 as_warn (_("Illegal break code (%ld)"),
7798 (long) imm_expr.X_add_number);
7799 imm_expr.X_add_number &= OP_MASK_CODE;
7801 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7802 imm_expr.X_op = O_absent;
7806 case 'q': /* lower break code */
7807 my_getExpression (&imm_expr, s);
7808 check_absolute_expr (ip, &imm_expr);
7809 if ((unsigned) imm_expr.X_add_number > 1023)
7811 as_warn (_("Illegal lower break code (%ld)"),
7812 (long) imm_expr.X_add_number);
7813 imm_expr.X_add_number &= OP_MASK_CODE2;
7815 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7816 imm_expr.X_op = O_absent;
7820 case 'B': /* 20-bit syscall/break code. */
7821 my_getExpression (&imm_expr, s);
7822 check_absolute_expr (ip, &imm_expr);
7823 if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20)
7824 as_warn (_("Illegal 20-bit code (%ld)"),
7825 (long) imm_expr.X_add_number);
7826 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7827 imm_expr.X_op = O_absent;
7831 case 'C': /* Coprocessor code */
7832 my_getExpression (&imm_expr, s);
7833 check_absolute_expr (ip, &imm_expr);
7834 if ((unsigned long) imm_expr.X_add_number >= (1<<25))
7836 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7837 (long) imm_expr.X_add_number);
7838 imm_expr.X_add_number &= ((1<<25) - 1);
7840 ip->insn_opcode |= imm_expr.X_add_number;
7841 imm_expr.X_op = O_absent;
7845 case 'J': /* 19-bit wait code. */
7846 my_getExpression (&imm_expr, s);
7847 check_absolute_expr (ip, &imm_expr);
7848 if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19)
7849 as_warn (_("Illegal 19-bit code (%ld)"),
7850 (long) imm_expr.X_add_number);
7851 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7852 imm_expr.X_op = O_absent;
7856 case 'P': /* Performance register */
7857 my_getExpression (&imm_expr, s);
7858 check_absolute_expr (ip, &imm_expr);
7859 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7861 as_warn (_("Invalid performance register (%ld)"),
7862 (long) imm_expr.X_add_number);
7863 imm_expr.X_add_number &= OP_MASK_PERFREG;
7865 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7866 imm_expr.X_op = O_absent;
7870 case 'b': /* base register */
7871 case 'd': /* destination register */
7872 case 's': /* source register */
7873 case 't': /* target register */
7874 case 'r': /* both target and source */
7875 case 'v': /* both dest and source */
7876 case 'w': /* both dest and target */
7877 case 'E': /* coprocessor target register */
7878 case 'G': /* coprocessor destination register */
7879 case 'x': /* ignore register name */
7880 case 'z': /* must be zero register */
7881 case 'U': /* destination register (clo/clz). */
7896 while (ISDIGIT (*s));
7898 as_bad (_("Invalid register number (%d)"), regno);
7900 else if (*args == 'E' || *args == 'G')
7904 if (s[1] == 'f' && s[2] == 'p')
7909 else if (s[1] == 's' && s[2] == 'p')
7914 else if (s[1] == 'g' && s[2] == 'p')
7919 else if (s[1] == 'a' && s[2] == 't')
7924 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
7929 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
7934 else if (itbl_have_entries)
7939 p = s + 1; /* advance past '$' */
7940 n = itbl_get_field (&p); /* n is name */
7942 /* See if this is a register defined in an
7944 if (itbl_get_reg_val (n, &r))
7946 /* Get_field advances to the start of
7947 the next field, so we need to back
7948 rack to the end of the last field. */
7952 s = strchr (s, '\0');
7965 as_warn (_("Used $at without \".set noat\""));
7971 if (c == 'r' || c == 'v' || c == 'w')
7978 /* 'z' only matches $0. */
7979 if (c == 'z' && regno != 0)
7982 /* Now that we have assembled one operand, we use the args string
7983 * to figure out where it goes in the instruction. */
7990 ip->insn_opcode |= regno << OP_SH_RS;
7994 ip->insn_opcode |= regno << OP_SH_RD;
7997 ip->insn_opcode |= regno << OP_SH_RD;
7998 ip->insn_opcode |= regno << OP_SH_RT;
8003 ip->insn_opcode |= regno << OP_SH_RT;
8006 /* This case exists because on the r3000 trunc
8007 expands into a macro which requires a gp
8008 register. On the r6000 or r4000 it is
8009 assembled into a single instruction which
8010 ignores the register. Thus the insn version
8011 is MIPS_ISA2 and uses 'x', and the macro
8012 version is MIPS_ISA1 and uses 't'. */
8015 /* This case is for the div instruction, which
8016 acts differently if the destination argument
8017 is $0. This only matches $0, and is checked
8018 outside the switch. */
8021 /* Itbl operand; not yet implemented. FIXME ?? */
8023 /* What about all other operands like 'i', which
8024 can be specified in the opcode table? */
8034 ip->insn_opcode |= lastregno << OP_SH_RS;
8037 ip->insn_opcode |= lastregno << OP_SH_RT;
8042 case 'D': /* floating point destination register */
8043 case 'S': /* floating point source register */
8044 case 'T': /* floating point target register */
8045 case 'R': /* floating point source register */
8049 if (s[0] == '$' && s[1] == 'f'
8060 while (ISDIGIT (*s));
8063 as_bad (_("Invalid float register number (%d)"), regno);
8065 if ((regno & 1) != 0
8067 && ! (strcmp (str, "mtc1") == 0
8068 || strcmp (str, "mfc1") == 0
8069 || strcmp (str, "lwc1") == 0
8070 || strcmp (str, "swc1") == 0
8071 || strcmp (str, "l.s") == 0
8072 || strcmp (str, "s.s") == 0))
8073 as_warn (_("Float register should be even, was %d"),
8081 if (c == 'V' || c == 'W')
8091 ip->insn_opcode |= regno << OP_SH_FD;
8095 ip->insn_opcode |= regno << OP_SH_FS;
8099 ip->insn_opcode |= regno << OP_SH_FT;
8102 ip->insn_opcode |= regno << OP_SH_FR;
8112 ip->insn_opcode |= lastregno << OP_SH_FS;
8115 ip->insn_opcode |= lastregno << OP_SH_FT;
8121 my_getExpression (&imm_expr, s);
8122 if (imm_expr.X_op != O_big
8123 && imm_expr.X_op != O_constant)
8124 insn_error = _("absolute expression required");
8129 my_getExpression (&offset_expr, s);
8130 *imm_reloc = BFD_RELOC_32;
8143 unsigned char temp[8];
8145 unsigned int length;
8150 /* These only appear as the last operand in an
8151 instruction, and every instruction that accepts
8152 them in any variant accepts them in all variants.
8153 This means we don't have to worry about backing out
8154 any changes if the instruction does not match.
8156 The difference between them is the size of the
8157 floating point constant and where it goes. For 'F'
8158 and 'L' the constant is 64 bits; for 'f' and 'l' it
8159 is 32 bits. Where the constant is placed is based
8160 on how the MIPS assembler does things:
8163 f -- immediate value
8166 The .lit4 and .lit8 sections are only used if
8167 permitted by the -G argument.
8169 When generating embedded PIC code, we use the
8170 .lit8 section but not the .lit4 section (we can do
8171 .lit4 inline easily; we need to put .lit8
8172 somewhere in the data segment, and using .lit8
8173 permits the linker to eventually combine identical
8176 The code below needs to know whether the target register
8177 is 32 or 64 bits wide. It relies on the fact 'f' and
8178 'F' are used with GPR-based instructions and 'l' and
8179 'L' are used with FPR-based instructions. */
8181 f64 = *args == 'F' || *args == 'L';
8182 using_gprs = *args == 'F' || *args == 'f';
8184 save_in = input_line_pointer;
8185 input_line_pointer = s;
8186 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8188 s = input_line_pointer;
8189 input_line_pointer = save_in;
8190 if (err != NULL && *err != '\0')
8192 as_bad (_("Bad floating point constant: %s"), err);
8193 memset (temp, '\0', sizeof temp);
8194 length = f64 ? 8 : 4;
8197 assert (length == (unsigned) (f64 ? 8 : 4));
8201 && (! USE_GLOBAL_POINTER_OPT
8202 || mips_pic == EMBEDDED_PIC
8203 || g_switch_value < 4
8204 || (temp[0] == 0 && temp[1] == 0)
8205 || (temp[2] == 0 && temp[3] == 0))))
8207 imm_expr.X_op = O_constant;
8208 if (! target_big_endian)
8209 imm_expr.X_add_number = bfd_getl32 (temp);
8211 imm_expr.X_add_number = bfd_getb32 (temp);
8214 && ! mips_disable_float_construction
8215 /* Constants can only be constructed in GPRs and
8216 copied to FPRs if the GPRs are at least as wide
8217 as the FPRs. Force the constant into memory if
8218 we are using 64-bit FPRs but the GPRs are only
8221 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8222 && ((temp[0] == 0 && temp[1] == 0)
8223 || (temp[2] == 0 && temp[3] == 0))
8224 && ((temp[4] == 0 && temp[5] == 0)
8225 || (temp[6] == 0 && temp[7] == 0)))
8227 /* The value is simple enough to load with a couple of
8228 instructions. If using 32-bit registers, set
8229 imm_expr to the high order 32 bits and offset_expr to
8230 the low order 32 bits. Otherwise, set imm_expr to
8231 the entire 64 bit constant. */
8232 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8234 imm_expr.X_op = O_constant;
8235 offset_expr.X_op = O_constant;
8236 if (! target_big_endian)
8238 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8239 offset_expr.X_add_number = bfd_getl32 (temp);
8243 imm_expr.X_add_number = bfd_getb32 (temp);
8244 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8246 if (offset_expr.X_add_number == 0)
8247 offset_expr.X_op = O_absent;
8249 else if (sizeof (imm_expr.X_add_number) > 4)
8251 imm_expr.X_op = O_constant;
8252 if (! target_big_endian)
8253 imm_expr.X_add_number = bfd_getl64 (temp);
8255 imm_expr.X_add_number = bfd_getb64 (temp);
8259 imm_expr.X_op = O_big;
8260 imm_expr.X_add_number = 4;
8261 if (! target_big_endian)
8263 generic_bignum[0] = bfd_getl16 (temp);
8264 generic_bignum[1] = bfd_getl16 (temp + 2);
8265 generic_bignum[2] = bfd_getl16 (temp + 4);
8266 generic_bignum[3] = bfd_getl16 (temp + 6);
8270 generic_bignum[0] = bfd_getb16 (temp + 6);
8271 generic_bignum[1] = bfd_getb16 (temp + 4);
8272 generic_bignum[2] = bfd_getb16 (temp + 2);
8273 generic_bignum[3] = bfd_getb16 (temp);
8279 const char *newname;
8282 /* Switch to the right section. */
8284 subseg = now_subseg;
8287 default: /* unused default case avoids warnings. */
8289 newname = RDATA_SECTION_NAME;
8290 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8291 || mips_pic == EMBEDDED_PIC)
8295 if (mips_pic == EMBEDDED_PIC)
8298 newname = RDATA_SECTION_NAME;
8301 assert (!USE_GLOBAL_POINTER_OPT
8302 || g_switch_value >= 4);
8306 new_seg = subseg_new (newname, (subsegT) 0);
8307 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8308 bfd_set_section_flags (stdoutput, new_seg,
8313 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8314 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8315 && strcmp (TARGET_OS, "elf") != 0)
8316 record_alignment (new_seg, 4);
8318 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8320 as_bad (_("Can't use floating point insn in this section"));
8322 /* Set the argument to the current address in the
8324 offset_expr.X_op = O_symbol;
8325 offset_expr.X_add_symbol =
8326 symbol_new ("L0\001", now_seg,
8327 (valueT) frag_now_fix (), frag_now);
8328 offset_expr.X_add_number = 0;
8330 /* Put the floating point number into the section. */
8331 p = frag_more ((int) length);
8332 memcpy (p, temp, length);
8334 /* Switch back to the original section. */
8335 subseg_set (seg, subseg);
8340 case 'i': /* 16 bit unsigned immediate */
8341 case 'j': /* 16 bit signed immediate */
8342 *imm_reloc = BFD_RELOC_LO16;
8343 c = my_getSmallExpression (&imm_expr, s);
8348 if (imm_expr.X_op == O_constant)
8349 imm_expr.X_add_number =
8350 (imm_expr.X_add_number >> 16) & 0xffff;
8352 else if (c == S_EX_HIGHEST)
8353 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8354 else if (c == S_EX_HIGHER)
8355 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8356 else if (c == S_EX_GP_REL)
8358 /* This occurs in NewABI only. */
8359 c = my_getSmallExpression (&imm_expr, s);
8361 as_bad (_("bad composition of relocations"));
8364 c = my_getSmallExpression (&imm_expr, s);
8366 as_bad (_("bad composition of relocations"));
8369 imm_reloc[0] = BFD_RELOC_GPREL16;
8370 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8371 imm_reloc[2] = BFD_RELOC_LO16;
8376 else if (c == S_EX_HI)
8378 *imm_reloc = BFD_RELOC_HI16_S;
8379 imm_unmatched_hi = true;
8382 *imm_reloc = BFD_RELOC_HI16;
8384 else if (imm_expr.X_op == O_constant)
8385 imm_expr.X_add_number &= 0xffff;
8389 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8390 || ((imm_expr.X_add_number < 0
8391 || imm_expr.X_add_number >= 0x10000)
8392 && imm_expr.X_op == O_constant))
8394 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8395 !strcmp (insn->name, insn[1].name))
8397 if (imm_expr.X_op == O_constant
8398 || imm_expr.X_op == O_big)
8399 as_bad (_("16 bit expression not in range 0..65535"));
8407 /* The upper bound should be 0x8000, but
8408 unfortunately the MIPS assembler accepts numbers
8409 from 0x8000 to 0xffff and sign extends them, and
8410 we want to be compatible. We only permit this
8411 extended range for an instruction which does not
8412 provide any further alternates, since those
8413 alternates may handle other cases. People should
8414 use the numbers they mean, rather than relying on
8415 a mysterious sign extension. */
8416 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8417 strcmp (insn->name, insn[1].name) == 0);
8422 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8423 || ((imm_expr.X_add_number < -0x8000
8424 || imm_expr.X_add_number >= max)
8425 && imm_expr.X_op == O_constant)
8427 && imm_expr.X_add_number < 0
8429 && imm_expr.X_unsigned
8430 && sizeof (imm_expr.X_add_number) <= 4))
8434 if (imm_expr.X_op == O_constant
8435 || imm_expr.X_op == O_big)
8436 as_bad (_("16 bit expression not in range -32768..32767"));
8442 case 'o': /* 16 bit offset */
8443 c = my_getSmallExpression (&offset_expr, s);
8445 /* If this value won't fit into a 16 bit offset, then go
8446 find a macro that will generate the 32 bit offset
8449 && (offset_expr.X_op != O_constant
8450 || offset_expr.X_add_number >= 0x8000
8451 || offset_expr.X_add_number < -0x8000))
8456 if (offset_expr.X_op != O_constant)
8458 offset_expr.X_add_number =
8459 (offset_expr.X_add_number >> 16) & 0xffff;
8461 *offset_reloc = BFD_RELOC_LO16;
8465 case 'p': /* pc relative offset */
8466 if (mips_pic == EMBEDDED_PIC)
8467 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8469 *offset_reloc = BFD_RELOC_16_PCREL;
8470 my_getExpression (&offset_expr, s);
8474 case 'u': /* upper 16 bits */
8475 c = my_getSmallExpression (&imm_expr, s);
8476 *imm_reloc = BFD_RELOC_LO16;
8481 if (imm_expr.X_op == O_constant)
8482 imm_expr.X_add_number =
8483 (imm_expr.X_add_number >> 16) & 0xffff;
8484 else if (c == S_EX_HI)
8486 *imm_reloc = BFD_RELOC_HI16_S;
8487 imm_unmatched_hi = true;
8490 else if (c == S_EX_HIGHEST)
8491 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8492 else if (c == S_EX_GP_REL)
8494 /* This occurs in NewABI only. */
8495 c = my_getSmallExpression (&imm_expr, s);
8497 as_bad (_("bad composition of relocations"));
8500 c = my_getSmallExpression (&imm_expr, s);
8502 as_bad (_("bad composition of relocations"));
8505 imm_reloc[0] = BFD_RELOC_GPREL16;
8506 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8507 imm_reloc[2] = BFD_RELOC_HI16_S;
8513 *imm_reloc = BFD_RELOC_HI16;
8515 else if (imm_expr.X_op == O_constant)
8516 imm_expr.X_add_number &= 0xffff;
8518 if (imm_expr.X_op == O_constant
8519 && (imm_expr.X_add_number < 0
8520 || imm_expr.X_add_number >= 0x10000))
8521 as_bad (_("lui expression not in range 0..65535"));
8525 case 'a': /* 26 bit address */
8526 my_getExpression (&offset_expr, s);
8528 *offset_reloc = BFD_RELOC_MIPS_JMP;
8531 case 'N': /* 3 bit branch condition code */
8532 case 'M': /* 3 bit compare condition code */
8533 if (strncmp (s, "$fcc", 4) != 0)
8543 while (ISDIGIT (*s));
8545 as_bad (_("invalid condition code register $fcc%d"), regno);
8547 ip->insn_opcode |= regno << OP_SH_BCC;
8549 ip->insn_opcode |= regno << OP_SH_CCC;
8553 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8564 while (ISDIGIT (*s));
8567 c = 8; /* Invalid sel value. */
8570 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8571 ip->insn_opcode |= c;
8575 as_bad (_("bad char = '%c'\n"), *args);
8580 /* Args don't match. */
8581 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8582 !strcmp (insn->name, insn[1].name))
8586 insn_error = _("illegal operands");
8591 insn_error = _("illegal operands");
8596 /* This routine assembles an instruction into its binary format when
8597 assembling for the mips16. As a side effect, it sets one of the
8598 global variables imm_reloc or offset_reloc to the type of
8599 relocation to do if one of the operands is an address expression.
8600 It also sets mips16_small and mips16_ext if the user explicitly
8601 requested a small or extended instruction. */
8606 struct mips_cl_insn *ip;
8610 struct mips_opcode *insn;
8613 unsigned int lastregno = 0;
8618 mips16_small = false;
8621 for (s = str; ISLOWER (*s); ++s)
8633 if (s[1] == 't' && s[2] == ' ')
8636 mips16_small = true;
8640 else if (s[1] == 'e' && s[2] == ' ')
8649 insn_error = _("unknown opcode");
8653 if (mips_opts.noautoextend && ! mips16_ext)
8654 mips16_small = true;
8656 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8658 insn_error = _("unrecognized opcode");
8665 assert (strcmp (insn->name, str) == 0);
8668 ip->insn_opcode = insn->match;
8669 ip->use_extend = false;
8670 imm_expr.X_op = O_absent;
8671 imm_reloc[0] = BFD_RELOC_UNUSED;
8672 imm_reloc[1] = BFD_RELOC_UNUSED;
8673 imm_reloc[2] = BFD_RELOC_UNUSED;
8674 offset_expr.X_op = O_absent;
8675 offset_reloc[0] = BFD_RELOC_UNUSED;
8676 offset_reloc[1] = BFD_RELOC_UNUSED;
8677 offset_reloc[2] = BFD_RELOC_UNUSED;
8678 for (args = insn->args; 1; ++args)
8685 /* In this switch statement we call break if we did not find
8686 a match, continue if we did find a match, or return if we
8695 /* Stuff the immediate value in now, if we can. */
8696 if (imm_expr.X_op == O_constant
8697 && *imm_reloc > BFD_RELOC_UNUSED
8698 && insn->pinfo != INSN_MACRO)
8700 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8701 imm_expr.X_add_number, true, mips16_small,
8702 mips16_ext, &ip->insn_opcode,
8703 &ip->use_extend, &ip->extend);
8704 imm_expr.X_op = O_absent;
8705 *imm_reloc = BFD_RELOC_UNUSED;
8719 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8722 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8738 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8740 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8767 while (ISDIGIT (*s));
8770 as_bad (_("invalid register number (%d)"), regno);
8776 if (s[1] == 'f' && s[2] == 'p')
8781 else if (s[1] == 's' && s[2] == 'p')
8786 else if (s[1] == 'g' && s[2] == 'p')
8791 else if (s[1] == 'a' && s[2] == 't')
8796 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8801 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8814 if (c == 'v' || c == 'w')
8816 regno = mips16_to_32_reg_map[lastregno];
8830 regno = mips32_to_16_reg_map[regno];
8835 regno = ILLEGAL_REG;
8840 regno = ILLEGAL_REG;
8845 regno = ILLEGAL_REG;
8850 if (regno == AT && ! mips_opts.noat)
8851 as_warn (_("used $at without \".set noat\""));
8858 if (regno == ILLEGAL_REG)
8865 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
8869 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
8872 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
8875 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
8881 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
8884 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
8885 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
8895 if (strncmp (s, "$pc", 3) == 0)
8919 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
8921 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8922 and generate the appropriate reloc. If the text
8923 inside %gprel is not a symbol name with an
8924 optional offset, then we generate a normal reloc
8925 and will probably fail later. */
8926 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
8927 if (imm_expr.X_op == O_symbol)
8930 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
8932 ip->use_extend = true;
8939 /* Just pick up a normal expression. */
8940 my_getExpression (&imm_expr, s);
8943 if (imm_expr.X_op == O_register)
8945 /* What we thought was an expression turned out to
8948 if (s[0] == '(' && args[1] == '(')
8950 /* It looks like the expression was omitted
8951 before a register indirection, which means
8952 that the expression is implicitly zero. We
8953 still set up imm_expr, so that we handle
8954 explicit extensions correctly. */
8955 imm_expr.X_op = O_constant;
8956 imm_expr.X_add_number = 0;
8957 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
8964 /* We need to relax this instruction. */
8965 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
8974 /* We use offset_reloc rather than imm_reloc for the PC
8975 relative operands. This lets macros with both
8976 immediate and address operands work correctly. */
8977 my_getExpression (&offset_expr, s);
8979 if (offset_expr.X_op == O_register)
8982 /* We need to relax this instruction. */
8983 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
8987 case '6': /* break code */
8988 my_getExpression (&imm_expr, s);
8989 check_absolute_expr (ip, &imm_expr);
8990 if ((unsigned long) imm_expr.X_add_number > 63)
8992 as_warn (_("Invalid value for `%s' (%lu)"),
8994 (unsigned long) imm_expr.X_add_number);
8995 imm_expr.X_add_number &= 0x3f;
8997 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
8998 imm_expr.X_op = O_absent;
9002 case 'a': /* 26 bit address */
9003 my_getExpression (&offset_expr, s);
9005 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9006 ip->insn_opcode <<= 16;
9009 case 'l': /* register list for entry macro */
9010 case 'L': /* register list for exit macro */
9020 int freg, reg1, reg2;
9022 while (*s == ' ' || *s == ',')
9026 as_bad (_("can't parse register list"));
9038 while (ISDIGIT (*s))
9060 as_bad (_("invalid register list"));
9065 while (ISDIGIT (*s))
9072 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9077 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9082 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9083 mask |= (reg2 - 3) << 3;
9084 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9085 mask |= (reg2 - 15) << 1;
9086 else if (reg1 == 31 && reg2 == 31)
9090 as_bad (_("invalid register list"));
9094 /* The mask is filled in in the opcode table for the
9095 benefit of the disassembler. We remove it before
9096 applying the actual mask. */
9097 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9098 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9102 case 'e': /* extend code */
9103 my_getExpression (&imm_expr, s);
9104 check_absolute_expr (ip, &imm_expr);
9105 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9107 as_warn (_("Invalid value for `%s' (%lu)"),
9109 (unsigned long) imm_expr.X_add_number);
9110 imm_expr.X_add_number &= 0x7ff;
9112 ip->insn_opcode |= imm_expr.X_add_number;
9113 imm_expr.X_op = O_absent;
9123 /* Args don't match. */
9124 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9125 strcmp (insn->name, insn[1].name) == 0)
9132 insn_error = _("illegal operands");
9138 /* This structure holds information we know about a mips16 immediate
9141 struct mips16_immed_operand
9143 /* The type code used in the argument string in the opcode table. */
9145 /* The number of bits in the short form of the opcode. */
9147 /* The number of bits in the extended form of the opcode. */
9149 /* The amount by which the short form is shifted when it is used;
9150 for example, the sw instruction has a shift count of 2. */
9152 /* The amount by which the short form is shifted when it is stored
9153 into the instruction code. */
9155 /* Non-zero if the short form is unsigned. */
9157 /* Non-zero if the extended form is unsigned. */
9159 /* Non-zero if the value is PC relative. */
9163 /* The mips16 immediate operand types. */
9165 static const struct mips16_immed_operand mips16_immed_operands[] =
9167 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9168 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9169 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9170 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9171 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9172 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9173 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9174 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9175 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9176 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9177 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9178 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9179 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9180 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9181 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9182 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9183 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9184 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9185 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9186 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9187 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9190 #define MIPS16_NUM_IMMED \
9191 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9193 /* Handle a mips16 instruction with an immediate value. This or's the
9194 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9195 whether an extended value is needed; if one is needed, it sets
9196 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9197 If SMALL is true, an unextended opcode was explicitly requested.
9198 If EXT is true, an extended opcode was explicitly requested. If
9199 WARN is true, warn if EXT does not match reality. */
9202 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9211 unsigned long *insn;
9212 boolean *use_extend;
9213 unsigned short *extend;
9215 register const struct mips16_immed_operand *op;
9216 int mintiny, maxtiny;
9219 op = mips16_immed_operands;
9220 while (op->type != type)
9223 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9228 if (type == '<' || type == '>' || type == '[' || type == ']')
9231 maxtiny = 1 << op->nbits;
9236 maxtiny = (1 << op->nbits) - 1;
9241 mintiny = - (1 << (op->nbits - 1));
9242 maxtiny = (1 << (op->nbits - 1)) - 1;
9245 /* Branch offsets have an implicit 0 in the lowest bit. */
9246 if (type == 'p' || type == 'q')
9249 if ((val & ((1 << op->shift) - 1)) != 0
9250 || val < (mintiny << op->shift)
9251 || val > (maxtiny << op->shift))
9256 if (warn && ext && ! needext)
9257 as_warn_where (file, line,
9258 _("extended operand requested but not required"));
9259 if (small && needext)
9260 as_bad_where (file, line, _("invalid unextended operand value"));
9262 if (small || (! ext && ! needext))
9266 *use_extend = false;
9267 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9268 insnval <<= op->op_shift;
9273 long minext, maxext;
9279 maxext = (1 << op->extbits) - 1;
9283 minext = - (1 << (op->extbits - 1));
9284 maxext = (1 << (op->extbits - 1)) - 1;
9286 if (val < minext || val > maxext)
9287 as_bad_where (file, line,
9288 _("operand value out of range for instruction"));
9291 if (op->extbits == 16)
9293 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9296 else if (op->extbits == 15)
9298 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9303 extval = ((val & 0x1f) << 6) | (val & 0x20);
9307 *extend = (unsigned short) extval;
9312 static struct percent_op_match
9315 const enum small_ex_type type;
9320 {"%call_hi", S_EX_CALL_HI},
9321 {"%call_lo", S_EX_CALL_LO},
9322 {"%call16", S_EX_CALL16},
9323 {"%got_disp", S_EX_GOT_DISP},
9324 {"%got_page", S_EX_GOT_PAGE},
9325 {"%got_ofst", S_EX_GOT_OFST},
9326 {"%got_hi", S_EX_GOT_HI},
9327 {"%got_lo", S_EX_GOT_LO},
9329 {"%gp_rel", S_EX_GP_REL},
9330 {"%half", S_EX_HALF},
9331 {"%highest", S_EX_HIGHEST},
9332 {"%higher", S_EX_HIGHER},
9338 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9339 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9340 can be nested, this is handled by blanking the innermost, parsing the
9341 rest by subsequent calls. */
9344 my_getSmallParser (str, len, nestlevel)
9350 *str += strspn (*str, " \t");
9351 /* Check for expression in parentheses. */
9354 char *b = *str + 1 + strspn (*str + 1, " \t");
9357 /* Check for base register. */
9361 && (e = b + strcspn (b, ") \t"))
9362 && e - b > 1 && e - b < 4)
9365 && ((b[1] == 'f' && b[2] == 'p')
9366 || (b[1] == 's' && b[2] == 'p')
9367 || (b[1] == 'g' && b[2] == 'p')
9368 || (b[1] == 'a' && b[2] == 't')
9370 && ISDIGIT (b[2]))))
9371 || (ISDIGIT (b[1])))
9373 *len = strcspn (*str, ")") + 1;
9374 return S_EX_REGISTER;
9378 /* Check for percent_op (in parentheses). */
9379 else if (b[0] == '%')
9382 return my_getPercentOp (str, len, nestlevel);
9385 /* Some other expression in the parentheses, which can contain
9386 parentheses itself. Attempt to find the matching one. */
9392 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9401 /* Check for percent_op (outside of parentheses). */
9402 else if (*str[0] == '%')
9403 return my_getPercentOp (str, len, nestlevel);
9405 /* Any other expression. */
9410 my_getPercentOp (str, len, nestlevel)
9415 char *tmp = *str + 1;
9418 while (ISALPHA (*tmp) || *tmp == '_')
9420 *tmp = TOLOWER (*tmp);
9423 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9425 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9429 int type = percent_op[i].type;
9431 /* Only %hi and %lo are allowed for OldABI. */
9432 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9435 *len = strlen (percent_op[i].str);
9444 my_getSmallExpression (ep, str)
9448 static char *oldstr = NULL;
9454 /* Don't update oldstr if the last call had nested percent_op's. We need
9455 it to parse the outer ones later. */
9462 c = my_getSmallParser (&str, &len, &nestlevel);
9463 if (c != S_EX_NONE && c != S_EX_REGISTER)
9466 while (c != S_EX_NONE && c != S_EX_REGISTER);
9470 /* A percent_op was encountered. Don't try to get an expression if
9471 it is already blanked out. */
9472 if (*(str + strspn (str + 1, " )")) != ')')
9476 /* Let my_getExpression() stop at the closing parenthesis. */
9477 save = *(str + len);
9478 *(str + len) = '\0';
9479 my_getExpression (ep, str);
9480 *(str + len) = save;
9484 /* Blank out including the % sign and the proper matching
9487 char *s = strrchr (oldstr, '%');
9490 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9494 else if (*end == ')')
9498 memset (s, ' ', end - s);
9502 expr_end = str + len;
9506 else if (c == S_EX_NONE)
9508 my_getExpression (ep, str);
9510 else if (c == S_EX_REGISTER)
9512 ep->X_op = O_constant;
9514 ep->X_add_symbol = NULL;
9515 ep->X_op_symbol = NULL;
9516 ep->X_add_number = 0;
9520 as_fatal(_("internal error"));
9524 /* All percent_op's have been handled. */
9531 my_getExpression (ep, str)
9538 save_in = input_line_pointer;
9539 input_line_pointer = str;
9541 expr_end = input_line_pointer;
9542 input_line_pointer = save_in;
9544 /* If we are in mips16 mode, and this is an expression based on `.',
9545 then we bump the value of the symbol by 1 since that is how other
9546 text symbols are handled. We don't bother to handle complex
9547 expressions, just `.' plus or minus a constant. */
9548 if (mips_opts.mips16
9549 && ep->X_op == O_symbol
9550 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9551 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9552 && symbol_get_frag (ep->X_add_symbol) == frag_now
9553 && symbol_constant_p (ep->X_add_symbol)
9554 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9555 S_SET_VALUE (ep->X_add_symbol, val + 1);
9558 /* Turn a string in input_line_pointer into a floating point constant
9559 of type TYPE, and store the appropriate bytes in *LITP. The number
9560 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9561 returned, or NULL on OK. */
9564 md_atof (type, litP, sizeP)
9570 LITTLENUM_TYPE words[4];
9586 return _("bad call to md_atof");
9589 t = atof_ieee (input_line_pointer, type, words);
9591 input_line_pointer = t;
9595 if (! target_big_endian)
9597 for (i = prec - 1; i >= 0; i--)
9599 md_number_to_chars (litP, (valueT) words[i], 2);
9605 for (i = 0; i < prec; i++)
9607 md_number_to_chars (litP, (valueT) words[i], 2);
9616 md_number_to_chars (buf, val, n)
9621 if (target_big_endian)
9622 number_to_chars_bigendian (buf, val, n);
9624 number_to_chars_littleendian (buf, val, n);
9628 static int support_64bit_objects(void)
9630 const char **list, **l;
9632 list = bfd_target_list ();
9633 for (l = list; *l != NULL; l++)
9635 /* This is traditional mips */
9636 if (strcmp (*l, "elf64-tradbigmips") == 0
9637 || strcmp (*l, "elf64-tradlittlemips") == 0)
9639 if (strcmp (*l, "elf64-bigmips") == 0
9640 || strcmp (*l, "elf64-littlemips") == 0)
9644 return (*l != NULL);
9646 #endif /* OBJ_ELF */
9648 CONST char *md_shortopts = "nO::g::G:";
9650 struct option md_longopts[] =
9652 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9653 {"mips0", no_argument, NULL, OPTION_MIPS1},
9654 {"mips1", no_argument, NULL, OPTION_MIPS1},
9655 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9656 {"mips2", no_argument, NULL, OPTION_MIPS2},
9657 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9658 {"mips3", no_argument, NULL, OPTION_MIPS3},
9659 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9660 {"mips4", no_argument, NULL, OPTION_MIPS4},
9661 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9662 {"mips5", no_argument, NULL, OPTION_MIPS5},
9663 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9664 {"mips32", no_argument, NULL, OPTION_MIPS32},
9665 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9666 {"mips64", no_argument, NULL, OPTION_MIPS64},
9667 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9668 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9669 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9670 {"trap", no_argument, NULL, OPTION_TRAP},
9671 {"no-break", no_argument, NULL, OPTION_TRAP},
9672 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9673 {"break", no_argument, NULL, OPTION_BREAK},
9674 {"no-trap", no_argument, NULL, OPTION_BREAK},
9675 #define OPTION_EB (OPTION_MD_BASE + 11)
9676 {"EB", no_argument, NULL, OPTION_EB},
9677 #define OPTION_EL (OPTION_MD_BASE + 12)
9678 {"EL", no_argument, NULL, OPTION_EL},
9679 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9680 {"mips16", no_argument, NULL, OPTION_MIPS16},
9681 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9682 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9683 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9684 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9685 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16)
9686 {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX},
9687 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9688 {"mfp32", no_argument, NULL, OPTION_FP32},
9689 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9690 {"mgp32", no_argument, NULL, OPTION_GP32},
9691 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9692 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9693 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9694 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9695 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9696 {"march", required_argument, NULL, OPTION_MARCH},
9697 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9698 {"mtune", required_argument, NULL, OPTION_MTUNE},
9699 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9700 {"mcpu", required_argument, NULL, OPTION_MCPU},
9701 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9702 {"m4650", no_argument, NULL, OPTION_M4650},
9703 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9704 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9705 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9706 {"m4010", no_argument, NULL, OPTION_M4010},
9707 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9708 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9709 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9710 {"m4100", no_argument, NULL, OPTION_M4100},
9711 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9712 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9713 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9714 {"m3900", no_argument, NULL, OPTION_M3900},
9715 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9716 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9717 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9718 {"mgp64", no_argument, NULL, OPTION_GP64},
9720 #define OPTION_ELF_BASE (OPTION_MD_BASE + 33)
9721 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9722 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9723 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9724 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9725 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
9726 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9727 {"xgot", no_argument, NULL, OPTION_XGOT},
9728 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9729 {"mabi", required_argument, NULL, OPTION_MABI},
9730 #define OPTION_32 (OPTION_ELF_BASE + 4)
9731 {"32", no_argument, NULL, OPTION_32},
9732 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9733 {"n32", no_argument, NULL, OPTION_N32},
9734 #define OPTION_64 (OPTION_ELF_BASE + 6)
9735 {"64", no_argument, NULL, OPTION_64},
9736 #endif /* OBJ_ELF */
9737 {NULL, no_argument, NULL, 0}
9739 size_t md_longopts_size = sizeof (md_longopts);
9742 md_parse_option (c, arg)
9748 case OPTION_CONSTRUCT_FLOATS:
9749 mips_disable_float_construction = 0;
9752 case OPTION_NO_CONSTRUCT_FLOATS:
9753 mips_disable_float_construction = 1;
9765 target_big_endian = 1;
9769 target_big_endian = 0;
9777 if (arg && arg[1] == '0')
9787 mips_debug = atoi (arg);
9788 /* When the MIPS assembler sees -g or -g2, it does not do
9789 optimizations which limit full symbolic debugging. We take
9790 that to be equivalent to -O0. */
9791 if (mips_debug == 2)
9796 mips_opts.isa = ISA_MIPS1;
9800 mips_opts.isa = ISA_MIPS2;
9804 mips_opts.isa = ISA_MIPS3;
9808 mips_opts.isa = ISA_MIPS4;
9812 mips_opts.isa = ISA_MIPS5;
9816 mips_opts.isa = ISA_MIPS32;
9820 mips_opts.isa = ISA_MIPS64;
9827 int cpu = CPU_UNKNOWN;
9829 /* Identify the processor type. */
9830 if (strcasecmp (arg, "default") != 0)
9832 const struct mips_cpu_info *ci;
9834 ci = mips_cpu_info_from_name (arg);
9835 if (ci == NULL || ci->is_isa)
9840 as_fatal (_("invalid architecture -mtune=%s"), arg);
9843 as_fatal (_("invalid architecture -march=%s"), arg);
9846 as_fatal (_("invalid architecture -mcpu=%s"), arg);
9857 if (mips_tune != CPU_UNKNOWN && mips_tune != cpu)
9858 as_warn(_("A different -mtune= was already specified, is now "
9863 if (mips_arch != CPU_UNKNOWN && mips_arch != cpu)
9864 as_warn(_("A different -march= was already specified, is now "
9869 if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu)
9870 as_warn(_("A different -mcpu= was already specified, is now "
9878 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650)
9879 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650))
9880 as_warn(_("A different -march= or -mtune= was already specified, "
9882 mips_arch = CPU_R4650;
9883 mips_tune = CPU_R4650;
9886 case OPTION_NO_M4650:
9890 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010)
9891 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010))
9892 as_warn(_("A different -march= or -mtune= was already specified, "
9894 mips_arch = CPU_R4010;
9895 mips_tune = CPU_R4010;
9898 case OPTION_NO_M4010:
9902 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100)
9903 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100))
9904 as_warn(_("A different -march= or -mtune= was already specified, "
9906 mips_arch = CPU_VR4100;
9907 mips_tune = CPU_VR4100;
9910 case OPTION_NO_M4100:
9914 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900)
9915 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900))
9916 as_warn(_("A different -march= or -mtune= was already specified, "
9918 mips_arch = CPU_R3900;
9919 mips_tune = CPU_R3900;
9922 case OPTION_NO_M3900:
9926 mips_opts.mips16 = 1;
9927 mips_no_prev_insn (false);
9930 case OPTION_NO_MIPS16:
9931 mips_opts.mips16 = 0;
9932 mips_no_prev_insn (false);
9935 case OPTION_MEMBEDDED_PIC:
9936 mips_pic = EMBEDDED_PIC;
9937 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
9939 as_bad (_("-G may not be used with embedded PIC code"));
9942 g_switch_value = 0x7fffffff;
9946 /* When generating ELF code, we permit -KPIC and -call_shared to
9947 select SVR4_PIC, and -non_shared to select no PIC. This is
9948 intended to be compatible with Irix 5. */
9949 case OPTION_CALL_SHARED:
9950 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
9952 as_bad (_("-call_shared is supported only for ELF format"));
9955 mips_pic = SVR4_PIC;
9956 if (g_switch_seen && g_switch_value != 0)
9958 as_bad (_("-G may not be used with SVR4 PIC code"));
9964 case OPTION_NON_SHARED:
9965 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
9967 as_bad (_("-non_shared is supported only for ELF format"));
9973 /* The -xgot option tells the assembler to use 32 offsets when
9974 accessing the got in SVR4_PIC mode. It is for Irix
9979 #endif /* OBJ_ELF */
9982 if (! USE_GLOBAL_POINTER_OPT)
9984 as_bad (_("-G is not supported for this configuration"));
9987 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
9989 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9993 g_switch_value = atoi (arg);
9998 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10001 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10003 as_bad (_("-32 is supported for ELF format only"));
10006 mips_opts.abi = O32_ABI;
10010 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10012 as_bad (_("-n32 is supported for ELF format only"));
10015 mips_opts.abi = N32_ABI;
10019 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10021 as_bad (_("-64 is supported for ELF format only"));
10024 mips_opts.abi = N64_ABI;
10025 if (! support_64bit_objects())
10026 as_fatal (_("No compiled in support for 64 bit object file format"));
10028 #endif /* OBJ_ELF */
10031 file_mips_gp32 = 1;
10032 if (mips_opts.abi != O32_ABI)
10033 mips_opts.abi = NO_ABI;
10037 file_mips_gp32 = 0;
10038 if (mips_opts.abi == O32_ABI)
10039 mips_opts.abi = NO_ABI;
10043 file_mips_fp32 = 1;
10044 if (mips_opts.abi != O32_ABI)
10045 mips_opts.abi = NO_ABI;
10050 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10052 as_bad (_("-mabi is supported for ELF format only"));
10055 if (strcmp (arg, "32") == 0)
10056 mips_opts.abi = O32_ABI;
10057 else if (strcmp (arg, "o64") == 0)
10058 mips_opts.abi = O64_ABI;
10059 else if (strcmp (arg, "n32") == 0)
10060 mips_opts.abi = N32_ABI;
10061 else if (strcmp (arg, "64") == 0)
10063 mips_opts.abi = N64_ABI;
10064 if (! support_64bit_objects())
10065 as_fatal (_("No compiled in support for 64 bit object file "
10068 else if (strcmp (arg, "eabi") == 0)
10069 mips_opts.abi = EABI_ABI;
10071 mips_opts.abi = NO_ABI;
10073 #endif /* OBJ_ELF */
10075 case OPTION_M7000_HILO_FIX:
10076 mips_7000_hilo_fix = true;
10079 case OPTION_NO_M7000_HILO_FIX:
10080 mips_7000_hilo_fix = false;
10091 show (stream, string, col_p, first_p)
10099 fprintf (stream, "%24s", "");
10104 fprintf (stream, ", ");
10108 if (*col_p + strlen (string) > 72)
10110 fprintf (stream, "\n%24s", "");
10114 fprintf (stream, "%s", string);
10115 *col_p += strlen (string);
10121 md_show_usage (stream)
10126 fprintf (stream, _("\
10128 -membedded-pic generate embedded position independent code\n\
10129 -EB generate big endian output\n\
10130 -EL generate little endian output\n\
10131 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10132 -G NUM allow referencing objects up to NUM bytes\n\
10133 implicitly with the gp register [default 8]\n"));
10134 fprintf (stream, _("\
10135 -mips1 generate MIPS ISA I instructions\n\
10136 -mips2 generate MIPS ISA II instructions\n\
10137 -mips3 generate MIPS ISA III instructions\n\
10138 -mips4 generate MIPS ISA IV instructions\n\
10139 -mips5 generate MIPS ISA V instructions\n\
10140 -mips32 generate MIPS32 ISA instructions\n\
10141 -mips64 generate MIPS64 ISA instructions\n\
10142 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10146 show (stream, "2000", &column, &first);
10147 show (stream, "3000", &column, &first);
10148 show (stream, "3900", &column, &first);
10149 show (stream, "4000", &column, &first);
10150 show (stream, "4010", &column, &first);
10151 show (stream, "4100", &column, &first);
10152 show (stream, "4111", &column, &first);
10153 show (stream, "4300", &column, &first);
10154 show (stream, "4400", &column, &first);
10155 show (stream, "4600", &column, &first);
10156 show (stream, "4650", &column, &first);
10157 show (stream, "5000", &column, &first);
10158 show (stream, "5200", &column, &first);
10159 show (stream, "5230", &column, &first);
10160 show (stream, "5231", &column, &first);
10161 show (stream, "5261", &column, &first);
10162 show (stream, "5721", &column, &first);
10163 show (stream, "6000", &column, &first);
10164 show (stream, "8000", &column, &first);
10165 show (stream, "10000", &column, &first);
10166 show (stream, "12000", &column, &first);
10167 show (stream, "sb1", &column, &first);
10168 fputc ('\n', stream);
10170 fprintf (stream, _("\
10171 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10172 -no-mCPU don't generate code specific to CPU.\n\
10173 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10177 show (stream, "3900", &column, &first);
10178 show (stream, "4010", &column, &first);
10179 show (stream, "4100", &column, &first);
10180 show (stream, "4650", &column, &first);
10181 fputc ('\n', stream);
10183 fprintf (stream, _("\
10184 -mips16 generate mips16 instructions\n\
10185 -no-mips16 do not generate mips16 instructions\n"));
10186 fprintf (stream, _("\
10187 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10188 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10189 -O0 remove unneeded NOPs, do not swap branches\n\
10190 -O remove unneeded NOPs and swap branches\n\
10191 -n warn about NOPs generated from macros\n\
10192 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10193 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10194 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10196 fprintf (stream, _("\
10197 -KPIC, -call_shared generate SVR4 position independent code\n\
10198 -non_shared do not generate position independent code\n\
10199 -xgot assume a 32 bit GOT\n\
10200 -mabi=ABI create ABI conformant object file for:\n"));
10204 show (stream, "32", &column, &first);
10205 show (stream, "o64", &column, &first);
10206 show (stream, "n32", &column, &first);
10207 show (stream, "64", &column, &first);
10208 show (stream, "eabi", &column, &first);
10210 fputc ('\n', stream);
10212 fprintf (stream, _("\
10213 -32 create o32 ABI object file (default)\n\
10214 -n32 create n32 ABI object file\n\
10215 -64 create 64 ABI object file\n"));
10220 mips_init_after_args ()
10222 /* initialize opcodes */
10223 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10224 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10228 md_pcrel_from (fixP)
10231 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10232 && fixP->fx_addsy != (symbolS *) NULL
10233 && ! S_IS_DEFINED (fixP->fx_addsy))
10235 /* This makes a branch to an undefined symbol be a branch to the
10236 current location. */
10237 if (mips_pic == EMBEDDED_PIC)
10243 /* return the address of the delay slot */
10244 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10247 /* This is called before the symbol table is processed. In order to
10248 work with gcc when using mips-tfile, we must keep all local labels.
10249 However, in other cases, we want to discard them. If we were
10250 called with -g, but we didn't see any debugging information, it may
10251 mean that gcc is smuggling debugging information through to
10252 mips-tfile, in which case we must generate all local labels. */
10255 mips_frob_file_before_adjust ()
10257 #ifndef NO_ECOFF_DEBUGGING
10258 if (ECOFF_DEBUGGING
10260 && ! ecoff_debugging_seen)
10261 flag_keep_locals = 1;
10265 /* Sort any unmatched HI16_S relocs so that they immediately precede
10266 the corresponding LO reloc. This is called before md_apply_fix3 and
10267 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10268 explicit use of the %hi modifier. */
10273 struct mips_hi_fixup *l;
10275 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10277 segment_info_type *seginfo;
10280 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10282 /* Check quickly whether the next fixup happens to be a matching
10284 if (l->fixp->fx_next != NULL
10285 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10286 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10287 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10290 /* Look through the fixups for this segment for a matching %lo.
10291 When we find one, move the %hi just in front of it. We do
10292 this in two passes. In the first pass, we try to find a
10293 unique %lo. In the second pass, we permit multiple %hi
10294 relocs for a single %lo (this is a GNU extension). */
10295 seginfo = seg_info (l->seg);
10296 for (pass = 0; pass < 2; pass++)
10301 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10303 /* Check whether this is a %lo fixup which matches l->fixp. */
10304 if (f->fx_r_type == BFD_RELOC_LO16
10305 && f->fx_addsy == l->fixp->fx_addsy
10306 && f->fx_offset == l->fixp->fx_offset
10309 || prev->fx_r_type != BFD_RELOC_HI16_S
10310 || prev->fx_addsy != f->fx_addsy
10311 || prev->fx_offset != f->fx_offset))
10315 /* Move l->fixp before f. */
10316 for (pf = &seginfo->fix_root;
10318 pf = &(*pf)->fx_next)
10319 assert (*pf != NULL);
10321 *pf = l->fixp->fx_next;
10323 l->fixp->fx_next = f;
10325 seginfo->fix_root = l->fixp;
10327 prev->fx_next = l->fixp;
10338 #if 0 /* GCC code motion plus incomplete dead code elimination
10339 can leave a %hi without a %lo. */
10341 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10342 _("Unmatched %%hi reloc"));
10348 /* When generating embedded PIC code we need to use a special
10349 relocation to represent the difference of two symbols in the .text
10350 section (switch tables use a difference of this sort). See
10351 include/coff/mips.h for details. This macro checks whether this
10352 fixup requires the special reloc. */
10353 #define SWITCH_TABLE(fixp) \
10354 ((fixp)->fx_r_type == BFD_RELOC_32 \
10355 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10356 && (fixp)->fx_addsy != NULL \
10357 && (fixp)->fx_subsy != NULL \
10358 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10359 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10361 /* When generating embedded PIC code we must keep all PC relative
10362 relocations, in case the linker has to relax a call. We also need
10363 to keep relocations for switch table entries.
10365 We may have combined relocations without symbols in the N32/N64 ABI.
10366 We have to prevent gas from dropping them. */
10369 mips_force_relocation (fixp)
10372 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10373 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10377 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10378 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10379 || fixp->fx_r_type == BFD_RELOC_HI16_S
10380 || fixp->fx_r_type == BFD_RELOC_LO16))
10383 return (mips_pic == EMBEDDED_PIC
10385 || SWITCH_TABLE (fixp)
10386 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10387 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10392 mips_need_elf_addend_fixup (fixP)
10395 return (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16
10396 || ((S_IS_WEAK (fixP->fx_addsy)
10397 || S_IS_EXTERN (fixP->fx_addsy))
10398 && !S_IS_COMMON (fixP->fx_addsy))
10399 || (symbol_used_in_reloc_p (fixP->fx_addsy)
10400 && (((bfd_get_section_flags (stdoutput,
10401 S_GET_SEGMENT (fixP->fx_addsy))
10402 & SEC_LINK_ONCE) != 0)
10403 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10405 sizeof (".gnu.linkonce") - 1))));
10409 /* Apply a fixup to the object file. */
10412 md_apply_fix3 (fixP, valP, seg)
10415 segT seg ATTRIBUTE_UNUSED;
10417 unsigned char *buf;
10421 assert (fixP->fx_size == 4
10422 || fixP->fx_r_type == BFD_RELOC_16
10423 || fixP->fx_r_type == BFD_RELOC_32
10424 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10425 || fixP->fx_r_type == BFD_RELOC_HI16_S
10426 || fixP->fx_r_type == BFD_RELOC_LO16
10427 || fixP->fx_r_type == BFD_RELOC_GPREL16
10428 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10429 || fixP->fx_r_type == BFD_RELOC_GPREL32
10430 || fixP->fx_r_type == BFD_RELOC_64
10431 || fixP->fx_r_type == BFD_RELOC_CTOR
10432 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10433 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10434 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10435 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10436 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10437 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10438 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10439 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
10443 /* If we aren't adjusting this fixup to be against the section
10444 symbol, we need to adjust the value. */
10446 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10448 if (mips_need_elf_addend_fixup (fixP))
10450 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10453 if (value != 0 && ! fixP->fx_pcrel)
10455 /* In this case, the bfd_install_relocation routine will
10456 incorrectly add the symbol value back in. We just want
10457 the addend to appear in the object file. */
10460 /* Make sure the addend is still non-zero. If it became zero
10461 after the last operation, set it to a spurious value and
10462 subtract the same value from the object file's contents. */
10467 /* The in-place addends for LO16 relocations are signed;
10468 leave the matching HI16 in-place addends as zero. */
10469 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10471 reloc_howto_type *howto;
10472 bfd_vma contents, mask, field;
10474 howto = bfd_reloc_type_lookup (stdoutput,
10477 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10480 target_big_endian);
10482 /* MASK has bits set where the relocation should go.
10483 FIELD is -value, shifted into the appropriate place
10484 for this relocation. */
10485 mask = 1 << (howto->bitsize - 1);
10486 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10487 field = (-value >> howto->rightshift) << howto->bitpos;
10489 bfd_put_bits ((field & mask) | (contents & ~mask),
10490 fixP->fx_frag->fr_literal + fixP->fx_where,
10492 target_big_endian);
10498 /* This code was generated using trial and error and so is
10499 fragile and not trustworthy. If you change it, you should
10500 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10501 they still pass. */
10502 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10504 value += fixP->fx_frag->fr_address + fixP->fx_where;
10506 /* BFD's REL handling, for MIPS, is _very_ weird.
10507 This gives the right results, but it can't possibly
10508 be the way things are supposed to work. */
10509 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10510 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10511 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10512 value += fixP->fx_frag->fr_address + fixP->fx_where;
10517 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10519 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
10522 switch (fixP->fx_r_type)
10524 case BFD_RELOC_MIPS_JMP:
10525 case BFD_RELOC_MIPS_SHIFT5:
10526 case BFD_RELOC_MIPS_SHIFT6:
10527 case BFD_RELOC_MIPS_GOT_DISP:
10528 case BFD_RELOC_MIPS_GOT_PAGE:
10529 case BFD_RELOC_MIPS_GOT_OFST:
10530 case BFD_RELOC_MIPS_SUB:
10531 case BFD_RELOC_MIPS_INSERT_A:
10532 case BFD_RELOC_MIPS_INSERT_B:
10533 case BFD_RELOC_MIPS_DELETE:
10534 case BFD_RELOC_MIPS_HIGHEST:
10535 case BFD_RELOC_MIPS_HIGHER:
10536 case BFD_RELOC_MIPS_SCN_DISP:
10537 case BFD_RELOC_MIPS_REL16:
10538 case BFD_RELOC_MIPS_RELGOT:
10539 case BFD_RELOC_MIPS_JALR:
10540 case BFD_RELOC_HI16:
10541 case BFD_RELOC_HI16_S:
10542 case BFD_RELOC_GPREL16:
10543 case BFD_RELOC_MIPS_LITERAL:
10544 case BFD_RELOC_MIPS_CALL16:
10545 case BFD_RELOC_MIPS_GOT16:
10546 case BFD_RELOC_GPREL32:
10547 case BFD_RELOC_MIPS_GOT_HI16:
10548 case BFD_RELOC_MIPS_GOT_LO16:
10549 case BFD_RELOC_MIPS_CALL_HI16:
10550 case BFD_RELOC_MIPS_CALL_LO16:
10551 case BFD_RELOC_MIPS16_GPREL:
10552 if (fixP->fx_pcrel)
10553 as_bad_where (fixP->fx_file, fixP->fx_line,
10554 _("Invalid PC relative reloc"));
10555 /* Nothing needed to do. The value comes from the reloc entry */
10558 case BFD_RELOC_MIPS16_JMP:
10559 /* We currently always generate a reloc against a symbol, which
10560 means that we don't want an addend even if the symbol is
10562 fixP->fx_addnumber = 0;
10565 case BFD_RELOC_PCREL_HI16_S:
10566 /* The addend for this is tricky if it is internal, so we just
10567 do everything here rather than in bfd_install_relocation. */
10568 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10573 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10575 /* For an external symbol adjust by the address to make it
10576 pcrel_offset. We use the address of the RELLO reloc
10577 which follows this one. */
10578 value += (fixP->fx_next->fx_frag->fr_address
10579 + fixP->fx_next->fx_where);
10581 value = ((value + 0x8000) >> 16) & 0xffff;
10582 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
10583 if (target_big_endian)
10585 md_number_to_chars (buf, value, 2);
10588 case BFD_RELOC_PCREL_LO16:
10589 /* The addend for this is tricky if it is internal, so we just
10590 do everything here rather than in bfd_install_relocation. */
10591 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10596 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10597 value += fixP->fx_frag->fr_address + fixP->fx_where;
10598 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
10599 if (target_big_endian)
10601 md_number_to_chars (buf, value, 2);
10605 /* This is handled like BFD_RELOC_32, but we output a sign
10606 extended value if we are only 32 bits. */
10608 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10610 if (8 <= sizeof (valueT))
10611 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10618 w1 = w2 = fixP->fx_where;
10619 if (target_big_endian)
10623 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
10624 if ((value & 0x80000000) != 0)
10628 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
10633 case BFD_RELOC_RVA:
10635 /* If we are deleting this reloc entry, we must fill in the
10636 value now. This can happen if we have a .word which is not
10637 resolved when it appears but is later defined. We also need
10638 to fill in the value if this is an embedded PIC switch table
10641 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10642 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10647 /* If we are deleting this reloc entry, we must fill in the
10649 assert (fixP->fx_size == 2);
10651 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10655 case BFD_RELOC_LO16:
10656 /* When handling an embedded PIC switch statement, we can wind
10657 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10660 if (value + 0x8000 > 0xffff)
10661 as_bad_where (fixP->fx_file, fixP->fx_line,
10662 _("relocation overflow"));
10663 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
10664 if (target_big_endian)
10666 md_number_to_chars (buf, value, 2);
10670 case BFD_RELOC_16_PCREL_S2:
10671 if ((value & 0x3) != 0)
10672 as_bad_where (fixP->fx_file, fixP->fx_line,
10673 _("Branch to odd address (%lx)"), (long) value);
10675 /* Fall through. */
10677 case BFD_RELOC_16_PCREL:
10679 * We need to save the bits in the instruction since fixup_segment()
10680 * might be deleting the relocation entry (i.e., a branch within
10681 * the current segment).
10683 if (!fixP->fx_done && value != 0)
10685 /* If 'value' is zero, the remaining reloc code won't actually
10686 do the store, so it must be done here. This is probably
10687 a bug somewhere. */
10688 if (!fixP->fx_done)
10689 value -= fixP->fx_frag->fr_address + fixP->fx_where;
10691 value = (offsetT) value >> 2;
10693 /* update old instruction data */
10694 buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal);
10695 if (target_big_endian)
10696 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
10698 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
10700 if (value + 0x8000 <= 0xffff)
10701 insn |= value & 0xffff;
10704 /* The branch offset is too large. If this is an
10705 unconditional branch, and we are not generating PIC code,
10706 we can convert it to an absolute jump instruction. */
10707 if (mips_pic == NO_PIC
10709 && fixP->fx_frag->fr_address >= text_section->vma
10710 && (fixP->fx_frag->fr_address
10711 < text_section->vma + text_section->_raw_size)
10712 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
10713 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
10714 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
10716 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
10717 insn = 0x0c000000; /* jal */
10719 insn = 0x08000000; /* j */
10720 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
10722 fixP->fx_addsy = section_symbol (text_section);
10723 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
10727 /* FIXME. It would be possible in principle to handle
10728 conditional branches which overflow. They could be
10729 transformed into a branch around a jump. This would
10730 require setting up variant frags for each different
10731 branch type. The native MIPS assembler attempts to
10732 handle these cases, but it appears to do it
10734 as_bad_where (fixP->fx_file, fixP->fx_line,
10735 _("Branch out of range"));
10739 md_number_to_chars ((char *) buf, (valueT) insn, 4);
10742 case BFD_RELOC_VTABLE_INHERIT:
10745 && !S_IS_DEFINED (fixP->fx_addsy)
10746 && !S_IS_WEAK (fixP->fx_addsy))
10747 S_SET_WEAK (fixP->fx_addsy);
10750 case BFD_RELOC_VTABLE_ENTRY:
10764 const struct mips_opcode *p;
10765 int treg, sreg, dreg, shamt;
10770 for (i = 0; i < NUMOPCODES; ++i)
10772 p = &mips_opcodes[i];
10773 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
10775 printf ("%08lx %s\t", oc, p->name);
10776 treg = (oc >> 16) & 0x1f;
10777 sreg = (oc >> 21) & 0x1f;
10778 dreg = (oc >> 11) & 0x1f;
10779 shamt = (oc >> 6) & 0x1f;
10781 for (args = p->args;; ++args)
10792 printf ("%c", *args);
10796 assert (treg == sreg);
10797 printf ("$%d,$%d", treg, sreg);
10802 printf ("$%d", dreg);
10807 printf ("$%d", treg);
10811 printf ("0x%x", treg);
10816 printf ("$%d", sreg);
10820 printf ("0x%08lx", oc & 0x1ffffff);
10827 printf ("%d", imm);
10832 printf ("$%d", shamt);
10843 printf (_("%08lx UNDEFINED\n"), oc);
10854 name = input_line_pointer;
10855 c = get_symbol_end ();
10856 p = (symbolS *) symbol_find_or_make (name);
10857 *input_line_pointer = c;
10861 /* Align the current frag to a given power of two. The MIPS assembler
10862 also automatically adjusts any preceding label. */
10865 mips_align (to, fill, label)
10870 mips_emit_delays (false);
10871 frag_align (to, fill, 0);
10872 record_alignment (now_seg, to);
10875 assert (S_GET_SEGMENT (label) == now_seg);
10876 symbol_set_frag (label, frag_now);
10877 S_SET_VALUE (label, (valueT) frag_now_fix ());
10881 /* Align to a given power of two. .align 0 turns off the automatic
10882 alignment used by the data creating pseudo-ops. */
10886 int x ATTRIBUTE_UNUSED;
10889 register long temp_fill;
10890 long max_alignment = 15;
10894 o Note that the assembler pulls down any immediately preceeding label
10895 to the aligned address.
10896 o It's not documented but auto alignment is reinstated by
10897 a .align pseudo instruction.
10898 o Note also that after auto alignment is turned off the mips assembler
10899 issues an error on attempt to assemble an improperly aligned data item.
10904 temp = get_absolute_expression ();
10905 if (temp > max_alignment)
10906 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
10909 as_warn (_("Alignment negative: 0 assumed."));
10912 if (*input_line_pointer == ',')
10914 input_line_pointer++;
10915 temp_fill = get_absolute_expression ();
10922 mips_align (temp, (int) temp_fill,
10923 insn_labels != NULL ? insn_labels->label : NULL);
10930 demand_empty_rest_of_line ();
10934 mips_flush_pending_output ()
10936 mips_emit_delays (false);
10937 mips_clear_insn_labels ();
10946 /* When generating embedded PIC code, we only use the .text, .lit8,
10947 .sdata and .sbss sections. We change the .data and .rdata
10948 pseudo-ops to use .sdata. */
10949 if (mips_pic == EMBEDDED_PIC
10950 && (sec == 'd' || sec == 'r'))
10954 /* The ELF backend needs to know that we are changing sections, so
10955 that .previous works correctly. We could do something like check
10956 for an obj_section_change_hook macro, but that might be confusing
10957 as it would not be appropriate to use it in the section changing
10958 functions in read.c, since obj-elf.c intercepts those. FIXME:
10959 This should be cleaner, somehow. */
10960 obj_elf_section_change_hook ();
10963 mips_emit_delays (false);
10973 subseg_set (bss_section, (subsegT) get_absolute_expression ());
10974 demand_empty_rest_of_line ();
10978 if (USE_GLOBAL_POINTER_OPT)
10980 seg = subseg_new (RDATA_SECTION_NAME,
10981 (subsegT) get_absolute_expression ());
10982 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
10984 bfd_set_section_flags (stdoutput, seg,
10990 if (strcmp (TARGET_OS, "elf") != 0)
10991 record_alignment (seg, 4);
10993 demand_empty_rest_of_line ();
10997 as_bad (_("No read only data section in this object file format"));
10998 demand_empty_rest_of_line ();
11004 if (USE_GLOBAL_POINTER_OPT)
11006 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11007 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11009 bfd_set_section_flags (stdoutput, seg,
11010 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11012 if (strcmp (TARGET_OS, "elf") != 0)
11013 record_alignment (seg, 4);
11015 demand_empty_rest_of_line ();
11020 as_bad (_("Global pointers not supported; recompile -G 0"));
11021 demand_empty_rest_of_line ();
11030 mips_enable_auto_align ()
11041 label = insn_labels != NULL ? insn_labels->label : NULL;
11042 mips_emit_delays (false);
11043 if (log_size > 0 && auto_align)
11044 mips_align (log_size, 0, label);
11045 mips_clear_insn_labels ();
11046 cons (1 << log_size);
11050 s_float_cons (type)
11055 label = insn_labels != NULL ? insn_labels->label : NULL;
11057 mips_emit_delays (false);
11062 mips_align (3, 0, label);
11064 mips_align (2, 0, label);
11067 mips_clear_insn_labels ();
11072 /* Handle .globl. We need to override it because on Irix 5 you are
11075 where foo is an undefined symbol, to mean that foo should be
11076 considered to be the address of a function. */
11080 int x ATTRIBUTE_UNUSED;
11087 name = input_line_pointer;
11088 c = get_symbol_end ();
11089 symbolP = symbol_find_or_make (name);
11090 *input_line_pointer = c;
11091 SKIP_WHITESPACE ();
11093 /* On Irix 5, every global symbol that is not explicitly labelled as
11094 being a function is apparently labelled as being an object. */
11097 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11102 secname = input_line_pointer;
11103 c = get_symbol_end ();
11104 sec = bfd_get_section_by_name (stdoutput, secname);
11106 as_bad (_("%s: no such section"), secname);
11107 *input_line_pointer = c;
11109 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11110 flag = BSF_FUNCTION;
11113 symbol_get_bfdsym (symbolP)->flags |= flag;
11115 S_SET_EXTERNAL (symbolP);
11116 demand_empty_rest_of_line ();
11121 int x ATTRIBUTE_UNUSED;
11126 opt = input_line_pointer;
11127 c = get_symbol_end ();
11131 /* FIXME: What does this mean? */
11133 else if (strncmp (opt, "pic", 3) == 0)
11137 i = atoi (opt + 3);
11141 mips_pic = SVR4_PIC;
11143 as_bad (_(".option pic%d not supported"), i);
11145 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11147 if (g_switch_seen && g_switch_value != 0)
11148 as_warn (_("-G may not be used with SVR4 PIC code"));
11149 g_switch_value = 0;
11150 bfd_set_gp_size (stdoutput, 0);
11154 as_warn (_("Unrecognized option \"%s\""), opt);
11156 *input_line_pointer = c;
11157 demand_empty_rest_of_line ();
11160 /* This structure is used to hold a stack of .set values. */
11162 struct mips_option_stack
11164 struct mips_option_stack *next;
11165 struct mips_set_options options;
11168 static struct mips_option_stack *mips_opts_stack;
11170 /* Handle the .set pseudo-op. */
11174 int x ATTRIBUTE_UNUSED;
11176 char *name = input_line_pointer, ch;
11178 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11179 input_line_pointer++;
11180 ch = *input_line_pointer;
11181 *input_line_pointer = '\0';
11183 if (strcmp (name, "reorder") == 0)
11185 if (mips_opts.noreorder && prev_nop_frag != NULL)
11187 /* If we still have pending nops, we can discard them. The
11188 usual nop handling will insert any that are still
11190 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11191 * (mips_opts.mips16 ? 2 : 4));
11192 prev_nop_frag = NULL;
11194 mips_opts.noreorder = 0;
11196 else if (strcmp (name, "noreorder") == 0)
11198 mips_emit_delays (true);
11199 mips_opts.noreorder = 1;
11200 mips_any_noreorder = 1;
11202 else if (strcmp (name, "at") == 0)
11204 mips_opts.noat = 0;
11206 else if (strcmp (name, "noat") == 0)
11208 mips_opts.noat = 1;
11210 else if (strcmp (name, "macro") == 0)
11212 mips_opts.warn_about_macros = 0;
11214 else if (strcmp (name, "nomacro") == 0)
11216 if (mips_opts.noreorder == 0)
11217 as_bad (_("`noreorder' must be set before `nomacro'"));
11218 mips_opts.warn_about_macros = 1;
11220 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11222 mips_opts.nomove = 0;
11224 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11226 mips_opts.nomove = 1;
11228 else if (strcmp (name, "bopt") == 0)
11230 mips_opts.nobopt = 0;
11232 else if (strcmp (name, "nobopt") == 0)
11234 mips_opts.nobopt = 1;
11236 else if (strcmp (name, "mips16") == 0
11237 || strcmp (name, "MIPS-16") == 0)
11238 mips_opts.mips16 = 1;
11239 else if (strcmp (name, "nomips16") == 0
11240 || strcmp (name, "noMIPS-16") == 0)
11241 mips_opts.mips16 = 0;
11242 else if (strncmp (name, "mips", 4) == 0)
11246 /* Permit the user to change the ISA on the fly. Needless to
11247 say, misuse can cause serious problems. */
11248 isa = atoi (name + 4);
11252 mips_opts.gp32 = file_mips_gp32;
11253 mips_opts.fp32 = file_mips_fp32;
11254 mips_opts.abi = file_mips_abi;
11259 mips_opts.gp32 = 1;
11260 mips_opts.fp32 = 1;
11266 /* Loosen ABI register width restriction. */
11267 if (mips_opts.abi == O32_ABI)
11268 mips_opts.abi = NO_ABI;
11269 mips_opts.gp32 = 0;
11270 mips_opts.fp32 = 0;
11273 as_bad (_("unknown ISA level %s"), name + 4);
11279 case 0: mips_opts.isa = file_mips_isa; break;
11280 case 1: mips_opts.isa = ISA_MIPS1; break;
11281 case 2: mips_opts.isa = ISA_MIPS2; break;
11282 case 3: mips_opts.isa = ISA_MIPS3; break;
11283 case 4: mips_opts.isa = ISA_MIPS4; break;
11284 case 5: mips_opts.isa = ISA_MIPS5; break;
11285 case 32: mips_opts.isa = ISA_MIPS32; break;
11286 case 64: mips_opts.isa = ISA_MIPS64; break;
11287 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11290 else if (strcmp (name, "autoextend") == 0)
11291 mips_opts.noautoextend = 0;
11292 else if (strcmp (name, "noautoextend") == 0)
11293 mips_opts.noautoextend = 1;
11294 else if (strcmp (name, "push") == 0)
11296 struct mips_option_stack *s;
11298 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11299 s->next = mips_opts_stack;
11300 s->options = mips_opts;
11301 mips_opts_stack = s;
11303 else if (strcmp (name, "pop") == 0)
11305 struct mips_option_stack *s;
11307 s = mips_opts_stack;
11309 as_bad (_(".set pop with no .set push"));
11312 /* If we're changing the reorder mode we need to handle
11313 delay slots correctly. */
11314 if (s->options.noreorder && ! mips_opts.noreorder)
11315 mips_emit_delays (true);
11316 else if (! s->options.noreorder && mips_opts.noreorder)
11318 if (prev_nop_frag != NULL)
11320 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11321 * (mips_opts.mips16 ? 2 : 4));
11322 prev_nop_frag = NULL;
11326 mips_opts = s->options;
11327 mips_opts_stack = s->next;
11333 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11335 *input_line_pointer = ch;
11336 demand_empty_rest_of_line ();
11339 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11340 .option pic2. It means to generate SVR4 PIC calls. */
11343 s_abicalls (ignore)
11344 int ignore ATTRIBUTE_UNUSED;
11346 mips_pic = SVR4_PIC;
11347 if (USE_GLOBAL_POINTER_OPT)
11349 if (g_switch_seen && g_switch_value != 0)
11350 as_warn (_("-G may not be used with SVR4 PIC code"));
11351 g_switch_value = 0;
11353 bfd_set_gp_size (stdoutput, 0);
11354 demand_empty_rest_of_line ();
11357 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11358 PIC code. It sets the $gp register for the function based on the
11359 function address, which is in the register named in the argument.
11360 This uses a relocation against _gp_disp, which is handled specially
11361 by the linker. The result is:
11362 lui $gp,%hi(_gp_disp)
11363 addiu $gp,$gp,%lo(_gp_disp)
11364 addu $gp,$gp,.cpload argument
11365 The .cpload argument is normally $25 == $t9. */
11369 int ignore ATTRIBUTE_UNUSED;
11374 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11375 .cpload is ignored. */
11376 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11382 /* .cpload should be in a .set noreorder section. */
11383 if (mips_opts.noreorder == 0)
11384 as_warn (_(".cpload not in noreorder section"));
11386 ex.X_op = O_symbol;
11387 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11388 ex.X_op_symbol = NULL;
11389 ex.X_add_number = 0;
11391 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11392 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11394 macro_build_lui (NULL, &icnt, &ex, GP);
11395 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP,
11396 (int) BFD_RELOC_LO16);
11398 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11399 GP, GP, tc_get_register (0));
11401 demand_empty_rest_of_line ();
11404 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11405 .cpsetup $reg1, offset|$reg2, label
11407 If offset is given, this results in:
11408 sd $gp, offset($sp)
11409 lui $gp, %hi(%neg(%gp_rel(label)))
11410 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11411 addu $gp, $gp, $reg1
11413 If $reg2 is given, this results in:
11414 daddu $reg2, $gp, $0
11415 lui $gp, %hi(%neg(%gp_rel(label)))
11416 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11417 addu $gp, $gp, $reg1
11421 int ignore ATTRIBUTE_UNUSED;
11423 expressionS ex_off;
11424 expressionS ex_sym;
11429 /* If we are not generating SVR4 PIC code, .cpload is ignored.
11430 We also need NewABI support. */
11431 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11437 reg1 = tc_get_register (0);
11438 SKIP_WHITESPACE ();
11439 if (*input_line_pointer != ',')
11441 as_bad (_("missing argument separator ',' for .cpsetup"));
11445 input_line_pointer++;
11446 SKIP_WHITESPACE ();
11447 if (*input_line_pointer == '$')
11448 mips_cpreturn_register = tc_get_register (0);
11450 mips_cpreturn_offset = get_absolute_expression ();
11451 SKIP_WHITESPACE ();
11452 if (*input_line_pointer != ',')
11454 as_bad (_("missing argument separator ',' for .cpsetup"));
11458 input_line_pointer++;
11459 SKIP_WHITESPACE ();
11460 sym = input_line_pointer;
11461 while (ISALNUM (*input_line_pointer))
11462 input_line_pointer++;
11463 *input_line_pointer = 0;
11465 ex_sym.X_op = O_symbol;
11466 ex_sym.X_add_symbol = symbol_find_or_make (sym);
11467 ex_sym.X_op_symbol = NULL;
11468 ex_sym.X_add_number = 0;
11470 if (mips_cpreturn_register == -1)
11472 ex_off.X_op = O_constant;
11473 ex_off.X_add_symbol = NULL;
11474 ex_off.X_op_symbol = NULL;
11475 ex_off.X_add_number = mips_cpreturn_offset;
11477 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11478 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11481 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11482 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11484 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11485 (int) BFD_RELOC_GPREL16);
11486 fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0,
11487 NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11488 fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0,
11489 NULL, 0, 0, BFD_RELOC_HI16_S);
11490 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11491 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11492 fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0,
11493 NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11494 fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0,
11495 NULL, 0, 0, BFD_RELOC_LO16);
11496 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11497 "d,v,t", mips_gp_register, mips_gp_register, reg1);
11499 demand_empty_rest_of_line ();
11504 int ignore ATTRIBUTE_UNUSED;
11506 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11507 .cplocal is ignored. */
11508 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11514 mips_gp_register = tc_get_register (0);
11517 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11518 offset from $sp. The offset is remembered, and after making a PIC
11519 call $gp is restored from that location. */
11522 s_cprestore (ignore)
11523 int ignore ATTRIBUTE_UNUSED;
11528 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11529 .cprestore is ignored. */
11530 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11536 mips_cprestore_offset = get_absolute_expression ();
11537 mips_cprestore_valid = 1;
11539 ex.X_op = O_constant;
11540 ex.X_add_symbol = NULL;
11541 ex.X_op_symbol = NULL;
11542 ex.X_add_number = mips_cprestore_offset;
11544 macro_build ((char *) NULL, &icnt, &ex,
11545 HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11546 "t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
11548 demand_empty_rest_of_line ();
11551 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11552 was given in the preceeding .gpsetup, it results in:
11553 ld $gp, offset($sp)
11555 If a register $reg2 was given there, it results in:
11556 daddiu $gp, $gp, $reg2
11559 s_cpreturn (ignore)
11560 int ignore ATTRIBUTE_UNUSED;
11565 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11566 We also need NewABI support. */
11567 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11573 if (mips_cpreturn_register == -1)
11575 ex.X_op = O_constant;
11576 ex.X_add_symbol = NULL;
11577 ex.X_op_symbol = NULL;
11578 ex.X_add_number = mips_cpreturn_offset;
11580 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
11581 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11584 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11585 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
11587 demand_empty_rest_of_line ();
11590 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11591 code. It sets the offset to use in gp_rel relocations. */
11595 int ignore ATTRIBUTE_UNUSED;
11597 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11598 We also need NewABI support. */
11599 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11605 mips_cpreturn_offset = get_absolute_expression ();
11607 demand_empty_rest_of_line ();
11610 /* Handle the .gpword pseudo-op. This is used when generating PIC
11611 code. It generates a 32 bit GP relative reloc. */
11615 int ignore ATTRIBUTE_UNUSED;
11621 /* When not generating PIC code, this is treated as .word. */
11622 if (mips_pic != SVR4_PIC)
11628 label = insn_labels != NULL ? insn_labels->label : NULL;
11629 mips_emit_delays (true);
11631 mips_align (2, 0, label);
11632 mips_clear_insn_labels ();
11636 if (ex.X_op != O_symbol || ex.X_add_number != 0)
11638 as_bad (_("Unsupported use of .gpword"));
11639 ignore_rest_of_line ();
11643 md_number_to_chars (p, (valueT) 0, 4);
11644 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0,
11645 BFD_RELOC_GPREL32);
11647 demand_empty_rest_of_line ();
11650 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11651 tables in SVR4 PIC code. */
11655 int ignore ATTRIBUTE_UNUSED;
11660 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11662 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11668 /* Add $gp to the register named as an argument. */
11669 reg = tc_get_register (0);
11670 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11671 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
11672 "d,v,t", reg, reg, GP);
11674 demand_empty_rest_of_line ();
11677 /* Handle the .insn pseudo-op. This marks instruction labels in
11678 mips16 mode. This permits the linker to handle them specially,
11679 such as generating jalx instructions when needed. We also make
11680 them odd for the duration of the assembly, in order to generate the
11681 right sort of code. We will make them even in the adjust_symtab
11682 routine, while leaving them marked. This is convenient for the
11683 debugger and the disassembler. The linker knows to make them odd
11688 int ignore ATTRIBUTE_UNUSED;
11690 if (mips_opts.mips16)
11691 mips16_mark_labels ();
11693 demand_empty_rest_of_line ();
11696 /* Handle a .stabn directive. We need these in order to mark a label
11697 as being a mips16 text label correctly. Sometimes the compiler
11698 will emit a label, followed by a .stabn, and then switch sections.
11699 If the label and .stabn are in mips16 mode, then the label is
11700 really a mips16 text label. */
11706 if (type == 'n' && mips_opts.mips16)
11707 mips16_mark_labels ();
11712 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11716 s_mips_weakext (ignore)
11717 int ignore ATTRIBUTE_UNUSED;
11724 name = input_line_pointer;
11725 c = get_symbol_end ();
11726 symbolP = symbol_find_or_make (name);
11727 S_SET_WEAK (symbolP);
11728 *input_line_pointer = c;
11730 SKIP_WHITESPACE ();
11732 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11734 if (S_IS_DEFINED (symbolP))
11736 as_bad ("ignoring attempt to redefine symbol %s",
11737 S_GET_NAME (symbolP));
11738 ignore_rest_of_line ();
11742 if (*input_line_pointer == ',')
11744 ++input_line_pointer;
11745 SKIP_WHITESPACE ();
11749 if (exp.X_op != O_symbol)
11751 as_bad ("bad .weakext directive");
11752 ignore_rest_of_line();
11755 symbol_set_value_expression (symbolP, &exp);
11758 demand_empty_rest_of_line ();
11761 /* Parse a register string into a number. Called from the ECOFF code
11762 to parse .frame. The argument is non-zero if this is the frame
11763 register, so that we can record it in mips_frame_reg. */
11766 tc_get_register (frame)
11771 SKIP_WHITESPACE ();
11772 if (*input_line_pointer++ != '$')
11774 as_warn (_("expected `$'"));
11777 else if (ISDIGIT (*input_line_pointer))
11779 reg = get_absolute_expression ();
11780 if (reg < 0 || reg >= 32)
11782 as_warn (_("Bad register number"));
11788 if (strncmp (input_line_pointer, "fp", 2) == 0)
11790 else if (strncmp (input_line_pointer, "sp", 2) == 0)
11792 else if (strncmp (input_line_pointer, "gp", 2) == 0)
11794 else if (strncmp (input_line_pointer, "at", 2) == 0)
11798 as_warn (_("Unrecognized register name"));
11801 input_line_pointer += 2;
11805 mips_frame_reg = reg != 0 ? reg : SP;
11806 mips_frame_reg_valid = 1;
11807 mips_cprestore_valid = 0;
11813 md_section_align (seg, addr)
11817 int align = bfd_get_section_alignment (stdoutput, seg);
11820 /* We don't need to align ELF sections to the full alignment.
11821 However, Irix 5 may prefer that we align them at least to a 16
11822 byte boundary. We don't bother to align the sections if we are
11823 targeted for an embedded system. */
11824 if (strcmp (TARGET_OS, "elf") == 0)
11830 return ((addr + (1 << align) - 1) & (-1 << align));
11833 /* Utility routine, called from above as well. If called while the
11834 input file is still being read, it's only an approximation. (For
11835 example, a symbol may later become defined which appeared to be
11836 undefined earlier.) */
11839 nopic_need_relax (sym, before_relaxing)
11841 int before_relaxing;
11846 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
11848 const char *symname;
11851 /* Find out whether this symbol can be referenced off the GP
11852 register. It can be if it is smaller than the -G size or if
11853 it is in the .sdata or .sbss section. Certain symbols can
11854 not be referenced off the GP, although it appears as though
11856 symname = S_GET_NAME (sym);
11857 if (symname != (const char *) NULL
11858 && (strcmp (symname, "eprol") == 0
11859 || strcmp (symname, "etext") == 0
11860 || strcmp (symname, "_gp") == 0
11861 || strcmp (symname, "edata") == 0
11862 || strcmp (symname, "_fbss") == 0
11863 || strcmp (symname, "_fdata") == 0
11864 || strcmp (symname, "_ftext") == 0
11865 || strcmp (symname, "end") == 0
11866 || strcmp (symname, "_gp_disp") == 0))
11868 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
11870 #ifndef NO_ECOFF_DEBUGGING
11871 || (symbol_get_obj (sym)->ecoff_extern_size != 0
11872 && (symbol_get_obj (sym)->ecoff_extern_size
11873 <= g_switch_value))
11875 /* We must defer this decision until after the whole
11876 file has been read, since there might be a .extern
11877 after the first use of this symbol. */
11878 || (before_relaxing
11879 #ifndef NO_ECOFF_DEBUGGING
11880 && symbol_get_obj (sym)->ecoff_extern_size == 0
11882 && S_GET_VALUE (sym) == 0)
11883 || (S_GET_VALUE (sym) != 0
11884 && S_GET_VALUE (sym) <= g_switch_value)))
11888 const char *segname;
11890 segname = segment_name (S_GET_SEGMENT (sym));
11891 assert (strcmp (segname, ".lit8") != 0
11892 && strcmp (segname, ".lit4") != 0);
11893 change = (strcmp (segname, ".sdata") != 0
11894 && strcmp (segname, ".sbss") != 0
11895 && strncmp (segname, ".sdata.", 7) != 0
11896 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
11901 /* We are not optimizing for the GP register. */
11905 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11906 extended opcode. SEC is the section the frag is in. */
11909 mips16_extended_frag (fragp, sec, stretch)
11915 register const struct mips16_immed_operand *op;
11917 int mintiny, maxtiny;
11921 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
11923 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
11926 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
11927 op = mips16_immed_operands;
11928 while (op->type != type)
11931 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11936 if (type == '<' || type == '>' || type == '[' || type == ']')
11939 maxtiny = 1 << op->nbits;
11944 maxtiny = (1 << op->nbits) - 1;
11949 mintiny = - (1 << (op->nbits - 1));
11950 maxtiny = (1 << (op->nbits - 1)) - 1;
11953 sym_frag = symbol_get_frag (fragp->fr_symbol);
11954 val = S_GET_VALUE (fragp->fr_symbol);
11955 symsec = S_GET_SEGMENT (fragp->fr_symbol);
11961 /* We won't have the section when we are called from
11962 mips_relax_frag. However, we will always have been called
11963 from md_estimate_size_before_relax first. If this is a
11964 branch to a different section, we mark it as such. If SEC is
11965 NULL, and the frag is not marked, then it must be a branch to
11966 the same section. */
11969 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
11974 /* Must have been called from md_estimate_size_before_relax. */
11977 fragp->fr_subtype =
11978 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
11980 /* FIXME: We should support this, and let the linker
11981 catch branches and loads that are out of range. */
11982 as_bad_where (fragp->fr_file, fragp->fr_line,
11983 _("unsupported PC relative reference to different section"));
11987 if (fragp != sym_frag && sym_frag->fr_address == 0)
11988 /* Assume non-extended on the first relaxation pass.
11989 The address we have calculated will be bogus if this is
11990 a forward branch to another frag, as the forward frag
11991 will have fr_address == 0. */
11995 /* In this case, we know for sure that the symbol fragment is in
11996 the same section. If the relax_marker of the symbol fragment
11997 differs from the relax_marker of this fragment, we have not
11998 yet adjusted the symbol fragment fr_address. We want to add
11999 in STRETCH in order to get a better estimate of the address.
12000 This particularly matters because of the shift bits. */
12002 && sym_frag->relax_marker != fragp->relax_marker)
12006 /* Adjust stretch for any alignment frag. Note that if have
12007 been expanding the earlier code, the symbol may be
12008 defined in what appears to be an earlier frag. FIXME:
12009 This doesn't handle the fr_subtype field, which specifies
12010 a maximum number of bytes to skip when doing an
12012 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12014 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12017 stretch = - ((- stretch)
12018 & ~ ((1 << (int) f->fr_offset) - 1));
12020 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12029 addr = fragp->fr_address + fragp->fr_fix;
12031 /* The base address rules are complicated. The base address of
12032 a branch is the following instruction. The base address of a
12033 PC relative load or add is the instruction itself, but if it
12034 is in a delay slot (in which case it can not be extended) use
12035 the address of the instruction whose delay slot it is in. */
12036 if (type == 'p' || type == 'q')
12040 /* If we are currently assuming that this frag should be
12041 extended, then, the current address is two bytes
12043 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12046 /* Ignore the low bit in the target, since it will be set
12047 for a text label. */
12048 if ((val & 1) != 0)
12051 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12053 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12056 val -= addr & ~ ((1 << op->shift) - 1);
12058 /* Branch offsets have an implicit 0 in the lowest bit. */
12059 if (type == 'p' || type == 'q')
12062 /* If any of the shifted bits are set, we must use an extended
12063 opcode. If the address depends on the size of this
12064 instruction, this can lead to a loop, so we arrange to always
12065 use an extended opcode. We only check this when we are in
12066 the main relaxation loop, when SEC is NULL. */
12067 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12069 fragp->fr_subtype =
12070 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12074 /* If we are about to mark a frag as extended because the value
12075 is precisely maxtiny + 1, then there is a chance of an
12076 infinite loop as in the following code:
12081 In this case when the la is extended, foo is 0x3fc bytes
12082 away, so the la can be shrunk, but then foo is 0x400 away, so
12083 the la must be extended. To avoid this loop, we mark the
12084 frag as extended if it was small, and is about to become
12085 extended with a value of maxtiny + 1. */
12086 if (val == ((maxtiny + 1) << op->shift)
12087 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12090 fragp->fr_subtype =
12091 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12095 else if (symsec != absolute_section && sec != NULL)
12096 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12098 if ((val & ((1 << op->shift) - 1)) != 0
12099 || val < (mintiny << op->shift)
12100 || val > (maxtiny << op->shift))
12106 /* Estimate the size of a frag before relaxing. Unless this is the
12107 mips16, we are not really relaxing here, and the final size is
12108 encoded in the subtype information. For the mips16, we have to
12109 decide whether we are using an extended opcode or not. */
12112 md_estimate_size_before_relax (fragp, segtype)
12117 boolean linkonce = false;
12119 if (RELAX_MIPS16_P (fragp->fr_subtype))
12121 if (mips16_extended_frag (fragp, segtype, 0))
12123 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12128 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12133 if (mips_pic == NO_PIC)
12135 change = nopic_need_relax (fragp->fr_symbol, 0);
12137 else if (mips_pic == SVR4_PIC)
12142 sym = fragp->fr_symbol;
12144 /* Handle the case of a symbol equated to another symbol. */
12145 while (symbol_equated_reloc_p (sym))
12149 /* It's possible to get a loop here in a badly written
12151 n = symbol_get_value_expression (sym)->X_add_symbol;
12157 symsec = S_GET_SEGMENT (sym);
12159 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12160 if (symsec != segtype && ! S_IS_LOCAL (sym))
12162 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12166 /* The GNU toolchain uses an extension for ELF: a section
12167 beginning with the magic string .gnu.linkonce is a linkonce
12169 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12170 sizeof ".gnu.linkonce" - 1) == 0)
12174 /* This must duplicate the test in adjust_reloc_syms. */
12175 change = (symsec != &bfd_und_section
12176 && symsec != &bfd_abs_section
12177 && ! bfd_is_com_section (symsec)
12180 /* A global or weak symbol is treated as external. */
12181 && (OUTPUT_FLAVOR == bfd_target_elf_flavour
12182 && ! (S_IS_EXTERN (sym) || S_IS_WEAK (sym)))
12191 /* Record the offset to the first reloc in the fr_opcode field.
12192 This lets md_convert_frag and tc_gen_reloc know that the code
12193 must be expanded. */
12194 fragp->fr_opcode = (fragp->fr_literal
12196 - RELAX_OLD (fragp->fr_subtype)
12197 + RELAX_RELOC1 (fragp->fr_subtype));
12198 /* FIXME: This really needs as_warn_where. */
12199 if (RELAX_WARN (fragp->fr_subtype))
12200 as_warn (_("AT used after \".set noat\" or macro used after "
12201 "\".set nomacro\""));
12203 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12209 /* This is called to see whether a reloc against a defined symbol
12210 should be converted into a reloc against a section. Don't adjust
12211 MIPS16 jump relocations, so we don't have to worry about the format
12212 of the offset in the .o file. Don't adjust relocations against
12213 mips16 symbols, so that the linker can find them if it needs to set
12217 mips_fix_adjustable (fixp)
12221 /* Prevent all adjustments to global symbols. */
12222 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12223 && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)))
12226 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12228 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12229 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12231 if (fixp->fx_addsy == NULL)
12234 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12235 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12236 && fixp->fx_subsy == NULL)
12242 /* Translate internal representation of relocation info to BFD target
12246 tc_gen_reloc (section, fixp)
12247 asection *section ATTRIBUTE_UNUSED;
12250 static arelent *retval[4];
12252 bfd_reloc_code_real_type code;
12254 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12257 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12258 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12259 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12261 if (mips_pic == EMBEDDED_PIC
12262 && SWITCH_TABLE (fixp))
12264 /* For a switch table entry we use a special reloc. The addend
12265 is actually the difference between the reloc address and the
12267 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12268 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12269 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12270 fixp->fx_r_type = BFD_RELOC_GPREL32;
12272 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12273 reloc->addend = fixp->fx_addnumber;
12274 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12276 /* We use a special addend for an internal RELLO reloc. */
12277 if (symbol_section_p (fixp->fx_addsy))
12278 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12280 reloc->addend = fixp->fx_addnumber + reloc->address;
12282 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12284 assert (fixp->fx_next != NULL
12285 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12286 /* We use a special addend for an internal RELHI reloc. The
12287 reloc is relative to the RELLO; adjust the addend
12289 if (symbol_section_p (fixp->fx_addsy))
12290 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12291 + fixp->fx_next->fx_where
12292 - S_GET_VALUE (fixp->fx_subsy));
12294 reloc->addend = (fixp->fx_addnumber
12295 + fixp->fx_next->fx_frag->fr_address
12296 + fixp->fx_next->fx_where);
12300 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12301 /* A gruesome hack which is a result of the gruesome gas reloc
12303 reloc->addend = reloc->address;
12305 reloc->addend = -reloc->address;
12308 /* If this is a variant frag, we may need to adjust the existing
12309 reloc and generate a new one. */
12310 if (fixp->fx_frag->fr_opcode != NULL
12311 && (fixp->fx_r_type == BFD_RELOC_GPREL16
12312 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12313 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12314 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12315 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12316 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12317 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12322 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12324 /* If this is not the last reloc in this frag, then we have two
12325 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12326 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12327 the second one handle all of them. */
12328 if (fixp->fx_next != NULL
12329 && fixp->fx_frag == fixp->fx_next->fx_frag)
12331 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12332 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12333 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12334 && (fixp->fx_next->fx_r_type
12335 == BFD_RELOC_MIPS_GOT_LO16))
12336 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12337 && (fixp->fx_next->fx_r_type
12338 == BFD_RELOC_MIPS_CALL_LO16)));
12343 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12344 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12345 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12347 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12348 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12349 reloc2->address = (reloc->address
12350 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12351 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12352 reloc2->addend = fixp->fx_addnumber;
12353 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12354 assert (reloc2->howto != NULL);
12356 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12360 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12363 reloc3->address += 4;
12366 if (mips_pic == NO_PIC)
12368 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12369 fixp->fx_r_type = BFD_RELOC_HI16_S;
12371 else if (mips_pic == SVR4_PIC)
12373 switch (fixp->fx_r_type)
12377 case BFD_RELOC_MIPS_GOT16:
12379 case BFD_RELOC_MIPS_CALL16:
12380 case BFD_RELOC_MIPS_GOT_LO16:
12381 case BFD_RELOC_MIPS_CALL_LO16:
12382 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12390 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12391 to be used in the relocation's section offset. */
12392 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12394 reloc->address = reloc->addend;
12398 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12399 fixup_segment converted a non-PC relative reloc into a PC
12400 relative reloc. In such a case, we need to convert the reloc
12402 code = fixp->fx_r_type;
12403 if (fixp->fx_pcrel)
12408 code = BFD_RELOC_8_PCREL;
12411 code = BFD_RELOC_16_PCREL;
12414 code = BFD_RELOC_32_PCREL;
12417 code = BFD_RELOC_64_PCREL;
12419 case BFD_RELOC_8_PCREL:
12420 case BFD_RELOC_16_PCREL:
12421 case BFD_RELOC_32_PCREL:
12422 case BFD_RELOC_64_PCREL:
12423 case BFD_RELOC_16_PCREL_S2:
12424 case BFD_RELOC_PCREL_HI16_S:
12425 case BFD_RELOC_PCREL_LO16:
12428 as_bad_where (fixp->fx_file, fixp->fx_line,
12429 _("Cannot make %s relocation PC relative"),
12430 bfd_get_reloc_code_name (code));
12435 /* md_apply_fix3 has a double-subtraction hack to get
12436 bfd_install_relocation to behave nicely. GPREL relocations are
12437 handled correctly without this hack, so undo it here. We can't
12438 stop md_apply_fix3 from subtracting twice in the first place since
12439 the fake addend is required for variant frags above. */
12440 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12441 && code == BFD_RELOC_GPREL16
12442 && reloc->addend != 0
12443 && mips_need_elf_addend_fixup (fixp))
12444 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12447 /* To support a PC relative reloc when generating embedded PIC code
12448 for ECOFF, we use a Cygnus extension. We check for that here to
12449 make sure that we don't let such a reloc escape normally. */
12450 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12451 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12452 && code == BFD_RELOC_16_PCREL_S2
12453 && mips_pic != EMBEDDED_PIC)
12454 reloc->howto = NULL;
12456 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12458 if (reloc->howto == NULL)
12460 as_bad_where (fixp->fx_file, fixp->fx_line,
12461 _("Can not represent %s relocation in this object file format"),
12462 bfd_get_reloc_code_name (code));
12469 /* Relax a machine dependent frag. This returns the amount by which
12470 the current size of the frag should change. */
12473 mips_relax_frag (fragp, stretch)
12477 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12480 if (mips16_extended_frag (fragp, NULL, stretch))
12482 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12484 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12489 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12491 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12498 /* Convert a machine dependent frag. */
12501 md_convert_frag (abfd, asec, fragp)
12502 bfd *abfd ATTRIBUTE_UNUSED;
12509 if (RELAX_MIPS16_P (fragp->fr_subtype))
12512 register const struct mips16_immed_operand *op;
12513 boolean small, ext;
12516 unsigned long insn;
12517 boolean use_extend;
12518 unsigned short extend;
12520 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12521 op = mips16_immed_operands;
12522 while (op->type != type)
12525 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12536 resolve_symbol_value (fragp->fr_symbol);
12537 val = S_GET_VALUE (fragp->fr_symbol);
12542 addr = fragp->fr_address + fragp->fr_fix;
12544 /* The rules for the base address of a PC relative reloc are
12545 complicated; see mips16_extended_frag. */
12546 if (type == 'p' || type == 'q')
12551 /* Ignore the low bit in the target, since it will be
12552 set for a text label. */
12553 if ((val & 1) != 0)
12556 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12558 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12561 addr &= ~ (addressT) ((1 << op->shift) - 1);
12564 /* Make sure the section winds up with the alignment we have
12567 record_alignment (asec, op->shift);
12571 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
12572 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
12573 as_warn_where (fragp->fr_file, fragp->fr_line,
12574 _("extended instruction in delay slot"));
12576 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
12578 if (target_big_endian)
12579 insn = bfd_getb16 (buf);
12581 insn = bfd_getl16 (buf);
12583 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
12584 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
12585 small, ext, &insn, &use_extend, &extend);
12589 md_number_to_chars (buf, 0xf000 | extend, 2);
12590 fragp->fr_fix += 2;
12594 md_number_to_chars (buf, insn, 2);
12595 fragp->fr_fix += 2;
12600 if (fragp->fr_opcode == NULL)
12603 old = RELAX_OLD (fragp->fr_subtype);
12604 new = RELAX_NEW (fragp->fr_subtype);
12605 fixptr = fragp->fr_literal + fragp->fr_fix;
12608 memcpy (fixptr - old, fixptr, new);
12610 fragp->fr_fix += new - old;
12616 /* This function is called after the relocs have been generated.
12617 We've been storing mips16 text labels as odd. Here we convert them
12618 back to even for the convenience of the debugger. */
12621 mips_frob_file_after_relocs ()
12624 unsigned int count, i;
12626 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
12629 syms = bfd_get_outsymbols (stdoutput);
12630 count = bfd_get_symcount (stdoutput);
12631 for (i = 0; i < count; i++, syms++)
12633 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
12634 && ((*syms)->value & 1) != 0)
12636 (*syms)->value &= ~1;
12637 /* If the symbol has an odd size, it was probably computed
12638 incorrectly, so adjust that as well. */
12639 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
12640 ++elf_symbol (*syms)->internal_elf_sym.st_size;
12647 /* This function is called whenever a label is defined. It is used
12648 when handling branch delays; if a branch has a label, we assume we
12649 can not move it. */
12652 mips_define_label (sym)
12655 struct insn_label_list *l;
12657 if (free_insn_labels == NULL)
12658 l = (struct insn_label_list *) xmalloc (sizeof *l);
12661 l = free_insn_labels;
12662 free_insn_labels = l->next;
12666 l->next = insn_labels;
12670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12672 /* Some special processing for a MIPS ELF file. */
12675 mips_elf_final_processing ()
12677 /* Write out the register information. */
12682 s.ri_gprmask = mips_gprmask;
12683 s.ri_cprmask[0] = mips_cprmask[0];
12684 s.ri_cprmask[1] = mips_cprmask[1];
12685 s.ri_cprmask[2] = mips_cprmask[2];
12686 s.ri_cprmask[3] = mips_cprmask[3];
12687 /* The gp_value field is set by the MIPS ELF backend. */
12689 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
12690 ((Elf32_External_RegInfo *)
12691 mips_regmask_frag));
12695 Elf64_Internal_RegInfo s;
12697 s.ri_gprmask = mips_gprmask;
12699 s.ri_cprmask[0] = mips_cprmask[0];
12700 s.ri_cprmask[1] = mips_cprmask[1];
12701 s.ri_cprmask[2] = mips_cprmask[2];
12702 s.ri_cprmask[3] = mips_cprmask[3];
12703 /* The gp_value field is set by the MIPS ELF backend. */
12705 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
12706 ((Elf64_External_RegInfo *)
12707 mips_regmask_frag));
12710 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12711 sort of BFD interface for this. */
12712 if (mips_any_noreorder)
12713 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
12714 if (mips_pic != NO_PIC)
12715 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
12717 /* Set the MIPS ELF ABI flags. */
12718 if (file_mips_abi == NO_ABI)
12720 else if (file_mips_abi == O32_ABI)
12721 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
12722 else if (file_mips_abi == O64_ABI)
12723 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
12724 else if (file_mips_abi == EABI_ABI)
12727 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
12729 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
12731 else if (file_mips_abi == N32_ABI)
12732 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
12734 /* Nothing to do for "64". */
12736 if (mips_32bitmode)
12737 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
12740 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12742 typedef struct proc {
12744 unsigned long reg_mask;
12745 unsigned long reg_offset;
12746 unsigned long fpreg_mask;
12747 unsigned long fpreg_offset;
12748 unsigned long frame_offset;
12749 unsigned long frame_reg;
12750 unsigned long pc_reg;
12753 static procS cur_proc;
12754 static procS *cur_proc_ptr;
12755 static int numprocs;
12757 /* Fill in an rs_align_code fragment. */
12760 mips_handle_align (fragp)
12763 if (fragp->fr_type != rs_align_code)
12766 if (mips_opts.mips16)
12768 static const unsigned char be_nop[] = { 0x65, 0x00 };
12769 static const unsigned char le_nop[] = { 0x00, 0x65 };
12774 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
12775 p = fragp->fr_literal + fragp->fr_fix;
12780 fragp->fr_fix += 1;
12783 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
12787 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12798 /* check for premature end, nesting errors, etc */
12800 as_warn (_("missing .end at end of assembly"));
12809 if (*input_line_pointer == '-')
12811 ++input_line_pointer;
12814 if (!ISDIGIT (*input_line_pointer))
12815 as_bad (_("expected simple number"));
12816 if (input_line_pointer[0] == '0')
12818 if (input_line_pointer[1] == 'x')
12820 input_line_pointer += 2;
12821 while (ISXDIGIT (*input_line_pointer))
12824 val |= hex_value (*input_line_pointer++);
12826 return negative ? -val : val;
12830 ++input_line_pointer;
12831 while (ISDIGIT (*input_line_pointer))
12834 val |= *input_line_pointer++ - '0';
12836 return negative ? -val : val;
12839 if (!ISDIGIT (*input_line_pointer))
12841 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12842 *input_line_pointer, *input_line_pointer);
12843 as_warn (_("invalid number"));
12846 while (ISDIGIT (*input_line_pointer))
12849 val += *input_line_pointer++ - '0';
12851 return negative ? -val : val;
12854 /* The .file directive; just like the usual .file directive, but there
12855 is an initial number which is the ECOFF file index. */
12859 int x ATTRIBUTE_UNUSED;
12863 line = get_number ();
12867 /* The .end directive. */
12871 int x ATTRIBUTE_UNUSED;
12876 /* Following functions need their own .frame and .cprestore directives. */
12877 mips_frame_reg_valid = 0;
12878 mips_cprestore_valid = 0;
12880 if (!is_end_of_line[(unsigned char) *input_line_pointer])
12883 demand_empty_rest_of_line ();
12888 #ifdef BFD_ASSEMBLER
12889 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
12894 if (now_seg != data_section && now_seg != bss_section)
12901 as_warn (_(".end not in text section"));
12905 as_warn (_(".end directive without a preceding .ent directive."));
12906 demand_empty_rest_of_line ();
12912 assert (S_GET_NAME (p));
12913 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
12914 as_warn (_(".end symbol does not match .ent symbol."));
12917 as_warn (_(".end directive missing or unknown symbol"));
12919 #ifdef MIPS_STABS_ELF
12921 segT saved_seg = now_seg;
12922 subsegT saved_subseg = now_subseg;
12927 dot = frag_now_fix ();
12929 #ifdef md_flush_pending_output
12930 md_flush_pending_output ();
12934 subseg_set (pdr_seg, 0);
12936 /* Write the symbol. */
12937 exp.X_op = O_symbol;
12938 exp.X_add_symbol = p;
12939 exp.X_add_number = 0;
12940 emit_expr (&exp, 4);
12942 fragp = frag_more (7 * 4);
12944 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
12945 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
12946 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
12947 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
12948 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
12949 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
12950 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
12952 subseg_set (saved_seg, saved_subseg);
12956 cur_proc_ptr = NULL;
12959 /* The .aent and .ent directives. */
12969 symbolP = get_symbol ();
12970 if (*input_line_pointer == ',')
12971 input_line_pointer++;
12972 SKIP_WHITESPACE ();
12973 if (ISDIGIT (*input_line_pointer)
12974 || *input_line_pointer == '-')
12975 number = get_number ();
12977 #ifdef BFD_ASSEMBLER
12978 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
12983 if (now_seg != data_section && now_seg != bss_section)
12990 as_warn (_(".ent or .aent not in text section."));
12992 if (!aent && cur_proc_ptr)
12993 as_warn (_("missing .end"));
12997 /* This function needs its own .frame and .cprestore directives. */
12998 mips_frame_reg_valid = 0;
12999 mips_cprestore_valid = 0;
13001 cur_proc_ptr = &cur_proc;
13002 memset (cur_proc_ptr, '\0', sizeof (procS));
13004 cur_proc_ptr->isym = symbolP;
13006 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13011 demand_empty_rest_of_line ();
13014 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13015 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13016 s_mips_frame is used so that we can set the PDR information correctly.
13017 We can't use the ecoff routines because they make reference to the ecoff
13018 symbol table (in the mdebug section). */
13021 s_mips_frame (ignore)
13022 int ignore ATTRIBUTE_UNUSED;
13024 #ifdef MIPS_STABS_ELF
13028 if (cur_proc_ptr == (procS *) NULL)
13030 as_warn (_(".frame outside of .ent"));
13031 demand_empty_rest_of_line ();
13035 cur_proc_ptr->frame_reg = tc_get_register (1);
13037 SKIP_WHITESPACE ();
13038 if (*input_line_pointer++ != ','
13039 || get_absolute_expression_and_terminator (&val) != ',')
13041 as_warn (_("Bad .frame directive"));
13042 --input_line_pointer;
13043 demand_empty_rest_of_line ();
13047 cur_proc_ptr->frame_offset = val;
13048 cur_proc_ptr->pc_reg = tc_get_register (0);
13050 demand_empty_rest_of_line ();
13053 #endif /* MIPS_STABS_ELF */
13056 /* The .fmask and .mask directives. If the mdebug section is present
13057 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13058 embedded targets, s_mips_mask is used so that we can set the PDR
13059 information correctly. We can't use the ecoff routines because they
13060 make reference to the ecoff symbol table (in the mdebug section). */
13063 s_mips_mask (reg_type)
13066 #ifdef MIPS_STABS_ELF
13069 if (cur_proc_ptr == (procS *) NULL)
13071 as_warn (_(".mask/.fmask outside of .ent"));
13072 demand_empty_rest_of_line ();
13076 if (get_absolute_expression_and_terminator (&mask) != ',')
13078 as_warn (_("Bad .mask/.fmask directive"));
13079 --input_line_pointer;
13080 demand_empty_rest_of_line ();
13084 off = get_absolute_expression ();
13086 if (reg_type == 'F')
13088 cur_proc_ptr->fpreg_mask = mask;
13089 cur_proc_ptr->fpreg_offset = off;
13093 cur_proc_ptr->reg_mask = mask;
13094 cur_proc_ptr->reg_offset = off;
13097 demand_empty_rest_of_line ();
13099 s_ignore (reg_type);
13100 #endif /* MIPS_STABS_ELF */
13103 /* The .loc directive. */
13114 assert (now_seg == text_section);
13116 lineno = get_number ();
13117 addroff = frag_now_fix ();
13119 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13120 S_SET_TYPE (symbolP, N_SLINE);
13121 S_SET_OTHER (symbolP, 0);
13122 S_SET_DESC (symbolP, lineno);
13123 symbolP->sy_segment = now_seg;
13127 /* CPU name/ISA/number mapping table.
13129 Entries are grouped by type. The first matching CPU or ISA entry
13130 gets chosen by CPU or ISA, so it should be the 'canonical' name
13131 for that type. Entries after that within the type are sorted
13134 Case is ignored in comparison, so put the canonical entry in the
13135 appropriate case but everything else in lower case to ease eye pain. */
13136 static const struct mips_cpu_info mips_cpu_info_table[] =
13139 { "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
13140 { "mips", 1, ISA_MIPS1, CPU_R3000, },
13143 { "MIPS2", 1, ISA_MIPS2, CPU_R6000, },
13146 { "MIPS3", 1, ISA_MIPS3, CPU_R4000, },
13149 { "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
13152 { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
13153 { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
13156 { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
13157 { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, },
13158 { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
13159 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13160 { "4km", 0, ISA_MIPS32, CPU_MIPS32, },
13161 { "4kp", 0, ISA_MIPS32, CPU_MIPS32, },
13163 /* For historical reasons. */
13164 { "MIPS64", 1, ISA_MIPS3, CPU_R4000, },
13167 { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, },
13168 { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
13169 { "5kc", 0, ISA_MIPS64, CPU_MIPS64, },
13170 { "20kc", 0, ISA_MIPS64, CPU_MIPS64, },
13173 { "R2000", 0, ISA_MIPS1, CPU_R2000, },
13174 { "2000", 0, ISA_MIPS1, CPU_R2000, },
13175 { "2k", 0, ISA_MIPS1, CPU_R2000, },
13176 { "r2k", 0, ISA_MIPS1, CPU_R2000, },
13179 { "R3000", 0, ISA_MIPS1, CPU_R3000, },
13180 { "3000", 0, ISA_MIPS1, CPU_R3000, },
13181 { "3k", 0, ISA_MIPS1, CPU_R3000, },
13182 { "r3k", 0, ISA_MIPS1, CPU_R3000, },
13185 { "R3900", 0, ISA_MIPS1, CPU_R3900, },
13186 { "3900", 0, ISA_MIPS1, CPU_R3900, },
13187 { "mipstx39", 0, ISA_MIPS1, CPU_R3900, },
13190 { "R4000", 0, ISA_MIPS3, CPU_R4000, },
13191 { "4000", 0, ISA_MIPS3, CPU_R4000, },
13192 { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */
13193 { "r4k", 0, ISA_MIPS3, CPU_R4000, },
13196 { "R4010", 0, ISA_MIPS2, CPU_R4010, },
13197 { "4010", 0, ISA_MIPS2, CPU_R4010, },
13200 { "R4400", 0, ISA_MIPS3, CPU_R4400, },
13201 { "4400", 0, ISA_MIPS3, CPU_R4400, },
13204 { "R4600", 0, ISA_MIPS3, CPU_R4600, },
13205 { "4600", 0, ISA_MIPS3, CPU_R4600, },
13206 { "mips64orion", 0, ISA_MIPS3, CPU_R4600, },
13207 { "orion", 0, ISA_MIPS3, CPU_R4600, },
13210 { "R4650", 0, ISA_MIPS3, CPU_R4650, },
13211 { "4650", 0, ISA_MIPS3, CPU_R4650, },
13214 { "R6000", 0, ISA_MIPS2, CPU_R6000, },
13215 { "6000", 0, ISA_MIPS2, CPU_R6000, },
13216 { "6k", 0, ISA_MIPS2, CPU_R6000, },
13217 { "r6k", 0, ISA_MIPS2, CPU_R6000, },
13220 { "R8000", 0, ISA_MIPS4, CPU_R8000, },
13221 { "8000", 0, ISA_MIPS4, CPU_R8000, },
13222 { "8k", 0, ISA_MIPS4, CPU_R8000, },
13223 { "r8k", 0, ISA_MIPS4, CPU_R8000, },
13226 { "R10000", 0, ISA_MIPS4, CPU_R10000, },
13227 { "10000", 0, ISA_MIPS4, CPU_R10000, },
13228 { "10k", 0, ISA_MIPS4, CPU_R10000, },
13229 { "r10k", 0, ISA_MIPS4, CPU_R10000, },
13232 { "R12000", 0, ISA_MIPS4, CPU_R12000, },
13233 { "12000", 0, ISA_MIPS4, CPU_R12000, },
13234 { "12k", 0, ISA_MIPS4, CPU_R12000, },
13235 { "r12k", 0, ISA_MIPS4, CPU_R12000, },
13238 { "VR4100", 0, ISA_MIPS3, CPU_VR4100, },
13239 { "4100", 0, ISA_MIPS3, CPU_VR4100, },
13240 { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, },
13241 { "r4100", 0, ISA_MIPS3, CPU_VR4100, },
13244 { "VR4111", 0, ISA_MIPS3, CPU_R4111, },
13245 { "4111", 0, ISA_MIPS3, CPU_R4111, },
13246 { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, },
13247 { "r4111", 0, ISA_MIPS3, CPU_R4111, },
13250 { "VR4300", 0, ISA_MIPS3, CPU_R4300, },
13251 { "4300", 0, ISA_MIPS3, CPU_R4300, },
13252 { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, },
13253 { "r4300", 0, ISA_MIPS3, CPU_R4300, },
13256 { "VR5000", 0, ISA_MIPS4, CPU_R5000, },
13257 { "5000", 0, ISA_MIPS4, CPU_R5000, },
13258 { "5k", 0, ISA_MIPS4, CPU_R5000, },
13259 { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, },
13260 { "r5000", 0, ISA_MIPS4, CPU_R5000, },
13261 { "r5200", 0, ISA_MIPS4, CPU_R5000, },
13262 { "rm5200", 0, ISA_MIPS4, CPU_R5000, },
13263 { "r5230", 0, ISA_MIPS4, CPU_R5000, },
13264 { "rm5230", 0, ISA_MIPS4, CPU_R5000, },
13265 { "r5231", 0, ISA_MIPS4, CPU_R5000, },
13266 { "rm5231", 0, ISA_MIPS4, CPU_R5000, },
13267 { "r5261", 0, ISA_MIPS4, CPU_R5000, },
13268 { "rm5261", 0, ISA_MIPS4, CPU_R5000, },
13269 { "r5721", 0, ISA_MIPS4, CPU_R5000, },
13270 { "rm5721", 0, ISA_MIPS4, CPU_R5000, },
13271 { "r5k", 0, ISA_MIPS4, CPU_R5000, },
13272 { "r7000", 0, ISA_MIPS4, CPU_R5000, },
13274 /* Broadcom SB-1 CPU */
13275 { "SB-1", 0, ISA_MIPS64, CPU_SB1, },
13276 { "sb-1250", 0, ISA_MIPS64, CPU_SB1, },
13277 { "sb1", 0, ISA_MIPS64, CPU_SB1, },
13278 { "sb1250", 0, ISA_MIPS64, CPU_SB1, },
13281 { NULL, 0, 0, 0, },
13284 static const struct mips_cpu_info *
13285 mips_cpu_info_from_name (name)
13290 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13291 if (strcasecmp (name, mips_cpu_info_table[i].name) == 0)
13292 return (&mips_cpu_info_table[i]);
13297 static const struct mips_cpu_info *
13298 mips_cpu_info_from_isa (isa)
13303 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13304 if (mips_cpu_info_table[i].is_isa
13305 && isa == mips_cpu_info_table[i].isa)
13306 return (&mips_cpu_info_table[i]);
13311 static const struct mips_cpu_info *
13312 mips_cpu_info_from_cpu (cpu)
13317 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13318 if (!mips_cpu_info_table[i].is_isa
13319 && cpu == mips_cpu_info_table[i].cpu)
13320 return (&mips_cpu_info_table[i]);