1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode *insn_mo;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p : 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p : 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p : 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p : 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p : 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi = NO_ABI;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls = FALSE;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared = TRUE;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32 = -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32 = -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float = 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float = 0;
275 /* True if -mnan=2008, false if -mnan=legacy. */
276 static bfd_boolean mips_flag_nan2008 = FALSE;
278 static struct mips_set_options mips_opts =
280 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
281 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
282 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
283 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
284 /* soft_float */ FALSE, /* single_float */ FALSE
287 /* The set of ASEs that were selected on the command line, either
288 explicitly via ASE options or implicitly through things like -march. */
289 static unsigned int file_ase;
291 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
292 static unsigned int file_ase_explicit;
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask;
298 unsigned long mips_cprmask[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa = ISA_UNKNOWN;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if any microMIPS code was produced. */
312 static int file_ase_micromips;
314 /* True if we want to create R_MIPS_JALR for jalr $25. */
316 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
318 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
319 because there's no place for any addend, the only acceptable
320 expression is a bare symbol. */
321 #define MIPS_JALR_HINT_P(EXPR) \
322 (!HAVE_IN_PLACE_ADDENDS \
323 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
326 /* The argument of the -march= flag. The architecture we are assembling. */
327 static int file_mips_arch = CPU_UNKNOWN;
328 static const char *mips_arch_string;
330 /* The argument of the -mtune= flag. The architecture for which we
332 static int mips_tune = CPU_UNKNOWN;
333 static const char *mips_tune_string;
335 /* True when generating 32-bit code for a 64-bit processor. */
336 static int mips_32bitmode = 0;
338 /* True if the given ABI requires 32-bit registers. */
339 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
341 /* Likewise 64-bit registers. */
342 #define ABI_NEEDS_64BIT_REGS(ABI) \
344 || (ABI) == N64_ABI \
347 /* Return true if ISA supports 64 bit wide gp registers. */
348 #define ISA_HAS_64BIT_REGS(ISA) \
349 ((ISA) == ISA_MIPS3 \
350 || (ISA) == ISA_MIPS4 \
351 || (ISA) == ISA_MIPS5 \
352 || (ISA) == ISA_MIPS64 \
353 || (ISA) == ISA_MIPS64R2)
355 /* Return true if ISA supports 64 bit wide float registers. */
356 #define ISA_HAS_64BIT_FPRS(ISA) \
357 ((ISA) == ISA_MIPS3 \
358 || (ISA) == ISA_MIPS4 \
359 || (ISA) == ISA_MIPS5 \
360 || (ISA) == ISA_MIPS32R2 \
361 || (ISA) == ISA_MIPS64 \
362 || (ISA) == ISA_MIPS64R2)
364 /* Return true if ISA supports 64-bit right rotate (dror et al.)
366 #define ISA_HAS_DROR(ISA) \
367 ((ISA) == ISA_MIPS64R2 \
368 || (mips_opts.micromips \
369 && ISA_HAS_64BIT_REGS (ISA)) \
372 /* Return true if ISA supports 32-bit right rotate (ror et al.)
374 #define ISA_HAS_ROR(ISA) \
375 ((ISA) == ISA_MIPS32R2 \
376 || (ISA) == ISA_MIPS64R2 \
377 || (mips_opts.ase & ASE_SMARTMIPS) \
378 || mips_opts.micromips \
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* Return true if the given CPU supports the microMIPS ASE. */
442 #define CPU_HAS_MICROMIPS(cpu) 0
444 /* True if CPU has a dror instruction. */
445 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
447 /* True if CPU has a ror instruction. */
448 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
450 /* True if CPU is in the Octeon family */
451 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
453 /* True if CPU has seq/sne and seqi/snei instructions. */
454 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
456 /* True, if CPU has support for ldc1 and sdc1. */
457 #define CPU_HAS_LDC1_SDC1(CPU) \
458 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
460 /* True if mflo and mfhi can be immediately followed by instructions
461 which write to the HI and LO registers.
463 According to MIPS specifications, MIPS ISAs I, II, and III need
464 (at least) two instructions between the reads of HI/LO and
465 instructions which write them, and later ISAs do not. Contradicting
466 the MIPS specifications, some MIPS IV processor user manuals (e.g.
467 the UM for the NEC Vr5000) document needing the instructions between
468 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
469 MIPS64 and later ISAs to have the interlocks, plus any specific
470 earlier-ISA CPUs for which CPU documentation declares that the
471 instructions are really interlocked. */
472 #define hilo_interlocks \
473 (mips_opts.isa == ISA_MIPS32 \
474 || mips_opts.isa == ISA_MIPS32R2 \
475 || mips_opts.isa == ISA_MIPS64 \
476 || mips_opts.isa == ISA_MIPS64R2 \
477 || mips_opts.arch == CPU_R4010 \
478 || mips_opts.arch == CPU_R5900 \
479 || mips_opts.arch == CPU_R10000 \
480 || mips_opts.arch == CPU_R12000 \
481 || mips_opts.arch == CPU_R14000 \
482 || mips_opts.arch == CPU_R16000 \
483 || mips_opts.arch == CPU_RM7000 \
484 || mips_opts.arch == CPU_VR5500 \
485 || mips_opts.micromips \
488 /* Whether the processor uses hardware interlocks to protect reads
489 from the GPRs after they are loaded from memory, and thus does not
490 require nops to be inserted. This applies to instructions marked
491 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
492 level I and microMIPS mode instructions are always interlocked. */
493 #define gpr_interlocks \
494 (mips_opts.isa != ISA_MIPS1 \
495 || mips_opts.arch == CPU_R3900 \
496 || mips_opts.arch == CPU_R5900 \
497 || mips_opts.micromips \
500 /* Whether the processor uses hardware interlocks to avoid delays
501 required by coprocessor instructions, and thus does not require
502 nops to be inserted. This applies to instructions marked
503 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
504 between instructions marked INSN_WRITE_COND_CODE and ones marked
505 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
506 levels I, II, and III and microMIPS mode instructions are always
508 /* Itbl support may require additional care here. */
509 #define cop_interlocks \
510 ((mips_opts.isa != ISA_MIPS1 \
511 && mips_opts.isa != ISA_MIPS2 \
512 && mips_opts.isa != ISA_MIPS3) \
513 || mips_opts.arch == CPU_R4300 \
514 || mips_opts.micromips \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I and microMIPS mode instructions are
522 always interlocked. */
523 #define cop_mem_interlocks \
524 (mips_opts.isa != ISA_MIPS1 \
525 || mips_opts.micromips \
528 /* Is this a mfhi or mflo instruction? */
529 #define MF_HILO_INSN(PINFO) \
530 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
532 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
533 has been selected. This implies, in particular, that addresses of text
534 labels have their LSB set. */
535 #define HAVE_CODE_COMPRESSION \
536 ((mips_opts.mips16 | mips_opts.micromips) != 0)
538 /* The minimum and maximum signed values that can be stored in a GPR. */
539 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
540 #define GPR_SMIN (-GPR_SMAX - 1)
542 /* MIPS PIC level. */
544 enum mips_pic_level mips_pic;
546 /* 1 if we should generate 32 bit offsets from the $gp register in
547 SVR4_PIC mode. Currently has no meaning in other modes. */
548 static int mips_big_got = 0;
550 /* 1 if trap instructions should used for overflow rather than break
552 static int mips_trap = 0;
554 /* 1 if double width floating point constants should not be constructed
555 by assembling two single width halves into two single width floating
556 point registers which just happen to alias the double width destination
557 register. On some architectures this aliasing can be disabled by a bit
558 in the status register, and the setting of this bit cannot be determined
559 automatically at assemble time. */
560 static int mips_disable_float_construction;
562 /* Non-zero if any .set noreorder directives were used. */
564 static int mips_any_noreorder;
566 /* Non-zero if nops should be inserted when the register referenced in
567 an mfhi/mflo instruction is read in the next two instructions. */
568 static int mips_7000_hilo_fix;
570 /* The size of objects in the small data section. */
571 static unsigned int g_switch_value = 8;
572 /* Whether the -G option was used. */
573 static int g_switch_seen = 0;
578 /* If we can determine in advance that GP optimization won't be
579 possible, we can skip the relaxation stuff that tries to produce
580 GP-relative references. This makes delay slot optimization work
583 This function can only provide a guess, but it seems to work for
584 gcc output. It needs to guess right for gcc, otherwise gcc
585 will put what it thinks is a GP-relative instruction in a branch
588 I don't know if a fix is needed for the SVR4_PIC mode. I've only
589 fixed it for the non-PIC mode. KR 95/04/07 */
590 static int nopic_need_relax (symbolS *, int);
592 /* handle of the OPCODE hash table */
593 static struct hash_control *op_hash = NULL;
595 /* The opcode hash table we use for the mips16. */
596 static struct hash_control *mips16_op_hash = NULL;
598 /* The opcode hash table we use for the microMIPS ASE. */
599 static struct hash_control *micromips_op_hash = NULL;
601 /* This array holds the chars that always start a comment. If the
602 pre-processor is disabled, these aren't very useful */
603 const char comment_chars[] = "#";
605 /* This array holds the chars that only start a comment at the beginning of
606 a line. If the line seems to have the form '# 123 filename'
607 .line and .file directives will appear in the pre-processed output */
608 /* Note that input_file.c hand checks for '#' at the beginning of the
609 first line of the input file. This is because the compiler outputs
610 #NO_APP at the beginning of its output. */
611 /* Also note that C style comments are always supported. */
612 const char line_comment_chars[] = "#";
614 /* This array holds machine specific line separator characters. */
615 const char line_separator_chars[] = ";";
617 /* Chars that can be used to separate mant from exp in floating point nums */
618 const char EXP_CHARS[] = "eE";
620 /* Chars that mean this number is a floating point constant */
623 const char FLT_CHARS[] = "rRsSfFdDxXpP";
625 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
626 changed in read.c . Ideally it shouldn't have to know about it at all,
627 but nothing is ideal around here.
630 static char *insn_error;
632 static int auto_align = 1;
634 /* When outputting SVR4 PIC code, the assembler needs to know the
635 offset in the stack frame from which to restore the $gp register.
636 This is set by the .cprestore pseudo-op, and saved in this
638 static offsetT mips_cprestore_offset = -1;
640 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
641 more optimizations, it can use a register value instead of a memory-saved
642 offset and even an other register than $gp as global pointer. */
643 static offsetT mips_cpreturn_offset = -1;
644 static int mips_cpreturn_register = -1;
645 static int mips_gp_register = GP;
646 static int mips_gprel_offset = 0;
648 /* Whether mips_cprestore_offset has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_cprestore_valid = 0;
652 /* This is the register which holds the stack frame, as set by the
653 .frame pseudo-op. This is needed to implement .cprestore. */
654 static int mips_frame_reg = SP;
656 /* Whether mips_frame_reg has been set in the current function
657 (or whether it has already been warned about, if not). */
658 static int mips_frame_reg_valid = 0;
660 /* To output NOP instructions correctly, we need to keep information
661 about the previous two instructions. */
663 /* Whether we are optimizing. The default value of 2 means to remove
664 unneeded NOPs and swap branch instructions when possible. A value
665 of 1 means to not swap branches. A value of 0 means to always
667 static int mips_optimize = 2;
669 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
670 equivalent to seeing no -g option at all. */
671 static int mips_debug = 0;
673 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
674 #define MAX_VR4130_NOPS 4
676 /* The maximum number of NOPs needed to fill delay slots. */
677 #define MAX_DELAY_NOPS 2
679 /* The maximum number of NOPs needed for any purpose. */
682 /* A list of previous instructions, with index 0 being the most recent.
683 We need to look back MAX_NOPS instructions when filling delay slots
684 or working around processor errata. We need to look back one
685 instruction further if we're thinking about using history[0] to
686 fill a branch delay slot. */
687 static struct mips_cl_insn history[1 + MAX_NOPS];
689 /* Nop instructions used by emit_nop. */
690 static struct mips_cl_insn nop_insn;
691 static struct mips_cl_insn mips16_nop_insn;
692 static struct mips_cl_insn micromips_nop16_insn;
693 static struct mips_cl_insn micromips_nop32_insn;
695 /* The appropriate nop for the current mode. */
696 #define NOP_INSN (mips_opts.mips16 \
698 : (mips_opts.micromips \
699 ? (mips_opts.insn32 \
700 ? µmips_nop32_insn \
701 : µmips_nop16_insn) \
704 /* The size of NOP_INSN in bytes. */
705 #define NOP_INSN_SIZE ((mips_opts.mips16 \
706 || (mips_opts.micromips && !mips_opts.insn32)) \
709 /* If this is set, it points to a frag holding nop instructions which
710 were inserted before the start of a noreorder section. If those
711 nops turn out to be unnecessary, the size of the frag can be
713 static fragS *prev_nop_frag;
715 /* The number of nop instructions we created in prev_nop_frag. */
716 static int prev_nop_frag_holds;
718 /* The number of nop instructions that we know we need in
720 static int prev_nop_frag_required;
722 /* The number of instructions we've seen since prev_nop_frag. */
723 static int prev_nop_frag_since;
725 /* Relocations against symbols are sometimes done in two parts, with a HI
726 relocation and a LO relocation. Each relocation has only 16 bits of
727 space to store an addend. This means that in order for the linker to
728 handle carries correctly, it must be able to locate both the HI and
729 the LO relocation. This means that the relocations must appear in
730 order in the relocation table.
732 In order to implement this, we keep track of each unmatched HI
733 relocation. We then sort them so that they immediately precede the
734 corresponding LO relocation. */
739 struct mips_hi_fixup *next;
742 /* The section this fixup is in. */
746 /* The list of unmatched HI relocs. */
748 static struct mips_hi_fixup *mips_hi_fixup_list;
750 /* The frag containing the last explicit relocation operator.
751 Null if explicit relocations have not been used. */
753 static fragS *prev_reloc_op_frag;
755 /* Map normal MIPS register numbers to mips16 register numbers. */
757 #define X ILLEGAL_REG
758 static const int mips32_to_16_reg_map[] =
760 X, X, 2, 3, 4, 5, 6, 7,
761 X, X, X, X, X, X, X, X,
762 0, 1, X, X, X, X, X, X,
763 X, X, X, X, X, X, X, X
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map normal MIPS register numbers to microMIPS register numbers. */
776 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
780 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
781 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
782 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
784 #define X ILLEGAL_REG
785 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
786 static const int mips32_to_micromips_reg_m_map[] =
788 0, X, 2, 3, X, X, X, X,
789 X, X, X, X, X, X, X, X,
790 4, 1, 5, 6, 7, X, X, X,
791 X, X, X, X, X, X, X, X
794 /* reg type q: 0, 2-7. 17. */
795 static const int mips32_to_micromips_reg_q_map[] =
797 0, X, 2, 3, 4, 5, 6, 7,
798 X, X, X, X, X, X, X, X,
799 X, 1, X, X, X, X, X, X,
800 X, X, X, X, X, X, X, X
803 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
806 /* Map microMIPS register numbers to normal MIPS register numbers. */
808 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
809 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
810 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
811 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
812 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
813 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
815 /* The microMIPS registers with type h. */
816 static const unsigned int micromips_to_32_reg_h_map1[] =
818 5, 5, 6, 4, 4, 4, 4, 4
820 static const unsigned int micromips_to_32_reg_h_map2[] =
822 6, 7, 7, 21, 22, 5, 6, 7
825 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
827 /* The microMIPS registers with type m. */
828 static const unsigned int micromips_to_32_reg_m_map[] =
830 0, 17, 2, 3, 16, 18, 19, 20
833 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
835 /* The microMIPS registers with type q. */
836 static const unsigned int micromips_to_32_reg_q_map[] =
838 0, 17, 2, 3, 4, 5, 6, 7
841 /* microMIPS imm type B. */
842 static const int micromips_imm_b_map[] =
844 1, 4, 8, 12, 16, 20, 24, -1
847 /* microMIPS imm type C. */
848 static const int micromips_imm_c_map[] =
850 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
853 /* Classifies the kind of instructions we're interested in when
854 implementing -mfix-vr4120. */
855 enum fix_vr4120_class
863 NUM_FIX_VR4120_CLASSES
866 /* ...likewise -mfix-loongson2f-jump. */
867 static bfd_boolean mips_fix_loongson2f_jump;
869 /* ...likewise -mfix-loongson2f-nop. */
870 static bfd_boolean mips_fix_loongson2f_nop;
872 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
873 static bfd_boolean mips_fix_loongson2f;
875 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
876 there must be at least one other instruction between an instruction
877 of type X and an instruction of type Y. */
878 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
880 /* True if -mfix-vr4120 is in force. */
881 static int mips_fix_vr4120;
883 /* ...likewise -mfix-vr4130. */
884 static int mips_fix_vr4130;
886 /* ...likewise -mfix-24k. */
887 static int mips_fix_24k;
889 /* ...likewise -mfix-cn63xxp1 */
890 static bfd_boolean mips_fix_cn63xxp1;
892 /* We don't relax branches by default, since this causes us to expand
893 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
894 fail to compute the offset before expanding the macro to the most
895 efficient expansion. */
897 static int mips_relax_branch;
899 /* The expansion of many macros depends on the type of symbol that
900 they refer to. For example, when generating position-dependent code,
901 a macro that refers to a symbol may have two different expansions,
902 one which uses GP-relative addresses and one which uses absolute
903 addresses. When generating SVR4-style PIC, a macro may have
904 different expansions for local and global symbols.
906 We handle these situations by generating both sequences and putting
907 them in variant frags. In position-dependent code, the first sequence
908 will be the GP-relative one and the second sequence will be the
909 absolute one. In SVR4 PIC, the first sequence will be for global
910 symbols and the second will be for local symbols.
912 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
913 SECOND are the lengths of the two sequences in bytes. These fields
914 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
915 the subtype has the following flags:
918 Set if it has been decided that we should use the second
919 sequence instead of the first.
922 Set in the first variant frag if the macro's second implementation
923 is longer than its first. This refers to the macro as a whole,
924 not an individual relaxation.
927 Set in the first variant frag if the macro appeared in a .set nomacro
928 block and if one alternative requires a warning but the other does not.
931 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
934 RELAX_DELAY_SLOT_16BIT
935 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
938 RELAX_DELAY_SLOT_SIZE_FIRST
939 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
940 the macro is of the wrong size for the branch delay slot.
942 RELAX_DELAY_SLOT_SIZE_SECOND
943 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
944 the macro is of the wrong size for the branch delay slot.
946 The frag's "opcode" points to the first fixup for relaxable code.
948 Relaxable macros are generated using a sequence such as:
950 relax_start (SYMBOL);
951 ... generate first expansion ...
953 ... generate second expansion ...
956 The code and fixups for the unwanted alternative are discarded
957 by md_convert_frag. */
958 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
960 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
961 #define RELAX_SECOND(X) ((X) & 0xff)
962 #define RELAX_USE_SECOND 0x10000
963 #define RELAX_SECOND_LONGER 0x20000
964 #define RELAX_NOMACRO 0x40000
965 #define RELAX_DELAY_SLOT 0x80000
966 #define RELAX_DELAY_SLOT_16BIT 0x100000
967 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
968 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
970 /* Branch without likely bit. If label is out of range, we turn:
972 beq reg1, reg2, label
982 with the following opcode replacements:
989 bltzal <-> bgezal (with jal label instead of j label)
991 Even though keeping the delay slot instruction in the delay slot of
992 the branch would be more efficient, it would be very tricky to do
993 correctly, because we'd have to introduce a variable frag *after*
994 the delay slot instruction, and expand that instead. Let's do it
995 the easy way for now, even if the branch-not-taken case now costs
996 one additional instruction. Out-of-range branches are not supposed
997 to be common, anyway.
999 Branch likely. If label is out of range, we turn:
1001 beql reg1, reg2, label
1002 delay slot (annulled if branch not taken)
1011 delay slot (executed only if branch taken)
1014 It would be possible to generate a shorter sequence by losing the
1015 likely bit, generating something like:
1020 delay slot (executed only if branch taken)
1032 bltzall -> bgezal (with jal label instead of j label)
1033 bgezall -> bltzal (ditto)
1036 but it's not clear that it would actually improve performance. */
1037 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1038 ((relax_substateT) \
1041 | ((toofar) ? 0x20 : 0) \
1042 | ((link) ? 0x40 : 0) \
1043 | ((likely) ? 0x80 : 0) \
1044 | ((uncond) ? 0x100 : 0)))
1045 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1046 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1047 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1048 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1049 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1050 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1052 /* For mips16 code, we use an entirely different form of relaxation.
1053 mips16 supports two versions of most instructions which take
1054 immediate values: a small one which takes some small value, and a
1055 larger one which takes a 16 bit value. Since branches also follow
1056 this pattern, relaxing these values is required.
1058 We can assemble both mips16 and normal MIPS code in a single
1059 object. Therefore, we need to support this type of relaxation at
1060 the same time that we support the relaxation described above. We
1061 use the high bit of the subtype field to distinguish these cases.
1063 The information we store for this type of relaxation is the
1064 argument code found in the opcode file for this relocation, whether
1065 the user explicitly requested a small or extended form, and whether
1066 the relocation is in a jump or jal delay slot. That tells us the
1067 size of the value, and how it should be stored. We also store
1068 whether the fragment is considered to be extended or not. We also
1069 store whether this is known to be a branch to a different section,
1070 whether we have tried to relax this frag yet, and whether we have
1071 ever extended a PC relative fragment because of a shift count. */
1072 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1075 | ((small) ? 0x100 : 0) \
1076 | ((ext) ? 0x200 : 0) \
1077 | ((dslot) ? 0x400 : 0) \
1078 | ((jal_dslot) ? 0x800 : 0))
1079 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1080 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1081 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1082 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1083 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1084 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1085 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1086 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1087 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1088 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1089 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1090 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1092 /* For microMIPS code, we use relaxation similar to one we use for
1093 MIPS16 code. Some instructions that take immediate values support
1094 two encodings: a small one which takes some small value, and a
1095 larger one which takes a 16 bit value. As some branches also follow
1096 this pattern, relaxing these values is required.
1098 We can assemble both microMIPS and normal MIPS code in a single
1099 object. Therefore, we need to support this type of relaxation at
1100 the same time that we support the relaxation described above. We
1101 use one of the high bits of the subtype field to distinguish these
1104 The information we store for this type of relaxation is the argument
1105 code found in the opcode file for this relocation, the register
1106 selected as the assembler temporary, whether the branch is
1107 unconditional, whether it is compact, whether it stores the link
1108 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1109 branches to a sequence of instructions is enabled, and whether the
1110 displacement of a branch is too large to fit as an immediate argument
1111 of a 16-bit and a 32-bit branch, respectively. */
1112 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1113 relax32, toofar16, toofar32) \
1116 | (((at) & 0x1f) << 8) \
1117 | ((uncond) ? 0x2000 : 0) \
1118 | ((compact) ? 0x4000 : 0) \
1119 | ((link) ? 0x8000 : 0) \
1120 | ((relax32) ? 0x10000 : 0) \
1121 | ((toofar16) ? 0x20000 : 0) \
1122 | ((toofar32) ? 0x40000 : 0))
1123 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1124 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1125 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1126 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1127 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1128 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1129 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1131 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1134 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1135 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1136 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1138 /* Sign-extend 16-bit value X. */
1139 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1141 /* Is the given value a sign-extended 32-bit value? */
1142 #define IS_SEXT_32BIT_NUM(x) \
1143 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1144 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1146 /* Is the given value a sign-extended 16-bit value? */
1147 #define IS_SEXT_16BIT_NUM(x) \
1148 (((x) &~ (offsetT) 0x7fff) == 0 \
1149 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1151 /* Is the given value a sign-extended 12-bit value? */
1152 #define IS_SEXT_12BIT_NUM(x) \
1153 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1155 /* Is the given value a sign-extended 9-bit value? */
1156 #define IS_SEXT_9BIT_NUM(x) \
1157 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1159 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1160 #define IS_ZEXT_32BIT_NUM(x) \
1161 (((x) &~ (offsetT) 0xffffffff) == 0 \
1162 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1164 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1165 VALUE << SHIFT. VALUE is evaluated exactly once. */
1166 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1167 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1168 | (((VALUE) & (MASK)) << (SHIFT)))
1170 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1172 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1173 (((STRUCT) >> (SHIFT)) & (MASK))
1175 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1176 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1178 include/opcode/mips.h specifies operand fields using the macros
1179 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1180 with "MIPS16OP" instead of "OP". */
1181 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 OP_MASK_##FIELD, OP_SH_##FIELD); \
1187 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1188 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1190 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1191 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1192 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1194 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1195 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1197 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1198 : EXTRACT_BITS ((INSN).insn_opcode, \
1199 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1200 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1201 EXTRACT_BITS ((INSN).insn_opcode, \
1202 MIPS16OP_MASK_##FIELD, \
1203 MIPS16OP_SH_##FIELD)
1205 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1206 #define MIPS16_EXTEND (0xf000U << 16)
1208 /* Whether or not we are emitting a branch-likely macro. */
1209 static bfd_boolean emit_branch_likely_macro = FALSE;
1211 /* Global variables used when generating relaxable macros. See the
1212 comment above RELAX_ENCODE for more details about how relaxation
1215 /* 0 if we're not emitting a relaxable macro.
1216 1 if we're emitting the first of the two relaxation alternatives.
1217 2 if we're emitting the second alternative. */
1220 /* The first relaxable fixup in the current frag. (In other words,
1221 the first fixup that refers to relaxable code.) */
1224 /* sizes[0] says how many bytes of the first alternative are stored in
1225 the current frag. Likewise sizes[1] for the second alternative. */
1226 unsigned int sizes[2];
1228 /* The symbol on which the choice of sequence depends. */
1232 /* Global variables used to decide whether a macro needs a warning. */
1234 /* True if the macro is in a branch delay slot. */
1235 bfd_boolean delay_slot_p;
1237 /* Set to the length in bytes required if the macro is in a delay slot
1238 that requires a specific length of instruction, otherwise zero. */
1239 unsigned int delay_slot_length;
1241 /* For relaxable macros, sizes[0] is the length of the first alternative
1242 in bytes and sizes[1] is the length of the second alternative.
1243 For non-relaxable macros, both elements give the length of the
1245 unsigned int sizes[2];
1247 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1248 instruction of the first alternative in bytes and first_insn_sizes[1]
1249 is the length of the first instruction of the second alternative.
1250 For non-relaxable macros, both elements give the length of the first
1251 instruction in bytes.
1253 Set to zero if we haven't yet seen the first instruction. */
1254 unsigned int first_insn_sizes[2];
1256 /* For relaxable macros, insns[0] is the number of instructions for the
1257 first alternative and insns[1] is the number of instructions for the
1260 For non-relaxable macros, both elements give the number of
1261 instructions for the macro. */
1262 unsigned int insns[2];
1264 /* The first variant frag for this macro. */
1266 } mips_macro_warning;
1268 /* Prototypes for static functions. */
1270 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1272 static void append_insn
1273 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1274 bfd_boolean expansionp);
1275 static void mips_no_prev_insn (void);
1276 static void macro_build (expressionS *, const char *, const char *, ...);
1277 static void mips16_macro_build
1278 (expressionS *, const char *, const char *, va_list *);
1279 static void load_register (int, expressionS *, int);
1280 static void macro_start (void);
1281 static void macro_end (void);
1282 static void macro (struct mips_cl_insn *ip, char *str);
1283 static void mips16_macro (struct mips_cl_insn * ip);
1284 static void mips_ip (char *str, struct mips_cl_insn * ip);
1285 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1286 static void mips16_immed
1287 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1288 unsigned int, unsigned long *);
1289 static size_t my_getSmallExpression
1290 (expressionS *, bfd_reloc_code_real_type *, char *);
1291 static void my_getExpression (expressionS *, char *);
1292 static void s_align (int);
1293 static void s_change_sec (int);
1294 static void s_change_section (int);
1295 static void s_cons (int);
1296 static void s_float_cons (int);
1297 static void s_mips_globl (int);
1298 static void s_option (int);
1299 static void s_mipsset (int);
1300 static void s_abicalls (int);
1301 static void s_cpload (int);
1302 static void s_cpsetup (int);
1303 static void s_cplocal (int);
1304 static void s_cprestore (int);
1305 static void s_cpreturn (int);
1306 static void s_dtprelword (int);
1307 static void s_dtpreldword (int);
1308 static void s_tprelword (int);
1309 static void s_tpreldword (int);
1310 static void s_gpvalue (int);
1311 static void s_gpword (int);
1312 static void s_gpdword (int);
1313 static void s_ehword (int);
1314 static void s_cpadd (int);
1315 static void s_insn (int);
1316 static void s_nan (int);
1317 static void md_obj_begin (void);
1318 static void md_obj_end (void);
1319 static void s_mips_ent (int);
1320 static void s_mips_end (int);
1321 static void s_mips_frame (int);
1322 static void s_mips_mask (int reg_type);
1323 static void s_mips_stab (int);
1324 static void s_mips_weakext (int);
1325 static void s_mips_file (int);
1326 static void s_mips_loc (int);
1327 static bfd_boolean pic_need_relax (symbolS *, asection *);
1328 static int relaxed_branch_length (fragS *, asection *, int);
1329 static int validate_mips_insn (const struct mips_opcode *);
1330 static int validate_micromips_insn (const struct mips_opcode *);
1331 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1332 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1334 /* Table and functions used to map between CPU/ISA names, and
1335 ISA levels, and CPU numbers. */
1337 struct mips_cpu_info
1339 const char *name; /* CPU or ISA name. */
1340 int flags; /* MIPS_CPU_* flags. */
1341 int ase; /* Set of ASEs implemented by the CPU. */
1342 int isa; /* ISA level. */
1343 int cpu; /* CPU number (default CPU if ISA). */
1346 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1348 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1349 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1350 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1352 /* Command-line options. */
1353 const char *md_shortopts = "O::g::G:";
1357 OPTION_MARCH = OPTION_MD_BASE,
1381 OPTION_NO_SMARTMIPS,
1387 OPTION_NO_MICROMIPS,
1390 OPTION_COMPAT_ARCH_BASE,
1399 OPTION_M7000_HILO_FIX,
1400 OPTION_MNO_7000_HILO_FIX,
1403 OPTION_FIX_LOONGSON2F_JUMP,
1404 OPTION_NO_FIX_LOONGSON2F_JUMP,
1405 OPTION_FIX_LOONGSON2F_NOP,
1406 OPTION_NO_FIX_LOONGSON2F_NOP,
1408 OPTION_NO_FIX_VR4120,
1410 OPTION_NO_FIX_VR4130,
1411 OPTION_FIX_CN63XXP1,
1412 OPTION_NO_FIX_CN63XXP1,
1419 OPTION_CONSTRUCT_FLOATS,
1420 OPTION_NO_CONSTRUCT_FLOATS,
1423 OPTION_RELAX_BRANCH,
1424 OPTION_NO_RELAX_BRANCH,
1433 OPTION_SINGLE_FLOAT,
1434 OPTION_DOUBLE_FLOAT,
1447 OPTION_MVXWORKS_PIC,
1452 struct option md_longopts[] =
1454 /* Options which specify architecture. */
1455 {"march", required_argument, NULL, OPTION_MARCH},
1456 {"mtune", required_argument, NULL, OPTION_MTUNE},
1457 {"mips0", no_argument, NULL, OPTION_MIPS1},
1458 {"mips1", no_argument, NULL, OPTION_MIPS1},
1459 {"mips2", no_argument, NULL, OPTION_MIPS2},
1460 {"mips3", no_argument, NULL, OPTION_MIPS3},
1461 {"mips4", no_argument, NULL, OPTION_MIPS4},
1462 {"mips5", no_argument, NULL, OPTION_MIPS5},
1463 {"mips32", no_argument, NULL, OPTION_MIPS32},
1464 {"mips64", no_argument, NULL, OPTION_MIPS64},
1465 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1466 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1468 /* Options which specify Application Specific Extensions (ASEs). */
1469 {"mips16", no_argument, NULL, OPTION_MIPS16},
1470 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1471 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1472 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1473 {"mdmx", no_argument, NULL, OPTION_MDMX},
1474 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1475 {"mdsp", no_argument, NULL, OPTION_DSP},
1476 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1477 {"mmt", no_argument, NULL, OPTION_MT},
1478 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1479 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1480 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1481 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1482 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1483 {"meva", no_argument, NULL, OPTION_EVA},
1484 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1485 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1486 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1487 {"mmcu", no_argument, NULL, OPTION_MCU},
1488 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1489 {"mvirt", no_argument, NULL, OPTION_VIRT},
1490 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1492 /* Old-style architecture options. Don't add more of these. */
1493 {"m4650", no_argument, NULL, OPTION_M4650},
1494 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1495 {"m4010", no_argument, NULL, OPTION_M4010},
1496 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1497 {"m4100", no_argument, NULL, OPTION_M4100},
1498 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1499 {"m3900", no_argument, NULL, OPTION_M3900},
1500 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1502 /* Options which enable bug fixes. */
1503 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1504 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1505 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1506 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1507 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1508 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1509 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1510 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1511 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1512 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1513 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1514 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1515 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1516 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1517 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1519 /* Miscellaneous options. */
1520 {"trap", no_argument, NULL, OPTION_TRAP},
1521 {"no-break", no_argument, NULL, OPTION_TRAP},
1522 {"break", no_argument, NULL, OPTION_BREAK},
1523 {"no-trap", no_argument, NULL, OPTION_BREAK},
1524 {"EB", no_argument, NULL, OPTION_EB},
1525 {"EL", no_argument, NULL, OPTION_EL},
1526 {"mfp32", no_argument, NULL, OPTION_FP32},
1527 {"mgp32", no_argument, NULL, OPTION_GP32},
1528 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1529 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1530 {"mfp64", no_argument, NULL, OPTION_FP64},
1531 {"mgp64", no_argument, NULL, OPTION_GP64},
1532 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1533 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1534 {"minsn32", no_argument, NULL, OPTION_INSN32},
1535 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1536 {"mshared", no_argument, NULL, OPTION_MSHARED},
1537 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1538 {"msym32", no_argument, NULL, OPTION_MSYM32},
1539 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1540 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1541 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1542 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1543 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1545 /* Strictly speaking this next option is ELF specific,
1546 but we allow it for other ports as well in order to
1547 make testing easier. */
1548 {"32", no_argument, NULL, OPTION_32},
1550 /* ELF-specific options. */
1551 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1552 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1553 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1554 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1555 {"xgot", no_argument, NULL, OPTION_XGOT},
1556 {"mabi", required_argument, NULL, OPTION_MABI},
1557 {"n32", no_argument, NULL, OPTION_N32},
1558 {"64", no_argument, NULL, OPTION_64},
1559 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1560 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1561 {"mpdr", no_argument, NULL, OPTION_PDR},
1562 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1563 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1564 {"mnan", required_argument, NULL, OPTION_NAN},
1566 {NULL, no_argument, NULL, 0}
1568 size_t md_longopts_size = sizeof (md_longopts);
1570 /* Information about either an Application Specific Extension or an
1571 optional architecture feature that, for simplicity, we treat in the
1572 same way as an ASE. */
1575 /* The name of the ASE, used in both the command-line and .set options. */
1578 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1579 and 64-bit architectures, the flags here refer to the subset that
1580 is available on both. */
1583 /* The ASE_* flag used for instructions that are available on 64-bit
1584 architectures but that are not included in FLAGS. */
1585 unsigned int flags64;
1587 /* The command-line options that turn the ASE on and off. */
1591 /* The minimum required architecture revisions for MIPS32, MIPS64,
1592 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1595 int micromips32_rev;
1596 int micromips64_rev;
1599 /* A table of all supported ASEs. */
1600 static const struct mips_ase mips_ases[] = {
1601 { "dsp", ASE_DSP, ASE_DSP64,
1602 OPTION_DSP, OPTION_NO_DSP,
1605 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1606 OPTION_DSPR2, OPTION_NO_DSPR2,
1609 { "eva", ASE_EVA, 0,
1610 OPTION_EVA, OPTION_NO_EVA,
1613 { "mcu", ASE_MCU, 0,
1614 OPTION_MCU, OPTION_NO_MCU,
1617 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1618 { "mdmx", ASE_MDMX, 0,
1619 OPTION_MDMX, OPTION_NO_MDMX,
1622 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1623 { "mips3d", ASE_MIPS3D, 0,
1624 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1628 OPTION_MT, OPTION_NO_MT,
1631 { "smartmips", ASE_SMARTMIPS, 0,
1632 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1635 { "virt", ASE_VIRT, ASE_VIRT64,
1636 OPTION_VIRT, OPTION_NO_VIRT,
1640 /* The set of ASEs that require -mfp64. */
1641 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1643 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1644 static const unsigned int mips_ase_groups[] = {
1650 The following pseudo-ops from the Kane and Heinrich MIPS book
1651 should be defined here, but are currently unsupported: .alias,
1652 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1654 The following pseudo-ops from the Kane and Heinrich MIPS book are
1655 specific to the type of debugging information being generated, and
1656 should be defined by the object format: .aent, .begin, .bend,
1657 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1660 The following pseudo-ops from the Kane and Heinrich MIPS book are
1661 not MIPS CPU specific, but are also not specific to the object file
1662 format. This file is probably the best place to define them, but
1663 they are not currently supported: .asm0, .endr, .lab, .struct. */
1665 static const pseudo_typeS mips_pseudo_table[] =
1667 /* MIPS specific pseudo-ops. */
1668 {"option", s_option, 0},
1669 {"set", s_mipsset, 0},
1670 {"rdata", s_change_sec, 'r'},
1671 {"sdata", s_change_sec, 's'},
1672 {"livereg", s_ignore, 0},
1673 {"abicalls", s_abicalls, 0},
1674 {"cpload", s_cpload, 0},
1675 {"cpsetup", s_cpsetup, 0},
1676 {"cplocal", s_cplocal, 0},
1677 {"cprestore", s_cprestore, 0},
1678 {"cpreturn", s_cpreturn, 0},
1679 {"dtprelword", s_dtprelword, 0},
1680 {"dtpreldword", s_dtpreldword, 0},
1681 {"tprelword", s_tprelword, 0},
1682 {"tpreldword", s_tpreldword, 0},
1683 {"gpvalue", s_gpvalue, 0},
1684 {"gpword", s_gpword, 0},
1685 {"gpdword", s_gpdword, 0},
1686 {"ehword", s_ehword, 0},
1687 {"cpadd", s_cpadd, 0},
1688 {"insn", s_insn, 0},
1691 /* Relatively generic pseudo-ops that happen to be used on MIPS
1693 {"asciiz", stringer, 8 + 1},
1694 {"bss", s_change_sec, 'b'},
1696 {"half", s_cons, 1},
1697 {"dword", s_cons, 3},
1698 {"weakext", s_mips_weakext, 0},
1699 {"origin", s_org, 0},
1700 {"repeat", s_rept, 0},
1702 /* For MIPS this is non-standard, but we define it for consistency. */
1703 {"sbss", s_change_sec, 'B'},
1705 /* These pseudo-ops are defined in read.c, but must be overridden
1706 here for one reason or another. */
1707 {"align", s_align, 0},
1708 {"byte", s_cons, 0},
1709 {"data", s_change_sec, 'd'},
1710 {"double", s_float_cons, 'd'},
1711 {"float", s_float_cons, 'f'},
1712 {"globl", s_mips_globl, 0},
1713 {"global", s_mips_globl, 0},
1714 {"hword", s_cons, 1},
1716 {"long", s_cons, 2},
1717 {"octa", s_cons, 4},
1718 {"quad", s_cons, 3},
1719 {"section", s_change_section, 0},
1720 {"short", s_cons, 1},
1721 {"single", s_float_cons, 'f'},
1722 {"stabd", s_mips_stab, 'd'},
1723 {"stabn", s_mips_stab, 'n'},
1724 {"stabs", s_mips_stab, 's'},
1725 {"text", s_change_sec, 't'},
1726 {"word", s_cons, 2},
1728 { "extern", ecoff_directive_extern, 0},
1733 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1735 /* These pseudo-ops should be defined by the object file format.
1736 However, a.out doesn't support them, so we have versions here. */
1737 {"aent", s_mips_ent, 1},
1738 {"bgnb", s_ignore, 0},
1739 {"end", s_mips_end, 0},
1740 {"endb", s_ignore, 0},
1741 {"ent", s_mips_ent, 0},
1742 {"file", s_mips_file, 0},
1743 {"fmask", s_mips_mask, 'F'},
1744 {"frame", s_mips_frame, 0},
1745 {"loc", s_mips_loc, 0},
1746 {"mask", s_mips_mask, 'R'},
1747 {"verstamp", s_ignore, 0},
1751 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1752 purpose of the `.dc.a' internal pseudo-op. */
1755 mips_address_bytes (void)
1757 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1760 extern void pop_insert (const pseudo_typeS *);
1763 mips_pop_insert (void)
1765 pop_insert (mips_pseudo_table);
1766 if (! ECOFF_DEBUGGING)
1767 pop_insert (mips_nonecoff_pseudo_table);
1770 /* Symbols labelling the current insn. */
1772 struct insn_label_list
1774 struct insn_label_list *next;
1778 static struct insn_label_list *free_insn_labels;
1779 #define label_list tc_segment_info_data.labels
1781 static void mips_clear_insn_labels (void);
1782 static void mips_mark_labels (void);
1783 static void mips_compressed_mark_labels (void);
1786 mips_clear_insn_labels (void)
1788 register struct insn_label_list **pl;
1789 segment_info_type *si;
1793 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1796 si = seg_info (now_seg);
1797 *pl = si->label_list;
1798 si->label_list = NULL;
1802 /* Mark instruction labels in MIPS16/microMIPS mode. */
1805 mips_mark_labels (void)
1807 if (HAVE_CODE_COMPRESSION)
1808 mips_compressed_mark_labels ();
1811 static char *expr_end;
1813 /* Expressions which appear in macro instructions. These are set by
1814 mips_ip and read by macro. */
1816 static expressionS imm_expr;
1817 static expressionS imm2_expr;
1819 /* The relocatable field in an instruction and the relocs associated
1820 with it. These variables are used for instructions like LUI and
1821 JAL as well as true offsets. They are also used for address
1822 operands in macros. */
1824 static expressionS offset_expr;
1825 static bfd_reloc_code_real_type offset_reloc[3]
1826 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1828 /* This is set to the resulting size of the instruction to be produced
1829 by mips16_ip if an explicit extension is used or by mips_ip if an
1830 explicit size is supplied. */
1832 static unsigned int forced_insn_length;
1834 /* True if we are assembling an instruction. All dot symbols defined during
1835 this time should be treated as code labels. */
1837 static bfd_boolean mips_assembling_insn;
1839 /* The pdr segment for per procedure frame/regmask info. Not used for
1842 static segT pdr_seg;
1844 /* The default target format to use. */
1846 #if defined (TE_FreeBSD)
1847 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1848 #elif defined (TE_TMIPS)
1849 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1851 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1855 mips_target_format (void)
1857 switch (OUTPUT_FLAVOR)
1859 case bfd_target_elf_flavour:
1861 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1862 return (target_big_endian
1863 ? "elf32-bigmips-vxworks"
1864 : "elf32-littlemips-vxworks");
1866 return (target_big_endian
1867 ? (HAVE_64BIT_OBJECTS
1868 ? ELF_TARGET ("elf64-", "big")
1870 ? ELF_TARGET ("elf32-n", "big")
1871 : ELF_TARGET ("elf32-", "big")))
1872 : (HAVE_64BIT_OBJECTS
1873 ? ELF_TARGET ("elf64-", "little")
1875 ? ELF_TARGET ("elf32-n", "little")
1876 : ELF_TARGET ("elf32-", "little"))));
1883 /* Return the ISA revision that is currently in use, or 0 if we are
1884 generating code for MIPS V or below. */
1889 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1892 /* microMIPS implies revision 2 or above. */
1893 if (mips_opts.micromips)
1896 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1902 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1905 mips_ase_mask (unsigned int flags)
1909 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1910 if (flags & mips_ase_groups[i])
1911 flags |= mips_ase_groups[i];
1915 /* Check whether the current ISA supports ASE. Issue a warning if
1919 mips_check_isa_supports_ase (const struct mips_ase *ase)
1923 static unsigned int warned_isa;
1924 static unsigned int warned_fp32;
1926 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1927 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1929 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1930 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1931 && (warned_isa & ase->flags) != ase->flags)
1933 warned_isa |= ase->flags;
1934 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1935 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1937 as_warn (_("The %d-bit %s architecture does not support the"
1938 " `%s' extension"), size, base, ase->name);
1940 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1941 ase->name, base, size, min_rev);
1943 if ((ase->flags & FP64_ASES)
1945 && (warned_fp32 & ase->flags) != ase->flags)
1947 warned_fp32 |= ase->flags;
1948 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1952 /* Check all enabled ASEs to see whether they are supported by the
1953 chosen architecture. */
1956 mips_check_isa_supports_ases (void)
1958 unsigned int i, mask;
1960 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1962 mask = mips_ase_mask (mips_ases[i].flags);
1963 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1964 mips_check_isa_supports_ase (&mips_ases[i]);
1968 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1969 that were affected. */
1972 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1976 mask = mips_ase_mask (ase->flags);
1977 mips_opts.ase &= ~mask;
1979 mips_opts.ase |= ase->flags;
1983 /* Return the ASE called NAME, or null if none. */
1985 static const struct mips_ase *
1986 mips_lookup_ase (const char *name)
1990 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1991 if (strcmp (name, mips_ases[i].name) == 0)
1992 return &mips_ases[i];
1996 /* Return the length of a microMIPS instruction in bytes. If bits of
1997 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1998 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1999 major opcode) will require further modifications to the opcode
2002 static inline unsigned int
2003 micromips_insn_length (const struct mips_opcode *mo)
2005 return (mo->mask >> 16) == 0 ? 2 : 4;
2008 /* Return the length of MIPS16 instruction OPCODE. */
2010 static inline unsigned int
2011 mips16_opcode_length (unsigned long opcode)
2013 return (opcode >> 16) == 0 ? 2 : 4;
2016 /* Return the length of instruction INSN. */
2018 static inline unsigned int
2019 insn_length (const struct mips_cl_insn *insn)
2021 if (mips_opts.micromips)
2022 return micromips_insn_length (insn->insn_mo);
2023 else if (mips_opts.mips16)
2024 return mips16_opcode_length (insn->insn_opcode);
2029 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2032 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2037 insn->insn_opcode = mo->match;
2040 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2041 insn->fixp[i] = NULL;
2042 insn->fixed_p = (mips_opts.noreorder > 0);
2043 insn->noreorder_p = (mips_opts.noreorder > 0);
2044 insn->mips16_absolute_jump_p = 0;
2045 insn->complete_p = 0;
2046 insn->cleared_p = 0;
2049 /* Record the current MIPS16/microMIPS mode in now_seg. */
2052 mips_record_compressed_mode (void)
2054 segment_info_type *si;
2056 si = seg_info (now_seg);
2057 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2058 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2059 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2060 si->tc_segment_info_data.micromips = mips_opts.micromips;
2063 /* Read a standard MIPS instruction from BUF. */
2065 static unsigned long
2066 read_insn (char *buf)
2068 if (target_big_endian)
2069 return bfd_getb32 ((bfd_byte *) buf);
2071 return bfd_getl32 ((bfd_byte *) buf);
2074 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2078 write_insn (char *buf, unsigned int insn)
2080 md_number_to_chars (buf, insn, 4);
2084 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2085 has length LENGTH. */
2087 static unsigned long
2088 read_compressed_insn (char *buf, unsigned int length)
2094 for (i = 0; i < length; i += 2)
2097 if (target_big_endian)
2098 insn |= bfd_getb16 ((char *) buf);
2100 insn |= bfd_getl16 ((char *) buf);
2106 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2107 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2110 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2114 for (i = 0; i < length; i += 2)
2115 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2116 return buf + length;
2119 /* Install INSN at the location specified by its "frag" and "where" fields. */
2122 install_insn (const struct mips_cl_insn *insn)
2124 char *f = insn->frag->fr_literal + insn->where;
2125 if (HAVE_CODE_COMPRESSION)
2126 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2128 write_insn (f, insn->insn_opcode);
2129 mips_record_compressed_mode ();
2132 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2133 and install the opcode in the new location. */
2136 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2141 insn->where = where;
2142 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2143 if (insn->fixp[i] != NULL)
2145 insn->fixp[i]->fx_frag = frag;
2146 insn->fixp[i]->fx_where = where;
2148 install_insn (insn);
2151 /* Add INSN to the end of the output. */
2154 add_fixed_insn (struct mips_cl_insn *insn)
2156 char *f = frag_more (insn_length (insn));
2157 move_insn (insn, frag_now, f - frag_now->fr_literal);
2160 /* Start a variant frag and move INSN to the start of the variant part,
2161 marking it as fixed. The other arguments are as for frag_var. */
2164 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2165 relax_substateT subtype, symbolS *symbol, offsetT offset)
2167 frag_grow (max_chars);
2168 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2170 frag_var (rs_machine_dependent, max_chars, var,
2171 subtype, symbol, offset, NULL);
2174 /* Insert N copies of INSN into the history buffer, starting at
2175 position FIRST. Neither FIRST nor N need to be clipped. */
2178 insert_into_history (unsigned int first, unsigned int n,
2179 const struct mips_cl_insn *insn)
2181 if (mips_relax.sequence != 2)
2185 for (i = ARRAY_SIZE (history); i-- > first;)
2187 history[i] = history[i - n];
2193 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2194 the idea is to make it obvious at a glance that each errata is
2198 init_vr4120_conflicts (void)
2200 #define CONFLICT(FIRST, SECOND) \
2201 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2203 /* Errata 21 - [D]DIV[U] after [D]MACC */
2204 CONFLICT (MACC, DIV);
2205 CONFLICT (DMACC, DIV);
2207 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2208 CONFLICT (DMULT, DMULT);
2209 CONFLICT (DMULT, DMACC);
2210 CONFLICT (DMACC, DMULT);
2211 CONFLICT (DMACC, DMACC);
2213 /* Errata 24 - MT{LO,HI} after [D]MACC */
2214 CONFLICT (MACC, MTHILO);
2215 CONFLICT (DMACC, MTHILO);
2217 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2218 instruction is executed immediately after a MACC or DMACC
2219 instruction, the result of [either instruction] is incorrect." */
2220 CONFLICT (MACC, MULT);
2221 CONFLICT (MACC, DMULT);
2222 CONFLICT (DMACC, MULT);
2223 CONFLICT (DMACC, DMULT);
2225 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2226 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2227 DDIV or DDIVU instruction, the result of the MACC or
2228 DMACC instruction is incorrect.". */
2229 CONFLICT (DMULT, MACC);
2230 CONFLICT (DMULT, DMACC);
2231 CONFLICT (DIV, MACC);
2232 CONFLICT (DIV, DMACC);
2242 #define RTYPE_MASK 0x1ff00
2243 #define RTYPE_NUM 0x00100
2244 #define RTYPE_FPU 0x00200
2245 #define RTYPE_FCC 0x00400
2246 #define RTYPE_VEC 0x00800
2247 #define RTYPE_GP 0x01000
2248 #define RTYPE_CP0 0x02000
2249 #define RTYPE_PC 0x04000
2250 #define RTYPE_ACC 0x08000
2251 #define RTYPE_CCC 0x10000
2252 #define RNUM_MASK 0x000ff
2253 #define RWARN 0x80000
2255 #define GENERIC_REGISTER_NUMBERS \
2256 {"$0", RTYPE_NUM | 0}, \
2257 {"$1", RTYPE_NUM | 1}, \
2258 {"$2", RTYPE_NUM | 2}, \
2259 {"$3", RTYPE_NUM | 3}, \
2260 {"$4", RTYPE_NUM | 4}, \
2261 {"$5", RTYPE_NUM | 5}, \
2262 {"$6", RTYPE_NUM | 6}, \
2263 {"$7", RTYPE_NUM | 7}, \
2264 {"$8", RTYPE_NUM | 8}, \
2265 {"$9", RTYPE_NUM | 9}, \
2266 {"$10", RTYPE_NUM | 10}, \
2267 {"$11", RTYPE_NUM | 11}, \
2268 {"$12", RTYPE_NUM | 12}, \
2269 {"$13", RTYPE_NUM | 13}, \
2270 {"$14", RTYPE_NUM | 14}, \
2271 {"$15", RTYPE_NUM | 15}, \
2272 {"$16", RTYPE_NUM | 16}, \
2273 {"$17", RTYPE_NUM | 17}, \
2274 {"$18", RTYPE_NUM | 18}, \
2275 {"$19", RTYPE_NUM | 19}, \
2276 {"$20", RTYPE_NUM | 20}, \
2277 {"$21", RTYPE_NUM | 21}, \
2278 {"$22", RTYPE_NUM | 22}, \
2279 {"$23", RTYPE_NUM | 23}, \
2280 {"$24", RTYPE_NUM | 24}, \
2281 {"$25", RTYPE_NUM | 25}, \
2282 {"$26", RTYPE_NUM | 26}, \
2283 {"$27", RTYPE_NUM | 27}, \
2284 {"$28", RTYPE_NUM | 28}, \
2285 {"$29", RTYPE_NUM | 29}, \
2286 {"$30", RTYPE_NUM | 30}, \
2287 {"$31", RTYPE_NUM | 31}
2289 #define FPU_REGISTER_NAMES \
2290 {"$f0", RTYPE_FPU | 0}, \
2291 {"$f1", RTYPE_FPU | 1}, \
2292 {"$f2", RTYPE_FPU | 2}, \
2293 {"$f3", RTYPE_FPU | 3}, \
2294 {"$f4", RTYPE_FPU | 4}, \
2295 {"$f5", RTYPE_FPU | 5}, \
2296 {"$f6", RTYPE_FPU | 6}, \
2297 {"$f7", RTYPE_FPU | 7}, \
2298 {"$f8", RTYPE_FPU | 8}, \
2299 {"$f9", RTYPE_FPU | 9}, \
2300 {"$f10", RTYPE_FPU | 10}, \
2301 {"$f11", RTYPE_FPU | 11}, \
2302 {"$f12", RTYPE_FPU | 12}, \
2303 {"$f13", RTYPE_FPU | 13}, \
2304 {"$f14", RTYPE_FPU | 14}, \
2305 {"$f15", RTYPE_FPU | 15}, \
2306 {"$f16", RTYPE_FPU | 16}, \
2307 {"$f17", RTYPE_FPU | 17}, \
2308 {"$f18", RTYPE_FPU | 18}, \
2309 {"$f19", RTYPE_FPU | 19}, \
2310 {"$f20", RTYPE_FPU | 20}, \
2311 {"$f21", RTYPE_FPU | 21}, \
2312 {"$f22", RTYPE_FPU | 22}, \
2313 {"$f23", RTYPE_FPU | 23}, \
2314 {"$f24", RTYPE_FPU | 24}, \
2315 {"$f25", RTYPE_FPU | 25}, \
2316 {"$f26", RTYPE_FPU | 26}, \
2317 {"$f27", RTYPE_FPU | 27}, \
2318 {"$f28", RTYPE_FPU | 28}, \
2319 {"$f29", RTYPE_FPU | 29}, \
2320 {"$f30", RTYPE_FPU | 30}, \
2321 {"$f31", RTYPE_FPU | 31}
2323 #define FPU_CONDITION_CODE_NAMES \
2324 {"$fcc0", RTYPE_FCC | 0}, \
2325 {"$fcc1", RTYPE_FCC | 1}, \
2326 {"$fcc2", RTYPE_FCC | 2}, \
2327 {"$fcc3", RTYPE_FCC | 3}, \
2328 {"$fcc4", RTYPE_FCC | 4}, \
2329 {"$fcc5", RTYPE_FCC | 5}, \
2330 {"$fcc6", RTYPE_FCC | 6}, \
2331 {"$fcc7", RTYPE_FCC | 7}
2333 #define COPROC_CONDITION_CODE_NAMES \
2334 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2335 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2336 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2337 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2338 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2339 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2340 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2341 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2343 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2344 {"$a4", RTYPE_GP | 8}, \
2345 {"$a5", RTYPE_GP | 9}, \
2346 {"$a6", RTYPE_GP | 10}, \
2347 {"$a7", RTYPE_GP | 11}, \
2348 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2349 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2350 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2351 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2352 {"$t0", RTYPE_GP | 12}, \
2353 {"$t1", RTYPE_GP | 13}, \
2354 {"$t2", RTYPE_GP | 14}, \
2355 {"$t3", RTYPE_GP | 15}
2357 #define O32_SYMBOLIC_REGISTER_NAMES \
2358 {"$t0", RTYPE_GP | 8}, \
2359 {"$t1", RTYPE_GP | 9}, \
2360 {"$t2", RTYPE_GP | 10}, \
2361 {"$t3", RTYPE_GP | 11}, \
2362 {"$t4", RTYPE_GP | 12}, \
2363 {"$t5", RTYPE_GP | 13}, \
2364 {"$t6", RTYPE_GP | 14}, \
2365 {"$t7", RTYPE_GP | 15}, \
2366 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2367 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2368 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2369 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2371 /* Remaining symbolic register names */
2372 #define SYMBOLIC_REGISTER_NAMES \
2373 {"$zero", RTYPE_GP | 0}, \
2374 {"$at", RTYPE_GP | 1}, \
2375 {"$AT", RTYPE_GP | 1}, \
2376 {"$v0", RTYPE_GP | 2}, \
2377 {"$v1", RTYPE_GP | 3}, \
2378 {"$a0", RTYPE_GP | 4}, \
2379 {"$a1", RTYPE_GP | 5}, \
2380 {"$a2", RTYPE_GP | 6}, \
2381 {"$a3", RTYPE_GP | 7}, \
2382 {"$s0", RTYPE_GP | 16}, \
2383 {"$s1", RTYPE_GP | 17}, \
2384 {"$s2", RTYPE_GP | 18}, \
2385 {"$s3", RTYPE_GP | 19}, \
2386 {"$s4", RTYPE_GP | 20}, \
2387 {"$s5", RTYPE_GP | 21}, \
2388 {"$s6", RTYPE_GP | 22}, \
2389 {"$s7", RTYPE_GP | 23}, \
2390 {"$t8", RTYPE_GP | 24}, \
2391 {"$t9", RTYPE_GP | 25}, \
2392 {"$k0", RTYPE_GP | 26}, \
2393 {"$kt0", RTYPE_GP | 26}, \
2394 {"$k1", RTYPE_GP | 27}, \
2395 {"$kt1", RTYPE_GP | 27}, \
2396 {"$gp", RTYPE_GP | 28}, \
2397 {"$sp", RTYPE_GP | 29}, \
2398 {"$s8", RTYPE_GP | 30}, \
2399 {"$fp", RTYPE_GP | 30}, \
2400 {"$ra", RTYPE_GP | 31}
2402 #define MIPS16_SPECIAL_REGISTER_NAMES \
2403 {"$pc", RTYPE_PC | 0}
2405 #define MDMX_VECTOR_REGISTER_NAMES \
2406 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2407 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2408 {"$v2", RTYPE_VEC | 2}, \
2409 {"$v3", RTYPE_VEC | 3}, \
2410 {"$v4", RTYPE_VEC | 4}, \
2411 {"$v5", RTYPE_VEC | 5}, \
2412 {"$v6", RTYPE_VEC | 6}, \
2413 {"$v7", RTYPE_VEC | 7}, \
2414 {"$v8", RTYPE_VEC | 8}, \
2415 {"$v9", RTYPE_VEC | 9}, \
2416 {"$v10", RTYPE_VEC | 10}, \
2417 {"$v11", RTYPE_VEC | 11}, \
2418 {"$v12", RTYPE_VEC | 12}, \
2419 {"$v13", RTYPE_VEC | 13}, \
2420 {"$v14", RTYPE_VEC | 14}, \
2421 {"$v15", RTYPE_VEC | 15}, \
2422 {"$v16", RTYPE_VEC | 16}, \
2423 {"$v17", RTYPE_VEC | 17}, \
2424 {"$v18", RTYPE_VEC | 18}, \
2425 {"$v19", RTYPE_VEC | 19}, \
2426 {"$v20", RTYPE_VEC | 20}, \
2427 {"$v21", RTYPE_VEC | 21}, \
2428 {"$v22", RTYPE_VEC | 22}, \
2429 {"$v23", RTYPE_VEC | 23}, \
2430 {"$v24", RTYPE_VEC | 24}, \
2431 {"$v25", RTYPE_VEC | 25}, \
2432 {"$v26", RTYPE_VEC | 26}, \
2433 {"$v27", RTYPE_VEC | 27}, \
2434 {"$v28", RTYPE_VEC | 28}, \
2435 {"$v29", RTYPE_VEC | 29}, \
2436 {"$v30", RTYPE_VEC | 30}, \
2437 {"$v31", RTYPE_VEC | 31}
2439 #define MIPS_DSP_ACCUMULATOR_NAMES \
2440 {"$ac0", RTYPE_ACC | 0}, \
2441 {"$ac1", RTYPE_ACC | 1}, \
2442 {"$ac2", RTYPE_ACC | 2}, \
2443 {"$ac3", RTYPE_ACC | 3}
2445 static const struct regname reg_names[] = {
2446 GENERIC_REGISTER_NUMBERS,
2448 FPU_CONDITION_CODE_NAMES,
2449 COPROC_CONDITION_CODE_NAMES,
2451 /* The $txx registers depends on the abi,
2452 these will be added later into the symbol table from
2453 one of the tables below once mips_abi is set after
2454 parsing of arguments from the command line. */
2455 SYMBOLIC_REGISTER_NAMES,
2457 MIPS16_SPECIAL_REGISTER_NAMES,
2458 MDMX_VECTOR_REGISTER_NAMES,
2459 MIPS_DSP_ACCUMULATOR_NAMES,
2463 static const struct regname reg_names_o32[] = {
2464 O32_SYMBOLIC_REGISTER_NAMES,
2468 static const struct regname reg_names_n32n64[] = {
2469 N32N64_SYMBOLIC_REGISTER_NAMES,
2473 /* Check if S points at a valid register specifier according to TYPES.
2474 If so, then return 1, advance S to consume the specifier and store
2475 the register's number in REGNOP, otherwise return 0. */
2478 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2485 /* Find end of name. */
2487 if (is_name_beginner (*e))
2489 while (is_part_of_name (*e))
2492 /* Terminate name. */
2496 /* Look for a register symbol. */
2497 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2499 int r = S_GET_VALUE (symbolP);
2501 reg = r & RNUM_MASK;
2502 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2503 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2504 reg = (r & RNUM_MASK) - 2;
2506 /* Else see if this is a register defined in an itbl entry. */
2507 else if ((types & RTYPE_GP) && itbl_have_entries)
2514 if (itbl_get_reg_val (n, &r))
2515 reg = r & RNUM_MASK;
2518 /* Advance to next token if a register was recognised. */
2521 else if (types & RWARN)
2522 as_warn (_("Unrecognized register name `%s'"), *s);
2530 /* Check if S points at a valid register list according to TYPES.
2531 If so, then return 1, advance S to consume the list and store
2532 the registers present on the list as a bitmask of ones in REGLISTP,
2533 otherwise return 0. A valid list comprises a comma-separated
2534 enumeration of valid single registers and/or dash-separated
2535 contiguous register ranges as determined by their numbers.
2537 As a special exception if one of s0-s7 registers is specified as
2538 the range's lower delimiter and s8 (fp) is its upper one, then no
2539 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2540 are selected; they have to be listed separately if needed. */
2543 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2545 unsigned int reglist = 0;
2546 unsigned int lastregno;
2547 bfd_boolean ok = TRUE;
2548 unsigned int regmask;
2549 char *s_endlist = *s;
2553 while (reg_lookup (s, types, ®no))
2559 ok = reg_lookup (s, types, &lastregno);
2560 if (ok && lastregno < regno)
2566 if (lastregno == FP && regno >= S0 && regno <= S7)
2571 regmask = 1 << lastregno;
2572 regmask = (regmask << 1) - 1;
2573 regmask ^= (1 << regno) - 1;
2587 *reglistp = reglist;
2588 return ok && reglist != 0;
2592 mips_lookup_reg_pair (unsigned int regno1, unsigned int regno2,
2593 const unsigned int *map1, const unsigned int *map2,
2598 for (i = 0; i < count; i++)
2599 if (map1[i] == regno1 && map2[i] == regno2)
2604 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2605 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2608 is_opcode_valid (const struct mips_opcode *mo)
2610 int isa = mips_opts.isa;
2611 int ase = mips_opts.ase;
2615 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2616 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2617 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2618 ase |= mips_ases[i].flags64;
2620 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2623 /* Check whether the instruction or macro requires single-precision or
2624 double-precision floating-point support. Note that this information is
2625 stored differently in the opcode table for insns and macros. */
2626 if (mo->pinfo == INSN_MACRO)
2628 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2629 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2633 fp_s = mo->pinfo & FP_S;
2634 fp_d = mo->pinfo & FP_D;
2637 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2640 if (fp_s && mips_opts.soft_float)
2646 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2647 selected ISA and architecture. */
2650 is_opcode_valid_16 (const struct mips_opcode *mo)
2652 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2655 /* Return TRUE if the size of the microMIPS opcode MO matches one
2656 explicitly requested. Always TRUE in the standard MIPS mode. */
2659 is_size_valid (const struct mips_opcode *mo)
2661 if (!mips_opts.micromips)
2664 if (mips_opts.insn32)
2666 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2668 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2671 if (!forced_insn_length)
2673 if (mo->pinfo == INSN_MACRO)
2675 return forced_insn_length == micromips_insn_length (mo);
2678 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2679 of the preceding instruction. Always TRUE in the standard MIPS mode.
2681 We don't accept macros in 16-bit delay slots to avoid a case where
2682 a macro expansion fails because it relies on a preceding 32-bit real
2683 instruction to have matched and does not handle the operands correctly.
2684 The only macros that may expand to 16-bit instructions are JAL that
2685 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2686 and BGT (that likewise cannot be placed in a delay slot) that decay to
2687 a NOP. In all these cases the macros precede any corresponding real
2688 instruction definitions in the opcode table, so they will match in the
2689 second pass where the size of the delay slot is ignored and therefore
2690 produce correct code. */
2693 is_delay_slot_valid (const struct mips_opcode *mo)
2695 if (!mips_opts.micromips)
2698 if (mo->pinfo == INSN_MACRO)
2699 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2700 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2701 && micromips_insn_length (mo) != 4)
2703 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2704 && micromips_insn_length (mo) != 2)
2710 /* This function is called once, at assembler startup time. It should set up
2711 all the tables, etc. that the MD part of the assembler will need. */
2716 const char *retval = NULL;
2720 if (mips_pic != NO_PIC)
2722 if (g_switch_seen && g_switch_value != 0)
2723 as_bad (_("-G may not be used in position-independent code"));
2727 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2728 as_warn (_("Could not set architecture and machine"));
2730 op_hash = hash_new ();
2732 for (i = 0; i < NUMOPCODES;)
2734 const char *name = mips_opcodes[i].name;
2736 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2739 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2740 mips_opcodes[i].name, retval);
2741 /* Probably a memory allocation problem? Give up now. */
2742 as_fatal (_("Broken assembler. No assembly attempted."));
2746 if (mips_opcodes[i].pinfo != INSN_MACRO)
2748 if (!validate_mips_insn (&mips_opcodes[i]))
2750 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2752 create_insn (&nop_insn, mips_opcodes + i);
2753 if (mips_fix_loongson2f_nop)
2754 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2755 nop_insn.fixed_p = 1;
2760 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2763 mips16_op_hash = hash_new ();
2766 while (i < bfd_mips16_num_opcodes)
2768 const char *name = mips16_opcodes[i].name;
2770 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2772 as_fatal (_("internal: can't hash `%s': %s"),
2773 mips16_opcodes[i].name, retval);
2776 if (mips16_opcodes[i].pinfo != INSN_MACRO
2777 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2778 != mips16_opcodes[i].match))
2780 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2781 mips16_opcodes[i].name, mips16_opcodes[i].args);
2784 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2786 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2787 mips16_nop_insn.fixed_p = 1;
2791 while (i < bfd_mips16_num_opcodes
2792 && strcmp (mips16_opcodes[i].name, name) == 0);
2795 micromips_op_hash = hash_new ();
2798 while (i < bfd_micromips_num_opcodes)
2800 const char *name = micromips_opcodes[i].name;
2802 retval = hash_insert (micromips_op_hash, name,
2803 (void *) µmips_opcodes[i]);
2805 as_fatal (_("internal: can't hash `%s': %s"),
2806 micromips_opcodes[i].name, retval);
2808 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2810 struct mips_cl_insn *micromips_nop_insn;
2812 if (!validate_micromips_insn (µmips_opcodes[i]))
2815 if (micromips_insn_length (micromips_opcodes + i) == 2)
2816 micromips_nop_insn = µmips_nop16_insn;
2817 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2818 micromips_nop_insn = µmips_nop32_insn;
2822 if (micromips_nop_insn->insn_mo == NULL
2823 && strcmp (name, "nop") == 0)
2825 create_insn (micromips_nop_insn, micromips_opcodes + i);
2826 micromips_nop_insn->fixed_p = 1;
2829 while (++i < bfd_micromips_num_opcodes
2830 && strcmp (micromips_opcodes[i].name, name) == 0);
2834 as_fatal (_("Broken assembler. No assembly attempted."));
2836 /* We add all the general register names to the symbol table. This
2837 helps us detect invalid uses of them. */
2838 for (i = 0; reg_names[i].name; i++)
2839 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2840 reg_names[i].num, /* & RNUM_MASK, */
2841 &zero_address_frag));
2843 for (i = 0; reg_names_n32n64[i].name; i++)
2844 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2845 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2846 &zero_address_frag));
2848 for (i = 0; reg_names_o32[i].name; i++)
2849 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2850 reg_names_o32[i].num, /* & RNUM_MASK, */
2851 &zero_address_frag));
2853 mips_no_prev_insn ();
2856 mips_cprmask[0] = 0;
2857 mips_cprmask[1] = 0;
2858 mips_cprmask[2] = 0;
2859 mips_cprmask[3] = 0;
2861 /* set the default alignment for the text section (2**2) */
2862 record_alignment (text_section, 2);
2864 bfd_set_gp_size (stdoutput, g_switch_value);
2866 /* On a native system other than VxWorks, sections must be aligned
2867 to 16 byte boundaries. When configured for an embedded ELF
2868 target, we don't bother. */
2869 if (strncmp (TARGET_OS, "elf", 3) != 0
2870 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2872 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2873 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2874 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2877 /* Create a .reginfo section for register masks and a .mdebug
2878 section for debugging information. */
2886 subseg = now_subseg;
2888 /* The ABI says this section should be loaded so that the
2889 running program can access it. However, we don't load it
2890 if we are configured for an embedded target */
2891 flags = SEC_READONLY | SEC_DATA;
2892 if (strncmp (TARGET_OS, "elf", 3) != 0)
2893 flags |= SEC_ALLOC | SEC_LOAD;
2895 if (mips_abi != N64_ABI)
2897 sec = subseg_new (".reginfo", (subsegT) 0);
2899 bfd_set_section_flags (stdoutput, sec, flags);
2900 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2902 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2906 /* The 64-bit ABI uses a .MIPS.options section rather than
2907 .reginfo section. */
2908 sec = subseg_new (".MIPS.options", (subsegT) 0);
2909 bfd_set_section_flags (stdoutput, sec, flags);
2910 bfd_set_section_alignment (stdoutput, sec, 3);
2912 /* Set up the option header. */
2914 Elf_Internal_Options opthdr;
2917 opthdr.kind = ODK_REGINFO;
2918 opthdr.size = (sizeof (Elf_External_Options)
2919 + sizeof (Elf64_External_RegInfo));
2922 f = frag_more (sizeof (Elf_External_Options));
2923 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2924 (Elf_External_Options *) f);
2926 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2930 if (ECOFF_DEBUGGING)
2932 sec = subseg_new (".mdebug", (subsegT) 0);
2933 (void) bfd_set_section_flags (stdoutput, sec,
2934 SEC_HAS_CONTENTS | SEC_READONLY);
2935 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2937 else if (mips_flag_pdr)
2939 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2940 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2941 SEC_READONLY | SEC_RELOC
2943 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2946 subseg_set (seg, subseg);
2949 if (! ECOFF_DEBUGGING)
2952 if (mips_fix_vr4120)
2953 init_vr4120_conflicts ();
2959 mips_emit_delays ();
2960 if (! ECOFF_DEBUGGING)
2965 md_assemble (char *str)
2967 struct mips_cl_insn insn;
2968 bfd_reloc_code_real_type unused_reloc[3]
2969 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2971 imm_expr.X_op = O_absent;
2972 imm2_expr.X_op = O_absent;
2973 offset_expr.X_op = O_absent;
2974 offset_reloc[0] = BFD_RELOC_UNUSED;
2975 offset_reloc[1] = BFD_RELOC_UNUSED;
2976 offset_reloc[2] = BFD_RELOC_UNUSED;
2978 mips_mark_labels ();
2979 mips_assembling_insn = TRUE;
2981 if (mips_opts.mips16)
2982 mips16_ip (str, &insn);
2985 mips_ip (str, &insn);
2986 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2987 str, insn.insn_opcode));
2991 as_bad ("%s `%s'", insn_error, str);
2992 else if (insn.insn_mo->pinfo == INSN_MACRO)
2995 if (mips_opts.mips16)
2996 mips16_macro (&insn);
3003 if (offset_expr.X_op != O_absent)
3004 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3006 append_insn (&insn, NULL, unused_reloc, FALSE);
3009 mips_assembling_insn = FALSE;
3012 /* Convenience functions for abstracting away the differences between
3013 MIPS16 and non-MIPS16 relocations. */
3015 static inline bfd_boolean
3016 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3020 case BFD_RELOC_MIPS16_JMP:
3021 case BFD_RELOC_MIPS16_GPREL:
3022 case BFD_RELOC_MIPS16_GOT16:
3023 case BFD_RELOC_MIPS16_CALL16:
3024 case BFD_RELOC_MIPS16_HI16_S:
3025 case BFD_RELOC_MIPS16_HI16:
3026 case BFD_RELOC_MIPS16_LO16:
3034 static inline bfd_boolean
3035 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3039 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3040 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3041 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3042 case BFD_RELOC_MICROMIPS_GPREL16:
3043 case BFD_RELOC_MICROMIPS_JMP:
3044 case BFD_RELOC_MICROMIPS_HI16:
3045 case BFD_RELOC_MICROMIPS_HI16_S:
3046 case BFD_RELOC_MICROMIPS_LO16:
3047 case BFD_RELOC_MICROMIPS_LITERAL:
3048 case BFD_RELOC_MICROMIPS_GOT16:
3049 case BFD_RELOC_MICROMIPS_CALL16:
3050 case BFD_RELOC_MICROMIPS_GOT_HI16:
3051 case BFD_RELOC_MICROMIPS_GOT_LO16:
3052 case BFD_RELOC_MICROMIPS_CALL_HI16:
3053 case BFD_RELOC_MICROMIPS_CALL_LO16:
3054 case BFD_RELOC_MICROMIPS_SUB:
3055 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3056 case BFD_RELOC_MICROMIPS_GOT_OFST:
3057 case BFD_RELOC_MICROMIPS_GOT_DISP:
3058 case BFD_RELOC_MICROMIPS_HIGHEST:
3059 case BFD_RELOC_MICROMIPS_HIGHER:
3060 case BFD_RELOC_MICROMIPS_SCN_DISP:
3061 case BFD_RELOC_MICROMIPS_JALR:
3069 static inline bfd_boolean
3070 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3072 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3075 static inline bfd_boolean
3076 got16_reloc_p (bfd_reloc_code_real_type reloc)
3078 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3079 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3082 static inline bfd_boolean
3083 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3085 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3086 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3089 static inline bfd_boolean
3090 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3092 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3093 || reloc == BFD_RELOC_MICROMIPS_LO16);
3096 static inline bfd_boolean
3097 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3099 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3102 static inline bfd_boolean
3103 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3105 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3106 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3109 /* Return true if RELOC is a PC-relative relocation that does not have
3110 full address range. */
3112 static inline bfd_boolean
3113 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3117 case BFD_RELOC_16_PCREL_S2:
3118 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3119 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3120 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3123 case BFD_RELOC_32_PCREL:
3124 return HAVE_64BIT_ADDRESSES;
3131 /* Return true if the given relocation might need a matching %lo().
3132 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3133 need a matching %lo() when applied to local symbols. */
3135 static inline bfd_boolean
3136 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3138 return (HAVE_IN_PLACE_ADDENDS
3139 && (hi16_reloc_p (reloc)
3140 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3141 all GOT16 relocations evaluate to "G". */
3142 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3145 /* Return the type of %lo() reloc needed by RELOC, given that
3146 reloc_needs_lo_p. */
3148 static inline bfd_reloc_code_real_type
3149 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3151 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3152 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3156 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3159 static inline bfd_boolean
3160 fixup_has_matching_lo_p (fixS *fixp)
3162 return (fixp->fx_next != NULL
3163 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3164 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3165 && fixp->fx_offset == fixp->fx_next->fx_offset);
3168 /* This function returns true if modifying a register requires a
3172 reg_needs_delay (unsigned int reg)
3174 unsigned long prev_pinfo;
3176 prev_pinfo = history[0].insn_mo->pinfo;
3177 if (! mips_opts.noreorder
3178 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
3179 && ! gpr_interlocks)
3180 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
3181 && ! cop_interlocks)))
3183 /* A load from a coprocessor or from memory. All load delays
3184 delay the use of general register rt for one instruction. */
3185 /* Itbl support may require additional care here. */
3186 know (prev_pinfo & INSN_WRITE_GPR_T);
3187 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
3194 /* Move all labels in LABELS to the current insertion point. TEXT_P
3195 says whether the labels refer to text or data. */
3198 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3200 struct insn_label_list *l;
3203 for (l = labels; l != NULL; l = l->next)
3205 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3206 symbol_set_frag (l->label, frag_now);
3207 val = (valueT) frag_now_fix ();
3208 /* MIPS16/microMIPS text labels are stored as odd. */
3209 if (text_p && HAVE_CODE_COMPRESSION)
3211 S_SET_VALUE (l->label, val);
3215 /* Move all labels in insn_labels to the current insertion point
3216 and treat them as text labels. */
3219 mips_move_text_labels (void)
3221 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3225 s_is_linkonce (symbolS *sym, segT from_seg)
3227 bfd_boolean linkonce = FALSE;
3228 segT symseg = S_GET_SEGMENT (sym);
3230 if (symseg != from_seg && !S_IS_LOCAL (sym))
3232 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3234 /* The GNU toolchain uses an extension for ELF: a section
3235 beginning with the magic string .gnu.linkonce is a
3236 linkonce section. */
3237 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3238 sizeof ".gnu.linkonce" - 1) == 0)
3244 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3245 linker to handle them specially, such as generating jalx instructions
3246 when needed. We also make them odd for the duration of the assembly,
3247 in order to generate the right sort of code. We will make them even
3248 in the adjust_symtab routine, while leaving them marked. This is
3249 convenient for the debugger and the disassembler. The linker knows
3250 to make them odd again. */
3253 mips_compressed_mark_label (symbolS *label)
3255 gas_assert (HAVE_CODE_COMPRESSION);
3257 if (mips_opts.mips16)
3258 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3260 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3261 if ((S_GET_VALUE (label) & 1) == 0
3262 /* Don't adjust the address if the label is global or weak, or
3263 in a link-once section, since we'll be emitting symbol reloc
3264 references to it which will be patched up by the linker, and
3265 the final value of the symbol may or may not be MIPS16/microMIPS. */
3266 && !S_IS_WEAK (label)
3267 && !S_IS_EXTERNAL (label)
3268 && !s_is_linkonce (label, now_seg))
3269 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3272 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3275 mips_compressed_mark_labels (void)
3277 struct insn_label_list *l;
3279 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3280 mips_compressed_mark_label (l->label);
3283 /* End the current frag. Make it a variant frag and record the
3287 relax_close_frag (void)
3289 mips_macro_warning.first_frag = frag_now;
3290 frag_var (rs_machine_dependent, 0, 0,
3291 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3292 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3294 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3295 mips_relax.first_fixup = 0;
3298 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3299 See the comment above RELAX_ENCODE for more details. */
3302 relax_start (symbolS *symbol)
3304 gas_assert (mips_relax.sequence == 0);
3305 mips_relax.sequence = 1;
3306 mips_relax.symbol = symbol;
3309 /* Start generating the second version of a relaxable sequence.
3310 See the comment above RELAX_ENCODE for more details. */
3315 gas_assert (mips_relax.sequence == 1);
3316 mips_relax.sequence = 2;
3319 /* End the current relaxable sequence. */
3324 gas_assert (mips_relax.sequence == 2);
3325 relax_close_frag ();
3326 mips_relax.sequence = 0;
3329 /* Return true if IP is a delayed branch or jump. */
3331 static inline bfd_boolean
3332 delayed_branch_p (const struct mips_cl_insn *ip)
3334 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3335 | INSN_COND_BRANCH_DELAY
3336 | INSN_COND_BRANCH_LIKELY)) != 0;
3339 /* Return true if IP is a compact branch or jump. */
3341 static inline bfd_boolean
3342 compact_branch_p (const struct mips_cl_insn *ip)
3344 if (mips_opts.mips16)
3345 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3346 | MIPS16_INSN_COND_BRANCH)) != 0;
3348 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3349 | INSN2_COND_BRANCH)) != 0;
3352 /* Return true if IP is an unconditional branch or jump. */
3354 static inline bfd_boolean
3355 uncond_branch_p (const struct mips_cl_insn *ip)
3357 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3358 || (mips_opts.mips16
3359 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3360 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3363 /* Return true if IP is a branch-likely instruction. */
3365 static inline bfd_boolean
3366 branch_likely_p (const struct mips_cl_insn *ip)
3368 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3371 /* Return the type of nop that should be used to fill the delay slot
3372 of delayed branch IP. */
3374 static struct mips_cl_insn *
3375 get_delay_slot_nop (const struct mips_cl_insn *ip)
3377 if (mips_opts.micromips
3378 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3379 return µmips_nop32_insn;
3383 /* Return the mask of core registers that IP reads or writes. */
3386 gpr_mod_mask (const struct mips_cl_insn *ip)
3388 unsigned long pinfo2;
3392 pinfo2 = ip->insn_mo->pinfo2;
3393 if (mips_opts.micromips)
3395 if (pinfo2 & INSN2_MOD_GPR_MD)
3396 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3397 if (pinfo2 & INSN2_MOD_GPR_MF)
3398 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3399 if (pinfo2 & INSN2_MOD_SP)
3405 /* Return the mask of core registers that IP reads. */
3408 gpr_read_mask (const struct mips_cl_insn *ip)
3410 unsigned long pinfo, pinfo2;
3413 mask = gpr_mod_mask (ip);
3414 pinfo = ip->insn_mo->pinfo;
3415 pinfo2 = ip->insn_mo->pinfo2;
3416 if (mips_opts.mips16)
3418 if (pinfo & MIPS16_INSN_READ_X)
3419 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3420 if (pinfo & MIPS16_INSN_READ_Y)
3421 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3422 if (pinfo & MIPS16_INSN_READ_T)
3424 if (pinfo & MIPS16_INSN_READ_SP)
3426 if (pinfo & MIPS16_INSN_READ_31)
3428 if (pinfo & MIPS16_INSN_READ_Z)
3429 mask |= 1 << (mips16_to_32_reg_map
3430 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3431 if (pinfo & MIPS16_INSN_READ_GPR_X)
3432 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3436 if (pinfo2 & INSN2_READ_GPR_D)
3437 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3438 if (pinfo & INSN_READ_GPR_T)
3439 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3440 if (pinfo & INSN_READ_GPR_S)
3441 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3442 if (pinfo2 & INSN2_READ_GP)
3444 if (pinfo2 & INSN2_READ_GPR_31)
3446 if (pinfo2 & INSN2_READ_GPR_Z)
3447 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3449 if (mips_opts.micromips)
3451 if (pinfo2 & INSN2_READ_GPR_MC)
3452 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3453 if (pinfo2 & INSN2_READ_GPR_ME)
3454 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3455 if (pinfo2 & INSN2_READ_GPR_MG)
3456 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3457 if (pinfo2 & INSN2_READ_GPR_MJ)
3458 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3459 if (pinfo2 & INSN2_READ_GPR_MMN)
3461 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3462 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3464 if (pinfo2 & INSN2_READ_GPR_MP)
3465 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3466 if (pinfo2 & INSN2_READ_GPR_MQ)
3467 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3469 /* Don't include register 0. */
3473 /* Return the mask of core registers that IP writes. */
3476 gpr_write_mask (const struct mips_cl_insn *ip)
3478 unsigned long pinfo, pinfo2;
3481 mask = gpr_mod_mask (ip);
3482 pinfo = ip->insn_mo->pinfo;
3483 pinfo2 = ip->insn_mo->pinfo2;
3484 if (mips_opts.mips16)
3486 if (pinfo & MIPS16_INSN_WRITE_X)
3487 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3488 if (pinfo & MIPS16_INSN_WRITE_Y)
3489 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3490 if (pinfo & MIPS16_INSN_WRITE_Z)
3491 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3492 if (pinfo & MIPS16_INSN_WRITE_T)
3494 if (pinfo & MIPS16_INSN_WRITE_SP)
3496 if (pinfo & MIPS16_INSN_WRITE_31)
3498 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3499 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3503 if (pinfo & INSN_WRITE_GPR_D)
3504 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3505 if (pinfo & INSN_WRITE_GPR_T)
3506 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3507 if (pinfo & INSN_WRITE_GPR_S)
3508 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3509 if (pinfo & INSN_WRITE_GPR_31)
3511 if (pinfo2 & INSN2_WRITE_GPR_Z)
3512 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3514 if (mips_opts.micromips)
3516 if (pinfo2 & INSN2_WRITE_GPR_MB)
3517 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3518 if (pinfo2 & INSN2_WRITE_GPR_MH)
3520 mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
3521 mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
3523 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3524 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3525 if (pinfo2 & INSN2_WRITE_GPR_MP)
3526 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3528 /* Don't include register 0. */
3532 /* Return the mask of floating-point registers that IP reads. */
3535 fpr_read_mask (const struct mips_cl_insn *ip)
3537 unsigned long pinfo, pinfo2;
3541 pinfo = ip->insn_mo->pinfo;
3542 pinfo2 = ip->insn_mo->pinfo2;
3543 if (!mips_opts.mips16)
3545 if (pinfo2 & INSN2_READ_FPR_D)
3546 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3547 if (pinfo & INSN_READ_FPR_S)
3548 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3549 if (pinfo & INSN_READ_FPR_T)
3550 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3551 if (pinfo & INSN_READ_FPR_R)
3552 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3553 if (pinfo2 & INSN2_READ_FPR_Z)
3554 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3556 /* Conservatively treat all operands to an FP_D instruction are doubles.
3557 (This is overly pessimistic for things like cvt.d.s.) */
3558 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3563 /* Return the mask of floating-point registers that IP writes. */
3566 fpr_write_mask (const struct mips_cl_insn *ip)
3568 unsigned long pinfo, pinfo2;
3572 pinfo = ip->insn_mo->pinfo;
3573 pinfo2 = ip->insn_mo->pinfo2;
3574 if (!mips_opts.mips16)
3576 if (pinfo & INSN_WRITE_FPR_D)
3577 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3578 if (pinfo & INSN_WRITE_FPR_S)
3579 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3580 if (pinfo & INSN_WRITE_FPR_T)
3581 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3582 if (pinfo2 & INSN2_WRITE_FPR_Z)
3583 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3585 /* Conservatively treat all operands to an FP_D instruction are doubles.
3586 (This is overly pessimistic for things like cvt.s.d.) */
3587 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3592 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3593 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3594 by VR4120 errata. */
3597 classify_vr4120_insn (const char *name)
3599 if (strncmp (name, "macc", 4) == 0)
3600 return FIX_VR4120_MACC;
3601 if (strncmp (name, "dmacc", 5) == 0)
3602 return FIX_VR4120_DMACC;
3603 if (strncmp (name, "mult", 4) == 0)
3604 return FIX_VR4120_MULT;
3605 if (strncmp (name, "dmult", 5) == 0)
3606 return FIX_VR4120_DMULT;
3607 if (strstr (name, "div"))
3608 return FIX_VR4120_DIV;
3609 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3610 return FIX_VR4120_MTHILO;
3611 return NUM_FIX_VR4120_CLASSES;
3614 #define INSN_ERET 0x42000018
3615 #define INSN_DERET 0x4200001f
3617 /* Return the number of instructions that must separate INSN1 and INSN2,
3618 where INSN1 is the earlier instruction. Return the worst-case value
3619 for any INSN2 if INSN2 is null. */
3622 insns_between (const struct mips_cl_insn *insn1,
3623 const struct mips_cl_insn *insn2)
3625 unsigned long pinfo1, pinfo2;
3628 /* This function needs to know which pinfo flags are set for INSN2
3629 and which registers INSN2 uses. The former is stored in PINFO2 and
3630 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3631 will have every flag set and INSN2_USES_GPR will always return true. */
3632 pinfo1 = insn1->insn_mo->pinfo;
3633 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3635 #define INSN2_USES_GPR(REG) \
3636 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3638 /* For most targets, write-after-read dependencies on the HI and LO
3639 registers must be separated by at least two instructions. */
3640 if (!hilo_interlocks)
3642 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3644 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3648 /* If we're working around r7000 errata, there must be two instructions
3649 between an mfhi or mflo and any instruction that uses the result. */
3650 if (mips_7000_hilo_fix
3651 && !mips_opts.micromips
3652 && MF_HILO_INSN (pinfo1)
3653 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3656 /* If we're working around 24K errata, one instruction is required
3657 if an ERET or DERET is followed by a branch instruction. */
3658 if (mips_fix_24k && !mips_opts.micromips)
3660 if (insn1->insn_opcode == INSN_ERET
3661 || insn1->insn_opcode == INSN_DERET)
3664 || insn2->insn_opcode == INSN_ERET
3665 || insn2->insn_opcode == INSN_DERET
3666 || delayed_branch_p (insn2))
3671 /* If working around VR4120 errata, check for combinations that need
3672 a single intervening instruction. */
3673 if (mips_fix_vr4120 && !mips_opts.micromips)
3675 unsigned int class1, class2;
3677 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3678 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3682 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3683 if (vr4120_conflicts[class1] & (1 << class2))
3688 if (!HAVE_CODE_COMPRESSION)
3690 /* Check for GPR or coprocessor load delays. All such delays
3691 are on the RT register. */
3692 /* Itbl support may require additional care here. */
3693 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3694 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3696 know (pinfo1 & INSN_WRITE_GPR_T);
3697 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3701 /* Check for generic coprocessor hazards.
3703 This case is not handled very well. There is no special
3704 knowledge of CP0 handling, and the coprocessors other than
3705 the floating point unit are not distinguished at all. */
3706 /* Itbl support may require additional care here. FIXME!
3707 Need to modify this to include knowledge about
3708 user specified delays! */
3709 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3710 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3712 /* Handle cases where INSN1 writes to a known general coprocessor
3713 register. There must be a one instruction delay before INSN2
3714 if INSN2 reads that register, otherwise no delay is needed. */
3715 mask = fpr_write_mask (insn1);
3718 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3723 /* Read-after-write dependencies on the control registers
3724 require a two-instruction gap. */
3725 if ((pinfo1 & INSN_WRITE_COND_CODE)
3726 && (pinfo2 & INSN_READ_COND_CODE))
3729 /* We don't know exactly what INSN1 does. If INSN2 is
3730 also a coprocessor instruction, assume there must be
3731 a one instruction gap. */
3732 if (pinfo2 & INSN_COP)
3737 /* Check for read-after-write dependencies on the coprocessor
3738 control registers in cases where INSN1 does not need a general
3739 coprocessor delay. This means that INSN1 is a floating point
3740 comparison instruction. */
3741 /* Itbl support may require additional care here. */
3742 else if (!cop_interlocks
3743 && (pinfo1 & INSN_WRITE_COND_CODE)
3744 && (pinfo2 & INSN_READ_COND_CODE))
3748 #undef INSN2_USES_GPR
3753 /* Return the number of nops that would be needed to work around the
3754 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3755 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3756 that are contained within the first IGNORE instructions of HIST. */
3759 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3760 const struct mips_cl_insn *insn)
3765 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3766 are not affected by the errata. */
3768 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3769 || strcmp (insn->insn_mo->name, "mtlo") == 0
3770 || strcmp (insn->insn_mo->name, "mthi") == 0))
3773 /* Search for the first MFLO or MFHI. */
3774 for (i = 0; i < MAX_VR4130_NOPS; i++)
3775 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3777 /* Extract the destination register. */
3778 mask = gpr_write_mask (&hist[i]);
3780 /* No nops are needed if INSN reads that register. */
3781 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3784 /* ...or if any of the intervening instructions do. */
3785 for (j = 0; j < i; j++)
3786 if (gpr_read_mask (&hist[j]) & mask)
3790 return MAX_VR4130_NOPS - i;
3795 #define BASE_REG_EQ(INSN1, INSN2) \
3796 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3797 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3799 /* Return the minimum alignment for this store instruction. */
3802 fix_24k_align_to (const struct mips_opcode *mo)
3804 if (strcmp (mo->name, "sh") == 0)
3807 if (strcmp (mo->name, "swc1") == 0
3808 || strcmp (mo->name, "swc2") == 0
3809 || strcmp (mo->name, "sw") == 0
3810 || strcmp (mo->name, "sc") == 0
3811 || strcmp (mo->name, "s.s") == 0)
3814 if (strcmp (mo->name, "sdc1") == 0
3815 || strcmp (mo->name, "sdc2") == 0
3816 || strcmp (mo->name, "s.d") == 0)
3823 struct fix_24k_store_info
3825 /* Immediate offset, if any, for this store instruction. */
3827 /* Alignment required by this store instruction. */
3829 /* True for register offsets. */
3830 int register_offset;
3833 /* Comparison function used by qsort. */
3836 fix_24k_sort (const void *a, const void *b)
3838 const struct fix_24k_store_info *pos1 = a;
3839 const struct fix_24k_store_info *pos2 = b;
3841 return (pos1->off - pos2->off);
3844 /* INSN is a store instruction. Try to record the store information
3845 in STINFO. Return false if the information isn't known. */
3848 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3849 const struct mips_cl_insn *insn)
3851 /* The instruction must have a known offset. */
3852 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3855 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3856 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3860 /* Return the number of nops that would be needed to work around the 24k
3861 "lost data on stores during refill" errata if instruction INSN
3862 immediately followed the 2 instructions described by HIST.
3863 Ignore hazards that are contained within the first IGNORE
3864 instructions of HIST.
3866 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3867 for the data cache refills and store data. The following describes
3868 the scenario where the store data could be lost.
3870 * A data cache miss, due to either a load or a store, causing fill
3871 data to be supplied by the memory subsystem
3872 * The first three doublewords of fill data are returned and written
3874 * A sequence of four stores occurs in consecutive cycles around the
3875 final doubleword of the fill:
3879 * Zero, One or more instructions
3882 The four stores A-D must be to different doublewords of the line that
3883 is being filled. The fourth instruction in the sequence above permits
3884 the fill of the final doubleword to be transferred from the FSB into
3885 the cache. In the sequence above, the stores may be either integer
3886 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3887 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3888 different doublewords on the line. If the floating point unit is
3889 running in 1:2 mode, it is not possible to create the sequence above
3890 using only floating point store instructions.
3892 In this case, the cache line being filled is incorrectly marked
3893 invalid, thereby losing the data from any store to the line that
3894 occurs between the original miss and the completion of the five
3895 cycle sequence shown above.
3897 The workarounds are:
3899 * Run the data cache in write-through mode.
3900 * Insert a non-store instruction between
3901 Store A and Store B or Store B and Store C. */
3904 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3905 const struct mips_cl_insn *insn)
3907 struct fix_24k_store_info pos[3];
3908 int align, i, base_offset;
3913 /* If the previous instruction wasn't a store, there's nothing to
3915 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3918 /* If the instructions after the previous one are unknown, we have
3919 to assume the worst. */
3923 /* Check whether we are dealing with three consecutive stores. */
3924 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3925 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3928 /* If we don't know the relationship between the store addresses,
3929 assume the worst. */
3930 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3931 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3934 if (!fix_24k_record_store_info (&pos[0], insn)
3935 || !fix_24k_record_store_info (&pos[1], &hist[0])
3936 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3939 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3941 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3942 X bytes and such that the base register + X is known to be aligned
3945 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3949 align = pos[0].align_to;
3950 base_offset = pos[0].off;
3951 for (i = 1; i < 3; i++)
3952 if (align < pos[i].align_to)
3954 align = pos[i].align_to;
3955 base_offset = pos[i].off;
3957 for (i = 0; i < 3; i++)
3958 pos[i].off -= base_offset;
3961 pos[0].off &= ~align + 1;
3962 pos[1].off &= ~align + 1;
3963 pos[2].off &= ~align + 1;
3965 /* If any two stores write to the same chunk, they also write to the
3966 same doubleword. The offsets are still sorted at this point. */
3967 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3970 /* A range of at least 9 bytes is needed for the stores to be in
3971 non-overlapping doublewords. */
3972 if (pos[2].off - pos[0].off <= 8)
3975 if (pos[2].off - pos[1].off >= 24
3976 || pos[1].off - pos[0].off >= 24
3977 || pos[2].off - pos[0].off >= 32)
3983 /* Return the number of nops that would be needed if instruction INSN
3984 immediately followed the MAX_NOPS instructions given by HIST,
3985 where HIST[0] is the most recent instruction. Ignore hazards
3986 between INSN and the first IGNORE instructions in HIST.
3988 If INSN is null, return the worse-case number of nops for any
3992 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3993 const struct mips_cl_insn *insn)
3995 int i, nops, tmp_nops;
3998 for (i = ignore; i < MAX_DELAY_NOPS; i++)
4000 tmp_nops = insns_between (hist + i, insn) - i;
4001 if (tmp_nops > nops)
4005 if (mips_fix_vr4130 && !mips_opts.micromips)
4007 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
4008 if (tmp_nops > nops)
4012 if (mips_fix_24k && !mips_opts.micromips)
4014 tmp_nops = nops_for_24k (ignore, hist, insn);
4015 if (tmp_nops > nops)
4022 /* The variable arguments provide NUM_INSNS extra instructions that
4023 might be added to HIST. Return the largest number of nops that
4024 would be needed after the extended sequence, ignoring hazards
4025 in the first IGNORE instructions. */
4028 nops_for_sequence (int num_insns, int ignore,
4029 const struct mips_cl_insn *hist, ...)
4032 struct mips_cl_insn buffer[MAX_NOPS];
4033 struct mips_cl_insn *cursor;
4036 va_start (args, hist);
4037 cursor = buffer + num_insns;
4038 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
4039 while (cursor > buffer)
4040 *--cursor = *va_arg (args, const struct mips_cl_insn *);
4042 nops = nops_for_insn (ignore, buffer, NULL);
4047 /* Like nops_for_insn, but if INSN is a branch, take into account the
4048 worst-case delay for the branch target. */
4051 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
4052 const struct mips_cl_insn *insn)
4056 nops = nops_for_insn (ignore, hist, insn);
4057 if (delayed_branch_p (insn))
4059 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
4060 hist, insn, get_delay_slot_nop (insn));
4061 if (tmp_nops > nops)
4064 else if (compact_branch_p (insn))
4066 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
4067 if (tmp_nops > nops)
4073 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4076 fix_loongson2f_nop (struct mips_cl_insn * ip)
4078 gas_assert (!HAVE_CODE_COMPRESSION);
4079 if (strcmp (ip->insn_mo->name, "nop") == 0)
4080 ip->insn_opcode = LOONGSON2F_NOP_INSN;
4083 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4084 jr target pc &= 'hffff_ffff_cfff_ffff. */
4087 fix_loongson2f_jump (struct mips_cl_insn * ip)
4089 gas_assert (!HAVE_CODE_COMPRESSION);
4090 if (strcmp (ip->insn_mo->name, "j") == 0
4091 || strcmp (ip->insn_mo->name, "jr") == 0
4092 || strcmp (ip->insn_mo->name, "jalr") == 0)
4100 sreg = EXTRACT_OPERAND (0, RS, *ip);
4101 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
4104 ep.X_op = O_constant;
4105 ep.X_add_number = 0xcfff0000;
4106 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
4107 ep.X_add_number = 0xffff;
4108 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
4109 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
4114 fix_loongson2f (struct mips_cl_insn * ip)
4116 if (mips_fix_loongson2f_nop)
4117 fix_loongson2f_nop (ip);
4119 if (mips_fix_loongson2f_jump)
4120 fix_loongson2f_jump (ip);
4123 /* IP is a branch that has a delay slot, and we need to fill it
4124 automatically. Return true if we can do that by swapping IP
4125 with the previous instruction.
4126 ADDRESS_EXPR is an operand of the instruction to be used with
4130 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
4131 bfd_reloc_code_real_type *reloc_type)
4133 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
4134 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
4136 /* -O2 and above is required for this optimization. */
4137 if (mips_optimize < 2)
4140 /* If we have seen .set volatile or .set nomove, don't optimize. */
4141 if (mips_opts.nomove)
4144 /* We can't swap if the previous instruction's position is fixed. */
4145 if (history[0].fixed_p)
4148 /* If the previous previous insn was in a .set noreorder, we can't
4149 swap. Actually, the MIPS assembler will swap in this situation.
4150 However, gcc configured -with-gnu-as will generate code like
4158 in which we can not swap the bne and INSN. If gcc is not configured
4159 -with-gnu-as, it does not output the .set pseudo-ops. */
4160 if (history[1].noreorder_p)
4163 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4164 This means that the previous instruction was a 4-byte one anyhow. */
4165 if (mips_opts.mips16 && history[0].fixp[0])
4168 /* If the branch is itself the target of a branch, we can not swap.
4169 We cheat on this; all we check for is whether there is a label on
4170 this instruction. If there are any branches to anything other than
4171 a label, users must use .set noreorder. */
4172 if (seg_info (now_seg)->label_list)
4175 /* If the previous instruction is in a variant frag other than this
4176 branch's one, we cannot do the swap. This does not apply to
4177 MIPS16 code, which uses variant frags for different purposes. */
4178 if (!mips_opts.mips16
4180 && history[0].frag->fr_type == rs_machine_dependent)
4183 /* We do not swap with instructions that cannot architecturally
4184 be placed in a branch delay slot, such as SYNC or ERET. We
4185 also refrain from swapping with a trap instruction, since it
4186 complicates trap handlers to have the trap instruction be in
4188 prev_pinfo = history[0].insn_mo->pinfo;
4189 if (prev_pinfo & INSN_NO_DELAY_SLOT)
4192 /* Check for conflicts between the branch and the instructions
4193 before the candidate delay slot. */
4194 if (nops_for_insn (0, history + 1, ip) > 0)
4197 /* Check for conflicts between the swapped sequence and the
4198 target of the branch. */
4199 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
4202 /* If the branch reads a register that the previous
4203 instruction sets, we can not swap. */
4204 gpr_read = gpr_read_mask (ip);
4205 prev_gpr_write = gpr_write_mask (&history[0]);
4206 if (gpr_read & prev_gpr_write)
4209 /* If the branch writes a register that the previous
4210 instruction sets, we can not swap. */
4211 gpr_write = gpr_write_mask (ip);
4212 if (gpr_write & prev_gpr_write)
4215 /* If the branch writes a register that the previous
4216 instruction reads, we can not swap. */
4217 prev_gpr_read = gpr_read_mask (&history[0]);
4218 if (gpr_write & prev_gpr_read)
4221 /* If one instruction sets a condition code and the
4222 other one uses a condition code, we can not swap. */
4223 pinfo = ip->insn_mo->pinfo;
4224 if ((pinfo & INSN_READ_COND_CODE)
4225 && (prev_pinfo & INSN_WRITE_COND_CODE))
4227 if ((pinfo & INSN_WRITE_COND_CODE)
4228 && (prev_pinfo & INSN_READ_COND_CODE))
4231 /* If the previous instruction uses the PC, we can not swap. */
4232 prev_pinfo2 = history[0].insn_mo->pinfo2;
4233 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
4235 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
4238 /* If the previous instruction has an incorrect size for a fixed
4239 branch delay slot in microMIPS mode, we cannot swap. */
4240 pinfo2 = ip->insn_mo->pinfo2;
4241 if (mips_opts.micromips
4242 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
4243 && insn_length (history) != 2)
4245 if (mips_opts.micromips
4246 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
4247 && insn_length (history) != 4)
4250 /* On R5900 short loops need to be fixed by inserting a nop in
4251 the branch delay slots.
4252 A short loop can be terminated too early. */
4253 if (mips_opts.arch == CPU_R5900
4254 /* Check if instruction has a parameter, ignore "j $31". */
4255 && (address_expr != NULL)
4256 /* Parameter must be 16 bit. */
4257 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
4258 /* Branch to same segment. */
4259 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
4260 /* Branch to same code fragment. */
4261 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
4262 /* Can only calculate branch offset if value is known. */
4263 && symbol_constant_p(address_expr->X_add_symbol)
4264 /* Check if branch is really conditional. */
4265 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
4266 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
4267 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
4270 /* Check if loop is shorter than 6 instructions including
4271 branch and delay slot. */
4272 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
4279 /* When the loop includes branches or jumps,
4280 it is not a short loop. */
4281 for (i = 0; i < (distance / 4); i++)
4283 if ((history[i].cleared_p)
4284 || delayed_branch_p(&history[i]))
4292 /* Insert nop after branch to fix short loop. */
4301 /* Decide how we should add IP to the instruction stream.
4302 ADDRESS_EXPR is an operand of the instruction to be used with
4305 static enum append_method
4306 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
4307 bfd_reloc_code_real_type *reloc_type)
4309 unsigned long pinfo;
4311 /* The relaxed version of a macro sequence must be inherently
4313 if (mips_relax.sequence == 2)
4316 /* We must not dabble with instructions in a ".set norerorder" block. */
4317 if (mips_opts.noreorder)
4320 /* Otherwise, it's our responsibility to fill branch delay slots. */
4321 if (delayed_branch_p (ip))
4323 if (!branch_likely_p (ip)
4324 && can_swap_branch_p (ip, address_expr, reloc_type))
4327 pinfo = ip->insn_mo->pinfo;
4328 if (mips_opts.mips16
4329 && ISA_SUPPORTS_MIPS16E
4330 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
4331 return APPEND_ADD_COMPACT;
4333 return APPEND_ADD_WITH_NOP;
4339 /* IP is a MIPS16 instruction whose opcode we have just changed.
4340 Point IP->insn_mo to the new opcode's definition. */
4343 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4345 const struct mips_opcode *mo, *end;
4347 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4348 for (mo = ip->insn_mo; mo < end; mo++)
4349 if ((ip->insn_opcode & mo->mask) == mo->match)
4357 /* For microMIPS macros, we need to generate a local number label
4358 as the target of branches. */
4359 #define MICROMIPS_LABEL_CHAR '\037'
4360 static unsigned long micromips_target_label;
4361 static char micromips_target_name[32];
4364 micromips_label_name (void)
4366 char *p = micromips_target_name;
4367 char symbol_name_temporary[24];
4375 l = micromips_target_label;
4376 #ifdef LOCAL_LABEL_PREFIX
4377 *p++ = LOCAL_LABEL_PREFIX;
4380 *p++ = MICROMIPS_LABEL_CHAR;
4383 symbol_name_temporary[i++] = l % 10 + '0';
4388 *p++ = symbol_name_temporary[--i];
4391 return micromips_target_name;
4395 micromips_label_expr (expressionS *label_expr)
4397 label_expr->X_op = O_symbol;
4398 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4399 label_expr->X_add_number = 0;
4403 micromips_label_inc (void)
4405 micromips_target_label++;
4406 *micromips_target_name = '\0';
4410 micromips_add_label (void)
4414 s = colon (micromips_label_name ());
4415 micromips_label_inc ();
4416 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4419 /* If assembling microMIPS code, then return the microMIPS reloc
4420 corresponding to the requested one if any. Otherwise return
4421 the reloc unchanged. */
4423 static bfd_reloc_code_real_type
4424 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4426 static const bfd_reloc_code_real_type relocs[][2] =
4428 /* Keep sorted incrementally by the left-hand key. */
4429 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4430 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4431 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4432 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4433 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4434 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4435 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4436 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4437 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4438 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4439 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4440 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4441 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4442 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4443 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4444 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4445 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4446 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4447 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4448 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4449 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4450 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4451 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4452 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4453 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4454 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4455 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4457 bfd_reloc_code_real_type r;
4460 if (!mips_opts.micromips)
4462 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4468 return relocs[i][1];
4473 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4474 Return true on success, storing the resolved value in RESULT. */
4477 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4482 case BFD_RELOC_MIPS_HIGHEST:
4483 case BFD_RELOC_MICROMIPS_HIGHEST:
4484 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4487 case BFD_RELOC_MIPS_HIGHER:
4488 case BFD_RELOC_MICROMIPS_HIGHER:
4489 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4492 case BFD_RELOC_HI16_S:
4493 case BFD_RELOC_MICROMIPS_HI16_S:
4494 case BFD_RELOC_MIPS16_HI16_S:
4495 *result = ((operand + 0x8000) >> 16) & 0xffff;
4498 case BFD_RELOC_HI16:
4499 case BFD_RELOC_MICROMIPS_HI16:
4500 case BFD_RELOC_MIPS16_HI16:
4501 *result = (operand >> 16) & 0xffff;
4504 case BFD_RELOC_LO16:
4505 case BFD_RELOC_MICROMIPS_LO16:
4506 case BFD_RELOC_MIPS16_LO16:
4507 *result = operand & 0xffff;
4510 case BFD_RELOC_UNUSED:
4519 /* Output an instruction. IP is the instruction information.
4520 ADDRESS_EXPR is an operand of the instruction to be used with
4521 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4522 a macro expansion. */
4525 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4526 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4528 unsigned long prev_pinfo2, pinfo;
4529 bfd_boolean relaxed_branch = FALSE;
4530 enum append_method method;
4531 bfd_boolean relax32;
4534 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4535 fix_loongson2f (ip);
4537 file_ase_mips16 |= mips_opts.mips16;
4538 file_ase_micromips |= mips_opts.micromips;
4540 prev_pinfo2 = history[0].insn_mo->pinfo2;
4541 pinfo = ip->insn_mo->pinfo;
4543 if (mips_opts.micromips
4545 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4546 && micromips_insn_length (ip->insn_mo) != 2)
4547 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4548 && micromips_insn_length (ip->insn_mo) != 4)))
4549 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4550 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4552 if (address_expr == NULL)
4554 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4555 && reloc_type[1] == BFD_RELOC_UNUSED
4556 && reloc_type[2] == BFD_RELOC_UNUSED
4557 && address_expr->X_op == O_constant)
4559 switch (*reloc_type)
4561 case BFD_RELOC_MIPS_JMP:
4565 shift = mips_opts.micromips ? 1 : 2;
4566 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4567 as_bad (_("jump to misaligned address (0x%lx)"),
4568 (unsigned long) address_expr->X_add_number);
4569 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4575 case BFD_RELOC_MIPS16_JMP:
4576 if ((address_expr->X_add_number & 3) != 0)
4577 as_bad (_("jump to misaligned address (0x%lx)"),
4578 (unsigned long) address_expr->X_add_number);
4580 (((address_expr->X_add_number & 0x7c0000) << 3)
4581 | ((address_expr->X_add_number & 0xf800000) >> 7)
4582 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4586 case BFD_RELOC_16_PCREL_S2:
4590 shift = mips_opts.micromips ? 1 : 2;
4591 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4592 as_bad (_("branch to misaligned address (0x%lx)"),
4593 (unsigned long) address_expr->X_add_number);
4594 if (!mips_relax_branch)
4596 if ((address_expr->X_add_number + (1 << (shift + 15)))
4597 & ~((1 << (shift + 16)) - 1))
4598 as_bad (_("branch address range overflow (0x%lx)"),
4599 (unsigned long) address_expr->X_add_number);
4600 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4610 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4613 ip->insn_opcode |= value & 0xffff;
4621 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4623 /* There are a lot of optimizations we could do that we don't.
4624 In particular, we do not, in general, reorder instructions.
4625 If you use gcc with optimization, it will reorder
4626 instructions and generally do much more optimization then we
4627 do here; repeating all that work in the assembler would only
4628 benefit hand written assembly code, and does not seem worth
4630 int nops = (mips_optimize == 0
4631 ? nops_for_insn (0, history, NULL)
4632 : nops_for_insn_or_target (0, history, ip));
4636 unsigned long old_frag_offset;
4639 old_frag = frag_now;
4640 old_frag_offset = frag_now_fix ();
4642 for (i = 0; i < nops; i++)
4643 add_fixed_insn (NOP_INSN);
4644 insert_into_history (0, nops, NOP_INSN);
4648 listing_prev_line ();
4649 /* We may be at the start of a variant frag. In case we
4650 are, make sure there is enough space for the frag
4651 after the frags created by listing_prev_line. The
4652 argument to frag_grow here must be at least as large
4653 as the argument to all other calls to frag_grow in
4654 this file. We don't have to worry about being in the
4655 middle of a variant frag, because the variants insert
4656 all needed nop instructions themselves. */
4660 mips_move_text_labels ();
4662 #ifndef NO_ECOFF_DEBUGGING
4663 if (ECOFF_DEBUGGING)
4664 ecoff_fix_loc (old_frag, old_frag_offset);
4668 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4672 /* Work out how many nops in prev_nop_frag are needed by IP,
4673 ignoring hazards generated by the first prev_nop_frag_since
4675 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4676 gas_assert (nops <= prev_nop_frag_holds);
4678 /* Enforce NOPS as a minimum. */
4679 if (nops > prev_nop_frag_required)
4680 prev_nop_frag_required = nops;
4682 if (prev_nop_frag_holds == prev_nop_frag_required)
4684 /* Settle for the current number of nops. Update the history
4685 accordingly (for the benefit of any future .set reorder code). */
4686 prev_nop_frag = NULL;
4687 insert_into_history (prev_nop_frag_since,
4688 prev_nop_frag_holds, NOP_INSN);
4692 /* Allow this instruction to replace one of the nops that was
4693 tentatively added to prev_nop_frag. */
4694 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4695 prev_nop_frag_holds--;
4696 prev_nop_frag_since++;
4700 method = get_append_method (ip, address_expr, reloc_type);
4701 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4703 dwarf2_emit_insn (0);
4704 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4705 so "move" the instruction address accordingly.
4707 Also, it doesn't seem appropriate for the assembler to reorder .loc
4708 entries. If this instruction is a branch that we are going to swap
4709 with the previous instruction, the two instructions should be
4710 treated as a unit, and the debug information for both instructions
4711 should refer to the start of the branch sequence. Using the
4712 current position is certainly wrong when swapping a 32-bit branch
4713 and a 16-bit delay slot, since the current position would then be
4714 in the middle of a branch. */
4715 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
4717 relax32 = (mips_relax_branch
4718 /* Don't try branch relaxation within .set nomacro, or within
4719 .set noat if we use $at for PIC computations. If it turns
4720 out that the branch was out-of-range, we'll get an error. */
4721 && !mips_opts.warn_about_macros
4722 && (mips_opts.at || mips_pic == NO_PIC)
4723 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4724 as they have no complementing branches. */
4725 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4727 if (!HAVE_CODE_COMPRESSION
4730 && *reloc_type == BFD_RELOC_16_PCREL_S2
4731 && delayed_branch_p (ip))
4733 relaxed_branch = TRUE;
4734 add_relaxed_insn (ip, (relaxed_branch_length
4736 uncond_branch_p (ip) ? -1
4737 : branch_likely_p (ip) ? 1
4741 uncond_branch_p (ip),
4742 branch_likely_p (ip),
4743 pinfo & INSN_WRITE_GPR_31,
4745 address_expr->X_add_symbol,
4746 address_expr->X_add_number);
4747 *reloc_type = BFD_RELOC_UNUSED;
4749 else if (mips_opts.micromips
4751 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4752 || *reloc_type > BFD_RELOC_UNUSED)
4753 && (delayed_branch_p (ip) || compact_branch_p (ip))
4754 /* Don't try branch relaxation when users specify
4755 16-bit/32-bit instructions. */
4756 && !forced_insn_length)
4758 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4759 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4760 int uncond = uncond_branch_p (ip) ? -1 : 0;
4761 int compact = compact_branch_p (ip);
4762 int al = pinfo & INSN_WRITE_GPR_31;
4765 gas_assert (address_expr != NULL);
4766 gas_assert (!mips_relax.sequence);
4768 relaxed_branch = TRUE;
4769 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4770 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4771 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4773 address_expr->X_add_symbol,
4774 address_expr->X_add_number);
4775 *reloc_type = BFD_RELOC_UNUSED;
4777 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4779 /* We need to set up a variant frag. */
4780 gas_assert (address_expr != NULL);
4781 add_relaxed_insn (ip, 4, 0,
4783 (*reloc_type - BFD_RELOC_UNUSED,
4784 forced_insn_length == 2, forced_insn_length == 4,
4785 delayed_branch_p (&history[0]),
4786 history[0].mips16_absolute_jump_p),
4787 make_expr_symbol (address_expr), 0);
4789 else if (mips_opts.mips16 && insn_length (ip) == 2)
4791 if (!delayed_branch_p (ip))
4792 /* Make sure there is enough room to swap this instruction with
4793 a following jump instruction. */
4795 add_fixed_insn (ip);
4799 if (mips_opts.mips16
4800 && mips_opts.noreorder
4801 && delayed_branch_p (&history[0]))
4802 as_warn (_("extended instruction in delay slot"));
4804 if (mips_relax.sequence)
4806 /* If we've reached the end of this frag, turn it into a variant
4807 frag and record the information for the instructions we've
4809 if (frag_room () < 4)
4810 relax_close_frag ();
4811 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4814 if (mips_relax.sequence != 2)
4816 if (mips_macro_warning.first_insn_sizes[0] == 0)
4817 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4818 mips_macro_warning.sizes[0] += insn_length (ip);
4819 mips_macro_warning.insns[0]++;
4821 if (mips_relax.sequence != 1)
4823 if (mips_macro_warning.first_insn_sizes[1] == 0)
4824 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4825 mips_macro_warning.sizes[1] += insn_length (ip);
4826 mips_macro_warning.insns[1]++;
4829 if (mips_opts.mips16)
4832 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4834 add_fixed_insn (ip);
4837 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4839 bfd_reloc_code_real_type final_type[3];
4840 reloc_howto_type *howto0;
4841 reloc_howto_type *howto;
4844 /* Perform any necessary conversion to microMIPS relocations
4845 and find out how many relocations there actually are. */
4846 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4847 final_type[i] = micromips_map_reloc (reloc_type[i]);
4849 /* In a compound relocation, it is the final (outermost)
4850 operator that determines the relocated field. */
4851 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4856 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4857 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4858 bfd_get_reloc_size (howto),
4860 howto0 && howto0->pc_relative,
4863 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4864 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4865 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4867 /* These relocations can have an addend that won't fit in
4868 4 octets for 64bit assembly. */
4870 && ! howto->partial_inplace
4871 && (reloc_type[0] == BFD_RELOC_16
4872 || reloc_type[0] == BFD_RELOC_32
4873 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4874 || reloc_type[0] == BFD_RELOC_GPREL16
4875 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4876 || reloc_type[0] == BFD_RELOC_GPREL32
4877 || reloc_type[0] == BFD_RELOC_64
4878 || reloc_type[0] == BFD_RELOC_CTOR
4879 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4880 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4881 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4882 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4883 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4884 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4885 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4886 || hi16_reloc_p (reloc_type[0])
4887 || lo16_reloc_p (reloc_type[0])))
4888 ip->fixp[0]->fx_no_overflow = 1;
4890 /* These relocations can have an addend that won't fit in 2 octets. */
4891 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4892 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4893 ip->fixp[0]->fx_no_overflow = 1;
4895 if (mips_relax.sequence)
4897 if (mips_relax.first_fixup == 0)
4898 mips_relax.first_fixup = ip->fixp[0];
4900 else if (reloc_needs_lo_p (*reloc_type))
4902 struct mips_hi_fixup *hi_fixup;
4904 /* Reuse the last entry if it already has a matching %lo. */
4905 hi_fixup = mips_hi_fixup_list;
4907 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4909 hi_fixup = ((struct mips_hi_fixup *)
4910 xmalloc (sizeof (struct mips_hi_fixup)));
4911 hi_fixup->next = mips_hi_fixup_list;
4912 mips_hi_fixup_list = hi_fixup;
4914 hi_fixup->fixp = ip->fixp[0];
4915 hi_fixup->seg = now_seg;
4918 /* Add fixups for the second and third relocations, if given.
4919 Note that the ABI allows the second relocation to be
4920 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4921 moment we only use RSS_UNDEF, but we could add support
4922 for the others if it ever becomes necessary. */
4923 for (i = 1; i < 3; i++)
4924 if (reloc_type[i] != BFD_RELOC_UNUSED)
4926 ip->fixp[i] = fix_new (ip->frag, ip->where,
4927 ip->fixp[0]->fx_size, NULL, 0,
4928 FALSE, final_type[i]);
4930 /* Use fx_tcbit to mark compound relocs. */
4931 ip->fixp[0]->fx_tcbit = 1;
4932 ip->fixp[i]->fx_tcbit = 1;
4937 /* Update the register mask information. */
4938 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4939 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4944 insert_into_history (0, 1, ip);
4947 case APPEND_ADD_WITH_NOP:
4949 struct mips_cl_insn *nop;
4951 insert_into_history (0, 1, ip);
4952 nop = get_delay_slot_nop (ip);
4953 add_fixed_insn (nop);
4954 insert_into_history (0, 1, nop);
4955 if (mips_relax.sequence)
4956 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4960 case APPEND_ADD_COMPACT:
4961 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4962 gas_assert (mips_opts.mips16);
4963 ip->insn_opcode |= 0x0080;
4964 find_altered_mips16_opcode (ip);
4966 insert_into_history (0, 1, ip);
4971 struct mips_cl_insn delay = history[0];
4972 if (mips_opts.mips16)
4974 know (delay.frag == ip->frag);
4975 move_insn (ip, delay.frag, delay.where);
4976 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4978 else if (relaxed_branch || delay.frag != ip->frag)
4980 /* Add the delay slot instruction to the end of the
4981 current frag and shrink the fixed part of the
4982 original frag. If the branch occupies the tail of
4983 the latter, move it backwards to cover the gap. */
4984 delay.frag->fr_fix -= branch_disp;
4985 if (delay.frag == ip->frag)
4986 move_insn (ip, ip->frag, ip->where - branch_disp);
4987 add_fixed_insn (&delay);
4991 move_insn (&delay, ip->frag,
4992 ip->where - branch_disp + insn_length (ip));
4993 move_insn (ip, history[0].frag, history[0].where);
4997 insert_into_history (0, 1, &delay);
5002 /* If we have just completed an unconditional branch, clear the history. */
5003 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
5004 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
5008 mips_no_prev_insn ();
5010 for (i = 0; i < ARRAY_SIZE (history); i++)
5011 history[i].cleared_p = 1;
5014 /* We need to emit a label at the end of branch-likely macros. */
5015 if (emit_branch_likely_macro)
5017 emit_branch_likely_macro = FALSE;
5018 micromips_add_label ();
5021 /* We just output an insn, so the next one doesn't have a label. */
5022 mips_clear_insn_labels ();
5025 /* Forget that there was any previous instruction or label.
5026 When BRANCH is true, the branch history is also flushed. */
5029 mips_no_prev_insn (void)
5031 prev_nop_frag = NULL;
5032 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
5033 mips_clear_insn_labels ();
5036 /* This function must be called before we emit something other than
5037 instructions. It is like mips_no_prev_insn except that it inserts
5038 any NOPS that might be needed by previous instructions. */
5041 mips_emit_delays (void)
5043 if (! mips_opts.noreorder)
5045 int nops = nops_for_insn (0, history, NULL);
5049 add_fixed_insn (NOP_INSN);
5050 mips_move_text_labels ();
5053 mips_no_prev_insn ();
5056 /* Start a (possibly nested) noreorder block. */
5059 start_noreorder (void)
5061 if (mips_opts.noreorder == 0)
5066 /* None of the instructions before the .set noreorder can be moved. */
5067 for (i = 0; i < ARRAY_SIZE (history); i++)
5068 history[i].fixed_p = 1;
5070 /* Insert any nops that might be needed between the .set noreorder
5071 block and the previous instructions. We will later remove any
5072 nops that turn out not to be needed. */
5073 nops = nops_for_insn (0, history, NULL);
5076 if (mips_optimize != 0)
5078 /* Record the frag which holds the nop instructions, so
5079 that we can remove them if we don't need them. */
5080 frag_grow (nops * NOP_INSN_SIZE);
5081 prev_nop_frag = frag_now;
5082 prev_nop_frag_holds = nops;
5083 prev_nop_frag_required = 0;
5084 prev_nop_frag_since = 0;
5087 for (; nops > 0; --nops)
5088 add_fixed_insn (NOP_INSN);
5090 /* Move on to a new frag, so that it is safe to simply
5091 decrease the size of prev_nop_frag. */
5092 frag_wane (frag_now);
5094 mips_move_text_labels ();
5096 mips_mark_labels ();
5097 mips_clear_insn_labels ();
5099 mips_opts.noreorder++;
5100 mips_any_noreorder = 1;
5103 /* End a nested noreorder block. */
5106 end_noreorder (void)
5108 mips_opts.noreorder--;
5109 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
5111 /* Commit to inserting prev_nop_frag_required nops and go back to
5112 handling nop insertion the .set reorder way. */
5113 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
5115 insert_into_history (prev_nop_frag_since,
5116 prev_nop_frag_required, NOP_INSN);
5117 prev_nop_frag = NULL;
5121 /* Set up global variables for the start of a new macro. */
5126 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
5127 memset (&mips_macro_warning.first_insn_sizes, 0,
5128 sizeof (mips_macro_warning.first_insn_sizes));
5129 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
5130 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
5131 && delayed_branch_p (&history[0]));
5132 switch (history[0].insn_mo->pinfo2
5133 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
5135 case INSN2_BRANCH_DELAY_32BIT:
5136 mips_macro_warning.delay_slot_length = 4;
5138 case INSN2_BRANCH_DELAY_16BIT:
5139 mips_macro_warning.delay_slot_length = 2;
5142 mips_macro_warning.delay_slot_length = 0;
5145 mips_macro_warning.first_frag = NULL;
5148 /* Given that a macro is longer than one instruction or of the wrong size,
5149 return the appropriate warning for it. Return null if no warning is
5150 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5151 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5152 and RELAX_NOMACRO. */
5155 macro_warning (relax_substateT subtype)
5157 if (subtype & RELAX_DELAY_SLOT)
5158 return _("Macro instruction expanded into multiple instructions"
5159 " in a branch delay slot");
5160 else if (subtype & RELAX_NOMACRO)
5161 return _("Macro instruction expanded into multiple instructions");
5162 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
5163 | RELAX_DELAY_SLOT_SIZE_SECOND))
5164 return ((subtype & RELAX_DELAY_SLOT_16BIT)
5165 ? _("Macro instruction expanded into a wrong size instruction"
5166 " in a 16-bit branch delay slot")
5167 : _("Macro instruction expanded into a wrong size instruction"
5168 " in a 32-bit branch delay slot"));
5173 /* Finish up a macro. Emit warnings as appropriate. */
5178 /* Relaxation warning flags. */
5179 relax_substateT subtype = 0;
5181 /* Check delay slot size requirements. */
5182 if (mips_macro_warning.delay_slot_length == 2)
5183 subtype |= RELAX_DELAY_SLOT_16BIT;
5184 if (mips_macro_warning.delay_slot_length != 0)
5186 if (mips_macro_warning.delay_slot_length
5187 != mips_macro_warning.first_insn_sizes[0])
5188 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
5189 if (mips_macro_warning.delay_slot_length
5190 != mips_macro_warning.first_insn_sizes[1])
5191 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
5194 /* Check instruction count requirements. */
5195 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
5197 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
5198 subtype |= RELAX_SECOND_LONGER;
5199 if (mips_opts.warn_about_macros)
5200 subtype |= RELAX_NOMACRO;
5201 if (mips_macro_warning.delay_slot_p)
5202 subtype |= RELAX_DELAY_SLOT;
5205 /* If both alternatives fail to fill a delay slot correctly,
5206 emit the warning now. */
5207 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
5208 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
5213 s = subtype & (RELAX_DELAY_SLOT_16BIT
5214 | RELAX_DELAY_SLOT_SIZE_FIRST
5215 | RELAX_DELAY_SLOT_SIZE_SECOND);
5216 msg = macro_warning (s);
5218 as_warn ("%s", msg);
5222 /* If both implementations are longer than 1 instruction, then emit the
5224 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
5229 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
5230 msg = macro_warning (s);
5232 as_warn ("%s", msg);
5236 /* If any flags still set, then one implementation might need a warning
5237 and the other either will need one of a different kind or none at all.
5238 Pass any remaining flags over to relaxation. */
5239 if (mips_macro_warning.first_frag != NULL)
5240 mips_macro_warning.first_frag->fr_subtype |= subtype;
5243 /* Instruction operand formats used in macros that vary between
5244 standard MIPS and microMIPS code. */
5246 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
5247 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
5248 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
5249 static const char * const lui_fmt[2] = { "t,u", "s,u" };
5250 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
5251 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
5252 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
5253 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
5255 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
5256 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5257 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5258 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5259 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5260 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
5261 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5262 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5264 /* Read a macro's relocation codes from *ARGS and store them in *R.
5265 The first argument in *ARGS will be either the code for a single
5266 relocation or -1 followed by the three codes that make up a
5267 composite relocation. */
5270 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
5274 next = va_arg (*args, int);
5276 r[0] = (bfd_reloc_code_real_type) next;
5279 for (i = 0; i < 3; i++)
5280 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
5281 /* This function is only used for 16-bit relocation fields.
5282 To make the macro code simpler, treat an unrelocated value
5283 in the same way as BFD_RELOC_LO16. */
5284 if (r[0] == BFD_RELOC_UNUSED)
5285 r[0] = BFD_RELOC_LO16;
5289 /* Build an instruction created by a macro expansion. This is passed
5290 a pointer to the count of instructions created so far, an
5291 expression, the name of the instruction to build, an operand format
5292 string, and corresponding arguments. */
5295 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
5297 const struct mips_opcode *mo = NULL;
5298 bfd_reloc_code_real_type r[3];
5299 const struct mips_opcode *amo;
5300 struct hash_control *hash;
5301 struct mips_cl_insn insn;
5304 va_start (args, fmt);
5306 if (mips_opts.mips16)
5308 mips16_macro_build (ep, name, fmt, &args);
5313 r[0] = BFD_RELOC_UNUSED;
5314 r[1] = BFD_RELOC_UNUSED;
5315 r[2] = BFD_RELOC_UNUSED;
5316 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
5317 amo = (struct mips_opcode *) hash_find (hash, name);
5319 gas_assert (strcmp (name, amo->name) == 0);
5323 /* Search until we get a match for NAME. It is assumed here that
5324 macros will never generate MDMX, MIPS-3D, or MT instructions.
5325 We try to match an instruction that fulfils the branch delay
5326 slot instruction length requirement (if any) of the previous
5327 instruction. While doing this we record the first instruction
5328 seen that matches all the other conditions and use it anyway
5329 if the requirement cannot be met; we will issue an appropriate
5330 warning later on. */
5331 if (strcmp (fmt, amo->args) == 0
5332 && amo->pinfo != INSN_MACRO
5333 && is_opcode_valid (amo)
5334 && is_size_valid (amo))
5336 if (is_delay_slot_valid (amo))
5346 gas_assert (amo->name);
5348 while (strcmp (name, amo->name) == 0);
5351 create_insn (&insn, mo);
5369 INSERT_OPERAND (mips_opts.micromips,
5370 EXTLSB, insn, va_arg (args, int));
5375 /* Note that in the macro case, these arguments are already
5376 in MSB form. (When handling the instruction in the
5377 non-macro case, these arguments are sizes from which
5378 MSB values must be calculated.) */
5379 INSERT_OPERAND (mips_opts.micromips,
5380 INSMSB, insn, va_arg (args, int));
5384 gas_assert (!mips_opts.micromips);
5385 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5391 /* Note that in the macro case, these arguments are already
5392 in MSBD form. (When handling the instruction in the
5393 non-macro case, these arguments are sizes from which
5394 MSBD values must be calculated.) */
5395 INSERT_OPERAND (mips_opts.micromips,
5396 EXTMSBD, insn, va_arg (args, int));
5400 gas_assert (!mips_opts.micromips);
5401 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5405 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
5414 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5418 gas_assert (mips_opts.micromips);
5422 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5426 INSERT_OPERAND (mips_opts.micromips, CODE, insn, va_arg (args, int));
5430 gas_assert (!mips_opts.micromips);
5432 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5436 if (mips_opts.micromips)
5437 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5439 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5443 gas_assert (!mips_opts.micromips);
5445 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5449 gas_assert (!mips_opts.micromips);
5451 int tmp = va_arg (args, int);
5453 INSERT_OPERAND (0, RT, insn, tmp);
5454 INSERT_OPERAND (0, RD, insn, tmp);
5460 gas_assert (!mips_opts.micromips);
5461 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5468 INSERT_OPERAND (mips_opts.micromips,
5469 SHAMT, insn, va_arg (args, int));
5473 gas_assert (!mips_opts.micromips);
5474 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5478 gas_assert (!mips_opts.micromips);
5479 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5483 gas_assert (!mips_opts.micromips);
5484 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5488 gas_assert (!mips_opts.micromips);
5489 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5496 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5501 macro_read_relocs (&args, r);
5502 gas_assert (*r == BFD_RELOC_GPREL16
5503 || *r == BFD_RELOC_MIPS_HIGHER
5504 || *r == BFD_RELOC_HI16_S
5505 || *r == BFD_RELOC_LO16
5506 || *r == BFD_RELOC_MIPS_GOT_OFST);
5510 macro_read_relocs (&args, r);
5514 macro_read_relocs (&args, r);
5515 gas_assert (ep != NULL
5516 && (ep->X_op == O_constant
5517 || (ep->X_op == O_symbol
5518 && (*r == BFD_RELOC_MIPS_HIGHEST
5519 || *r == BFD_RELOC_HI16_S
5520 || *r == BFD_RELOC_HI16
5521 || *r == BFD_RELOC_GPREL16
5522 || *r == BFD_RELOC_MIPS_GOT_HI16
5523 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5527 gas_assert (ep != NULL);
5530 * This allows macro() to pass an immediate expression for
5531 * creating short branches without creating a symbol.
5533 * We don't allow branch relaxation for these branches, as
5534 * they should only appear in ".set nomacro" anyway.
5536 if (ep->X_op == O_constant)
5538 /* For microMIPS we always use relocations for branches.
5539 So we should not resolve immediate values. */
5540 gas_assert (!mips_opts.micromips);
5542 if ((ep->X_add_number & 3) != 0)
5543 as_bad (_("branch to misaligned address (0x%lx)"),
5544 (unsigned long) ep->X_add_number);
5545 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5546 as_bad (_("branch address range overflow (0x%lx)"),
5547 (unsigned long) ep->X_add_number);
5548 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5552 *r = BFD_RELOC_16_PCREL_S2;
5556 gas_assert (ep != NULL);
5557 *r = BFD_RELOC_MIPS_JMP;
5561 gas_assert (!mips_opts.micromips);
5562 INSERT_OPERAND (0, COPZ, insn, va_arg (args, int));
5566 INSERT_OPERAND (mips_opts.micromips,
5567 CACHE, insn, va_arg (args, int));
5571 gas_assert (mips_opts.micromips);
5572 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5576 gas_assert (mips_opts.micromips);
5577 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5581 INSERT_OPERAND (mips_opts.micromips,
5582 3BITPOS, insn, va_arg (args, int));
5586 INSERT_OPERAND (mips_opts.micromips,
5587 OFFSET12, insn, va_arg (args, int));
5591 gas_assert (mips_opts.micromips);
5592 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5595 case 'm': /* Opcode extension character. */
5596 gas_assert (mips_opts.micromips);
5600 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5604 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5608 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5622 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5624 append_insn (&insn, ep, r, TRUE);
5628 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5631 struct mips_opcode *mo;
5632 struct mips_cl_insn insn;
5633 bfd_reloc_code_real_type r[3]
5634 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5636 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5638 gas_assert (strcmp (name, mo->name) == 0);
5640 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5643 gas_assert (mo->name);
5644 gas_assert (strcmp (name, mo->name) == 0);
5647 create_insn (&insn, mo);
5665 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5670 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5674 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5678 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5688 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5710 gas_assert (ep != NULL);
5712 if (ep->X_op != O_constant)
5713 *r = (int) BFD_RELOC_UNUSED + c;
5714 else if (calculate_reloc (*r, ep->X_add_number, &value))
5716 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5718 *r = BFD_RELOC_UNUSED;
5724 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5731 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5733 append_insn (&insn, ep, r, TRUE);
5737 * Sign-extend 32-bit mode constants that have bit 31 set and all
5738 * higher bits unset.
5741 normalize_constant_expr (expressionS *ex)
5743 if (ex->X_op == O_constant
5744 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5745 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5750 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5751 * all higher bits unset.
5754 normalize_address_expr (expressionS *ex)
5756 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5757 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5758 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5759 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5764 * Generate a "jalr" instruction with a relocation hint to the called
5765 * function. This occurs in NewABI PIC code.
5768 macro_build_jalr (expressionS *ep, int cprestore)
5770 static const bfd_reloc_code_real_type jalr_relocs[2]
5771 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5772 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5776 if (MIPS_JALR_HINT_P (ep))
5781 if (mips_opts.micromips)
5783 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
5784 ? "jalr" : "jalrs");
5785 if (MIPS_JALR_HINT_P (ep)
5787 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5788 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5790 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5793 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5794 if (MIPS_JALR_HINT_P (ep))
5795 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5799 * Generate a "lui" instruction.
5802 macro_build_lui (expressionS *ep, int regnum)
5804 gas_assert (! mips_opts.mips16);
5806 if (ep->X_op != O_constant)
5808 gas_assert (ep->X_op == O_symbol);
5809 /* _gp_disp is a special case, used from s_cpload.
5810 __gnu_local_gp is used if mips_no_shared. */
5811 gas_assert (mips_pic == NO_PIC
5813 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5814 || (! mips_in_shared
5815 && strcmp (S_GET_NAME (ep->X_add_symbol),
5816 "__gnu_local_gp") == 0));
5819 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5822 /* Generate a sequence of instructions to do a load or store from a constant
5823 offset off of a base register (breg) into/from a target register (treg),
5824 using AT if necessary. */
5826 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5827 int treg, int breg, int dbl)
5829 gas_assert (ep->X_op == O_constant);
5831 /* Sign-extending 32-bit constants makes their handling easier. */
5833 normalize_constant_expr (ep);
5835 /* Right now, this routine can only handle signed 32-bit constants. */
5836 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5837 as_warn (_("operand overflow"));
5839 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5841 /* Signed 16-bit offset will fit in the op. Easy! */
5842 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5846 /* 32-bit offset, need multiple instructions and AT, like:
5847 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5848 addu $tempreg,$tempreg,$breg
5849 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5850 to handle the complete offset. */
5851 macro_build_lui (ep, AT);
5852 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5853 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5856 as_bad (_("Macro used $at after \".set noat\""));
5861 * Generates code to set the $at register to true (one)
5862 * if reg is less than the immediate expression.
5865 set_at (int reg, int unsignedp)
5867 if (imm_expr.X_op == O_constant
5868 && imm_expr.X_add_number >= -0x8000
5869 && imm_expr.X_add_number < 0x8000)
5870 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5871 AT, reg, BFD_RELOC_LO16);
5874 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5875 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5879 /* Warn if an expression is not a constant. */
5882 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5884 if (ex->X_op == O_big)
5885 as_bad (_("unsupported large constant"));
5886 else if (ex->X_op != O_constant)
5887 as_bad (_("Instruction %s requires absolute expression"),
5890 if (HAVE_32BIT_GPRS)
5891 normalize_constant_expr (ex);
5894 /* Count the leading zeroes by performing a binary chop. This is a
5895 bulky bit of source, but performance is a LOT better for the
5896 majority of values than a simple loop to count the bits:
5897 for (lcnt = 0; (lcnt < 32); lcnt++)
5898 if ((v) & (1 << (31 - lcnt)))
5900 However it is not code size friendly, and the gain will drop a bit
5901 on certain cached systems.
5903 #define COUNT_TOP_ZEROES(v) \
5904 (((v) & ~0xffff) == 0 \
5905 ? ((v) & ~0xff) == 0 \
5906 ? ((v) & ~0xf) == 0 \
5907 ? ((v) & ~0x3) == 0 \
5908 ? ((v) & ~0x1) == 0 \
5913 : ((v) & ~0x7) == 0 \
5916 : ((v) & ~0x3f) == 0 \
5917 ? ((v) & ~0x1f) == 0 \
5920 : ((v) & ~0x7f) == 0 \
5923 : ((v) & ~0xfff) == 0 \
5924 ? ((v) & ~0x3ff) == 0 \
5925 ? ((v) & ~0x1ff) == 0 \
5928 : ((v) & ~0x7ff) == 0 \
5931 : ((v) & ~0x3fff) == 0 \
5932 ? ((v) & ~0x1fff) == 0 \
5935 : ((v) & ~0x7fff) == 0 \
5938 : ((v) & ~0xffffff) == 0 \
5939 ? ((v) & ~0xfffff) == 0 \
5940 ? ((v) & ~0x3ffff) == 0 \
5941 ? ((v) & ~0x1ffff) == 0 \
5944 : ((v) & ~0x7ffff) == 0 \
5947 : ((v) & ~0x3fffff) == 0 \
5948 ? ((v) & ~0x1fffff) == 0 \
5951 : ((v) & ~0x7fffff) == 0 \
5954 : ((v) & ~0xfffffff) == 0 \
5955 ? ((v) & ~0x3ffffff) == 0 \
5956 ? ((v) & ~0x1ffffff) == 0 \
5959 : ((v) & ~0x7ffffff) == 0 \
5962 : ((v) & ~0x3fffffff) == 0 \
5963 ? ((v) & ~0x1fffffff) == 0 \
5966 : ((v) & ~0x7fffffff) == 0 \
5971 * This routine generates the least number of instructions necessary to load
5972 * an absolute expression value into a register.
5975 load_register (int reg, expressionS *ep, int dbl)
5978 expressionS hi32, lo32;
5980 if (ep->X_op != O_big)
5982 gas_assert (ep->X_op == O_constant);
5984 /* Sign-extending 32-bit constants makes their handling easier. */
5986 normalize_constant_expr (ep);
5988 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5990 /* We can handle 16 bit signed values with an addiu to
5991 $zero. No need to ever use daddiu here, since $zero and
5992 the result are always correct in 32 bit mode. */
5993 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5996 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5998 /* We can handle 16 bit unsigned values with an ori to
6000 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6003 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
6005 /* 32 bit values require an lui. */
6006 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6007 if ((ep->X_add_number & 0xffff) != 0)
6008 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6013 /* The value is larger than 32 bits. */
6015 if (!dbl || HAVE_32BIT_GPRS)
6019 sprintf_vma (value, ep->X_add_number);
6020 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6021 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6025 if (ep->X_op != O_big)
6028 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6029 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6030 hi32.X_add_number &= 0xffffffff;
6032 lo32.X_add_number &= 0xffffffff;
6036 gas_assert (ep->X_add_number > 2);
6037 if (ep->X_add_number == 3)
6038 generic_bignum[3] = 0;
6039 else if (ep->X_add_number > 4)
6040 as_bad (_("Number larger than 64 bits"));
6041 lo32.X_op = O_constant;
6042 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
6043 hi32.X_op = O_constant;
6044 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
6047 if (hi32.X_add_number == 0)
6052 unsigned long hi, lo;
6054 if (hi32.X_add_number == (offsetT) 0xffffffff)
6056 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
6058 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6061 if (lo32.X_add_number & 0x80000000)
6063 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6064 if (lo32.X_add_number & 0xffff)
6065 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6070 /* Check for 16bit shifted constant. We know that hi32 is
6071 non-zero, so start the mask on the first bit of the hi32
6076 unsigned long himask, lomask;
6080 himask = 0xffff >> (32 - shift);
6081 lomask = (0xffff << shift) & 0xffffffff;
6085 himask = 0xffff << (shift - 32);
6088 if ((hi32.X_add_number & ~(offsetT) himask) == 0
6089 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
6093 tmp.X_op = O_constant;
6095 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
6096 | (lo32.X_add_number >> shift));
6098 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
6099 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6100 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6101 reg, reg, (shift >= 32) ? shift - 32 : shift);
6106 while (shift <= (64 - 16));
6108 /* Find the bit number of the lowest one bit, and store the
6109 shifted value in hi/lo. */
6110 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
6111 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
6115 while ((lo & 1) == 0)
6120 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
6126 while ((hi & 1) == 0)
6135 /* Optimize if the shifted value is a (power of 2) - 1. */
6136 if ((hi == 0 && ((lo + 1) & lo) == 0)
6137 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
6139 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
6144 /* This instruction will set the register to be all
6146 tmp.X_op = O_constant;
6147 tmp.X_add_number = (offsetT) -1;
6148 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6152 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6153 reg, reg, (bit >= 32) ? bit - 32 : bit);
6155 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
6156 reg, reg, (shift >= 32) ? shift - 32 : shift);
6161 /* Sign extend hi32 before calling load_register, because we can
6162 generally get better code when we load a sign extended value. */
6163 if ((hi32.X_add_number & 0x80000000) != 0)
6164 hi32.X_add_number |= ~(offsetT) 0xffffffff;
6165 load_register (reg, &hi32, 0);
6168 if ((lo32.X_add_number & 0xffff0000) == 0)
6172 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
6180 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
6182 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6183 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
6189 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
6193 mid16.X_add_number >>= 16;
6194 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6195 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6198 if ((lo32.X_add_number & 0xffff) != 0)
6199 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6203 load_delay_nop (void)
6205 if (!gpr_interlocks)
6206 macro_build (NULL, "nop", "");
6209 /* Load an address into a register. */
6212 load_address (int reg, expressionS *ep, int *used_at)
6214 if (ep->X_op != O_constant
6215 && ep->X_op != O_symbol)
6217 as_bad (_("expression too complex"));
6218 ep->X_op = O_constant;
6221 if (ep->X_op == O_constant)
6223 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
6227 if (mips_pic == NO_PIC)
6229 /* If this is a reference to a GP relative symbol, we want
6230 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6232 lui $reg,<sym> (BFD_RELOC_HI16_S)
6233 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6234 If we have an addend, we always use the latter form.
6236 With 64bit address space and a usable $at we want
6237 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6238 lui $at,<sym> (BFD_RELOC_HI16_S)
6239 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6240 daddiu $at,<sym> (BFD_RELOC_LO16)
6244 If $at is already in use, we use a path which is suboptimal
6245 on superscalar processors.
6246 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6247 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6249 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6251 daddiu $reg,<sym> (BFD_RELOC_LO16)
6253 For GP relative symbols in 64bit address space we can use
6254 the same sequence as in 32bit address space. */
6255 if (HAVE_64BIT_SYMBOLS)
6257 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6258 && !nopic_need_relax (ep->X_add_symbol, 1))
6260 relax_start (ep->X_add_symbol);
6261 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6262 mips_gp_register, BFD_RELOC_GPREL16);
6266 if (*used_at == 0 && mips_opts.at)
6268 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6269 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
6270 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6271 BFD_RELOC_MIPS_HIGHER);
6272 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
6273 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
6274 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
6279 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6280 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6281 BFD_RELOC_MIPS_HIGHER);
6282 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6283 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
6284 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6285 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
6288 if (mips_relax.sequence)
6293 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6294 && !nopic_need_relax (ep->X_add_symbol, 1))
6296 relax_start (ep->X_add_symbol);
6297 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6298 mips_gp_register, BFD_RELOC_GPREL16);
6301 macro_build_lui (ep, reg);
6302 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
6303 reg, reg, BFD_RELOC_LO16);
6304 if (mips_relax.sequence)
6308 else if (!mips_big_got)
6312 /* If this is a reference to an external symbol, we want
6313 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6315 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6317 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6318 If there is a constant, it must be added in after.
6320 If we have NewABI, we want
6321 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6322 unless we're referencing a global symbol with a non-zero
6323 offset, in which case cst must be added separately. */
6326 if (ep->X_add_number)
6328 ex.X_add_number = ep->X_add_number;
6329 ep->X_add_number = 0;
6330 relax_start (ep->X_add_symbol);
6331 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6332 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6333 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6334 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6335 ex.X_op = O_constant;
6336 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6337 reg, reg, BFD_RELOC_LO16);
6338 ep->X_add_number = ex.X_add_number;
6341 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6342 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6343 if (mips_relax.sequence)
6348 ex.X_add_number = ep->X_add_number;
6349 ep->X_add_number = 0;
6350 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6351 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6353 relax_start (ep->X_add_symbol);
6355 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6359 if (ex.X_add_number != 0)
6361 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6362 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6363 ex.X_op = O_constant;
6364 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6365 reg, reg, BFD_RELOC_LO16);
6369 else if (mips_big_got)
6373 /* This is the large GOT case. If this is a reference to an
6374 external symbol, we want
6375 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6377 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6379 Otherwise, for a reference to a local symbol in old ABI, we want
6380 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6382 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6383 If there is a constant, it must be added in after.
6385 In the NewABI, for local symbols, with or without offsets, we want:
6386 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6387 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6391 ex.X_add_number = ep->X_add_number;
6392 ep->X_add_number = 0;
6393 relax_start (ep->X_add_symbol);
6394 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6395 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6396 reg, reg, mips_gp_register);
6397 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6398 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6399 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6400 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6401 else if (ex.X_add_number)
6403 ex.X_op = O_constant;
6404 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6408 ep->X_add_number = ex.X_add_number;
6410 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6411 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6412 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6413 BFD_RELOC_MIPS_GOT_OFST);
6418 ex.X_add_number = ep->X_add_number;
6419 ep->X_add_number = 0;
6420 relax_start (ep->X_add_symbol);
6421 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6422 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6423 reg, reg, mips_gp_register);
6424 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6425 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6427 if (reg_needs_delay (mips_gp_register))
6429 /* We need a nop before loading from $gp. This special
6430 check is required because the lui which starts the main
6431 instruction stream does not refer to $gp, and so will not
6432 insert the nop which may be required. */
6433 macro_build (NULL, "nop", "");
6435 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6436 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6438 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6442 if (ex.X_add_number != 0)
6444 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6445 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6446 ex.X_op = O_constant;
6447 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6455 if (!mips_opts.at && *used_at == 1)
6456 as_bad (_("Macro used $at after \".set noat\""));
6459 /* Move the contents of register SOURCE into register DEST. */
6462 move_register (int dest, int source)
6464 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6465 instruction specifically requires a 32-bit one. */
6466 if (mips_opts.micromips
6467 && !mips_opts.insn32
6468 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6469 macro_build (NULL, "move", "mp,mj", dest, source);
6471 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6475 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6476 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6477 The two alternatives are:
6479 Global symbol Local sybmol
6480 ------------- ------------
6481 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6483 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6485 load_got_offset emits the first instruction and add_got_offset
6486 emits the second for a 16-bit offset or add_got_offset_hilo emits
6487 a sequence to add a 32-bit offset using a scratch register. */
6490 load_got_offset (int dest, expressionS *local)
6495 global.X_add_number = 0;
6497 relax_start (local->X_add_symbol);
6498 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6499 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6501 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6502 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6507 add_got_offset (int dest, expressionS *local)
6511 global.X_op = O_constant;
6512 global.X_op_symbol = NULL;
6513 global.X_add_symbol = NULL;
6514 global.X_add_number = local->X_add_number;
6516 relax_start (local->X_add_symbol);
6517 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6518 dest, dest, BFD_RELOC_LO16);
6520 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6525 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6528 int hold_mips_optimize;
6530 global.X_op = O_constant;
6531 global.X_op_symbol = NULL;
6532 global.X_add_symbol = NULL;
6533 global.X_add_number = local->X_add_number;
6535 relax_start (local->X_add_symbol);
6536 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6538 /* Set mips_optimize around the lui instruction to avoid
6539 inserting an unnecessary nop after the lw. */
6540 hold_mips_optimize = mips_optimize;
6542 macro_build_lui (&global, tmp);
6543 mips_optimize = hold_mips_optimize;
6544 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6547 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6550 /* Emit a sequence of instructions to emulate a branch likely operation.
6551 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6552 is its complementing branch with the original condition negated.
6553 CALL is set if the original branch specified the link operation.
6554 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6556 Code like this is produced in the noreorder mode:
6561 delay slot (executed only if branch taken)
6569 delay slot (executed only if branch taken)
6572 In the reorder mode the delay slot would be filled with a nop anyway,
6573 so code produced is simply:
6578 This function is used when producing code for the microMIPS ASE that
6579 does not implement branch likely instructions in hardware. */
6582 macro_build_branch_likely (const char *br, const char *brneg,
6583 int call, expressionS *ep, const char *fmt,
6584 unsigned int sreg, unsigned int treg)
6586 int noreorder = mips_opts.noreorder;
6589 gas_assert (mips_opts.micromips);
6593 micromips_label_expr (&expr1);
6594 macro_build (&expr1, brneg, fmt, sreg, treg);
6595 macro_build (NULL, "nop", "");
6596 macro_build (ep, call ? "bal" : "b", "p");
6598 /* Set to true so that append_insn adds a label. */
6599 emit_branch_likely_macro = TRUE;
6603 macro_build (ep, br, fmt, sreg, treg);
6604 macro_build (NULL, "nop", "");
6609 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6610 the condition code tested. EP specifies the branch target. */
6613 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6640 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6643 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6644 the register tested. EP specifies the branch target. */
6647 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6649 const char *brneg = NULL;
6659 br = mips_opts.micromips ? "bgez" : "bgezl";
6663 gas_assert (mips_opts.micromips);
6664 br = mips_opts.insn32 ? "bgezal" : "bgezals";
6672 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6679 br = mips_opts.micromips ? "blez" : "blezl";
6686 br = mips_opts.micromips ? "bltz" : "bltzl";
6690 gas_assert (mips_opts.micromips);
6691 br = mips_opts.insn32 ? "bltzal" : "bltzals";
6698 if (mips_opts.micromips && brneg)
6699 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6701 macro_build (ep, br, "s,p", sreg);
6704 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6705 TREG as the registers tested. EP specifies the branch target. */
6708 macro_build_branch_rsrt (int type, expressionS *ep,
6709 unsigned int sreg, unsigned int treg)
6711 const char *brneg = NULL;
6723 br = mips_opts.micromips ? "beq" : "beql";
6732 br = mips_opts.micromips ? "bne" : "bnel";
6738 if (mips_opts.micromips && brneg)
6739 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6741 macro_build (ep, br, "s,t,p", sreg, treg);
6744 /* Return the high part that should be loaded in order to make the low
6745 part of VALUE accessible using an offset of OFFBITS bits. */
6748 offset_high_part (offsetT value, unsigned int offbits)
6755 bias = 1 << (offbits - 1);
6756 low_mask = bias * 2 - 1;
6757 return (value + bias) & ~low_mask;
6760 /* Return true if the value stored in offset_expr and offset_reloc
6761 fits into a signed offset of OFFBITS bits. RANGE is the maximum
6762 amount that the caller wants to add without inducing overflow
6763 and ALIGN is the known alignment of the value in bytes. */
6766 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
6770 /* Accept any relocation operator if overflow isn't a concern. */
6771 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
6774 /* These relocations are guaranteed not to overflow in correct links. */
6775 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
6776 || gprel16_reloc_p (*offset_reloc))
6779 if (offset_expr.X_op == O_constant
6780 && offset_high_part (offset_expr.X_add_number, offbits) == 0
6781 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
6788 * This routine implements the seemingly endless macro or synthesized
6789 * instructions and addressing modes in the mips assembly language. Many
6790 * of these macros are simple and are similar to each other. These could
6791 * probably be handled by some kind of table or grammar approach instead of
6792 * this verbose method. Others are not simple macros but are more like
6793 * optimizing code generation.
6794 * One interesting optimization is when several store macros appear
6795 * consecutively that would load AT with the upper half of the same address.
6796 * The ensuing load upper instructions are ommited. This implies some kind
6797 * of global optimization. We currently only optimize within a single macro.
6798 * For many of the load and store macros if the address is specified as a
6799 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6800 * first load register 'at' with zero and use it as the base register. The
6801 * mips assembler simply uses register $zero. Just one tiny optimization
6805 macro (struct mips_cl_insn *ip, char *str)
6807 unsigned int treg, sreg, dreg, breg;
6808 unsigned int tempreg;
6811 expressionS label_expr;
6826 bfd_boolean large_offset;
6828 int hold_mips_optimize;
6831 gas_assert (! mips_opts.mips16);
6833 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6834 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6835 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6836 mask = ip->insn_mo->mask;
6838 label_expr.X_op = O_constant;
6839 label_expr.X_op_symbol = NULL;
6840 label_expr.X_add_symbol = NULL;
6841 label_expr.X_add_number = 0;
6843 expr1.X_op = O_constant;
6844 expr1.X_op_symbol = NULL;
6845 expr1.X_add_symbol = NULL;
6846 expr1.X_add_number = 1;
6862 if (mips_opts.micromips)
6863 micromips_label_expr (&label_expr);
6865 label_expr.X_add_number = 8;
6866 macro_build (&label_expr, "bgez", "s,p", sreg);
6868 macro_build (NULL, "nop", "");
6870 move_register (dreg, sreg);
6871 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6872 if (mips_opts.micromips)
6873 micromips_add_label ();
6890 if (!mips_opts.micromips)
6892 if (imm_expr.X_op == O_constant
6893 && imm_expr.X_add_number >= -0x200
6894 && imm_expr.X_add_number < 0x200)
6896 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6905 if (imm_expr.X_op == O_constant
6906 && imm_expr.X_add_number >= -0x8000
6907 && imm_expr.X_add_number < 0x8000)
6909 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6914 load_register (AT, &imm_expr, dbl);
6915 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6934 if (imm_expr.X_op == O_constant
6935 && imm_expr.X_add_number >= 0
6936 && imm_expr.X_add_number < 0x10000)
6938 if (mask != M_NOR_I)
6939 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6942 macro_build (&imm_expr, "ori", "t,r,i",
6943 treg, sreg, BFD_RELOC_LO16);
6944 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6950 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6951 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6955 switch (imm_expr.X_add_number)
6958 macro_build (NULL, "nop", "");
6961 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6965 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6966 (int) imm_expr.X_add_number);
6969 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6970 (unsigned long) imm_expr.X_add_number);
6979 gas_assert (mips_opts.micromips);
6980 macro_build_branch_ccl (mask, &offset_expr,
6981 EXTRACT_OPERAND (1, BCC, *ip));
6988 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6994 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6999 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
7006 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
7008 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
7012 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7013 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7014 &offset_expr, AT, ZERO);
7024 macro_build_branch_rs (mask, &offset_expr, sreg);
7030 /* Check for > max integer. */
7031 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7034 /* Result is always false. */
7036 macro_build (NULL, "nop", "");
7038 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
7041 if (imm_expr.X_op != O_constant)
7042 as_bad (_("Unsupported large constant"));
7043 ++imm_expr.X_add_number;
7047 if (mask == M_BGEL_I)
7049 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7051 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
7052 &offset_expr, sreg);
7055 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7057 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
7058 &offset_expr, sreg);
7061 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
7064 /* result is always true */
7065 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
7066 macro_build (&offset_expr, "b", "p");
7071 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7072 &offset_expr, AT, ZERO);
7081 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7082 &offset_expr, ZERO, treg);
7086 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7087 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7088 &offset_expr, AT, ZERO);
7097 && imm_expr.X_op == O_constant
7098 && imm_expr.X_add_number == -1))
7100 if (imm_expr.X_op != O_constant)
7101 as_bad (_("Unsupported large constant"));
7102 ++imm_expr.X_add_number;
7106 if (mask == M_BGEUL_I)
7108 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7110 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7111 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7112 &offset_expr, sreg, ZERO);
7117 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7118 &offset_expr, AT, ZERO);
7126 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
7128 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
7132 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7133 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7134 &offset_expr, AT, ZERO);
7142 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7143 &offset_expr, sreg, ZERO);
7149 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7150 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7151 &offset_expr, AT, ZERO);
7159 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7161 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
7165 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7166 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7167 &offset_expr, AT, ZERO);
7174 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7176 if (imm_expr.X_op != O_constant)
7177 as_bad (_("Unsupported large constant"));
7178 ++imm_expr.X_add_number;
7182 if (mask == M_BLTL_I)
7184 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7185 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7186 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7187 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7192 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7193 &offset_expr, AT, ZERO);
7201 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7202 &offset_expr, sreg, ZERO);
7208 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7209 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7210 &offset_expr, AT, ZERO);
7219 && imm_expr.X_op == O_constant
7220 && imm_expr.X_add_number == -1))
7222 if (imm_expr.X_op != O_constant)
7223 as_bad (_("Unsupported large constant"));
7224 ++imm_expr.X_add_number;
7228 if (mask == M_BLTUL_I)
7230 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7232 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7233 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7234 &offset_expr, sreg, ZERO);
7239 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7240 &offset_expr, AT, ZERO);
7248 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7250 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
7254 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7255 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7256 &offset_expr, AT, ZERO);
7266 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7267 &offset_expr, ZERO, treg);
7271 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7272 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7273 &offset_expr, AT, ZERO);
7279 /* Use unsigned arithmetic. */
7283 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7285 as_bad (_("Unsupported large constant"));
7290 pos = imm_expr.X_add_number;
7291 size = imm2_expr.X_add_number;
7296 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7299 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7301 as_bad (_("Improper extract size (%lu, position %lu)"),
7302 (unsigned long) size, (unsigned long) pos);
7306 if (size <= 32 && pos < 32)
7311 else if (size <= 32)
7321 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7328 /* Use unsigned arithmetic. */
7332 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7334 as_bad (_("Unsupported large constant"));
7339 pos = imm_expr.X_add_number;
7340 size = imm2_expr.X_add_number;
7345 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7348 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7350 as_bad (_("Improper insert size (%lu, position %lu)"),
7351 (unsigned long) size, (unsigned long) pos);
7355 if (pos < 32 && (pos + size - 1) < 32)
7370 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7371 (int) (pos + size - 1));
7387 as_warn (_("Divide by zero."));
7389 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7391 macro_build (NULL, "break", BRK_FMT, 7);
7398 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7399 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7403 if (mips_opts.micromips)
7404 micromips_label_expr (&label_expr);
7406 label_expr.X_add_number = 8;
7407 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7408 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7409 macro_build (NULL, "break", BRK_FMT, 7);
7410 if (mips_opts.micromips)
7411 micromips_add_label ();
7413 expr1.X_add_number = -1;
7415 load_register (AT, &expr1, dbl);
7416 if (mips_opts.micromips)
7417 micromips_label_expr (&label_expr);
7419 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7420 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7423 expr1.X_add_number = 1;
7424 load_register (AT, &expr1, dbl);
7425 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7429 expr1.X_add_number = 0x80000000;
7430 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7434 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7435 /* We want to close the noreorder block as soon as possible, so
7436 that later insns are available for delay slot filling. */
7441 if (mips_opts.micromips)
7442 micromips_label_expr (&label_expr);
7444 label_expr.X_add_number = 8;
7445 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7446 macro_build (NULL, "nop", "");
7448 /* We want to close the noreorder block as soon as possible, so
7449 that later insns are available for delay slot filling. */
7452 macro_build (NULL, "break", BRK_FMT, 6);
7454 if (mips_opts.micromips)
7455 micromips_add_label ();
7456 macro_build (NULL, s, MFHL_FMT, dreg);
7495 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7497 as_warn (_("Divide by zero."));
7499 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7501 macro_build (NULL, "break", BRK_FMT, 7);
7504 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7506 if (strcmp (s2, "mflo") == 0)
7507 move_register (dreg, sreg);
7509 move_register (dreg, ZERO);
7512 if (imm_expr.X_op == O_constant
7513 && imm_expr.X_add_number == -1
7514 && s[strlen (s) - 1] != 'u')
7516 if (strcmp (s2, "mflo") == 0)
7518 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7521 move_register (dreg, ZERO);
7526 load_register (AT, &imm_expr, dbl);
7527 macro_build (NULL, s, "z,s,t", sreg, AT);
7528 macro_build (NULL, s2, MFHL_FMT, dreg);
7550 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7551 macro_build (NULL, s, "z,s,t", sreg, treg);
7552 /* We want to close the noreorder block as soon as possible, so
7553 that later insns are available for delay slot filling. */
7558 if (mips_opts.micromips)
7559 micromips_label_expr (&label_expr);
7561 label_expr.X_add_number = 8;
7562 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7563 macro_build (NULL, s, "z,s,t", sreg, treg);
7565 /* We want to close the noreorder block as soon as possible, so
7566 that later insns are available for delay slot filling. */
7568 macro_build (NULL, "break", BRK_FMT, 7);
7569 if (mips_opts.micromips)
7570 micromips_add_label ();
7572 macro_build (NULL, s2, MFHL_FMT, dreg);
7584 /* Load the address of a symbol into a register. If breg is not
7585 zero, we then add a base register to it. */
7587 if (dbl && HAVE_32BIT_GPRS)
7588 as_warn (_("dla used to load 32-bit register"));
7590 if (!dbl && HAVE_64BIT_OBJECTS)
7591 as_warn (_("la used to load 64-bit address"));
7593 if (small_offset_p (0, align, 16))
7595 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
7596 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
7600 if (mips_opts.at && (treg == breg))
7610 if (offset_expr.X_op != O_symbol
7611 && offset_expr.X_op != O_constant)
7613 as_bad (_("Expression too complex"));
7614 offset_expr.X_op = O_constant;
7617 if (offset_expr.X_op == O_constant)
7618 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7619 else if (mips_pic == NO_PIC)
7621 /* If this is a reference to a GP relative symbol, we want
7622 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7624 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7625 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7626 If we have a constant, we need two instructions anyhow,
7627 so we may as well always use the latter form.
7629 With 64bit address space and a usable $at we want
7630 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7631 lui $at,<sym> (BFD_RELOC_HI16_S)
7632 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7633 daddiu $at,<sym> (BFD_RELOC_LO16)
7635 daddu $tempreg,$tempreg,$at
7637 If $at is already in use, we use a path which is suboptimal
7638 on superscalar processors.
7639 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7640 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7642 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7644 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7646 For GP relative symbols in 64bit address space we can use
7647 the same sequence as in 32bit address space. */
7648 if (HAVE_64BIT_SYMBOLS)
7650 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7651 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7653 relax_start (offset_expr.X_add_symbol);
7654 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7655 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7659 if (used_at == 0 && mips_opts.at)
7661 macro_build (&offset_expr, "lui", LUI_FMT,
7662 tempreg, BFD_RELOC_MIPS_HIGHEST);
7663 macro_build (&offset_expr, "lui", LUI_FMT,
7664 AT, BFD_RELOC_HI16_S);
7665 macro_build (&offset_expr, "daddiu", "t,r,j",
7666 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7667 macro_build (&offset_expr, "daddiu", "t,r,j",
7668 AT, AT, BFD_RELOC_LO16);
7669 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7670 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7675 macro_build (&offset_expr, "lui", LUI_FMT,
7676 tempreg, BFD_RELOC_MIPS_HIGHEST);
7677 macro_build (&offset_expr, "daddiu", "t,r,j",
7678 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7679 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7680 macro_build (&offset_expr, "daddiu", "t,r,j",
7681 tempreg, tempreg, BFD_RELOC_HI16_S);
7682 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7683 macro_build (&offset_expr, "daddiu", "t,r,j",
7684 tempreg, tempreg, BFD_RELOC_LO16);
7687 if (mips_relax.sequence)
7692 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7693 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7695 relax_start (offset_expr.X_add_symbol);
7696 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7697 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7700 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7701 as_bad (_("Offset too large"));
7702 macro_build_lui (&offset_expr, tempreg);
7703 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7704 tempreg, tempreg, BFD_RELOC_LO16);
7705 if (mips_relax.sequence)
7709 else if (!mips_big_got && !HAVE_NEWABI)
7711 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7713 /* If this is a reference to an external symbol, and there
7714 is no constant, we want
7715 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7716 or for lca or if tempreg is PIC_CALL_REG
7717 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7718 For a local symbol, we want
7719 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7721 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7723 If we have a small constant, and this is a reference to
7724 an external symbol, we want
7725 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7727 addiu $tempreg,$tempreg,<constant>
7728 For a local symbol, we want the same instruction
7729 sequence, but we output a BFD_RELOC_LO16 reloc on the
7732 If we have a large constant, and this is a reference to
7733 an external symbol, we want
7734 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7735 lui $at,<hiconstant>
7736 addiu $at,$at,<loconstant>
7737 addu $tempreg,$tempreg,$at
7738 For a local symbol, we want the same instruction
7739 sequence, but we output a BFD_RELOC_LO16 reloc on the
7743 if (offset_expr.X_add_number == 0)
7745 if (mips_pic == SVR4_PIC
7747 && (call || tempreg == PIC_CALL_REG))
7748 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7750 relax_start (offset_expr.X_add_symbol);
7751 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7752 lw_reloc_type, mips_gp_register);
7755 /* We're going to put in an addu instruction using
7756 tempreg, so we may as well insert the nop right
7761 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7762 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7764 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7765 tempreg, tempreg, BFD_RELOC_LO16);
7767 /* FIXME: If breg == 0, and the next instruction uses
7768 $tempreg, then if this variant case is used an extra
7769 nop will be generated. */
7771 else if (offset_expr.X_add_number >= -0x8000
7772 && offset_expr.X_add_number < 0x8000)
7774 load_got_offset (tempreg, &offset_expr);
7776 add_got_offset (tempreg, &offset_expr);
7780 expr1.X_add_number = offset_expr.X_add_number;
7781 offset_expr.X_add_number =
7782 SEXT_16BIT (offset_expr.X_add_number);
7783 load_got_offset (tempreg, &offset_expr);
7784 offset_expr.X_add_number = expr1.X_add_number;
7785 /* If we are going to add in a base register, and the
7786 target register and the base register are the same,
7787 then we are using AT as a temporary register. Since
7788 we want to load the constant into AT, we add our
7789 current AT (from the global offset table) and the
7790 register into the register now, and pretend we were
7791 not using a base register. */
7795 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7800 add_got_offset_hilo (tempreg, &offset_expr, AT);
7804 else if (!mips_big_got && HAVE_NEWABI)
7806 int add_breg_early = 0;
7808 /* If this is a reference to an external, and there is no
7809 constant, or local symbol (*), with or without a
7811 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7812 or for lca or if tempreg is PIC_CALL_REG
7813 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7815 If we have a small constant, and this is a reference to
7816 an external symbol, we want
7817 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7818 addiu $tempreg,$tempreg,<constant>
7820 If we have a large constant, and this is a reference to
7821 an external symbol, we want
7822 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7823 lui $at,<hiconstant>
7824 addiu $at,$at,<loconstant>
7825 addu $tempreg,$tempreg,$at
7827 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7828 local symbols, even though it introduces an additional
7831 if (offset_expr.X_add_number)
7833 expr1.X_add_number = offset_expr.X_add_number;
7834 offset_expr.X_add_number = 0;
7836 relax_start (offset_expr.X_add_symbol);
7837 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7838 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7840 if (expr1.X_add_number >= -0x8000
7841 && expr1.X_add_number < 0x8000)
7843 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7844 tempreg, tempreg, BFD_RELOC_LO16);
7846 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7848 /* If we are going to add in a base register, and the
7849 target register and the base register are the same,
7850 then we are using AT as a temporary register. Since
7851 we want to load the constant into AT, we add our
7852 current AT (from the global offset table) and the
7853 register into the register now, and pretend we were
7854 not using a base register. */
7859 gas_assert (tempreg == AT);
7860 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7866 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7867 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7873 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7876 offset_expr.X_add_number = expr1.X_add_number;
7878 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7879 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7882 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7883 treg, tempreg, breg);
7889 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7891 relax_start (offset_expr.X_add_symbol);
7892 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7893 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7895 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7896 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7901 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7902 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7905 else if (mips_big_got && !HAVE_NEWABI)
7908 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7909 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7910 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7912 /* This is the large GOT case. If this is a reference to an
7913 external symbol, and there is no constant, we want
7914 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7915 addu $tempreg,$tempreg,$gp
7916 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7917 or for lca or if tempreg is PIC_CALL_REG
7918 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7919 addu $tempreg,$tempreg,$gp
7920 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7921 For a local symbol, we want
7922 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7924 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7926 If we have a small constant, and this is a reference to
7927 an external symbol, we want
7928 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7929 addu $tempreg,$tempreg,$gp
7930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7932 addiu $tempreg,$tempreg,<constant>
7933 For a local symbol, we want
7934 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7936 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7938 If we have a large constant, and this is a reference to
7939 an external symbol, we want
7940 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7941 addu $tempreg,$tempreg,$gp
7942 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7943 lui $at,<hiconstant>
7944 addiu $at,$at,<loconstant>
7945 addu $tempreg,$tempreg,$at
7946 For a local symbol, we want
7947 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7948 lui $at,<hiconstant>
7949 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7950 addu $tempreg,$tempreg,$at
7953 expr1.X_add_number = offset_expr.X_add_number;
7954 offset_expr.X_add_number = 0;
7955 relax_start (offset_expr.X_add_symbol);
7956 gpdelay = reg_needs_delay (mips_gp_register);
7957 if (expr1.X_add_number == 0 && breg == 0
7958 && (call || tempreg == PIC_CALL_REG))
7960 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7961 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7963 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7964 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7965 tempreg, tempreg, mips_gp_register);
7966 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7967 tempreg, lw_reloc_type, tempreg);
7968 if (expr1.X_add_number == 0)
7972 /* We're going to put in an addu instruction using
7973 tempreg, so we may as well insert the nop right
7978 else if (expr1.X_add_number >= -0x8000
7979 && expr1.X_add_number < 0x8000)
7982 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7983 tempreg, tempreg, BFD_RELOC_LO16);
7987 /* If we are going to add in a base register, and the
7988 target register and the base register are the same,
7989 then we are using AT as a temporary register. Since
7990 we want to load the constant into AT, we add our
7991 current AT (from the global offset table) and the
7992 register into the register now, and pretend we were
7993 not using a base register. */
7998 gas_assert (tempreg == AT);
8000 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8005 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8006 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8010 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
8015 /* This is needed because this instruction uses $gp, but
8016 the first instruction on the main stream does not. */
8017 macro_build (NULL, "nop", "");
8020 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8021 local_reloc_type, mips_gp_register);
8022 if (expr1.X_add_number >= -0x8000
8023 && expr1.X_add_number < 0x8000)
8026 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8027 tempreg, tempreg, BFD_RELOC_LO16);
8028 /* FIXME: If add_number is 0, and there was no base
8029 register, the external symbol case ended with a load,
8030 so if the symbol turns out to not be external, and
8031 the next instruction uses tempreg, an unnecessary nop
8032 will be inserted. */
8038 /* We must add in the base register now, as in the
8039 external symbol case. */
8040 gas_assert (tempreg == AT);
8042 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8045 /* We set breg to 0 because we have arranged to add
8046 it in in both cases. */
8050 macro_build_lui (&expr1, AT);
8051 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8052 AT, AT, BFD_RELOC_LO16);
8053 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8054 tempreg, tempreg, AT);
8059 else if (mips_big_got && HAVE_NEWABI)
8061 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
8062 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
8063 int add_breg_early = 0;
8065 /* This is the large GOT case. If this is a reference to an
8066 external symbol, and there is no constant, we want
8067 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8068 add $tempreg,$tempreg,$gp
8069 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8070 or for lca or if tempreg is PIC_CALL_REG
8071 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8072 add $tempreg,$tempreg,$gp
8073 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8075 If we have a small constant, and this is a reference to
8076 an external symbol, we want
8077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8078 add $tempreg,$tempreg,$gp
8079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8080 addi $tempreg,$tempreg,<constant>
8082 If we have a large constant, and this is a reference to
8083 an external symbol, we want
8084 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8085 addu $tempreg,$tempreg,$gp
8086 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8087 lui $at,<hiconstant>
8088 addi $at,$at,<loconstant>
8089 add $tempreg,$tempreg,$at
8091 If we have NewABI, and we know it's a local symbol, we want
8092 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8093 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8094 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8096 relax_start (offset_expr.X_add_symbol);
8098 expr1.X_add_number = offset_expr.X_add_number;
8099 offset_expr.X_add_number = 0;
8101 if (expr1.X_add_number == 0 && breg == 0
8102 && (call || tempreg == PIC_CALL_REG))
8104 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
8105 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
8107 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
8108 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8109 tempreg, tempreg, mips_gp_register);
8110 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8111 tempreg, lw_reloc_type, tempreg);
8113 if (expr1.X_add_number == 0)
8115 else if (expr1.X_add_number >= -0x8000
8116 && expr1.X_add_number < 0x8000)
8118 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
8119 tempreg, tempreg, BFD_RELOC_LO16);
8121 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
8123 /* If we are going to add in a base register, and the
8124 target register and the base register are the same,
8125 then we are using AT as a temporary register. Since
8126 we want to load the constant into AT, we add our
8127 current AT (from the global offset table) and the
8128 register into the register now, and pretend we were
8129 not using a base register. */
8134 gas_assert (tempreg == AT);
8135 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8141 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8142 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8147 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8150 offset_expr.X_add_number = expr1.X_add_number;
8151 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8152 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8153 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8154 tempreg, BFD_RELOC_MIPS_GOT_OFST);
8157 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8158 treg, tempreg, breg);
8168 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
8172 gas_assert (!mips_opts.micromips);
8173 macro_build (NULL, "c2", "C", (treg << 16) | 0x01);
8177 gas_assert (!mips_opts.micromips);
8178 macro_build (NULL, "c2", "C", 0x02);
8182 gas_assert (!mips_opts.micromips);
8183 macro_build (NULL, "c2", "C", (treg << 16) | 0x02);
8187 gas_assert (!mips_opts.micromips);
8188 macro_build (NULL, "c2", "C", 3);
8192 gas_assert (!mips_opts.micromips);
8193 macro_build (NULL, "c2", "C", (treg << 16) | 0x03);
8197 /* The j instruction may not be used in PIC code, since it
8198 requires an absolute address. We convert it to a b
8200 if (mips_pic == NO_PIC)
8201 macro_build (&offset_expr, "j", "a");
8203 macro_build (&offset_expr, "b", "p");
8206 /* The jal instructions must be handled as macros because when
8207 generating PIC code they expand to multi-instruction
8208 sequences. Normally they are simple instructions. */
8213 gas_assert (mips_opts.micromips);
8214 if (mips_opts.insn32)
8216 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8226 if (mips_pic == NO_PIC)
8228 s = jals ? "jalrs" : "jalr";
8229 if (mips_opts.micromips
8230 && !mips_opts.insn32
8232 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8233 macro_build (NULL, s, "mj", sreg);
8235 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8239 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
8240 && mips_cprestore_offset >= 0);
8242 if (sreg != PIC_CALL_REG)
8243 as_warn (_("MIPS PIC call to register other than $25"));
8245 s = ((mips_opts.micromips
8246 && !mips_opts.insn32
8247 && (!mips_opts.noreorder || cprestore))
8248 ? "jalrs" : "jalr");
8249 if (mips_opts.micromips
8250 && !mips_opts.insn32
8252 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8253 macro_build (NULL, s, "mj", sreg);
8255 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8256 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
8258 if (mips_cprestore_offset < 0)
8259 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8262 if (!mips_frame_reg_valid)
8264 as_warn (_("No .frame pseudo-op used in PIC code"));
8265 /* Quiet this warning. */
8266 mips_frame_reg_valid = 1;
8268 if (!mips_cprestore_valid)
8270 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8271 /* Quiet this warning. */
8272 mips_cprestore_valid = 1;
8274 if (mips_opts.noreorder)
8275 macro_build (NULL, "nop", "");
8276 expr1.X_add_number = mips_cprestore_offset;
8277 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8280 HAVE_64BIT_ADDRESSES);
8288 gas_assert (mips_opts.micromips);
8289 if (mips_opts.insn32)
8291 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8297 if (mips_pic == NO_PIC)
8298 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
8299 else if (mips_pic == SVR4_PIC)
8301 /* If this is a reference to an external symbol, and we are
8302 using a small GOT, we want
8303 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8307 lw $gp,cprestore($sp)
8308 The cprestore value is set using the .cprestore
8309 pseudo-op. If we are using a big GOT, we want
8310 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8312 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8316 lw $gp,cprestore($sp)
8317 If the symbol is not external, we want
8318 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8320 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8323 lw $gp,cprestore($sp)
8325 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8326 sequences above, minus nops, unless the symbol is local,
8327 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8333 relax_start (offset_expr.X_add_symbol);
8334 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8335 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8338 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8339 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8345 relax_start (offset_expr.X_add_symbol);
8346 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8347 BFD_RELOC_MIPS_CALL_HI16);
8348 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8349 PIC_CALL_REG, mips_gp_register);
8350 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8351 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8354 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8355 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8357 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8358 PIC_CALL_REG, PIC_CALL_REG,
8359 BFD_RELOC_MIPS_GOT_OFST);
8363 macro_build_jalr (&offset_expr, 0);
8367 relax_start (offset_expr.X_add_symbol);
8370 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8371 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8380 gpdelay = reg_needs_delay (mips_gp_register);
8381 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8382 BFD_RELOC_MIPS_CALL_HI16);
8383 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8384 PIC_CALL_REG, mips_gp_register);
8385 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8386 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8391 macro_build (NULL, "nop", "");
8393 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8394 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8397 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8398 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8400 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8402 if (mips_cprestore_offset < 0)
8403 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8406 if (!mips_frame_reg_valid)
8408 as_warn (_("No .frame pseudo-op used in PIC code"));
8409 /* Quiet this warning. */
8410 mips_frame_reg_valid = 1;
8412 if (!mips_cprestore_valid)
8414 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8415 /* Quiet this warning. */
8416 mips_cprestore_valid = 1;
8418 if (mips_opts.noreorder)
8419 macro_build (NULL, "nop", "");
8420 expr1.X_add_number = mips_cprestore_offset;
8421 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8424 HAVE_64BIT_ADDRESSES);
8428 else if (mips_pic == VXWORKS_PIC)
8429 as_bad (_("Non-PIC jump used in PIC library"));
8507 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8513 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8538 gas_assert (!mips_opts.micromips);
8541 /* Itbl support may require additional care here. */
8547 /* Itbl support may require additional care here. */
8553 offbits = (mips_opts.micromips ? 12 : 16);
8554 /* Itbl support may require additional care here. */
8558 gas_assert (!mips_opts.micromips);
8561 /* Itbl support may require additional care here. */
8567 offbits = (mips_opts.micromips ? 12 : 16);
8572 offbits = (mips_opts.micromips ? 12 : 16);
8577 /* Itbl support may require additional care here. */
8583 offbits = (mips_opts.micromips ? 12 : 16);
8584 /* Itbl support may require additional care here. */
8590 /* Itbl support may require additional care here. */
8596 /* Itbl support may require additional care here. */
8602 offbits = (mips_opts.micromips ? 12 : 16);
8607 offbits = (mips_opts.micromips ? 12 : 16);
8612 offbits = (mips_opts.micromips ? 12 : 16);
8617 offbits = (mips_opts.micromips ? 12 : 16);
8622 offbits = (mips_opts.micromips ? 12 : 16);
8625 gas_assert (mips_opts.micromips);
8632 gas_assert (mips_opts.micromips);
8639 gas_assert (mips_opts.micromips);
8645 gas_assert (mips_opts.micromips);
8652 /* We don't want to use $0 as tempreg. */
8653 if (breg == treg + lp || treg + lp == ZERO)
8656 tempreg = treg + lp;
8672 gas_assert (!mips_opts.micromips);
8675 /* Itbl support may require additional care here. */
8681 /* Itbl support may require additional care here. */
8687 offbits = (mips_opts.micromips ? 12 : 16);
8688 /* Itbl support may require additional care here. */
8692 gas_assert (!mips_opts.micromips);
8695 /* Itbl support may require additional care here. */
8701 offbits = (mips_opts.micromips ? 12 : 16);
8706 offbits = (mips_opts.micromips ? 12 : 16);
8711 offbits = (mips_opts.micromips ? 12 : 16);
8716 offbits = (mips_opts.micromips ? 12 : 16);
8720 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8721 offbits = (mips_opts.micromips ? 12 : 16);
8730 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8731 offbits = (mips_opts.micromips ? 12 : 16);
8742 /* Itbl support may require additional care here. */
8747 offbits = (mips_opts.micromips ? 12 : 16);
8748 /* Itbl support may require additional care here. */
8754 /* Itbl support may require additional care here. */
8758 gas_assert (!mips_opts.micromips);
8761 /* Itbl support may require additional care here. */
8767 offbits = (mips_opts.micromips ? 12 : 16);
8772 offbits = (mips_opts.micromips ? 12 : 16);
8775 gas_assert (mips_opts.micromips);
8781 gas_assert (mips_opts.micromips);
8787 gas_assert (mips_opts.micromips);
8793 gas_assert (mips_opts.micromips);
8801 if (small_offset_p (0, align, 16))
8803 /* The first case exists for M_LD_AB and M_SD_AB, which are
8804 macros for o32 but which should act like normal instructions
8807 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
8808 offset_reloc[1], offset_reloc[2], breg);
8809 else if (small_offset_p (0, align, offbits))
8812 macro_build (NULL, s, fmt, treg, breg);
8814 macro_build (NULL, s, fmt, treg,
8815 (int) offset_expr.X_add_number, breg);
8821 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8822 tempreg, breg, -1, offset_reloc[0],
8823 offset_reloc[1], offset_reloc[2]);
8825 macro_build (NULL, s, fmt, treg, tempreg);
8827 macro_build (NULL, s, fmt, treg, 0, tempreg);
8835 if (offset_expr.X_op != O_constant
8836 && offset_expr.X_op != O_symbol)
8838 as_bad (_("Expression too complex"));
8839 offset_expr.X_op = O_constant;
8842 if (HAVE_32BIT_ADDRESSES
8843 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8847 sprintf_vma (value, offset_expr.X_add_number);
8848 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8851 /* A constant expression in PIC code can be handled just as it
8852 is in non PIC code. */
8853 if (offset_expr.X_op == O_constant)
8855 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
8856 offbits == 0 ? 16 : offbits);
8857 offset_expr.X_add_number -= expr1.X_add_number;
8859 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8861 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8862 tempreg, tempreg, breg);
8865 if (offset_expr.X_add_number != 0)
8866 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8867 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
8868 macro_build (NULL, s, fmt, treg, tempreg);
8870 else if (offbits == 16)
8871 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8873 macro_build (NULL, s, fmt, treg,
8874 (int) offset_expr.X_add_number, tempreg);
8876 else if (offbits != 16)
8878 /* The offset field is too narrow to be used for a low-part
8879 relocation, so load the whole address into the auxillary
8881 load_address (tempreg, &offset_expr, &used_at);
8883 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8884 tempreg, tempreg, breg);
8886 macro_build (NULL, s, fmt, treg, tempreg);
8888 macro_build (NULL, s, fmt, treg, 0, tempreg);
8890 else if (mips_pic == NO_PIC)
8892 /* If this is a reference to a GP relative symbol, and there
8893 is no base register, we want
8894 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8895 Otherwise, if there is no base register, we want
8896 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8897 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8898 If we have a constant, we need two instructions anyhow,
8899 so we always use the latter form.
8901 If we have a base register, and this is a reference to a
8902 GP relative symbol, we want
8903 addu $tempreg,$breg,$gp
8904 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8906 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8907 addu $tempreg,$tempreg,$breg
8908 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8909 With a constant we always use the latter case.
8911 With 64bit address space and no base register and $at usable,
8913 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8914 lui $at,<sym> (BFD_RELOC_HI16_S)
8915 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8918 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8919 If we have a base register, we want
8920 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8921 lui $at,<sym> (BFD_RELOC_HI16_S)
8922 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8926 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8928 Without $at we can't generate the optimal path for superscalar
8929 processors here since this would require two temporary registers.
8930 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8931 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8933 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8935 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8936 If we have a base register, we want
8937 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8938 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8940 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8942 daddu $tempreg,$tempreg,$breg
8943 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8945 For GP relative symbols in 64bit address space we can use
8946 the same sequence as in 32bit address space. */
8947 if (HAVE_64BIT_SYMBOLS)
8949 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8950 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8952 relax_start (offset_expr.X_add_symbol);
8955 macro_build (&offset_expr, s, fmt, treg,
8956 BFD_RELOC_GPREL16, mips_gp_register);
8960 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8961 tempreg, breg, mips_gp_register);
8962 macro_build (&offset_expr, s, fmt, treg,
8963 BFD_RELOC_GPREL16, tempreg);
8968 if (used_at == 0 && mips_opts.at)
8970 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8971 BFD_RELOC_MIPS_HIGHEST);
8972 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8974 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8975 tempreg, BFD_RELOC_MIPS_HIGHER);
8977 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8978 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8979 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8980 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8986 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8987 BFD_RELOC_MIPS_HIGHEST);
8988 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8989 tempreg, BFD_RELOC_MIPS_HIGHER);
8990 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8991 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8992 tempreg, BFD_RELOC_HI16_S);
8993 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8995 macro_build (NULL, "daddu", "d,v,t",
8996 tempreg, tempreg, breg);
8997 macro_build (&offset_expr, s, fmt, treg,
8998 BFD_RELOC_LO16, tempreg);
9001 if (mips_relax.sequence)
9008 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9009 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9011 relax_start (offset_expr.X_add_symbol);
9012 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
9016 macro_build_lui (&offset_expr, tempreg);
9017 macro_build (&offset_expr, s, fmt, treg,
9018 BFD_RELOC_LO16, tempreg);
9019 if (mips_relax.sequence)
9024 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9025 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9027 relax_start (offset_expr.X_add_symbol);
9028 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9029 tempreg, breg, mips_gp_register);
9030 macro_build (&offset_expr, s, fmt, treg,
9031 BFD_RELOC_GPREL16, tempreg);
9034 macro_build_lui (&offset_expr, tempreg);
9035 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9036 tempreg, tempreg, breg);
9037 macro_build (&offset_expr, s, fmt, treg,
9038 BFD_RELOC_LO16, tempreg);
9039 if (mips_relax.sequence)
9043 else if (!mips_big_got)
9045 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9047 /* If this is a reference to an external symbol, we want
9048 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9050 <op> $treg,0($tempreg)
9052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9054 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9055 <op> $treg,0($tempreg)
9058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9059 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9061 If there is a base register, we add it to $tempreg before
9062 the <op>. If there is a constant, we stick it in the
9063 <op> instruction. We don't handle constants larger than
9064 16 bits, because we have no way to load the upper 16 bits
9065 (actually, we could handle them for the subset of cases
9066 in which we are not using $at). */
9067 gas_assert (offset_expr.X_op == O_symbol);
9070 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9071 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9073 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9074 tempreg, tempreg, breg);
9075 macro_build (&offset_expr, s, fmt, treg,
9076 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9079 expr1.X_add_number = offset_expr.X_add_number;
9080 offset_expr.X_add_number = 0;
9081 if (expr1.X_add_number < -0x8000
9082 || expr1.X_add_number >= 0x8000)
9083 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9084 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9085 lw_reloc_type, mips_gp_register);
9087 relax_start (offset_expr.X_add_symbol);
9089 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9090 tempreg, BFD_RELOC_LO16);
9093 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9094 tempreg, tempreg, breg);
9095 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9097 else if (mips_big_got && !HAVE_NEWABI)
9101 /* If this is a reference to an external symbol, we want
9102 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9103 addu $tempreg,$tempreg,$gp
9104 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9105 <op> $treg,0($tempreg)
9107 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9109 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9110 <op> $treg,0($tempreg)
9111 If there is a base register, we add it to $tempreg before
9112 the <op>. If there is a constant, we stick it in the
9113 <op> instruction. We don't handle constants larger than
9114 16 bits, because we have no way to load the upper 16 bits
9115 (actually, we could handle them for the subset of cases
9116 in which we are not using $at). */
9117 gas_assert (offset_expr.X_op == O_symbol);
9118 expr1.X_add_number = offset_expr.X_add_number;
9119 offset_expr.X_add_number = 0;
9120 if (expr1.X_add_number < -0x8000
9121 || expr1.X_add_number >= 0x8000)
9122 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9123 gpdelay = reg_needs_delay (mips_gp_register);
9124 relax_start (offset_expr.X_add_symbol);
9125 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9126 BFD_RELOC_MIPS_GOT_HI16);
9127 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9129 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9130 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9133 macro_build (NULL, "nop", "");
9134 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9135 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9137 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9138 tempreg, BFD_RELOC_LO16);
9142 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9143 tempreg, tempreg, breg);
9144 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9146 else if (mips_big_got && HAVE_NEWABI)
9148 /* If this is a reference to an external symbol, we want
9149 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9150 add $tempreg,$tempreg,$gp
9151 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9152 <op> $treg,<ofst>($tempreg)
9153 Otherwise, for local symbols, we want:
9154 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9155 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9156 gas_assert (offset_expr.X_op == O_symbol);
9157 expr1.X_add_number = offset_expr.X_add_number;
9158 offset_expr.X_add_number = 0;
9159 if (expr1.X_add_number < -0x8000
9160 || expr1.X_add_number >= 0x8000)
9161 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9162 relax_start (offset_expr.X_add_symbol);
9163 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9164 BFD_RELOC_MIPS_GOT_HI16);
9165 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9167 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9168 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9170 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9171 tempreg, tempreg, breg);
9172 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9175 offset_expr.X_add_number = expr1.X_add_number;
9176 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9177 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9180 tempreg, tempreg, breg);
9181 macro_build (&offset_expr, s, fmt, treg,
9182 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9191 gas_assert (mips_opts.micromips);
9192 gas_assert (mips_opts.insn32);
9194 macro_build (NULL, "jr", "s", RA);
9195 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
9196 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
9201 gas_assert (mips_opts.micromips);
9202 gas_assert (mips_opts.insn32);
9203 macro_build (NULL, "jr", "s", sreg);
9204 if (mips_opts.noreorder)
9205 macro_build (NULL, "nop", "");
9210 load_register (treg, &imm_expr, 0);
9214 load_register (treg, &imm_expr, 1);
9218 if (imm_expr.X_op == O_constant)
9221 load_register (AT, &imm_expr, 0);
9222 macro_build (NULL, "mtc1", "t,G", AT, treg);
9227 gas_assert (offset_expr.X_op == O_symbol
9228 && strcmp (segment_name (S_GET_SEGMENT
9229 (offset_expr.X_add_symbol)),
9231 && offset_expr.X_add_number == 0);
9232 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
9233 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9238 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9239 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9240 order 32 bits of the value and the low order 32 bits are either
9241 zero or in OFFSET_EXPR. */
9242 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9244 if (HAVE_64BIT_GPRS)
9245 load_register (treg, &imm_expr, 1);
9250 if (target_big_endian)
9262 load_register (hreg, &imm_expr, 0);
9265 if (offset_expr.X_op == O_absent)
9266 move_register (lreg, 0);
9269 gas_assert (offset_expr.X_op == O_constant);
9270 load_register (lreg, &offset_expr, 0);
9277 /* We know that sym is in the .rdata section. First we get the
9278 upper 16 bits of the address. */
9279 if (mips_pic == NO_PIC)
9281 macro_build_lui (&offset_expr, AT);
9286 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9287 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9291 /* Now we load the register(s). */
9292 if (HAVE_64BIT_GPRS)
9295 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9300 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9303 /* FIXME: How in the world do we deal with the possible
9305 offset_expr.X_add_number += 4;
9306 macro_build (&offset_expr, "lw", "t,o(b)",
9307 treg + 1, BFD_RELOC_LO16, AT);
9313 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9314 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9315 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9316 the value and the low order 32 bits are either zero or in
9318 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9321 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
9322 if (HAVE_64BIT_FPRS)
9324 gas_assert (HAVE_64BIT_GPRS);
9325 macro_build (NULL, "dmtc1", "t,S", AT, treg);
9329 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
9330 if (offset_expr.X_op == O_absent)
9331 macro_build (NULL, "mtc1", "t,G", 0, treg);
9334 gas_assert (offset_expr.X_op == O_constant);
9335 load_register (AT, &offset_expr, 0);
9336 macro_build (NULL, "mtc1", "t,G", AT, treg);
9342 gas_assert (offset_expr.X_op == O_symbol
9343 && offset_expr.X_add_number == 0);
9344 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
9345 if (strcmp (s, ".lit8") == 0)
9347 breg = mips_gp_register;
9348 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
9349 offset_reloc[1] = BFD_RELOC_UNUSED;
9350 offset_reloc[2] = BFD_RELOC_UNUSED;
9354 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9356 if (mips_pic != NO_PIC)
9357 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9358 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9361 /* FIXME: This won't work for a 64 bit address. */
9362 macro_build_lui (&offset_expr, AT);
9366 offset_reloc[0] = BFD_RELOC_LO16;
9367 offset_reloc[1] = BFD_RELOC_UNUSED;
9368 offset_reloc[2] = BFD_RELOC_UNUSED;
9375 * The MIPS assembler seems to check for X_add_number not
9376 * being double aligned and generating:
9379 * addiu at,at,%lo(foo+1)
9382 * But, the resulting address is the same after relocation so why
9383 * generate the extra instruction?
9385 /* Itbl support may require additional care here. */
9388 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9397 gas_assert (!mips_opts.micromips);
9398 /* Itbl support may require additional care here. */
9401 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9421 if (HAVE_64BIT_GPRS)
9431 if (HAVE_64BIT_GPRS)
9439 /* Even on a big endian machine $fn comes before $fn+1. We have
9440 to adjust when loading from memory. We set coproc if we must
9441 load $fn+1 first. */
9442 /* Itbl support may require additional care here. */
9443 if (!target_big_endian)
9446 if (small_offset_p (0, align, 16))
9449 if (!small_offset_p (4, align, 16))
9451 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
9452 -1, offset_reloc[0], offset_reloc[1],
9454 expr1.X_add_number = 0;
9458 offset_reloc[0] = BFD_RELOC_LO16;
9459 offset_reloc[1] = BFD_RELOC_UNUSED;
9460 offset_reloc[2] = BFD_RELOC_UNUSED;
9462 if (strcmp (s, "lw") == 0 && treg == breg)
9464 ep->X_add_number += 4;
9465 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
9466 offset_reloc[1], offset_reloc[2], breg);
9467 ep->X_add_number -= 4;
9468 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
9469 offset_reloc[1], offset_reloc[2], breg);
9473 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
9474 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9476 ep->X_add_number += 4;
9477 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
9478 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9484 if (offset_expr.X_op != O_symbol
9485 && offset_expr.X_op != O_constant)
9487 as_bad (_("Expression too complex"));
9488 offset_expr.X_op = O_constant;
9491 if (HAVE_32BIT_ADDRESSES
9492 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9496 sprintf_vma (value, offset_expr.X_add_number);
9497 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9500 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9502 /* If this is a reference to a GP relative symbol, we want
9503 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9504 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9505 If we have a base register, we use this
9507 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9508 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9509 If this is not a GP relative symbol, we want
9510 lui $at,<sym> (BFD_RELOC_HI16_S)
9511 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9512 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9513 If there is a base register, we add it to $at after the
9514 lui instruction. If there is a constant, we always use
9516 if (offset_expr.X_op == O_symbol
9517 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9518 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9520 relax_start (offset_expr.X_add_symbol);
9523 tempreg = mips_gp_register;
9527 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9528 AT, breg, mips_gp_register);
9533 /* Itbl support may require additional care here. */
9534 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9535 BFD_RELOC_GPREL16, tempreg);
9536 offset_expr.X_add_number += 4;
9538 /* Set mips_optimize to 2 to avoid inserting an
9540 hold_mips_optimize = mips_optimize;
9542 /* Itbl support may require additional care here. */
9543 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9544 BFD_RELOC_GPREL16, tempreg);
9545 mips_optimize = hold_mips_optimize;
9549 offset_expr.X_add_number -= 4;
9552 if (offset_high_part (offset_expr.X_add_number, 16)
9553 != offset_high_part (offset_expr.X_add_number + 4, 16))
9555 load_address (AT, &offset_expr, &used_at);
9556 offset_expr.X_op = O_constant;
9557 offset_expr.X_add_number = 0;
9560 macro_build_lui (&offset_expr, AT);
9562 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9563 /* Itbl support may require additional care here. */
9564 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9565 BFD_RELOC_LO16, AT);
9566 /* FIXME: How do we handle overflow here? */
9567 offset_expr.X_add_number += 4;
9568 /* Itbl support may require additional care here. */
9569 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9570 BFD_RELOC_LO16, AT);
9571 if (mips_relax.sequence)
9574 else if (!mips_big_got)
9576 /* If this is a reference to an external symbol, we want
9577 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9582 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9584 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9585 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9586 If there is a base register we add it to $at before the
9587 lwc1 instructions. If there is a constant we include it
9588 in the lwc1 instructions. */
9590 expr1.X_add_number = offset_expr.X_add_number;
9591 if (expr1.X_add_number < -0x8000
9592 || expr1.X_add_number >= 0x8000 - 4)
9593 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9594 load_got_offset (AT, &offset_expr);
9597 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9599 /* Set mips_optimize to 2 to avoid inserting an undesired
9601 hold_mips_optimize = mips_optimize;
9604 /* Itbl support may require additional care here. */
9605 relax_start (offset_expr.X_add_symbol);
9606 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9607 BFD_RELOC_LO16, AT);
9608 expr1.X_add_number += 4;
9609 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9610 BFD_RELOC_LO16, AT);
9612 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9613 BFD_RELOC_LO16, AT);
9614 offset_expr.X_add_number += 4;
9615 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9616 BFD_RELOC_LO16, AT);
9619 mips_optimize = hold_mips_optimize;
9621 else if (mips_big_got)
9625 /* If this is a reference to an external symbol, we want
9626 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9628 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9633 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9635 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9636 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9637 If there is a base register we add it to $at before the
9638 lwc1 instructions. If there is a constant we include it
9639 in the lwc1 instructions. */
9641 expr1.X_add_number = offset_expr.X_add_number;
9642 offset_expr.X_add_number = 0;
9643 if (expr1.X_add_number < -0x8000
9644 || expr1.X_add_number >= 0x8000 - 4)
9645 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9646 gpdelay = reg_needs_delay (mips_gp_register);
9647 relax_start (offset_expr.X_add_symbol);
9648 macro_build (&offset_expr, "lui", LUI_FMT,
9649 AT, BFD_RELOC_MIPS_GOT_HI16);
9650 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9651 AT, AT, mips_gp_register);
9652 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9653 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9656 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9657 /* Itbl support may require additional care here. */
9658 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9659 BFD_RELOC_LO16, AT);
9660 expr1.X_add_number += 4;
9662 /* Set mips_optimize to 2 to avoid inserting an undesired
9664 hold_mips_optimize = mips_optimize;
9666 /* Itbl support may require additional care here. */
9667 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9668 BFD_RELOC_LO16, AT);
9669 mips_optimize = hold_mips_optimize;
9670 expr1.X_add_number -= 4;
9673 offset_expr.X_add_number = expr1.X_add_number;
9675 macro_build (NULL, "nop", "");
9676 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9677 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9680 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9681 /* Itbl support may require additional care here. */
9682 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9683 BFD_RELOC_LO16, AT);
9684 offset_expr.X_add_number += 4;
9686 /* Set mips_optimize to 2 to avoid inserting an undesired
9688 hold_mips_optimize = mips_optimize;
9690 /* Itbl support may require additional care here. */
9691 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9692 BFD_RELOC_LO16, AT);
9693 mips_optimize = hold_mips_optimize;
9712 /* New code added to support COPZ instructions.
9713 This code builds table entries out of the macros in mip_opcodes.
9714 R4000 uses interlocks to handle coproc delays.
9715 Other chips (like the R3000) require nops to be inserted for delays.
9717 FIXME: Currently, we require that the user handle delays.
9718 In order to fill delay slots for non-interlocked chips,
9719 we must have a way to specify delays based on the coprocessor.
9720 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9721 What are the side-effects of the cop instruction?
9722 What cache support might we have and what are its effects?
9723 Both coprocessor & memory require delays. how long???
9724 What registers are read/set/modified?
9726 If an itbl is provided to interpret cop instructions,
9727 this knowledge can be encoded in the itbl spec. */
9741 gas_assert (!mips_opts.micromips);
9742 /* For now we just do C (same as Cz). The parameter will be
9743 stored in insn_opcode by mips_ip. */
9744 macro_build (NULL, s, "C", (int) ip->insn_opcode);
9748 move_register (dreg, sreg);
9752 gas_assert (mips_opts.micromips);
9753 gas_assert (mips_opts.insn32);
9754 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
9755 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
9756 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
9757 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
9758 move_register (dreg, sreg);
9759 move_register (breg, treg);
9765 if (mips_opts.arch == CPU_R5900)
9767 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9771 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9772 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9779 /* The MIPS assembler some times generates shifts and adds. I'm
9780 not trying to be that fancy. GCC should do this for us
9783 load_register (AT, &imm_expr, dbl);
9784 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9785 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9801 load_register (AT, &imm_expr, dbl);
9802 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9803 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9804 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9805 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9807 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9810 if (mips_opts.micromips)
9811 micromips_label_expr (&label_expr);
9813 label_expr.X_add_number = 8;
9814 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9815 macro_build (NULL, "nop", "");
9816 macro_build (NULL, "break", BRK_FMT, 6);
9817 if (mips_opts.micromips)
9818 micromips_add_label ();
9821 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9837 load_register (AT, &imm_expr, dbl);
9838 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9839 sreg, imm ? AT : treg);
9840 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9841 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9843 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9846 if (mips_opts.micromips)
9847 micromips_label_expr (&label_expr);
9849 label_expr.X_add_number = 8;
9850 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9851 macro_build (NULL, "nop", "");
9852 macro_build (NULL, "break", BRK_FMT, 6);
9853 if (mips_opts.micromips)
9854 micromips_add_label ();
9860 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9871 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9872 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9876 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9877 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9878 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9879 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9883 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9894 macro_build (NULL, "negu", "d,w", tempreg, treg);
9895 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9899 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9900 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9901 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9902 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9911 if (imm_expr.X_op != O_constant)
9912 as_bad (_("Improper rotate count"));
9913 rot = imm_expr.X_add_number & 0x3f;
9914 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9916 rot = (64 - rot) & 0x3f;
9918 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9920 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9925 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9928 l = (rot < 0x20) ? "dsll" : "dsll32";
9929 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9932 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9933 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9934 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9942 if (imm_expr.X_op != O_constant)
9943 as_bad (_("Improper rotate count"));
9944 rot = imm_expr.X_add_number & 0x1f;
9945 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9947 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9952 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9956 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9957 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9958 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9963 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9965 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9969 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9970 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9971 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9972 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9976 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9978 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9982 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9983 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9984 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9985 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9994 if (imm_expr.X_op != O_constant)
9995 as_bad (_("Improper rotate count"));
9996 rot = imm_expr.X_add_number & 0x3f;
9997 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
10000 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
10002 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
10007 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
10010 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
10011 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
10014 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
10015 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10016 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10024 if (imm_expr.X_op != O_constant)
10025 as_bad (_("Improper rotate count"));
10026 rot = imm_expr.X_add_number & 0x1f;
10027 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10029 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
10034 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
10038 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
10039 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10040 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10046 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
10047 else if (treg == 0)
10048 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10051 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10052 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10057 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10059 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10064 as_warn (_("Instruction %s: result is always false"),
10065 ip->insn_mo->name);
10066 move_register (dreg, 0);
10069 if (CPU_HAS_SEQ (mips_opts.arch)
10070 && -512 <= imm_expr.X_add_number
10071 && imm_expr.X_add_number < 512)
10073 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
10074 (int) imm_expr.X_add_number);
10077 if (imm_expr.X_op == O_constant
10078 && imm_expr.X_add_number >= 0
10079 && imm_expr.X_add_number < 0x10000)
10081 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10083 else if (imm_expr.X_op == O_constant
10084 && imm_expr.X_add_number > -0x8000
10085 && imm_expr.X_add_number < 0)
10087 imm_expr.X_add_number = -imm_expr.X_add_number;
10088 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10089 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10091 else if (CPU_HAS_SEQ (mips_opts.arch))
10094 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10095 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
10100 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10101 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10104 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10107 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
10113 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
10114 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10117 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
10119 if (imm_expr.X_op == O_constant
10120 && imm_expr.X_add_number >= -0x8000
10121 && imm_expr.X_add_number < 0x8000)
10123 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
10124 dreg, sreg, BFD_RELOC_LO16);
10128 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10129 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
10133 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10136 case M_SGT: /* sreg > treg <==> treg < sreg */
10142 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10145 case M_SGT_I: /* sreg > I <==> I < sreg */
10152 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10153 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10156 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10162 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10163 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10166 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10173 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10174 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10175 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10179 if (imm_expr.X_op == O_constant
10180 && imm_expr.X_add_number >= -0x8000
10181 && imm_expr.X_add_number < 0x8000)
10183 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10187 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10188 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
10192 if (imm_expr.X_op == O_constant
10193 && imm_expr.X_add_number >= -0x8000
10194 && imm_expr.X_add_number < 0x8000)
10196 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
10201 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10202 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
10207 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
10208 else if (treg == 0)
10209 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10212 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10213 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10218 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10220 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10225 as_warn (_("Instruction %s: result is always true"),
10226 ip->insn_mo->name);
10227 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
10228 dreg, 0, BFD_RELOC_LO16);
10231 if (CPU_HAS_SEQ (mips_opts.arch)
10232 && -512 <= imm_expr.X_add_number
10233 && imm_expr.X_add_number < 512)
10235 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
10236 (int) imm_expr.X_add_number);
10239 if (imm_expr.X_op == O_constant
10240 && imm_expr.X_add_number >= 0
10241 && imm_expr.X_add_number < 0x10000)
10243 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10245 else if (imm_expr.X_op == O_constant
10246 && imm_expr.X_add_number > -0x8000
10247 && imm_expr.X_add_number < 0)
10249 imm_expr.X_add_number = -imm_expr.X_add_number;
10250 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10251 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10253 else if (CPU_HAS_SEQ (mips_opts.arch))
10256 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10257 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
10262 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10263 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10266 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10281 if (!mips_opts.micromips)
10283 if (imm_expr.X_op == O_constant
10284 && imm_expr.X_add_number > -0x200
10285 && imm_expr.X_add_number <= 0x200)
10287 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
10296 if (imm_expr.X_op == O_constant
10297 && imm_expr.X_add_number > -0x8000
10298 && imm_expr.X_add_number <= 0x8000)
10300 imm_expr.X_add_number = -imm_expr.X_add_number;
10301 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10306 load_register (AT, &imm_expr, dbl);
10307 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
10329 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10330 macro_build (NULL, s, "s,t", sreg, AT);
10335 gas_assert (!mips_opts.micromips);
10336 gas_assert (mips_opts.isa == ISA_MIPS1);
10338 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
10339 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
10342 * Is the double cfc1 instruction a bug in the mips assembler;
10343 * or is there a reason for it?
10345 start_noreorder ();
10346 macro_build (NULL, "cfc1", "t,G", treg, RA);
10347 macro_build (NULL, "cfc1", "t,G", treg, RA);
10348 macro_build (NULL, "nop", "");
10349 expr1.X_add_number = 3;
10350 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10351 expr1.X_add_number = 2;
10352 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10353 macro_build (NULL, "ctc1", "t,G", AT, RA);
10354 macro_build (NULL, "nop", "");
10355 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10357 macro_build (NULL, "ctc1", "t,G", treg, RA);
10358 macro_build (NULL, "nop", "");
10375 offbits = (mips_opts.micromips ? 12 : 16);
10381 offbits = (mips_opts.micromips ? 12 : 16);
10393 offbits = (mips_opts.micromips ? 12 : 16);
10400 offbits = (mips_opts.micromips ? 12 : 16);
10405 large_offset = !small_offset_p (off, align, offbits);
10407 expr1.X_add_number = 0;
10412 if (small_offset_p (0, align, 16))
10413 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
10414 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10417 load_address (tempreg, ep, &used_at);
10419 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10420 tempreg, tempreg, breg);
10422 offset_reloc[0] = BFD_RELOC_LO16;
10423 offset_reloc[1] = BFD_RELOC_UNUSED;
10424 offset_reloc[2] = BFD_RELOC_UNUSED;
10429 else if (!ust && treg == breg)
10440 if (!target_big_endian)
10441 ep->X_add_number += off;
10443 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
10445 macro_build (ep, s, "t,o(b)", tempreg, -1,
10446 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10448 if (!target_big_endian)
10449 ep->X_add_number -= off;
10451 ep->X_add_number += off;
10453 macro_build (NULL, s2, "t,~(b)",
10454 tempreg, (int) ep->X_add_number, breg);
10456 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10457 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10459 /* If necessary, move the result in tempreg to the final destination. */
10460 if (!ust && treg != tempreg)
10462 /* Protect second load's delay slot. */
10464 move_register (treg, tempreg);
10470 if (target_big_endian == ust)
10471 ep->X_add_number += off;
10472 tempreg = ust || large_offset ? treg : AT;
10473 macro_build (ep, s, "t,o(b)", tempreg, -1,
10474 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10476 /* For halfword transfers we need a temporary register to shuffle
10477 bytes. Unfortunately for M_USH_A we have none available before
10478 the next store as AT holds the base address. We deal with this
10479 case by clobbering TREG and then restoring it as with ULH. */
10480 tempreg = ust == large_offset ? treg : AT;
10482 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10484 if (target_big_endian == ust)
10485 ep->X_add_number -= off;
10487 ep->X_add_number += off;
10488 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10489 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10491 /* For M_USH_A re-retrieve the LSB. */
10492 if (ust && large_offset)
10494 if (target_big_endian)
10495 ep->X_add_number += off;
10497 ep->X_add_number -= off;
10498 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
10499 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
10501 /* For ULH and M_USH_A OR the LSB in. */
10502 if (!ust || large_offset)
10504 tempreg = !large_offset ? AT : treg;
10505 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10506 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10511 /* FIXME: Check if this is one of the itbl macros, since they
10512 are added dynamically. */
10513 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10516 if (!mips_opts.at && used_at)
10517 as_bad (_("Macro used $at after \".set noat\""));
10520 /* Implement macros in mips16 mode. */
10523 mips16_macro (struct mips_cl_insn *ip)
10526 int xreg, yreg, zreg, tmp;
10529 const char *s, *s2, *s3;
10531 mask = ip->insn_mo->mask;
10533 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10534 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10535 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10537 expr1.X_op = O_constant;
10538 expr1.X_op_symbol = NULL;
10539 expr1.X_add_symbol = NULL;
10540 expr1.X_add_number = 1;
10559 start_noreorder ();
10560 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10561 expr1.X_add_number = 2;
10562 macro_build (&expr1, "bnez", "x,p", yreg);
10563 macro_build (NULL, "break", "6", 7);
10565 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10566 since that causes an overflow. We should do that as well,
10567 but I don't see how to do the comparisons without a temporary
10570 macro_build (NULL, s, "x", zreg);
10589 start_noreorder ();
10590 macro_build (NULL, s, "0,x,y", xreg, yreg);
10591 expr1.X_add_number = 2;
10592 macro_build (&expr1, "bnez", "x,p", yreg);
10593 macro_build (NULL, "break", "6", 7);
10595 macro_build (NULL, s2, "x", zreg);
10601 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10602 macro_build (NULL, "mflo", "x", zreg);
10610 if (imm_expr.X_op != O_constant)
10611 as_bad (_("Unsupported large constant"));
10612 imm_expr.X_add_number = -imm_expr.X_add_number;
10613 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10617 if (imm_expr.X_op != O_constant)
10618 as_bad (_("Unsupported large constant"));
10619 imm_expr.X_add_number = -imm_expr.X_add_number;
10620 macro_build (&imm_expr, "addiu", "x,k", xreg);
10624 if (imm_expr.X_op != O_constant)
10625 as_bad (_("Unsupported large constant"));
10626 imm_expr.X_add_number = -imm_expr.X_add_number;
10627 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10649 goto do_reverse_branch;
10653 goto do_reverse_branch;
10665 goto do_reverse_branch;
10676 macro_build (NULL, s, "x,y", xreg, yreg);
10677 macro_build (&offset_expr, s2, "p");
10704 goto do_addone_branch_i;
10709 goto do_addone_branch_i;
10724 goto do_addone_branch_i;
10730 do_addone_branch_i:
10731 if (imm_expr.X_op != O_constant)
10732 as_bad (_("Unsupported large constant"));
10733 ++imm_expr.X_add_number;
10736 macro_build (&imm_expr, s, s3, xreg);
10737 macro_build (&offset_expr, s2, "p");
10741 expr1.X_add_number = 0;
10742 macro_build (&expr1, "slti", "x,8", yreg);
10744 move_register (xreg, yreg);
10745 expr1.X_add_number = 2;
10746 macro_build (&expr1, "bteqz", "p");
10747 macro_build (NULL, "neg", "x,w", xreg, xreg);
10751 /* For consistency checking, verify that all bits are specified either
10752 by the match/mask part of the instruction definition, or by the
10755 validate_mips_insn (const struct mips_opcode *opc)
10757 const char *p = opc->args;
10759 unsigned long used_bits = opc->mask;
10761 if ((used_bits & opc->match) != opc->match)
10763 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10764 opc->name, opc->args);
10767 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10777 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10778 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10779 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10780 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10781 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10782 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10783 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10784 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10785 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10786 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10787 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10789 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10790 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10791 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10792 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10793 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10794 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10795 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10796 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10797 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10798 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10799 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10800 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10801 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10802 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10803 case 'i': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10804 case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
10807 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10808 c, opc->name, opc->args);
10812 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10813 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10815 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10816 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10817 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10818 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10820 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10821 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10823 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10824 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10826 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10827 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10828 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10829 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10830 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10831 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10832 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10833 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10834 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10835 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10836 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10837 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10838 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10839 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10840 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10841 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10842 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10844 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10845 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10846 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10847 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10849 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10850 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10851 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10852 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10853 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10854 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10855 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10856 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10857 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10860 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10861 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10862 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10863 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10864 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10865 case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break;
10866 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10867 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10868 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10869 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10870 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10871 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10872 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10873 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10874 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10875 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10876 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10877 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10878 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10879 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10880 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10881 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10882 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10883 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10884 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10886 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10887 c, opc->name, opc->args);
10891 if (used_bits != 0xffffffff)
10893 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10894 ~used_bits & 0xffffffff, opc->name, opc->args);
10900 /* For consistency checking, verify that the length implied matches the
10901 major opcode and that all bits are specified either by the match/mask
10902 part of the instruction definition, or by the operand list. */
10905 validate_micromips_insn (const struct mips_opcode *opc)
10907 unsigned long match = opc->match;
10908 unsigned long mask = opc->mask;
10909 const char *p = opc->args;
10910 unsigned long insn_bits;
10911 unsigned long used_bits;
10912 unsigned long major;
10913 unsigned int length;
10917 if ((mask & match) != match)
10919 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10920 opc->name, opc->args);
10923 length = micromips_insn_length (opc);
10924 if (length != 2 && length != 4)
10926 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10927 "%s %s"), length, opc->name, opc->args);
10930 major = match >> (10 + 8 * (length - 2));
10931 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10932 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10934 as_bad (_("Internal error: bad microMIPS opcode "
10935 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10939 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10940 insn_bits = 1 << 4 * length;
10941 insn_bits <<= 4 * length;
10944 #define USE_BITS(field) \
10945 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10956 case 'A': USE_BITS (EXTLSB); break;
10957 case 'B': USE_BITS (INSMSB); break;
10958 case 'C': USE_BITS (EXTMSBD); break;
10959 case 'E': USE_BITS (EXTLSB); break;
10960 case 'F': USE_BITS (INSMSB); break;
10961 case 'G': USE_BITS (EXTMSBD); break;
10962 case 'H': USE_BITS (EXTMSBD); break;
10963 case 'i': USE_BITS (TARGET); break;
10964 case 'j': USE_BITS (EVAOFFSET); break;
10966 as_bad (_("Internal error: bad mips opcode "
10967 "(unknown extension operand type `%c%c'): %s %s"),
10968 e, c, opc->name, opc->args);
10976 case 'A': USE_BITS (IMMA); break;
10977 case 'B': USE_BITS (IMMB); break;
10978 case 'C': USE_BITS (IMMC); break;
10979 case 'D': USE_BITS (IMMD); break;
10980 case 'E': USE_BITS (IMME); break;
10981 case 'F': USE_BITS (IMMF); break;
10982 case 'G': USE_BITS (IMMG); break;
10983 case 'H': USE_BITS (IMMH); break;
10984 case 'I': USE_BITS (IMMI); break;
10985 case 'J': USE_BITS (IMMJ); break;
10986 case 'L': USE_BITS (IMML); break;
10987 case 'M': USE_BITS (IMMM); break;
10988 case 'N': USE_BITS (IMMN); break;
10989 case 'O': USE_BITS (IMMO); break;
10990 case 'P': USE_BITS (IMMP); break;
10991 case 'Q': USE_BITS (IMMQ); break;
10992 case 'U': USE_BITS (IMMU); break;
10993 case 'W': USE_BITS (IMMW); break;
10994 case 'X': USE_BITS (IMMX); break;
10995 case 'Y': USE_BITS (IMMY); break;
10998 case 'b': USE_BITS (MB); break;
10999 case 'c': USE_BITS (MC); break;
11000 case 'd': USE_BITS (MD); break;
11001 case 'e': USE_BITS (ME); break;
11002 case 'f': USE_BITS (MF); break;
11003 case 'g': USE_BITS (MG); break;
11004 case 'h': USE_BITS (MH); break;
11005 case 'j': USE_BITS (MJ); break;
11006 case 'l': USE_BITS (ML); break;
11007 case 'm': USE_BITS (MM); break;
11008 case 'n': USE_BITS (MN); break;
11009 case 'p': USE_BITS (MP); break;
11010 case 'q': USE_BITS (MQ); break;
11018 as_bad (_("Internal error: bad mips opcode "
11019 "(unknown extension operand type `%c%c'): %s %s"),
11020 e, c, opc->name, opc->args);
11024 case '.': USE_BITS (OFFSET10); break;
11025 case '1': USE_BITS (STYPE); break;
11026 case '2': USE_BITS (BP); break;
11027 case '3': USE_BITS (SA3); break;
11028 case '4': USE_BITS (SA4); break;
11029 case '5': USE_BITS (IMM8); break;
11030 case '6': USE_BITS (RS); break;
11031 case '7': USE_BITS (DSPACC); break;
11032 case '8': USE_BITS (WRDSP); break;
11033 case '0': USE_BITS (DSPSFT); break;
11034 case '<': USE_BITS (SHAMT); break;
11035 case '>': USE_BITS (SHAMT); break;
11036 case '@': USE_BITS (IMM10); break;
11037 case 'B': USE_BITS (CODE10); break;
11038 case 'C': USE_BITS (COPZ); break;
11039 case 'D': USE_BITS (FD); break;
11040 case 'E': USE_BITS (RT); break;
11041 case 'G': USE_BITS (RS); break;
11042 case 'H': USE_BITS (SEL); break;
11043 case 'K': USE_BITS (RS); break;
11044 case 'M': USE_BITS (CCC); break;
11045 case 'N': USE_BITS (BCC); break;
11046 case 'R': USE_BITS (FR); break;
11047 case 'S': USE_BITS (FS); break;
11048 case 'T': USE_BITS (FT); break;
11049 case 'V': USE_BITS (FS); break;
11050 case '\\': USE_BITS (3BITPOS); break;
11051 case '^': USE_BITS (RD); break;
11052 case 'a': USE_BITS (TARGET); break;
11053 case 'b': USE_BITS (RS); break;
11054 case 'c': USE_BITS (CODE); break;
11055 case 'd': USE_BITS (RD); break;
11056 case 'h': USE_BITS (PREFX); break;
11057 case 'i': USE_BITS (IMMEDIATE); break;
11058 case 'j': USE_BITS (DELTA); break;
11059 case 'k': USE_BITS (CACHE); break;
11060 case 'n': USE_BITS (RT); break;
11061 case 'o': USE_BITS (DELTA); break;
11062 case 'p': USE_BITS (DELTA); break;
11063 case 'q': USE_BITS (CODE2); break;
11064 case 'r': USE_BITS (RS); break;
11065 case 's': USE_BITS (RS); break;
11066 case 't': USE_BITS (RT); break;
11067 case 'u': USE_BITS (IMMEDIATE); break;
11068 case 'v': USE_BITS (RS); break;
11069 case 'w': USE_BITS (RT); break;
11070 case 'y': USE_BITS (RS3); break;
11072 case '|': USE_BITS (TRAP); break;
11073 case '~': USE_BITS (OFFSET12); break;
11075 as_bad (_("Internal error: bad microMIPS opcode "
11076 "(unknown operand type `%c'): %s %s"),
11077 c, opc->name, opc->args);
11081 if (used_bits != insn_bits)
11083 if (~used_bits & insn_bits)
11084 as_bad (_("Internal error: bad microMIPS opcode "
11085 "(bits 0x%lx undefined): %s %s"),
11086 ~used_bits & insn_bits, opc->name, opc->args);
11087 if (used_bits & ~insn_bits)
11088 as_bad (_("Internal error: bad microMIPS opcode "
11089 "(bits 0x%lx defined): %s %s"),
11090 used_bits & ~insn_bits, opc->name, opc->args);
11096 /* UDI immediates. */
11097 struct mips_immed {
11099 unsigned int shift;
11100 unsigned long mask;
11104 static const struct mips_immed mips_immed[] = {
11105 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
11106 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
11107 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
11108 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
11112 /* Check whether an odd floating-point register is allowed. */
11114 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
11116 const char *s = insn->name;
11118 if (insn->pinfo == INSN_MACRO)
11119 /* Let a macro pass, we'll catch it later when it is expanded. */
11122 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
11124 /* Allow odd registers for single-precision ops. */
11125 switch (insn->pinfo & (FP_S | FP_D))
11129 return 1; /* both single precision - ok */
11131 return 0; /* both double precision - fail */
11136 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11137 s = strchr (insn->name, '.');
11139 s = s != NULL ? strchr (s + 1, '.') : NULL;
11140 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
11143 /* Single-precision coprocessor loads and moves are OK too. */
11144 if ((insn->pinfo & FP_S)
11145 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
11146 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
11152 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11153 taking bits from BIT up. */
11155 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
11157 return (ep->X_op == O_constant
11158 && (ep->X_add_number & ((1 << bit) - 1)) == 0
11159 && ep->X_add_number >= min << bit
11160 && ep->X_add_number < max << bit);
11163 /* Assemble an instruction into its binary format. If the instruction
11164 is a macro, set imm_expr, imm2_expr and offset_expr to the values
11165 associated with "I", "+I" and "A" operands respectively. Otherwise
11166 store the value of the relocatable field (if any) in offset_expr.
11167 In both cases set offset_reloc to the relocation operators applied
11171 mips_ip (char *str, struct mips_cl_insn *ip)
11173 bfd_boolean wrong_delay_slot_insns = FALSE;
11174 bfd_boolean need_delay_slot_ok = TRUE;
11175 struct mips_opcode *firstinsn = NULL;
11176 const struct mips_opcode *past;
11177 struct hash_control *hash;
11181 struct mips_opcode *insn;
11183 unsigned int regno, regno2;
11184 unsigned int lastregno;
11185 unsigned int destregno = 0;
11186 unsigned int lastpos = 0;
11187 unsigned int limlo, limhi;
11190 offsetT min_range, max_range;
11194 unsigned int rtype;
11200 if (mips_opts.micromips)
11202 hash = micromips_op_hash;
11203 past = µmips_opcodes[bfd_micromips_num_opcodes];
11208 past = &mips_opcodes[NUMOPCODES];
11210 forced_insn_length = 0;
11213 /* We first try to match an instruction up to a space or to the end. */
11214 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
11217 /* Make a copy of the instruction so that we can fiddle with it. */
11218 name = alloca (end + 1);
11219 memcpy (name, str, end);
11224 insn = (struct mips_opcode *) hash_find (hash, name);
11226 if (insn != NULL || !mips_opts.micromips)
11228 if (forced_insn_length)
11231 /* See if there's an instruction size override suffix,
11232 either `16' or `32', at the end of the mnemonic proper,
11233 that defines the operation, i.e. before the first `.'
11234 character if any. Strip it and retry. */
11235 dot = strchr (name, '.');
11236 opend = dot != NULL ? dot - name : end;
11239 if (name[opend - 2] == '1' && name[opend - 1] == '6')
11240 forced_insn_length = 2;
11241 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
11242 forced_insn_length = 4;
11245 memcpy (name + opend - 2, name + opend, end - opend + 1);
11249 insn_error = _("Unrecognized opcode");
11253 /* For microMIPS instructions placed in a fixed-length branch delay slot
11254 we make up to two passes over the relevant fragment of the opcode
11255 table. First we try instructions that meet the delay slot's length
11256 requirement. If none matched, then we retry with the remaining ones
11257 and if one matches, then we use it and then issue an appropriate
11258 warning later on. */
11259 argsStart = s = str + end;
11262 bfd_boolean delay_slot_ok;
11263 bfd_boolean size_ok;
11266 gas_assert (strcmp (insn->name, name) == 0);
11268 ok = is_opcode_valid (insn);
11269 size_ok = is_size_valid (insn);
11270 delay_slot_ok = is_delay_slot_valid (insn);
11271 if (!delay_slot_ok && !wrong_delay_slot_insns)
11274 wrong_delay_slot_insns = TRUE;
11276 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
11278 static char buf[256];
11280 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
11285 if (wrong_delay_slot_insns && need_delay_slot_ok)
11287 gas_assert (firstinsn);
11288 need_delay_slot_ok = FALSE;
11298 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
11299 mips_cpu_info_from_arch (mips_opts.arch)->name,
11300 mips_cpu_info_from_isa (mips_opts.isa)->name);
11301 else if (mips_opts.insn32)
11302 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
11304 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
11305 8 * forced_insn_length);
11311 imm_expr.X_op = O_absent;
11312 imm2_expr.X_op = O_absent;
11313 offset_expr.X_op = O_absent;
11314 offset_reloc[0] = BFD_RELOC_UNUSED;
11315 offset_reloc[1] = BFD_RELOC_UNUSED;
11316 offset_reloc[2] = BFD_RELOC_UNUSED;
11318 create_insn (ip, insn);
11321 lastregno = 0xffffffff;
11322 for (args = insn->args;; ++args)
11326 s += strspn (s, " \t");
11330 case '\0': /* end of args */
11336 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11337 code) or 14 (for microMIPS code). */
11338 my_getExpression (&imm_expr, s);
11339 check_absolute_expr (ip, &imm_expr);
11340 if ((unsigned long) imm_expr.X_add_number != 1
11341 && (unsigned long) imm_expr.X_add_number != 3)
11343 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11344 (unsigned long) imm_expr.X_add_number);
11346 INSERT_OPERAND (mips_opts.micromips,
11347 BP, *ip, imm_expr.X_add_number);
11348 imm_expr.X_op = O_absent;
11353 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11354 code) or 13 (for microMIPS code). */
11356 unsigned long mask = (mips_opts.micromips
11357 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11359 my_getExpression (&imm_expr, s);
11360 check_absolute_expr (ip, &imm_expr);
11361 if ((unsigned long) imm_expr.X_add_number > mask)
11362 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11363 mask, (unsigned long) imm_expr.X_add_number);
11364 INSERT_OPERAND (mips_opts.micromips,
11365 SA3, *ip, imm_expr.X_add_number);
11366 imm_expr.X_op = O_absent;
11372 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11373 code) or 12 (for microMIPS code). */
11375 unsigned long mask = (mips_opts.micromips
11376 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11378 my_getExpression (&imm_expr, s);
11379 check_absolute_expr (ip, &imm_expr);
11380 if ((unsigned long) imm_expr.X_add_number > mask)
11381 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11382 mask, (unsigned long) imm_expr.X_add_number);
11383 INSERT_OPERAND (mips_opts.micromips,
11384 SA4, *ip, imm_expr.X_add_number);
11385 imm_expr.X_op = O_absent;
11391 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11392 code) or 13 (for microMIPS code). */
11394 unsigned long mask = (mips_opts.micromips
11395 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11397 my_getExpression (&imm_expr, s);
11398 check_absolute_expr (ip, &imm_expr);
11399 if ((unsigned long) imm_expr.X_add_number > mask)
11400 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11401 mask, (unsigned long) imm_expr.X_add_number);
11402 INSERT_OPERAND (mips_opts.micromips,
11403 IMM8, *ip, imm_expr.X_add_number);
11404 imm_expr.X_op = O_absent;
11410 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11411 code) or 16 (for microMIPS code). */
11413 unsigned long mask = (mips_opts.micromips
11414 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11416 my_getExpression (&imm_expr, s);
11417 check_absolute_expr (ip, &imm_expr);
11418 if ((unsigned long) imm_expr.X_add_number > mask)
11419 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11420 mask, (unsigned long) imm_expr.X_add_number);
11421 INSERT_OPERAND (mips_opts.micromips,
11422 RS, *ip, imm_expr.X_add_number);
11423 imm_expr.X_op = O_absent;
11429 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11430 or 14 (for microMIPS code). */
11431 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11432 && s[3] >= '0' && s[3] <= '3')
11434 regno = s[3] - '0';
11436 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11440 as_bad (_("Invalid dsp acc register"));
11444 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11445 code) or 14 (for microMIPS code). */
11447 unsigned long mask = (mips_opts.micromips
11448 ? MICROMIPSOP_MASK_WRDSP
11451 my_getExpression (&imm_expr, s);
11452 check_absolute_expr (ip, &imm_expr);
11453 if ((unsigned long) imm_expr.X_add_number > mask)
11454 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11455 mask, (unsigned long) imm_expr.X_add_number);
11456 INSERT_OPERAND (mips_opts.micromips,
11457 WRDSP, *ip, imm_expr.X_add_number);
11458 imm_expr.X_op = O_absent;
11463 case '9': /* Four DSP accumulators in bits 21,22. */
11464 gas_assert (!mips_opts.micromips);
11465 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11466 && s[3] >= '0' && s[3] <= '3')
11468 regno = s[3] - '0';
11470 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11474 as_bad (_("Invalid dsp acc register"));
11478 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11479 code) or 16 (for microMIPS code). */
11481 long mask = (mips_opts.micromips
11482 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11484 my_getExpression (&imm_expr, s);
11485 check_absolute_expr (ip, &imm_expr);
11486 min_range = -((mask + 1) >> 1);
11487 max_range = ((mask + 1) >> 1) - 1;
11488 if (imm_expr.X_add_number < min_range
11489 || imm_expr.X_add_number > max_range)
11490 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11491 (long) min_range, (long) max_range,
11492 (long) imm_expr.X_add_number);
11493 INSERT_OPERAND (mips_opts.micromips,
11494 DSPSFT, *ip, imm_expr.X_add_number);
11495 imm_expr.X_op = O_absent;
11500 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11501 gas_assert (!mips_opts.micromips);
11502 my_getExpression (&imm_expr, s);
11503 check_absolute_expr (ip, &imm_expr);
11504 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11506 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11508 (unsigned long) imm_expr.X_add_number);
11510 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11511 imm_expr.X_op = O_absent;
11515 case ':': /* DSP 7-bit signed immediate in bit 19. */
11516 gas_assert (!mips_opts.micromips);
11517 my_getExpression (&imm_expr, s);
11518 check_absolute_expr (ip, &imm_expr);
11519 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11520 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11521 if (imm_expr.X_add_number < min_range ||
11522 imm_expr.X_add_number > max_range)
11524 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11525 (long) min_range, (long) max_range,
11526 (long) imm_expr.X_add_number);
11528 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11529 imm_expr.X_op = O_absent;
11533 case '@': /* DSP 10-bit signed immediate in bit 16. */
11535 long mask = (mips_opts.micromips
11536 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11538 my_getExpression (&imm_expr, s);
11539 check_absolute_expr (ip, &imm_expr);
11540 min_range = -((mask + 1) >> 1);
11541 max_range = ((mask + 1) >> 1) - 1;
11542 if (imm_expr.X_add_number < min_range
11543 || imm_expr.X_add_number > max_range)
11544 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11545 (long) min_range, (long) max_range,
11546 (long) imm_expr.X_add_number);
11547 INSERT_OPERAND (mips_opts.micromips,
11548 IMM10, *ip, imm_expr.X_add_number);
11549 imm_expr.X_op = O_absent;
11554 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11555 gas_assert (mips_opts.micromips);
11556 my_getExpression (&imm_expr, s);
11557 check_absolute_expr (ip, &imm_expr);
11558 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11559 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11560 MICROMIPSOP_MASK_RD,
11561 (unsigned long) imm_expr.X_add_number);
11562 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11563 imm_expr.X_op = O_absent;
11567 case '!': /* MT usermode flag bit. */
11568 gas_assert (!mips_opts.micromips);
11569 my_getExpression (&imm_expr, s);
11570 check_absolute_expr (ip, &imm_expr);
11571 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11572 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11573 (unsigned long) imm_expr.X_add_number);
11574 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11575 imm_expr.X_op = O_absent;
11579 case '$': /* MT load high flag bit. */
11580 gas_assert (!mips_opts.micromips);
11581 my_getExpression (&imm_expr, s);
11582 check_absolute_expr (ip, &imm_expr);
11583 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11584 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11585 (unsigned long) imm_expr.X_add_number);
11586 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11587 imm_expr.X_op = O_absent;
11591 case '*': /* Four DSP accumulators in bits 18,19. */
11592 gas_assert (!mips_opts.micromips);
11593 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11594 s[3] >= '0' && s[3] <= '3')
11596 regno = s[3] - '0';
11598 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11602 as_bad (_("Invalid dsp/smartmips acc register"));
11605 case '&': /* Four DSP accumulators in bits 13,14. */
11606 gas_assert (!mips_opts.micromips);
11607 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11608 s[3] >= '0' && s[3] <= '3')
11610 regno = s[3] - '0';
11612 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11616 as_bad (_("Invalid dsp/smartmips acc register"));
11619 case '\\': /* 3-bit bit position. */
11621 unsigned long mask = (mips_opts.micromips
11622 ? MICROMIPSOP_MASK_3BITPOS
11623 : OP_MASK_3BITPOS);
11625 my_getExpression (&imm_expr, s);
11626 check_absolute_expr (ip, &imm_expr);
11627 if ((unsigned long) imm_expr.X_add_number > mask)
11628 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11630 mask, (unsigned long) imm_expr.X_add_number);
11631 INSERT_OPERAND (mips_opts.micromips,
11632 3BITPOS, *ip, imm_expr.X_add_number);
11633 imm_expr.X_op = O_absent;
11647 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11651 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11655 gas_assert (!mips_opts.micromips);
11656 INSERT_OPERAND (0, FT, *ip, lastregno);
11660 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11666 /* Handle optional base register.
11667 Either the base register is omitted or
11668 we must have a left paren. */
11669 /* This is dependent on the next operand specifier
11670 is a base register specification. */
11671 gas_assert (args[1] == 'b'
11672 || (mips_opts.micromips
11674 && (args[2] == 'l' || args[2] == 'n'
11675 || args[2] == 's' || args[2] == 'a')));
11676 if (*s == '\0' && args[1] == 'b')
11678 /* Fall through. */
11680 case ')': /* These must match exactly. */
11685 case '+': /* Opcode extension character. */
11688 case '1': /* UDI immediates. */
11692 gas_assert (!mips_opts.micromips);
11694 const struct mips_immed *imm = mips_immed;
11696 while (imm->type && imm->type != *args)
11700 my_getExpression (&imm_expr, s);
11701 check_absolute_expr (ip, &imm_expr);
11702 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11704 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11705 imm->desc ? imm->desc : ip->insn_mo->name,
11706 (unsigned long) imm_expr.X_add_number,
11707 (unsigned long) imm_expr.X_add_number);
11708 imm_expr.X_add_number &= imm->mask;
11710 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11712 imm_expr.X_op = O_absent;
11717 case 'J': /* 10-bit hypcall code. */
11718 gas_assert (!mips_opts.micromips);
11720 unsigned long mask = OP_MASK_CODE10;
11722 my_getExpression (&imm_expr, s);
11723 check_absolute_expr (ip, &imm_expr);
11724 if ((unsigned long) imm_expr.X_add_number > mask)
11725 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11727 mask, (unsigned long) imm_expr.X_add_number);
11728 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11729 imm_expr.X_op = O_absent;
11734 case 'A': /* ins/ext position, becomes LSB. */
11743 my_getExpression (&imm_expr, s);
11744 check_absolute_expr (ip, &imm_expr);
11745 if ((unsigned long) imm_expr.X_add_number < limlo
11746 || (unsigned long) imm_expr.X_add_number > limhi)
11748 as_bad (_("Improper position (%lu)"),
11749 (unsigned long) imm_expr.X_add_number);
11750 imm_expr.X_add_number = limlo;
11752 lastpos = imm_expr.X_add_number;
11753 INSERT_OPERAND (mips_opts.micromips,
11754 EXTLSB, *ip, imm_expr.X_add_number);
11755 imm_expr.X_op = O_absent;
11759 case 'B': /* ins size, becomes MSB. */
11768 my_getExpression (&imm_expr, s);
11769 check_absolute_expr (ip, &imm_expr);
11770 /* Check for negative input so that small negative numbers
11771 will not succeed incorrectly. The checks against
11772 (pos+size) transitively check "size" itself,
11773 assuming that "pos" is reasonable. */
11774 if ((long) imm_expr.X_add_number < 0
11775 || ((unsigned long) imm_expr.X_add_number
11777 || ((unsigned long) imm_expr.X_add_number
11778 + lastpos) > limhi)
11780 as_bad (_("Improper insert size (%lu, position %lu)"),
11781 (unsigned long) imm_expr.X_add_number,
11782 (unsigned long) lastpos);
11783 imm_expr.X_add_number = limlo - lastpos;
11785 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11786 lastpos + imm_expr.X_add_number - 1);
11787 imm_expr.X_op = O_absent;
11791 case 'C': /* ext size, becomes MSBD. */
11807 my_getExpression (&imm_expr, s);
11808 check_absolute_expr (ip, &imm_expr);
11809 /* The checks against (pos+size) don't transitively check
11810 "size" itself, assuming that "pos" is reasonable.
11811 We also need to check the lower bound of "size". */
11812 if ((long) imm_expr.X_add_number < sizelo
11813 || ((unsigned long) imm_expr.X_add_number
11815 || ((unsigned long) imm_expr.X_add_number
11816 + lastpos) > limhi)
11818 as_bad (_("Improper extract size (%lu, position %lu)"),
11819 (unsigned long) imm_expr.X_add_number,
11820 (unsigned long) lastpos);
11821 imm_expr.X_add_number = limlo - lastpos;
11823 INSERT_OPERAND (mips_opts.micromips,
11824 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11825 imm_expr.X_op = O_absent;
11830 /* "+I" is like "I", except that imm2_expr is used. */
11831 my_getExpression (&imm2_expr, s);
11832 if (imm2_expr.X_op != O_big
11833 && imm2_expr.X_op != O_constant)
11834 insn_error = _("absolute expression required");
11835 if (HAVE_32BIT_GPRS)
11836 normalize_constant_expr (&imm2_expr);
11840 case 't': /* Coprocessor register number. */
11841 gas_assert (!mips_opts.micromips);
11842 if (s[0] == '$' && ISDIGIT (s[1]))
11852 while (ISDIGIT (*s));
11854 as_bad (_("Invalid register number (%d)"), regno);
11857 INSERT_OPERAND (0, RT, *ip, regno);
11862 as_bad (_("Invalid coprocessor 0 register number"));
11866 /* bbit[01] and bbit[01]32 bit index. Give error if index
11867 is not in the valid range. */
11868 gas_assert (!mips_opts.micromips);
11869 my_getExpression (&imm_expr, s);
11870 check_absolute_expr (ip, &imm_expr);
11871 if ((unsigned) imm_expr.X_add_number > 31)
11873 as_bad (_("Improper bit index (%lu)"),
11874 (unsigned long) imm_expr.X_add_number);
11875 imm_expr.X_add_number = 0;
11877 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11878 imm_expr.X_op = O_absent;
11883 /* bbit[01] bit index when bbit is used but we generate
11884 bbit[01]32 because the index is over 32. Move to the
11885 next candidate if index is not in the valid range. */
11886 gas_assert (!mips_opts.micromips);
11887 my_getExpression (&imm_expr, s);
11888 check_absolute_expr (ip, &imm_expr);
11889 if ((unsigned) imm_expr.X_add_number < 32
11890 || (unsigned) imm_expr.X_add_number > 63)
11892 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11893 imm_expr.X_op = O_absent;
11898 /* cins, cins32, exts and exts32 position field. Give error
11899 if it's not in the valid range. */
11900 gas_assert (!mips_opts.micromips);
11901 my_getExpression (&imm_expr, s);
11902 check_absolute_expr (ip, &imm_expr);
11903 if ((unsigned) imm_expr.X_add_number > 31)
11905 as_bad (_("Improper position (%lu)"),
11906 (unsigned long) imm_expr.X_add_number);
11907 imm_expr.X_add_number = 0;
11909 lastpos = imm_expr.X_add_number;
11910 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11911 imm_expr.X_op = O_absent;
11916 /* cins, cins32, exts and exts32 position field. Move to
11917 the next candidate if it's not in the valid range. */
11918 gas_assert (!mips_opts.micromips);
11919 my_getExpression (&imm_expr, s);
11920 check_absolute_expr (ip, &imm_expr);
11921 if ((unsigned) imm_expr.X_add_number < 32
11922 || (unsigned) imm_expr.X_add_number > 63)
11924 lastpos = imm_expr.X_add_number;
11925 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11926 imm_expr.X_op = O_absent;
11931 /* cins32 and exts32 length-minus-one field. */
11932 gas_assert (!mips_opts.micromips);
11933 my_getExpression (&imm_expr, s);
11934 check_absolute_expr (ip, &imm_expr);
11935 if ((unsigned long) imm_expr.X_add_number > 31
11936 || (unsigned long) imm_expr.X_add_number + lastpos > 31)
11938 as_bad (_("Improper size (%lu)"),
11939 (unsigned long) imm_expr.X_add_number);
11940 imm_expr.X_add_number = 0;
11942 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11943 imm_expr.X_op = O_absent;
11948 /* cins/exts length-minus-one field. */
11949 gas_assert (!mips_opts.micromips);
11950 my_getExpression (&imm_expr, s);
11951 check_absolute_expr (ip, &imm_expr);
11952 if ((unsigned long) imm_expr.X_add_number > 31
11953 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11955 as_bad (_("Improper size (%lu)"),
11956 (unsigned long) imm_expr.X_add_number);
11957 imm_expr.X_add_number = 0;
11959 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11960 imm_expr.X_op = O_absent;
11965 /* seqi/snei immediate field. */
11966 gas_assert (!mips_opts.micromips);
11967 my_getExpression (&imm_expr, s);
11968 check_absolute_expr (ip, &imm_expr);
11969 if ((long) imm_expr.X_add_number < -512
11970 || (long) imm_expr.X_add_number >= 512)
11972 as_bad (_("Improper immediate (%ld)"),
11973 (long) imm_expr.X_add_number);
11974 imm_expr.X_add_number = 0;
11976 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11977 imm_expr.X_op = O_absent;
11981 case 'a': /* 8-bit signed offset in bit 6 */
11982 gas_assert (!mips_opts.micromips);
11983 my_getExpression (&imm_expr, s);
11984 check_absolute_expr (ip, &imm_expr);
11985 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11986 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11987 if (imm_expr.X_add_number < min_range
11988 || imm_expr.X_add_number > max_range)
11990 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11991 (long) min_range, (long) max_range,
11992 (long) imm_expr.X_add_number);
11994 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11995 imm_expr.X_op = O_absent;
11999 case 'b': /* 8-bit signed offset in bit 3 */
12000 gas_assert (!mips_opts.micromips);
12001 my_getExpression (&imm_expr, s);
12002 check_absolute_expr (ip, &imm_expr);
12003 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
12004 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
12005 if (imm_expr.X_add_number < min_range
12006 || imm_expr.X_add_number > max_range)
12008 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12009 (long) min_range, (long) max_range,
12010 (long) imm_expr.X_add_number);
12012 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
12013 imm_expr.X_op = O_absent;
12017 case 'c': /* 9-bit signed offset in bit 6 */
12018 gas_assert (!mips_opts.micromips);
12019 my_getExpression (&imm_expr, s);
12020 check_absolute_expr (ip, &imm_expr);
12021 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
12022 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
12023 /* We check the offset range before adjusted. */
12026 if (imm_expr.X_add_number < min_range
12027 || imm_expr.X_add_number > max_range)
12029 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12030 (long) min_range, (long) max_range,
12031 (long) imm_expr.X_add_number);
12033 if (imm_expr.X_add_number & 0xf)
12035 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12036 (long) imm_expr.X_add_number);
12038 /* Right shift 4 bits to adjust the offset operand. */
12039 INSERT_OPERAND (0, OFFSET_C, *ip,
12040 imm_expr.X_add_number >> 4);
12041 imm_expr.X_op = O_absent;
12046 gas_assert (!mips_opts.micromips);
12047 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
12049 if (regno == AT && mips_opts.at)
12051 if (mips_opts.at == ATREG)
12052 as_warn (_("used $at without \".set noat\""));
12054 as_warn (_("used $%u with \".set at=$%u\""),
12055 regno, mips_opts.at);
12057 INSERT_OPERAND (0, RZ, *ip, regno);
12061 gas_assert (!mips_opts.micromips);
12062 if (!reg_lookup (&s, RTYPE_FPU, ®no))
12064 INSERT_OPERAND (0, FZ, *ip, regno);
12074 bfd_reloc_code_real_type r[3];
12076 /* Check whether there is only a single bracketed expression
12077 left. If so, it must be the base register and the
12078 constant must be zero. */
12079 if (*s == '(' && strchr (s + 1, '(') == 0)
12082 /* If this value won't fit into the offset, then go find
12083 a macro that will generate a 16- or 32-bit offset code
12085 i = my_getSmallExpression (&imm_expr, r, s);
12086 if ((i == 0 && (imm_expr.X_op != O_constant
12087 || imm_expr.X_add_number >= 1 << shift
12088 || imm_expr.X_add_number < -1 << shift))
12091 imm_expr.X_op = O_absent;
12094 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
12095 imm_expr.X_add_number);
12096 imm_expr.X_op = O_absent;
12102 as_bad (_("Internal error: bad %s opcode "
12103 "(unknown extension operand type `+%c'): %s %s"),
12104 mips_opts.micromips ? "microMIPS" : "MIPS",
12105 *args, insn->name, insn->args);
12106 /* Further processing is fruitless. */
12111 case '.': /* 10-bit offset. */
12112 gas_assert (mips_opts.micromips);
12113 case '~': /* 12-bit offset. */
12115 int shift = *args == '.' ? 9 : 11;
12117 bfd_reloc_code_real_type r[3];
12119 /* Check whether there is only a single bracketed expression
12120 left. If so, it must be the base register and the
12121 constant must be zero. */
12122 if (*s == '(' && strchr (s + 1, '(') == 0)
12125 /* If this value won't fit into the offset, then go find
12126 a macro that will generate a 16- or 32-bit offset code
12128 i = my_getSmallExpression (&imm_expr, r, s);
12129 if ((i == 0 && (imm_expr.X_op != O_constant
12130 || imm_expr.X_add_number >= 1 << shift
12131 || imm_expr.X_add_number < -1 << shift))
12134 imm_expr.X_op = O_absent;
12138 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
12140 INSERT_OPERAND (mips_opts.micromips,
12141 OFFSET12, *ip, imm_expr.X_add_number);
12142 imm_expr.X_op = O_absent;
12147 case '<': /* must be at least one digit */
12149 * According to the manual, if the shift amount is greater
12150 * than 31 or less than 0, then the shift amount should be
12151 * mod 32. In reality the mips assembler issues an error.
12152 * We issue a warning and mask out all but the low 5 bits.
12154 my_getExpression (&imm_expr, s);
12155 check_absolute_expr (ip, &imm_expr);
12156 if ((unsigned long) imm_expr.X_add_number > 31)
12157 as_warn (_("Improper shift amount (%lu)"),
12158 (unsigned long) imm_expr.X_add_number);
12159 INSERT_OPERAND (mips_opts.micromips,
12160 SHAMT, *ip, imm_expr.X_add_number);
12161 imm_expr.X_op = O_absent;
12165 case '>': /* shift amount minus 32 */
12166 my_getExpression (&imm_expr, s);
12167 check_absolute_expr (ip, &imm_expr);
12168 if ((unsigned long) imm_expr.X_add_number < 32
12169 || (unsigned long) imm_expr.X_add_number > 63)
12171 INSERT_OPERAND (mips_opts.micromips,
12172 SHAMT, *ip, imm_expr.X_add_number - 32);
12173 imm_expr.X_op = O_absent;
12177 case 'k': /* CACHE code. */
12178 case 'h': /* PREFX code. */
12179 case '1': /* SYNC type. */
12180 my_getExpression (&imm_expr, s);
12181 check_absolute_expr (ip, &imm_expr);
12182 if ((unsigned long) imm_expr.X_add_number > 31)
12183 as_warn (_("Invalid value for `%s' (%lu)"),
12185 (unsigned long) imm_expr.X_add_number);
12189 if (mips_fix_cn63xxp1
12190 && !mips_opts.micromips
12191 && strcmp ("pref", insn->name) == 0)
12192 switch (imm_expr.X_add_number)
12201 case 31: /* These are ok. */
12204 default: /* The rest must be changed to 28. */
12205 imm_expr.X_add_number = 28;
12208 INSERT_OPERAND (mips_opts.micromips,
12209 CACHE, *ip, imm_expr.X_add_number);
12212 INSERT_OPERAND (mips_opts.micromips,
12213 PREFX, *ip, imm_expr.X_add_number);
12216 INSERT_OPERAND (mips_opts.micromips,
12217 STYPE, *ip, imm_expr.X_add_number);
12220 imm_expr.X_op = O_absent;
12224 case 'c': /* BREAK code. */
12226 unsigned long mask = (mips_opts.micromips
12227 ? MICROMIPSOP_MASK_CODE
12230 my_getExpression (&imm_expr, s);
12231 check_absolute_expr (ip, &imm_expr);
12232 if ((unsigned long) imm_expr.X_add_number > mask)
12233 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12235 mask, (unsigned long) imm_expr.X_add_number);
12236 INSERT_OPERAND (mips_opts.micromips,
12237 CODE, *ip, imm_expr.X_add_number);
12238 imm_expr.X_op = O_absent;
12243 case 'q': /* Lower BREAK code. */
12245 unsigned long mask = (mips_opts.micromips
12246 ? MICROMIPSOP_MASK_CODE2
12249 my_getExpression (&imm_expr, s);
12250 check_absolute_expr (ip, &imm_expr);
12251 if ((unsigned long) imm_expr.X_add_number > mask)
12252 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12254 mask, (unsigned long) imm_expr.X_add_number);
12255 INSERT_OPERAND (mips_opts.micromips,
12256 CODE2, *ip, imm_expr.X_add_number);
12257 imm_expr.X_op = O_absent;
12262 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12264 unsigned long mask = (mips_opts.micromips
12265 ? MICROMIPSOP_MASK_CODE10
12268 my_getExpression (&imm_expr, s);
12269 check_absolute_expr (ip, &imm_expr);
12270 if ((unsigned long) imm_expr.X_add_number > mask)
12271 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12273 mask, (unsigned long) imm_expr.X_add_number);
12274 if (mips_opts.micromips)
12275 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
12277 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
12278 imm_expr.X_op = O_absent;
12283 case 'C': /* 25- or 23-bit coprocessor code. */
12285 unsigned long mask = (mips_opts.micromips
12286 ? MICROMIPSOP_MASK_COPZ
12289 my_getExpression (&imm_expr, s);
12290 check_absolute_expr (ip, &imm_expr);
12291 if ((unsigned long) imm_expr.X_add_number > mask)
12292 as_warn (_("Coproccesor code > %u bits (%lu)"),
12293 mips_opts.micromips ? 23U : 25U,
12294 (unsigned long) imm_expr.X_add_number);
12295 INSERT_OPERAND (mips_opts.micromips,
12296 COPZ, *ip, imm_expr.X_add_number);
12297 imm_expr.X_op = O_absent;
12302 case 'J': /* 19-bit WAIT code. */
12303 gas_assert (!mips_opts.micromips);
12304 my_getExpression (&imm_expr, s);
12305 check_absolute_expr (ip, &imm_expr);
12306 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
12308 as_warn (_("Illegal 19-bit code (%lu)"),
12309 (unsigned long) imm_expr.X_add_number);
12310 imm_expr.X_add_number &= OP_MASK_CODE19;
12312 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
12313 imm_expr.X_op = O_absent;
12317 case 'P': /* Performance register. */
12318 gas_assert (!mips_opts.micromips);
12319 my_getExpression (&imm_expr, s);
12320 check_absolute_expr (ip, &imm_expr);
12321 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
12322 as_warn (_("Invalid performance register (%lu)"),
12323 (unsigned long) imm_expr.X_add_number);
12324 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
12325 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
12326 as_warn (_("Invalid performance register (%lu)"),
12327 (unsigned long) imm_expr.X_add_number);
12328 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
12329 imm_expr.X_op = O_absent;
12333 case 'G': /* Coprocessor destination register. */
12335 unsigned long opcode = ip->insn_opcode;
12336 unsigned long mask;
12337 unsigned int types;
12340 if (mips_opts.micromips)
12342 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
12343 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
12344 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
12348 case 0x000000fc: /* mfc0 */
12349 case 0x000002fc: /* mtc0 */
12350 case 0x580000fc: /* dmfc0 */
12351 case 0x580002fc: /* dmtc0 */
12361 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12362 cop0 = opcode == OP_OP_COP0;
12364 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12365 ok = reg_lookup (&s, types, ®no);
12366 if (mips_opts.micromips)
12367 INSERT_OPERAND (1, RS, *ip, regno);
12369 INSERT_OPERAND (0, RD, *ip, regno);
12378 case 'y': /* ALNV.PS source register. */
12379 gas_assert (mips_opts.micromips);
12381 case 'x': /* Ignore register name. */
12382 case 'U': /* Destination register (CLO/CLZ). */
12383 case 'g': /* Coprocessor destination register. */
12384 gas_assert (!mips_opts.micromips);
12385 case 'b': /* Base register. */
12386 case 'd': /* Destination register. */
12387 case 's': /* Source register. */
12388 case 't': /* Target register. */
12389 case 'r': /* Both target and source. */
12390 case 'v': /* Both dest and source. */
12391 case 'w': /* Both dest and target. */
12392 case 'E': /* Coprocessor target register. */
12393 case 'K': /* RDHWR destination register. */
12394 case 'z': /* Must be zero register. */
12397 if (*args == 'E' || *args == 'K')
12398 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12401 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12402 if (regno == AT && mips_opts.at)
12404 if (mips_opts.at == ATREG)
12405 as_warn (_("Used $at without \".set noat\""));
12407 as_warn (_("Used $%u with \".set at=$%u\""),
12408 regno, mips_opts.at);
12418 if (c == 'r' || c == 'v' || c == 'w')
12425 /* 'z' only matches $0. */
12426 if (c == 'z' && regno != 0)
12429 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12431 if (regno == lastregno)
12434 = _("Source and destination must be different");
12437 if (regno == 31 && lastregno == 0xffffffff)
12440 = _("A destination register must be supplied");
12444 /* Now that we have assembled one operand, we use the args
12445 string to figure out where it goes in the instruction. */
12452 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12456 if (mips_opts.micromips)
12457 INSERT_OPERAND (1, RS, *ip, regno);
12459 INSERT_OPERAND (0, RD, *ip, regno);
12464 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12468 gas_assert (!mips_opts.micromips);
12469 INSERT_OPERAND (0, RD, *ip, regno);
12470 INSERT_OPERAND (0, RT, *ip, regno);
12476 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12480 gas_assert (mips_opts.micromips);
12481 INSERT_OPERAND (1, RS3, *ip, regno);
12485 /* This case exists because on the r3000 trunc
12486 expands into a macro which requires a gp
12487 register. On the r6000 or r4000 it is
12488 assembled into a single instruction which
12489 ignores the register. Thus the insn version
12490 is MIPS_ISA2 and uses 'x', and the macro
12491 version is MIPS_ISA1 and uses 't'. */
12495 /* This case is for the div instruction, which
12496 acts differently if the destination argument
12497 is $0. This only matches $0, and is checked
12498 outside the switch. */
12508 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12512 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12517 case 'O': /* MDMX alignment immediate constant. */
12518 gas_assert (!mips_opts.micromips);
12519 my_getExpression (&imm_expr, s);
12520 check_absolute_expr (ip, &imm_expr);
12521 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12522 as_warn (_("Improper align amount (%ld), using low bits"),
12523 (long) imm_expr.X_add_number);
12524 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12525 imm_expr.X_op = O_absent;
12529 case 'Q': /* MDMX vector, element sel, or const. */
12532 /* MDMX Immediate. */
12533 gas_assert (!mips_opts.micromips);
12534 my_getExpression (&imm_expr, s);
12535 check_absolute_expr (ip, &imm_expr);
12536 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12537 as_warn (_("Invalid MDMX Immediate (%ld)"),
12538 (long) imm_expr.X_add_number);
12539 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12540 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12541 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12543 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12544 imm_expr.X_op = O_absent;
12548 /* Not MDMX Immediate. Fall through. */
12549 case 'X': /* MDMX destination register. */
12550 case 'Y': /* MDMX source register. */
12551 case 'Z': /* MDMX target register. */
12552 is_mdmx = !(insn->membership & INSN_5400);
12554 gas_assert (!mips_opts.micromips);
12555 case 'D': /* Floating point destination register. */
12556 case 'S': /* Floating point source register. */
12557 case 'T': /* Floating point target register. */
12558 case 'R': /* Floating point source register. */
12562 || ((mips_opts.ase & ASE_MDMX)
12563 && (ip->insn_mo->pinfo & FP_D)
12564 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12565 | INSN_COPROC_MEMORY_DELAY
12566 | INSN_LOAD_COPROC_DELAY
12567 | INSN_LOAD_MEMORY_DELAY
12568 | INSN_STORE_MEMORY))))
12569 rtype |= RTYPE_VEC;
12571 if (reg_lookup (&s, rtype, ®no))
12573 if ((regno & 1) != 0
12575 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12576 as_warn (_("Float register should be even, was %d"),
12584 if (c == 'V' || c == 'W')
12595 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12601 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12605 /* This is like 'Z', but also needs to fix the MDMX
12606 vector/scalar select bits. Note that the
12607 scalar immediate case is handled above. */
12608 if ((ip->insn_mo->membership & INSN_5400)
12609 && strcmp (insn->name, "rzu.ob") == 0)
12610 as_bad (_("Operand %d of `%s' must be an immediate"),
12611 argnum, ip->insn_mo->name);
12615 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12616 int max_el = (is_qh ? 3 : 7);
12618 my_getExpression(&imm_expr, s);
12619 check_absolute_expr (ip, &imm_expr);
12621 if (imm_expr.X_add_number > max_el)
12622 as_bad (_("Bad element selector %ld"),
12623 (long) imm_expr.X_add_number);
12624 imm_expr.X_add_number &= max_el;
12625 ip->insn_opcode |= (imm_expr.X_add_number
12628 imm_expr.X_op = O_absent;
12630 as_warn (_("Expecting ']' found '%s'"), s);
12636 if ((ip->insn_mo->membership & INSN_5400)
12637 && (strcmp (insn->name, "sll.ob") == 0
12638 || strcmp (insn->name, "srl.ob") == 0))
12639 as_bad (_("Operand %d of `%s' must be scalar"),
12640 argnum, ip->insn_mo->name);
12642 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12643 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12646 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12649 /* Fall through. */
12653 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12657 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12667 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12671 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12677 my_getExpression (&imm_expr, s);
12678 if (imm_expr.X_op != O_big
12679 && imm_expr.X_op != O_constant)
12680 insn_error = _("absolute expression required");
12681 if (HAVE_32BIT_GPRS)
12682 normalize_constant_expr (&imm_expr);
12687 my_getSmallExpression (&offset_expr, offset_reloc, s);
12688 if (offset_expr.X_op == O_register)
12690 /* Assume that the offset has been elided and that what
12691 we saw was a base register. The match will fail later
12692 if that assumption turns out to be wrong. */
12693 offset_expr.X_op = O_constant;
12694 offset_expr.X_add_number = 0;
12698 normalize_address_expr (&offset_expr);
12712 unsigned char temp[8];
12714 unsigned int length;
12719 /* These only appear as the last operand in an
12720 instruction, and every instruction that accepts
12721 them in any variant accepts them in all variants.
12722 This means we don't have to worry about backing out
12723 any changes if the instruction does not match.
12725 The difference between them is the size of the
12726 floating point constant and where it goes. For 'F'
12727 and 'L' the constant is 64 bits; for 'f' and 'l' it
12728 is 32 bits. Where the constant is placed is based
12729 on how the MIPS assembler does things:
12732 f -- immediate value
12735 The .lit4 and .lit8 sections are only used if
12736 permitted by the -G argument.
12738 The code below needs to know whether the target register
12739 is 32 or 64 bits wide. It relies on the fact 'f' and
12740 'F' are used with GPR-based instructions and 'l' and
12741 'L' are used with FPR-based instructions. */
12743 f64 = *args == 'F' || *args == 'L';
12744 using_gprs = *args == 'F' || *args == 'f';
12746 save_in = input_line_pointer;
12747 input_line_pointer = s;
12748 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12750 s = input_line_pointer;
12751 input_line_pointer = save_in;
12752 if (err != NULL && *err != '\0')
12754 as_bad (_("Bad floating point constant: %s"), err);
12755 memset (temp, '\0', sizeof temp);
12756 length = f64 ? 8 : 4;
12759 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12763 && (g_switch_value < 4
12764 || (temp[0] == 0 && temp[1] == 0)
12765 || (temp[2] == 0 && temp[3] == 0))))
12767 imm_expr.X_op = O_constant;
12768 if (!target_big_endian)
12769 imm_expr.X_add_number = bfd_getl32 (temp);
12771 imm_expr.X_add_number = bfd_getb32 (temp);
12773 else if (length > 4
12774 && !mips_disable_float_construction
12775 /* Constants can only be constructed in GPRs and
12776 copied to FPRs if the GPRs are at least as wide
12777 as the FPRs. Force the constant into memory if
12778 we are using 64-bit FPRs but the GPRs are only
12781 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12782 && ((temp[0] == 0 && temp[1] == 0)
12783 || (temp[2] == 0 && temp[3] == 0))
12784 && ((temp[4] == 0 && temp[5] == 0)
12785 || (temp[6] == 0 && temp[7] == 0)))
12787 /* The value is simple enough to load with a couple of
12788 instructions. If using 32-bit registers, set
12789 imm_expr to the high order 32 bits and offset_expr to
12790 the low order 32 bits. Otherwise, set imm_expr to
12791 the entire 64 bit constant. */
12792 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12794 imm_expr.X_op = O_constant;
12795 offset_expr.X_op = O_constant;
12796 if (!target_big_endian)
12798 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12799 offset_expr.X_add_number = bfd_getl32 (temp);
12803 imm_expr.X_add_number = bfd_getb32 (temp);
12804 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12806 if (offset_expr.X_add_number == 0)
12807 offset_expr.X_op = O_absent;
12811 imm_expr.X_op = O_constant;
12812 if (!target_big_endian)
12813 imm_expr.X_add_number = bfd_getl64 (temp);
12815 imm_expr.X_add_number = bfd_getb64 (temp);
12820 const char *newname;
12823 /* Switch to the right section. */
12825 subseg = now_subseg;
12828 default: /* unused default case avoids warnings. */
12830 newname = RDATA_SECTION_NAME;
12831 if (g_switch_value >= 8)
12835 newname = RDATA_SECTION_NAME;
12838 gas_assert (g_switch_value >= 4);
12842 new_seg = subseg_new (newname, (subsegT) 0);
12843 bfd_set_section_flags (stdoutput, new_seg,
12848 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12849 if (strncmp (TARGET_OS, "elf", 3) != 0)
12850 record_alignment (new_seg, 4);
12852 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12853 if (seg == now_seg)
12854 as_bad (_("Can't use floating point insn in this section"));
12856 /* Set the argument to the current address in the
12858 offset_expr.X_op = O_symbol;
12859 offset_expr.X_add_symbol = symbol_temp_new_now ();
12860 offset_expr.X_add_number = 0;
12862 /* Put the floating point number into the section. */
12863 p = frag_more ((int) length);
12864 memcpy (p, temp, length);
12866 /* Switch back to the original section. */
12867 subseg_set (seg, subseg);
12872 case 'i': /* 16-bit unsigned immediate. */
12873 case 'j': /* 16-bit signed immediate. */
12874 *offset_reloc = BFD_RELOC_LO16;
12875 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0)
12878 offsetT minval, maxval;
12880 more = (insn + 1 < past
12881 && strcmp (insn->name, insn[1].name) == 0);
12883 /* For compatibility with older assemblers, we accept
12884 0x8000-0xffff as signed 16-bit numbers when only
12885 signed numbers are allowed. */
12887 minval = 0, maxval = 0xffff;
12889 minval = -0x8000, maxval = 0x7fff;
12891 minval = -0x8000, maxval = 0xffff;
12893 if (offset_expr.X_op != O_constant
12894 || offset_expr.X_add_number < minval
12895 || offset_expr.X_add_number > maxval)
12899 if (offset_expr.X_op == O_constant
12900 || offset_expr.X_op == O_big)
12901 as_bad (_("Expression out of range"));
12907 case 'o': /* 16-bit offset. */
12908 offset_reloc[0] = BFD_RELOC_LO16;
12909 offset_reloc[1] = BFD_RELOC_UNUSED;
12910 offset_reloc[2] = BFD_RELOC_UNUSED;
12912 /* Check whether there is only a single bracketed expression
12913 left. If so, it must be the base register and the
12914 constant must be zero. */
12915 if (*s == '(' && strchr (s + 1, '(') == 0)
12917 offset_expr.X_op = O_constant;
12918 offset_expr.X_add_number = 0;
12922 /* If this value won't fit into a 16 bit offset, then go
12923 find a macro that will generate the 32 bit offset
12925 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12926 && (offset_expr.X_op != O_constant
12927 || offset_expr.X_add_number >= 0x8000
12928 || offset_expr.X_add_number < -0x8000))
12934 case 'p': /* PC-relative offset. */
12935 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12936 my_getExpression (&offset_expr, s);
12940 case 'u': /* Upper 16 bits. */
12941 *offset_reloc = BFD_RELOC_LO16;
12942 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12943 && offset_expr.X_op == O_constant
12944 && (offset_expr.X_add_number < 0
12945 || offset_expr.X_add_number >= 0x10000))
12946 as_bad (_("lui expression (%lu) not in range 0..65535"),
12947 (unsigned long) offset_expr.X_add_number);
12951 case 'a': /* 26-bit address. */
12953 *offset_reloc = BFD_RELOC_MIPS_JMP;
12954 my_getExpression (&offset_expr, s);
12958 case 'N': /* 3-bit branch condition code. */
12959 case 'M': /* 3-bit compare condition code. */
12961 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12962 rtype |= RTYPE_FCC;
12963 if (!reg_lookup (&s, rtype, ®no))
12965 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12966 || strcmp (str + strlen (str) - 5, "any2f") == 0
12967 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12968 && (regno & 1) != 0)
12969 as_warn (_("Condition code register should be even for %s, "
12972 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12973 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12974 && (regno & 3) != 0)
12975 as_warn (_("Condition code register should be 0 or 4 for %s, "
12979 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12981 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12985 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12996 while (ISDIGIT (*s));
12999 c = 8; /* Invalid sel value. */
13002 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13003 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
13007 gas_assert (!mips_opts.micromips);
13008 /* Must be at least one digit. */
13009 my_getExpression (&imm_expr, s);
13010 check_absolute_expr (ip, &imm_expr);
13012 if ((unsigned long) imm_expr.X_add_number
13013 > (unsigned long) OP_MASK_VECBYTE)
13015 as_bad (_("bad byte vector index (%ld)"),
13016 (long) imm_expr.X_add_number);
13017 imm_expr.X_add_number = 0;
13020 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
13021 imm_expr.X_op = O_absent;
13026 gas_assert (!mips_opts.micromips);
13027 my_getExpression (&imm_expr, s);
13028 check_absolute_expr (ip, &imm_expr);
13030 if ((unsigned long) imm_expr.X_add_number
13031 > (unsigned long) OP_MASK_VECALIGN)
13033 as_bad (_("bad byte vector index (%ld)"),
13034 (long) imm_expr.X_add_number);
13035 imm_expr.X_add_number = 0;
13038 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
13039 imm_expr.X_op = O_absent;
13043 case 'm': /* Opcode extension character. */
13044 gas_assert (mips_opts.micromips);
13049 if (strncmp (s, "$pc", 3) == 0)
13076 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
13077 if (regno == AT && mips_opts.at)
13079 if (mips_opts.at == ATREG)
13080 as_warn (_("Used $at without \".set noat\""));
13082 as_warn (_("Used $%u with \".set at=$%u\""),
13083 regno, mips_opts.at);
13089 gas_assert (args[1] == ',');
13095 gas_assert (args[1] == ',');
13097 continue; /* Nothing to do. */
13103 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
13105 if (regno == lastregno)
13108 = _("Source and destination must be different");
13111 if (regno == 31 && lastregno == 0xffffffff)
13114 = _("A destination register must be supplied");
13125 gas_assert (args[1] == ',');
13132 gas_assert (args[1] == ',');
13135 continue; /* Nothing to do. */
13139 /* Make sure regno is the same as lastregno. */
13140 if (c == 't' && regno != lastregno)
13143 /* Make sure regno is the same as destregno. */
13144 if (c == 'x' && regno != destregno)
13147 /* We need to save regno, before regno maps to the
13148 microMIPS register encoding. */
13158 regno = ILLEGAL_REG;
13162 regno = mips32_to_micromips_reg_b_map[regno];
13166 regno = mips32_to_micromips_reg_c_map[regno];
13170 regno = mips32_to_micromips_reg_d_map[regno];
13174 regno = mips32_to_micromips_reg_e_map[regno];
13178 regno = mips32_to_micromips_reg_f_map[regno];
13182 regno = mips32_to_micromips_reg_g_map[regno];
13186 s += strspn (s, " \t");
13189 regno = ILLEGAL_REG;
13193 s += strspn (s, " \t");
13194 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no2);
13197 regno = ILLEGAL_REG;
13200 if (regno2 == AT && mips_opts.at)
13202 if (mips_opts.at == ATREG)
13203 as_warn (_("Used $at without \".set noat\""));
13205 as_warn (_("Used $%u with \".set at=$%u\""),
13206 regno2, mips_opts.at);
13208 regno = (mips_lookup_reg_pair
13210 micromips_to_32_reg_h_map1,
13211 micromips_to_32_reg_h_map2, 8));
13215 regno = mips32_to_micromips_reg_l_map[regno];
13219 regno = mips32_to_micromips_reg_m_map[regno];
13223 regno = mips32_to_micromips_reg_n_map[regno];
13227 regno = mips32_to_micromips_reg_q_map[regno];
13232 regno = ILLEGAL_REG;
13237 regno = ILLEGAL_REG;
13242 regno = ILLEGAL_REG;
13245 case 'j': /* Do nothing. */
13255 if (regno == ILLEGAL_REG)
13261 INSERT_OPERAND (1, MB, *ip, regno);
13265 INSERT_OPERAND (1, MC, *ip, regno);
13269 INSERT_OPERAND (1, MD, *ip, regno);
13273 INSERT_OPERAND (1, ME, *ip, regno);
13277 INSERT_OPERAND (1, MF, *ip, regno);
13281 INSERT_OPERAND (1, MG, *ip, regno);
13285 INSERT_OPERAND (1, MH, *ip, regno);
13289 INSERT_OPERAND (1, MJ, *ip, regno);
13293 INSERT_OPERAND (1, ML, *ip, regno);
13297 INSERT_OPERAND (1, MM, *ip, regno);
13301 INSERT_OPERAND (1, MN, *ip, regno);
13305 INSERT_OPERAND (1, MP, *ip, regno);
13309 INSERT_OPERAND (1, MQ, *ip, regno);
13312 case 'a': /* Do nothing. */
13313 case 's': /* Do nothing. */
13314 case 't': /* Do nothing. */
13315 case 'x': /* Do nothing. */
13316 case 'y': /* Do nothing. */
13317 case 'z': /* Do nothing. */
13327 bfd_reloc_code_real_type r[3];
13331 /* Check whether there is only a single bracketed
13332 expression left. If so, it must be the base register
13333 and the constant must be zero. */
13334 if (*s == '(' && strchr (s + 1, '(') == 0)
13336 INSERT_OPERAND (1, IMMA, *ip, 0);
13340 if (my_getSmallExpression (&ep, r, s) > 0
13341 || !expr_const_in_range (&ep, -64, 64, 2))
13344 imm = ep.X_add_number >> 2;
13345 INSERT_OPERAND (1, IMMA, *ip, imm);
13352 bfd_reloc_code_real_type r[3];
13356 if (my_getSmallExpression (&ep, r, s) > 0
13357 || ep.X_op != O_constant)
13360 for (imm = 0; imm < 8; imm++)
13361 if (micromips_imm_b_map[imm] == ep.X_add_number)
13366 INSERT_OPERAND (1, IMMB, *ip, imm);
13373 bfd_reloc_code_real_type r[3];
13377 if (my_getSmallExpression (&ep, r, s) > 0
13378 || ep.X_op != O_constant)
13381 for (imm = 0; imm < 16; imm++)
13382 if (micromips_imm_c_map[imm] == ep.X_add_number)
13387 INSERT_OPERAND (1, IMMC, *ip, imm);
13392 case 'D': /* pc relative offset */
13393 case 'E': /* pc relative offset */
13394 my_getExpression (&offset_expr, s);
13395 if (offset_expr.X_op == O_register)
13398 if (!forced_insn_length)
13399 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13401 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13403 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13409 bfd_reloc_code_real_type r[3];
13413 if (my_getSmallExpression (&ep, r, s) > 0
13414 || !expr_const_in_range (&ep, 0, 16, 0))
13417 imm = ep.X_add_number;
13418 INSERT_OPERAND (1, IMMF, *ip, imm);
13425 bfd_reloc_code_real_type r[3];
13429 /* Check whether there is only a single bracketed
13430 expression left. If so, it must be the base register
13431 and the constant must be zero. */
13432 if (*s == '(' && strchr (s + 1, '(') == 0)
13434 INSERT_OPERAND (1, IMMG, *ip, 0);
13438 if (my_getSmallExpression (&ep, r, s) > 0
13439 || !expr_const_in_range (&ep, -1, 15, 0))
13442 imm = ep.X_add_number & 15;
13443 INSERT_OPERAND (1, IMMG, *ip, imm);
13450 bfd_reloc_code_real_type r[3];
13454 /* Check whether there is only a single bracketed
13455 expression left. If so, it must be the base register
13456 and the constant must be zero. */
13457 if (*s == '(' && strchr (s + 1, '(') == 0)
13459 INSERT_OPERAND (1, IMMH, *ip, 0);
13463 if (my_getSmallExpression (&ep, r, s) > 0
13464 || !expr_const_in_range (&ep, 0, 16, 1))
13467 imm = ep.X_add_number >> 1;
13468 INSERT_OPERAND (1, IMMH, *ip, imm);
13475 bfd_reloc_code_real_type r[3];
13479 if (my_getSmallExpression (&ep, r, s) > 0
13480 || !expr_const_in_range (&ep, -1, 127, 0))
13483 imm = ep.X_add_number & 127;
13484 INSERT_OPERAND (1, IMMI, *ip, imm);
13491 bfd_reloc_code_real_type r[3];
13495 /* Check whether there is only a single bracketed
13496 expression left. If so, it must be the base register
13497 and the constant must be zero. */
13498 if (*s == '(' && strchr (s + 1, '(') == 0)
13500 INSERT_OPERAND (1, IMMJ, *ip, 0);
13504 if (my_getSmallExpression (&ep, r, s) > 0
13505 || !expr_const_in_range (&ep, 0, 16, 2))
13508 imm = ep.X_add_number >> 2;
13509 INSERT_OPERAND (1, IMMJ, *ip, imm);
13516 bfd_reloc_code_real_type r[3];
13520 /* Check whether there is only a single bracketed
13521 expression left. If so, it must be the base register
13522 and the constant must be zero. */
13523 if (*s == '(' && strchr (s + 1, '(') == 0)
13525 INSERT_OPERAND (1, IMML, *ip, 0);
13529 if (my_getSmallExpression (&ep, r, s) > 0
13530 || !expr_const_in_range (&ep, 0, 16, 0))
13533 imm = ep.X_add_number;
13534 INSERT_OPERAND (1, IMML, *ip, imm);
13541 bfd_reloc_code_real_type r[3];
13545 if (my_getSmallExpression (&ep, r, s) > 0
13546 || !expr_const_in_range (&ep, 1, 9, 0))
13549 imm = ep.X_add_number & 7;
13550 INSERT_OPERAND (1, IMMM, *ip, imm);
13555 case 'N': /* Register list for lwm and swm. */
13557 /* A comma-separated list of registers and/or
13558 dash-separated contiguous ranges including
13559 both ra and a set of one or more registers
13560 starting at s0 up to s3 which have to be
13567 and any permutations of these. */
13568 unsigned int reglist;
13571 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13574 if ((reglist & 0xfff1ffff) != 0x80010000)
13577 reglist = (reglist >> 17) & 7;
13579 if ((reglist & -reglist) != reglist)
13582 imm = ffs (reglist) - 1;
13583 INSERT_OPERAND (1, IMMN, *ip, imm);
13587 case 'O': /* sdbbp 4-bit code. */
13589 bfd_reloc_code_real_type r[3];
13593 if (my_getSmallExpression (&ep, r, s) > 0
13594 || !expr_const_in_range (&ep, 0, 16, 0))
13597 imm = ep.X_add_number;
13598 INSERT_OPERAND (1, IMMO, *ip, imm);
13605 bfd_reloc_code_real_type r[3];
13609 if (my_getSmallExpression (&ep, r, s) > 0
13610 || !expr_const_in_range (&ep, 0, 32, 2))
13613 imm = ep.X_add_number >> 2;
13614 INSERT_OPERAND (1, IMMP, *ip, imm);
13621 bfd_reloc_code_real_type r[3];
13625 if (my_getSmallExpression (&ep, r, s) > 0
13626 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13629 imm = ep.X_add_number >> 2;
13630 INSERT_OPERAND (1, IMMQ, *ip, imm);
13637 bfd_reloc_code_real_type r[3];
13641 /* Check whether there is only a single bracketed
13642 expression left. If so, it must be the base register
13643 and the constant must be zero. */
13644 if (*s == '(' && strchr (s + 1, '(') == 0)
13646 INSERT_OPERAND (1, IMMU, *ip, 0);
13650 if (my_getSmallExpression (&ep, r, s) > 0
13651 || !expr_const_in_range (&ep, 0, 32, 2))
13654 imm = ep.X_add_number >> 2;
13655 INSERT_OPERAND (1, IMMU, *ip, imm);
13662 bfd_reloc_code_real_type r[3];
13666 if (my_getSmallExpression (&ep, r, s) > 0
13667 || !expr_const_in_range (&ep, 0, 64, 2))
13670 imm = ep.X_add_number >> 2;
13671 INSERT_OPERAND (1, IMMW, *ip, imm);
13678 bfd_reloc_code_real_type r[3];
13682 if (my_getSmallExpression (&ep, r, s) > 0
13683 || !expr_const_in_range (&ep, -8, 8, 0))
13686 imm = ep.X_add_number;
13687 INSERT_OPERAND (1, IMMX, *ip, imm);
13694 bfd_reloc_code_real_type r[3];
13698 if (my_getSmallExpression (&ep, r, s) > 0
13699 || expr_const_in_range (&ep, -2, 2, 2)
13700 || !expr_const_in_range (&ep, -258, 258, 2))
13703 imm = ep.X_add_number >> 2;
13704 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13705 INSERT_OPERAND (1, IMMY, *ip, imm);
13712 bfd_reloc_code_real_type r[3];
13715 if (my_getSmallExpression (&ep, r, s) > 0
13716 || !expr_const_in_range (&ep, 0, 1, 0))
13723 as_bad (_("Internal error: bad microMIPS opcode "
13724 "(unknown extension operand type `m%c'): %s %s"),
13725 *args, insn->name, insn->args);
13726 /* Further processing is fruitless. */
13731 case 'n': /* Register list for 32-bit lwm and swm. */
13732 gas_assert (mips_opts.micromips);
13734 /* A comma-separated list of registers and/or
13735 dash-separated contiguous ranges including
13736 at least one of ra and a set of one or more
13737 registers starting at s0 up to s7 and then
13738 s8 which have to be consecutive, e.g.:
13746 and any permutations of these. */
13747 unsigned int reglist;
13751 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13754 if ((reglist & 0x3f00ffff) != 0)
13757 ra = (reglist >> 27) & 0x10;
13758 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13760 if ((reglist & -reglist) != reglist)
13763 imm = (ffs (reglist) - 1) | ra;
13764 INSERT_OPERAND (1, RT, *ip, imm);
13765 imm_expr.X_op = O_absent;
13769 case '|': /* 4-bit trap code. */
13770 gas_assert (mips_opts.micromips);
13771 my_getExpression (&imm_expr, s);
13772 check_absolute_expr (ip, &imm_expr);
13773 if ((unsigned long) imm_expr.X_add_number
13774 > MICROMIPSOP_MASK_TRAP)
13775 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13776 (unsigned long) imm_expr.X_add_number,
13777 ip->insn_mo->name);
13778 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13779 imm_expr.X_op = O_absent;
13784 as_bad (_("Bad char = '%c'\n"), *args);
13789 /* Args don't match. */
13791 insn_error = _("Illegal operands");
13792 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13797 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13799 gas_assert (firstinsn);
13800 need_delay_slot_ok = FALSE;
13809 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13811 /* As for mips_ip, but used when assembling MIPS16 code.
13812 Also set forced_insn_length to the resulting instruction size in
13813 bytes if the user explicitly requested a small or extended instruction. */
13816 mips16_ip (char *str, struct mips_cl_insn *ip)
13820 struct mips_opcode *insn;
13822 unsigned int regno;
13823 unsigned int lastregno = 0;
13829 forced_insn_length = 0;
13831 for (s = str; ISLOWER (*s); ++s)
13843 if (s[1] == 't' && s[2] == ' ')
13846 forced_insn_length = 2;
13850 else if (s[1] == 'e' && s[2] == ' ')
13853 forced_insn_length = 4;
13857 /* Fall through. */
13859 insn_error = _("unknown opcode");
13863 if (mips_opts.noautoextend && !forced_insn_length)
13864 forced_insn_length = 2;
13866 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13868 insn_error = _("unrecognized opcode");
13878 gas_assert (strcmp (insn->name, str) == 0);
13880 ok = is_opcode_valid_16 (insn);
13883 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13884 && strcmp (insn->name, insn[1].name) == 0)
13893 static char buf[100];
13895 _("Opcode not supported on this processor: %s (%s)"),
13896 mips_cpu_info_from_arch (mips_opts.arch)->name,
13897 mips_cpu_info_from_isa (mips_opts.isa)->name);
13904 create_insn (ip, insn);
13905 imm_expr.X_op = O_absent;
13906 imm2_expr.X_op = O_absent;
13907 offset_expr.X_op = O_absent;
13908 offset_reloc[0] = BFD_RELOC_UNUSED;
13909 offset_reloc[1] = BFD_RELOC_UNUSED;
13910 offset_reloc[2] = BFD_RELOC_UNUSED;
13912 for (args = insn->args; 1; ++args)
13919 /* In this switch statement we call break if we did not find
13920 a match, continue if we did find a match, or return if we
13931 /* Stuff the immediate value in now, if we can. */
13932 if (insn->pinfo == INSN_MACRO)
13934 gas_assert (relax_char == 0);
13935 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
13937 else if (relax_char
13938 && offset_expr.X_op == O_constant
13939 && calculate_reloc (*offset_reloc,
13940 offset_expr.X_add_number,
13943 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
13944 forced_insn_length, &ip->insn_opcode);
13945 offset_expr.X_op = O_absent;
13946 *offset_reloc = BFD_RELOC_UNUSED;
13948 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
13950 if (forced_insn_length == 2)
13951 as_bad (_("invalid unextended operand value"));
13952 forced_insn_length = 4;
13953 ip->insn_opcode |= MIPS16_EXTEND;
13955 else if (relax_char)
13956 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
13969 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13972 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13988 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13990 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13994 /* Fall through. */
14005 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
14007 if (c == 'v' || c == 'w')
14010 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14012 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14023 if (c == 'v' || c == 'w')
14025 regno = mips16_to_32_reg_map[lastregno];
14039 regno = mips32_to_16_reg_map[regno];
14044 regno = ILLEGAL_REG;
14049 regno = ILLEGAL_REG;
14054 regno = ILLEGAL_REG;
14059 if (regno == AT && mips_opts.at)
14061 if (mips_opts.at == ATREG)
14062 as_warn (_("used $at without \".set noat\""));
14064 as_warn (_("used $%u with \".set at=$%u\""),
14065 regno, mips_opts.at);
14073 if (regno == ILLEGAL_REG)
14080 MIPS16_INSERT_OPERAND (RX, *ip, regno);
14084 MIPS16_INSERT_OPERAND (RY, *ip, regno);
14087 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
14090 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
14096 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
14099 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
14100 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
14110 if (strncmp (s, "$pc", 3) == 0)
14127 i = my_getSmallExpression (&offset_expr, offset_reloc, s);
14134 *offset_reloc = BFD_RELOC_UNUSED;
14135 /* Fall through. */
14142 my_getExpression (&offset_expr, s);
14143 if (offset_expr.X_op == O_register)
14145 /* What we thought was an expression turned out to
14148 if (s[0] == '(' && args[1] == '(')
14150 /* It looks like the expression was omitted
14151 before a register indirection, which means
14152 that the expression is implicitly zero. We
14153 still set up offset_expr, so that we handle
14154 explicit extensions correctly. */
14155 offset_expr.X_op = O_constant;
14156 offset_expr.X_add_number = 0;
14164 /* We need to relax this instruction. */
14174 /* We use offset_reloc rather than imm_reloc for the PC
14175 relative operands. This lets macros with both
14176 immediate and address operands work correctly. */
14177 my_getExpression (&offset_expr, s);
14179 if (offset_expr.X_op == O_register)
14182 /* We need to relax this instruction. */
14187 case '6': /* break code */
14188 my_getExpression (&imm_expr, s);
14189 check_absolute_expr (ip, &imm_expr);
14190 if ((unsigned long) imm_expr.X_add_number > 63)
14191 as_warn (_("Invalid value for `%s' (%lu)"),
14193 (unsigned long) imm_expr.X_add_number);
14194 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
14195 imm_expr.X_op = O_absent;
14200 my_getExpression (&imm_expr, s);
14201 if (imm_expr.X_op != O_big
14202 && imm_expr.X_op != O_constant)
14203 insn_error = _("absolute expression required");
14204 if (HAVE_32BIT_GPRS)
14205 normalize_constant_expr (&imm_expr);
14209 case 'a': /* 26 bit address */
14211 my_getExpression (&offset_expr, s);
14213 *offset_reloc = BFD_RELOC_MIPS16_JMP;
14214 ip->insn_opcode <<= 16;
14217 case 'l': /* register list for entry macro */
14218 case 'L': /* register list for exit macro */
14228 unsigned int freg, reg1, reg2;
14230 while (*s == ' ' || *s == ',')
14232 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14234 else if (reg_lookup (&s, RTYPE_FPU, ®1))
14238 as_bad (_("can't parse register list"));
14248 if (!reg_lookup (&s, freg ? RTYPE_FPU
14249 : (RTYPE_GP | RTYPE_NUM), ®2))
14251 as_bad (_("invalid register list"));
14255 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
14257 mask &= ~ (7 << 3);
14260 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
14262 mask &= ~ (7 << 3);
14265 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
14266 mask |= (reg2 - 3) << 3;
14267 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
14268 mask |= (reg2 - 15) << 1;
14269 else if (reg1 == RA && reg2 == RA)
14273 as_bad (_("invalid register list"));
14277 /* The mask is filled in in the opcode table for the
14278 benefit of the disassembler. We remove it before
14279 applying the actual mask. */
14280 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
14281 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
14285 case 'm': /* Register list for save insn. */
14286 case 'M': /* Register list for restore insn. */
14288 int opcode = ip->insn_opcode;
14289 int framesz = 0, seen_framesz = 0;
14290 int nargs = 0, statics = 0, sregs = 0;
14294 unsigned int reg1, reg2;
14296 SKIP_SPACE_TABS (s);
14299 SKIP_SPACE_TABS (s);
14301 my_getExpression (&imm_expr, s);
14302 if (imm_expr.X_op == O_constant)
14304 /* Handle the frame size. */
14307 as_bad (_("more than one frame size in list"));
14311 framesz = imm_expr.X_add_number;
14312 imm_expr.X_op = O_absent;
14317 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14319 as_bad (_("can't parse register list"));
14331 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
14334 as_bad (_("can't parse register list"));
14339 while (reg1 <= reg2)
14341 if (reg1 >= 4 && reg1 <= 7)
14345 nargs |= 1 << (reg1 - 4);
14347 /* statics $a0-$a3 */
14348 statics |= 1 << (reg1 - 4);
14350 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14353 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14355 else if (reg1 == 31)
14357 /* Add $ra to insn. */
14362 as_bad (_("unexpected register in list"));
14370 /* Encode args/statics combination. */
14371 if (nargs & statics)
14372 as_bad (_("arg/static registers overlap"));
14373 else if (nargs == 0xf)
14374 /* All $a0-$a3 are args. */
14375 opcode |= MIPS16_ALL_ARGS << 16;
14376 else if (statics == 0xf)
14377 /* All $a0-$a3 are statics. */
14378 opcode |= MIPS16_ALL_STATICS << 16;
14381 int narg = 0, nstat = 0;
14383 /* Count arg registers. */
14384 while (nargs & 0x1)
14390 as_bad (_("invalid arg register list"));
14392 /* Count static registers. */
14393 while (statics & 0x8)
14395 statics = (statics << 1) & 0xf;
14399 as_bad (_("invalid static register list"));
14401 /* Encode args/statics. */
14402 opcode |= ((narg << 2) | nstat) << 16;
14405 /* Encode $s0/$s1. */
14406 if (sregs & (1 << 0)) /* $s0 */
14408 if (sregs & (1 << 1)) /* $s1 */
14414 /* Count regs $s2-$s8. */
14422 as_bad (_("invalid static register list"));
14423 /* Encode $s2-$s8. */
14424 opcode |= nsreg << 24;
14427 /* Encode frame size. */
14429 as_bad (_("missing frame size"));
14430 else if ((framesz & 7) != 0 || framesz < 0
14431 || framesz > 0xff * 8)
14432 as_bad (_("invalid frame size"));
14433 else if (framesz != 128 || (opcode >> 16) != 0)
14436 opcode |= (((framesz & 0xf0) << 16)
14437 | (framesz & 0x0f));
14440 /* Finally build the instruction. */
14441 if ((opcode >> 16) != 0 || framesz == 0)
14442 opcode |= MIPS16_EXTEND;
14443 ip->insn_opcode = opcode;
14447 case 'e': /* extend code */
14448 my_getExpression (&imm_expr, s);
14449 check_absolute_expr (ip, &imm_expr);
14450 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14452 as_warn (_("Invalid value for `%s' (%lu)"),
14454 (unsigned long) imm_expr.X_add_number);
14455 imm_expr.X_add_number &= 0x7ff;
14457 ip->insn_opcode |= imm_expr.X_add_number;
14458 imm_expr.X_op = O_absent;
14468 /* Args don't match. */
14469 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14470 strcmp (insn->name, insn[1].name) == 0)
14477 insn_error = _("illegal operands");
14483 /* This structure holds information we know about a mips16 immediate
14486 struct mips16_immed_operand
14488 /* The type code used in the argument string in the opcode table. */
14490 /* The number of bits in the short form of the opcode. */
14492 /* The number of bits in the extended form of the opcode. */
14494 /* The amount by which the short form is shifted when it is used;
14495 for example, the sw instruction has a shift count of 2. */
14497 /* The amount by which the short form is shifted when it is stored
14498 into the instruction code. */
14500 /* Non-zero if the short form is unsigned. */
14502 /* Non-zero if the extended form is unsigned. */
14504 /* Non-zero if the value is PC relative. */
14508 /* The mips16 immediate operand types. */
14510 static const struct mips16_immed_operand mips16_immed_operands[] =
14512 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14513 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14514 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14515 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14516 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14517 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14518 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14519 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14520 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14521 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14522 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14523 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14524 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14525 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14526 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14527 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14528 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14529 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14530 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14531 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14532 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14535 #define MIPS16_NUM_IMMED \
14536 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14538 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14539 NBITS is the number of significant bits in VAL. */
14541 static unsigned long
14542 mips16_immed_extend (offsetT val, unsigned int nbits)
14547 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14550 else if (nbits == 15)
14552 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14557 extval = ((val & 0x1f) << 6) | (val & 0x20);
14560 return (extval << 16) | val;
14563 /* Install immediate value VAL into MIPS16 instruction *INSN,
14564 extending it if necessary. The instruction in *INSN may
14565 already be extended.
14567 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14568 if none. In the former case, VAL is a 16-bit number with no
14569 defined signedness.
14571 TYPE is the type of the immediate field. USER_INSN_LENGTH
14572 is the length that the user requested, or 0 if none. */
14575 mips16_immed (char *file, unsigned int line, int type,
14576 bfd_reloc_code_real_type reloc, offsetT val,
14577 unsigned int user_insn_length, unsigned long *insn)
14579 const struct mips16_immed_operand *op;
14580 int mintiny, maxtiny;
14582 op = mips16_immed_operands;
14583 while (op->type != type)
14586 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14591 if (type == '<' || type == '>' || type == '[' || type == ']')
14594 maxtiny = 1 << op->nbits;
14599 maxtiny = (1 << op->nbits) - 1;
14601 if (reloc != BFD_RELOC_UNUSED)
14606 mintiny = - (1 << (op->nbits - 1));
14607 maxtiny = (1 << (op->nbits - 1)) - 1;
14608 if (reloc != BFD_RELOC_UNUSED)
14609 val = SEXT_16BIT (val);
14612 /* Branch offsets have an implicit 0 in the lowest bit. */
14613 if (type == 'p' || type == 'q')
14616 if ((val & ((1 << op->shift) - 1)) != 0
14617 || val < (mintiny << op->shift)
14618 || val > (maxtiny << op->shift))
14620 /* We need an extended instruction. */
14621 if (user_insn_length == 2)
14622 as_bad_where (file, line, _("invalid unextended operand value"));
14624 *insn |= MIPS16_EXTEND;
14626 else if (user_insn_length == 4)
14628 /* The operand doesn't force an unextended instruction to be extended.
14629 Warn if the user wanted an extended instruction anyway. */
14630 *insn |= MIPS16_EXTEND;
14631 as_warn_where (file, line,
14632 _("extended operand requested but not required"));
14635 if (mips16_opcode_length (*insn) == 2)
14639 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14640 insnval <<= op->op_shift;
14645 long minext, maxext;
14647 if (reloc == BFD_RELOC_UNUSED)
14652 maxext = (1 << op->extbits) - 1;
14656 minext = - (1 << (op->extbits - 1));
14657 maxext = (1 << (op->extbits - 1)) - 1;
14659 if (val < minext || val > maxext)
14660 as_bad_where (file, line,
14661 _("operand value out of range for instruction"));
14664 *insn |= mips16_immed_extend (val, op->extbits);
14668 struct percent_op_match
14671 bfd_reloc_code_real_type reloc;
14674 static const struct percent_op_match mips_percent_op[] =
14676 {"%lo", BFD_RELOC_LO16},
14677 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14678 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14679 {"%call16", BFD_RELOC_MIPS_CALL16},
14680 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14681 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14682 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14683 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14684 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14685 {"%got", BFD_RELOC_MIPS_GOT16},
14686 {"%gp_rel", BFD_RELOC_GPREL16},
14687 {"%half", BFD_RELOC_16},
14688 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14689 {"%higher", BFD_RELOC_MIPS_HIGHER},
14690 {"%neg", BFD_RELOC_MIPS_SUB},
14691 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14692 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14693 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14694 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14695 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14696 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14697 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14698 {"%hi", BFD_RELOC_HI16_S}
14701 static const struct percent_op_match mips16_percent_op[] =
14703 {"%lo", BFD_RELOC_MIPS16_LO16},
14704 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14705 {"%got", BFD_RELOC_MIPS16_GOT16},
14706 {"%call16", BFD_RELOC_MIPS16_CALL16},
14707 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14708 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14709 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14710 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14711 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14712 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14713 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14714 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14718 /* Return true if *STR points to a relocation operator. When returning true,
14719 move *STR over the operator and store its relocation code in *RELOC.
14720 Leave both *STR and *RELOC alone when returning false. */
14723 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14725 const struct percent_op_match *percent_op;
14728 if (mips_opts.mips16)
14730 percent_op = mips16_percent_op;
14731 limit = ARRAY_SIZE (mips16_percent_op);
14735 percent_op = mips_percent_op;
14736 limit = ARRAY_SIZE (mips_percent_op);
14739 for (i = 0; i < limit; i++)
14740 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14742 int len = strlen (percent_op[i].str);
14744 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14747 *str += strlen (percent_op[i].str);
14748 *reloc = percent_op[i].reloc;
14750 /* Check whether the output BFD supports this relocation.
14751 If not, issue an error and fall back on something safe. */
14752 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14754 as_bad (_("relocation %s isn't supported by the current ABI"),
14755 percent_op[i].str);
14756 *reloc = BFD_RELOC_UNUSED;
14764 /* Parse string STR as a 16-bit relocatable operand. Store the
14765 expression in *EP and the relocations in the array starting
14766 at RELOC. Return the number of relocation operators used.
14768 On exit, EXPR_END points to the first character after the expression. */
14771 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14774 bfd_reloc_code_real_type reversed_reloc[3];
14775 size_t reloc_index, i;
14776 int crux_depth, str_depth;
14779 /* Search for the start of the main expression, recoding relocations
14780 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14781 of the main expression and with CRUX_DEPTH containing the number
14782 of open brackets at that point. */
14789 crux_depth = str_depth;
14791 /* Skip over whitespace and brackets, keeping count of the number
14793 while (*str == ' ' || *str == '\t' || *str == '(')
14798 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14799 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14801 my_getExpression (ep, crux);
14804 /* Match every open bracket. */
14805 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14809 if (crux_depth > 0)
14810 as_bad (_("unclosed '('"));
14814 if (reloc_index != 0)
14816 prev_reloc_op_frag = frag_now;
14817 for (i = 0; i < reloc_index; i++)
14818 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14821 return reloc_index;
14825 my_getExpression (expressionS *ep, char *str)
14829 save_in = input_line_pointer;
14830 input_line_pointer = str;
14832 expr_end = input_line_pointer;
14833 input_line_pointer = save_in;
14837 md_atof (int type, char *litP, int *sizeP)
14839 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14843 md_number_to_chars (char *buf, valueT val, int n)
14845 if (target_big_endian)
14846 number_to_chars_bigendian (buf, val, n);
14848 number_to_chars_littleendian (buf, val, n);
14851 static int support_64bit_objects(void)
14853 const char **list, **l;
14856 list = bfd_target_list ();
14857 for (l = list; *l != NULL; l++)
14858 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14859 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14861 yes = (*l != NULL);
14866 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14867 NEW_VALUE. Warn if another value was already specified. Note:
14868 we have to defer parsing the -march and -mtune arguments in order
14869 to handle 'from-abi' correctly, since the ABI might be specified
14870 in a later argument. */
14873 mips_set_option_string (const char **string_ptr, const char *new_value)
14875 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14876 as_warn (_("A different %s was already specified, is now %s"),
14877 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14880 *string_ptr = new_value;
14884 md_parse_option (int c, char *arg)
14888 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14889 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14891 file_ase_explicit |= mips_set_ase (&mips_ases[i],
14892 c == mips_ases[i].option_on);
14898 case OPTION_CONSTRUCT_FLOATS:
14899 mips_disable_float_construction = 0;
14902 case OPTION_NO_CONSTRUCT_FLOATS:
14903 mips_disable_float_construction = 1;
14915 target_big_endian = 1;
14919 target_big_endian = 0;
14925 else if (arg[0] == '0')
14927 else if (arg[0] == '1')
14937 mips_debug = atoi (arg);
14941 file_mips_isa = ISA_MIPS1;
14945 file_mips_isa = ISA_MIPS2;
14949 file_mips_isa = ISA_MIPS3;
14953 file_mips_isa = ISA_MIPS4;
14957 file_mips_isa = ISA_MIPS5;
14960 case OPTION_MIPS32:
14961 file_mips_isa = ISA_MIPS32;
14964 case OPTION_MIPS32R2:
14965 file_mips_isa = ISA_MIPS32R2;
14968 case OPTION_MIPS64R2:
14969 file_mips_isa = ISA_MIPS64R2;
14972 case OPTION_MIPS64:
14973 file_mips_isa = ISA_MIPS64;
14977 mips_set_option_string (&mips_tune_string, arg);
14981 mips_set_option_string (&mips_arch_string, arg);
14985 mips_set_option_string (&mips_arch_string, "4650");
14986 mips_set_option_string (&mips_tune_string, "4650");
14989 case OPTION_NO_M4650:
14993 mips_set_option_string (&mips_arch_string, "4010");
14994 mips_set_option_string (&mips_tune_string, "4010");
14997 case OPTION_NO_M4010:
15001 mips_set_option_string (&mips_arch_string, "4100");
15002 mips_set_option_string (&mips_tune_string, "4100");
15005 case OPTION_NO_M4100:
15009 mips_set_option_string (&mips_arch_string, "3900");
15010 mips_set_option_string (&mips_tune_string, "3900");
15013 case OPTION_NO_M3900:
15016 case OPTION_MICROMIPS:
15017 if (mips_opts.mips16 == 1)
15019 as_bad (_("-mmicromips cannot be used with -mips16"));
15022 mips_opts.micromips = 1;
15023 mips_no_prev_insn ();
15026 case OPTION_NO_MICROMIPS:
15027 mips_opts.micromips = 0;
15028 mips_no_prev_insn ();
15031 case OPTION_MIPS16:
15032 if (mips_opts.micromips == 1)
15034 as_bad (_("-mips16 cannot be used with -micromips"));
15037 mips_opts.mips16 = 1;
15038 mips_no_prev_insn ();
15041 case OPTION_NO_MIPS16:
15042 mips_opts.mips16 = 0;
15043 mips_no_prev_insn ();
15046 case OPTION_FIX_24K:
15050 case OPTION_NO_FIX_24K:
15054 case OPTION_FIX_LOONGSON2F_JUMP:
15055 mips_fix_loongson2f_jump = TRUE;
15058 case OPTION_NO_FIX_LOONGSON2F_JUMP:
15059 mips_fix_loongson2f_jump = FALSE;
15062 case OPTION_FIX_LOONGSON2F_NOP:
15063 mips_fix_loongson2f_nop = TRUE;
15066 case OPTION_NO_FIX_LOONGSON2F_NOP:
15067 mips_fix_loongson2f_nop = FALSE;
15070 case OPTION_FIX_VR4120:
15071 mips_fix_vr4120 = 1;
15074 case OPTION_NO_FIX_VR4120:
15075 mips_fix_vr4120 = 0;
15078 case OPTION_FIX_VR4130:
15079 mips_fix_vr4130 = 1;
15082 case OPTION_NO_FIX_VR4130:
15083 mips_fix_vr4130 = 0;
15086 case OPTION_FIX_CN63XXP1:
15087 mips_fix_cn63xxp1 = TRUE;
15090 case OPTION_NO_FIX_CN63XXP1:
15091 mips_fix_cn63xxp1 = FALSE;
15094 case OPTION_RELAX_BRANCH:
15095 mips_relax_branch = 1;
15098 case OPTION_NO_RELAX_BRANCH:
15099 mips_relax_branch = 0;
15102 case OPTION_INSN32:
15103 mips_opts.insn32 = TRUE;
15106 case OPTION_NO_INSN32:
15107 mips_opts.insn32 = FALSE;
15110 case OPTION_MSHARED:
15111 mips_in_shared = TRUE;
15114 case OPTION_MNO_SHARED:
15115 mips_in_shared = FALSE;
15118 case OPTION_MSYM32:
15119 mips_opts.sym32 = TRUE;
15122 case OPTION_MNO_SYM32:
15123 mips_opts.sym32 = FALSE;
15126 /* When generating ELF code, we permit -KPIC and -call_shared to
15127 select SVR4_PIC, and -non_shared to select no PIC. This is
15128 intended to be compatible with Irix 5. */
15129 case OPTION_CALL_SHARED:
15130 mips_pic = SVR4_PIC;
15131 mips_abicalls = TRUE;
15134 case OPTION_CALL_NONPIC:
15136 mips_abicalls = TRUE;
15139 case OPTION_NON_SHARED:
15141 mips_abicalls = FALSE;
15144 /* The -xgot option tells the assembler to use 32 bit offsets
15145 when accessing the got in SVR4_PIC mode. It is for Irix
15152 g_switch_value = atoi (arg);
15156 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15159 mips_abi = O32_ABI;
15163 mips_abi = N32_ABI;
15167 mips_abi = N64_ABI;
15168 if (!support_64bit_objects())
15169 as_fatal (_("No compiled in support for 64 bit object file format"));
15173 file_mips_gp32 = 1;
15177 file_mips_gp32 = 0;
15181 file_mips_fp32 = 1;
15185 file_mips_fp32 = 0;
15188 case OPTION_SINGLE_FLOAT:
15189 file_mips_single_float = 1;
15192 case OPTION_DOUBLE_FLOAT:
15193 file_mips_single_float = 0;
15196 case OPTION_SOFT_FLOAT:
15197 file_mips_soft_float = 1;
15200 case OPTION_HARD_FLOAT:
15201 file_mips_soft_float = 0;
15205 if (strcmp (arg, "32") == 0)
15206 mips_abi = O32_ABI;
15207 else if (strcmp (arg, "o64") == 0)
15208 mips_abi = O64_ABI;
15209 else if (strcmp (arg, "n32") == 0)
15210 mips_abi = N32_ABI;
15211 else if (strcmp (arg, "64") == 0)
15213 mips_abi = N64_ABI;
15214 if (! support_64bit_objects())
15215 as_fatal (_("No compiled in support for 64 bit object file "
15218 else if (strcmp (arg, "eabi") == 0)
15219 mips_abi = EABI_ABI;
15222 as_fatal (_("invalid abi -mabi=%s"), arg);
15227 case OPTION_M7000_HILO_FIX:
15228 mips_7000_hilo_fix = TRUE;
15231 case OPTION_MNO_7000_HILO_FIX:
15232 mips_7000_hilo_fix = FALSE;
15235 case OPTION_MDEBUG:
15236 mips_flag_mdebug = TRUE;
15239 case OPTION_NO_MDEBUG:
15240 mips_flag_mdebug = FALSE;
15244 mips_flag_pdr = TRUE;
15247 case OPTION_NO_PDR:
15248 mips_flag_pdr = FALSE;
15251 case OPTION_MVXWORKS_PIC:
15252 mips_pic = VXWORKS_PIC;
15256 if (strcmp (arg, "2008") == 0)
15257 mips_flag_nan2008 = TRUE;
15258 else if (strcmp (arg, "legacy") == 0)
15259 mips_flag_nan2008 = FALSE;
15262 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
15271 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15276 /* Set up globals to generate code for the ISA or processor
15277 described by INFO. */
15280 mips_set_architecture (const struct mips_cpu_info *info)
15284 file_mips_arch = info->cpu;
15285 mips_opts.arch = info->cpu;
15286 mips_opts.isa = info->isa;
15291 /* Likewise for tuning. */
15294 mips_set_tune (const struct mips_cpu_info *info)
15297 mips_tune = info->cpu;
15302 mips_after_parse_args (void)
15304 const struct mips_cpu_info *arch_info = 0;
15305 const struct mips_cpu_info *tune_info = 0;
15307 /* GP relative stuff not working for PE */
15308 if (strncmp (TARGET_OS, "pe", 2) == 0)
15310 if (g_switch_seen && g_switch_value != 0)
15311 as_bad (_("-G not supported in this configuration."));
15312 g_switch_value = 0;
15315 if (mips_abi == NO_ABI)
15316 mips_abi = MIPS_DEFAULT_ABI;
15318 /* The following code determines the architecture and register size.
15319 Similar code was added to GCC 3.3 (see override_options() in
15320 config/mips/mips.c). The GAS and GCC code should be kept in sync
15321 as much as possible. */
15323 if (mips_arch_string != 0)
15324 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15326 if (file_mips_isa != ISA_UNKNOWN)
15328 /* Handle -mipsN. At this point, file_mips_isa contains the
15329 ISA level specified by -mipsN, while arch_info->isa contains
15330 the -march selection (if any). */
15331 if (arch_info != 0)
15333 /* -march takes precedence over -mipsN, since it is more descriptive.
15334 There's no harm in specifying both as long as the ISA levels
15336 if (file_mips_isa != arch_info->isa)
15337 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15338 mips_cpu_info_from_isa (file_mips_isa)->name,
15339 mips_cpu_info_from_isa (arch_info->isa)->name);
15342 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15345 if (arch_info == 0)
15347 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15348 gas_assert (arch_info);
15351 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15352 as_bad (_("-march=%s is not compatible with the selected ABI"),
15355 mips_set_architecture (arch_info);
15357 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15358 if (mips_tune_string != 0)
15359 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15361 if (tune_info == 0)
15362 mips_set_tune (arch_info);
15364 mips_set_tune (tune_info);
15366 if (file_mips_gp32 >= 0)
15368 /* The user specified the size of the integer registers. Make sure
15369 it agrees with the ABI and ISA. */
15370 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15371 as_bad (_("-mgp64 used with a 32-bit processor"));
15372 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15373 as_bad (_("-mgp32 used with a 64-bit ABI"));
15374 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15375 as_bad (_("-mgp64 used with a 32-bit ABI"));
15379 /* Infer the integer register size from the ABI and processor.
15380 Restrict ourselves to 32-bit registers if that's all the
15381 processor has, or if the ABI cannot handle 64-bit registers. */
15382 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15383 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15386 switch (file_mips_fp32)
15390 /* No user specified float register size.
15391 ??? GAS treats single-float processors as though they had 64-bit
15392 float registers (although it complains when double-precision
15393 instructions are used). As things stand, saying they have 32-bit
15394 registers would lead to spurious "register must be even" messages.
15395 So here we assume float registers are never smaller than the
15397 if (file_mips_gp32 == 0)
15398 /* 64-bit integer registers implies 64-bit float registers. */
15399 file_mips_fp32 = 0;
15400 else if ((mips_opts.ase & FP64_ASES)
15401 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15402 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15403 file_mips_fp32 = 0;
15405 /* 32-bit float registers. */
15406 file_mips_fp32 = 1;
15409 /* The user specified the size of the float registers. Check if it
15410 agrees with the ABI and ISA. */
15412 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15413 as_bad (_("-mfp64 used with a 32-bit fpu"));
15414 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15415 && !ISA_HAS_MXHC1 (mips_opts.isa))
15416 as_warn (_("-mfp64 used with a 32-bit ABI"));
15419 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15420 as_warn (_("-mfp32 used with a 64-bit ABI"));
15424 /* End of GCC-shared inference code. */
15426 /* This flag is set when we have a 64-bit capable CPU but use only
15427 32-bit wide registers. Note that EABI does not use it. */
15428 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15429 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15430 || mips_abi == O32_ABI))
15431 mips_32bitmode = 1;
15433 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15434 as_bad (_("trap exception not supported at ISA 1"));
15436 /* If the selected architecture includes support for ASEs, enable
15437 generation of code for them. */
15438 if (mips_opts.mips16 == -1)
15439 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15440 if (mips_opts.micromips == -1)
15441 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15443 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15444 ASEs from being selected implicitly. */
15445 if (file_mips_fp32 == 1)
15446 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
15448 /* If the user didn't explicitly select or deselect a particular ASE,
15449 use the default setting for the CPU. */
15450 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
15452 file_mips_isa = mips_opts.isa;
15453 file_ase = mips_opts.ase;
15454 mips_opts.gp32 = file_mips_gp32;
15455 mips_opts.fp32 = file_mips_fp32;
15456 mips_opts.soft_float = file_mips_soft_float;
15457 mips_opts.single_float = file_mips_single_float;
15459 mips_check_isa_supports_ases ();
15461 if (mips_flag_mdebug < 0)
15462 mips_flag_mdebug = 0;
15466 mips_init_after_args (void)
15468 /* initialize opcodes */
15469 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15470 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15474 md_pcrel_from (fixS *fixP)
15476 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15477 switch (fixP->fx_r_type)
15479 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15480 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15481 /* Return the address of the delay slot. */
15484 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15485 case BFD_RELOC_MICROMIPS_JMP:
15486 case BFD_RELOC_16_PCREL_S2:
15487 case BFD_RELOC_MIPS_JMP:
15488 /* Return the address of the delay slot. */
15491 case BFD_RELOC_32_PCREL:
15495 /* We have no relocation type for PC relative MIPS16 instructions. */
15496 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15497 as_bad_where (fixP->fx_file, fixP->fx_line,
15498 _("PC relative MIPS16 instruction references a different section"));
15503 /* This is called before the symbol table is processed. In order to
15504 work with gcc when using mips-tfile, we must keep all local labels.
15505 However, in other cases, we want to discard them. If we were
15506 called with -g, but we didn't see any debugging information, it may
15507 mean that gcc is smuggling debugging information through to
15508 mips-tfile, in which case we must generate all local labels. */
15511 mips_frob_file_before_adjust (void)
15513 #ifndef NO_ECOFF_DEBUGGING
15514 if (ECOFF_DEBUGGING
15516 && ! ecoff_debugging_seen)
15517 flag_keep_locals = 1;
15521 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15522 the corresponding LO16 reloc. This is called before md_apply_fix and
15523 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15524 relocation operators.
15526 For our purposes, a %lo() expression matches a %got() or %hi()
15529 (a) it refers to the same symbol; and
15530 (b) the offset applied in the %lo() expression is no lower than
15531 the offset applied in the %got() or %hi().
15533 (b) allows us to cope with code like:
15536 lh $4,%lo(foo+2)($4)
15538 ...which is legal on RELA targets, and has a well-defined behaviour
15539 if the user knows that adding 2 to "foo" will not induce a carry to
15542 When several %lo()s match a particular %got() or %hi(), we use the
15543 following rules to distinguish them:
15545 (1) %lo()s with smaller offsets are a better match than %lo()s with
15548 (2) %lo()s with no matching %got() or %hi() are better than those
15549 that already have a matching %got() or %hi().
15551 (3) later %lo()s are better than earlier %lo()s.
15553 These rules are applied in order.
15555 (1) means, among other things, that %lo()s with identical offsets are
15556 chosen if they exist.
15558 (2) means that we won't associate several high-part relocations with
15559 the same low-part relocation unless there's no alternative. Having
15560 several high parts for the same low part is a GNU extension; this rule
15561 allows careful users to avoid it.
15563 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15564 with the last high-part relocation being at the front of the list.
15565 It therefore makes sense to choose the last matching low-part
15566 relocation, all other things being equal. It's also easier
15567 to code that way. */
15570 mips_frob_file (void)
15572 struct mips_hi_fixup *l;
15573 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15575 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15577 segment_info_type *seginfo;
15578 bfd_boolean matched_lo_p;
15579 fixS **hi_pos, **lo_pos, **pos;
15581 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15583 /* If a GOT16 relocation turns out to be against a global symbol,
15584 there isn't supposed to be a matching LO. Ignore %gots against
15585 constants; we'll report an error for those later. */
15586 if (got16_reloc_p (l->fixp->fx_r_type)
15587 && !(l->fixp->fx_addsy
15588 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15591 /* Check quickly whether the next fixup happens to be a matching %lo. */
15592 if (fixup_has_matching_lo_p (l->fixp))
15595 seginfo = seg_info (l->seg);
15597 /* Set HI_POS to the position of this relocation in the chain.
15598 Set LO_POS to the position of the chosen low-part relocation.
15599 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15600 relocation that matches an immediately-preceding high-part
15604 matched_lo_p = FALSE;
15605 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15607 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15609 if (*pos == l->fixp)
15612 if ((*pos)->fx_r_type == looking_for_rtype
15613 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15614 && (*pos)->fx_offset >= l->fixp->fx_offset
15616 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15618 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15621 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15622 && fixup_has_matching_lo_p (*pos));
15625 /* If we found a match, remove the high-part relocation from its
15626 current position and insert it before the low-part relocation.
15627 Make the offsets match so that fixup_has_matching_lo_p()
15630 We don't warn about unmatched high-part relocations since some
15631 versions of gcc have been known to emit dead "lui ...%hi(...)"
15633 if (lo_pos != NULL)
15635 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15636 if (l->fixp->fx_next != *lo_pos)
15638 *hi_pos = l->fixp->fx_next;
15639 l->fixp->fx_next = *lo_pos;
15647 mips_force_relocation (fixS *fixp)
15649 if (generic_force_reloc (fixp))
15652 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15653 so that the linker relaxation can update targets. */
15654 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15655 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15656 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15662 /* Read the instruction associated with RELOC from BUF. */
15664 static unsigned int
15665 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15667 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15668 return read_compressed_insn (buf, 4);
15670 return read_insn (buf);
15673 /* Write instruction INSN to BUF, given that it has been relocated
15677 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15678 unsigned long insn)
15680 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15681 write_compressed_insn (buf, insn, 4);
15683 write_insn (buf, insn);
15686 /* Apply a fixup to the object file. */
15689 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15692 unsigned long insn;
15693 reloc_howto_type *howto;
15695 /* We ignore generic BFD relocations we don't know about. */
15696 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15700 gas_assert (fixP->fx_size == 2
15701 || fixP->fx_size == 4
15702 || fixP->fx_r_type == BFD_RELOC_16
15703 || fixP->fx_r_type == BFD_RELOC_64
15704 || fixP->fx_r_type == BFD_RELOC_CTOR
15705 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15706 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15707 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15708 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15709 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15711 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15713 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15714 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15715 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15716 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15717 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15719 /* Don't treat parts of a composite relocation as done. There are two
15722 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15723 should nevertheless be emitted if the first part is.
15725 (2) In normal usage, composite relocations are never assembly-time
15726 constants. The easiest way of dealing with the pathological
15727 exceptions is to generate a relocation against STN_UNDEF and
15728 leave everything up to the linker. */
15729 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15732 switch (fixP->fx_r_type)
15734 case BFD_RELOC_MIPS_TLS_GD:
15735 case BFD_RELOC_MIPS_TLS_LDM:
15736 case BFD_RELOC_MIPS_TLS_DTPREL32:
15737 case BFD_RELOC_MIPS_TLS_DTPREL64:
15738 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15739 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15740 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15741 case BFD_RELOC_MIPS_TLS_TPREL32:
15742 case BFD_RELOC_MIPS_TLS_TPREL64:
15743 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15744 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15745 case BFD_RELOC_MICROMIPS_TLS_GD:
15746 case BFD_RELOC_MICROMIPS_TLS_LDM:
15747 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15748 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15749 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15750 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15751 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15752 case BFD_RELOC_MIPS16_TLS_GD:
15753 case BFD_RELOC_MIPS16_TLS_LDM:
15754 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15755 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15756 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15757 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15758 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15759 if (!fixP->fx_addsy)
15761 as_bad_where (fixP->fx_file, fixP->fx_line,
15762 _("TLS relocation against a constant"));
15765 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15768 case BFD_RELOC_MIPS_JMP:
15769 case BFD_RELOC_MIPS_SHIFT5:
15770 case BFD_RELOC_MIPS_SHIFT6:
15771 case BFD_RELOC_MIPS_GOT_DISP:
15772 case BFD_RELOC_MIPS_GOT_PAGE:
15773 case BFD_RELOC_MIPS_GOT_OFST:
15774 case BFD_RELOC_MIPS_SUB:
15775 case BFD_RELOC_MIPS_INSERT_A:
15776 case BFD_RELOC_MIPS_INSERT_B:
15777 case BFD_RELOC_MIPS_DELETE:
15778 case BFD_RELOC_MIPS_HIGHEST:
15779 case BFD_RELOC_MIPS_HIGHER:
15780 case BFD_RELOC_MIPS_SCN_DISP:
15781 case BFD_RELOC_MIPS_REL16:
15782 case BFD_RELOC_MIPS_RELGOT:
15783 case BFD_RELOC_MIPS_JALR:
15784 case BFD_RELOC_HI16:
15785 case BFD_RELOC_HI16_S:
15786 case BFD_RELOC_LO16:
15787 case BFD_RELOC_GPREL16:
15788 case BFD_RELOC_MIPS_LITERAL:
15789 case BFD_RELOC_MIPS_CALL16:
15790 case BFD_RELOC_MIPS_GOT16:
15791 case BFD_RELOC_GPREL32:
15792 case BFD_RELOC_MIPS_GOT_HI16:
15793 case BFD_RELOC_MIPS_GOT_LO16:
15794 case BFD_RELOC_MIPS_CALL_HI16:
15795 case BFD_RELOC_MIPS_CALL_LO16:
15796 case BFD_RELOC_MIPS16_GPREL:
15797 case BFD_RELOC_MIPS16_GOT16:
15798 case BFD_RELOC_MIPS16_CALL16:
15799 case BFD_RELOC_MIPS16_HI16:
15800 case BFD_RELOC_MIPS16_HI16_S:
15801 case BFD_RELOC_MIPS16_LO16:
15802 case BFD_RELOC_MIPS16_JMP:
15803 case BFD_RELOC_MICROMIPS_JMP:
15804 case BFD_RELOC_MICROMIPS_GOT_DISP:
15805 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15806 case BFD_RELOC_MICROMIPS_GOT_OFST:
15807 case BFD_RELOC_MICROMIPS_SUB:
15808 case BFD_RELOC_MICROMIPS_HIGHEST:
15809 case BFD_RELOC_MICROMIPS_HIGHER:
15810 case BFD_RELOC_MICROMIPS_SCN_DISP:
15811 case BFD_RELOC_MICROMIPS_JALR:
15812 case BFD_RELOC_MICROMIPS_HI16:
15813 case BFD_RELOC_MICROMIPS_HI16_S:
15814 case BFD_RELOC_MICROMIPS_LO16:
15815 case BFD_RELOC_MICROMIPS_GPREL16:
15816 case BFD_RELOC_MICROMIPS_LITERAL:
15817 case BFD_RELOC_MICROMIPS_CALL16:
15818 case BFD_RELOC_MICROMIPS_GOT16:
15819 case BFD_RELOC_MICROMIPS_GOT_HI16:
15820 case BFD_RELOC_MICROMIPS_GOT_LO16:
15821 case BFD_RELOC_MICROMIPS_CALL_HI16:
15822 case BFD_RELOC_MICROMIPS_CALL_LO16:
15823 case BFD_RELOC_MIPS_EH:
15828 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15830 insn = read_reloc_insn (buf, fixP->fx_r_type);
15831 if (mips16_reloc_p (fixP->fx_r_type))
15832 insn |= mips16_immed_extend (value, 16);
15834 insn |= (value & 0xffff);
15835 write_reloc_insn (buf, fixP->fx_r_type, insn);
15838 as_bad_where (fixP->fx_file, fixP->fx_line,
15839 _("Unsupported constant in relocation"));
15844 /* This is handled like BFD_RELOC_32, but we output a sign
15845 extended value if we are only 32 bits. */
15848 if (8 <= sizeof (valueT))
15849 md_number_to_chars (buf, *valP, 8);
15854 if ((*valP & 0x80000000) != 0)
15858 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15859 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15864 case BFD_RELOC_RVA:
15866 case BFD_RELOC_32_PCREL:
15868 /* If we are deleting this reloc entry, we must fill in the
15869 value now. This can happen if we have a .word which is not
15870 resolved when it appears but is later defined. */
15872 md_number_to_chars (buf, *valP, fixP->fx_size);
15875 case BFD_RELOC_16_PCREL_S2:
15876 if ((*valP & 0x3) != 0)
15877 as_bad_where (fixP->fx_file, fixP->fx_line,
15878 _("Branch to misaligned address (%lx)"), (long) *valP);
15880 /* We need to save the bits in the instruction since fixup_segment()
15881 might be deleting the relocation entry (i.e., a branch within
15882 the current segment). */
15883 if (! fixP->fx_done)
15886 /* Update old instruction data. */
15887 insn = read_insn (buf);
15889 if (*valP + 0x20000 <= 0x3ffff)
15891 insn |= (*valP >> 2) & 0xffff;
15892 write_insn (buf, insn);
15894 else if (mips_pic == NO_PIC
15896 && fixP->fx_frag->fr_address >= text_section->vma
15897 && (fixP->fx_frag->fr_address
15898 < text_section->vma + bfd_get_section_size (text_section))
15899 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15900 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15901 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15903 /* The branch offset is too large. If this is an
15904 unconditional branch, and we are not generating PIC code,
15905 we can convert it to an absolute jump instruction. */
15906 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15907 insn = 0x0c000000; /* jal */
15909 insn = 0x08000000; /* j */
15910 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15912 fixP->fx_addsy = section_symbol (text_section);
15913 *valP += md_pcrel_from (fixP);
15914 write_insn (buf, insn);
15918 /* If we got here, we have branch-relaxation disabled,
15919 and there's nothing we can do to fix this instruction
15920 without turning it into a longer sequence. */
15921 as_bad_where (fixP->fx_file, fixP->fx_line,
15922 _("Branch out of range"));
15926 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15927 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15928 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15929 /* We adjust the offset back to even. */
15930 if ((*valP & 0x1) != 0)
15933 if (! fixP->fx_done)
15936 /* Should never visit here, because we keep the relocation. */
15940 case BFD_RELOC_VTABLE_INHERIT:
15943 && !S_IS_DEFINED (fixP->fx_addsy)
15944 && !S_IS_WEAK (fixP->fx_addsy))
15945 S_SET_WEAK (fixP->fx_addsy);
15948 case BFD_RELOC_VTABLE_ENTRY:
15956 /* Remember value for tc_gen_reloc. */
15957 fixP->fx_addnumber = *valP;
15967 name = input_line_pointer;
15968 c = get_symbol_end ();
15969 p = (symbolS *) symbol_find_or_make (name);
15970 *input_line_pointer = c;
15974 /* Align the current frag to a given power of two. If a particular
15975 fill byte should be used, FILL points to an integer that contains
15976 that byte, otherwise FILL is null.
15978 This function used to have the comment:
15980 The MIPS assembler also automatically adjusts any preceding label.
15982 The implementation therefore applied the adjustment to a maximum of
15983 one label. However, other label adjustments are applied to batches
15984 of labels, and adjusting just one caused problems when new labels
15985 were added for the sake of debugging or unwind information.
15986 We therefore adjust all preceding labels (given as LABELS) instead. */
15989 mips_align (int to, int *fill, struct insn_label_list *labels)
15991 mips_emit_delays ();
15992 mips_record_compressed_mode ();
15993 if (fill == NULL && subseg_text_p (now_seg))
15994 frag_align_code (to, 0);
15996 frag_align (to, fill ? *fill : 0, 0);
15997 record_alignment (now_seg, to);
15998 mips_move_labels (labels, FALSE);
16001 /* Align to a given power of two. .align 0 turns off the automatic
16002 alignment used by the data creating pseudo-ops. */
16005 s_align (int x ATTRIBUTE_UNUSED)
16007 int temp, fill_value, *fill_ptr;
16008 long max_alignment = 28;
16010 /* o Note that the assembler pulls down any immediately preceding label
16011 to the aligned address.
16012 o It's not documented but auto alignment is reinstated by
16013 a .align pseudo instruction.
16014 o Note also that after auto alignment is turned off the mips assembler
16015 issues an error on attempt to assemble an improperly aligned data item.
16018 temp = get_absolute_expression ();
16019 if (temp > max_alignment)
16020 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16023 as_warn (_("Alignment negative: 0 assumed."));
16026 if (*input_line_pointer == ',')
16028 ++input_line_pointer;
16029 fill_value = get_absolute_expression ();
16030 fill_ptr = &fill_value;
16036 segment_info_type *si = seg_info (now_seg);
16037 struct insn_label_list *l = si->label_list;
16038 /* Auto alignment should be switched on by next section change. */
16040 mips_align (temp, fill_ptr, l);
16047 demand_empty_rest_of_line ();
16051 s_change_sec (int sec)
16055 /* The ELF backend needs to know that we are changing sections, so
16056 that .previous works correctly. We could do something like check
16057 for an obj_section_change_hook macro, but that might be confusing
16058 as it would not be appropriate to use it in the section changing
16059 functions in read.c, since obj-elf.c intercepts those. FIXME:
16060 This should be cleaner, somehow. */
16061 obj_elf_section_change_hook ();
16063 mips_emit_delays ();
16074 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16075 demand_empty_rest_of_line ();
16079 seg = subseg_new (RDATA_SECTION_NAME,
16080 (subsegT) get_absolute_expression ());
16081 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16082 | SEC_READONLY | SEC_RELOC
16084 if (strncmp (TARGET_OS, "elf", 3) != 0)
16085 record_alignment (seg, 4);
16086 demand_empty_rest_of_line ();
16090 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16091 bfd_set_section_flags (stdoutput, seg,
16092 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16093 if (strncmp (TARGET_OS, "elf", 3) != 0)
16094 record_alignment (seg, 4);
16095 demand_empty_rest_of_line ();
16099 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16100 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16101 if (strncmp (TARGET_OS, "elf", 3) != 0)
16102 record_alignment (seg, 4);
16103 demand_empty_rest_of_line ();
16111 s_change_section (int ignore ATTRIBUTE_UNUSED)
16113 char *section_name;
16118 int section_entry_size;
16119 int section_alignment;
16121 section_name = input_line_pointer;
16122 c = get_symbol_end ();
16124 next_c = *(input_line_pointer + 1);
16126 /* Do we have .section Name<,"flags">? */
16127 if (c != ',' || (c == ',' && next_c == '"'))
16129 /* just after name is now '\0'. */
16130 *input_line_pointer = c;
16131 input_line_pointer = section_name;
16132 obj_elf_section (ignore);
16135 input_line_pointer++;
16137 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16139 section_type = get_absolute_expression ();
16142 if (*input_line_pointer++ == ',')
16143 section_flag = get_absolute_expression ();
16146 if (*input_line_pointer++ == ',')
16147 section_entry_size = get_absolute_expression ();
16149 section_entry_size = 0;
16150 if (*input_line_pointer++ == ',')
16151 section_alignment = get_absolute_expression ();
16153 section_alignment = 0;
16154 /* FIXME: really ignore? */
16155 (void) section_alignment;
16157 section_name = xstrdup (section_name);
16159 /* When using the generic form of .section (as implemented by obj-elf.c),
16160 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16161 traditionally had to fall back on the more common @progbits instead.
16163 There's nothing really harmful in this, since bfd will correct
16164 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16165 means that, for backwards compatibility, the special_section entries
16166 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16168 Even so, we shouldn't force users of the MIPS .section syntax to
16169 incorrectly label the sections as SHT_PROGBITS. The best compromise
16170 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16171 generic type-checking code. */
16172 if (section_type == SHT_MIPS_DWARF)
16173 section_type = SHT_PROGBITS;
16175 obj_elf_change_section (section_name, section_type, section_flag,
16176 section_entry_size, 0, 0, 0);
16178 if (now_seg->name != section_name)
16179 free (section_name);
16183 mips_enable_auto_align (void)
16189 s_cons (int log_size)
16191 segment_info_type *si = seg_info (now_seg);
16192 struct insn_label_list *l = si->label_list;
16194 mips_emit_delays ();
16195 if (log_size > 0 && auto_align)
16196 mips_align (log_size, 0, l);
16197 cons (1 << log_size);
16198 mips_clear_insn_labels ();
16202 s_float_cons (int type)
16204 segment_info_type *si = seg_info (now_seg);
16205 struct insn_label_list *l = si->label_list;
16207 mips_emit_delays ();
16212 mips_align (3, 0, l);
16214 mips_align (2, 0, l);
16218 mips_clear_insn_labels ();
16221 /* Handle .globl. We need to override it because on Irix 5 you are
16224 where foo is an undefined symbol, to mean that foo should be
16225 considered to be the address of a function. */
16228 s_mips_globl (int x ATTRIBUTE_UNUSED)
16237 name = input_line_pointer;
16238 c = get_symbol_end ();
16239 symbolP = symbol_find_or_make (name);
16240 S_SET_EXTERNAL (symbolP);
16242 *input_line_pointer = c;
16243 SKIP_WHITESPACE ();
16245 /* On Irix 5, every global symbol that is not explicitly labelled as
16246 being a function is apparently labelled as being an object. */
16249 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16250 && (*input_line_pointer != ','))
16255 secname = input_line_pointer;
16256 c = get_symbol_end ();
16257 sec = bfd_get_section_by_name (stdoutput, secname);
16259 as_bad (_("%s: no such section"), secname);
16260 *input_line_pointer = c;
16262 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16263 flag = BSF_FUNCTION;
16266 symbol_get_bfdsym (symbolP)->flags |= flag;
16268 c = *input_line_pointer;
16271 input_line_pointer++;
16272 SKIP_WHITESPACE ();
16273 if (is_end_of_line[(unsigned char) *input_line_pointer])
16279 demand_empty_rest_of_line ();
16283 s_option (int x ATTRIBUTE_UNUSED)
16288 opt = input_line_pointer;
16289 c = get_symbol_end ();
16293 /* FIXME: What does this mean? */
16295 else if (strncmp (opt, "pic", 3) == 0)
16299 i = atoi (opt + 3);
16304 mips_pic = SVR4_PIC;
16305 mips_abicalls = TRUE;
16308 as_bad (_(".option pic%d not supported"), i);
16310 if (mips_pic == SVR4_PIC)
16312 if (g_switch_seen && g_switch_value != 0)
16313 as_warn (_("-G may not be used with SVR4 PIC code"));
16314 g_switch_value = 0;
16315 bfd_set_gp_size (stdoutput, 0);
16319 as_warn (_("Unrecognized option \"%s\""), opt);
16321 *input_line_pointer = c;
16322 demand_empty_rest_of_line ();
16325 /* This structure is used to hold a stack of .set values. */
16327 struct mips_option_stack
16329 struct mips_option_stack *next;
16330 struct mips_set_options options;
16333 static struct mips_option_stack *mips_opts_stack;
16335 /* Handle the .set pseudo-op. */
16338 s_mipsset (int x ATTRIBUTE_UNUSED)
16340 char *name = input_line_pointer, ch;
16341 const struct mips_ase *ase;
16343 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16344 ++input_line_pointer;
16345 ch = *input_line_pointer;
16346 *input_line_pointer = '\0';
16348 if (strcmp (name, "reorder") == 0)
16350 if (mips_opts.noreorder)
16353 else if (strcmp (name, "noreorder") == 0)
16355 if (!mips_opts.noreorder)
16356 start_noreorder ();
16358 else if (strncmp (name, "at=", 3) == 0)
16360 char *s = name + 3;
16362 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16363 as_bad (_("Unrecognized register name `%s'"), s);
16365 else if (strcmp (name, "at") == 0)
16367 mips_opts.at = ATREG;
16369 else if (strcmp (name, "noat") == 0)
16371 mips_opts.at = ZERO;
16373 else if (strcmp (name, "macro") == 0)
16375 mips_opts.warn_about_macros = 0;
16377 else if (strcmp (name, "nomacro") == 0)
16379 if (mips_opts.noreorder == 0)
16380 as_bad (_("`noreorder' must be set before `nomacro'"));
16381 mips_opts.warn_about_macros = 1;
16383 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16385 mips_opts.nomove = 0;
16387 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16389 mips_opts.nomove = 1;
16391 else if (strcmp (name, "bopt") == 0)
16393 mips_opts.nobopt = 0;
16395 else if (strcmp (name, "nobopt") == 0)
16397 mips_opts.nobopt = 1;
16399 else if (strcmp (name, "gp=default") == 0)
16400 mips_opts.gp32 = file_mips_gp32;
16401 else if (strcmp (name, "gp=32") == 0)
16402 mips_opts.gp32 = 1;
16403 else if (strcmp (name, "gp=64") == 0)
16405 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16406 as_warn (_("%s isa does not support 64-bit registers"),
16407 mips_cpu_info_from_isa (mips_opts.isa)->name);
16408 mips_opts.gp32 = 0;
16410 else if (strcmp (name, "fp=default") == 0)
16411 mips_opts.fp32 = file_mips_fp32;
16412 else if (strcmp (name, "fp=32") == 0)
16413 mips_opts.fp32 = 1;
16414 else if (strcmp (name, "fp=64") == 0)
16416 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16417 as_warn (_("%s isa does not support 64-bit floating point registers"),
16418 mips_cpu_info_from_isa (mips_opts.isa)->name);
16419 mips_opts.fp32 = 0;
16421 else if (strcmp (name, "softfloat") == 0)
16422 mips_opts.soft_float = 1;
16423 else if (strcmp (name, "hardfloat") == 0)
16424 mips_opts.soft_float = 0;
16425 else if (strcmp (name, "singlefloat") == 0)
16426 mips_opts.single_float = 1;
16427 else if (strcmp (name, "doublefloat") == 0)
16428 mips_opts.single_float = 0;
16429 else if (strcmp (name, "mips16") == 0
16430 || strcmp (name, "MIPS-16") == 0)
16432 if (mips_opts.micromips == 1)
16433 as_fatal (_("`mips16' cannot be used with `micromips'"));
16434 mips_opts.mips16 = 1;
16436 else if (strcmp (name, "nomips16") == 0
16437 || strcmp (name, "noMIPS-16") == 0)
16438 mips_opts.mips16 = 0;
16439 else if (strcmp (name, "micromips") == 0)
16441 if (mips_opts.mips16 == 1)
16442 as_fatal (_("`micromips' cannot be used with `mips16'"));
16443 mips_opts.micromips = 1;
16445 else if (strcmp (name, "nomicromips") == 0)
16446 mips_opts.micromips = 0;
16447 else if (name[0] == 'n'
16449 && (ase = mips_lookup_ase (name + 2)))
16450 mips_set_ase (ase, FALSE);
16451 else if ((ase = mips_lookup_ase (name)))
16452 mips_set_ase (ase, TRUE);
16453 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16457 /* Permit the user to change the ISA and architecture on the fly.
16458 Needless to say, misuse can cause serious problems. */
16459 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16462 mips_opts.isa = file_mips_isa;
16463 mips_opts.arch = file_mips_arch;
16465 else if (strncmp (name, "arch=", 5) == 0)
16467 const struct mips_cpu_info *p;
16469 p = mips_parse_cpu("internal use", name + 5);
16471 as_bad (_("unknown architecture %s"), name + 5);
16474 mips_opts.arch = p->cpu;
16475 mips_opts.isa = p->isa;
16478 else if (strncmp (name, "mips", 4) == 0)
16480 const struct mips_cpu_info *p;
16482 p = mips_parse_cpu("internal use", name);
16484 as_bad (_("unknown ISA level %s"), name + 4);
16487 mips_opts.arch = p->cpu;
16488 mips_opts.isa = p->isa;
16492 as_bad (_("unknown ISA or architecture %s"), name);
16494 switch (mips_opts.isa)
16502 mips_opts.gp32 = 1;
16503 mips_opts.fp32 = 1;
16510 mips_opts.gp32 = 0;
16511 if (mips_opts.arch == CPU_R5900)
16513 mips_opts.fp32 = 1;
16517 mips_opts.fp32 = 0;
16521 as_bad (_("unknown ISA level %s"), name + 4);
16526 mips_opts.gp32 = file_mips_gp32;
16527 mips_opts.fp32 = file_mips_fp32;
16530 else if (strcmp (name, "autoextend") == 0)
16531 mips_opts.noautoextend = 0;
16532 else if (strcmp (name, "noautoextend") == 0)
16533 mips_opts.noautoextend = 1;
16534 else if (strcmp (name, "insn32") == 0)
16535 mips_opts.insn32 = TRUE;
16536 else if (strcmp (name, "noinsn32") == 0)
16537 mips_opts.insn32 = FALSE;
16538 else if (strcmp (name, "push") == 0)
16540 struct mips_option_stack *s;
16542 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16543 s->next = mips_opts_stack;
16544 s->options = mips_opts;
16545 mips_opts_stack = s;
16547 else if (strcmp (name, "pop") == 0)
16549 struct mips_option_stack *s;
16551 s = mips_opts_stack;
16553 as_bad (_(".set pop with no .set push"));
16556 /* If we're changing the reorder mode we need to handle
16557 delay slots correctly. */
16558 if (s->options.noreorder && ! mips_opts.noreorder)
16559 start_noreorder ();
16560 else if (! s->options.noreorder && mips_opts.noreorder)
16563 mips_opts = s->options;
16564 mips_opts_stack = s->next;
16568 else if (strcmp (name, "sym32") == 0)
16569 mips_opts.sym32 = TRUE;
16570 else if (strcmp (name, "nosym32") == 0)
16571 mips_opts.sym32 = FALSE;
16572 else if (strchr (name, ','))
16574 /* Generic ".set" directive; use the generic handler. */
16575 *input_line_pointer = ch;
16576 input_line_pointer = name;
16582 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16584 mips_check_isa_supports_ases ();
16585 *input_line_pointer = ch;
16586 demand_empty_rest_of_line ();
16589 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16590 .option pic2. It means to generate SVR4 PIC calls. */
16593 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16595 mips_pic = SVR4_PIC;
16596 mips_abicalls = TRUE;
16598 if (g_switch_seen && g_switch_value != 0)
16599 as_warn (_("-G may not be used with SVR4 PIC code"));
16600 g_switch_value = 0;
16602 bfd_set_gp_size (stdoutput, 0);
16603 demand_empty_rest_of_line ();
16606 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16607 PIC code. It sets the $gp register for the function based on the
16608 function address, which is in the register named in the argument.
16609 This uses a relocation against _gp_disp, which is handled specially
16610 by the linker. The result is:
16611 lui $gp,%hi(_gp_disp)
16612 addiu $gp,$gp,%lo(_gp_disp)
16613 addu $gp,$gp,.cpload argument
16614 The .cpload argument is normally $25 == $t9.
16616 The -mno-shared option changes this to:
16617 lui $gp,%hi(__gnu_local_gp)
16618 addiu $gp,$gp,%lo(__gnu_local_gp)
16619 and the argument is ignored. This saves an instruction, but the
16620 resulting code is not position independent; it uses an absolute
16621 address for __gnu_local_gp. Thus code assembled with -mno-shared
16622 can go into an ordinary executable, but not into a shared library. */
16625 s_cpload (int ignore ATTRIBUTE_UNUSED)
16631 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16632 .cpload is ignored. */
16633 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16639 if (mips_opts.mips16)
16641 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16642 ignore_rest_of_line ();
16646 /* .cpload should be in a .set noreorder section. */
16647 if (mips_opts.noreorder == 0)
16648 as_warn (_(".cpload not in noreorder section"));
16650 reg = tc_get_register (0);
16652 /* If we need to produce a 64-bit address, we are better off using
16653 the default instruction sequence. */
16654 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16656 ex.X_op = O_symbol;
16657 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16659 ex.X_op_symbol = NULL;
16660 ex.X_add_number = 0;
16662 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16663 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16665 mips_mark_labels ();
16666 mips_assembling_insn = TRUE;
16669 macro_build_lui (&ex, mips_gp_register);
16670 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16671 mips_gp_register, BFD_RELOC_LO16);
16673 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16674 mips_gp_register, reg);
16677 mips_assembling_insn = FALSE;
16678 demand_empty_rest_of_line ();
16681 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16682 .cpsetup $reg1, offset|$reg2, label
16684 If offset is given, this results in:
16685 sd $gp, offset($sp)
16686 lui $gp, %hi(%neg(%gp_rel(label)))
16687 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16688 daddu $gp, $gp, $reg1
16690 If $reg2 is given, this results in:
16691 daddu $reg2, $gp, $0
16692 lui $gp, %hi(%neg(%gp_rel(label)))
16693 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16694 daddu $gp, $gp, $reg1
16695 $reg1 is normally $25 == $t9.
16697 The -mno-shared option replaces the last three instructions with
16699 addiu $gp,$gp,%lo(_gp) */
16702 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16704 expressionS ex_off;
16705 expressionS ex_sym;
16708 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16709 We also need NewABI support. */
16710 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16716 if (mips_opts.mips16)
16718 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16719 ignore_rest_of_line ();
16723 reg1 = tc_get_register (0);
16724 SKIP_WHITESPACE ();
16725 if (*input_line_pointer != ',')
16727 as_bad (_("missing argument separator ',' for .cpsetup"));
16731 ++input_line_pointer;
16732 SKIP_WHITESPACE ();
16733 if (*input_line_pointer == '$')
16735 mips_cpreturn_register = tc_get_register (0);
16736 mips_cpreturn_offset = -1;
16740 mips_cpreturn_offset = get_absolute_expression ();
16741 mips_cpreturn_register = -1;
16743 SKIP_WHITESPACE ();
16744 if (*input_line_pointer != ',')
16746 as_bad (_("missing argument separator ',' for .cpsetup"));
16750 ++input_line_pointer;
16751 SKIP_WHITESPACE ();
16752 expression (&ex_sym);
16754 mips_mark_labels ();
16755 mips_assembling_insn = TRUE;
16758 if (mips_cpreturn_register == -1)
16760 ex_off.X_op = O_constant;
16761 ex_off.X_add_symbol = NULL;
16762 ex_off.X_op_symbol = NULL;
16763 ex_off.X_add_number = mips_cpreturn_offset;
16765 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16766 BFD_RELOC_LO16, SP);
16769 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16770 mips_gp_register, 0);
16772 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16774 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16775 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16778 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16779 mips_gp_register, -1, BFD_RELOC_GPREL16,
16780 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16783 mips_gp_register, reg1);
16789 ex.X_op = O_symbol;
16790 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16791 ex.X_op_symbol = NULL;
16792 ex.X_add_number = 0;
16794 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16795 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16797 macro_build_lui (&ex, mips_gp_register);
16798 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16799 mips_gp_register, BFD_RELOC_LO16);
16804 mips_assembling_insn = FALSE;
16805 demand_empty_rest_of_line ();
16809 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16811 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16812 .cplocal is ignored. */
16813 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16819 if (mips_opts.mips16)
16821 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16822 ignore_rest_of_line ();
16826 mips_gp_register = tc_get_register (0);
16827 demand_empty_rest_of_line ();
16830 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16831 offset from $sp. The offset is remembered, and after making a PIC
16832 call $gp is restored from that location. */
16835 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16839 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16840 .cprestore is ignored. */
16841 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16847 if (mips_opts.mips16)
16849 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16850 ignore_rest_of_line ();
16854 mips_cprestore_offset = get_absolute_expression ();
16855 mips_cprestore_valid = 1;
16857 ex.X_op = O_constant;
16858 ex.X_add_symbol = NULL;
16859 ex.X_op_symbol = NULL;
16860 ex.X_add_number = mips_cprestore_offset;
16862 mips_mark_labels ();
16863 mips_assembling_insn = TRUE;
16866 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16867 SP, HAVE_64BIT_ADDRESSES);
16870 mips_assembling_insn = FALSE;
16871 demand_empty_rest_of_line ();
16874 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16875 was given in the preceding .cpsetup, it results in:
16876 ld $gp, offset($sp)
16878 If a register $reg2 was given there, it results in:
16879 daddu $gp, $reg2, $0 */
16882 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16886 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16887 We also need NewABI support. */
16888 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16894 if (mips_opts.mips16)
16896 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16897 ignore_rest_of_line ();
16901 mips_mark_labels ();
16902 mips_assembling_insn = TRUE;
16905 if (mips_cpreturn_register == -1)
16907 ex.X_op = O_constant;
16908 ex.X_add_symbol = NULL;
16909 ex.X_op_symbol = NULL;
16910 ex.X_add_number = mips_cpreturn_offset;
16912 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16915 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16916 mips_cpreturn_register, 0);
16919 mips_assembling_insn = FALSE;
16920 demand_empty_rest_of_line ();
16923 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16924 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16925 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16926 debug information or MIPS16 TLS. */
16929 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16930 bfd_reloc_code_real_type rtype)
16937 if (ex.X_op != O_symbol)
16939 as_bad (_("Unsupported use of %s"), dirstr);
16940 ignore_rest_of_line ();
16943 p = frag_more (bytes);
16944 md_number_to_chars (p, 0, bytes);
16945 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16946 demand_empty_rest_of_line ();
16947 mips_clear_insn_labels ();
16950 /* Handle .dtprelword. */
16953 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16955 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16958 /* Handle .dtpreldword. */
16961 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16963 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16966 /* Handle .tprelword. */
16969 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16971 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16974 /* Handle .tpreldword. */
16977 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16979 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16982 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16983 code. It sets the offset to use in gp_rel relocations. */
16986 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16988 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16989 We also need NewABI support. */
16990 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16996 mips_gprel_offset = get_absolute_expression ();
16998 demand_empty_rest_of_line ();
17001 /* Handle the .gpword pseudo-op. This is used when generating PIC
17002 code. It generates a 32 bit GP relative reloc. */
17005 s_gpword (int ignore ATTRIBUTE_UNUSED)
17007 segment_info_type *si;
17008 struct insn_label_list *l;
17012 /* When not generating PIC code, this is treated as .word. */
17013 if (mips_pic != SVR4_PIC)
17019 si = seg_info (now_seg);
17020 l = si->label_list;
17021 mips_emit_delays ();
17023 mips_align (2, 0, l);
17026 mips_clear_insn_labels ();
17028 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17030 as_bad (_("Unsupported use of .gpword"));
17031 ignore_rest_of_line ();
17035 md_number_to_chars (p, 0, 4);
17036 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17037 BFD_RELOC_GPREL32);
17039 demand_empty_rest_of_line ();
17043 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17045 segment_info_type *si;
17046 struct insn_label_list *l;
17050 /* When not generating PIC code, this is treated as .dword. */
17051 if (mips_pic != SVR4_PIC)
17057 si = seg_info (now_seg);
17058 l = si->label_list;
17059 mips_emit_delays ();
17061 mips_align (3, 0, l);
17064 mips_clear_insn_labels ();
17066 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17068 as_bad (_("Unsupported use of .gpdword"));
17069 ignore_rest_of_line ();
17073 md_number_to_chars (p, 0, 8);
17074 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17075 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17077 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17078 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17079 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17081 demand_empty_rest_of_line ();
17084 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17085 tables. It generates a R_MIPS_EH reloc. */
17088 s_ehword (int ignore ATTRIBUTE_UNUSED)
17093 mips_emit_delays ();
17096 mips_clear_insn_labels ();
17098 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17100 as_bad (_("Unsupported use of .ehword"));
17101 ignore_rest_of_line ();
17105 md_number_to_chars (p, 0, 4);
17106 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17107 BFD_RELOC_MIPS_EH);
17109 demand_empty_rest_of_line ();
17112 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17113 tables in SVR4 PIC code. */
17116 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17120 /* This is ignored when not generating SVR4 PIC code. */
17121 if (mips_pic != SVR4_PIC)
17127 mips_mark_labels ();
17128 mips_assembling_insn = TRUE;
17130 /* Add $gp to the register named as an argument. */
17132 reg = tc_get_register (0);
17133 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17136 mips_assembling_insn = FALSE;
17137 demand_empty_rest_of_line ();
17140 /* Handle the .insn pseudo-op. This marks instruction labels in
17141 mips16/micromips mode. This permits the linker to handle them specially,
17142 such as generating jalx instructions when needed. We also make
17143 them odd for the duration of the assembly, in order to generate the
17144 right sort of code. We will make them even in the adjust_symtab
17145 routine, while leaving them marked. This is convenient for the
17146 debugger and the disassembler. The linker knows to make them odd
17150 s_insn (int ignore ATTRIBUTE_UNUSED)
17152 mips_mark_labels ();
17154 demand_empty_rest_of_line ();
17157 /* Handle the .nan pseudo-op. */
17160 s_nan (int ignore ATTRIBUTE_UNUSED)
17162 static const char str_legacy[] = "legacy";
17163 static const char str_2008[] = "2008";
17166 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17168 if (i == sizeof (str_2008) - 1
17169 && memcmp (input_line_pointer, str_2008, i) == 0)
17170 mips_flag_nan2008 = TRUE;
17171 else if (i == sizeof (str_legacy) - 1
17172 && memcmp (input_line_pointer, str_legacy, i) == 0)
17173 mips_flag_nan2008 = FALSE;
17175 as_bad (_("Bad .nan directive"));
17177 input_line_pointer += i;
17178 demand_empty_rest_of_line ();
17181 /* Handle a .stab[snd] directive. Ideally these directives would be
17182 implemented in a transparent way, so that removing them would not
17183 have any effect on the generated instructions. However, s_stab
17184 internally changes the section, so in practice we need to decide
17185 now whether the preceding label marks compressed code. We do not
17186 support changing the compression mode of a label after a .stab*
17187 directive, such as in:
17193 so the current mode wins. */
17196 s_mips_stab (int type)
17198 mips_mark_labels ();
17202 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17205 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17212 name = input_line_pointer;
17213 c = get_symbol_end ();
17214 symbolP = symbol_find_or_make (name);
17215 S_SET_WEAK (symbolP);
17216 *input_line_pointer = c;
17218 SKIP_WHITESPACE ();
17220 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17222 if (S_IS_DEFINED (symbolP))
17224 as_bad (_("ignoring attempt to redefine symbol %s"),
17225 S_GET_NAME (symbolP));
17226 ignore_rest_of_line ();
17230 if (*input_line_pointer == ',')
17232 ++input_line_pointer;
17233 SKIP_WHITESPACE ();
17237 if (exp.X_op != O_symbol)
17239 as_bad (_("bad .weakext directive"));
17240 ignore_rest_of_line ();
17243 symbol_set_value_expression (symbolP, &exp);
17246 demand_empty_rest_of_line ();
17249 /* Parse a register string into a number. Called from the ECOFF code
17250 to parse .frame. The argument is non-zero if this is the frame
17251 register, so that we can record it in mips_frame_reg. */
17254 tc_get_register (int frame)
17258 SKIP_WHITESPACE ();
17259 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17263 mips_frame_reg = reg != 0 ? reg : SP;
17264 mips_frame_reg_valid = 1;
17265 mips_cprestore_valid = 0;
17271 md_section_align (asection *seg, valueT addr)
17273 int align = bfd_get_section_alignment (stdoutput, seg);
17275 /* We don't need to align ELF sections to the full alignment.
17276 However, Irix 5 may prefer that we align them at least to a 16
17277 byte boundary. We don't bother to align the sections if we
17278 are targeted for an embedded system. */
17279 if (strncmp (TARGET_OS, "elf", 3) == 0)
17284 return ((addr + (1 << align) - 1) & (-1 << align));
17287 /* Utility routine, called from above as well. If called while the
17288 input file is still being read, it's only an approximation. (For
17289 example, a symbol may later become defined which appeared to be
17290 undefined earlier.) */
17293 nopic_need_relax (symbolS *sym, int before_relaxing)
17298 if (g_switch_value > 0)
17300 const char *symname;
17303 /* Find out whether this symbol can be referenced off the $gp
17304 register. It can be if it is smaller than the -G size or if
17305 it is in the .sdata or .sbss section. Certain symbols can
17306 not be referenced off the $gp, although it appears as though
17308 symname = S_GET_NAME (sym);
17309 if (symname != (const char *) NULL
17310 && (strcmp (symname, "eprol") == 0
17311 || strcmp (symname, "etext") == 0
17312 || strcmp (symname, "_gp") == 0
17313 || strcmp (symname, "edata") == 0
17314 || strcmp (symname, "_fbss") == 0
17315 || strcmp (symname, "_fdata") == 0
17316 || strcmp (symname, "_ftext") == 0
17317 || strcmp (symname, "end") == 0
17318 || strcmp (symname, "_gp_disp") == 0))
17320 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17322 #ifndef NO_ECOFF_DEBUGGING
17323 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17324 && (symbol_get_obj (sym)->ecoff_extern_size
17325 <= g_switch_value))
17327 /* We must defer this decision until after the whole
17328 file has been read, since there might be a .extern
17329 after the first use of this symbol. */
17330 || (before_relaxing
17331 #ifndef NO_ECOFF_DEBUGGING
17332 && symbol_get_obj (sym)->ecoff_extern_size == 0
17334 && S_GET_VALUE (sym) == 0)
17335 || (S_GET_VALUE (sym) != 0
17336 && S_GET_VALUE (sym) <= g_switch_value)))
17340 const char *segname;
17342 segname = segment_name (S_GET_SEGMENT (sym));
17343 gas_assert (strcmp (segname, ".lit8") != 0
17344 && strcmp (segname, ".lit4") != 0);
17345 change = (strcmp (segname, ".sdata") != 0
17346 && strcmp (segname, ".sbss") != 0
17347 && strncmp (segname, ".sdata.", 7) != 0
17348 && strncmp (segname, ".sbss.", 6) != 0
17349 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17350 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17355 /* We are not optimizing for the $gp register. */
17360 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17363 pic_need_relax (symbolS *sym, asection *segtype)
17367 /* Handle the case of a symbol equated to another symbol. */
17368 while (symbol_equated_reloc_p (sym))
17372 /* It's possible to get a loop here in a badly written program. */
17373 n = symbol_get_value_expression (sym)->X_add_symbol;
17379 if (symbol_section_p (sym))
17382 symsec = S_GET_SEGMENT (sym);
17384 /* This must duplicate the test in adjust_reloc_syms. */
17385 return (!bfd_is_und_section (symsec)
17386 && !bfd_is_abs_section (symsec)
17387 && !bfd_is_com_section (symsec)
17388 && !s_is_linkonce (sym, segtype)
17389 /* A global or weak symbol is treated as external. */
17390 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17394 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17395 extended opcode. SEC is the section the frag is in. */
17398 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17401 const struct mips16_immed_operand *op;
17403 int mintiny, maxtiny;
17407 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17409 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17412 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17413 op = mips16_immed_operands;
17414 while (op->type != type)
17417 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17422 if (type == '<' || type == '>' || type == '[' || type == ']')
17425 maxtiny = 1 << op->nbits;
17430 maxtiny = (1 << op->nbits) - 1;
17435 mintiny = - (1 << (op->nbits - 1));
17436 maxtiny = (1 << (op->nbits - 1)) - 1;
17439 sym_frag = symbol_get_frag (fragp->fr_symbol);
17440 val = S_GET_VALUE (fragp->fr_symbol);
17441 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17447 /* We won't have the section when we are called from
17448 mips_relax_frag. However, we will always have been called
17449 from md_estimate_size_before_relax first. If this is a
17450 branch to a different section, we mark it as such. If SEC is
17451 NULL, and the frag is not marked, then it must be a branch to
17452 the same section. */
17455 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17460 /* Must have been called from md_estimate_size_before_relax. */
17463 fragp->fr_subtype =
17464 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17466 /* FIXME: We should support this, and let the linker
17467 catch branches and loads that are out of range. */
17468 as_bad_where (fragp->fr_file, fragp->fr_line,
17469 _("unsupported PC relative reference to different section"));
17473 if (fragp != sym_frag && sym_frag->fr_address == 0)
17474 /* Assume non-extended on the first relaxation pass.
17475 The address we have calculated will be bogus if this is
17476 a forward branch to another frag, as the forward frag
17477 will have fr_address == 0. */
17481 /* In this case, we know for sure that the symbol fragment is in
17482 the same section. If the relax_marker of the symbol fragment
17483 differs from the relax_marker of this fragment, we have not
17484 yet adjusted the symbol fragment fr_address. We want to add
17485 in STRETCH in order to get a better estimate of the address.
17486 This particularly matters because of the shift bits. */
17488 && sym_frag->relax_marker != fragp->relax_marker)
17492 /* Adjust stretch for any alignment frag. Note that if have
17493 been expanding the earlier code, the symbol may be
17494 defined in what appears to be an earlier frag. FIXME:
17495 This doesn't handle the fr_subtype field, which specifies
17496 a maximum number of bytes to skip when doing an
17498 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17500 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17503 stretch = - ((- stretch)
17504 & ~ ((1 << (int) f->fr_offset) - 1));
17506 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17515 addr = fragp->fr_address + fragp->fr_fix;
17517 /* The base address rules are complicated. The base address of
17518 a branch is the following instruction. The base address of a
17519 PC relative load or add is the instruction itself, but if it
17520 is in a delay slot (in which case it can not be extended) use
17521 the address of the instruction whose delay slot it is in. */
17522 if (type == 'p' || type == 'q')
17526 /* If we are currently assuming that this frag should be
17527 extended, then, the current address is two bytes
17529 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17532 /* Ignore the low bit in the target, since it will be set
17533 for a text label. */
17534 if ((val & 1) != 0)
17537 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17539 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17542 val -= addr & ~ ((1 << op->shift) - 1);
17544 /* Branch offsets have an implicit 0 in the lowest bit. */
17545 if (type == 'p' || type == 'q')
17548 /* If any of the shifted bits are set, we must use an extended
17549 opcode. If the address depends on the size of this
17550 instruction, this can lead to a loop, so we arrange to always
17551 use an extended opcode. We only check this when we are in
17552 the main relaxation loop, when SEC is NULL. */
17553 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17555 fragp->fr_subtype =
17556 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17560 /* If we are about to mark a frag as extended because the value
17561 is precisely maxtiny + 1, then there is a chance of an
17562 infinite loop as in the following code:
17567 In this case when the la is extended, foo is 0x3fc bytes
17568 away, so the la can be shrunk, but then foo is 0x400 away, so
17569 the la must be extended. To avoid this loop, we mark the
17570 frag as extended if it was small, and is about to become
17571 extended with a value of maxtiny + 1. */
17572 if (val == ((maxtiny + 1) << op->shift)
17573 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17576 fragp->fr_subtype =
17577 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17581 else if (symsec != absolute_section && sec != NULL)
17582 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17584 if ((val & ((1 << op->shift) - 1)) != 0
17585 || val < (mintiny << op->shift)
17586 || val > (maxtiny << op->shift))
17592 /* Compute the length of a branch sequence, and adjust the
17593 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17594 worst-case length is computed, with UPDATE being used to indicate
17595 whether an unconditional (-1), branch-likely (+1) or regular (0)
17596 branch is to be computed. */
17598 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17600 bfd_boolean toofar;
17604 && S_IS_DEFINED (fragp->fr_symbol)
17605 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17610 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17612 addr = fragp->fr_address + fragp->fr_fix + 4;
17616 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17619 /* If the symbol is not defined or it's in a different segment,
17620 assume the user knows what's going on and emit a short
17626 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17628 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17629 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17630 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17631 RELAX_BRANCH_LINK (fragp->fr_subtype),
17637 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17640 if (mips_pic != NO_PIC)
17642 /* Additional space for PIC loading of target address. */
17644 if (mips_opts.isa == ISA_MIPS1)
17645 /* Additional space for $at-stabilizing nop. */
17649 /* If branch is conditional. */
17650 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17657 /* Compute the length of a branch sequence, and adjust the
17658 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17659 worst-case length is computed, with UPDATE being used to indicate
17660 whether an unconditional (-1), or regular (0) branch is to be
17664 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17666 bfd_boolean toofar;
17670 && S_IS_DEFINED (fragp->fr_symbol)
17671 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17676 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17677 /* Ignore the low bit in the target, since it will be set
17678 for a text label. */
17679 if ((val & 1) != 0)
17682 addr = fragp->fr_address + fragp->fr_fix + 4;
17686 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17689 /* If the symbol is not defined or it's in a different segment,
17690 assume the user knows what's going on and emit a short
17696 if (fragp && update
17697 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17698 fragp->fr_subtype = (toofar
17699 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17700 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17705 bfd_boolean compact_known = fragp != NULL;
17706 bfd_boolean compact = FALSE;
17707 bfd_boolean uncond;
17710 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17712 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17714 uncond = update < 0;
17716 /* If label is out of range, we turn branch <br>:
17718 <br> label # 4 bytes
17724 nop # 2 bytes if compact && !PIC
17727 if (mips_pic == NO_PIC && (!compact_known || compact))
17730 /* If assembling PIC code, we further turn:
17736 lw/ld at, %got(label)(gp) # 4 bytes
17737 d/addiu at, %lo(label) # 4 bytes
17740 if (mips_pic != NO_PIC)
17743 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17745 <brneg> 0f # 4 bytes
17746 nop # 2 bytes if !compact
17749 length += (compact_known && compact) ? 4 : 6;
17755 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17756 bit accordingly. */
17759 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17761 bfd_boolean toofar;
17764 && S_IS_DEFINED (fragp->fr_symbol)
17765 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17771 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17772 /* Ignore the low bit in the target, since it will be set
17773 for a text label. */
17774 if ((val & 1) != 0)
17777 /* Assume this is a 2-byte branch. */
17778 addr = fragp->fr_address + fragp->fr_fix + 2;
17780 /* We try to avoid the infinite loop by not adding 2 more bytes for
17785 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17787 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17788 else if (type == 'E')
17789 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17794 /* If the symbol is not defined or it's in a different segment,
17795 we emit a normal 32-bit branch. */
17798 if (fragp && update
17799 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17801 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17802 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17810 /* Estimate the size of a frag before relaxing. Unless this is the
17811 mips16, we are not really relaxing here, and the final size is
17812 encoded in the subtype information. For the mips16, we have to
17813 decide whether we are using an extended opcode or not. */
17816 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17820 if (RELAX_BRANCH_P (fragp->fr_subtype))
17823 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17825 return fragp->fr_var;
17828 if (RELAX_MIPS16_P (fragp->fr_subtype))
17829 /* We don't want to modify the EXTENDED bit here; it might get us
17830 into infinite loops. We change it only in mips_relax_frag(). */
17831 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17833 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17837 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17838 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17839 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17840 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17841 fragp->fr_var = length;
17846 if (mips_pic == NO_PIC)
17847 change = nopic_need_relax (fragp->fr_symbol, 0);
17848 else if (mips_pic == SVR4_PIC)
17849 change = pic_need_relax (fragp->fr_symbol, segtype);
17850 else if (mips_pic == VXWORKS_PIC)
17851 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17858 fragp->fr_subtype |= RELAX_USE_SECOND;
17859 return -RELAX_FIRST (fragp->fr_subtype);
17862 return -RELAX_SECOND (fragp->fr_subtype);
17865 /* This is called to see whether a reloc against a defined symbol
17866 should be converted into a reloc against a section. */
17869 mips_fix_adjustable (fixS *fixp)
17871 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17872 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17875 if (fixp->fx_addsy == NULL)
17878 /* If symbol SYM is in a mergeable section, relocations of the form
17879 SYM + 0 can usually be made section-relative. The mergeable data
17880 is then identified by the section offset rather than by the symbol.
17882 However, if we're generating REL LO16 relocations, the offset is split
17883 between the LO16 and parterning high part relocation. The linker will
17884 need to recalculate the complete offset in order to correctly identify
17887 The linker has traditionally not looked for the parterning high part
17888 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17889 placed anywhere. Rather than break backwards compatibility by changing
17890 this, it seems better not to force the issue, and instead keep the
17891 original symbol. This will work with either linker behavior. */
17892 if ((lo16_reloc_p (fixp->fx_r_type)
17893 || reloc_needs_lo_p (fixp->fx_r_type))
17894 && HAVE_IN_PLACE_ADDENDS
17895 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17898 /* There is no place to store an in-place offset for JALR relocations.
17899 Likewise an in-range offset of limited PC-relative relocations may
17900 overflow the in-place relocatable field if recalculated against the
17901 start address of the symbol's containing section. */
17902 if (HAVE_IN_PLACE_ADDENDS
17903 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17904 || jalr_reloc_p (fixp->fx_r_type)))
17907 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17908 to a floating-point stub. The same is true for non-R_MIPS16_26
17909 relocations against MIPS16 functions; in this case, the stub becomes
17910 the function's canonical address.
17912 Floating-point stubs are stored in unique .mips16.call.* or
17913 .mips16.fn.* sections. If a stub T for function F is in section S,
17914 the first relocation in section S must be against F; this is how the
17915 linker determines the target function. All relocations that might
17916 resolve to T must also be against F. We therefore have the following
17917 restrictions, which are given in an intentionally-redundant way:
17919 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17922 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17923 if that stub might be used.
17925 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17928 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17929 that stub might be used.
17931 There is a further restriction:
17933 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17934 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17935 targets with in-place addends; the relocation field cannot
17936 encode the low bit.
17938 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17939 against a MIPS16 symbol. We deal with (5) by by not reducing any
17940 such relocations on REL targets.
17942 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17943 relocation against some symbol R, no relocation against R may be
17944 reduced. (Note that this deals with (2) as well as (1) because
17945 relocations against global symbols will never be reduced on ELF
17946 targets.) This approach is a little simpler than trying to detect
17947 stub sections, and gives the "all or nothing" per-symbol consistency
17948 that we have for MIPS16 symbols. */
17949 if (fixp->fx_subsy == NULL
17950 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17951 || *symbol_get_tc (fixp->fx_addsy)
17952 || (HAVE_IN_PLACE_ADDENDS
17953 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17954 && jmp_reloc_p (fixp->fx_r_type))))
17960 /* Translate internal representation of relocation info to BFD target
17964 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17966 static arelent *retval[4];
17968 bfd_reloc_code_real_type code;
17970 memset (retval, 0, sizeof(retval));
17971 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17972 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17973 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17974 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17976 if (fixp->fx_pcrel)
17978 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17979 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17980 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17981 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17982 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
17984 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17985 Relocations want only the symbol offset. */
17986 reloc->addend = fixp->fx_addnumber + reloc->address;
17989 reloc->addend = fixp->fx_addnumber;
17991 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17992 entry to be used in the relocation's section offset. */
17993 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17995 reloc->address = reloc->addend;
17999 code = fixp->fx_r_type;
18001 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18002 if (reloc->howto == NULL)
18004 as_bad_where (fixp->fx_file, fixp->fx_line,
18005 _("Can not represent %s relocation in this object file format"),
18006 bfd_get_reloc_code_name (code));
18013 /* Relax a machine dependent frag. This returns the amount by which
18014 the current size of the frag should change. */
18017 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18019 if (RELAX_BRANCH_P (fragp->fr_subtype))
18021 offsetT old_var = fragp->fr_var;
18023 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18025 return fragp->fr_var - old_var;
18028 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18030 offsetT old_var = fragp->fr_var;
18031 offsetT new_var = 4;
18033 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18034 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18035 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18036 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18037 fragp->fr_var = new_var;
18039 return new_var - old_var;
18042 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18045 if (mips16_extended_frag (fragp, NULL, stretch))
18047 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18049 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18054 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18056 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18063 /* Convert a machine dependent frag. */
18066 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18068 if (RELAX_BRANCH_P (fragp->fr_subtype))
18071 unsigned long insn;
18075 buf = fragp->fr_literal + fragp->fr_fix;
18076 insn = read_insn (buf);
18078 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18080 /* We generate a fixup instead of applying it right now
18081 because, if there are linker relaxations, we're going to
18082 need the relocations. */
18083 exp.X_op = O_symbol;
18084 exp.X_add_symbol = fragp->fr_symbol;
18085 exp.X_add_number = fragp->fr_offset;
18087 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18088 BFD_RELOC_16_PCREL_S2);
18089 fixp->fx_file = fragp->fr_file;
18090 fixp->fx_line = fragp->fr_line;
18092 buf = write_insn (buf, insn);
18098 as_warn_where (fragp->fr_file, fragp->fr_line,
18099 _("Relaxed out-of-range branch into a jump"));
18101 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18104 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18106 /* Reverse the branch. */
18107 switch ((insn >> 28) & 0xf)
18110 /* bc[0-3][tf]l? instructions can have the condition
18111 reversed by tweaking a single TF bit, and their
18112 opcodes all have 0x4???????. */
18113 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18114 insn ^= 0x00010000;
18118 /* bltz 0x04000000 bgez 0x04010000
18119 bltzal 0x04100000 bgezal 0x04110000 */
18120 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18121 insn ^= 0x00010000;
18125 /* beq 0x10000000 bne 0x14000000
18126 blez 0x18000000 bgtz 0x1c000000 */
18127 insn ^= 0x04000000;
18135 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18137 /* Clear the and-link bit. */
18138 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18140 /* bltzal 0x04100000 bgezal 0x04110000
18141 bltzall 0x04120000 bgezall 0x04130000 */
18142 insn &= ~0x00100000;
18145 /* Branch over the branch (if the branch was likely) or the
18146 full jump (not likely case). Compute the offset from the
18147 current instruction to branch to. */
18148 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18152 /* How many bytes in instructions we've already emitted? */
18153 i = buf - fragp->fr_literal - fragp->fr_fix;
18154 /* How many bytes in instructions from here to the end? */
18155 i = fragp->fr_var - i;
18157 /* Convert to instruction count. */
18159 /* Branch counts from the next instruction. */
18162 /* Branch over the jump. */
18163 buf = write_insn (buf, insn);
18166 buf = write_insn (buf, 0);
18168 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18170 /* beql $0, $0, 2f */
18172 /* Compute the PC offset from the current instruction to
18173 the end of the variable frag. */
18174 /* How many bytes in instructions we've already emitted? */
18175 i = buf - fragp->fr_literal - fragp->fr_fix;
18176 /* How many bytes in instructions from here to the end? */
18177 i = fragp->fr_var - i;
18178 /* Convert to instruction count. */
18180 /* Don't decrement i, because we want to branch over the
18184 buf = write_insn (buf, insn);
18185 buf = write_insn (buf, 0);
18189 if (mips_pic == NO_PIC)
18192 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18193 ? 0x0c000000 : 0x08000000);
18194 exp.X_op = O_symbol;
18195 exp.X_add_symbol = fragp->fr_symbol;
18196 exp.X_add_number = fragp->fr_offset;
18198 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18199 FALSE, BFD_RELOC_MIPS_JMP);
18200 fixp->fx_file = fragp->fr_file;
18201 fixp->fx_line = fragp->fr_line;
18203 buf = write_insn (buf, insn);
18207 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18209 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18210 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18211 insn |= at << OP_SH_RT;
18212 exp.X_op = O_symbol;
18213 exp.X_add_symbol = fragp->fr_symbol;
18214 exp.X_add_number = fragp->fr_offset;
18216 if (fragp->fr_offset)
18218 exp.X_add_symbol = make_expr_symbol (&exp);
18219 exp.X_add_number = 0;
18222 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18223 FALSE, BFD_RELOC_MIPS_GOT16);
18224 fixp->fx_file = fragp->fr_file;
18225 fixp->fx_line = fragp->fr_line;
18227 buf = write_insn (buf, insn);
18229 if (mips_opts.isa == ISA_MIPS1)
18231 buf = write_insn (buf, 0);
18233 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18234 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18235 insn |= at << OP_SH_RS | at << OP_SH_RT;
18237 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18238 FALSE, BFD_RELOC_LO16);
18239 fixp->fx_file = fragp->fr_file;
18240 fixp->fx_line = fragp->fr_line;
18242 buf = write_insn (buf, insn);
18245 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18249 insn |= at << OP_SH_RS;
18251 buf = write_insn (buf, insn);
18255 fragp->fr_fix += fragp->fr_var;
18256 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18260 /* Relax microMIPS branches. */
18261 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18263 char *buf = fragp->fr_literal + fragp->fr_fix;
18264 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18265 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18266 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18267 bfd_boolean short_ds;
18268 unsigned long insn;
18272 exp.X_op = O_symbol;
18273 exp.X_add_symbol = fragp->fr_symbol;
18274 exp.X_add_number = fragp->fr_offset;
18276 fragp->fr_fix += fragp->fr_var;
18278 /* Handle 16-bit branches that fit or are forced to fit. */
18279 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18281 /* We generate a fixup instead of applying it right now,
18282 because if there is linker relaxation, we're going to
18283 need the relocations. */
18285 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18286 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18287 else if (type == 'E')
18288 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18289 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18293 fixp->fx_file = fragp->fr_file;
18294 fixp->fx_line = fragp->fr_line;
18296 /* These relocations can have an addend that won't fit in
18298 fixp->fx_no_overflow = 1;
18303 /* Handle 32-bit branches that fit or are forced to fit. */
18304 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18305 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18307 /* We generate a fixup instead of applying it right now,
18308 because if there is linker relaxation, we're going to
18309 need the relocations. */
18310 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18311 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18312 fixp->fx_file = fragp->fr_file;
18313 fixp->fx_line = fragp->fr_line;
18319 /* Relax 16-bit branches to 32-bit branches. */
18322 insn = read_compressed_insn (buf, 2);
18324 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18325 insn = 0x94000000; /* beq */
18326 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18328 unsigned long regno;
18330 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18331 regno = micromips_to_32_reg_d_map [regno];
18332 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18333 insn |= regno << MICROMIPSOP_SH_RS;
18338 /* Nothing else to do, just write it out. */
18339 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18340 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18342 buf = write_compressed_insn (buf, insn, 4);
18343 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18348 insn = read_compressed_insn (buf, 4);
18350 /* Relax 32-bit branches to a sequence of instructions. */
18351 as_warn_where (fragp->fr_file, fragp->fr_line,
18352 _("Relaxed out-of-range branch into a jump"));
18354 /* Set the short-delay-slot bit. */
18355 short_ds = al && (insn & 0x02000000) != 0;
18357 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18361 /* Reverse the branch. */
18362 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18363 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18364 insn ^= 0x20000000;
18365 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18366 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18367 || (insn & 0xffe00000) == 0x40800000 /* blez */
18368 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18369 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18370 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18371 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18372 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18373 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18374 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18375 insn ^= 0x00400000;
18376 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18377 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18378 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18379 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18380 insn ^= 0x00200000;
18386 /* Clear the and-link and short-delay-slot bits. */
18387 gas_assert ((insn & 0xfda00000) == 0x40200000);
18389 /* bltzal 0x40200000 bgezal 0x40600000 */
18390 /* bltzals 0x42200000 bgezals 0x42600000 */
18391 insn &= ~0x02200000;
18394 /* Make a label at the end for use with the branch. */
18395 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18396 micromips_label_inc ();
18397 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18400 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18401 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18402 fixp->fx_file = fragp->fr_file;
18403 fixp->fx_line = fragp->fr_line;
18405 /* Branch over the jump. */
18406 buf = write_compressed_insn (buf, insn, 4);
18409 buf = write_compressed_insn (buf, 0x0c00, 2);
18412 if (mips_pic == NO_PIC)
18414 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18416 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18417 insn = al ? jal : 0xd4000000;
18419 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18420 BFD_RELOC_MICROMIPS_JMP);
18421 fixp->fx_file = fragp->fr_file;
18422 fixp->fx_line = fragp->fr_line;
18424 buf = write_compressed_insn (buf, insn, 4);
18427 buf = write_compressed_insn (buf, 0x0c00, 2);
18431 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18432 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18433 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18435 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18436 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18437 insn |= at << MICROMIPSOP_SH_RT;
18439 if (exp.X_add_number)
18441 exp.X_add_symbol = make_expr_symbol (&exp);
18442 exp.X_add_number = 0;
18445 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18446 BFD_RELOC_MICROMIPS_GOT16);
18447 fixp->fx_file = fragp->fr_file;
18448 fixp->fx_line = fragp->fr_line;
18450 buf = write_compressed_insn (buf, insn, 4);
18452 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18453 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18454 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18456 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18457 BFD_RELOC_MICROMIPS_LO16);
18458 fixp->fx_file = fragp->fr_file;
18459 fixp->fx_line = fragp->fr_line;
18461 buf = write_compressed_insn (buf, insn, 4);
18463 /* jr/jrc/jalr/jalrs $at */
18464 insn = al ? jalr : jr;
18465 insn |= at << MICROMIPSOP_SH_MJ;
18467 buf = write_compressed_insn (buf, insn, 2);
18470 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18474 if (RELAX_MIPS16_P (fragp->fr_subtype))
18477 const struct mips16_immed_operand *op;
18480 unsigned int user_length, length;
18481 unsigned long insn;
18484 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18485 op = mips16_immed_operands;
18486 while (op->type != type)
18489 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18490 val = resolve_symbol_value (fragp->fr_symbol);
18495 addr = fragp->fr_address + fragp->fr_fix;
18497 /* The rules for the base address of a PC relative reloc are
18498 complicated; see mips16_extended_frag. */
18499 if (type == 'p' || type == 'q')
18504 /* Ignore the low bit in the target, since it will be
18505 set for a text label. */
18506 if ((val & 1) != 0)
18509 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18511 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18514 addr &= ~ (addressT) ((1 << op->shift) - 1);
18517 /* Make sure the section winds up with the alignment we have
18520 record_alignment (asec, op->shift);
18524 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18525 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18526 as_warn_where (fragp->fr_file, fragp->fr_line,
18527 _("extended instruction in delay slot"));
18529 buf = fragp->fr_literal + fragp->fr_fix;
18531 insn = read_compressed_insn (buf, 2);
18533 insn |= MIPS16_EXTEND;
18535 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18537 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18542 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18543 BFD_RELOC_UNUSED, val, user_length, &insn);
18545 length = (ext ? 4 : 2);
18546 gas_assert (mips16_opcode_length (insn) == length);
18547 write_compressed_insn (buf, insn, length);
18548 fragp->fr_fix += length;
18552 relax_substateT subtype = fragp->fr_subtype;
18553 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18554 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18558 first = RELAX_FIRST (subtype);
18559 second = RELAX_SECOND (subtype);
18560 fixp = (fixS *) fragp->fr_opcode;
18562 /* If the delay slot chosen does not match the size of the instruction,
18563 then emit a warning. */
18564 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18565 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18570 s = subtype & (RELAX_DELAY_SLOT_16BIT
18571 | RELAX_DELAY_SLOT_SIZE_FIRST
18572 | RELAX_DELAY_SLOT_SIZE_SECOND);
18573 msg = macro_warning (s);
18575 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18579 /* Possibly emit a warning if we've chosen the longer option. */
18580 if (use_second == second_longer)
18586 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18587 msg = macro_warning (s);
18589 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18593 /* Go through all the fixups for the first sequence. Disable them
18594 (by marking them as done) if we're going to use the second
18595 sequence instead. */
18597 && fixp->fx_frag == fragp
18598 && fixp->fx_where < fragp->fr_fix - second)
18600 if (subtype & RELAX_USE_SECOND)
18602 fixp = fixp->fx_next;
18605 /* Go through the fixups for the second sequence. Disable them if
18606 we're going to use the first sequence, otherwise adjust their
18607 addresses to account for the relaxation. */
18608 while (fixp && fixp->fx_frag == fragp)
18610 if (subtype & RELAX_USE_SECOND)
18611 fixp->fx_where -= first;
18614 fixp = fixp->fx_next;
18617 /* Now modify the frag contents. */
18618 if (subtype & RELAX_USE_SECOND)
18622 start = fragp->fr_literal + fragp->fr_fix - first - second;
18623 memmove (start, start + first, second);
18624 fragp->fr_fix -= first;
18627 fragp->fr_fix -= second;
18631 /* This function is called after the relocs have been generated.
18632 We've been storing mips16 text labels as odd. Here we convert them
18633 back to even for the convenience of the debugger. */
18636 mips_frob_file_after_relocs (void)
18639 unsigned int count, i;
18641 syms = bfd_get_outsymbols (stdoutput);
18642 count = bfd_get_symcount (stdoutput);
18643 for (i = 0; i < count; i++, syms++)
18644 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18645 && ((*syms)->value & 1) != 0)
18647 (*syms)->value &= ~1;
18648 /* If the symbol has an odd size, it was probably computed
18649 incorrectly, so adjust that as well. */
18650 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18651 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18655 /* This function is called whenever a label is defined, including fake
18656 labels instantiated off the dot special symbol. It is used when
18657 handling branch delays; if a branch has a label, we assume we cannot
18658 move it. This also bumps the value of the symbol by 1 in compressed
18662 mips_record_label (symbolS *sym)
18664 segment_info_type *si = seg_info (now_seg);
18665 struct insn_label_list *l;
18667 if (free_insn_labels == NULL)
18668 l = (struct insn_label_list *) xmalloc (sizeof *l);
18671 l = free_insn_labels;
18672 free_insn_labels = l->next;
18676 l->next = si->label_list;
18677 si->label_list = l;
18680 /* This function is called as tc_frob_label() whenever a label is defined
18681 and adds a DWARF-2 record we only want for true labels. */
18684 mips_define_label (symbolS *sym)
18686 mips_record_label (sym);
18687 dwarf2_emit_label (sym);
18690 /* This function is called by tc_new_dot_label whenever a new dot symbol
18694 mips_add_dot_label (symbolS *sym)
18696 mips_record_label (sym);
18697 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18698 mips_compressed_mark_label (sym);
18701 /* Some special processing for a MIPS ELF file. */
18704 mips_elf_final_processing (void)
18706 /* Write out the register information. */
18707 if (mips_abi != N64_ABI)
18711 s.ri_gprmask = mips_gprmask;
18712 s.ri_cprmask[0] = mips_cprmask[0];
18713 s.ri_cprmask[1] = mips_cprmask[1];
18714 s.ri_cprmask[2] = mips_cprmask[2];
18715 s.ri_cprmask[3] = mips_cprmask[3];
18716 /* The gp_value field is set by the MIPS ELF backend. */
18718 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18719 ((Elf32_External_RegInfo *)
18720 mips_regmask_frag));
18724 Elf64_Internal_RegInfo s;
18726 s.ri_gprmask = mips_gprmask;
18728 s.ri_cprmask[0] = mips_cprmask[0];
18729 s.ri_cprmask[1] = mips_cprmask[1];
18730 s.ri_cprmask[2] = mips_cprmask[2];
18731 s.ri_cprmask[3] = mips_cprmask[3];
18732 /* The gp_value field is set by the MIPS ELF backend. */
18734 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18735 ((Elf64_External_RegInfo *)
18736 mips_regmask_frag));
18739 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18740 sort of BFD interface for this. */
18741 if (mips_any_noreorder)
18742 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18743 if (mips_pic != NO_PIC)
18745 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18746 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18749 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18751 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18752 defined at present; this might need to change in future. */
18753 if (file_ase_mips16)
18754 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18755 if (file_ase_micromips)
18756 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18757 if (file_ase & ASE_MDMX)
18758 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18760 /* Set the MIPS ELF ABI flags. */
18761 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18762 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18763 else if (mips_abi == O64_ABI)
18764 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18765 else if (mips_abi == EABI_ABI)
18767 if (!file_mips_gp32)
18768 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18770 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18772 else if (mips_abi == N32_ABI)
18773 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18775 /* Nothing to do for N64_ABI. */
18777 if (mips_32bitmode)
18778 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18780 if (mips_flag_nan2008)
18781 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18783 #if 0 /* XXX FIXME */
18784 /* 32 bit code with 64 bit FP registers. */
18785 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18786 elf_elfheader (stdoutput)->e_flags |= ???;
18790 typedef struct proc {
18792 symbolS *func_end_sym;
18793 unsigned long reg_mask;
18794 unsigned long reg_offset;
18795 unsigned long fpreg_mask;
18796 unsigned long fpreg_offset;
18797 unsigned long frame_offset;
18798 unsigned long frame_reg;
18799 unsigned long pc_reg;
18802 static procS cur_proc;
18803 static procS *cur_proc_ptr;
18804 static int numprocs;
18806 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18807 as "2", and a normal nop as "0". */
18809 #define NOP_OPCODE_MIPS 0
18810 #define NOP_OPCODE_MIPS16 1
18811 #define NOP_OPCODE_MICROMIPS 2
18814 mips_nop_opcode (void)
18816 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18817 return NOP_OPCODE_MICROMIPS;
18818 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18819 return NOP_OPCODE_MIPS16;
18821 return NOP_OPCODE_MIPS;
18824 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18825 32-bit microMIPS NOPs here (if applicable). */
18828 mips_handle_align (fragS *fragp)
18832 int bytes, size, excess;
18835 if (fragp->fr_type != rs_align_code)
18838 p = fragp->fr_literal + fragp->fr_fix;
18840 switch (nop_opcode)
18842 case NOP_OPCODE_MICROMIPS:
18843 opcode = micromips_nop32_insn.insn_opcode;
18846 case NOP_OPCODE_MIPS16:
18847 opcode = mips16_nop_insn.insn_opcode;
18850 case NOP_OPCODE_MIPS:
18852 opcode = nop_insn.insn_opcode;
18857 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18858 excess = bytes % size;
18860 /* Handle the leading part if we're not inserting a whole number of
18861 instructions, and make it the end of the fixed part of the frag.
18862 Try to fit in a short microMIPS NOP if applicable and possible,
18863 and use zeroes otherwise. */
18864 gas_assert (excess < 4);
18865 fragp->fr_fix += excess;
18870 /* Fall through. */
18872 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18874 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18878 /* Fall through. */
18881 /* Fall through. */
18886 md_number_to_chars (p, opcode, size);
18887 fragp->fr_var = size;
18891 md_obj_begin (void)
18898 /* Check for premature end, nesting errors, etc. */
18900 as_warn (_("missing .end at end of assembly"));
18909 if (*input_line_pointer == '-')
18911 ++input_line_pointer;
18914 if (!ISDIGIT (*input_line_pointer))
18915 as_bad (_("expected simple number"));
18916 if (input_line_pointer[0] == '0')
18918 if (input_line_pointer[1] == 'x')
18920 input_line_pointer += 2;
18921 while (ISXDIGIT (*input_line_pointer))
18924 val |= hex_value (*input_line_pointer++);
18926 return negative ? -val : val;
18930 ++input_line_pointer;
18931 while (ISDIGIT (*input_line_pointer))
18934 val |= *input_line_pointer++ - '0';
18936 return negative ? -val : val;
18939 if (!ISDIGIT (*input_line_pointer))
18941 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18942 *input_line_pointer, *input_line_pointer);
18943 as_warn (_("invalid number"));
18946 while (ISDIGIT (*input_line_pointer))
18949 val += *input_line_pointer++ - '0';
18951 return negative ? -val : val;
18954 /* The .file directive; just like the usual .file directive, but there
18955 is an initial number which is the ECOFF file index. In the non-ECOFF
18956 case .file implies DWARF-2. */
18959 s_mips_file (int x ATTRIBUTE_UNUSED)
18961 static int first_file_directive = 0;
18963 if (ECOFF_DEBUGGING)
18972 filename = dwarf2_directive_file (0);
18974 /* Versions of GCC up to 3.1 start files with a ".file"
18975 directive even for stabs output. Make sure that this
18976 ".file" is handled. Note that you need a version of GCC
18977 after 3.1 in order to support DWARF-2 on MIPS. */
18978 if (filename != NULL && ! first_file_directive)
18980 (void) new_logical_line (filename, -1);
18981 s_app_file_string (filename, 0);
18983 first_file_directive = 1;
18987 /* The .loc directive, implying DWARF-2. */
18990 s_mips_loc (int x ATTRIBUTE_UNUSED)
18992 if (!ECOFF_DEBUGGING)
18993 dwarf2_directive_loc (0);
18996 /* The .end directive. */
18999 s_mips_end (int x ATTRIBUTE_UNUSED)
19003 /* Following functions need their own .frame and .cprestore directives. */
19004 mips_frame_reg_valid = 0;
19005 mips_cprestore_valid = 0;
19007 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19010 demand_empty_rest_of_line ();
19015 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19016 as_warn (_(".end not in text section"));
19020 as_warn (_(".end directive without a preceding .ent directive."));
19021 demand_empty_rest_of_line ();
19027 gas_assert (S_GET_NAME (p));
19028 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19029 as_warn (_(".end symbol does not match .ent symbol."));
19031 if (debug_type == DEBUG_STABS)
19032 stabs_generate_asm_endfunc (S_GET_NAME (p),
19036 as_warn (_(".end directive missing or unknown symbol"));
19038 /* Create an expression to calculate the size of the function. */
19039 if (p && cur_proc_ptr)
19041 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19042 expressionS *exp = xmalloc (sizeof (expressionS));
19045 exp->X_op = O_subtract;
19046 exp->X_add_symbol = symbol_temp_new_now ();
19047 exp->X_op_symbol = p;
19048 exp->X_add_number = 0;
19050 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19053 /* Generate a .pdr section. */
19054 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19056 segT saved_seg = now_seg;
19057 subsegT saved_subseg = now_subseg;
19061 #ifdef md_flush_pending_output
19062 md_flush_pending_output ();
19065 gas_assert (pdr_seg);
19066 subseg_set (pdr_seg, 0);
19068 /* Write the symbol. */
19069 exp.X_op = O_symbol;
19070 exp.X_add_symbol = p;
19071 exp.X_add_number = 0;
19072 emit_expr (&exp, 4);
19074 fragp = frag_more (7 * 4);
19076 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19077 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19078 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19079 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19080 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19081 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19082 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19084 subseg_set (saved_seg, saved_subseg);
19087 cur_proc_ptr = NULL;
19090 /* The .aent and .ent directives. */
19093 s_mips_ent (int aent)
19097 symbolP = get_symbol ();
19098 if (*input_line_pointer == ',')
19099 ++input_line_pointer;
19100 SKIP_WHITESPACE ();
19101 if (ISDIGIT (*input_line_pointer)
19102 || *input_line_pointer == '-')
19105 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19106 as_warn (_(".ent or .aent not in text section."));
19108 if (!aent && cur_proc_ptr)
19109 as_warn (_("missing .end"));
19113 /* This function needs its own .frame and .cprestore directives. */
19114 mips_frame_reg_valid = 0;
19115 mips_cprestore_valid = 0;
19117 cur_proc_ptr = &cur_proc;
19118 memset (cur_proc_ptr, '\0', sizeof (procS));
19120 cur_proc_ptr->func_sym = symbolP;
19124 if (debug_type == DEBUG_STABS)
19125 stabs_generate_asm_func (S_GET_NAME (symbolP),
19126 S_GET_NAME (symbolP));
19129 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19131 demand_empty_rest_of_line ();
19134 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19135 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19136 s_mips_frame is used so that we can set the PDR information correctly.
19137 We can't use the ecoff routines because they make reference to the ecoff
19138 symbol table (in the mdebug section). */
19141 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19143 if (ECOFF_DEBUGGING)
19149 if (cur_proc_ptr == (procS *) NULL)
19151 as_warn (_(".frame outside of .ent"));
19152 demand_empty_rest_of_line ();
19156 cur_proc_ptr->frame_reg = tc_get_register (1);
19158 SKIP_WHITESPACE ();
19159 if (*input_line_pointer++ != ','
19160 || get_absolute_expression_and_terminator (&val) != ',')
19162 as_warn (_("Bad .frame directive"));
19163 --input_line_pointer;
19164 demand_empty_rest_of_line ();
19168 cur_proc_ptr->frame_offset = val;
19169 cur_proc_ptr->pc_reg = tc_get_register (0);
19171 demand_empty_rest_of_line ();
19175 /* The .fmask and .mask directives. If the mdebug section is present
19176 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19177 embedded targets, s_mips_mask is used so that we can set the PDR
19178 information correctly. We can't use the ecoff routines because they
19179 make reference to the ecoff symbol table (in the mdebug section). */
19182 s_mips_mask (int reg_type)
19184 if (ECOFF_DEBUGGING)
19185 s_ignore (reg_type);
19190 if (cur_proc_ptr == (procS *) NULL)
19192 as_warn (_(".mask/.fmask outside of .ent"));
19193 demand_empty_rest_of_line ();
19197 if (get_absolute_expression_and_terminator (&mask) != ',')
19199 as_warn (_("Bad .mask/.fmask directive"));
19200 --input_line_pointer;
19201 demand_empty_rest_of_line ();
19205 off = get_absolute_expression ();
19207 if (reg_type == 'F')
19209 cur_proc_ptr->fpreg_mask = mask;
19210 cur_proc_ptr->fpreg_offset = off;
19214 cur_proc_ptr->reg_mask = mask;
19215 cur_proc_ptr->reg_offset = off;
19218 demand_empty_rest_of_line ();
19222 /* A table describing all the processors gas knows about. Names are
19223 matched in the order listed.
19225 To ease comparison, please keep this table in the same order as
19226 gcc's mips_cpu_info_table[]. */
19227 static const struct mips_cpu_info mips_cpu_info_table[] =
19229 /* Entries for generic ISAs */
19230 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19231 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19232 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19233 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19234 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19235 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19236 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19237 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19238 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19241 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19242 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19243 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19246 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19249 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19250 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19251 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19252 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19253 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19254 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19255 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19256 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19257 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19258 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19259 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19260 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19261 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19262 /* ST Microelectronics Loongson 2E and 2F cores */
19263 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19264 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19267 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19268 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19269 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19270 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19271 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19272 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19273 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19274 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19275 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19276 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19277 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19278 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19279 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19280 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19281 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19284 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19285 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19286 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19287 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19289 /* MIPS 32 Release 2 */
19290 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19291 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19292 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19293 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19294 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19295 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19296 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19297 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19298 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19299 ISA_MIPS32R2, CPU_MIPS32R2 },
19300 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19301 ISA_MIPS32R2, CPU_MIPS32R2 },
19302 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19303 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19304 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19305 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19306 /* Deprecated forms of the above. */
19307 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19308 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19309 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19310 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19311 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19312 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19313 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19314 /* Deprecated forms of the above. */
19315 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19316 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19317 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19318 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19319 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19320 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19321 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19322 /* Deprecated forms of the above. */
19323 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19324 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19325 /* 34Kn is a 34kc without DSP. */
19326 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19327 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19328 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19329 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19330 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19331 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19332 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19333 /* Deprecated forms of the above. */
19334 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19335 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19336 /* 1004K cores are multiprocessor versions of the 34K. */
19337 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19338 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19339 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19340 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19343 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19344 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19345 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19346 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19348 /* Broadcom SB-1 CPU core */
19349 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19350 /* Broadcom SB-1A CPU core */
19351 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19353 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
19355 /* MIPS 64 Release 2 */
19357 /* Cavium Networks Octeon CPU core */
19358 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19359 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19360 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19363 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19366 XLP is mostly like XLR, with the prominent exception that it is
19367 MIPS64R2 rather than MIPS64. */
19368 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19371 { NULL, 0, 0, 0, 0 }
19375 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19376 with a final "000" replaced by "k". Ignore case.
19378 Note: this function is shared between GCC and GAS. */
19381 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19383 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19384 given++, canonical++;
19386 return ((*given == 0 && *canonical == 0)
19387 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19391 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19392 CPU name. We've traditionally allowed a lot of variation here.
19394 Note: this function is shared between GCC and GAS. */
19397 mips_matching_cpu_name_p (const char *canonical, const char *given)
19399 /* First see if the name matches exactly, or with a final "000"
19400 turned into "k". */
19401 if (mips_strict_matching_cpu_name_p (canonical, given))
19404 /* If not, try comparing based on numerical designation alone.
19405 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19406 if (TOLOWER (*given) == 'r')
19408 if (!ISDIGIT (*given))
19411 /* Skip over some well-known prefixes in the canonical name,
19412 hoping to find a number there too. */
19413 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19415 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19417 else if (TOLOWER (canonical[0]) == 'r')
19420 return mips_strict_matching_cpu_name_p (canonical, given);
19424 /* Parse an option that takes the name of a processor as its argument.
19425 OPTION is the name of the option and CPU_STRING is the argument.
19426 Return the corresponding processor enumeration if the CPU_STRING is
19427 recognized, otherwise report an error and return null.
19429 A similar function exists in GCC. */
19431 static const struct mips_cpu_info *
19432 mips_parse_cpu (const char *option, const char *cpu_string)
19434 const struct mips_cpu_info *p;
19436 /* 'from-abi' selects the most compatible architecture for the given
19437 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19438 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19439 version. Look first at the -mgp options, if given, otherwise base
19440 the choice on MIPS_DEFAULT_64BIT.
19442 Treat NO_ABI like the EABIs. One reason to do this is that the
19443 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19444 architecture. This code picks MIPS I for 'mips' and MIPS III for
19445 'mips64', just as we did in the days before 'from-abi'. */
19446 if (strcasecmp (cpu_string, "from-abi") == 0)
19448 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19449 return mips_cpu_info_from_isa (ISA_MIPS1);
19451 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19452 return mips_cpu_info_from_isa (ISA_MIPS3);
19454 if (file_mips_gp32 >= 0)
19455 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19457 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19462 /* 'default' has traditionally been a no-op. Probably not very useful. */
19463 if (strcasecmp (cpu_string, "default") == 0)
19466 for (p = mips_cpu_info_table; p->name != 0; p++)
19467 if (mips_matching_cpu_name_p (p->name, cpu_string))
19470 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19474 /* Return the canonical processor information for ISA (a member of the
19475 ISA_MIPS* enumeration). */
19477 static const struct mips_cpu_info *
19478 mips_cpu_info_from_isa (int isa)
19482 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19483 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19484 && isa == mips_cpu_info_table[i].isa)
19485 return (&mips_cpu_info_table[i]);
19490 static const struct mips_cpu_info *
19491 mips_cpu_info_from_arch (int arch)
19495 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19496 if (arch == mips_cpu_info_table[i].cpu)
19497 return (&mips_cpu_info_table[i]);
19503 show (FILE *stream, const char *string, int *col_p, int *first_p)
19507 fprintf (stream, "%24s", "");
19512 fprintf (stream, ", ");
19516 if (*col_p + strlen (string) > 72)
19518 fprintf (stream, "\n%24s", "");
19522 fprintf (stream, "%s", string);
19523 *col_p += strlen (string);
19529 md_show_usage (FILE *stream)
19534 fprintf (stream, _("\
19536 -EB generate big endian output\n\
19537 -EL generate little endian output\n\
19538 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19539 -G NUM allow referencing objects up to NUM bytes\n\
19540 implicitly with the gp register [default 8]\n"));
19541 fprintf (stream, _("\
19542 -mips1 generate MIPS ISA I instructions\n\
19543 -mips2 generate MIPS ISA II instructions\n\
19544 -mips3 generate MIPS ISA III instructions\n\
19545 -mips4 generate MIPS ISA IV instructions\n\
19546 -mips5 generate MIPS ISA V instructions\n\
19547 -mips32 generate MIPS32 ISA instructions\n\
19548 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19549 -mips64 generate MIPS64 ISA instructions\n\
19550 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19551 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19555 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19556 show (stream, mips_cpu_info_table[i].name, &column, &first);
19557 show (stream, "from-abi", &column, &first);
19558 fputc ('\n', stream);
19560 fprintf (stream, _("\
19561 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19562 -no-mCPU don't generate code specific to CPU.\n\
19563 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19567 show (stream, "3900", &column, &first);
19568 show (stream, "4010", &column, &first);
19569 show (stream, "4100", &column, &first);
19570 show (stream, "4650", &column, &first);
19571 fputc ('\n', stream);
19573 fprintf (stream, _("\
19574 -mips16 generate mips16 instructions\n\
19575 -no-mips16 do not generate mips16 instructions\n"));
19576 fprintf (stream, _("\
19577 -mmicromips generate microMIPS instructions\n\
19578 -mno-micromips do not generate microMIPS instructions\n"));
19579 fprintf (stream, _("\
19580 -msmartmips generate smartmips instructions\n\
19581 -mno-smartmips do not generate smartmips instructions\n"));
19582 fprintf (stream, _("\
19583 -mdsp generate DSP instructions\n\
19584 -mno-dsp do not generate DSP instructions\n"));
19585 fprintf (stream, _("\
19586 -mdspr2 generate DSP R2 instructions\n\
19587 -mno-dspr2 do not generate DSP R2 instructions\n"));
19588 fprintf (stream, _("\
19589 -mmt generate MT instructions\n\
19590 -mno-mt do not generate MT instructions\n"));
19591 fprintf (stream, _("\
19592 -mmcu generate MCU instructions\n\
19593 -mno-mcu do not generate MCU instructions\n"));
19594 fprintf (stream, _("\
19595 -mvirt generate Virtualization instructions\n\
19596 -mno-virt do not generate Virtualization instructions\n"));
19597 fprintf (stream, _("\
19598 -minsn32 only generate 32-bit microMIPS instructions\n\
19599 -mno-insn32 generate all microMIPS instructions\n"));
19600 fprintf (stream, _("\
19601 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19602 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19603 -mfix-vr4120 work around certain VR4120 errata\n\
19604 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19605 -mfix-24k insert a nop after ERET and DERET instructions\n\
19606 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19607 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19608 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19609 -msym32 assume all symbols have 32-bit values\n\
19610 -O0 remove unneeded NOPs, do not swap branches\n\
19611 -O remove unneeded NOPs and swap branches\n\
19612 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19613 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19614 fprintf (stream, _("\
19615 -mhard-float allow floating-point instructions\n\
19616 -msoft-float do not allow floating-point instructions\n\
19617 -msingle-float only allow 32-bit floating-point operations\n\
19618 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19619 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19620 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19621 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19625 show (stream, "legacy", &column, &first);
19626 show (stream, "2008", &column, &first);
19628 fputc ('\n', stream);
19630 fprintf (stream, _("\
19631 -KPIC, -call_shared generate SVR4 position independent code\n\
19632 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19633 -mvxworks-pic generate VxWorks position independent code\n\
19634 -non_shared do not generate code that can operate with DSOs\n\
19635 -xgot assume a 32 bit GOT\n\
19636 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19637 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19638 position dependent (non shared) code\n\
19639 -mabi=ABI create ABI conformant object file for:\n"));
19643 show (stream, "32", &column, &first);
19644 show (stream, "o64", &column, &first);
19645 show (stream, "n32", &column, &first);
19646 show (stream, "64", &column, &first);
19647 show (stream, "eabi", &column, &first);
19649 fputc ('\n', stream);
19651 fprintf (stream, _("\
19652 -32 create o32 ABI object file (default)\n\
19653 -n32 create n32 ABI object file\n\
19654 -64 create 64 ABI object file\n"));
19659 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19661 if (HAVE_64BIT_SYMBOLS)
19662 return dwarf2_format_64bit_irix;
19664 return dwarf2_format_32bit;
19669 mips_dwarf2_addr_size (void)
19671 if (HAVE_64BIT_OBJECTS)
19677 /* Standard calling conventions leave the CFA at SP on entry. */
19679 mips_cfi_frame_initial_instructions (void)
19681 cfi_add_CFA_def_cfa_register (SP);
19685 tc_mips_regname_to_dw2regnum (char *regname)
19687 unsigned int regnum = -1;
19690 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))