1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* Some ISA's have delay slots for instructions which read or write
241 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
242 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
243 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
244 delay slot in this ISA. The uses of this macro assume that any
245 ISA that has delay slots for one of these, has them for all. They
246 also assume that ISAs which don't have delays for these insns, don't
247 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
248 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
250 || (ISA) == ISA_MIPS2 \
251 || (ISA) == ISA_MIPS3 \
254 /* True if the given ABI requires 32-bit registers. */
255 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
257 /* Likewise 64-bit registers. */
258 #define ABI_NEEDS_64BIT_REGS(ABI) \
260 || (ABI) == N64_ABI \
263 /* Return true if ISA supports 64 bit gp register instructions. */
264 #define ISA_HAS_64BIT_REGS(ISA) ( \
266 || (ISA) == ISA_MIPS4 \
267 || (ISA) == ISA_MIPS5 \
268 || (ISA) == ISA_MIPS64 \
271 /* Return true if ISA supports 64-bit right rotate (dror et al.)
273 #define ISA_HAS_DROR(ISA) ( \
277 /* Return true if ISA supports 32-bit right rotate (ror et al.)
279 #define ISA_HAS_ROR(ISA) ( \
280 (ISA) == ISA_MIPS32R2 \
283 #define HAVE_32BIT_GPRS \
284 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
286 #define HAVE_32BIT_FPRS \
287 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
289 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
290 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
292 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
294 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
296 /* We can only have 64bit addresses if the object file format
298 #define HAVE_32BIT_ADDRESSES \
300 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
301 || ! HAVE_64BIT_OBJECTS) \
302 && mips_pic != EMBEDDED_PIC))
304 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
306 /* Addresses are loaded in different ways, depending on the address size
307 in use. The n32 ABI Documentation also mandates the use of additions
308 with overflow checking, but existing implementations don't follow it. */
309 #define ADDRESS_ADD_INSN \
310 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
312 #define ADDRESS_ADDI_INSN \
313 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
315 #define ADDRESS_LOAD_INSN \
316 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
318 #define ADDRESS_STORE_INSN \
319 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
321 /* Return true if the given CPU supports the MIPS16 ASE. */
322 #define CPU_HAS_MIPS16(cpu) \
323 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
324 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
326 /* Return true if the given CPU supports the MIPS3D ASE. */
327 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
330 /* Return true if the given CPU supports the MDMX ASE. */
331 #define CPU_HAS_MDMX(cpu) (FALSE \
334 /* True if CPU has a dror instruction. */
335 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
337 /* True if CPU has a ror instruction. */
338 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
340 /* Whether the processor uses hardware interlocks to protect
341 reads from the HI and LO registers, and thus does not
342 require nops to be inserted. */
344 #define hilo_interlocks (mips_opts.arch == CPU_R4010 \
345 || mips_opts.arch == CPU_VR5500 \
346 || mips_opts.arch == CPU_RM7000 \
347 || mips_opts.arch == CPU_SB1 \
350 /* Whether the processor uses hardware interlocks to protect reads
351 from the GPRs, and thus does not require nops to be inserted. */
352 #define gpr_interlocks \
353 (mips_opts.isa != ISA_MIPS1 \
354 || mips_opts.arch == CPU_VR5400 \
355 || mips_opts.arch == CPU_VR5500 \
356 || mips_opts.arch == CPU_R3900)
358 /* As with other "interlocks" this is used by hardware that has FP
359 (co-processor) interlocks. */
360 /* Itbl support may require additional care here. */
361 #define cop_interlocks (mips_opts.arch == CPU_R4300 \
362 || mips_opts.arch == CPU_VR5400 \
363 || mips_opts.arch == CPU_VR5500 \
364 || mips_opts.arch == CPU_SB1 \
367 /* Is this a mfhi or mflo instruction? */
368 #define MF_HILO_INSN(PINFO) \
369 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
371 /* MIPS PIC level. */
373 enum mips_pic_level mips_pic;
375 /* Warn about all NOPS that the assembler generates. */
376 static int warn_nops = 0;
378 /* 1 if we should generate 32 bit offsets from the $gp register in
379 SVR4_PIC mode. Currently has no meaning in other modes. */
380 static int mips_big_got = 0;
382 /* 1 if trap instructions should used for overflow rather than break
384 static int mips_trap = 0;
386 /* 1 if double width floating point constants should not be constructed
387 by assembling two single width halves into two single width floating
388 point registers which just happen to alias the double width destination
389 register. On some architectures this aliasing can be disabled by a bit
390 in the status register, and the setting of this bit cannot be determined
391 automatically at assemble time. */
392 static int mips_disable_float_construction;
394 /* Non-zero if any .set noreorder directives were used. */
396 static int mips_any_noreorder;
398 /* Non-zero if nops should be inserted when the register referenced in
399 an mfhi/mflo instruction is read in the next two instructions. */
400 static int mips_7000_hilo_fix;
402 /* The size of the small data section. */
403 static unsigned int g_switch_value = 8;
404 /* Whether the -G option was used. */
405 static int g_switch_seen = 0;
410 /* If we can determine in advance that GP optimization won't be
411 possible, we can skip the relaxation stuff that tries to produce
412 GP-relative references. This makes delay slot optimization work
415 This function can only provide a guess, but it seems to work for
416 gcc output. It needs to guess right for gcc, otherwise gcc
417 will put what it thinks is a GP-relative instruction in a branch
420 I don't know if a fix is needed for the SVR4_PIC mode. I've only
421 fixed it for the non-PIC mode. KR 95/04/07 */
422 static int nopic_need_relax (symbolS *, int);
424 /* handle of the OPCODE hash table */
425 static struct hash_control *op_hash = NULL;
427 /* The opcode hash table we use for the mips16. */
428 static struct hash_control *mips16_op_hash = NULL;
430 /* This array holds the chars that always start a comment. If the
431 pre-processor is disabled, these aren't very useful */
432 const char comment_chars[] = "#";
434 /* This array holds the chars that only start a comment at the beginning of
435 a line. If the line seems to have the form '# 123 filename'
436 .line and .file directives will appear in the pre-processed output */
437 /* Note that input_file.c hand checks for '#' at the beginning of the
438 first line of the input file. This is because the compiler outputs
439 #NO_APP at the beginning of its output. */
440 /* Also note that C style comments are always supported. */
441 const char line_comment_chars[] = "#";
443 /* This array holds machine specific line separator characters. */
444 const char line_separator_chars[] = ";";
446 /* Chars that can be used to separate mant from exp in floating point nums */
447 const char EXP_CHARS[] = "eE";
449 /* Chars that mean this number is a floating point constant */
452 const char FLT_CHARS[] = "rRsSfFdDxXpP";
454 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
455 changed in read.c . Ideally it shouldn't have to know about it at all,
456 but nothing is ideal around here.
459 static char *insn_error;
461 static int auto_align = 1;
463 /* When outputting SVR4 PIC code, the assembler needs to know the
464 offset in the stack frame from which to restore the $gp register.
465 This is set by the .cprestore pseudo-op, and saved in this
467 static offsetT mips_cprestore_offset = -1;
469 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
470 more optimizations, it can use a register value instead of a memory-saved
471 offset and even an other register than $gp as global pointer. */
472 static offsetT mips_cpreturn_offset = -1;
473 static int mips_cpreturn_register = -1;
474 static int mips_gp_register = GP;
475 static int mips_gprel_offset = 0;
477 /* Whether mips_cprestore_offset has been set in the current function
478 (or whether it has already been warned about, if not). */
479 static int mips_cprestore_valid = 0;
481 /* This is the register which holds the stack frame, as set by the
482 .frame pseudo-op. This is needed to implement .cprestore. */
483 static int mips_frame_reg = SP;
485 /* Whether mips_frame_reg has been set in the current function
486 (or whether it has already been warned about, if not). */
487 static int mips_frame_reg_valid = 0;
489 /* To output NOP instructions correctly, we need to keep information
490 about the previous two instructions. */
492 /* Whether we are optimizing. The default value of 2 means to remove
493 unneeded NOPs and swap branch instructions when possible. A value
494 of 1 means to not swap branches. A value of 0 means to always
496 static int mips_optimize = 2;
498 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
499 equivalent to seeing no -g option at all. */
500 static int mips_debug = 0;
502 /* The previous instruction. */
503 static struct mips_cl_insn prev_insn;
505 /* The instruction before prev_insn. */
506 static struct mips_cl_insn prev_prev_insn;
508 /* If we don't want information for prev_insn or prev_prev_insn, we
509 point the insn_mo field at this dummy integer. */
510 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
512 /* Non-zero if prev_insn is valid. */
513 static int prev_insn_valid;
515 /* The frag for the previous instruction. */
516 static struct frag *prev_insn_frag;
518 /* The offset into prev_insn_frag for the previous instruction. */
519 static long prev_insn_where;
521 /* The reloc type for the previous instruction, if any. */
522 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
524 /* The reloc for the previous instruction, if any. */
525 static fixS *prev_insn_fixp[3];
527 /* Non-zero if the previous instruction was in a delay slot. */
528 static int prev_insn_is_delay_slot;
530 /* Non-zero if the previous instruction was in a .set noreorder. */
531 static int prev_insn_unreordered;
533 /* Non-zero if the previous instruction uses an extend opcode (if
535 static int prev_insn_extended;
537 /* Non-zero if the previous previous instruction was in a .set
539 static int prev_prev_insn_unreordered;
541 /* If this is set, it points to a frag holding nop instructions which
542 were inserted before the start of a noreorder section. If those
543 nops turn out to be unnecessary, the size of the frag can be
545 static fragS *prev_nop_frag;
547 /* The number of nop instructions we created in prev_nop_frag. */
548 static int prev_nop_frag_holds;
550 /* The number of nop instructions that we know we need in
552 static int prev_nop_frag_required;
554 /* The number of instructions we've seen since prev_nop_frag. */
555 static int prev_nop_frag_since;
557 /* For ECOFF and ELF, relocations against symbols are done in two
558 parts, with a HI relocation and a LO relocation. Each relocation
559 has only 16 bits of space to store an addend. This means that in
560 order for the linker to handle carries correctly, it must be able
561 to locate both the HI and the LO relocation. This means that the
562 relocations must appear in order in the relocation table.
564 In order to implement this, we keep track of each unmatched HI
565 relocation. We then sort them so that they immediately precede the
566 corresponding LO relocation. */
571 struct mips_hi_fixup *next;
574 /* The section this fixup is in. */
578 /* The list of unmatched HI relocs. */
580 static struct mips_hi_fixup *mips_hi_fixup_list;
582 /* The frag containing the last explicit relocation operator.
583 Null if explicit relocations have not been used. */
585 static fragS *prev_reloc_op_frag;
587 /* Map normal MIPS register numbers to mips16 register numbers. */
589 #define X ILLEGAL_REG
590 static const int mips32_to_16_reg_map[] =
592 X, X, 2, 3, 4, 5, 6, 7,
593 X, X, X, X, X, X, X, X,
594 0, 1, X, X, X, X, X, X,
595 X, X, X, X, X, X, X, X
599 /* Map mips16 register numbers to normal MIPS register numbers. */
601 static const unsigned int mips16_to_32_reg_map[] =
603 16, 17, 2, 3, 4, 5, 6, 7
606 static int mips_fix_4122_bugs;
608 /* We don't relax branches by default, since this causes us to expand
609 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
610 fail to compute the offset before expanding the macro to the most
611 efficient expansion. */
613 static int mips_relax_branch;
615 /* Since the MIPS does not have multiple forms of PC relative
616 instructions, we do not have to do relaxing as is done on other
617 platforms. However, we do have to handle GP relative addressing
618 correctly, which turns out to be a similar problem.
620 Every macro that refers to a symbol can occur in (at least) two
621 forms, one with GP relative addressing and one without. For
622 example, loading a global variable into a register generally uses
623 a macro instruction like this:
625 If i can be addressed off the GP register (this is true if it is in
626 the .sbss or .sdata section, or if it is known to be smaller than
627 the -G argument) this will generate the following instruction:
629 This instruction will use a GPREL reloc. If i can not be addressed
630 off the GP register, the following instruction sequence will be used:
633 In this case the first instruction will have a HI16 reloc, and the
634 second reloc will have a LO16 reloc. Both relocs will be against
637 The issue here is that we may not know whether i is GP addressable
638 until after we see the instruction that uses it. Therefore, we
639 want to be able to choose the final instruction sequence only at
640 the end of the assembly. This is similar to the way other
641 platforms choose the size of a PC relative instruction only at the
644 When generating position independent code we do not use GP
645 addressing in quite the same way, but the issue still arises as
646 external symbols and local symbols must be handled differently.
648 We handle these issues by actually generating both possible
649 instruction sequences. The longer one is put in a frag_var with
650 type rs_machine_dependent. We encode what to do with the frag in
651 the subtype field. We encode (1) the number of existing bytes to
652 replace, (2) the number of new bytes to use, (3) the offset from
653 the start of the existing bytes to the first reloc we must generate
654 (that is, the offset is applied from the start of the existing
655 bytes after they are replaced by the new bytes, if any), (4) the
656 offset from the start of the existing bytes to the second reloc,
657 (5) whether a third reloc is needed (the third reloc is always four
658 bytes after the second reloc), and (6) whether to warn if this
659 variant is used (this is sometimes needed if .set nomacro or .set
660 noat is in effect). All these numbers are reasonably small.
662 Generating two instruction sequences must be handled carefully to
663 ensure that delay slots are handled correctly. Fortunately, there
664 are a limited number of cases. When the second instruction
665 sequence is generated, append_insn is directed to maintain the
666 existing delay slot information, so it continues to apply to any
667 code after the second instruction sequence. This means that the
668 second instruction sequence must not impose any requirements not
669 required by the first instruction sequence.
671 These variant frags are then handled in functions called by the
672 machine independent code. md_estimate_size_before_relax returns
673 the final size of the frag. md_convert_frag sets up the final form
674 of the frag. tc_gen_reloc adjust the first reloc and adds a second
676 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
680 | (((reloc1) + 64) << 9) \
681 | (((reloc2) + 64) << 2) \
682 | ((reloc3) ? (1 << 1) : 0) \
684 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
685 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
686 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
687 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
688 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
689 #define RELAX_WARN(i) ((i) & 1)
691 /* Branch without likely bit. If label is out of range, we turn:
693 beq reg1, reg2, label
703 with the following opcode replacements:
710 bltzal <-> bgezal (with jal label instead of j label)
712 Even though keeping the delay slot instruction in the delay slot of
713 the branch would be more efficient, it would be very tricky to do
714 correctly, because we'd have to introduce a variable frag *after*
715 the delay slot instruction, and expand that instead. Let's do it
716 the easy way for now, even if the branch-not-taken case now costs
717 one additional instruction. Out-of-range branches are not supposed
718 to be common, anyway.
720 Branch likely. If label is out of range, we turn:
722 beql reg1, reg2, label
723 delay slot (annulled if branch not taken)
732 delay slot (executed only if branch taken)
735 It would be possible to generate a shorter sequence by losing the
736 likely bit, generating something like:
741 delay slot (executed only if branch taken)
753 bltzall -> bgezal (with jal label instead of j label)
754 bgezall -> bltzal (ditto)
757 but it's not clear that it would actually improve performance. */
758 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
761 | ((toofar) ? 1 : 0) \
763 | ((likely) ? 4 : 0) \
764 | ((uncond) ? 8 : 0)))
765 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
766 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
767 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
768 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
769 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
771 /* For mips16 code, we use an entirely different form of relaxation.
772 mips16 supports two versions of most instructions which take
773 immediate values: a small one which takes some small value, and a
774 larger one which takes a 16 bit value. Since branches also follow
775 this pattern, relaxing these values is required.
777 We can assemble both mips16 and normal MIPS code in a single
778 object. Therefore, we need to support this type of relaxation at
779 the same time that we support the relaxation described above. We
780 use the high bit of the subtype field to distinguish these cases.
782 The information we store for this type of relaxation is the
783 argument code found in the opcode file for this relocation, whether
784 the user explicitly requested a small or extended form, and whether
785 the relocation is in a jump or jal delay slot. That tells us the
786 size of the value, and how it should be stored. We also store
787 whether the fragment is considered to be extended or not. We also
788 store whether this is known to be a branch to a different section,
789 whether we have tried to relax this frag yet, and whether we have
790 ever extended a PC relative fragment because of a shift count. */
791 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
794 | ((small) ? 0x100 : 0) \
795 | ((ext) ? 0x200 : 0) \
796 | ((dslot) ? 0x400 : 0) \
797 | ((jal_dslot) ? 0x800 : 0))
798 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
799 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
800 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
801 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
802 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
803 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
804 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
805 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
806 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
807 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
808 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
809 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
811 /* Is the given value a sign-extended 32-bit value? */
812 #define IS_SEXT_32BIT_NUM(x) \
813 (((x) &~ (offsetT) 0x7fffffff) == 0 \
814 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
816 /* Is the given value a sign-extended 16-bit value? */
817 #define IS_SEXT_16BIT_NUM(x) \
818 (((x) &~ (offsetT) 0x7fff) == 0 \
819 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
822 /* Prototypes for static functions. */
824 #define internalError() \
825 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
827 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
829 static void append_insn
830 (char *place, struct mips_cl_insn *ip, expressionS *p,
831 bfd_reloc_code_real_type *r);
832 static void mips_no_prev_insn (int);
833 static void mips16_macro_build
834 (char *, int *, expressionS *, const char *, const char *, va_list);
835 static void load_register (int *, int, expressionS *, int);
836 static void macro (struct mips_cl_insn * ip);
837 static void mips16_macro (struct mips_cl_insn * ip);
838 #ifdef LOSING_COMPILER
839 static void macro2 (struct mips_cl_insn * ip);
841 static void mips_ip (char *str, struct mips_cl_insn * ip);
842 static void mips16_ip (char *str, struct mips_cl_insn * ip);
843 static void mips16_immed
844 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
845 unsigned long *, bfd_boolean *, unsigned short *);
846 static size_t my_getSmallExpression
847 (expressionS *, bfd_reloc_code_real_type *, char *);
848 static void my_getExpression (expressionS *, char *);
849 static void s_align (int);
850 static void s_change_sec (int);
851 static void s_change_section (int);
852 static void s_cons (int);
853 static void s_float_cons (int);
854 static void s_mips_globl (int);
855 static void s_option (int);
856 static void s_mipsset (int);
857 static void s_abicalls (int);
858 static void s_cpload (int);
859 static void s_cpsetup (int);
860 static void s_cplocal (int);
861 static void s_cprestore (int);
862 static void s_cpreturn (int);
863 static void s_gpvalue (int);
864 static void s_gpword (int);
865 static void s_gpdword (int);
866 static void s_cpadd (int);
867 static void s_insn (int);
868 static void md_obj_begin (void);
869 static void md_obj_end (void);
870 static void s_mips_ent (int);
871 static void s_mips_end (int);
872 static void s_mips_frame (int);
873 static void s_mips_mask (int reg_type);
874 static void s_mips_stab (int);
875 static void s_mips_weakext (int);
876 static void s_mips_file (int);
877 static void s_mips_loc (int);
878 static bfd_boolean pic_need_relax (symbolS *, asection *);
879 static int relaxed_branch_length (fragS *, asection *, int);
880 static int validate_mips_insn (const struct mips_opcode *);
882 /* Table and functions used to map between CPU/ISA names, and
883 ISA levels, and CPU numbers. */
887 const char *name; /* CPU or ISA name. */
888 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
889 int isa; /* ISA level. */
890 int cpu; /* CPU number (default CPU if ISA). */
893 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
894 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
895 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
899 The following pseudo-ops from the Kane and Heinrich MIPS book
900 should be defined here, but are currently unsupported: .alias,
901 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
903 The following pseudo-ops from the Kane and Heinrich MIPS book are
904 specific to the type of debugging information being generated, and
905 should be defined by the object format: .aent, .begin, .bend,
906 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
909 The following pseudo-ops from the Kane and Heinrich MIPS book are
910 not MIPS CPU specific, but are also not specific to the object file
911 format. This file is probably the best place to define them, but
912 they are not currently supported: .asm0, .endr, .lab, .repeat,
915 static const pseudo_typeS mips_pseudo_table[] =
917 /* MIPS specific pseudo-ops. */
918 {"option", s_option, 0},
919 {"set", s_mipsset, 0},
920 {"rdata", s_change_sec, 'r'},
921 {"sdata", s_change_sec, 's'},
922 {"livereg", s_ignore, 0},
923 {"abicalls", s_abicalls, 0},
924 {"cpload", s_cpload, 0},
925 {"cpsetup", s_cpsetup, 0},
926 {"cplocal", s_cplocal, 0},
927 {"cprestore", s_cprestore, 0},
928 {"cpreturn", s_cpreturn, 0},
929 {"gpvalue", s_gpvalue, 0},
930 {"gpword", s_gpword, 0},
931 {"gpdword", s_gpdword, 0},
932 {"cpadd", s_cpadd, 0},
935 /* Relatively generic pseudo-ops that happen to be used on MIPS
937 {"asciiz", stringer, 1},
938 {"bss", s_change_sec, 'b'},
941 {"dword", s_cons, 3},
942 {"weakext", s_mips_weakext, 0},
944 /* These pseudo-ops are defined in read.c, but must be overridden
945 here for one reason or another. */
946 {"align", s_align, 0},
948 {"data", s_change_sec, 'd'},
949 {"double", s_float_cons, 'd'},
950 {"float", s_float_cons, 'f'},
951 {"globl", s_mips_globl, 0},
952 {"global", s_mips_globl, 0},
953 {"hword", s_cons, 1},
958 {"section", s_change_section, 0},
959 {"short", s_cons, 1},
960 {"single", s_float_cons, 'f'},
961 {"stabn", s_mips_stab, 'n'},
962 {"text", s_change_sec, 't'},
965 { "extern", ecoff_directive_extern, 0},
970 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
972 /* These pseudo-ops should be defined by the object file format.
973 However, a.out doesn't support them, so we have versions here. */
974 {"aent", s_mips_ent, 1},
975 {"bgnb", s_ignore, 0},
976 {"end", s_mips_end, 0},
977 {"endb", s_ignore, 0},
978 {"ent", s_mips_ent, 0},
979 {"file", s_mips_file, 0},
980 {"fmask", s_mips_mask, 'F'},
981 {"frame", s_mips_frame, 0},
982 {"loc", s_mips_loc, 0},
983 {"mask", s_mips_mask, 'R'},
984 {"verstamp", s_ignore, 0},
988 extern void pop_insert (const pseudo_typeS *);
991 mips_pop_insert (void)
993 pop_insert (mips_pseudo_table);
994 if (! ECOFF_DEBUGGING)
995 pop_insert (mips_nonecoff_pseudo_table);
998 /* Symbols labelling the current insn. */
1000 struct insn_label_list
1002 struct insn_label_list *next;
1006 static struct insn_label_list *insn_labels;
1007 static struct insn_label_list *free_insn_labels;
1009 static void mips_clear_insn_labels (void);
1012 mips_clear_insn_labels (void)
1014 register struct insn_label_list **pl;
1016 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1022 static char *expr_end;
1024 /* Expressions which appear in instructions. These are set by
1027 static expressionS imm_expr;
1028 static expressionS offset_expr;
1030 /* Relocs associated with imm_expr and offset_expr. */
1032 static bfd_reloc_code_real_type imm_reloc[3]
1033 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1034 static bfd_reloc_code_real_type offset_reloc[3]
1035 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1037 /* These are set by mips16_ip if an explicit extension is used. */
1039 static bfd_boolean mips16_small, mips16_ext;
1042 /* The pdr segment for per procedure frame/regmask info. Not used for
1045 static segT pdr_seg;
1048 /* The default target format to use. */
1051 mips_target_format (void)
1053 switch (OUTPUT_FLAVOR)
1055 case bfd_target_aout_flavour:
1056 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1057 case bfd_target_ecoff_flavour:
1058 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1059 case bfd_target_coff_flavour:
1061 case bfd_target_elf_flavour:
1063 /* This is traditional mips. */
1064 return (target_big_endian
1065 ? (HAVE_64BIT_OBJECTS
1066 ? "elf64-tradbigmips"
1068 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1069 : (HAVE_64BIT_OBJECTS
1070 ? "elf64-tradlittlemips"
1072 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1074 return (target_big_endian
1075 ? (HAVE_64BIT_OBJECTS
1078 ? "elf32-nbigmips" : "elf32-bigmips"))
1079 : (HAVE_64BIT_OBJECTS
1080 ? "elf64-littlemips"
1082 ? "elf32-nlittlemips" : "elf32-littlemips")));
1090 /* This function is called once, at assembler startup time. It should
1091 set up all the tables, etc. that the MD part of the assembler will need. */
1096 register const char *retval = NULL;
1100 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1101 as_warn (_("Could not set architecture and machine"));
1103 op_hash = hash_new ();
1105 for (i = 0; i < NUMOPCODES;)
1107 const char *name = mips_opcodes[i].name;
1109 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1112 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1113 mips_opcodes[i].name, retval);
1114 /* Probably a memory allocation problem? Give up now. */
1115 as_fatal (_("Broken assembler. No assembly attempted."));
1119 if (mips_opcodes[i].pinfo != INSN_MACRO)
1121 if (!validate_mips_insn (&mips_opcodes[i]))
1126 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1129 mips16_op_hash = hash_new ();
1132 while (i < bfd_mips16_num_opcodes)
1134 const char *name = mips16_opcodes[i].name;
1136 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1138 as_fatal (_("internal: can't hash `%s': %s"),
1139 mips16_opcodes[i].name, retval);
1142 if (mips16_opcodes[i].pinfo != INSN_MACRO
1143 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1144 != mips16_opcodes[i].match))
1146 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1147 mips16_opcodes[i].name, mips16_opcodes[i].args);
1152 while (i < bfd_mips16_num_opcodes
1153 && strcmp (mips16_opcodes[i].name, name) == 0);
1157 as_fatal (_("Broken assembler. No assembly attempted."));
1159 /* We add all the general register names to the symbol table. This
1160 helps us detect invalid uses of them. */
1161 for (i = 0; i < 32; i++)
1165 sprintf (buf, "$%d", i);
1166 symbol_table_insert (symbol_new (buf, reg_section, i,
1167 &zero_address_frag));
1169 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1170 &zero_address_frag));
1171 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1172 &zero_address_frag));
1173 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1174 &zero_address_frag));
1175 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1176 &zero_address_frag));
1177 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1178 &zero_address_frag));
1179 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1180 &zero_address_frag));
1181 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1182 &zero_address_frag));
1183 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1184 &zero_address_frag));
1185 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1186 &zero_address_frag));
1188 /* If we don't add these register names to the symbol table, they
1189 may end up being added as regular symbols by operand(), and then
1190 make it to the object file as undefined in case they're not
1191 regarded as local symbols. They're local in o32, since `$' is a
1192 local symbol prefix, but not in n32 or n64. */
1193 for (i = 0; i < 8; i++)
1197 sprintf (buf, "$fcc%i", i);
1198 symbol_table_insert (symbol_new (buf, reg_section, -1,
1199 &zero_address_frag));
1202 mips_no_prev_insn (FALSE);
1205 mips_cprmask[0] = 0;
1206 mips_cprmask[1] = 0;
1207 mips_cprmask[2] = 0;
1208 mips_cprmask[3] = 0;
1210 /* set the default alignment for the text section (2**2) */
1211 record_alignment (text_section, 2);
1213 if (USE_GLOBAL_POINTER_OPT)
1214 bfd_set_gp_size (stdoutput, g_switch_value);
1216 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1218 /* On a native system, sections must be aligned to 16 byte
1219 boundaries. When configured for an embedded ELF target, we
1221 if (strcmp (TARGET_OS, "elf") != 0)
1223 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1224 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1225 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1228 /* Create a .reginfo section for register masks and a .mdebug
1229 section for debugging information. */
1237 subseg = now_subseg;
1239 /* The ABI says this section should be loaded so that the
1240 running program can access it. However, we don't load it
1241 if we are configured for an embedded target */
1242 flags = SEC_READONLY | SEC_DATA;
1243 if (strcmp (TARGET_OS, "elf") != 0)
1244 flags |= SEC_ALLOC | SEC_LOAD;
1246 if (mips_abi != N64_ABI)
1248 sec = subseg_new (".reginfo", (subsegT) 0);
1250 bfd_set_section_flags (stdoutput, sec, flags);
1251 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1254 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1259 /* The 64-bit ABI uses a .MIPS.options section rather than
1260 .reginfo section. */
1261 sec = subseg_new (".MIPS.options", (subsegT) 0);
1262 bfd_set_section_flags (stdoutput, sec, flags);
1263 bfd_set_section_alignment (stdoutput, sec, 3);
1266 /* Set up the option header. */
1268 Elf_Internal_Options opthdr;
1271 opthdr.kind = ODK_REGINFO;
1272 opthdr.size = (sizeof (Elf_External_Options)
1273 + sizeof (Elf64_External_RegInfo));
1276 f = frag_more (sizeof (Elf_External_Options));
1277 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1278 (Elf_External_Options *) f);
1280 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1285 if (ECOFF_DEBUGGING)
1287 sec = subseg_new (".mdebug", (subsegT) 0);
1288 (void) bfd_set_section_flags (stdoutput, sec,
1289 SEC_HAS_CONTENTS | SEC_READONLY);
1290 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1293 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1295 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1296 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1297 SEC_READONLY | SEC_RELOC
1299 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1303 subseg_set (seg, subseg);
1307 if (! ECOFF_DEBUGGING)
1314 if (! ECOFF_DEBUGGING)
1319 md_assemble (char *str)
1321 struct mips_cl_insn insn;
1322 bfd_reloc_code_real_type unused_reloc[3]
1323 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1325 imm_expr.X_op = O_absent;
1326 offset_expr.X_op = O_absent;
1327 imm_reloc[0] = BFD_RELOC_UNUSED;
1328 imm_reloc[1] = BFD_RELOC_UNUSED;
1329 imm_reloc[2] = BFD_RELOC_UNUSED;
1330 offset_reloc[0] = BFD_RELOC_UNUSED;
1331 offset_reloc[1] = BFD_RELOC_UNUSED;
1332 offset_reloc[2] = BFD_RELOC_UNUSED;
1334 if (mips_opts.mips16)
1335 mips16_ip (str, &insn);
1338 mips_ip (str, &insn);
1339 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1340 str, insn.insn_opcode));
1345 as_bad ("%s `%s'", insn_error, str);
1349 if (insn.insn_mo->pinfo == INSN_MACRO)
1351 if (mips_opts.mips16)
1352 mips16_macro (&insn);
1358 if (imm_expr.X_op != O_absent)
1359 append_insn (NULL, &insn, &imm_expr, imm_reloc);
1360 else if (offset_expr.X_op != O_absent)
1361 append_insn (NULL, &insn, &offset_expr, offset_reloc);
1363 append_insn (NULL, &insn, NULL, unused_reloc);
1367 /* Return true if the given relocation might need a matching %lo().
1368 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1369 applied to local symbols. */
1371 static inline bfd_boolean
1372 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1374 return (reloc == BFD_RELOC_HI16_S
1375 || reloc == BFD_RELOC_MIPS_GOT16);
1378 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1381 static inline bfd_boolean
1382 fixup_has_matching_lo_p (fixS *fixp)
1384 return (fixp->fx_next != NULL
1385 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1386 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1387 && fixp->fx_offset == fixp->fx_next->fx_offset);
1390 /* See whether instruction IP reads register REG. CLASS is the type
1394 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1395 enum mips_regclass class)
1397 if (class == MIPS16_REG)
1399 assert (mips_opts.mips16);
1400 reg = mips16_to_32_reg_map[reg];
1401 class = MIPS_GR_REG;
1404 /* Don't report on general register ZERO, since it never changes. */
1405 if (class == MIPS_GR_REG && reg == ZERO)
1408 if (class == MIPS_FP_REG)
1410 assert (! mips_opts.mips16);
1411 /* If we are called with either $f0 or $f1, we must check $f0.
1412 This is not optimal, because it will introduce an unnecessary
1413 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1414 need to distinguish reading both $f0 and $f1 or just one of
1415 them. Note that we don't have to check the other way,
1416 because there is no instruction that sets both $f0 and $f1
1417 and requires a delay. */
1418 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1419 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1420 == (reg &~ (unsigned) 1)))
1422 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1423 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1424 == (reg &~ (unsigned) 1)))
1427 else if (! mips_opts.mips16)
1429 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1430 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1432 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1433 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1438 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1439 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1440 & MIPS16OP_MASK_RX)]
1443 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1444 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1445 & MIPS16OP_MASK_RY)]
1448 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1449 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1450 & MIPS16OP_MASK_MOVE32Z)]
1453 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1455 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1457 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1459 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1460 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1461 & MIPS16OP_MASK_REGR32) == reg)
1468 /* This function returns true if modifying a register requires a
1472 reg_needs_delay (unsigned int reg)
1474 unsigned long prev_pinfo;
1476 prev_pinfo = prev_insn.insn_mo->pinfo;
1477 if (! mips_opts.noreorder
1478 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1479 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1480 || (! gpr_interlocks
1481 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1483 /* A load from a coprocessor or from memory. All load
1484 delays delay the use of general register rt for one
1485 instruction on the r3000. The r6000 and r4000 use
1487 /* Itbl support may require additional care here. */
1488 know (prev_pinfo & INSN_WRITE_GPR_T);
1489 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1496 /* Mark instruction labels in mips16 mode. This permits the linker to
1497 handle them specially, such as generating jalx instructions when
1498 needed. We also make them odd for the duration of the assembly, in
1499 order to generate the right sort of code. We will make them even
1500 in the adjust_symtab routine, while leaving them marked. This is
1501 convenient for the debugger and the disassembler. The linker knows
1502 to make them odd again. */
1505 mips16_mark_labels (void)
1507 if (mips_opts.mips16)
1509 struct insn_label_list *l;
1512 for (l = insn_labels; l != NULL; l = l->next)
1515 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1516 S_SET_OTHER (l->label, STO_MIPS16);
1518 val = S_GET_VALUE (l->label);
1520 S_SET_VALUE (l->label, val + 1);
1525 /* Output an instruction. PLACE is where to put the instruction; if
1526 it is NULL, this uses frag_more to get room. IP is the instruction
1527 information. ADDRESS_EXPR is an operand of the instruction to be
1528 used with RELOC_TYPE. */
1531 append_insn (char *place, struct mips_cl_insn *ip, expressionS *address_expr,
1532 bfd_reloc_code_real_type *reloc_type)
1534 register unsigned long prev_pinfo, pinfo;
1538 bfd_boolean force_new_frag = FALSE;
1540 /* Mark instruction labels in mips16 mode. */
1541 mips16_mark_labels ();
1543 prev_pinfo = prev_insn.insn_mo->pinfo;
1544 pinfo = ip->insn_mo->pinfo;
1546 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1550 /* If the previous insn required any delay slots, see if we need
1551 to insert a NOP or two. There are eight kinds of possible
1552 hazards, of which an instruction can have at most one type.
1553 (1) a load from memory delay
1554 (2) a load from a coprocessor delay
1555 (3) an unconditional branch delay
1556 (4) a conditional branch delay
1557 (5) a move to coprocessor register delay
1558 (6) a load coprocessor register from memory delay
1559 (7) a coprocessor condition code delay
1560 (8) a HI/LO special register delay
1562 There are a lot of optimizations we could do that we don't.
1563 In particular, we do not, in general, reorder instructions.
1564 If you use gcc with optimization, it will reorder
1565 instructions and generally do much more optimization then we
1566 do here; repeating all that work in the assembler would only
1567 benefit hand written assembly code, and does not seem worth
1570 /* This is how a NOP is emitted. */
1571 #define emit_nop() \
1573 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1574 : md_number_to_chars (frag_more (4), 0, 4))
1576 /* The previous insn might require a delay slot, depending upon
1577 the contents of the current insn. */
1578 if (! mips_opts.mips16
1579 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1580 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1581 && ! cop_interlocks)
1582 || (! gpr_interlocks
1583 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1585 /* A load from a coprocessor or from memory. All load
1586 delays delay the use of general register rt for one
1587 instruction on the r3000. The r6000 and r4000 use
1589 /* Itbl support may require additional care here. */
1590 know (prev_pinfo & INSN_WRITE_GPR_T);
1591 if (mips_optimize == 0
1592 || insn_uses_reg (ip,
1593 ((prev_insn.insn_opcode >> OP_SH_RT)
1598 else if (! mips_opts.mips16
1599 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1600 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1601 && ! cop_interlocks)
1602 || (mips_opts.isa == ISA_MIPS1
1603 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1605 /* A generic coprocessor delay. The previous instruction
1606 modified a coprocessor general or control register. If
1607 it modified a control register, we need to avoid any
1608 coprocessor instruction (this is probably not always
1609 required, but it sometimes is). If it modified a general
1610 register, we avoid using that register.
1612 On the r6000 and r4000 loading a coprocessor register
1613 from memory is interlocked, and does not require a delay.
1615 This case is not handled very well. There is no special
1616 knowledge of CP0 handling, and the coprocessors other
1617 than the floating point unit are not distinguished at
1619 /* Itbl support may require additional care here. FIXME!
1620 Need to modify this to include knowledge about
1621 user specified delays! */
1622 if (prev_pinfo & INSN_WRITE_FPR_T)
1624 if (mips_optimize == 0
1625 || insn_uses_reg (ip,
1626 ((prev_insn.insn_opcode >> OP_SH_FT)
1631 else if (prev_pinfo & INSN_WRITE_FPR_S)
1633 if (mips_optimize == 0
1634 || insn_uses_reg (ip,
1635 ((prev_insn.insn_opcode >> OP_SH_FS)
1642 /* We don't know exactly what the previous instruction
1643 does. If the current instruction uses a coprocessor
1644 register, we must insert a NOP. If previous
1645 instruction may set the condition codes, and the
1646 current instruction uses them, we must insert two
1648 /* Itbl support may require additional care here. */
1649 if (mips_optimize == 0
1650 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1651 && (pinfo & INSN_READ_COND_CODE)))
1653 else if (pinfo & INSN_COP)
1657 else if (! mips_opts.mips16
1658 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1659 && (prev_pinfo & INSN_WRITE_COND_CODE)
1660 && ! cop_interlocks)
1662 /* The previous instruction sets the coprocessor condition
1663 codes, but does not require a general coprocessor delay
1664 (this means it is a floating point comparison
1665 instruction). If this instruction uses the condition
1666 codes, we need to insert a single NOP. */
1667 /* Itbl support may require additional care here. */
1668 if (mips_optimize == 0
1669 || (pinfo & INSN_READ_COND_CODE))
1673 /* If we're fixing up mfhi/mflo for the r7000 and the
1674 previous insn was an mfhi/mflo and the current insn
1675 reads the register that the mfhi/mflo wrote to, then
1678 else if (mips_7000_hilo_fix
1679 && MF_HILO_INSN (prev_pinfo)
1680 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1687 /* If we're fixing up mfhi/mflo for the r7000 and the
1688 2nd previous insn was an mfhi/mflo and the current insn
1689 reads the register that the mfhi/mflo wrote to, then
1692 else if (mips_7000_hilo_fix
1693 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1694 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1702 else if (prev_pinfo & INSN_READ_LO)
1704 /* The previous instruction reads the LO register; if the
1705 current instruction writes to the LO register, we must
1706 insert two NOPS. Some newer processors have interlocks.
1707 Also the tx39's multiply instructions can be exectuted
1708 immediatly after a read from HI/LO (without the delay),
1709 though the tx39's divide insns still do require the
1711 if (! (hilo_interlocks
1712 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1713 && (mips_optimize == 0
1714 || (pinfo & INSN_WRITE_LO)))
1716 /* Most mips16 branch insns don't have a delay slot.
1717 If a read from LO is immediately followed by a branch
1718 to a write to LO we have a read followed by a write
1719 less than 2 insns away. We assume the target of
1720 a branch might be a write to LO, and insert a nop
1721 between a read and an immediately following branch. */
1722 else if (mips_opts.mips16
1723 && (mips_optimize == 0
1724 || (pinfo & MIPS16_INSN_BRANCH)))
1727 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1729 /* The previous instruction reads the HI register; if the
1730 current instruction writes to the HI register, we must
1731 insert a NOP. Some newer processors have interlocks.
1732 Also the note tx39's multiply above. */
1733 if (! (hilo_interlocks
1734 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1735 && (mips_optimize == 0
1736 || (pinfo & INSN_WRITE_HI)))
1738 /* Most mips16 branch insns don't have a delay slot.
1739 If a read from HI is immediately followed by a branch
1740 to a write to HI we have a read followed by a write
1741 less than 2 insns away. We assume the target of
1742 a branch might be a write to HI, and insert a nop
1743 between a read and an immediately following branch. */
1744 else if (mips_opts.mips16
1745 && (mips_optimize == 0
1746 || (pinfo & MIPS16_INSN_BRANCH)))
1750 /* If the previous instruction was in a noreorder section, then
1751 we don't want to insert the nop after all. */
1752 /* Itbl support may require additional care here. */
1753 if (prev_insn_unreordered)
1756 /* There are two cases which require two intervening
1757 instructions: 1) setting the condition codes using a move to
1758 coprocessor instruction which requires a general coprocessor
1759 delay and then reading the condition codes 2) reading the HI
1760 or LO register and then writing to it (except on processors
1761 which have interlocks). If we are not already emitting a NOP
1762 instruction, we must check for these cases compared to the
1763 instruction previous to the previous instruction. */
1764 if ((! mips_opts.mips16
1765 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1766 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1767 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1768 && (pinfo & INSN_READ_COND_CODE)
1769 && ! cop_interlocks)
1770 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1771 && (pinfo & INSN_WRITE_LO)
1772 && ! (hilo_interlocks
1773 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1774 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1775 && (pinfo & INSN_WRITE_HI)
1776 && ! (hilo_interlocks
1777 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1782 if (prev_prev_insn_unreordered)
1785 if (prev_prev_nop && nops == 0)
1788 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
1790 /* We're out of bits in pinfo, so we must resort to string
1791 ops here. Shortcuts are selected based on opcodes being
1792 limited to the VR4122 instruction set. */
1794 const char *pn = prev_insn.insn_mo->name;
1795 const char *tn = ip->insn_mo->name;
1796 if (strncmp(pn, "macc", 4) == 0
1797 || strncmp(pn, "dmacc", 5) == 0)
1799 /* Errata 21 - [D]DIV[U] after [D]MACC */
1800 if (strstr (tn, "div"))
1805 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1806 if (pn[0] == 'd' /* dmacc */
1807 && (strncmp(tn, "dmult", 5) == 0
1808 || strncmp(tn, "dmacc", 5) == 0))
1813 /* Errata 24 - MT{LO,HI} after [D]MACC */
1814 if (strcmp (tn, "mtlo") == 0
1815 || strcmp (tn, "mthi") == 0)
1821 else if (strncmp(pn, "dmult", 5) == 0
1822 && (strncmp(tn, "dmult", 5) == 0
1823 || strncmp(tn, "dmacc", 5) == 0))
1825 /* Here is the rest of errata 23. */
1828 if (nops < min_nops)
1832 /* If we are being given a nop instruction, don't bother with
1833 one of the nops we would otherwise output. This will only
1834 happen when a nop instruction is used with mips_optimize set
1837 && ! mips_opts.noreorder
1838 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1841 /* Now emit the right number of NOP instructions. */
1842 if (nops > 0 && ! mips_opts.noreorder)
1845 unsigned long old_frag_offset;
1847 struct insn_label_list *l;
1849 old_frag = frag_now;
1850 old_frag_offset = frag_now_fix ();
1852 for (i = 0; i < nops; i++)
1857 listing_prev_line ();
1858 /* We may be at the start of a variant frag. In case we
1859 are, make sure there is enough space for the frag
1860 after the frags created by listing_prev_line. The
1861 argument to frag_grow here must be at least as large
1862 as the argument to all other calls to frag_grow in
1863 this file. We don't have to worry about being in the
1864 middle of a variant frag, because the variants insert
1865 all needed nop instructions themselves. */
1869 for (l = insn_labels; l != NULL; l = l->next)
1873 assert (S_GET_SEGMENT (l->label) == now_seg);
1874 symbol_set_frag (l->label, frag_now);
1875 val = (valueT) frag_now_fix ();
1876 /* mips16 text labels are stored as odd. */
1877 if (mips_opts.mips16)
1879 S_SET_VALUE (l->label, val);
1882 #ifndef NO_ECOFF_DEBUGGING
1883 if (ECOFF_DEBUGGING)
1884 ecoff_fix_loc (old_frag, old_frag_offset);
1887 else if (prev_nop_frag != NULL)
1889 /* We have a frag holding nops we may be able to remove. If
1890 we don't need any nops, we can decrease the size of
1891 prev_nop_frag by the size of one instruction. If we do
1892 need some nops, we count them in prev_nops_required. */
1893 if (prev_nop_frag_since == 0)
1897 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1898 --prev_nop_frag_holds;
1901 prev_nop_frag_required += nops;
1905 if (prev_prev_nop == 0)
1907 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1908 --prev_nop_frag_holds;
1911 ++prev_nop_frag_required;
1914 if (prev_nop_frag_holds <= prev_nop_frag_required)
1915 prev_nop_frag = NULL;
1917 ++prev_nop_frag_since;
1919 /* Sanity check: by the time we reach the second instruction
1920 after prev_nop_frag, we should have used up all the nops
1921 one way or another. */
1922 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1928 && *reloc_type == BFD_RELOC_16_PCREL_S2
1929 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
1930 || pinfo & INSN_COND_BRANCH_LIKELY)
1931 && mips_relax_branch
1932 /* Don't try branch relaxation within .set nomacro, or within
1933 .set noat if we use $at for PIC computations. If it turns
1934 out that the branch was out-of-range, we'll get an error. */
1935 && !mips_opts.warn_about_macros
1936 && !(mips_opts.noat && mips_pic != NO_PIC)
1937 && !mips_opts.mips16)
1939 f = frag_var (rs_machine_dependent,
1940 relaxed_branch_length
1942 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
1943 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
1945 (pinfo & INSN_UNCOND_BRANCH_DELAY,
1946 pinfo & INSN_COND_BRANCH_LIKELY,
1947 pinfo & INSN_WRITE_GPR_31,
1949 address_expr->X_add_symbol,
1950 address_expr->X_add_number,
1952 *reloc_type = BFD_RELOC_UNUSED;
1954 else if (*reloc_type > BFD_RELOC_UNUSED)
1956 /* We need to set up a variant frag. */
1957 assert (mips_opts.mips16 && address_expr != NULL);
1958 f = frag_var (rs_machine_dependent, 4, 0,
1959 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1960 mips16_small, mips16_ext,
1962 & INSN_UNCOND_BRANCH_DELAY),
1963 (*prev_insn_reloc_type
1964 == BFD_RELOC_MIPS16_JMP)),
1965 make_expr_symbol (address_expr), 0, NULL);
1967 else if (place != NULL)
1969 else if (mips_opts.mips16
1971 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1973 /* Make sure there is enough room to swap this instruction with
1974 a following jump instruction. */
1980 if (mips_opts.mips16
1981 && mips_opts.noreorder
1982 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1983 as_warn (_("extended instruction in delay slot"));
1988 fixp[0] = fixp[1] = fixp[2] = NULL;
1989 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1991 if (address_expr->X_op == O_constant)
1995 switch (*reloc_type)
1998 ip->insn_opcode |= address_expr->X_add_number;
2001 case BFD_RELOC_MIPS_HIGHEST:
2002 tmp = (address_expr->X_add_number
2003 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2005 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2008 case BFD_RELOC_MIPS_HIGHER:
2009 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2010 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2013 case BFD_RELOC_HI16_S:
2014 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2018 case BFD_RELOC_HI16:
2019 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2022 case BFD_RELOC_LO16:
2023 case BFD_RELOC_MIPS_GOT_DISP:
2024 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2027 case BFD_RELOC_MIPS_JMP:
2028 if ((address_expr->X_add_number & 3) != 0)
2029 as_bad (_("jump to misaligned address (0x%lx)"),
2030 (unsigned long) address_expr->X_add_number);
2031 if (address_expr->X_add_number & ~0xfffffff)
2032 as_bad (_("jump address range overflow (0x%lx)"),
2033 (unsigned long) address_expr->X_add_number);
2034 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2037 case BFD_RELOC_MIPS16_JMP:
2038 if ((address_expr->X_add_number & 3) != 0)
2039 as_bad (_("jump to misaligned address (0x%lx)"),
2040 (unsigned long) address_expr->X_add_number);
2041 if (address_expr->X_add_number & ~0xfffffff)
2042 as_bad (_("jump address range overflow (0x%lx)"),
2043 (unsigned long) address_expr->X_add_number);
2045 (((address_expr->X_add_number & 0x7c0000) << 3)
2046 | ((address_expr->X_add_number & 0xf800000) >> 7)
2047 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2050 case BFD_RELOC_16_PCREL_S2:
2060 /* Don't generate a reloc if we are writing into a variant frag. */
2063 reloc_howto_type *howto;
2066 /* In a compound relocation, it is the final (outermost)
2067 operator that determines the relocated field. */
2068 for (i = 1; i < 3; i++)
2069 if (reloc_type[i] == BFD_RELOC_UNUSED)
2072 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2073 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2074 bfd_get_reloc_size(howto),
2076 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2079 /* These relocations can have an addend that won't fit in
2080 4 octets for 64bit assembly. */
2082 && ! howto->partial_inplace
2083 && (reloc_type[0] == BFD_RELOC_16
2084 || reloc_type[0] == BFD_RELOC_32
2085 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2086 || reloc_type[0] == BFD_RELOC_HI16_S
2087 || reloc_type[0] == BFD_RELOC_LO16
2088 || reloc_type[0] == BFD_RELOC_GPREL16
2089 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2090 || reloc_type[0] == BFD_RELOC_GPREL32
2091 || reloc_type[0] == BFD_RELOC_64
2092 || reloc_type[0] == BFD_RELOC_CTOR
2093 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2094 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2095 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2096 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2097 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2098 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2099 fixp[0]->fx_no_overflow = 1;
2101 if (reloc_needs_lo_p (*reloc_type))
2103 struct mips_hi_fixup *hi_fixup;
2105 /* Reuse the last entry if it already has a matching %lo. */
2106 hi_fixup = mips_hi_fixup_list;
2108 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2110 hi_fixup = ((struct mips_hi_fixup *)
2111 xmalloc (sizeof (struct mips_hi_fixup)));
2112 hi_fixup->next = mips_hi_fixup_list;
2113 mips_hi_fixup_list = hi_fixup;
2115 hi_fixup->fixp = fixp[0];
2116 hi_fixup->seg = now_seg;
2119 /* Add fixups for the second and third relocations, if given.
2120 Note that the ABI allows the second relocation to be
2121 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2122 moment we only use RSS_UNDEF, but we could add support
2123 for the others if it ever becomes necessary. */
2124 for (i = 1; i < 3; i++)
2125 if (reloc_type[i] != BFD_RELOC_UNUSED)
2127 address_expr->X_op = O_absent;
2128 address_expr->X_add_symbol = 0;
2129 address_expr->X_add_number = 0;
2131 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2132 fixp[0]->fx_size, address_expr,
2133 FALSE, reloc_type[i]);
2139 if (! mips_opts.mips16)
2141 md_number_to_chars (f, ip->insn_opcode, 4);
2143 dwarf2_emit_insn (4);
2146 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2148 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2149 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2151 dwarf2_emit_insn (4);
2158 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2161 md_number_to_chars (f, ip->insn_opcode, 2);
2163 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2167 /* Update the register mask information. */
2168 if (! mips_opts.mips16)
2170 if (pinfo & INSN_WRITE_GPR_D)
2171 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2172 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2173 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2174 if (pinfo & INSN_READ_GPR_S)
2175 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2176 if (pinfo & INSN_WRITE_GPR_31)
2177 mips_gprmask |= 1 << RA;
2178 if (pinfo & INSN_WRITE_FPR_D)
2179 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2180 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2181 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2182 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2183 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2184 if ((pinfo & INSN_READ_FPR_R) != 0)
2185 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2186 if (pinfo & INSN_COP)
2188 /* We don't keep enough information to sort these cases out.
2189 The itbl support does keep this information however, although
2190 we currently don't support itbl fprmats as part of the cop
2191 instruction. May want to add this support in the future. */
2193 /* Never set the bit for $0, which is always zero. */
2194 mips_gprmask &= ~1 << 0;
2198 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2199 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2200 & MIPS16OP_MASK_RX);
2201 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2202 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2203 & MIPS16OP_MASK_RY);
2204 if (pinfo & MIPS16_INSN_WRITE_Z)
2205 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2206 & MIPS16OP_MASK_RZ);
2207 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2208 mips_gprmask |= 1 << TREG;
2209 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2210 mips_gprmask |= 1 << SP;
2211 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2212 mips_gprmask |= 1 << RA;
2213 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2214 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2215 if (pinfo & MIPS16_INSN_READ_Z)
2216 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2217 & MIPS16OP_MASK_MOVE32Z);
2218 if (pinfo & MIPS16_INSN_READ_GPR_X)
2219 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2220 & MIPS16OP_MASK_REGR32);
2223 if (place == NULL && ! mips_opts.noreorder)
2225 /* Filling the branch delay slot is more complex. We try to
2226 switch the branch with the previous instruction, which we can
2227 do if the previous instruction does not set up a condition
2228 that the branch tests and if the branch is not itself the
2229 target of any branch. */
2230 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2231 || (pinfo & INSN_COND_BRANCH_DELAY))
2233 if (mips_optimize < 2
2234 /* If we have seen .set volatile or .set nomove, don't
2236 || mips_opts.nomove != 0
2237 /* If we had to emit any NOP instructions, then we
2238 already know we can not swap. */
2240 /* If we don't even know the previous insn, we can not
2242 || ! prev_insn_valid
2243 /* If the previous insn is already in a branch delay
2244 slot, then we can not swap. */
2245 || prev_insn_is_delay_slot
2246 /* If the previous previous insn was in a .set
2247 noreorder, we can't swap. Actually, the MIPS
2248 assembler will swap in this situation. However, gcc
2249 configured -with-gnu-as will generate code like
2255 in which we can not swap the bne and INSN. If gcc is
2256 not configured -with-gnu-as, it does not output the
2257 .set pseudo-ops. We don't have to check
2258 prev_insn_unreordered, because prev_insn_valid will
2259 be 0 in that case. We don't want to use
2260 prev_prev_insn_valid, because we do want to be able
2261 to swap at the start of a function. */
2262 || prev_prev_insn_unreordered
2263 /* If the branch is itself the target of a branch, we
2264 can not swap. We cheat on this; all we check for is
2265 whether there is a label on this instruction. If
2266 there are any branches to anything other than a
2267 label, users must use .set noreorder. */
2268 || insn_labels != NULL
2269 /* If the previous instruction is in a variant frag, we
2270 can not do the swap. This does not apply to the
2271 mips16, which uses variant frags for different
2273 || (! mips_opts.mips16
2274 && prev_insn_frag->fr_type == rs_machine_dependent)
2275 /* If the branch reads the condition codes, we don't
2276 even try to swap, because in the sequence
2281 we can not swap, and I don't feel like handling that
2283 || (! mips_opts.mips16
2284 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2285 && (pinfo & INSN_READ_COND_CODE))
2286 /* We can not swap with an instruction that requires a
2287 delay slot, becase the target of the branch might
2288 interfere with that instruction. */
2289 || (! mips_opts.mips16
2290 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2292 /* Itbl support may require additional care here. */
2293 & (INSN_LOAD_COPROC_DELAY
2294 | INSN_COPROC_MOVE_DELAY
2295 | INSN_WRITE_COND_CODE)))
2296 || (! (hilo_interlocks
2297 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2301 || (! mips_opts.mips16
2303 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2304 || (! mips_opts.mips16
2305 && mips_opts.isa == ISA_MIPS1
2306 /* Itbl support may require additional care here. */
2307 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2308 /* We can not swap with a branch instruction. */
2310 & (INSN_UNCOND_BRANCH_DELAY
2311 | INSN_COND_BRANCH_DELAY
2312 | INSN_COND_BRANCH_LIKELY))
2313 /* We do not swap with a trap instruction, since it
2314 complicates trap handlers to have the trap
2315 instruction be in a delay slot. */
2316 || (prev_pinfo & INSN_TRAP)
2317 /* If the branch reads a register that the previous
2318 instruction sets, we can not swap. */
2319 || (! mips_opts.mips16
2320 && (prev_pinfo & INSN_WRITE_GPR_T)
2321 && insn_uses_reg (ip,
2322 ((prev_insn.insn_opcode >> OP_SH_RT)
2325 || (! mips_opts.mips16
2326 && (prev_pinfo & INSN_WRITE_GPR_D)
2327 && insn_uses_reg (ip,
2328 ((prev_insn.insn_opcode >> OP_SH_RD)
2331 || (mips_opts.mips16
2332 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2333 && insn_uses_reg (ip,
2334 ((prev_insn.insn_opcode
2336 & MIPS16OP_MASK_RX),
2338 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2339 && insn_uses_reg (ip,
2340 ((prev_insn.insn_opcode
2342 & MIPS16OP_MASK_RY),
2344 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2345 && insn_uses_reg (ip,
2346 ((prev_insn.insn_opcode
2348 & MIPS16OP_MASK_RZ),
2350 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2351 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2352 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2353 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2354 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2355 && insn_uses_reg (ip,
2356 MIPS16OP_EXTRACT_REG32R (prev_insn.
2359 /* If the branch writes a register that the previous
2360 instruction sets, we can not swap (we know that
2361 branches write only to RD or to $31). */
2362 || (! mips_opts.mips16
2363 && (prev_pinfo & INSN_WRITE_GPR_T)
2364 && (((pinfo & INSN_WRITE_GPR_D)
2365 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2366 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2367 || ((pinfo & INSN_WRITE_GPR_31)
2368 && (((prev_insn.insn_opcode >> OP_SH_RT)
2371 || (! mips_opts.mips16
2372 && (prev_pinfo & INSN_WRITE_GPR_D)
2373 && (((pinfo & INSN_WRITE_GPR_D)
2374 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2375 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2376 || ((pinfo & INSN_WRITE_GPR_31)
2377 && (((prev_insn.insn_opcode >> OP_SH_RD)
2380 || (mips_opts.mips16
2381 && (pinfo & MIPS16_INSN_WRITE_31)
2382 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2383 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2384 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2386 /* If the branch writes a register that the previous
2387 instruction reads, we can not swap (we know that
2388 branches only write to RD or to $31). */
2389 || (! mips_opts.mips16
2390 && (pinfo & INSN_WRITE_GPR_D)
2391 && insn_uses_reg (&prev_insn,
2392 ((ip->insn_opcode >> OP_SH_RD)
2395 || (! mips_opts.mips16
2396 && (pinfo & INSN_WRITE_GPR_31)
2397 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2398 || (mips_opts.mips16
2399 && (pinfo & MIPS16_INSN_WRITE_31)
2400 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2401 /* If we are generating embedded PIC code, the branch
2402 might be expanded into a sequence which uses $at, so
2403 we can't swap with an instruction which reads it. */
2404 || (mips_pic == EMBEDDED_PIC
2405 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2406 /* If the previous previous instruction has a load
2407 delay, and sets a register that the branch reads, we
2409 || (! mips_opts.mips16
2410 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2411 /* Itbl support may require additional care here. */
2412 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2413 || (! gpr_interlocks
2414 && (prev_prev_insn.insn_mo->pinfo
2415 & INSN_LOAD_MEMORY_DELAY)))
2416 && insn_uses_reg (ip,
2417 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2420 /* If one instruction sets a condition code and the
2421 other one uses a condition code, we can not swap. */
2422 || ((pinfo & INSN_READ_COND_CODE)
2423 && (prev_pinfo & INSN_WRITE_COND_CODE))
2424 || ((pinfo & INSN_WRITE_COND_CODE)
2425 && (prev_pinfo & INSN_READ_COND_CODE))
2426 /* If the previous instruction uses the PC, we can not
2428 || (mips_opts.mips16
2429 && (prev_pinfo & MIPS16_INSN_READ_PC))
2430 /* If the previous instruction was extended, we can not
2432 || (mips_opts.mips16 && prev_insn_extended)
2433 /* If the previous instruction had a fixup in mips16
2434 mode, we can not swap. This normally means that the
2435 previous instruction was a 4 byte branch anyhow. */
2436 || (mips_opts.mips16 && prev_insn_fixp[0])
2437 /* If the previous instruction is a sync, sync.l, or
2438 sync.p, we can not swap. */
2439 || (prev_pinfo & INSN_SYNC))
2441 /* We could do even better for unconditional branches to
2442 portions of this object file; we could pick up the
2443 instruction at the destination, put it in the delay
2444 slot, and bump the destination address. */
2446 /* Update the previous insn information. */
2447 prev_prev_insn = *ip;
2448 prev_insn.insn_mo = &dummy_opcode;
2452 /* It looks like we can actually do the swap. */
2453 if (! mips_opts.mips16)
2458 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2459 memcpy (temp, prev_f, 4);
2460 memcpy (prev_f, f, 4);
2461 memcpy (f, temp, 4);
2462 if (prev_insn_fixp[0])
2464 prev_insn_fixp[0]->fx_frag = frag_now;
2465 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2467 if (prev_insn_fixp[1])
2469 prev_insn_fixp[1]->fx_frag = frag_now;
2470 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2472 if (prev_insn_fixp[2])
2474 prev_insn_fixp[2]->fx_frag = frag_now;
2475 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2477 if (prev_insn_fixp[0] && HAVE_NEWABI
2478 && prev_insn_frag != frag_now
2479 && (prev_insn_fixp[0]->fx_r_type
2480 == BFD_RELOC_MIPS_GOT_DISP
2481 || (prev_insn_fixp[0]->fx_r_type
2482 == BFD_RELOC_MIPS_CALL16)))
2484 /* To avoid confusion in tc_gen_reloc, we must
2485 ensure that this does not become a variant
2487 force_new_frag = TRUE;
2491 fixp[0]->fx_frag = prev_insn_frag;
2492 fixp[0]->fx_where = prev_insn_where;
2496 fixp[1]->fx_frag = prev_insn_frag;
2497 fixp[1]->fx_where = prev_insn_where;
2501 fixp[2]->fx_frag = prev_insn_frag;
2502 fixp[2]->fx_where = prev_insn_where;
2510 assert (prev_insn_fixp[0] == NULL);
2511 assert (prev_insn_fixp[1] == NULL);
2512 assert (prev_insn_fixp[2] == NULL);
2513 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2514 memcpy (temp, prev_f, 2);
2515 memcpy (prev_f, f, 2);
2516 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2518 assert (*reloc_type == BFD_RELOC_UNUSED);
2519 memcpy (f, temp, 2);
2523 memcpy (f, f + 2, 2);
2524 memcpy (f + 2, temp, 2);
2528 fixp[0]->fx_frag = prev_insn_frag;
2529 fixp[0]->fx_where = prev_insn_where;
2533 fixp[1]->fx_frag = prev_insn_frag;
2534 fixp[1]->fx_where = prev_insn_where;
2538 fixp[2]->fx_frag = prev_insn_frag;
2539 fixp[2]->fx_where = prev_insn_where;
2543 /* Update the previous insn information; leave prev_insn
2545 prev_prev_insn = *ip;
2547 prev_insn_is_delay_slot = 1;
2549 /* If that was an unconditional branch, forget the previous
2550 insn information. */
2551 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2553 prev_prev_insn.insn_mo = &dummy_opcode;
2554 prev_insn.insn_mo = &dummy_opcode;
2557 prev_insn_fixp[0] = NULL;
2558 prev_insn_fixp[1] = NULL;
2559 prev_insn_fixp[2] = NULL;
2560 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2561 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2562 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2563 prev_insn_extended = 0;
2565 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2567 /* We don't yet optimize a branch likely. What we should do
2568 is look at the target, copy the instruction found there
2569 into the delay slot, and increment the branch to jump to
2570 the next instruction. */
2572 /* Update the previous insn information. */
2573 prev_prev_insn = *ip;
2574 prev_insn.insn_mo = &dummy_opcode;
2575 prev_insn_fixp[0] = NULL;
2576 prev_insn_fixp[1] = NULL;
2577 prev_insn_fixp[2] = NULL;
2578 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2579 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2580 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2581 prev_insn_extended = 0;
2585 /* Update the previous insn information. */
2587 prev_prev_insn.insn_mo = &dummy_opcode;
2589 prev_prev_insn = prev_insn;
2592 /* Any time we see a branch, we always fill the delay slot
2593 immediately; since this insn is not a branch, we know it
2594 is not in a delay slot. */
2595 prev_insn_is_delay_slot = 0;
2597 prev_insn_fixp[0] = fixp[0];
2598 prev_insn_fixp[1] = fixp[1];
2599 prev_insn_fixp[2] = fixp[2];
2600 prev_insn_reloc_type[0] = reloc_type[0];
2601 prev_insn_reloc_type[1] = reloc_type[1];
2602 prev_insn_reloc_type[2] = reloc_type[2];
2603 if (mips_opts.mips16)
2604 prev_insn_extended = (ip->use_extend
2605 || *reloc_type > BFD_RELOC_UNUSED);
2608 prev_prev_insn_unreordered = prev_insn_unreordered;
2609 prev_insn_unreordered = 0;
2610 prev_insn_frag = frag_now;
2611 prev_insn_where = f - frag_now->fr_literal;
2612 prev_insn_valid = 1;
2614 else if (place == NULL)
2616 /* We need to record a bit of information even when we are not
2617 reordering, in order to determine the base address for mips16
2618 PC relative relocs. */
2619 prev_prev_insn = prev_insn;
2621 prev_insn_reloc_type[0] = reloc_type[0];
2622 prev_insn_reloc_type[1] = reloc_type[1];
2623 prev_insn_reloc_type[2] = reloc_type[2];
2624 prev_prev_insn_unreordered = prev_insn_unreordered;
2625 prev_insn_unreordered = 1;
2628 /* We just output an insn, so the next one doesn't have a label. */
2629 mips_clear_insn_labels ();
2631 /* We must ensure that the frag to which an instruction that was
2632 moved from a non-variant frag doesn't become a variant frag,
2633 otherwise tc_gen_reloc may get confused. */
2636 frag_wane (frag_now);
2641 /* This function forgets that there was any previous instruction or
2642 label. If PRESERVE is non-zero, it remembers enough information to
2643 know whether nops are needed before a noreorder section. */
2646 mips_no_prev_insn (int preserve)
2650 prev_insn.insn_mo = &dummy_opcode;
2651 prev_prev_insn.insn_mo = &dummy_opcode;
2652 prev_nop_frag = NULL;
2653 prev_nop_frag_holds = 0;
2654 prev_nop_frag_required = 0;
2655 prev_nop_frag_since = 0;
2657 prev_insn_valid = 0;
2658 prev_insn_is_delay_slot = 0;
2659 prev_insn_unreordered = 0;
2660 prev_insn_extended = 0;
2661 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2662 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2663 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2664 prev_prev_insn_unreordered = 0;
2665 mips_clear_insn_labels ();
2668 /* This function must be called whenever we turn on noreorder or emit
2669 something other than instructions. It inserts any NOPS which might
2670 be needed by the previous instruction, and clears the information
2671 kept for the previous instructions. The INSNS parameter is true if
2672 instructions are to follow. */
2675 mips_emit_delays (bfd_boolean insns)
2677 if (! mips_opts.noreorder)
2682 if ((! mips_opts.mips16
2683 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2684 && (! cop_interlocks
2685 && (prev_insn.insn_mo->pinfo
2686 & (INSN_LOAD_COPROC_DELAY
2687 | INSN_COPROC_MOVE_DELAY
2688 | INSN_WRITE_COND_CODE))))
2689 || (! hilo_interlocks
2690 && (prev_insn.insn_mo->pinfo
2693 || (! mips_opts.mips16
2695 && (prev_insn.insn_mo->pinfo
2696 & INSN_LOAD_MEMORY_DELAY))
2697 || (! mips_opts.mips16
2698 && mips_opts.isa == ISA_MIPS1
2699 && (prev_insn.insn_mo->pinfo
2700 & INSN_COPROC_MEMORY_DELAY)))
2702 /* Itbl support may require additional care here. */
2704 if ((! mips_opts.mips16
2705 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2706 && (! cop_interlocks
2707 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2708 || (! hilo_interlocks
2709 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2710 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2713 if (prev_insn_unreordered)
2716 else if ((! mips_opts.mips16
2717 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2718 && (! cop_interlocks
2719 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2720 || (! hilo_interlocks
2721 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2722 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2724 /* Itbl support may require additional care here. */
2725 if (! prev_prev_insn_unreordered)
2729 if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
2732 const char *pn = prev_insn.insn_mo->name;
2733 if (strncmp(pn, "macc", 4) == 0
2734 || strncmp(pn, "dmacc", 5) == 0
2735 || strncmp(pn, "dmult", 5) == 0)
2739 if (nops < min_nops)
2745 struct insn_label_list *l;
2749 /* Record the frag which holds the nop instructions, so
2750 that we can remove them if we don't need them. */
2751 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2752 prev_nop_frag = frag_now;
2753 prev_nop_frag_holds = nops;
2754 prev_nop_frag_required = 0;
2755 prev_nop_frag_since = 0;
2758 for (; nops > 0; --nops)
2763 /* Move on to a new frag, so that it is safe to simply
2764 decrease the size of prev_nop_frag. */
2765 frag_wane (frag_now);
2769 for (l = insn_labels; l != NULL; l = l->next)
2773 assert (S_GET_SEGMENT (l->label) == now_seg);
2774 symbol_set_frag (l->label, frag_now);
2775 val = (valueT) frag_now_fix ();
2776 /* mips16 text labels are stored as odd. */
2777 if (mips_opts.mips16)
2779 S_SET_VALUE (l->label, val);
2784 /* Mark instruction labels in mips16 mode. */
2786 mips16_mark_labels ();
2788 mips_no_prev_insn (insns);
2791 /* Build an instruction created by a macro expansion. This is passed
2792 a pointer to the count of instructions created so far, an
2793 expression, the name of the instruction to build, an operand format
2794 string, and corresponding arguments. */
2797 macro_build (char *place, int *counter, expressionS *ep, const char *name,
2798 const char *fmt, ...)
2800 struct mips_cl_insn insn;
2801 bfd_reloc_code_real_type r[3];
2804 va_start (args, fmt);
2807 * If the macro is about to expand into a second instruction,
2808 * print a warning if needed. We need to pass ip as a parameter
2809 * to generate a better warning message here...
2811 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2812 as_warn (_("Macro instruction expanded into multiple instructions"));
2815 * If the macro is about to expand into a second instruction,
2816 * and it is in a delay slot, print a warning.
2820 && mips_opts.noreorder
2821 && (prev_prev_insn.insn_mo->pinfo
2822 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2823 | INSN_COND_BRANCH_LIKELY)) != 0)
2824 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2827 ++*counter; /* bump instruction counter */
2829 if (mips_opts.mips16)
2831 mips16_macro_build (place, counter, ep, name, fmt, args);
2836 r[0] = BFD_RELOC_UNUSED;
2837 r[1] = BFD_RELOC_UNUSED;
2838 r[2] = BFD_RELOC_UNUSED;
2839 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2840 assert (insn.insn_mo);
2841 assert (strcmp (name, insn.insn_mo->name) == 0);
2843 /* Search until we get a match for NAME. */
2846 /* It is assumed here that macros will never generate
2847 MDMX or MIPS-3D instructions. */
2848 if (strcmp (fmt, insn.insn_mo->args) == 0
2849 && insn.insn_mo->pinfo != INSN_MACRO
2850 && OPCODE_IS_MEMBER (insn.insn_mo,
2852 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
2854 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2858 assert (insn.insn_mo->name);
2859 assert (strcmp (name, insn.insn_mo->name) == 0);
2862 insn.insn_opcode = insn.insn_mo->match;
2878 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2882 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2887 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2893 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2898 int tmp = va_arg (args, int);
2900 insn.insn_opcode |= tmp << OP_SH_RT;
2901 insn.insn_opcode |= tmp << OP_SH_RD;
2907 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2914 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2918 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2922 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2926 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2930 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2937 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2943 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2944 assert (*r == BFD_RELOC_GPREL16
2945 || *r == BFD_RELOC_MIPS_LITERAL
2946 || *r == BFD_RELOC_MIPS_HIGHER
2947 || *r == BFD_RELOC_HI16_S
2948 || *r == BFD_RELOC_LO16
2949 || *r == BFD_RELOC_MIPS_GOT16
2950 || *r == BFD_RELOC_MIPS_CALL16
2951 || *r == BFD_RELOC_MIPS_GOT_DISP
2952 || *r == BFD_RELOC_MIPS_GOT_PAGE
2953 || *r == BFD_RELOC_MIPS_GOT_OFST
2954 || *r == BFD_RELOC_MIPS_GOT_LO16
2955 || *r == BFD_RELOC_MIPS_CALL_LO16
2956 || (ep->X_op == O_subtract
2957 && *r == BFD_RELOC_PCREL_LO16));
2961 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2963 && (ep->X_op == O_constant
2964 || (ep->X_op == O_symbol
2965 && (*r == BFD_RELOC_MIPS_HIGHEST
2966 || *r == BFD_RELOC_HI16_S
2967 || *r == BFD_RELOC_HI16
2968 || *r == BFD_RELOC_GPREL16
2969 || *r == BFD_RELOC_MIPS_GOT_HI16
2970 || *r == BFD_RELOC_MIPS_CALL_HI16))
2971 || (ep->X_op == O_subtract
2972 && *r == BFD_RELOC_PCREL_HI16_S)));
2976 assert (ep != NULL);
2978 * This allows macro() to pass an immediate expression for
2979 * creating short branches without creating a symbol.
2980 * Note that the expression still might come from the assembly
2981 * input, in which case the value is not checked for range nor
2982 * is a relocation entry generated (yuck).
2984 if (ep->X_op == O_constant)
2986 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2990 *r = BFD_RELOC_16_PCREL_S2;
2994 assert (ep != NULL);
2995 *r = BFD_RELOC_MIPS_JMP;
2999 insn.insn_opcode |= va_arg (args, unsigned long);
3008 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3010 append_insn (place, &insn, ep, r);
3014 mips16_macro_build (char *place, int *counter ATTRIBUTE_UNUSED,
3015 expressionS *ep, const char *name, const char *fmt,
3018 struct mips_cl_insn insn;
3019 bfd_reloc_code_real_type r[3]
3020 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3022 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3023 assert (insn.insn_mo);
3024 assert (strcmp (name, insn.insn_mo->name) == 0);
3026 while (strcmp (fmt, insn.insn_mo->args) != 0
3027 || insn.insn_mo->pinfo == INSN_MACRO)
3030 assert (insn.insn_mo->name);
3031 assert (strcmp (name, insn.insn_mo->name) == 0);
3034 insn.insn_opcode = insn.insn_mo->match;
3035 insn.use_extend = FALSE;
3054 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3059 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3063 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3067 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3077 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3084 regno = va_arg (args, int);
3085 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3086 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3107 assert (ep != NULL);
3109 if (ep->X_op != O_constant)
3110 *r = (int) BFD_RELOC_UNUSED + c;
3113 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3114 FALSE, &insn.insn_opcode, &insn.use_extend,
3117 *r = BFD_RELOC_UNUSED;
3123 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3130 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3132 append_insn (place, &insn, ep, r);
3136 * Generate a "jalr" instruction with a relocation hint to the called
3137 * function. This occurs in NewABI PIC code.
3140 macro_build_jalr (int icnt, expressionS *ep)
3149 macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3151 fix_new_exp (frag_now, f - frag_now->fr_literal,
3152 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3156 * Generate a "lui" instruction.
3159 macro_build_lui (char *place, int *counter, expressionS *ep, int regnum)
3161 expressionS high_expr;
3162 struct mips_cl_insn insn;
3163 bfd_reloc_code_real_type r[3]
3164 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3165 const char *name = "lui";
3166 const char *fmt = "t,u";
3168 assert (! mips_opts.mips16);
3174 high_expr.X_op = O_constant;
3175 high_expr.X_add_number = ep->X_add_number;
3178 if (high_expr.X_op == O_constant)
3180 /* we can compute the instruction now without a relocation entry */
3181 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3183 *r = BFD_RELOC_UNUSED;
3187 assert (ep->X_op == O_symbol);
3188 /* _gp_disp is a special case, used from s_cpload. */
3189 assert (mips_pic == NO_PIC
3191 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3192 *r = BFD_RELOC_HI16_S;
3196 * If the macro is about to expand into a second instruction,
3197 * print a warning if needed. We need to pass ip as a parameter
3198 * to generate a better warning message here...
3200 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3201 as_warn (_("Macro instruction expanded into multiple instructions"));
3204 ++*counter; /* bump instruction counter */
3206 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3207 assert (insn.insn_mo);
3208 assert (strcmp (name, insn.insn_mo->name) == 0);
3209 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3211 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3212 if (*r == BFD_RELOC_UNUSED)
3214 insn.insn_opcode |= high_expr.X_add_number;
3215 append_insn (place, &insn, NULL, r);
3218 append_insn (place, &insn, &high_expr, r);
3221 /* Generate a sequence of instructions to do a load or store from a constant
3222 offset off of a base register (breg) into/from a target register (treg),
3223 using AT if necessary. */
3225 macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
3226 const char *op, int treg, int breg, int dbl)
3228 assert (ep->X_op == O_constant);
3230 /* Sign-extending 32-bit constants makes their handling easier. */
3232 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3235 /* Right now, this routine can only handle signed 32-bit contants. */
3236 if (! IS_SEXT_32BIT_NUM(ep->X_add_number))
3237 as_warn (_("operand overflow"));
3239 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3241 /* Signed 16-bit offset will fit in the op. Easy! */
3242 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3247 /* 32-bit offset, need multiple instructions and AT, like:
3248 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3249 addu $tempreg,$tempreg,$breg
3250 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3251 to handle the complete offset. */
3252 macro_build_lui (place, counter, ep, AT);
3255 macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
3259 macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
3263 as_warn (_("Macro used $at after \".set noat\""));
3268 * Generates code to set the $at register to true (one)
3269 * if reg is less than the immediate expression.
3272 set_at (int *counter, int reg, int unsignedp)
3274 if (imm_expr.X_op == O_constant
3275 && imm_expr.X_add_number >= -0x8000
3276 && imm_expr.X_add_number < 0x8000)
3277 macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
3278 "t,r,j", AT, reg, BFD_RELOC_LO16);
3281 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3282 macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
3283 "d,v,t", AT, reg, AT);
3287 /* Warn if an expression is not a constant. */
3290 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3292 if (ex->X_op == O_big)
3293 as_bad (_("unsupported large constant"));
3294 else if (ex->X_op != O_constant)
3295 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3298 /* Count the leading zeroes by performing a binary chop. This is a
3299 bulky bit of source, but performance is a LOT better for the
3300 majority of values than a simple loop to count the bits:
3301 for (lcnt = 0; (lcnt < 32); lcnt++)
3302 if ((v) & (1 << (31 - lcnt)))
3304 However it is not code size friendly, and the gain will drop a bit
3305 on certain cached systems.
3307 #define COUNT_TOP_ZEROES(v) \
3308 (((v) & ~0xffff) == 0 \
3309 ? ((v) & ~0xff) == 0 \
3310 ? ((v) & ~0xf) == 0 \
3311 ? ((v) & ~0x3) == 0 \
3312 ? ((v) & ~0x1) == 0 \
3317 : ((v) & ~0x7) == 0 \
3320 : ((v) & ~0x3f) == 0 \
3321 ? ((v) & ~0x1f) == 0 \
3324 : ((v) & ~0x7f) == 0 \
3327 : ((v) & ~0xfff) == 0 \
3328 ? ((v) & ~0x3ff) == 0 \
3329 ? ((v) & ~0x1ff) == 0 \
3332 : ((v) & ~0x7ff) == 0 \
3335 : ((v) & ~0x3fff) == 0 \
3336 ? ((v) & ~0x1fff) == 0 \
3339 : ((v) & ~0x7fff) == 0 \
3342 : ((v) & ~0xffffff) == 0 \
3343 ? ((v) & ~0xfffff) == 0 \
3344 ? ((v) & ~0x3ffff) == 0 \
3345 ? ((v) & ~0x1ffff) == 0 \
3348 : ((v) & ~0x7ffff) == 0 \
3351 : ((v) & ~0x3fffff) == 0 \
3352 ? ((v) & ~0x1fffff) == 0 \
3355 : ((v) & ~0x7fffff) == 0 \
3358 : ((v) & ~0xfffffff) == 0 \
3359 ? ((v) & ~0x3ffffff) == 0 \
3360 ? ((v) & ~0x1ffffff) == 0 \
3363 : ((v) & ~0x7ffffff) == 0 \
3366 : ((v) & ~0x3fffffff) == 0 \
3367 ? ((v) & ~0x1fffffff) == 0 \
3370 : ((v) & ~0x7fffffff) == 0 \
3375 * This routine generates the least number of instructions neccessary to load
3376 * an absolute expression value into a register.
3379 load_register (int *counter, int reg, expressionS *ep, int dbl)
3382 expressionS hi32, lo32;
3384 if (ep->X_op != O_big)
3386 assert (ep->X_op == O_constant);
3388 /* Sign-extending 32-bit constants makes their handling easier. */
3390 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3393 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3395 /* We can handle 16 bit signed values with an addiu to
3396 $zero. No need to ever use daddiu here, since $zero and
3397 the result are always correct in 32 bit mode. */
3398 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3402 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3404 /* We can handle 16 bit unsigned values with an ori to
3406 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
3410 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3412 /* 32 bit values require an lui. */
3413 macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3414 if ((ep->X_add_number & 0xffff) != 0)
3415 macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
3421 /* The value is larger than 32 bits. */
3423 if (HAVE_32BIT_GPRS)
3425 as_bad (_("Number (0x%lx) larger than 32 bits"),
3426 (unsigned long) ep->X_add_number);
3427 macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3432 if (ep->X_op != O_big)
3435 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3436 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3437 hi32.X_add_number &= 0xffffffff;
3439 lo32.X_add_number &= 0xffffffff;
3443 assert (ep->X_add_number > 2);
3444 if (ep->X_add_number == 3)
3445 generic_bignum[3] = 0;
3446 else if (ep->X_add_number > 4)
3447 as_bad (_("Number larger than 64 bits"));
3448 lo32.X_op = O_constant;
3449 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3450 hi32.X_op = O_constant;
3451 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3454 if (hi32.X_add_number == 0)
3459 unsigned long hi, lo;
3461 if (hi32.X_add_number == (offsetT) 0xffffffff)
3463 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3465 macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
3469 if (lo32.X_add_number & 0x80000000)
3471 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3473 if (lo32.X_add_number & 0xffff)
3474 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
3480 /* Check for 16bit shifted constant. We know that hi32 is
3481 non-zero, so start the mask on the first bit of the hi32
3486 unsigned long himask, lomask;
3490 himask = 0xffff >> (32 - shift);
3491 lomask = (0xffff << shift) & 0xffffffff;
3495 himask = 0xffff << (shift - 32);
3498 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3499 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3503 tmp.X_op = O_constant;
3505 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3506 | (lo32.X_add_number >> shift));
3508 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3509 macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
3511 macro_build (NULL, counter, NULL,
3512 (shift >= 32) ? "dsll32" : "dsll",
3514 (shift >= 32) ? shift - 32 : shift);
3519 while (shift <= (64 - 16));
3521 /* Find the bit number of the lowest one bit, and store the
3522 shifted value in hi/lo. */
3523 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3524 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3528 while ((lo & 1) == 0)
3533 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3539 while ((hi & 1) == 0)
3548 /* Optimize if the shifted value is a (power of 2) - 1. */
3549 if ((hi == 0 && ((lo + 1) & lo) == 0)
3550 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3552 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3557 /* This instruction will set the register to be all
3559 tmp.X_op = O_constant;
3560 tmp.X_add_number = (offsetT) -1;
3561 macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
3566 macro_build (NULL, counter, NULL,
3567 (bit >= 32) ? "dsll32" : "dsll",
3569 (bit >= 32) ? bit - 32 : bit);
3571 macro_build (NULL, counter, NULL,
3572 (shift >= 32) ? "dsrl32" : "dsrl",
3574 (shift >= 32) ? shift - 32 : shift);
3579 /* Sign extend hi32 before calling load_register, because we can
3580 generally get better code when we load a sign extended value. */
3581 if ((hi32.X_add_number & 0x80000000) != 0)
3582 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3583 load_register (counter, reg, &hi32, 0);
3586 if ((lo32.X_add_number & 0xffff0000) == 0)
3590 macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
3598 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3600 macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
3602 macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
3608 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
3612 mid16.X_add_number >>= 16;
3613 macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
3615 macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3618 if ((lo32.X_add_number & 0xffff) != 0)
3619 macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3623 /* Load an address into a register. */
3626 load_address (int *counter, int reg, expressionS *ep, int *used_at)
3630 if (ep->X_op != O_constant
3631 && ep->X_op != O_symbol)
3633 as_bad (_("expression too complex"));
3634 ep->X_op = O_constant;
3637 if (ep->X_op == O_constant)
3639 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3643 if (mips_pic == NO_PIC)
3645 /* If this is a reference to a GP relative symbol, we want
3646 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3648 lui $reg,<sym> (BFD_RELOC_HI16_S)
3649 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3650 If we have an addend, we always use the latter form.
3652 With 64bit address space and a usable $at we want
3653 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3654 lui $at,<sym> (BFD_RELOC_HI16_S)
3655 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3656 daddiu $at,<sym> (BFD_RELOC_LO16)
3660 If $at is already in use, we use a path which is suboptimal
3661 on superscalar processors.
3662 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3663 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3665 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3667 daddiu $reg,<sym> (BFD_RELOC_LO16)
3669 if (HAVE_64BIT_ADDRESSES)
3671 /* We don't do GP optimization for now because RELAX_ENCODE can't
3672 hold the data for such large chunks. */
3674 if (*used_at == 0 && ! mips_opts.noat)
3676 macro_build (p, counter, ep, "lui", "t,u",
3677 reg, BFD_RELOC_MIPS_HIGHEST);
3678 macro_build (p, counter, ep, "lui", "t,u",
3679 AT, BFD_RELOC_HI16_S);
3680 macro_build (p, counter, ep, "daddiu", "t,r,j",
3681 reg, reg, BFD_RELOC_MIPS_HIGHER);
3682 macro_build (p, counter, ep, "daddiu", "t,r,j",
3683 AT, AT, BFD_RELOC_LO16);
3684 macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
3685 macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
3690 macro_build (p, counter, ep, "lui", "t,u",
3691 reg, BFD_RELOC_MIPS_HIGHEST);
3692 macro_build (p, counter, ep, "daddiu", "t,r,j",
3693 reg, reg, BFD_RELOC_MIPS_HIGHER);
3694 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3695 macro_build (p, counter, ep, "daddiu", "t,r,j",
3696 reg, reg, BFD_RELOC_HI16_S);
3697 macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
3698 macro_build (p, counter, ep, "daddiu", "t,r,j",
3699 reg, reg, BFD_RELOC_LO16);
3704 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3705 && ! nopic_need_relax (ep->X_add_symbol, 1))
3708 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3709 mips_gp_register, BFD_RELOC_GPREL16);
3710 p = frag_var (rs_machine_dependent, 8, 0,
3711 RELAX_ENCODE (4, 8, 0, 4, 0,
3712 mips_opts.warn_about_macros),
3713 ep->X_add_symbol, 0, NULL);
3715 macro_build_lui (p, counter, ep, reg);
3718 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3722 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3726 /* If this is a reference to an external symbol, we want
3727 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3729 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3731 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3732 If there is a constant, it must be added in after.
3734 If we have NewABI, we want
3735 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3736 unless we're referencing a global symbol with a non-zero
3737 offset, in which case cst must be added separately. */
3742 if (ep->X_add_number)
3744 frag_now->tc_frag_data.tc_fr_offset =
3745 ex.X_add_number = ep->X_add_number;
3746 ep->X_add_number = 0;
3747 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
3748 reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3749 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3750 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3751 ex.X_op = O_constant;
3752 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3753 reg, reg, BFD_RELOC_LO16);
3754 p = frag_var (rs_machine_dependent, 8, 0,
3755 RELAX_ENCODE (8, 4, 0, 0, 0,
3756 mips_opts.warn_about_macros),
3757 ep->X_add_symbol, 0, NULL);
3758 ep->X_add_number = ex.X_add_number;
3761 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3762 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3766 /* To avoid confusion in tc_gen_reloc, we must ensure
3767 that this does not become a variant frag. */
3768 frag_wane (frag_now);
3774 ex.X_add_number = ep->X_add_number;
3775 ep->X_add_number = 0;
3777 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3778 BFD_RELOC_MIPS_GOT16,
3780 macro_build (NULL, counter, NULL, "nop", "");
3781 p = frag_var (rs_machine_dependent, 4, 0,
3782 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3783 ep->X_add_symbol, 0, NULL);
3784 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3787 if (ex.X_add_number != 0)
3789 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3790 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3791 ex.X_op = O_constant;
3792 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3793 reg, reg, BFD_RELOC_LO16);
3797 else if (mips_pic == SVR4_PIC)
3802 /* This is the large GOT case. If this is a reference to an
3803 external symbol, we want
3804 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3806 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3808 Otherwise, for a reference to a local symbol in old ABI, we want
3809 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3811 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3812 If there is a constant, it must be added in after.
3814 In the NewABI, for local symbols, with or without offsets, we want:
3815 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3816 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3822 frag_now->tc_frag_data.tc_fr_offset =
3823 ex.X_add_number = ep->X_add_number;
3824 ep->X_add_number = 0;
3825 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3826 BFD_RELOC_MIPS_GOT_HI16);
3827 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3828 reg, mips_gp_register);
3829 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3830 BFD_RELOC_MIPS_GOT_LO16, reg);
3831 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3832 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3833 else if (ex.X_add_number)
3835 ex.X_op = O_constant;
3836 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3837 reg, reg, BFD_RELOC_LO16);
3840 ep->X_add_number = ex.X_add_number;
3841 p = frag_var (rs_machine_dependent, 8, 0,
3842 RELAX_ENCODE (ex.X_add_number ? 16 : 12, 8, 0, 4, 0,
3843 mips_opts.warn_about_macros),
3844 ep->X_add_symbol, 0, NULL);
3845 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3846 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3847 macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3848 reg, BFD_RELOC_MIPS_GOT_OFST);
3852 ex.X_add_number = ep->X_add_number;
3853 ep->X_add_number = 0;
3854 if (reg_needs_delay (mips_gp_register))
3859 macro_build (NULL, counter, ep, "lui", "t,u", reg,
3860 BFD_RELOC_MIPS_GOT_HI16);
3861 macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
3862 reg, mips_gp_register);
3863 macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3864 BFD_RELOC_MIPS_GOT_LO16, reg);
3865 p = frag_var (rs_machine_dependent, 12 + off, 0,
3866 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3867 mips_opts.warn_about_macros),
3868 ep->X_add_symbol, 0, NULL);
3871 /* We need a nop before loading from $gp. This special
3872 check is required because the lui which starts the main
3873 instruction stream does not refer to $gp, and so will not
3874 insert the nop which may be required. */
3875 macro_build (p, counter, NULL, "nop", "");
3878 macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3879 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3881 macro_build (p, counter, NULL, "nop", "");
3883 macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3886 if (ex.X_add_number != 0)
3888 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3889 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3890 ex.X_op = O_constant;
3891 macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
3892 reg, reg, BFD_RELOC_LO16);
3896 else if (mips_pic == EMBEDDED_PIC)
3899 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3901 macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3902 mips_gp_register, BFD_RELOC_GPREL16);
3908 /* Move the contents of register SOURCE into register DEST. */
3911 move_register (int *counter, int dest, int source)
3913 macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
3914 "d,v,t", dest, source, 0);
3919 * This routine implements the seemingly endless macro or synthesized
3920 * instructions and addressing modes in the mips assembly language. Many
3921 * of these macros are simple and are similar to each other. These could
3922 * probably be handled by some kind of table or grammer aproach instead of
3923 * this verbose method. Others are not simple macros but are more like
3924 * optimizing code generation.
3925 * One interesting optimization is when several store macros appear
3926 * consecutivly that would load AT with the upper half of the same address.
3927 * The ensuing load upper instructions are ommited. This implies some kind
3928 * of global optimization. We currently only optimize within a single macro.
3929 * For many of the load and store macros if the address is specified as a
3930 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3931 * first load register 'at' with zero and use it as the base register. The
3932 * mips assembler simply uses register $zero. Just one tiny optimization
3936 macro (struct mips_cl_insn *ip)
3938 register int treg, sreg, dreg, breg;
3954 bfd_reloc_code_real_type r;
3955 int hold_mips_optimize;
3957 assert (! mips_opts.mips16);
3959 treg = (ip->insn_opcode >> 16) & 0x1f;
3960 dreg = (ip->insn_opcode >> 11) & 0x1f;
3961 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3962 mask = ip->insn_mo->mask;
3964 expr1.X_op = O_constant;
3965 expr1.X_op_symbol = NULL;
3966 expr1.X_add_symbol = NULL;
3967 expr1.X_add_number = 1;
3969 /* Umatched fixups should not be put in the same frag as a relaxable
3970 macro. For example, suppose we have:
3974 addiu $4,$4,%lo(l1) # 3
3976 If instructions 1 and 2 were put in the same frag, md_frob_file would
3977 move the fixup for #1 after the fixups for the "unrelaxed" version of
3978 #2. This would confuse tc_gen_reloc, which expects the relocations
3979 for #2 to be the last for that frag.
3981 Also, if tc_gen_reloc sees certain relocations in a variant frag,
3982 it assumes that they belong to a relaxable macro. We mustn't put
3983 other uses of such relocations into a variant frag.
3985 To avoid both problems, finish the current frag it contains a
3986 %reloc() operator. The macro then goes into a new frag. */
3987 if (prev_reloc_op_frag == frag_now)
3989 frag_wane (frag_now);
4003 mips_emit_delays (TRUE);
4004 ++mips_opts.noreorder;
4005 mips_any_noreorder = 1;
4007 expr1.X_add_number = 8;
4008 macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
4010 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4012 move_register (&icnt, dreg, sreg);
4013 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
4016 --mips_opts.noreorder;
4037 if (imm_expr.X_op == O_constant
4038 && imm_expr.X_add_number >= -0x8000
4039 && imm_expr.X_add_number < 0x8000)
4041 macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
4045 load_register (&icnt, AT, &imm_expr, dbl);
4046 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4065 if (imm_expr.X_op == O_constant
4066 && imm_expr.X_add_number >= 0
4067 && imm_expr.X_add_number < 0x10000)
4069 if (mask != M_NOR_I)
4070 macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
4074 macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
4076 macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
4081 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4082 macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
4099 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4101 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
4104 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4105 macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4113 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4119 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4123 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4124 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4131 /* check for > max integer */
4132 maxnum = 0x7fffffff;
4133 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4140 if (imm_expr.X_op == O_constant
4141 && imm_expr.X_add_number >= maxnum
4142 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4145 /* result is always false */
4149 as_warn (_("Branch %s is always false (nop)"),
4151 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4156 as_warn (_("Branch likely %s is always false"),
4158 macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
4162 if (imm_expr.X_op != O_constant)
4163 as_bad (_("Unsupported large constant"));
4164 ++imm_expr.X_add_number;
4168 if (mask == M_BGEL_I)
4170 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4172 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4176 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4178 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4182 maxnum = 0x7fffffff;
4183 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4190 maxnum = - maxnum - 1;
4191 if (imm_expr.X_op == O_constant
4192 && imm_expr.X_add_number <= maxnum
4193 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4196 /* result is always true */
4197 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4198 macro_build (NULL, &icnt, &offset_expr, "b", "p");
4201 set_at (&icnt, sreg, 0);
4202 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4213 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4217 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4218 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4227 && imm_expr.X_op == O_constant
4228 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4230 if (imm_expr.X_op != O_constant)
4231 as_bad (_("Unsupported large constant"));
4232 ++imm_expr.X_add_number;
4236 if (mask == M_BGEUL_I)
4238 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4240 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4242 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4246 set_at (&icnt, sreg, 1);
4247 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4256 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4262 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4266 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4267 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4276 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4282 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4283 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4292 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4298 macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
4302 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
4303 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4310 maxnum = 0x7fffffff;
4311 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4318 if (imm_expr.X_op == O_constant
4319 && imm_expr.X_add_number >= maxnum
4320 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4322 if (imm_expr.X_op != O_constant)
4323 as_bad (_("Unsupported large constant"));
4324 ++imm_expr.X_add_number;
4328 if (mask == M_BLTL_I)
4330 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4332 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4336 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4338 macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
4342 set_at (&icnt, sreg, 0);
4343 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4352 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4358 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
4359 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4368 && imm_expr.X_op == O_constant
4369 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4371 if (imm_expr.X_op != O_constant)
4372 as_bad (_("Unsupported large constant"));
4373 ++imm_expr.X_add_number;
4377 if (mask == M_BLTUL_I)
4379 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4381 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4383 macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
4387 set_at (&icnt, sreg, 1);
4388 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4397 macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
4403 macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
4407 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
4408 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4419 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4423 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
4424 macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
4440 as_warn (_("Divide by zero."));
4442 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4444 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4448 mips_emit_delays (TRUE);
4449 ++mips_opts.noreorder;
4450 mips_any_noreorder = 1;
4453 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4454 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4459 expr1.X_add_number = 8;
4460 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4461 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
4463 macro_build (NULL, &icnt,NULL, "break", "c", 7);
4465 expr1.X_add_number = -1;
4466 macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
4467 AT, 0, BFD_RELOC_LO16);
4468 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4469 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4472 expr1.X_add_number = 1;
4473 macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4475 macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
4479 expr1.X_add_number = 0x80000000;
4480 macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
4485 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
4486 /* We want to close the noreorder block as soon as possible, so
4487 that later insns are available for delay slot filling. */
4488 --mips_opts.noreorder;
4492 expr1.X_add_number = 8;
4493 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4494 macro_build (NULL, &icnt, NULL, "nop", "", 0);
4496 /* We want to close the noreorder block as soon as possible, so
4497 that later insns are available for delay slot filling. */
4498 --mips_opts.noreorder;
4500 macro_build (NULL, &icnt, NULL, "break", "c", 6);
4502 macro_build (NULL, &icnt, NULL, s, "d", dreg);
4541 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4543 as_warn (_("Divide by zero."));
4545 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
4547 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4550 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4552 if (strcmp (s2, "mflo") == 0)
4553 move_register (&icnt, dreg, sreg);
4555 move_register (&icnt, dreg, 0);
4558 if (imm_expr.X_op == O_constant
4559 && imm_expr.X_add_number == -1
4560 && s[strlen (s) - 1] != 'u')
4562 if (strcmp (s2, "mflo") == 0)
4564 macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
4568 move_register (&icnt, dreg, 0);
4572 load_register (&icnt, AT, &imm_expr, dbl);
4573 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
4574 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4593 mips_emit_delays (TRUE);
4594 ++mips_opts.noreorder;
4595 mips_any_noreorder = 1;
4598 macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
4599 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4600 /* We want to close the noreorder block as soon as possible, so
4601 that later insns are available for delay slot filling. */
4602 --mips_opts.noreorder;
4606 expr1.X_add_number = 8;
4607 macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4608 macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4610 /* We want to close the noreorder block as soon as possible, so
4611 that later insns are available for delay slot filling. */
4612 --mips_opts.noreorder;
4613 macro_build (NULL, &icnt, NULL, "break", "c", 7);
4615 macro_build (NULL, &icnt, NULL, s2, "d", dreg);
4621 /* Load the address of a symbol into a register. If breg is not
4622 zero, we then add a base register to it. */
4624 if (dbl && HAVE_32BIT_GPRS)
4625 as_warn (_("dla used to load 32-bit register"));
4627 if (! dbl && HAVE_64BIT_OBJECTS)
4628 as_warn (_("la used to load 64-bit address"));
4630 if (offset_expr.X_op == O_constant
4631 && offset_expr.X_add_number >= -0x8000
4632 && offset_expr.X_add_number < 0x8000)
4634 macro_build (NULL, &icnt, &offset_expr,
4635 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4636 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4651 /* When generating embedded PIC code, we permit expressions of
4654 la $treg,foo-bar($breg)
4655 where bar is an address in the current section. These are used
4656 when getting the addresses of functions. We don't permit
4657 X_add_number to be non-zero, because if the symbol is
4658 external the relaxing code needs to know that any addend is
4659 purely the offset to X_op_symbol. */
4660 if (mips_pic == EMBEDDED_PIC
4661 && offset_expr.X_op == O_subtract
4662 && (symbol_constant_p (offset_expr.X_op_symbol)
4663 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4664 : (symbol_equated_p (offset_expr.X_op_symbol)
4666 (symbol_get_value_expression (offset_expr.X_op_symbol)
4669 && (offset_expr.X_add_number == 0
4670 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4676 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4677 BFD_RELOC_PCREL_HI16_S);
4681 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
4682 BFD_RELOC_PCREL_HI16_S);
4683 macro_build (NULL, &icnt, NULL,
4684 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4685 "d,v,t", tempreg, tempreg, breg);
4687 macro_build (NULL, &icnt, &offset_expr,
4688 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4689 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4695 if (offset_expr.X_op != O_symbol
4696 && offset_expr.X_op != O_constant)
4698 as_bad (_("expression too complex"));
4699 offset_expr.X_op = O_constant;
4702 if (offset_expr.X_op == O_constant)
4703 load_register (&icnt, tempreg, &offset_expr,
4704 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4705 ? (dbl || HAVE_64BIT_ADDRESSES)
4706 : HAVE_64BIT_ADDRESSES));
4707 else if (mips_pic == NO_PIC)
4709 /* If this is a reference to a GP relative symbol, we want
4710 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4712 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4713 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4714 If we have a constant, we need two instructions anyhow,
4715 so we may as well always use the latter form.
4717 With 64bit address space and a usable $at we want
4718 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4719 lui $at,<sym> (BFD_RELOC_HI16_S)
4720 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4721 daddiu $at,<sym> (BFD_RELOC_LO16)
4723 daddu $tempreg,$tempreg,$at
4725 If $at is already in use, we use a path which is suboptimal
4726 on superscalar processors.
4727 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4728 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4730 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4732 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4735 if (HAVE_64BIT_ADDRESSES)
4737 /* We don't do GP optimization for now because RELAX_ENCODE can't
4738 hold the data for such large chunks. */
4740 if (used_at == 0 && ! mips_opts.noat)
4742 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4743 tempreg, BFD_RELOC_MIPS_HIGHEST);
4744 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4745 AT, BFD_RELOC_HI16_S);
4746 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4747 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4748 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4749 AT, AT, BFD_RELOC_LO16);
4750 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
4751 tempreg, tempreg, 0);
4752 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
4753 tempreg, tempreg, AT);
4758 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4759 tempreg, BFD_RELOC_MIPS_HIGHEST);
4760 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4761 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4762 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4763 tempreg, tempreg, 16);
4764 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4765 tempreg, tempreg, BFD_RELOC_HI16_S);
4766 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
4767 tempreg, tempreg, 16);
4768 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4769 tempreg, tempreg, BFD_RELOC_LO16);
4774 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4775 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4778 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4779 "t,r,j", tempreg, mips_gp_register,
4781 p = frag_var (rs_machine_dependent, 8, 0,
4782 RELAX_ENCODE (4, 8, 0, 4, 0,
4783 mips_opts.warn_about_macros),
4784 offset_expr.X_add_symbol, 0, NULL);
4786 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4789 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
4790 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4793 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
4795 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4797 /* If this is a reference to an external symbol, and there
4798 is no constant, we want
4799 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4800 or if tempreg is PIC_CALL_REG
4801 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4802 For a local symbol, we want
4803 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4805 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4807 If we have a small constant, and this is a reference to
4808 an external symbol, we want
4809 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4811 addiu $tempreg,$tempreg,<constant>
4812 For a local symbol, we want the same instruction
4813 sequence, but we output a BFD_RELOC_LO16 reloc on the
4816 If we have a large constant, and this is a reference to
4817 an external symbol, we want
4818 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4819 lui $at,<hiconstant>
4820 addiu $at,$at,<loconstant>
4821 addu $tempreg,$tempreg,$at
4822 For a local symbol, we want the same instruction
4823 sequence, but we output a BFD_RELOC_LO16 reloc on the
4827 expr1.X_add_number = offset_expr.X_add_number;
4828 offset_expr.X_add_number = 0;
4830 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4831 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4832 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
4833 tempreg, lw_reloc_type, mips_gp_register);
4834 if (expr1.X_add_number == 0)
4843 /* We're going to put in an addu instruction using
4844 tempreg, so we may as well insert the nop right
4846 macro_build (NULL, &icnt, NULL, "nop", "");
4849 p = frag_var (rs_machine_dependent, 8 - off, 0,
4850 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4852 ? mips_opts.warn_about_macros
4854 offset_expr.X_add_symbol, 0, NULL);
4857 macro_build (p, &icnt, NULL, "nop", "");
4860 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
4861 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4862 /* FIXME: If breg == 0, and the next instruction uses
4863 $tempreg, then if this variant case is used an extra
4864 nop will be generated. */
4866 else if (expr1.X_add_number >= -0x8000
4867 && expr1.X_add_number < 0x8000)
4869 macro_build (NULL, &icnt, NULL, "nop", "");
4870 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
4871 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4872 frag_var (rs_machine_dependent, 0, 0,
4873 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4874 offset_expr.X_add_symbol, 0, NULL);
4880 /* If we are going to add in a base register, and the
4881 target register and the base register are the same,
4882 then we are using AT as a temporary register. Since
4883 we want to load the constant into AT, we add our
4884 current AT (from the global offset table) and the
4885 register into the register now, and pretend we were
4886 not using a base register. */
4891 macro_build (NULL, &icnt, NULL, "nop", "");
4892 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
4899 /* Set mips_optimize around the lui instruction to avoid
4900 inserting an unnecessary nop after the lw. */
4901 hold_mips_optimize = mips_optimize;
4903 macro_build_lui (NULL, &icnt, &expr1, AT);
4904 mips_optimize = hold_mips_optimize;
4906 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
4907 AT, AT, BFD_RELOC_LO16);
4908 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
4909 tempreg, tempreg, AT);
4910 frag_var (rs_machine_dependent, 0, 0,
4911 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4912 offset_expr.X_add_symbol, 0, NULL);
4916 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
4919 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
4922 /* If this is a reference to an external, and there is no
4923 constant, or local symbol (*), with or without a
4925 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4926 or if tempreg is PIC_CALL_REG
4927 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4929 If we have a small constant, and this is a reference to
4930 an external symbol, we want
4931 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4932 addiu $tempreg,$tempreg,<constant>
4934 If we have a large constant, and this is a reference to
4935 an external symbol, we want
4936 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4937 lui $at,<hiconstant>
4938 addiu $at,$at,<loconstant>
4939 addu $tempreg,$tempreg,$at
4941 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
4942 local symbols, even though it introduces an additional
4946 if (offset_expr.X_add_number == 0 && tempreg == PIC_CALL_REG)
4947 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4948 if (offset_expr.X_add_number)
4950 frag_now->tc_frag_data.tc_fr_offset =
4951 expr1.X_add_number = offset_expr.X_add_number;
4952 offset_expr.X_add_number = 0;
4954 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
4955 "t,o(b)", tempreg, lw_reloc_type,
4958 if (expr1.X_add_number >= -0x8000
4959 && expr1.X_add_number < 0x8000)
4961 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
4962 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
4963 p = frag_var (rs_machine_dependent, 4, 0,
4964 RELAX_ENCODE (8, 4, 0, 0, 0, 0),
4965 offset_expr.X_add_symbol, 0, NULL);
4967 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number))
4971 /* If we are going to add in a base register, and the
4972 target register and the base register are the same,
4973 then we are using AT as a temporary register. Since
4974 we want to load the constant into AT, we add our
4975 current AT (from the global offset table) and the
4976 register into the register now, and pretend we were
4977 not using a base register. */
4982 assert (tempreg == AT);
4983 macro_build (NULL, &icnt,NULL, ADDRESS_ADD_INSN,
4984 "d,v,t", treg, AT, breg);
4989 macro_build_lui (NULL, &icnt, &expr1, AT);
4990 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
4991 "t,r,j", AT, AT, BFD_RELOC_LO16);
4992 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
4995 p = frag_var (rs_machine_dependent, 4 + adj, 0,
4996 RELAX_ENCODE (16 + adj, 4 + adj,
4998 offset_expr.X_add_symbol, 0, NULL);
5003 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5005 offset_expr.X_add_number = expr1.X_add_number;
5007 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5008 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
5012 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5013 treg, tempreg, breg);
5020 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5021 "t,o(b)", tempreg, lw_reloc_type,
5023 if (lw_reloc_type != BFD_RELOC_MIPS_GOT_DISP)
5024 p = frag_var (rs_machine_dependent, 0, 0,
5025 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5026 offset_expr.X_add_symbol, 0, NULL);
5031 /* To avoid confusion in tc_gen_reloc, we must ensure
5032 that this does not become a variant frag. */
5033 frag_wane (frag_now);
5037 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5041 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5042 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5043 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5045 /* This is the large GOT case. If this is a reference to an
5046 external symbol, and there is no constant, we want
5047 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5048 addu $tempreg,$tempreg,$gp
5049 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5050 or if tempreg is PIC_CALL_REG
5051 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5052 addu $tempreg,$tempreg,$gp
5053 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5054 For a local symbol, we want
5055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5057 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5059 If we have a small constant, and this is a reference to
5060 an external symbol, we want
5061 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5062 addu $tempreg,$tempreg,$gp
5063 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5065 addiu $tempreg,$tempreg,<constant>
5066 For a local symbol, we want
5067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5069 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5071 If we have a large constant, and this is a reference to
5072 an external symbol, we want
5073 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5074 addu $tempreg,$tempreg,$gp
5075 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5076 lui $at,<hiconstant>
5077 addiu $at,$at,<loconstant>
5078 addu $tempreg,$tempreg,$at
5079 For a local symbol, we want
5080 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5081 lui $at,<hiconstant>
5082 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5083 addu $tempreg,$tempreg,$at
5086 expr1.X_add_number = offset_expr.X_add_number;
5087 offset_expr.X_add_number = 0;
5089 if (reg_needs_delay (mips_gp_register))
5093 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5095 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5096 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5098 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5099 tempreg, lui_reloc_type);
5100 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5101 tempreg, tempreg, mips_gp_register);
5102 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5103 tempreg, lw_reloc_type, tempreg);
5104 if (expr1.X_add_number == 0)
5112 /* We're going to put in an addu instruction using
5113 tempreg, so we may as well insert the nop right
5115 macro_build (NULL, &icnt, NULL, "nop", "");
5119 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5120 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
5123 ? mips_opts.warn_about_macros
5125 offset_expr.X_add_symbol, 0, NULL);
5127 else if (expr1.X_add_number >= -0x8000
5128 && expr1.X_add_number < 0x8000)
5130 macro_build (NULL, &icnt, NULL, "nop", "");
5131 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5132 tempreg, tempreg, BFD_RELOC_LO16);
5134 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5135 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
5137 ? mips_opts.warn_about_macros
5139 offset_expr.X_add_symbol, 0, NULL);
5145 /* If we are going to add in a base register, and the
5146 target register and the base register are the same,
5147 then we are using AT as a temporary register. Since
5148 we want to load the constant into AT, we add our
5149 current AT (from the global offset table) and the
5150 register into the register now, and pretend we were
5151 not using a base register. */
5159 assert (tempreg == AT);
5160 macro_build (NULL, &icnt, NULL, "nop", "");
5161 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5167 /* Set mips_optimize around the lui instruction to avoid
5168 inserting an unnecessary nop after the lw. */
5169 hold_mips_optimize = mips_optimize;
5171 macro_build_lui (NULL, &icnt, &expr1, AT);
5172 mips_optimize = hold_mips_optimize;
5174 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5175 AT, AT, BFD_RELOC_LO16);
5176 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5179 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5180 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5183 ? mips_opts.warn_about_macros
5185 offset_expr.X_add_symbol, 0, NULL);
5192 /* This is needed because this instruction uses $gp, but
5193 the first instruction on the main stream does not. */
5194 macro_build (p, &icnt, NULL, "nop", "");
5198 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5199 tempreg, local_reloc_type, mips_gp_register);
5201 if (expr1.X_add_number >= -0x8000
5202 && expr1.X_add_number < 0x8000)
5204 macro_build (p, &icnt, NULL, "nop", "");
5206 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN,
5207 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
5208 /* FIXME: If add_number is 0, and there was no base
5209 register, the external symbol case ended with a load,
5210 so if the symbol turns out to not be external, and
5211 the next instruction uses tempreg, an unnecessary nop
5212 will be inserted. */
5218 /* We must add in the base register now, as in the
5219 external symbol case. */
5220 assert (tempreg == AT);
5221 macro_build (p, &icnt, NULL, "nop", "");
5223 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5227 /* We set breg to 0 because we have arranged to add
5228 it in in both cases. */
5232 macro_build_lui (p, &icnt, &expr1, AT);
5234 macro_build (p, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5235 AT, AT, BFD_RELOC_LO16);
5237 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5238 tempreg, tempreg, AT);
5242 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5245 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5246 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5249 /* This is the large GOT case. If this is a reference to an
5250 external symbol, and there is no constant, we want
5251 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5252 add $tempreg,$tempreg,$gp
5253 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5254 or if tempreg is PIC_CALL_REG
5255 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5256 add $tempreg,$tempreg,$gp
5257 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5259 If we have a small constant, and this is a reference to
5260 an external symbol, we want
5261 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5262 add $tempreg,$tempreg,$gp
5263 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5264 addi $tempreg,$tempreg,<constant>
5266 If we have a large constant, and this is a reference to
5267 an external symbol, we want
5268 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5269 addu $tempreg,$tempreg,$gp
5270 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5271 lui $at,<hiconstant>
5272 addi $at,$at,<loconstant>
5273 add $tempreg,$tempreg,$at
5275 If we have NewABI, and we know it's a local symbol, we want
5276 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5277 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5278 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5282 frag_now->tc_frag_data.tc_fr_offset =
5283 expr1.X_add_number = offset_expr.X_add_number;
5284 offset_expr.X_add_number = 0;
5286 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
5288 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5289 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5291 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5292 tempreg, lui_reloc_type);
5293 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5294 tempreg, tempreg, mips_gp_register);
5295 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5296 "t,o(b)", tempreg, lw_reloc_type, tempreg);
5298 if (expr1.X_add_number == 0)
5300 p = frag_var (rs_machine_dependent, 8, 0,
5301 RELAX_ENCODE (12, 8, 0, 4, 0,
5302 mips_opts.warn_about_macros),
5303 offset_expr.X_add_symbol, 0, NULL);
5305 else if (expr1.X_add_number >= -0x8000
5306 && expr1.X_add_number < 0x8000)
5308 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
5309 tempreg, tempreg, BFD_RELOC_LO16);
5310 p = frag_var (rs_machine_dependent, 8, 0,
5311 RELAX_ENCODE (16, 8, 0, 4, 0,
5312 mips_opts.warn_about_macros),
5313 offset_expr.X_add_symbol, 0, NULL);
5315 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number))
5319 /* If we are going to add in a base register, and the
5320 target register and the base register are the same,
5321 then we are using AT as a temporary register. Since
5322 we want to load the constant into AT, we add our
5323 current AT (from the global offset table) and the
5324 register into the register now, and pretend we were
5325 not using a base register. */
5330 assert (tempreg == AT);
5331 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5337 /* Set mips_optimize around the lui instruction to avoid
5338 inserting an unnecessary nop after the lw. */
5339 macro_build_lui (NULL, &icnt, &expr1, AT);
5340 macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
5341 "t,r,j", AT, AT, BFD_RELOC_LO16);
5342 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5345 p = frag_var (rs_machine_dependent, 8 + adj, 0,
5346 RELAX_ENCODE (24 + adj, 8 + adj,
5349 ? mips_opts.warn_about_macros
5351 offset_expr.X_add_symbol, 0, NULL);
5356 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5358 offset_expr.X_add_number = expr1.X_add_number;
5359 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5360 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5361 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5362 tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
5365 macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5366 treg, tempreg, breg);
5371 else if (mips_pic == EMBEDDED_PIC)
5374 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5376 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5377 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5386 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5387 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5389 s = ADDRESS_ADD_INSN;
5391 macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
5400 /* The j instruction may not be used in PIC code, since it
5401 requires an absolute address. We convert it to a b
5403 if (mips_pic == NO_PIC)
5404 macro_build (NULL, &icnt, &offset_expr, "j", "a");
5406 macro_build (NULL, &icnt, &offset_expr, "b", "p");
5409 /* The jal instructions must be handled as macros because when
5410 generating PIC code they expand to multi-instruction
5411 sequences. Normally they are simple instructions. */
5416 if (mips_pic == NO_PIC
5417 || mips_pic == EMBEDDED_PIC)
5418 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5419 else if (mips_pic == SVR4_PIC)
5421 if (sreg != PIC_CALL_REG)
5422 as_warn (_("MIPS PIC call to register other than $25"));
5424 macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
5427 if (mips_cprestore_offset < 0)
5428 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5431 if (! mips_frame_reg_valid)
5433 as_warn (_("No .frame pseudo-op used in PIC code"));
5434 /* Quiet this warning. */
5435 mips_frame_reg_valid = 1;
5437 if (! mips_cprestore_valid)
5439 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5440 /* Quiet this warning. */
5441 mips_cprestore_valid = 1;
5443 expr1.X_add_number = mips_cprestore_offset;
5444 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5448 HAVE_64BIT_ADDRESSES);
5458 if (mips_pic == NO_PIC)
5459 macro_build (NULL, &icnt, &offset_expr, "jal", "a");
5460 else if (mips_pic == SVR4_PIC)
5464 /* If this is a reference to an external symbol, and we are
5465 using a small GOT, we want
5466 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5470 lw $gp,cprestore($sp)
5471 The cprestore value is set using the .cprestore
5472 pseudo-op. If we are using a big GOT, we want
5473 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5475 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5479 lw $gp,cprestore($sp)
5480 If the symbol is not external, we want
5481 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5483 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5486 lw $gp,cprestore($sp)
5488 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5489 sequences above, minus nops, unless the symbol is local,
5490 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5497 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5498 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5500 frag_var (rs_machine_dependent, 0, 0,
5501 RELAX_ENCODE (0, 0, -4, 0, 0, 0),
5502 offset_expr.X_add_symbol, 0, NULL);
5507 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5508 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5509 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5510 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5511 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5512 "t,o(b)", PIC_CALL_REG,
5513 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5514 p = frag_var (rs_machine_dependent, 8, 0,
5515 RELAX_ENCODE (12, 8, 0, 4, 0, 0),
5516 offset_expr.X_add_symbol, 0, NULL);
5517 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5518 "t,o(b)", PIC_CALL_REG,
5519 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5520 macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5521 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5522 BFD_RELOC_MIPS_GOT_OFST);
5525 macro_build_jalr (icnt, &offset_expr);
5532 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5533 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5535 macro_build (NULL, &icnt, NULL, "nop", "");
5536 p = frag_var (rs_machine_dependent, 4, 0,
5537 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5538 offset_expr.X_add_symbol, 0, NULL);
5544 if (reg_needs_delay (mips_gp_register))
5548 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
5549 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
5550 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
5551 PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
5552 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5553 "t,o(b)", PIC_CALL_REG,
5554 BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5555 macro_build (NULL, &icnt, NULL, "nop", "");
5556 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5557 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5559 offset_expr.X_add_symbol, 0, NULL);
5562 macro_build (p, &icnt, NULL, "nop", "");
5565 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
5566 "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5569 macro_build (p, &icnt, NULL, "nop", "");
5572 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
5573 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5575 macro_build_jalr (icnt, &offset_expr);
5577 if (mips_cprestore_offset < 0)
5578 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5581 if (! mips_frame_reg_valid)
5583 as_warn (_("No .frame pseudo-op used in PIC code"));
5584 /* Quiet this warning. */
5585 mips_frame_reg_valid = 1;
5587 if (! mips_cprestore_valid)
5589 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5590 /* Quiet this warning. */
5591 mips_cprestore_valid = 1;
5593 if (mips_opts.noreorder)
5594 macro_build (NULL, &icnt, NULL, "nop", "");
5595 expr1.X_add_number = mips_cprestore_offset;
5596 macro_build_ldst_constoffset (NULL, &icnt, &expr1,
5600 HAVE_64BIT_ADDRESSES);
5604 else if (mips_pic == EMBEDDED_PIC)
5606 macro_build (NULL, &icnt, &offset_expr, "bal", "p");
5607 /* The linker may expand the call to a longer sequence which
5608 uses $at, so we must break rather than return. */
5633 /* Itbl support may require additional care here. */
5638 /* Itbl support may require additional care here. */
5643 /* Itbl support may require additional care here. */
5648 /* Itbl support may require additional care here. */
5660 if (mips_opts.arch == CPU_R4650)
5662 as_bad (_("opcode not supported on this processor"));
5666 /* Itbl support may require additional care here. */
5671 /* Itbl support may require additional care here. */
5676 /* Itbl support may require additional care here. */
5696 if (breg == treg || coproc || lr)
5718 /* Itbl support may require additional care here. */
5723 /* Itbl support may require additional care here. */
5728 /* Itbl support may require additional care here. */
5733 /* Itbl support may require additional care here. */
5749 if (mips_opts.arch == CPU_R4650)
5751 as_bad (_("opcode not supported on this processor"));
5756 /* Itbl support may require additional care here. */
5760 /* Itbl support may require additional care here. */
5765 /* Itbl support may require additional care here. */
5777 /* Itbl support may require additional care here. */
5778 if (mask == M_LWC1_AB
5779 || mask == M_SWC1_AB
5780 || mask == M_LDC1_AB
5781 || mask == M_SDC1_AB
5790 /* Sign-extending 32-bit constants makes their handling easier.
5791 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5793 if ((! HAVE_64BIT_ADDRESSES
5794 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5795 && (offset_expr.X_op == O_constant))
5796 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5797 ^ 0x80000000) - 0x80000000);
5799 /* For embedded PIC, we allow loads where the offset is calculated
5800 by subtracting a symbol in the current segment from an unknown
5801 symbol, relative to a base register, e.g.:
5802 <op> $treg, <sym>-<localsym>($breg)
5803 This is used by the compiler for switch statements. */
5804 if (mips_pic == EMBEDDED_PIC
5805 && offset_expr.X_op == O_subtract
5806 && (symbol_constant_p (offset_expr.X_op_symbol)
5807 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5808 : (symbol_equated_p (offset_expr.X_op_symbol)
5810 (symbol_get_value_expression (offset_expr.X_op_symbol)
5814 && (offset_expr.X_add_number == 0
5815 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5817 /* For this case, we output the instructions:
5818 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5819 addiu $tempreg,$tempreg,$breg
5820 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5821 If the relocation would fit entirely in 16 bits, it would be
5823 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5824 instead, but that seems quite difficult. */
5825 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
5826 BFD_RELOC_PCREL_HI16_S);
5827 macro_build (NULL, &icnt, NULL,
5828 ((bfd_arch_bits_per_address (stdoutput) == 32
5829 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5830 ? "addu" : "daddu"),
5831 "d,v,t", tempreg, tempreg, breg);
5832 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
5833 BFD_RELOC_PCREL_LO16, tempreg);
5839 if (offset_expr.X_op != O_constant
5840 && offset_expr.X_op != O_symbol)
5842 as_bad (_("expression too complex"));
5843 offset_expr.X_op = O_constant;
5846 /* A constant expression in PIC code can be handled just as it
5847 is in non PIC code. */
5848 if (mips_pic == NO_PIC
5849 || offset_expr.X_op == O_constant)
5853 /* If this is a reference to a GP relative symbol, and there
5854 is no base register, we want
5855 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5856 Otherwise, if there is no base register, we want
5857 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5858 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5859 If we have a constant, we need two instructions anyhow,
5860 so we always use the latter form.
5862 If we have a base register, and this is a reference to a
5863 GP relative symbol, we want
5864 addu $tempreg,$breg,$gp
5865 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5867 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5868 addu $tempreg,$tempreg,$breg
5869 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5870 With a constant we always use the latter case.
5872 With 64bit address space and no base register and $at usable,
5874 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5875 lui $at,<sym> (BFD_RELOC_HI16_S)
5876 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5879 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5880 If we have a base register, we want
5881 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5882 lui $at,<sym> (BFD_RELOC_HI16_S)
5883 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5887 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5889 Without $at we can't generate the optimal path for superscalar
5890 processors here since this would require two temporary registers.
5891 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5892 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5894 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5896 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5897 If we have a base register, we want
5898 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5899 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5901 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5903 daddu $tempreg,$tempreg,$breg
5904 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5906 If we have 64-bit addresses, as an optimization, for
5907 addresses which are 32-bit constants (e.g. kseg0/kseg1
5908 addresses) we fall back to the 32-bit address generation
5909 mechanism since it is more efficient. Note that due to
5910 the signed offset used by memory operations, the 32-bit
5911 range is shifted down by 32768 here. This code should
5912 probably attempt to generate 64-bit constants more
5913 efficiently in general.
5915 As an extension for architectures with 64-bit registers,
5916 we don't truncate 64-bit addresses given as literal
5917 constants down to 32 bits, to support existing practice
5918 in the mips64 Linux (the kernel), that compiles source
5919 files with -mabi=64, assembling them as o32 or n32 (with
5920 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5921 the whole kernel is loaded into a memory region that is
5922 addressible with sign-extended 32-bit addresses, it is
5923 wasteful to compute the upper 32 bits of every
5924 non-literal address, that takes more space and time.
5925 Some day this should probably be implemented as an
5926 assembler option, such that the kernel doesn't have to
5927 use such ugly hacks, even though it will still have to
5928 end up converting the binary to ELF32 for a number of
5929 platforms whose boot loaders don't support ELF64
5931 if ((HAVE_64BIT_ADDRESSES
5932 && ! (offset_expr.X_op == O_constant
5933 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5935 && offset_expr.X_op == O_constant
5936 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5940 /* We don't do GP optimization for now because RELAX_ENCODE can't
5941 hold the data for such large chunks. */
5943 if (used_at == 0 && ! mips_opts.noat)
5945 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5946 tempreg, BFD_RELOC_MIPS_HIGHEST);
5947 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5948 AT, BFD_RELOC_HI16_S);
5949 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5950 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5952 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5954 macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
5955 tempreg, tempreg, 0);
5956 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5957 tempreg, tempreg, AT);
5958 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5959 BFD_RELOC_LO16, tempreg);
5964 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5965 tempreg, BFD_RELOC_MIPS_HIGHEST);
5966 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5967 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5968 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
5969 tempreg, tempreg, 16);
5970 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5971 tempreg, tempreg, BFD_RELOC_HI16_S);
5972 macro_build (p, &icnt, NULL, "dsll", "d,w,<",
5973 tempreg, tempreg, 16);
5975 macro_build (p, &icnt, NULL, "daddu", "d,v,t",
5976 tempreg, tempreg, breg);
5977 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5978 BFD_RELOC_LO16, tempreg);
5984 if (offset_expr.X_op == O_constant
5985 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5986 as_bad (_("load/store address overflow (max 32 bits)"));
5990 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5991 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5996 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
5997 BFD_RELOC_GPREL16, mips_gp_register);
5998 p = frag_var (rs_machine_dependent, 8, 0,
5999 RELAX_ENCODE (4, 8, 0, 4, 0,
6000 (mips_opts.warn_about_macros
6002 && mips_opts.noat))),
6003 offset_expr.X_add_symbol, 0, NULL);
6006 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6009 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6010 BFD_RELOC_LO16, tempreg);
6014 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6015 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6020 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6021 tempreg, breg, mips_gp_register);
6022 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6023 BFD_RELOC_GPREL16, tempreg);
6024 p = frag_var (rs_machine_dependent, 12, 0,
6025 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
6026 offset_expr.X_add_symbol, 0, NULL);
6028 macro_build_lui (p, &icnt, &offset_expr, tempreg);
6031 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6032 tempreg, tempreg, breg);
6035 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
6036 BFD_RELOC_LO16, tempreg);
6039 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6042 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6044 /* If this is a reference to an external symbol, we want
6045 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6047 <op> $treg,0($tempreg)
6049 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6051 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6052 <op> $treg,0($tempreg)
6055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6056 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6058 If there is a base register, we add it to $tempreg before
6059 the <op>. If there is a constant, we stick it in the
6060 <op> instruction. We don't handle constants larger than
6061 16 bits, because we have no way to load the upper 16 bits
6062 (actually, we could handle them for the subset of cases
6063 in which we are not using $at). */
6064 assert (offset_expr.X_op == O_symbol);
6067 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6068 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
6071 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6072 tempreg, tempreg, breg);
6073 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6074 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6081 expr1.X_add_number = offset_expr.X_add_number;
6082 offset_expr.X_add_number = 0;
6083 if (expr1.X_add_number < -0x8000
6084 || expr1.X_add_number >= 0x8000)
6085 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6087 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6088 tempreg, lw_reloc_type, mips_gp_register);
6089 macro_build (NULL, &icnt, NULL, "nop", "");
6090 p = frag_var (rs_machine_dependent, 4, 0,
6091 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
6092 offset_expr.X_add_symbol, 0, NULL);
6093 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
6094 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
6096 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6097 tempreg, tempreg, breg);
6098 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6101 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6106 /* If this is a reference to an external symbol, we want
6107 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6108 addu $tempreg,$tempreg,$gp
6109 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6110 <op> $treg,0($tempreg)
6112 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6114 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6115 <op> $treg,0($tempreg)
6116 If there is a base register, we add it to $tempreg before
6117 the <op>. If there is a constant, we stick it in the
6118 <op> instruction. We don't handle constants larger than
6119 16 bits, because we have no way to load the upper 16 bits
6120 (actually, we could handle them for the subset of cases
6121 in which we are not using $at). */
6122 assert (offset_expr.X_op == O_symbol);
6123 expr1.X_add_number = offset_expr.X_add_number;
6124 offset_expr.X_add_number = 0;
6125 if (expr1.X_add_number < -0x8000
6126 || expr1.X_add_number >= 0x8000)
6127 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6128 if (reg_needs_delay (mips_gp_register))
6133 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6134 BFD_RELOC_MIPS_GOT_HI16);
6135 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6136 tempreg, tempreg, mips_gp_register);
6137 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6138 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6139 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
6140 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
6141 offset_expr.X_add_symbol, 0, NULL);
6144 macro_build (p, &icnt, NULL, "nop", "");
6147 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6148 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6150 macro_build (p, &icnt, NULL, "nop", "");
6152 macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6153 tempreg, tempreg, BFD_RELOC_LO16);
6155 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6156 tempreg, tempreg, breg);
6157 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6160 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6163 int bregsz = breg != 0 ? 4 : 0;
6165 /* If this is a reference to an external symbol, we want
6166 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6167 add $tempreg,$tempreg,$gp
6168 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6169 <op> $treg,<ofst>($tempreg)
6170 Otherwise, for local symbols, we want:
6171 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6172 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6173 assert (offset_expr.X_op == O_symbol);
6174 frag_now->tc_frag_data.tc_fr_offset =
6175 expr1.X_add_number = offset_expr.X_add_number;
6176 offset_expr.X_add_number = 0;
6177 if (expr1.X_add_number < -0x8000
6178 || expr1.X_add_number >= 0x8000)
6179 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6181 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
6182 BFD_RELOC_MIPS_GOT_HI16);
6183 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6184 tempreg, tempreg, mips_gp_register);
6185 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6186 tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
6188 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6189 tempreg, tempreg, breg);
6190 macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
6193 offset_expr.X_add_number = expr1.X_add_number;
6194 p = frag_var (rs_machine_dependent, 12 + bregsz, 0,
6195 RELAX_ENCODE (16 + bregsz, 8 + bregsz,
6196 0, 4 + bregsz, 0, 0),
6197 offset_expr.X_add_symbol, 0, NULL);
6198 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6199 tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6201 macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6202 tempreg, tempreg, breg);
6203 macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
6204 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6206 else if (mips_pic == EMBEDDED_PIC)
6208 /* If there is no base register, we want
6209 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6210 If there is a base register, we want
6211 addu $tempreg,$breg,$gp
6212 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6214 assert (offset_expr.X_op == O_symbol);
6217 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6218 BFD_RELOC_GPREL16, mips_gp_register);
6223 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6224 tempreg, breg, mips_gp_register);
6225 macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
6226 BFD_RELOC_GPREL16, tempreg);
6239 load_register (&icnt, treg, &imm_expr, 0);
6243 load_register (&icnt, treg, &imm_expr, 1);
6247 if (imm_expr.X_op == O_constant)
6249 load_register (&icnt, AT, &imm_expr, 0);
6250 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6255 assert (offset_expr.X_op == O_symbol
6256 && strcmp (segment_name (S_GET_SEGMENT
6257 (offset_expr.X_add_symbol)),
6259 && offset_expr.X_add_number == 0);
6260 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
6261 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6266 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6267 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6268 order 32 bits of the value and the low order 32 bits are either
6269 zero or in OFFSET_EXPR. */
6270 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6272 if (HAVE_64BIT_GPRS)
6273 load_register (&icnt, treg, &imm_expr, 1);
6278 if (target_big_endian)
6290 load_register (&icnt, hreg, &imm_expr, 0);
6293 if (offset_expr.X_op == O_absent)
6294 move_register (&icnt, lreg, 0);
6297 assert (offset_expr.X_op == O_constant);
6298 load_register (&icnt, lreg, &offset_expr, 0);
6305 /* We know that sym is in the .rdata section. First we get the
6306 upper 16 bits of the address. */
6307 if (mips_pic == NO_PIC)
6309 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6311 else if (mips_pic == SVR4_PIC)
6313 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6314 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6316 else if (mips_pic == EMBEDDED_PIC)
6318 /* For embedded PIC we pick up the entire address off $gp in
6319 a single instruction. */
6320 macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6321 AT, mips_gp_register, BFD_RELOC_GPREL16);
6322 offset_expr.X_op = O_constant;
6323 offset_expr.X_add_number = 0;
6328 /* Now we load the register(s). */
6329 if (HAVE_64BIT_GPRS)
6330 macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
6331 BFD_RELOC_LO16, AT);
6334 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
6335 BFD_RELOC_LO16, AT);
6338 /* FIXME: How in the world do we deal with the possible
6340 offset_expr.X_add_number += 4;
6341 macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
6342 treg + 1, BFD_RELOC_LO16, AT);
6346 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6347 does not become a variant frag. */
6348 frag_wane (frag_now);
6354 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6355 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6356 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6357 the value and the low order 32 bits are either zero or in
6359 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6361 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
6362 if (HAVE_64BIT_FPRS)
6364 assert (HAVE_64BIT_GPRS);
6365 macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
6369 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
6370 if (offset_expr.X_op == O_absent)
6371 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
6374 assert (offset_expr.X_op == O_constant);
6375 load_register (&icnt, AT, &offset_expr, 0);
6376 macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
6382 assert (offset_expr.X_op == O_symbol
6383 && offset_expr.X_add_number == 0);
6384 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6385 if (strcmp (s, ".lit8") == 0)
6387 if (mips_opts.isa != ISA_MIPS1)
6389 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6390 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6393 breg = mips_gp_register;
6394 r = BFD_RELOC_MIPS_LITERAL;
6399 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6400 if (mips_pic == SVR4_PIC)
6401 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
6402 "t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
6406 /* FIXME: This won't work for a 64 bit address. */
6407 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6410 if (mips_opts.isa != ISA_MIPS1)
6412 macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
6413 BFD_RELOC_LO16, AT);
6415 /* To avoid confusion in tc_gen_reloc, we must ensure
6416 that this does not become a variant frag. */
6417 frag_wane (frag_now);
6428 if (mips_opts.arch == CPU_R4650)
6430 as_bad (_("opcode not supported on this processor"));
6433 /* Even on a big endian machine $fn comes before $fn+1. We have
6434 to adjust when loading from memory. */
6437 assert (mips_opts.isa == ISA_MIPS1);
6438 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6439 target_big_endian ? treg + 1 : treg, r, breg);
6440 /* FIXME: A possible overflow which I don't know how to deal
6442 offset_expr.X_add_number += 4;
6443 macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6444 target_big_endian ? treg : treg + 1, r, breg);
6446 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6447 does not become a variant frag. */
6448 frag_wane (frag_now);
6457 * The MIPS assembler seems to check for X_add_number not
6458 * being double aligned and generating:
6461 * addiu at,at,%lo(foo+1)
6464 * But, the resulting address is the same after relocation so why
6465 * generate the extra instruction?
6467 if (mips_opts.arch == CPU_R4650)
6469 as_bad (_("opcode not supported on this processor"));
6472 /* Itbl support may require additional care here. */
6474 if (mips_opts.isa != ISA_MIPS1)
6485 if (mips_opts.arch == CPU_R4650)
6487 as_bad (_("opcode not supported on this processor"));
6491 if (mips_opts.isa != ISA_MIPS1)
6499 /* Itbl support may require additional care here. */
6504 if (HAVE_64BIT_GPRS)
6515 if (HAVE_64BIT_GPRS)
6525 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6526 loads for the case of doing a pair of loads to simulate an 'ld'.
6527 This is not currently done by the compiler, and assembly coders
6528 writing embedded-pic code can cope. */
6530 if (offset_expr.X_op != O_symbol
6531 && offset_expr.X_op != O_constant)
6533 as_bad (_("expression too complex"));
6534 offset_expr.X_op = O_constant;
6537 /* Even on a big endian machine $fn comes before $fn+1. We have
6538 to adjust when loading from memory. We set coproc if we must
6539 load $fn+1 first. */
6540 /* Itbl support may require additional care here. */
6541 if (! target_big_endian)
6544 if (mips_pic == NO_PIC
6545 || offset_expr.X_op == O_constant)
6549 /* If this is a reference to a GP relative symbol, we want
6550 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6551 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6552 If we have a base register, we use this
6554 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6555 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6556 If this is not a GP relative symbol, we want
6557 lui $at,<sym> (BFD_RELOC_HI16_S)
6558 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6559 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6560 If there is a base register, we add it to $at after the
6561 lui instruction. If there is a constant, we always use
6563 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6564 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6576 tempreg = mips_gp_register;
6583 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6584 AT, breg, mips_gp_register);
6590 /* Itbl support may require additional care here. */
6591 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6592 coproc ? treg + 1 : treg,
6593 BFD_RELOC_GPREL16, tempreg);
6594 offset_expr.X_add_number += 4;
6596 /* Set mips_optimize to 2 to avoid inserting an
6598 hold_mips_optimize = mips_optimize;
6600 /* Itbl support may require additional care here. */
6601 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6602 coproc ? treg : treg + 1,
6603 BFD_RELOC_GPREL16, tempreg);
6604 mips_optimize = hold_mips_optimize;
6606 p = frag_var (rs_machine_dependent, 12 + off, 0,
6607 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6608 used_at && mips_opts.noat),
6609 offset_expr.X_add_symbol, 0, NULL);
6611 /* We just generated two relocs. When tc_gen_reloc
6612 handles this case, it will skip the first reloc and
6613 handle the second. The second reloc already has an
6614 extra addend of 4, which we added above. We must
6615 subtract it out, and then subtract another 4 to make
6616 the first reloc come out right. The second reloc
6617 will come out right because we are going to add 4 to
6618 offset_expr when we build its instruction below.
6620 If we have a symbol, then we don't want to include
6621 the offset, because it will wind up being included
6622 when we generate the reloc. */
6624 if (offset_expr.X_op == O_constant)
6625 offset_expr.X_add_number -= 8;
6628 offset_expr.X_add_number = -4;
6629 offset_expr.X_op = O_constant;
6632 macro_build_lui (p, &icnt, &offset_expr, AT);
6637 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6642 /* Itbl support may require additional care here. */
6643 macro_build (p, &icnt, &offset_expr, s, fmt,
6644 coproc ? treg + 1 : treg,
6645 BFD_RELOC_LO16, AT);
6648 /* FIXME: How do we handle overflow here? */
6649 offset_expr.X_add_number += 4;
6650 /* Itbl support may require additional care here. */
6651 macro_build (p, &icnt, &offset_expr, s, fmt,
6652 coproc ? treg : treg + 1,
6653 BFD_RELOC_LO16, AT);
6655 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6659 /* If this is a reference to an external symbol, we want
6660 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6665 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6667 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6668 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6669 If there is a base register we add it to $at before the
6670 lwc1 instructions. If there is a constant we include it
6671 in the lwc1 instructions. */
6673 expr1.X_add_number = offset_expr.X_add_number;
6674 offset_expr.X_add_number = 0;
6675 if (expr1.X_add_number < -0x8000
6676 || expr1.X_add_number >= 0x8000 - 4)
6677 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6682 frag_grow (24 + off);
6683 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6684 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6685 macro_build (NULL, &icnt, NULL, "nop", "");
6687 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6689 /* Itbl support may require additional care here. */
6690 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6691 BFD_RELOC_LO16, AT);
6692 expr1.X_add_number += 4;
6694 /* Set mips_optimize to 2 to avoid inserting an undesired
6696 hold_mips_optimize = mips_optimize;
6698 /* Itbl support may require additional care here. */
6699 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6700 BFD_RELOC_LO16, AT);
6701 mips_optimize = hold_mips_optimize;
6703 (void) frag_var (rs_machine_dependent, 0, 0,
6704 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6705 offset_expr.X_add_symbol, 0, NULL);
6707 else if (mips_pic == SVR4_PIC)
6712 /* If this is a reference to an external symbol, we want
6713 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6715 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6720 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6722 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6723 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6724 If there is a base register we add it to $at before the
6725 lwc1 instructions. If there is a constant we include it
6726 in the lwc1 instructions. */
6728 expr1.X_add_number = offset_expr.X_add_number;
6729 offset_expr.X_add_number = 0;
6730 if (expr1.X_add_number < -0x8000
6731 || expr1.X_add_number >= 0x8000 - 4)
6732 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6733 if (reg_needs_delay (mips_gp_register))
6742 macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
6743 BFD_RELOC_MIPS_GOT_HI16);
6744 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6745 AT, AT, mips_gp_register);
6746 macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6747 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6748 macro_build (NULL, &icnt, NULL, "nop", "");
6750 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6752 /* Itbl support may require additional care here. */
6753 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6754 BFD_RELOC_LO16, AT);
6755 expr1.X_add_number += 4;
6757 /* Set mips_optimize to 2 to avoid inserting an undesired
6759 hold_mips_optimize = mips_optimize;
6761 /* Itbl support may require additional care here. */
6762 macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6763 BFD_RELOC_LO16, AT);
6764 mips_optimize = hold_mips_optimize;
6765 expr1.X_add_number -= 4;
6767 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6768 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6769 8 + gpdel + off, 1, 0),
6770 offset_expr.X_add_symbol, 0, NULL);
6773 macro_build (p, &icnt, NULL, "nop", "");
6776 macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6777 AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6779 macro_build (p, &icnt, NULL, "nop", "");
6783 macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6787 /* Itbl support may require additional care here. */
6788 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
6789 BFD_RELOC_LO16, AT);
6791 expr1.X_add_number += 4;
6793 /* Set mips_optimize to 2 to avoid inserting an undesired
6795 hold_mips_optimize = mips_optimize;
6797 /* Itbl support may require additional care here. */
6798 macro_build (p, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
6799 BFD_RELOC_LO16, AT);
6800 mips_optimize = hold_mips_optimize;
6802 else if (mips_pic == EMBEDDED_PIC)
6804 /* If there is no base register, we use
6805 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6806 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6807 If we have a base register, we use
6809 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6810 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6814 tempreg = mips_gp_register;
6819 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
6820 AT, breg, mips_gp_register);
6825 /* Itbl support may require additional care here. */
6826 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6827 coproc ? treg + 1 : treg,
6828 BFD_RELOC_GPREL16, tempreg);
6829 offset_expr.X_add_number += 4;
6830 /* Itbl support may require additional care here. */
6831 macro_build (NULL, &icnt, &offset_expr, s, fmt,
6832 coproc ? treg : treg + 1,
6833 BFD_RELOC_GPREL16, tempreg);
6849 assert (HAVE_32BIT_ADDRESSES);
6850 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6851 BFD_RELOC_LO16, breg);
6852 offset_expr.X_add_number += 4;
6853 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6854 BFD_RELOC_LO16, breg);
6857 /* New code added to support COPZ instructions.
6858 This code builds table entries out of the macros in mip_opcodes.
6859 R4000 uses interlocks to handle coproc delays.
6860 Other chips (like the R3000) require nops to be inserted for delays.
6862 FIXME: Currently, we require that the user handle delays.
6863 In order to fill delay slots for non-interlocked chips,
6864 we must have a way to specify delays based on the coprocessor.
6865 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6866 What are the side-effects of the cop instruction?
6867 What cache support might we have and what are its effects?
6868 Both coprocessor & memory require delays. how long???
6869 What registers are read/set/modified?
6871 If an itbl is provided to interpret cop instructions,
6872 this knowledge can be encoded in the itbl spec. */
6886 /* For now we just do C (same as Cz). The parameter will be
6887 stored in insn_opcode by mips_ip. */
6888 macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
6892 move_register (&icnt, dreg, sreg);
6895 #ifdef LOSING_COMPILER
6897 /* Try and see if this is a new itbl instruction.
6898 This code builds table entries out of the macros in mip_opcodes.
6899 FIXME: For now we just assemble the expression and pass it's
6900 value along as a 32-bit immediate.
6901 We may want to have the assembler assemble this value,
6902 so that we gain the assembler's knowledge of delay slots,
6904 Would it be more efficient to use mask (id) here? */
6905 if (itbl_have_entries
6906 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6908 s = ip->insn_mo->name;
6910 coproc = ITBL_DECODE_PNUM (immed_expr);;
6911 macro_build (NULL, &icnt, &immed_expr, s, "C");
6918 as_warn (_("Macro used $at after \".set noat\""));
6922 macro2 (struct mips_cl_insn *ip)
6924 register int treg, sreg, dreg, breg;
6940 bfd_reloc_code_real_type r;
6943 treg = (ip->insn_opcode >> 16) & 0x1f;
6944 dreg = (ip->insn_opcode >> 11) & 0x1f;
6945 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6946 mask = ip->insn_mo->mask;
6948 expr1.X_op = O_constant;
6949 expr1.X_op_symbol = NULL;
6950 expr1.X_add_symbol = NULL;
6951 expr1.X_add_number = 1;
6955 #endif /* LOSING_COMPILER */
6960 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
6962 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
6968 /* The MIPS assembler some times generates shifts and adds. I'm
6969 not trying to be that fancy. GCC should do this for us
6971 load_register (&icnt, AT, &imm_expr, dbl);
6972 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
6974 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
6987 mips_emit_delays (TRUE);
6988 ++mips_opts.noreorder;
6989 mips_any_noreorder = 1;
6991 load_register (&icnt, AT, &imm_expr, dbl);
6992 macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
6993 sreg, imm ? AT : treg);
6994 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
6995 macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
6997 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
6999 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
7002 expr1.X_add_number = 8;
7003 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
7004 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7005 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7007 --mips_opts.noreorder;
7008 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7021 mips_emit_delays (TRUE);
7022 ++mips_opts.noreorder;
7023 mips_any_noreorder = 1;
7025 load_register (&icnt, AT, &imm_expr, dbl);
7026 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
7027 sreg, imm ? AT : treg);
7028 macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
7029 macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
7031 macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
7034 expr1.X_add_number = 8;
7035 macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
7036 macro_build (NULL, &icnt, NULL, "nop", "", 0);
7037 macro_build (NULL, &icnt, NULL, "break", "c", 6);
7039 --mips_opts.noreorder;
7043 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7055 macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
7056 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
7062 macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
7063 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7064 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7065 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7069 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7081 macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
7082 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
7088 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7089 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
7090 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
7091 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7099 if (imm_expr.X_op != O_constant)
7100 as_bad (_("Improper rotate count"));
7101 rot = imm_expr.X_add_number & 0x3f;
7102 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7104 rot = (64 - rot) & 0x3f;
7106 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7107 dreg, sreg, rot - 32);
7109 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7115 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7118 l = (rot < 0x20) ? "dsll" : "dsll32";
7119 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7121 macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
7122 macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
7123 (0x20 - rot) & 0x1f);
7124 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7132 if (imm_expr.X_op != O_constant)
7133 as_bad (_("Improper rotate count"));
7134 rot = imm_expr.X_add_number & 0x1f;
7135 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7137 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
7143 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7146 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
7147 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
7148 (0x20 - rot) & 0x1f);
7149 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7154 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7156 macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
7159 macro_build (NULL, &icnt,NULL, "dsubu", "d,v,t", AT, 0, treg);
7160 macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
7161 macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7162 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7166 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7168 macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
7171 macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
7172 macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
7173 macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
7174 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7182 if (imm_expr.X_op != O_constant)
7183 as_bad (_("Improper rotate count"));
7184 rot = imm_expr.X_add_number & 0x3f;
7185 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7188 macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
7189 dreg, sreg, rot - 32);
7191 macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
7197 macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7200 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7201 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7203 macro_build ( NULL, &icnt,NULL, r, "d,w,<", AT, sreg, rot);
7204 macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
7205 (0x20 - rot) & 0x1f);
7206 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7214 if (imm_expr.X_op != O_constant)
7215 as_bad (_("Improper rotate count"));
7216 rot = imm_expr.X_add_number & 0x1f;
7217 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7219 macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
7224 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
7227 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
7228 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
7229 (0x20 - rot) & 0x1f);
7230 macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
7235 if (mips_opts.arch == CPU_R4650)
7237 as_bad (_("opcode not supported on this processor"));
7240 assert (mips_opts.isa == ISA_MIPS1);
7241 /* Even on a big endian machine $fn comes before $fn+1. We have
7242 to adjust when storing to memory. */
7243 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7244 target_big_endian ? treg + 1 : treg,
7245 BFD_RELOC_LO16, breg);
7246 offset_expr.X_add_number += 4;
7247 macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
7248 target_big_endian ? treg : treg + 1,
7249 BFD_RELOC_LO16, breg);
7254 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
7257 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7261 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7262 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7268 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7270 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
7276 as_warn (_("Instruction %s: result is always false"),
7278 move_register (&icnt, dreg, 0);
7281 if (imm_expr.X_op == O_constant
7282 && imm_expr.X_add_number >= 0
7283 && imm_expr.X_add_number < 0x10000)
7285 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7289 else if (imm_expr.X_op == O_constant
7290 && imm_expr.X_add_number > -0x8000
7291 && imm_expr.X_add_number < 0)
7293 imm_expr.X_add_number = -imm_expr.X_add_number;
7294 macro_build (NULL, &icnt, &imm_expr,
7295 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7296 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7301 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7302 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7305 macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
7311 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7317 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
7318 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7322 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7324 if (imm_expr.X_op == O_constant
7325 && imm_expr.X_add_number >= -0x8000
7326 && imm_expr.X_add_number < 0x8000)
7328 macro_build (NULL, &icnt, &imm_expr,
7329 mask == M_SGE_I ? "slti" : "sltiu",
7330 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7335 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7336 macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
7337 "d,v,t", dreg, sreg, AT);
7340 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7346 case M_SGT: /* sreg > treg <==> treg < sreg */
7352 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7355 case M_SGT_I: /* sreg > I <==> I < sreg */
7361 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7362 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7365 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7371 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
7372 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7376 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7382 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7383 macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
7384 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
7389 if (imm_expr.X_op == O_constant
7390 && imm_expr.X_add_number >= -0x8000
7391 && imm_expr.X_add_number < 0x8000)
7393 macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
7397 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7398 macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
7402 if (imm_expr.X_op == O_constant
7403 && imm_expr.X_add_number >= -0x8000
7404 && imm_expr.X_add_number < 0x8000)
7406 macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
7410 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7411 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
7416 macro_build (NULL, &icnt,NULL, "sltu","d,v,t", dreg, 0, treg);
7418 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7421 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
7422 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7427 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7429 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
7434 as_warn (_("Instruction %s: result is always true"),
7436 macro_build (NULL, &icnt, &expr1,
7437 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7438 "t,r,j", dreg, 0, BFD_RELOC_LO16);
7441 if (imm_expr.X_op == O_constant
7442 && imm_expr.X_add_number >= 0
7443 && imm_expr.X_add_number < 0x10000)
7445 macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
7449 else if (imm_expr.X_op == O_constant
7450 && imm_expr.X_add_number > -0x8000
7451 && imm_expr.X_add_number < 0)
7453 imm_expr.X_add_number = -imm_expr.X_add_number;
7454 macro_build (NULL, &icnt, &imm_expr,
7455 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7456 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7461 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7462 macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
7465 macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
7473 if (imm_expr.X_op == O_constant
7474 && imm_expr.X_add_number > -0x8000
7475 && imm_expr.X_add_number <= 0x8000)
7477 imm_expr.X_add_number = -imm_expr.X_add_number;
7478 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
7479 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7482 load_register (&icnt, AT, &imm_expr, dbl);
7483 macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
7490 if (imm_expr.X_op == O_constant
7491 && imm_expr.X_add_number > -0x8000
7492 && imm_expr.X_add_number <= 0x8000)
7494 imm_expr.X_add_number = -imm_expr.X_add_number;
7495 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
7496 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7499 load_register (&icnt, AT, &imm_expr, dbl);
7500 macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
7522 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7523 macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
7528 assert (mips_opts.isa == ISA_MIPS1);
7529 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7530 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7533 * Is the double cfc1 instruction a bug in the mips assembler;
7534 * or is there a reason for it?
7536 mips_emit_delays (TRUE);
7537 ++mips_opts.noreorder;
7538 mips_any_noreorder = 1;
7539 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7540 macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
7541 macro_build (NULL, &icnt, NULL, "nop", "");
7542 expr1.X_add_number = 3;
7543 macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7545 expr1.X_add_number = 2;
7546 macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7548 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
7549 macro_build (NULL, &icnt, NULL, "nop", "");
7550 macro_build (NULL, &icnt, NULL,
7551 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
7553 macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
7554 macro_build (NULL, &icnt, NULL, "nop", "");
7555 --mips_opts.noreorder;
7564 if (offset_expr.X_add_number >= 0x7fff)
7565 as_bad (_("operand overflow"));
7566 if (! target_big_endian)
7567 ++offset_expr.X_add_number;
7568 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
7569 BFD_RELOC_LO16, breg);
7570 if (! target_big_endian)
7571 --offset_expr.X_add_number;
7573 ++offset_expr.X_add_number;
7574 macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
7575 BFD_RELOC_LO16, breg);
7576 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
7577 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7590 if (offset_expr.X_add_number >= 0x8000 - off)
7591 as_bad (_("operand overflow"));
7596 if (! target_big_endian)
7597 offset_expr.X_add_number += off;
7598 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
7599 BFD_RELOC_LO16, breg);
7600 if (! target_big_endian)
7601 offset_expr.X_add_number -= off;
7603 offset_expr.X_add_number += off;
7604 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
7605 BFD_RELOC_LO16, breg);
7607 /* If necessary, move the result in tempreg the final destination. */
7608 if (treg == tempreg)
7610 /* Protect second load's delay slot. */
7611 if (!gpr_interlocks)
7612 macro_build (NULL, &icnt, NULL, "nop", "");
7613 move_register (&icnt, treg, tempreg);
7627 load_address (&icnt, AT, &offset_expr, &used_at);
7629 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7631 if (! target_big_endian)
7632 expr1.X_add_number = off;
7634 expr1.X_add_number = 0;
7635 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7636 BFD_RELOC_LO16, AT);
7637 if (! target_big_endian)
7638 expr1.X_add_number = 0;
7640 expr1.X_add_number = off;
7641 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7642 BFD_RELOC_LO16, AT);
7648 load_address (&icnt, AT, &offset_expr, &used_at);
7650 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7652 if (target_big_endian)
7653 expr1.X_add_number = 0;
7654 macro_build (NULL, &icnt, &expr1,
7655 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7656 treg, BFD_RELOC_LO16, AT);
7657 if (target_big_endian)
7658 expr1.X_add_number = 1;
7660 expr1.X_add_number = 0;
7661 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
7662 AT, BFD_RELOC_LO16, AT);
7663 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7664 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7668 if (offset_expr.X_add_number >= 0x7fff)
7669 as_bad (_("operand overflow"));
7670 if (target_big_endian)
7671 ++offset_expr.X_add_number;
7672 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7673 BFD_RELOC_LO16, breg);
7674 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
7675 if (target_big_endian)
7676 --offset_expr.X_add_number;
7678 ++offset_expr.X_add_number;
7679 macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7680 BFD_RELOC_LO16, breg);
7693 if (offset_expr.X_add_number >= 0x8000 - off)
7694 as_bad (_("operand overflow"));
7695 if (! target_big_endian)
7696 offset_expr.X_add_number += off;
7697 macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7698 BFD_RELOC_LO16, breg);
7699 if (! target_big_endian)
7700 offset_expr.X_add_number -= off;
7702 offset_expr.X_add_number += off;
7703 macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7704 BFD_RELOC_LO16, breg);
7718 load_address (&icnt, AT, &offset_expr, &used_at);
7720 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7722 if (! target_big_endian)
7723 expr1.X_add_number = off;
7725 expr1.X_add_number = 0;
7726 macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
7727 BFD_RELOC_LO16, AT);
7728 if (! target_big_endian)
7729 expr1.X_add_number = 0;
7731 expr1.X_add_number = off;
7732 macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7733 BFD_RELOC_LO16, AT);
7738 load_address (&icnt, AT, &offset_expr, &used_at);
7740 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
7742 if (! target_big_endian)
7743 expr1.X_add_number = 0;
7744 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7745 BFD_RELOC_LO16, AT);
7746 macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
7747 if (! target_big_endian)
7748 expr1.X_add_number = 1;
7750 expr1.X_add_number = 0;
7751 macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7752 BFD_RELOC_LO16, AT);
7753 if (! target_big_endian)
7754 expr1.X_add_number = 0;
7756 expr1.X_add_number = 1;
7757 macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7758 BFD_RELOC_LO16, AT);
7759 macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
7760 macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
7764 /* FIXME: Check if this is one of the itbl macros, since they
7765 are added dynamically. */
7766 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7770 as_warn (_("Macro used $at after \".set noat\""));
7773 /* Implement macros in mips16 mode. */
7776 mips16_macro (struct mips_cl_insn *ip)
7779 int xreg, yreg, zreg, tmp;
7783 const char *s, *s2, *s3;
7785 mask = ip->insn_mo->mask;
7787 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7788 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7789 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7793 expr1.X_op = O_constant;
7794 expr1.X_op_symbol = NULL;
7795 expr1.X_add_symbol = NULL;
7796 expr1.X_add_number = 1;
7815 mips_emit_delays (TRUE);
7816 ++mips_opts.noreorder;
7817 mips_any_noreorder = 1;
7818 macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
7820 expr1.X_add_number = 2;
7821 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7822 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7824 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7825 since that causes an overflow. We should do that as well,
7826 but I don't see how to do the comparisons without a temporary
7828 --mips_opts.noreorder;
7829 macro_build (NULL, &icnt, NULL, s, "x", zreg);
7848 mips_emit_delays (TRUE);
7849 ++mips_opts.noreorder;
7850 mips_any_noreorder = 1;
7851 macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
7852 expr1.X_add_number = 2;
7853 macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7854 macro_build (NULL, &icnt, NULL, "break", "6", 7);
7855 --mips_opts.noreorder;
7856 macro_build (NULL, &icnt, NULL, s2, "x", zreg);
7862 macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
7864 macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
7872 if (imm_expr.X_op != O_constant)
7873 as_bad (_("Unsupported large constant"));
7874 imm_expr.X_add_number = -imm_expr.X_add_number;
7875 macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
7880 if (imm_expr.X_op != O_constant)
7881 as_bad (_("Unsupported large constant"));
7882 imm_expr.X_add_number = -imm_expr.X_add_number;
7883 macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
7887 if (imm_expr.X_op != O_constant)
7888 as_bad (_("Unsupported large constant"));
7889 imm_expr.X_add_number = -imm_expr.X_add_number;
7890 macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
7912 goto do_reverse_branch;
7916 goto do_reverse_branch;
7928 goto do_reverse_branch;
7939 macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
7940 macro_build (NULL, &icnt, &offset_expr, s2, "p");
7967 goto do_addone_branch_i;
7972 goto do_addone_branch_i;
7987 goto do_addone_branch_i;
7994 if (imm_expr.X_op != O_constant)
7995 as_bad (_("Unsupported large constant"));
7996 ++imm_expr.X_add_number;
7999 macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
8000 macro_build (NULL, &icnt, &offset_expr, s2, "p");
8004 expr1.X_add_number = 0;
8005 macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
8007 move_register (&icnt, xreg, yreg);
8008 expr1.X_add_number = 2;
8009 macro_build (NULL, &icnt, &expr1, "bteqz", "p");
8010 macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
8014 /* For consistency checking, verify that all bits are specified either
8015 by the match/mask part of the instruction definition, or by the
8018 validate_mips_insn (const struct mips_opcode *opc)
8020 const char *p = opc->args;
8022 unsigned long used_bits = opc->mask;
8024 if ((used_bits & opc->match) != opc->match)
8026 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8027 opc->name, opc->args);
8030 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8040 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8041 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8042 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8043 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8044 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8046 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8047 c, opc->name, opc->args);
8051 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8052 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8054 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8055 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8056 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8057 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8059 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8060 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8062 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8063 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8065 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8066 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8067 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8068 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8069 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8070 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8071 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8072 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8073 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8074 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8075 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8076 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8077 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8078 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8079 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8080 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8081 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8083 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8084 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8085 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8086 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8088 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8089 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8090 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8091 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8092 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8093 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8094 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8095 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8096 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8099 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8100 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8101 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8102 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8103 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8107 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8108 c, opc->name, opc->args);
8112 if (used_bits != 0xffffffff)
8114 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8115 ~used_bits & 0xffffffff, opc->name, opc->args);
8121 /* This routine assembles an instruction into its binary format. As a
8122 side effect, it sets one of the global variables imm_reloc or
8123 offset_reloc to the type of relocation to do if one of the operands
8124 is an address expression. */
8127 mips_ip (char *str, struct mips_cl_insn *ip)
8132 struct mips_opcode *insn;
8135 unsigned int lastregno = 0;
8136 unsigned int lastpos = 0;
8137 unsigned int limlo, limhi;
8143 /* If the instruction contains a '.', we first try to match an instruction
8144 including the '.'. Then we try again without the '.'. */
8146 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8149 /* If we stopped on whitespace, then replace the whitespace with null for
8150 the call to hash_find. Save the character we replaced just in case we
8151 have to re-parse the instruction. */
8158 insn = (struct mips_opcode *) hash_find (op_hash, str);
8160 /* If we didn't find the instruction in the opcode table, try again, but
8161 this time with just the instruction up to, but not including the
8165 /* Restore the character we overwrite above (if any). */
8169 /* Scan up to the first '.' or whitespace. */
8171 *s != '\0' && *s != '.' && !ISSPACE (*s);
8175 /* If we did not find a '.', then we can quit now. */
8178 insn_error = "unrecognized opcode";
8182 /* Lookup the instruction in the hash table. */
8184 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8186 insn_error = "unrecognized opcode";
8196 assert (strcmp (insn->name, str) == 0);
8198 if (OPCODE_IS_MEMBER (insn,
8200 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8201 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8202 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8208 if (insn->pinfo != INSN_MACRO)
8210 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8216 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8217 && strcmp (insn->name, insn[1].name) == 0)
8226 static char buf[100];
8228 _("opcode not supported on this processor: %s (%s)"),
8229 mips_cpu_info_from_arch (mips_opts.arch)->name,
8230 mips_cpu_info_from_isa (mips_opts.isa)->name);
8240 ip->insn_opcode = insn->match;
8242 for (args = insn->args;; ++args)
8246 s += strspn (s, " \t");
8250 case '\0': /* end of args */
8263 ip->insn_opcode |= lastregno << OP_SH_RS;
8267 ip->insn_opcode |= lastregno << OP_SH_RT;
8271 ip->insn_opcode |= lastregno << OP_SH_FT;
8275 ip->insn_opcode |= lastregno << OP_SH_FS;
8281 /* Handle optional base register.
8282 Either the base register is omitted or
8283 we must have a left paren. */
8284 /* This is dependent on the next operand specifier
8285 is a base register specification. */
8286 assert (args[1] == 'b' || args[1] == '5'
8287 || args[1] == '-' || args[1] == '4');
8291 case ')': /* these must match exactly */
8298 case '+': /* Opcode extension character. */
8301 case 'A': /* ins/ext position, becomes LSB. */
8304 my_getExpression (&imm_expr, s);
8305 check_absolute_expr (ip, &imm_expr);
8306 if ((unsigned long) imm_expr.X_add_number < limlo
8307 || (unsigned long) imm_expr.X_add_number > limhi)
8309 as_bad (_("Improper position (%lu)"),
8310 (unsigned long) imm_expr.X_add_number);
8311 imm_expr.X_add_number = limlo;
8313 lastpos = imm_expr.X_add_number;
8314 ip->insn_opcode |= (imm_expr.X_add_number
8315 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8316 imm_expr.X_op = O_absent;
8320 case 'B': /* ins size, becomes MSB. */
8323 my_getExpression (&imm_expr, s);
8324 check_absolute_expr (ip, &imm_expr);
8325 /* Check for negative input so that small negative numbers
8326 will not succeed incorrectly. The checks against
8327 (pos+size) transitively check "size" itself,
8328 assuming that "pos" is reasonable. */
8329 if ((long) imm_expr.X_add_number < 0
8330 || ((unsigned long) imm_expr.X_add_number
8332 || ((unsigned long) imm_expr.X_add_number
8335 as_bad (_("Improper insert size (%lu, position %lu)"),
8336 (unsigned long) imm_expr.X_add_number,
8337 (unsigned long) lastpos);
8338 imm_expr.X_add_number = limlo - lastpos;
8340 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8341 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8342 imm_expr.X_op = O_absent;
8346 case 'C': /* ext size, becomes MSBD. */
8349 my_getExpression (&imm_expr, s);
8350 check_absolute_expr (ip, &imm_expr);
8351 /* Check for negative input so that small negative numbers
8352 will not succeed incorrectly. The checks against
8353 (pos+size) transitively check "size" itself,
8354 assuming that "pos" is reasonable. */
8355 if ((long) imm_expr.X_add_number < 0
8356 || ((unsigned long) imm_expr.X_add_number
8358 || ((unsigned long) imm_expr.X_add_number
8361 as_bad (_("Improper extract size (%lu, position %lu)"),
8362 (unsigned long) imm_expr.X_add_number,
8363 (unsigned long) lastpos);
8364 imm_expr.X_add_number = limlo - lastpos;
8366 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8367 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8368 imm_expr.X_op = O_absent;
8373 /* +D is for disassembly only; never match. */
8377 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8378 *args, insn->name, insn->args);
8379 /* Further processing is fruitless. */
8384 case '<': /* must be at least one digit */
8386 * According to the manual, if the shift amount is greater
8387 * than 31 or less than 0, then the shift amount should be
8388 * mod 32. In reality the mips assembler issues an error.
8389 * We issue a warning and mask out all but the low 5 bits.
8391 my_getExpression (&imm_expr, s);
8392 check_absolute_expr (ip, &imm_expr);
8393 if ((unsigned long) imm_expr.X_add_number > 31)
8395 as_warn (_("Improper shift amount (%lu)"),
8396 (unsigned long) imm_expr.X_add_number);
8397 imm_expr.X_add_number &= OP_MASK_SHAMT;
8399 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8400 imm_expr.X_op = O_absent;
8404 case '>': /* shift amount minus 32 */
8405 my_getExpression (&imm_expr, s);
8406 check_absolute_expr (ip, &imm_expr);
8407 if ((unsigned long) imm_expr.X_add_number < 32
8408 || (unsigned long) imm_expr.X_add_number > 63)
8410 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8411 imm_expr.X_op = O_absent;
8415 case 'k': /* cache code */
8416 case 'h': /* prefx code */
8417 my_getExpression (&imm_expr, s);
8418 check_absolute_expr (ip, &imm_expr);
8419 if ((unsigned long) imm_expr.X_add_number > 31)
8421 as_warn (_("Invalid value for `%s' (%lu)"),
8423 (unsigned long) imm_expr.X_add_number);
8424 imm_expr.X_add_number &= 0x1f;
8427 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8429 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8430 imm_expr.X_op = O_absent;
8434 case 'c': /* break code */
8435 my_getExpression (&imm_expr, s);
8436 check_absolute_expr (ip, &imm_expr);
8437 if ((unsigned long) imm_expr.X_add_number > 1023)
8439 as_warn (_("Illegal break code (%lu)"),
8440 (unsigned long) imm_expr.X_add_number);
8441 imm_expr.X_add_number &= OP_MASK_CODE;
8443 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8444 imm_expr.X_op = O_absent;
8448 case 'q': /* lower break code */
8449 my_getExpression (&imm_expr, s);
8450 check_absolute_expr (ip, &imm_expr);
8451 if ((unsigned long) imm_expr.X_add_number > 1023)
8453 as_warn (_("Illegal lower break code (%lu)"),
8454 (unsigned long) imm_expr.X_add_number);
8455 imm_expr.X_add_number &= OP_MASK_CODE2;
8457 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8458 imm_expr.X_op = O_absent;
8462 case 'B': /* 20-bit syscall/break code. */
8463 my_getExpression (&imm_expr, s);
8464 check_absolute_expr (ip, &imm_expr);
8465 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8466 as_warn (_("Illegal 20-bit code (%lu)"),
8467 (unsigned long) imm_expr.X_add_number);
8468 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8469 imm_expr.X_op = O_absent;
8473 case 'C': /* Coprocessor code */
8474 my_getExpression (&imm_expr, s);
8475 check_absolute_expr (ip, &imm_expr);
8476 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8478 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8479 (unsigned long) imm_expr.X_add_number);
8480 imm_expr.X_add_number &= ((1 << 25) - 1);
8482 ip->insn_opcode |= imm_expr.X_add_number;
8483 imm_expr.X_op = O_absent;
8487 case 'J': /* 19-bit wait code. */
8488 my_getExpression (&imm_expr, s);
8489 check_absolute_expr (ip, &imm_expr);
8490 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8491 as_warn (_("Illegal 19-bit code (%lu)"),
8492 (unsigned long) imm_expr.X_add_number);
8493 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8494 imm_expr.X_op = O_absent;
8498 case 'P': /* Performance register */
8499 my_getExpression (&imm_expr, s);
8500 check_absolute_expr (ip, &imm_expr);
8501 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8503 as_warn (_("Invalid performance register (%lu)"),
8504 (unsigned long) imm_expr.X_add_number);
8505 imm_expr.X_add_number &= OP_MASK_PERFREG;
8507 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8508 imm_expr.X_op = O_absent;
8512 case 'b': /* base register */
8513 case 'd': /* destination register */
8514 case 's': /* source register */
8515 case 't': /* target register */
8516 case 'r': /* both target and source */
8517 case 'v': /* both dest and source */
8518 case 'w': /* both dest and target */
8519 case 'E': /* coprocessor target register */
8520 case 'G': /* coprocessor destination register */
8521 case 'K': /* 'rdhwr' destination register */
8522 case 'x': /* ignore register name */
8523 case 'z': /* must be zero register */
8524 case 'U': /* destination register (clo/clz). */
8539 while (ISDIGIT (*s));
8541 as_bad (_("Invalid register number (%d)"), regno);
8543 else if (*args == 'E' || *args == 'G' || *args == 'K')
8547 if (s[1] == 'r' && s[2] == 'a')
8552 else if (s[1] == 'f' && s[2] == 'p')
8557 else if (s[1] == 's' && s[2] == 'p')
8562 else if (s[1] == 'g' && s[2] == 'p')
8567 else if (s[1] == 'a' && s[2] == 't')
8572 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8577 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8582 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8587 else if (itbl_have_entries)
8592 p = s + 1; /* advance past '$' */
8593 n = itbl_get_field (&p); /* n is name */
8595 /* See if this is a register defined in an
8597 if (itbl_get_reg_val (n, &r))
8599 /* Get_field advances to the start of
8600 the next field, so we need to back
8601 rack to the end of the last field. */
8605 s = strchr (s, '\0');
8619 as_warn (_("Used $at without \".set noat\""));
8625 if (c == 'r' || c == 'v' || c == 'w')
8632 /* 'z' only matches $0. */
8633 if (c == 'z' && regno != 0)
8636 /* Now that we have assembled one operand, we use the args string
8637 * to figure out where it goes in the instruction. */
8644 ip->insn_opcode |= regno << OP_SH_RS;
8649 ip->insn_opcode |= regno << OP_SH_RD;
8652 ip->insn_opcode |= regno << OP_SH_RD;
8653 ip->insn_opcode |= regno << OP_SH_RT;
8658 ip->insn_opcode |= regno << OP_SH_RT;
8661 /* This case exists because on the r3000 trunc
8662 expands into a macro which requires a gp
8663 register. On the r6000 or r4000 it is
8664 assembled into a single instruction which
8665 ignores the register. Thus the insn version
8666 is MIPS_ISA2 and uses 'x', and the macro
8667 version is MIPS_ISA1 and uses 't'. */
8670 /* This case is for the div instruction, which
8671 acts differently if the destination argument
8672 is $0. This only matches $0, and is checked
8673 outside the switch. */
8676 /* Itbl operand; not yet implemented. FIXME ?? */
8678 /* What about all other operands like 'i', which
8679 can be specified in the opcode table? */
8689 ip->insn_opcode |= lastregno << OP_SH_RS;
8692 ip->insn_opcode |= lastregno << OP_SH_RT;
8697 case 'O': /* MDMX alignment immediate constant. */
8698 my_getExpression (&imm_expr, s);
8699 check_absolute_expr (ip, &imm_expr);
8700 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8702 as_warn ("Improper align amount (%ld), using low bits",
8703 (long) imm_expr.X_add_number);
8704 imm_expr.X_add_number &= OP_MASK_ALN;
8706 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8707 imm_expr.X_op = O_absent;
8711 case 'Q': /* MDMX vector, element sel, or const. */
8714 /* MDMX Immediate. */
8715 my_getExpression (&imm_expr, s);
8716 check_absolute_expr (ip, &imm_expr);
8717 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8719 as_warn (_("Invalid MDMX Immediate (%ld)"),
8720 (long) imm_expr.X_add_number);
8721 imm_expr.X_add_number &= OP_MASK_FT;
8723 imm_expr.X_add_number &= OP_MASK_FT;
8724 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8725 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8727 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8728 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8729 imm_expr.X_op = O_absent;
8733 /* Not MDMX Immediate. Fall through. */
8734 case 'X': /* MDMX destination register. */
8735 case 'Y': /* MDMX source register. */
8736 case 'Z': /* MDMX target register. */
8738 case 'D': /* floating point destination register */
8739 case 'S': /* floating point source register */
8740 case 'T': /* floating point target register */
8741 case 'R': /* floating point source register */
8745 /* Accept $fN for FP and MDMX register numbers, and in
8746 addition accept $vN for MDMX register numbers. */
8747 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8748 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8759 while (ISDIGIT (*s));
8762 as_bad (_("Invalid float register number (%d)"), regno);
8764 if ((regno & 1) != 0
8766 && ! (strcmp (str, "mtc1") == 0
8767 || strcmp (str, "mfc1") == 0
8768 || strcmp (str, "lwc1") == 0
8769 || strcmp (str, "swc1") == 0
8770 || strcmp (str, "l.s") == 0
8771 || strcmp (str, "s.s") == 0))
8772 as_warn (_("Float register should be even, was %d"),
8780 if (c == 'V' || c == 'W')
8791 ip->insn_opcode |= regno << OP_SH_FD;
8796 ip->insn_opcode |= regno << OP_SH_FS;
8799 /* This is like 'Z', but also needs to fix the MDMX
8800 vector/scalar select bits. Note that the
8801 scalar immediate case is handled above. */
8804 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8805 int max_el = (is_qh ? 3 : 7);
8807 my_getExpression(&imm_expr, s);
8808 check_absolute_expr (ip, &imm_expr);
8810 if (imm_expr.X_add_number > max_el)
8811 as_bad(_("Bad element selector %ld"),
8812 (long) imm_expr.X_add_number);
8813 imm_expr.X_add_number &= max_el;
8814 ip->insn_opcode |= (imm_expr.X_add_number
8818 as_warn(_("Expecting ']' found '%s'"), s);
8824 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8825 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8828 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8835 ip->insn_opcode |= regno << OP_SH_FT;
8838 ip->insn_opcode |= regno << OP_SH_FR;
8848 ip->insn_opcode |= lastregno << OP_SH_FS;
8851 ip->insn_opcode |= lastregno << OP_SH_FT;
8857 my_getExpression (&imm_expr, s);
8858 if (imm_expr.X_op != O_big
8859 && imm_expr.X_op != O_constant)
8860 insn_error = _("absolute expression required");
8865 my_getExpression (&offset_expr, s);
8866 *imm_reloc = BFD_RELOC_32;
8879 unsigned char temp[8];
8881 unsigned int length;
8886 /* These only appear as the last operand in an
8887 instruction, and every instruction that accepts
8888 them in any variant accepts them in all variants.
8889 This means we don't have to worry about backing out
8890 any changes if the instruction does not match.
8892 The difference between them is the size of the
8893 floating point constant and where it goes. For 'F'
8894 and 'L' the constant is 64 bits; for 'f' and 'l' it
8895 is 32 bits. Where the constant is placed is based
8896 on how the MIPS assembler does things:
8899 f -- immediate value
8902 The .lit4 and .lit8 sections are only used if
8903 permitted by the -G argument.
8905 When generating embedded PIC code, we use the
8906 .lit8 section but not the .lit4 section (we can do
8907 .lit4 inline easily; we need to put .lit8
8908 somewhere in the data segment, and using .lit8
8909 permits the linker to eventually combine identical
8912 The code below needs to know whether the target register
8913 is 32 or 64 bits wide. It relies on the fact 'f' and
8914 'F' are used with GPR-based instructions and 'l' and
8915 'L' are used with FPR-based instructions. */
8917 f64 = *args == 'F' || *args == 'L';
8918 using_gprs = *args == 'F' || *args == 'f';
8920 save_in = input_line_pointer;
8921 input_line_pointer = s;
8922 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8924 s = input_line_pointer;
8925 input_line_pointer = save_in;
8926 if (err != NULL && *err != '\0')
8928 as_bad (_("Bad floating point constant: %s"), err);
8929 memset (temp, '\0', sizeof temp);
8930 length = f64 ? 8 : 4;
8933 assert (length == (unsigned) (f64 ? 8 : 4));
8937 && (! USE_GLOBAL_POINTER_OPT
8938 || mips_pic == EMBEDDED_PIC
8939 || g_switch_value < 4
8940 || (temp[0] == 0 && temp[1] == 0)
8941 || (temp[2] == 0 && temp[3] == 0))))
8943 imm_expr.X_op = O_constant;
8944 if (! target_big_endian)
8945 imm_expr.X_add_number = bfd_getl32 (temp);
8947 imm_expr.X_add_number = bfd_getb32 (temp);
8950 && ! mips_disable_float_construction
8951 /* Constants can only be constructed in GPRs and
8952 copied to FPRs if the GPRs are at least as wide
8953 as the FPRs. Force the constant into memory if
8954 we are using 64-bit FPRs but the GPRs are only
8957 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8958 && ((temp[0] == 0 && temp[1] == 0)
8959 || (temp[2] == 0 && temp[3] == 0))
8960 && ((temp[4] == 0 && temp[5] == 0)
8961 || (temp[6] == 0 && temp[7] == 0)))
8963 /* The value is simple enough to load with a couple of
8964 instructions. If using 32-bit registers, set
8965 imm_expr to the high order 32 bits and offset_expr to
8966 the low order 32 bits. Otherwise, set imm_expr to
8967 the entire 64 bit constant. */
8968 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8970 imm_expr.X_op = O_constant;
8971 offset_expr.X_op = O_constant;
8972 if (! target_big_endian)
8974 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8975 offset_expr.X_add_number = bfd_getl32 (temp);
8979 imm_expr.X_add_number = bfd_getb32 (temp);
8980 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8982 if (offset_expr.X_add_number == 0)
8983 offset_expr.X_op = O_absent;
8985 else if (sizeof (imm_expr.X_add_number) > 4)
8987 imm_expr.X_op = O_constant;
8988 if (! target_big_endian)
8989 imm_expr.X_add_number = bfd_getl64 (temp);
8991 imm_expr.X_add_number = bfd_getb64 (temp);
8995 imm_expr.X_op = O_big;
8996 imm_expr.X_add_number = 4;
8997 if (! target_big_endian)
8999 generic_bignum[0] = bfd_getl16 (temp);
9000 generic_bignum[1] = bfd_getl16 (temp + 2);
9001 generic_bignum[2] = bfd_getl16 (temp + 4);
9002 generic_bignum[3] = bfd_getl16 (temp + 6);
9006 generic_bignum[0] = bfd_getb16 (temp + 6);
9007 generic_bignum[1] = bfd_getb16 (temp + 4);
9008 generic_bignum[2] = bfd_getb16 (temp + 2);
9009 generic_bignum[3] = bfd_getb16 (temp);
9015 const char *newname;
9018 /* Switch to the right section. */
9020 subseg = now_subseg;
9023 default: /* unused default case avoids warnings. */
9025 newname = RDATA_SECTION_NAME;
9026 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
9027 || mips_pic == EMBEDDED_PIC)
9031 if (mips_pic == EMBEDDED_PIC)
9034 newname = RDATA_SECTION_NAME;
9037 assert (!USE_GLOBAL_POINTER_OPT
9038 || g_switch_value >= 4);
9042 new_seg = subseg_new (newname, (subsegT) 0);
9043 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9044 bfd_set_section_flags (stdoutput, new_seg,
9049 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9050 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9051 && strcmp (TARGET_OS, "elf") != 0)
9052 record_alignment (new_seg, 4);
9054 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9056 as_bad (_("Can't use floating point insn in this section"));
9058 /* Set the argument to the current address in the
9060 offset_expr.X_op = O_symbol;
9061 offset_expr.X_add_symbol =
9062 symbol_new ("L0\001", now_seg,
9063 (valueT) frag_now_fix (), frag_now);
9064 offset_expr.X_add_number = 0;
9066 /* Put the floating point number into the section. */
9067 p = frag_more ((int) length);
9068 memcpy (p, temp, length);
9070 /* Switch back to the original section. */
9071 subseg_set (seg, subseg);
9076 case 'i': /* 16 bit unsigned immediate */
9077 case 'j': /* 16 bit signed immediate */
9078 *imm_reloc = BFD_RELOC_LO16;
9079 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9082 offsetT minval, maxval;
9084 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9085 && strcmp (insn->name, insn[1].name) == 0);
9087 /* If the expression was written as an unsigned number,
9088 only treat it as signed if there are no more
9092 && sizeof (imm_expr.X_add_number) <= 4
9093 && imm_expr.X_op == O_constant
9094 && imm_expr.X_add_number < 0
9095 && imm_expr.X_unsigned
9099 /* For compatibility with older assemblers, we accept
9100 0x8000-0xffff as signed 16-bit numbers when only
9101 signed numbers are allowed. */
9103 minval = 0, maxval = 0xffff;
9105 minval = -0x8000, maxval = 0x7fff;
9107 minval = -0x8000, maxval = 0xffff;
9109 if (imm_expr.X_op != O_constant
9110 || imm_expr.X_add_number < minval
9111 || imm_expr.X_add_number > maxval)
9115 if (imm_expr.X_op == O_constant
9116 || imm_expr.X_op == O_big)
9117 as_bad (_("expression out of range"));
9123 case 'o': /* 16 bit offset */
9124 /* Check whether there is only a single bracketed expression
9125 left. If so, it must be the base register and the
9126 constant must be zero. */
9127 if (*s == '(' && strchr (s + 1, '(') == 0)
9129 offset_expr.X_op = O_constant;
9130 offset_expr.X_add_number = 0;
9134 /* If this value won't fit into a 16 bit offset, then go
9135 find a macro that will generate the 32 bit offset
9137 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9138 && (offset_expr.X_op != O_constant
9139 || offset_expr.X_add_number >= 0x8000
9140 || offset_expr.X_add_number < -0x8000))
9146 case 'p': /* pc relative offset */
9147 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9148 my_getExpression (&offset_expr, s);
9152 case 'u': /* upper 16 bits */
9153 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9154 && imm_expr.X_op == O_constant
9155 && (imm_expr.X_add_number < 0
9156 || imm_expr.X_add_number >= 0x10000))
9157 as_bad (_("lui expression not in range 0..65535"));
9161 case 'a': /* 26 bit address */
9162 my_getExpression (&offset_expr, s);
9164 *offset_reloc = BFD_RELOC_MIPS_JMP;
9167 case 'N': /* 3 bit branch condition code */
9168 case 'M': /* 3 bit compare condition code */
9169 if (strncmp (s, "$fcc", 4) != 0)
9179 while (ISDIGIT (*s));
9181 as_bad (_("invalid condition code register $fcc%d"), regno);
9183 ip->insn_opcode |= regno << OP_SH_BCC;
9185 ip->insn_opcode |= regno << OP_SH_CCC;
9189 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9200 while (ISDIGIT (*s));
9203 c = 8; /* Invalid sel value. */
9206 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9207 ip->insn_opcode |= c;
9211 /* Must be at least one digit. */
9212 my_getExpression (&imm_expr, s);
9213 check_absolute_expr (ip, &imm_expr);
9215 if ((unsigned long) imm_expr.X_add_number
9216 > (unsigned long) OP_MASK_VECBYTE)
9218 as_bad (_("bad byte vector index (%ld)"),
9219 (long) imm_expr.X_add_number);
9220 imm_expr.X_add_number = 0;
9223 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9224 imm_expr.X_op = O_absent;
9229 my_getExpression (&imm_expr, s);
9230 check_absolute_expr (ip, &imm_expr);
9232 if ((unsigned long) imm_expr.X_add_number
9233 > (unsigned long) OP_MASK_VECALIGN)
9235 as_bad (_("bad byte vector index (%ld)"),
9236 (long) imm_expr.X_add_number);
9237 imm_expr.X_add_number = 0;
9240 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9241 imm_expr.X_op = O_absent;
9246 as_bad (_("bad char = '%c'\n"), *args);
9251 /* Args don't match. */
9252 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9253 !strcmp (insn->name, insn[1].name))
9257 insn_error = _("illegal operands");
9262 insn_error = _("illegal operands");
9267 /* This routine assembles an instruction into its binary format when
9268 assembling for the mips16. As a side effect, it sets one of the
9269 global variables imm_reloc or offset_reloc to the type of
9270 relocation to do if one of the operands is an address expression.
9271 It also sets mips16_small and mips16_ext if the user explicitly
9272 requested a small or extended instruction. */
9275 mips16_ip (char *str, struct mips_cl_insn *ip)
9279 struct mips_opcode *insn;
9282 unsigned int lastregno = 0;
9287 mips16_small = FALSE;
9290 for (s = str; ISLOWER (*s); ++s)
9302 if (s[1] == 't' && s[2] == ' ')
9305 mips16_small = TRUE;
9309 else if (s[1] == 'e' && s[2] == ' ')
9318 insn_error = _("unknown opcode");
9322 if (mips_opts.noautoextend && ! mips16_ext)
9323 mips16_small = TRUE;
9325 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9327 insn_error = _("unrecognized opcode");
9334 assert (strcmp (insn->name, str) == 0);
9337 ip->insn_opcode = insn->match;
9338 ip->use_extend = FALSE;
9339 imm_expr.X_op = O_absent;
9340 imm_reloc[0] = BFD_RELOC_UNUSED;
9341 imm_reloc[1] = BFD_RELOC_UNUSED;
9342 imm_reloc[2] = BFD_RELOC_UNUSED;
9343 offset_expr.X_op = O_absent;
9344 offset_reloc[0] = BFD_RELOC_UNUSED;
9345 offset_reloc[1] = BFD_RELOC_UNUSED;
9346 offset_reloc[2] = BFD_RELOC_UNUSED;
9347 for (args = insn->args; 1; ++args)
9354 /* In this switch statement we call break if we did not find
9355 a match, continue if we did find a match, or return if we
9364 /* Stuff the immediate value in now, if we can. */
9365 if (imm_expr.X_op == O_constant
9366 && *imm_reloc > BFD_RELOC_UNUSED
9367 && insn->pinfo != INSN_MACRO)
9369 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9370 imm_expr.X_add_number, TRUE, mips16_small,
9371 mips16_ext, &ip->insn_opcode,
9372 &ip->use_extend, &ip->extend);
9373 imm_expr.X_op = O_absent;
9374 *imm_reloc = BFD_RELOC_UNUSED;
9388 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9391 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9407 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9409 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9436 while (ISDIGIT (*s));
9439 as_bad (_("invalid register number (%d)"), regno);
9445 if (s[1] == 'r' && s[2] == 'a')
9450 else if (s[1] == 'f' && s[2] == 'p')
9455 else if (s[1] == 's' && s[2] == 'p')
9460 else if (s[1] == 'g' && s[2] == 'p')
9465 else if (s[1] == 'a' && s[2] == 't')
9470 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9475 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9480 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9493 if (c == 'v' || c == 'w')
9495 regno = mips16_to_32_reg_map[lastregno];
9509 regno = mips32_to_16_reg_map[regno];
9514 regno = ILLEGAL_REG;
9519 regno = ILLEGAL_REG;
9524 regno = ILLEGAL_REG;
9529 if (regno == AT && ! mips_opts.noat)
9530 as_warn (_("used $at without \".set noat\""));
9537 if (regno == ILLEGAL_REG)
9544 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9548 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9551 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9554 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9560 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9563 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9564 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9574 if (strncmp (s, "$pc", 3) == 0)
9598 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9600 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9601 and generate the appropriate reloc. If the text
9602 inside %gprel is not a symbol name with an
9603 optional offset, then we generate a normal reloc
9604 and will probably fail later. */
9605 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9606 if (imm_expr.X_op == O_symbol)
9609 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9611 ip->use_extend = TRUE;
9618 /* Just pick up a normal expression. */
9619 my_getExpression (&imm_expr, s);
9622 if (imm_expr.X_op == O_register)
9624 /* What we thought was an expression turned out to
9627 if (s[0] == '(' && args[1] == '(')
9629 /* It looks like the expression was omitted
9630 before a register indirection, which means
9631 that the expression is implicitly zero. We
9632 still set up imm_expr, so that we handle
9633 explicit extensions correctly. */
9634 imm_expr.X_op = O_constant;
9635 imm_expr.X_add_number = 0;
9636 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9643 /* We need to relax this instruction. */
9644 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9653 /* We use offset_reloc rather than imm_reloc for the PC
9654 relative operands. This lets macros with both
9655 immediate and address operands work correctly. */
9656 my_getExpression (&offset_expr, s);
9658 if (offset_expr.X_op == O_register)
9661 /* We need to relax this instruction. */
9662 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9666 case '6': /* break code */
9667 my_getExpression (&imm_expr, s);
9668 check_absolute_expr (ip, &imm_expr);
9669 if ((unsigned long) imm_expr.X_add_number > 63)
9671 as_warn (_("Invalid value for `%s' (%lu)"),
9673 (unsigned long) imm_expr.X_add_number);
9674 imm_expr.X_add_number &= 0x3f;
9676 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9677 imm_expr.X_op = O_absent;
9681 case 'a': /* 26 bit address */
9682 my_getExpression (&offset_expr, s);
9684 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9685 ip->insn_opcode <<= 16;
9688 case 'l': /* register list for entry macro */
9689 case 'L': /* register list for exit macro */
9699 int freg, reg1, reg2;
9701 while (*s == ' ' || *s == ',')
9705 as_bad (_("can't parse register list"));
9717 while (ISDIGIT (*s))
9739 as_bad (_("invalid register list"));
9744 while (ISDIGIT (*s))
9751 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9756 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9761 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9762 mask |= (reg2 - 3) << 3;
9763 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9764 mask |= (reg2 - 15) << 1;
9765 else if (reg1 == RA && reg2 == RA)
9769 as_bad (_("invalid register list"));
9773 /* The mask is filled in in the opcode table for the
9774 benefit of the disassembler. We remove it before
9775 applying the actual mask. */
9776 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9777 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9781 case 'e': /* extend code */
9782 my_getExpression (&imm_expr, s);
9783 check_absolute_expr (ip, &imm_expr);
9784 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9786 as_warn (_("Invalid value for `%s' (%lu)"),
9788 (unsigned long) imm_expr.X_add_number);
9789 imm_expr.X_add_number &= 0x7ff;
9791 ip->insn_opcode |= imm_expr.X_add_number;
9792 imm_expr.X_op = O_absent;
9802 /* Args don't match. */
9803 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9804 strcmp (insn->name, insn[1].name) == 0)
9811 insn_error = _("illegal operands");
9817 /* This structure holds information we know about a mips16 immediate
9820 struct mips16_immed_operand
9822 /* The type code used in the argument string in the opcode table. */
9824 /* The number of bits in the short form of the opcode. */
9826 /* The number of bits in the extended form of the opcode. */
9828 /* The amount by which the short form is shifted when it is used;
9829 for example, the sw instruction has a shift count of 2. */
9831 /* The amount by which the short form is shifted when it is stored
9832 into the instruction code. */
9834 /* Non-zero if the short form is unsigned. */
9836 /* Non-zero if the extended form is unsigned. */
9838 /* Non-zero if the value is PC relative. */
9842 /* The mips16 immediate operand types. */
9844 static const struct mips16_immed_operand mips16_immed_operands[] =
9846 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9847 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9848 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9849 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9850 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9851 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9852 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9853 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9854 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9855 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9856 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9857 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9858 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9859 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9860 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9861 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9862 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9863 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9864 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9865 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9866 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9869 #define MIPS16_NUM_IMMED \
9870 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9872 /* Handle a mips16 instruction with an immediate value. This or's the
9873 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9874 whether an extended value is needed; if one is needed, it sets
9875 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9876 If SMALL is true, an unextended opcode was explicitly requested.
9877 If EXT is true, an extended opcode was explicitly requested. If
9878 WARN is true, warn if EXT does not match reality. */
9881 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9882 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9883 unsigned long *insn, bfd_boolean *use_extend,
9884 unsigned short *extend)
9886 register const struct mips16_immed_operand *op;
9887 int mintiny, maxtiny;
9888 bfd_boolean needext;
9890 op = mips16_immed_operands;
9891 while (op->type != type)
9894 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9899 if (type == '<' || type == '>' || type == '[' || type == ']')
9902 maxtiny = 1 << op->nbits;
9907 maxtiny = (1 << op->nbits) - 1;
9912 mintiny = - (1 << (op->nbits - 1));
9913 maxtiny = (1 << (op->nbits - 1)) - 1;
9916 /* Branch offsets have an implicit 0 in the lowest bit. */
9917 if (type == 'p' || type == 'q')
9920 if ((val & ((1 << op->shift) - 1)) != 0
9921 || val < (mintiny << op->shift)
9922 || val > (maxtiny << op->shift))
9927 if (warn && ext && ! needext)
9928 as_warn_where (file, line,
9929 _("extended operand requested but not required"));
9930 if (small && needext)
9931 as_bad_where (file, line, _("invalid unextended operand value"));
9933 if (small || (! ext && ! needext))
9937 *use_extend = FALSE;
9938 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9939 insnval <<= op->op_shift;
9944 long minext, maxext;
9950 maxext = (1 << op->extbits) - 1;
9954 minext = - (1 << (op->extbits - 1));
9955 maxext = (1 << (op->extbits - 1)) - 1;
9957 if (val < minext || val > maxext)
9958 as_bad_where (file, line,
9959 _("operand value out of range for instruction"));
9962 if (op->extbits == 16)
9964 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9967 else if (op->extbits == 15)
9969 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9974 extval = ((val & 0x1f) << 6) | (val & 0x20);
9978 *extend = (unsigned short) extval;
9983 static const struct percent_op_match
9986 bfd_reloc_code_real_type reloc;
9989 {"%lo", BFD_RELOC_LO16},
9991 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9992 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9993 {"%call16", BFD_RELOC_MIPS_CALL16},
9994 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9995 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9996 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9997 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9998 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9999 {"%got", BFD_RELOC_MIPS_GOT16},
10000 {"%gp_rel", BFD_RELOC_GPREL16},
10001 {"%half", BFD_RELOC_16},
10002 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10003 {"%higher", BFD_RELOC_MIPS_HIGHER},
10004 {"%neg", BFD_RELOC_MIPS_SUB},
10006 {"%hi", BFD_RELOC_HI16_S}
10010 /* Return true if *STR points to a relocation operator. When returning true,
10011 move *STR over the operator and store its relocation code in *RELOC.
10012 Leave both *STR and *RELOC alone when returning false. */
10015 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10019 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10020 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10022 *str += strlen (percent_op[i].str);
10023 *reloc = percent_op[i].reloc;
10025 /* Check whether the output BFD supports this relocation.
10026 If not, issue an error and fall back on something safe. */
10027 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10029 as_bad ("relocation %s isn't supported by the current ABI",
10030 percent_op[i].str);
10031 *reloc = BFD_RELOC_LO16;
10039 /* Parse string STR as a 16-bit relocatable operand. Store the
10040 expression in *EP and the relocations in the array starting
10041 at RELOC. Return the number of relocation operators used.
10043 On exit, EXPR_END points to the first character after the expression.
10044 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10047 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10050 bfd_reloc_code_real_type reversed_reloc[3];
10051 size_t reloc_index, i;
10052 int crux_depth, str_depth;
10055 /* Search for the start of the main expression, recoding relocations
10056 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10057 of the main expression and with CRUX_DEPTH containing the number
10058 of open brackets at that point. */
10065 crux_depth = str_depth;
10067 /* Skip over whitespace and brackets, keeping count of the number
10069 while (*str == ' ' || *str == '\t' || *str == '(')
10074 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10075 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10077 my_getExpression (ep, crux);
10080 /* Match every open bracket. */
10081 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10085 if (crux_depth > 0)
10086 as_bad ("unclosed '('");
10090 if (reloc_index == 0)
10091 reloc[0] = BFD_RELOC_LO16;
10094 prev_reloc_op_frag = frag_now;
10095 for (i = 0; i < reloc_index; i++)
10096 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10099 return reloc_index;
10103 my_getExpression (expressionS *ep, char *str)
10108 save_in = input_line_pointer;
10109 input_line_pointer = str;
10111 expr_end = input_line_pointer;
10112 input_line_pointer = save_in;
10114 /* If we are in mips16 mode, and this is an expression based on `.',
10115 then we bump the value of the symbol by 1 since that is how other
10116 text symbols are handled. We don't bother to handle complex
10117 expressions, just `.' plus or minus a constant. */
10118 if (mips_opts.mips16
10119 && ep->X_op == O_symbol
10120 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10121 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10122 && symbol_get_frag (ep->X_add_symbol) == frag_now
10123 && symbol_constant_p (ep->X_add_symbol)
10124 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10125 S_SET_VALUE (ep->X_add_symbol, val + 1);
10128 /* Turn a string in input_line_pointer into a floating point constant
10129 of type TYPE, and store the appropriate bytes in *LITP. The number
10130 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10131 returned, or NULL on OK. */
10134 md_atof (int type, char *litP, int *sizeP)
10137 LITTLENUM_TYPE words[4];
10153 return _("bad call to md_atof");
10156 t = atof_ieee (input_line_pointer, type, words);
10158 input_line_pointer = t;
10162 if (! target_big_endian)
10164 for (i = prec - 1; i >= 0; i--)
10166 md_number_to_chars (litP, words[i], 2);
10172 for (i = 0; i < prec; i++)
10174 md_number_to_chars (litP, words[i], 2);
10183 md_number_to_chars (char *buf, valueT val, int n)
10185 if (target_big_endian)
10186 number_to_chars_bigendian (buf, val, n);
10188 number_to_chars_littleendian (buf, val, n);
10192 static int support_64bit_objects(void)
10194 const char **list, **l;
10197 list = bfd_target_list ();
10198 for (l = list; *l != NULL; l++)
10200 /* This is traditional mips */
10201 if (strcmp (*l, "elf64-tradbigmips") == 0
10202 || strcmp (*l, "elf64-tradlittlemips") == 0)
10204 if (strcmp (*l, "elf64-bigmips") == 0
10205 || strcmp (*l, "elf64-littlemips") == 0)
10208 yes = (*l != NULL);
10212 #endif /* OBJ_ELF */
10214 const char *md_shortopts = "nO::g::G:";
10216 struct option md_longopts[] =
10218 /* Options which specify architecture. */
10219 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10220 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10221 {"march", required_argument, NULL, OPTION_MARCH},
10222 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10223 {"mtune", required_argument, NULL, OPTION_MTUNE},
10224 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10225 {"mips0", no_argument, NULL, OPTION_MIPS1},
10226 {"mips1", no_argument, NULL, OPTION_MIPS1},
10227 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10228 {"mips2", no_argument, NULL, OPTION_MIPS2},
10229 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10230 {"mips3", no_argument, NULL, OPTION_MIPS3},
10231 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10232 {"mips4", no_argument, NULL, OPTION_MIPS4},
10233 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10234 {"mips5", no_argument, NULL, OPTION_MIPS5},
10235 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10236 {"mips32", no_argument, NULL, OPTION_MIPS32},
10237 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10238 {"mips64", no_argument, NULL, OPTION_MIPS64},
10239 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10240 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10242 /* Options which specify Application Specific Extensions (ASEs). */
10243 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 10)
10244 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10245 {"mips16", no_argument, NULL, OPTION_MIPS16},
10246 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10247 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10248 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10249 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10250 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10251 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10252 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10253 {"mdmx", no_argument, NULL, OPTION_MDMX},
10254 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10255 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10257 /* Old-style architecture options. Don't add more of these. */
10258 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10259 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10260 {"m4650", no_argument, NULL, OPTION_M4650},
10261 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10262 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10263 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10264 {"m4010", no_argument, NULL, OPTION_M4010},
10265 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10266 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10267 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10268 {"m4100", no_argument, NULL, OPTION_M4100},
10269 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10270 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10271 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10272 {"m3900", no_argument, NULL, OPTION_M3900},
10273 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10274 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10276 /* Options which enable bug fixes. */
10277 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10278 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10279 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10280 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10281 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10282 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10283 #define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
10284 #define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
10285 {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
10286 {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
10288 /* Miscellaneous options. */
10289 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10290 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10291 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10292 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10293 {"trap", no_argument, NULL, OPTION_TRAP},
10294 {"no-break", no_argument, NULL, OPTION_TRAP},
10295 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10296 {"break", no_argument, NULL, OPTION_BREAK},
10297 {"no-trap", no_argument, NULL, OPTION_BREAK},
10298 #define OPTION_EB (OPTION_MISC_BASE + 3)
10299 {"EB", no_argument, NULL, OPTION_EB},
10300 #define OPTION_EL (OPTION_MISC_BASE + 4)
10301 {"EL", no_argument, NULL, OPTION_EL},
10302 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10303 {"mfp32", no_argument, NULL, OPTION_FP32},
10304 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10305 {"mgp32", no_argument, NULL, OPTION_GP32},
10306 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10307 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10308 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10309 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10310 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10311 {"mfp64", no_argument, NULL, OPTION_FP64},
10312 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10313 {"mgp64", no_argument, NULL, OPTION_GP64},
10314 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10315 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10316 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10317 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10319 /* ELF-specific options. */
10321 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10322 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10323 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10324 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10325 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10326 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10327 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10328 {"xgot", no_argument, NULL, OPTION_XGOT},
10329 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10330 {"mabi", required_argument, NULL, OPTION_MABI},
10331 #define OPTION_32 (OPTION_ELF_BASE + 4)
10332 {"32", no_argument, NULL, OPTION_32},
10333 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10334 {"n32", no_argument, NULL, OPTION_N32},
10335 #define OPTION_64 (OPTION_ELF_BASE + 6)
10336 {"64", no_argument, NULL, OPTION_64},
10337 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10338 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10339 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10340 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10341 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10342 {"mpdr", no_argument, NULL, OPTION_PDR},
10343 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10344 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10345 #endif /* OBJ_ELF */
10347 {NULL, no_argument, NULL, 0}
10349 size_t md_longopts_size = sizeof (md_longopts);
10351 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10352 NEW_VALUE. Warn if another value was already specified. Note:
10353 we have to defer parsing the -march and -mtune arguments in order
10354 to handle 'from-abi' correctly, since the ABI might be specified
10355 in a later argument. */
10358 mips_set_option_string (const char **string_ptr, const char *new_value)
10360 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10361 as_warn (_("A different %s was already specified, is now %s"),
10362 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10365 *string_ptr = new_value;
10369 md_parse_option (int c, char *arg)
10373 case OPTION_CONSTRUCT_FLOATS:
10374 mips_disable_float_construction = 0;
10377 case OPTION_NO_CONSTRUCT_FLOATS:
10378 mips_disable_float_construction = 1;
10390 target_big_endian = 1;
10394 target_big_endian = 0;
10402 if (arg && arg[1] == '0')
10412 mips_debug = atoi (arg);
10413 /* When the MIPS assembler sees -g or -g2, it does not do
10414 optimizations which limit full symbolic debugging. We take
10415 that to be equivalent to -O0. */
10416 if (mips_debug == 2)
10421 file_mips_isa = ISA_MIPS1;
10425 file_mips_isa = ISA_MIPS2;
10429 file_mips_isa = ISA_MIPS3;
10433 file_mips_isa = ISA_MIPS4;
10437 file_mips_isa = ISA_MIPS5;
10440 case OPTION_MIPS32:
10441 file_mips_isa = ISA_MIPS32;
10444 case OPTION_MIPS32R2:
10445 file_mips_isa = ISA_MIPS32R2;
10448 case OPTION_MIPS64:
10449 file_mips_isa = ISA_MIPS64;
10453 mips_set_option_string (&mips_tune_string, arg);
10457 mips_set_option_string (&mips_arch_string, arg);
10461 mips_set_option_string (&mips_arch_string, "4650");
10462 mips_set_option_string (&mips_tune_string, "4650");
10465 case OPTION_NO_M4650:
10469 mips_set_option_string (&mips_arch_string, "4010");
10470 mips_set_option_string (&mips_tune_string, "4010");
10473 case OPTION_NO_M4010:
10477 mips_set_option_string (&mips_arch_string, "4100");
10478 mips_set_option_string (&mips_tune_string, "4100");
10481 case OPTION_NO_M4100:
10485 mips_set_option_string (&mips_arch_string, "3900");
10486 mips_set_option_string (&mips_tune_string, "3900");
10489 case OPTION_NO_M3900:
10493 mips_opts.ase_mdmx = 1;
10496 case OPTION_NO_MDMX:
10497 mips_opts.ase_mdmx = 0;
10500 case OPTION_MIPS16:
10501 mips_opts.mips16 = 1;
10502 mips_no_prev_insn (FALSE);
10505 case OPTION_NO_MIPS16:
10506 mips_opts.mips16 = 0;
10507 mips_no_prev_insn (FALSE);
10510 case OPTION_MIPS3D:
10511 mips_opts.ase_mips3d = 1;
10514 case OPTION_NO_MIPS3D:
10515 mips_opts.ase_mips3d = 0;
10518 case OPTION_MEMBEDDED_PIC:
10519 mips_pic = EMBEDDED_PIC;
10520 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10522 as_bad (_("-G may not be used with embedded PIC code"));
10525 g_switch_value = 0x7fffffff;
10528 case OPTION_FIX_VR4122:
10529 mips_fix_4122_bugs = 1;
10532 case OPTION_NO_FIX_VR4122:
10533 mips_fix_4122_bugs = 0;
10536 case OPTION_RELAX_BRANCH:
10537 mips_relax_branch = 1;
10540 case OPTION_NO_RELAX_BRANCH:
10541 mips_relax_branch = 0;
10545 /* When generating ELF code, we permit -KPIC and -call_shared to
10546 select SVR4_PIC, and -non_shared to select no PIC. This is
10547 intended to be compatible with Irix 5. */
10548 case OPTION_CALL_SHARED:
10549 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10551 as_bad (_("-call_shared is supported only for ELF format"));
10554 mips_pic = SVR4_PIC;
10555 mips_abicalls = TRUE;
10556 if (g_switch_seen && g_switch_value != 0)
10558 as_bad (_("-G may not be used with SVR4 PIC code"));
10561 g_switch_value = 0;
10564 case OPTION_NON_SHARED:
10565 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10567 as_bad (_("-non_shared is supported only for ELF format"));
10571 mips_abicalls = FALSE;
10574 /* The -xgot option tells the assembler to use 32 offsets when
10575 accessing the got in SVR4_PIC mode. It is for Irix
10580 #endif /* OBJ_ELF */
10583 if (! USE_GLOBAL_POINTER_OPT)
10585 as_bad (_("-G is not supported for this configuration"));
10588 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10590 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10594 g_switch_value = atoi (arg);
10599 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10602 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10604 as_bad (_("-32 is supported for ELF format only"));
10607 mips_abi = O32_ABI;
10611 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10613 as_bad (_("-n32 is supported for ELF format only"));
10616 mips_abi = N32_ABI;
10620 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10622 as_bad (_("-64 is supported for ELF format only"));
10625 mips_abi = N64_ABI;
10626 if (! support_64bit_objects())
10627 as_fatal (_("No compiled in support for 64 bit object file format"));
10629 #endif /* OBJ_ELF */
10632 file_mips_gp32 = 1;
10636 file_mips_gp32 = 0;
10640 file_mips_fp32 = 1;
10644 file_mips_fp32 = 0;
10649 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10651 as_bad (_("-mabi is supported for ELF format only"));
10654 if (strcmp (arg, "32") == 0)
10655 mips_abi = O32_ABI;
10656 else if (strcmp (arg, "o64") == 0)
10657 mips_abi = O64_ABI;
10658 else if (strcmp (arg, "n32") == 0)
10659 mips_abi = N32_ABI;
10660 else if (strcmp (arg, "64") == 0)
10662 mips_abi = N64_ABI;
10663 if (! support_64bit_objects())
10664 as_fatal (_("No compiled in support for 64 bit object file "
10667 else if (strcmp (arg, "eabi") == 0)
10668 mips_abi = EABI_ABI;
10671 as_fatal (_("invalid abi -mabi=%s"), arg);
10675 #endif /* OBJ_ELF */
10677 case OPTION_M7000_HILO_FIX:
10678 mips_7000_hilo_fix = TRUE;
10681 case OPTION_MNO_7000_HILO_FIX:
10682 mips_7000_hilo_fix = FALSE;
10686 case OPTION_MDEBUG:
10687 mips_flag_mdebug = TRUE;
10690 case OPTION_NO_MDEBUG:
10691 mips_flag_mdebug = FALSE;
10695 mips_flag_pdr = TRUE;
10698 case OPTION_NO_PDR:
10699 mips_flag_pdr = FALSE;
10701 #endif /* OBJ_ELF */
10710 /* Set up globals to generate code for the ISA or processor
10711 described by INFO. */
10714 mips_set_architecture (const struct mips_cpu_info *info)
10718 file_mips_arch = info->cpu;
10719 mips_opts.arch = info->cpu;
10720 mips_opts.isa = info->isa;
10725 /* Likewise for tuning. */
10728 mips_set_tune (const struct mips_cpu_info *info)
10731 mips_tune = info->cpu;
10736 mips_after_parse_args (void)
10738 const struct mips_cpu_info *arch_info = 0;
10739 const struct mips_cpu_info *tune_info = 0;
10741 /* GP relative stuff not working for PE */
10742 if (strncmp (TARGET_OS, "pe", 2) == 0
10743 && g_switch_value != 0)
10746 as_bad (_("-G not supported in this configuration."));
10747 g_switch_value = 0;
10750 if (mips_abi == NO_ABI)
10751 mips_abi = MIPS_DEFAULT_ABI;
10753 /* The following code determines the architecture and register size.
10754 Similar code was added to GCC 3.3 (see override_options() in
10755 config/mips/mips.c). The GAS and GCC code should be kept in sync
10756 as much as possible. */
10758 if (mips_arch_string != 0)
10759 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10761 if (file_mips_isa != ISA_UNKNOWN)
10763 /* Handle -mipsN. At this point, file_mips_isa contains the
10764 ISA level specified by -mipsN, while arch_info->isa contains
10765 the -march selection (if any). */
10766 if (arch_info != 0)
10768 /* -march takes precedence over -mipsN, since it is more descriptive.
10769 There's no harm in specifying both as long as the ISA levels
10771 if (file_mips_isa != arch_info->isa)
10772 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10773 mips_cpu_info_from_isa (file_mips_isa)->name,
10774 mips_cpu_info_from_isa (arch_info->isa)->name);
10777 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10780 if (arch_info == 0)
10781 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10783 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10784 as_bad ("-march=%s is not compatible with the selected ABI",
10787 mips_set_architecture (arch_info);
10789 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10790 if (mips_tune_string != 0)
10791 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10793 if (tune_info == 0)
10794 mips_set_tune (arch_info);
10796 mips_set_tune (tune_info);
10798 if (file_mips_gp32 >= 0)
10800 /* The user specified the size of the integer registers. Make sure
10801 it agrees with the ABI and ISA. */
10802 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10803 as_bad (_("-mgp64 used with a 32-bit processor"));
10804 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10805 as_bad (_("-mgp32 used with a 64-bit ABI"));
10806 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10807 as_bad (_("-mgp64 used with a 32-bit ABI"));
10811 /* Infer the integer register size from the ABI and processor.
10812 Restrict ourselves to 32-bit registers if that's all the
10813 processor has, or if the ABI cannot handle 64-bit registers. */
10814 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10815 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10818 /* ??? GAS treats single-float processors as though they had 64-bit
10819 float registers (although it complains when double-precision
10820 instructions are used). As things stand, saying they have 32-bit
10821 registers would lead to spurious "register must be even" messages.
10822 So here we assume float registers are always the same size as
10823 integer ones, unless the user says otherwise. */
10824 if (file_mips_fp32 < 0)
10825 file_mips_fp32 = file_mips_gp32;
10827 /* End of GCC-shared inference code. */
10829 /* This flag is set when we have a 64-bit capable CPU but use only
10830 32-bit wide registers. Note that EABI does not use it. */
10831 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10832 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10833 || mips_abi == O32_ABI))
10834 mips_32bitmode = 1;
10836 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10837 as_bad (_("trap exception not supported at ISA 1"));
10839 /* If the selected architecture includes support for ASEs, enable
10840 generation of code for them. */
10841 if (mips_opts.mips16 == -1)
10842 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10843 if (mips_opts.ase_mips3d == -1)
10844 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10845 if (mips_opts.ase_mdmx == -1)
10846 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10848 file_mips_isa = mips_opts.isa;
10849 file_ase_mips16 = mips_opts.mips16;
10850 file_ase_mips3d = mips_opts.ase_mips3d;
10851 file_ase_mdmx = mips_opts.ase_mdmx;
10852 mips_opts.gp32 = file_mips_gp32;
10853 mips_opts.fp32 = file_mips_fp32;
10855 if (mips_flag_mdebug < 0)
10857 #ifdef OBJ_MAYBE_ECOFF
10858 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10859 mips_flag_mdebug = 1;
10861 #endif /* OBJ_MAYBE_ECOFF */
10862 mips_flag_mdebug = 0;
10867 mips_init_after_args (void)
10869 /* initialize opcodes */
10870 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10871 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10875 md_pcrel_from (fixS *fixP)
10877 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10878 switch (fixP->fx_r_type)
10880 case BFD_RELOC_16_PCREL_S2:
10881 case BFD_RELOC_MIPS_JMP:
10882 /* Return the address of the delay slot. */
10889 /* This is called before the symbol table is processed. In order to
10890 work with gcc when using mips-tfile, we must keep all local labels.
10891 However, in other cases, we want to discard them. If we were
10892 called with -g, but we didn't see any debugging information, it may
10893 mean that gcc is smuggling debugging information through to
10894 mips-tfile, in which case we must generate all local labels. */
10897 mips_frob_file_before_adjust (void)
10899 #ifndef NO_ECOFF_DEBUGGING
10900 if (ECOFF_DEBUGGING
10902 && ! ecoff_debugging_seen)
10903 flag_keep_locals = 1;
10907 /* Sort any unmatched HI16_S relocs so that they immediately precede
10908 the corresponding LO reloc. This is called before md_apply_fix3 and
10909 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10910 explicit use of the %hi modifier. */
10913 mips_frob_file (void)
10915 struct mips_hi_fixup *l;
10917 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10919 segment_info_type *seginfo;
10922 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10924 /* If a GOT16 relocation turns out to be against a global symbol,
10925 there isn't supposed to be a matching LO. */
10926 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10927 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10930 /* Check quickly whether the next fixup happens to be a matching %lo. */
10931 if (fixup_has_matching_lo_p (l->fixp))
10934 /* Look through the fixups for this segment for a matching %lo.
10935 When we find one, move the %hi just in front of it. We do
10936 this in two passes. In the first pass, we try to find a
10937 unique %lo. In the second pass, we permit multiple %hi
10938 relocs for a single %lo (this is a GNU extension). */
10939 seginfo = seg_info (l->seg);
10940 for (pass = 0; pass < 2; pass++)
10945 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10947 /* Check whether this is a %lo fixup which matches l->fixp. */
10948 if (f->fx_r_type == BFD_RELOC_LO16
10949 && f->fx_addsy == l->fixp->fx_addsy
10950 && f->fx_offset == l->fixp->fx_offset
10953 || !reloc_needs_lo_p (prev->fx_r_type)
10954 || !fixup_has_matching_lo_p (prev)))
10958 /* Move l->fixp before f. */
10959 for (pf = &seginfo->fix_root;
10961 pf = &(*pf)->fx_next)
10962 assert (*pf != NULL);
10964 *pf = l->fixp->fx_next;
10966 l->fixp->fx_next = f;
10968 seginfo->fix_root = l->fixp;
10970 prev->fx_next = l->fixp;
10981 #if 0 /* GCC code motion plus incomplete dead code elimination
10982 can leave a %hi without a %lo. */
10984 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10985 _("Unmatched %%hi reloc"));
10991 /* When generating embedded PIC code we need to use a special
10992 relocation to represent the difference of two symbols in the .text
10993 section (switch tables use a difference of this sort). See
10994 include/coff/mips.h for details. This macro checks whether this
10995 fixup requires the special reloc. */
10996 #define SWITCH_TABLE(fixp) \
10997 ((fixp)->fx_r_type == BFD_RELOC_32 \
10998 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10999 && (fixp)->fx_addsy != NULL \
11000 && (fixp)->fx_subsy != NULL \
11001 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11002 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11004 /* When generating embedded PIC code we must keep all PC relative
11005 relocations, in case the linker has to relax a call. We also need
11006 to keep relocations for switch table entries.
11008 We may have combined relocations without symbols in the N32/N64 ABI.
11009 We have to prevent gas from dropping them. */
11012 mips_force_relocation (fixS *fixp)
11014 if (generic_force_reloc (fixp))
11018 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11019 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11020 || fixp->fx_r_type == BFD_RELOC_HI16_S
11021 || fixp->fx_r_type == BFD_RELOC_LO16))
11024 return (mips_pic == EMBEDDED_PIC
11026 || SWITCH_TABLE (fixp)
11027 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11028 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11031 /* This hook is called before a fix is simplified. We don't really
11032 decide whether to skip a fix here. Rather, we turn global symbols
11033 used as branch targets into local symbols, such that they undergo
11034 simplification. We can only do this if the symbol is defined and
11035 it is in the same section as the branch. If this doesn't hold, we
11036 emit a better error message than just saying the relocation is not
11037 valid for the selected object format.
11039 FIXP is the fix-up we're going to try to simplify, SEG is the
11040 segment in which the fix up occurs. The return value should be
11041 non-zero to indicate the fix-up is valid for further
11042 simplifications. */
11045 mips_validate_fix (struct fix *fixP, asection *seg)
11047 /* There's a lot of discussion on whether it should be possible to
11048 use R_MIPS_PC16 to represent branch relocations. The outcome
11049 seems to be that it can, but gas/bfd are very broken in creating
11050 RELA relocations for this, so for now we only accept branches to
11051 symbols in the same section. Anything else is of dubious value,
11052 since there's no guarantee that at link time the symbol would be
11053 in range. Even for branches to local symbols this is arguably
11054 wrong, since it we assume the symbol is not going to be
11055 overridden, which should be possible per ELF library semantics,
11056 but then, there isn't a dynamic relocation that could be used to
11057 this effect, and the target would likely be out of range as well.
11059 Unfortunately, it seems that there is too much code out there
11060 that relies on branches to symbols that are global to be resolved
11061 as if they were local, like the IRIX tools do, so we do it as
11062 well, but with a warning so that people are reminded to fix their
11063 code. If we ever get back to using R_MIPS_PC16 for branch
11064 targets, this entire block should go away (and probably the
11065 whole function). */
11067 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11068 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11069 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11070 && mips_pic != EMBEDDED_PIC)
11071 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11074 if (! S_IS_DEFINED (fixP->fx_addsy))
11076 as_bad_where (fixP->fx_file, fixP->fx_line,
11077 _("Cannot branch to undefined symbol."));
11078 /* Avoid any further errors about this fixup. */
11081 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11083 as_bad_where (fixP->fx_file, fixP->fx_line,
11084 _("Cannot branch to symbol in another section."));
11087 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11089 symbolS *sym = fixP->fx_addsy;
11091 if (mips_pic == SVR4_PIC)
11092 as_warn_where (fixP->fx_file, fixP->fx_line,
11093 _("Pretending global symbol used as branch target is local."));
11095 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11096 S_GET_SEGMENT (sym),
11098 symbol_get_frag (sym));
11099 copy_symbol_attributes (fixP->fx_addsy, sym);
11100 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11101 assert (symbol_resolved_p (sym));
11102 symbol_mark_resolved (fixP->fx_addsy);
11111 mips_need_elf_addend_fixup (fixS *fixP)
11113 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
11115 if (mips_pic == EMBEDDED_PIC
11116 && S_IS_WEAK (fixP->fx_addsy))
11118 if (mips_pic != EMBEDDED_PIC
11119 && (S_IS_WEAK (fixP->fx_addsy)
11120 || S_IS_EXTERNAL (fixP->fx_addsy))
11121 && !S_IS_COMMON (fixP->fx_addsy))
11123 if (((bfd_get_section_flags (stdoutput,
11124 S_GET_SEGMENT (fixP->fx_addsy))
11125 & (SEC_LINK_ONCE | SEC_MERGE)) != 0)
11126 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
11128 sizeof (".gnu.linkonce") - 1))
11134 /* Apply a fixup to the object file. */
11137 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11141 static int previous_fx_r_type = 0;
11142 reloc_howto_type *howto;
11144 /* We ignore generic BFD relocations we don't know about. */
11145 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11149 assert (fixP->fx_size == 4
11150 || fixP->fx_r_type == BFD_RELOC_16
11151 || fixP->fx_r_type == BFD_RELOC_64
11152 || fixP->fx_r_type == BFD_RELOC_CTOR
11153 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11154 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11155 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11157 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11159 /* If we aren't adjusting this fixup to be against the section
11160 symbol, we need to adjust the value. */
11162 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
11164 if (mips_need_elf_addend_fixup (fixP)
11165 && howto->partial_inplace
11166 && fixP->fx_r_type != BFD_RELOC_GPREL16
11167 && fixP->fx_r_type != BFD_RELOC_GPREL32
11168 && fixP->fx_r_type != BFD_RELOC_MIPS16_GPREL)
11170 /* In this case, the bfd_install_relocation routine will
11171 incorrectly add the symbol value back in. We just want
11172 the addend to appear in the object file.
11174 The condition above used to include
11175 "&& (! fixP->fx_pcrel || howto->pcrel_offset)".
11177 However, howto can't be trusted here, because we
11178 might change the reloc type in tc_gen_reloc. We can
11179 check howto->partial_inplace because that conversion
11180 happens to preserve howto->partial_inplace; but it
11181 does not preserve howto->pcrel_offset. I've just
11182 eliminated the check, because all MIPS PC-relative
11183 relocations are marked howto->pcrel_offset.
11185 howto->pcrel_offset was originally added for
11186 R_MIPS_PC16, which is generated for code like
11195 *valP -= S_GET_VALUE (fixP->fx_addsy);
11198 /* This code was generated using trial and error and so is
11199 fragile and not trustworthy. If you change it, you should
11200 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11201 they still pass. */
11202 if (fixP->fx_pcrel)
11204 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11206 /* BFD's REL handling, for MIPS, is _very_ weird.
11207 This gives the right results, but it can't possibly
11208 be the way things are supposed to work. */
11209 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11214 /* We are not done if this is a composite relocation to set up gp. */
11215 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11216 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11217 || (fixP->fx_r_type == BFD_RELOC_64
11218 && (previous_fx_r_type == BFD_RELOC_GPREL32
11219 || previous_fx_r_type == BFD_RELOC_GPREL16))
11220 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11221 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11222 || fixP->fx_r_type == BFD_RELOC_LO16))))
11224 previous_fx_r_type = fixP->fx_r_type;
11226 switch (fixP->fx_r_type)
11228 case BFD_RELOC_MIPS_JMP:
11229 case BFD_RELOC_MIPS_SHIFT5:
11230 case BFD_RELOC_MIPS_SHIFT6:
11231 case BFD_RELOC_MIPS_GOT_DISP:
11232 case BFD_RELOC_MIPS_GOT_PAGE:
11233 case BFD_RELOC_MIPS_GOT_OFST:
11234 case BFD_RELOC_MIPS_SUB:
11235 case BFD_RELOC_MIPS_INSERT_A:
11236 case BFD_RELOC_MIPS_INSERT_B:
11237 case BFD_RELOC_MIPS_DELETE:
11238 case BFD_RELOC_MIPS_HIGHEST:
11239 case BFD_RELOC_MIPS_HIGHER:
11240 case BFD_RELOC_MIPS_SCN_DISP:
11241 case BFD_RELOC_MIPS_REL16:
11242 case BFD_RELOC_MIPS_RELGOT:
11243 case BFD_RELOC_MIPS_JALR:
11244 case BFD_RELOC_HI16:
11245 case BFD_RELOC_HI16_S:
11246 case BFD_RELOC_GPREL16:
11247 case BFD_RELOC_MIPS_LITERAL:
11248 case BFD_RELOC_MIPS_CALL16:
11249 case BFD_RELOC_MIPS_GOT16:
11250 case BFD_RELOC_GPREL32:
11251 case BFD_RELOC_MIPS_GOT_HI16:
11252 case BFD_RELOC_MIPS_GOT_LO16:
11253 case BFD_RELOC_MIPS_CALL_HI16:
11254 case BFD_RELOC_MIPS_CALL_LO16:
11255 case BFD_RELOC_MIPS16_GPREL:
11256 if (fixP->fx_pcrel)
11257 as_bad_where (fixP->fx_file, fixP->fx_line,
11258 _("Invalid PC relative reloc"));
11259 /* Nothing needed to do. The value comes from the reloc entry */
11262 case BFD_RELOC_MIPS16_JMP:
11263 /* We currently always generate a reloc against a symbol, which
11264 means that we don't want an addend even if the symbol is
11269 case BFD_RELOC_PCREL_HI16_S:
11270 /* The addend for this is tricky if it is internal, so we just
11271 do everything here rather than in bfd_install_relocation. */
11272 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11275 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11277 /* For an external symbol adjust by the address to make it
11278 pcrel_offset. We use the address of the RELLO reloc
11279 which follows this one. */
11280 *valP += (fixP->fx_next->fx_frag->fr_address
11281 + fixP->fx_next->fx_where);
11283 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11284 if (target_big_endian)
11286 md_number_to_chars (buf, *valP, 2);
11289 case BFD_RELOC_PCREL_LO16:
11290 /* The addend for this is tricky if it is internal, so we just
11291 do everything here rather than in bfd_install_relocation. */
11292 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11295 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11296 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11297 if (target_big_endian)
11299 md_number_to_chars (buf, *valP, 2);
11303 /* This is handled like BFD_RELOC_32, but we output a sign
11304 extended value if we are only 32 bits. */
11306 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11308 if (8 <= sizeof (valueT))
11309 md_number_to_chars (buf, *valP, 8);
11314 if ((*valP & 0x80000000) != 0)
11318 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11320 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11326 case BFD_RELOC_RVA:
11328 /* If we are deleting this reloc entry, we must fill in the
11329 value now. This can happen if we have a .word which is not
11330 resolved when it appears but is later defined. We also need
11331 to fill in the value if this is an embedded PIC switch table
11334 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11335 md_number_to_chars (buf, *valP, 4);
11339 /* If we are deleting this reloc entry, we must fill in the
11341 assert (fixP->fx_size == 2);
11343 md_number_to_chars (buf, *valP, 2);
11346 case BFD_RELOC_LO16:
11347 /* When handling an embedded PIC switch statement, we can wind
11348 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11351 if (*valP + 0x8000 > 0xffff)
11352 as_bad_where (fixP->fx_file, fixP->fx_line,
11353 _("relocation overflow"));
11354 if (target_big_endian)
11356 md_number_to_chars (buf, *valP, 2);
11360 case BFD_RELOC_16_PCREL_S2:
11361 if ((*valP & 0x3) != 0)
11362 as_bad_where (fixP->fx_file, fixP->fx_line,
11363 _("Branch to odd address (%lx)"), (long) *valP);
11366 * We need to save the bits in the instruction since fixup_segment()
11367 * might be deleting the relocation entry (i.e., a branch within
11368 * the current segment).
11370 if (! fixP->fx_done)
11373 /* update old instruction data */
11374 if (target_big_endian)
11375 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11377 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11379 if (*valP + 0x20000 <= 0x3ffff)
11381 insn |= (*valP >> 2) & 0xffff;
11382 md_number_to_chars (buf, insn, 4);
11384 else if (mips_pic == NO_PIC
11386 && fixP->fx_frag->fr_address >= text_section->vma
11387 && (fixP->fx_frag->fr_address
11388 < text_section->vma + text_section->_raw_size)
11389 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11390 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11391 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11393 /* The branch offset is too large. If this is an
11394 unconditional branch, and we are not generating PIC code,
11395 we can convert it to an absolute jump instruction. */
11396 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11397 insn = 0x0c000000; /* jal */
11399 insn = 0x08000000; /* j */
11400 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11402 fixP->fx_addsy = section_symbol (text_section);
11403 *valP += md_pcrel_from (fixP);
11404 md_number_to_chars (buf, insn, 4);
11408 /* If we got here, we have branch-relaxation disabled,
11409 and there's nothing we can do to fix this instruction
11410 without turning it into a longer sequence. */
11411 as_bad_where (fixP->fx_file, fixP->fx_line,
11412 _("Branch out of range"));
11416 case BFD_RELOC_VTABLE_INHERIT:
11419 && !S_IS_DEFINED (fixP->fx_addsy)
11420 && !S_IS_WEAK (fixP->fx_addsy))
11421 S_SET_WEAK (fixP->fx_addsy);
11424 case BFD_RELOC_VTABLE_ENTRY:
11432 /* Remember value for tc_gen_reloc. */
11433 fixP->fx_addnumber = *valP;
11438 printInsn (unsigned long oc)
11440 const struct mips_opcode *p;
11441 int treg, sreg, dreg, shamt;
11446 for (i = 0; i < NUMOPCODES; ++i)
11448 p = &mips_opcodes[i];
11449 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11451 printf ("%08lx %s\t", oc, p->name);
11452 treg = (oc >> 16) & 0x1f;
11453 sreg = (oc >> 21) & 0x1f;
11454 dreg = (oc >> 11) & 0x1f;
11455 shamt = (oc >> 6) & 0x1f;
11457 for (args = p->args;; ++args)
11468 printf ("%c", *args);
11472 assert (treg == sreg);
11473 printf ("$%d,$%d", treg, sreg);
11478 printf ("$%d", dreg);
11483 printf ("$%d", treg);
11487 printf ("0x%x", treg);
11492 printf ("$%d", sreg);
11496 printf ("0x%08lx", oc & 0x1ffffff);
11503 printf ("%d", imm);
11508 printf ("$%d", shamt);
11519 printf (_("%08lx UNDEFINED\n"), oc);
11530 name = input_line_pointer;
11531 c = get_symbol_end ();
11532 p = (symbolS *) symbol_find_or_make (name);
11533 *input_line_pointer = c;
11537 /* Align the current frag to a given power of two. The MIPS assembler
11538 also automatically adjusts any preceding label. */
11541 mips_align (int to, int fill, symbolS *label)
11543 mips_emit_delays (FALSE);
11544 frag_align (to, fill, 0);
11545 record_alignment (now_seg, to);
11548 assert (S_GET_SEGMENT (label) == now_seg);
11549 symbol_set_frag (label, frag_now);
11550 S_SET_VALUE (label, (valueT) frag_now_fix ());
11554 /* Align to a given power of two. .align 0 turns off the automatic
11555 alignment used by the data creating pseudo-ops. */
11558 s_align (int x ATTRIBUTE_UNUSED)
11561 register long temp_fill;
11562 long max_alignment = 15;
11566 o Note that the assembler pulls down any immediately preceeding label
11567 to the aligned address.
11568 o It's not documented but auto alignment is reinstated by
11569 a .align pseudo instruction.
11570 o Note also that after auto alignment is turned off the mips assembler
11571 issues an error on attempt to assemble an improperly aligned data item.
11576 temp = get_absolute_expression ();
11577 if (temp > max_alignment)
11578 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11581 as_warn (_("Alignment negative: 0 assumed."));
11584 if (*input_line_pointer == ',')
11586 ++input_line_pointer;
11587 temp_fill = get_absolute_expression ();
11594 mips_align (temp, (int) temp_fill,
11595 insn_labels != NULL ? insn_labels->label : NULL);
11602 demand_empty_rest_of_line ();
11606 mips_flush_pending_output (void)
11608 mips_emit_delays (FALSE);
11609 mips_clear_insn_labels ();
11613 s_change_sec (int sec)
11617 /* When generating embedded PIC code, we only use the .text, .lit8,
11618 .sdata and .sbss sections. We change the .data and .rdata
11619 pseudo-ops to use .sdata. */
11620 if (mips_pic == EMBEDDED_PIC
11621 && (sec == 'd' || sec == 'r'))
11625 /* The ELF backend needs to know that we are changing sections, so
11626 that .previous works correctly. We could do something like check
11627 for an obj_section_change_hook macro, but that might be confusing
11628 as it would not be appropriate to use it in the section changing
11629 functions in read.c, since obj-elf.c intercepts those. FIXME:
11630 This should be cleaner, somehow. */
11631 obj_elf_section_change_hook ();
11634 mips_emit_delays (FALSE);
11644 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11645 demand_empty_rest_of_line ();
11649 if (USE_GLOBAL_POINTER_OPT)
11651 seg = subseg_new (RDATA_SECTION_NAME,
11652 (subsegT) get_absolute_expression ());
11653 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11655 bfd_set_section_flags (stdoutput, seg,
11661 if (strcmp (TARGET_OS, "elf") != 0)
11662 record_alignment (seg, 4);
11664 demand_empty_rest_of_line ();
11668 as_bad (_("No read only data section in this object file format"));
11669 demand_empty_rest_of_line ();
11675 if (USE_GLOBAL_POINTER_OPT)
11677 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11678 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11680 bfd_set_section_flags (stdoutput, seg,
11681 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11683 if (strcmp (TARGET_OS, "elf") != 0)
11684 record_alignment (seg, 4);
11686 demand_empty_rest_of_line ();
11691 as_bad (_("Global pointers not supported; recompile -G 0"));
11692 demand_empty_rest_of_line ();
11701 s_change_section (int ignore ATTRIBUTE_UNUSED)
11704 char *section_name;
11709 int section_entry_size;
11710 int section_alignment;
11712 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11715 section_name = input_line_pointer;
11716 c = get_symbol_end ();
11718 next_c = *(input_line_pointer + 1);
11720 /* Do we have .section Name<,"flags">? */
11721 if (c != ',' || (c == ',' && next_c == '"'))
11723 /* just after name is now '\0'. */
11724 *input_line_pointer = c;
11725 input_line_pointer = section_name;
11726 obj_elf_section (ignore);
11729 input_line_pointer++;
11731 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11733 section_type = get_absolute_expression ();
11736 if (*input_line_pointer++ == ',')
11737 section_flag = get_absolute_expression ();
11740 if (*input_line_pointer++ == ',')
11741 section_entry_size = get_absolute_expression ();
11743 section_entry_size = 0;
11744 if (*input_line_pointer++ == ',')
11745 section_alignment = get_absolute_expression ();
11747 section_alignment = 0;
11749 section_name = xstrdup (section_name);
11751 obj_elf_change_section (section_name, section_type, section_flag,
11752 section_entry_size, 0, 0, 0);
11754 if (now_seg->name != section_name)
11755 free (section_name);
11756 #endif /* OBJ_ELF */
11760 mips_enable_auto_align (void)
11766 s_cons (int log_size)
11770 label = insn_labels != NULL ? insn_labels->label : NULL;
11771 mips_emit_delays (FALSE);
11772 if (log_size > 0 && auto_align)
11773 mips_align (log_size, 0, label);
11774 mips_clear_insn_labels ();
11775 cons (1 << log_size);
11779 s_float_cons (int type)
11783 label = insn_labels != NULL ? insn_labels->label : NULL;
11785 mips_emit_delays (FALSE);
11790 mips_align (3, 0, label);
11792 mips_align (2, 0, label);
11795 mips_clear_insn_labels ();
11800 /* Handle .globl. We need to override it because on Irix 5 you are
11803 where foo is an undefined symbol, to mean that foo should be
11804 considered to be the address of a function. */
11807 s_mips_globl (int x ATTRIBUTE_UNUSED)
11814 name = input_line_pointer;
11815 c = get_symbol_end ();
11816 symbolP = symbol_find_or_make (name);
11817 *input_line_pointer = c;
11818 SKIP_WHITESPACE ();
11820 /* On Irix 5, every global symbol that is not explicitly labelled as
11821 being a function is apparently labelled as being an object. */
11824 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11829 secname = input_line_pointer;
11830 c = get_symbol_end ();
11831 sec = bfd_get_section_by_name (stdoutput, secname);
11833 as_bad (_("%s: no such section"), secname);
11834 *input_line_pointer = c;
11836 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11837 flag = BSF_FUNCTION;
11840 symbol_get_bfdsym (symbolP)->flags |= flag;
11842 S_SET_EXTERNAL (symbolP);
11843 demand_empty_rest_of_line ();
11847 s_option (int x ATTRIBUTE_UNUSED)
11852 opt = input_line_pointer;
11853 c = get_symbol_end ();
11857 /* FIXME: What does this mean? */
11859 else if (strncmp (opt, "pic", 3) == 0)
11863 i = atoi (opt + 3);
11868 mips_pic = SVR4_PIC;
11869 mips_abicalls = TRUE;
11872 as_bad (_(".option pic%d not supported"), i);
11874 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11876 if (g_switch_seen && g_switch_value != 0)
11877 as_warn (_("-G may not be used with SVR4 PIC code"));
11878 g_switch_value = 0;
11879 bfd_set_gp_size (stdoutput, 0);
11883 as_warn (_("Unrecognized option \"%s\""), opt);
11885 *input_line_pointer = c;
11886 demand_empty_rest_of_line ();
11889 /* This structure is used to hold a stack of .set values. */
11891 struct mips_option_stack
11893 struct mips_option_stack *next;
11894 struct mips_set_options options;
11897 static struct mips_option_stack *mips_opts_stack;
11899 /* Handle the .set pseudo-op. */
11902 s_mipsset (int x ATTRIBUTE_UNUSED)
11904 char *name = input_line_pointer, ch;
11906 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11907 ++input_line_pointer;
11908 ch = *input_line_pointer;
11909 *input_line_pointer = '\0';
11911 if (strcmp (name, "reorder") == 0)
11913 if (mips_opts.noreorder && prev_nop_frag != NULL)
11915 /* If we still have pending nops, we can discard them. The
11916 usual nop handling will insert any that are still
11918 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11919 * (mips_opts.mips16 ? 2 : 4));
11920 prev_nop_frag = NULL;
11922 mips_opts.noreorder = 0;
11924 else if (strcmp (name, "noreorder") == 0)
11926 mips_emit_delays (TRUE);
11927 mips_opts.noreorder = 1;
11928 mips_any_noreorder = 1;
11930 else if (strcmp (name, "at") == 0)
11932 mips_opts.noat = 0;
11934 else if (strcmp (name, "noat") == 0)
11936 mips_opts.noat = 1;
11938 else if (strcmp (name, "macro") == 0)
11940 mips_opts.warn_about_macros = 0;
11942 else if (strcmp (name, "nomacro") == 0)
11944 if (mips_opts.noreorder == 0)
11945 as_bad (_("`noreorder' must be set before `nomacro'"));
11946 mips_opts.warn_about_macros = 1;
11948 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11950 mips_opts.nomove = 0;
11952 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11954 mips_opts.nomove = 1;
11956 else if (strcmp (name, "bopt") == 0)
11958 mips_opts.nobopt = 0;
11960 else if (strcmp (name, "nobopt") == 0)
11962 mips_opts.nobopt = 1;
11964 else if (strcmp (name, "mips16") == 0
11965 || strcmp (name, "MIPS-16") == 0)
11966 mips_opts.mips16 = 1;
11967 else if (strcmp (name, "nomips16") == 0
11968 || strcmp (name, "noMIPS-16") == 0)
11969 mips_opts.mips16 = 0;
11970 else if (strcmp (name, "mips3d") == 0)
11971 mips_opts.ase_mips3d = 1;
11972 else if (strcmp (name, "nomips3d") == 0)
11973 mips_opts.ase_mips3d = 0;
11974 else if (strcmp (name, "mdmx") == 0)
11975 mips_opts.ase_mdmx = 1;
11976 else if (strcmp (name, "nomdmx") == 0)
11977 mips_opts.ase_mdmx = 0;
11978 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11982 /* Permit the user to change the ISA and architecture on the fly.
11983 Needless to say, misuse can cause serious problems. */
11984 if (strcmp (name, "mips0") == 0)
11987 mips_opts.isa = file_mips_isa;
11989 else if (strcmp (name, "mips1") == 0)
11990 mips_opts.isa = ISA_MIPS1;
11991 else if (strcmp (name, "mips2") == 0)
11992 mips_opts.isa = ISA_MIPS2;
11993 else if (strcmp (name, "mips3") == 0)
11994 mips_opts.isa = ISA_MIPS3;
11995 else if (strcmp (name, "mips4") == 0)
11996 mips_opts.isa = ISA_MIPS4;
11997 else if (strcmp (name, "mips5") == 0)
11998 mips_opts.isa = ISA_MIPS5;
11999 else if (strcmp (name, "mips32") == 0)
12000 mips_opts.isa = ISA_MIPS32;
12001 else if (strcmp (name, "mips32r2") == 0)
12002 mips_opts.isa = ISA_MIPS32R2;
12003 else if (strcmp (name, "mips64") == 0)
12004 mips_opts.isa = ISA_MIPS64;
12005 else if (strcmp (name, "arch=default") == 0)
12008 mips_opts.arch = file_mips_arch;
12009 mips_opts.isa = file_mips_isa;
12011 else if (strncmp (name, "arch=", 5) == 0)
12013 const struct mips_cpu_info *p;
12015 p = mips_parse_cpu("internal use", name + 5);
12017 as_bad (_("unknown architecture %s"), name + 5);
12020 mips_opts.arch = p->cpu;
12021 mips_opts.isa = p->isa;
12025 as_bad (_("unknown ISA level %s"), name + 4);
12027 switch (mips_opts.isa)
12035 mips_opts.gp32 = 1;
12036 mips_opts.fp32 = 1;
12042 mips_opts.gp32 = 0;
12043 mips_opts.fp32 = 0;
12046 as_bad (_("unknown ISA level %s"), name + 4);
12051 mips_opts.gp32 = file_mips_gp32;
12052 mips_opts.fp32 = file_mips_fp32;
12055 else if (strcmp (name, "autoextend") == 0)
12056 mips_opts.noautoextend = 0;
12057 else if (strcmp (name, "noautoextend") == 0)
12058 mips_opts.noautoextend = 1;
12059 else if (strcmp (name, "push") == 0)
12061 struct mips_option_stack *s;
12063 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12064 s->next = mips_opts_stack;
12065 s->options = mips_opts;
12066 mips_opts_stack = s;
12068 else if (strcmp (name, "pop") == 0)
12070 struct mips_option_stack *s;
12072 s = mips_opts_stack;
12074 as_bad (_(".set pop with no .set push"));
12077 /* If we're changing the reorder mode we need to handle
12078 delay slots correctly. */
12079 if (s->options.noreorder && ! mips_opts.noreorder)
12080 mips_emit_delays (TRUE);
12081 else if (! s->options.noreorder && mips_opts.noreorder)
12083 if (prev_nop_frag != NULL)
12085 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12086 * (mips_opts.mips16 ? 2 : 4));
12087 prev_nop_frag = NULL;
12091 mips_opts = s->options;
12092 mips_opts_stack = s->next;
12098 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12100 *input_line_pointer = ch;
12101 demand_empty_rest_of_line ();
12104 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12105 .option pic2. It means to generate SVR4 PIC calls. */
12108 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12110 mips_pic = SVR4_PIC;
12111 mips_abicalls = TRUE;
12112 if (USE_GLOBAL_POINTER_OPT)
12114 if (g_switch_seen && g_switch_value != 0)
12115 as_warn (_("-G may not be used with SVR4 PIC code"));
12116 g_switch_value = 0;
12118 bfd_set_gp_size (stdoutput, 0);
12119 demand_empty_rest_of_line ();
12122 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12123 PIC code. It sets the $gp register for the function based on the
12124 function address, which is in the register named in the argument.
12125 This uses a relocation against _gp_disp, which is handled specially
12126 by the linker. The result is:
12127 lui $gp,%hi(_gp_disp)
12128 addiu $gp,$gp,%lo(_gp_disp)
12129 addu $gp,$gp,.cpload argument
12130 The .cpload argument is normally $25 == $t9. */
12133 s_cpload (int ignore ATTRIBUTE_UNUSED)
12138 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12139 .cpload is ignored. */
12140 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12146 /* .cpload should be in a .set noreorder section. */
12147 if (mips_opts.noreorder == 0)
12148 as_warn (_(".cpload not in noreorder section"));
12150 ex.X_op = O_symbol;
12151 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12152 ex.X_op_symbol = NULL;
12153 ex.X_add_number = 0;
12155 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12156 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12158 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
12159 macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
12160 mips_gp_register, BFD_RELOC_LO16);
12162 macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
12163 mips_gp_register, tc_get_register (0));
12165 demand_empty_rest_of_line ();
12168 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12169 .cpsetup $reg1, offset|$reg2, label
12171 If offset is given, this results in:
12172 sd $gp, offset($sp)
12173 lui $gp, %hi(%neg(%gp_rel(label)))
12174 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12175 daddu $gp, $gp, $reg1
12177 If $reg2 is given, this results in:
12178 daddu $reg2, $gp, $0
12179 lui $gp, %hi(%neg(%gp_rel(label)))
12180 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12181 daddu $gp, $gp, $reg1
12182 $reg1 is normally $25 == $t9. */
12184 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12186 expressionS ex_off;
12187 expressionS ex_sym;
12192 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12193 We also need NewABI support. */
12194 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12200 reg1 = tc_get_register (0);
12201 SKIP_WHITESPACE ();
12202 if (*input_line_pointer != ',')
12204 as_bad (_("missing argument separator ',' for .cpsetup"));
12208 ++input_line_pointer;
12209 SKIP_WHITESPACE ();
12210 if (*input_line_pointer == '$')
12212 mips_cpreturn_register = tc_get_register (0);
12213 mips_cpreturn_offset = -1;
12217 mips_cpreturn_offset = get_absolute_expression ();
12218 mips_cpreturn_register = -1;
12220 SKIP_WHITESPACE ();
12221 if (*input_line_pointer != ',')
12223 as_bad (_("missing argument separator ',' for .cpsetup"));
12227 ++input_line_pointer;
12228 SKIP_WHITESPACE ();
12229 expression (&ex_sym);
12231 if (mips_cpreturn_register == -1)
12233 ex_off.X_op = O_constant;
12234 ex_off.X_add_symbol = NULL;
12235 ex_off.X_op_symbol = NULL;
12236 ex_off.X_add_number = mips_cpreturn_offset;
12238 macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
12239 BFD_RELOC_LO16, SP);
12242 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
12243 mips_gp_register, 0);
12245 /* Ensure there's room for the next two instructions, so that `f'
12246 doesn't end up with an address in the wrong frag. */
12249 macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
12250 BFD_RELOC_GPREL16);
12251 fix_new (frag_now, f - frag_now->fr_literal,
12252 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12253 fix_new (frag_now, f - frag_now->fr_literal,
12254 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12257 macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
12258 mips_gp_register, BFD_RELOC_GPREL16);
12259 fix_new (frag_now, f - frag_now->fr_literal,
12260 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12261 fix_new (frag_now, f - frag_now->fr_literal,
12262 4, NULL, 0, 0, BFD_RELOC_LO16);
12264 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12265 mips_gp_register, reg1);
12267 demand_empty_rest_of_line ();
12271 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12273 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12274 .cplocal is ignored. */
12275 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12281 mips_gp_register = tc_get_register (0);
12282 demand_empty_rest_of_line ();
12285 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12286 offset from $sp. The offset is remembered, and after making a PIC
12287 call $gp is restored from that location. */
12290 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12295 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12296 .cprestore is ignored. */
12297 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12303 mips_cprestore_offset = get_absolute_expression ();
12304 mips_cprestore_valid = 1;
12306 ex.X_op = O_constant;
12307 ex.X_add_symbol = NULL;
12308 ex.X_op_symbol = NULL;
12309 ex.X_add_number = mips_cprestore_offset;
12311 macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
12312 mips_gp_register, SP, HAVE_64BIT_ADDRESSES);
12314 demand_empty_rest_of_line ();
12317 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12318 was given in the preceeding .gpsetup, it results in:
12319 ld $gp, offset($sp)
12321 If a register $reg2 was given there, it results in:
12322 daddiu $gp, $gp, $reg2
12325 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12330 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12331 We also need NewABI support. */
12332 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12338 if (mips_cpreturn_register == -1)
12340 ex.X_op = O_constant;
12341 ex.X_add_symbol = NULL;
12342 ex.X_op_symbol = NULL;
12343 ex.X_add_number = mips_cpreturn_offset;
12345 macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
12346 BFD_RELOC_LO16, SP);
12349 macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
12350 mips_cpreturn_register, 0);
12352 demand_empty_rest_of_line ();
12355 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12356 code. It sets the offset to use in gp_rel relocations. */
12359 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12361 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12362 We also need NewABI support. */
12363 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12369 mips_gprel_offset = get_absolute_expression ();
12371 demand_empty_rest_of_line ();
12374 /* Handle the .gpword pseudo-op. This is used when generating PIC
12375 code. It generates a 32 bit GP relative reloc. */
12378 s_gpword (int ignore ATTRIBUTE_UNUSED)
12384 /* When not generating PIC code, this is treated as .word. */
12385 if (mips_pic != SVR4_PIC)
12391 label = insn_labels != NULL ? insn_labels->label : NULL;
12392 mips_emit_delays (TRUE);
12394 mips_align (2, 0, label);
12395 mips_clear_insn_labels ();
12399 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12401 as_bad (_("Unsupported use of .gpword"));
12402 ignore_rest_of_line ();
12406 md_number_to_chars (p, 0, 4);
12407 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12408 BFD_RELOC_GPREL32);
12410 demand_empty_rest_of_line ();
12414 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12420 /* When not generating PIC code, this is treated as .dword. */
12421 if (mips_pic != SVR4_PIC)
12427 label = insn_labels != NULL ? insn_labels->label : NULL;
12428 mips_emit_delays (TRUE);
12430 mips_align (3, 0, label);
12431 mips_clear_insn_labels ();
12435 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12437 as_bad (_("Unsupported use of .gpdword"));
12438 ignore_rest_of_line ();
12442 md_number_to_chars (p, 0, 8);
12443 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12444 BFD_RELOC_GPREL32);
12446 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12447 ex.X_op = O_absent;
12448 ex.X_add_symbol = 0;
12449 ex.X_add_number = 0;
12450 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12453 demand_empty_rest_of_line ();
12456 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12457 tables in SVR4 PIC code. */
12460 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12465 /* This is ignored when not generating SVR4 PIC code. */
12466 if (mips_pic != SVR4_PIC)
12472 /* Add $gp to the register named as an argument. */
12473 reg = tc_get_register (0);
12474 macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
12475 reg, reg, mips_gp_register);
12477 demand_empty_rest_of_line ();
12480 /* Handle the .insn pseudo-op. This marks instruction labels in
12481 mips16 mode. This permits the linker to handle them specially,
12482 such as generating jalx instructions when needed. We also make
12483 them odd for the duration of the assembly, in order to generate the
12484 right sort of code. We will make them even in the adjust_symtab
12485 routine, while leaving them marked. This is convenient for the
12486 debugger and the disassembler. The linker knows to make them odd
12490 s_insn (int ignore ATTRIBUTE_UNUSED)
12492 mips16_mark_labels ();
12494 demand_empty_rest_of_line ();
12497 /* Handle a .stabn directive. We need these in order to mark a label
12498 as being a mips16 text label correctly. Sometimes the compiler
12499 will emit a label, followed by a .stabn, and then switch sections.
12500 If the label and .stabn are in mips16 mode, then the label is
12501 really a mips16 text label. */
12504 s_mips_stab (int type)
12507 mips16_mark_labels ();
12512 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12516 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12523 name = input_line_pointer;
12524 c = get_symbol_end ();
12525 symbolP = symbol_find_or_make (name);
12526 S_SET_WEAK (symbolP);
12527 *input_line_pointer = c;
12529 SKIP_WHITESPACE ();
12531 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12533 if (S_IS_DEFINED (symbolP))
12535 as_bad ("ignoring attempt to redefine symbol %s",
12536 S_GET_NAME (symbolP));
12537 ignore_rest_of_line ();
12541 if (*input_line_pointer == ',')
12543 ++input_line_pointer;
12544 SKIP_WHITESPACE ();
12548 if (exp.X_op != O_symbol)
12550 as_bad ("bad .weakext directive");
12551 ignore_rest_of_line ();
12554 symbol_set_value_expression (symbolP, &exp);
12557 demand_empty_rest_of_line ();
12560 /* Parse a register string into a number. Called from the ECOFF code
12561 to parse .frame. The argument is non-zero if this is the frame
12562 register, so that we can record it in mips_frame_reg. */
12565 tc_get_register (int frame)
12569 SKIP_WHITESPACE ();
12570 if (*input_line_pointer++ != '$')
12572 as_warn (_("expected `$'"));
12575 else if (ISDIGIT (*input_line_pointer))
12577 reg = get_absolute_expression ();
12578 if (reg < 0 || reg >= 32)
12580 as_warn (_("Bad register number"));
12586 if (strncmp (input_line_pointer, "ra", 2) == 0)
12589 input_line_pointer += 2;
12591 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12594 input_line_pointer += 2;
12596 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12599 input_line_pointer += 2;
12601 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12604 input_line_pointer += 2;
12606 else if (strncmp (input_line_pointer, "at", 2) == 0)
12609 input_line_pointer += 2;
12611 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12614 input_line_pointer += 3;
12616 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12619 input_line_pointer += 3;
12621 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12624 input_line_pointer += 4;
12628 as_warn (_("Unrecognized register name"));
12630 while (ISALNUM(*input_line_pointer))
12631 input_line_pointer++;
12636 mips_frame_reg = reg != 0 ? reg : SP;
12637 mips_frame_reg_valid = 1;
12638 mips_cprestore_valid = 0;
12644 md_section_align (asection *seg, valueT addr)
12646 int align = bfd_get_section_alignment (stdoutput, seg);
12649 /* We don't need to align ELF sections to the full alignment.
12650 However, Irix 5 may prefer that we align them at least to a 16
12651 byte boundary. We don't bother to align the sections if we are
12652 targeted for an embedded system. */
12653 if (strcmp (TARGET_OS, "elf") == 0)
12659 return ((addr + (1 << align) - 1) & (-1 << align));
12662 /* Utility routine, called from above as well. If called while the
12663 input file is still being read, it's only an approximation. (For
12664 example, a symbol may later become defined which appeared to be
12665 undefined earlier.) */
12668 nopic_need_relax (symbolS *sym, int before_relaxing)
12673 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12675 const char *symname;
12678 /* Find out whether this symbol can be referenced off the $gp
12679 register. It can be if it is smaller than the -G size or if
12680 it is in the .sdata or .sbss section. Certain symbols can
12681 not be referenced off the $gp, although it appears as though
12683 symname = S_GET_NAME (sym);
12684 if (symname != (const char *) NULL
12685 && (strcmp (symname, "eprol") == 0
12686 || strcmp (symname, "etext") == 0
12687 || strcmp (symname, "_gp") == 0
12688 || strcmp (symname, "edata") == 0
12689 || strcmp (symname, "_fbss") == 0
12690 || strcmp (symname, "_fdata") == 0
12691 || strcmp (symname, "_ftext") == 0
12692 || strcmp (symname, "end") == 0
12693 || strcmp (symname, "_gp_disp") == 0))
12695 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12697 #ifndef NO_ECOFF_DEBUGGING
12698 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12699 && (symbol_get_obj (sym)->ecoff_extern_size
12700 <= g_switch_value))
12702 /* We must defer this decision until after the whole
12703 file has been read, since there might be a .extern
12704 after the first use of this symbol. */
12705 || (before_relaxing
12706 #ifndef NO_ECOFF_DEBUGGING
12707 && symbol_get_obj (sym)->ecoff_extern_size == 0
12709 && S_GET_VALUE (sym) == 0)
12710 || (S_GET_VALUE (sym) != 0
12711 && S_GET_VALUE (sym) <= g_switch_value)))
12715 const char *segname;
12717 segname = segment_name (S_GET_SEGMENT (sym));
12718 assert (strcmp (segname, ".lit8") != 0
12719 && strcmp (segname, ".lit4") != 0);
12720 change = (strcmp (segname, ".sdata") != 0
12721 && strcmp (segname, ".sbss") != 0
12722 && strncmp (segname, ".sdata.", 7) != 0
12723 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12728 /* We are not optimizing for the $gp register. */
12733 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12736 pic_need_relax (symbolS *sym, asection *segtype)
12739 bfd_boolean linkonce;
12741 /* Handle the case of a symbol equated to another symbol. */
12742 while (symbol_equated_reloc_p (sym))
12746 /* It's possible to get a loop here in a badly written
12748 n = symbol_get_value_expression (sym)->X_add_symbol;
12754 symsec = S_GET_SEGMENT (sym);
12756 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12758 if (symsec != segtype && ! S_IS_LOCAL (sym))
12760 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12764 /* The GNU toolchain uses an extension for ELF: a section
12765 beginning with the magic string .gnu.linkonce is a linkonce
12767 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12768 sizeof ".gnu.linkonce" - 1) == 0)
12772 /* This must duplicate the test in adjust_reloc_syms. */
12773 return (symsec != &bfd_und_section
12774 && symsec != &bfd_abs_section
12775 && ! bfd_is_com_section (symsec)
12778 /* A global or weak symbol is treated as external. */
12779 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12780 || (! S_IS_WEAK (sym)
12781 && (! S_IS_EXTERNAL (sym)
12782 || mips_pic == EMBEDDED_PIC)))
12788 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12789 extended opcode. SEC is the section the frag is in. */
12792 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12795 register const struct mips16_immed_operand *op;
12797 int mintiny, maxtiny;
12801 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12803 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12806 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12807 op = mips16_immed_operands;
12808 while (op->type != type)
12811 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12816 if (type == '<' || type == '>' || type == '[' || type == ']')
12819 maxtiny = 1 << op->nbits;
12824 maxtiny = (1 << op->nbits) - 1;
12829 mintiny = - (1 << (op->nbits - 1));
12830 maxtiny = (1 << (op->nbits - 1)) - 1;
12833 sym_frag = symbol_get_frag (fragp->fr_symbol);
12834 val = S_GET_VALUE (fragp->fr_symbol);
12835 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12841 /* We won't have the section when we are called from
12842 mips_relax_frag. However, we will always have been called
12843 from md_estimate_size_before_relax first. If this is a
12844 branch to a different section, we mark it as such. If SEC is
12845 NULL, and the frag is not marked, then it must be a branch to
12846 the same section. */
12849 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12854 /* Must have been called from md_estimate_size_before_relax. */
12857 fragp->fr_subtype =
12858 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12860 /* FIXME: We should support this, and let the linker
12861 catch branches and loads that are out of range. */
12862 as_bad_where (fragp->fr_file, fragp->fr_line,
12863 _("unsupported PC relative reference to different section"));
12867 if (fragp != sym_frag && sym_frag->fr_address == 0)
12868 /* Assume non-extended on the first relaxation pass.
12869 The address we have calculated will be bogus if this is
12870 a forward branch to another frag, as the forward frag
12871 will have fr_address == 0. */
12875 /* In this case, we know for sure that the symbol fragment is in
12876 the same section. If the relax_marker of the symbol fragment
12877 differs from the relax_marker of this fragment, we have not
12878 yet adjusted the symbol fragment fr_address. We want to add
12879 in STRETCH in order to get a better estimate of the address.
12880 This particularly matters because of the shift bits. */
12882 && sym_frag->relax_marker != fragp->relax_marker)
12886 /* Adjust stretch for any alignment frag. Note that if have
12887 been expanding the earlier code, the symbol may be
12888 defined in what appears to be an earlier frag. FIXME:
12889 This doesn't handle the fr_subtype field, which specifies
12890 a maximum number of bytes to skip when doing an
12892 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12894 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12897 stretch = - ((- stretch)
12898 & ~ ((1 << (int) f->fr_offset) - 1));
12900 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12909 addr = fragp->fr_address + fragp->fr_fix;
12911 /* The base address rules are complicated. The base address of
12912 a branch is the following instruction. The base address of a
12913 PC relative load or add is the instruction itself, but if it
12914 is in a delay slot (in which case it can not be extended) use
12915 the address of the instruction whose delay slot it is in. */
12916 if (type == 'p' || type == 'q')
12920 /* If we are currently assuming that this frag should be
12921 extended, then, the current address is two bytes
12923 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12926 /* Ignore the low bit in the target, since it will be set
12927 for a text label. */
12928 if ((val & 1) != 0)
12931 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12933 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12936 val -= addr & ~ ((1 << op->shift) - 1);
12938 /* Branch offsets have an implicit 0 in the lowest bit. */
12939 if (type == 'p' || type == 'q')
12942 /* If any of the shifted bits are set, we must use an extended
12943 opcode. If the address depends on the size of this
12944 instruction, this can lead to a loop, so we arrange to always
12945 use an extended opcode. We only check this when we are in
12946 the main relaxation loop, when SEC is NULL. */
12947 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12949 fragp->fr_subtype =
12950 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12954 /* If we are about to mark a frag as extended because the value
12955 is precisely maxtiny + 1, then there is a chance of an
12956 infinite loop as in the following code:
12961 In this case when the la is extended, foo is 0x3fc bytes
12962 away, so the la can be shrunk, but then foo is 0x400 away, so
12963 the la must be extended. To avoid this loop, we mark the
12964 frag as extended if it was small, and is about to become
12965 extended with a value of maxtiny + 1. */
12966 if (val == ((maxtiny + 1) << op->shift)
12967 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12970 fragp->fr_subtype =
12971 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12975 else if (symsec != absolute_section && sec != NULL)
12976 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12978 if ((val & ((1 << op->shift) - 1)) != 0
12979 || val < (mintiny << op->shift)
12980 || val > (maxtiny << op->shift))
12986 /* Compute the length of a branch sequence, and adjust the
12987 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12988 worst-case length is computed, with UPDATE being used to indicate
12989 whether an unconditional (-1), branch-likely (+1) or regular (0)
12990 branch is to be computed. */
12992 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12994 bfd_boolean toofar;
12998 && S_IS_DEFINED (fragp->fr_symbol)
12999 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13004 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13006 addr = fragp->fr_address + fragp->fr_fix + 4;
13010 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13013 /* If the symbol is not defined or it's in a different segment,
13014 assume the user knows what's going on and emit a short
13020 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13022 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13023 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13024 RELAX_BRANCH_LINK (fragp->fr_subtype),
13030 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13033 if (mips_pic != NO_PIC)
13035 /* Additional space for PIC loading of target address. */
13037 if (mips_opts.isa == ISA_MIPS1)
13038 /* Additional space for $at-stabilizing nop. */
13042 /* If branch is conditional. */
13043 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13050 /* Estimate the size of a frag before relaxing. Unless this is the
13051 mips16, we are not really relaxing here, and the final size is
13052 encoded in the subtype information. For the mips16, we have to
13053 decide whether we are using an extended opcode or not. */
13056 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13060 if (RELAX_BRANCH_P (fragp->fr_subtype))
13063 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13065 return fragp->fr_var;
13068 if (RELAX_MIPS16_P (fragp->fr_subtype))
13069 /* We don't want to modify the EXTENDED bit here; it might get us
13070 into infinite loops. We change it only in mips_relax_frag(). */
13071 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13073 if (mips_pic == NO_PIC)
13074 change = nopic_need_relax (fragp->fr_symbol, 0);
13075 else if (mips_pic == SVR4_PIC)
13076 change = pic_need_relax (fragp->fr_symbol, segtype);
13082 /* Record the offset to the first reloc in the fr_opcode field.
13083 This lets md_convert_frag and tc_gen_reloc know that the code
13084 must be expanded. */
13085 fragp->fr_opcode = (fragp->fr_literal
13087 - RELAX_OLD (fragp->fr_subtype)
13088 + RELAX_RELOC1 (fragp->fr_subtype));
13089 /* FIXME: This really needs as_warn_where. */
13090 if (RELAX_WARN (fragp->fr_subtype))
13091 as_warn (_("AT used after \".set noat\" or macro used after "
13092 "\".set nomacro\""));
13094 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
13100 /* This is called to see whether a reloc against a defined symbol
13101 should be converted into a reloc against a section. Don't adjust
13102 MIPS16 jump relocations, so we don't have to worry about the format
13103 of the offset in the .o file. Don't adjust relocations against
13104 mips16 symbols, so that the linker can find them if it needs to set
13108 mips_fix_adjustable (fixS *fixp)
13110 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13113 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13114 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13117 if (fixp->fx_addsy == NULL)
13121 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13122 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13123 && fixp->fx_subsy == NULL)
13130 /* Translate internal representation of relocation info to BFD target
13134 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13136 static arelent *retval[4];
13138 bfd_reloc_code_real_type code;
13140 memset (retval, 0, sizeof(retval));
13141 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13142 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13143 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13144 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13146 if (mips_pic == EMBEDDED_PIC
13147 && SWITCH_TABLE (fixp))
13149 /* For a switch table entry we use a special reloc. The addend
13150 is actually the difference between the reloc address and the
13152 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13153 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13154 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13155 fixp->fx_r_type = BFD_RELOC_GPREL32;
13157 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
13159 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13160 reloc->addend = fixp->fx_addnumber;
13163 /* We use a special addend for an internal RELLO reloc. */
13164 if (symbol_section_p (fixp->fx_addsy))
13165 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13167 reloc->addend = fixp->fx_addnumber + reloc->address;
13170 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13172 assert (fixp->fx_next != NULL
13173 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13175 /* The reloc is relative to the RELLO; adjust the addend
13177 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13178 reloc->addend = fixp->fx_next->fx_addnumber;
13181 /* We use a special addend for an internal RELHI reloc. */
13182 if (symbol_section_p (fixp->fx_addsy))
13183 reloc->addend = (fixp->fx_next->fx_frag->fr_address
13184 + fixp->fx_next->fx_where
13185 - S_GET_VALUE (fixp->fx_subsy));
13187 reloc->addend = (fixp->fx_addnumber
13188 + fixp->fx_next->fx_frag->fr_address
13189 + fixp->fx_next->fx_where);
13192 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13193 reloc->addend = fixp->fx_addnumber;
13196 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13197 /* A gruesome hack which is a result of the gruesome gas reloc
13199 reloc->addend = reloc->address;
13201 reloc->addend = -reloc->address;
13204 /* If this is a variant frag, we may need to adjust the existing
13205 reloc and generate a new one. */
13206 if (fixp->fx_frag->fr_opcode != NULL
13207 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
13209 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_DISP
13211 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
13212 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
13213 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13214 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
13215 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13216 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
13221 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
13223 /* If this is not the last reloc in this frag, then we have two
13224 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13225 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13226 the second one handle all of them. */
13227 if (fixp->fx_next != NULL
13228 && fixp->fx_frag == fixp->fx_next->fx_frag)
13230 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
13231 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
13232 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
13233 && (fixp->fx_next->fx_r_type
13234 == BFD_RELOC_MIPS_GOT_LO16))
13235 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
13236 && (fixp->fx_next->fx_r_type
13237 == BFD_RELOC_MIPS_CALL_LO16)));
13242 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
13243 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13244 reloc->addend += fixp->fx_frag->tc_frag_data.tc_fr_offset;
13245 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
13246 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13247 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13248 reloc2->address = (reloc->address
13249 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
13250 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
13251 reloc2->addend = fixp->fx_addnumber - S_GET_VALUE (fixp->fx_addsy)
13252 + fixp->fx_frag->tc_frag_data.tc_fr_offset;
13253 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
13254 assert (reloc2->howto != NULL);
13256 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
13260 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
13262 reloc3->address += 4;
13265 if (mips_pic == NO_PIC)
13267 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
13268 fixp->fx_r_type = BFD_RELOC_HI16_S;
13270 else if (mips_pic == SVR4_PIC)
13272 switch (fixp->fx_r_type)
13276 case BFD_RELOC_MIPS_GOT16:
13278 case BFD_RELOC_MIPS_GOT_LO16:
13279 case BFD_RELOC_MIPS_CALL_LO16:
13282 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
13283 reloc2->howto = bfd_reloc_type_lookup
13284 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
13287 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13289 case BFD_RELOC_MIPS_CALL16:
13290 case BFD_RELOC_MIPS_GOT_OFST:
13291 case BFD_RELOC_MIPS_GOT_DISP:
13294 /* It may seem nonsensical to relax GOT_DISP to
13295 GOT_DISP, but we're actually turning a GOT_DISP
13296 without offset into a GOT_DISP with an offset,
13297 getting rid of the separate addition, which we can
13298 do when the symbol is found to be local. */
13299 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
13303 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
13311 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13312 entry to be used in the relocation's section offset. */
13313 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13315 reloc->address = reloc->addend;
13319 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13320 fixup_segment converted a non-PC relative reloc into a PC
13321 relative reloc. In such a case, we need to convert the reloc
13323 code = fixp->fx_r_type;
13324 if (fixp->fx_pcrel)
13329 code = BFD_RELOC_8_PCREL;
13332 code = BFD_RELOC_16_PCREL;
13335 code = BFD_RELOC_32_PCREL;
13338 code = BFD_RELOC_64_PCREL;
13340 case BFD_RELOC_8_PCREL:
13341 case BFD_RELOC_16_PCREL:
13342 case BFD_RELOC_32_PCREL:
13343 case BFD_RELOC_64_PCREL:
13344 case BFD_RELOC_16_PCREL_S2:
13345 case BFD_RELOC_PCREL_HI16_S:
13346 case BFD_RELOC_PCREL_LO16:
13349 as_bad_where (fixp->fx_file, fixp->fx_line,
13350 _("Cannot make %s relocation PC relative"),
13351 bfd_get_reloc_code_name (code));
13355 /* To support a PC relative reloc when generating embedded PIC code
13356 for ECOFF, we use a Cygnus extension. We check for that here to
13357 make sure that we don't let such a reloc escape normally. */
13358 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13359 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13360 && code == BFD_RELOC_16_PCREL_S2
13361 && mips_pic != EMBEDDED_PIC)
13362 reloc->howto = NULL;
13364 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13366 if (reloc->howto == NULL)
13368 as_bad_where (fixp->fx_file, fixp->fx_line,
13369 _("Can not represent %s relocation in this object file format"),
13370 bfd_get_reloc_code_name (code));
13377 /* Relax a machine dependent frag. This returns the amount by which
13378 the current size of the frag should change. */
13381 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13383 if (RELAX_BRANCH_P (fragp->fr_subtype))
13385 offsetT old_var = fragp->fr_var;
13387 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13389 return fragp->fr_var - old_var;
13392 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13395 if (mips16_extended_frag (fragp, NULL, stretch))
13397 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13399 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13404 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13406 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13413 /* Convert a machine dependent frag. */
13416 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13421 if (RELAX_BRANCH_P (fragp->fr_subtype))
13424 unsigned long insn;
13428 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13430 if (target_big_endian)
13431 insn = bfd_getb32 (buf);
13433 insn = bfd_getl32 (buf);
13435 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13437 /* We generate a fixup instead of applying it right now
13438 because, if there are linker relaxations, we're going to
13439 need the relocations. */
13440 exp.X_op = O_symbol;
13441 exp.X_add_symbol = fragp->fr_symbol;
13442 exp.X_add_number = fragp->fr_offset;
13444 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13446 BFD_RELOC_16_PCREL_S2);
13447 fixp->fx_file = fragp->fr_file;
13448 fixp->fx_line = fragp->fr_line;
13450 md_number_to_chars (buf, insn, 4);
13457 as_warn_where (fragp->fr_file, fragp->fr_line,
13458 _("relaxed out-of-range branch into a jump"));
13460 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13463 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13465 /* Reverse the branch. */
13466 switch ((insn >> 28) & 0xf)
13469 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13470 have the condition reversed by tweaking a single
13471 bit, and their opcodes all have 0x4???????. */
13472 assert ((insn & 0xf1000000) == 0x41000000);
13473 insn ^= 0x00010000;
13477 /* bltz 0x04000000 bgez 0x04010000
13478 bltzal 0x04100000 bgezal 0x04110000 */
13479 assert ((insn & 0xfc0e0000) == 0x04000000);
13480 insn ^= 0x00010000;
13484 /* beq 0x10000000 bne 0x14000000
13485 blez 0x18000000 bgtz 0x1c000000 */
13486 insn ^= 0x04000000;
13494 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13496 /* Clear the and-link bit. */
13497 assert ((insn & 0xfc1c0000) == 0x04100000);
13499 /* bltzal 0x04100000 bgezal 0x04110000
13500 bltzall 0x04120000 bgezall 0x04130000 */
13501 insn &= ~0x00100000;
13504 /* Branch over the branch (if the branch was likely) or the
13505 full jump (not likely case). Compute the offset from the
13506 current instruction to branch to. */
13507 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13511 /* How many bytes in instructions we've already emitted? */
13512 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13513 /* How many bytes in instructions from here to the end? */
13514 i = fragp->fr_var - i;
13516 /* Convert to instruction count. */
13518 /* Branch counts from the next instruction. */
13521 /* Branch over the jump. */
13522 md_number_to_chars (buf, insn, 4);
13526 md_number_to_chars (buf, 0, 4);
13529 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13531 /* beql $0, $0, 2f */
13533 /* Compute the PC offset from the current instruction to
13534 the end of the variable frag. */
13535 /* How many bytes in instructions we've already emitted? */
13536 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13537 /* How many bytes in instructions from here to the end? */
13538 i = fragp->fr_var - i;
13539 /* Convert to instruction count. */
13541 /* Don't decrement i, because we want to branch over the
13545 md_number_to_chars (buf, insn, 4);
13548 md_number_to_chars (buf, 0, 4);
13553 if (mips_pic == NO_PIC)
13556 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13557 ? 0x0c000000 : 0x08000000);
13558 exp.X_op = O_symbol;
13559 exp.X_add_symbol = fragp->fr_symbol;
13560 exp.X_add_number = fragp->fr_offset;
13562 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13563 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13564 fixp->fx_file = fragp->fr_file;
13565 fixp->fx_line = fragp->fr_line;
13567 md_number_to_chars (buf, insn, 4);
13572 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13573 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13574 exp.X_op = O_symbol;
13575 exp.X_add_symbol = fragp->fr_symbol;
13576 exp.X_add_number = fragp->fr_offset;
13578 if (fragp->fr_offset)
13580 exp.X_add_symbol = make_expr_symbol (&exp);
13581 exp.X_add_number = 0;
13584 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13585 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13586 fixp->fx_file = fragp->fr_file;
13587 fixp->fx_line = fragp->fr_line;
13589 md_number_to_chars (buf, insn, 4);
13592 if (mips_opts.isa == ISA_MIPS1)
13595 md_number_to_chars (buf, 0, 4);
13599 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13600 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13602 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13603 4, &exp, 0, BFD_RELOC_LO16);
13604 fixp->fx_file = fragp->fr_file;
13605 fixp->fx_line = fragp->fr_line;
13607 md_number_to_chars (buf, insn, 4);
13611 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13616 md_number_to_chars (buf, insn, 4);
13621 assert (buf == (bfd_byte *)fragp->fr_literal
13622 + fragp->fr_fix + fragp->fr_var);
13624 fragp->fr_fix += fragp->fr_var;
13629 if (RELAX_MIPS16_P (fragp->fr_subtype))
13632 register const struct mips16_immed_operand *op;
13633 bfd_boolean small, ext;
13636 unsigned long insn;
13637 bfd_boolean use_extend;
13638 unsigned short extend;
13640 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13641 op = mips16_immed_operands;
13642 while (op->type != type)
13645 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13656 resolve_symbol_value (fragp->fr_symbol);
13657 val = S_GET_VALUE (fragp->fr_symbol);
13662 addr = fragp->fr_address + fragp->fr_fix;
13664 /* The rules for the base address of a PC relative reloc are
13665 complicated; see mips16_extended_frag. */
13666 if (type == 'p' || type == 'q')
13671 /* Ignore the low bit in the target, since it will be
13672 set for a text label. */
13673 if ((val & 1) != 0)
13676 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13678 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13681 addr &= ~ (addressT) ((1 << op->shift) - 1);
13684 /* Make sure the section winds up with the alignment we have
13687 record_alignment (asec, op->shift);
13691 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13692 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13693 as_warn_where (fragp->fr_file, fragp->fr_line,
13694 _("extended instruction in delay slot"));
13696 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13698 if (target_big_endian)
13699 insn = bfd_getb16 (buf);
13701 insn = bfd_getl16 (buf);
13703 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13704 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13705 small, ext, &insn, &use_extend, &extend);
13709 md_number_to_chars (buf, 0xf000 | extend, 2);
13710 fragp->fr_fix += 2;
13714 md_number_to_chars (buf, insn, 2);
13715 fragp->fr_fix += 2;
13720 if (fragp->fr_opcode == NULL)
13723 old = RELAX_OLD (fragp->fr_subtype);
13724 new = RELAX_NEW (fragp->fr_subtype);
13725 fixptr = fragp->fr_literal + fragp->fr_fix;
13728 memmove (fixptr - old, fixptr, new);
13730 fragp->fr_fix += new - old;
13736 /* This function is called after the relocs have been generated.
13737 We've been storing mips16 text labels as odd. Here we convert them
13738 back to even for the convenience of the debugger. */
13741 mips_frob_file_after_relocs (void)
13744 unsigned int count, i;
13746 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13749 syms = bfd_get_outsymbols (stdoutput);
13750 count = bfd_get_symcount (stdoutput);
13751 for (i = 0; i < count; i++, syms++)
13753 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13754 && ((*syms)->value & 1) != 0)
13756 (*syms)->value &= ~1;
13757 /* If the symbol has an odd size, it was probably computed
13758 incorrectly, so adjust that as well. */
13759 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13760 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13767 /* This function is called whenever a label is defined. It is used
13768 when handling branch delays; if a branch has a label, we assume we
13769 can not move it. */
13772 mips_define_label (symbolS *sym)
13774 struct insn_label_list *l;
13776 if (free_insn_labels == NULL)
13777 l = (struct insn_label_list *) xmalloc (sizeof *l);
13780 l = free_insn_labels;
13781 free_insn_labels = l->next;
13785 l->next = insn_labels;
13789 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13791 /* Some special processing for a MIPS ELF file. */
13794 mips_elf_final_processing (void)
13796 /* Write out the register information. */
13797 if (mips_abi != N64_ABI)
13801 s.ri_gprmask = mips_gprmask;
13802 s.ri_cprmask[0] = mips_cprmask[0];
13803 s.ri_cprmask[1] = mips_cprmask[1];
13804 s.ri_cprmask[2] = mips_cprmask[2];
13805 s.ri_cprmask[3] = mips_cprmask[3];
13806 /* The gp_value field is set by the MIPS ELF backend. */
13808 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13809 ((Elf32_External_RegInfo *)
13810 mips_regmask_frag));
13814 Elf64_Internal_RegInfo s;
13816 s.ri_gprmask = mips_gprmask;
13818 s.ri_cprmask[0] = mips_cprmask[0];
13819 s.ri_cprmask[1] = mips_cprmask[1];
13820 s.ri_cprmask[2] = mips_cprmask[2];
13821 s.ri_cprmask[3] = mips_cprmask[3];
13822 /* The gp_value field is set by the MIPS ELF backend. */
13824 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13825 ((Elf64_External_RegInfo *)
13826 mips_regmask_frag));
13829 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13830 sort of BFD interface for this. */
13831 if (mips_any_noreorder)
13832 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13833 if (mips_pic != NO_PIC)
13835 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13836 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13839 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13841 /* Set MIPS ELF flags for ASEs. */
13842 if (file_ase_mips16)
13843 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13844 #if 0 /* XXX FIXME */
13845 if (file_ase_mips3d)
13846 elf_elfheader (stdoutput)->e_flags |= ???;
13849 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13851 /* Set the MIPS ELF ABI flags. */
13852 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13853 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13854 else if (mips_abi == O64_ABI)
13855 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13856 else if (mips_abi == EABI_ABI)
13858 if (!file_mips_gp32)
13859 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13861 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13863 else if (mips_abi == N32_ABI)
13864 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13866 /* Nothing to do for N64_ABI. */
13868 if (mips_32bitmode)
13869 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13872 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13874 typedef struct proc {
13876 unsigned long reg_mask;
13877 unsigned long reg_offset;
13878 unsigned long fpreg_mask;
13879 unsigned long fpreg_offset;
13880 unsigned long frame_offset;
13881 unsigned long frame_reg;
13882 unsigned long pc_reg;
13885 static procS cur_proc;
13886 static procS *cur_proc_ptr;
13887 static int numprocs;
13889 /* Fill in an rs_align_code fragment. */
13892 mips_handle_align (fragS *fragp)
13894 if (fragp->fr_type != rs_align_code)
13897 if (mips_opts.mips16)
13899 static const unsigned char be_nop[] = { 0x65, 0x00 };
13900 static const unsigned char le_nop[] = { 0x00, 0x65 };
13905 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13906 p = fragp->fr_literal + fragp->fr_fix;
13914 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13918 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13922 md_obj_begin (void)
13929 /* check for premature end, nesting errors, etc */
13931 as_warn (_("missing .end at end of assembly"));
13940 if (*input_line_pointer == '-')
13942 ++input_line_pointer;
13945 if (!ISDIGIT (*input_line_pointer))
13946 as_bad (_("expected simple number"));
13947 if (input_line_pointer[0] == '0')
13949 if (input_line_pointer[1] == 'x')
13951 input_line_pointer += 2;
13952 while (ISXDIGIT (*input_line_pointer))
13955 val |= hex_value (*input_line_pointer++);
13957 return negative ? -val : val;
13961 ++input_line_pointer;
13962 while (ISDIGIT (*input_line_pointer))
13965 val |= *input_line_pointer++ - '0';
13967 return negative ? -val : val;
13970 if (!ISDIGIT (*input_line_pointer))
13972 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13973 *input_line_pointer, *input_line_pointer);
13974 as_warn (_("invalid number"));
13977 while (ISDIGIT (*input_line_pointer))
13980 val += *input_line_pointer++ - '0';
13982 return negative ? -val : val;
13985 /* The .file directive; just like the usual .file directive, but there
13986 is an initial number which is the ECOFF file index. In the non-ECOFF
13987 case .file implies DWARF-2. */
13990 s_mips_file (int x ATTRIBUTE_UNUSED)
13992 static int first_file_directive = 0;
13994 if (ECOFF_DEBUGGING)
14003 filename = dwarf2_directive_file (0);
14005 /* Versions of GCC up to 3.1 start files with a ".file"
14006 directive even for stabs output. Make sure that this
14007 ".file" is handled. Note that you need a version of GCC
14008 after 3.1 in order to support DWARF-2 on MIPS. */
14009 if (filename != NULL && ! first_file_directive)
14011 (void) new_logical_line (filename, -1);
14012 s_app_file_string (filename);
14014 first_file_directive = 1;
14018 /* The .loc directive, implying DWARF-2. */
14021 s_mips_loc (int x ATTRIBUTE_UNUSED)
14023 if (!ECOFF_DEBUGGING)
14024 dwarf2_directive_loc (0);
14027 /* The .end directive. */
14030 s_mips_end (int x ATTRIBUTE_UNUSED)
14034 /* Following functions need their own .frame and .cprestore directives. */
14035 mips_frame_reg_valid = 0;
14036 mips_cprestore_valid = 0;
14038 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14041 demand_empty_rest_of_line ();
14046 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14047 as_warn (_(".end not in text section"));
14051 as_warn (_(".end directive without a preceding .ent directive."));
14052 demand_empty_rest_of_line ();
14058 assert (S_GET_NAME (p));
14059 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14060 as_warn (_(".end symbol does not match .ent symbol."));
14062 if (debug_type == DEBUG_STABS)
14063 stabs_generate_asm_endfunc (S_GET_NAME (p),
14067 as_warn (_(".end directive missing or unknown symbol"));
14070 /* Generate a .pdr section. */
14071 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14074 segT saved_seg = now_seg;
14075 subsegT saved_subseg = now_subseg;
14080 dot = frag_now_fix ();
14082 #ifdef md_flush_pending_output
14083 md_flush_pending_output ();
14087 subseg_set (pdr_seg, 0);
14089 /* Write the symbol. */
14090 exp.X_op = O_symbol;
14091 exp.X_add_symbol = p;
14092 exp.X_add_number = 0;
14093 emit_expr (&exp, 4);
14095 fragp = frag_more (7 * 4);
14097 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14098 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14099 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14100 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14101 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14102 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14103 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14105 subseg_set (saved_seg, saved_subseg);
14107 #endif /* OBJ_ELF */
14109 cur_proc_ptr = NULL;
14112 /* The .aent and .ent directives. */
14115 s_mips_ent (int aent)
14119 symbolP = get_symbol ();
14120 if (*input_line_pointer == ',')
14121 ++input_line_pointer;
14122 SKIP_WHITESPACE ();
14123 if (ISDIGIT (*input_line_pointer)
14124 || *input_line_pointer == '-')
14127 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14128 as_warn (_(".ent or .aent not in text section."));
14130 if (!aent && cur_proc_ptr)
14131 as_warn (_("missing .end"));
14135 /* This function needs its own .frame and .cprestore directives. */
14136 mips_frame_reg_valid = 0;
14137 mips_cprestore_valid = 0;
14139 cur_proc_ptr = &cur_proc;
14140 memset (cur_proc_ptr, '\0', sizeof (procS));
14142 cur_proc_ptr->isym = symbolP;
14144 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14148 if (debug_type == DEBUG_STABS)
14149 stabs_generate_asm_func (S_GET_NAME (symbolP),
14150 S_GET_NAME (symbolP));
14153 demand_empty_rest_of_line ();
14156 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14157 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14158 s_mips_frame is used so that we can set the PDR information correctly.
14159 We can't use the ecoff routines because they make reference to the ecoff
14160 symbol table (in the mdebug section). */
14163 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14166 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14170 if (cur_proc_ptr == (procS *) NULL)
14172 as_warn (_(".frame outside of .ent"));
14173 demand_empty_rest_of_line ();
14177 cur_proc_ptr->frame_reg = tc_get_register (1);
14179 SKIP_WHITESPACE ();
14180 if (*input_line_pointer++ != ','
14181 || get_absolute_expression_and_terminator (&val) != ',')
14183 as_warn (_("Bad .frame directive"));
14184 --input_line_pointer;
14185 demand_empty_rest_of_line ();
14189 cur_proc_ptr->frame_offset = val;
14190 cur_proc_ptr->pc_reg = tc_get_register (0);
14192 demand_empty_rest_of_line ();
14195 #endif /* OBJ_ELF */
14199 /* The .fmask and .mask directives. If the mdebug section is present
14200 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14201 embedded targets, s_mips_mask is used so that we can set the PDR
14202 information correctly. We can't use the ecoff routines because they
14203 make reference to the ecoff symbol table (in the mdebug section). */
14206 s_mips_mask (int reg_type)
14209 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14213 if (cur_proc_ptr == (procS *) NULL)
14215 as_warn (_(".mask/.fmask outside of .ent"));
14216 demand_empty_rest_of_line ();
14220 if (get_absolute_expression_and_terminator (&mask) != ',')
14222 as_warn (_("Bad .mask/.fmask directive"));
14223 --input_line_pointer;
14224 demand_empty_rest_of_line ();
14228 off = get_absolute_expression ();
14230 if (reg_type == 'F')
14232 cur_proc_ptr->fpreg_mask = mask;
14233 cur_proc_ptr->fpreg_offset = off;
14237 cur_proc_ptr->reg_mask = mask;
14238 cur_proc_ptr->reg_offset = off;
14241 demand_empty_rest_of_line ();
14244 #endif /* OBJ_ELF */
14245 s_ignore (reg_type);
14248 /* The .loc directive. */
14258 assert (now_seg == text_section);
14260 lineno = get_number ();
14261 addroff = frag_now_fix ();
14263 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14264 S_SET_TYPE (symbolP, N_SLINE);
14265 S_SET_OTHER (symbolP, 0);
14266 S_SET_DESC (symbolP, lineno);
14267 symbolP->sy_segment = now_seg;
14271 /* A table describing all the processors gas knows about. Names are
14272 matched in the order listed.
14274 To ease comparison, please keep this table in the same order as
14275 gcc's mips_cpu_info_table[]. */
14276 static const struct mips_cpu_info mips_cpu_info_table[] =
14278 /* Entries for generic ISAs */
14279 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14280 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14281 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14282 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14283 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14284 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14285 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14286 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14289 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14290 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14291 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14294 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14297 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14298 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14299 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14300 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14301 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14302 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14303 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14304 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14305 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14306 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14307 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14308 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14311 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14312 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14313 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14314 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14315 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14316 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14317 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14318 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14319 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14320 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14321 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14322 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14323 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14326 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14327 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14328 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14331 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14332 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14334 /* Broadcom SB-1 CPU core */
14335 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14342 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14343 with a final "000" replaced by "k". Ignore case.
14345 Note: this function is shared between GCC and GAS. */
14348 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14350 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14351 given++, canonical++;
14353 return ((*given == 0 && *canonical == 0)
14354 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14358 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14359 CPU name. We've traditionally allowed a lot of variation here.
14361 Note: this function is shared between GCC and GAS. */
14364 mips_matching_cpu_name_p (const char *canonical, const char *given)
14366 /* First see if the name matches exactly, or with a final "000"
14367 turned into "k". */
14368 if (mips_strict_matching_cpu_name_p (canonical, given))
14371 /* If not, try comparing based on numerical designation alone.
14372 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14373 if (TOLOWER (*given) == 'r')
14375 if (!ISDIGIT (*given))
14378 /* Skip over some well-known prefixes in the canonical name,
14379 hoping to find a number there too. */
14380 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14382 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14384 else if (TOLOWER (canonical[0]) == 'r')
14387 return mips_strict_matching_cpu_name_p (canonical, given);
14391 /* Parse an option that takes the name of a processor as its argument.
14392 OPTION is the name of the option and CPU_STRING is the argument.
14393 Return the corresponding processor enumeration if the CPU_STRING is
14394 recognized, otherwise report an error and return null.
14396 A similar function exists in GCC. */
14398 static const struct mips_cpu_info *
14399 mips_parse_cpu (const char *option, const char *cpu_string)
14401 const struct mips_cpu_info *p;
14403 /* 'from-abi' selects the most compatible architecture for the given
14404 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14405 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14406 version. Look first at the -mgp options, if given, otherwise base
14407 the choice on MIPS_DEFAULT_64BIT.
14409 Treat NO_ABI like the EABIs. One reason to do this is that the
14410 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14411 architecture. This code picks MIPS I for 'mips' and MIPS III for
14412 'mips64', just as we did in the days before 'from-abi'. */
14413 if (strcasecmp (cpu_string, "from-abi") == 0)
14415 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14416 return mips_cpu_info_from_isa (ISA_MIPS1);
14418 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14419 return mips_cpu_info_from_isa (ISA_MIPS3);
14421 if (file_mips_gp32 >= 0)
14422 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14424 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14429 /* 'default' has traditionally been a no-op. Probably not very useful. */
14430 if (strcasecmp (cpu_string, "default") == 0)
14433 for (p = mips_cpu_info_table; p->name != 0; p++)
14434 if (mips_matching_cpu_name_p (p->name, cpu_string))
14437 as_bad ("Bad value (%s) for %s", cpu_string, option);
14441 /* Return the canonical processor information for ISA (a member of the
14442 ISA_MIPS* enumeration). */
14444 static const struct mips_cpu_info *
14445 mips_cpu_info_from_isa (int isa)
14449 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14450 if (mips_cpu_info_table[i].is_isa
14451 && isa == mips_cpu_info_table[i].isa)
14452 return (&mips_cpu_info_table[i]);
14457 static const struct mips_cpu_info *
14458 mips_cpu_info_from_arch (int arch)
14462 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14463 if (arch == mips_cpu_info_table[i].cpu)
14464 return (&mips_cpu_info_table[i]);
14470 show (FILE *stream, const char *string, int *col_p, int *first_p)
14474 fprintf (stream, "%24s", "");
14479 fprintf (stream, ", ");
14483 if (*col_p + strlen (string) > 72)
14485 fprintf (stream, "\n%24s", "");
14489 fprintf (stream, "%s", string);
14490 *col_p += strlen (string);
14496 md_show_usage (FILE *stream)
14501 fprintf (stream, _("\
14503 -membedded-pic generate embedded position independent code\n\
14504 -EB generate big endian output\n\
14505 -EL generate little endian output\n\
14506 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14507 -G NUM allow referencing objects up to NUM bytes\n\
14508 implicitly with the gp register [default 8]\n"));
14509 fprintf (stream, _("\
14510 -mips1 generate MIPS ISA I instructions\n\
14511 -mips2 generate MIPS ISA II instructions\n\
14512 -mips3 generate MIPS ISA III instructions\n\
14513 -mips4 generate MIPS ISA IV instructions\n\
14514 -mips5 generate MIPS ISA V instructions\n\
14515 -mips32 generate MIPS32 ISA instructions\n\
14516 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14517 -mips64 generate MIPS64 ISA instructions\n\
14518 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14522 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14523 show (stream, mips_cpu_info_table[i].name, &column, &first);
14524 show (stream, "from-abi", &column, &first);
14525 fputc ('\n', stream);
14527 fprintf (stream, _("\
14528 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14529 -no-mCPU don't generate code specific to CPU.\n\
14530 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14534 show (stream, "3900", &column, &first);
14535 show (stream, "4010", &column, &first);
14536 show (stream, "4100", &column, &first);
14537 show (stream, "4650", &column, &first);
14538 fputc ('\n', stream);
14540 fprintf (stream, _("\
14541 -mips16 generate mips16 instructions\n\
14542 -no-mips16 do not generate mips16 instructions\n"));
14543 fprintf (stream, _("\
14544 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14545 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14546 -O0 remove unneeded NOPs, do not swap branches\n\
14547 -O remove unneeded NOPs and swap branches\n\
14548 -n warn about NOPs generated from macros\n\
14549 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14550 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14551 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14553 fprintf (stream, _("\
14554 -KPIC, -call_shared generate SVR4 position independent code\n\
14555 -non_shared do not generate position independent code\n\
14556 -xgot assume a 32 bit GOT\n\
14557 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14558 -mabi=ABI create ABI conformant object file for:\n"));
14562 show (stream, "32", &column, &first);
14563 show (stream, "o64", &column, &first);
14564 show (stream, "n32", &column, &first);
14565 show (stream, "64", &column, &first);
14566 show (stream, "eabi", &column, &first);
14568 fputc ('\n', stream);
14570 fprintf (stream, _("\
14571 -32 create o32 ABI object file (default)\n\
14572 -n32 create n32 ABI object file\n\
14573 -64 create 64 ABI object file\n"));
14578 mips_dwarf2_format (void)
14580 if (mips_abi == N64_ABI)
14583 return dwarf2_format_64bit_irix;
14585 return dwarf2_format_64bit;
14589 return dwarf2_format_32bit;