1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1138 | ((e2) ? 0x100 : 0) \
1139 | ((pic) ? 0x200 : 0) \
1140 | ((sym32) ? 0x400 : 0) \
1141 | ((nomacro) ? 0x800 : 0) \
1142 | ((small) ? 0x1000 : 0) \
1143 | ((ext) ? 0x2000 : 0) \
1144 | ((dslot) ? 0x4000 : 0) \
1145 | ((jal_dslot) ? 0x8000 : 0))
1147 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1148 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1149 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1150 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1151 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1152 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1153 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1154 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1155 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1156 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1158 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1159 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1160 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1161 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1162 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1163 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1164 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1165 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1166 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1168 /* For microMIPS code, we use relaxation similar to one we use for
1169 MIPS16 code. Some instructions that take immediate values support
1170 two encodings: a small one which takes some small value, and a
1171 larger one which takes a 16 bit value. As some branches also follow
1172 this pattern, relaxing these values is required.
1174 We can assemble both microMIPS and normal MIPS code in a single
1175 object. Therefore, we need to support this type of relaxation at
1176 the same time that we support the relaxation described above. We
1177 use one of the high bits of the subtype field to distinguish these
1180 The information we store for this type of relaxation is the argument
1181 code found in the opcode file for this relocation, the register
1182 selected as the assembler temporary, whether in the 32-bit
1183 instruction mode, whether the branch is unconditional, whether it is
1184 compact, whether there is no delay-slot instruction available to fill
1185 in, whether it stores the link address implicitly in $ra, whether
1186 relaxation of out-of-range 32-bit branches to a sequence of
1187 instructions is enabled, and whether the displacement of a branch is
1188 too large to fit as an immediate argument of a 16-bit and a 32-bit
1189 branch, respectively. */
1190 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1191 uncond, compact, link, nods, \
1192 relax32, toofar16, toofar32) \
1195 | (((at) & 0x1f) << 8) \
1196 | ((insn32) ? 0x2000 : 0) \
1197 | ((pic) ? 0x4000 : 0) \
1198 | ((uncond) ? 0x8000 : 0) \
1199 | ((compact) ? 0x10000 : 0) \
1200 | ((link) ? 0x20000 : 0) \
1201 | ((nods) ? 0x40000 : 0) \
1202 | ((relax32) ? 0x80000 : 0) \
1203 | ((toofar16) ? 0x100000 : 0) \
1204 | ((toofar32) ? 0x200000 : 0))
1205 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1206 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1207 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1208 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1209 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1210 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1211 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1212 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1213 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1214 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1216 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1217 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1218 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1219 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1220 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1221 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1223 /* Sign-extend 16-bit value X. */
1224 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1226 /* Is the given value a sign-extended 32-bit value? */
1227 #define IS_SEXT_32BIT_NUM(x) \
1228 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1229 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1231 /* Is the given value a sign-extended 16-bit value? */
1232 #define IS_SEXT_16BIT_NUM(x) \
1233 (((x) &~ (offsetT) 0x7fff) == 0 \
1234 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1236 /* Is the given value a sign-extended 12-bit value? */
1237 #define IS_SEXT_12BIT_NUM(x) \
1238 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1240 /* Is the given value a sign-extended 9-bit value? */
1241 #define IS_SEXT_9BIT_NUM(x) \
1242 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1244 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1245 #define IS_ZEXT_32BIT_NUM(x) \
1246 (((x) &~ (offsetT) 0xffffffff) == 0 \
1247 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1249 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1251 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1252 (((STRUCT) >> (SHIFT)) & (MASK))
1254 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1255 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1257 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1258 : EXTRACT_BITS ((INSN).insn_opcode, \
1259 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1260 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1261 EXTRACT_BITS ((INSN).insn_opcode, \
1262 MIPS16OP_MASK_##FIELD, \
1263 MIPS16OP_SH_##FIELD)
1265 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1266 #define MIPS16_EXTEND (0xf000U << 16)
1268 /* Whether or not we are emitting a branch-likely macro. */
1269 static bfd_boolean emit_branch_likely_macro = FALSE;
1271 /* Global variables used when generating relaxable macros. See the
1272 comment above RELAX_ENCODE for more details about how relaxation
1275 /* 0 if we're not emitting a relaxable macro.
1276 1 if we're emitting the first of the two relaxation alternatives.
1277 2 if we're emitting the second alternative. */
1280 /* The first relaxable fixup in the current frag. (In other words,
1281 the first fixup that refers to relaxable code.) */
1284 /* sizes[0] says how many bytes of the first alternative are stored in
1285 the current frag. Likewise sizes[1] for the second alternative. */
1286 unsigned int sizes[2];
1288 /* The symbol on which the choice of sequence depends. */
1292 /* Global variables used to decide whether a macro needs a warning. */
1294 /* True if the macro is in a branch delay slot. */
1295 bfd_boolean delay_slot_p;
1297 /* Set to the length in bytes required if the macro is in a delay slot
1298 that requires a specific length of instruction, otherwise zero. */
1299 unsigned int delay_slot_length;
1301 /* For relaxable macros, sizes[0] is the length of the first alternative
1302 in bytes and sizes[1] is the length of the second alternative.
1303 For non-relaxable macros, both elements give the length of the
1305 unsigned int sizes[2];
1307 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1308 instruction of the first alternative in bytes and first_insn_sizes[1]
1309 is the length of the first instruction of the second alternative.
1310 For non-relaxable macros, both elements give the length of the first
1311 instruction in bytes.
1313 Set to zero if we haven't yet seen the first instruction. */
1314 unsigned int first_insn_sizes[2];
1316 /* For relaxable macros, insns[0] is the number of instructions for the
1317 first alternative and insns[1] is the number of instructions for the
1320 For non-relaxable macros, both elements give the number of
1321 instructions for the macro. */
1322 unsigned int insns[2];
1324 /* The first variant frag for this macro. */
1326 } mips_macro_warning;
1328 /* Prototypes for static functions. */
1330 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1332 static void append_insn
1333 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1334 bfd_boolean expansionp);
1335 static void mips_no_prev_insn (void);
1336 static void macro_build (expressionS *, const char *, const char *, ...);
1337 static void mips16_macro_build
1338 (expressionS *, const char *, const char *, va_list *);
1339 static void load_register (int, expressionS *, int);
1340 static void macro_start (void);
1341 static void macro_end (void);
1342 static void macro (struct mips_cl_insn *ip, char *str);
1343 static void mips16_macro (struct mips_cl_insn * ip);
1344 static void mips_ip (char *str, struct mips_cl_insn * ip);
1345 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1346 static unsigned long mips16_immed_extend (offsetT, unsigned int);
1347 static void mips16_immed
1348 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS *, bfd_reloc_code_real_type *, char *);
1352 static void my_getExpression (expressionS *, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void s_nan (int);
1378 static void s_module (int);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean pic_need_relax (symbolS *);
1388 static int relaxed_branch_length (fragS *, asection *, int);
1389 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1390 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1391 static void file_mips_check_options (void);
1393 /* Table and functions used to map between CPU/ISA names, and
1394 ISA levels, and CPU numbers. */
1396 struct mips_cpu_info
1398 const char *name; /* CPU or ISA name. */
1399 int flags; /* MIPS_CPU_* flags. */
1400 int ase; /* Set of ASEs implemented by the CPU. */
1401 int isa; /* ISA level. */
1402 int cpu; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1407 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1408 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1409 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1411 /* Command-line options. */
1412 const char *md_shortopts = "O::g::G:";
1416 OPTION_MARCH = OPTION_MD_BASE,
1448 OPTION_NO_SMARTMIPS,
1458 OPTION_NO_MICROMIPS,
1463 OPTION_COMPAT_ARCH_BASE,
1472 OPTION_M7000_HILO_FIX,
1473 OPTION_MNO_7000_HILO_FIX,
1477 OPTION_NO_FIX_RM7000,
1478 OPTION_FIX_LOONGSON2F_JUMP,
1479 OPTION_NO_FIX_LOONGSON2F_JUMP,
1480 OPTION_FIX_LOONGSON2F_NOP,
1481 OPTION_NO_FIX_LOONGSON2F_NOP,
1483 OPTION_NO_FIX_VR4120,
1485 OPTION_NO_FIX_VR4130,
1486 OPTION_FIX_CN63XXP1,
1487 OPTION_NO_FIX_CN63XXP1,
1494 OPTION_CONSTRUCT_FLOATS,
1495 OPTION_NO_CONSTRUCT_FLOATS,
1499 OPTION_RELAX_BRANCH,
1500 OPTION_NO_RELAX_BRANCH,
1501 OPTION_IGNORE_BRANCH_ISA,
1502 OPTION_NO_IGNORE_BRANCH_ISA,
1511 OPTION_SINGLE_FLOAT,
1512 OPTION_DOUBLE_FLOAT,
1525 OPTION_MVXWORKS_PIC,
1528 OPTION_NO_ODD_SPREG,
1532 struct option md_longopts[] =
1534 /* Options which specify architecture. */
1535 {"march", required_argument, NULL, OPTION_MARCH},
1536 {"mtune", required_argument, NULL, OPTION_MTUNE},
1537 {"mips0", no_argument, NULL, OPTION_MIPS1},
1538 {"mips1", no_argument, NULL, OPTION_MIPS1},
1539 {"mips2", no_argument, NULL, OPTION_MIPS2},
1540 {"mips3", no_argument, NULL, OPTION_MIPS3},
1541 {"mips4", no_argument, NULL, OPTION_MIPS4},
1542 {"mips5", no_argument, NULL, OPTION_MIPS5},
1543 {"mips32", no_argument, NULL, OPTION_MIPS32},
1544 {"mips64", no_argument, NULL, OPTION_MIPS64},
1545 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1546 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1547 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1548 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1549 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1550 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1551 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1552 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1554 /* Options which specify Application Specific Extensions (ASEs). */
1555 {"mips16", no_argument, NULL, OPTION_MIPS16},
1556 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1557 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1558 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1559 {"mdmx", no_argument, NULL, OPTION_MDMX},
1560 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1561 {"mdsp", no_argument, NULL, OPTION_DSP},
1562 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1563 {"mmt", no_argument, NULL, OPTION_MT},
1564 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1565 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1566 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1567 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1568 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1569 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1570 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1571 {"meva", no_argument, NULL, OPTION_EVA},
1572 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1573 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1574 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1575 {"mmcu", no_argument, NULL, OPTION_MCU},
1576 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1577 {"mvirt", no_argument, NULL, OPTION_VIRT},
1578 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1579 {"mmsa", no_argument, NULL, OPTION_MSA},
1580 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1581 {"mxpa", no_argument, NULL, OPTION_XPA},
1582 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1583 {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2},
1584 {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
1586 /* Old-style architecture options. Don't add more of these. */
1587 {"m4650", no_argument, NULL, OPTION_M4650},
1588 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1589 {"m4010", no_argument, NULL, OPTION_M4010},
1590 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1591 {"m4100", no_argument, NULL, OPTION_M4100},
1592 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1593 {"m3900", no_argument, NULL, OPTION_M3900},
1594 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1596 /* Options which enable bug fixes. */
1597 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1598 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1599 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1600 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1601 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1602 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1603 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1604 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1605 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1606 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1607 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1608 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1609 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1610 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1611 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1612 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1613 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1615 /* Miscellaneous options. */
1616 {"trap", no_argument, NULL, OPTION_TRAP},
1617 {"no-break", no_argument, NULL, OPTION_TRAP},
1618 {"break", no_argument, NULL, OPTION_BREAK},
1619 {"no-trap", no_argument, NULL, OPTION_BREAK},
1620 {"EB", no_argument, NULL, OPTION_EB},
1621 {"EL", no_argument, NULL, OPTION_EL},
1622 {"mfp32", no_argument, NULL, OPTION_FP32},
1623 {"mgp32", no_argument, NULL, OPTION_GP32},
1624 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1625 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1626 {"mfp64", no_argument, NULL, OPTION_FP64},
1627 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1628 {"mgp64", no_argument, NULL, OPTION_GP64},
1629 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1630 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1631 {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA},
1632 {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA},
1633 {"minsn32", no_argument, NULL, OPTION_INSN32},
1634 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1635 {"mshared", no_argument, NULL, OPTION_MSHARED},
1636 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1637 {"msym32", no_argument, NULL, OPTION_MSYM32},
1638 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1639 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1640 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1641 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1642 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1643 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1644 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1646 /* Strictly speaking this next option is ELF specific,
1647 but we allow it for other ports as well in order to
1648 make testing easier. */
1649 {"32", no_argument, NULL, OPTION_32},
1651 /* ELF-specific options. */
1652 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1653 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1654 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1655 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1656 {"xgot", no_argument, NULL, OPTION_XGOT},
1657 {"mabi", required_argument, NULL, OPTION_MABI},
1658 {"n32", no_argument, NULL, OPTION_N32},
1659 {"64", no_argument, NULL, OPTION_64},
1660 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1661 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1662 {"mpdr", no_argument, NULL, OPTION_PDR},
1663 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1664 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1665 {"mnan", required_argument, NULL, OPTION_NAN},
1667 {NULL, no_argument, NULL, 0}
1669 size_t md_longopts_size = sizeof (md_longopts);
1671 /* Information about either an Application Specific Extension or an
1672 optional architecture feature that, for simplicity, we treat in the
1673 same way as an ASE. */
1676 /* The name of the ASE, used in both the command-line and .set options. */
1679 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1680 and 64-bit architectures, the flags here refer to the subset that
1681 is available on both. */
1684 /* The ASE_* flag used for instructions that are available on 64-bit
1685 architectures but that are not included in FLAGS. */
1686 unsigned int flags64;
1688 /* The command-line options that turn the ASE on and off. */
1692 /* The minimum required architecture revisions for MIPS32, MIPS64,
1693 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1696 int micromips32_rev;
1697 int micromips64_rev;
1699 /* The architecture where the ASE was removed or -1 if the extension has not
1704 /* A table of all supported ASEs. */
1705 static const struct mips_ase mips_ases[] = {
1706 { "dsp", ASE_DSP, ASE_DSP64,
1707 OPTION_DSP, OPTION_NO_DSP,
1711 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1712 OPTION_DSPR2, OPTION_NO_DSPR2,
1716 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1717 OPTION_DSPR3, OPTION_NO_DSPR3,
1721 { "eva", ASE_EVA, 0,
1722 OPTION_EVA, OPTION_NO_EVA,
1726 { "mcu", ASE_MCU, 0,
1727 OPTION_MCU, OPTION_NO_MCU,
1731 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1732 { "mdmx", ASE_MDMX, 0,
1733 OPTION_MDMX, OPTION_NO_MDMX,
1737 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1738 { "mips3d", ASE_MIPS3D, 0,
1739 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1744 OPTION_MT, OPTION_NO_MT,
1748 { "smartmips", ASE_SMARTMIPS, 0,
1749 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1753 { "virt", ASE_VIRT, ASE_VIRT64,
1754 OPTION_VIRT, OPTION_NO_VIRT,
1758 { "msa", ASE_MSA, ASE_MSA64,
1759 OPTION_MSA, OPTION_NO_MSA,
1763 { "xpa", ASE_XPA, 0,
1764 OPTION_XPA, OPTION_NO_XPA,
1768 { "mips16e2", ASE_MIPS16E2, 0,
1769 OPTION_MIPS16E2, OPTION_NO_MIPS16E2,
1774 /* The set of ASEs that require -mfp64. */
1775 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1777 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1778 static const unsigned int mips_ase_groups[] = {
1779 ASE_DSP | ASE_DSPR2 | ASE_DSPR3
1784 The following pseudo-ops from the Kane and Heinrich MIPS book
1785 should be defined here, but are currently unsupported: .alias,
1786 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1788 The following pseudo-ops from the Kane and Heinrich MIPS book are
1789 specific to the type of debugging information being generated, and
1790 should be defined by the object format: .aent, .begin, .bend,
1791 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1794 The following pseudo-ops from the Kane and Heinrich MIPS book are
1795 not MIPS CPU specific, but are also not specific to the object file
1796 format. This file is probably the best place to define them, but
1797 they are not currently supported: .asm0, .endr, .lab, .struct. */
1799 static const pseudo_typeS mips_pseudo_table[] =
1801 /* MIPS specific pseudo-ops. */
1802 {"option", s_option, 0},
1803 {"set", s_mipsset, 0},
1804 {"rdata", s_change_sec, 'r'},
1805 {"sdata", s_change_sec, 's'},
1806 {"livereg", s_ignore, 0},
1807 {"abicalls", s_abicalls, 0},
1808 {"cpload", s_cpload, 0},
1809 {"cpsetup", s_cpsetup, 0},
1810 {"cplocal", s_cplocal, 0},
1811 {"cprestore", s_cprestore, 0},
1812 {"cpreturn", s_cpreturn, 0},
1813 {"dtprelword", s_dtprelword, 0},
1814 {"dtpreldword", s_dtpreldword, 0},
1815 {"tprelword", s_tprelword, 0},
1816 {"tpreldword", s_tpreldword, 0},
1817 {"gpvalue", s_gpvalue, 0},
1818 {"gpword", s_gpword, 0},
1819 {"gpdword", s_gpdword, 0},
1820 {"ehword", s_ehword, 0},
1821 {"cpadd", s_cpadd, 0},
1822 {"insn", s_insn, 0},
1824 {"module", s_module, 0},
1826 /* Relatively generic pseudo-ops that happen to be used on MIPS
1828 {"asciiz", stringer, 8 + 1},
1829 {"bss", s_change_sec, 'b'},
1831 {"half", s_cons, 1},
1832 {"dword", s_cons, 3},
1833 {"weakext", s_mips_weakext, 0},
1834 {"origin", s_org, 0},
1835 {"repeat", s_rept, 0},
1837 /* For MIPS this is non-standard, but we define it for consistency. */
1838 {"sbss", s_change_sec, 'B'},
1840 /* These pseudo-ops are defined in read.c, but must be overridden
1841 here for one reason or another. */
1842 {"align", s_align, 0},
1843 {"byte", s_cons, 0},
1844 {"data", s_change_sec, 'd'},
1845 {"double", s_float_cons, 'd'},
1846 {"float", s_float_cons, 'f'},
1847 {"globl", s_mips_globl, 0},
1848 {"global", s_mips_globl, 0},
1849 {"hword", s_cons, 1},
1851 {"long", s_cons, 2},
1852 {"octa", s_cons, 4},
1853 {"quad", s_cons, 3},
1854 {"section", s_change_section, 0},
1855 {"short", s_cons, 1},
1856 {"single", s_float_cons, 'f'},
1857 {"stabd", s_mips_stab, 'd'},
1858 {"stabn", s_mips_stab, 'n'},
1859 {"stabs", s_mips_stab, 's'},
1860 {"text", s_change_sec, 't'},
1861 {"word", s_cons, 2},
1863 { "extern", ecoff_directive_extern, 0},
1868 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1870 /* These pseudo-ops should be defined by the object file format.
1871 However, a.out doesn't support them, so we have versions here. */
1872 {"aent", s_mips_ent, 1},
1873 {"bgnb", s_ignore, 0},
1874 {"end", s_mips_end, 0},
1875 {"endb", s_ignore, 0},
1876 {"ent", s_mips_ent, 0},
1877 {"file", s_mips_file, 0},
1878 {"fmask", s_mips_mask, 'F'},
1879 {"frame", s_mips_frame, 0},
1880 {"loc", s_mips_loc, 0},
1881 {"mask", s_mips_mask, 'R'},
1882 {"verstamp", s_ignore, 0},
1886 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1887 purpose of the `.dc.a' internal pseudo-op. */
1890 mips_address_bytes (void)
1892 file_mips_check_options ();
1893 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1896 extern void pop_insert (const pseudo_typeS *);
1899 mips_pop_insert (void)
1901 pop_insert (mips_pseudo_table);
1902 if (! ECOFF_DEBUGGING)
1903 pop_insert (mips_nonecoff_pseudo_table);
1906 /* Symbols labelling the current insn. */
1908 struct insn_label_list
1910 struct insn_label_list *next;
1914 static struct insn_label_list *free_insn_labels;
1915 #define label_list tc_segment_info_data.labels
1917 static void mips_clear_insn_labels (void);
1918 static void mips_mark_labels (void);
1919 static void mips_compressed_mark_labels (void);
1922 mips_clear_insn_labels (void)
1924 struct insn_label_list **pl;
1925 segment_info_type *si;
1929 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1932 si = seg_info (now_seg);
1933 *pl = si->label_list;
1934 si->label_list = NULL;
1938 /* Mark instruction labels in MIPS16/microMIPS mode. */
1941 mips_mark_labels (void)
1943 if (HAVE_CODE_COMPRESSION)
1944 mips_compressed_mark_labels ();
1947 static char *expr_end;
1949 /* An expression in a macro instruction. This is set by mips_ip and
1950 mips16_ip and when populated is always an O_constant. */
1952 static expressionS imm_expr;
1954 /* The relocatable field in an instruction and the relocs associated
1955 with it. These variables are used for instructions like LUI and
1956 JAL as well as true offsets. They are also used for address
1957 operands in macros. */
1959 static expressionS offset_expr;
1960 static bfd_reloc_code_real_type offset_reloc[3]
1961 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1963 /* This is set to the resulting size of the instruction to be produced
1964 by mips16_ip if an explicit extension is used or by mips_ip if an
1965 explicit size is supplied. */
1967 static unsigned int forced_insn_length;
1969 /* True if we are assembling an instruction. All dot symbols defined during
1970 this time should be treated as code labels. */
1972 static bfd_boolean mips_assembling_insn;
1974 /* The pdr segment for per procedure frame/regmask info. Not used for
1977 static segT pdr_seg;
1979 /* The default target format to use. */
1981 #if defined (TE_FreeBSD)
1982 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1983 #elif defined (TE_TMIPS)
1984 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1986 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1990 mips_target_format (void)
1992 switch (OUTPUT_FLAVOR)
1994 case bfd_target_elf_flavour:
1996 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1997 return (target_big_endian
1998 ? "elf32-bigmips-vxworks"
1999 : "elf32-littlemips-vxworks");
2001 return (target_big_endian
2002 ? (HAVE_64BIT_OBJECTS
2003 ? ELF_TARGET ("elf64-", "big")
2005 ? ELF_TARGET ("elf32-n", "big")
2006 : ELF_TARGET ("elf32-", "big")))
2007 : (HAVE_64BIT_OBJECTS
2008 ? ELF_TARGET ("elf64-", "little")
2010 ? ELF_TARGET ("elf32-n", "little")
2011 : ELF_TARGET ("elf32-", "little"))));
2018 /* Return the ISA revision that is currently in use, or 0 if we are
2019 generating code for MIPS V or below. */
2024 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
2027 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
2030 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
2033 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
2036 /* microMIPS implies revision 2 or above. */
2037 if (mips_opts.micromips)
2040 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
2046 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2049 mips_ase_mask (unsigned int flags)
2053 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2054 if (flags & mips_ase_groups[i])
2055 flags |= mips_ase_groups[i];
2059 /* Check whether the current ISA supports ASE. Issue a warning if
2063 mips_check_isa_supports_ase (const struct mips_ase *ase)
2067 static unsigned int warned_isa;
2068 static unsigned int warned_fp32;
2070 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2071 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2073 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2074 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2075 && (warned_isa & ase->flags) != ase->flags)
2077 warned_isa |= ase->flags;
2078 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2079 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2081 as_warn (_("the %d-bit %s architecture does not support the"
2082 " `%s' extension"), size, base, ase->name);
2084 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2085 ase->name, base, size, min_rev);
2087 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2088 && (warned_isa & ase->flags) != ase->flags)
2090 warned_isa |= ase->flags;
2091 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2092 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2093 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2094 ase->name, base, size, ase->rem_rev);
2097 if ((ase->flags & FP64_ASES)
2098 && mips_opts.fp != 64
2099 && (warned_fp32 & ase->flags) != ase->flags)
2101 warned_fp32 |= ase->flags;
2102 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2106 /* Check all enabled ASEs to see whether they are supported by the
2107 chosen architecture. */
2110 mips_check_isa_supports_ases (void)
2112 unsigned int i, mask;
2114 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2116 mask = mips_ase_mask (mips_ases[i].flags);
2117 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2118 mips_check_isa_supports_ase (&mips_ases[i]);
2122 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2123 that were affected. */
2126 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2127 bfd_boolean enabled_p)
2131 mask = mips_ase_mask (ase->flags);
2134 /* Clear combination ASE flags, which need to be recalculated based on
2135 updated regular ASE settings. */
2136 opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT);
2139 opts->ase |= ase->flags;
2141 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2142 instructions which are only valid when both ASEs are enabled.
2143 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2144 if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT))
2146 opts->ase |= ASE_XPA_VIRT;
2147 mask |= ASE_XPA_VIRT;
2149 if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
2151 opts->ase |= ASE_MIPS16E2_MT;
2152 mask |= ASE_MIPS16E2_MT;
2158 /* Return the ASE called NAME, or null if none. */
2160 static const struct mips_ase *
2161 mips_lookup_ase (const char *name)
2165 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2166 if (strcmp (name, mips_ases[i].name) == 0)
2167 return &mips_ases[i];
2171 /* Return the length of a microMIPS instruction in bytes. If bits of
2172 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2173 otherwise it is a 32-bit instruction. */
2175 static inline unsigned int
2176 micromips_insn_length (const struct mips_opcode *mo)
2178 return mips_opcode_32bit_p (mo) ? 4 : 2;
2181 /* Return the length of MIPS16 instruction OPCODE. */
2183 static inline unsigned int
2184 mips16_opcode_length (unsigned long opcode)
2186 return (opcode >> 16) == 0 ? 2 : 4;
2189 /* Return the length of instruction INSN. */
2191 static inline unsigned int
2192 insn_length (const struct mips_cl_insn *insn)
2194 if (mips_opts.micromips)
2195 return micromips_insn_length (insn->insn_mo);
2196 else if (mips_opts.mips16)
2197 return mips16_opcode_length (insn->insn_opcode);
2202 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2205 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2210 insn->insn_opcode = mo->match;
2213 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2214 insn->fixp[i] = NULL;
2215 insn->fixed_p = (mips_opts.noreorder > 0);
2216 insn->noreorder_p = (mips_opts.noreorder > 0);
2217 insn->mips16_absolute_jump_p = 0;
2218 insn->complete_p = 0;
2219 insn->cleared_p = 0;
2222 /* Get a list of all the operands in INSN. */
2224 static const struct mips_operand_array *
2225 insn_operands (const struct mips_cl_insn *insn)
2227 if (insn->insn_mo >= &mips_opcodes[0]
2228 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2229 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2231 if (insn->insn_mo >= &mips16_opcodes[0]
2232 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2233 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2235 if (insn->insn_mo >= µmips_opcodes[0]
2236 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2237 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2242 /* Get a description of operand OPNO of INSN. */
2244 static const struct mips_operand *
2245 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2247 const struct mips_operand_array *operands;
2249 operands = insn_operands (insn);
2250 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2252 return operands->operand[opno];
2255 /* Install UVAL as the value of OPERAND in INSN. */
2258 insn_insert_operand (struct mips_cl_insn *insn,
2259 const struct mips_operand *operand, unsigned int uval)
2261 if (mips_opts.mips16
2262 && operand->type == OP_INT && operand->lsb == 0
2263 && mips_opcode_32bit_p (insn->insn_mo))
2264 insn->insn_opcode |= mips16_immed_extend (uval, operand->size);
2266 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2269 /* Extract the value of OPERAND from INSN. */
2271 static inline unsigned
2272 insn_extract_operand (const struct mips_cl_insn *insn,
2273 const struct mips_operand *operand)
2275 return mips_extract_operand (operand, insn->insn_opcode);
2278 /* Record the current MIPS16/microMIPS mode in now_seg. */
2281 mips_record_compressed_mode (void)
2283 segment_info_type *si;
2285 si = seg_info (now_seg);
2286 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2287 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2288 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2289 si->tc_segment_info_data.micromips = mips_opts.micromips;
2292 /* Read a standard MIPS instruction from BUF. */
2294 static unsigned long
2295 read_insn (char *buf)
2297 if (target_big_endian)
2298 return bfd_getb32 ((bfd_byte *) buf);
2300 return bfd_getl32 ((bfd_byte *) buf);
2303 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2307 write_insn (char *buf, unsigned int insn)
2309 md_number_to_chars (buf, insn, 4);
2313 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2314 has length LENGTH. */
2316 static unsigned long
2317 read_compressed_insn (char *buf, unsigned int length)
2323 for (i = 0; i < length; i += 2)
2326 if (target_big_endian)
2327 insn |= bfd_getb16 ((char *) buf);
2329 insn |= bfd_getl16 ((char *) buf);
2335 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2336 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2339 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2343 for (i = 0; i < length; i += 2)
2344 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2345 return buf + length;
2348 /* Install INSN at the location specified by its "frag" and "where" fields. */
2351 install_insn (const struct mips_cl_insn *insn)
2353 char *f = insn->frag->fr_literal + insn->where;
2354 if (HAVE_CODE_COMPRESSION)
2355 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2357 write_insn (f, insn->insn_opcode);
2358 mips_record_compressed_mode ();
2361 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2362 and install the opcode in the new location. */
2365 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2370 insn->where = where;
2371 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2372 if (insn->fixp[i] != NULL)
2374 insn->fixp[i]->fx_frag = frag;
2375 insn->fixp[i]->fx_where = where;
2377 install_insn (insn);
2380 /* Add INSN to the end of the output. */
2383 add_fixed_insn (struct mips_cl_insn *insn)
2385 char *f = frag_more (insn_length (insn));
2386 move_insn (insn, frag_now, f - frag_now->fr_literal);
2389 /* Start a variant frag and move INSN to the start of the variant part,
2390 marking it as fixed. The other arguments are as for frag_var. */
2393 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2394 relax_substateT subtype, symbolS *symbol, offsetT offset)
2396 frag_grow (max_chars);
2397 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2399 frag_var (rs_machine_dependent, max_chars, var,
2400 subtype, symbol, offset, NULL);
2403 /* Insert N copies of INSN into the history buffer, starting at
2404 position FIRST. Neither FIRST nor N need to be clipped. */
2407 insert_into_history (unsigned int first, unsigned int n,
2408 const struct mips_cl_insn *insn)
2410 if (mips_relax.sequence != 2)
2414 for (i = ARRAY_SIZE (history); i-- > first;)
2416 history[i] = history[i - n];
2422 /* Clear the error in insn_error. */
2425 clear_insn_error (void)
2427 memset (&insn_error, 0, sizeof (insn_error));
2430 /* Possibly record error message MSG for the current instruction.
2431 If the error is about a particular argument, ARGNUM is the 1-based
2432 number of that argument, otherwise it is 0. FORMAT is the format
2433 of MSG. Return true if MSG was used, false if the current message
2437 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2442 /* Give priority to errors against specific arguments, and to
2443 the first whole-instruction message. */
2449 /* Keep insn_error if it is against a later argument. */
2450 if (argnum < insn_error.min_argnum)
2453 /* If both errors are against the same argument but are different,
2454 give up on reporting a specific error for this argument.
2455 See the comment about mips_insn_error for details. */
2456 if (argnum == insn_error.min_argnum
2458 && strcmp (insn_error.msg, msg) != 0)
2461 insn_error.min_argnum += 1;
2465 insn_error.min_argnum = argnum;
2466 insn_error.format = format;
2467 insn_error.msg = msg;
2471 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2472 as for set_insn_error_format. */
2475 set_insn_error (int argnum, const char *msg)
2477 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2480 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2481 as for set_insn_error_format. */
2484 set_insn_error_i (int argnum, const char *msg, int i)
2486 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2490 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2491 are as for set_insn_error_format. */
2494 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2496 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2498 insn_error.u.ss[0] = s1;
2499 insn_error.u.ss[1] = s2;
2503 /* Report the error in insn_error, which is against assembly code STR. */
2506 report_insn_error (const char *str)
2508 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2510 switch (insn_error.format)
2517 as_bad (msg, insn_error.u.i, str);
2521 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2525 free ((char *) msg);
2528 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2529 the idea is to make it obvious at a glance that each errata is
2533 init_vr4120_conflicts (void)
2535 #define CONFLICT(FIRST, SECOND) \
2536 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2538 /* Errata 21 - [D]DIV[U] after [D]MACC */
2539 CONFLICT (MACC, DIV);
2540 CONFLICT (DMACC, DIV);
2542 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2543 CONFLICT (DMULT, DMULT);
2544 CONFLICT (DMULT, DMACC);
2545 CONFLICT (DMACC, DMULT);
2546 CONFLICT (DMACC, DMACC);
2548 /* Errata 24 - MT{LO,HI} after [D]MACC */
2549 CONFLICT (MACC, MTHILO);
2550 CONFLICT (DMACC, MTHILO);
2552 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2553 instruction is executed immediately after a MACC or DMACC
2554 instruction, the result of [either instruction] is incorrect." */
2555 CONFLICT (MACC, MULT);
2556 CONFLICT (MACC, DMULT);
2557 CONFLICT (DMACC, MULT);
2558 CONFLICT (DMACC, DMULT);
2560 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2561 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2562 DDIV or DDIVU instruction, the result of the MACC or
2563 DMACC instruction is incorrect.". */
2564 CONFLICT (DMULT, MACC);
2565 CONFLICT (DMULT, DMACC);
2566 CONFLICT (DIV, MACC);
2567 CONFLICT (DIV, DMACC);
2577 #define RNUM_MASK 0x00000ff
2578 #define RTYPE_MASK 0x0ffff00
2579 #define RTYPE_NUM 0x0000100
2580 #define RTYPE_FPU 0x0000200
2581 #define RTYPE_FCC 0x0000400
2582 #define RTYPE_VEC 0x0000800
2583 #define RTYPE_GP 0x0001000
2584 #define RTYPE_CP0 0x0002000
2585 #define RTYPE_PC 0x0004000
2586 #define RTYPE_ACC 0x0008000
2587 #define RTYPE_CCC 0x0010000
2588 #define RTYPE_VI 0x0020000
2589 #define RTYPE_VF 0x0040000
2590 #define RTYPE_R5900_I 0x0080000
2591 #define RTYPE_R5900_Q 0x0100000
2592 #define RTYPE_R5900_R 0x0200000
2593 #define RTYPE_R5900_ACC 0x0400000
2594 #define RTYPE_MSA 0x0800000
2595 #define RWARN 0x8000000
2597 #define GENERIC_REGISTER_NUMBERS \
2598 {"$0", RTYPE_NUM | 0}, \
2599 {"$1", RTYPE_NUM | 1}, \
2600 {"$2", RTYPE_NUM | 2}, \
2601 {"$3", RTYPE_NUM | 3}, \
2602 {"$4", RTYPE_NUM | 4}, \
2603 {"$5", RTYPE_NUM | 5}, \
2604 {"$6", RTYPE_NUM | 6}, \
2605 {"$7", RTYPE_NUM | 7}, \
2606 {"$8", RTYPE_NUM | 8}, \
2607 {"$9", RTYPE_NUM | 9}, \
2608 {"$10", RTYPE_NUM | 10}, \
2609 {"$11", RTYPE_NUM | 11}, \
2610 {"$12", RTYPE_NUM | 12}, \
2611 {"$13", RTYPE_NUM | 13}, \
2612 {"$14", RTYPE_NUM | 14}, \
2613 {"$15", RTYPE_NUM | 15}, \
2614 {"$16", RTYPE_NUM | 16}, \
2615 {"$17", RTYPE_NUM | 17}, \
2616 {"$18", RTYPE_NUM | 18}, \
2617 {"$19", RTYPE_NUM | 19}, \
2618 {"$20", RTYPE_NUM | 20}, \
2619 {"$21", RTYPE_NUM | 21}, \
2620 {"$22", RTYPE_NUM | 22}, \
2621 {"$23", RTYPE_NUM | 23}, \
2622 {"$24", RTYPE_NUM | 24}, \
2623 {"$25", RTYPE_NUM | 25}, \
2624 {"$26", RTYPE_NUM | 26}, \
2625 {"$27", RTYPE_NUM | 27}, \
2626 {"$28", RTYPE_NUM | 28}, \
2627 {"$29", RTYPE_NUM | 29}, \
2628 {"$30", RTYPE_NUM | 30}, \
2629 {"$31", RTYPE_NUM | 31}
2631 #define FPU_REGISTER_NAMES \
2632 {"$f0", RTYPE_FPU | 0}, \
2633 {"$f1", RTYPE_FPU | 1}, \
2634 {"$f2", RTYPE_FPU | 2}, \
2635 {"$f3", RTYPE_FPU | 3}, \
2636 {"$f4", RTYPE_FPU | 4}, \
2637 {"$f5", RTYPE_FPU | 5}, \
2638 {"$f6", RTYPE_FPU | 6}, \
2639 {"$f7", RTYPE_FPU | 7}, \
2640 {"$f8", RTYPE_FPU | 8}, \
2641 {"$f9", RTYPE_FPU | 9}, \
2642 {"$f10", RTYPE_FPU | 10}, \
2643 {"$f11", RTYPE_FPU | 11}, \
2644 {"$f12", RTYPE_FPU | 12}, \
2645 {"$f13", RTYPE_FPU | 13}, \
2646 {"$f14", RTYPE_FPU | 14}, \
2647 {"$f15", RTYPE_FPU | 15}, \
2648 {"$f16", RTYPE_FPU | 16}, \
2649 {"$f17", RTYPE_FPU | 17}, \
2650 {"$f18", RTYPE_FPU | 18}, \
2651 {"$f19", RTYPE_FPU | 19}, \
2652 {"$f20", RTYPE_FPU | 20}, \
2653 {"$f21", RTYPE_FPU | 21}, \
2654 {"$f22", RTYPE_FPU | 22}, \
2655 {"$f23", RTYPE_FPU | 23}, \
2656 {"$f24", RTYPE_FPU | 24}, \
2657 {"$f25", RTYPE_FPU | 25}, \
2658 {"$f26", RTYPE_FPU | 26}, \
2659 {"$f27", RTYPE_FPU | 27}, \
2660 {"$f28", RTYPE_FPU | 28}, \
2661 {"$f29", RTYPE_FPU | 29}, \
2662 {"$f30", RTYPE_FPU | 30}, \
2663 {"$f31", RTYPE_FPU | 31}
2665 #define FPU_CONDITION_CODE_NAMES \
2666 {"$fcc0", RTYPE_FCC | 0}, \
2667 {"$fcc1", RTYPE_FCC | 1}, \
2668 {"$fcc2", RTYPE_FCC | 2}, \
2669 {"$fcc3", RTYPE_FCC | 3}, \
2670 {"$fcc4", RTYPE_FCC | 4}, \
2671 {"$fcc5", RTYPE_FCC | 5}, \
2672 {"$fcc6", RTYPE_FCC | 6}, \
2673 {"$fcc7", RTYPE_FCC | 7}
2675 #define COPROC_CONDITION_CODE_NAMES \
2676 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2677 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2678 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2679 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2680 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2681 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2682 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2683 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2685 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2686 {"$a4", RTYPE_GP | 8}, \
2687 {"$a5", RTYPE_GP | 9}, \
2688 {"$a6", RTYPE_GP | 10}, \
2689 {"$a7", RTYPE_GP | 11}, \
2690 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2691 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2692 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2693 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2694 {"$t0", RTYPE_GP | 12}, \
2695 {"$t1", RTYPE_GP | 13}, \
2696 {"$t2", RTYPE_GP | 14}, \
2697 {"$t3", RTYPE_GP | 15}
2699 #define O32_SYMBOLIC_REGISTER_NAMES \
2700 {"$t0", RTYPE_GP | 8}, \
2701 {"$t1", RTYPE_GP | 9}, \
2702 {"$t2", RTYPE_GP | 10}, \
2703 {"$t3", RTYPE_GP | 11}, \
2704 {"$t4", RTYPE_GP | 12}, \
2705 {"$t5", RTYPE_GP | 13}, \
2706 {"$t6", RTYPE_GP | 14}, \
2707 {"$t7", RTYPE_GP | 15}, \
2708 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2709 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2710 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2711 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2713 /* Remaining symbolic register names */
2714 #define SYMBOLIC_REGISTER_NAMES \
2715 {"$zero", RTYPE_GP | 0}, \
2716 {"$at", RTYPE_GP | 1}, \
2717 {"$AT", RTYPE_GP | 1}, \
2718 {"$v0", RTYPE_GP | 2}, \
2719 {"$v1", RTYPE_GP | 3}, \
2720 {"$a0", RTYPE_GP | 4}, \
2721 {"$a1", RTYPE_GP | 5}, \
2722 {"$a2", RTYPE_GP | 6}, \
2723 {"$a3", RTYPE_GP | 7}, \
2724 {"$s0", RTYPE_GP | 16}, \
2725 {"$s1", RTYPE_GP | 17}, \
2726 {"$s2", RTYPE_GP | 18}, \
2727 {"$s3", RTYPE_GP | 19}, \
2728 {"$s4", RTYPE_GP | 20}, \
2729 {"$s5", RTYPE_GP | 21}, \
2730 {"$s6", RTYPE_GP | 22}, \
2731 {"$s7", RTYPE_GP | 23}, \
2732 {"$t8", RTYPE_GP | 24}, \
2733 {"$t9", RTYPE_GP | 25}, \
2734 {"$k0", RTYPE_GP | 26}, \
2735 {"$kt0", RTYPE_GP | 26}, \
2736 {"$k1", RTYPE_GP | 27}, \
2737 {"$kt1", RTYPE_GP | 27}, \
2738 {"$gp", RTYPE_GP | 28}, \
2739 {"$sp", RTYPE_GP | 29}, \
2740 {"$s8", RTYPE_GP | 30}, \
2741 {"$fp", RTYPE_GP | 30}, \
2742 {"$ra", RTYPE_GP | 31}
2744 #define MIPS16_SPECIAL_REGISTER_NAMES \
2745 {"$pc", RTYPE_PC | 0}
2747 #define MDMX_VECTOR_REGISTER_NAMES \
2748 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2749 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2750 {"$v2", RTYPE_VEC | 2}, \
2751 {"$v3", RTYPE_VEC | 3}, \
2752 {"$v4", RTYPE_VEC | 4}, \
2753 {"$v5", RTYPE_VEC | 5}, \
2754 {"$v6", RTYPE_VEC | 6}, \
2755 {"$v7", RTYPE_VEC | 7}, \
2756 {"$v8", RTYPE_VEC | 8}, \
2757 {"$v9", RTYPE_VEC | 9}, \
2758 {"$v10", RTYPE_VEC | 10}, \
2759 {"$v11", RTYPE_VEC | 11}, \
2760 {"$v12", RTYPE_VEC | 12}, \
2761 {"$v13", RTYPE_VEC | 13}, \
2762 {"$v14", RTYPE_VEC | 14}, \
2763 {"$v15", RTYPE_VEC | 15}, \
2764 {"$v16", RTYPE_VEC | 16}, \
2765 {"$v17", RTYPE_VEC | 17}, \
2766 {"$v18", RTYPE_VEC | 18}, \
2767 {"$v19", RTYPE_VEC | 19}, \
2768 {"$v20", RTYPE_VEC | 20}, \
2769 {"$v21", RTYPE_VEC | 21}, \
2770 {"$v22", RTYPE_VEC | 22}, \
2771 {"$v23", RTYPE_VEC | 23}, \
2772 {"$v24", RTYPE_VEC | 24}, \
2773 {"$v25", RTYPE_VEC | 25}, \
2774 {"$v26", RTYPE_VEC | 26}, \
2775 {"$v27", RTYPE_VEC | 27}, \
2776 {"$v28", RTYPE_VEC | 28}, \
2777 {"$v29", RTYPE_VEC | 29}, \
2778 {"$v30", RTYPE_VEC | 30}, \
2779 {"$v31", RTYPE_VEC | 31}
2781 #define R5900_I_NAMES \
2782 {"$I", RTYPE_R5900_I | 0}
2784 #define R5900_Q_NAMES \
2785 {"$Q", RTYPE_R5900_Q | 0}
2787 #define R5900_R_NAMES \
2788 {"$R", RTYPE_R5900_R | 0}
2790 #define R5900_ACC_NAMES \
2791 {"$ACC", RTYPE_R5900_ACC | 0 }
2793 #define MIPS_DSP_ACCUMULATOR_NAMES \
2794 {"$ac0", RTYPE_ACC | 0}, \
2795 {"$ac1", RTYPE_ACC | 1}, \
2796 {"$ac2", RTYPE_ACC | 2}, \
2797 {"$ac3", RTYPE_ACC | 3}
2799 static const struct regname reg_names[] = {
2800 GENERIC_REGISTER_NUMBERS,
2802 FPU_CONDITION_CODE_NAMES,
2803 COPROC_CONDITION_CODE_NAMES,
2805 /* The $txx registers depends on the abi,
2806 these will be added later into the symbol table from
2807 one of the tables below once mips_abi is set after
2808 parsing of arguments from the command line. */
2809 SYMBOLIC_REGISTER_NAMES,
2811 MIPS16_SPECIAL_REGISTER_NAMES,
2812 MDMX_VECTOR_REGISTER_NAMES,
2817 MIPS_DSP_ACCUMULATOR_NAMES,
2821 static const struct regname reg_names_o32[] = {
2822 O32_SYMBOLIC_REGISTER_NAMES,
2826 static const struct regname reg_names_n32n64[] = {
2827 N32N64_SYMBOLIC_REGISTER_NAMES,
2831 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2832 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2833 of these register symbols, return the associated vector register,
2834 otherwise return SYMVAL itself. */
2837 mips_prefer_vec_regno (unsigned int symval)
2839 if ((symval & -2) == (RTYPE_GP | 2))
2840 return RTYPE_VEC | (symval & 1);
2844 /* Return true if string [S, E) is a valid register name, storing its
2845 symbol value in *SYMVAL_PTR if so. */
2848 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2853 /* Terminate name. */
2857 /* Look up the name. */
2858 symbol = symbol_find (s);
2861 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2864 *symval_ptr = S_GET_VALUE (symbol);
2868 /* Return true if the string at *SPTR is a valid register name. Allow it
2869 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2872 When returning true, move *SPTR past the register, store the
2873 register's symbol value in *SYMVAL_PTR and the channel mask in
2874 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2875 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2876 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2879 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2880 unsigned int *channels_ptr)
2884 unsigned int channels, symval, bit;
2886 /* Find end of name. */
2888 if (is_name_beginner (*e))
2890 while (is_part_of_name (*e))
2894 if (!mips_parse_register_1 (s, e, &symval))
2899 /* Eat characters from the end of the string that are valid
2900 channel suffixes. The preceding register must be $ACC or
2901 end with a digit, so there is no ambiguity. */
2904 for (q = "wzyx"; *q; q++, bit <<= 1)
2905 if (m > s && m[-1] == *q)
2912 || !mips_parse_register_1 (s, m, &symval)
2913 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2918 *symval_ptr = symval;
2920 *channels_ptr = channels;
2924 /* Check if SPTR points at a valid register specifier according to TYPES.
2925 If so, then return 1, advance S to consume the specifier and store
2926 the register's number in REGNOP, otherwise return 0. */
2929 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2933 if (mips_parse_register (s, ®no, NULL))
2935 if (types & RTYPE_VEC)
2936 regno = mips_prefer_vec_regno (regno);
2945 as_warn (_("unrecognized register name `%s'"), *s);
2950 return regno <= RNUM_MASK;
2953 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2954 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2957 mips_parse_vu0_channels (char *s, unsigned int *channels)
2962 for (i = 0; i < 4; i++)
2963 if (*s == "xyzw"[i])
2965 *channels |= 1 << (3 - i);
2971 /* Token types for parsed operand lists. */
2972 enum mips_operand_token_type {
2973 /* A plain register, e.g. $f2. */
2976 /* A 4-bit XYZW channel mask. */
2979 /* A constant vector index, e.g. [1]. */
2982 /* A register vector index, e.g. [$2]. */
2985 /* A continuous range of registers, e.g. $s0-$s4. */
2988 /* A (possibly relocated) expression. */
2991 /* A floating-point value. */
2994 /* A single character. This can be '(', ')' or ',', but '(' only appears
2998 /* A doubled character, either "--" or "++". */
3001 /* The end of the operand list. */
3005 /* A parsed operand token. */
3006 struct mips_operand_token
3008 /* The type of token. */
3009 enum mips_operand_token_type type;
3012 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3015 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3016 unsigned int channels;
3018 /* The integer value of an OT_INTEGER_INDEX. */
3021 /* The two register symbol values involved in an OT_REG_RANGE. */
3023 unsigned int regno1;
3024 unsigned int regno2;
3027 /* The value of an OT_INTEGER. The value is represented as an
3028 expression and the relocation operators that were applied to
3029 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3030 relocation operators were used. */
3033 bfd_reloc_code_real_type relocs[3];
3036 /* The binary data for an OT_FLOAT constant, and the number of bytes
3039 unsigned char data[8];
3043 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3048 /* An obstack used to construct lists of mips_operand_tokens. */
3049 static struct obstack mips_operand_tokens;
3051 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3054 mips_add_token (struct mips_operand_token *token,
3055 enum mips_operand_token_type type)
3058 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
3061 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3062 and OT_REG tokens for them if so, and return a pointer to the first
3063 unconsumed character. Return null otherwise. */
3066 mips_parse_base_start (char *s)
3068 struct mips_operand_token token;
3069 unsigned int regno, channels;
3070 bfd_boolean decrement_p;
3076 SKIP_SPACE_TABS (s);
3078 /* Only match "--" as part of a base expression. In other contexts "--X"
3079 is a double negative. */
3080 decrement_p = (s[0] == '-' && s[1] == '-');
3084 SKIP_SPACE_TABS (s);
3087 /* Allow a channel specifier because that leads to better error messages
3088 than treating something like "$vf0x++" as an expression. */
3089 if (!mips_parse_register (&s, ®no, &channels))
3093 mips_add_token (&token, OT_CHAR);
3098 mips_add_token (&token, OT_DOUBLE_CHAR);
3101 token.u.regno = regno;
3102 mips_add_token (&token, OT_REG);
3106 token.u.channels = channels;
3107 mips_add_token (&token, OT_CHANNELS);
3110 /* For consistency, only match "++" as part of base expressions too. */
3111 SKIP_SPACE_TABS (s);
3112 if (s[0] == '+' && s[1] == '+')
3116 mips_add_token (&token, OT_DOUBLE_CHAR);
3122 /* Parse one or more tokens from S. Return a pointer to the first
3123 unconsumed character on success. Return null if an error was found
3124 and store the error text in insn_error. FLOAT_FORMAT is as for
3125 mips_parse_arguments. */
3128 mips_parse_argument_token (char *s, char float_format)
3130 char *end, *save_in;
3132 unsigned int regno1, regno2, channels;
3133 struct mips_operand_token token;
3135 /* First look for "($reg", since we want to treat that as an
3136 OT_CHAR and OT_REG rather than an expression. */
3137 end = mips_parse_base_start (s);
3141 /* Handle other characters that end up as OT_CHARs. */
3142 if (*s == ')' || *s == ',')
3145 mips_add_token (&token, OT_CHAR);
3150 /* Handle tokens that start with a register. */
3151 if (mips_parse_register (&s, ®no1, &channels))
3155 /* A register and a VU0 channel suffix. */
3156 token.u.regno = regno1;
3157 mips_add_token (&token, OT_REG);
3159 token.u.channels = channels;
3160 mips_add_token (&token, OT_CHANNELS);
3164 SKIP_SPACE_TABS (s);
3167 /* A register range. */
3169 SKIP_SPACE_TABS (s);
3170 if (!mips_parse_register (&s, ®no2, NULL))
3172 set_insn_error (0, _("invalid register range"));
3176 token.u.reg_range.regno1 = regno1;
3177 token.u.reg_range.regno2 = regno2;
3178 mips_add_token (&token, OT_REG_RANGE);
3182 /* Add the register itself. */
3183 token.u.regno = regno1;
3184 mips_add_token (&token, OT_REG);
3186 /* Check for a vector index. */
3190 SKIP_SPACE_TABS (s);
3191 if (mips_parse_register (&s, &token.u.regno, NULL))
3192 mips_add_token (&token, OT_REG_INDEX);
3195 expressionS element;
3197 my_getExpression (&element, s);
3198 if (element.X_op != O_constant)
3200 set_insn_error (0, _("vector element must be constant"));
3204 token.u.index = element.X_add_number;
3205 mips_add_token (&token, OT_INTEGER_INDEX);
3207 SKIP_SPACE_TABS (s);
3210 set_insn_error (0, _("missing `]'"));
3220 /* First try to treat expressions as floats. */
3221 save_in = input_line_pointer;
3222 input_line_pointer = s;
3223 err = md_atof (float_format, (char *) token.u.flt.data,
3224 &token.u.flt.length);
3225 end = input_line_pointer;
3226 input_line_pointer = save_in;
3229 set_insn_error (0, err);
3234 mips_add_token (&token, OT_FLOAT);
3239 /* Treat everything else as an integer expression. */
3240 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3241 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3242 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3243 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3245 mips_add_token (&token, OT_INTEGER);
3249 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3250 if expressions should be treated as 32-bit floating-point constants,
3251 'd' if they should be treated as 64-bit floating-point constants,
3252 or 0 if they should be treated as integer expressions (the usual case).
3254 Return a list of tokens on success, otherwise return 0. The caller
3255 must obstack_free the list after use. */
3257 static struct mips_operand_token *
3258 mips_parse_arguments (char *s, char float_format)
3260 struct mips_operand_token token;
3262 SKIP_SPACE_TABS (s);
3265 s = mips_parse_argument_token (s, float_format);
3268 obstack_free (&mips_operand_tokens,
3269 obstack_finish (&mips_operand_tokens));
3272 SKIP_SPACE_TABS (s);
3274 mips_add_token (&token, OT_END);
3275 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3278 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3279 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3282 is_opcode_valid (const struct mips_opcode *mo)
3284 int isa = mips_opts.isa;
3285 int ase = mips_opts.ase;
3289 if (ISA_HAS_64BIT_REGS (isa))
3290 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3291 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3292 ase |= mips_ases[i].flags64;
3294 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3297 /* Check whether the instruction or macro requires single-precision or
3298 double-precision floating-point support. Note that this information is
3299 stored differently in the opcode table for insns and macros. */
3300 if (mo->pinfo == INSN_MACRO)
3302 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3303 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3307 fp_s = mo->pinfo & FP_S;
3308 fp_d = mo->pinfo & FP_D;
3311 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3314 if (fp_s && mips_opts.soft_float)
3320 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3321 selected ISA and architecture. */
3324 is_opcode_valid_16 (const struct mips_opcode *mo)
3326 int isa = mips_opts.isa;
3327 int ase = mips_opts.ase;
3330 if (ISA_HAS_64BIT_REGS (isa))
3331 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3332 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3333 ase |= mips_ases[i].flags64;
3335 return opcode_is_member (mo, isa, ase, mips_opts.arch);
3338 /* Return TRUE if the size of the microMIPS opcode MO matches one
3339 explicitly requested. Always TRUE in the standard MIPS mode.
3340 Use is_size_valid_16 for MIPS16 opcodes. */
3343 is_size_valid (const struct mips_opcode *mo)
3345 if (!mips_opts.micromips)
3348 if (mips_opts.insn32)
3350 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3352 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3355 if (!forced_insn_length)
3357 if (mo->pinfo == INSN_MACRO)
3359 return forced_insn_length == micromips_insn_length (mo);
3362 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3363 explicitly requested. */
3366 is_size_valid_16 (const struct mips_opcode *mo)
3368 if (!forced_insn_length)
3370 if (mo->pinfo == INSN_MACRO)
3372 if (forced_insn_length == 2 && mips_opcode_32bit_p (mo))
3374 if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY))
3379 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3380 of the preceding instruction. Always TRUE in the standard MIPS mode.
3382 We don't accept macros in 16-bit delay slots to avoid a case where
3383 a macro expansion fails because it relies on a preceding 32-bit real
3384 instruction to have matched and does not handle the operands correctly.
3385 The only macros that may expand to 16-bit instructions are JAL that
3386 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3387 and BGT (that likewise cannot be placed in a delay slot) that decay to
3388 a NOP. In all these cases the macros precede any corresponding real
3389 instruction definitions in the opcode table, so they will match in the
3390 second pass where the size of the delay slot is ignored and therefore
3391 produce correct code. */
3394 is_delay_slot_valid (const struct mips_opcode *mo)
3396 if (!mips_opts.micromips)
3399 if (mo->pinfo == INSN_MACRO)
3400 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3401 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3402 && micromips_insn_length (mo) != 4)
3404 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3405 && micromips_insn_length (mo) != 2)
3411 /* For consistency checking, verify that all bits of OPCODE are specified
3412 either by the match/mask part of the instruction definition, or by the
3413 operand list. Also build up a list of operands in OPERANDS.
3415 INSN_BITS says which bits of the instruction are significant.
3416 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3417 provides the mips_operand description of each operand. DECODE_OPERAND
3418 is null for MIPS16 instructions. */
3421 validate_mips_insn (const struct mips_opcode *opcode,
3422 unsigned long insn_bits,
3423 const struct mips_operand *(*decode_operand) (const char *),
3424 struct mips_operand_array *operands)
3427 unsigned long used_bits, doubled, undefined, opno, mask;
3428 const struct mips_operand *operand;
3430 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3431 if ((mask & opcode->match) != opcode->match)
3433 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3434 opcode->name, opcode->args);
3439 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3440 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3441 for (s = opcode->args; *s; ++s)
3454 if (!decode_operand)
3455 operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode));
3457 operand = decode_operand (s);
3458 if (!operand && opcode->pinfo != INSN_MACRO)
3460 as_bad (_("internal: unknown operand type: %s %s"),
3461 opcode->name, opcode->args);
3464 gas_assert (opno < MAX_OPERANDS);
3465 operands->operand[opno] = operand;
3466 if (!decode_operand && operand
3467 && operand->type == OP_INT && operand->lsb == 0
3468 && mips_opcode_32bit_p (opcode))
3469 used_bits |= mips16_immed_extend (-1, operand->size);
3470 else if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3472 used_bits = mips_insert_operand (operand, used_bits, -1);
3473 if (operand->type == OP_MDMX_IMM_REG)
3474 /* Bit 5 is the format selector (OB vs QH). The opcode table
3475 has separate entries for each format. */
3476 used_bits &= ~(1 << (operand->lsb + 5));
3477 if (operand->type == OP_ENTRY_EXIT_LIST)
3478 used_bits &= ~(mask & 0x700);
3479 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3480 operand field that cannot be fully described with LSB/SIZE. */
3481 if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6)
3482 used_bits &= ~0x6000;
3484 /* Skip prefix characters. */
3485 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3490 doubled = used_bits & mask & insn_bits;
3493 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3494 " %s %s"), doubled, opcode->name, opcode->args);
3498 undefined = ~used_bits & insn_bits;
3499 if (opcode->pinfo != INSN_MACRO && undefined)
3501 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3502 undefined, opcode->name, opcode->args);
3505 used_bits &= ~insn_bits;
3508 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3509 used_bits, opcode->name, opcode->args);
3515 /* The MIPS16 version of validate_mips_insn. */
3518 validate_mips16_insn (const struct mips_opcode *opcode,
3519 struct mips_operand_array *operands)
3521 unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff;
3523 return validate_mips_insn (opcode, insn_bits, 0, operands);
3526 /* The microMIPS version of validate_mips_insn. */
3529 validate_micromips_insn (const struct mips_opcode *opc,
3530 struct mips_operand_array *operands)
3532 unsigned long insn_bits;
3533 unsigned long major;
3534 unsigned int length;
3536 if (opc->pinfo == INSN_MACRO)
3537 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3540 length = micromips_insn_length (opc);
3541 if (length != 2 && length != 4)
3543 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3544 "%s %s"), length, opc->name, opc->args);
3547 major = opc->match >> (10 + 8 * (length - 2));
3548 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3549 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3551 as_bad (_("internal error: bad microMIPS opcode "
3552 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3556 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3557 insn_bits = 1 << 4 * length;
3558 insn_bits <<= 4 * length;
3560 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3564 /* This function is called once, at assembler startup time. It should set up
3565 all the tables, etc. that the MD part of the assembler will need. */
3570 const char *retval = NULL;
3574 if (mips_pic != NO_PIC)
3576 if (g_switch_seen && g_switch_value != 0)
3577 as_bad (_("-G may not be used in position-independent code"));
3580 else if (mips_abicalls)
3582 if (g_switch_seen && g_switch_value != 0)
3583 as_bad (_("-G may not be used with abicalls"));
3587 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3588 as_warn (_("could not set architecture and machine"));
3590 op_hash = hash_new ();
3592 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3593 for (i = 0; i < NUMOPCODES;)
3595 const char *name = mips_opcodes[i].name;
3597 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3600 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3601 mips_opcodes[i].name, retval);
3602 /* Probably a memory allocation problem? Give up now. */
3603 as_fatal (_("broken assembler, no assembly attempted"));
3607 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3608 decode_mips_operand, &mips_operands[i]))
3610 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3612 create_insn (&nop_insn, mips_opcodes + i);
3613 if (mips_fix_loongson2f_nop)
3614 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3615 nop_insn.fixed_p = 1;
3619 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3622 mips16_op_hash = hash_new ();
3623 mips16_operands = XCNEWVEC (struct mips_operand_array,
3624 bfd_mips16_num_opcodes);
3627 while (i < bfd_mips16_num_opcodes)
3629 const char *name = mips16_opcodes[i].name;
3631 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3633 as_fatal (_("internal: can't hash `%s': %s"),
3634 mips16_opcodes[i].name, retval);
3637 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3639 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3641 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3642 mips16_nop_insn.fixed_p = 1;
3646 while (i < bfd_mips16_num_opcodes
3647 && strcmp (mips16_opcodes[i].name, name) == 0);
3650 micromips_op_hash = hash_new ();
3651 micromips_operands = XCNEWVEC (struct mips_operand_array,
3652 bfd_micromips_num_opcodes);
3655 while (i < bfd_micromips_num_opcodes)
3657 const char *name = micromips_opcodes[i].name;
3659 retval = hash_insert (micromips_op_hash, name,
3660 (void *) µmips_opcodes[i]);
3662 as_fatal (_("internal: can't hash `%s': %s"),
3663 micromips_opcodes[i].name, retval);
3666 struct mips_cl_insn *micromips_nop_insn;
3668 if (!validate_micromips_insn (µmips_opcodes[i],
3669 µmips_operands[i]))
3672 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3674 if (micromips_insn_length (micromips_opcodes + i) == 2)
3675 micromips_nop_insn = µmips_nop16_insn;
3676 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3677 micromips_nop_insn = µmips_nop32_insn;
3681 if (micromips_nop_insn->insn_mo == NULL
3682 && strcmp (name, "nop") == 0)
3684 create_insn (micromips_nop_insn, micromips_opcodes + i);
3685 micromips_nop_insn->fixed_p = 1;
3689 while (++i < bfd_micromips_num_opcodes
3690 && strcmp (micromips_opcodes[i].name, name) == 0);
3694 as_fatal (_("broken assembler, no assembly attempted"));
3696 /* We add all the general register names to the symbol table. This
3697 helps us detect invalid uses of them. */
3698 for (i = 0; reg_names[i].name; i++)
3699 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3700 reg_names[i].num, /* & RNUM_MASK, */
3701 &zero_address_frag));
3703 for (i = 0; reg_names_n32n64[i].name; i++)
3704 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3705 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3706 &zero_address_frag));
3708 for (i = 0; reg_names_o32[i].name; i++)
3709 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3710 reg_names_o32[i].num, /* & RNUM_MASK, */
3711 &zero_address_frag));
3713 for (i = 0; i < 32; i++)
3717 /* R5900 VU0 floating-point register. */
3718 sprintf (regname, "$vf%d", i);
3719 symbol_table_insert (symbol_new (regname, reg_section,
3720 RTYPE_VF | i, &zero_address_frag));
3722 /* R5900 VU0 integer register. */
3723 sprintf (regname, "$vi%d", i);
3724 symbol_table_insert (symbol_new (regname, reg_section,
3725 RTYPE_VI | i, &zero_address_frag));
3728 sprintf (regname, "$w%d", i);
3729 symbol_table_insert (symbol_new (regname, reg_section,
3730 RTYPE_MSA | i, &zero_address_frag));
3733 obstack_init (&mips_operand_tokens);
3735 mips_no_prev_insn ();
3738 mips_cprmask[0] = 0;
3739 mips_cprmask[1] = 0;
3740 mips_cprmask[2] = 0;
3741 mips_cprmask[3] = 0;
3743 /* set the default alignment for the text section (2**2) */
3744 record_alignment (text_section, 2);
3746 bfd_set_gp_size (stdoutput, g_switch_value);
3748 /* On a native system other than VxWorks, sections must be aligned
3749 to 16 byte boundaries. When configured for an embedded ELF
3750 target, we don't bother. */
3751 if (strncmp (TARGET_OS, "elf", 3) != 0
3752 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3754 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3755 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3756 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3759 /* Create a .reginfo section for register masks and a .mdebug
3760 section for debugging information. */
3768 subseg = now_subseg;
3770 /* The ABI says this section should be loaded so that the
3771 running program can access it. However, we don't load it
3772 if we are configured for an embedded target */
3773 flags = SEC_READONLY | SEC_DATA;
3774 if (strncmp (TARGET_OS, "elf", 3) != 0)
3775 flags |= SEC_ALLOC | SEC_LOAD;
3777 if (mips_abi != N64_ABI)
3779 sec = subseg_new (".reginfo", (subsegT) 0);
3781 bfd_set_section_flags (stdoutput, sec, flags);
3782 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3784 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3788 /* The 64-bit ABI uses a .MIPS.options section rather than
3789 .reginfo section. */
3790 sec = subseg_new (".MIPS.options", (subsegT) 0);
3791 bfd_set_section_flags (stdoutput, sec, flags);
3792 bfd_set_section_alignment (stdoutput, sec, 3);
3794 /* Set up the option header. */
3796 Elf_Internal_Options opthdr;
3799 opthdr.kind = ODK_REGINFO;
3800 opthdr.size = (sizeof (Elf_External_Options)
3801 + sizeof (Elf64_External_RegInfo));
3804 f = frag_more (sizeof (Elf_External_Options));
3805 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3806 (Elf_External_Options *) f);
3808 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3812 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3813 bfd_set_section_flags (stdoutput, sec,
3814 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3815 bfd_set_section_alignment (stdoutput, sec, 3);
3816 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3818 if (ECOFF_DEBUGGING)
3820 sec = subseg_new (".mdebug", (subsegT) 0);
3821 (void) bfd_set_section_flags (stdoutput, sec,
3822 SEC_HAS_CONTENTS | SEC_READONLY);
3823 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3825 else if (mips_flag_pdr)
3827 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3828 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3829 SEC_READONLY | SEC_RELOC
3831 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3834 subseg_set (seg, subseg);
3837 if (mips_fix_vr4120)
3838 init_vr4120_conflicts ();
3842 fpabi_incompatible_with (int fpabi, const char *what)
3844 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3845 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3849 fpabi_requires (int fpabi, const char *what)
3851 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3852 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3855 /* Check -mabi and register sizes against the specified FP ABI. */
3857 check_fpabi (int fpabi)
3861 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3862 if (file_mips_opts.soft_float)
3863 fpabi_incompatible_with (fpabi, "softfloat");
3864 else if (file_mips_opts.single_float)
3865 fpabi_incompatible_with (fpabi, "singlefloat");
3866 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3867 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3868 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3869 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3872 case Val_GNU_MIPS_ABI_FP_XX:
3873 if (mips_abi != O32_ABI)
3874 fpabi_requires (fpabi, "-mabi=32");
3875 else if (file_mips_opts.soft_float)
3876 fpabi_incompatible_with (fpabi, "softfloat");
3877 else if (file_mips_opts.single_float)
3878 fpabi_incompatible_with (fpabi, "singlefloat");
3879 else if (file_mips_opts.fp != 0)
3880 fpabi_requires (fpabi, "fp=xx");
3883 case Val_GNU_MIPS_ABI_FP_64A:
3884 case Val_GNU_MIPS_ABI_FP_64:
3885 if (mips_abi != O32_ABI)
3886 fpabi_requires (fpabi, "-mabi=32");
3887 else if (file_mips_opts.soft_float)
3888 fpabi_incompatible_with (fpabi, "softfloat");
3889 else if (file_mips_opts.single_float)
3890 fpabi_incompatible_with (fpabi, "singlefloat");
3891 else if (file_mips_opts.fp != 64)
3892 fpabi_requires (fpabi, "fp=64");
3893 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3894 fpabi_incompatible_with (fpabi, "nooddspreg");
3895 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3896 fpabi_requires (fpabi, "nooddspreg");
3899 case Val_GNU_MIPS_ABI_FP_SINGLE:
3900 if (file_mips_opts.soft_float)
3901 fpabi_incompatible_with (fpabi, "softfloat");
3902 else if (!file_mips_opts.single_float)
3903 fpabi_requires (fpabi, "singlefloat");
3906 case Val_GNU_MIPS_ABI_FP_SOFT:
3907 if (!file_mips_opts.soft_float)
3908 fpabi_requires (fpabi, "softfloat");
3911 case Val_GNU_MIPS_ABI_FP_OLD_64:
3912 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3913 Tag_GNU_MIPS_ABI_FP, fpabi);
3916 case Val_GNU_MIPS_ABI_FP_NAN2008:
3917 /* Silently ignore compatibility value. */
3921 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3922 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3927 /* Perform consistency checks on the current options. */
3930 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3932 /* Check the size of integer registers agrees with the ABI and ISA. */
3933 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3934 as_bad (_("`gp=64' used with a 32-bit processor"));
3936 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3937 as_bad (_("`gp=32' used with a 64-bit ABI"));
3939 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3940 as_bad (_("`gp=64' used with a 32-bit ABI"));
3942 /* Check the size of the float registers agrees with the ABI and ISA. */
3946 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3947 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3948 else if (opts->single_float == 1)
3949 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3952 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3953 as_bad (_("`fp=64' used with a 32-bit fpu"));
3955 && ABI_NEEDS_32BIT_REGS (mips_abi)
3956 && !ISA_HAS_MXHC1 (opts->isa))
3957 as_warn (_("`fp=64' used with a 32-bit ABI"));
3961 && ABI_NEEDS_64BIT_REGS (mips_abi))
3962 as_warn (_("`fp=32' used with a 64-bit ABI"));
3963 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
3964 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3967 as_bad (_("Unknown size of floating point registers"));
3971 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3972 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3974 if (opts->micromips == 1 && opts->mips16 == 1)
3975 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3976 else if (ISA_IS_R6 (opts->isa)
3977 && (opts->micromips == 1
3978 || opts->mips16 == 1))
3979 as_fatal (_("`%s' cannot be used with `%s'"),
3980 opts->micromips ? "micromips" : "mips16",
3981 mips_cpu_info_from_isa (opts->isa)->name);
3983 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3984 as_fatal (_("branch relaxation is not supported in `%s'"),
3985 mips_cpu_info_from_isa (opts->isa)->name);
3988 /* Perform consistency checks on the module level options exactly once.
3989 This is a deferred check that happens:
3990 at the first .set directive
3991 or, at the first pseudo op that generates code (inc .dc.a)
3992 or, at the first instruction
3996 file_mips_check_options (void)
3998 const struct mips_cpu_info *arch_info = 0;
4000 if (file_mips_opts_checked)
4003 /* The following code determines the register size.
4004 Similar code was added to GCC 3.3 (see override_options() in
4005 config/mips/mips.c). The GAS and GCC code should be kept in sync
4006 as much as possible. */
4008 if (file_mips_opts.gp < 0)
4010 /* Infer the integer register size from the ABI and processor.
4011 Restrict ourselves to 32-bit registers if that's all the
4012 processor has, or if the ABI cannot handle 64-bit registers. */
4013 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
4014 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
4018 if (file_mips_opts.fp < 0)
4020 /* No user specified float register size.
4021 ??? GAS treats single-float processors as though they had 64-bit
4022 float registers (although it complains when double-precision
4023 instructions are used). As things stand, saying they have 32-bit
4024 registers would lead to spurious "register must be even" messages.
4025 So here we assume float registers are never smaller than the
4027 if (file_mips_opts.gp == 64)
4028 /* 64-bit integer registers implies 64-bit float registers. */
4029 file_mips_opts.fp = 64;
4030 else if ((file_mips_opts.ase & FP64_ASES)
4031 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
4032 /* Handle ASEs that require 64-bit float registers, if possible. */
4033 file_mips_opts.fp = 64;
4034 else if (ISA_IS_R6 (mips_opts.isa))
4035 /* R6 implies 64-bit float registers. */
4036 file_mips_opts.fp = 64;
4038 /* 32-bit float registers. */
4039 file_mips_opts.fp = 32;
4042 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
4044 /* Disable operations on odd-numbered floating-point registers by default
4045 when using the FPXX ABI. */
4046 if (file_mips_opts.oddspreg < 0)
4048 if (file_mips_opts.fp == 0)
4049 file_mips_opts.oddspreg = 0;
4051 file_mips_opts.oddspreg = 1;
4054 /* End of GCC-shared inference code. */
4056 /* This flag is set when we have a 64-bit capable CPU but use only
4057 32-bit wide registers. Note that EABI does not use it. */
4058 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
4059 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
4060 || mips_abi == O32_ABI))
4063 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
4064 as_bad (_("trap exception not supported at ISA 1"));
4066 /* If the selected architecture includes support for ASEs, enable
4067 generation of code for them. */
4068 if (file_mips_opts.mips16 == -1)
4069 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
4070 if (file_mips_opts.micromips == -1)
4071 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
4074 if (mips_nan2008 == -1)
4075 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
4076 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
4077 as_fatal (_("`%s' does not support legacy NaN"),
4078 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
4080 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4081 being selected implicitly. */
4082 if (file_mips_opts.fp != 64)
4083 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
4085 /* If the user didn't explicitly select or deselect a particular ASE,
4086 use the default setting for the CPU. */
4087 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
4089 /* Set up the current options. These may change throughout assembly. */
4090 mips_opts = file_mips_opts;
4092 mips_check_isa_supports_ases ();
4093 mips_check_options (&file_mips_opts, TRUE);
4094 file_mips_opts_checked = TRUE;
4096 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
4097 as_warn (_("could not set architecture and machine"));
4101 md_assemble (char *str)
4103 struct mips_cl_insn insn;
4104 bfd_reloc_code_real_type unused_reloc[3]
4105 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4107 file_mips_check_options ();
4109 imm_expr.X_op = O_absent;
4110 offset_expr.X_op = O_absent;
4111 offset_reloc[0] = BFD_RELOC_UNUSED;
4112 offset_reloc[1] = BFD_RELOC_UNUSED;
4113 offset_reloc[2] = BFD_RELOC_UNUSED;
4115 mips_mark_labels ();
4116 mips_assembling_insn = TRUE;
4117 clear_insn_error ();
4119 if (mips_opts.mips16)
4120 mips16_ip (str, &insn);
4123 mips_ip (str, &insn);
4124 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4125 str, insn.insn_opcode));
4129 report_insn_error (str);
4130 else if (insn.insn_mo->pinfo == INSN_MACRO)
4133 if (mips_opts.mips16)
4134 mips16_macro (&insn);
4141 if (offset_expr.X_op != O_absent)
4142 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4144 append_insn (&insn, NULL, unused_reloc, FALSE);
4147 mips_assembling_insn = FALSE;
4150 /* Convenience functions for abstracting away the differences between
4151 MIPS16 and non-MIPS16 relocations. */
4153 static inline bfd_boolean
4154 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4158 case BFD_RELOC_MIPS16_JMP:
4159 case BFD_RELOC_MIPS16_GPREL:
4160 case BFD_RELOC_MIPS16_GOT16:
4161 case BFD_RELOC_MIPS16_CALL16:
4162 case BFD_RELOC_MIPS16_HI16_S:
4163 case BFD_RELOC_MIPS16_HI16:
4164 case BFD_RELOC_MIPS16_LO16:
4165 case BFD_RELOC_MIPS16_16_PCREL_S1:
4173 static inline bfd_boolean
4174 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4178 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4179 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4180 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4181 case BFD_RELOC_MICROMIPS_GPREL16:
4182 case BFD_RELOC_MICROMIPS_JMP:
4183 case BFD_RELOC_MICROMIPS_HI16:
4184 case BFD_RELOC_MICROMIPS_HI16_S:
4185 case BFD_RELOC_MICROMIPS_LO16:
4186 case BFD_RELOC_MICROMIPS_LITERAL:
4187 case BFD_RELOC_MICROMIPS_GOT16:
4188 case BFD_RELOC_MICROMIPS_CALL16:
4189 case BFD_RELOC_MICROMIPS_GOT_HI16:
4190 case BFD_RELOC_MICROMIPS_GOT_LO16:
4191 case BFD_RELOC_MICROMIPS_CALL_HI16:
4192 case BFD_RELOC_MICROMIPS_CALL_LO16:
4193 case BFD_RELOC_MICROMIPS_SUB:
4194 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4195 case BFD_RELOC_MICROMIPS_GOT_OFST:
4196 case BFD_RELOC_MICROMIPS_GOT_DISP:
4197 case BFD_RELOC_MICROMIPS_HIGHEST:
4198 case BFD_RELOC_MICROMIPS_HIGHER:
4199 case BFD_RELOC_MICROMIPS_SCN_DISP:
4200 case BFD_RELOC_MICROMIPS_JALR:
4208 static inline bfd_boolean
4209 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4211 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4214 static inline bfd_boolean
4215 b_reloc_p (bfd_reloc_code_real_type reloc)
4217 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4218 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4219 || reloc == BFD_RELOC_16_PCREL_S2
4220 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
4221 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4222 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4223 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4226 static inline bfd_boolean
4227 got16_reloc_p (bfd_reloc_code_real_type reloc)
4229 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4230 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4233 static inline bfd_boolean
4234 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4236 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4237 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4240 static inline bfd_boolean
4241 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4243 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4244 || reloc == BFD_RELOC_MICROMIPS_LO16);
4247 static inline bfd_boolean
4248 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4250 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4253 static inline bfd_boolean
4254 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4256 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4257 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4260 /* Return true if RELOC is a PC-relative relocation that does not have
4261 full address range. */
4263 static inline bfd_boolean
4264 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4268 case BFD_RELOC_16_PCREL_S2:
4269 case BFD_RELOC_MIPS16_16_PCREL_S1:
4270 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4271 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4272 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4273 case BFD_RELOC_MIPS_21_PCREL_S2:
4274 case BFD_RELOC_MIPS_26_PCREL_S2:
4275 case BFD_RELOC_MIPS_18_PCREL_S3:
4276 case BFD_RELOC_MIPS_19_PCREL_S2:
4279 case BFD_RELOC_32_PCREL:
4280 case BFD_RELOC_HI16_S_PCREL:
4281 case BFD_RELOC_LO16_PCREL:
4282 return HAVE_64BIT_ADDRESSES;
4289 /* Return true if the given relocation might need a matching %lo().
4290 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4291 need a matching %lo() when applied to local symbols. */
4293 static inline bfd_boolean
4294 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4296 return (HAVE_IN_PLACE_ADDENDS
4297 && (hi16_reloc_p (reloc)
4298 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4299 all GOT16 relocations evaluate to "G". */
4300 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4303 /* Return the type of %lo() reloc needed by RELOC, given that
4304 reloc_needs_lo_p. */
4306 static inline bfd_reloc_code_real_type
4307 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4309 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4310 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4314 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4317 static inline bfd_boolean
4318 fixup_has_matching_lo_p (fixS *fixp)
4320 return (fixp->fx_next != NULL
4321 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4322 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4323 && fixp->fx_offset == fixp->fx_next->fx_offset);
4326 /* Move all labels in LABELS to the current insertion point. TEXT_P
4327 says whether the labels refer to text or data. */
4330 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4332 struct insn_label_list *l;
4335 for (l = labels; l != NULL; l = l->next)
4337 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4338 symbol_set_frag (l->label, frag_now);
4339 val = (valueT) frag_now_fix ();
4340 /* MIPS16/microMIPS text labels are stored as odd. */
4341 if (text_p && HAVE_CODE_COMPRESSION)
4343 S_SET_VALUE (l->label, val);
4347 /* Move all labels in insn_labels to the current insertion point
4348 and treat them as text labels. */
4351 mips_move_text_labels (void)
4353 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4356 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4359 s_is_linkonce (symbolS *sym, segT from_seg)
4361 bfd_boolean linkonce = FALSE;
4362 segT symseg = S_GET_SEGMENT (sym);
4364 if (symseg != from_seg && !S_IS_LOCAL (sym))
4366 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4368 /* The GNU toolchain uses an extension for ELF: a section
4369 beginning with the magic string .gnu.linkonce is a
4370 linkonce section. */
4371 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4372 sizeof ".gnu.linkonce" - 1) == 0)
4378 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4379 linker to handle them specially, such as generating jalx instructions
4380 when needed. We also make them odd for the duration of the assembly,
4381 in order to generate the right sort of code. We will make them even
4382 in the adjust_symtab routine, while leaving them marked. This is
4383 convenient for the debugger and the disassembler. The linker knows
4384 to make them odd again. */
4387 mips_compressed_mark_label (symbolS *label)
4389 gas_assert (HAVE_CODE_COMPRESSION);
4391 if (mips_opts.mips16)
4392 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4394 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4395 if ((S_GET_VALUE (label) & 1) == 0
4396 /* Don't adjust the address if the label is global or weak, or
4397 in a link-once section, since we'll be emitting symbol reloc
4398 references to it which will be patched up by the linker, and
4399 the final value of the symbol may or may not be MIPS16/microMIPS. */
4400 && !S_IS_WEAK (label)
4401 && !S_IS_EXTERNAL (label)
4402 && !s_is_linkonce (label, now_seg))
4403 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4406 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4409 mips_compressed_mark_labels (void)
4411 struct insn_label_list *l;
4413 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4414 mips_compressed_mark_label (l->label);
4417 /* End the current frag. Make it a variant frag and record the
4421 relax_close_frag (void)
4423 mips_macro_warning.first_frag = frag_now;
4424 frag_var (rs_machine_dependent, 0, 0,
4425 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1],
4426 mips_pic != NO_PIC),
4427 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4429 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4430 mips_relax.first_fixup = 0;
4433 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4434 See the comment above RELAX_ENCODE for more details. */
4437 relax_start (symbolS *symbol)
4439 gas_assert (mips_relax.sequence == 0);
4440 mips_relax.sequence = 1;
4441 mips_relax.symbol = symbol;
4444 /* Start generating the second version of a relaxable sequence.
4445 See the comment above RELAX_ENCODE for more details. */
4450 gas_assert (mips_relax.sequence == 1);
4451 mips_relax.sequence = 2;
4454 /* End the current relaxable sequence. */
4459 gas_assert (mips_relax.sequence == 2);
4460 relax_close_frag ();
4461 mips_relax.sequence = 0;
4464 /* Return true if IP is a delayed branch or jump. */
4466 static inline bfd_boolean
4467 delayed_branch_p (const struct mips_cl_insn *ip)
4469 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4470 | INSN_COND_BRANCH_DELAY
4471 | INSN_COND_BRANCH_LIKELY)) != 0;
4474 /* Return true if IP is a compact branch or jump. */
4476 static inline bfd_boolean
4477 compact_branch_p (const struct mips_cl_insn *ip)
4479 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4480 | INSN2_COND_BRANCH)) != 0;
4483 /* Return true if IP is an unconditional branch or jump. */
4485 static inline bfd_boolean
4486 uncond_branch_p (const struct mips_cl_insn *ip)
4488 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4489 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4492 /* Return true if IP is a branch-likely instruction. */
4494 static inline bfd_boolean
4495 branch_likely_p (const struct mips_cl_insn *ip)
4497 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4500 /* Return the type of nop that should be used to fill the delay slot
4501 of delayed branch IP. */
4503 static struct mips_cl_insn *
4504 get_delay_slot_nop (const struct mips_cl_insn *ip)
4506 if (mips_opts.micromips
4507 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4508 return µmips_nop32_insn;
4512 /* Return a mask that has bit N set if OPCODE reads the register(s)
4516 insn_read_mask (const struct mips_opcode *opcode)
4518 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4521 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4525 insn_write_mask (const struct mips_opcode *opcode)
4527 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4530 /* Return a mask of the registers specified by operand OPERAND of INSN.
4531 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4535 operand_reg_mask (const struct mips_cl_insn *insn,
4536 const struct mips_operand *operand,
4537 unsigned int type_mask)
4539 unsigned int uval, vsel;
4541 switch (operand->type)
4548 case OP_ADDIUSP_INT:
4549 case OP_ENTRY_EXIT_LIST:
4550 case OP_REPEAT_DEST_REG:
4551 case OP_REPEAT_PREV_REG:
4554 case OP_VU0_MATCH_SUFFIX:
4562 case OP_OPTIONAL_REG:
4564 const struct mips_reg_operand *reg_op;
4566 reg_op = (const struct mips_reg_operand *) operand;
4567 if (!(type_mask & (1 << reg_op->reg_type)))
4569 uval = insn_extract_operand (insn, operand);
4570 return 1 << mips_decode_reg_operand (reg_op, uval);
4575 const struct mips_reg_pair_operand *pair_op;
4577 pair_op = (const struct mips_reg_pair_operand *) operand;
4578 if (!(type_mask & (1 << pair_op->reg_type)))
4580 uval = insn_extract_operand (insn, operand);
4581 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4584 case OP_CLO_CLZ_DEST:
4585 if (!(type_mask & (1 << OP_REG_GP)))
4587 uval = insn_extract_operand (insn, operand);
4588 return (1 << (uval & 31)) | (1 << (uval >> 5));
4591 if (!(type_mask & (1 << OP_REG_GP)))
4593 uval = insn_extract_operand (insn, operand);
4594 gas_assert ((uval & 31) == (uval >> 5));
4595 return 1 << (uval & 31);
4598 case OP_NON_ZERO_REG:
4599 if (!(type_mask & (1 << OP_REG_GP)))
4601 uval = insn_extract_operand (insn, operand);
4602 return 1 << (uval & 31);
4604 case OP_LWM_SWM_LIST:
4607 case OP_SAVE_RESTORE_LIST:
4610 case OP_MDMX_IMM_REG:
4611 if (!(type_mask & (1 << OP_REG_VEC)))
4613 uval = insn_extract_operand (insn, operand);
4615 if ((vsel & 0x18) == 0x18)
4617 return 1 << (uval & 31);
4620 if (!(type_mask & (1 << OP_REG_GP)))
4622 return 1 << insn_extract_operand (insn, operand);
4627 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4628 where bit N of OPNO_MASK is set if operand N should be included.
4629 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4633 insn_reg_mask (const struct mips_cl_insn *insn,
4634 unsigned int type_mask, unsigned int opno_mask)
4636 unsigned int opno, reg_mask;
4640 while (opno_mask != 0)
4643 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4650 /* Return the mask of core registers that IP reads. */
4653 gpr_read_mask (const struct mips_cl_insn *ip)
4655 unsigned long pinfo, pinfo2;
4658 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4659 pinfo = ip->insn_mo->pinfo;
4660 pinfo2 = ip->insn_mo->pinfo2;
4661 if (pinfo & INSN_UDI)
4663 /* UDI instructions have traditionally been assumed to read RS
4665 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4666 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4668 if (pinfo & INSN_READ_GPR_24)
4670 if (pinfo2 & INSN2_READ_GPR_16)
4672 if (pinfo2 & INSN2_READ_SP)
4674 if (pinfo2 & INSN2_READ_GPR_31)
4676 /* Don't include register 0. */
4680 /* Return the mask of core registers that IP writes. */
4683 gpr_write_mask (const struct mips_cl_insn *ip)
4685 unsigned long pinfo, pinfo2;
4688 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4689 pinfo = ip->insn_mo->pinfo;
4690 pinfo2 = ip->insn_mo->pinfo2;
4691 if (pinfo & INSN_WRITE_GPR_24)
4693 if (pinfo & INSN_WRITE_GPR_31)
4695 if (pinfo & INSN_UDI)
4696 /* UDI instructions have traditionally been assumed to write to RD. */
4697 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4698 if (pinfo2 & INSN2_WRITE_SP)
4700 /* Don't include register 0. */
4704 /* Return the mask of floating-point registers that IP reads. */
4707 fpr_read_mask (const struct mips_cl_insn *ip)
4709 unsigned long pinfo;
4712 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4713 | (1 << OP_REG_MSA)),
4714 insn_read_mask (ip->insn_mo));
4715 pinfo = ip->insn_mo->pinfo;
4716 /* Conservatively treat all operands to an FP_D instruction are doubles.
4717 (This is overly pessimistic for things like cvt.d.s.) */
4718 if (FPR_SIZE != 64 && (pinfo & FP_D))
4723 /* Return the mask of floating-point registers that IP writes. */
4726 fpr_write_mask (const struct mips_cl_insn *ip)
4728 unsigned long pinfo;
4731 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4732 | (1 << OP_REG_MSA)),
4733 insn_write_mask (ip->insn_mo));
4734 pinfo = ip->insn_mo->pinfo;
4735 /* Conservatively treat all operands to an FP_D instruction are doubles.
4736 (This is overly pessimistic for things like cvt.s.d.) */
4737 if (FPR_SIZE != 64 && (pinfo & FP_D))
4742 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4743 Check whether that is allowed. */
4746 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4748 const char *s = insn->name;
4749 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4751 && mips_opts.oddspreg;
4753 if (insn->pinfo == INSN_MACRO)
4754 /* Let a macro pass, we'll catch it later when it is expanded. */
4757 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4758 otherwise it depends on oddspreg. */
4759 if ((insn->pinfo & FP_S)
4760 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4761 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4762 return FPR_SIZE == 32 || oddspreg;
4764 /* Allow odd registers for single-precision ops and double-precision if the
4765 floating-point registers are 64-bit wide. */
4766 switch (insn->pinfo & (FP_S | FP_D))
4772 return FPR_SIZE == 64;
4777 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4778 s = strchr (insn->name, '.');
4779 if (s != NULL && opnum == 2)
4780 s = strchr (s + 1, '.');
4781 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4784 return FPR_SIZE == 64;
4787 /* Information about an instruction argument that we're trying to match. */
4788 struct mips_arg_info
4790 /* The instruction so far. */
4791 struct mips_cl_insn *insn;
4793 /* The first unconsumed operand token. */
4794 struct mips_operand_token *token;
4796 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4799 /* The 1-based argument number, for error reporting. This does not
4800 count elided optional registers, etc.. */
4803 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4804 unsigned int last_regno;
4806 /* If the first operand was an OP_REG, this is the register that it
4807 specified, otherwise it is ILLEGAL_REG. */
4808 unsigned int dest_regno;
4810 /* The value of the last OP_INT operand. Only used for OP_MSB,
4811 where it gives the lsb position. */
4812 unsigned int last_op_int;
4814 /* If true, match routines should assume that no later instruction
4815 alternative matches and should therefore be as accommodating as
4816 possible. Match routines should not report errors if something
4817 is only invalid for !LAX_MATCH. */
4818 bfd_boolean lax_match;
4820 /* True if a reference to the current AT register was seen. */
4821 bfd_boolean seen_at;
4824 /* Record that the argument is out of range. */
4827 match_out_of_range (struct mips_arg_info *arg)
4829 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4832 /* Record that the argument isn't constant but needs to be. */
4835 match_not_constant (struct mips_arg_info *arg)
4837 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4841 /* Try to match an OT_CHAR token for character CH. Consume the token
4842 and return true on success, otherwise return false. */
4845 match_char (struct mips_arg_info *arg, char ch)
4847 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4857 /* Try to get an expression from the next tokens in ARG. Consume the
4858 tokens and return true on success, storing the expression value in
4859 VALUE and relocation types in R. */
4862 match_expression (struct mips_arg_info *arg, expressionS *value,
4863 bfd_reloc_code_real_type *r)
4865 /* If the next token is a '(' that was parsed as being part of a base
4866 expression, assume we have an elided offset. The later match will fail
4867 if this turns out to be wrong. */
4868 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4870 value->X_op = O_constant;
4871 value->X_add_number = 0;
4872 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4876 /* Reject register-based expressions such as "0+$2" and "(($2))".
4877 For plain registers the default error seems more appropriate. */
4878 if (arg->token->type == OT_INTEGER
4879 && arg->token->u.integer.value.X_op == O_register)
4881 set_insn_error (arg->argnum, _("register value used as expression"));
4885 if (arg->token->type == OT_INTEGER)
4887 *value = arg->token->u.integer.value;
4888 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4894 (arg->argnum, _("operand %d must be an immediate expression"),
4899 /* Try to get a constant expression from the next tokens in ARG. Consume
4900 the tokens and return true on success, storing the constant value
4904 match_const_int (struct mips_arg_info *arg, offsetT *value)
4907 bfd_reloc_code_real_type r[3];
4909 if (!match_expression (arg, &ex, r))
4912 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4913 *value = ex.X_add_number;
4916 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big)
4917 match_out_of_range (arg);
4919 match_not_constant (arg);
4925 /* Return the RTYPE_* flags for a register operand of type TYPE that
4926 appears in instruction OPCODE. */
4929 convert_reg_type (const struct mips_opcode *opcode,
4930 enum mips_reg_operand_type type)
4935 return RTYPE_NUM | RTYPE_GP;
4938 /* Allow vector register names for MDMX if the instruction is a 64-bit
4939 FPR load, store or move (including moves to and from GPRs). */
4940 if ((mips_opts.ase & ASE_MDMX)
4941 && (opcode->pinfo & FP_D)
4942 && (opcode->pinfo & (INSN_COPROC_MOVE
4943 | INSN_COPROC_MEMORY_DELAY
4946 | INSN_STORE_MEMORY)))
4947 return RTYPE_FPU | RTYPE_VEC;
4951 if (opcode->pinfo & (FP_D | FP_S))
4952 return RTYPE_CCC | RTYPE_FCC;
4956 if (opcode->membership & INSN_5400)
4958 return RTYPE_FPU | RTYPE_VEC;
4964 if (opcode->name[strlen (opcode->name) - 1] == '0')
4965 return RTYPE_NUM | RTYPE_CP0;
4972 return RTYPE_NUM | RTYPE_VI;
4975 return RTYPE_NUM | RTYPE_VF;
4977 case OP_REG_R5900_I:
4978 return RTYPE_R5900_I;
4980 case OP_REG_R5900_Q:
4981 return RTYPE_R5900_Q;
4983 case OP_REG_R5900_R:
4984 return RTYPE_R5900_R;
4986 case OP_REG_R5900_ACC:
4987 return RTYPE_R5900_ACC;
4992 case OP_REG_MSA_CTRL:
4998 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5001 check_regno (struct mips_arg_info *arg,
5002 enum mips_reg_operand_type type, unsigned int regno)
5004 if (AT && type == OP_REG_GP && regno == AT)
5005 arg->seen_at = TRUE;
5007 if (type == OP_REG_FP
5009 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
5011 /* This was a warning prior to introducing O32 FPXX and FP64 support
5012 so maintain a warning for FP32 but raise an error for the new
5015 as_warn (_("float register should be even, was %d"), regno);
5017 as_bad (_("float register should be even, was %d"), regno);
5020 if (type == OP_REG_CCC)
5025 name = arg->insn->insn_mo->name;
5026 length = strlen (name);
5027 if ((regno & 1) != 0
5028 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
5029 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
5030 as_warn (_("condition code register should be even for %s, was %d"),
5033 if ((regno & 3) != 0
5034 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
5035 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5040 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5041 a register of type TYPE. Return true on success, storing the register
5042 number in *REGNO and warning about any dubious uses. */
5045 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5046 unsigned int symval, unsigned int *regno)
5048 if (type == OP_REG_VEC)
5049 symval = mips_prefer_vec_regno (symval);
5050 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
5053 *regno = symval & RNUM_MASK;
5054 check_regno (arg, type, *regno);
5058 /* Try to interpret the next token in ARG as a register of type TYPE.
5059 Consume the token and return true on success, storing the register
5060 number in *REGNO. Return false on failure. */
5063 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5064 unsigned int *regno)
5066 if (arg->token->type == OT_REG
5067 && match_regno (arg, type, arg->token->u.regno, regno))
5075 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5076 Consume the token and return true on success, storing the register numbers
5077 in *REGNO1 and *REGNO2. Return false on failure. */
5080 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5081 unsigned int *regno1, unsigned int *regno2)
5083 if (match_reg (arg, type, regno1))
5088 if (arg->token->type == OT_REG_RANGE
5089 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
5090 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
5091 && *regno1 <= *regno2)
5099 /* OP_INT matcher. */
5102 match_int_operand (struct mips_arg_info *arg,
5103 const struct mips_operand *operand_base)
5105 const struct mips_int_operand *operand;
5107 int min_val, max_val, factor;
5110 operand = (const struct mips_int_operand *) operand_base;
5111 factor = 1 << operand->shift;
5112 min_val = mips_int_operand_min (operand);
5113 max_val = mips_int_operand_max (operand);
5115 if (operand_base->lsb == 0
5116 && operand_base->size == 16
5117 && operand->shift == 0
5118 && operand->bias == 0
5119 && (operand->max_val == 32767 || operand->max_val == 65535))
5121 /* The operand can be relocated. */
5122 if (!match_expression (arg, &offset_expr, offset_reloc))
5125 if (offset_expr.X_op == O_big)
5127 match_out_of_range (arg);
5131 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5132 /* Relocation operators were used. Accept the argument and
5133 leave the relocation value in offset_expr and offset_relocs
5134 for the caller to process. */
5137 if (offset_expr.X_op != O_constant)
5139 /* Accept non-constant operands if no later alternative matches,
5140 leaving it for the caller to process. */
5141 if (!arg->lax_match)
5143 match_not_constant (arg);
5146 offset_reloc[0] = BFD_RELOC_LO16;
5150 /* Clear the global state; we're going to install the operand
5152 sval = offset_expr.X_add_number;
5153 offset_expr.X_op = O_absent;
5155 /* For compatibility with older assemblers, we accept
5156 0x8000-0xffff as signed 16-bit numbers when only
5157 signed numbers are allowed. */
5160 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5161 if (!arg->lax_match && sval <= max_val)
5163 match_out_of_range (arg);
5170 if (!match_const_int (arg, &sval))
5174 arg->last_op_int = sval;
5176 if (sval < min_val || sval > max_val || sval % factor)
5178 match_out_of_range (arg);
5182 uval = (unsigned int) sval >> operand->shift;
5183 uval -= operand->bias;
5185 /* Handle -mfix-cn63xxp1. */
5187 && mips_fix_cn63xxp1
5188 && !mips_opts.micromips
5189 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5204 /* The rest must be changed to 28. */
5209 insn_insert_operand (arg->insn, operand_base, uval);
5213 /* OP_MAPPED_INT matcher. */
5216 match_mapped_int_operand (struct mips_arg_info *arg,
5217 const struct mips_operand *operand_base)
5219 const struct mips_mapped_int_operand *operand;
5220 unsigned int uval, num_vals;
5223 operand = (const struct mips_mapped_int_operand *) operand_base;
5224 if (!match_const_int (arg, &sval))
5227 num_vals = 1 << operand_base->size;
5228 for (uval = 0; uval < num_vals; uval++)
5229 if (operand->int_map[uval] == sval)
5231 if (uval == num_vals)
5233 match_out_of_range (arg);
5237 insn_insert_operand (arg->insn, operand_base, uval);
5241 /* OP_MSB matcher. */
5244 match_msb_operand (struct mips_arg_info *arg,
5245 const struct mips_operand *operand_base)
5247 const struct mips_msb_operand *operand;
5248 int min_val, max_val, max_high;
5249 offsetT size, sval, high;
5251 operand = (const struct mips_msb_operand *) operand_base;
5252 min_val = operand->bias;
5253 max_val = min_val + (1 << operand_base->size) - 1;
5254 max_high = operand->opsize;
5256 if (!match_const_int (arg, &size))
5259 high = size + arg->last_op_int;
5260 sval = operand->add_lsb ? high : size;
5262 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5264 match_out_of_range (arg);
5267 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5271 /* OP_REG matcher. */
5274 match_reg_operand (struct mips_arg_info *arg,
5275 const struct mips_operand *operand_base)
5277 const struct mips_reg_operand *operand;
5278 unsigned int regno, uval, num_vals;
5280 operand = (const struct mips_reg_operand *) operand_base;
5281 if (!match_reg (arg, operand->reg_type, ®no))
5284 if (operand->reg_map)
5286 num_vals = 1 << operand->root.size;
5287 for (uval = 0; uval < num_vals; uval++)
5288 if (operand->reg_map[uval] == regno)
5290 if (num_vals == uval)
5296 arg->last_regno = regno;
5297 if (arg->opnum == 1)
5298 arg->dest_regno = regno;
5299 insn_insert_operand (arg->insn, operand_base, uval);
5303 /* OP_REG_PAIR matcher. */
5306 match_reg_pair_operand (struct mips_arg_info *arg,
5307 const struct mips_operand *operand_base)
5309 const struct mips_reg_pair_operand *operand;
5310 unsigned int regno1, regno2, uval, num_vals;
5312 operand = (const struct mips_reg_pair_operand *) operand_base;
5313 if (!match_reg (arg, operand->reg_type, ®no1)
5314 || !match_char (arg, ',')
5315 || !match_reg (arg, operand->reg_type, ®no2))
5318 num_vals = 1 << operand_base->size;
5319 for (uval = 0; uval < num_vals; uval++)
5320 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5322 if (uval == num_vals)
5325 insn_insert_operand (arg->insn, operand_base, uval);
5329 /* OP_PCREL matcher. The caller chooses the relocation type. */
5332 match_pcrel_operand (struct mips_arg_info *arg)
5334 bfd_reloc_code_real_type r[3];
5336 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5339 /* OP_PERF_REG matcher. */
5342 match_perf_reg_operand (struct mips_arg_info *arg,
5343 const struct mips_operand *operand)
5347 if (!match_const_int (arg, &sval))
5352 || (mips_opts.arch == CPU_R5900
5353 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5354 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5356 set_insn_error (arg->argnum, _("invalid performance register"));
5360 insn_insert_operand (arg->insn, operand, sval);
5364 /* OP_ADDIUSP matcher. */
5367 match_addiusp_operand (struct mips_arg_info *arg,
5368 const struct mips_operand *operand)
5373 if (!match_const_int (arg, &sval))
5378 match_out_of_range (arg);
5383 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5385 match_out_of_range (arg);
5389 uval = (unsigned int) sval;
5390 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5391 insn_insert_operand (arg->insn, operand, uval);
5395 /* OP_CLO_CLZ_DEST matcher. */
5398 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5399 const struct mips_operand *operand)
5403 if (!match_reg (arg, OP_REG_GP, ®no))
5406 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5410 /* OP_CHECK_PREV matcher. */
5413 match_check_prev_operand (struct mips_arg_info *arg,
5414 const struct mips_operand *operand_base)
5416 const struct mips_check_prev_operand *operand;
5419 operand = (const struct mips_check_prev_operand *) operand_base;
5421 if (!match_reg (arg, OP_REG_GP, ®no))
5424 if (!operand->zero_ok && regno == 0)
5427 if ((operand->less_than_ok && regno < arg->last_regno)
5428 || (operand->greater_than_ok && regno > arg->last_regno)
5429 || (operand->equal_ok && regno == arg->last_regno))
5431 arg->last_regno = regno;
5432 insn_insert_operand (arg->insn, operand_base, regno);
5439 /* OP_SAME_RS_RT matcher. */
5442 match_same_rs_rt_operand (struct mips_arg_info *arg,
5443 const struct mips_operand *operand)
5447 if (!match_reg (arg, OP_REG_GP, ®no))
5452 set_insn_error (arg->argnum, _("the source register must not be $0"));
5456 arg->last_regno = regno;
5458 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5462 /* OP_LWM_SWM_LIST matcher. */
5465 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5466 const struct mips_operand *operand)
5468 unsigned int reglist, sregs, ra, regno1, regno2;
5469 struct mips_arg_info reset;
5472 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5476 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5481 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5484 while (match_char (arg, ',')
5485 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5488 if (operand->size == 2)
5490 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5496 and any permutations of these. */
5497 if ((reglist & 0xfff1ffff) != 0x80010000)
5500 sregs = (reglist >> 17) & 7;
5505 /* The list must include at least one of ra and s0-sN,
5506 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5507 which are $23 and $30 respectively.) E.g.:
5515 and any permutations of these. */
5516 if ((reglist & 0x3f00ffff) != 0)
5519 ra = (reglist >> 27) & 0x10;
5520 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5523 if ((sregs & -sregs) != sregs)
5526 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5530 /* OP_ENTRY_EXIT_LIST matcher. */
5533 match_entry_exit_operand (struct mips_arg_info *arg,
5534 const struct mips_operand *operand)
5537 bfd_boolean is_exit;
5539 /* The format is the same for both ENTRY and EXIT, but the constraints
5541 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5542 mask = (is_exit ? 7 << 3 : 0);
5545 unsigned int regno1, regno2;
5546 bfd_boolean is_freg;
5548 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5550 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5555 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5558 mask |= (5 + regno2) << 3;
5560 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5561 mask |= (regno2 - 3) << 3;
5562 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5563 mask |= (regno2 - 15) << 1;
5564 else if (regno1 == RA && regno2 == RA)
5569 while (match_char (arg, ','));
5571 insn_insert_operand (arg->insn, operand, mask);
5575 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5576 the argument register mask AMASK, the number of static registers
5577 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5578 respectively, and the frame size FRAME_SIZE. */
5581 mips_encode_save_restore (unsigned int amask, unsigned int nsreg,
5582 unsigned int ra, unsigned int s0, unsigned int s1,
5583 unsigned int frame_size)
5585 return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15)
5586 | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6));
5589 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5590 argument register mask AMASK, the number of static registers saved
5591 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5592 respectively, and the frame size FRAME_SIZE. */
5595 mips16_encode_save_restore (unsigned int amask, unsigned int nsreg,
5596 unsigned int ra, unsigned int s0, unsigned int s1,
5597 unsigned int frame_size)
5601 args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf);
5602 if (nsreg || amask || frame_size == 0 || frame_size > 16)
5603 args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16)
5604 | ((frame_size & 0xf0) << 16));
5608 /* OP_SAVE_RESTORE_LIST matcher. */
5611 match_save_restore_list_operand (struct mips_arg_info *arg)
5613 unsigned int opcode, args, statics, sregs;
5614 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5615 unsigned int arg_mask, ra, s0, s1;
5618 opcode = arg->insn->insn_opcode;
5620 num_frame_sizes = 0;
5629 unsigned int regno1, regno2;
5631 if (arg->token->type == OT_INTEGER)
5633 /* Handle the frame size. */
5634 if (!match_const_int (arg, &frame_size))
5636 num_frame_sizes += 1;
5640 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5643 while (regno1 <= regno2)
5645 if (regno1 >= 4 && regno1 <= 7)
5647 if (num_frame_sizes == 0)
5649 args |= 1 << (regno1 - 4);
5651 /* statics $a0-$a3 */
5652 statics |= 1 << (regno1 - 4);
5654 else if (regno1 >= 16 && regno1 <= 23)
5656 sregs |= 1 << (regno1 - 16);
5657 else if (regno1 == 30)
5660 else if (regno1 == 31)
5661 /* Add $ra to insn. */
5671 while (match_char (arg, ','));
5673 /* Encode args/statics combination. */
5676 else if (args == 0xf)
5677 /* All $a0-$a3 are args. */
5678 arg_mask = MIPS_SVRS_ALL_ARGS;
5679 else if (statics == 0xf)
5680 /* All $a0-$a3 are statics. */
5681 arg_mask = MIPS_SVRS_ALL_STATICS;
5684 /* Count arg registers. */
5694 /* Count static registers. */
5696 while (statics & 0x8)
5698 statics = (statics << 1) & 0xf;
5704 /* Encode args/statics. */
5705 arg_mask = (num_args << 2) | num_statics;
5708 /* Encode $s0/$s1. */
5709 if (sregs & (1 << 0)) /* $s0 */
5711 if (sregs & (1 << 1)) /* $s1 */
5715 /* Encode $s2-$s8. */
5725 /* Encode frame size. */
5726 if (num_frame_sizes == 0)
5728 set_insn_error (arg->argnum, _("missing frame size"));
5731 if (num_frame_sizes > 1)
5733 set_insn_error (arg->argnum, _("frame size specified twice"));
5736 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5738 set_insn_error (arg->argnum, _("invalid frame size"));
5743 /* Finally build the instruction. */
5744 if (mips_opts.mips16)
5745 opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5747 else if (!mips_opts.micromips)
5748 opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5753 arg->insn->insn_opcode = opcode;
5757 /* OP_MDMX_IMM_REG matcher. */
5760 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5761 const struct mips_operand *operand)
5763 unsigned int regno, uval;
5765 const struct mips_opcode *opcode;
5767 /* The mips_opcode records whether this is an octobyte or quadhalf
5768 instruction. Start out with that bit in place. */
5769 opcode = arg->insn->insn_mo;
5770 uval = mips_extract_operand (operand, opcode->match);
5771 is_qh = (uval != 0);
5773 if (arg->token->type == OT_REG)
5775 if ((opcode->membership & INSN_5400)
5776 && strcmp (opcode->name, "rzu.ob") == 0)
5778 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5783 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5787 /* Check whether this is a vector register or a broadcast of
5788 a single element. */
5789 if (arg->token->type == OT_INTEGER_INDEX)
5791 if (arg->token->u.index > (is_qh ? 3 : 7))
5793 set_insn_error (arg->argnum, _("invalid element selector"));
5796 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5801 /* A full vector. */
5802 if ((opcode->membership & INSN_5400)
5803 && (strcmp (opcode->name, "sll.ob") == 0
5804 || strcmp (opcode->name, "srl.ob") == 0))
5806 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5812 uval |= MDMX_FMTSEL_VEC_QH << 5;
5814 uval |= MDMX_FMTSEL_VEC_OB << 5;
5822 if (!match_const_int (arg, &sval))
5824 if (sval < 0 || sval > 31)
5826 match_out_of_range (arg);
5829 uval |= (sval & 31);
5831 uval |= MDMX_FMTSEL_IMM_QH << 5;
5833 uval |= MDMX_FMTSEL_IMM_OB << 5;
5835 insn_insert_operand (arg->insn, operand, uval);
5839 /* OP_IMM_INDEX matcher. */
5842 match_imm_index_operand (struct mips_arg_info *arg,
5843 const struct mips_operand *operand)
5845 unsigned int max_val;
5847 if (arg->token->type != OT_INTEGER_INDEX)
5850 max_val = (1 << operand->size) - 1;
5851 if (arg->token->u.index > max_val)
5853 match_out_of_range (arg);
5856 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5861 /* OP_REG_INDEX matcher. */
5864 match_reg_index_operand (struct mips_arg_info *arg,
5865 const struct mips_operand *operand)
5869 if (arg->token->type != OT_REG_INDEX)
5872 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5875 insn_insert_operand (arg->insn, operand, regno);
5880 /* OP_PC matcher. */
5883 match_pc_operand (struct mips_arg_info *arg)
5885 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5893 /* OP_REG28 matcher. */
5896 match_reg28_operand (struct mips_arg_info *arg)
5900 if (arg->token->type == OT_REG
5901 && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)
5910 /* OP_NON_ZERO_REG matcher. */
5913 match_non_zero_reg_operand (struct mips_arg_info *arg,
5914 const struct mips_operand *operand)
5918 if (!match_reg (arg, OP_REG_GP, ®no))
5924 arg->last_regno = regno;
5925 insn_insert_operand (arg->insn, operand, regno);
5929 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5930 register that we need to match. */
5933 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5937 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5940 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
5941 LENGTH is the length of the value in bytes (4 for float, 8 for double)
5942 and USING_GPRS says whether the destination is a GPR rather than an FPR.
5944 Return the constant in IMM and OFFSET as follows:
5946 - If the constant should be loaded via memory, set IMM to O_absent and
5947 OFFSET to the memory address.
5949 - Otherwise, if the constant should be loaded into two 32-bit registers,
5950 set IMM to the O_constant to load into the high register and OFFSET
5951 to the corresponding value for the low register.
5953 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5955 These constants only appear as the last operand in an instruction,
5956 and every instruction that accepts them in any variant accepts them
5957 in all variants. This means we don't have to worry about backing out
5958 any changes if the instruction does not match. We just match
5959 unconditionally and report an error if the constant is invalid. */
5962 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5963 expressionS *offset, int length, bfd_boolean using_gprs)
5968 const char *newname;
5969 unsigned char *data;
5971 /* Where the constant is placed is based on how the MIPS assembler
5974 length == 4 && using_gprs -- immediate value only
5975 length == 8 && using_gprs -- .rdata or immediate value
5976 length == 4 && !using_gprs -- .lit4 or immediate value
5977 length == 8 && !using_gprs -- .lit8 or immediate value
5979 The .lit4 and .lit8 sections are only used if permitted by the
5981 if (arg->token->type != OT_FLOAT)
5983 set_insn_error (arg->argnum, _("floating-point expression required"));
5987 gas_assert (arg->token->u.flt.length == length);
5988 data = arg->token->u.flt.data;
5991 /* Handle 32-bit constants for which an immediate value is best. */
5994 || g_switch_value < 4
5995 || (data[0] == 0 && data[1] == 0)
5996 || (data[2] == 0 && data[3] == 0)))
5998 imm->X_op = O_constant;
5999 if (!target_big_endian)
6000 imm->X_add_number = bfd_getl32 (data);
6002 imm->X_add_number = bfd_getb32 (data);
6003 offset->X_op = O_absent;
6007 /* Handle 64-bit constants for which an immediate value is best. */
6009 && !mips_disable_float_construction
6010 /* Constants can only be constructed in GPRs and copied to FPRs if the
6011 GPRs are at least as wide as the FPRs or MTHC1 is available.
6012 Unlike most tests for 32-bit floating-point registers this check
6013 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6014 permit 64-bit moves without MXHC1.
6015 Force the constant into memory otherwise. */
6018 || ISA_HAS_MXHC1 (mips_opts.isa)
6020 && ((data[0] == 0 && data[1] == 0)
6021 || (data[2] == 0 && data[3] == 0))
6022 && ((data[4] == 0 && data[5] == 0)
6023 || (data[6] == 0 && data[7] == 0)))
6025 /* The value is simple enough to load with a couple of instructions.
6026 If using 32-bit registers, set IMM to the high order 32 bits and
6027 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6029 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
6031 imm->X_op = O_constant;
6032 offset->X_op = O_constant;
6033 if (!target_big_endian)
6035 imm->X_add_number = bfd_getl32 (data + 4);
6036 offset->X_add_number = bfd_getl32 (data);
6040 imm->X_add_number = bfd_getb32 (data);
6041 offset->X_add_number = bfd_getb32 (data + 4);
6043 if (offset->X_add_number == 0)
6044 offset->X_op = O_absent;
6048 imm->X_op = O_constant;
6049 if (!target_big_endian)
6050 imm->X_add_number = bfd_getl64 (data);
6052 imm->X_add_number = bfd_getb64 (data);
6053 offset->X_op = O_absent;
6058 /* Switch to the right section. */
6060 subseg = now_subseg;
6063 gas_assert (!using_gprs && g_switch_value >= 4);
6068 if (using_gprs || g_switch_value < 8)
6069 newname = RDATA_SECTION_NAME;
6074 new_seg = subseg_new (newname, (subsegT) 0);
6075 bfd_set_section_flags (stdoutput, new_seg,
6076 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
6077 frag_align (length == 4 ? 2 : 3, 0, 0);
6078 if (strncmp (TARGET_OS, "elf", 3) != 0)
6079 record_alignment (new_seg, 4);
6081 record_alignment (new_seg, length == 4 ? 2 : 3);
6083 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
6085 /* Set the argument to the current address in the section. */
6086 imm->X_op = O_absent;
6087 offset->X_op = O_symbol;
6088 offset->X_add_symbol = symbol_temp_new_now ();
6089 offset->X_add_number = 0;
6091 /* Put the floating point number into the section. */
6092 p = frag_more (length);
6093 memcpy (p, data, length);
6095 /* Switch back to the original section. */
6096 subseg_set (seg, subseg);
6100 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6104 match_vu0_suffix_operand (struct mips_arg_info *arg,
6105 const struct mips_operand *operand,
6106 bfd_boolean match_p)
6110 /* The operand can be an XYZW mask or a single 2-bit channel index
6111 (with X being 0). */
6112 gas_assert (operand->size == 2 || operand->size == 4);
6114 /* The suffix can be omitted when it is already part of the opcode. */
6115 if (arg->token->type != OT_CHANNELS)
6118 uval = arg->token->u.channels;
6119 if (operand->size == 2)
6121 /* Check that a single bit is set and convert it into a 2-bit index. */
6122 if ((uval & -uval) != uval)
6124 uval = 4 - ffs (uval);
6127 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
6132 insn_insert_operand (arg->insn, operand, uval);
6136 /* Try to match a token from ARG against OPERAND. Consume the token
6137 and return true on success, otherwise return false. */
6140 match_operand (struct mips_arg_info *arg,
6141 const struct mips_operand *operand)
6143 switch (operand->type)
6146 return match_int_operand (arg, operand);
6149 return match_mapped_int_operand (arg, operand);
6152 return match_msb_operand (arg, operand);
6155 case OP_OPTIONAL_REG:
6156 return match_reg_operand (arg, operand);
6159 return match_reg_pair_operand (arg, operand);
6162 return match_pcrel_operand (arg);
6165 return match_perf_reg_operand (arg, operand);
6167 case OP_ADDIUSP_INT:
6168 return match_addiusp_operand (arg, operand);
6170 case OP_CLO_CLZ_DEST:
6171 return match_clo_clz_dest_operand (arg, operand);
6173 case OP_LWM_SWM_LIST:
6174 return match_lwm_swm_list_operand (arg, operand);
6176 case OP_ENTRY_EXIT_LIST:
6177 return match_entry_exit_operand (arg, operand);
6179 case OP_SAVE_RESTORE_LIST:
6180 return match_save_restore_list_operand (arg);
6182 case OP_MDMX_IMM_REG:
6183 return match_mdmx_imm_reg_operand (arg, operand);
6185 case OP_REPEAT_DEST_REG:
6186 return match_tied_reg_operand (arg, arg->dest_regno);
6188 case OP_REPEAT_PREV_REG:
6189 return match_tied_reg_operand (arg, arg->last_regno);
6192 return match_pc_operand (arg);
6195 return match_reg28_operand (arg);
6198 return match_vu0_suffix_operand (arg, operand, FALSE);
6200 case OP_VU0_MATCH_SUFFIX:
6201 return match_vu0_suffix_operand (arg, operand, TRUE);
6204 return match_imm_index_operand (arg, operand);
6207 return match_reg_index_operand (arg, operand);
6210 return match_same_rs_rt_operand (arg, operand);
6213 return match_check_prev_operand (arg, operand);
6215 case OP_NON_ZERO_REG:
6216 return match_non_zero_reg_operand (arg, operand);
6221 /* ARG is the state after successfully matching an instruction.
6222 Issue any queued-up warnings. */
6225 check_completed_insn (struct mips_arg_info *arg)
6230 as_warn (_("used $at without \".set noat\""));
6232 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6236 /* Return true if modifying general-purpose register REG needs a delay. */
6239 reg_needs_delay (unsigned int reg)
6241 unsigned long prev_pinfo;
6243 prev_pinfo = history[0].insn_mo->pinfo;
6244 if (!mips_opts.noreorder
6245 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6246 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6247 && (gpr_write_mask (&history[0]) & (1 << reg)))
6253 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6254 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6255 by VR4120 errata. */
6258 classify_vr4120_insn (const char *name)
6260 if (strncmp (name, "macc", 4) == 0)
6261 return FIX_VR4120_MACC;
6262 if (strncmp (name, "dmacc", 5) == 0)
6263 return FIX_VR4120_DMACC;
6264 if (strncmp (name, "mult", 4) == 0)
6265 return FIX_VR4120_MULT;
6266 if (strncmp (name, "dmult", 5) == 0)
6267 return FIX_VR4120_DMULT;
6268 if (strstr (name, "div"))
6269 return FIX_VR4120_DIV;
6270 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6271 return FIX_VR4120_MTHILO;
6272 return NUM_FIX_VR4120_CLASSES;
6275 #define INSN_ERET 0x42000018
6276 #define INSN_DERET 0x4200001f
6277 #define INSN_DMULT 0x1c
6278 #define INSN_DMULTU 0x1d
6280 /* Return the number of instructions that must separate INSN1 and INSN2,
6281 where INSN1 is the earlier instruction. Return the worst-case value
6282 for any INSN2 if INSN2 is null. */
6285 insns_between (const struct mips_cl_insn *insn1,
6286 const struct mips_cl_insn *insn2)
6288 unsigned long pinfo1, pinfo2;
6291 /* If INFO2 is null, pessimistically assume that all flags are set for
6292 the second instruction. */
6293 pinfo1 = insn1->insn_mo->pinfo;
6294 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6296 /* For most targets, write-after-read dependencies on the HI and LO
6297 registers must be separated by at least two instructions. */
6298 if (!hilo_interlocks)
6300 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6302 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6306 /* If we're working around r7000 errata, there must be two instructions
6307 between an mfhi or mflo and any instruction that uses the result. */
6308 if (mips_7000_hilo_fix
6309 && !mips_opts.micromips
6310 && MF_HILO_INSN (pinfo1)
6311 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6314 /* If we're working around 24K errata, one instruction is required
6315 if an ERET or DERET is followed by a branch instruction. */
6316 if (mips_fix_24k && !mips_opts.micromips)
6318 if (insn1->insn_opcode == INSN_ERET
6319 || insn1->insn_opcode == INSN_DERET)
6322 || insn2->insn_opcode == INSN_ERET
6323 || insn2->insn_opcode == INSN_DERET
6324 || delayed_branch_p (insn2))
6329 /* If we're working around PMC RM7000 errata, there must be three
6330 nops between a dmult and a load instruction. */
6331 if (mips_fix_rm7000 && !mips_opts.micromips)
6333 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6334 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6336 if (pinfo2 & INSN_LOAD_MEMORY)
6341 /* If working around VR4120 errata, check for combinations that need
6342 a single intervening instruction. */
6343 if (mips_fix_vr4120 && !mips_opts.micromips)
6345 unsigned int class1, class2;
6347 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6348 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6352 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6353 if (vr4120_conflicts[class1] & (1 << class2))
6358 if (!HAVE_CODE_COMPRESSION)
6360 /* Check for GPR or coprocessor load delays. All such delays
6361 are on the RT register. */
6362 /* Itbl support may require additional care here. */
6363 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6364 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6366 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6370 /* Check for generic coprocessor hazards.
6372 This case is not handled very well. There is no special
6373 knowledge of CP0 handling, and the coprocessors other than
6374 the floating point unit are not distinguished at all. */
6375 /* Itbl support may require additional care here. FIXME!
6376 Need to modify this to include knowledge about
6377 user specified delays! */
6378 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6379 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6381 /* Handle cases where INSN1 writes to a known general coprocessor
6382 register. There must be a one instruction delay before INSN2
6383 if INSN2 reads that register, otherwise no delay is needed. */
6384 mask = fpr_write_mask (insn1);
6387 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6392 /* Read-after-write dependencies on the control registers
6393 require a two-instruction gap. */
6394 if ((pinfo1 & INSN_WRITE_COND_CODE)
6395 && (pinfo2 & INSN_READ_COND_CODE))
6398 /* We don't know exactly what INSN1 does. If INSN2 is
6399 also a coprocessor instruction, assume there must be
6400 a one instruction gap. */
6401 if (pinfo2 & INSN_COP)
6406 /* Check for read-after-write dependencies on the coprocessor
6407 control registers in cases where INSN1 does not need a general
6408 coprocessor delay. This means that INSN1 is a floating point
6409 comparison instruction. */
6410 /* Itbl support may require additional care here. */
6411 else if (!cop_interlocks
6412 && (pinfo1 & INSN_WRITE_COND_CODE)
6413 && (pinfo2 & INSN_READ_COND_CODE))
6417 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6418 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6420 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6421 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6422 || (insn2 && delayed_branch_p (insn2))))
6428 /* Return the number of nops that would be needed to work around the
6429 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6430 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6431 that are contained within the first IGNORE instructions of HIST. */
6434 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6435 const struct mips_cl_insn *insn)
6440 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6441 are not affected by the errata. */
6443 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6444 || strcmp (insn->insn_mo->name, "mtlo") == 0
6445 || strcmp (insn->insn_mo->name, "mthi") == 0))
6448 /* Search for the first MFLO or MFHI. */
6449 for (i = 0; i < MAX_VR4130_NOPS; i++)
6450 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6452 /* Extract the destination register. */
6453 mask = gpr_write_mask (&hist[i]);
6455 /* No nops are needed if INSN reads that register. */
6456 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6459 /* ...or if any of the intervening instructions do. */
6460 for (j = 0; j < i; j++)
6461 if (gpr_read_mask (&hist[j]) & mask)
6465 return MAX_VR4130_NOPS - i;
6470 #define BASE_REG_EQ(INSN1, INSN2) \
6471 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6472 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6474 /* Return the minimum alignment for this store instruction. */
6477 fix_24k_align_to (const struct mips_opcode *mo)
6479 if (strcmp (mo->name, "sh") == 0)
6482 if (strcmp (mo->name, "swc1") == 0
6483 || strcmp (mo->name, "swc2") == 0
6484 || strcmp (mo->name, "sw") == 0
6485 || strcmp (mo->name, "sc") == 0
6486 || strcmp (mo->name, "s.s") == 0)
6489 if (strcmp (mo->name, "sdc1") == 0
6490 || strcmp (mo->name, "sdc2") == 0
6491 || strcmp (mo->name, "s.d") == 0)
6498 struct fix_24k_store_info
6500 /* Immediate offset, if any, for this store instruction. */
6502 /* Alignment required by this store instruction. */
6504 /* True for register offsets. */
6505 int register_offset;
6508 /* Comparison function used by qsort. */
6511 fix_24k_sort (const void *a, const void *b)
6513 const struct fix_24k_store_info *pos1 = a;
6514 const struct fix_24k_store_info *pos2 = b;
6516 return (pos1->off - pos2->off);
6519 /* INSN is a store instruction. Try to record the store information
6520 in STINFO. Return false if the information isn't known. */
6523 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6524 const struct mips_cl_insn *insn)
6526 /* The instruction must have a known offset. */
6527 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6530 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6531 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6535 /* Return the number of nops that would be needed to work around the 24k
6536 "lost data on stores during refill" errata if instruction INSN
6537 immediately followed the 2 instructions described by HIST.
6538 Ignore hazards that are contained within the first IGNORE
6539 instructions of HIST.
6541 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6542 for the data cache refills and store data. The following describes
6543 the scenario where the store data could be lost.
6545 * A data cache miss, due to either a load or a store, causing fill
6546 data to be supplied by the memory subsystem
6547 * The first three doublewords of fill data are returned and written
6549 * A sequence of four stores occurs in consecutive cycles around the
6550 final doubleword of the fill:
6554 * Zero, One or more instructions
6557 The four stores A-D must be to different doublewords of the line that
6558 is being filled. The fourth instruction in the sequence above permits
6559 the fill of the final doubleword to be transferred from the FSB into
6560 the cache. In the sequence above, the stores may be either integer
6561 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6562 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6563 different doublewords on the line. If the floating point unit is
6564 running in 1:2 mode, it is not possible to create the sequence above
6565 using only floating point store instructions.
6567 In this case, the cache line being filled is incorrectly marked
6568 invalid, thereby losing the data from any store to the line that
6569 occurs between the original miss and the completion of the five
6570 cycle sequence shown above.
6572 The workarounds are:
6574 * Run the data cache in write-through mode.
6575 * Insert a non-store instruction between
6576 Store A and Store B or Store B and Store C. */
6579 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6580 const struct mips_cl_insn *insn)
6582 struct fix_24k_store_info pos[3];
6583 int align, i, base_offset;
6588 /* If the previous instruction wasn't a store, there's nothing to
6590 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6593 /* If the instructions after the previous one are unknown, we have
6594 to assume the worst. */
6598 /* Check whether we are dealing with three consecutive stores. */
6599 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6600 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6603 /* If we don't know the relationship between the store addresses,
6604 assume the worst. */
6605 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6606 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6609 if (!fix_24k_record_store_info (&pos[0], insn)
6610 || !fix_24k_record_store_info (&pos[1], &hist[0])
6611 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6614 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6616 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6617 X bytes and such that the base register + X is known to be aligned
6620 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6624 align = pos[0].align_to;
6625 base_offset = pos[0].off;
6626 for (i = 1; i < 3; i++)
6627 if (align < pos[i].align_to)
6629 align = pos[i].align_to;
6630 base_offset = pos[i].off;
6632 for (i = 0; i < 3; i++)
6633 pos[i].off -= base_offset;
6636 pos[0].off &= ~align + 1;
6637 pos[1].off &= ~align + 1;
6638 pos[2].off &= ~align + 1;
6640 /* If any two stores write to the same chunk, they also write to the
6641 same doubleword. The offsets are still sorted at this point. */
6642 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6645 /* A range of at least 9 bytes is needed for the stores to be in
6646 non-overlapping doublewords. */
6647 if (pos[2].off - pos[0].off <= 8)
6650 if (pos[2].off - pos[1].off >= 24
6651 || pos[1].off - pos[0].off >= 24
6652 || pos[2].off - pos[0].off >= 32)
6658 /* Return the number of nops that would be needed if instruction INSN
6659 immediately followed the MAX_NOPS instructions given by HIST,
6660 where HIST[0] is the most recent instruction. Ignore hazards
6661 between INSN and the first IGNORE instructions in HIST.
6663 If INSN is null, return the worse-case number of nops for any
6667 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6668 const struct mips_cl_insn *insn)
6670 int i, nops, tmp_nops;
6673 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6675 tmp_nops = insns_between (hist + i, insn) - i;
6676 if (tmp_nops > nops)
6680 if (mips_fix_vr4130 && !mips_opts.micromips)
6682 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6683 if (tmp_nops > nops)
6687 if (mips_fix_24k && !mips_opts.micromips)
6689 tmp_nops = nops_for_24k (ignore, hist, insn);
6690 if (tmp_nops > nops)
6697 /* The variable arguments provide NUM_INSNS extra instructions that
6698 might be added to HIST. Return the largest number of nops that
6699 would be needed after the extended sequence, ignoring hazards
6700 in the first IGNORE instructions. */
6703 nops_for_sequence (int num_insns, int ignore,
6704 const struct mips_cl_insn *hist, ...)
6707 struct mips_cl_insn buffer[MAX_NOPS];
6708 struct mips_cl_insn *cursor;
6711 va_start (args, hist);
6712 cursor = buffer + num_insns;
6713 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6714 while (cursor > buffer)
6715 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6717 nops = nops_for_insn (ignore, buffer, NULL);
6722 /* Like nops_for_insn, but if INSN is a branch, take into account the
6723 worst-case delay for the branch target. */
6726 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6727 const struct mips_cl_insn *insn)
6731 nops = nops_for_insn (ignore, hist, insn);
6732 if (delayed_branch_p (insn))
6734 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6735 hist, insn, get_delay_slot_nop (insn));
6736 if (tmp_nops > nops)
6739 else if (compact_branch_p (insn))
6741 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6742 if (tmp_nops > nops)
6748 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6751 fix_loongson2f_nop (struct mips_cl_insn * ip)
6753 gas_assert (!HAVE_CODE_COMPRESSION);
6754 if (strcmp (ip->insn_mo->name, "nop") == 0)
6755 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6758 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6759 jr target pc &= 'hffff_ffff_cfff_ffff. */
6762 fix_loongson2f_jump (struct mips_cl_insn * ip)
6764 gas_assert (!HAVE_CODE_COMPRESSION);
6765 if (strcmp (ip->insn_mo->name, "j") == 0
6766 || strcmp (ip->insn_mo->name, "jr") == 0
6767 || strcmp (ip->insn_mo->name, "jalr") == 0)
6775 sreg = EXTRACT_OPERAND (0, RS, *ip);
6776 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6779 ep.X_op = O_constant;
6780 ep.X_add_number = 0xcfff0000;
6781 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6782 ep.X_add_number = 0xffff;
6783 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6784 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6789 fix_loongson2f (struct mips_cl_insn * ip)
6791 if (mips_fix_loongson2f_nop)
6792 fix_loongson2f_nop (ip);
6794 if (mips_fix_loongson2f_jump)
6795 fix_loongson2f_jump (ip);
6798 /* IP is a branch that has a delay slot, and we need to fill it
6799 automatically. Return true if we can do that by swapping IP
6800 with the previous instruction.
6801 ADDRESS_EXPR is an operand of the instruction to be used with
6805 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6806 bfd_reloc_code_real_type *reloc_type)
6808 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6809 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6810 unsigned int fpr_read, prev_fpr_write;
6812 /* -O2 and above is required for this optimization. */
6813 if (mips_optimize < 2)
6816 /* If we have seen .set volatile or .set nomove, don't optimize. */
6817 if (mips_opts.nomove)
6820 /* We can't swap if the previous instruction's position is fixed. */
6821 if (history[0].fixed_p)
6824 /* If the previous previous insn was in a .set noreorder, we can't
6825 swap. Actually, the MIPS assembler will swap in this situation.
6826 However, gcc configured -with-gnu-as will generate code like
6834 in which we can not swap the bne and INSN. If gcc is not configured
6835 -with-gnu-as, it does not output the .set pseudo-ops. */
6836 if (history[1].noreorder_p)
6839 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6840 This means that the previous instruction was a 4-byte one anyhow. */
6841 if (mips_opts.mips16 && history[0].fixp[0])
6844 /* If the branch is itself the target of a branch, we can not swap.
6845 We cheat on this; all we check for is whether there is a label on
6846 this instruction. If there are any branches to anything other than
6847 a label, users must use .set noreorder. */
6848 if (seg_info (now_seg)->label_list)
6851 /* If the previous instruction is in a variant frag other than this
6852 branch's one, we cannot do the swap. This does not apply to
6853 MIPS16 code, which uses variant frags for different purposes. */
6854 if (!mips_opts.mips16
6856 && history[0].frag->fr_type == rs_machine_dependent)
6859 /* We do not swap with instructions that cannot architecturally
6860 be placed in a branch delay slot, such as SYNC or ERET. We
6861 also refrain from swapping with a trap instruction, since it
6862 complicates trap handlers to have the trap instruction be in
6864 prev_pinfo = history[0].insn_mo->pinfo;
6865 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6868 /* Check for conflicts between the branch and the instructions
6869 before the candidate delay slot. */
6870 if (nops_for_insn (0, history + 1, ip) > 0)
6873 /* Check for conflicts between the swapped sequence and the
6874 target of the branch. */
6875 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6878 /* If the branch reads a register that the previous
6879 instruction sets, we can not swap. */
6880 gpr_read = gpr_read_mask (ip);
6881 prev_gpr_write = gpr_write_mask (&history[0]);
6882 if (gpr_read & prev_gpr_write)
6885 fpr_read = fpr_read_mask (ip);
6886 prev_fpr_write = fpr_write_mask (&history[0]);
6887 if (fpr_read & prev_fpr_write)
6890 /* If the branch writes a register that the previous
6891 instruction sets, we can not swap. */
6892 gpr_write = gpr_write_mask (ip);
6893 if (gpr_write & prev_gpr_write)
6896 /* If the branch writes a register that the previous
6897 instruction reads, we can not swap. */
6898 prev_gpr_read = gpr_read_mask (&history[0]);
6899 if (gpr_write & prev_gpr_read)
6902 /* If one instruction sets a condition code and the
6903 other one uses a condition code, we can not swap. */
6904 pinfo = ip->insn_mo->pinfo;
6905 if ((pinfo & INSN_READ_COND_CODE)
6906 && (prev_pinfo & INSN_WRITE_COND_CODE))
6908 if ((pinfo & INSN_WRITE_COND_CODE)
6909 && (prev_pinfo & INSN_READ_COND_CODE))
6912 /* If the previous instruction uses the PC, we can not swap. */
6913 prev_pinfo2 = history[0].insn_mo->pinfo2;
6914 if (prev_pinfo2 & INSN2_READ_PC)
6917 /* If the previous instruction has an incorrect size for a fixed
6918 branch delay slot in microMIPS mode, we cannot swap. */
6919 pinfo2 = ip->insn_mo->pinfo2;
6920 if (mips_opts.micromips
6921 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6922 && insn_length (history) != 2)
6924 if (mips_opts.micromips
6925 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6926 && insn_length (history) != 4)
6929 /* On R5900 short loops need to be fixed by inserting a nop in
6930 the branch delay slots.
6931 A short loop can be terminated too early. */
6932 if (mips_opts.arch == CPU_R5900
6933 /* Check if instruction has a parameter, ignore "j $31". */
6934 && (address_expr != NULL)
6935 /* Parameter must be 16 bit. */
6936 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6937 /* Branch to same segment. */
6938 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6939 /* Branch to same code fragment. */
6940 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6941 /* Can only calculate branch offset if value is known. */
6942 && symbol_constant_p (address_expr->X_add_symbol)
6943 /* Check if branch is really conditional. */
6944 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6945 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6946 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6949 /* Check if loop is shorter than 6 instructions including
6950 branch and delay slot. */
6951 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
6958 /* When the loop includes branches or jumps,
6959 it is not a short loop. */
6960 for (i = 0; i < (distance / 4); i++)
6962 if ((history[i].cleared_p)
6963 || delayed_branch_p (&history[i]))
6971 /* Insert nop after branch to fix short loop. */
6980 /* Decide how we should add IP to the instruction stream.
6981 ADDRESS_EXPR is an operand of the instruction to be used with
6984 static enum append_method
6985 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6986 bfd_reloc_code_real_type *reloc_type)
6988 /* The relaxed version of a macro sequence must be inherently
6990 if (mips_relax.sequence == 2)
6993 /* We must not dabble with instructions in a ".set noreorder" block. */
6994 if (mips_opts.noreorder)
6997 /* Otherwise, it's our responsibility to fill branch delay slots. */
6998 if (delayed_branch_p (ip))
7000 if (!branch_likely_p (ip)
7001 && can_swap_branch_p (ip, address_expr, reloc_type))
7004 if (mips_opts.mips16
7005 && ISA_SUPPORTS_MIPS16E
7006 && gpr_read_mask (ip) != 0)
7007 return APPEND_ADD_COMPACT;
7009 if (mips_opts.micromips
7010 && ((ip->insn_opcode & 0xffe0) == 0x4580
7011 || (!forced_insn_length
7012 && ((ip->insn_opcode & 0xfc00) == 0xcc00
7013 || (ip->insn_opcode & 0xdc00) == 0x8c00))
7014 || (ip->insn_opcode & 0xdfe00000) == 0x94000000
7015 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
7016 return APPEND_ADD_COMPACT;
7018 return APPEND_ADD_WITH_NOP;
7024 /* IP is an instruction whose opcode we have just changed, END points
7025 to the end of the opcode table processed. Point IP->insn_mo to the
7026 new opcode's definition. */
7029 find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
7031 const struct mips_opcode *mo;
7033 for (mo = ip->insn_mo; mo < end; mo++)
7034 if (mo->pinfo != INSN_MACRO
7035 && (ip->insn_opcode & mo->mask) == mo->match)
7043 /* IP is a MIPS16 instruction whose opcode we have just changed.
7044 Point IP->insn_mo to the new opcode's definition. */
7047 find_altered_mips16_opcode (struct mips_cl_insn *ip)
7049 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
7052 /* IP is a microMIPS instruction whose opcode we have just changed.
7053 Point IP->insn_mo to the new opcode's definition. */
7056 find_altered_micromips_opcode (struct mips_cl_insn *ip)
7058 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]);
7061 /* For microMIPS macros, we need to generate a local number label
7062 as the target of branches. */
7063 #define MICROMIPS_LABEL_CHAR '\037'
7064 static unsigned long micromips_target_label;
7065 static char micromips_target_name[32];
7068 micromips_label_name (void)
7070 char *p = micromips_target_name;
7071 char symbol_name_temporary[24];
7079 l = micromips_target_label;
7080 #ifdef LOCAL_LABEL_PREFIX
7081 *p++ = LOCAL_LABEL_PREFIX;
7084 *p++ = MICROMIPS_LABEL_CHAR;
7087 symbol_name_temporary[i++] = l % 10 + '0';
7092 *p++ = symbol_name_temporary[--i];
7095 return micromips_target_name;
7099 micromips_label_expr (expressionS *label_expr)
7101 label_expr->X_op = O_symbol;
7102 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
7103 label_expr->X_add_number = 0;
7107 micromips_label_inc (void)
7109 micromips_target_label++;
7110 *micromips_target_name = '\0';
7114 micromips_add_label (void)
7118 s = colon (micromips_label_name ());
7119 micromips_label_inc ();
7120 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
7123 /* If assembling microMIPS code, then return the microMIPS reloc
7124 corresponding to the requested one if any. Otherwise return
7125 the reloc unchanged. */
7127 static bfd_reloc_code_real_type
7128 micromips_map_reloc (bfd_reloc_code_real_type reloc)
7130 static const bfd_reloc_code_real_type relocs[][2] =
7132 /* Keep sorted incrementally by the left-hand key. */
7133 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
7134 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
7135 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
7136 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
7137 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
7138 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
7139 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
7140 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
7141 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
7142 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
7143 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
7144 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
7145 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
7146 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
7147 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
7148 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
7149 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
7150 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
7151 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
7152 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
7153 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
7154 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
7155 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
7156 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
7157 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
7158 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
7159 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
7161 bfd_reloc_code_real_type r;
7164 if (!mips_opts.micromips)
7166 for (i = 0; i < ARRAY_SIZE (relocs); i++)
7172 return relocs[i][1];
7177 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7178 Return true on success, storing the resolved value in RESULT. */
7181 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
7186 case BFD_RELOC_MIPS_HIGHEST:
7187 case BFD_RELOC_MICROMIPS_HIGHEST:
7188 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
7191 case BFD_RELOC_MIPS_HIGHER:
7192 case BFD_RELOC_MICROMIPS_HIGHER:
7193 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
7196 case BFD_RELOC_HI16_S:
7197 case BFD_RELOC_HI16_S_PCREL:
7198 case BFD_RELOC_MICROMIPS_HI16_S:
7199 case BFD_RELOC_MIPS16_HI16_S:
7200 *result = ((operand + 0x8000) >> 16) & 0xffff;
7203 case BFD_RELOC_HI16:
7204 case BFD_RELOC_MICROMIPS_HI16:
7205 case BFD_RELOC_MIPS16_HI16:
7206 *result = (operand >> 16) & 0xffff;
7209 case BFD_RELOC_LO16:
7210 case BFD_RELOC_LO16_PCREL:
7211 case BFD_RELOC_MICROMIPS_LO16:
7212 case BFD_RELOC_MIPS16_LO16:
7213 *result = operand & 0xffff;
7216 case BFD_RELOC_UNUSED:
7225 /* Output an instruction. IP is the instruction information.
7226 ADDRESS_EXPR is an operand of the instruction to be used with
7227 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7228 a macro expansion. */
7231 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7232 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7234 unsigned long prev_pinfo2, pinfo;
7235 bfd_boolean relaxed_branch = FALSE;
7236 enum append_method method;
7237 bfd_boolean relax32;
7240 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7241 fix_loongson2f (ip);
7243 file_ase_mips16 |= mips_opts.mips16;
7244 file_ase_micromips |= mips_opts.micromips;
7246 prev_pinfo2 = history[0].insn_mo->pinfo2;
7247 pinfo = ip->insn_mo->pinfo;
7249 /* Don't raise alarm about `nods' frags as they'll fill in the right
7250 kind of nop in relaxation if required. */
7251 if (mips_opts.micromips
7253 && !(history[0].frag
7254 && history[0].frag->fr_type == rs_machine_dependent
7255 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
7256 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
7257 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7258 && micromips_insn_length (ip->insn_mo) != 2)
7259 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7260 && micromips_insn_length (ip->insn_mo) != 4)))
7261 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7262 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7264 if (address_expr == NULL)
7266 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7267 && reloc_type[1] == BFD_RELOC_UNUSED
7268 && reloc_type[2] == BFD_RELOC_UNUSED
7269 && address_expr->X_op == O_constant)
7271 switch (*reloc_type)
7273 case BFD_RELOC_MIPS_JMP:
7277 /* Shift is 2, unusually, for microMIPS JALX. */
7278 shift = (mips_opts.micromips
7279 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7280 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7281 as_bad (_("jump to misaligned address (0x%lx)"),
7282 (unsigned long) address_expr->X_add_number);
7283 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7289 case BFD_RELOC_MIPS16_JMP:
7290 if ((address_expr->X_add_number & 3) != 0)
7291 as_bad (_("jump to misaligned address (0x%lx)"),
7292 (unsigned long) address_expr->X_add_number);
7294 (((address_expr->X_add_number & 0x7c0000) << 3)
7295 | ((address_expr->X_add_number & 0xf800000) >> 7)
7296 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7300 case BFD_RELOC_16_PCREL_S2:
7304 shift = mips_opts.micromips ? 1 : 2;
7305 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7306 as_bad (_("branch to misaligned address (0x%lx)"),
7307 (unsigned long) address_expr->X_add_number);
7308 if (!mips_relax_branch)
7310 if ((address_expr->X_add_number + (1 << (shift + 15)))
7311 & ~((1 << (shift + 16)) - 1))
7312 as_bad (_("branch address range overflow (0x%lx)"),
7313 (unsigned long) address_expr->X_add_number);
7314 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7320 case BFD_RELOC_MIPS_21_PCREL_S2:
7325 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7326 as_bad (_("branch to misaligned address (0x%lx)"),
7327 (unsigned long) address_expr->X_add_number);
7328 if ((address_expr->X_add_number + (1 << (shift + 20)))
7329 & ~((1 << (shift + 21)) - 1))
7330 as_bad (_("branch address range overflow (0x%lx)"),
7331 (unsigned long) address_expr->X_add_number);
7332 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7337 case BFD_RELOC_MIPS_26_PCREL_S2:
7342 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7343 as_bad (_("branch to misaligned address (0x%lx)"),
7344 (unsigned long) address_expr->X_add_number);
7345 if ((address_expr->X_add_number + (1 << (shift + 25)))
7346 & ~((1 << (shift + 26)) - 1))
7347 as_bad (_("branch address range overflow (0x%lx)"),
7348 (unsigned long) address_expr->X_add_number);
7349 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7358 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7361 ip->insn_opcode |= value & 0xffff;
7369 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7371 /* There are a lot of optimizations we could do that we don't.
7372 In particular, we do not, in general, reorder instructions.
7373 If you use gcc with optimization, it will reorder
7374 instructions and generally do much more optimization then we
7375 do here; repeating all that work in the assembler would only
7376 benefit hand written assembly code, and does not seem worth
7378 int nops = (mips_optimize == 0
7379 ? nops_for_insn (0, history, NULL)
7380 : nops_for_insn_or_target (0, history, ip));
7384 unsigned long old_frag_offset;
7387 old_frag = frag_now;
7388 old_frag_offset = frag_now_fix ();
7390 for (i = 0; i < nops; i++)
7391 add_fixed_insn (NOP_INSN);
7392 insert_into_history (0, nops, NOP_INSN);
7396 listing_prev_line ();
7397 /* We may be at the start of a variant frag. In case we
7398 are, make sure there is enough space for the frag
7399 after the frags created by listing_prev_line. The
7400 argument to frag_grow here must be at least as large
7401 as the argument to all other calls to frag_grow in
7402 this file. We don't have to worry about being in the
7403 middle of a variant frag, because the variants insert
7404 all needed nop instructions themselves. */
7408 mips_move_text_labels ();
7410 #ifndef NO_ECOFF_DEBUGGING
7411 if (ECOFF_DEBUGGING)
7412 ecoff_fix_loc (old_frag, old_frag_offset);
7416 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7420 /* Work out how many nops in prev_nop_frag are needed by IP,
7421 ignoring hazards generated by the first prev_nop_frag_since
7423 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7424 gas_assert (nops <= prev_nop_frag_holds);
7426 /* Enforce NOPS as a minimum. */
7427 if (nops > prev_nop_frag_required)
7428 prev_nop_frag_required = nops;
7430 if (prev_nop_frag_holds == prev_nop_frag_required)
7432 /* Settle for the current number of nops. Update the history
7433 accordingly (for the benefit of any future .set reorder code). */
7434 prev_nop_frag = NULL;
7435 insert_into_history (prev_nop_frag_since,
7436 prev_nop_frag_holds, NOP_INSN);
7440 /* Allow this instruction to replace one of the nops that was
7441 tentatively added to prev_nop_frag. */
7442 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7443 prev_nop_frag_holds--;
7444 prev_nop_frag_since++;
7448 method = get_append_method (ip, address_expr, reloc_type);
7449 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7451 dwarf2_emit_insn (0);
7452 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7453 so "move" the instruction address accordingly.
7455 Also, it doesn't seem appropriate for the assembler to reorder .loc
7456 entries. If this instruction is a branch that we are going to swap
7457 with the previous instruction, the two instructions should be
7458 treated as a unit, and the debug information for both instructions
7459 should refer to the start of the branch sequence. Using the
7460 current position is certainly wrong when swapping a 32-bit branch
7461 and a 16-bit delay slot, since the current position would then be
7462 in the middle of a branch. */
7463 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7465 relax32 = (mips_relax_branch
7466 /* Don't try branch relaxation within .set nomacro, or within
7467 .set noat if we use $at for PIC computations. If it turns
7468 out that the branch was out-of-range, we'll get an error. */
7469 && !mips_opts.warn_about_macros
7470 && (mips_opts.at || mips_pic == NO_PIC)
7471 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7472 as they have no complementing branches. */
7473 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7475 if (!HAVE_CODE_COMPRESSION
7478 && *reloc_type == BFD_RELOC_16_PCREL_S2
7479 && delayed_branch_p (ip))
7481 relaxed_branch = TRUE;
7482 add_relaxed_insn (ip, (relaxed_branch_length
7484 uncond_branch_p (ip) ? -1
7485 : branch_likely_p (ip) ? 1
7488 (AT, mips_pic != NO_PIC,
7489 uncond_branch_p (ip),
7490 branch_likely_p (ip),
7491 pinfo & INSN_WRITE_GPR_31,
7493 address_expr->X_add_symbol,
7494 address_expr->X_add_number);
7495 *reloc_type = BFD_RELOC_UNUSED;
7497 else if (mips_opts.micromips
7499 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7500 || *reloc_type > BFD_RELOC_UNUSED)
7501 && (delayed_branch_p (ip) || compact_branch_p (ip))
7502 /* Don't try branch relaxation when users specify
7503 16-bit/32-bit instructions. */
7504 && !forced_insn_length)
7506 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
7507 && *reloc_type > BFD_RELOC_UNUSED);
7508 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7509 int uncond = uncond_branch_p (ip) ? -1 : 0;
7510 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
7511 int nods = method == APPEND_ADD_WITH_NOP;
7512 int al = pinfo & INSN_WRITE_GPR_31;
7513 int length32 = nods ? 8 : 4;
7515 gas_assert (address_expr != NULL);
7516 gas_assert (!mips_relax.sequence);
7518 relaxed_branch = TRUE;
7520 method = APPEND_ADD;
7522 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7523 add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
7524 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
7526 uncond, compact, al, nods,
7528 address_expr->X_add_symbol,
7529 address_expr->X_add_number);
7530 *reloc_type = BFD_RELOC_UNUSED;
7532 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7534 bfd_boolean require_unextended;
7535 bfd_boolean require_extended;
7539 if (forced_insn_length != 0)
7541 require_unextended = forced_insn_length == 2;
7542 require_extended = forced_insn_length == 4;
7546 require_unextended = (mips_opts.noautoextend
7547 && !mips_opcode_32bit_p (ip->insn_mo));
7548 require_extended = 0;
7551 /* We need to set up a variant frag. */
7552 gas_assert (address_expr != NULL);
7553 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7554 symbol created by `make_expr_symbol' may not get a necessary
7555 external relocation produced. */
7556 if (address_expr->X_op == O_symbol)
7558 symbol = address_expr->X_add_symbol;
7559 offset = address_expr->X_add_number;
7563 symbol = make_expr_symbol (address_expr);
7564 symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP);
7567 add_relaxed_insn (ip, 12, 0,
7569 (*reloc_type - BFD_RELOC_UNUSED,
7570 mips_opts.ase & ASE_MIPS16E2,
7573 mips_opts.warn_about_macros,
7574 require_unextended, require_extended,
7575 delayed_branch_p (&history[0]),
7576 history[0].mips16_absolute_jump_p),
7579 else if (mips_opts.mips16 && insn_length (ip) == 2)
7581 if (!delayed_branch_p (ip))
7582 /* Make sure there is enough room to swap this instruction with
7583 a following jump instruction. */
7585 add_fixed_insn (ip);
7589 if (mips_opts.mips16
7590 && mips_opts.noreorder
7591 && delayed_branch_p (&history[0]))
7592 as_warn (_("extended instruction in delay slot"));
7594 if (mips_relax.sequence)
7596 /* If we've reached the end of this frag, turn it into a variant
7597 frag and record the information for the instructions we've
7599 if (frag_room () < 4)
7600 relax_close_frag ();
7601 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7604 if (mips_relax.sequence != 2)
7606 if (mips_macro_warning.first_insn_sizes[0] == 0)
7607 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7608 mips_macro_warning.sizes[0] += insn_length (ip);
7609 mips_macro_warning.insns[0]++;
7611 if (mips_relax.sequence != 1)
7613 if (mips_macro_warning.first_insn_sizes[1] == 0)
7614 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7615 mips_macro_warning.sizes[1] += insn_length (ip);
7616 mips_macro_warning.insns[1]++;
7619 if (mips_opts.mips16)
7622 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7624 add_fixed_insn (ip);
7627 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7629 bfd_reloc_code_real_type final_type[3];
7630 reloc_howto_type *howto0;
7631 reloc_howto_type *howto;
7634 /* Perform any necessary conversion to microMIPS relocations
7635 and find out how many relocations there actually are. */
7636 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7637 final_type[i] = micromips_map_reloc (reloc_type[i]);
7639 /* In a compound relocation, it is the final (outermost)
7640 operator that determines the relocated field. */
7641 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7646 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7647 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7648 bfd_get_reloc_size (howto),
7650 howto0 && howto0->pc_relative,
7652 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7653 ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC;
7655 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7656 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7657 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7659 /* These relocations can have an addend that won't fit in
7660 4 octets for 64bit assembly. */
7662 && ! howto->partial_inplace
7663 && (reloc_type[0] == BFD_RELOC_16
7664 || reloc_type[0] == BFD_RELOC_32
7665 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7666 || reloc_type[0] == BFD_RELOC_GPREL16
7667 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7668 || reloc_type[0] == BFD_RELOC_GPREL32
7669 || reloc_type[0] == BFD_RELOC_64
7670 || reloc_type[0] == BFD_RELOC_CTOR
7671 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7672 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7673 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7674 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7675 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7676 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7677 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7678 || hi16_reloc_p (reloc_type[0])
7679 || lo16_reloc_p (reloc_type[0])))
7680 ip->fixp[0]->fx_no_overflow = 1;
7682 /* These relocations can have an addend that won't fit in 2 octets. */
7683 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7684 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7685 ip->fixp[0]->fx_no_overflow = 1;
7687 if (mips_relax.sequence)
7689 if (mips_relax.first_fixup == 0)
7690 mips_relax.first_fixup = ip->fixp[0];
7692 else if (reloc_needs_lo_p (*reloc_type))
7694 struct mips_hi_fixup *hi_fixup;
7696 /* Reuse the last entry if it already has a matching %lo. */
7697 hi_fixup = mips_hi_fixup_list;
7699 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7701 hi_fixup = XNEW (struct mips_hi_fixup);
7702 hi_fixup->next = mips_hi_fixup_list;
7703 mips_hi_fixup_list = hi_fixup;
7705 hi_fixup->fixp = ip->fixp[0];
7706 hi_fixup->seg = now_seg;
7709 /* Add fixups for the second and third relocations, if given.
7710 Note that the ABI allows the second relocation to be
7711 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7712 moment we only use RSS_UNDEF, but we could add support
7713 for the others if it ever becomes necessary. */
7714 for (i = 1; i < 3; i++)
7715 if (reloc_type[i] != BFD_RELOC_UNUSED)
7717 ip->fixp[i] = fix_new (ip->frag, ip->where,
7718 ip->fixp[0]->fx_size, NULL, 0,
7719 FALSE, final_type[i]);
7721 /* Use fx_tcbit to mark compound relocs. */
7722 ip->fixp[0]->fx_tcbit = 1;
7723 ip->fixp[i]->fx_tcbit = 1;
7727 /* Update the register mask information. */
7728 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7729 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7734 insert_into_history (0, 1, ip);
7737 case APPEND_ADD_WITH_NOP:
7739 struct mips_cl_insn *nop;
7741 insert_into_history (0, 1, ip);
7742 nop = get_delay_slot_nop (ip);
7743 add_fixed_insn (nop);
7744 insert_into_history (0, 1, nop);
7745 if (mips_relax.sequence)
7746 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7750 case APPEND_ADD_COMPACT:
7751 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7752 if (mips_opts.mips16)
7754 ip->insn_opcode |= 0x0080;
7755 find_altered_mips16_opcode (ip);
7757 /* Convert microMIPS instructions. */
7758 else if (mips_opts.micromips)
7761 if ((ip->insn_opcode & 0xffe0) == 0x4580)
7762 ip->insn_opcode |= 0x0020;
7764 else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
7765 ip->insn_opcode = 0x40e00000;
7766 /* beqz16->beqzc, bnez16->bnezc */
7767 else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
7769 unsigned long regno;
7771 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
7772 regno &= MICROMIPSOP_MASK_MD;
7773 regno = micromips_to_32_reg_d_map[regno];
7774 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
7775 | (regno << MICROMIPSOP_SH_RS)
7776 | 0x40a00000) ^ 0x00400000;
7778 /* beqz->beqzc, bnez->bnezc */
7779 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
7780 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
7781 | ((ip->insn_opcode >> 7) & 0x00400000)
7782 | 0x40a00000) ^ 0x00400000;
7783 /* beq $0->beqzc, bne $0->bnezc */
7784 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
7785 ip->insn_opcode = (((ip->insn_opcode >>
7786 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
7787 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
7788 | ((ip->insn_opcode >> 7) & 0x00400000)
7789 | 0x40a00000) ^ 0x00400000;
7792 find_altered_micromips_opcode (ip);
7797 insert_into_history (0, 1, ip);
7802 struct mips_cl_insn delay = history[0];
7804 if (relaxed_branch || delay.frag != ip->frag)
7806 /* Add the delay slot instruction to the end of the
7807 current frag and shrink the fixed part of the
7808 original frag. If the branch occupies the tail of
7809 the latter, move it backwards to cover the gap. */
7810 delay.frag->fr_fix -= branch_disp;
7811 if (delay.frag == ip->frag)
7812 move_insn (ip, ip->frag, ip->where - branch_disp);
7813 add_fixed_insn (&delay);
7817 /* If this is not a relaxed branch and we are in the
7818 same frag, then just swap the instructions. */
7819 move_insn (ip, delay.frag, delay.where);
7820 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7824 insert_into_history (0, 1, &delay);
7829 /* If we have just completed an unconditional branch, clear the history. */
7830 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7831 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7835 mips_no_prev_insn ();
7837 for (i = 0; i < ARRAY_SIZE (history); i++)
7838 history[i].cleared_p = 1;
7841 /* We need to emit a label at the end of branch-likely macros. */
7842 if (emit_branch_likely_macro)
7844 emit_branch_likely_macro = FALSE;
7845 micromips_add_label ();
7848 /* We just output an insn, so the next one doesn't have a label. */
7849 mips_clear_insn_labels ();
7852 /* Forget that there was any previous instruction or label.
7853 When BRANCH is true, the branch history is also flushed. */
7856 mips_no_prev_insn (void)
7858 prev_nop_frag = NULL;
7859 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7860 mips_clear_insn_labels ();
7863 /* This function must be called before we emit something other than
7864 instructions. It is like mips_no_prev_insn except that it inserts
7865 any NOPS that might be needed by previous instructions. */
7868 mips_emit_delays (void)
7870 if (! mips_opts.noreorder)
7872 int nops = nops_for_insn (0, history, NULL);
7876 add_fixed_insn (NOP_INSN);
7877 mips_move_text_labels ();
7880 mips_no_prev_insn ();
7883 /* Start a (possibly nested) noreorder block. */
7886 start_noreorder (void)
7888 if (mips_opts.noreorder == 0)
7893 /* None of the instructions before the .set noreorder can be moved. */
7894 for (i = 0; i < ARRAY_SIZE (history); i++)
7895 history[i].fixed_p = 1;
7897 /* Insert any nops that might be needed between the .set noreorder
7898 block and the previous instructions. We will later remove any
7899 nops that turn out not to be needed. */
7900 nops = nops_for_insn (0, history, NULL);
7903 if (mips_optimize != 0)
7905 /* Record the frag which holds the nop instructions, so
7906 that we can remove them if we don't need them. */
7907 frag_grow (nops * NOP_INSN_SIZE);
7908 prev_nop_frag = frag_now;
7909 prev_nop_frag_holds = nops;
7910 prev_nop_frag_required = 0;
7911 prev_nop_frag_since = 0;
7914 for (; nops > 0; --nops)
7915 add_fixed_insn (NOP_INSN);
7917 /* Move on to a new frag, so that it is safe to simply
7918 decrease the size of prev_nop_frag. */
7919 frag_wane (frag_now);
7921 mips_move_text_labels ();
7923 mips_mark_labels ();
7924 mips_clear_insn_labels ();
7926 mips_opts.noreorder++;
7927 mips_any_noreorder = 1;
7930 /* End a nested noreorder block. */
7933 end_noreorder (void)
7935 mips_opts.noreorder--;
7936 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7938 /* Commit to inserting prev_nop_frag_required nops and go back to
7939 handling nop insertion the .set reorder way. */
7940 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7942 insert_into_history (prev_nop_frag_since,
7943 prev_nop_frag_required, NOP_INSN);
7944 prev_nop_frag = NULL;
7948 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7949 higher bits unset. */
7952 normalize_constant_expr (expressionS *ex)
7954 if (ex->X_op == O_constant
7955 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7956 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7960 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7961 all higher bits unset. */
7964 normalize_address_expr (expressionS *ex)
7966 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7967 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7968 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7969 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7973 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7974 Return true if the match was successful.
7976 OPCODE_EXTRA is a value that should be ORed into the opcode
7977 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7978 there are more alternatives after OPCODE and SOFT_MATCH is
7979 as for mips_arg_info. */
7982 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7983 struct mips_operand_token *tokens, unsigned int opcode_extra,
7984 bfd_boolean lax_match, bfd_boolean complete_p)
7987 struct mips_arg_info arg;
7988 const struct mips_operand *operand;
7991 imm_expr.X_op = O_absent;
7992 offset_expr.X_op = O_absent;
7993 offset_reloc[0] = BFD_RELOC_UNUSED;
7994 offset_reloc[1] = BFD_RELOC_UNUSED;
7995 offset_reloc[2] = BFD_RELOC_UNUSED;
7997 create_insn (insn, opcode);
7998 /* When no opcode suffix is specified, assume ".xyzw". */
7999 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
8000 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
8002 insn->insn_opcode |= opcode_extra;
8003 memset (&arg, 0, sizeof (arg));
8007 arg.last_regno = ILLEGAL_REG;
8008 arg.dest_regno = ILLEGAL_REG;
8009 arg.lax_match = lax_match;
8010 for (args = opcode->args;; ++args)
8012 if (arg.token->type == OT_END)
8014 /* Handle unary instructions in which only one operand is given.
8015 The source is then the same as the destination. */
8016 if (arg.opnum == 1 && *args == ',')
8018 operand = (mips_opts.micromips
8019 ? decode_micromips_operand (args + 1)
8020 : decode_mips_operand (args + 1));
8021 if (operand && mips_optional_operand_p (operand))
8029 /* Treat elided base registers as $0. */
8030 if (strcmp (args, "(b)") == 0)
8038 /* The register suffix is optional. */
8043 /* Fail the match if there were too few operands. */
8047 /* Successful match. */
8050 clear_insn_error ();
8051 if (arg.dest_regno == arg.last_regno
8052 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
8056 (0, _("source and destination must be different"));
8057 else if (arg.last_regno == 31)
8059 (0, _("a destination register must be supplied"));
8061 else if (arg.last_regno == 31
8062 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
8063 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
8064 set_insn_error (0, _("the source register must not be $31"));
8065 check_completed_insn (&arg);
8069 /* Fail the match if the line has too many operands. */
8073 /* Handle characters that need to match exactly. */
8074 if (*args == '(' || *args == ')' || *args == ',')
8076 if (match_char (&arg, *args))
8083 if (arg.token->type == OT_DOUBLE_CHAR
8084 && arg.token->u.ch == *args)
8092 /* Handle special macro operands. Work out the properties of
8101 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
8105 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
8114 *offset_reloc = BFD_RELOC_MIPS_JMP;
8118 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
8122 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
8128 if (!match_const_int (&arg, &imm_expr.X_add_number))
8130 imm_expr.X_op = O_constant;
8132 normalize_constant_expr (&imm_expr);
8136 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8138 /* Assume that the offset has been elided and that what
8139 we saw was a base register. The match will fail later
8140 if that assumption turns out to be wrong. */
8141 offset_expr.X_op = O_constant;
8142 offset_expr.X_add_number = 0;
8146 if (!match_expression (&arg, &offset_expr, offset_reloc))
8148 normalize_address_expr (&offset_expr);
8153 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8159 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8165 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8171 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8177 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8181 *offset_reloc = BFD_RELOC_MIPS_JMP;
8185 gas_assert (mips_opts.micromips);
8191 if (!forced_insn_length)
8192 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
8194 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
8196 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
8202 operand = (mips_opts.micromips
8203 ? decode_micromips_operand (args)
8204 : decode_mips_operand (args));
8208 /* Skip prefixes. */
8209 if (*args == '+' || *args == 'm' || *args == '-')
8212 if (mips_optional_operand_p (operand)
8214 && (arg.token[0].type != OT_REG
8215 || arg.token[1].type == OT_END))
8217 /* Assume that the register has been elided and is the
8218 same as the first operand. */
8223 if (!match_operand (&arg, operand))
8228 /* Like match_insn, but for MIPS16. */
8231 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8232 struct mips_operand_token *tokens)
8235 const struct mips_operand *operand;
8236 const struct mips_operand *ext_operand;
8237 bfd_boolean pcrel = FALSE;
8238 int required_insn_length;
8239 struct mips_arg_info arg;
8242 if (forced_insn_length)
8243 required_insn_length = forced_insn_length;
8244 else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode))
8245 required_insn_length = 2;
8247 required_insn_length = 0;
8249 create_insn (insn, opcode);
8250 imm_expr.X_op = O_absent;
8251 offset_expr.X_op = O_absent;
8252 offset_reloc[0] = BFD_RELOC_UNUSED;
8253 offset_reloc[1] = BFD_RELOC_UNUSED;
8254 offset_reloc[2] = BFD_RELOC_UNUSED;
8257 memset (&arg, 0, sizeof (arg));
8261 arg.last_regno = ILLEGAL_REG;
8262 arg.dest_regno = ILLEGAL_REG;
8264 for (args = opcode->args;; ++args)
8268 if (arg.token->type == OT_END)
8272 /* Handle unary instructions in which only one operand is given.
8273 The source is then the same as the destination. */
8274 if (arg.opnum == 1 && *args == ',')
8276 operand = decode_mips16_operand (args[1], FALSE);
8277 if (operand && mips_optional_operand_p (operand))
8285 /* Fail the match if there were too few operands. */
8289 /* Successful match. Stuff the immediate value in now, if
8291 clear_insn_error ();
8292 if (opcode->pinfo == INSN_MACRO)
8294 gas_assert (relax_char == 0 || relax_char == 'p');
8295 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8298 && offset_expr.X_op == O_constant
8300 && calculate_reloc (*offset_reloc,
8301 offset_expr.X_add_number,
8304 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8305 required_insn_length, &insn->insn_opcode);
8306 offset_expr.X_op = O_absent;
8307 *offset_reloc = BFD_RELOC_UNUSED;
8309 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8311 if (required_insn_length == 2)
8312 set_insn_error (0, _("invalid unextended operand value"));
8313 else if (!mips_opcode_32bit_p (opcode))
8315 forced_insn_length = 4;
8316 insn->insn_opcode |= MIPS16_EXTEND;
8319 else if (relax_char)
8320 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8322 check_completed_insn (&arg);
8326 /* Fail the match if the line has too many operands. */
8330 /* Handle characters that need to match exactly. */
8331 if (*args == '(' || *args == ')' || *args == ',')
8333 if (match_char (&arg, *args))
8353 if (!match_const_int (&arg, &imm_expr.X_add_number))
8355 imm_expr.X_op = O_constant;
8357 normalize_constant_expr (&imm_expr);
8362 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8366 operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode));
8370 if (operand->type == OP_PCREL)
8374 ext_operand = decode_mips16_operand (c, TRUE);
8375 if (operand != ext_operand)
8377 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8379 offset_expr.X_op = O_constant;
8380 offset_expr.X_add_number = 0;
8385 if (!match_expression (&arg, &offset_expr, offset_reloc))
8388 /* '8' is used for SLTI(U) and has traditionally not
8389 been allowed to take relocation operators. */
8390 if (offset_reloc[0] != BFD_RELOC_UNUSED
8391 && (ext_operand->size != 16 || c == '8'))
8393 match_not_constant (&arg);
8397 if (offset_expr.X_op == O_big)
8399 match_out_of_range (&arg);
8408 if (mips_optional_operand_p (operand)
8410 && (arg.token[0].type != OT_REG
8411 || arg.token[1].type == OT_END))
8413 /* Assume that the register has been elided and is the
8414 same as the first operand. */
8419 if (!match_operand (&arg, operand))
8424 /* Record that the current instruction is invalid for the current ISA. */
8427 match_invalid_for_isa (void)
8430 (0, _("opcode not supported on this processor: %s (%s)"),
8431 mips_cpu_info_from_arch (mips_opts.arch)->name,
8432 mips_cpu_info_from_isa (mips_opts.isa)->name);
8435 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8436 Return true if a definite match or failure was found, storing any match
8437 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8438 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8439 tried and failed to match under normal conditions and now want to try a
8440 more relaxed match. */
8443 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8444 const struct mips_opcode *past, struct mips_operand_token *tokens,
8445 int opcode_extra, bfd_boolean lax_match)
8447 const struct mips_opcode *opcode;
8448 const struct mips_opcode *invalid_delay_slot;
8449 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8451 /* Search for a match, ignoring alternatives that don't satisfy the
8452 current ISA or forced_length. */
8453 invalid_delay_slot = 0;
8454 seen_valid_for_isa = FALSE;
8455 seen_valid_for_size = FALSE;
8459 gas_assert (strcmp (opcode->name, first->name) == 0);
8460 if (is_opcode_valid (opcode))
8462 seen_valid_for_isa = TRUE;
8463 if (is_size_valid (opcode))
8465 bfd_boolean delay_slot_ok;
8467 seen_valid_for_size = TRUE;
8468 delay_slot_ok = is_delay_slot_valid (opcode);
8469 if (match_insn (insn, opcode, tokens, opcode_extra,
8470 lax_match, delay_slot_ok))
8474 if (!invalid_delay_slot)
8475 invalid_delay_slot = opcode;
8484 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8486 /* If the only matches we found had the wrong length for the delay slot,
8487 pick the first such match. We'll issue an appropriate warning later. */
8488 if (invalid_delay_slot)
8490 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8496 /* Handle the case where we didn't try to match an instruction because
8497 all the alternatives were incompatible with the current ISA. */
8498 if (!seen_valid_for_isa)
8500 match_invalid_for_isa ();
8504 /* Handle the case where we didn't try to match an instruction because
8505 all the alternatives were of the wrong size. */
8506 if (!seen_valid_for_size)
8508 if (mips_opts.insn32)
8509 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8512 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8513 8 * forced_insn_length);
8520 /* Like match_insns, but for MIPS16. */
8523 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8524 struct mips_operand_token *tokens)
8526 const struct mips_opcode *opcode;
8527 bfd_boolean seen_valid_for_isa;
8528 bfd_boolean seen_valid_for_size;
8530 /* Search for a match, ignoring alternatives that don't satisfy the
8531 current ISA. There are no separate entries for extended forms so
8532 we deal with forced_length later. */
8533 seen_valid_for_isa = FALSE;
8534 seen_valid_for_size = FALSE;
8538 gas_assert (strcmp (opcode->name, first->name) == 0);
8539 if (is_opcode_valid_16 (opcode))
8541 seen_valid_for_isa = TRUE;
8542 if (is_size_valid_16 (opcode))
8544 seen_valid_for_size = TRUE;
8545 if (match_mips16_insn (insn, opcode, tokens))
8551 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8552 && strcmp (opcode->name, first->name) == 0);
8554 /* Handle the case where we didn't try to match an instruction because
8555 all the alternatives were incompatible with the current ISA. */
8556 if (!seen_valid_for_isa)
8558 match_invalid_for_isa ();
8562 /* Handle the case where we didn't try to match an instruction because
8563 all the alternatives were of the wrong size. */
8564 if (!seen_valid_for_size)
8566 if (forced_insn_length == 2)
8568 (0, _("unrecognized unextended version of MIPS16 opcode"));
8571 (0, _("unrecognized extended version of MIPS16 opcode"));
8578 /* Set up global variables for the start of a new macro. */
8583 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8584 memset (&mips_macro_warning.first_insn_sizes, 0,
8585 sizeof (mips_macro_warning.first_insn_sizes));
8586 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8587 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8588 && delayed_branch_p (&history[0]));
8590 && history[0].frag->fr_type == rs_machine_dependent
8591 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
8592 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
8593 mips_macro_warning.delay_slot_length = 0;
8595 switch (history[0].insn_mo->pinfo2
8596 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8598 case INSN2_BRANCH_DELAY_32BIT:
8599 mips_macro_warning.delay_slot_length = 4;
8601 case INSN2_BRANCH_DELAY_16BIT:
8602 mips_macro_warning.delay_slot_length = 2;
8605 mips_macro_warning.delay_slot_length = 0;
8608 mips_macro_warning.first_frag = NULL;
8611 /* Given that a macro is longer than one instruction or of the wrong size,
8612 return the appropriate warning for it. Return null if no warning is
8613 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8614 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8615 and RELAX_NOMACRO. */
8618 macro_warning (relax_substateT subtype)
8620 if (subtype & RELAX_DELAY_SLOT)
8621 return _("macro instruction expanded into multiple instructions"
8622 " in a branch delay slot");
8623 else if (subtype & RELAX_NOMACRO)
8624 return _("macro instruction expanded into multiple instructions");
8625 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8626 | RELAX_DELAY_SLOT_SIZE_SECOND))
8627 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8628 ? _("macro instruction expanded into a wrong size instruction"
8629 " in a 16-bit branch delay slot")
8630 : _("macro instruction expanded into a wrong size instruction"
8631 " in a 32-bit branch delay slot"));
8636 /* Finish up a macro. Emit warnings as appropriate. */
8641 /* Relaxation warning flags. */
8642 relax_substateT subtype = 0;
8644 /* Check delay slot size requirements. */
8645 if (mips_macro_warning.delay_slot_length == 2)
8646 subtype |= RELAX_DELAY_SLOT_16BIT;
8647 if (mips_macro_warning.delay_slot_length != 0)
8649 if (mips_macro_warning.delay_slot_length
8650 != mips_macro_warning.first_insn_sizes[0])
8651 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8652 if (mips_macro_warning.delay_slot_length
8653 != mips_macro_warning.first_insn_sizes[1])
8654 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8657 /* Check instruction count requirements. */
8658 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8660 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8661 subtype |= RELAX_SECOND_LONGER;
8662 if (mips_opts.warn_about_macros)
8663 subtype |= RELAX_NOMACRO;
8664 if (mips_macro_warning.delay_slot_p)
8665 subtype |= RELAX_DELAY_SLOT;
8668 /* If both alternatives fail to fill a delay slot correctly,
8669 emit the warning now. */
8670 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8671 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8676 s = subtype & (RELAX_DELAY_SLOT_16BIT
8677 | RELAX_DELAY_SLOT_SIZE_FIRST
8678 | RELAX_DELAY_SLOT_SIZE_SECOND);
8679 msg = macro_warning (s);
8681 as_warn ("%s", msg);
8685 /* If both implementations are longer than 1 instruction, then emit the
8687 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8692 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8693 msg = macro_warning (s);
8695 as_warn ("%s", msg);
8699 /* If any flags still set, then one implementation might need a warning
8700 and the other either will need one of a different kind or none at all.
8701 Pass any remaining flags over to relaxation. */
8702 if (mips_macro_warning.first_frag != NULL)
8703 mips_macro_warning.first_frag->fr_subtype |= subtype;
8706 /* Instruction operand formats used in macros that vary between
8707 standard MIPS and microMIPS code. */
8709 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8710 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8711 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8712 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8713 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8714 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8715 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8716 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8718 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8719 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8720 : cop12_fmt[mips_opts.micromips])
8721 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8722 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8723 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8724 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8725 : mem12_fmt[mips_opts.micromips])
8726 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8727 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8728 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8730 /* Read a macro's relocation codes from *ARGS and store them in *R.
8731 The first argument in *ARGS will be either the code for a single
8732 relocation or -1 followed by the three codes that make up a
8733 composite relocation. */
8736 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8740 next = va_arg (*args, int);
8742 r[0] = (bfd_reloc_code_real_type) next;
8745 for (i = 0; i < 3; i++)
8746 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8747 /* This function is only used for 16-bit relocation fields.
8748 To make the macro code simpler, treat an unrelocated value
8749 in the same way as BFD_RELOC_LO16. */
8750 if (r[0] == BFD_RELOC_UNUSED)
8751 r[0] = BFD_RELOC_LO16;
8755 /* Build an instruction created by a macro expansion. This is passed
8756 a pointer to the count of instructions created so far, an
8757 expression, the name of the instruction to build, an operand format
8758 string, and corresponding arguments. */
8761 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8763 const struct mips_opcode *mo = NULL;
8764 bfd_reloc_code_real_type r[3];
8765 const struct mips_opcode *amo;
8766 const struct mips_operand *operand;
8767 struct hash_control *hash;
8768 struct mips_cl_insn insn;
8772 va_start (args, fmt);
8774 if (mips_opts.mips16)
8776 mips16_macro_build (ep, name, fmt, &args);
8781 r[0] = BFD_RELOC_UNUSED;
8782 r[1] = BFD_RELOC_UNUSED;
8783 r[2] = BFD_RELOC_UNUSED;
8784 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8785 amo = (struct mips_opcode *) hash_find (hash, name);
8787 gas_assert (strcmp (name, amo->name) == 0);
8791 /* Search until we get a match for NAME. It is assumed here that
8792 macros will never generate MDMX, MIPS-3D, or MT instructions.
8793 We try to match an instruction that fulfills the branch delay
8794 slot instruction length requirement (if any) of the previous
8795 instruction. While doing this we record the first instruction
8796 seen that matches all the other conditions and use it anyway
8797 if the requirement cannot be met; we will issue an appropriate
8798 warning later on. */
8799 if (strcmp (fmt, amo->args) == 0
8800 && amo->pinfo != INSN_MACRO
8801 && is_opcode_valid (amo)
8802 && is_size_valid (amo))
8804 if (is_delay_slot_valid (amo))
8814 gas_assert (amo->name);
8816 while (strcmp (name, amo->name) == 0);
8819 create_insn (&insn, mo);
8832 macro_read_relocs (&args, r);
8833 gas_assert (*r == BFD_RELOC_GPREL16
8834 || *r == BFD_RELOC_MIPS_HIGHER
8835 || *r == BFD_RELOC_HI16_S
8836 || *r == BFD_RELOC_LO16
8837 || *r == BFD_RELOC_MIPS_GOT_OFST);
8841 macro_read_relocs (&args, r);
8845 macro_read_relocs (&args, r);
8846 gas_assert (ep != NULL
8847 && (ep->X_op == O_constant
8848 || (ep->X_op == O_symbol
8849 && (*r == BFD_RELOC_MIPS_HIGHEST
8850 || *r == BFD_RELOC_HI16_S
8851 || *r == BFD_RELOC_HI16
8852 || *r == BFD_RELOC_GPREL16
8853 || *r == BFD_RELOC_MIPS_GOT_HI16
8854 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8858 gas_assert (ep != NULL);
8861 * This allows macro() to pass an immediate expression for
8862 * creating short branches without creating a symbol.
8864 * We don't allow branch relaxation for these branches, as
8865 * they should only appear in ".set nomacro" anyway.
8867 if (ep->X_op == O_constant)
8869 /* For microMIPS we always use relocations for branches.
8870 So we should not resolve immediate values. */
8871 gas_assert (!mips_opts.micromips);
8873 if ((ep->X_add_number & 3) != 0)
8874 as_bad (_("branch to misaligned address (0x%lx)"),
8875 (unsigned long) ep->X_add_number);
8876 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8877 as_bad (_("branch address range overflow (0x%lx)"),
8878 (unsigned long) ep->X_add_number);
8879 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8883 *r = BFD_RELOC_16_PCREL_S2;
8887 gas_assert (ep != NULL);
8888 *r = BFD_RELOC_MIPS_JMP;
8892 operand = (mips_opts.micromips
8893 ? decode_micromips_operand (fmt)
8894 : decode_mips_operand (fmt));
8898 uval = va_arg (args, int);
8899 if (operand->type == OP_CLO_CLZ_DEST)
8900 uval |= (uval << 5);
8901 insn_insert_operand (&insn, operand, uval);
8903 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8909 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8911 append_insn (&insn, ep, r, TRUE);
8915 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8918 struct mips_opcode *mo;
8919 struct mips_cl_insn insn;
8920 const struct mips_operand *operand;
8921 bfd_reloc_code_real_type r[3]
8922 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8924 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8926 gas_assert (strcmp (name, mo->name) == 0);
8928 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8931 gas_assert (mo->name);
8932 gas_assert (strcmp (name, mo->name) == 0);
8935 create_insn (&insn, mo);
8972 gas_assert (ep != NULL);
8974 if (ep->X_op != O_constant)
8975 *r = (int) BFD_RELOC_UNUSED + c;
8976 else if (calculate_reloc (*r, ep->X_add_number, &value))
8978 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8980 *r = BFD_RELOC_UNUSED;
8986 operand = decode_mips16_operand (c, FALSE);
8990 insn_insert_operand (&insn, operand, va_arg (*args, int));
8995 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8997 append_insn (&insn, ep, r, TRUE);
9001 * Generate a "jalr" instruction with a relocation hint to the called
9002 * function. This occurs in NewABI PIC code.
9005 macro_build_jalr (expressionS *ep, int cprestore)
9007 static const bfd_reloc_code_real_type jalr_relocs[2]
9008 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
9009 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
9013 if (MIPS_JALR_HINT_P (ep))
9018 if (mips_opts.micromips)
9020 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
9021 ? "jalr" : "jalrs");
9022 if (MIPS_JALR_HINT_P (ep)
9024 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9025 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
9027 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
9030 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
9031 if (MIPS_JALR_HINT_P (ep))
9032 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
9036 * Generate a "lui" instruction.
9039 macro_build_lui (expressionS *ep, int regnum)
9041 gas_assert (! mips_opts.mips16);
9043 if (ep->X_op != O_constant)
9045 gas_assert (ep->X_op == O_symbol);
9046 /* _gp_disp is a special case, used from s_cpload.
9047 __gnu_local_gp is used if mips_no_shared. */
9048 gas_assert (mips_pic == NO_PIC
9050 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
9051 || (! mips_in_shared
9052 && strcmp (S_GET_NAME (ep->X_add_symbol),
9053 "__gnu_local_gp") == 0));
9056 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
9059 /* Generate a sequence of instructions to do a load or store from a constant
9060 offset off of a base register (breg) into/from a target register (treg),
9061 using AT if necessary. */
9063 macro_build_ldst_constoffset (expressionS *ep, const char *op,
9064 int treg, int breg, int dbl)
9066 gas_assert (ep->X_op == O_constant);
9068 /* Sign-extending 32-bit constants makes their handling easier. */
9070 normalize_constant_expr (ep);
9072 /* Right now, this routine can only handle signed 32-bit constants. */
9073 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
9074 as_warn (_("operand overflow"));
9076 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
9078 /* Signed 16-bit offset will fit in the op. Easy! */
9079 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
9083 /* 32-bit offset, need multiple instructions and AT, like:
9084 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9085 addu $tempreg,$tempreg,$breg
9086 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9087 to handle the complete offset. */
9088 macro_build_lui (ep, AT);
9089 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
9090 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
9093 as_bad (_("macro used $at after \".set noat\""));
9098 * Generates code to set the $at register to true (one)
9099 * if reg is less than the immediate expression.
9102 set_at (int reg, int unsignedp)
9104 if (imm_expr.X_add_number >= -0x8000
9105 && imm_expr.X_add_number < 0x8000)
9106 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
9107 AT, reg, BFD_RELOC_LO16);
9110 load_register (AT, &imm_expr, GPR_SIZE == 64);
9111 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
9115 /* Count the leading zeroes by performing a binary chop. This is a
9116 bulky bit of source, but performance is a LOT better for the
9117 majority of values than a simple loop to count the bits:
9118 for (lcnt = 0; (lcnt < 32); lcnt++)
9119 if ((v) & (1 << (31 - lcnt)))
9121 However it is not code size friendly, and the gain will drop a bit
9122 on certain cached systems.
9124 #define COUNT_TOP_ZEROES(v) \
9125 (((v) & ~0xffff) == 0 \
9126 ? ((v) & ~0xff) == 0 \
9127 ? ((v) & ~0xf) == 0 \
9128 ? ((v) & ~0x3) == 0 \
9129 ? ((v) & ~0x1) == 0 \
9134 : ((v) & ~0x7) == 0 \
9137 : ((v) & ~0x3f) == 0 \
9138 ? ((v) & ~0x1f) == 0 \
9141 : ((v) & ~0x7f) == 0 \
9144 : ((v) & ~0xfff) == 0 \
9145 ? ((v) & ~0x3ff) == 0 \
9146 ? ((v) & ~0x1ff) == 0 \
9149 : ((v) & ~0x7ff) == 0 \
9152 : ((v) & ~0x3fff) == 0 \
9153 ? ((v) & ~0x1fff) == 0 \
9156 : ((v) & ~0x7fff) == 0 \
9159 : ((v) & ~0xffffff) == 0 \
9160 ? ((v) & ~0xfffff) == 0 \
9161 ? ((v) & ~0x3ffff) == 0 \
9162 ? ((v) & ~0x1ffff) == 0 \
9165 : ((v) & ~0x7ffff) == 0 \
9168 : ((v) & ~0x3fffff) == 0 \
9169 ? ((v) & ~0x1fffff) == 0 \
9172 : ((v) & ~0x7fffff) == 0 \
9175 : ((v) & ~0xfffffff) == 0 \
9176 ? ((v) & ~0x3ffffff) == 0 \
9177 ? ((v) & ~0x1ffffff) == 0 \
9180 : ((v) & ~0x7ffffff) == 0 \
9183 : ((v) & ~0x3fffffff) == 0 \
9184 ? ((v) & ~0x1fffffff) == 0 \
9187 : ((v) & ~0x7fffffff) == 0 \
9192 * This routine generates the least number of instructions necessary to load
9193 * an absolute expression value into a register.
9196 load_register (int reg, expressionS *ep, int dbl)
9199 expressionS hi32, lo32;
9201 if (ep->X_op != O_big)
9203 gas_assert (ep->X_op == O_constant);
9205 /* Sign-extending 32-bit constants makes their handling easier. */
9207 normalize_constant_expr (ep);
9209 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
9211 /* We can handle 16 bit signed values with an addiu to
9212 $zero. No need to ever use daddiu here, since $zero and
9213 the result are always correct in 32 bit mode. */
9214 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9217 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
9219 /* We can handle 16 bit unsigned values with an ori to
9221 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9224 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
9226 /* 32 bit values require an lui. */
9227 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9228 if ((ep->X_add_number & 0xffff) != 0)
9229 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9234 /* The value is larger than 32 bits. */
9236 if (!dbl || GPR_SIZE == 32)
9240 sprintf_vma (value, ep->X_add_number);
9241 as_bad (_("number (0x%s) larger than 32 bits"), value);
9242 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9246 if (ep->X_op != O_big)
9249 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9250 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9251 hi32.X_add_number &= 0xffffffff;
9253 lo32.X_add_number &= 0xffffffff;
9257 gas_assert (ep->X_add_number > 2);
9258 if (ep->X_add_number == 3)
9259 generic_bignum[3] = 0;
9260 else if (ep->X_add_number > 4)
9261 as_bad (_("number larger than 64 bits"));
9262 lo32.X_op = O_constant;
9263 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
9264 hi32.X_op = O_constant;
9265 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
9268 if (hi32.X_add_number == 0)
9273 unsigned long hi, lo;
9275 if (hi32.X_add_number == (offsetT) 0xffffffff)
9277 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
9279 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9282 if (lo32.X_add_number & 0x80000000)
9284 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9285 if (lo32.X_add_number & 0xffff)
9286 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9291 /* Check for 16bit shifted constant. We know that hi32 is
9292 non-zero, so start the mask on the first bit of the hi32
9297 unsigned long himask, lomask;
9301 himask = 0xffff >> (32 - shift);
9302 lomask = (0xffff << shift) & 0xffffffff;
9306 himask = 0xffff << (shift - 32);
9309 if ((hi32.X_add_number & ~(offsetT) himask) == 0
9310 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
9314 tmp.X_op = O_constant;
9316 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9317 | (lo32.X_add_number >> shift));
9319 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
9320 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9321 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9322 reg, reg, (shift >= 32) ? shift - 32 : shift);
9327 while (shift <= (64 - 16));
9329 /* Find the bit number of the lowest one bit, and store the
9330 shifted value in hi/lo. */
9331 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9332 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9336 while ((lo & 1) == 0)
9341 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
9347 while ((hi & 1) == 0)
9356 /* Optimize if the shifted value is a (power of 2) - 1. */
9357 if ((hi == 0 && ((lo + 1) & lo) == 0)
9358 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9360 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9365 /* This instruction will set the register to be all
9367 tmp.X_op = O_constant;
9368 tmp.X_add_number = (offsetT) -1;
9369 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9373 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9374 reg, reg, (bit >= 32) ? bit - 32 : bit);
9376 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9377 reg, reg, (shift >= 32) ? shift - 32 : shift);
9382 /* Sign extend hi32 before calling load_register, because we can
9383 generally get better code when we load a sign extended value. */
9384 if ((hi32.X_add_number & 0x80000000) != 0)
9385 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9386 load_register (reg, &hi32, 0);
9389 if ((lo32.X_add_number & 0xffff0000) == 0)
9393 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9401 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9403 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9404 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9410 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9414 mid16.X_add_number >>= 16;
9415 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9416 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9419 if ((lo32.X_add_number & 0xffff) != 0)
9420 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9424 load_delay_nop (void)
9426 if (!gpr_interlocks)
9427 macro_build (NULL, "nop", "");
9430 /* Load an address into a register. */
9433 load_address (int reg, expressionS *ep, int *used_at)
9435 if (ep->X_op != O_constant
9436 && ep->X_op != O_symbol)
9438 as_bad (_("expression too complex"));
9439 ep->X_op = O_constant;
9442 if (ep->X_op == O_constant)
9444 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9448 if (mips_pic == NO_PIC)
9450 /* If this is a reference to a GP relative symbol, we want
9451 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9453 lui $reg,<sym> (BFD_RELOC_HI16_S)
9454 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9455 If we have an addend, we always use the latter form.
9457 With 64bit address space and a usable $at we want
9458 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9459 lui $at,<sym> (BFD_RELOC_HI16_S)
9460 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9461 daddiu $at,<sym> (BFD_RELOC_LO16)
9465 If $at is already in use, we use a path which is suboptimal
9466 on superscalar processors.
9467 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9468 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9470 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9472 daddiu $reg,<sym> (BFD_RELOC_LO16)
9474 For GP relative symbols in 64bit address space we can use
9475 the same sequence as in 32bit address space. */
9476 if (HAVE_64BIT_SYMBOLS)
9478 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9479 && !nopic_need_relax (ep->X_add_symbol, 1))
9481 relax_start (ep->X_add_symbol);
9482 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9483 mips_gp_register, BFD_RELOC_GPREL16);
9487 if (*used_at == 0 && mips_opts.at)
9489 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9490 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9491 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9492 BFD_RELOC_MIPS_HIGHER);
9493 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9494 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9495 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9500 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9501 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9502 BFD_RELOC_MIPS_HIGHER);
9503 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9504 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9505 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9506 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9509 if (mips_relax.sequence)
9514 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9515 && !nopic_need_relax (ep->X_add_symbol, 1))
9517 relax_start (ep->X_add_symbol);
9518 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9519 mips_gp_register, BFD_RELOC_GPREL16);
9522 macro_build_lui (ep, reg);
9523 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9524 reg, reg, BFD_RELOC_LO16);
9525 if (mips_relax.sequence)
9529 else if (!mips_big_got)
9533 /* If this is a reference to an external symbol, we want
9534 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9536 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9538 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9539 If there is a constant, it must be added in after.
9541 If we have NewABI, we want
9542 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9543 unless we're referencing a global symbol with a non-zero
9544 offset, in which case cst must be added separately. */
9547 if (ep->X_add_number)
9549 ex.X_add_number = ep->X_add_number;
9550 ep->X_add_number = 0;
9551 relax_start (ep->X_add_symbol);
9552 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9553 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9554 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9555 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9556 ex.X_op = O_constant;
9557 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9558 reg, reg, BFD_RELOC_LO16);
9559 ep->X_add_number = ex.X_add_number;
9562 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9563 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9564 if (mips_relax.sequence)
9569 ex.X_add_number = ep->X_add_number;
9570 ep->X_add_number = 0;
9571 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9572 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9574 relax_start (ep->X_add_symbol);
9576 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9580 if (ex.X_add_number != 0)
9582 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9583 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9584 ex.X_op = O_constant;
9585 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9586 reg, reg, BFD_RELOC_LO16);
9590 else if (mips_big_got)
9594 /* This is the large GOT case. If this is a reference to an
9595 external symbol, we want
9596 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9598 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9600 Otherwise, for a reference to a local symbol in old ABI, we want
9601 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9603 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9604 If there is a constant, it must be added in after.
9606 In the NewABI, for local symbols, with or without offsets, we want:
9607 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9608 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9612 ex.X_add_number = ep->X_add_number;
9613 ep->X_add_number = 0;
9614 relax_start (ep->X_add_symbol);
9615 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9616 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9617 reg, reg, mips_gp_register);
9618 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9619 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9620 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9621 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9622 else if (ex.X_add_number)
9624 ex.X_op = O_constant;
9625 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9629 ep->X_add_number = ex.X_add_number;
9631 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9632 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9633 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9634 BFD_RELOC_MIPS_GOT_OFST);
9639 ex.X_add_number = ep->X_add_number;
9640 ep->X_add_number = 0;
9641 relax_start (ep->X_add_symbol);
9642 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9643 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9644 reg, reg, mips_gp_register);
9645 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9646 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9648 if (reg_needs_delay (mips_gp_register))
9650 /* We need a nop before loading from $gp. This special
9651 check is required because the lui which starts the main
9652 instruction stream does not refer to $gp, and so will not
9653 insert the nop which may be required. */
9654 macro_build (NULL, "nop", "");
9656 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9657 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9659 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9663 if (ex.X_add_number != 0)
9665 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9666 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9667 ex.X_op = O_constant;
9668 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9676 if (!mips_opts.at && *used_at == 1)
9677 as_bad (_("macro used $at after \".set noat\""));
9680 /* Move the contents of register SOURCE into register DEST. */
9683 move_register (int dest, int source)
9685 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9686 instruction specifically requires a 32-bit one. */
9687 if (mips_opts.micromips
9688 && !mips_opts.insn32
9689 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9690 macro_build (NULL, "move", "mp,mj", dest, source);
9692 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9695 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9696 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9697 The two alternatives are:
9699 Global symbol Local symbol
9700 ------------- ------------
9701 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9703 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9705 load_got_offset emits the first instruction and add_got_offset
9706 emits the second for a 16-bit offset or add_got_offset_hilo emits
9707 a sequence to add a 32-bit offset using a scratch register. */
9710 load_got_offset (int dest, expressionS *local)
9715 global.X_add_number = 0;
9717 relax_start (local->X_add_symbol);
9718 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9719 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9721 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9722 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9727 add_got_offset (int dest, expressionS *local)
9731 global.X_op = O_constant;
9732 global.X_op_symbol = NULL;
9733 global.X_add_symbol = NULL;
9734 global.X_add_number = local->X_add_number;
9736 relax_start (local->X_add_symbol);
9737 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9738 dest, dest, BFD_RELOC_LO16);
9740 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9745 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9748 int hold_mips_optimize;
9750 global.X_op = O_constant;
9751 global.X_op_symbol = NULL;
9752 global.X_add_symbol = NULL;
9753 global.X_add_number = local->X_add_number;
9755 relax_start (local->X_add_symbol);
9756 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9758 /* Set mips_optimize around the lui instruction to avoid
9759 inserting an unnecessary nop after the lw. */
9760 hold_mips_optimize = mips_optimize;
9762 macro_build_lui (&global, tmp);
9763 mips_optimize = hold_mips_optimize;
9764 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9767 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9770 /* Emit a sequence of instructions to emulate a branch likely operation.
9771 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9772 is its complementing branch with the original condition negated.
9773 CALL is set if the original branch specified the link operation.
9774 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9776 Code like this is produced in the noreorder mode:
9781 delay slot (executed only if branch taken)
9789 delay slot (executed only if branch taken)
9792 In the reorder mode the delay slot would be filled with a nop anyway,
9793 so code produced is simply:
9798 This function is used when producing code for the microMIPS ASE that
9799 does not implement branch likely instructions in hardware. */
9802 macro_build_branch_likely (const char *br, const char *brneg,
9803 int call, expressionS *ep, const char *fmt,
9804 unsigned int sreg, unsigned int treg)
9806 int noreorder = mips_opts.noreorder;
9809 gas_assert (mips_opts.micromips);
9813 micromips_label_expr (&expr1);
9814 macro_build (&expr1, brneg, fmt, sreg, treg);
9815 macro_build (NULL, "nop", "");
9816 macro_build (ep, call ? "bal" : "b", "p");
9818 /* Set to true so that append_insn adds a label. */
9819 emit_branch_likely_macro = TRUE;
9823 macro_build (ep, br, fmt, sreg, treg);
9824 macro_build (NULL, "nop", "");
9829 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9830 the condition code tested. EP specifies the branch target. */
9833 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9860 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9863 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9864 the register tested. EP specifies the branch target. */
9867 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9869 const char *brneg = NULL;
9879 br = mips_opts.micromips ? "bgez" : "bgezl";
9883 gas_assert (mips_opts.micromips);
9884 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9892 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9899 br = mips_opts.micromips ? "blez" : "blezl";
9906 br = mips_opts.micromips ? "bltz" : "bltzl";
9910 gas_assert (mips_opts.micromips);
9911 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9918 if (mips_opts.micromips && brneg)
9919 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9921 macro_build (ep, br, "s,p", sreg);
9924 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9925 TREG as the registers tested. EP specifies the branch target. */
9928 macro_build_branch_rsrt (int type, expressionS *ep,
9929 unsigned int sreg, unsigned int treg)
9931 const char *brneg = NULL;
9943 br = mips_opts.micromips ? "beq" : "beql";
9952 br = mips_opts.micromips ? "bne" : "bnel";
9958 if (mips_opts.micromips && brneg)
9959 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9961 macro_build (ep, br, "s,t,p", sreg, treg);
9964 /* Return the high part that should be loaded in order to make the low
9965 part of VALUE accessible using an offset of OFFBITS bits. */
9968 offset_high_part (offsetT value, unsigned int offbits)
9975 bias = 1 << (offbits - 1);
9976 low_mask = bias * 2 - 1;
9977 return (value + bias) & ~low_mask;
9980 /* Return true if the value stored in offset_expr and offset_reloc
9981 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9982 amount that the caller wants to add without inducing overflow
9983 and ALIGN is the known alignment of the value in bytes. */
9986 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9990 /* Accept any relocation operator if overflow isn't a concern. */
9991 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9994 /* These relocations are guaranteed not to overflow in correct links. */
9995 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9996 || gprel16_reloc_p (*offset_reloc))
9999 if (offset_expr.X_op == O_constant
10000 && offset_high_part (offset_expr.X_add_number, offbits) == 0
10001 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
10008 * This routine implements the seemingly endless macro or synthesized
10009 * instructions and addressing modes in the mips assembly language. Many
10010 * of these macros are simple and are similar to each other. These could
10011 * probably be handled by some kind of table or grammar approach instead of
10012 * this verbose method. Others are not simple macros but are more like
10013 * optimizing code generation.
10014 * One interesting optimization is when several store macros appear
10015 * consecutively that would load AT with the upper half of the same address.
10016 * The ensuing load upper instructions are omitted. This implies some kind
10017 * of global optimization. We currently only optimize within a single macro.
10018 * For many of the load and store macros if the address is specified as a
10019 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10020 * first load register 'at' with zero and use it as the base register. The
10021 * mips assembler simply uses register $zero. Just one tiny optimization
10025 macro (struct mips_cl_insn *ip, char *str)
10027 const struct mips_operand_array *operands;
10028 unsigned int breg, i;
10029 unsigned int tempreg;
10032 expressionS label_expr;
10047 bfd_boolean large_offset;
10049 int hold_mips_optimize;
10050 unsigned int align;
10051 unsigned int op[MAX_OPERANDS];
10053 gas_assert (! mips_opts.mips16);
10055 operands = insn_operands (ip);
10056 for (i = 0; i < MAX_OPERANDS; i++)
10057 if (operands->operand[i])
10058 op[i] = insn_extract_operand (ip, operands->operand[i]);
10062 mask = ip->insn_mo->mask;
10064 label_expr.X_op = O_constant;
10065 label_expr.X_op_symbol = NULL;
10066 label_expr.X_add_symbol = NULL;
10067 label_expr.X_add_number = 0;
10069 expr1.X_op = O_constant;
10070 expr1.X_op_symbol = NULL;
10071 expr1.X_add_symbol = NULL;
10072 expr1.X_add_number = 1;
10079 /* Fall through. */
10087 start_noreorder ();
10089 if (mips_opts.micromips)
10090 micromips_label_expr (&label_expr);
10092 label_expr.X_add_number = 8;
10093 macro_build (&label_expr, "bgez", "s,p", op[1]);
10094 if (op[0] == op[1])
10095 macro_build (NULL, "nop", "");
10097 move_register (op[0], op[1]);
10098 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
10099 if (mips_opts.micromips)
10100 micromips_add_label ();
10117 if (!mips_opts.micromips)
10119 if (imm_expr.X_add_number >= -0x200
10120 && imm_expr.X_add_number < 0x200)
10122 macro_build (NULL, s, "t,r,.", op[0], op[1],
10123 (int) imm_expr.X_add_number);
10132 if (imm_expr.X_add_number >= -0x8000
10133 && imm_expr.X_add_number < 0x8000)
10135 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
10140 load_register (AT, &imm_expr, dbl);
10141 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10160 if (imm_expr.X_add_number >= 0
10161 && imm_expr.X_add_number < 0x10000)
10163 if (mask != M_NOR_I)
10164 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
10167 macro_build (&imm_expr, "ori", "t,r,i",
10168 op[0], op[1], BFD_RELOC_LO16);
10169 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
10175 load_register (AT, &imm_expr, GPR_SIZE == 64);
10176 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10180 switch (imm_expr.X_add_number)
10183 macro_build (NULL, "nop", "");
10186 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
10190 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
10191 (int) imm_expr.X_add_number);
10194 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10195 (unsigned long) imm_expr.X_add_number);
10204 gas_assert (mips_opts.micromips);
10205 macro_build_branch_ccl (mask, &offset_expr,
10206 EXTRACT_OPERAND (1, BCC, *ip));
10213 if (imm_expr.X_add_number == 0)
10219 load_register (op[1], &imm_expr, GPR_SIZE == 64);
10221 /* Fall through. */
10224 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
10229 /* Fall through. */
10232 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
10233 else if (op[0] == 0)
10234 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
10238 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10239 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10240 &offset_expr, AT, ZERO);
10250 macro_build_branch_rs (mask, &offset_expr, op[0]);
10255 /* Fall through. */
10257 /* Check for > max integer. */
10258 if (imm_expr.X_add_number >= GPR_SMAX)
10261 /* Result is always false. */
10263 macro_build (NULL, "nop", "");
10265 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
10268 ++imm_expr.X_add_number;
10272 if (mask == M_BGEL_I)
10274 if (imm_expr.X_add_number == 0)
10276 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
10277 &offset_expr, op[0]);
10280 if (imm_expr.X_add_number == 1)
10282 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
10283 &offset_expr, op[0]);
10286 if (imm_expr.X_add_number <= GPR_SMIN)
10289 /* result is always true */
10290 as_warn (_("branch %s is always true"), ip->insn_mo->name);
10291 macro_build (&offset_expr, "b", "p");
10296 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10297 &offset_expr, AT, ZERO);
10302 /* Fall through. */
10306 else if (op[0] == 0)
10307 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10308 &offset_expr, ZERO, op[1]);
10312 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10313 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10314 &offset_expr, AT, ZERO);
10320 /* Fall through. */
10324 && imm_expr.X_add_number == -1))
10326 ++imm_expr.X_add_number;
10330 if (mask == M_BGEUL_I)
10332 if (imm_expr.X_add_number == 0)
10334 else if (imm_expr.X_add_number == 1)
10335 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10336 &offset_expr, op[0], ZERO);
10341 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10342 &offset_expr, AT, ZERO);
10348 /* Fall through. */
10351 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10352 else if (op[0] == 0)
10353 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10357 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10358 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10359 &offset_expr, AT, ZERO);
10365 /* Fall through. */
10368 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10369 &offset_expr, op[0], ZERO);
10370 else if (op[0] == 0)
10375 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10376 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10377 &offset_expr, AT, ZERO);
10383 /* Fall through. */
10386 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10387 else if (op[0] == 0)
10388 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10392 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10393 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10394 &offset_expr, AT, ZERO);
10400 /* Fall through. */
10402 if (imm_expr.X_add_number >= GPR_SMAX)
10404 ++imm_expr.X_add_number;
10408 if (mask == M_BLTL_I)
10410 if (imm_expr.X_add_number == 0)
10411 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10412 else if (imm_expr.X_add_number == 1)
10413 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10418 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10419 &offset_expr, AT, ZERO);
10425 /* Fall through. */
10428 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10429 &offset_expr, op[0], ZERO);
10430 else if (op[0] == 0)
10435 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10436 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10437 &offset_expr, AT, ZERO);
10443 /* Fall through. */
10447 && imm_expr.X_add_number == -1))
10449 ++imm_expr.X_add_number;
10453 if (mask == M_BLTUL_I)
10455 if (imm_expr.X_add_number == 0)
10457 else if (imm_expr.X_add_number == 1)
10458 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10459 &offset_expr, op[0], ZERO);
10464 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10465 &offset_expr, AT, ZERO);
10471 /* Fall through. */
10474 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10475 else if (op[0] == 0)
10476 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10480 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10481 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10482 &offset_expr, AT, ZERO);
10488 /* Fall through. */
10492 else if (op[0] == 0)
10493 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10494 &offset_expr, ZERO, op[1]);
10498 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10499 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10500 &offset_expr, AT, ZERO);
10506 /* Fall through. */
10512 /* Fall through. */
10518 as_warn (_("divide by zero"));
10520 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10522 macro_build (NULL, "break", BRK_FMT, 7);
10526 start_noreorder ();
10529 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10530 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10534 if (mips_opts.micromips)
10535 micromips_label_expr (&label_expr);
10537 label_expr.X_add_number = 8;
10538 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10539 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10540 macro_build (NULL, "break", BRK_FMT, 7);
10541 if (mips_opts.micromips)
10542 micromips_add_label ();
10544 expr1.X_add_number = -1;
10546 load_register (AT, &expr1, dbl);
10547 if (mips_opts.micromips)
10548 micromips_label_expr (&label_expr);
10550 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10551 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10554 expr1.X_add_number = 1;
10555 load_register (AT, &expr1, dbl);
10556 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10560 expr1.X_add_number = 0x80000000;
10561 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10565 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10566 /* We want to close the noreorder block as soon as possible, so
10567 that later insns are available for delay slot filling. */
10572 if (mips_opts.micromips)
10573 micromips_label_expr (&label_expr);
10575 label_expr.X_add_number = 8;
10576 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10577 macro_build (NULL, "nop", "");
10579 /* We want to close the noreorder block as soon as possible, so
10580 that later insns are available for delay slot filling. */
10583 macro_build (NULL, "break", BRK_FMT, 6);
10585 if (mips_opts.micromips)
10586 micromips_add_label ();
10587 macro_build (NULL, s, MFHL_FMT, op[0]);
10626 if (imm_expr.X_add_number == 0)
10628 as_warn (_("divide by zero"));
10630 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10632 macro_build (NULL, "break", BRK_FMT, 7);
10635 if (imm_expr.X_add_number == 1)
10637 if (strcmp (s2, "mflo") == 0)
10638 move_register (op[0], op[1]);
10640 move_register (op[0], ZERO);
10643 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10645 if (strcmp (s2, "mflo") == 0)
10646 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10648 move_register (op[0], ZERO);
10653 load_register (AT, &imm_expr, dbl);
10654 macro_build (NULL, s, "z,s,t", op[1], AT);
10655 macro_build (NULL, s2, MFHL_FMT, op[0]);
10674 start_noreorder ();
10677 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10678 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10679 /* We want to close the noreorder block as soon as possible, so
10680 that later insns are available for delay slot filling. */
10685 if (mips_opts.micromips)
10686 micromips_label_expr (&label_expr);
10688 label_expr.X_add_number = 8;
10689 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10690 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10692 /* We want to close the noreorder block as soon as possible, so
10693 that later insns are available for delay slot filling. */
10695 macro_build (NULL, "break", BRK_FMT, 7);
10696 if (mips_opts.micromips)
10697 micromips_add_label ();
10699 macro_build (NULL, s2, MFHL_FMT, op[0]);
10704 /* Fall through. */
10710 /* Fall through. */
10713 /* Load the address of a symbol into a register. If breg is not
10714 zero, we then add a base register to it. */
10717 if (dbl && GPR_SIZE == 32)
10718 as_warn (_("dla used to load 32-bit register; recommend using la "
10721 if (!dbl && HAVE_64BIT_OBJECTS)
10722 as_warn (_("la used to load 64-bit address; recommend using dla "
10725 if (small_offset_p (0, align, 16))
10727 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10728 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10732 if (mips_opts.at && (op[0] == breg))
10740 if (offset_expr.X_op != O_symbol
10741 && offset_expr.X_op != O_constant)
10743 as_bad (_("expression too complex"));
10744 offset_expr.X_op = O_constant;
10747 if (offset_expr.X_op == O_constant)
10748 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10749 else if (mips_pic == NO_PIC)
10751 /* If this is a reference to a GP relative symbol, we want
10752 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10754 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10755 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10756 If we have a constant, we need two instructions anyhow,
10757 so we may as well always use the latter form.
10759 With 64bit address space and a usable $at we want
10760 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10761 lui $at,<sym> (BFD_RELOC_HI16_S)
10762 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10763 daddiu $at,<sym> (BFD_RELOC_LO16)
10765 daddu $tempreg,$tempreg,$at
10767 If $at is already in use, we use a path which is suboptimal
10768 on superscalar processors.
10769 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10770 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10772 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10774 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10776 For GP relative symbols in 64bit address space we can use
10777 the same sequence as in 32bit address space. */
10778 if (HAVE_64BIT_SYMBOLS)
10780 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10781 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10783 relax_start (offset_expr.X_add_symbol);
10784 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10785 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10789 if (used_at == 0 && mips_opts.at)
10791 macro_build (&offset_expr, "lui", LUI_FMT,
10792 tempreg, BFD_RELOC_MIPS_HIGHEST);
10793 macro_build (&offset_expr, "lui", LUI_FMT,
10794 AT, BFD_RELOC_HI16_S);
10795 macro_build (&offset_expr, "daddiu", "t,r,j",
10796 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10797 macro_build (&offset_expr, "daddiu", "t,r,j",
10798 AT, AT, BFD_RELOC_LO16);
10799 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10800 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10805 macro_build (&offset_expr, "lui", LUI_FMT,
10806 tempreg, BFD_RELOC_MIPS_HIGHEST);
10807 macro_build (&offset_expr, "daddiu", "t,r,j",
10808 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10809 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10810 macro_build (&offset_expr, "daddiu", "t,r,j",
10811 tempreg, tempreg, BFD_RELOC_HI16_S);
10812 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10813 macro_build (&offset_expr, "daddiu", "t,r,j",
10814 tempreg, tempreg, BFD_RELOC_LO16);
10817 if (mips_relax.sequence)
10822 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10823 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10825 relax_start (offset_expr.X_add_symbol);
10826 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10827 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10830 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10831 as_bad (_("offset too large"));
10832 macro_build_lui (&offset_expr, tempreg);
10833 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10834 tempreg, tempreg, BFD_RELOC_LO16);
10835 if (mips_relax.sequence)
10839 else if (!mips_big_got && !HAVE_NEWABI)
10841 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10843 /* If this is a reference to an external symbol, and there
10844 is no constant, we want
10845 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10846 or for lca or if tempreg is PIC_CALL_REG
10847 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10848 For a local symbol, we want
10849 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10851 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10853 If we have a small constant, and this is a reference to
10854 an external symbol, we want
10855 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10857 addiu $tempreg,$tempreg,<constant>
10858 For a local symbol, we want the same instruction
10859 sequence, but we output a BFD_RELOC_LO16 reloc on the
10862 If we have a large constant, and this is a reference to
10863 an external symbol, we want
10864 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10865 lui $at,<hiconstant>
10866 addiu $at,$at,<loconstant>
10867 addu $tempreg,$tempreg,$at
10868 For a local symbol, we want the same instruction
10869 sequence, but we output a BFD_RELOC_LO16 reloc on the
10873 if (offset_expr.X_add_number == 0)
10875 if (mips_pic == SVR4_PIC
10877 && (call || tempreg == PIC_CALL_REG))
10878 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10880 relax_start (offset_expr.X_add_symbol);
10881 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10882 lw_reloc_type, mips_gp_register);
10885 /* We're going to put in an addu instruction using
10886 tempreg, so we may as well insert the nop right
10891 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10892 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10894 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10895 tempreg, tempreg, BFD_RELOC_LO16);
10897 /* FIXME: If breg == 0, and the next instruction uses
10898 $tempreg, then if this variant case is used an extra
10899 nop will be generated. */
10901 else if (offset_expr.X_add_number >= -0x8000
10902 && offset_expr.X_add_number < 0x8000)
10904 load_got_offset (tempreg, &offset_expr);
10906 add_got_offset (tempreg, &offset_expr);
10910 expr1.X_add_number = offset_expr.X_add_number;
10911 offset_expr.X_add_number =
10912 SEXT_16BIT (offset_expr.X_add_number);
10913 load_got_offset (tempreg, &offset_expr);
10914 offset_expr.X_add_number = expr1.X_add_number;
10915 /* If we are going to add in a base register, and the
10916 target register and the base register are the same,
10917 then we are using AT as a temporary register. Since
10918 we want to load the constant into AT, we add our
10919 current AT (from the global offset table) and the
10920 register into the register now, and pretend we were
10921 not using a base register. */
10925 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10930 add_got_offset_hilo (tempreg, &offset_expr, AT);
10934 else if (!mips_big_got && HAVE_NEWABI)
10936 int add_breg_early = 0;
10938 /* If this is a reference to an external, and there is no
10939 constant, or local symbol (*), with or without a
10941 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10942 or for lca or if tempreg is PIC_CALL_REG
10943 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10945 If we have a small constant, and this is a reference to
10946 an external symbol, we want
10947 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10948 addiu $tempreg,$tempreg,<constant>
10950 If we have a large constant, and this is a reference to
10951 an external symbol, we want
10952 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10953 lui $at,<hiconstant>
10954 addiu $at,$at,<loconstant>
10955 addu $tempreg,$tempreg,$at
10957 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10958 local symbols, even though it introduces an additional
10961 if (offset_expr.X_add_number)
10963 expr1.X_add_number = offset_expr.X_add_number;
10964 offset_expr.X_add_number = 0;
10966 relax_start (offset_expr.X_add_symbol);
10967 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10968 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10970 if (expr1.X_add_number >= -0x8000
10971 && expr1.X_add_number < 0x8000)
10973 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10974 tempreg, tempreg, BFD_RELOC_LO16);
10976 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10980 /* If we are going to add in a base register, and the
10981 target register and the base register are the same,
10982 then we are using AT as a temporary register. Since
10983 we want to load the constant into AT, we add our
10984 current AT (from the global offset table) and the
10985 register into the register now, and pretend we were
10986 not using a base register. */
10991 gas_assert (tempreg == AT);
10992 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10995 add_breg_early = 1;
10998 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10999 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11005 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11008 offset_expr.X_add_number = expr1.X_add_number;
11010 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11011 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11012 if (add_breg_early)
11014 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11015 op[0], tempreg, breg);
11021 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
11023 relax_start (offset_expr.X_add_symbol);
11024 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11025 BFD_RELOC_MIPS_CALL16, mips_gp_register);
11027 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11028 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11033 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11034 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11037 else if (mips_big_got && !HAVE_NEWABI)
11040 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11041 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11042 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11044 /* This is the large GOT case. If this is a reference to an
11045 external symbol, and there is no constant, we want
11046 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11047 addu $tempreg,$tempreg,$gp
11048 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11049 or for lca or if tempreg is PIC_CALL_REG
11050 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11051 addu $tempreg,$tempreg,$gp
11052 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11053 For a local symbol, we want
11054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11056 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11058 If we have a small constant, and this is a reference to
11059 an external symbol, we want
11060 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11061 addu $tempreg,$tempreg,$gp
11062 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11064 addiu $tempreg,$tempreg,<constant>
11065 For a local symbol, we want
11066 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11068 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11070 If we have a large constant, and this is a reference to
11071 an external symbol, we want
11072 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11073 addu $tempreg,$tempreg,$gp
11074 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11075 lui $at,<hiconstant>
11076 addiu $at,$at,<loconstant>
11077 addu $tempreg,$tempreg,$at
11078 For a local symbol, we want
11079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11080 lui $at,<hiconstant>
11081 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11082 addu $tempreg,$tempreg,$at
11085 expr1.X_add_number = offset_expr.X_add_number;
11086 offset_expr.X_add_number = 0;
11087 relax_start (offset_expr.X_add_symbol);
11088 gpdelay = reg_needs_delay (mips_gp_register);
11089 if (expr1.X_add_number == 0 && breg == 0
11090 && (call || tempreg == PIC_CALL_REG))
11092 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11093 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11095 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11096 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11097 tempreg, tempreg, mips_gp_register);
11098 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11099 tempreg, lw_reloc_type, tempreg);
11100 if (expr1.X_add_number == 0)
11104 /* We're going to put in an addu instruction using
11105 tempreg, so we may as well insert the nop right
11110 else if (expr1.X_add_number >= -0x8000
11111 && expr1.X_add_number < 0x8000)
11114 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11115 tempreg, tempreg, BFD_RELOC_LO16);
11121 /* If we are going to add in a base register, and the
11122 target register and the base register are the same,
11123 then we are using AT as a temporary register. Since
11124 we want to load the constant into AT, we add our
11125 current AT (from the global offset table) and the
11126 register into the register now, and pretend we were
11127 not using a base register. */
11132 gas_assert (tempreg == AT);
11134 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11139 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11140 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11144 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
11149 /* This is needed because this instruction uses $gp, but
11150 the first instruction on the main stream does not. */
11151 macro_build (NULL, "nop", "");
11154 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11155 local_reloc_type, mips_gp_register);
11156 if (expr1.X_add_number >= -0x8000
11157 && expr1.X_add_number < 0x8000)
11160 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11161 tempreg, tempreg, BFD_RELOC_LO16);
11162 /* FIXME: If add_number is 0, and there was no base
11163 register, the external symbol case ended with a load,
11164 so if the symbol turns out to not be external, and
11165 the next instruction uses tempreg, an unnecessary nop
11166 will be inserted. */
11172 /* We must add in the base register now, as in the
11173 external symbol case. */
11174 gas_assert (tempreg == AT);
11176 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11179 /* We set breg to 0 because we have arranged to add
11180 it in in both cases. */
11184 macro_build_lui (&expr1, AT);
11185 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11186 AT, AT, BFD_RELOC_LO16);
11187 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11188 tempreg, tempreg, AT);
11193 else if (mips_big_got && HAVE_NEWABI)
11195 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11196 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11197 int add_breg_early = 0;
11199 /* This is the large GOT case. If this is a reference to an
11200 external symbol, and there is no constant, we want
11201 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11202 add $tempreg,$tempreg,$gp
11203 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11204 or for lca or if tempreg is PIC_CALL_REG
11205 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11206 add $tempreg,$tempreg,$gp
11207 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11209 If we have a small constant, and this is a reference to
11210 an external symbol, we want
11211 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11212 add $tempreg,$tempreg,$gp
11213 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11214 addi $tempreg,$tempreg,<constant>
11216 If we have a large constant, and this is a reference to
11217 an external symbol, we want
11218 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11219 addu $tempreg,$tempreg,$gp
11220 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11221 lui $at,<hiconstant>
11222 addi $at,$at,<loconstant>
11223 add $tempreg,$tempreg,$at
11225 If we have NewABI, and we know it's a local symbol, we want
11226 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11227 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11228 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11230 relax_start (offset_expr.X_add_symbol);
11232 expr1.X_add_number = offset_expr.X_add_number;
11233 offset_expr.X_add_number = 0;
11235 if (expr1.X_add_number == 0 && breg == 0
11236 && (call || tempreg == PIC_CALL_REG))
11238 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11239 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11241 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11242 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11243 tempreg, tempreg, mips_gp_register);
11244 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11245 tempreg, lw_reloc_type, tempreg);
11247 if (expr1.X_add_number == 0)
11249 else if (expr1.X_add_number >= -0x8000
11250 && expr1.X_add_number < 0x8000)
11252 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11253 tempreg, tempreg, BFD_RELOC_LO16);
11255 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11259 /* If we are going to add in a base register, and the
11260 target register and the base register are the same,
11261 then we are using AT as a temporary register. Since
11262 we want to load the constant into AT, we add our
11263 current AT (from the global offset table) and the
11264 register into the register now, and pretend we were
11265 not using a base register. */
11270 gas_assert (tempreg == AT);
11271 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11274 add_breg_early = 1;
11277 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11278 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11283 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11286 offset_expr.X_add_number = expr1.X_add_number;
11287 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11288 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11289 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11290 tempreg, BFD_RELOC_MIPS_GOT_OFST);
11291 if (add_breg_early)
11293 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11294 op[0], tempreg, breg);
11304 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
11308 gas_assert (!mips_opts.micromips);
11309 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
11313 gas_assert (!mips_opts.micromips);
11314 macro_build (NULL, "c2", "C", 0x02);
11318 gas_assert (!mips_opts.micromips);
11319 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
11323 gas_assert (!mips_opts.micromips);
11324 macro_build (NULL, "c2", "C", 3);
11328 gas_assert (!mips_opts.micromips);
11329 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
11333 /* The j instruction may not be used in PIC code, since it
11334 requires an absolute address. We convert it to a b
11336 if (mips_pic == NO_PIC)
11337 macro_build (&offset_expr, "j", "a");
11339 macro_build (&offset_expr, "b", "p");
11342 /* The jal instructions must be handled as macros because when
11343 generating PIC code they expand to multi-instruction
11344 sequences. Normally they are simple instructions. */
11348 /* Fall through. */
11350 gas_assert (mips_opts.micromips);
11351 if (mips_opts.insn32)
11353 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11361 /* Fall through. */
11364 if (mips_pic == NO_PIC)
11366 s = jals ? "jalrs" : "jalr";
11367 if (mips_opts.micromips
11368 && !mips_opts.insn32
11370 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11371 macro_build (NULL, s, "mj", op[1]);
11373 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11377 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11378 && mips_cprestore_offset >= 0);
11380 if (op[1] != PIC_CALL_REG)
11381 as_warn (_("MIPS PIC call to register other than $25"));
11383 s = ((mips_opts.micromips
11384 && !mips_opts.insn32
11385 && (!mips_opts.noreorder || cprestore))
11386 ? "jalrs" : "jalr");
11387 if (mips_opts.micromips
11388 && !mips_opts.insn32
11390 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11391 macro_build (NULL, s, "mj", op[1]);
11393 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11394 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11396 if (mips_cprestore_offset < 0)
11397 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11400 if (!mips_frame_reg_valid)
11402 as_warn (_("no .frame pseudo-op used in PIC code"));
11403 /* Quiet this warning. */
11404 mips_frame_reg_valid = 1;
11406 if (!mips_cprestore_valid)
11408 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11409 /* Quiet this warning. */
11410 mips_cprestore_valid = 1;
11412 if (mips_opts.noreorder)
11413 macro_build (NULL, "nop", "");
11414 expr1.X_add_number = mips_cprestore_offset;
11415 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11418 HAVE_64BIT_ADDRESSES);
11426 gas_assert (mips_opts.micromips);
11427 if (mips_opts.insn32)
11429 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11433 /* Fall through. */
11435 if (mips_pic == NO_PIC)
11436 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11437 else if (mips_pic == SVR4_PIC)
11439 /* If this is a reference to an external symbol, and we are
11440 using a small GOT, we want
11441 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11445 lw $gp,cprestore($sp)
11446 The cprestore value is set using the .cprestore
11447 pseudo-op. If we are using a big GOT, we want
11448 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11450 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11454 lw $gp,cprestore($sp)
11455 If the symbol is not external, we want
11456 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11458 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11461 lw $gp,cprestore($sp)
11463 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11464 sequences above, minus nops, unless the symbol is local,
11465 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11471 relax_start (offset_expr.X_add_symbol);
11472 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11473 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11476 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11477 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11483 relax_start (offset_expr.X_add_symbol);
11484 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11485 BFD_RELOC_MIPS_CALL_HI16);
11486 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11487 PIC_CALL_REG, mips_gp_register);
11488 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11489 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11492 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11493 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11495 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11496 PIC_CALL_REG, PIC_CALL_REG,
11497 BFD_RELOC_MIPS_GOT_OFST);
11501 macro_build_jalr (&offset_expr, 0);
11505 relax_start (offset_expr.X_add_symbol);
11508 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11509 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11518 gpdelay = reg_needs_delay (mips_gp_register);
11519 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11520 BFD_RELOC_MIPS_CALL_HI16);
11521 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11522 PIC_CALL_REG, mips_gp_register);
11523 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11524 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11529 macro_build (NULL, "nop", "");
11531 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11532 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11535 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11536 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11538 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11540 if (mips_cprestore_offset < 0)
11541 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11544 if (!mips_frame_reg_valid)
11546 as_warn (_("no .frame pseudo-op used in PIC code"));
11547 /* Quiet this warning. */
11548 mips_frame_reg_valid = 1;
11550 if (!mips_cprestore_valid)
11552 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11553 /* Quiet this warning. */
11554 mips_cprestore_valid = 1;
11556 if (mips_opts.noreorder)
11557 macro_build (NULL, "nop", "");
11558 expr1.X_add_number = mips_cprestore_offset;
11559 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11562 HAVE_64BIT_ADDRESSES);
11566 else if (mips_pic == VXWORKS_PIC)
11567 as_bad (_("non-PIC jump used in PIC library"));
11674 gas_assert (!mips_opts.micromips);
11677 /* Itbl support may require additional care here. */
11683 /* Itbl support may require additional care here. */
11689 offbits = (mips_opts.micromips ? 12
11690 : ISA_IS_R6 (mips_opts.isa) ? 11
11692 /* Itbl support may require additional care here. */
11696 gas_assert (!mips_opts.micromips);
11699 /* Itbl support may require additional care here. */
11705 offbits = (mips_opts.micromips ? 12 : 16);
11710 offbits = (mips_opts.micromips ? 12 : 16);
11715 /* Itbl support may require additional care here. */
11721 offbits = (mips_opts.micromips ? 12
11722 : ISA_IS_R6 (mips_opts.isa) ? 11
11724 /* Itbl support may require additional care here. */
11730 /* Itbl support may require additional care here. */
11736 /* Itbl support may require additional care here. */
11742 offbits = (mips_opts.micromips ? 12 : 16);
11747 offbits = (mips_opts.micromips ? 12 : 16);
11752 offbits = (mips_opts.micromips ? 12
11753 : ISA_IS_R6 (mips_opts.isa) ? 9
11759 offbits = (mips_opts.micromips ? 12
11760 : ISA_IS_R6 (mips_opts.isa) ? 9
11766 offbits = (mips_opts.micromips ? 12 : 16);
11769 gas_assert (mips_opts.micromips);
11776 gas_assert (mips_opts.micromips);
11783 gas_assert (mips_opts.micromips);
11789 gas_assert (mips_opts.micromips);
11796 /* We don't want to use $0 as tempreg. */
11797 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11800 tempreg = op[0] + lp;
11816 gas_assert (!mips_opts.micromips);
11819 /* Itbl support may require additional care here. */
11825 /* Itbl support may require additional care here. */
11831 offbits = (mips_opts.micromips ? 12
11832 : ISA_IS_R6 (mips_opts.isa) ? 11
11834 /* Itbl support may require additional care here. */
11838 gas_assert (!mips_opts.micromips);
11841 /* Itbl support may require additional care here. */
11847 offbits = (mips_opts.micromips ? 12 : 16);
11852 offbits = (mips_opts.micromips ? 12 : 16);
11857 offbits = (mips_opts.micromips ? 12
11858 : ISA_IS_R6 (mips_opts.isa) ? 9
11864 offbits = (mips_opts.micromips ? 12
11865 : ISA_IS_R6 (mips_opts.isa) ? 9
11870 fmt = (mips_opts.micromips ? "k,~(b)"
11871 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11873 offbits = (mips_opts.micromips ? 12
11874 : ISA_IS_R6 (mips_opts.isa) ? 9
11884 fmt = (mips_opts.micromips ? "k,~(b)"
11885 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11887 offbits = (mips_opts.micromips ? 12
11888 : ISA_IS_R6 (mips_opts.isa) ? 9
11900 /* Itbl support may require additional care here. */
11905 offbits = (mips_opts.micromips ? 12
11906 : ISA_IS_R6 (mips_opts.isa) ? 11
11908 /* Itbl support may require additional care here. */
11914 /* Itbl support may require additional care here. */
11918 gas_assert (!mips_opts.micromips);
11921 /* Itbl support may require additional care here. */
11927 offbits = (mips_opts.micromips ? 12 : 16);
11932 offbits = (mips_opts.micromips ? 12 : 16);
11935 gas_assert (mips_opts.micromips);
11941 gas_assert (mips_opts.micromips);
11947 gas_assert (mips_opts.micromips);
11953 gas_assert (mips_opts.micromips);
11962 if (small_offset_p (0, align, 16))
11964 /* The first case exists for M_LD_AB and M_SD_AB, which are
11965 macros for o32 but which should act like normal instructions
11968 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11969 offset_reloc[1], offset_reloc[2], breg);
11970 else if (small_offset_p (0, align, offbits))
11973 macro_build (NULL, s, fmt, op[0], breg);
11975 macro_build (NULL, s, fmt, op[0],
11976 (int) offset_expr.X_add_number, breg);
11982 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11983 tempreg, breg, -1, offset_reloc[0],
11984 offset_reloc[1], offset_reloc[2]);
11986 macro_build (NULL, s, fmt, op[0], tempreg);
11988 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11996 if (offset_expr.X_op != O_constant
11997 && offset_expr.X_op != O_symbol)
11999 as_bad (_("expression too complex"));
12000 offset_expr.X_op = O_constant;
12003 if (HAVE_32BIT_ADDRESSES
12004 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12008 sprintf_vma (value, offset_expr.X_add_number);
12009 as_bad (_("number (0x%s) larger than 32 bits"), value);
12012 /* A constant expression in PIC code can be handled just as it
12013 is in non PIC code. */
12014 if (offset_expr.X_op == O_constant)
12016 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
12017 offbits == 0 ? 16 : offbits);
12018 offset_expr.X_add_number -= expr1.X_add_number;
12020 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
12022 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12023 tempreg, tempreg, breg);
12026 if (offset_expr.X_add_number != 0)
12027 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
12028 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
12029 macro_build (NULL, s, fmt, op[0], tempreg);
12031 else if (offbits == 16)
12032 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12034 macro_build (NULL, s, fmt, op[0],
12035 (int) offset_expr.X_add_number, tempreg);
12037 else if (offbits != 16)
12039 /* The offset field is too narrow to be used for a low-part
12040 relocation, so load the whole address into the auxiliary
12042 load_address (tempreg, &offset_expr, &used_at);
12044 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12045 tempreg, tempreg, breg);
12047 macro_build (NULL, s, fmt, op[0], tempreg);
12049 macro_build (NULL, s, fmt, op[0], 0, tempreg);
12051 else if (mips_pic == NO_PIC)
12053 /* If this is a reference to a GP relative symbol, and there
12054 is no base register, we want
12055 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12056 Otherwise, if there is no base register, we want
12057 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12058 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12059 If we have a constant, we need two instructions anyhow,
12060 so we always use the latter form.
12062 If we have a base register, and this is a reference to a
12063 GP relative symbol, we want
12064 addu $tempreg,$breg,$gp
12065 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12067 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12068 addu $tempreg,$tempreg,$breg
12069 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12070 With a constant we always use the latter case.
12072 With 64bit address space and no base register and $at usable,
12074 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12075 lui $at,<sym> (BFD_RELOC_HI16_S)
12076 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12079 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12080 If we have a base register, we want
12081 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12082 lui $at,<sym> (BFD_RELOC_HI16_S)
12083 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12087 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12089 Without $at we can't generate the optimal path for superscalar
12090 processors here since this would require two temporary registers.
12091 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12092 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12094 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12096 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12097 If we have a base register, we want
12098 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12099 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12101 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12103 daddu $tempreg,$tempreg,$breg
12104 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12106 For GP relative symbols in 64bit address space we can use
12107 the same sequence as in 32bit address space. */
12108 if (HAVE_64BIT_SYMBOLS)
12110 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12111 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12113 relax_start (offset_expr.X_add_symbol);
12116 macro_build (&offset_expr, s, fmt, op[0],
12117 BFD_RELOC_GPREL16, mips_gp_register);
12121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12122 tempreg, breg, mips_gp_register);
12123 macro_build (&offset_expr, s, fmt, op[0],
12124 BFD_RELOC_GPREL16, tempreg);
12129 if (used_at == 0 && mips_opts.at)
12131 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12132 BFD_RELOC_MIPS_HIGHEST);
12133 macro_build (&offset_expr, "lui", LUI_FMT, AT,
12135 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12136 tempreg, BFD_RELOC_MIPS_HIGHER);
12138 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
12139 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
12140 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
12141 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
12147 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12148 BFD_RELOC_MIPS_HIGHEST);
12149 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12150 tempreg, BFD_RELOC_MIPS_HIGHER);
12151 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12152 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12153 tempreg, BFD_RELOC_HI16_S);
12154 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12156 macro_build (NULL, "daddu", "d,v,t",
12157 tempreg, tempreg, breg);
12158 macro_build (&offset_expr, s, fmt, op[0],
12159 BFD_RELOC_LO16, tempreg);
12162 if (mips_relax.sequence)
12169 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12170 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12172 relax_start (offset_expr.X_add_symbol);
12173 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
12177 macro_build_lui (&offset_expr, tempreg);
12178 macro_build (&offset_expr, s, fmt, op[0],
12179 BFD_RELOC_LO16, tempreg);
12180 if (mips_relax.sequence)
12185 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12186 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12188 relax_start (offset_expr.X_add_symbol);
12189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12190 tempreg, breg, mips_gp_register);
12191 macro_build (&offset_expr, s, fmt, op[0],
12192 BFD_RELOC_GPREL16, tempreg);
12195 macro_build_lui (&offset_expr, tempreg);
12196 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12197 tempreg, tempreg, breg);
12198 macro_build (&offset_expr, s, fmt, op[0],
12199 BFD_RELOC_LO16, tempreg);
12200 if (mips_relax.sequence)
12204 else if (!mips_big_got)
12206 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
12208 /* If this is a reference to an external symbol, we want
12209 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12211 <op> op[0],0($tempreg)
12213 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12215 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12216 <op> op[0],0($tempreg)
12218 For NewABI, we want
12219 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12220 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12222 If there is a base register, we add it to $tempreg before
12223 the <op>. If there is a constant, we stick it in the
12224 <op> instruction. We don't handle constants larger than
12225 16 bits, because we have no way to load the upper 16 bits
12226 (actually, we could handle them for the subset of cases
12227 in which we are not using $at). */
12228 gas_assert (offset_expr.X_op == O_symbol);
12231 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12232 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12234 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12235 tempreg, tempreg, breg);
12236 macro_build (&offset_expr, s, fmt, op[0],
12237 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12240 expr1.X_add_number = offset_expr.X_add_number;
12241 offset_expr.X_add_number = 0;
12242 if (expr1.X_add_number < -0x8000
12243 || expr1.X_add_number >= 0x8000)
12244 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12245 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12246 lw_reloc_type, mips_gp_register);
12248 relax_start (offset_expr.X_add_symbol);
12250 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12251 tempreg, BFD_RELOC_LO16);
12254 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12255 tempreg, tempreg, breg);
12256 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12258 else if (mips_big_got && !HAVE_NEWABI)
12262 /* If this is a reference to an external symbol, we want
12263 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12264 addu $tempreg,$tempreg,$gp
12265 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12266 <op> op[0],0($tempreg)
12268 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12270 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12271 <op> op[0],0($tempreg)
12272 If there is a base register, we add it to $tempreg before
12273 the <op>. If there is a constant, we stick it in the
12274 <op> instruction. We don't handle constants larger than
12275 16 bits, because we have no way to load the upper 16 bits
12276 (actually, we could handle them for the subset of cases
12277 in which we are not using $at). */
12278 gas_assert (offset_expr.X_op == O_symbol);
12279 expr1.X_add_number = offset_expr.X_add_number;
12280 offset_expr.X_add_number = 0;
12281 if (expr1.X_add_number < -0x8000
12282 || expr1.X_add_number >= 0x8000)
12283 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12284 gpdelay = reg_needs_delay (mips_gp_register);
12285 relax_start (offset_expr.X_add_symbol);
12286 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12287 BFD_RELOC_MIPS_GOT_HI16);
12288 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12290 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12291 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12294 macro_build (NULL, "nop", "");
12295 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12296 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12298 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12299 tempreg, BFD_RELOC_LO16);
12303 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12304 tempreg, tempreg, breg);
12305 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12307 else if (mips_big_got && HAVE_NEWABI)
12309 /* If this is a reference to an external symbol, we want
12310 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12311 add $tempreg,$tempreg,$gp
12312 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12313 <op> op[0],<ofst>($tempreg)
12314 Otherwise, for local symbols, we want:
12315 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12316 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12317 gas_assert (offset_expr.X_op == O_symbol);
12318 expr1.X_add_number = offset_expr.X_add_number;
12319 offset_expr.X_add_number = 0;
12320 if (expr1.X_add_number < -0x8000
12321 || expr1.X_add_number >= 0x8000)
12322 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12323 relax_start (offset_expr.X_add_symbol);
12324 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12325 BFD_RELOC_MIPS_GOT_HI16);
12326 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12328 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12329 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12331 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12332 tempreg, tempreg, breg);
12333 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12336 offset_expr.X_add_number = expr1.X_add_number;
12337 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12338 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12340 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12341 tempreg, tempreg, breg);
12342 macro_build (&offset_expr, s, fmt, op[0],
12343 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12352 gas_assert (mips_opts.micromips);
12353 gas_assert (mips_opts.insn32);
12354 start_noreorder ();
12355 macro_build (NULL, "jr", "s", RA);
12356 expr1.X_add_number = op[0] << 2;
12357 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12362 gas_assert (mips_opts.micromips);
12363 gas_assert (mips_opts.insn32);
12364 macro_build (NULL, "jr", "s", op[0]);
12365 if (mips_opts.noreorder)
12366 macro_build (NULL, "nop", "");
12371 load_register (op[0], &imm_expr, 0);
12375 load_register (op[0], &imm_expr, 1);
12379 if (imm_expr.X_op == O_constant)
12382 load_register (AT, &imm_expr, 0);
12383 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12388 gas_assert (imm_expr.X_op == O_absent
12389 && offset_expr.X_op == O_symbol
12390 && strcmp (segment_name (S_GET_SEGMENT
12391 (offset_expr.X_add_symbol)),
12393 && offset_expr.X_add_number == 0);
12394 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12395 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12400 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12401 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12402 order 32 bits of the value and the low order 32 bits are either
12403 zero or in OFFSET_EXPR. */
12404 if (imm_expr.X_op == O_constant)
12406 if (GPR_SIZE == 64)
12407 load_register (op[0], &imm_expr, 1);
12412 if (target_big_endian)
12424 load_register (hreg, &imm_expr, 0);
12427 if (offset_expr.X_op == O_absent)
12428 move_register (lreg, 0);
12431 gas_assert (offset_expr.X_op == O_constant);
12432 load_register (lreg, &offset_expr, 0);
12438 gas_assert (imm_expr.X_op == O_absent);
12440 /* We know that sym is in the .rdata section. First we get the
12441 upper 16 bits of the address. */
12442 if (mips_pic == NO_PIC)
12444 macro_build_lui (&offset_expr, AT);
12449 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12450 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12454 /* Now we load the register(s). */
12455 if (GPR_SIZE == 64)
12458 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12459 BFD_RELOC_LO16, AT);
12464 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12465 BFD_RELOC_LO16, AT);
12468 /* FIXME: How in the world do we deal with the possible
12470 offset_expr.X_add_number += 4;
12471 macro_build (&offset_expr, "lw", "t,o(b)",
12472 op[0] + 1, BFD_RELOC_LO16, AT);
12478 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12479 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12480 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12481 the value and the low order 32 bits are either zero or in
12483 if (imm_expr.X_op == O_constant)
12486 load_register (AT, &imm_expr, FPR_SIZE == 64);
12487 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12488 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12491 if (ISA_HAS_MXHC1 (mips_opts.isa))
12492 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12493 else if (FPR_SIZE != 32)
12494 as_bad (_("Unable to generate `%s' compliant code "
12496 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12498 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12499 if (offset_expr.X_op == O_absent)
12500 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12503 gas_assert (offset_expr.X_op == O_constant);
12504 load_register (AT, &offset_expr, 0);
12505 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12511 gas_assert (imm_expr.X_op == O_absent
12512 && offset_expr.X_op == O_symbol
12513 && offset_expr.X_add_number == 0);
12514 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12515 if (strcmp (s, ".lit8") == 0)
12517 op[2] = mips_gp_register;
12518 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12519 offset_reloc[1] = BFD_RELOC_UNUSED;
12520 offset_reloc[2] = BFD_RELOC_UNUSED;
12524 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12526 if (mips_pic != NO_PIC)
12527 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12528 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12531 /* FIXME: This won't work for a 64 bit address. */
12532 macro_build_lui (&offset_expr, AT);
12536 offset_reloc[0] = BFD_RELOC_LO16;
12537 offset_reloc[1] = BFD_RELOC_UNUSED;
12538 offset_reloc[2] = BFD_RELOC_UNUSED;
12545 * The MIPS assembler seems to check for X_add_number not
12546 * being double aligned and generating:
12547 * lui at,%hi(foo+1)
12549 * addiu at,at,%lo(foo+1)
12552 * But, the resulting address is the same after relocation so why
12553 * generate the extra instruction?
12555 /* Itbl support may require additional care here. */
12558 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12567 gas_assert (!mips_opts.micromips);
12568 /* Itbl support may require additional care here. */
12571 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12591 if (GPR_SIZE == 64)
12601 if (GPR_SIZE == 64)
12609 /* Even on a big endian machine $fn comes before $fn+1. We have
12610 to adjust when loading from memory. We set coproc if we must
12611 load $fn+1 first. */
12612 /* Itbl support may require additional care here. */
12613 if (!target_big_endian)
12617 if (small_offset_p (0, align, 16))
12620 if (!small_offset_p (4, align, 16))
12622 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12623 -1, offset_reloc[0], offset_reloc[1],
12625 expr1.X_add_number = 0;
12629 offset_reloc[0] = BFD_RELOC_LO16;
12630 offset_reloc[1] = BFD_RELOC_UNUSED;
12631 offset_reloc[2] = BFD_RELOC_UNUSED;
12633 if (strcmp (s, "lw") == 0 && op[0] == breg)
12635 ep->X_add_number += 4;
12636 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12637 offset_reloc[1], offset_reloc[2], breg);
12638 ep->X_add_number -= 4;
12639 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12640 offset_reloc[1], offset_reloc[2], breg);
12644 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12645 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12647 ep->X_add_number += 4;
12648 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12649 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12655 if (offset_expr.X_op != O_symbol
12656 && offset_expr.X_op != O_constant)
12658 as_bad (_("expression too complex"));
12659 offset_expr.X_op = O_constant;
12662 if (HAVE_32BIT_ADDRESSES
12663 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12667 sprintf_vma (value, offset_expr.X_add_number);
12668 as_bad (_("number (0x%s) larger than 32 bits"), value);
12671 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12673 /* If this is a reference to a GP relative symbol, we want
12674 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12675 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12676 If we have a base register, we use this
12678 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12679 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12680 If this is not a GP relative symbol, we want
12681 lui $at,<sym> (BFD_RELOC_HI16_S)
12682 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12683 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12684 If there is a base register, we add it to $at after the
12685 lui instruction. If there is a constant, we always use
12687 if (offset_expr.X_op == O_symbol
12688 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12689 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12691 relax_start (offset_expr.X_add_symbol);
12694 tempreg = mips_gp_register;
12698 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12699 AT, breg, mips_gp_register);
12704 /* Itbl support may require additional care here. */
12705 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12706 BFD_RELOC_GPREL16, tempreg);
12707 offset_expr.X_add_number += 4;
12709 /* Set mips_optimize to 2 to avoid inserting an
12711 hold_mips_optimize = mips_optimize;
12713 /* Itbl support may require additional care here. */
12714 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12715 BFD_RELOC_GPREL16, tempreg);
12716 mips_optimize = hold_mips_optimize;
12720 offset_expr.X_add_number -= 4;
12723 if (offset_high_part (offset_expr.X_add_number, 16)
12724 != offset_high_part (offset_expr.X_add_number + 4, 16))
12726 load_address (AT, &offset_expr, &used_at);
12727 offset_expr.X_op = O_constant;
12728 offset_expr.X_add_number = 0;
12731 macro_build_lui (&offset_expr, AT);
12733 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12734 /* Itbl support may require additional care here. */
12735 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12736 BFD_RELOC_LO16, AT);
12737 /* FIXME: How do we handle overflow here? */
12738 offset_expr.X_add_number += 4;
12739 /* Itbl support may require additional care here. */
12740 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12741 BFD_RELOC_LO16, AT);
12742 if (mips_relax.sequence)
12745 else if (!mips_big_got)
12747 /* If this is a reference to an external symbol, we want
12748 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12751 <op> op[0]+1,4($at)
12753 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12755 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12756 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12757 If there is a base register we add it to $at before the
12758 lwc1 instructions. If there is a constant we include it
12759 in the lwc1 instructions. */
12761 expr1.X_add_number = offset_expr.X_add_number;
12762 if (expr1.X_add_number < -0x8000
12763 || expr1.X_add_number >= 0x8000 - 4)
12764 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12765 load_got_offset (AT, &offset_expr);
12768 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12770 /* Set mips_optimize to 2 to avoid inserting an undesired
12772 hold_mips_optimize = mips_optimize;
12775 /* Itbl support may require additional care here. */
12776 relax_start (offset_expr.X_add_symbol);
12777 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12778 BFD_RELOC_LO16, AT);
12779 expr1.X_add_number += 4;
12780 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12781 BFD_RELOC_LO16, AT);
12783 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12784 BFD_RELOC_LO16, AT);
12785 offset_expr.X_add_number += 4;
12786 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12787 BFD_RELOC_LO16, AT);
12790 mips_optimize = hold_mips_optimize;
12792 else if (mips_big_got)
12796 /* If this is a reference to an external symbol, we want
12797 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12799 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12802 <op> op[0]+1,4($at)
12804 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12806 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12807 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12808 If there is a base register we add it to $at before the
12809 lwc1 instructions. If there is a constant we include it
12810 in the lwc1 instructions. */
12812 expr1.X_add_number = offset_expr.X_add_number;
12813 offset_expr.X_add_number = 0;
12814 if (expr1.X_add_number < -0x8000
12815 || expr1.X_add_number >= 0x8000 - 4)
12816 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12817 gpdelay = reg_needs_delay (mips_gp_register);
12818 relax_start (offset_expr.X_add_symbol);
12819 macro_build (&offset_expr, "lui", LUI_FMT,
12820 AT, BFD_RELOC_MIPS_GOT_HI16);
12821 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12822 AT, AT, mips_gp_register);
12823 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12824 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12827 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12828 /* Itbl support may require additional care here. */
12829 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12830 BFD_RELOC_LO16, AT);
12831 expr1.X_add_number += 4;
12833 /* Set mips_optimize to 2 to avoid inserting an undesired
12835 hold_mips_optimize = mips_optimize;
12837 /* Itbl support may require additional care here. */
12838 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12839 BFD_RELOC_LO16, AT);
12840 mips_optimize = hold_mips_optimize;
12841 expr1.X_add_number -= 4;
12844 offset_expr.X_add_number = expr1.X_add_number;
12846 macro_build (NULL, "nop", "");
12847 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12848 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12851 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12852 /* Itbl support may require additional care here. */
12853 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12854 BFD_RELOC_LO16, AT);
12855 offset_expr.X_add_number += 4;
12857 /* Set mips_optimize to 2 to avoid inserting an undesired
12859 hold_mips_optimize = mips_optimize;
12861 /* Itbl support may require additional care here. */
12862 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12863 BFD_RELOC_LO16, AT);
12864 mips_optimize = hold_mips_optimize;
12878 gas_assert (!mips_opts.micromips);
12883 /* New code added to support COPZ instructions.
12884 This code builds table entries out of the macros in mip_opcodes.
12885 R4000 uses interlocks to handle coproc delays.
12886 Other chips (like the R3000) require nops to be inserted for delays.
12888 FIXME: Currently, we require that the user handle delays.
12889 In order to fill delay slots for non-interlocked chips,
12890 we must have a way to specify delays based on the coprocessor.
12891 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12892 What are the side-effects of the cop instruction?
12893 What cache support might we have and what are its effects?
12894 Both coprocessor & memory require delays. how long???
12895 What registers are read/set/modified?
12897 If an itbl is provided to interpret cop instructions,
12898 this knowledge can be encoded in the itbl spec. */
12912 gas_assert (!mips_opts.micromips);
12913 /* For now we just do C (same as Cz). The parameter will be
12914 stored in insn_opcode by mips_ip. */
12915 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12919 move_register (op[0], op[1]);
12923 gas_assert (mips_opts.micromips);
12924 gas_assert (mips_opts.insn32);
12925 move_register (micromips_to_32_reg_h_map1[op[0]],
12926 micromips_to_32_reg_m_map[op[1]]);
12927 move_register (micromips_to_32_reg_h_map2[op[0]],
12928 micromips_to_32_reg_n_map[op[2]]);
12933 /* Fall through. */
12935 if (mips_opts.arch == CPU_R5900)
12936 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12940 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12941 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12947 /* Fall through. */
12949 /* The MIPS assembler some times generates shifts and adds. I'm
12950 not trying to be that fancy. GCC should do this for us
12953 load_register (AT, &imm_expr, dbl);
12954 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12955 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12960 /* Fall through. */
12967 /* Fall through. */
12970 start_noreorder ();
12973 load_register (AT, &imm_expr, dbl);
12974 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12975 op[1], imm ? AT : op[2]);
12976 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12977 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12978 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12980 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12983 if (mips_opts.micromips)
12984 micromips_label_expr (&label_expr);
12986 label_expr.X_add_number = 8;
12987 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12988 macro_build (NULL, "nop", "");
12989 macro_build (NULL, "break", BRK_FMT, 6);
12990 if (mips_opts.micromips)
12991 micromips_add_label ();
12994 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12999 /* Fall through. */
13006 /* Fall through. */
13009 start_noreorder ();
13012 load_register (AT, &imm_expr, dbl);
13013 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
13014 op[1], imm ? AT : op[2]);
13015 macro_build (NULL, "mfhi", MFHL_FMT, AT);
13016 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13018 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
13021 if (mips_opts.micromips)
13022 micromips_label_expr (&label_expr);
13024 label_expr.X_add_number = 8;
13025 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
13026 macro_build (NULL, "nop", "");
13027 macro_build (NULL, "break", BRK_FMT, 6);
13028 if (mips_opts.micromips)
13029 micromips_add_label ();
13035 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13037 if (op[0] == op[1])
13044 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
13045 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
13049 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13050 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
13051 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
13052 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13056 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13058 if (op[0] == op[1])
13065 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
13066 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
13070 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13071 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
13072 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
13073 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13082 rot = imm_expr.X_add_number & 0x3f;
13083 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13085 rot = (64 - rot) & 0x3f;
13087 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13089 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13094 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13097 l = (rot < 0x20) ? "dsll" : "dsll32";
13098 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
13101 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
13102 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13103 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13111 rot = imm_expr.X_add_number & 0x1f;
13112 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13114 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
13115 (32 - rot) & 0x1f);
13120 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13124 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
13125 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13126 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13131 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13133 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
13137 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13138 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
13139 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
13140 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13144 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13146 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
13150 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13151 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
13152 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
13153 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13162 rot = imm_expr.X_add_number & 0x3f;
13163 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13166 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13168 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13173 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13176 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
13177 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
13180 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
13181 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13182 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13190 rot = imm_expr.X_add_number & 0x1f;
13191 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13193 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
13198 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13202 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
13203 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13204 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13210 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
13211 else if (op[2] == 0)
13212 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13215 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13216 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13221 if (imm_expr.X_add_number == 0)
13223 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13228 as_warn (_("instruction %s: result is always false"),
13229 ip->insn_mo->name);
13230 move_register (op[0], 0);
13233 if (CPU_HAS_SEQ (mips_opts.arch)
13234 && -512 <= imm_expr.X_add_number
13235 && imm_expr.X_add_number < 512)
13237 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
13238 (int) imm_expr.X_add_number);
13241 if (imm_expr.X_add_number >= 0
13242 && imm_expr.X_add_number < 0x10000)
13243 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
13244 else if (imm_expr.X_add_number > -0x8000
13245 && imm_expr.X_add_number < 0)
13247 imm_expr.X_add_number = -imm_expr.X_add_number;
13248 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13249 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13251 else if (CPU_HAS_SEQ (mips_opts.arch))
13254 load_register (AT, &imm_expr, GPR_SIZE == 64);
13255 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
13260 load_register (AT, &imm_expr, GPR_SIZE == 64);
13261 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13264 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13267 case M_SGE: /* X >= Y <==> not (X < Y) */
13273 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
13274 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13277 case M_SGE_I: /* X >= I <==> not (X < I) */
13279 if (imm_expr.X_add_number >= -0x8000
13280 && imm_expr.X_add_number < 0x8000)
13281 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
13282 op[0], op[1], BFD_RELOC_LO16);
13285 load_register (AT, &imm_expr, GPR_SIZE == 64);
13286 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
13290 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13293 case M_SGT: /* X > Y <==> Y < X */
13299 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13302 case M_SGT_I: /* X > I <==> I < X */
13309 load_register (AT, &imm_expr, GPR_SIZE == 64);
13310 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13313 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
13319 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13320 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13323 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
13330 load_register (AT, &imm_expr, GPR_SIZE == 64);
13331 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13332 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13336 if (imm_expr.X_add_number >= -0x8000
13337 && imm_expr.X_add_number < 0x8000)
13339 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13344 load_register (AT, &imm_expr, GPR_SIZE == 64);
13345 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
13349 if (imm_expr.X_add_number >= -0x8000
13350 && imm_expr.X_add_number < 0x8000)
13352 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
13357 load_register (AT, &imm_expr, GPR_SIZE == 64);
13358 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13363 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13364 else if (op[2] == 0)
13365 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13368 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13369 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13374 if (imm_expr.X_add_number == 0)
13376 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13381 as_warn (_("instruction %s: result is always true"),
13382 ip->insn_mo->name);
13383 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13384 op[0], 0, BFD_RELOC_LO16);
13387 if (CPU_HAS_SEQ (mips_opts.arch)
13388 && -512 <= imm_expr.X_add_number
13389 && imm_expr.X_add_number < 512)
13391 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13392 (int) imm_expr.X_add_number);
13395 if (imm_expr.X_add_number >= 0
13396 && imm_expr.X_add_number < 0x10000)
13398 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13401 else if (imm_expr.X_add_number > -0x8000
13402 && imm_expr.X_add_number < 0)
13404 imm_expr.X_add_number = -imm_expr.X_add_number;
13405 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13406 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13408 else if (CPU_HAS_SEQ (mips_opts.arch))
13411 load_register (AT, &imm_expr, GPR_SIZE == 64);
13412 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13417 load_register (AT, &imm_expr, GPR_SIZE == 64);
13418 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13421 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13436 if (!mips_opts.micromips)
13438 if (imm_expr.X_add_number > -0x200
13439 && imm_expr.X_add_number <= 0x200)
13441 macro_build (NULL, s, "t,r,.", op[0], op[1],
13442 (int) -imm_expr.X_add_number);
13451 if (imm_expr.X_add_number > -0x8000
13452 && imm_expr.X_add_number <= 0x8000)
13454 imm_expr.X_add_number = -imm_expr.X_add_number;
13455 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13460 load_register (AT, &imm_expr, dbl);
13461 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13483 load_register (AT, &imm_expr, GPR_SIZE == 64);
13484 macro_build (NULL, s, "s,t", op[0], AT);
13489 gas_assert (!mips_opts.micromips);
13490 gas_assert (mips_opts.isa == ISA_MIPS1);
13494 * Is the double cfc1 instruction a bug in the mips assembler;
13495 * or is there a reason for it?
13497 start_noreorder ();
13498 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13499 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13500 macro_build (NULL, "nop", "");
13501 expr1.X_add_number = 3;
13502 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13503 expr1.X_add_number = 2;
13504 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13505 macro_build (NULL, "ctc1", "t,G", AT, RA);
13506 macro_build (NULL, "nop", "");
13507 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13509 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13510 macro_build (NULL, "nop", "");
13527 offbits = (mips_opts.micromips ? 12 : 16);
13533 offbits = (mips_opts.micromips ? 12 : 16);
13545 offbits = (mips_opts.micromips ? 12 : 16);
13552 offbits = (mips_opts.micromips ? 12 : 16);
13558 large_offset = !small_offset_p (off, align, offbits);
13560 expr1.X_add_number = 0;
13565 if (small_offset_p (0, align, 16))
13566 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13567 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13570 load_address (tempreg, ep, &used_at);
13572 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13573 tempreg, tempreg, breg);
13575 offset_reloc[0] = BFD_RELOC_LO16;
13576 offset_reloc[1] = BFD_RELOC_UNUSED;
13577 offset_reloc[2] = BFD_RELOC_UNUSED;
13582 else if (!ust && op[0] == breg)
13593 if (!target_big_endian)
13594 ep->X_add_number += off;
13596 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13598 macro_build (ep, s, "t,o(b)", tempreg, -1,
13599 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13601 if (!target_big_endian)
13602 ep->X_add_number -= off;
13604 ep->X_add_number += off;
13606 macro_build (NULL, s2, "t,~(b)",
13607 tempreg, (int) ep->X_add_number, breg);
13609 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13610 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13612 /* If necessary, move the result in tempreg to the final destination. */
13613 if (!ust && op[0] != tempreg)
13615 /* Protect second load's delay slot. */
13617 move_register (op[0], tempreg);
13623 if (target_big_endian == ust)
13624 ep->X_add_number += off;
13625 tempreg = ust || large_offset ? op[0] : AT;
13626 macro_build (ep, s, "t,o(b)", tempreg, -1,
13627 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13629 /* For halfword transfers we need a temporary register to shuffle
13630 bytes. Unfortunately for M_USH_A we have none available before
13631 the next store as AT holds the base address. We deal with this
13632 case by clobbering TREG and then restoring it as with ULH. */
13633 tempreg = ust == large_offset ? op[0] : AT;
13635 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13637 if (target_big_endian == ust)
13638 ep->X_add_number -= off;
13640 ep->X_add_number += off;
13641 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13642 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13644 /* For M_USH_A re-retrieve the LSB. */
13645 if (ust && large_offset)
13647 if (target_big_endian)
13648 ep->X_add_number += off;
13650 ep->X_add_number -= off;
13651 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13652 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13654 /* For ULH and M_USH_A OR the LSB in. */
13655 if (!ust || large_offset)
13657 tempreg = !large_offset ? AT : op[0];
13658 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13659 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13664 /* FIXME: Check if this is one of the itbl macros, since they
13665 are added dynamically. */
13666 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13669 if (!mips_opts.at && used_at)
13670 as_bad (_("macro used $at after \".set noat\""));
13673 /* Implement macros in mips16 mode. */
13676 mips16_macro (struct mips_cl_insn *ip)
13678 const struct mips_operand_array *operands;
13683 const char *s, *s2, *s3;
13684 unsigned int op[MAX_OPERANDS];
13687 mask = ip->insn_mo->mask;
13689 operands = insn_operands (ip);
13690 for (i = 0; i < MAX_OPERANDS; i++)
13691 if (operands->operand[i])
13692 op[i] = insn_extract_operand (ip, operands->operand[i]);
13696 expr1.X_op = O_constant;
13697 expr1.X_op_symbol = NULL;
13698 expr1.X_add_symbol = NULL;
13699 expr1.X_add_number = 1;
13710 /* Fall through. */
13716 /* Fall through. */
13720 start_noreorder ();
13721 macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]);
13722 expr1.X_add_number = 2;
13723 macro_build (&expr1, "bnez", "x,p", op[2]);
13724 macro_build (NULL, "break", "6", 7);
13726 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13727 since that causes an overflow. We should do that as well,
13728 but I don't see how to do the comparisons without a temporary
13731 macro_build (NULL, s, "x", op[0]);
13750 start_noreorder ();
13751 macro_build (NULL, s, ".,x,y", op[1], op[2]);
13752 expr1.X_add_number = 2;
13753 macro_build (&expr1, "bnez", "x,p", op[2]);
13754 macro_build (NULL, "break", "6", 7);
13756 macro_build (NULL, s2, "x", op[0]);
13761 /* Fall through. */
13763 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13764 macro_build (NULL, "mflo", "x", op[0]);
13772 imm_expr.X_add_number = -imm_expr.X_add_number;
13773 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]);
13777 imm_expr.X_add_number = -imm_expr.X_add_number;
13778 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13782 imm_expr.X_add_number = -imm_expr.X_add_number;
13783 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13805 goto do_reverse_branch;
13809 goto do_reverse_branch;
13821 goto do_reverse_branch;
13832 macro_build (NULL, s, "x,y", op[0], op[1]);
13833 macro_build (&offset_expr, s2, "p");
13860 goto do_addone_branch_i;
13865 goto do_addone_branch_i;
13880 goto do_addone_branch_i;
13886 do_addone_branch_i:
13887 ++imm_expr.X_add_number;
13890 macro_build (&imm_expr, s, s3, op[0]);
13891 macro_build (&offset_expr, s2, "p");
13895 expr1.X_add_number = 0;
13896 macro_build (&expr1, "slti", "x,8", op[1]);
13897 if (op[0] != op[1])
13898 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13899 expr1.X_add_number = 2;
13900 macro_build (&expr1, "bteqz", "p");
13901 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13906 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13907 opcode bits in *OPCODE_EXTRA. */
13909 static struct mips_opcode *
13910 mips_lookup_insn (struct hash_control *hash, const char *start,
13911 ssize_t length, unsigned int *opcode_extra)
13913 char *name, *dot, *p;
13914 unsigned int mask, suffix;
13916 struct mips_opcode *insn;
13918 /* Make a copy of the instruction so that we can fiddle with it. */
13919 name = xstrndup (start, length);
13921 /* Look up the instruction as-is. */
13922 insn = (struct mips_opcode *) hash_find (hash, name);
13926 dot = strchr (name, '.');
13929 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13930 p = mips_parse_vu0_channels (dot + 1, &mask);
13931 if (*p == 0 && mask != 0)
13934 insn = (struct mips_opcode *) hash_find (hash, name);
13936 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13938 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13944 if (mips_opts.micromips)
13946 /* See if there's an instruction size override suffix,
13947 either `16' or `32', at the end of the mnemonic proper,
13948 that defines the operation, i.e. before the first `.'
13949 character if any. Strip it and retry. */
13950 opend = dot != NULL ? dot - name : length;
13951 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13953 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13959 memcpy (name + opend - 2, name + opend, length - opend + 1);
13960 insn = (struct mips_opcode *) hash_find (hash, name);
13963 forced_insn_length = suffix;
13975 /* Assemble an instruction into its binary format. If the instruction
13976 is a macro, set imm_expr and offset_expr to the values associated
13977 with "I" and "A" operands respectively. Otherwise store the value
13978 of the relocatable field (if any) in offset_expr. In both cases
13979 set offset_reloc to the relocation operators applied to offset_expr. */
13982 mips_ip (char *str, struct mips_cl_insn *insn)
13984 const struct mips_opcode *first, *past;
13985 struct hash_control *hash;
13988 struct mips_operand_token *tokens;
13989 unsigned int opcode_extra;
13991 if (mips_opts.micromips)
13993 hash = micromips_op_hash;
13994 past = µmips_opcodes[bfd_micromips_num_opcodes];
13999 past = &mips_opcodes[NUMOPCODES];
14001 forced_insn_length = 0;
14004 /* We first try to match an instruction up to a space or to the end. */
14005 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
14008 first = mips_lookup_insn (hash, str, end, &opcode_extra);
14011 set_insn_error (0, _("unrecognized opcode"));
14015 if (strcmp (first->name, "li.s") == 0)
14017 else if (strcmp (first->name, "li.d") == 0)
14021 tokens = mips_parse_arguments (str + end, format);
14025 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
14026 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
14027 set_insn_error (0, _("invalid operands"));
14029 obstack_free (&mips_operand_tokens, tokens);
14032 /* As for mips_ip, but used when assembling MIPS16 code.
14033 Also set forced_insn_length to the resulting instruction size in
14034 bytes if the user explicitly requested a small or extended instruction. */
14037 mips16_ip (char *str, struct mips_cl_insn *insn)
14040 struct mips_opcode *first;
14041 struct mips_operand_token *tokens;
14044 for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s)
14066 else if (*s == 'e')
14073 else if (*s++ == ' ')
14075 set_insn_error (0, _("unrecognized opcode"));
14078 forced_insn_length = l;
14081 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
14086 set_insn_error (0, _("unrecognized opcode"));
14090 tokens = mips_parse_arguments (s, 0);
14094 if (!match_mips16_insns (insn, first, tokens))
14095 set_insn_error (0, _("invalid operands"));
14097 obstack_free (&mips_operand_tokens, tokens);
14100 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14101 NBITS is the number of significant bits in VAL. */
14103 static unsigned long
14104 mips16_immed_extend (offsetT val, unsigned int nbits)
14109 val &= (1U << nbits) - 1;
14110 if (nbits == 16 || nbits == 9)
14112 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14115 else if (nbits == 15)
14117 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14120 else if (nbits == 6)
14122 extval = ((val & 0x1f) << 6) | (val & 0x20);
14125 return (extval << 16) | val;
14128 /* Like decode_mips16_operand, but require the operand to be defined and
14129 require it to be an integer. */
14131 static const struct mips_int_operand *
14132 mips16_immed_operand (int type, bfd_boolean extended_p)
14134 const struct mips_operand *operand;
14136 operand = decode_mips16_operand (type, extended_p);
14137 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
14139 return (const struct mips_int_operand *) operand;
14142 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14145 mips16_immed_in_range_p (const struct mips_int_operand *operand,
14146 bfd_reloc_code_real_type reloc, offsetT sval)
14148 int min_val, max_val;
14150 min_val = mips_int_operand_min (operand);
14151 max_val = mips_int_operand_max (operand);
14152 if (reloc != BFD_RELOC_UNUSED)
14155 sval = SEXT_16BIT (sval);
14160 return (sval >= min_val
14162 && (sval & ((1 << operand->shift) - 1)) == 0);
14165 /* Install immediate value VAL into MIPS16 instruction *INSN,
14166 extending it if necessary. The instruction in *INSN may
14167 already be extended.
14169 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14170 if none. In the former case, VAL is a 16-bit number with no
14171 defined signedness.
14173 TYPE is the type of the immediate field. USER_INSN_LENGTH
14174 is the length that the user requested, or 0 if none. */
14177 mips16_immed (const char *file, unsigned int line, int type,
14178 bfd_reloc_code_real_type reloc, offsetT val,
14179 unsigned int user_insn_length, unsigned long *insn)
14181 const struct mips_int_operand *operand;
14182 unsigned int uval, length;
14184 operand = mips16_immed_operand (type, FALSE);
14185 if (!mips16_immed_in_range_p (operand, reloc, val))
14187 /* We need an extended instruction. */
14188 if (user_insn_length == 2)
14189 as_bad_where (file, line, _("invalid unextended operand value"));
14191 *insn |= MIPS16_EXTEND;
14193 else if (user_insn_length == 4)
14195 /* The operand doesn't force an unextended instruction to be extended.
14196 Warn if the user wanted an extended instruction anyway. */
14197 *insn |= MIPS16_EXTEND;
14198 as_warn_where (file, line,
14199 _("extended operand requested but not required"));
14202 length = mips16_opcode_length (*insn);
14205 operand = mips16_immed_operand (type, TRUE);
14206 if (!mips16_immed_in_range_p (operand, reloc, val))
14207 as_bad_where (file, line,
14208 _("operand value out of range for instruction"));
14210 uval = ((unsigned int) val >> operand->shift) - operand->bias;
14211 if (length == 2 || operand->root.lsb != 0)
14212 *insn = mips_insert_operand (&operand->root, *insn, uval);
14214 *insn |= mips16_immed_extend (uval, operand->root.size);
14217 struct percent_op_match
14220 bfd_reloc_code_real_type reloc;
14223 static const struct percent_op_match mips_percent_op[] =
14225 {"%lo", BFD_RELOC_LO16},
14226 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14227 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14228 {"%call16", BFD_RELOC_MIPS_CALL16},
14229 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14230 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14231 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14232 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14233 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14234 {"%got", BFD_RELOC_MIPS_GOT16},
14235 {"%gp_rel", BFD_RELOC_GPREL16},
14236 {"%gprel", BFD_RELOC_GPREL16},
14237 {"%half", BFD_RELOC_16},
14238 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14239 {"%higher", BFD_RELOC_MIPS_HIGHER},
14240 {"%neg", BFD_RELOC_MIPS_SUB},
14241 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14242 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14243 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14244 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14245 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14246 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14247 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14248 {"%hi", BFD_RELOC_HI16_S},
14249 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
14250 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
14253 static const struct percent_op_match mips16_percent_op[] =
14255 {"%lo", BFD_RELOC_MIPS16_LO16},
14256 {"%gp_rel", BFD_RELOC_MIPS16_GPREL},
14257 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14258 {"%got", BFD_RELOC_MIPS16_GOT16},
14259 {"%call16", BFD_RELOC_MIPS16_CALL16},
14260 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14261 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14262 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14263 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14264 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14265 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14266 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14267 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14271 /* Return true if *STR points to a relocation operator. When returning true,
14272 move *STR over the operator and store its relocation code in *RELOC.
14273 Leave both *STR and *RELOC alone when returning false. */
14276 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14278 const struct percent_op_match *percent_op;
14281 if (mips_opts.mips16)
14283 percent_op = mips16_percent_op;
14284 limit = ARRAY_SIZE (mips16_percent_op);
14288 percent_op = mips_percent_op;
14289 limit = ARRAY_SIZE (mips_percent_op);
14292 for (i = 0; i < limit; i++)
14293 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14295 int len = strlen (percent_op[i].str);
14297 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14300 *str += strlen (percent_op[i].str);
14301 *reloc = percent_op[i].reloc;
14303 /* Check whether the output BFD supports this relocation.
14304 If not, issue an error and fall back on something safe. */
14305 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14307 as_bad (_("relocation %s isn't supported by the current ABI"),
14308 percent_op[i].str);
14309 *reloc = BFD_RELOC_UNUSED;
14317 /* Parse string STR as a 16-bit relocatable operand. Store the
14318 expression in *EP and the relocations in the array starting
14319 at RELOC. Return the number of relocation operators used.
14321 On exit, EXPR_END points to the first character after the expression. */
14324 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14327 bfd_reloc_code_real_type reversed_reloc[3];
14328 size_t reloc_index, i;
14329 int crux_depth, str_depth;
14332 /* Search for the start of the main expression, recoding relocations
14333 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14334 of the main expression and with CRUX_DEPTH containing the number
14335 of open brackets at that point. */
14342 crux_depth = str_depth;
14344 /* Skip over whitespace and brackets, keeping count of the number
14346 while (*str == ' ' || *str == '\t' || *str == '(')
14351 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14352 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14354 my_getExpression (ep, crux);
14357 /* Match every open bracket. */
14358 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14362 if (crux_depth > 0)
14363 as_bad (_("unclosed '('"));
14367 if (reloc_index != 0)
14369 prev_reloc_op_frag = frag_now;
14370 for (i = 0; i < reloc_index; i++)
14371 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14374 return reloc_index;
14378 my_getExpression (expressionS *ep, char *str)
14382 save_in = input_line_pointer;
14383 input_line_pointer = str;
14385 expr_end = input_line_pointer;
14386 input_line_pointer = save_in;
14390 md_atof (int type, char *litP, int *sizeP)
14392 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14396 md_number_to_chars (char *buf, valueT val, int n)
14398 if (target_big_endian)
14399 number_to_chars_bigendian (buf, val, n);
14401 number_to_chars_littleendian (buf, val, n);
14404 static int support_64bit_objects(void)
14406 const char **list, **l;
14409 list = bfd_target_list ();
14410 for (l = list; *l != NULL; l++)
14411 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14412 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14414 yes = (*l != NULL);
14419 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14420 NEW_VALUE. Warn if another value was already specified. Note:
14421 we have to defer parsing the -march and -mtune arguments in order
14422 to handle 'from-abi' correctly, since the ABI might be specified
14423 in a later argument. */
14426 mips_set_option_string (const char **string_ptr, const char *new_value)
14428 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14429 as_warn (_("a different %s was already specified, is now %s"),
14430 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14433 *string_ptr = new_value;
14437 md_parse_option (int c, const char *arg)
14441 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14442 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14444 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14445 c == mips_ases[i].option_on);
14451 case OPTION_CONSTRUCT_FLOATS:
14452 mips_disable_float_construction = 0;
14455 case OPTION_NO_CONSTRUCT_FLOATS:
14456 mips_disable_float_construction = 1;
14468 target_big_endian = 1;
14472 target_big_endian = 0;
14478 else if (arg[0] == '0')
14480 else if (arg[0] == '1')
14490 mips_debug = atoi (arg);
14494 file_mips_opts.isa = ISA_MIPS1;
14498 file_mips_opts.isa = ISA_MIPS2;
14502 file_mips_opts.isa = ISA_MIPS3;
14506 file_mips_opts.isa = ISA_MIPS4;
14510 file_mips_opts.isa = ISA_MIPS5;
14513 case OPTION_MIPS32:
14514 file_mips_opts.isa = ISA_MIPS32;
14517 case OPTION_MIPS32R2:
14518 file_mips_opts.isa = ISA_MIPS32R2;
14521 case OPTION_MIPS32R3:
14522 file_mips_opts.isa = ISA_MIPS32R3;
14525 case OPTION_MIPS32R5:
14526 file_mips_opts.isa = ISA_MIPS32R5;
14529 case OPTION_MIPS32R6:
14530 file_mips_opts.isa = ISA_MIPS32R6;
14533 case OPTION_MIPS64R2:
14534 file_mips_opts.isa = ISA_MIPS64R2;
14537 case OPTION_MIPS64R3:
14538 file_mips_opts.isa = ISA_MIPS64R3;
14541 case OPTION_MIPS64R5:
14542 file_mips_opts.isa = ISA_MIPS64R5;
14545 case OPTION_MIPS64R6:
14546 file_mips_opts.isa = ISA_MIPS64R6;
14549 case OPTION_MIPS64:
14550 file_mips_opts.isa = ISA_MIPS64;
14554 mips_set_option_string (&mips_tune_string, arg);
14558 mips_set_option_string (&mips_arch_string, arg);
14562 mips_set_option_string (&mips_arch_string, "4650");
14563 mips_set_option_string (&mips_tune_string, "4650");
14566 case OPTION_NO_M4650:
14570 mips_set_option_string (&mips_arch_string, "4010");
14571 mips_set_option_string (&mips_tune_string, "4010");
14574 case OPTION_NO_M4010:
14578 mips_set_option_string (&mips_arch_string, "4100");
14579 mips_set_option_string (&mips_tune_string, "4100");
14582 case OPTION_NO_M4100:
14586 mips_set_option_string (&mips_arch_string, "3900");
14587 mips_set_option_string (&mips_tune_string, "3900");
14590 case OPTION_NO_M3900:
14593 case OPTION_MICROMIPS:
14594 if (file_mips_opts.mips16 == 1)
14596 as_bad (_("-mmicromips cannot be used with -mips16"));
14599 file_mips_opts.micromips = 1;
14600 mips_no_prev_insn ();
14603 case OPTION_NO_MICROMIPS:
14604 file_mips_opts.micromips = 0;
14605 mips_no_prev_insn ();
14608 case OPTION_MIPS16:
14609 if (file_mips_opts.micromips == 1)
14611 as_bad (_("-mips16 cannot be used with -micromips"));
14614 file_mips_opts.mips16 = 1;
14615 mips_no_prev_insn ();
14618 case OPTION_NO_MIPS16:
14619 file_mips_opts.mips16 = 0;
14620 mips_no_prev_insn ();
14623 case OPTION_FIX_24K:
14627 case OPTION_NO_FIX_24K:
14631 case OPTION_FIX_RM7000:
14632 mips_fix_rm7000 = 1;
14635 case OPTION_NO_FIX_RM7000:
14636 mips_fix_rm7000 = 0;
14639 case OPTION_FIX_LOONGSON2F_JUMP:
14640 mips_fix_loongson2f_jump = TRUE;
14643 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14644 mips_fix_loongson2f_jump = FALSE;
14647 case OPTION_FIX_LOONGSON2F_NOP:
14648 mips_fix_loongson2f_nop = TRUE;
14651 case OPTION_NO_FIX_LOONGSON2F_NOP:
14652 mips_fix_loongson2f_nop = FALSE;
14655 case OPTION_FIX_VR4120:
14656 mips_fix_vr4120 = 1;
14659 case OPTION_NO_FIX_VR4120:
14660 mips_fix_vr4120 = 0;
14663 case OPTION_FIX_VR4130:
14664 mips_fix_vr4130 = 1;
14667 case OPTION_NO_FIX_VR4130:
14668 mips_fix_vr4130 = 0;
14671 case OPTION_FIX_CN63XXP1:
14672 mips_fix_cn63xxp1 = TRUE;
14675 case OPTION_NO_FIX_CN63XXP1:
14676 mips_fix_cn63xxp1 = FALSE;
14679 case OPTION_RELAX_BRANCH:
14680 mips_relax_branch = 1;
14683 case OPTION_NO_RELAX_BRANCH:
14684 mips_relax_branch = 0;
14687 case OPTION_IGNORE_BRANCH_ISA:
14688 mips_ignore_branch_isa = TRUE;
14691 case OPTION_NO_IGNORE_BRANCH_ISA:
14692 mips_ignore_branch_isa = FALSE;
14695 case OPTION_INSN32:
14696 file_mips_opts.insn32 = TRUE;
14699 case OPTION_NO_INSN32:
14700 file_mips_opts.insn32 = FALSE;
14703 case OPTION_MSHARED:
14704 mips_in_shared = TRUE;
14707 case OPTION_MNO_SHARED:
14708 mips_in_shared = FALSE;
14711 case OPTION_MSYM32:
14712 file_mips_opts.sym32 = TRUE;
14715 case OPTION_MNO_SYM32:
14716 file_mips_opts.sym32 = FALSE;
14719 /* When generating ELF code, we permit -KPIC and -call_shared to
14720 select SVR4_PIC, and -non_shared to select no PIC. This is
14721 intended to be compatible with Irix 5. */
14722 case OPTION_CALL_SHARED:
14723 mips_pic = SVR4_PIC;
14724 mips_abicalls = TRUE;
14727 case OPTION_CALL_NONPIC:
14729 mips_abicalls = TRUE;
14732 case OPTION_NON_SHARED:
14734 mips_abicalls = FALSE;
14737 /* The -xgot option tells the assembler to use 32 bit offsets
14738 when accessing the got in SVR4_PIC mode. It is for Irix
14745 g_switch_value = atoi (arg);
14749 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14752 mips_abi = O32_ABI;
14756 mips_abi = N32_ABI;
14760 mips_abi = N64_ABI;
14761 if (!support_64bit_objects())
14762 as_fatal (_("no compiled in support for 64 bit object file format"));
14766 file_mips_opts.gp = 32;
14770 file_mips_opts.gp = 64;
14774 file_mips_opts.fp = 32;
14778 file_mips_opts.fp = 0;
14782 file_mips_opts.fp = 64;
14785 case OPTION_ODD_SPREG:
14786 file_mips_opts.oddspreg = 1;
14789 case OPTION_NO_ODD_SPREG:
14790 file_mips_opts.oddspreg = 0;
14793 case OPTION_SINGLE_FLOAT:
14794 file_mips_opts.single_float = 1;
14797 case OPTION_DOUBLE_FLOAT:
14798 file_mips_opts.single_float = 0;
14801 case OPTION_SOFT_FLOAT:
14802 file_mips_opts.soft_float = 1;
14805 case OPTION_HARD_FLOAT:
14806 file_mips_opts.soft_float = 0;
14810 if (strcmp (arg, "32") == 0)
14811 mips_abi = O32_ABI;
14812 else if (strcmp (arg, "o64") == 0)
14813 mips_abi = O64_ABI;
14814 else if (strcmp (arg, "n32") == 0)
14815 mips_abi = N32_ABI;
14816 else if (strcmp (arg, "64") == 0)
14818 mips_abi = N64_ABI;
14819 if (! support_64bit_objects())
14820 as_fatal (_("no compiled in support for 64 bit object file "
14823 else if (strcmp (arg, "eabi") == 0)
14824 mips_abi = EABI_ABI;
14827 as_fatal (_("invalid abi -mabi=%s"), arg);
14832 case OPTION_M7000_HILO_FIX:
14833 mips_7000_hilo_fix = TRUE;
14836 case OPTION_MNO_7000_HILO_FIX:
14837 mips_7000_hilo_fix = FALSE;
14840 case OPTION_MDEBUG:
14841 mips_flag_mdebug = TRUE;
14844 case OPTION_NO_MDEBUG:
14845 mips_flag_mdebug = FALSE;
14849 mips_flag_pdr = TRUE;
14852 case OPTION_NO_PDR:
14853 mips_flag_pdr = FALSE;
14856 case OPTION_MVXWORKS_PIC:
14857 mips_pic = VXWORKS_PIC;
14861 if (strcmp (arg, "2008") == 0)
14863 else if (strcmp (arg, "legacy") == 0)
14867 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14876 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14881 /* Set up globals to tune for the ISA or processor described by INFO. */
14884 mips_set_tune (const struct mips_cpu_info *info)
14887 mips_tune = info->cpu;
14892 mips_after_parse_args (void)
14894 const struct mips_cpu_info *arch_info = 0;
14895 const struct mips_cpu_info *tune_info = 0;
14897 /* GP relative stuff not working for PE */
14898 if (strncmp (TARGET_OS, "pe", 2) == 0)
14900 if (g_switch_seen && g_switch_value != 0)
14901 as_bad (_("-G not supported in this configuration"));
14902 g_switch_value = 0;
14905 if (mips_abi == NO_ABI)
14906 mips_abi = MIPS_DEFAULT_ABI;
14908 /* The following code determines the architecture.
14909 Similar code was added to GCC 3.3 (see override_options() in
14910 config/mips/mips.c). The GAS and GCC code should be kept in sync
14911 as much as possible. */
14913 if (mips_arch_string != 0)
14914 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14916 if (file_mips_opts.isa != ISA_UNKNOWN)
14918 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14919 ISA level specified by -mipsN, while arch_info->isa contains
14920 the -march selection (if any). */
14921 if (arch_info != 0)
14923 /* -march takes precedence over -mipsN, since it is more descriptive.
14924 There's no harm in specifying both as long as the ISA levels
14926 if (file_mips_opts.isa != arch_info->isa)
14927 as_bad (_("-%s conflicts with the other architecture options,"
14928 " which imply -%s"),
14929 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14930 mips_cpu_info_from_isa (arch_info->isa)->name);
14933 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14936 if (arch_info == 0)
14938 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14939 gas_assert (arch_info);
14942 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14943 as_bad (_("-march=%s is not compatible with the selected ABI"),
14946 file_mips_opts.arch = arch_info->cpu;
14947 file_mips_opts.isa = arch_info->isa;
14949 /* Set up initial mips_opts state. */
14950 mips_opts = file_mips_opts;
14952 /* The register size inference code is now placed in
14953 file_mips_check_options. */
14955 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14957 if (mips_tune_string != 0)
14958 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14960 if (tune_info == 0)
14961 mips_set_tune (arch_info);
14963 mips_set_tune (tune_info);
14965 if (mips_flag_mdebug < 0)
14966 mips_flag_mdebug = 0;
14970 mips_init_after_args (void)
14972 /* initialize opcodes */
14973 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14974 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14978 md_pcrel_from (fixS *fixP)
14980 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14981 switch (fixP->fx_r_type)
14983 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14984 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14985 /* Return the address of the delay slot. */
14988 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14989 case BFD_RELOC_MICROMIPS_JMP:
14990 case BFD_RELOC_MIPS16_16_PCREL_S1:
14991 case BFD_RELOC_16_PCREL_S2:
14992 case BFD_RELOC_MIPS_21_PCREL_S2:
14993 case BFD_RELOC_MIPS_26_PCREL_S2:
14994 case BFD_RELOC_MIPS_JMP:
14995 /* Return the address of the delay slot. */
14998 case BFD_RELOC_MIPS_18_PCREL_S3:
14999 /* Return the aligned address of the doubleword containing
15000 the instruction. */
15008 /* This is called before the symbol table is processed. In order to
15009 work with gcc when using mips-tfile, we must keep all local labels.
15010 However, in other cases, we want to discard them. If we were
15011 called with -g, but we didn't see any debugging information, it may
15012 mean that gcc is smuggling debugging information through to
15013 mips-tfile, in which case we must generate all local labels. */
15016 mips_frob_file_before_adjust (void)
15018 #ifndef NO_ECOFF_DEBUGGING
15019 if (ECOFF_DEBUGGING
15021 && ! ecoff_debugging_seen)
15022 flag_keep_locals = 1;
15026 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15027 the corresponding LO16 reloc. This is called before md_apply_fix and
15028 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15029 relocation operators.
15031 For our purposes, a %lo() expression matches a %got() or %hi()
15034 (a) it refers to the same symbol; and
15035 (b) the offset applied in the %lo() expression is no lower than
15036 the offset applied in the %got() or %hi().
15038 (b) allows us to cope with code like:
15041 lh $4,%lo(foo+2)($4)
15043 ...which is legal on RELA targets, and has a well-defined behaviour
15044 if the user knows that adding 2 to "foo" will not induce a carry to
15047 When several %lo()s match a particular %got() or %hi(), we use the
15048 following rules to distinguish them:
15050 (1) %lo()s with smaller offsets are a better match than %lo()s with
15053 (2) %lo()s with no matching %got() or %hi() are better than those
15054 that already have a matching %got() or %hi().
15056 (3) later %lo()s are better than earlier %lo()s.
15058 These rules are applied in order.
15060 (1) means, among other things, that %lo()s with identical offsets are
15061 chosen if they exist.
15063 (2) means that we won't associate several high-part relocations with
15064 the same low-part relocation unless there's no alternative. Having
15065 several high parts for the same low part is a GNU extension; this rule
15066 allows careful users to avoid it.
15068 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15069 with the last high-part relocation being at the front of the list.
15070 It therefore makes sense to choose the last matching low-part
15071 relocation, all other things being equal. It's also easier
15072 to code that way. */
15075 mips_frob_file (void)
15077 struct mips_hi_fixup *l;
15078 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15080 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15082 segment_info_type *seginfo;
15083 bfd_boolean matched_lo_p;
15084 fixS **hi_pos, **lo_pos, **pos;
15086 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15088 /* If a GOT16 relocation turns out to be against a global symbol,
15089 there isn't supposed to be a matching LO. Ignore %gots against
15090 constants; we'll report an error for those later. */
15091 if (got16_reloc_p (l->fixp->fx_r_type)
15092 && !(l->fixp->fx_addsy
15093 && pic_need_relax (l->fixp->fx_addsy)))
15096 /* Check quickly whether the next fixup happens to be a matching %lo. */
15097 if (fixup_has_matching_lo_p (l->fixp))
15100 seginfo = seg_info (l->seg);
15102 /* Set HI_POS to the position of this relocation in the chain.
15103 Set LO_POS to the position of the chosen low-part relocation.
15104 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15105 relocation that matches an immediately-preceding high-part
15109 matched_lo_p = FALSE;
15110 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15112 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15114 if (*pos == l->fixp)
15117 if ((*pos)->fx_r_type == looking_for_rtype
15118 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15119 && (*pos)->fx_offset >= l->fixp->fx_offset
15121 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15123 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15126 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15127 && fixup_has_matching_lo_p (*pos));
15130 /* If we found a match, remove the high-part relocation from its
15131 current position and insert it before the low-part relocation.
15132 Make the offsets match so that fixup_has_matching_lo_p()
15135 We don't warn about unmatched high-part relocations since some
15136 versions of gcc have been known to emit dead "lui ...%hi(...)"
15138 if (lo_pos != NULL)
15140 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15141 if (l->fixp->fx_next != *lo_pos)
15143 *hi_pos = l->fixp->fx_next;
15144 l->fixp->fx_next = *lo_pos;
15152 mips_force_relocation (fixS *fixp)
15154 if (generic_force_reloc (fixp))
15157 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15158 so that the linker relaxation can update targets. */
15159 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15160 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15161 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15164 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15165 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15166 microMIPS symbols so that we can do cross-mode branch diagnostics
15167 and BAL to JALX conversion by the linker. */
15168 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15169 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15170 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2)
15172 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy)))
15175 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15176 if (ISA_IS_R6 (file_mips_opts.isa)
15177 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15178 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15179 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
15180 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
15181 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
15182 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
15183 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
15189 /* Implement TC_FORCE_RELOCATION_ABS. */
15192 mips_force_relocation_abs (fixS *fixp)
15194 if (generic_force_reloc (fixp))
15197 /* These relocations do not have enough bits in the in-place addend
15198 to hold an arbitrary absolute section's offset. */
15199 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
15205 /* Read the instruction associated with RELOC from BUF. */
15207 static unsigned int
15208 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15210 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15211 return read_compressed_insn (buf, 4);
15213 return read_insn (buf);
15216 /* Write instruction INSN to BUF, given that it has been relocated
15220 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15221 unsigned long insn)
15223 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15224 write_compressed_insn (buf, insn, 4);
15226 write_insn (buf, insn);
15229 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15230 to a symbol in another ISA mode, which cannot be converted to JALX. */
15233 fix_bad_cross_mode_jump_p (fixS *fixP)
15235 unsigned long opcode;
15239 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15242 other = S_GET_OTHER (fixP->fx_addsy);
15243 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15244 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15245 switch (fixP->fx_r_type)
15247 case BFD_RELOC_MIPS_JMP:
15248 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other);
15249 case BFD_RELOC_MICROMIPS_JMP:
15250 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
15256 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15257 jump to a symbol in the same ISA mode. */
15260 fix_bad_same_mode_jalx_p (fixS *fixP)
15262 unsigned long opcode;
15266 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15269 other = S_GET_OTHER (fixP->fx_addsy);
15270 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15271 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15272 switch (fixP->fx_r_type)
15274 case BFD_RELOC_MIPS_JMP:
15275 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other);
15276 case BFD_RELOC_MIPS16_JMP:
15277 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other);
15278 case BFD_RELOC_MICROMIPS_JMP:
15279 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
15285 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15286 to a symbol whose value plus addend is not aligned according to the
15287 ultimate (after linker relaxation) jump instruction's immediate field
15288 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15289 regular MIPS code, to (1 << 2). */
15292 fix_bad_misaligned_jump_p (fixS *fixP, int shift)
15294 bfd_boolean micro_to_mips_p;
15298 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15301 other = S_GET_OTHER (fixP->fx_addsy);
15302 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
15303 val += fixP->fx_offset;
15304 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15305 && !ELF_ST_IS_MICROMIPS (other));
15306 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1))
15307 != ELF_ST_IS_COMPRESSED (other));
15310 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15311 to a symbol whose annotation indicates another ISA mode. For absolute
15312 symbols check the ISA bit instead.
15314 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15315 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15316 MIPS symbols and associated with BAL instructions as these instructions
15317 may be converted to JALX by the linker. */
15320 fix_bad_cross_mode_branch_p (fixS *fixP)
15322 bfd_boolean absolute_p;
15323 unsigned long opcode;
15329 if (mips_ignore_branch_isa)
15332 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15335 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15336 absolute_p = bfd_is_abs_section (symsec);
15338 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
15339 other = S_GET_OTHER (fixP->fx_addsy);
15341 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15342 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16;
15343 switch (fixP->fx_r_type)
15345 case BFD_RELOC_16_PCREL_S2:
15346 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other))
15347 && opcode != 0x0411);
15348 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15349 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
15350 && opcode != 0x4060);
15351 case BFD_RELOC_MIPS_21_PCREL_S2:
15352 case BFD_RELOC_MIPS_26_PCREL_S2:
15353 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
15354 case BFD_RELOC_MIPS16_16_PCREL_S1:
15355 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other);
15356 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15357 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15358 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
15364 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15365 branch instruction pointed to by FIXP is not aligned according to the
15366 branch instruction's immediate field requirement. We need the addend
15367 to preserve the ISA bit and also the sum must not have bit 2 set. We
15368 must explicitly OR in the ISA bit from symbol annotation as the bit
15369 won't be set in the symbol's value then. */
15372 fix_bad_misaligned_branch_p (fixS *fixP)
15374 bfd_boolean absolute_p;
15381 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
15384 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15385 absolute_p = bfd_is_abs_section (symsec);
15387 val = S_GET_VALUE (fixP->fx_addsy);
15388 other = S_GET_OTHER (fixP->fx_addsy);
15389 off = fixP->fx_offset;
15391 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other);
15392 val |= ELF_ST_IS_COMPRESSED (other);
15394 return (val & 0x3) != isa_bit;
15397 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15398 and its calculated value VAL. */
15401 fix_validate_branch (fixS *fixP, valueT val)
15403 if (fixP->fx_done && (val & 0x3) != 0)
15404 as_bad_where (fixP->fx_file, fixP->fx_line,
15405 _("branch to misaligned address (0x%lx)"),
15406 (long) (val + md_pcrel_from (fixP)));
15407 else if (fix_bad_cross_mode_branch_p (fixP))
15408 as_bad_where (fixP->fx_file, fixP->fx_line,
15409 _("branch to a symbol in another ISA mode"));
15410 else if (fix_bad_misaligned_branch_p (fixP))
15411 as_bad_where (fixP->fx_file, fixP->fx_line,
15412 _("branch to misaligned address (0x%lx)"),
15413 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15414 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0)
15415 as_bad_where (fixP->fx_file, fixP->fx_line,
15416 _("cannot encode misaligned addend "
15417 "in the relocatable field (0x%lx)"),
15418 (long) fixP->fx_offset);
15421 /* Apply a fixup to the object file. */
15424 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15427 unsigned long insn;
15428 reloc_howto_type *howto;
15430 if (fixP->fx_pcrel)
15431 switch (fixP->fx_r_type)
15433 case BFD_RELOC_16_PCREL_S2:
15434 case BFD_RELOC_MIPS16_16_PCREL_S1:
15435 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15436 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15437 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15438 case BFD_RELOC_32_PCREL:
15439 case BFD_RELOC_MIPS_21_PCREL_S2:
15440 case BFD_RELOC_MIPS_26_PCREL_S2:
15441 case BFD_RELOC_MIPS_18_PCREL_S3:
15442 case BFD_RELOC_MIPS_19_PCREL_S2:
15443 case BFD_RELOC_HI16_S_PCREL:
15444 case BFD_RELOC_LO16_PCREL:
15448 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15452 as_bad_where (fixP->fx_file, fixP->fx_line,
15453 _("PC-relative reference to a different section"));
15457 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15458 that have no MIPS ELF equivalent. */
15459 if (fixP->fx_r_type != BFD_RELOC_8)
15461 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15466 gas_assert (fixP->fx_size == 2
15467 || fixP->fx_size == 4
15468 || fixP->fx_r_type == BFD_RELOC_8
15469 || fixP->fx_r_type == BFD_RELOC_16
15470 || fixP->fx_r_type == BFD_RELOC_64
15471 || fixP->fx_r_type == BFD_RELOC_CTOR
15472 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15473 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15474 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15475 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15476 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
15477 || fixP->fx_r_type == BFD_RELOC_NONE);
15479 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15481 /* Don't treat parts of a composite relocation as done. There are two
15484 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15485 should nevertheless be emitted if the first part is.
15487 (2) In normal usage, composite relocations are never assembly-time
15488 constants. The easiest way of dealing with the pathological
15489 exceptions is to generate a relocation against STN_UNDEF and
15490 leave everything up to the linker. */
15491 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15494 switch (fixP->fx_r_type)
15496 case BFD_RELOC_MIPS_TLS_GD:
15497 case BFD_RELOC_MIPS_TLS_LDM:
15498 case BFD_RELOC_MIPS_TLS_DTPREL32:
15499 case BFD_RELOC_MIPS_TLS_DTPREL64:
15500 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15501 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15502 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15503 case BFD_RELOC_MIPS_TLS_TPREL32:
15504 case BFD_RELOC_MIPS_TLS_TPREL64:
15505 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15506 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15507 case BFD_RELOC_MICROMIPS_TLS_GD:
15508 case BFD_RELOC_MICROMIPS_TLS_LDM:
15509 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15510 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15511 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15512 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15513 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15514 case BFD_RELOC_MIPS16_TLS_GD:
15515 case BFD_RELOC_MIPS16_TLS_LDM:
15516 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15517 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15518 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15519 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15520 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15521 if (fixP->fx_addsy)
15522 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15524 as_bad_where (fixP->fx_file, fixP->fx_line,
15525 _("TLS relocation against a constant"));
15528 case BFD_RELOC_MIPS_JMP:
15529 case BFD_RELOC_MIPS16_JMP:
15530 case BFD_RELOC_MICROMIPS_JMP:
15534 gas_assert (!fixP->fx_done);
15536 /* Shift is 2, unusually, for microMIPS JALX. */
15537 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15538 && (read_compressed_insn (buf, 4) >> 26) != 0x3c)
15543 if (fix_bad_cross_mode_jump_p (fixP))
15544 as_bad_where (fixP->fx_file, fixP->fx_line,
15545 _("jump to a symbol in another ISA mode"));
15546 else if (fix_bad_same_mode_jalx_p (fixP))
15547 as_bad_where (fixP->fx_file, fixP->fx_line,
15548 _("JALX to a symbol in the same ISA mode"));
15549 else if (fix_bad_misaligned_jump_p (fixP, shift))
15550 as_bad_where (fixP->fx_file, fixP->fx_line,
15551 _("jump to misaligned address (0x%lx)"),
15552 (long) (S_GET_VALUE (fixP->fx_addsy)
15553 + fixP->fx_offset));
15554 else if (HAVE_IN_PLACE_ADDENDS
15555 && (fixP->fx_offset & ((1 << shift) - 1)) != 0)
15556 as_bad_where (fixP->fx_file, fixP->fx_line,
15557 _("cannot encode misaligned addend "
15558 "in the relocatable field (0x%lx)"),
15559 (long) fixP->fx_offset);
15561 /* Fall through. */
15563 case BFD_RELOC_MIPS_SHIFT5:
15564 case BFD_RELOC_MIPS_SHIFT6:
15565 case BFD_RELOC_MIPS_GOT_DISP:
15566 case BFD_RELOC_MIPS_GOT_PAGE:
15567 case BFD_RELOC_MIPS_GOT_OFST:
15568 case BFD_RELOC_MIPS_SUB:
15569 case BFD_RELOC_MIPS_INSERT_A:
15570 case BFD_RELOC_MIPS_INSERT_B:
15571 case BFD_RELOC_MIPS_DELETE:
15572 case BFD_RELOC_MIPS_HIGHEST:
15573 case BFD_RELOC_MIPS_HIGHER:
15574 case BFD_RELOC_MIPS_SCN_DISP:
15575 case BFD_RELOC_MIPS_REL16:
15576 case BFD_RELOC_MIPS_RELGOT:
15577 case BFD_RELOC_MIPS_JALR:
15578 case BFD_RELOC_HI16:
15579 case BFD_RELOC_HI16_S:
15580 case BFD_RELOC_LO16:
15581 case BFD_RELOC_GPREL16:
15582 case BFD_RELOC_MIPS_LITERAL:
15583 case BFD_RELOC_MIPS_CALL16:
15584 case BFD_RELOC_MIPS_GOT16:
15585 case BFD_RELOC_GPREL32:
15586 case BFD_RELOC_MIPS_GOT_HI16:
15587 case BFD_RELOC_MIPS_GOT_LO16:
15588 case BFD_RELOC_MIPS_CALL_HI16:
15589 case BFD_RELOC_MIPS_CALL_LO16:
15590 case BFD_RELOC_HI16_S_PCREL:
15591 case BFD_RELOC_LO16_PCREL:
15592 case BFD_RELOC_MIPS16_GPREL:
15593 case BFD_RELOC_MIPS16_GOT16:
15594 case BFD_RELOC_MIPS16_CALL16:
15595 case BFD_RELOC_MIPS16_HI16:
15596 case BFD_RELOC_MIPS16_HI16_S:
15597 case BFD_RELOC_MIPS16_LO16:
15598 case BFD_RELOC_MICROMIPS_GOT_DISP:
15599 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15600 case BFD_RELOC_MICROMIPS_GOT_OFST:
15601 case BFD_RELOC_MICROMIPS_SUB:
15602 case BFD_RELOC_MICROMIPS_HIGHEST:
15603 case BFD_RELOC_MICROMIPS_HIGHER:
15604 case BFD_RELOC_MICROMIPS_SCN_DISP:
15605 case BFD_RELOC_MICROMIPS_JALR:
15606 case BFD_RELOC_MICROMIPS_HI16:
15607 case BFD_RELOC_MICROMIPS_HI16_S:
15608 case BFD_RELOC_MICROMIPS_LO16:
15609 case BFD_RELOC_MICROMIPS_GPREL16:
15610 case BFD_RELOC_MICROMIPS_LITERAL:
15611 case BFD_RELOC_MICROMIPS_CALL16:
15612 case BFD_RELOC_MICROMIPS_GOT16:
15613 case BFD_RELOC_MICROMIPS_GOT_HI16:
15614 case BFD_RELOC_MICROMIPS_GOT_LO16:
15615 case BFD_RELOC_MICROMIPS_CALL_HI16:
15616 case BFD_RELOC_MICROMIPS_CALL_LO16:
15617 case BFD_RELOC_MIPS_EH:
15622 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15624 insn = read_reloc_insn (buf, fixP->fx_r_type);
15625 if (mips16_reloc_p (fixP->fx_r_type))
15626 insn |= mips16_immed_extend (value, 16);
15628 insn |= (value & 0xffff);
15629 write_reloc_insn (buf, fixP->fx_r_type, insn);
15632 as_bad_where (fixP->fx_file, fixP->fx_line,
15633 _("unsupported constant in relocation"));
15638 /* This is handled like BFD_RELOC_32, but we output a sign
15639 extended value if we are only 32 bits. */
15642 if (8 <= sizeof (valueT))
15643 md_number_to_chars (buf, *valP, 8);
15648 if ((*valP & 0x80000000) != 0)
15652 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15653 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15658 case BFD_RELOC_RVA:
15660 case BFD_RELOC_32_PCREL:
15663 /* If we are deleting this reloc entry, we must fill in the
15664 value now. This can happen if we have a .word which is not
15665 resolved when it appears but is later defined. */
15667 md_number_to_chars (buf, *valP, fixP->fx_size);
15670 case BFD_RELOC_MIPS_21_PCREL_S2:
15671 fix_validate_branch (fixP, *valP);
15672 if (!fixP->fx_done)
15675 if (*valP + 0x400000 <= 0x7fffff)
15677 insn = read_insn (buf);
15678 insn |= (*valP >> 2) & 0x1fffff;
15679 write_insn (buf, insn);
15682 as_bad_where (fixP->fx_file, fixP->fx_line,
15683 _("branch out of range"));
15686 case BFD_RELOC_MIPS_26_PCREL_S2:
15687 fix_validate_branch (fixP, *valP);
15688 if (!fixP->fx_done)
15691 if (*valP + 0x8000000 <= 0xfffffff)
15693 insn = read_insn (buf);
15694 insn |= (*valP >> 2) & 0x3ffffff;
15695 write_insn (buf, insn);
15698 as_bad_where (fixP->fx_file, fixP->fx_line,
15699 _("branch out of range"));
15702 case BFD_RELOC_MIPS_18_PCREL_S3:
15703 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15704 as_bad_where (fixP->fx_file, fixP->fx_line,
15705 _("PC-relative access using misaligned symbol (%lx)"),
15706 (long) S_GET_VALUE (fixP->fx_addsy));
15707 if ((fixP->fx_offset & 0x7) != 0)
15708 as_bad_where (fixP->fx_file, fixP->fx_line,
15709 _("PC-relative access using misaligned offset (%lx)"),
15710 (long) fixP->fx_offset);
15711 if (!fixP->fx_done)
15714 if (*valP + 0x100000 <= 0x1fffff)
15716 insn = read_insn (buf);
15717 insn |= (*valP >> 3) & 0x3ffff;
15718 write_insn (buf, insn);
15721 as_bad_where (fixP->fx_file, fixP->fx_line,
15722 _("PC-relative access out of range"));
15725 case BFD_RELOC_MIPS_19_PCREL_S2:
15726 if ((*valP & 0x3) != 0)
15727 as_bad_where (fixP->fx_file, fixP->fx_line,
15728 _("PC-relative access to misaligned address (%lx)"),
15730 if (!fixP->fx_done)
15733 if (*valP + 0x100000 <= 0x1fffff)
15735 insn = read_insn (buf);
15736 insn |= (*valP >> 2) & 0x7ffff;
15737 write_insn (buf, insn);
15740 as_bad_where (fixP->fx_file, fixP->fx_line,
15741 _("PC-relative access out of range"));
15744 case BFD_RELOC_16_PCREL_S2:
15745 fix_validate_branch (fixP, *valP);
15747 /* We need to save the bits in the instruction since fixup_segment()
15748 might be deleting the relocation entry (i.e., a branch within
15749 the current segment). */
15750 if (! fixP->fx_done)
15753 /* Update old instruction data. */
15754 insn = read_insn (buf);
15756 if (*valP + 0x20000 <= 0x3ffff)
15758 insn |= (*valP >> 2) & 0xffff;
15759 write_insn (buf, insn);
15761 else if (fixP->fx_tcbit2
15763 && fixP->fx_frag->fr_address >= text_section->vma
15764 && (fixP->fx_frag->fr_address
15765 < text_section->vma + bfd_get_section_size (text_section))
15766 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15767 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15768 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15770 /* The branch offset is too large. If this is an
15771 unconditional branch, and we are not generating PIC code,
15772 we can convert it to an absolute jump instruction. */
15773 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15774 insn = 0x0c000000; /* jal */
15776 insn = 0x08000000; /* j */
15777 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15779 fixP->fx_addsy = section_symbol (text_section);
15780 *valP += md_pcrel_from (fixP);
15781 write_insn (buf, insn);
15785 /* If we got here, we have branch-relaxation disabled,
15786 and there's nothing we can do to fix this instruction
15787 without turning it into a longer sequence. */
15788 as_bad_where (fixP->fx_file, fixP->fx_line,
15789 _("branch out of range"));
15793 case BFD_RELOC_MIPS16_16_PCREL_S1:
15794 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15795 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15796 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15797 gas_assert (!fixP->fx_done);
15798 if (fix_bad_cross_mode_branch_p (fixP))
15799 as_bad_where (fixP->fx_file, fixP->fx_line,
15800 _("branch to a symbol in another ISA mode"));
15801 else if (fixP->fx_addsy
15802 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
15803 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
15804 && (fixP->fx_offset & 0x1) != 0)
15805 as_bad_where (fixP->fx_file, fixP->fx_line,
15806 _("branch to misaligned address (0x%lx)"),
15807 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15808 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0)
15809 as_bad_where (fixP->fx_file, fixP->fx_line,
15810 _("cannot encode misaligned addend "
15811 "in the relocatable field (0x%lx)"),
15812 (long) fixP->fx_offset);
15815 case BFD_RELOC_VTABLE_INHERIT:
15818 && !S_IS_DEFINED (fixP->fx_addsy)
15819 && !S_IS_WEAK (fixP->fx_addsy))
15820 S_SET_WEAK (fixP->fx_addsy);
15823 case BFD_RELOC_NONE:
15824 case BFD_RELOC_VTABLE_ENTRY:
15832 /* Remember value for tc_gen_reloc. */
15833 fixP->fx_addnumber = *valP;
15843 c = get_symbol_name (&name);
15844 p = (symbolS *) symbol_find_or_make (name);
15845 (void) restore_line_pointer (c);
15849 /* Align the current frag to a given power of two. If a particular
15850 fill byte should be used, FILL points to an integer that contains
15851 that byte, otherwise FILL is null.
15853 This function used to have the comment:
15855 The MIPS assembler also automatically adjusts any preceding label.
15857 The implementation therefore applied the adjustment to a maximum of
15858 one label. However, other label adjustments are applied to batches
15859 of labels, and adjusting just one caused problems when new labels
15860 were added for the sake of debugging or unwind information.
15861 We therefore adjust all preceding labels (given as LABELS) instead. */
15864 mips_align (int to, int *fill, struct insn_label_list *labels)
15866 mips_emit_delays ();
15867 mips_record_compressed_mode ();
15868 if (fill == NULL && subseg_text_p (now_seg))
15869 frag_align_code (to, 0);
15871 frag_align (to, fill ? *fill : 0, 0);
15872 record_alignment (now_seg, to);
15873 mips_move_labels (labels, FALSE);
15876 /* Align to a given power of two. .align 0 turns off the automatic
15877 alignment used by the data creating pseudo-ops. */
15880 s_align (int x ATTRIBUTE_UNUSED)
15882 int temp, fill_value, *fill_ptr;
15883 long max_alignment = 28;
15885 /* o Note that the assembler pulls down any immediately preceding label
15886 to the aligned address.
15887 o It's not documented but auto alignment is reinstated by
15888 a .align pseudo instruction.
15889 o Note also that after auto alignment is turned off the mips assembler
15890 issues an error on attempt to assemble an improperly aligned data item.
15893 temp = get_absolute_expression ();
15894 if (temp > max_alignment)
15895 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15898 as_warn (_("alignment negative, 0 assumed"));
15901 if (*input_line_pointer == ',')
15903 ++input_line_pointer;
15904 fill_value = get_absolute_expression ();
15905 fill_ptr = &fill_value;
15911 segment_info_type *si = seg_info (now_seg);
15912 struct insn_label_list *l = si->label_list;
15913 /* Auto alignment should be switched on by next section change. */
15915 mips_align (temp, fill_ptr, l);
15922 demand_empty_rest_of_line ();
15926 s_change_sec (int sec)
15930 /* The ELF backend needs to know that we are changing sections, so
15931 that .previous works correctly. We could do something like check
15932 for an obj_section_change_hook macro, but that might be confusing
15933 as it would not be appropriate to use it in the section changing
15934 functions in read.c, since obj-elf.c intercepts those. FIXME:
15935 This should be cleaner, somehow. */
15936 obj_elf_section_change_hook ();
15938 mips_emit_delays ();
15949 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15950 demand_empty_rest_of_line ();
15954 seg = subseg_new (RDATA_SECTION_NAME,
15955 (subsegT) get_absolute_expression ());
15956 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15957 | SEC_READONLY | SEC_RELOC
15959 if (strncmp (TARGET_OS, "elf", 3) != 0)
15960 record_alignment (seg, 4);
15961 demand_empty_rest_of_line ();
15965 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15966 bfd_set_section_flags (stdoutput, seg,
15967 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15968 if (strncmp (TARGET_OS, "elf", 3) != 0)
15969 record_alignment (seg, 4);
15970 demand_empty_rest_of_line ();
15974 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15975 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15976 if (strncmp (TARGET_OS, "elf", 3) != 0)
15977 record_alignment (seg, 4);
15978 demand_empty_rest_of_line ();
15986 s_change_section (int ignore ATTRIBUTE_UNUSED)
15989 char *section_name;
15994 int section_entry_size;
15995 int section_alignment;
15997 saved_ilp = input_line_pointer;
15998 endc = get_symbol_name (§ion_name);
15999 c = (endc == '"' ? input_line_pointer[1] : endc);
16001 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
16003 /* Do we have .section Name<,"flags">? */
16004 if (c != ',' || (c == ',' && next_c == '"'))
16006 /* Just after name is now '\0'. */
16007 (void) restore_line_pointer (endc);
16008 input_line_pointer = saved_ilp;
16009 obj_elf_section (ignore);
16013 section_name = xstrdup (section_name);
16014 c = restore_line_pointer (endc);
16016 input_line_pointer++;
16018 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16020 section_type = get_absolute_expression ();
16024 if (*input_line_pointer++ == ',')
16025 section_flag = get_absolute_expression ();
16029 if (*input_line_pointer++ == ',')
16030 section_entry_size = get_absolute_expression ();
16032 section_entry_size = 0;
16034 if (*input_line_pointer++ == ',')
16035 section_alignment = get_absolute_expression ();
16037 section_alignment = 0;
16039 /* FIXME: really ignore? */
16040 (void) section_alignment;
16042 /* When using the generic form of .section (as implemented by obj-elf.c),
16043 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16044 traditionally had to fall back on the more common @progbits instead.
16046 There's nothing really harmful in this, since bfd will correct
16047 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16048 means that, for backwards compatibility, the special_section entries
16049 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16051 Even so, we shouldn't force users of the MIPS .section syntax to
16052 incorrectly label the sections as SHT_PROGBITS. The best compromise
16053 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16054 generic type-checking code. */
16055 if (section_type == SHT_MIPS_DWARF)
16056 section_type = SHT_PROGBITS;
16058 obj_elf_change_section (section_name, section_type, 0, section_flag,
16059 section_entry_size, 0, 0, 0);
16061 if (now_seg->name != section_name)
16062 free (section_name);
16066 mips_enable_auto_align (void)
16072 s_cons (int log_size)
16074 segment_info_type *si = seg_info (now_seg);
16075 struct insn_label_list *l = si->label_list;
16077 mips_emit_delays ();
16078 if (log_size > 0 && auto_align)
16079 mips_align (log_size, 0, l);
16080 cons (1 << log_size);
16081 mips_clear_insn_labels ();
16085 s_float_cons (int type)
16087 segment_info_type *si = seg_info (now_seg);
16088 struct insn_label_list *l = si->label_list;
16090 mips_emit_delays ();
16095 mips_align (3, 0, l);
16097 mips_align (2, 0, l);
16101 mips_clear_insn_labels ();
16104 /* Handle .globl. We need to override it because on Irix 5 you are
16107 where foo is an undefined symbol, to mean that foo should be
16108 considered to be the address of a function. */
16111 s_mips_globl (int x ATTRIBUTE_UNUSED)
16120 c = get_symbol_name (&name);
16121 symbolP = symbol_find_or_make (name);
16122 S_SET_EXTERNAL (symbolP);
16124 *input_line_pointer = c;
16125 SKIP_WHITESPACE_AFTER_NAME ();
16127 /* On Irix 5, every global symbol that is not explicitly labelled as
16128 being a function is apparently labelled as being an object. */
16131 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16132 && (*input_line_pointer != ','))
16137 c = get_symbol_name (&secname);
16138 sec = bfd_get_section_by_name (stdoutput, secname);
16140 as_bad (_("%s: no such section"), secname);
16141 (void) restore_line_pointer (c);
16143 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16144 flag = BSF_FUNCTION;
16147 symbol_get_bfdsym (symbolP)->flags |= flag;
16149 c = *input_line_pointer;
16152 input_line_pointer++;
16153 SKIP_WHITESPACE ();
16154 if (is_end_of_line[(unsigned char) *input_line_pointer])
16160 demand_empty_rest_of_line ();
16164 s_option (int x ATTRIBUTE_UNUSED)
16169 c = get_symbol_name (&opt);
16173 /* FIXME: What does this mean? */
16175 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
16179 i = atoi (opt + 3);
16180 if (i != 0 && i != 2)
16181 as_bad (_(".option pic%d not supported"), i);
16182 else if (mips_pic == VXWORKS_PIC)
16183 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
16188 mips_pic = SVR4_PIC;
16189 mips_abicalls = TRUE;
16192 if (mips_pic == SVR4_PIC)
16194 if (g_switch_seen && g_switch_value != 0)
16195 as_warn (_("-G may not be used with SVR4 PIC code"));
16196 g_switch_value = 0;
16197 bfd_set_gp_size (stdoutput, 0);
16201 as_warn (_("unrecognized option \"%s\""), opt);
16203 (void) restore_line_pointer (c);
16204 demand_empty_rest_of_line ();
16207 /* This structure is used to hold a stack of .set values. */
16209 struct mips_option_stack
16211 struct mips_option_stack *next;
16212 struct mips_set_options options;
16215 static struct mips_option_stack *mips_opts_stack;
16217 /* Return status for .set/.module option handling. */
16219 enum code_option_type
16221 /* Unrecognized option. */
16222 OPTION_TYPE_BAD = -1,
16224 /* Ordinary option. */
16225 OPTION_TYPE_NORMAL,
16227 /* ISA changing option. */
16231 /* Handle common .set/.module options. Return status indicating option
16234 static enum code_option_type
16235 parse_code_option (char * name)
16237 bfd_boolean isa_set = FALSE;
16238 const struct mips_ase *ase;
16240 if (strncmp (name, "at=", 3) == 0)
16242 char *s = name + 3;
16244 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16245 as_bad (_("unrecognized register name `%s'"), s);
16247 else if (strcmp (name, "at") == 0)
16248 mips_opts.at = ATREG;
16249 else if (strcmp (name, "noat") == 0)
16250 mips_opts.at = ZERO;
16251 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16252 mips_opts.nomove = 0;
16253 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16254 mips_opts.nomove = 1;
16255 else if (strcmp (name, "bopt") == 0)
16256 mips_opts.nobopt = 0;
16257 else if (strcmp (name, "nobopt") == 0)
16258 mips_opts.nobopt = 1;
16259 else if (strcmp (name, "gp=32") == 0)
16261 else if (strcmp (name, "gp=64") == 0)
16263 else if (strcmp (name, "fp=32") == 0)
16265 else if (strcmp (name, "fp=xx") == 0)
16267 else if (strcmp (name, "fp=64") == 0)
16269 else if (strcmp (name, "softfloat") == 0)
16270 mips_opts.soft_float = 1;
16271 else if (strcmp (name, "hardfloat") == 0)
16272 mips_opts.soft_float = 0;
16273 else if (strcmp (name, "singlefloat") == 0)
16274 mips_opts.single_float = 1;
16275 else if (strcmp (name, "doublefloat") == 0)
16276 mips_opts.single_float = 0;
16277 else if (strcmp (name, "nooddspreg") == 0)
16278 mips_opts.oddspreg = 0;
16279 else if (strcmp (name, "oddspreg") == 0)
16280 mips_opts.oddspreg = 1;
16281 else if (strcmp (name, "mips16") == 0
16282 || strcmp (name, "MIPS-16") == 0)
16283 mips_opts.mips16 = 1;
16284 else if (strcmp (name, "nomips16") == 0
16285 || strcmp (name, "noMIPS-16") == 0)
16286 mips_opts.mips16 = 0;
16287 else if (strcmp (name, "micromips") == 0)
16288 mips_opts.micromips = 1;
16289 else if (strcmp (name, "nomicromips") == 0)
16290 mips_opts.micromips = 0;
16291 else if (name[0] == 'n'
16293 && (ase = mips_lookup_ase (name + 2)))
16294 mips_set_ase (ase, &mips_opts, FALSE);
16295 else if ((ase = mips_lookup_ase (name)))
16296 mips_set_ase (ase, &mips_opts, TRUE);
16297 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16299 /* Permit the user to change the ISA and architecture on the fly.
16300 Needless to say, misuse can cause serious problems. */
16301 if (strncmp (name, "arch=", 5) == 0)
16303 const struct mips_cpu_info *p;
16305 p = mips_parse_cpu ("internal use", name + 5);
16307 as_bad (_("unknown architecture %s"), name + 5);
16310 mips_opts.arch = p->cpu;
16311 mips_opts.isa = p->isa;
16315 else if (strncmp (name, "mips", 4) == 0)
16317 const struct mips_cpu_info *p;
16319 p = mips_parse_cpu ("internal use", name);
16321 as_bad (_("unknown ISA level %s"), name + 4);
16324 mips_opts.arch = p->cpu;
16325 mips_opts.isa = p->isa;
16330 as_bad (_("unknown ISA or architecture %s"), name);
16332 else if (strcmp (name, "autoextend") == 0)
16333 mips_opts.noautoextend = 0;
16334 else if (strcmp (name, "noautoextend") == 0)
16335 mips_opts.noautoextend = 1;
16336 else if (strcmp (name, "insn32") == 0)
16337 mips_opts.insn32 = TRUE;
16338 else if (strcmp (name, "noinsn32") == 0)
16339 mips_opts.insn32 = FALSE;
16340 else if (strcmp (name, "sym32") == 0)
16341 mips_opts.sym32 = TRUE;
16342 else if (strcmp (name, "nosym32") == 0)
16343 mips_opts.sym32 = FALSE;
16345 return OPTION_TYPE_BAD;
16347 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
16350 /* Handle the .set pseudo-op. */
16353 s_mipsset (int x ATTRIBUTE_UNUSED)
16355 enum code_option_type type = OPTION_TYPE_NORMAL;
16356 char *name = input_line_pointer, ch;
16358 file_mips_check_options ();
16360 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16361 ++input_line_pointer;
16362 ch = *input_line_pointer;
16363 *input_line_pointer = '\0';
16365 if (strchr (name, ','))
16367 /* Generic ".set" directive; use the generic handler. */
16368 *input_line_pointer = ch;
16369 input_line_pointer = name;
16374 if (strcmp (name, "reorder") == 0)
16376 if (mips_opts.noreorder)
16379 else if (strcmp (name, "noreorder") == 0)
16381 if (!mips_opts.noreorder)
16382 start_noreorder ();
16384 else if (strcmp (name, "macro") == 0)
16385 mips_opts.warn_about_macros = 0;
16386 else if (strcmp (name, "nomacro") == 0)
16388 if (mips_opts.noreorder == 0)
16389 as_bad (_("`noreorder' must be set before `nomacro'"));
16390 mips_opts.warn_about_macros = 1;
16392 else if (strcmp (name, "gp=default") == 0)
16393 mips_opts.gp = file_mips_opts.gp;
16394 else if (strcmp (name, "fp=default") == 0)
16395 mips_opts.fp = file_mips_opts.fp;
16396 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16398 mips_opts.isa = file_mips_opts.isa;
16399 mips_opts.arch = file_mips_opts.arch;
16400 mips_opts.gp = file_mips_opts.gp;
16401 mips_opts.fp = file_mips_opts.fp;
16403 else if (strcmp (name, "push") == 0)
16405 struct mips_option_stack *s;
16407 s = XNEW (struct mips_option_stack);
16408 s->next = mips_opts_stack;
16409 s->options = mips_opts;
16410 mips_opts_stack = s;
16412 else if (strcmp (name, "pop") == 0)
16414 struct mips_option_stack *s;
16416 s = mips_opts_stack;
16418 as_bad (_(".set pop with no .set push"));
16421 /* If we're changing the reorder mode we need to handle
16422 delay slots correctly. */
16423 if (s->options.noreorder && ! mips_opts.noreorder)
16424 start_noreorder ();
16425 else if (! s->options.noreorder && mips_opts.noreorder)
16428 mips_opts = s->options;
16429 mips_opts_stack = s->next;
16435 type = parse_code_option (name);
16436 if (type == OPTION_TYPE_BAD)
16437 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
16440 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16441 registers based on what is supported by the arch/cpu. */
16442 if (type == OPTION_TYPE_ISA)
16444 switch (mips_opts.isa)
16449 /* MIPS I cannot support FPXX. */
16451 /* fall-through. */
16458 if (mips_opts.fp != 0)
16474 if (mips_opts.fp != 0)
16476 if (mips_opts.arch == CPU_R5900)
16483 as_bad (_("unknown ISA level %s"), name + 4);
16488 mips_check_options (&mips_opts, FALSE);
16490 mips_check_isa_supports_ases ();
16491 *input_line_pointer = ch;
16492 demand_empty_rest_of_line ();
16495 /* Handle the .module pseudo-op. */
16498 s_module (int ignore ATTRIBUTE_UNUSED)
16500 char *name = input_line_pointer, ch;
16502 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16503 ++input_line_pointer;
16504 ch = *input_line_pointer;
16505 *input_line_pointer = '\0';
16507 if (!file_mips_opts_checked)
16509 if (parse_code_option (name) == OPTION_TYPE_BAD)
16510 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
16512 /* Update module level settings from mips_opts. */
16513 file_mips_opts = mips_opts;
16516 as_bad (_(".module is not permitted after generating code"));
16518 *input_line_pointer = ch;
16519 demand_empty_rest_of_line ();
16522 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16523 .option pic2. It means to generate SVR4 PIC calls. */
16526 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16528 mips_pic = SVR4_PIC;
16529 mips_abicalls = TRUE;
16531 if (g_switch_seen && g_switch_value != 0)
16532 as_warn (_("-G may not be used with SVR4 PIC code"));
16533 g_switch_value = 0;
16535 bfd_set_gp_size (stdoutput, 0);
16536 demand_empty_rest_of_line ();
16539 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16540 PIC code. It sets the $gp register for the function based on the
16541 function address, which is in the register named in the argument.
16542 This uses a relocation against _gp_disp, which is handled specially
16543 by the linker. The result is:
16544 lui $gp,%hi(_gp_disp)
16545 addiu $gp,$gp,%lo(_gp_disp)
16546 addu $gp,$gp,.cpload argument
16547 The .cpload argument is normally $25 == $t9.
16549 The -mno-shared option changes this to:
16550 lui $gp,%hi(__gnu_local_gp)
16551 addiu $gp,$gp,%lo(__gnu_local_gp)
16552 and the argument is ignored. This saves an instruction, but the
16553 resulting code is not position independent; it uses an absolute
16554 address for __gnu_local_gp. Thus code assembled with -mno-shared
16555 can go into an ordinary executable, but not into a shared library. */
16558 s_cpload (int ignore ATTRIBUTE_UNUSED)
16564 file_mips_check_options ();
16566 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16567 .cpload is ignored. */
16568 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16574 if (mips_opts.mips16)
16576 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16577 ignore_rest_of_line ();
16581 /* .cpload should be in a .set noreorder section. */
16582 if (mips_opts.noreorder == 0)
16583 as_warn (_(".cpload not in noreorder section"));
16585 reg = tc_get_register (0);
16587 /* If we need to produce a 64-bit address, we are better off using
16588 the default instruction sequence. */
16589 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16591 ex.X_op = O_symbol;
16592 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16594 ex.X_op_symbol = NULL;
16595 ex.X_add_number = 0;
16597 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16598 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16600 mips_mark_labels ();
16601 mips_assembling_insn = TRUE;
16604 macro_build_lui (&ex, mips_gp_register);
16605 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16606 mips_gp_register, BFD_RELOC_LO16);
16608 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16609 mips_gp_register, reg);
16612 mips_assembling_insn = FALSE;
16613 demand_empty_rest_of_line ();
16616 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16617 .cpsetup $reg1, offset|$reg2, label
16619 If offset is given, this results in:
16620 sd $gp, offset($sp)
16621 lui $gp, %hi(%neg(%gp_rel(label)))
16622 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16623 daddu $gp, $gp, $reg1
16625 If $reg2 is given, this results in:
16627 lui $gp, %hi(%neg(%gp_rel(label)))
16628 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16629 daddu $gp, $gp, $reg1
16630 $reg1 is normally $25 == $t9.
16632 The -mno-shared option replaces the last three instructions with
16634 addiu $gp,$gp,%lo(_gp) */
16637 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16639 expressionS ex_off;
16640 expressionS ex_sym;
16643 file_mips_check_options ();
16645 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16646 We also need NewABI support. */
16647 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16653 if (mips_opts.mips16)
16655 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16656 ignore_rest_of_line ();
16660 reg1 = tc_get_register (0);
16661 SKIP_WHITESPACE ();
16662 if (*input_line_pointer != ',')
16664 as_bad (_("missing argument separator ',' for .cpsetup"));
16668 ++input_line_pointer;
16669 SKIP_WHITESPACE ();
16670 if (*input_line_pointer == '$')
16672 mips_cpreturn_register = tc_get_register (0);
16673 mips_cpreturn_offset = -1;
16677 mips_cpreturn_offset = get_absolute_expression ();
16678 mips_cpreturn_register = -1;
16680 SKIP_WHITESPACE ();
16681 if (*input_line_pointer != ',')
16683 as_bad (_("missing argument separator ',' for .cpsetup"));
16687 ++input_line_pointer;
16688 SKIP_WHITESPACE ();
16689 expression (&ex_sym);
16691 mips_mark_labels ();
16692 mips_assembling_insn = TRUE;
16695 if (mips_cpreturn_register == -1)
16697 ex_off.X_op = O_constant;
16698 ex_off.X_add_symbol = NULL;
16699 ex_off.X_op_symbol = NULL;
16700 ex_off.X_add_number = mips_cpreturn_offset;
16702 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16703 BFD_RELOC_LO16, SP);
16706 move_register (mips_cpreturn_register, mips_gp_register);
16708 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16710 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16711 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16714 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16715 mips_gp_register, -1, BFD_RELOC_GPREL16,
16716 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16718 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16719 mips_gp_register, reg1);
16725 ex.X_op = O_symbol;
16726 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16727 ex.X_op_symbol = NULL;
16728 ex.X_add_number = 0;
16730 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16731 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16733 macro_build_lui (&ex, mips_gp_register);
16734 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16735 mips_gp_register, BFD_RELOC_LO16);
16740 mips_assembling_insn = FALSE;
16741 demand_empty_rest_of_line ();
16745 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16747 file_mips_check_options ();
16749 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16750 .cplocal is ignored. */
16751 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16757 if (mips_opts.mips16)
16759 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16760 ignore_rest_of_line ();
16764 mips_gp_register = tc_get_register (0);
16765 demand_empty_rest_of_line ();
16768 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16769 offset from $sp. The offset is remembered, and after making a PIC
16770 call $gp is restored from that location. */
16773 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16777 file_mips_check_options ();
16779 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16780 .cprestore is ignored. */
16781 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16787 if (mips_opts.mips16)
16789 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16790 ignore_rest_of_line ();
16794 mips_cprestore_offset = get_absolute_expression ();
16795 mips_cprestore_valid = 1;
16797 ex.X_op = O_constant;
16798 ex.X_add_symbol = NULL;
16799 ex.X_op_symbol = NULL;
16800 ex.X_add_number = mips_cprestore_offset;
16802 mips_mark_labels ();
16803 mips_assembling_insn = TRUE;
16806 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16807 SP, HAVE_64BIT_ADDRESSES);
16810 mips_assembling_insn = FALSE;
16811 demand_empty_rest_of_line ();
16814 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16815 was given in the preceding .cpsetup, it results in:
16816 ld $gp, offset($sp)
16818 If a register $reg2 was given there, it results in:
16819 or $gp, $reg2, $0 */
16822 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16826 file_mips_check_options ();
16828 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16829 We also need NewABI support. */
16830 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16836 if (mips_opts.mips16)
16838 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16839 ignore_rest_of_line ();
16843 mips_mark_labels ();
16844 mips_assembling_insn = TRUE;
16847 if (mips_cpreturn_register == -1)
16849 ex.X_op = O_constant;
16850 ex.X_add_symbol = NULL;
16851 ex.X_op_symbol = NULL;
16852 ex.X_add_number = mips_cpreturn_offset;
16854 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16857 move_register (mips_gp_register, mips_cpreturn_register);
16861 mips_assembling_insn = FALSE;
16862 demand_empty_rest_of_line ();
16865 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16866 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16867 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16868 debug information or MIPS16 TLS. */
16871 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16872 bfd_reloc_code_real_type rtype)
16879 if (ex.X_op != O_symbol)
16881 as_bad (_("unsupported use of %s"), dirstr);
16882 ignore_rest_of_line ();
16885 p = frag_more (bytes);
16886 md_number_to_chars (p, 0, bytes);
16887 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16888 demand_empty_rest_of_line ();
16889 mips_clear_insn_labels ();
16892 /* Handle .dtprelword. */
16895 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16897 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16900 /* Handle .dtpreldword. */
16903 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16905 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16908 /* Handle .tprelword. */
16911 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16913 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16916 /* Handle .tpreldword. */
16919 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16921 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16924 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16925 code. It sets the offset to use in gp_rel relocations. */
16928 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16930 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16931 We also need NewABI support. */
16932 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16938 mips_gprel_offset = get_absolute_expression ();
16940 demand_empty_rest_of_line ();
16943 /* Handle the .gpword pseudo-op. This is used when generating PIC
16944 code. It generates a 32 bit GP relative reloc. */
16947 s_gpword (int ignore ATTRIBUTE_UNUSED)
16949 segment_info_type *si;
16950 struct insn_label_list *l;
16954 /* When not generating PIC code, this is treated as .word. */
16955 if (mips_pic != SVR4_PIC)
16961 si = seg_info (now_seg);
16962 l = si->label_list;
16963 mips_emit_delays ();
16965 mips_align (2, 0, l);
16968 mips_clear_insn_labels ();
16970 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16972 as_bad (_("unsupported use of .gpword"));
16973 ignore_rest_of_line ();
16977 md_number_to_chars (p, 0, 4);
16978 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16979 BFD_RELOC_GPREL32);
16981 demand_empty_rest_of_line ();
16985 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16987 segment_info_type *si;
16988 struct insn_label_list *l;
16992 /* When not generating PIC code, this is treated as .dword. */
16993 if (mips_pic != SVR4_PIC)
16999 si = seg_info (now_seg);
17000 l = si->label_list;
17001 mips_emit_delays ();
17003 mips_align (3, 0, l);
17006 mips_clear_insn_labels ();
17008 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17010 as_bad (_("unsupported use of .gpdword"));
17011 ignore_rest_of_line ();
17015 md_number_to_chars (p, 0, 8);
17016 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17017 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17019 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17020 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17021 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17023 demand_empty_rest_of_line ();
17026 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17027 tables. It generates a R_MIPS_EH reloc. */
17030 s_ehword (int ignore ATTRIBUTE_UNUSED)
17035 mips_emit_delays ();
17038 mips_clear_insn_labels ();
17040 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17042 as_bad (_("unsupported use of .ehword"));
17043 ignore_rest_of_line ();
17047 md_number_to_chars (p, 0, 4);
17048 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17049 BFD_RELOC_32_PCREL);
17051 demand_empty_rest_of_line ();
17054 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17055 tables in SVR4 PIC code. */
17058 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17062 file_mips_check_options ();
17064 /* This is ignored when not generating SVR4 PIC code. */
17065 if (mips_pic != SVR4_PIC)
17071 mips_mark_labels ();
17072 mips_assembling_insn = TRUE;
17074 /* Add $gp to the register named as an argument. */
17076 reg = tc_get_register (0);
17077 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17080 mips_assembling_insn = FALSE;
17081 demand_empty_rest_of_line ();
17084 /* Handle the .insn pseudo-op. This marks instruction labels in
17085 mips16/micromips mode. This permits the linker to handle them specially,
17086 such as generating jalx instructions when needed. We also make
17087 them odd for the duration of the assembly, in order to generate the
17088 right sort of code. We will make them even in the adjust_symtab
17089 routine, while leaving them marked. This is convenient for the
17090 debugger and the disassembler. The linker knows to make them odd
17094 s_insn (int ignore ATTRIBUTE_UNUSED)
17096 file_mips_check_options ();
17097 file_ase_mips16 |= mips_opts.mips16;
17098 file_ase_micromips |= mips_opts.micromips;
17100 mips_mark_labels ();
17102 demand_empty_rest_of_line ();
17105 /* Handle the .nan pseudo-op. */
17108 s_nan (int ignore ATTRIBUTE_UNUSED)
17110 static const char str_legacy[] = "legacy";
17111 static const char str_2008[] = "2008";
17114 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17116 if (i == sizeof (str_2008) - 1
17117 && memcmp (input_line_pointer, str_2008, i) == 0)
17119 else if (i == sizeof (str_legacy) - 1
17120 && memcmp (input_line_pointer, str_legacy, i) == 0)
17122 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
17125 as_bad (_("`%s' does not support legacy NaN"),
17126 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
17129 as_bad (_("bad .nan directive"));
17131 input_line_pointer += i;
17132 demand_empty_rest_of_line ();
17135 /* Handle a .stab[snd] directive. Ideally these directives would be
17136 implemented in a transparent way, so that removing them would not
17137 have any effect on the generated instructions. However, s_stab
17138 internally changes the section, so in practice we need to decide
17139 now whether the preceding label marks compressed code. We do not
17140 support changing the compression mode of a label after a .stab*
17141 directive, such as in:
17147 so the current mode wins. */
17150 s_mips_stab (int type)
17152 file_mips_check_options ();
17153 mips_mark_labels ();
17157 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17160 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17167 c = get_symbol_name (&name);
17168 symbolP = symbol_find_or_make (name);
17169 S_SET_WEAK (symbolP);
17170 *input_line_pointer = c;
17172 SKIP_WHITESPACE_AFTER_NAME ();
17174 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17176 if (S_IS_DEFINED (symbolP))
17178 as_bad (_("ignoring attempt to redefine symbol %s"),
17179 S_GET_NAME (symbolP));
17180 ignore_rest_of_line ();
17184 if (*input_line_pointer == ',')
17186 ++input_line_pointer;
17187 SKIP_WHITESPACE ();
17191 if (exp.X_op != O_symbol)
17193 as_bad (_("bad .weakext directive"));
17194 ignore_rest_of_line ();
17197 symbol_set_value_expression (symbolP, &exp);
17200 demand_empty_rest_of_line ();
17203 /* Parse a register string into a number. Called from the ECOFF code
17204 to parse .frame. The argument is non-zero if this is the frame
17205 register, so that we can record it in mips_frame_reg. */
17208 tc_get_register (int frame)
17212 SKIP_WHITESPACE ();
17213 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17217 mips_frame_reg = reg != 0 ? reg : SP;
17218 mips_frame_reg_valid = 1;
17219 mips_cprestore_valid = 0;
17225 md_section_align (asection *seg, valueT addr)
17227 int align = bfd_get_section_alignment (stdoutput, seg);
17229 /* We don't need to align ELF sections to the full alignment.
17230 However, Irix 5 may prefer that we align them at least to a 16
17231 byte boundary. We don't bother to align the sections if we
17232 are targeted for an embedded system. */
17233 if (strncmp (TARGET_OS, "elf", 3) == 0)
17238 return ((addr + (1 << align) - 1) & -(1 << align));
17241 /* Utility routine, called from above as well. If called while the
17242 input file is still being read, it's only an approximation. (For
17243 example, a symbol may later become defined which appeared to be
17244 undefined earlier.) */
17247 nopic_need_relax (symbolS *sym, int before_relaxing)
17252 if (g_switch_value > 0)
17254 const char *symname;
17257 /* Find out whether this symbol can be referenced off the $gp
17258 register. It can be if it is smaller than the -G size or if
17259 it is in the .sdata or .sbss section. Certain symbols can
17260 not be referenced off the $gp, although it appears as though
17262 symname = S_GET_NAME (sym);
17263 if (symname != (const char *) NULL
17264 && (strcmp (symname, "eprol") == 0
17265 || strcmp (symname, "etext") == 0
17266 || strcmp (symname, "_gp") == 0
17267 || strcmp (symname, "edata") == 0
17268 || strcmp (symname, "_fbss") == 0
17269 || strcmp (symname, "_fdata") == 0
17270 || strcmp (symname, "_ftext") == 0
17271 || strcmp (symname, "end") == 0
17272 || strcmp (symname, "_gp_disp") == 0))
17274 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17276 #ifndef NO_ECOFF_DEBUGGING
17277 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17278 && (symbol_get_obj (sym)->ecoff_extern_size
17279 <= g_switch_value))
17281 /* We must defer this decision until after the whole
17282 file has been read, since there might be a .extern
17283 after the first use of this symbol. */
17284 || (before_relaxing
17285 #ifndef NO_ECOFF_DEBUGGING
17286 && symbol_get_obj (sym)->ecoff_extern_size == 0
17288 && S_GET_VALUE (sym) == 0)
17289 || (S_GET_VALUE (sym) != 0
17290 && S_GET_VALUE (sym) <= g_switch_value)))
17294 const char *segname;
17296 segname = segment_name (S_GET_SEGMENT (sym));
17297 gas_assert (strcmp (segname, ".lit8") != 0
17298 && strcmp (segname, ".lit4") != 0);
17299 change = (strcmp (segname, ".sdata") != 0
17300 && strcmp (segname, ".sbss") != 0
17301 && strncmp (segname, ".sdata.", 7) != 0
17302 && strncmp (segname, ".sbss.", 6) != 0
17303 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17304 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17309 /* We are not optimizing for the $gp register. */
17314 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17317 pic_need_relax (symbolS *sym)
17321 /* Handle the case of a symbol equated to another symbol. */
17322 while (symbol_equated_reloc_p (sym))
17326 /* It's possible to get a loop here in a badly written program. */
17327 n = symbol_get_value_expression (sym)->X_add_symbol;
17333 if (symbol_section_p (sym))
17336 symsec = S_GET_SEGMENT (sym);
17338 /* This must duplicate the test in adjust_reloc_syms. */
17339 return (!bfd_is_und_section (symsec)
17340 && !bfd_is_abs_section (symsec)
17341 && !bfd_is_com_section (symsec)
17342 /* A global or weak symbol is treated as external. */
17343 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17346 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17347 convert a section-relative value VAL to the equivalent PC-relative
17351 mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op,
17352 offsetT val, long stretch)
17357 gas_assert (pcrel_op->root.root.type == OP_PCREL);
17359 sym_frag = symbol_get_frag (fragp->fr_symbol);
17361 /* If the relax_marker of the symbol fragment differs from the
17362 relax_marker of this fragment, we have not yet adjusted the
17363 symbol fragment fr_address. We want to add in STRETCH in
17364 order to get a better estimate of the address. This
17365 particularly matters because of the shift bits. */
17366 if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker)
17370 /* Adjust stretch for any alignment frag. Note that if have
17371 been expanding the earlier code, the symbol may be
17372 defined in what appears to be an earlier frag. FIXME:
17373 This doesn't handle the fr_subtype field, which specifies
17374 a maximum number of bytes to skip when doing an
17376 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17378 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17381 stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1));
17383 stretch &= ~((1 << (int) f->fr_offset) - 1);
17392 addr = fragp->fr_address + fragp->fr_fix;
17394 /* The base address rules are complicated. The base address of
17395 a branch is the following instruction. The base address of a
17396 PC relative load or add is the instruction itself, but if it
17397 is in a delay slot (in which case it can not be extended) use
17398 the address of the instruction whose delay slot it is in. */
17399 if (pcrel_op->include_isa_bit)
17403 /* If we are currently assuming that this frag should be
17404 extended, then the current address is two bytes higher. */
17405 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17408 /* Ignore the low bit in the target, since it will be set
17409 for a text label. */
17412 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17414 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17417 val -= addr & -(1 << pcrel_op->align_log2);
17422 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17423 extended opcode. SEC is the section the frag is in. */
17426 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17428 const struct mips_int_operand *operand;
17433 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17435 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17438 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17439 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17440 operand = mips16_immed_operand (type, FALSE);
17441 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
17442 || (operand->root.type == OP_PCREL
17444 : !bfd_is_abs_section (symsec)))
17447 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17449 if (operand->root.type == OP_PCREL)
17451 const struct mips_pcrel_operand *pcrel_op;
17454 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype))
17457 pcrel_op = (const struct mips_pcrel_operand *) operand;
17458 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17460 /* If any of the shifted bits are set, we must use an extended
17461 opcode. If the address depends on the size of this
17462 instruction, this can lead to a loop, so we arrange to always
17463 use an extended opcode. */
17464 if ((val & ((1 << operand->shift) - 1)) != 0)
17466 fragp->fr_subtype =
17467 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17471 /* If we are about to mark a frag as extended because the value
17472 is precisely the next value above maxtiny, then there is a
17473 chance of an infinite loop as in the following code:
17478 In this case when the la is extended, foo is 0x3fc bytes
17479 away, so the la can be shrunk, but then foo is 0x400 away, so
17480 the la must be extended. To avoid this loop, we mark the
17481 frag as extended if it was small, and is about to become
17482 extended with the next value above maxtiny. */
17483 maxtiny = mips_int_operand_max (operand);
17484 if (val == maxtiny + (1 << operand->shift)
17485 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17487 fragp->fr_subtype =
17488 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17493 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17496 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17497 macro expansion. SEC is the section the frag is in. We only
17498 support PC-relative instructions (LA, DLA, LW, LD) here, in
17499 non-PIC code using 32-bit addressing. */
17502 mips16_macro_frag (fragS *fragp, asection *sec, long stretch)
17504 const struct mips_pcrel_operand *pcrel_op;
17505 const struct mips_int_operand *operand;
17510 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype));
17512 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17514 if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype))
17517 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17523 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17524 if (bfd_is_abs_section (symsec))
17526 if (RELAX_MIPS16_PIC (fragp->fr_subtype))
17528 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec)
17531 operand = mips16_immed_operand (type, TRUE);
17532 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17533 pcrel_op = (const struct mips_pcrel_operand *) operand;
17534 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17536 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17543 /* Compute the length of a branch sequence, and adjust the
17544 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17545 worst-case length is computed, with UPDATE being used to indicate
17546 whether an unconditional (-1), branch-likely (+1) or regular (0)
17547 branch is to be computed. */
17549 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17551 bfd_boolean toofar;
17555 && S_IS_DEFINED (fragp->fr_symbol)
17556 && !S_IS_WEAK (fragp->fr_symbol)
17557 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17562 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17564 addr = fragp->fr_address + fragp->fr_fix + 4;
17568 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17571 /* If the symbol is not defined or it's in a different segment,
17572 we emit the long sequence. */
17575 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17577 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17578 RELAX_BRANCH_PIC (fragp->fr_subtype),
17579 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17580 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17581 RELAX_BRANCH_LINK (fragp->fr_subtype),
17587 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17590 if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype))
17592 /* Additional space for PIC loading of target address. */
17594 if (mips_opts.isa == ISA_MIPS1)
17595 /* Additional space for $at-stabilizing nop. */
17599 /* If branch is conditional. */
17600 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17607 /* Get a FRAG's branch instruction delay slot size, either from the
17608 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17609 or SHORT_INSN_SIZE otherwise. */
17612 frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
17614 char *buf = fragp->fr_literal + fragp->fr_fix;
17617 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
17619 return short_insn_size;
17622 /* Compute the length of a branch sequence, and adjust the
17623 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17624 worst-case length is computed, with UPDATE being used to indicate
17625 whether an unconditional (-1), or regular (0) branch is to be
17629 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17631 bfd_boolean insn32 = TRUE;
17632 bfd_boolean nods = TRUE;
17633 bfd_boolean pic = TRUE;
17634 bfd_boolean al = TRUE;
17635 int short_insn_size;
17636 bfd_boolean toofar;
17641 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
17642 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
17643 pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
17644 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17646 short_insn_size = insn32 ? 4 : 2;
17649 && S_IS_DEFINED (fragp->fr_symbol)
17650 && !S_IS_WEAK (fragp->fr_symbol)
17651 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17656 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17657 /* Ignore the low bit in the target, since it will be set
17658 for a text label. */
17659 if ((val & 1) != 0)
17662 addr = fragp->fr_address + fragp->fr_fix + 4;
17666 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17669 /* If the symbol is not defined or it's in a different segment,
17670 we emit the long sequence. */
17673 if (fragp && update
17674 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17675 fragp->fr_subtype = (toofar
17676 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17677 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17682 bfd_boolean compact_known = fragp != NULL;
17683 bfd_boolean compact = FALSE;
17684 bfd_boolean uncond;
17688 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17689 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17692 uncond = update < 0;
17694 /* If label is out of range, we turn branch <br>:
17696 <br> label # 4 bytes
17703 # compact && (!PIC || insn32)
17706 if ((!pic || insn32) && (!compact_known || compact))
17707 length += short_insn_size;
17709 /* If assembling PIC code, we further turn:
17715 lw/ld at, %got(label)(gp) # 4 bytes
17716 d/addiu at, %lo(label) # 4 bytes
17717 jr/c at # 2/4 bytes
17720 length += 4 + short_insn_size;
17722 /* Add an extra nop if the jump has no compact form and we need
17723 to fill the delay slot. */
17724 if ((!pic || al) && nods)
17726 ? frag_branch_delay_slot_size (fragp, al, short_insn_size)
17727 : short_insn_size);
17729 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17731 <brneg> 0f # 4 bytes
17732 nop # 2/4 bytes if !compact
17735 length += (compact_known && compact) ? 4 : 4 + short_insn_size;
17739 /* Add an extra nop to fill the delay slot. */
17740 gas_assert (fragp);
17741 length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
17747 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17748 bit accordingly. */
17751 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17753 bfd_boolean toofar;
17756 && S_IS_DEFINED (fragp->fr_symbol)
17757 && !S_IS_WEAK (fragp->fr_symbol)
17758 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17764 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17765 /* Ignore the low bit in the target, since it will be set
17766 for a text label. */
17767 if ((val & 1) != 0)
17770 /* Assume this is a 2-byte branch. */
17771 addr = fragp->fr_address + fragp->fr_fix + 2;
17773 /* We try to avoid the infinite loop by not adding 2 more bytes for
17778 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17780 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17781 else if (type == 'E')
17782 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17787 /* If the symbol is not defined or it's in a different segment,
17788 we emit a normal 32-bit branch. */
17791 if (fragp && update
17792 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17794 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17795 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17803 /* Estimate the size of a frag before relaxing. Unless this is the
17804 mips16, we are not really relaxing here, and the final size is
17805 encoded in the subtype information. For the mips16, we have to
17806 decide whether we are using an extended opcode or not. */
17809 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17813 if (RELAX_BRANCH_P (fragp->fr_subtype))
17816 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17818 return fragp->fr_var;
17821 if (RELAX_MIPS16_P (fragp->fr_subtype))
17823 /* We don't want to modify the EXTENDED bit here; it might get us
17824 into infinite loops. We change it only in mips_relax_frag(). */
17825 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
17826 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12;
17828 return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2;
17831 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17835 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17836 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17837 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17838 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17839 fragp->fr_var = length;
17844 if (mips_pic == VXWORKS_PIC)
17845 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17847 else if (RELAX_PIC (fragp->fr_subtype))
17848 change = pic_need_relax (fragp->fr_symbol);
17850 change = nopic_need_relax (fragp->fr_symbol, 0);
17854 fragp->fr_subtype |= RELAX_USE_SECOND;
17855 return -RELAX_FIRST (fragp->fr_subtype);
17858 return -RELAX_SECOND (fragp->fr_subtype);
17861 /* This is called to see whether a reloc against a defined symbol
17862 should be converted into a reloc against a section. */
17865 mips_fix_adjustable (fixS *fixp)
17867 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17868 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17871 if (fixp->fx_addsy == NULL)
17874 /* Allow relocs used for EH tables. */
17875 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17878 /* If symbol SYM is in a mergeable section, relocations of the form
17879 SYM + 0 can usually be made section-relative. The mergeable data
17880 is then identified by the section offset rather than by the symbol.
17882 However, if we're generating REL LO16 relocations, the offset is split
17883 between the LO16 and partnering high part relocation. The linker will
17884 need to recalculate the complete offset in order to correctly identify
17887 The linker has traditionally not looked for the partnering high part
17888 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17889 placed anywhere. Rather than break backwards compatibility by changing
17890 this, it seems better not to force the issue, and instead keep the
17891 original symbol. This will work with either linker behavior. */
17892 if ((lo16_reloc_p (fixp->fx_r_type)
17893 || reloc_needs_lo_p (fixp->fx_r_type))
17894 && HAVE_IN_PLACE_ADDENDS
17895 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17898 /* There is no place to store an in-place offset for JALR relocations. */
17899 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
17902 /* Likewise an in-range offset of limited PC-relative relocations may
17903 overflow the in-place relocatable field if recalculated against the
17904 start address of the symbol's containing section.
17906 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17907 section relative to allow linker relaxations to be performed later on. */
17908 if (limited_pcrel_reloc_p (fixp->fx_r_type)
17909 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
17912 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17913 to a floating-point stub. The same is true for non-R_MIPS16_26
17914 relocations against MIPS16 functions; in this case, the stub becomes
17915 the function's canonical address.
17917 Floating-point stubs are stored in unique .mips16.call.* or
17918 .mips16.fn.* sections. If a stub T for function F is in section S,
17919 the first relocation in section S must be against F; this is how the
17920 linker determines the target function. All relocations that might
17921 resolve to T must also be against F. We therefore have the following
17922 restrictions, which are given in an intentionally-redundant way:
17924 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17927 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17928 if that stub might be used.
17930 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17933 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17934 that stub might be used.
17936 There is a further restriction:
17938 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17939 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17940 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17941 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17942 against MIPS16 or microMIPS symbols because we need to keep the
17943 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17944 detection and JAL or BAL to JALX instruction conversion in the
17947 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17948 against a MIPS16 symbol. We deal with (5) by additionally leaving
17949 alone any jump and branch relocations against a microMIPS symbol.
17951 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17952 relocation against some symbol R, no relocation against R may be
17953 reduced. (Note that this deals with (2) as well as (1) because
17954 relocations against global symbols will never be reduced on ELF
17955 targets.) This approach is a little simpler than trying to detect
17956 stub sections, and gives the "all or nothing" per-symbol consistency
17957 that we have for MIPS16 symbols. */
17958 if (fixp->fx_subsy == NULL
17959 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17960 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17961 && (jmp_reloc_p (fixp->fx_r_type)
17962 || b_reloc_p (fixp->fx_r_type)))
17963 || *symbol_get_tc (fixp->fx_addsy)))
17969 /* Translate internal representation of relocation info to BFD target
17973 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17975 static arelent *retval[4];
17977 bfd_reloc_code_real_type code;
17979 memset (retval, 0, sizeof(retval));
17980 reloc = retval[0] = XCNEW (arelent);
17981 reloc->sym_ptr_ptr = XNEW (asymbol *);
17982 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17983 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17985 if (fixp->fx_pcrel)
17987 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17988 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
17989 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17990 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17991 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17992 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17993 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17994 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17995 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17996 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17997 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17998 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
18000 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18001 Relocations want only the symbol offset. */
18002 switch (fixp->fx_r_type)
18004 case BFD_RELOC_MIPS_18_PCREL_S3:
18005 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
18008 reloc->addend = fixp->fx_addnumber + reloc->address;
18012 else if (HAVE_IN_PLACE_ADDENDS
18013 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
18014 && (read_compressed_insn (fixp->fx_frag->fr_literal
18015 + fixp->fx_where, 4) >> 26) == 0x3c)
18017 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18018 addend accordingly. */
18019 reloc->addend = fixp->fx_addnumber >> 1;
18022 reloc->addend = fixp->fx_addnumber;
18024 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18025 entry to be used in the relocation's section offset. */
18026 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18028 reloc->address = reloc->addend;
18032 code = fixp->fx_r_type;
18034 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18035 if (reloc->howto == NULL)
18037 as_bad_where (fixp->fx_file, fixp->fx_line,
18038 _("cannot represent %s relocation in this object file"
18040 bfd_get_reloc_code_name (code));
18047 /* Relax a machine dependent frag. This returns the amount by which
18048 the current size of the frag should change. */
18051 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18053 if (RELAX_BRANCH_P (fragp->fr_subtype))
18055 offsetT old_var = fragp->fr_var;
18057 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18059 return fragp->fr_var - old_var;
18062 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18064 offsetT old_var = fragp->fr_var;
18065 offsetT new_var = 4;
18067 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18068 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18069 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18070 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18071 fragp->fr_var = new_var;
18073 return new_var - old_var;
18076 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18079 if (!mips16_extended_frag (fragp, sec, stretch))
18081 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18083 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18084 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10;
18086 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18088 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18094 else if (!mips16_macro_frag (fragp, sec, stretch))
18096 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18098 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18099 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18100 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8;
18102 else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18104 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18112 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18114 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18116 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18117 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18118 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8;
18122 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18123 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10;
18130 /* Convert a machine dependent frag. */
18133 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18135 if (RELAX_BRANCH_P (fragp->fr_subtype))
18138 unsigned long insn;
18141 buf = fragp->fr_literal + fragp->fr_fix;
18142 insn = read_insn (buf);
18144 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18146 /* We generate a fixup instead of applying it right now
18147 because, if there are linker relaxations, we're going to
18148 need the relocations. */
18149 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18150 fragp->fr_symbol, fragp->fr_offset,
18151 TRUE, BFD_RELOC_16_PCREL_S2);
18152 fixp->fx_file = fragp->fr_file;
18153 fixp->fx_line = fragp->fr_line;
18155 buf = write_insn (buf, insn);
18161 as_warn_where (fragp->fr_file, fragp->fr_line,
18162 _("relaxed out-of-range branch into a jump"));
18164 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18167 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18169 /* Reverse the branch. */
18170 switch ((insn >> 28) & 0xf)
18173 if ((insn & 0xff000000) == 0x47000000
18174 || (insn & 0xff600000) == 0x45600000)
18176 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18177 reversed by tweaking bit 23. */
18178 insn ^= 0x00800000;
18182 /* bc[0-3][tf]l? instructions can have the condition
18183 reversed by tweaking a single TF bit, and their
18184 opcodes all have 0x4???????. */
18185 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18186 insn ^= 0x00010000;
18191 /* bltz 0x04000000 bgez 0x04010000
18192 bltzal 0x04100000 bgezal 0x04110000 */
18193 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18194 insn ^= 0x00010000;
18198 /* beq 0x10000000 bne 0x14000000
18199 blez 0x18000000 bgtz 0x1c000000 */
18200 insn ^= 0x04000000;
18208 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18210 /* Clear the and-link bit. */
18211 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18213 /* bltzal 0x04100000 bgezal 0x04110000
18214 bltzall 0x04120000 bgezall 0x04130000 */
18215 insn &= ~0x00100000;
18218 /* Branch over the branch (if the branch was likely) or the
18219 full jump (not likely case). Compute the offset from the
18220 current instruction to branch to. */
18221 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18225 /* How many bytes in instructions we've already emitted? */
18226 i = buf - fragp->fr_literal - fragp->fr_fix;
18227 /* How many bytes in instructions from here to the end? */
18228 i = fragp->fr_var - i;
18230 /* Convert to instruction count. */
18232 /* Branch counts from the next instruction. */
18235 /* Branch over the jump. */
18236 buf = write_insn (buf, insn);
18239 buf = write_insn (buf, 0);
18241 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18243 /* beql $0, $0, 2f */
18245 /* Compute the PC offset from the current instruction to
18246 the end of the variable frag. */
18247 /* How many bytes in instructions we've already emitted? */
18248 i = buf - fragp->fr_literal - fragp->fr_fix;
18249 /* How many bytes in instructions from here to the end? */
18250 i = fragp->fr_var - i;
18251 /* Convert to instruction count. */
18253 /* Don't decrement i, because we want to branch over the
18257 buf = write_insn (buf, insn);
18258 buf = write_insn (buf, 0);
18262 if (!RELAX_BRANCH_PIC (fragp->fr_subtype))
18265 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18266 ? 0x0c000000 : 0x08000000);
18268 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18269 fragp->fr_symbol, fragp->fr_offset,
18270 FALSE, BFD_RELOC_MIPS_JMP);
18271 fixp->fx_file = fragp->fr_file;
18272 fixp->fx_line = fragp->fr_line;
18274 buf = write_insn (buf, insn);
18278 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18280 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18281 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18282 insn |= at << OP_SH_RT;
18284 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18285 fragp->fr_symbol, fragp->fr_offset,
18286 FALSE, BFD_RELOC_MIPS_GOT16);
18287 fixp->fx_file = fragp->fr_file;
18288 fixp->fx_line = fragp->fr_line;
18290 buf = write_insn (buf, insn);
18292 if (mips_opts.isa == ISA_MIPS1)
18294 buf = write_insn (buf, 0);
18296 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18297 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18298 insn |= at << OP_SH_RS | at << OP_SH_RT;
18300 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18301 fragp->fr_symbol, fragp->fr_offset,
18302 FALSE, BFD_RELOC_LO16);
18303 fixp->fx_file = fragp->fr_file;
18304 fixp->fx_line = fragp->fr_line;
18306 buf = write_insn (buf, insn);
18309 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18313 insn |= at << OP_SH_RS;
18315 buf = write_insn (buf, insn);
18319 fragp->fr_fix += fragp->fr_var;
18320 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18324 /* Relax microMIPS branches. */
18325 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18327 char *buf = fragp->fr_literal + fragp->fr_fix;
18328 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18329 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
18330 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
18331 bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
18332 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18333 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18334 bfd_boolean short_ds;
18335 unsigned long insn;
18338 fragp->fr_fix += fragp->fr_var;
18340 /* Handle 16-bit branches that fit or are forced to fit. */
18341 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18343 /* We generate a fixup instead of applying it right now,
18344 because if there is linker relaxation, we're going to
18345 need the relocations. */
18349 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18350 fragp->fr_symbol, fragp->fr_offset,
18351 TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1);
18354 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18355 fragp->fr_symbol, fragp->fr_offset,
18356 TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1);
18362 fixp->fx_file = fragp->fr_file;
18363 fixp->fx_line = fragp->fr_line;
18365 /* These relocations can have an addend that won't fit in
18367 fixp->fx_no_overflow = 1;
18372 /* Handle 32-bit branches that fit or are forced to fit. */
18373 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18374 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18376 /* We generate a fixup instead of applying it right now,
18377 because if there is linker relaxation, we're going to
18378 need the relocations. */
18379 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18380 fragp->fr_symbol, fragp->fr_offset,
18381 TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18382 fixp->fx_file = fragp->fr_file;
18383 fixp->fx_line = fragp->fr_line;
18387 insn = read_compressed_insn (buf, 4);
18392 /* Check the short-delay-slot bit. */
18393 if (!al || (insn & 0x02000000) != 0)
18394 buf = write_compressed_insn (buf, 0x0c00, 2);
18396 buf = write_compressed_insn (buf, 0x00000000, 4);
18399 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18404 /* Relax 16-bit branches to 32-bit branches. */
18407 insn = read_compressed_insn (buf, 2);
18409 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18410 insn = 0x94000000; /* beq */
18411 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18413 unsigned long regno;
18415 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18416 regno = micromips_to_32_reg_d_map [regno];
18417 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18418 insn |= regno << MICROMIPSOP_SH_RS;
18423 /* Nothing else to do, just write it out. */
18424 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18425 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18427 buf = write_compressed_insn (buf, insn, 4);
18429 buf = write_compressed_insn (buf, 0x0c00, 2);
18430 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18435 insn = read_compressed_insn (buf, 4);
18437 /* Relax 32-bit branches to a sequence of instructions. */
18438 as_warn_where (fragp->fr_file, fragp->fr_line,
18439 _("relaxed out-of-range branch into a jump"));
18441 /* Set the short-delay-slot bit. */
18442 short_ds = !al || (insn & 0x02000000) != 0;
18444 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18448 /* Reverse the branch. */
18449 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18450 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18451 insn ^= 0x20000000;
18452 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18453 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18454 || (insn & 0xffe00000) == 0x40800000 /* blez */
18455 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18456 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18457 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18458 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18459 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18460 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18461 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18462 insn ^= 0x00400000;
18463 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18464 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18465 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18466 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18467 insn ^= 0x00200000;
18468 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
18470 || (insn & 0xff600000) == 0x81600000) /* BZ.V
18472 insn ^= 0x00800000;
18478 /* Clear the and-link and short-delay-slot bits. */
18479 gas_assert ((insn & 0xfda00000) == 0x40200000);
18481 /* bltzal 0x40200000 bgezal 0x40600000 */
18482 /* bltzals 0x42200000 bgezals 0x42600000 */
18483 insn &= ~0x02200000;
18486 /* Make a label at the end for use with the branch. */
18487 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18488 micromips_label_inc ();
18489 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18492 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18493 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18494 fixp->fx_file = fragp->fr_file;
18495 fixp->fx_line = fragp->fr_line;
18497 /* Branch over the jump. */
18498 buf = write_compressed_insn (buf, insn, 4);
18504 buf = write_compressed_insn (buf, 0x00000000, 4);
18506 buf = write_compressed_insn (buf, 0x0c00, 2);
18512 unsigned long jal = (short_ds || nods
18513 ? 0x74000000 : 0xf4000000); /* jal/s */
18515 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18516 insn = al ? jal : 0xd4000000;
18518 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18519 fragp->fr_symbol, fragp->fr_offset,
18520 FALSE, BFD_RELOC_MICROMIPS_JMP);
18521 fixp->fx_file = fragp->fr_file;
18522 fixp->fx_line = fragp->fr_line;
18524 buf = write_compressed_insn (buf, insn, 4);
18526 if (compact || nods)
18530 buf = write_compressed_insn (buf, 0x00000000, 4);
18532 buf = write_compressed_insn (buf, 0x0c00, 2);
18537 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18539 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18540 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18541 insn |= at << MICROMIPSOP_SH_RT;
18543 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18544 fragp->fr_symbol, fragp->fr_offset,
18545 FALSE, BFD_RELOC_MICROMIPS_GOT16);
18546 fixp->fx_file = fragp->fr_file;
18547 fixp->fx_line = fragp->fr_line;
18549 buf = write_compressed_insn (buf, insn, 4);
18551 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18552 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18553 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18555 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18556 fragp->fr_symbol, fragp->fr_offset,
18557 FALSE, BFD_RELOC_MICROMIPS_LO16);
18558 fixp->fx_file = fragp->fr_file;
18559 fixp->fx_line = fragp->fr_line;
18561 buf = write_compressed_insn (buf, insn, 4);
18566 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT;
18567 insn |= at << MICROMIPSOP_SH_RS;
18569 buf = write_compressed_insn (buf, insn, 4);
18571 if (compact || nods)
18573 buf = write_compressed_insn (buf, 0x00000000, 4);
18577 /* jr/jrc/jalr/jalrs $at */
18578 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18579 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
18581 insn = al ? jalr : jr;
18582 insn |= at << MICROMIPSOP_SH_MJ;
18584 buf = write_compressed_insn (buf, insn, 2);
18589 buf = write_compressed_insn (buf, 0x0c00, 2);
18591 buf = write_compressed_insn (buf, 0x00000000, 4);
18596 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18600 if (RELAX_MIPS16_P (fragp->fr_subtype))
18603 const struct mips_int_operand *operand;
18606 unsigned int user_length;
18607 bfd_boolean need_reloc;
18608 unsigned long insn;
18613 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18614 operand = mips16_immed_operand (type, FALSE);
18616 mac = RELAX_MIPS16_MACRO (fragp->fr_subtype);
18617 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18618 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
18620 symsec = S_GET_SEGMENT (fragp->fr_symbol);
18621 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
18622 || (operand->root.type == OP_PCREL && !mac
18624 : !bfd_is_abs_section (symsec)));
18626 if (operand->root.type == OP_PCREL && !mac)
18628 const struct mips_pcrel_operand *pcrel_op;
18630 pcrel_op = (const struct mips_pcrel_operand *) operand;
18632 if (pcrel_op->include_isa_bit && !need_reloc)
18634 if (!mips_ignore_branch_isa
18635 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol)))
18636 as_bad_where (fragp->fr_file, fragp->fr_line,
18637 _("branch to a symbol in another ISA mode"));
18638 else if ((fragp->fr_offset & 0x1) != 0)
18639 as_bad_where (fragp->fr_file, fragp->fr_line,
18640 _("branch to misaligned address (0x%lx)"),
18644 val = mips16_pcrel_val (fragp, pcrel_op, val, 0);
18646 /* Make sure the section winds up with the alignment we have
18648 if (operand->shift > 0)
18649 record_alignment (asec, operand->shift);
18652 if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18653 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18656 as_warn_where (fragp->fr_file, fragp->fr_line,
18657 _("macro instruction expanded into multiple "
18658 "instructions in a branch delay slot"));
18660 as_warn_where (fragp->fr_file, fragp->fr_line,
18661 _("extended instruction in a branch delay slot"));
18663 else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac)
18664 as_warn_where (fragp->fr_file, fragp->fr_line,
18665 _("macro instruction expanded into multiple "
18668 buf = fragp->fr_literal + fragp->fr_fix;
18670 insn = read_compressed_insn (buf, 2);
18672 insn |= MIPS16_EXTEND;
18674 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18676 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18688 gas_assert (type == 'A' || type == 'B' || type == 'E');
18689 gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype));
18691 e2 = RELAX_MIPS16_E2 (fragp->fr_subtype);
18697 gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype));
18699 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18700 fragp->fr_symbol, fragp->fr_offset,
18701 FALSE, BFD_RELOC_MIPS16_HI16_S);
18702 fixp->fx_file = fragp->fr_file;
18703 fixp->fx_line = fragp->fr_line;
18705 fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4,
18706 fragp->fr_symbol, fragp->fr_offset,
18707 FALSE, BFD_RELOC_MIPS16_LO16);
18708 fixp->fx_file = fragp->fr_file;
18709 fixp->fx_line = fragp->fr_line;
18714 switch (insn & 0xf800)
18716 case 0x0800: /* ADDIU */
18717 reg = (insn >> 8) & 0x7;
18718 op = 0xf0004800 | (reg << 8);
18720 case 0xb000: /* LW */
18721 reg = (insn >> 8) & 0x7;
18722 op = 0xf0009800 | (reg << 8) | (reg << 5);
18724 case 0xf800: /* I64 */
18725 reg = (insn >> 5) & 0x7;
18726 switch (insn & 0x0700)
18728 case 0x0400: /* LD */
18729 op = 0xf0003800 | (reg << 8) | (reg << 5);
18731 case 0x0600: /* DADDIU */
18732 op = 0xf000fd00 | (reg << 5);
18742 new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */
18743 new |= mips16_immed_extend ((val + 0x8000) >> 16, 16);
18744 buf = write_compressed_insn (buf, new, 4);
18747 new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */
18748 buf = write_compressed_insn (buf, new, 4);
18750 op |= mips16_immed_extend (val, 16);
18751 buf = write_compressed_insn (buf, op, 4);
18753 fragp->fr_fix += e2 ? 8 : 12;
18757 unsigned int length = ext ? 4 : 2;
18761 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
18768 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
18773 if (mac || reloc == BFD_RELOC_NONE)
18774 as_bad_where (fragp->fr_file, fragp->fr_line,
18775 _("unsupported relocation"));
18778 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18779 fragp->fr_symbol, fragp->fr_offset,
18781 fixp->fx_file = fragp->fr_file;
18782 fixp->fx_line = fragp->fr_line;
18785 as_bad_where (fragp->fr_file, fragp->fr_line,
18786 _("invalid unextended operand value"));
18789 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18790 BFD_RELOC_UNUSED, val, user_length, &insn);
18792 gas_assert (mips16_opcode_length (insn) == length);
18793 write_compressed_insn (buf, insn, length);
18794 fragp->fr_fix += length;
18799 relax_substateT subtype = fragp->fr_subtype;
18800 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18801 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18805 first = RELAX_FIRST (subtype);
18806 second = RELAX_SECOND (subtype);
18807 fixp = (fixS *) fragp->fr_opcode;
18809 /* If the delay slot chosen does not match the size of the instruction,
18810 then emit a warning. */
18811 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18812 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18817 s = subtype & (RELAX_DELAY_SLOT_16BIT
18818 | RELAX_DELAY_SLOT_SIZE_FIRST
18819 | RELAX_DELAY_SLOT_SIZE_SECOND);
18820 msg = macro_warning (s);
18822 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18826 /* Possibly emit a warning if we've chosen the longer option. */
18827 if (use_second == second_longer)
18833 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18834 msg = macro_warning (s);
18836 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18840 /* Go through all the fixups for the first sequence. Disable them
18841 (by marking them as done) if we're going to use the second
18842 sequence instead. */
18844 && fixp->fx_frag == fragp
18845 && fixp->fx_where < fragp->fr_fix - second)
18847 if (subtype & RELAX_USE_SECOND)
18849 fixp = fixp->fx_next;
18852 /* Go through the fixups for the second sequence. Disable them if
18853 we're going to use the first sequence, otherwise adjust their
18854 addresses to account for the relaxation. */
18855 while (fixp && fixp->fx_frag == fragp)
18857 if (subtype & RELAX_USE_SECOND)
18858 fixp->fx_where -= first;
18861 fixp = fixp->fx_next;
18864 /* Now modify the frag contents. */
18865 if (subtype & RELAX_USE_SECOND)
18869 start = fragp->fr_literal + fragp->fr_fix - first - second;
18870 memmove (start, start + first, second);
18871 fragp->fr_fix -= first;
18874 fragp->fr_fix -= second;
18878 /* This function is called after the relocs have been generated.
18879 We've been storing mips16 text labels as odd. Here we convert them
18880 back to even for the convenience of the debugger. */
18883 mips_frob_file_after_relocs (void)
18886 unsigned int count, i;
18888 syms = bfd_get_outsymbols (stdoutput);
18889 count = bfd_get_symcount (stdoutput);
18890 for (i = 0; i < count; i++, syms++)
18891 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18892 && ((*syms)->value & 1) != 0)
18894 (*syms)->value &= ~1;
18895 /* If the symbol has an odd size, it was probably computed
18896 incorrectly, so adjust that as well. */
18897 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18898 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18902 /* This function is called whenever a label is defined, including fake
18903 labels instantiated off the dot special symbol. It is used when
18904 handling branch delays; if a branch has a label, we assume we cannot
18905 move it. This also bumps the value of the symbol by 1 in compressed
18909 mips_record_label (symbolS *sym)
18911 segment_info_type *si = seg_info (now_seg);
18912 struct insn_label_list *l;
18914 if (free_insn_labels == NULL)
18915 l = XNEW (struct insn_label_list);
18918 l = free_insn_labels;
18919 free_insn_labels = l->next;
18923 l->next = si->label_list;
18924 si->label_list = l;
18927 /* This function is called as tc_frob_label() whenever a label is defined
18928 and adds a DWARF-2 record we only want for true labels. */
18931 mips_define_label (symbolS *sym)
18933 mips_record_label (sym);
18934 dwarf2_emit_label (sym);
18937 /* This function is called by tc_new_dot_label whenever a new dot symbol
18941 mips_add_dot_label (symbolS *sym)
18943 mips_record_label (sym);
18944 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18945 mips_compressed_mark_label (sym);
18948 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18949 static unsigned int
18950 mips_convert_ase_flags (int ase)
18952 unsigned int ext_ases = 0;
18955 ext_ases |= AFL_ASE_DSP;
18956 if (ase & ASE_DSPR2)
18957 ext_ases |= AFL_ASE_DSPR2;
18958 if (ase & ASE_DSPR3)
18959 ext_ases |= AFL_ASE_DSPR3;
18961 ext_ases |= AFL_ASE_EVA;
18963 ext_ases |= AFL_ASE_MCU;
18964 if (ase & ASE_MDMX)
18965 ext_ases |= AFL_ASE_MDMX;
18966 if (ase & ASE_MIPS3D)
18967 ext_ases |= AFL_ASE_MIPS3D;
18969 ext_ases |= AFL_ASE_MT;
18970 if (ase & ASE_SMARTMIPS)
18971 ext_ases |= AFL_ASE_SMARTMIPS;
18972 if (ase & ASE_VIRT)
18973 ext_ases |= AFL_ASE_VIRT;
18975 ext_ases |= AFL_ASE_MSA;
18977 ext_ases |= AFL_ASE_XPA;
18978 if (ase & ASE_MIPS16E2)
18979 ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
18983 /* Some special processing for a MIPS ELF file. */
18986 mips_elf_final_processing (void)
18989 Elf_Internal_ABIFlags_v0 flags;
18993 switch (file_mips_opts.isa)
18996 flags.isa_level = 1;
18999 flags.isa_level = 2;
19002 flags.isa_level = 3;
19005 flags.isa_level = 4;
19008 flags.isa_level = 5;
19011 flags.isa_level = 32;
19015 flags.isa_level = 32;
19019 flags.isa_level = 32;
19023 flags.isa_level = 32;
19027 flags.isa_level = 32;
19031 flags.isa_level = 64;
19035 flags.isa_level = 64;
19039 flags.isa_level = 64;
19043 flags.isa_level = 64;
19047 flags.isa_level = 64;
19052 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
19053 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
19054 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
19055 : (file_mips_opts.fp == 64) ? AFL_REG_64
19057 flags.cpr2_size = AFL_REG_NONE;
19058 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19059 Tag_GNU_MIPS_ABI_FP);
19060 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
19061 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
19062 if (file_ase_mips16)
19063 flags.ases |= AFL_ASE_MIPS16;
19064 if (file_ase_micromips)
19065 flags.ases |= AFL_ASE_MICROMIPS;
19067 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
19068 || file_mips_opts.fp == 64)
19069 && file_mips_opts.oddspreg)
19070 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
19073 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
19074 ((Elf_External_ABIFlags_v0 *)
19077 /* Write out the register information. */
19078 if (mips_abi != N64_ABI)
19082 s.ri_gprmask = mips_gprmask;
19083 s.ri_cprmask[0] = mips_cprmask[0];
19084 s.ri_cprmask[1] = mips_cprmask[1];
19085 s.ri_cprmask[2] = mips_cprmask[2];
19086 s.ri_cprmask[3] = mips_cprmask[3];
19087 /* The gp_value field is set by the MIPS ELF backend. */
19089 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
19090 ((Elf32_External_RegInfo *)
19091 mips_regmask_frag));
19095 Elf64_Internal_RegInfo s;
19097 s.ri_gprmask = mips_gprmask;
19099 s.ri_cprmask[0] = mips_cprmask[0];
19100 s.ri_cprmask[1] = mips_cprmask[1];
19101 s.ri_cprmask[2] = mips_cprmask[2];
19102 s.ri_cprmask[3] = mips_cprmask[3];
19103 /* The gp_value field is set by the MIPS ELF backend. */
19105 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
19106 ((Elf64_External_RegInfo *)
19107 mips_regmask_frag));
19110 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19111 sort of BFD interface for this. */
19112 if (mips_any_noreorder)
19113 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
19114 if (mips_pic != NO_PIC)
19116 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
19117 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19120 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19122 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19123 defined at present; this might need to change in future. */
19124 if (file_ase_mips16)
19125 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
19126 if (file_ase_micromips)
19127 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
19128 if (file_mips_opts.ase & ASE_MDMX)
19129 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
19131 /* Set the MIPS ELF ABI flags. */
19132 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
19133 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
19134 else if (mips_abi == O64_ABI)
19135 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
19136 else if (mips_abi == EABI_ABI)
19138 if (file_mips_opts.gp == 64)
19139 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
19141 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
19144 /* Nothing to do for N32_ABI or N64_ABI. */
19146 if (mips_32bitmode)
19147 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
19149 if (mips_nan2008 == 1)
19150 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
19152 /* 32 bit code with 64 bit FP registers. */
19153 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19154 Tag_GNU_MIPS_ABI_FP);
19155 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
19156 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
19159 typedef struct proc {
19161 symbolS *func_end_sym;
19162 unsigned long reg_mask;
19163 unsigned long reg_offset;
19164 unsigned long fpreg_mask;
19165 unsigned long fpreg_offset;
19166 unsigned long frame_offset;
19167 unsigned long frame_reg;
19168 unsigned long pc_reg;
19171 static procS cur_proc;
19172 static procS *cur_proc_ptr;
19173 static int numprocs;
19175 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19176 as "2", and a normal nop as "0". */
19178 #define NOP_OPCODE_MIPS 0
19179 #define NOP_OPCODE_MIPS16 1
19180 #define NOP_OPCODE_MICROMIPS 2
19183 mips_nop_opcode (void)
19185 if (seg_info (now_seg)->tc_segment_info_data.micromips)
19186 return NOP_OPCODE_MICROMIPS;
19187 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
19188 return NOP_OPCODE_MIPS16;
19190 return NOP_OPCODE_MIPS;
19193 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19194 32-bit microMIPS NOPs here (if applicable). */
19197 mips_handle_align (fragS *fragp)
19201 int bytes, size, excess;
19204 if (fragp->fr_type != rs_align_code)
19207 p = fragp->fr_literal + fragp->fr_fix;
19209 switch (nop_opcode)
19211 case NOP_OPCODE_MICROMIPS:
19212 opcode = micromips_nop32_insn.insn_opcode;
19215 case NOP_OPCODE_MIPS16:
19216 opcode = mips16_nop_insn.insn_opcode;
19219 case NOP_OPCODE_MIPS:
19221 opcode = nop_insn.insn_opcode;
19226 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
19227 excess = bytes % size;
19229 /* Handle the leading part if we're not inserting a whole number of
19230 instructions, and make it the end of the fixed part of the frag.
19231 Try to fit in a short microMIPS NOP if applicable and possible,
19232 and use zeroes otherwise. */
19233 gas_assert (excess < 4);
19234 fragp->fr_fix += excess;
19239 /* Fall through. */
19241 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
19243 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
19247 /* Fall through. */
19250 /* Fall through. */
19255 md_number_to_chars (p, opcode, size);
19256 fragp->fr_var = size;
19265 if (*input_line_pointer == '-')
19267 ++input_line_pointer;
19270 if (!ISDIGIT (*input_line_pointer))
19271 as_bad (_("expected simple number"));
19272 if (input_line_pointer[0] == '0')
19274 if (input_line_pointer[1] == 'x')
19276 input_line_pointer += 2;
19277 while (ISXDIGIT (*input_line_pointer))
19280 val |= hex_value (*input_line_pointer++);
19282 return negative ? -val : val;
19286 ++input_line_pointer;
19287 while (ISDIGIT (*input_line_pointer))
19290 val |= *input_line_pointer++ - '0';
19292 return negative ? -val : val;
19295 if (!ISDIGIT (*input_line_pointer))
19297 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19298 *input_line_pointer, *input_line_pointer);
19299 as_warn (_("invalid number"));
19302 while (ISDIGIT (*input_line_pointer))
19305 val += *input_line_pointer++ - '0';
19307 return negative ? -val : val;
19310 /* The .file directive; just like the usual .file directive, but there
19311 is an initial number which is the ECOFF file index. In the non-ECOFF
19312 case .file implies DWARF-2. */
19315 s_mips_file (int x ATTRIBUTE_UNUSED)
19317 static int first_file_directive = 0;
19319 if (ECOFF_DEBUGGING)
19328 filename = dwarf2_directive_file (0);
19330 /* Versions of GCC up to 3.1 start files with a ".file"
19331 directive even for stabs output. Make sure that this
19332 ".file" is handled. Note that you need a version of GCC
19333 after 3.1 in order to support DWARF-2 on MIPS. */
19334 if (filename != NULL && ! first_file_directive)
19336 (void) new_logical_line (filename, -1);
19337 s_app_file_string (filename, 0);
19339 first_file_directive = 1;
19343 /* The .loc directive, implying DWARF-2. */
19346 s_mips_loc (int x ATTRIBUTE_UNUSED)
19348 if (!ECOFF_DEBUGGING)
19349 dwarf2_directive_loc (0);
19352 /* The .end directive. */
19355 s_mips_end (int x ATTRIBUTE_UNUSED)
19359 /* Following functions need their own .frame and .cprestore directives. */
19360 mips_frame_reg_valid = 0;
19361 mips_cprestore_valid = 0;
19363 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19366 demand_empty_rest_of_line ();
19371 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19372 as_warn (_(".end not in text section"));
19376 as_warn (_(".end directive without a preceding .ent directive"));
19377 demand_empty_rest_of_line ();
19383 gas_assert (S_GET_NAME (p));
19384 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19385 as_warn (_(".end symbol does not match .ent symbol"));
19387 if (debug_type == DEBUG_STABS)
19388 stabs_generate_asm_endfunc (S_GET_NAME (p),
19392 as_warn (_(".end directive missing or unknown symbol"));
19394 /* Create an expression to calculate the size of the function. */
19395 if (p && cur_proc_ptr)
19397 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19398 expressionS *exp = XNEW (expressionS);
19401 exp->X_op = O_subtract;
19402 exp->X_add_symbol = symbol_temp_new_now ();
19403 exp->X_op_symbol = p;
19404 exp->X_add_number = 0;
19406 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19409 #ifdef md_flush_pending_output
19410 md_flush_pending_output ();
19413 /* Generate a .pdr section. */
19414 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19416 segT saved_seg = now_seg;
19417 subsegT saved_subseg = now_subseg;
19421 gas_assert (pdr_seg);
19422 subseg_set (pdr_seg, 0);
19424 /* Write the symbol. */
19425 exp.X_op = O_symbol;
19426 exp.X_add_symbol = p;
19427 exp.X_add_number = 0;
19428 emit_expr (&exp, 4);
19430 fragp = frag_more (7 * 4);
19432 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19433 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19434 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19435 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19436 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19437 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19438 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19440 subseg_set (saved_seg, saved_subseg);
19443 cur_proc_ptr = NULL;
19446 /* The .aent and .ent directives. */
19449 s_mips_ent (int aent)
19453 symbolP = get_symbol ();
19454 if (*input_line_pointer == ',')
19455 ++input_line_pointer;
19456 SKIP_WHITESPACE ();
19457 if (ISDIGIT (*input_line_pointer)
19458 || *input_line_pointer == '-')
19461 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19462 as_warn (_(".ent or .aent not in text section"));
19464 if (!aent && cur_proc_ptr)
19465 as_warn (_("missing .end"));
19469 /* This function needs its own .frame and .cprestore directives. */
19470 mips_frame_reg_valid = 0;
19471 mips_cprestore_valid = 0;
19473 cur_proc_ptr = &cur_proc;
19474 memset (cur_proc_ptr, '\0', sizeof (procS));
19476 cur_proc_ptr->func_sym = symbolP;
19480 if (debug_type == DEBUG_STABS)
19481 stabs_generate_asm_func (S_GET_NAME (symbolP),
19482 S_GET_NAME (symbolP));
19485 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19487 demand_empty_rest_of_line ();
19490 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19491 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19492 s_mips_frame is used so that we can set the PDR information correctly.
19493 We can't use the ecoff routines because they make reference to the ecoff
19494 symbol table (in the mdebug section). */
19497 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19499 if (ECOFF_DEBUGGING)
19505 if (cur_proc_ptr == (procS *) NULL)
19507 as_warn (_(".frame outside of .ent"));
19508 demand_empty_rest_of_line ();
19512 cur_proc_ptr->frame_reg = tc_get_register (1);
19514 SKIP_WHITESPACE ();
19515 if (*input_line_pointer++ != ','
19516 || get_absolute_expression_and_terminator (&val) != ',')
19518 as_warn (_("bad .frame directive"));
19519 --input_line_pointer;
19520 demand_empty_rest_of_line ();
19524 cur_proc_ptr->frame_offset = val;
19525 cur_proc_ptr->pc_reg = tc_get_register (0);
19527 demand_empty_rest_of_line ();
19531 /* The .fmask and .mask directives. If the mdebug section is present
19532 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19533 embedded targets, s_mips_mask is used so that we can set the PDR
19534 information correctly. We can't use the ecoff routines because they
19535 make reference to the ecoff symbol table (in the mdebug section). */
19538 s_mips_mask (int reg_type)
19540 if (ECOFF_DEBUGGING)
19541 s_ignore (reg_type);
19546 if (cur_proc_ptr == (procS *) NULL)
19548 as_warn (_(".mask/.fmask outside of .ent"));
19549 demand_empty_rest_of_line ();
19553 if (get_absolute_expression_and_terminator (&mask) != ',')
19555 as_warn (_("bad .mask/.fmask directive"));
19556 --input_line_pointer;
19557 demand_empty_rest_of_line ();
19561 off = get_absolute_expression ();
19563 if (reg_type == 'F')
19565 cur_proc_ptr->fpreg_mask = mask;
19566 cur_proc_ptr->fpreg_offset = off;
19570 cur_proc_ptr->reg_mask = mask;
19571 cur_proc_ptr->reg_offset = off;
19574 demand_empty_rest_of_line ();
19578 /* A table describing all the processors gas knows about. Names are
19579 matched in the order listed.
19581 To ease comparison, please keep this table in the same order as
19582 gcc's mips_cpu_info_table[]. */
19583 static const struct mips_cpu_info mips_cpu_info_table[] =
19585 /* Entries for generic ISAs */
19586 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19587 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19588 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19589 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19590 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19591 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19592 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19593 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
19594 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
19595 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
19596 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19597 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19598 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
19599 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
19600 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
19603 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19604 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19605 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19608 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19611 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19612 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19613 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19614 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19615 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19616 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19617 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19618 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19619 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19620 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19621 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19622 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19623 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19624 /* ST Microelectronics Loongson 2E and 2F cores */
19625 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19626 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19629 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19630 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19631 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19632 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19633 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19634 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19635 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19636 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19637 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19638 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19639 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19640 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19641 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19642 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19643 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19646 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19647 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19648 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19649 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19651 /* MIPS 32 Release 2 */
19652 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19653 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19654 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19655 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19656 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19657 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19658 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19659 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19660 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19661 ISA_MIPS32R2, CPU_MIPS32R2 },
19662 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19663 ISA_MIPS32R2, CPU_MIPS32R2 },
19664 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19665 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19666 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19667 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19668 /* Deprecated forms of the above. */
19669 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19670 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19671 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19672 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19673 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19674 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19675 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19676 /* Deprecated forms of the above. */
19677 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19678 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19679 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19680 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19681 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19682 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19683 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19684 /* Deprecated forms of the above. */
19685 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19686 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19687 /* 34Kn is a 34kc without DSP. */
19688 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19689 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19690 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19691 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19692 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19693 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19694 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19695 /* Deprecated forms of the above. */
19696 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19697 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19698 /* 1004K cores are multiprocessor versions of the 34K. */
19699 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19700 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19701 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19702 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19703 /* interaptiv is the new name for 1004kf */
19704 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19705 { "interaptiv-mr2", 0,
19706 ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT,
19707 ISA_MIPS32R3, CPU_INTERAPTIV_MR2 },
19709 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19710 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
19711 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19712 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
19715 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19716 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19717 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19718 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19720 /* Broadcom SB-1 CPU core */
19721 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19722 /* Broadcom SB-1A CPU core */
19723 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19725 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
19727 /* MIPS 64 Release 2 */
19729 /* Cavium Networks Octeon CPU core */
19730 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19731 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19732 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19733 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
19736 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19739 XLP is mostly like XLR, with the prominent exception that it is
19740 MIPS64R2 rather than MIPS64. */
19741 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19743 /* MIPS 64 Release 6 */
19744 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19745 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
19748 { NULL, 0, 0, 0, 0 }
19752 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19753 with a final "000" replaced by "k". Ignore case.
19755 Note: this function is shared between GCC and GAS. */
19758 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19760 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19761 given++, canonical++;
19763 return ((*given == 0 && *canonical == 0)
19764 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19768 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19769 CPU name. We've traditionally allowed a lot of variation here.
19771 Note: this function is shared between GCC and GAS. */
19774 mips_matching_cpu_name_p (const char *canonical, const char *given)
19776 /* First see if the name matches exactly, or with a final "000"
19777 turned into "k". */
19778 if (mips_strict_matching_cpu_name_p (canonical, given))
19781 /* If not, try comparing based on numerical designation alone.
19782 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19783 if (TOLOWER (*given) == 'r')
19785 if (!ISDIGIT (*given))
19788 /* Skip over some well-known prefixes in the canonical name,
19789 hoping to find a number there too. */
19790 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19792 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19794 else if (TOLOWER (canonical[0]) == 'r')
19797 return mips_strict_matching_cpu_name_p (canonical, given);
19801 /* Parse an option that takes the name of a processor as its argument.
19802 OPTION is the name of the option and CPU_STRING is the argument.
19803 Return the corresponding processor enumeration if the CPU_STRING is
19804 recognized, otherwise report an error and return null.
19806 A similar function exists in GCC. */
19808 static const struct mips_cpu_info *
19809 mips_parse_cpu (const char *option, const char *cpu_string)
19811 const struct mips_cpu_info *p;
19813 /* 'from-abi' selects the most compatible architecture for the given
19814 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19815 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19816 version. Look first at the -mgp options, if given, otherwise base
19817 the choice on MIPS_DEFAULT_64BIT.
19819 Treat NO_ABI like the EABIs. One reason to do this is that the
19820 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19821 architecture. This code picks MIPS I for 'mips' and MIPS III for
19822 'mips64', just as we did in the days before 'from-abi'. */
19823 if (strcasecmp (cpu_string, "from-abi") == 0)
19825 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19826 return mips_cpu_info_from_isa (ISA_MIPS1);
19828 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19829 return mips_cpu_info_from_isa (ISA_MIPS3);
19831 if (file_mips_opts.gp >= 0)
19832 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
19833 ? ISA_MIPS1 : ISA_MIPS3);
19835 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19840 /* 'default' has traditionally been a no-op. Probably not very useful. */
19841 if (strcasecmp (cpu_string, "default") == 0)
19844 for (p = mips_cpu_info_table; p->name != 0; p++)
19845 if (mips_matching_cpu_name_p (p->name, cpu_string))
19848 as_bad (_("bad value (%s) for %s"), cpu_string, option);
19852 /* Return the canonical processor information for ISA (a member of the
19853 ISA_MIPS* enumeration). */
19855 static const struct mips_cpu_info *
19856 mips_cpu_info_from_isa (int isa)
19860 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19861 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19862 && isa == mips_cpu_info_table[i].isa)
19863 return (&mips_cpu_info_table[i]);
19868 static const struct mips_cpu_info *
19869 mips_cpu_info_from_arch (int arch)
19873 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19874 if (arch == mips_cpu_info_table[i].cpu)
19875 return (&mips_cpu_info_table[i]);
19881 show (FILE *stream, const char *string, int *col_p, int *first_p)
19885 fprintf (stream, "%24s", "");
19890 fprintf (stream, ", ");
19894 if (*col_p + strlen (string) > 72)
19896 fprintf (stream, "\n%24s", "");
19900 fprintf (stream, "%s", string);
19901 *col_p += strlen (string);
19907 md_show_usage (FILE *stream)
19912 fprintf (stream, _("\
19914 -EB generate big endian output\n\
19915 -EL generate little endian output\n\
19916 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19917 -G NUM allow referencing objects up to NUM bytes\n\
19918 implicitly with the gp register [default 8]\n"));
19919 fprintf (stream, _("\
19920 -mips1 generate MIPS ISA I instructions\n\
19921 -mips2 generate MIPS ISA II instructions\n\
19922 -mips3 generate MIPS ISA III instructions\n\
19923 -mips4 generate MIPS ISA IV instructions\n\
19924 -mips5 generate MIPS ISA V instructions\n\
19925 -mips32 generate MIPS32 ISA instructions\n\
19926 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19927 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19928 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19929 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19930 -mips64 generate MIPS64 ISA instructions\n\
19931 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19932 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19933 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19934 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19935 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19939 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19940 show (stream, mips_cpu_info_table[i].name, &column, &first);
19941 show (stream, "from-abi", &column, &first);
19942 fputc ('\n', stream);
19944 fprintf (stream, _("\
19945 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19946 -no-mCPU don't generate code specific to CPU.\n\
19947 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19951 show (stream, "3900", &column, &first);
19952 show (stream, "4010", &column, &first);
19953 show (stream, "4100", &column, &first);
19954 show (stream, "4650", &column, &first);
19955 fputc ('\n', stream);
19957 fprintf (stream, _("\
19958 -mips16 generate mips16 instructions\n\
19959 -no-mips16 do not generate mips16 instructions\n"));
19960 fprintf (stream, _("\
19961 -mmicromips generate microMIPS instructions\n\
19962 -mno-micromips do not generate microMIPS instructions\n"));
19963 fprintf (stream, _("\
19964 -msmartmips generate smartmips instructions\n\
19965 -mno-smartmips do not generate smartmips instructions\n"));
19966 fprintf (stream, _("\
19967 -mdsp generate DSP instructions\n\
19968 -mno-dsp do not generate DSP instructions\n"));
19969 fprintf (stream, _("\
19970 -mdspr2 generate DSP R2 instructions\n\
19971 -mno-dspr2 do not generate DSP R2 instructions\n"));
19972 fprintf (stream, _("\
19973 -mdspr3 generate DSP R3 instructions\n\
19974 -mno-dspr3 do not generate DSP R3 instructions\n"));
19975 fprintf (stream, _("\
19976 -mmt generate MT instructions\n\
19977 -mno-mt do not generate MT instructions\n"));
19978 fprintf (stream, _("\
19979 -mmcu generate MCU instructions\n\
19980 -mno-mcu do not generate MCU instructions\n"));
19981 fprintf (stream, _("\
19982 -mmsa generate MSA instructions\n\
19983 -mno-msa do not generate MSA instructions\n"));
19984 fprintf (stream, _("\
19985 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19986 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19987 fprintf (stream, _("\
19988 -mvirt generate Virtualization instructions\n\
19989 -mno-virt do not generate Virtualization instructions\n"));
19990 fprintf (stream, _("\
19991 -minsn32 only generate 32-bit microMIPS instructions\n\
19992 -mno-insn32 generate all microMIPS instructions\n"));
19993 fprintf (stream, _("\
19994 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19995 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19996 -mfix-vr4120 work around certain VR4120 errata\n\
19997 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19998 -mfix-24k insert a nop after ERET and DERET instructions\n\
19999 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20000 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20001 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20002 -msym32 assume all symbols have 32-bit values\n\
20003 -O0 remove unneeded NOPs, do not swap branches\n\
20004 -O remove unneeded NOPs and swap branches\n\
20005 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20006 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20007 fprintf (stream, _("\
20008 -mhard-float allow floating-point instructions\n\
20009 -msoft-float do not allow floating-point instructions\n\
20010 -msingle-float only allow 32-bit floating-point operations\n\
20011 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20012 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20013 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20014 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20015 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20016 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20020 show (stream, "legacy", &column, &first);
20021 show (stream, "2008", &column, &first);
20023 fputc ('\n', stream);
20025 fprintf (stream, _("\
20026 -KPIC, -call_shared generate SVR4 position independent code\n\
20027 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20028 -mvxworks-pic generate VxWorks position independent code\n\
20029 -non_shared do not generate code that can operate with DSOs\n\
20030 -xgot assume a 32 bit GOT\n\
20031 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20032 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20033 position dependent (non shared) code\n\
20034 -mabi=ABI create ABI conformant object file for:\n"));
20038 show (stream, "32", &column, &first);
20039 show (stream, "o64", &column, &first);
20040 show (stream, "n32", &column, &first);
20041 show (stream, "64", &column, &first);
20042 show (stream, "eabi", &column, &first);
20044 fputc ('\n', stream);
20046 fprintf (stream, _("\
20047 -32 create o32 ABI object file (default)\n\
20048 -n32 create n32 ABI object file\n\
20049 -64 create 64 ABI object file\n"));
20054 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
20056 if (HAVE_64BIT_SYMBOLS)
20057 return dwarf2_format_64bit_irix;
20059 return dwarf2_format_32bit;
20064 mips_dwarf2_addr_size (void)
20066 if (HAVE_64BIT_OBJECTS)
20072 /* Standard calling conventions leave the CFA at SP on entry. */
20074 mips_cfi_frame_initial_instructions (void)
20076 cfi_add_CFA_def_cfa_register (SP);
20080 tc_mips_regname_to_dw2regnum (char *regname)
20082 unsigned int regnum = -1;
20085 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
20091 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20092 Given a symbolic attribute NAME, return the proper integer value.
20093 Returns -1 if the attribute is not known. */
20096 mips_convert_symbolic_attribute (const char *name)
20098 static const struct
20103 attribute_table[] =
20105 #define T(tag) {#tag, tag}
20106 T (Tag_GNU_MIPS_ABI_FP),
20107 T (Tag_GNU_MIPS_ABI_MSA),
20115 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
20116 if (streq (name, attribute_table[i].name))
20117 return attribute_table[i].tag;
20125 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
20127 mips_emit_delays ();
20129 as_warn (_("missing .end at end of assembly"));
20131 /* Just in case no code was emitted, do the consistency check. */
20132 file_mips_check_options ();
20134 /* Set a floating-point ABI if the user did not. */
20135 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
20137 /* Perform consistency checks on the floating-point ABI. */
20138 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20139 Tag_GNU_MIPS_ABI_FP);
20140 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
20141 check_fpabi (fpabi);
20145 /* Soft-float gets precedence over single-float, the two options should
20146 not be used together so this should not matter. */
20147 if (file_mips_opts.soft_float == 1)
20148 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
20149 /* Single-float gets precedence over all double_float cases. */
20150 else if (file_mips_opts.single_float == 1)
20151 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
20154 switch (file_mips_opts.fp)
20157 if (file_mips_opts.gp == 32)
20158 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20161 fpabi = Val_GNU_MIPS_ABI_FP_XX;
20164 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
20165 fpabi = Val_GNU_MIPS_ABI_FP_64A;
20166 else if (file_mips_opts.gp == 32)
20167 fpabi = Val_GNU_MIPS_ABI_FP_64;
20169 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20174 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20175 Tag_GNU_MIPS_ABI_FP, fpabi);
20179 /* Returns the relocation type required for a particular CFI encoding. */
20181 bfd_reloc_code_real_type
20182 mips_cfi_reloc_for_encoding (int encoding)
20184 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
20185 return BFD_RELOC_32_PCREL;
20186 else return BFD_RELOC_NONE;