1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi = NO_ABI;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Enabled Application Specific Extensions (ASEs). These are set to -1
141 if they have not been initialized. Changed by `.set <asename>', by
142 command line options, and based on the default architecture. */
144 /* Whether we are assembling for the mips16 processor. 0 if we are
145 not, 1 if we are, and -1 if the value has not been initialized.
146 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
147 -nomips16 command line options, and the default CPU. */
149 /* Non-zero if we should not reorder instructions. Changed by `.set
150 reorder' and `.set noreorder'. */
152 /* Non-zero if we should not permit the $at ($1) register to be used
153 in instructions. Changed by `.set at' and `.set noat'. */
155 /* Non-zero if we should warn when a macro instruction expands into
156 more than one machine instruction. Changed by `.set nomacro' and
158 int warn_about_macros;
159 /* Non-zero if we should not move instructions. Changed by `.set
160 move', `.set volatile', `.set nomove', and `.set novolatile'. */
162 /* Non-zero if we should not optimize branches by moving the target
163 of the branch into the delay slot. Actually, we don't perform
164 this optimization anyhow. Changed by `.set bopt' and `.set
167 /* Non-zero if we should not autoextend mips16 instructions.
168 Changed by `.set autoextend' and `.set noautoextend'. */
170 /* Restrict general purpose registers and floating point registers
171 to 32 bit. This is initially determined when -mgp32 or -mfp32
172 is passed but can changed if the assembler code uses .set mipsN. */
175 /* The ABI currently in use. This is changed by .set mipsN to loosen
176 restrictions and doesn't affect the whole file. */
177 enum mips_abi_level abi;
180 /* True if -mgp32 was passed. */
181 static int file_mips_gp32 = -1;
183 /* True if -mfp32 was passed. */
184 static int file_mips_fp32 = -1;
186 /* This is the struct we use to hold the current set of options. Note
187 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
188 -1 to indicate that they have not been initialized. */
190 static struct mips_set_options mips_opts =
192 ISA_UNKNOWN, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
195 /* These variables are filled in with the masks of registers used.
196 The object format code reads them and puts them in the appropriate
198 unsigned long mips_gprmask;
199 unsigned long mips_cprmask[4];
201 /* MIPS ISA we are using for this output file. */
202 static int file_mips_isa = ISA_UNKNOWN;
204 /* True if -mips3d was passed or implied by arguments passed on the
205 command line (e.g., by -march). */
206 static int file_ase_mips3d;
208 /* The argument of the -mcpu= flag. Historical for code generation. */
209 static int mips_cpu = CPU_UNKNOWN;
211 /* The argument of the -march= flag. The architecture we are assembling. */
212 static int mips_arch = CPU_UNKNOWN;
214 /* The argument of the -mtune= flag. The architecture for which we
216 static int mips_tune = CPU_UNKNOWN;
218 /* Whether we should mark the file EABI64 or EABI32. */
219 static int mips_eabi64 = 0;
221 /* If they asked for mips1 or mips2 and a cpu that is
222 mips3 or greater, then mark the object file 32BITMODE. */
223 static int mips_32bitmode = 0;
225 /* Some ISA's have delay slots for instructions which read or write
226 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
227 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
228 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
229 delay slot in this ISA. The uses of this macro assume that any
230 ISA that has delay slots for one of these, has them for all. They
231 also assume that ISAs which don't have delays for these insns, don't
232 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
233 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
235 || (ISA) == ISA_MIPS2 \
236 || (ISA) == ISA_MIPS3 \
239 /* Return true if ISA supports 64 bit gp register instructions. */
240 #define ISA_HAS_64BIT_REGS(ISA) ( \
242 || (ISA) == ISA_MIPS4 \
243 || (ISA) == ISA_MIPS5 \
244 || (ISA) == ISA_MIPS64 \
247 #define HAVE_32BIT_GPRS \
249 || mips_opts.abi == O32_ABI \
250 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
252 #define HAVE_32BIT_FPRS \
254 || mips_opts.abi == O32_ABI \
255 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
257 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
258 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
260 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
262 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
264 /* We can only have 64bit addresses if the object file format
266 #define HAVE_32BIT_ADDRESSES \
268 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
269 || ! HAVE_64BIT_OBJECTS) \
270 && mips_pic != EMBEDDED_PIC))
272 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
274 /* Return true if the given CPU supports the MIPS3D ASE. */
275 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
278 /* Whether the processor uses hardware interlocks to protect
279 reads from the HI and LO registers, and thus does not
280 require nops to be inserted. */
282 #define hilo_interlocks (mips_arch == CPU_R4010 \
283 || mips_arch == CPU_SB1 \
286 /* Whether the processor uses hardware interlocks to protect reads
287 from the GPRs, and thus does not require nops to be inserted. */
288 #define gpr_interlocks \
289 (mips_opts.isa != ISA_MIPS1 \
290 || mips_arch == CPU_R3900)
292 /* As with other "interlocks" this is used by hardware that has FP
293 (co-processor) interlocks. */
294 /* Itbl support may require additional care here. */
295 #define cop_interlocks (mips_arch == CPU_R4300 \
296 || mips_arch == CPU_SB1 \
299 /* Is this a mfhi or mflo instruction? */
300 #define MF_HILO_INSN(PINFO) \
301 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
303 /* MIPS PIC level. */
307 /* Do not generate PIC code. */
310 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
311 not sure what it is supposed to do. */
314 /* Generate PIC code as in the SVR4 MIPS ABI. */
317 /* Generate PIC code without using a global offset table: the data
318 segment has a maximum size of 64K, all data references are off
319 the $gp register, and all text references are PC relative. This
320 is used on some embedded systems. */
324 static enum mips_pic_level mips_pic;
326 /* Warn about all NOPS that the assembler generates. */
327 static int warn_nops = 0;
329 /* 1 if we should generate 32 bit offsets from the GP register in
330 SVR4_PIC mode. Currently has no meaning in other modes. */
331 static int mips_big_got;
333 /* 1 if trap instructions should used for overflow rather than break
335 static int mips_trap;
337 /* 1 if double width floating point constants should not be constructed
338 by assembling two single width halves into two single width floating
339 point registers which just happen to alias the double width destination
340 register. On some architectures this aliasing can be disabled by a bit
341 in the status register, and the setting of this bit cannot be determined
342 automatically at assemble time. */
343 static int mips_disable_float_construction;
345 /* Non-zero if any .set noreorder directives were used. */
347 static int mips_any_noreorder;
349 /* Non-zero if nops should be inserted when the register referenced in
350 an mfhi/mflo instruction is read in the next two instructions. */
351 static int mips_7000_hilo_fix;
353 /* The size of the small data section. */
354 static unsigned int g_switch_value = 8;
355 /* Whether the -G option was used. */
356 static int g_switch_seen = 0;
361 /* If we can determine in advance that GP optimization won't be
362 possible, we can skip the relaxation stuff that tries to produce
363 GP-relative references. This makes delay slot optimization work
366 This function can only provide a guess, but it seems to work for
367 gcc output. It needs to guess right for gcc, otherwise gcc
368 will put what it thinks is a GP-relative instruction in a branch
371 I don't know if a fix is needed for the SVR4_PIC mode. I've only
372 fixed it for the non-PIC mode. KR 95/04/07 */
373 static int nopic_need_relax PARAMS ((symbolS *, int));
375 /* handle of the OPCODE hash table */
376 static struct hash_control *op_hash = NULL;
378 /* The opcode hash table we use for the mips16. */
379 static struct hash_control *mips16_op_hash = NULL;
381 /* This array holds the chars that always start a comment. If the
382 pre-processor is disabled, these aren't very useful */
383 const char comment_chars[] = "#";
385 /* This array holds the chars that only start a comment at the beginning of
386 a line. If the line seems to have the form '# 123 filename'
387 .line and .file directives will appear in the pre-processed output */
388 /* Note that input_file.c hand checks for '#' at the beginning of the
389 first line of the input file. This is because the compiler outputs
390 #NO_APP at the beginning of its output. */
391 /* Also note that C style comments are always supported. */
392 const char line_comment_chars[] = "#";
394 /* This array holds machine specific line separator characters. */
395 const char line_separator_chars[] = ";";
397 /* Chars that can be used to separate mant from exp in floating point nums */
398 const char EXP_CHARS[] = "eE";
400 /* Chars that mean this number is a floating point constant */
403 const char FLT_CHARS[] = "rRsSfFdDxXpP";
405 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
406 changed in read.c . Ideally it shouldn't have to know about it at all,
407 but nothing is ideal around here.
410 static char *insn_error;
412 static int auto_align = 1;
414 /* When outputting SVR4 PIC code, the assembler needs to know the
415 offset in the stack frame from which to restore the $gp register.
416 This is set by the .cprestore pseudo-op, and saved in this
418 static offsetT mips_cprestore_offset = -1;
420 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
421 more optimizations, it can use a register value instead of a memory-saved
422 offset and even an other register than $gp as global pointer. */
423 static offsetT mips_cpreturn_offset = -1;
424 static int mips_cpreturn_register = -1;
425 static int mips_gp_register = GP;
427 /* Whether mips_cprestore_offset has been set in the current function
428 (or whether it has already been warned about, if not). */
429 static int mips_cprestore_valid = 0;
431 /* This is the register which holds the stack frame, as set by the
432 .frame pseudo-op. This is needed to implement .cprestore. */
433 static int mips_frame_reg = SP;
435 /* Whether mips_frame_reg has been set in the current function
436 (or whether it has already been warned about, if not). */
437 static int mips_frame_reg_valid = 0;
439 /* To output NOP instructions correctly, we need to keep information
440 about the previous two instructions. */
442 /* Whether we are optimizing. The default value of 2 means to remove
443 unneeded NOPs and swap branch instructions when possible. A value
444 of 1 means to not swap branches. A value of 0 means to always
446 static int mips_optimize = 2;
448 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
449 equivalent to seeing no -g option at all. */
450 static int mips_debug = 0;
452 /* The previous instruction. */
453 static struct mips_cl_insn prev_insn;
455 /* The instruction before prev_insn. */
456 static struct mips_cl_insn prev_prev_insn;
458 /* If we don't want information for prev_insn or prev_prev_insn, we
459 point the insn_mo field at this dummy integer. */
460 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
462 /* Non-zero if prev_insn is valid. */
463 static int prev_insn_valid;
465 /* The frag for the previous instruction. */
466 static struct frag *prev_insn_frag;
468 /* The offset into prev_insn_frag for the previous instruction. */
469 static long prev_insn_where;
471 /* The reloc type for the previous instruction, if any. */
472 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
474 /* The reloc for the previous instruction, if any. */
475 static fixS *prev_insn_fixp[3];
477 /* Non-zero if the previous instruction was in a delay slot. */
478 static int prev_insn_is_delay_slot;
480 /* Non-zero if the previous instruction was in a .set noreorder. */
481 static int prev_insn_unreordered;
483 /* Non-zero if the previous instruction uses an extend opcode (if
485 static int prev_insn_extended;
487 /* Non-zero if the previous previous instruction was in a .set
489 static int prev_prev_insn_unreordered;
491 /* If this is set, it points to a frag holding nop instructions which
492 were inserted before the start of a noreorder section. If those
493 nops turn out to be unnecessary, the size of the frag can be
495 static fragS *prev_nop_frag;
497 /* The number of nop instructions we created in prev_nop_frag. */
498 static int prev_nop_frag_holds;
500 /* The number of nop instructions that we know we need in
502 static int prev_nop_frag_required;
504 /* The number of instructions we've seen since prev_nop_frag. */
505 static int prev_nop_frag_since;
507 /* For ECOFF and ELF, relocations against symbols are done in two
508 parts, with a HI relocation and a LO relocation. Each relocation
509 has only 16 bits of space to store an addend. This means that in
510 order for the linker to handle carries correctly, it must be able
511 to locate both the HI and the LO relocation. This means that the
512 relocations must appear in order in the relocation table.
514 In order to implement this, we keep track of each unmatched HI
515 relocation. We then sort them so that they immediately precede the
516 corresponding LO relocation. */
521 struct mips_hi_fixup *next;
524 /* The section this fixup is in. */
528 /* The list of unmatched HI relocs. */
530 static struct mips_hi_fixup *mips_hi_fixup_list;
532 /* Map normal MIPS register numbers to mips16 register numbers. */
534 #define X ILLEGAL_REG
535 static const int mips32_to_16_reg_map[] =
537 X, X, 2, 3, 4, 5, 6, 7,
538 X, X, X, X, X, X, X, X,
539 0, 1, X, X, X, X, X, X,
540 X, X, X, X, X, X, X, X
544 /* Map mips16 register numbers to normal MIPS register numbers. */
546 static const unsigned int mips16_to_32_reg_map[] =
548 16, 17, 2, 3, 4, 5, 6, 7
551 /* Since the MIPS does not have multiple forms of PC relative
552 instructions, we do not have to do relaxing as is done on other
553 platforms. However, we do have to handle GP relative addressing
554 correctly, which turns out to be a similar problem.
556 Every macro that refers to a symbol can occur in (at least) two
557 forms, one with GP relative addressing and one without. For
558 example, loading a global variable into a register generally uses
559 a macro instruction like this:
561 If i can be addressed off the GP register (this is true if it is in
562 the .sbss or .sdata section, or if it is known to be smaller than
563 the -G argument) this will generate the following instruction:
565 This instruction will use a GPREL reloc. If i can not be addressed
566 off the GP register, the following instruction sequence will be used:
569 In this case the first instruction will have a HI16 reloc, and the
570 second reloc will have a LO16 reloc. Both relocs will be against
573 The issue here is that we may not know whether i is GP addressable
574 until after we see the instruction that uses it. Therefore, we
575 want to be able to choose the final instruction sequence only at
576 the end of the assembly. This is similar to the way other
577 platforms choose the size of a PC relative instruction only at the
580 When generating position independent code we do not use GP
581 addressing in quite the same way, but the issue still arises as
582 external symbols and local symbols must be handled differently.
584 We handle these issues by actually generating both possible
585 instruction sequences. The longer one is put in a frag_var with
586 type rs_machine_dependent. We encode what to do with the frag in
587 the subtype field. We encode (1) the number of existing bytes to
588 replace, (2) the number of new bytes to use, (3) the offset from
589 the start of the existing bytes to the first reloc we must generate
590 (that is, the offset is applied from the start of the existing
591 bytes after they are replaced by the new bytes, if any), (4) the
592 offset from the start of the existing bytes to the second reloc,
593 (5) whether a third reloc is needed (the third reloc is always four
594 bytes after the second reloc), and (6) whether to warn if this
595 variant is used (this is sometimes needed if .set nomacro or .set
596 noat is in effect). All these numbers are reasonably small.
598 Generating two instruction sequences must be handled carefully to
599 ensure that delay slots are handled correctly. Fortunately, there
600 are a limited number of cases. When the second instruction
601 sequence is generated, append_insn is directed to maintain the
602 existing delay slot information, so it continues to apply to any
603 code after the second instruction sequence. This means that the
604 second instruction sequence must not impose any requirements not
605 required by the first instruction sequence.
607 These variant frags are then handled in functions called by the
608 machine independent code. md_estimate_size_before_relax returns
609 the final size of the frag. md_convert_frag sets up the final form
610 of the frag. tc_gen_reloc adjust the first reloc and adds a second
612 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
616 | (((reloc1) + 64) << 9) \
617 | (((reloc2) + 64) << 2) \
618 | ((reloc3) ? (1 << 1) : 0) \
620 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
621 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
622 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
623 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
624 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
625 #define RELAX_WARN(i) ((i) & 1)
627 /* For mips16 code, we use an entirely different form of relaxation.
628 mips16 supports two versions of most instructions which take
629 immediate values: a small one which takes some small value, and a
630 larger one which takes a 16 bit value. Since branches also follow
631 this pattern, relaxing these values is required.
633 We can assemble both mips16 and normal MIPS code in a single
634 object. Therefore, we need to support this type of relaxation at
635 the same time that we support the relaxation described above. We
636 use the high bit of the subtype field to distinguish these cases.
638 The information we store for this type of relaxation is the
639 argument code found in the opcode file for this relocation, whether
640 the user explicitly requested a small or extended form, and whether
641 the relocation is in a jump or jal delay slot. That tells us the
642 size of the value, and how it should be stored. We also store
643 whether the fragment is considered to be extended or not. We also
644 store whether this is known to be a branch to a different section,
645 whether we have tried to relax this frag yet, and whether we have
646 ever extended a PC relative fragment because of a shift count. */
647 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
650 | ((small) ? 0x100 : 0) \
651 | ((ext) ? 0x200 : 0) \
652 | ((dslot) ? 0x400 : 0) \
653 | ((jal_dslot) ? 0x800 : 0))
654 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
655 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
656 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
657 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
658 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
659 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
660 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
661 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
662 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
663 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
664 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
665 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
667 /* Prototypes for static functions. */
670 #define internalError() \
671 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
673 #define internalError() as_fatal (_("MIPS internal Error"));
676 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
678 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
679 unsigned int reg, enum mips_regclass class));
680 static int reg_needs_delay PARAMS ((unsigned int));
681 static void mips16_mark_labels PARAMS ((void));
682 static void append_insn PARAMS ((char *place,
683 struct mips_cl_insn * ip,
685 bfd_reloc_code_real_type *r,
687 static void mips_no_prev_insn PARAMS ((int));
688 static void mips_emit_delays PARAMS ((boolean));
690 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
691 const char *name, const char *fmt,
694 static void macro_build ();
696 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
697 const char *, const char *,
699 static void macro_build_lui PARAMS ((char *place, int *counter,
700 expressionS * ep, int regnum));
701 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
702 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
704 static void load_register PARAMS ((int *, int, expressionS *, int));
705 static void load_address PARAMS ((int *, int, expressionS *, int, int *));
706 static void move_register PARAMS ((int *, int, int));
707 static void macro PARAMS ((struct mips_cl_insn * ip));
708 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
709 #ifdef LOSING_COMPILER
710 static void macro2 PARAMS ((struct mips_cl_insn * ip));
712 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
713 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
714 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
715 boolean, boolean, unsigned long *,
716 boolean *, unsigned short *));
717 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
718 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
719 static int my_getSmallExpression PARAMS ((expressionS *, char *));
720 static void my_getExpression PARAMS ((expressionS *, char *));
722 static int support_64bit_objects PARAMS((void));
724 static symbolS *get_symbol PARAMS ((void));
725 static void mips_align PARAMS ((int to, int fill, symbolS *label));
726 static void s_align PARAMS ((int));
727 static void s_change_sec PARAMS ((int));
728 static void s_cons PARAMS ((int));
729 static void s_float_cons PARAMS ((int));
730 static void s_mips_globl PARAMS ((int));
731 static void s_option PARAMS ((int));
732 static void s_mipsset PARAMS ((int));
733 static void s_abicalls PARAMS ((int));
734 static void s_cpload PARAMS ((int));
735 static void s_cpsetup PARAMS ((int));
736 static void s_cplocal PARAMS ((int));
737 static void s_cprestore PARAMS ((int));
738 static void s_cpreturn PARAMS ((int));
739 static void s_gpvalue PARAMS ((int));
740 static void s_gpword PARAMS ((int));
741 static void s_cpadd PARAMS ((int));
742 static void s_insn PARAMS ((int));
743 static void md_obj_begin PARAMS ((void));
744 static void md_obj_end PARAMS ((void));
745 static long get_number PARAMS ((void));
746 static void s_mips_ent PARAMS ((int));
747 static void s_mips_end PARAMS ((int));
748 static void s_mips_frame PARAMS ((int));
749 static void s_mips_mask PARAMS ((int));
750 static void s_mips_stab PARAMS ((int));
751 static void s_mips_weakext PARAMS ((int));
752 static void s_file PARAMS ((int));
753 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
754 static const char *mips_isa_to_str PARAMS ((int));
755 static const char *mips_cpu_to_str PARAMS ((int));
756 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
757 static void show PARAMS ((FILE *, char *, int *, int *));
759 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
762 /* Return values of my_getSmallExpression(). */
769 /* Direct relocation creation by %percent_op(). */
788 /* Table and functions used to map between CPU/ISA names, and
789 ISA levels, and CPU numbers. */
793 const char *name; /* CPU or ISA name. */
794 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
795 int isa; /* ISA level. */
796 int cpu; /* CPU number (default CPU if ISA). */
799 static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *));
800 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
801 static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
805 The following pseudo-ops from the Kane and Heinrich MIPS book
806 should be defined here, but are currently unsupported: .alias,
807 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
809 The following pseudo-ops from the Kane and Heinrich MIPS book are
810 specific to the type of debugging information being generated, and
811 should be defined by the object format: .aent, .begin, .bend,
812 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
815 The following pseudo-ops from the Kane and Heinrich MIPS book are
816 not MIPS CPU specific, but are also not specific to the object file
817 format. This file is probably the best place to define them, but
818 they are not currently supported: .asm0, .endr, .lab, .repeat,
821 static const pseudo_typeS mips_pseudo_table[] =
823 /* MIPS specific pseudo-ops. */
824 {"option", s_option, 0},
825 {"set", s_mipsset, 0},
826 {"rdata", s_change_sec, 'r'},
827 {"sdata", s_change_sec, 's'},
828 {"livereg", s_ignore, 0},
829 {"abicalls", s_abicalls, 0},
830 {"cpload", s_cpload, 0},
831 {"cpsetup", s_cpsetup, 0},
832 {"cplocal", s_cplocal, 0},
833 {"cprestore", s_cprestore, 0},
834 {"cpreturn", s_cpreturn, 0},
835 {"gpvalue", s_gpvalue, 0},
836 {"gpword", s_gpword, 0},
837 {"cpadd", s_cpadd, 0},
840 /* Relatively generic pseudo-ops that happen to be used on MIPS
842 {"asciiz", stringer, 1},
843 {"bss", s_change_sec, 'b'},
846 {"dword", s_cons, 3},
847 {"weakext", s_mips_weakext, 0},
849 /* These pseudo-ops are defined in read.c, but must be overridden
850 here for one reason or another. */
851 {"align", s_align, 0},
853 {"data", s_change_sec, 'd'},
854 {"double", s_float_cons, 'd'},
855 {"float", s_float_cons, 'f'},
856 {"globl", s_mips_globl, 0},
857 {"global", s_mips_globl, 0},
858 {"hword", s_cons, 1},
863 {"short", s_cons, 1},
864 {"single", s_float_cons, 'f'},
865 {"stabn", s_mips_stab, 'n'},
866 {"text", s_change_sec, 't'},
869 #ifdef MIPS_STABS_ELF
870 { "extern", ecoff_directive_extern, 0},
876 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
878 /* These pseudo-ops should be defined by the object file format.
879 However, a.out doesn't support them, so we have versions here. */
880 {"aent", s_mips_ent, 1},
881 {"bgnb", s_ignore, 0},
882 {"end", s_mips_end, 0},
883 {"endb", s_ignore, 0},
884 {"ent", s_mips_ent, 0},
886 {"fmask", s_mips_mask, 'F'},
887 {"frame", s_mips_frame, 0},
888 {"loc", s_ignore, 0},
889 {"mask", s_mips_mask, 'R'},
890 {"verstamp", s_ignore, 0},
894 extern void pop_insert PARAMS ((const pseudo_typeS *));
899 pop_insert (mips_pseudo_table);
900 if (! ECOFF_DEBUGGING)
901 pop_insert (mips_nonecoff_pseudo_table);
904 /* Symbols labelling the current insn. */
906 struct insn_label_list
908 struct insn_label_list *next;
912 static struct insn_label_list *insn_labels;
913 static struct insn_label_list *free_insn_labels;
915 static void mips_clear_insn_labels PARAMS ((void));
918 mips_clear_insn_labels ()
920 register struct insn_label_list **pl;
922 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
928 static char *expr_end;
930 /* Expressions which appear in instructions. These are set by
933 static expressionS imm_expr;
934 static expressionS offset_expr;
936 /* Relocs associated with imm_expr and offset_expr. */
938 static bfd_reloc_code_real_type imm_reloc[3]
939 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
940 static bfd_reloc_code_real_type offset_reloc[3]
941 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
943 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
945 static boolean imm_unmatched_hi;
947 /* These are set by mips16_ip if an explicit extension is used. */
949 static boolean mips16_small, mips16_ext;
951 #ifdef MIPS_STABS_ELF
952 /* The pdr segment for per procedure frame/regmask info */
958 mips_isa_to_str (isa)
961 const struct mips_cpu_info *ci;
964 ci = mips_cpu_info_from_isa (isa);
968 sprintf (s, "ISA#%d", isa);
973 mips_cpu_to_str (cpu)
976 const struct mips_cpu_info *ci;
979 ci = mips_cpu_info_from_cpu (cpu);
983 sprintf (s, "CPU#%d", cpu);
987 /* The default target format to use. */
990 mips_target_format ()
992 switch (OUTPUT_FLAVOR)
994 case bfd_target_aout_flavour:
995 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
996 case bfd_target_ecoff_flavour:
997 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
998 case bfd_target_coff_flavour:
1000 case bfd_target_elf_flavour:
1002 /* This is traditional mips */
1003 return (target_big_endian
1004 ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips"
1005 : "elf32-tradbigmips")
1006 : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips"
1007 : "elf32-tradlittlemips"));
1009 return (target_big_endian
1010 ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips")
1011 : (HAVE_64BIT_OBJECTS ? "elf64-littlemips"
1012 : "elf32-littlemips"));
1020 /* This function is called once, at assembler startup time. It should
1021 set up all the tables, etc. that the MD part of the assembler will need. */
1026 register const char *retval = NULL;
1031 int mips_isa_from_cpu;
1032 int target_cpu_had_mips16 = 0;
1033 const struct mips_cpu_info *ci;
1035 /* GP relative stuff not working for PE */
1036 if (strncmp (TARGET_OS, "pe", 2) == 0
1037 && g_switch_value != 0)
1040 as_bad (_("-G not supported in this configuration."));
1045 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
1047 a = xmalloc (sizeof TARGET_CPU);
1048 strcpy (a, TARGET_CPU);
1049 a[(sizeof TARGET_CPU) - 3] = '\0';
1053 if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0)
1055 target_cpu_had_mips16 = 1;
1056 cpu += sizeof "mips16" - 1;
1059 if (mips_opts.mips16 < 0)
1060 mips_opts.mips16 = target_cpu_had_mips16;
1062 /* Backward compatibility for historic -mcpu= option. Check for
1063 incompatible options, warn if -mcpu is used. */
1064 if (mips_cpu != CPU_UNKNOWN
1065 && mips_arch != CPU_UNKNOWN
1066 && mips_cpu != mips_arch)
1068 as_fatal (_("The -mcpu option can't be used together with -march. "
1069 "Use -mtune instead of -mcpu."));
1072 if (mips_cpu != CPU_UNKNOWN
1073 && mips_tune != CPU_UNKNOWN
1074 && mips_cpu != mips_tune)
1076 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1077 "Use -march instead of -mcpu."));
1081 /* For backward compatibility, let -mipsN set various defaults. */
1082 /* This code should go away, to be replaced with something rather more
1083 draconian. Until GCC 3.1 has been released for some reasonable
1084 amount of time, however, we need to support this. */
1085 if (mips_opts.isa != ISA_UNKNOWN)
1087 /* Translate -mipsN to the appropriate settings of file_mips_gp32
1088 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
1089 if (file_mips_gp32 < 0)
1091 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1096 if (file_mips_fp32 < 0)
1098 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1104 ci = mips_cpu_info_from_isa (mips_opts.isa);
1105 assert (ci != NULL);
1106 /* -mipsN has higher priority than -mcpu but lower than -march. */
1107 if (mips_arch == CPU_UNKNOWN)
1108 mips_arch = ci->cpu;
1110 /* Default mips_abi. */
1111 if (mips_opts.abi == NO_ABI)
1113 if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2)
1114 mips_opts.abi = O32_ABI;
1115 else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4)
1116 mips_opts.abi = O64_ABI;
1120 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1122 ci = mips_cpu_info_from_cpu (mips_cpu);
1123 assert (ci != NULL);
1124 mips_arch = ci->cpu;
1125 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1126 "-mtune instead."));
1129 /* Set tune from -mcpu, not from -mipsN. */
1130 if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1132 ci = mips_cpu_info_from_cpu (mips_cpu);
1133 assert (ci != NULL);
1134 mips_tune = ci->cpu;
1137 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1138 specified on the command line, or some other value if one was.
1139 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1140 the command line, or will be set otherwise if one was. */
1142 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1143 /* Handled above. */;
1145 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
1147 ci = mips_cpu_info_from_cpu (mips_cpu);
1148 assert (ci != NULL);
1149 mips_arch = ci->cpu;
1150 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1151 "-mtune instead."));
1154 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1155 specified on the command line, or some other value if one was.
1156 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1157 the command line, or will be set otherwise if one was. */
1159 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1161 /* We have to check if the isa is the default isa of arch. Otherwise
1162 we'll get invalid object file headers. */
1163 ci = mips_cpu_info_from_cpu (mips_arch);
1164 assert (ci != NULL);
1165 if (mips_opts.isa != ci->isa)
1167 /* This really should be an error instead of a warning, but old
1168 compilers only have -mcpu which sets both arch and tune. For
1169 now, we discard arch and preserve tune. */
1170 as_warn (_("The -march option is incompatible to -mipsN and "
1171 "therefore ignored."));
1172 if (mips_tune == CPU_UNKNOWN)
1173 mips_tune = mips_arch;
1174 ci = mips_cpu_info_from_isa (mips_opts.isa);
1175 assert (ci != NULL);
1176 mips_arch = ci->cpu;
1180 else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
1182 /* We have ARCH, we need ISA. */
1183 ci = mips_cpu_info_from_cpu (mips_arch);
1184 assert (ci != NULL);
1185 mips_opts.isa = ci->isa;
1187 else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1189 /* We have ISA, we need default ARCH. */
1190 ci = mips_cpu_info_from_isa (mips_opts.isa);
1191 assert (ci != NULL);
1192 mips_arch = ci->cpu;
1196 /* We need to set both ISA and ARCH from target cpu. */
1197 ci = mips_cpu_info_from_name (cpu);
1199 ci = mips_cpu_info_from_cpu (CPU_R3000);
1200 assert (ci != NULL);
1201 mips_opts.isa = ci->isa;
1202 mips_arch = ci->cpu;
1205 if (mips_tune == CPU_UNKNOWN)
1206 mips_tune = mips_arch;
1208 ci = mips_cpu_info_from_cpu (mips_arch);
1209 assert (ci != NULL);
1210 mips_isa_from_cpu = ci->isa;
1212 /* End of TARGET_CPU processing, get rid of malloced memory
1221 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
1222 as_bad (_("trap exception not supported at ISA 1"));
1224 /* Set the EABI kind based on the ISA before the user gets
1225 to change the ISA with directives. This isn't really
1226 the best, but then neither is basing the abi on the isa. */
1227 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
1228 && mips_opts.abi == EABI_ABI)
1231 /* If they asked for mips1 or mips2 and a cpu that is
1232 mips3 or greater, then mark the object file 32BITMODE. */
1233 if (mips_isa_from_cpu != ISA_UNKNOWN
1234 && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
1235 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
1238 /* If the selected architecture includes support for ASEs, enable
1239 generation of code for them. */
1240 if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch))
1241 mips_opts.ase_mips3d = 1;
1243 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1244 as_warn (_("Could not set architecture and machine"));
1246 if (file_mips_gp32 < 0)
1248 if (file_mips_fp32 < 0)
1251 file_mips_isa = mips_opts.isa;
1252 file_mips_abi = mips_opts.abi;
1253 file_ase_mips3d = mips_opts.ase_mips3d;
1254 mips_opts.gp32 = file_mips_gp32;
1255 mips_opts.fp32 = file_mips_fp32;
1257 op_hash = hash_new ();
1259 for (i = 0; i < NUMOPCODES;)
1261 const char *name = mips_opcodes[i].name;
1263 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1266 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1267 mips_opcodes[i].name, retval);
1268 /* Probably a memory allocation problem? Give up now. */
1269 as_fatal (_("Broken assembler. No assembly attempted."));
1273 if (mips_opcodes[i].pinfo != INSN_MACRO)
1275 if (!validate_mips_insn (&mips_opcodes[i]))
1280 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1283 mips16_op_hash = hash_new ();
1286 while (i < bfd_mips16_num_opcodes)
1288 const char *name = mips16_opcodes[i].name;
1290 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1292 as_fatal (_("internal: can't hash `%s': %s"),
1293 mips16_opcodes[i].name, retval);
1296 if (mips16_opcodes[i].pinfo != INSN_MACRO
1297 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1298 != mips16_opcodes[i].match))
1300 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1301 mips16_opcodes[i].name, mips16_opcodes[i].args);
1306 while (i < bfd_mips16_num_opcodes
1307 && strcmp (mips16_opcodes[i].name, name) == 0);
1311 as_fatal (_("Broken assembler. No assembly attempted."));
1313 /* We add all the general register names to the symbol table. This
1314 helps us detect invalid uses of them. */
1315 for (i = 0; i < 32; i++)
1319 sprintf (buf, "$%d", i);
1320 symbol_table_insert (symbol_new (buf, reg_section, i,
1321 &zero_address_frag));
1323 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1324 &zero_address_frag));
1325 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1326 &zero_address_frag));
1327 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1328 &zero_address_frag));
1329 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1330 &zero_address_frag));
1331 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1332 &zero_address_frag));
1333 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1334 &zero_address_frag));
1335 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1336 &zero_address_frag));
1338 mips_no_prev_insn (false);
1341 mips_cprmask[0] = 0;
1342 mips_cprmask[1] = 0;
1343 mips_cprmask[2] = 0;
1344 mips_cprmask[3] = 0;
1346 /* set the default alignment for the text section (2**2) */
1347 record_alignment (text_section, 2);
1349 if (USE_GLOBAL_POINTER_OPT)
1350 bfd_set_gp_size (stdoutput, g_switch_value);
1352 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1354 /* On a native system, sections must be aligned to 16 byte
1355 boundaries. When configured for an embedded ELF target, we
1357 if (strcmp (TARGET_OS, "elf") != 0)
1359 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1360 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1361 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1364 /* Create a .reginfo section for register masks and a .mdebug
1365 section for debugging information. */
1373 subseg = now_subseg;
1375 /* The ABI says this section should be loaded so that the
1376 running program can access it. However, we don't load it
1377 if we are configured for an embedded target */
1378 flags = SEC_READONLY | SEC_DATA;
1379 if (strcmp (TARGET_OS, "elf") != 0)
1380 flags |= SEC_ALLOC | SEC_LOAD;
1382 if (file_mips_abi != N64_ABI)
1384 sec = subseg_new (".reginfo", (subsegT) 0);
1386 bfd_set_section_flags (stdoutput, sec, flags);
1387 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1390 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1395 /* The 64-bit ABI uses a .MIPS.options section rather than
1396 .reginfo section. */
1397 sec = subseg_new (".MIPS.options", (subsegT) 0);
1398 bfd_set_section_flags (stdoutput, sec, flags);
1399 bfd_set_section_alignment (stdoutput, sec, 3);
1402 /* Set up the option header. */
1404 Elf_Internal_Options opthdr;
1407 opthdr.kind = ODK_REGINFO;
1408 opthdr.size = (sizeof (Elf_External_Options)
1409 + sizeof (Elf64_External_RegInfo));
1412 f = frag_more (sizeof (Elf_External_Options));
1413 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1414 (Elf_External_Options *) f);
1416 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1421 if (ECOFF_DEBUGGING)
1423 sec = subseg_new (".mdebug", (subsegT) 0);
1424 (void) bfd_set_section_flags (stdoutput, sec,
1425 SEC_HAS_CONTENTS | SEC_READONLY);
1426 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1429 #ifdef MIPS_STABS_ELF
1430 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1431 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1432 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
1433 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1436 subseg_set (seg, subseg);
1440 if (! ECOFF_DEBUGGING)
1447 if (! ECOFF_DEBUGGING)
1455 struct mips_cl_insn insn;
1456 bfd_reloc_code_real_type unused_reloc[3]
1457 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1459 imm_expr.X_op = O_absent;
1460 imm_unmatched_hi = false;
1461 offset_expr.X_op = O_absent;
1462 imm_reloc[0] = BFD_RELOC_UNUSED;
1463 imm_reloc[1] = BFD_RELOC_UNUSED;
1464 imm_reloc[2] = BFD_RELOC_UNUSED;
1465 offset_reloc[0] = BFD_RELOC_UNUSED;
1466 offset_reloc[1] = BFD_RELOC_UNUSED;
1467 offset_reloc[2] = BFD_RELOC_UNUSED;
1469 if (mips_opts.mips16)
1470 mips16_ip (str, &insn);
1473 mips_ip (str, &insn);
1474 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1475 str, insn.insn_opcode));
1480 as_bad ("%s `%s'", insn_error, str);
1484 if (insn.insn_mo->pinfo == INSN_MACRO)
1486 if (mips_opts.mips16)
1487 mips16_macro (&insn);
1493 if (imm_expr.X_op != O_absent)
1494 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1495 else if (offset_expr.X_op != O_absent)
1496 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1498 append_insn (NULL, &insn, NULL, unused_reloc, false);
1502 /* See whether instruction IP reads register REG. CLASS is the type
1506 insn_uses_reg (ip, reg, class)
1507 struct mips_cl_insn *ip;
1509 enum mips_regclass class;
1511 if (class == MIPS16_REG)
1513 assert (mips_opts.mips16);
1514 reg = mips16_to_32_reg_map[reg];
1515 class = MIPS_GR_REG;
1518 /* Don't report on general register 0, since it never changes. */
1519 if (class == MIPS_GR_REG && reg == 0)
1522 if (class == MIPS_FP_REG)
1524 assert (! mips_opts.mips16);
1525 /* If we are called with either $f0 or $f1, we must check $f0.
1526 This is not optimal, because it will introduce an unnecessary
1527 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1528 need to distinguish reading both $f0 and $f1 or just one of
1529 them. Note that we don't have to check the other way,
1530 because there is no instruction that sets both $f0 and $f1
1531 and requires a delay. */
1532 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1533 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1534 == (reg &~ (unsigned) 1)))
1536 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1537 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1538 == (reg &~ (unsigned) 1)))
1541 else if (! mips_opts.mips16)
1543 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1544 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1546 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1547 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1552 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1553 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1554 & MIPS16OP_MASK_RX)]
1557 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1558 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1559 & MIPS16OP_MASK_RY)]
1562 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1563 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1564 & MIPS16OP_MASK_MOVE32Z)]
1567 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1569 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1571 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1573 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1574 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1575 & MIPS16OP_MASK_REGR32) == reg)
1582 /* This function returns true if modifying a register requires a
1586 reg_needs_delay (reg)
1589 unsigned long prev_pinfo;
1591 prev_pinfo = prev_insn.insn_mo->pinfo;
1592 if (! mips_opts.noreorder
1593 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1594 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1595 || (! gpr_interlocks
1596 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1598 /* A load from a coprocessor or from memory. All load
1599 delays delay the use of general register rt for one
1600 instruction on the r3000. The r6000 and r4000 use
1602 /* Itbl support may require additional care here. */
1603 know (prev_pinfo & INSN_WRITE_GPR_T);
1604 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1611 /* Mark instruction labels in mips16 mode. This permits the linker to
1612 handle them specially, such as generating jalx instructions when
1613 needed. We also make them odd for the duration of the assembly, in
1614 order to generate the right sort of code. We will make them even
1615 in the adjust_symtab routine, while leaving them marked. This is
1616 convenient for the debugger and the disassembler. The linker knows
1617 to make them odd again. */
1620 mips16_mark_labels ()
1622 if (mips_opts.mips16)
1624 struct insn_label_list *l;
1627 for (l = insn_labels; l != NULL; l = l->next)
1630 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1631 S_SET_OTHER (l->label, STO_MIPS16);
1633 val = S_GET_VALUE (l->label);
1635 S_SET_VALUE (l->label, val + 1);
1640 /* Output an instruction. PLACE is where to put the instruction; if
1641 it is NULL, this uses frag_more to get room. IP is the instruction
1642 information. ADDRESS_EXPR is an operand of the instruction to be
1643 used with RELOC_TYPE. */
1646 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1648 struct mips_cl_insn *ip;
1649 expressionS *address_expr;
1650 bfd_reloc_code_real_type *reloc_type;
1651 boolean unmatched_hi;
1653 register unsigned long prev_pinfo, pinfo;
1658 /* Mark instruction labels in mips16 mode. */
1659 if (mips_opts.mips16)
1660 mips16_mark_labels ();
1662 prev_pinfo = prev_insn.insn_mo->pinfo;
1663 pinfo = ip->insn_mo->pinfo;
1665 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1669 /* If the previous insn required any delay slots, see if we need
1670 to insert a NOP or two. There are eight kinds of possible
1671 hazards, of which an instruction can have at most one type.
1672 (1) a load from memory delay
1673 (2) a load from a coprocessor delay
1674 (3) an unconditional branch delay
1675 (4) a conditional branch delay
1676 (5) a move to coprocessor register delay
1677 (6) a load coprocessor register from memory delay
1678 (7) a coprocessor condition code delay
1679 (8) a HI/LO special register delay
1681 There are a lot of optimizations we could do that we don't.
1682 In particular, we do not, in general, reorder instructions.
1683 If you use gcc with optimization, it will reorder
1684 instructions and generally do much more optimization then we
1685 do here; repeating all that work in the assembler would only
1686 benefit hand written assembly code, and does not seem worth
1689 /* This is how a NOP is emitted. */
1690 #define emit_nop() \
1692 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1693 : md_number_to_chars (frag_more (4), 0, 4))
1695 /* The previous insn might require a delay slot, depending upon
1696 the contents of the current insn. */
1697 if (! mips_opts.mips16
1698 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1699 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1700 && ! cop_interlocks)
1701 || (! gpr_interlocks
1702 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1704 /* A load from a coprocessor or from memory. All load
1705 delays delay the use of general register rt for one
1706 instruction on the r3000. The r6000 and r4000 use
1708 /* Itbl support may require additional care here. */
1709 know (prev_pinfo & INSN_WRITE_GPR_T);
1710 if (mips_optimize == 0
1711 || insn_uses_reg (ip,
1712 ((prev_insn.insn_opcode >> OP_SH_RT)
1717 else if (! mips_opts.mips16
1718 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1719 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1720 && ! cop_interlocks)
1721 || (mips_opts.isa == ISA_MIPS1
1722 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1724 /* A generic coprocessor delay. The previous instruction
1725 modified a coprocessor general or control register. If
1726 it modified a control register, we need to avoid any
1727 coprocessor instruction (this is probably not always
1728 required, but it sometimes is). If it modified a general
1729 register, we avoid using that register.
1731 On the r6000 and r4000 loading a coprocessor register
1732 from memory is interlocked, and does not require a delay.
1734 This case is not handled very well. There is no special
1735 knowledge of CP0 handling, and the coprocessors other
1736 than the floating point unit are not distinguished at
1738 /* Itbl support may require additional care here. FIXME!
1739 Need to modify this to include knowledge about
1740 user specified delays! */
1741 if (prev_pinfo & INSN_WRITE_FPR_T)
1743 if (mips_optimize == 0
1744 || insn_uses_reg (ip,
1745 ((prev_insn.insn_opcode >> OP_SH_FT)
1750 else if (prev_pinfo & INSN_WRITE_FPR_S)
1752 if (mips_optimize == 0
1753 || insn_uses_reg (ip,
1754 ((prev_insn.insn_opcode >> OP_SH_FS)
1761 /* We don't know exactly what the previous instruction
1762 does. If the current instruction uses a coprocessor
1763 register, we must insert a NOP. If previous
1764 instruction may set the condition codes, and the
1765 current instruction uses them, we must insert two
1767 /* Itbl support may require additional care here. */
1768 if (mips_optimize == 0
1769 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1770 && (pinfo & INSN_READ_COND_CODE)))
1772 else if (pinfo & INSN_COP)
1776 else if (! mips_opts.mips16
1777 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1778 && (prev_pinfo & INSN_WRITE_COND_CODE)
1779 && ! cop_interlocks)
1781 /* The previous instruction sets the coprocessor condition
1782 codes, but does not require a general coprocessor delay
1783 (this means it is a floating point comparison
1784 instruction). If this instruction uses the condition
1785 codes, we need to insert a single NOP. */
1786 /* Itbl support may require additional care here. */
1787 if (mips_optimize == 0
1788 || (pinfo & INSN_READ_COND_CODE))
1792 /* If we're fixing up mfhi/mflo for the r7000 and the
1793 previous insn was an mfhi/mflo and the current insn
1794 reads the register that the mfhi/mflo wrote to, then
1797 else if (mips_7000_hilo_fix
1798 && MF_HILO_INSN (prev_pinfo)
1799 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1806 /* If we're fixing up mfhi/mflo for the r7000 and the
1807 2nd previous insn was an mfhi/mflo and the current insn
1808 reads the register that the mfhi/mflo wrote to, then
1811 else if (mips_7000_hilo_fix
1812 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1813 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1821 else if (prev_pinfo & INSN_READ_LO)
1823 /* The previous instruction reads the LO register; if the
1824 current instruction writes to the LO register, we must
1825 insert two NOPS. Some newer processors have interlocks.
1826 Also the tx39's multiply instructions can be exectuted
1827 immediatly after a read from HI/LO (without the delay),
1828 though the tx39's divide insns still do require the
1830 if (! (hilo_interlocks
1831 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1832 && (mips_optimize == 0
1833 || (pinfo & INSN_WRITE_LO)))
1835 /* Most mips16 branch insns don't have a delay slot.
1836 If a read from LO is immediately followed by a branch
1837 to a write to LO we have a read followed by a write
1838 less than 2 insns away. We assume the target of
1839 a branch might be a write to LO, and insert a nop
1840 between a read and an immediately following branch. */
1841 else if (mips_opts.mips16
1842 && (mips_optimize == 0
1843 || (pinfo & MIPS16_INSN_BRANCH)))
1846 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1848 /* The previous instruction reads the HI register; if the
1849 current instruction writes to the HI register, we must
1850 insert a NOP. Some newer processors have interlocks.
1851 Also the note tx39's multiply above. */
1852 if (! (hilo_interlocks
1853 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1854 && (mips_optimize == 0
1855 || (pinfo & INSN_WRITE_HI)))
1857 /* Most mips16 branch insns don't have a delay slot.
1858 If a read from HI is immediately followed by a branch
1859 to a write to HI we have a read followed by a write
1860 less than 2 insns away. We assume the target of
1861 a branch might be a write to HI, and insert a nop
1862 between a read and an immediately following branch. */
1863 else if (mips_opts.mips16
1864 && (mips_optimize == 0
1865 || (pinfo & MIPS16_INSN_BRANCH)))
1869 /* If the previous instruction was in a noreorder section, then
1870 we don't want to insert the nop after all. */
1871 /* Itbl support may require additional care here. */
1872 if (prev_insn_unreordered)
1875 /* There are two cases which require two intervening
1876 instructions: 1) setting the condition codes using a move to
1877 coprocessor instruction which requires a general coprocessor
1878 delay and then reading the condition codes 2) reading the HI
1879 or LO register and then writing to it (except on processors
1880 which have interlocks). If we are not already emitting a NOP
1881 instruction, we must check for these cases compared to the
1882 instruction previous to the previous instruction. */
1883 if ((! mips_opts.mips16
1884 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1885 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1886 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1887 && (pinfo & INSN_READ_COND_CODE)
1888 && ! cop_interlocks)
1889 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1890 && (pinfo & INSN_WRITE_LO)
1891 && ! (hilo_interlocks
1892 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1893 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1894 && (pinfo & INSN_WRITE_HI)
1895 && ! (hilo_interlocks
1896 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1901 if (prev_prev_insn_unreordered)
1904 if (prev_prev_nop && nops == 0)
1907 /* If we are being given a nop instruction, don't bother with
1908 one of the nops we would otherwise output. This will only
1909 happen when a nop instruction is used with mips_optimize set
1912 && ! mips_opts.noreorder
1913 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1916 /* Now emit the right number of NOP instructions. */
1917 if (nops > 0 && ! mips_opts.noreorder)
1920 unsigned long old_frag_offset;
1922 struct insn_label_list *l;
1924 old_frag = frag_now;
1925 old_frag_offset = frag_now_fix ();
1927 for (i = 0; i < nops; i++)
1932 listing_prev_line ();
1933 /* We may be at the start of a variant frag. In case we
1934 are, make sure there is enough space for the frag
1935 after the frags created by listing_prev_line. The
1936 argument to frag_grow here must be at least as large
1937 as the argument to all other calls to frag_grow in
1938 this file. We don't have to worry about being in the
1939 middle of a variant frag, because the variants insert
1940 all needed nop instructions themselves. */
1944 for (l = insn_labels; l != NULL; l = l->next)
1948 assert (S_GET_SEGMENT (l->label) == now_seg);
1949 symbol_set_frag (l->label, frag_now);
1950 val = (valueT) frag_now_fix ();
1951 /* mips16 text labels are stored as odd. */
1952 if (mips_opts.mips16)
1954 S_SET_VALUE (l->label, val);
1957 #ifndef NO_ECOFF_DEBUGGING
1958 if (ECOFF_DEBUGGING)
1959 ecoff_fix_loc (old_frag, old_frag_offset);
1962 else if (prev_nop_frag != NULL)
1964 /* We have a frag holding nops we may be able to remove. If
1965 we don't need any nops, we can decrease the size of
1966 prev_nop_frag by the size of one instruction. If we do
1967 need some nops, we count them in prev_nops_required. */
1968 if (prev_nop_frag_since == 0)
1972 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1973 --prev_nop_frag_holds;
1976 prev_nop_frag_required += nops;
1980 if (prev_prev_nop == 0)
1982 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1983 --prev_nop_frag_holds;
1986 ++prev_nop_frag_required;
1989 if (prev_nop_frag_holds <= prev_nop_frag_required)
1990 prev_nop_frag = NULL;
1992 ++prev_nop_frag_since;
1994 /* Sanity check: by the time we reach the second instruction
1995 after prev_nop_frag, we should have used up all the nops
1996 one way or another. */
1997 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2001 if (*reloc_type > BFD_RELOC_UNUSED)
2003 /* We need to set up a variant frag. */
2004 assert (mips_opts.mips16 && address_expr != NULL);
2005 f = frag_var (rs_machine_dependent, 4, 0,
2006 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2007 mips16_small, mips16_ext,
2009 & INSN_UNCOND_BRANCH_DELAY),
2010 (*prev_insn_reloc_type
2011 == BFD_RELOC_MIPS16_JMP)),
2012 make_expr_symbol (address_expr), 0, NULL);
2014 else if (place != NULL)
2016 else if (mips_opts.mips16
2018 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2020 /* Make sure there is enough room to swap this instruction with
2021 a following jump instruction. */
2027 if (mips_opts.mips16
2028 && mips_opts.noreorder
2029 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2030 as_warn (_("extended instruction in delay slot"));
2035 fixp[0] = fixp[1] = fixp[2] = NULL;
2036 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2038 if (address_expr->X_op == O_constant)
2042 switch (*reloc_type)
2045 ip->insn_opcode |= address_expr->X_add_number;
2048 case BFD_RELOC_MIPS_HIGHEST:
2049 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
2051 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2054 case BFD_RELOC_MIPS_HIGHER:
2055 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2056 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2059 case BFD_RELOC_HI16_S:
2060 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2064 case BFD_RELOC_HI16:
2065 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2068 case BFD_RELOC_LO16:
2069 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2072 case BFD_RELOC_MIPS_JMP:
2073 if ((address_expr->X_add_number & 3) != 0)
2074 as_bad (_("jump to misaligned address (0x%lx)"),
2075 (unsigned long) address_expr->X_add_number);
2076 if (address_expr->X_add_number & ~0xfffffff
2077 || address_expr->X_add_number > 0x7fffffc)
2078 as_bad (_("jump address range overflow (0x%lx)"),
2079 (unsigned long) address_expr->X_add_number);
2080 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2083 case BFD_RELOC_MIPS16_JMP:
2084 if ((address_expr->X_add_number & 3) != 0)
2085 as_bad (_("jump to misaligned address (0x%lx)"),
2086 (unsigned long) address_expr->X_add_number);
2087 if (address_expr->X_add_number & ~0xfffffff
2088 || address_expr->X_add_number > 0x7fffffc)
2089 as_bad (_("jump address range overflow (0x%lx)"),
2090 (unsigned long) address_expr->X_add_number);
2092 (((address_expr->X_add_number & 0x7c0000) << 3)
2093 | ((address_expr->X_add_number & 0xf800000) >> 7)
2094 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2097 case BFD_RELOC_16_PCREL:
2098 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2101 case BFD_RELOC_16_PCREL_S2:
2111 /* Don't generate a reloc if we are writing into a variant frag. */
2114 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
2116 (*reloc_type == BFD_RELOC_16_PCREL
2117 || *reloc_type == BFD_RELOC_16_PCREL_S2),
2120 /* These relocations can have an addend that won't fit in
2121 4 octets for 64bit assembly. */
2122 if (HAVE_64BIT_GPRS &&
2123 (*reloc_type == BFD_RELOC_16
2124 || *reloc_type == BFD_RELOC_32
2125 || *reloc_type == BFD_RELOC_MIPS_JMP
2126 || *reloc_type == BFD_RELOC_HI16_S
2127 || *reloc_type == BFD_RELOC_LO16
2128 || *reloc_type == BFD_RELOC_GPREL16
2129 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2130 || *reloc_type == BFD_RELOC_GPREL32
2131 || *reloc_type == BFD_RELOC_64
2132 || *reloc_type == BFD_RELOC_CTOR
2133 || *reloc_type == BFD_RELOC_MIPS_SUB
2134 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2135 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2136 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2137 || *reloc_type == BFD_RELOC_MIPS_REL16
2138 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2139 fixp[0]->fx_no_overflow = 1;
2143 struct mips_hi_fixup *hi_fixup;
2145 assert (*reloc_type == BFD_RELOC_HI16_S);
2146 hi_fixup = ((struct mips_hi_fixup *)
2147 xmalloc (sizeof (struct mips_hi_fixup)));
2148 hi_fixup->fixp = fixp[0];
2149 hi_fixup->seg = now_seg;
2150 hi_fixup->next = mips_hi_fixup_list;
2151 mips_hi_fixup_list = hi_fixup;
2154 if (reloc_type[1] != BFD_RELOC_UNUSED)
2156 /* FIXME: This symbol can be one of
2157 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2158 address_expr->X_op = O_absent;
2159 address_expr->X_add_symbol = 0;
2160 address_expr->X_add_number = 0;
2162 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2163 4, address_expr, false,
2166 /* These relocations can have an addend that won't fit in
2167 4 octets for 64bit assembly. */
2168 if (HAVE_64BIT_GPRS &&
2169 (*reloc_type == BFD_RELOC_16
2170 || *reloc_type == BFD_RELOC_32
2171 || *reloc_type == BFD_RELOC_MIPS_JMP
2172 || *reloc_type == BFD_RELOC_HI16_S
2173 || *reloc_type == BFD_RELOC_LO16
2174 || *reloc_type == BFD_RELOC_GPREL16
2175 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2176 || *reloc_type == BFD_RELOC_GPREL32
2177 || *reloc_type == BFD_RELOC_64
2178 || *reloc_type == BFD_RELOC_CTOR
2179 || *reloc_type == BFD_RELOC_MIPS_SUB
2180 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2181 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2182 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2183 || *reloc_type == BFD_RELOC_MIPS_REL16
2184 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2185 fixp[1]->fx_no_overflow = 1;
2187 if (reloc_type[2] != BFD_RELOC_UNUSED)
2189 address_expr->X_op = O_absent;
2190 address_expr->X_add_symbol = 0;
2191 address_expr->X_add_number = 0;
2193 fixp[2] = fix_new_exp (frag_now,
2194 f - frag_now->fr_literal, 4,
2195 address_expr, false,
2198 /* These relocations can have an addend that won't fit in
2199 4 octets for 64bit assembly. */
2200 if (HAVE_64BIT_GPRS &&
2201 (*reloc_type == BFD_RELOC_16
2202 || *reloc_type == BFD_RELOC_32
2203 || *reloc_type == BFD_RELOC_MIPS_JMP
2204 || *reloc_type == BFD_RELOC_HI16_S
2205 || *reloc_type == BFD_RELOC_LO16
2206 || *reloc_type == BFD_RELOC_GPREL16
2207 || *reloc_type == BFD_RELOC_MIPS_LITERAL
2208 || *reloc_type == BFD_RELOC_GPREL32
2209 || *reloc_type == BFD_RELOC_64
2210 || *reloc_type == BFD_RELOC_CTOR
2211 || *reloc_type == BFD_RELOC_MIPS_SUB
2212 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2213 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2214 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2215 || *reloc_type == BFD_RELOC_MIPS_REL16
2216 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2217 fixp[2]->fx_no_overflow = 1;
2224 if (! mips_opts.mips16)
2225 md_number_to_chars (f, ip->insn_opcode, 4);
2226 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2228 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2229 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2235 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2238 md_number_to_chars (f, ip->insn_opcode, 2);
2241 /* Update the register mask information. */
2242 if (! mips_opts.mips16)
2244 if (pinfo & INSN_WRITE_GPR_D)
2245 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2246 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2247 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2248 if (pinfo & INSN_READ_GPR_S)
2249 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2250 if (pinfo & INSN_WRITE_GPR_31)
2251 mips_gprmask |= 1 << 31;
2252 if (pinfo & INSN_WRITE_FPR_D)
2253 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2254 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2255 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2256 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2257 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2258 if ((pinfo & INSN_READ_FPR_R) != 0)
2259 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2260 if (pinfo & INSN_COP)
2262 /* We don't keep enough information to sort these cases out.
2263 The itbl support does keep this information however, although
2264 we currently don't support itbl fprmats as part of the cop
2265 instruction. May want to add this support in the future. */
2267 /* Never set the bit for $0, which is always zero. */
2268 mips_gprmask &= ~1 << 0;
2272 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2273 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2274 & MIPS16OP_MASK_RX);
2275 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2276 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2277 & MIPS16OP_MASK_RY);
2278 if (pinfo & MIPS16_INSN_WRITE_Z)
2279 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2280 & MIPS16OP_MASK_RZ);
2281 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2282 mips_gprmask |= 1 << TREG;
2283 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2284 mips_gprmask |= 1 << SP;
2285 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2286 mips_gprmask |= 1 << RA;
2287 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2288 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2289 if (pinfo & MIPS16_INSN_READ_Z)
2290 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2291 & MIPS16OP_MASK_MOVE32Z);
2292 if (pinfo & MIPS16_INSN_READ_GPR_X)
2293 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2294 & MIPS16OP_MASK_REGR32);
2297 if (place == NULL && ! mips_opts.noreorder)
2299 /* Filling the branch delay slot is more complex. We try to
2300 switch the branch with the previous instruction, which we can
2301 do if the previous instruction does not set up a condition
2302 that the branch tests and if the branch is not itself the
2303 target of any branch. */
2304 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2305 || (pinfo & INSN_COND_BRANCH_DELAY))
2307 if (mips_optimize < 2
2308 /* If we have seen .set volatile or .set nomove, don't
2310 || mips_opts.nomove != 0
2311 /* If we had to emit any NOP instructions, then we
2312 already know we can not swap. */
2314 /* If we don't even know the previous insn, we can not
2316 || ! prev_insn_valid
2317 /* If the previous insn is already in a branch delay
2318 slot, then we can not swap. */
2319 || prev_insn_is_delay_slot
2320 /* If the previous previous insn was in a .set
2321 noreorder, we can't swap. Actually, the MIPS
2322 assembler will swap in this situation. However, gcc
2323 configured -with-gnu-as will generate code like
2329 in which we can not swap the bne and INSN. If gcc is
2330 not configured -with-gnu-as, it does not output the
2331 .set pseudo-ops. We don't have to check
2332 prev_insn_unreordered, because prev_insn_valid will
2333 be 0 in that case. We don't want to use
2334 prev_prev_insn_valid, because we do want to be able
2335 to swap at the start of a function. */
2336 || prev_prev_insn_unreordered
2337 /* If the branch is itself the target of a branch, we
2338 can not swap. We cheat on this; all we check for is
2339 whether there is a label on this instruction. If
2340 there are any branches to anything other than a
2341 label, users must use .set noreorder. */
2342 || insn_labels != NULL
2343 /* If the previous instruction is in a variant frag, we
2344 can not do the swap. This does not apply to the
2345 mips16, which uses variant frags for different
2347 || (! mips_opts.mips16
2348 && prev_insn_frag->fr_type == rs_machine_dependent)
2349 /* If the branch reads the condition codes, we don't
2350 even try to swap, because in the sequence
2355 we can not swap, and I don't feel like handling that
2357 || (! mips_opts.mips16
2358 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2359 && (pinfo & INSN_READ_COND_CODE))
2360 /* We can not swap with an instruction that requires a
2361 delay slot, becase the target of the branch might
2362 interfere with that instruction. */
2363 || (! mips_opts.mips16
2364 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2366 /* Itbl support may require additional care here. */
2367 & (INSN_LOAD_COPROC_DELAY
2368 | INSN_COPROC_MOVE_DELAY
2369 | INSN_WRITE_COND_CODE)))
2370 || (! (hilo_interlocks
2371 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2375 || (! mips_opts.mips16
2377 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2378 || (! mips_opts.mips16
2379 && mips_opts.isa == ISA_MIPS1
2380 /* Itbl support may require additional care here. */
2381 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2382 /* We can not swap with a branch instruction. */
2384 & (INSN_UNCOND_BRANCH_DELAY
2385 | INSN_COND_BRANCH_DELAY
2386 | INSN_COND_BRANCH_LIKELY))
2387 /* We do not swap with a trap instruction, since it
2388 complicates trap handlers to have the trap
2389 instruction be in a delay slot. */
2390 || (prev_pinfo & INSN_TRAP)
2391 /* If the branch reads a register that the previous
2392 instruction sets, we can not swap. */
2393 || (! mips_opts.mips16
2394 && (prev_pinfo & INSN_WRITE_GPR_T)
2395 && insn_uses_reg (ip,
2396 ((prev_insn.insn_opcode >> OP_SH_RT)
2399 || (! mips_opts.mips16
2400 && (prev_pinfo & INSN_WRITE_GPR_D)
2401 && insn_uses_reg (ip,
2402 ((prev_insn.insn_opcode >> OP_SH_RD)
2405 || (mips_opts.mips16
2406 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2407 && insn_uses_reg (ip,
2408 ((prev_insn.insn_opcode
2410 & MIPS16OP_MASK_RX),
2412 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2413 && insn_uses_reg (ip,
2414 ((prev_insn.insn_opcode
2416 & MIPS16OP_MASK_RY),
2418 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2419 && insn_uses_reg (ip,
2420 ((prev_insn.insn_opcode
2422 & MIPS16OP_MASK_RZ),
2424 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2425 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2426 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2427 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2428 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2429 && insn_uses_reg (ip,
2430 MIPS16OP_EXTRACT_REG32R (prev_insn.
2433 /* If the branch writes a register that the previous
2434 instruction sets, we can not swap (we know that
2435 branches write only to RD or to $31). */
2436 || (! mips_opts.mips16
2437 && (prev_pinfo & INSN_WRITE_GPR_T)
2438 && (((pinfo & INSN_WRITE_GPR_D)
2439 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2440 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2441 || ((pinfo & INSN_WRITE_GPR_31)
2442 && (((prev_insn.insn_opcode >> OP_SH_RT)
2445 || (! mips_opts.mips16
2446 && (prev_pinfo & INSN_WRITE_GPR_D)
2447 && (((pinfo & INSN_WRITE_GPR_D)
2448 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2449 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2450 || ((pinfo & INSN_WRITE_GPR_31)
2451 && (((prev_insn.insn_opcode >> OP_SH_RD)
2454 || (mips_opts.mips16
2455 && (pinfo & MIPS16_INSN_WRITE_31)
2456 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2457 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2458 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2460 /* If the branch writes a register that the previous
2461 instruction reads, we can not swap (we know that
2462 branches only write to RD or to $31). */
2463 || (! mips_opts.mips16
2464 && (pinfo & INSN_WRITE_GPR_D)
2465 && insn_uses_reg (&prev_insn,
2466 ((ip->insn_opcode >> OP_SH_RD)
2469 || (! mips_opts.mips16
2470 && (pinfo & INSN_WRITE_GPR_31)
2471 && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG))
2472 || (mips_opts.mips16
2473 && (pinfo & MIPS16_INSN_WRITE_31)
2474 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2475 /* If we are generating embedded PIC code, the branch
2476 might be expanded into a sequence which uses $at, so
2477 we can't swap with an instruction which reads it. */
2478 || (mips_pic == EMBEDDED_PIC
2479 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2480 /* If the previous previous instruction has a load
2481 delay, and sets a register that the branch reads, we
2483 || (! mips_opts.mips16
2484 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2485 /* Itbl support may require additional care here. */
2486 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2487 || (! gpr_interlocks
2488 && (prev_prev_insn.insn_mo->pinfo
2489 & INSN_LOAD_MEMORY_DELAY)))
2490 && insn_uses_reg (ip,
2491 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2494 /* If one instruction sets a condition code and the
2495 other one uses a condition code, we can not swap. */
2496 || ((pinfo & INSN_READ_COND_CODE)
2497 && (prev_pinfo & INSN_WRITE_COND_CODE))
2498 || ((pinfo & INSN_WRITE_COND_CODE)
2499 && (prev_pinfo & INSN_READ_COND_CODE))
2500 /* If the previous instruction uses the PC, we can not
2502 || (mips_opts.mips16
2503 && (prev_pinfo & MIPS16_INSN_READ_PC))
2504 /* If the previous instruction was extended, we can not
2506 || (mips_opts.mips16 && prev_insn_extended)
2507 /* If the previous instruction had a fixup in mips16
2508 mode, we can not swap. This normally means that the
2509 previous instruction was a 4 byte branch anyhow. */
2510 || (mips_opts.mips16 && prev_insn_fixp[0])
2511 /* If the previous instruction is a sync, sync.l, or
2512 sync.p, we can not swap. */
2513 || (prev_pinfo & INSN_SYNC))
2515 /* We could do even better for unconditional branches to
2516 portions of this object file; we could pick up the
2517 instruction at the destination, put it in the delay
2518 slot, and bump the destination address. */
2520 /* Update the previous insn information. */
2521 prev_prev_insn = *ip;
2522 prev_insn.insn_mo = &dummy_opcode;
2526 /* It looks like we can actually do the swap. */
2527 if (! mips_opts.mips16)
2532 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2533 memcpy (temp, prev_f, 4);
2534 memcpy (prev_f, f, 4);
2535 memcpy (f, temp, 4);
2536 if (prev_insn_fixp[0])
2538 prev_insn_fixp[0]->fx_frag = frag_now;
2539 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2541 if (prev_insn_fixp[1])
2543 prev_insn_fixp[1]->fx_frag = frag_now;
2544 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2546 if (prev_insn_fixp[2])
2548 prev_insn_fixp[2]->fx_frag = frag_now;
2549 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2553 fixp[0]->fx_frag = prev_insn_frag;
2554 fixp[0]->fx_where = prev_insn_where;
2558 fixp[1]->fx_frag = prev_insn_frag;
2559 fixp[1]->fx_where = prev_insn_where;
2563 fixp[2]->fx_frag = prev_insn_frag;
2564 fixp[2]->fx_where = prev_insn_where;
2572 assert (prev_insn_fixp[0] == NULL);
2573 assert (prev_insn_fixp[1] == NULL);
2574 assert (prev_insn_fixp[2] == NULL);
2575 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2576 memcpy (temp, prev_f, 2);
2577 memcpy (prev_f, f, 2);
2578 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2580 assert (*reloc_type == BFD_RELOC_UNUSED);
2581 memcpy (f, temp, 2);
2585 memcpy (f, f + 2, 2);
2586 memcpy (f + 2, temp, 2);
2590 fixp[0]->fx_frag = prev_insn_frag;
2591 fixp[0]->fx_where = prev_insn_where;
2595 fixp[1]->fx_frag = prev_insn_frag;
2596 fixp[1]->fx_where = prev_insn_where;
2600 fixp[2]->fx_frag = prev_insn_frag;
2601 fixp[2]->fx_where = prev_insn_where;
2605 /* Update the previous insn information; leave prev_insn
2607 prev_prev_insn = *ip;
2609 prev_insn_is_delay_slot = 1;
2611 /* If that was an unconditional branch, forget the previous
2612 insn information. */
2613 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2615 prev_prev_insn.insn_mo = &dummy_opcode;
2616 prev_insn.insn_mo = &dummy_opcode;
2619 prev_insn_fixp[0] = NULL;
2620 prev_insn_fixp[1] = NULL;
2621 prev_insn_fixp[2] = NULL;
2622 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2623 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2624 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2625 prev_insn_extended = 0;
2627 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2629 /* We don't yet optimize a branch likely. What we should do
2630 is look at the target, copy the instruction found there
2631 into the delay slot, and increment the branch to jump to
2632 the next instruction. */
2634 /* Update the previous insn information. */
2635 prev_prev_insn = *ip;
2636 prev_insn.insn_mo = &dummy_opcode;
2637 prev_insn_fixp[0] = NULL;
2638 prev_insn_fixp[1] = NULL;
2639 prev_insn_fixp[2] = NULL;
2640 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2641 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2642 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2643 prev_insn_extended = 0;
2647 /* Update the previous insn information. */
2649 prev_prev_insn.insn_mo = &dummy_opcode;
2651 prev_prev_insn = prev_insn;
2654 /* Any time we see a branch, we always fill the delay slot
2655 immediately; since this insn is not a branch, we know it
2656 is not in a delay slot. */
2657 prev_insn_is_delay_slot = 0;
2659 prev_insn_fixp[0] = fixp[0];
2660 prev_insn_fixp[1] = fixp[1];
2661 prev_insn_fixp[2] = fixp[2];
2662 prev_insn_reloc_type[0] = reloc_type[0];
2663 prev_insn_reloc_type[1] = reloc_type[1];
2664 prev_insn_reloc_type[2] = reloc_type[2];
2665 if (mips_opts.mips16)
2666 prev_insn_extended = (ip->use_extend
2667 || *reloc_type > BFD_RELOC_UNUSED);
2670 prev_prev_insn_unreordered = prev_insn_unreordered;
2671 prev_insn_unreordered = 0;
2672 prev_insn_frag = frag_now;
2673 prev_insn_where = f - frag_now->fr_literal;
2674 prev_insn_valid = 1;
2676 else if (place == NULL)
2678 /* We need to record a bit of information even when we are not
2679 reordering, in order to determine the base address for mips16
2680 PC relative relocs. */
2681 prev_prev_insn = prev_insn;
2683 prev_insn_reloc_type[0] = reloc_type[0];
2684 prev_insn_reloc_type[1] = reloc_type[1];
2685 prev_insn_reloc_type[2] = reloc_type[2];
2686 prev_prev_insn_unreordered = prev_insn_unreordered;
2687 prev_insn_unreordered = 1;
2690 /* We just output an insn, so the next one doesn't have a label. */
2691 mips_clear_insn_labels ();
2693 /* We must ensure that a fixup associated with an unmatched %hi
2694 reloc does not become a variant frag. Otherwise, the
2695 rearrangement of %hi relocs in frob_file may confuse
2699 frag_wane (frag_now);
2704 /* This function forgets that there was any previous instruction or
2705 label. If PRESERVE is non-zero, it remembers enough information to
2706 know whether nops are needed before a noreorder section. */
2709 mips_no_prev_insn (preserve)
2714 prev_insn.insn_mo = &dummy_opcode;
2715 prev_prev_insn.insn_mo = &dummy_opcode;
2716 prev_nop_frag = NULL;
2717 prev_nop_frag_holds = 0;
2718 prev_nop_frag_required = 0;
2719 prev_nop_frag_since = 0;
2721 prev_insn_valid = 0;
2722 prev_insn_is_delay_slot = 0;
2723 prev_insn_unreordered = 0;
2724 prev_insn_extended = 0;
2725 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2726 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2727 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2728 prev_prev_insn_unreordered = 0;
2729 mips_clear_insn_labels ();
2732 /* This function must be called whenever we turn on noreorder or emit
2733 something other than instructions. It inserts any NOPS which might
2734 be needed by the previous instruction, and clears the information
2735 kept for the previous instructions. The INSNS parameter is true if
2736 instructions are to follow. */
2739 mips_emit_delays (insns)
2742 if (! mips_opts.noreorder)
2747 if ((! mips_opts.mips16
2748 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2749 && (! cop_interlocks
2750 && (prev_insn.insn_mo->pinfo
2751 & (INSN_LOAD_COPROC_DELAY
2752 | INSN_COPROC_MOVE_DELAY
2753 | INSN_WRITE_COND_CODE))))
2754 || (! hilo_interlocks
2755 && (prev_insn.insn_mo->pinfo
2758 || (! mips_opts.mips16
2760 && (prev_insn.insn_mo->pinfo
2761 & INSN_LOAD_MEMORY_DELAY))
2762 || (! mips_opts.mips16
2763 && mips_opts.isa == ISA_MIPS1
2764 && (prev_insn.insn_mo->pinfo
2765 & INSN_COPROC_MEMORY_DELAY)))
2767 /* Itbl support may require additional care here. */
2769 if ((! mips_opts.mips16
2770 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2771 && (! cop_interlocks
2772 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2773 || (! hilo_interlocks
2774 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2775 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2778 if (prev_insn_unreordered)
2781 else if ((! mips_opts.mips16
2782 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2783 && (! cop_interlocks
2784 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2785 || (! hilo_interlocks
2786 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2787 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2789 /* Itbl support may require additional care here. */
2790 if (! prev_prev_insn_unreordered)
2796 struct insn_label_list *l;
2800 /* Record the frag which holds the nop instructions, so
2801 that we can remove them if we don't need them. */
2802 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2803 prev_nop_frag = frag_now;
2804 prev_nop_frag_holds = nops;
2805 prev_nop_frag_required = 0;
2806 prev_nop_frag_since = 0;
2809 for (; nops > 0; --nops)
2814 /* Move on to a new frag, so that it is safe to simply
2815 decrease the size of prev_nop_frag. */
2816 frag_wane (frag_now);
2820 for (l = insn_labels; l != NULL; l = l->next)
2824 assert (S_GET_SEGMENT (l->label) == now_seg);
2825 symbol_set_frag (l->label, frag_now);
2826 val = (valueT) frag_now_fix ();
2827 /* mips16 text labels are stored as odd. */
2828 if (mips_opts.mips16)
2830 S_SET_VALUE (l->label, val);
2835 /* Mark instruction labels in mips16 mode. */
2836 if (mips_opts.mips16 && insns)
2837 mips16_mark_labels ();
2839 mips_no_prev_insn (insns);
2842 /* Build an instruction created by a macro expansion. This is passed
2843 a pointer to the count of instructions created so far, an
2844 expression, the name of the instruction to build, an operand format
2845 string, and corresponding arguments. */
2849 macro_build (char *place,
2857 macro_build (place, counter, ep, name, fmt, va_alist)
2866 struct mips_cl_insn insn;
2867 bfd_reloc_code_real_type r[3];
2871 va_start (args, fmt);
2877 * If the macro is about to expand into a second instruction,
2878 * print a warning if needed. We need to pass ip as a parameter
2879 * to generate a better warning message here...
2881 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2882 as_warn (_("Macro instruction expanded into multiple instructions"));
2885 * If the macro is about to expand into a second instruction,
2886 * and it is in a delay slot, print a warning.
2890 && mips_opts.noreorder
2891 && (prev_prev_insn.insn_mo->pinfo
2892 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2893 | INSN_COND_BRANCH_LIKELY)) != 0)
2894 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2897 *counter += 1; /* bump instruction counter */
2899 if (mips_opts.mips16)
2901 mips16_macro_build (place, counter, ep, name, fmt, args);
2906 r[0] = BFD_RELOC_UNUSED;
2907 r[1] = BFD_RELOC_UNUSED;
2908 r[2] = BFD_RELOC_UNUSED;
2909 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2910 assert (insn.insn_mo);
2911 assert (strcmp (name, insn.insn_mo->name) == 0);
2913 /* Search until we get a match for NAME. */
2916 /* It is assumed here that macros will never generate
2917 MIPS-3D instructions. */
2918 if (strcmp (fmt, insn.insn_mo->args) == 0
2919 && insn.insn_mo->pinfo != INSN_MACRO
2920 && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
2921 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2925 assert (insn.insn_mo->name);
2926 assert (strcmp (name, insn.insn_mo->name) == 0);
2929 insn.insn_opcode = insn.insn_mo->match;
2945 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2949 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2954 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2959 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2964 int tmp = va_arg (args, int);
2966 insn.insn_opcode |= tmp << OP_SH_RT;
2967 insn.insn_opcode |= tmp << OP_SH_RD;
2973 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2980 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2984 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2988 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2992 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2996 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3003 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3009 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3010 assert (*r == BFD_RELOC_GPREL16
3011 || *r == BFD_RELOC_MIPS_LITERAL
3012 || *r == BFD_RELOC_MIPS_HIGHER
3013 || *r == BFD_RELOC_HI16_S
3014 || *r == BFD_RELOC_LO16
3015 || *r == BFD_RELOC_MIPS_GOT16
3016 || *r == BFD_RELOC_MIPS_CALL16
3017 || *r == BFD_RELOC_MIPS_GOT_LO16
3018 || *r == BFD_RELOC_MIPS_CALL_LO16
3019 || (ep->X_op == O_subtract
3020 && *r == BFD_RELOC_PCREL_LO16));
3024 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3026 && (ep->X_op == O_constant
3027 || (ep->X_op == O_symbol
3028 && (*r == BFD_RELOC_MIPS_HIGHEST
3029 || *r == BFD_RELOC_HI16_S
3030 || *r == BFD_RELOC_HI16
3031 || *r == BFD_RELOC_GPREL16
3032 || *r == BFD_RELOC_MIPS_GOT_HI16
3033 || *r == BFD_RELOC_MIPS_CALL_HI16))
3034 || (ep->X_op == O_subtract
3035 && *r == BFD_RELOC_PCREL_HI16_S)));
3039 assert (ep != NULL);
3041 * This allows macro() to pass an immediate expression for
3042 * creating short branches without creating a symbol.
3043 * Note that the expression still might come from the assembly
3044 * input, in which case the value is not checked for range nor
3045 * is a relocation entry generated (yuck).
3047 if (ep->X_op == O_constant)
3049 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3053 if (mips_pic == EMBEDDED_PIC)
3054 *r = BFD_RELOC_16_PCREL_S2;
3056 *r = BFD_RELOC_16_PCREL;
3060 assert (ep != NULL);
3061 *r = BFD_RELOC_MIPS_JMP;
3065 insn.insn_opcode |= va_arg (args, unsigned long);
3074 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3076 append_insn (place, &insn, ep, r, false);
3080 mips16_macro_build (place, counter, ep, name, fmt, args)
3082 int *counter ATTRIBUTE_UNUSED;
3088 struct mips_cl_insn insn;
3089 bfd_reloc_code_real_type r[3]
3090 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3092 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3093 assert (insn.insn_mo);
3094 assert (strcmp (name, insn.insn_mo->name) == 0);
3096 while (strcmp (fmt, insn.insn_mo->args) != 0
3097 || insn.insn_mo->pinfo == INSN_MACRO)
3100 assert (insn.insn_mo->name);
3101 assert (strcmp (name, insn.insn_mo->name) == 0);
3104 insn.insn_opcode = insn.insn_mo->match;
3105 insn.use_extend = false;
3124 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3129 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3133 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3137 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3147 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3154 regno = va_arg (args, int);
3155 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3156 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3177 assert (ep != NULL);
3179 if (ep->X_op != O_constant)
3180 *r = (int) BFD_RELOC_UNUSED + c;
3183 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
3184 false, &insn.insn_opcode, &insn.use_extend,
3187 *r = BFD_RELOC_UNUSED;
3193 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3200 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3202 append_insn (place, &insn, ep, r, false);
3206 * Generate a "lui" instruction.
3209 macro_build_lui (place, counter, ep, regnum)
3215 expressionS high_expr;
3216 struct mips_cl_insn insn;
3217 bfd_reloc_code_real_type r[3]
3218 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3219 CONST char *name = "lui";
3220 CONST char *fmt = "t,u";
3222 assert (! mips_opts.mips16);
3228 high_expr.X_op = O_constant;
3229 high_expr.X_add_number = ep->X_add_number;
3232 if (high_expr.X_op == O_constant)
3234 /* we can compute the instruction now without a relocation entry */
3235 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3237 *r = BFD_RELOC_UNUSED;
3239 else if (! HAVE_NEWABI)
3241 assert (ep->X_op == O_symbol);
3242 /* _gp_disp is a special case, used from s_cpload. */
3243 assert (mips_pic == NO_PIC
3244 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3245 *r = BFD_RELOC_HI16_S;
3249 * If the macro is about to expand into a second instruction,
3250 * print a warning if needed. We need to pass ip as a parameter
3251 * to generate a better warning message here...
3253 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3254 as_warn (_("Macro instruction expanded into multiple instructions"));
3257 *counter += 1; /* bump instruction counter */
3259 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3260 assert (insn.insn_mo);
3261 assert (strcmp (name, insn.insn_mo->name) == 0);
3262 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3264 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3265 if (*r == BFD_RELOC_UNUSED)
3267 insn.insn_opcode |= high_expr.X_add_number;
3268 append_insn (place, &insn, NULL, r, false);
3271 append_insn (place, &insn, &high_expr, r, false);
3275 * Generates code to set the $at register to true (one)
3276 * if reg is less than the immediate expression.
3279 set_at (counter, reg, unsignedp)
3284 if (imm_expr.X_op == O_constant
3285 && imm_expr.X_add_number >= -0x8000
3286 && imm_expr.X_add_number < 0x8000)
3287 macro_build ((char *) NULL, counter, &imm_expr,
3288 unsignedp ? "sltiu" : "slti",
3289 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3292 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3293 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3294 unsignedp ? "sltu" : "slt",
3295 "d,v,t", AT, reg, AT);
3299 /* Warn if an expression is not a constant. */
3302 check_absolute_expr (ip, ex)
3303 struct mips_cl_insn *ip;
3306 if (ex->X_op == O_big)
3307 as_bad (_("unsupported large constant"));
3308 else if (ex->X_op != O_constant)
3309 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3312 /* Count the leading zeroes by performing a binary chop. This is a
3313 bulky bit of source, but performance is a LOT better for the
3314 majority of values than a simple loop to count the bits:
3315 for (lcnt = 0; (lcnt < 32); lcnt++)
3316 if ((v) & (1 << (31 - lcnt)))
3318 However it is not code size friendly, and the gain will drop a bit
3319 on certain cached systems.
3321 #define COUNT_TOP_ZEROES(v) \
3322 (((v) & ~0xffff) == 0 \
3323 ? ((v) & ~0xff) == 0 \
3324 ? ((v) & ~0xf) == 0 \
3325 ? ((v) & ~0x3) == 0 \
3326 ? ((v) & ~0x1) == 0 \
3331 : ((v) & ~0x7) == 0 \
3334 : ((v) & ~0x3f) == 0 \
3335 ? ((v) & ~0x1f) == 0 \
3338 : ((v) & ~0x7f) == 0 \
3341 : ((v) & ~0xfff) == 0 \
3342 ? ((v) & ~0x3ff) == 0 \
3343 ? ((v) & ~0x1ff) == 0 \
3346 : ((v) & ~0x7ff) == 0 \
3349 : ((v) & ~0x3fff) == 0 \
3350 ? ((v) & ~0x1fff) == 0 \
3353 : ((v) & ~0x7fff) == 0 \
3356 : ((v) & ~0xffffff) == 0 \
3357 ? ((v) & ~0xfffff) == 0 \
3358 ? ((v) & ~0x3ffff) == 0 \
3359 ? ((v) & ~0x1ffff) == 0 \
3362 : ((v) & ~0x7ffff) == 0 \
3365 : ((v) & ~0x3fffff) == 0 \
3366 ? ((v) & ~0x1fffff) == 0 \
3369 : ((v) & ~0x7fffff) == 0 \
3372 : ((v) & ~0xfffffff) == 0 \
3373 ? ((v) & ~0x3ffffff) == 0 \
3374 ? ((v) & ~0x1ffffff) == 0 \
3377 : ((v) & ~0x7ffffff) == 0 \
3380 : ((v) & ~0x3fffffff) == 0 \
3381 ? ((v) & ~0x1fffffff) == 0 \
3384 : ((v) & ~0x7fffffff) == 0 \
3388 /* Is the given value a sign-extended 32-bit value? */
3389 #define IS_SEXT_32BIT_NUM(x) \
3390 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3391 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3394 * This routine generates the least number of instructions neccessary to load
3395 * an absolute expression value into a register.
3398 load_register (counter, reg, ep, dbl)
3405 expressionS hi32, lo32;
3407 if (ep->X_op != O_big)
3409 assert (ep->X_op == O_constant);
3410 if (ep->X_add_number < 0x8000
3411 && (ep->X_add_number >= 0
3412 || (ep->X_add_number >= -0x8000
3415 || sizeof (ep->X_add_number) > 4))))
3417 /* We can handle 16 bit signed values with an addiu to
3418 $zero. No need to ever use daddiu here, since $zero and
3419 the result are always correct in 32 bit mode. */
3420 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3421 (int) BFD_RELOC_LO16);
3424 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3426 /* We can handle 16 bit unsigned values with an ori to
3428 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3429 (int) BFD_RELOC_LO16);
3432 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3435 || sizeof (ep->X_add_number) > 4
3436 || (ep->X_add_number & 0x80000000) == 0))
3437 || ((HAVE_32BIT_GPRS || ! dbl)
3438 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3441 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3442 == ~ (offsetT) 0xffffffff)))
3444 /* 32 bit values require an lui. */
3445 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3446 (int) BFD_RELOC_HI16);
3447 if ((ep->X_add_number & 0xffff) != 0)
3448 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3449 (int) BFD_RELOC_LO16);
3454 /* The value is larger than 32 bits. */
3456 if (HAVE_32BIT_GPRS)
3458 as_bad (_("Number (0x%lx) larger than 32 bits"),
3459 (unsigned long) ep->X_add_number);
3460 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3461 (int) BFD_RELOC_LO16);
3465 if (ep->X_op != O_big)
3468 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3469 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3470 hi32.X_add_number &= 0xffffffff;
3472 lo32.X_add_number &= 0xffffffff;
3476 assert (ep->X_add_number > 2);
3477 if (ep->X_add_number == 3)
3478 generic_bignum[3] = 0;
3479 else if (ep->X_add_number > 4)
3480 as_bad (_("Number larger than 64 bits"));
3481 lo32.X_op = O_constant;
3482 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3483 hi32.X_op = O_constant;
3484 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3487 if (hi32.X_add_number == 0)
3492 unsigned long hi, lo;
3494 if (hi32.X_add_number == (offsetT) 0xffffffff)
3496 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3498 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3499 reg, 0, (int) BFD_RELOC_LO16);
3502 if (lo32.X_add_number & 0x80000000)
3504 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3505 (int) BFD_RELOC_HI16);
3506 if (lo32.X_add_number & 0xffff)
3507 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3508 reg, reg, (int) BFD_RELOC_LO16);
3513 /* Check for 16bit shifted constant. We know that hi32 is
3514 non-zero, so start the mask on the first bit of the hi32
3519 unsigned long himask, lomask;
3523 himask = 0xffff >> (32 - shift);
3524 lomask = (0xffff << shift) & 0xffffffff;
3528 himask = 0xffff << (shift - 32);
3531 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3532 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3536 tmp.X_op = O_constant;
3538 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3539 | (lo32.X_add_number >> shift));
3541 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3542 macro_build ((char *) NULL, counter, &tmp,
3543 "ori", "t,r,i", reg, 0,
3544 (int) BFD_RELOC_LO16);
3545 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3546 (shift >= 32) ? "dsll32" : "dsll",
3548 (shift >= 32) ? shift - 32 : shift);
3553 while (shift <= (64 - 16));
3555 /* Find the bit number of the lowest one bit, and store the
3556 shifted value in hi/lo. */
3557 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3558 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3562 while ((lo & 1) == 0)
3567 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3573 while ((hi & 1) == 0)
3582 /* Optimize if the shifted value is a (power of 2) - 1. */
3583 if ((hi == 0 && ((lo + 1) & lo) == 0)
3584 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3586 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3591 /* This instruction will set the register to be all
3593 tmp.X_op = O_constant;
3594 tmp.X_add_number = (offsetT) -1;
3595 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3596 reg, 0, (int) BFD_RELOC_LO16);
3600 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3601 (bit >= 32) ? "dsll32" : "dsll",
3603 (bit >= 32) ? bit - 32 : bit);
3605 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3606 (shift >= 32) ? "dsrl32" : "dsrl",
3608 (shift >= 32) ? shift - 32 : shift);
3613 /* Sign extend hi32 before calling load_register, because we can
3614 generally get better code when we load a sign extended value. */
3615 if ((hi32.X_add_number & 0x80000000) != 0)
3616 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3617 load_register (counter, reg, &hi32, 0);
3620 if ((lo32.X_add_number & 0xffff0000) == 0)
3624 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3625 "dsll32", "d,w,<", reg, freg, 0);
3633 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3635 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3636 (int) BFD_RELOC_HI16);
3637 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3638 "dsrl32", "d,w,<", reg, reg, 0);
3644 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3645 "d,w,<", reg, freg, 16);
3649 mid16.X_add_number >>= 16;
3650 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3651 freg, (int) BFD_RELOC_LO16);
3652 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3653 "d,w,<", reg, reg, 16);
3656 if ((lo32.X_add_number & 0xffff) != 0)
3657 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3658 (int) BFD_RELOC_LO16);
3661 /* Load an address into a register. */
3664 load_address (counter, reg, ep, dbl, used_at)
3673 if (ep->X_op != O_constant
3674 && ep->X_op != O_symbol)
3676 as_bad (_("expression too complex"));
3677 ep->X_op = O_constant;
3680 if (ep->X_op == O_constant)
3682 load_register (counter, reg, ep, dbl);
3686 if (mips_pic == NO_PIC)
3688 /* If this is a reference to a GP relative symbol, we want
3689 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3691 lui $reg,<sym> (BFD_RELOC_HI16_S)
3692 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3693 If we have an addend, we always use the latter form.
3695 With 64bit address space and a usable $at we want
3696 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3697 lui $at,<sym> (BFD_RELOC_HI16_S)
3698 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3699 daddiu $at,<sym> (BFD_RELOC_LO16)
3703 If $at is already in use, we use an path which is suboptimal
3704 on superscalar processors.
3705 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3706 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3708 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3710 daddiu $reg,<sym> (BFD_RELOC_LO16)
3716 /* We don't do GP optimization for now because RELAX_ENCODE can't
3717 hold the data for such large chunks. */
3721 macro_build (p, counter, ep, "lui", "t,u",
3722 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3723 macro_build (p, counter, ep, "lui", "t,u",
3724 AT, (int) BFD_RELOC_HI16_S);
3725 macro_build (p, counter, ep, "daddiu", "t,r,j",
3726 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3727 macro_build (p, counter, ep, "daddiu", "t,r,j",
3728 AT, AT, (int) BFD_RELOC_LO16);
3729 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3730 "d,w,<", reg, reg, 0);
3731 macro_build (p, counter, (expressionS *) NULL, "dadd",
3732 "d,v,t", reg, reg, AT);
3737 macro_build (p, counter, ep, "lui", "t,u",
3738 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3739 macro_build (p, counter, ep, "daddiu", "t,r,j",
3740 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3741 macro_build (p, counter, (expressionS *) NULL, "dsll",
3742 "d,w,<", reg, reg, 16);
3743 macro_build (p, counter, ep, "daddiu", "t,r,j",
3744 reg, reg, (int) BFD_RELOC_HI16_S);
3745 macro_build (p, counter, (expressionS *) NULL, "dsll",
3746 "d,w,<", reg, reg, 16);
3747 macro_build (p, counter, ep, "daddiu", "t,r,j",
3748 reg, reg, (int) BFD_RELOC_LO16);
3754 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3755 && ! nopic_need_relax (ep->X_add_symbol, 1))
3758 macro_build ((char *) NULL, counter, ep,
3759 dbl ? "daddiu" : "addiu", "t,r,j", reg, GP,
3760 (int) BFD_RELOC_GPREL16);
3761 p = frag_var (rs_machine_dependent, 8, 0,
3762 RELAX_ENCODE (4, 8, 0, 4, 0,
3763 mips_opts.warn_about_macros),
3764 ep->X_add_symbol, 0, NULL);
3766 macro_build_lui (p, counter, ep, reg);
3769 macro_build (p, counter, ep, dbl ? "daddiu" : "addiu",
3770 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3773 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3777 /* If this is a reference to an external symbol, we want
3778 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3780 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3782 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3783 If there is a constant, it must be added in after. */
3784 ex.X_add_number = ep->X_add_number;
3785 ep->X_add_number = 0;
3787 macro_build ((char *) NULL, counter, ep,
3788 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3789 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
3790 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3791 p = frag_var (rs_machine_dependent, 4, 0,
3792 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3793 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3794 macro_build (p, counter, ep,
3795 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3796 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3797 if (ex.X_add_number != 0)
3799 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3800 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3801 ex.X_op = O_constant;
3802 macro_build ((char *) NULL, counter, &ex,
3803 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3804 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3807 else if (mips_pic == SVR4_PIC)
3812 /* This is the large GOT case. If this is a reference to an
3813 external symbol, we want
3814 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3816 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3817 Otherwise, for a reference to a local symbol, we want
3818 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3820 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3821 If there is a constant, it must be added in after. */
3822 ex.X_add_number = ep->X_add_number;
3823 ep->X_add_number = 0;
3824 if (reg_needs_delay (GP))
3829 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3830 (int) BFD_RELOC_MIPS_GOT_HI16);
3831 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3832 dbl ? "daddu" : "addu", "d,v,t", reg, reg, GP);
3833 macro_build ((char *) NULL, counter, ep, dbl ? "ld" : "lw",
3834 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3835 p = frag_var (rs_machine_dependent, 12 + off, 0,
3836 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3837 mips_opts.warn_about_macros),
3838 ep->X_add_symbol, 0, NULL);
3841 /* We need a nop before loading from $gp. This special
3842 check is required because the lui which starts the main
3843 instruction stream does not refer to $gp, and so will not
3844 insert the nop which may be required. */
3845 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3848 macro_build (p, counter, ep, dbl ? "ld" : "lw",
3849 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
3851 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3853 macro_build (p, counter, ep, dbl ? "daddiu" : "addiu",
3854 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3855 if (ex.X_add_number != 0)
3857 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3858 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3859 ex.X_op = O_constant;
3860 macro_build ((char *) NULL, counter, &ex, dbl ? "daddiu" : "addiu",
3861 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3864 else if (mips_pic == EMBEDDED_PIC)
3867 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3869 macro_build ((char *) NULL, counter, ep, dbl ? "daddiu" : "addiu",
3870 "t,r,j", reg, GP, (int) BFD_RELOC_GPREL16);
3876 /* Move the contents of register SOURCE into register DEST. */
3879 move_register (counter, dest, source)
3884 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3885 HAVE_32BIT_GPRS ? "addu" : "daddu",
3886 "d,v,t", dest, source, 0);
3891 * This routine implements the seemingly endless macro or synthesized
3892 * instructions and addressing modes in the mips assembly language. Many
3893 * of these macros are simple and are similar to each other. These could
3894 * probably be handled by some kind of table or grammer aproach instead of
3895 * this verbose method. Others are not simple macros but are more like
3896 * optimizing code generation.
3897 * One interesting optimization is when several store macros appear
3898 * consecutivly that would load AT with the upper half of the same address.
3899 * The ensuing load upper instructions are ommited. This implies some kind
3900 * of global optimization. We currently only optimize within a single macro.
3901 * For many of the load and store macros if the address is specified as a
3902 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3903 * first load register 'at' with zero and use it as the base register. The
3904 * mips assembler simply uses register $zero. Just one tiny optimization
3909 struct mips_cl_insn *ip;
3911 register int treg, sreg, dreg, breg;
3927 bfd_reloc_code_real_type r;
3929 int hold_mips_optimize;
3931 assert (! mips_opts.mips16);
3933 treg = (ip->insn_opcode >> 16) & 0x1f;
3934 dreg = (ip->insn_opcode >> 11) & 0x1f;
3935 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3936 mask = ip->insn_mo->mask;
3938 expr1.X_op = O_constant;
3939 expr1.X_op_symbol = NULL;
3940 expr1.X_add_symbol = NULL;
3941 expr1.X_add_number = 1;
3953 mips_emit_delays (true);
3954 ++mips_opts.noreorder;
3955 mips_any_noreorder = 1;
3957 expr1.X_add_number = 8;
3958 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3960 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3963 move_register (&icnt, dreg, sreg);
3964 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3965 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3967 --mips_opts.noreorder;
3988 if (imm_expr.X_op == O_constant
3989 && imm_expr.X_add_number >= -0x8000
3990 && imm_expr.X_add_number < 0x8000)
3992 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3993 (int) BFD_RELOC_LO16);
3996 load_register (&icnt, AT, &imm_expr, dbl);
3997 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4017 if (imm_expr.X_op == O_constant
4018 && imm_expr.X_add_number >= 0
4019 && imm_expr.X_add_number < 0x10000)
4021 if (mask != M_NOR_I)
4022 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
4023 sreg, (int) BFD_RELOC_LO16);
4026 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
4027 treg, sreg, (int) BFD_RELOC_LO16);
4028 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
4029 "d,v,t", treg, treg, 0);
4034 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4035 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
4053 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4055 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
4059 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
4060 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
4068 macro_build ((char *) NULL, &icnt, &offset_expr,
4069 likely ? "bgezl" : "bgez", "s,p", sreg);
4074 macro_build ((char *) NULL, &icnt, &offset_expr,
4075 likely ? "blezl" : "blez", "s,p", treg);
4078 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4080 macro_build ((char *) NULL, &icnt, &offset_expr,
4081 likely ? "beql" : "beq", "s,t,p", AT, 0);
4087 /* check for > max integer */
4088 maxnum = 0x7fffffff;
4089 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4096 if (imm_expr.X_op == O_constant
4097 && imm_expr.X_add_number >= maxnum
4098 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4101 /* result is always false */
4105 as_warn (_("Branch %s is always false (nop)"),
4107 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
4113 as_warn (_("Branch likely %s is always false"),
4115 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
4120 if (imm_expr.X_op != O_constant)
4121 as_bad (_("Unsupported large constant"));
4122 imm_expr.X_add_number++;
4126 if (mask == M_BGEL_I)
4128 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4130 macro_build ((char *) NULL, &icnt, &offset_expr,
4131 likely ? "bgezl" : "bgez", "s,p", sreg);
4134 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4136 macro_build ((char *) NULL, &icnt, &offset_expr,
4137 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4140 maxnum = 0x7fffffff;
4141 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4148 maxnum = - maxnum - 1;
4149 if (imm_expr.X_op == O_constant
4150 && imm_expr.X_add_number <= maxnum
4151 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4154 /* result is always true */
4155 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4156 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4159 set_at (&icnt, sreg, 0);
4160 macro_build ((char *) NULL, &icnt, &offset_expr,
4161 likely ? "beql" : "beq", "s,t,p", AT, 0);
4171 macro_build ((char *) NULL, &icnt, &offset_expr,
4172 likely ? "beql" : "beq", "s,t,p", 0, treg);
4175 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4176 "d,v,t", AT, sreg, treg);
4177 macro_build ((char *) NULL, &icnt, &offset_expr,
4178 likely ? "beql" : "beq", "s,t,p", AT, 0);
4186 && imm_expr.X_op == O_constant
4187 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4189 if (imm_expr.X_op != O_constant)
4190 as_bad (_("Unsupported large constant"));
4191 imm_expr.X_add_number++;
4195 if (mask == M_BGEUL_I)
4197 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4199 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4201 macro_build ((char *) NULL, &icnt, &offset_expr,
4202 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4205 set_at (&icnt, sreg, 1);
4206 macro_build ((char *) NULL, &icnt, &offset_expr,
4207 likely ? "beql" : "beq", "s,t,p", AT, 0);
4215 macro_build ((char *) NULL, &icnt, &offset_expr,
4216 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4221 macro_build ((char *) NULL, &icnt, &offset_expr,
4222 likely ? "bltzl" : "bltz", "s,p", treg);
4225 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4227 macro_build ((char *) NULL, &icnt, &offset_expr,
4228 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4236 macro_build ((char *) NULL, &icnt, &offset_expr,
4237 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4242 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4243 "d,v,t", AT, treg, sreg);
4244 macro_build ((char *) NULL, &icnt, &offset_expr,
4245 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4253 macro_build ((char *) NULL, &icnt, &offset_expr,
4254 likely ? "blezl" : "blez", "s,p", sreg);
4259 macro_build ((char *) NULL, &icnt, &offset_expr,
4260 likely ? "bgezl" : "bgez", "s,p", treg);
4263 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4265 macro_build ((char *) NULL, &icnt, &offset_expr,
4266 likely ? "beql" : "beq", "s,t,p", AT, 0);
4272 maxnum = 0x7fffffff;
4273 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4280 if (imm_expr.X_op == O_constant
4281 && imm_expr.X_add_number >= maxnum
4282 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4284 if (imm_expr.X_op != O_constant)
4285 as_bad (_("Unsupported large constant"));
4286 imm_expr.X_add_number++;
4290 if (mask == M_BLTL_I)
4292 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4294 macro_build ((char *) NULL, &icnt, &offset_expr,
4295 likely ? "bltzl" : "bltz", "s,p", sreg);
4298 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4300 macro_build ((char *) NULL, &icnt, &offset_expr,
4301 likely ? "blezl" : "blez", "s,p", sreg);
4304 set_at (&icnt, sreg, 0);
4305 macro_build ((char *) NULL, &icnt, &offset_expr,
4306 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4314 macro_build ((char *) NULL, &icnt, &offset_expr,
4315 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4320 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4321 "d,v,t", AT, treg, sreg);
4322 macro_build ((char *) NULL, &icnt, &offset_expr,
4323 likely ? "beql" : "beq", "s,t,p", AT, 0);
4331 && imm_expr.X_op == O_constant
4332 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4334 if (imm_expr.X_op != O_constant)
4335 as_bad (_("Unsupported large constant"));
4336 imm_expr.X_add_number++;
4340 if (mask == M_BLTUL_I)
4342 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4344 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4346 macro_build ((char *) NULL, &icnt, &offset_expr,
4347 likely ? "beql" : "beq",
4351 set_at (&icnt, sreg, 1);
4352 macro_build ((char *) NULL, &icnt, &offset_expr,
4353 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4361 macro_build ((char *) NULL, &icnt, &offset_expr,
4362 likely ? "bltzl" : "bltz", "s,p", sreg);
4367 macro_build ((char *) NULL, &icnt, &offset_expr,
4368 likely ? "bgtzl" : "bgtz", "s,p", treg);
4371 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4373 macro_build ((char *) NULL, &icnt, &offset_expr,
4374 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4384 macro_build ((char *) NULL, &icnt, &offset_expr,
4385 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4388 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4391 macro_build ((char *) NULL, &icnt, &offset_expr,
4392 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4407 as_warn (_("Divide by zero."));
4409 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4412 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4417 mips_emit_delays (true);
4418 ++mips_opts.noreorder;
4419 mips_any_noreorder = 1;
4422 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4424 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4425 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4429 expr1.X_add_number = 8;
4430 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4431 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4432 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4433 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4436 expr1.X_add_number = -1;
4437 macro_build ((char *) NULL, &icnt, &expr1,
4438 dbl ? "daddiu" : "addiu",
4439 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4440 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4441 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4444 expr1.X_add_number = 1;
4445 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4446 (int) BFD_RELOC_LO16);
4447 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4448 "d,w,<", AT, AT, 31);
4452 expr1.X_add_number = 0x80000000;
4453 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4454 (int) BFD_RELOC_HI16);
4458 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4460 /* We want to close the noreorder block as soon as possible, so
4461 that later insns are available for delay slot filling. */
4462 --mips_opts.noreorder;
4466 expr1.X_add_number = 8;
4467 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4468 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4471 /* We want to close the noreorder block as soon as possible, so
4472 that later insns are available for delay slot filling. */
4473 --mips_opts.noreorder;
4475 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4478 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4517 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4519 as_warn (_("Divide by zero."));
4521 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4524 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4528 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4530 if (strcmp (s2, "mflo") == 0)
4531 move_register (&icnt, dreg, sreg);
4533 move_register (&icnt, dreg, 0);
4536 if (imm_expr.X_op == O_constant
4537 && imm_expr.X_add_number == -1
4538 && s[strlen (s) - 1] != 'u')
4540 if (strcmp (s2, "mflo") == 0)
4542 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4543 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4546 move_register (&icnt, dreg, 0);
4550 load_register (&icnt, AT, &imm_expr, dbl);
4551 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4553 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4572 mips_emit_delays (true);
4573 ++mips_opts.noreorder;
4574 mips_any_noreorder = 1;
4577 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4579 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4581 /* We want to close the noreorder block as soon as possible, so
4582 that later insns are available for delay slot filling. */
4583 --mips_opts.noreorder;
4587 expr1.X_add_number = 8;
4588 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4589 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4592 /* We want to close the noreorder block as soon as possible, so
4593 that later insns are available for delay slot filling. */
4594 --mips_opts.noreorder;
4595 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4598 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4604 /* Load the address of a symbol into a register. If breg is not
4605 zero, we then add a base register to it. */
4618 /* When generating embedded PIC code, we permit expressions of
4621 la $treg,foo-bar($breg)
4622 where bar is an address in the current section. These are used
4623 when getting the addresses of functions. We don't permit
4624 X_add_number to be non-zero, because if the symbol is
4625 external the relaxing code needs to know that any addend is
4626 purely the offset to X_op_symbol. */
4627 if (mips_pic == EMBEDDED_PIC
4628 && offset_expr.X_op == O_subtract
4629 && (symbol_constant_p (offset_expr.X_op_symbol)
4630 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4631 : (symbol_equated_p (offset_expr.X_op_symbol)
4633 (symbol_get_value_expression (offset_expr.X_op_symbol)
4636 && (offset_expr.X_add_number == 0
4637 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4643 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4644 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4648 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4649 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4650 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4651 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4652 "d,v,t", tempreg, tempreg, breg);
4654 macro_build ((char *) NULL, &icnt, &offset_expr,
4655 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4656 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4662 if (offset_expr.X_op != O_symbol
4663 && offset_expr.X_op != O_constant)
4665 as_bad (_("expression too complex"));
4666 offset_expr.X_op = O_constant;
4669 if (offset_expr.X_op == O_constant)
4670 load_register (&icnt, tempreg, &offset_expr,
4671 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4672 ? (dbl || HAVE_64BIT_ADDRESSES)
4673 : HAVE_64BIT_ADDRESSES));
4674 else if (mips_pic == NO_PIC)
4676 /* If this is a reference to a GP relative symbol, we want
4677 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4679 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4680 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4681 If we have a constant, we need two instructions anyhow,
4682 so we may as well always use the latter form.
4684 With 64bit address space and a usable $at we want
4685 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4686 lui $at,<sym> (BFD_RELOC_HI16_S)
4687 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4688 daddiu $at,<sym> (BFD_RELOC_LO16)
4690 dadd $tempreg,$tempreg,$at
4692 If $at is already in use, we use an path which is suboptimal
4693 on superscalar processors.
4694 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4695 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4697 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4699 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4702 if (HAVE_64BIT_ADDRESSES)
4704 /* We don't do GP optimization for now because RELAX_ENCODE can't
4705 hold the data for such large chunks. */
4709 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4710 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4711 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4712 AT, (int) BFD_RELOC_HI16_S);
4713 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4714 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4715 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4716 AT, AT, (int) BFD_RELOC_LO16);
4717 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4718 "d,w,<", tempreg, tempreg, 0);
4719 macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t",
4720 tempreg, tempreg, AT);
4725 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4726 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4727 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4728 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4729 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4730 tempreg, tempreg, 16);
4731 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4732 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4733 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4734 tempreg, tempreg, 16);
4735 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4736 tempreg, tempreg, (int) BFD_RELOC_LO16);
4741 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4742 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4745 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4746 "t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16);
4747 p = frag_var (rs_machine_dependent, 8, 0,
4748 RELAX_ENCODE (4, 8, 0, 4, 0,
4749 mips_opts.warn_about_macros),
4750 offset_expr.X_add_symbol, 0, NULL);
4752 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4755 macro_build (p, &icnt, &offset_expr, "addiu",
4756 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4759 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4761 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4763 /* If this is a reference to an external symbol, and there
4764 is no constant, we want
4765 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4766 or if tempreg is PIC_CALL_REG
4767 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4768 For a local symbol, we want
4769 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4771 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4773 If we have a small constant, and this is a reference to
4774 an external symbol, we want
4775 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4777 addiu $tempreg,$tempreg,<constant>
4778 For a local symbol, we want the same instruction
4779 sequence, but we output a BFD_RELOC_LO16 reloc on the
4782 If we have a large constant, and this is a reference to
4783 an external symbol, we want
4784 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4785 lui $at,<hiconstant>
4786 addiu $at,$at,<loconstant>
4787 addu $tempreg,$tempreg,$at
4788 For a local symbol, we want the same instruction
4789 sequence, but we output a BFD_RELOC_LO16 reloc on the
4790 addiu instruction. */
4791 expr1.X_add_number = offset_expr.X_add_number;
4792 offset_expr.X_add_number = 0;
4794 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4795 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4796 macro_build ((char *) NULL, &icnt, &offset_expr,
4797 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4798 "t,o(b)", tempreg, lw_reloc_type, GP);
4799 if (expr1.X_add_number == 0)
4807 /* We're going to put in an addu instruction using
4808 tempreg, so we may as well insert the nop right
4810 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4814 p = frag_var (rs_machine_dependent, 8 - off, 0,
4815 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4817 ? mips_opts.warn_about_macros
4819 offset_expr.X_add_symbol, 0, NULL);
4822 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4825 macro_build (p, &icnt, &expr1,
4826 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4827 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4828 /* FIXME: If breg == 0, and the next instruction uses
4829 $tempreg, then if this variant case is used an extra
4830 nop will be generated. */
4832 else if (expr1.X_add_number >= -0x8000
4833 && expr1.X_add_number < 0x8000)
4835 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4837 macro_build ((char *) NULL, &icnt, &expr1,
4838 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4839 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4840 frag_var (rs_machine_dependent, 0, 0,
4841 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4842 offset_expr.X_add_symbol, 0, NULL);
4848 /* If we are going to add in a base register, and the
4849 target register and the base register are the same,
4850 then we are using AT as a temporary register. Since
4851 we want to load the constant into AT, we add our
4852 current AT (from the global offset table) and the
4853 register into the register now, and pretend we were
4854 not using a base register. */
4859 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4861 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4862 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4863 "d,v,t", treg, AT, breg);
4869 /* Set mips_optimize around the lui instruction to avoid
4870 inserting an unnecessary nop after the lw. */
4871 hold_mips_optimize = mips_optimize;
4873 macro_build_lui (NULL, &icnt, &expr1, AT);
4874 mips_optimize = hold_mips_optimize;
4876 macro_build ((char *) NULL, &icnt, &expr1,
4877 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4878 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4879 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4880 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4881 "d,v,t", tempreg, tempreg, AT);
4882 frag_var (rs_machine_dependent, 0, 0,
4883 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4884 offset_expr.X_add_symbol, 0, NULL);
4888 else if (mips_pic == SVR4_PIC)
4891 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4892 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4894 /* This is the large GOT case. If this is a reference to an
4895 external symbol, and there is no constant, we want
4896 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4897 addu $tempreg,$tempreg,$gp
4898 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4899 or if tempreg is PIC_CALL_REG
4900 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4901 addu $tempreg,$tempreg,$gp
4902 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4903 For a local symbol, we want
4904 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4906 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4908 If we have a small constant, and this is a reference to
4909 an external symbol, we want
4910 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4911 addu $tempreg,$tempreg,$gp
4912 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4914 addiu $tempreg,$tempreg,<constant>
4915 For a local symbol, we want
4916 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4918 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4920 If we have a large constant, and this is a reference to
4921 an external symbol, we want
4922 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4923 addu $tempreg,$tempreg,$gp
4924 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4925 lui $at,<hiconstant>
4926 addiu $at,$at,<loconstant>
4927 addu $tempreg,$tempreg,$at
4928 For a local symbol, we want
4929 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4930 lui $at,<hiconstant>
4931 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4932 addu $tempreg,$tempreg,$at
4934 expr1.X_add_number = offset_expr.X_add_number;
4935 offset_expr.X_add_number = 0;
4937 if (reg_needs_delay (GP))
4941 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4943 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4944 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4946 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4947 tempreg, lui_reloc_type);
4948 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4949 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4950 "d,v,t", tempreg, tempreg, GP);
4951 macro_build ((char *) NULL, &icnt, &offset_expr,
4952 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4953 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4954 if (expr1.X_add_number == 0)
4962 /* We're going to put in an addu instruction using
4963 tempreg, so we may as well insert the nop right
4965 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4970 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4971 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4974 ? mips_opts.warn_about_macros
4976 offset_expr.X_add_symbol, 0, NULL);
4978 else if (expr1.X_add_number >= -0x8000
4979 && expr1.X_add_number < 0x8000)
4981 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4983 macro_build ((char *) NULL, &icnt, &expr1,
4984 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4985 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4987 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4988 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4990 ? mips_opts.warn_about_macros
4992 offset_expr.X_add_symbol, 0, NULL);
4998 /* If we are going to add in a base register, and the
4999 target register and the base register are the same,
5000 then we are using AT as a temporary register. Since
5001 we want to load the constant into AT, we add our
5002 current AT (from the global offset table) and the
5003 register into the register now, and pretend we were
5004 not using a base register. */
5012 assert (tempreg == AT);
5013 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5015 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5016 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5017 "d,v,t", treg, AT, breg);
5022 /* Set mips_optimize around the lui instruction to avoid
5023 inserting an unnecessary nop after the lw. */
5024 hold_mips_optimize = mips_optimize;
5026 macro_build_lui (NULL, &icnt, &expr1, AT);
5027 mips_optimize = hold_mips_optimize;
5029 macro_build ((char *) NULL, &icnt, &expr1,
5030 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5031 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5032 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5033 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5034 "d,v,t", dreg, dreg, AT);
5036 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
5037 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
5040 ? mips_opts.warn_about_macros
5042 offset_expr.X_add_symbol, 0, NULL);
5049 /* This is needed because this instruction uses $gp, but
5050 the first instruction on the main stream does not. */
5051 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5054 macro_build (p, &icnt, &offset_expr,
5055 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5056 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
5058 if (expr1.X_add_number >= -0x8000
5059 && expr1.X_add_number < 0x8000)
5061 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5063 macro_build (p, &icnt, &expr1,
5064 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5065 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5066 /* FIXME: If add_number is 0, and there was no base
5067 register, the external symbol case ended with a load,
5068 so if the symbol turns out to not be external, and
5069 the next instruction uses tempreg, an unnecessary nop
5070 will be inserted. */
5076 /* We must add in the base register now, as in the
5077 external symbol case. */
5078 assert (tempreg == AT);
5079 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5081 macro_build (p, &icnt, (expressionS *) NULL,
5082 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5083 "d,v,t", treg, AT, breg);
5086 /* We set breg to 0 because we have arranged to add
5087 it in in both cases. */
5091 macro_build_lui (p, &icnt, &expr1, AT);
5093 macro_build (p, &icnt, &expr1,
5094 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5095 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5097 macro_build (p, &icnt, (expressionS *) NULL,
5098 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5099 "d,v,t", tempreg, tempreg, AT);
5103 else if (mips_pic == EMBEDDED_PIC)
5106 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5108 macro_build ((char *) NULL, &icnt, &offset_expr,
5109 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5110 "t,r,j", tempreg, GP, (int) BFD_RELOC_GPREL16);
5119 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5120 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5122 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5124 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5125 "d,v,t", treg, tempreg, breg);
5134 /* The j instruction may not be used in PIC code, since it
5135 requires an absolute address. We convert it to a b
5137 if (mips_pic == NO_PIC)
5138 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5140 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5143 /* The jal instructions must be handled as macros because when
5144 generating PIC code they expand to multi-instruction
5145 sequences. Normally they are simple instructions. */
5150 if (mips_pic == NO_PIC
5151 || mips_pic == EMBEDDED_PIC)
5152 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5154 else if (mips_pic == SVR4_PIC)
5156 if (sreg != PIC_CALL_REG)
5157 as_warn (_("MIPS PIC call to register other than $25"));
5159 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5163 if (mips_cprestore_offset < 0)
5164 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5167 if (! mips_frame_reg_valid)
5169 as_warn (_("No .frame pseudo-op used in PIC code"));
5170 /* Quiet this warning. */
5171 mips_frame_reg_valid = 1;
5173 if (! mips_cprestore_valid)
5175 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5176 /* Quiet this warning. */
5177 mips_cprestore_valid = 1;
5179 expr1.X_add_number = mips_cprestore_offset;
5180 macro_build ((char *) NULL, &icnt, &expr1,
5181 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5182 GP, (int) BFD_RELOC_LO16, mips_frame_reg);
5192 if (mips_pic == NO_PIC)
5193 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5194 else if (mips_pic == SVR4_PIC)
5196 /* If this is a reference to an external symbol, and we are
5197 using a small GOT, we want
5198 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5202 lw $gp,cprestore($sp)
5203 The cprestore value is set using the .cprestore
5204 pseudo-op. If we are using a big GOT, we want
5205 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5207 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5211 lw $gp,cprestore($sp)
5212 If the symbol is not external, we want
5213 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5215 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5218 lw $gp,cprestore($sp) */
5222 macro_build ((char *) NULL, &icnt, &offset_expr,
5223 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5224 "t,o(b)", PIC_CALL_REG,
5225 (int) BFD_RELOC_MIPS_CALL16, GP);
5226 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5228 p = frag_var (rs_machine_dependent, 4, 0,
5229 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5230 offset_expr.X_add_symbol, 0, NULL);
5236 if (reg_needs_delay (GP))
5240 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5241 PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
5242 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5243 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5244 "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
5245 macro_build ((char *) NULL, &icnt, &offset_expr,
5246 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5247 "t,o(b)", PIC_CALL_REG,
5248 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5249 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5251 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5252 RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel,
5254 offset_expr.X_add_symbol, 0, NULL);
5257 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5260 macro_build (p, &icnt, &offset_expr,
5261 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5262 "t,o(b)", PIC_CALL_REG,
5263 (int) BFD_RELOC_MIPS_GOT16, GP);
5265 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5268 macro_build (p, &icnt, &offset_expr,
5269 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5270 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5271 (int) BFD_RELOC_LO16);
5272 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5273 "jalr", "s", PIC_CALL_REG);
5276 if (mips_cprestore_offset < 0)
5277 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5280 if (! mips_frame_reg_valid)
5282 as_warn (_("No .frame pseudo-op used in PIC code"));
5283 /* Quiet this warning. */
5284 mips_frame_reg_valid = 1;
5286 if (! mips_cprestore_valid)
5288 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5289 /* Quiet this warning. */
5290 mips_cprestore_valid = 1;
5292 if (mips_opts.noreorder)
5293 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5295 expr1.X_add_number = mips_cprestore_offset;
5296 macro_build ((char *) NULL, &icnt, &expr1,
5297 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5298 GP, (int) BFD_RELOC_LO16, mips_frame_reg);
5302 else if (mips_pic == EMBEDDED_PIC)
5304 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5305 /* The linker may expand the call to a longer sequence which
5306 uses $at, so we must break rather than return. */
5331 /* Itbl support may require additional care here. */
5336 /* Itbl support may require additional care here. */
5341 /* Itbl support may require additional care here. */
5346 /* Itbl support may require additional care here. */
5358 if (mips_arch == CPU_R4650)
5360 as_bad (_("opcode not supported on this processor"));
5364 /* Itbl support may require additional care here. */
5369 /* Itbl support may require additional care here. */
5374 /* Itbl support may require additional care here. */
5394 if (breg == treg || coproc || lr)
5416 /* Itbl support may require additional care here. */
5421 /* Itbl support may require additional care here. */
5426 /* Itbl support may require additional care here. */
5431 /* Itbl support may require additional care here. */
5447 if (mips_arch == CPU_R4650)
5449 as_bad (_("opcode not supported on this processor"));
5454 /* Itbl support may require additional care here. */
5458 /* Itbl support may require additional care here. */
5463 /* Itbl support may require additional care here. */
5475 /* Itbl support may require additional care here. */
5476 if (mask == M_LWC1_AB
5477 || mask == M_SWC1_AB
5478 || mask == M_LDC1_AB
5479 || mask == M_SDC1_AB
5488 /* For embedded PIC, we allow loads where the offset is calculated
5489 by subtracting a symbol in the current segment from an unknown
5490 symbol, relative to a base register, e.g.:
5491 <op> $treg, <sym>-<localsym>($breg)
5492 This is used by the compiler for switch statements. */
5493 if (mips_pic == EMBEDDED_PIC
5494 && offset_expr.X_op == O_subtract
5495 && (symbol_constant_p (offset_expr.X_op_symbol)
5496 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5497 : (symbol_equated_p (offset_expr.X_op_symbol)
5499 (symbol_get_value_expression (offset_expr.X_op_symbol)
5503 && (offset_expr.X_add_number == 0
5504 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5506 /* For this case, we output the instructions:
5507 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5508 addiu $tempreg,$tempreg,$breg
5509 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5510 If the relocation would fit entirely in 16 bits, it would be
5512 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5513 instead, but that seems quite difficult. */
5514 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5515 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5516 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5517 ((bfd_arch_bits_per_address (stdoutput) == 32
5518 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5519 ? "addu" : "daddu"),
5520 "d,v,t", tempreg, tempreg, breg);
5521 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5522 (int) BFD_RELOC_PCREL_LO16, tempreg);
5528 if (offset_expr.X_op != O_constant
5529 && offset_expr.X_op != O_symbol)
5531 as_bad (_("expression too complex"));
5532 offset_expr.X_op = O_constant;
5535 /* A constant expression in PIC code can be handled just as it
5536 is in non PIC code. */
5537 if (mips_pic == NO_PIC
5538 || offset_expr.X_op == O_constant)
5540 /* If this is a reference to a GP relative symbol, and there
5541 is no base register, we want
5542 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5543 Otherwise, if there is no base register, we want
5544 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5545 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5546 If we have a constant, we need two instructions anyhow,
5547 so we always use the latter form.
5549 If we have a base register, and this is a reference to a
5550 GP relative symbol, we want
5551 addu $tempreg,$breg,$gp
5552 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5554 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5555 addu $tempreg,$tempreg,$breg
5556 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5557 With a constant we always use the latter case.
5559 With 64bit address space and no base register and $at usable,
5561 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5562 lui $at,<sym> (BFD_RELOC_HI16_S)
5563 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5566 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5567 If we have a base register, we want
5568 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5569 lui $at,<sym> (BFD_RELOC_HI16_S)
5570 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5574 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5576 Without $at we can't generate the optimal path for superscalar
5577 processors here since this would require two temporary registers.
5578 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5579 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5581 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5583 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5584 If we have a base register, we want
5585 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5586 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5588 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5590 daddu $tempreg,$tempreg,$breg
5591 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5593 If we have 64-bit addresses, as an optimization, for
5594 addresses which are 32-bit constants (e.g. kseg0/kseg1
5595 addresses) we fall back to the 32-bit address generation
5596 mechanism since it is more efficient. This code should
5597 probably attempt to generate 64-bit constants more
5598 efficiently in general.
5600 if (HAVE_64BIT_ADDRESSES
5601 && !(offset_expr.X_op == O_constant
5602 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number)))
5606 /* We don't do GP optimization for now because RELAX_ENCODE can't
5607 hold the data for such large chunks. */
5611 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5612 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5613 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5614 AT, (int) BFD_RELOC_HI16_S);
5615 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5616 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5618 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5619 "d,v,t", AT, AT, breg);
5620 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5621 "d,w,<", tempreg, tempreg, 0);
5622 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5623 "d,v,t", tempreg, tempreg, AT);
5624 macro_build (p, &icnt, &offset_expr, s,
5625 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5630 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5631 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5632 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5633 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5634 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5635 "d,w,<", tempreg, tempreg, 16);
5636 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5637 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5638 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5639 "d,w,<", tempreg, tempreg, 16);
5641 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5642 "d,v,t", tempreg, tempreg, breg);
5643 macro_build (p, &icnt, &offset_expr, s,
5644 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5652 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5653 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5658 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5659 treg, (int) BFD_RELOC_GPREL16, GP);
5660 p = frag_var (rs_machine_dependent, 8, 0,
5661 RELAX_ENCODE (4, 8, 0, 4, 0,
5662 (mips_opts.warn_about_macros
5664 && mips_opts.noat))),
5665 offset_expr.X_add_symbol, 0, NULL);
5668 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5671 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5672 (int) BFD_RELOC_LO16, tempreg);
5676 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5677 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5682 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5683 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5684 "d,v,t", tempreg, breg, GP);
5685 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5686 treg, (int) BFD_RELOC_GPREL16, tempreg);
5687 p = frag_var (rs_machine_dependent, 12, 0,
5688 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5689 offset_expr.X_add_symbol, 0, NULL);
5691 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5694 macro_build (p, &icnt, (expressionS *) NULL,
5695 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5696 "d,v,t", tempreg, tempreg, breg);
5699 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5700 (int) BFD_RELOC_LO16, tempreg);
5703 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5705 /* If this is a reference to an external symbol, we want
5706 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5708 <op> $treg,0($tempreg)
5710 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5712 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5713 <op> $treg,0($tempreg)
5714 If there is a base register, we add it to $tempreg before
5715 the <op>. If there is a constant, we stick it in the
5716 <op> instruction. We don't handle constants larger than
5717 16 bits, because we have no way to load the upper 16 bits
5718 (actually, we could handle them for the subset of cases
5719 in which we are not using $at). */
5720 assert (offset_expr.X_op == O_symbol);
5721 expr1.X_add_number = offset_expr.X_add_number;
5722 offset_expr.X_add_number = 0;
5723 if (expr1.X_add_number < -0x8000
5724 || expr1.X_add_number >= 0x8000)
5725 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5727 macro_build ((char *) NULL, &icnt, &offset_expr,
5728 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5729 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
5730 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5731 p = frag_var (rs_machine_dependent, 4, 0,
5732 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5733 offset_expr.X_add_symbol, 0, NULL);
5734 macro_build (p, &icnt, &offset_expr,
5735 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5736 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5738 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5739 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5740 "d,v,t", tempreg, tempreg, breg);
5741 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5742 (int) BFD_RELOC_LO16, tempreg);
5744 else if (mips_pic == SVR4_PIC)
5748 /* If this is a reference to an external symbol, we want
5749 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5750 addu $tempreg,$tempreg,$gp
5751 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5752 <op> $treg,0($tempreg)
5754 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5756 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5757 <op> $treg,0($tempreg)
5758 If there is a base register, we add it to $tempreg before
5759 the <op>. If there is a constant, we stick it in the
5760 <op> instruction. We don't handle constants larger than
5761 16 bits, because we have no way to load the upper 16 bits
5762 (actually, we could handle them for the subset of cases
5763 in which we are not using $at). */
5764 assert (offset_expr.X_op == O_symbol);
5765 expr1.X_add_number = offset_expr.X_add_number;
5766 offset_expr.X_add_number = 0;
5767 if (expr1.X_add_number < -0x8000
5768 || expr1.X_add_number >= 0x8000)
5769 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5770 if (reg_needs_delay (GP))
5775 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5776 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5777 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5778 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5779 "d,v,t", tempreg, tempreg, GP);
5780 macro_build ((char *) NULL, &icnt, &offset_expr,
5781 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5782 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5784 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5785 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5786 offset_expr.X_add_symbol, 0, NULL);
5789 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5792 macro_build (p, &icnt, &offset_expr,
5793 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5794 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
5796 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5798 macro_build (p, &icnt, &offset_expr,
5799 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5800 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5802 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5803 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5804 "d,v,t", tempreg, tempreg, breg);
5805 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5806 (int) BFD_RELOC_LO16, tempreg);
5808 else if (mips_pic == EMBEDDED_PIC)
5810 /* If there is no base register, we want
5811 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5812 If there is a base register, we want
5813 addu $tempreg,$breg,$gp
5814 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5816 assert (offset_expr.X_op == O_symbol);
5819 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5820 treg, (int) BFD_RELOC_GPREL16, GP);
5825 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5826 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5827 "d,v,t", tempreg, breg, GP);
5828 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5829 treg, (int) BFD_RELOC_GPREL16, tempreg);
5842 load_register (&icnt, treg, &imm_expr, 0);
5846 load_register (&icnt, treg, &imm_expr, 1);
5850 if (imm_expr.X_op == O_constant)
5852 load_register (&icnt, AT, &imm_expr, 0);
5853 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5854 "mtc1", "t,G", AT, treg);
5859 assert (offset_expr.X_op == O_symbol
5860 && strcmp (segment_name (S_GET_SEGMENT
5861 (offset_expr.X_add_symbol)),
5863 && offset_expr.X_add_number == 0);
5864 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5865 treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
5870 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5871 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5872 order 32 bits of the value and the low order 32 bits are either
5873 zero or in OFFSET_EXPR. */
5874 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5876 if (HAVE_64BIT_GPRS)
5877 load_register (&icnt, treg, &imm_expr, 1);
5882 if (target_big_endian)
5894 load_register (&icnt, hreg, &imm_expr, 0);
5897 if (offset_expr.X_op == O_absent)
5898 move_register (&icnt, lreg, 0);
5901 assert (offset_expr.X_op == O_constant);
5902 load_register (&icnt, lreg, &offset_expr, 0);
5909 /* We know that sym is in the .rdata section. First we get the
5910 upper 16 bits of the address. */
5911 if (mips_pic == NO_PIC)
5913 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5915 else if (mips_pic == SVR4_PIC)
5917 macro_build ((char *) NULL, &icnt, &offset_expr,
5918 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5919 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
5921 else if (mips_pic == EMBEDDED_PIC)
5923 /* For embedded PIC we pick up the entire address off $gp in
5924 a single instruction. */
5925 macro_build ((char *) NULL, &icnt, &offset_expr,
5926 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5927 "t,r,j", AT, GP, (int) BFD_RELOC_GPREL16);
5928 offset_expr.X_op = O_constant;
5929 offset_expr.X_add_number = 0;
5934 /* Now we load the register(s). */
5935 if (HAVE_64BIT_GPRS)
5936 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5937 treg, (int) BFD_RELOC_LO16, AT);
5940 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5941 treg, (int) BFD_RELOC_LO16, AT);
5944 /* FIXME: How in the world do we deal with the possible
5946 offset_expr.X_add_number += 4;
5947 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5948 treg + 1, (int) BFD_RELOC_LO16, AT);
5952 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5953 does not become a variant frag. */
5954 frag_wane (frag_now);
5960 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5961 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5962 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5963 the value and the low order 32 bits are either zero or in
5965 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5967 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5968 if (HAVE_64BIT_FPRS)
5970 assert (HAVE_64BIT_GPRS);
5971 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5972 "dmtc1", "t,S", AT, treg);
5976 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5977 "mtc1", "t,G", AT, treg + 1);
5978 if (offset_expr.X_op == O_absent)
5979 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5980 "mtc1", "t,G", 0, treg);
5983 assert (offset_expr.X_op == O_constant);
5984 load_register (&icnt, AT, &offset_expr, 0);
5985 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5986 "mtc1", "t,G", AT, treg);
5992 assert (offset_expr.X_op == O_symbol
5993 && offset_expr.X_add_number == 0);
5994 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5995 if (strcmp (s, ".lit8") == 0)
5997 if (mips_opts.isa != ISA_MIPS1)
5999 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6000 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
6004 r = BFD_RELOC_MIPS_LITERAL;
6009 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6010 if (mips_pic == SVR4_PIC)
6011 macro_build ((char *) NULL, &icnt, &offset_expr,
6012 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6013 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
6016 /* FIXME: This won't work for a 64 bit address. */
6017 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6020 if (mips_opts.isa != ISA_MIPS1)
6022 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6023 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
6025 /* To avoid confusion in tc_gen_reloc, we must ensure
6026 that this does not become a variant frag. */
6027 frag_wane (frag_now);
6038 if (mips_arch == CPU_R4650)
6040 as_bad (_("opcode not supported on this processor"));
6043 /* Even on a big endian machine $fn comes before $fn+1. We have
6044 to adjust when loading from memory. */
6047 assert (mips_opts.isa == ISA_MIPS1);
6048 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6049 target_big_endian ? treg + 1 : treg,
6051 /* FIXME: A possible overflow which I don't know how to deal
6053 offset_expr.X_add_number += 4;
6054 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6055 target_big_endian ? treg : treg + 1,
6058 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6059 does not become a variant frag. */
6060 frag_wane (frag_now);
6069 * The MIPS assembler seems to check for X_add_number not
6070 * being double aligned and generating:
6073 * addiu at,at,%lo(foo+1)
6076 * But, the resulting address is the same after relocation so why
6077 * generate the extra instruction?
6079 if (mips_arch == CPU_R4650)
6081 as_bad (_("opcode not supported on this processor"));
6084 /* Itbl support may require additional care here. */
6086 if (mips_opts.isa != ISA_MIPS1)
6097 if (mips_arch == CPU_R4650)
6099 as_bad (_("opcode not supported on this processor"));
6103 if (mips_opts.isa != ISA_MIPS1)
6111 /* Itbl support may require additional care here. */
6116 if (HAVE_64BIT_GPRS)
6127 if (HAVE_64BIT_GPRS)
6137 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6138 loads for the case of doing a pair of loads to simulate an 'ld'.
6139 This is not currently done by the compiler, and assembly coders
6140 writing embedded-pic code can cope. */
6142 if (offset_expr.X_op != O_symbol
6143 && offset_expr.X_op != O_constant)
6145 as_bad (_("expression too complex"));
6146 offset_expr.X_op = O_constant;
6149 /* Even on a big endian machine $fn comes before $fn+1. We have
6150 to adjust when loading from memory. We set coproc if we must
6151 load $fn+1 first. */
6152 /* Itbl support may require additional care here. */
6153 if (! target_big_endian)
6156 if (mips_pic == NO_PIC
6157 || offset_expr.X_op == O_constant)
6159 /* If this is a reference to a GP relative symbol, we want
6160 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6161 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6162 If we have a base register, we use this
6164 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6165 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6166 If this is not a GP relative symbol, we want
6167 lui $at,<sym> (BFD_RELOC_HI16_S)
6168 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6169 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6170 If there is a base register, we add it to $at after the
6171 lui instruction. If there is a constant, we always use
6173 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6174 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6193 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6194 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6195 "d,v,t", AT, breg, GP);
6201 /* Itbl support may require additional care here. */
6202 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6203 coproc ? treg + 1 : treg,
6204 (int) BFD_RELOC_GPREL16, tempreg);
6205 offset_expr.X_add_number += 4;
6207 /* Set mips_optimize to 2 to avoid inserting an
6209 hold_mips_optimize = mips_optimize;
6211 /* Itbl support may require additional care here. */
6212 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6213 coproc ? treg : treg + 1,
6214 (int) BFD_RELOC_GPREL16, tempreg);
6215 mips_optimize = hold_mips_optimize;
6217 p = frag_var (rs_machine_dependent, 12 + off, 0,
6218 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6219 used_at && mips_opts.noat),
6220 offset_expr.X_add_symbol, 0, NULL);
6222 /* We just generated two relocs. When tc_gen_reloc
6223 handles this case, it will skip the first reloc and
6224 handle the second. The second reloc already has an
6225 extra addend of 4, which we added above. We must
6226 subtract it out, and then subtract another 4 to make
6227 the first reloc come out right. The second reloc
6228 will come out right because we are going to add 4 to
6229 offset_expr when we build its instruction below.
6231 If we have a symbol, then we don't want to include
6232 the offset, because it will wind up being included
6233 when we generate the reloc. */
6235 if (offset_expr.X_op == O_constant)
6236 offset_expr.X_add_number -= 8;
6239 offset_expr.X_add_number = -4;
6240 offset_expr.X_op = O_constant;
6243 macro_build_lui (p, &icnt, &offset_expr, AT);
6248 macro_build (p, &icnt, (expressionS *) NULL,
6249 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6250 "d,v,t", AT, breg, AT);
6254 /* Itbl support may require additional care here. */
6255 macro_build (p, &icnt, &offset_expr, s, fmt,
6256 coproc ? treg + 1 : treg,
6257 (int) BFD_RELOC_LO16, AT);
6260 /* FIXME: How do we handle overflow here? */
6261 offset_expr.X_add_number += 4;
6262 /* Itbl support may require additional care here. */
6263 macro_build (p, &icnt, &offset_expr, s, fmt,
6264 coproc ? treg : treg + 1,
6265 (int) BFD_RELOC_LO16, AT);
6267 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6271 /* If this is a reference to an external symbol, we want
6272 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6277 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6279 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6280 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6281 If there is a base register we add it to $at before the
6282 lwc1 instructions. If there is a constant we include it
6283 in the lwc1 instructions. */
6285 expr1.X_add_number = offset_expr.X_add_number;
6286 offset_expr.X_add_number = 0;
6287 if (expr1.X_add_number < -0x8000
6288 || expr1.X_add_number >= 0x8000 - 4)
6289 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6294 frag_grow (24 + off);
6295 macro_build ((char *) NULL, &icnt, &offset_expr,
6296 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6297 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
6298 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6300 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6301 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6302 "d,v,t", AT, breg, AT);
6303 /* Itbl support may require additional care here. */
6304 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6305 coproc ? treg + 1 : treg,
6306 (int) BFD_RELOC_LO16, AT);
6307 expr1.X_add_number += 4;
6309 /* Set mips_optimize to 2 to avoid inserting an undesired
6311 hold_mips_optimize = mips_optimize;
6313 /* Itbl support may require additional care here. */
6314 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6315 coproc ? treg : treg + 1,
6316 (int) BFD_RELOC_LO16, AT);
6317 mips_optimize = hold_mips_optimize;
6319 (void) frag_var (rs_machine_dependent, 0, 0,
6320 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6321 offset_expr.X_add_symbol, 0, NULL);
6323 else if (mips_pic == SVR4_PIC)
6327 /* If this is a reference to an external symbol, we want
6328 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6330 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6335 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6337 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6338 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6339 If there is a base register we add it to $at before the
6340 lwc1 instructions. If there is a constant we include it
6341 in the lwc1 instructions. */
6343 expr1.X_add_number = offset_expr.X_add_number;
6344 offset_expr.X_add_number = 0;
6345 if (expr1.X_add_number < -0x8000
6346 || expr1.X_add_number >= 0x8000 - 4)
6347 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6348 if (reg_needs_delay (GP))
6357 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6358 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6359 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6360 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6361 "d,v,t", AT, AT, GP);
6362 macro_build ((char *) NULL, &icnt, &offset_expr,
6363 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6364 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6365 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6367 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6368 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6369 "d,v,t", AT, breg, AT);
6370 /* Itbl support may require additional care here. */
6371 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6372 coproc ? treg + 1 : treg,
6373 (int) BFD_RELOC_LO16, AT);
6374 expr1.X_add_number += 4;
6376 /* Set mips_optimize to 2 to avoid inserting an undesired
6378 hold_mips_optimize = mips_optimize;
6380 /* Itbl support may require additional care here. */
6381 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6382 coproc ? treg : treg + 1,
6383 (int) BFD_RELOC_LO16, AT);
6384 mips_optimize = hold_mips_optimize;
6385 expr1.X_add_number -= 4;
6387 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6388 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6389 8 + gpdel + off, 1, 0),
6390 offset_expr.X_add_symbol, 0, NULL);
6393 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6396 macro_build (p, &icnt, &offset_expr,
6397 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6398 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
6400 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6404 macro_build (p, &icnt, (expressionS *) NULL,
6405 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6406 "d,v,t", AT, breg, AT);
6409 /* Itbl support may require additional care here. */
6410 macro_build (p, &icnt, &expr1, s, fmt,
6411 coproc ? treg + 1 : treg,
6412 (int) BFD_RELOC_LO16, AT);
6414 expr1.X_add_number += 4;
6416 /* Set mips_optimize to 2 to avoid inserting an undesired
6418 hold_mips_optimize = mips_optimize;
6420 /* Itbl support may require additional care here. */
6421 macro_build (p, &icnt, &expr1, s, fmt,
6422 coproc ? treg : treg + 1,
6423 (int) BFD_RELOC_LO16, AT);
6424 mips_optimize = hold_mips_optimize;
6426 else if (mips_pic == EMBEDDED_PIC)
6428 /* If there is no base register, we use
6429 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6430 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6431 If we have a base register, we use
6433 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6434 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6443 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6444 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6445 "d,v,t", AT, breg, GP);
6450 /* Itbl support may require additional care here. */
6451 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6452 coproc ? treg + 1 : treg,
6453 (int) BFD_RELOC_GPREL16, tempreg);
6454 offset_expr.X_add_number += 4;
6455 /* Itbl support may require additional care here. */
6456 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6457 coproc ? treg : treg + 1,
6458 (int) BFD_RELOC_GPREL16, tempreg);
6474 assert (HAVE_32BIT_ADDRESSES);
6475 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6476 (int) BFD_RELOC_LO16, breg);
6477 offset_expr.X_add_number += 4;
6478 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6479 (int) BFD_RELOC_LO16, breg);
6482 /* New code added to support COPZ instructions.
6483 This code builds table entries out of the macros in mip_opcodes.
6484 R4000 uses interlocks to handle coproc delays.
6485 Other chips (like the R3000) require nops to be inserted for delays.
6487 FIXME: Currently, we require that the user handle delays.
6488 In order to fill delay slots for non-interlocked chips,
6489 we must have a way to specify delays based on the coprocessor.
6490 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6491 What are the side-effects of the cop instruction?
6492 What cache support might we have and what are its effects?
6493 Both coprocessor & memory require delays. how long???
6494 What registers are read/set/modified?
6496 If an itbl is provided to interpret cop instructions,
6497 this knowledge can be encoded in the itbl spec. */
6511 /* For now we just do C (same as Cz). The parameter will be
6512 stored in insn_opcode by mips_ip. */
6513 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6518 move_register (&icnt, dreg, sreg);
6521 #ifdef LOSING_COMPILER
6523 /* Try and see if this is a new itbl instruction.
6524 This code builds table entries out of the macros in mip_opcodes.
6525 FIXME: For now we just assemble the expression and pass it's
6526 value along as a 32-bit immediate.
6527 We may want to have the assembler assemble this value,
6528 so that we gain the assembler's knowledge of delay slots,
6530 Would it be more efficient to use mask (id) here? */
6531 if (itbl_have_entries
6532 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6534 s = ip->insn_mo->name;
6536 coproc = ITBL_DECODE_PNUM (immed_expr);;
6537 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6544 as_warn (_("Macro used $at after \".set noat\""));
6549 struct mips_cl_insn *ip;
6551 register int treg, sreg, dreg, breg;
6567 bfd_reloc_code_real_type r;
6570 treg = (ip->insn_opcode >> 16) & 0x1f;
6571 dreg = (ip->insn_opcode >> 11) & 0x1f;
6572 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6573 mask = ip->insn_mo->mask;
6575 expr1.X_op = O_constant;
6576 expr1.X_op_symbol = NULL;
6577 expr1.X_add_symbol = NULL;
6578 expr1.X_add_number = 1;
6582 #endif /* LOSING_COMPILER */
6587 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6588 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6589 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6596 /* The MIPS assembler some times generates shifts and adds. I'm
6597 not trying to be that fancy. GCC should do this for us
6599 load_register (&icnt, AT, &imm_expr, dbl);
6600 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6601 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6602 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6616 mips_emit_delays (true);
6617 ++mips_opts.noreorder;
6618 mips_any_noreorder = 1;
6620 load_register (&icnt, AT, &imm_expr, dbl);
6621 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6622 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6623 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6625 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6626 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, 31);
6627 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6630 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6634 expr1.X_add_number = 8;
6635 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6637 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6639 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6642 --mips_opts.noreorder;
6643 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6656 mips_emit_delays (true);
6657 ++mips_opts.noreorder;
6658 mips_any_noreorder = 1;
6660 load_register (&icnt, AT, &imm_expr, dbl);
6661 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6662 dbl ? "dmultu" : "multu",
6663 "s,t", sreg, imm ? AT : treg);
6664 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6666 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6669 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6673 expr1.X_add_number = 8;
6674 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6675 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6677 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6680 --mips_opts.noreorder;
6684 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6685 "d,v,t", AT, 0, treg);
6686 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6687 "d,t,s", AT, sreg, AT);
6688 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6689 "d,t,s", dreg, sreg, treg);
6690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6691 "d,v,t", dreg, dreg, AT);
6695 if (imm_expr.X_op != O_constant)
6696 as_bad (_("rotate count too large"));
6697 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
6698 AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
6699 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
6700 dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
6701 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
6706 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6707 "d,v,t", AT, 0, treg);
6708 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6709 "d,t,s", AT, sreg, AT);
6710 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6711 "d,t,s", dreg, sreg, treg);
6712 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6713 "d,v,t", dreg, dreg, AT);
6717 if (imm_expr.X_op != O_constant)
6718 as_bad (_("rotate count too large"));
6719 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
6720 AT, sreg, (int) (imm_expr.X_add_number & 0x1f));
6721 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
6722 dreg, sreg, (int) ((0 - imm_expr.X_add_number) & 0x1f));
6723 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
6728 if (mips_arch == CPU_R4650)
6730 as_bad (_("opcode not supported on this processor"));
6733 assert (mips_opts.isa == ISA_MIPS1);
6734 /* Even on a big endian machine $fn comes before $fn+1. We have
6735 to adjust when storing to memory. */
6736 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6737 target_big_endian ? treg + 1 : treg,
6738 (int) BFD_RELOC_LO16, breg);
6739 offset_expr.X_add_number += 4;
6740 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6741 target_big_endian ? treg : treg + 1,
6742 (int) BFD_RELOC_LO16, breg);
6747 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6748 treg, (int) BFD_RELOC_LO16);
6750 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6751 sreg, (int) BFD_RELOC_LO16);
6754 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6755 "d,v,t", dreg, sreg, treg);
6756 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6757 dreg, (int) BFD_RELOC_LO16);
6762 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6764 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6765 sreg, (int) BFD_RELOC_LO16);
6770 as_warn (_("Instruction %s: result is always false"),
6772 move_register (&icnt, dreg, 0);
6775 if (imm_expr.X_op == O_constant
6776 && imm_expr.X_add_number >= 0
6777 && imm_expr.X_add_number < 0x10000)
6779 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6780 sreg, (int) BFD_RELOC_LO16);
6783 else if (imm_expr.X_op == O_constant
6784 && imm_expr.X_add_number > -0x8000
6785 && imm_expr.X_add_number < 0)
6787 imm_expr.X_add_number = -imm_expr.X_add_number;
6788 macro_build ((char *) NULL, &icnt, &imm_expr,
6789 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6790 "t,r,j", dreg, sreg,
6791 (int) BFD_RELOC_LO16);
6796 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6797 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6798 "d,v,t", dreg, sreg, AT);
6801 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6802 (int) BFD_RELOC_LO16);
6807 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6813 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6815 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6816 (int) BFD_RELOC_LO16);
6819 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6821 if (imm_expr.X_op == O_constant
6822 && imm_expr.X_add_number >= -0x8000
6823 && imm_expr.X_add_number < 0x8000)
6825 macro_build ((char *) NULL, &icnt, &imm_expr,
6826 mask == M_SGE_I ? "slti" : "sltiu",
6827 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6832 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6833 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6834 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6838 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6839 (int) BFD_RELOC_LO16);
6844 case M_SGT: /* sreg > treg <==> treg < sreg */
6850 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6854 case M_SGT_I: /* sreg > I <==> I < sreg */
6860 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6861 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6865 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6871 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6873 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6874 (int) BFD_RELOC_LO16);
6877 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6883 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6884 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6886 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6887 (int) BFD_RELOC_LO16);
6891 if (imm_expr.X_op == O_constant
6892 && imm_expr.X_add_number >= -0x8000
6893 && imm_expr.X_add_number < 0x8000)
6895 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6896 dreg, sreg, (int) BFD_RELOC_LO16);
6899 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6900 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
6905 if (imm_expr.X_op == O_constant
6906 && imm_expr.X_add_number >= -0x8000
6907 && imm_expr.X_add_number < 0x8000)
6909 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6910 dreg, sreg, (int) BFD_RELOC_LO16);
6913 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6914 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6915 "d,v,t", dreg, sreg, AT);
6920 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6921 "d,v,t", dreg, 0, treg);
6923 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6924 "d,v,t", dreg, 0, sreg);
6927 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6928 "d,v,t", dreg, sreg, treg);
6929 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6930 "d,v,t", dreg, 0, dreg);
6935 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6937 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6938 "d,v,t", dreg, 0, sreg);
6943 as_warn (_("Instruction %s: result is always true"),
6945 macro_build ((char *) NULL, &icnt, &expr1,
6946 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6947 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
6950 if (imm_expr.X_op == O_constant
6951 && imm_expr.X_add_number >= 0
6952 && imm_expr.X_add_number < 0x10000)
6954 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
6955 dreg, sreg, (int) BFD_RELOC_LO16);
6958 else if (imm_expr.X_op == O_constant
6959 && imm_expr.X_add_number > -0x8000
6960 && imm_expr.X_add_number < 0)
6962 imm_expr.X_add_number = -imm_expr.X_add_number;
6963 macro_build ((char *) NULL, &icnt, &imm_expr,
6964 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6965 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6970 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6971 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6972 "d,v,t", dreg, sreg, AT);
6975 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6976 "d,v,t", dreg, 0, dreg);
6984 if (imm_expr.X_op == O_constant
6985 && imm_expr.X_add_number > -0x8000
6986 && imm_expr.X_add_number <= 0x8000)
6988 imm_expr.X_add_number = -imm_expr.X_add_number;
6989 macro_build ((char *) NULL, &icnt, &imm_expr,
6990 dbl ? "daddi" : "addi",
6991 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6994 load_register (&icnt, AT, &imm_expr, dbl);
6995 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6996 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7002 if (imm_expr.X_op == O_constant
7003 && imm_expr.X_add_number > -0x8000
7004 && imm_expr.X_add_number <= 0x8000)
7006 imm_expr.X_add_number = -imm_expr.X_add_number;
7007 macro_build ((char *) NULL, &icnt, &imm_expr,
7008 dbl ? "daddiu" : "addiu",
7009 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7012 load_register (&icnt, AT, &imm_expr, dbl);
7013 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7014 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7035 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7036 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7042 assert (mips_opts.isa == ISA_MIPS1);
7043 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7044 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7047 * Is the double cfc1 instruction a bug in the mips assembler;
7048 * or is there a reason for it?
7050 mips_emit_delays (true);
7051 ++mips_opts.noreorder;
7052 mips_any_noreorder = 1;
7053 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7055 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7057 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7058 expr1.X_add_number = 3;
7059 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7060 (int) BFD_RELOC_LO16);
7061 expr1.X_add_number = 2;
7062 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7063 (int) BFD_RELOC_LO16);
7064 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7066 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7067 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7068 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7069 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7071 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7072 --mips_opts.noreorder;
7081 if (offset_expr.X_add_number >= 0x7fff)
7082 as_bad (_("operand overflow"));
7083 /* avoid load delay */
7084 if (! target_big_endian)
7085 offset_expr.X_add_number += 1;
7086 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7087 (int) BFD_RELOC_LO16, breg);
7088 if (! target_big_endian)
7089 offset_expr.X_add_number -= 1;
7091 offset_expr.X_add_number += 1;
7092 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7093 (int) BFD_RELOC_LO16, breg);
7094 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7096 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7110 if (offset_expr.X_add_number >= 0x8000 - off)
7111 as_bad (_("operand overflow"));
7112 if (! target_big_endian)
7113 offset_expr.X_add_number += off;
7114 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7115 (int) BFD_RELOC_LO16, breg);
7116 if (! target_big_endian)
7117 offset_expr.X_add_number -= off;
7119 offset_expr.X_add_number += off;
7120 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7121 (int) BFD_RELOC_LO16, breg);
7135 load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at);
7137 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7138 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7139 "d,v,t", AT, AT, breg);
7140 if (! target_big_endian)
7141 expr1.X_add_number = off;
7143 expr1.X_add_number = 0;
7144 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7145 (int) BFD_RELOC_LO16, AT);
7146 if (! target_big_endian)
7147 expr1.X_add_number = 0;
7149 expr1.X_add_number = off;
7150 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7151 (int) BFD_RELOC_LO16, AT);
7157 load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at);
7159 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7160 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7161 "d,v,t", AT, AT, breg);
7162 if (target_big_endian)
7163 expr1.X_add_number = 0;
7164 macro_build ((char *) NULL, &icnt, &expr1,
7165 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7166 (int) BFD_RELOC_LO16, AT);
7167 if (target_big_endian)
7168 expr1.X_add_number = 1;
7170 expr1.X_add_number = 0;
7171 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7172 (int) BFD_RELOC_LO16, AT);
7173 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7175 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7180 if (offset_expr.X_add_number >= 0x7fff)
7181 as_bad (_("operand overflow"));
7182 if (target_big_endian)
7183 offset_expr.X_add_number += 1;
7184 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7185 (int) BFD_RELOC_LO16, breg);
7186 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7188 if (target_big_endian)
7189 offset_expr.X_add_number -= 1;
7191 offset_expr.X_add_number += 1;
7192 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7193 (int) BFD_RELOC_LO16, breg);
7206 if (offset_expr.X_add_number >= 0x8000 - off)
7207 as_bad (_("operand overflow"));
7208 if (! target_big_endian)
7209 offset_expr.X_add_number += off;
7210 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7211 (int) BFD_RELOC_LO16, breg);
7212 if (! target_big_endian)
7213 offset_expr.X_add_number -= off;
7215 offset_expr.X_add_number += off;
7216 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7217 (int) BFD_RELOC_LO16, breg);
7231 load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at);
7233 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7234 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7235 "d,v,t", AT, AT, breg);
7236 if (! target_big_endian)
7237 expr1.X_add_number = off;
7239 expr1.X_add_number = 0;
7240 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7241 (int) BFD_RELOC_LO16, AT);
7242 if (! target_big_endian)
7243 expr1.X_add_number = 0;
7245 expr1.X_add_number = off;
7246 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7247 (int) BFD_RELOC_LO16, AT);
7252 load_address (&icnt, AT, &offset_expr, HAVE_64BIT_ADDRESSES, &used_at);
7254 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7255 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7256 "d,v,t", AT, AT, breg);
7257 if (! target_big_endian)
7258 expr1.X_add_number = 0;
7259 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7260 (int) BFD_RELOC_LO16, AT);
7261 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7263 if (! target_big_endian)
7264 expr1.X_add_number = 1;
7266 expr1.X_add_number = 0;
7267 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7268 (int) BFD_RELOC_LO16, AT);
7269 if (! target_big_endian)
7270 expr1.X_add_number = 0;
7272 expr1.X_add_number = 1;
7273 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7274 (int) BFD_RELOC_LO16, AT);
7275 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7277 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7282 /* FIXME: Check if this is one of the itbl macros, since they
7283 are added dynamically. */
7284 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7288 as_warn (_("Macro used $at after \".set noat\""));
7291 /* Implement macros in mips16 mode. */
7295 struct mips_cl_insn *ip;
7298 int xreg, yreg, zreg, tmp;
7302 const char *s, *s2, *s3;
7304 mask = ip->insn_mo->mask;
7306 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7307 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7308 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7312 expr1.X_op = O_constant;
7313 expr1.X_op_symbol = NULL;
7314 expr1.X_add_symbol = NULL;
7315 expr1.X_add_number = 1;
7334 mips_emit_delays (true);
7335 ++mips_opts.noreorder;
7336 mips_any_noreorder = 1;
7337 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7338 dbl ? "ddiv" : "div",
7339 "0,x,y", xreg, yreg);
7340 expr1.X_add_number = 2;
7341 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7342 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7345 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7346 since that causes an overflow. We should do that as well,
7347 but I don't see how to do the comparisons without a temporary
7349 --mips_opts.noreorder;
7350 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7369 mips_emit_delays (true);
7370 ++mips_opts.noreorder;
7371 mips_any_noreorder = 1;
7372 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7374 expr1.X_add_number = 2;
7375 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7376 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7378 --mips_opts.noreorder;
7379 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7385 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7386 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7387 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7396 if (imm_expr.X_op != O_constant)
7397 as_bad (_("Unsupported large constant"));
7398 imm_expr.X_add_number = -imm_expr.X_add_number;
7399 macro_build ((char *) NULL, &icnt, &imm_expr,
7400 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7404 if (imm_expr.X_op != O_constant)
7405 as_bad (_("Unsupported large constant"));
7406 imm_expr.X_add_number = -imm_expr.X_add_number;
7407 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7412 if (imm_expr.X_op != O_constant)
7413 as_bad (_("Unsupported large constant"));
7414 imm_expr.X_add_number = -imm_expr.X_add_number;
7415 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7438 goto do_reverse_branch;
7442 goto do_reverse_branch;
7454 goto do_reverse_branch;
7465 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7467 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7494 goto do_addone_branch_i;
7499 goto do_addone_branch_i;
7514 goto do_addone_branch_i;
7521 if (imm_expr.X_op != O_constant)
7522 as_bad (_("Unsupported large constant"));
7523 ++imm_expr.X_add_number;
7526 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7527 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7531 expr1.X_add_number = 0;
7532 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7534 move_register (&icnt, xreg, yreg);
7535 expr1.X_add_number = 2;
7536 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7537 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7538 "neg", "x,w", xreg, xreg);
7542 /* For consistency checking, verify that all bits are specified either
7543 by the match/mask part of the instruction definition, or by the
7546 validate_mips_insn (opc)
7547 const struct mips_opcode *opc;
7549 const char *p = opc->args;
7551 unsigned long used_bits = opc->mask;
7553 if ((used_bits & opc->match) != opc->match)
7555 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7556 opc->name, opc->args);
7559 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7566 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7567 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7569 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7570 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7571 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7572 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7574 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7575 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7577 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7579 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7580 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7581 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7582 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7583 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7584 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7585 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7586 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7587 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7588 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7589 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7591 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7592 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7593 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7594 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7596 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7597 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7598 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7599 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7600 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7601 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7602 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7603 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7604 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7607 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7608 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7609 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7611 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7612 c, opc->name, opc->args);
7616 if (used_bits != 0xffffffff)
7618 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7619 ~used_bits & 0xffffffff, opc->name, opc->args);
7625 /* This routine assembles an instruction into its binary format. As a
7626 side effect, it sets one of the global variables imm_reloc or
7627 offset_reloc to the type of relocation to do if one of the operands
7628 is an address expression. */
7633 struct mips_cl_insn *ip;
7638 struct mips_opcode *insn;
7641 unsigned int lastregno = 0;
7647 /* If the instruction contains a '.', we first try to match an instruction
7648 including the '.'. Then we try again without the '.'. */
7650 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7653 /* If we stopped on whitespace, then replace the whitespace with null for
7654 the call to hash_find. Save the character we replaced just in case we
7655 have to re-parse the instruction. */
7662 insn = (struct mips_opcode *) hash_find (op_hash, str);
7664 /* If we didn't find the instruction in the opcode table, try again, but
7665 this time with just the instruction up to, but not including the
7669 /* Restore the character we overwrite above (if any). */
7673 /* Scan up to the first '.' or whitespace. */
7675 *s != '\0' && *s != '.' && !ISSPACE (*s);
7679 /* If we did not find a '.', then we can quit now. */
7682 insn_error = "unrecognized opcode";
7686 /* Lookup the instruction in the hash table. */
7688 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7690 insn_error = "unrecognized opcode";
7700 assert (strcmp (insn->name, str) == 0);
7702 if (OPCODE_IS_MEMBER (insn,
7704 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7710 if (insn->pinfo != INSN_MACRO)
7712 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7718 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7719 && strcmp (insn->name, insn[1].name) == 0)
7728 static char buf[100];
7730 _("opcode not supported on this processor: %s (%s)"),
7731 mips_cpu_to_str (mips_arch),
7732 mips_isa_to_str (mips_opts.isa));
7743 ip->insn_opcode = insn->match;
7745 for (args = insn->args;; ++args)
7747 s += strspn (s, " \t");
7750 case '\0': /* end of args */
7763 ip->insn_opcode |= lastregno << OP_SH_RS;
7767 ip->insn_opcode |= lastregno << OP_SH_RT;
7771 ip->insn_opcode |= lastregno << OP_SH_FT;
7775 ip->insn_opcode |= lastregno << OP_SH_FS;
7781 /* Handle optional base register.
7782 Either the base register is omitted or
7783 we must have a left paren. */
7784 /* This is dependent on the next operand specifier
7785 is a base register specification. */
7786 assert (args[1] == 'b' || args[1] == '5'
7787 || args[1] == '-' || args[1] == '4');
7791 case ')': /* these must match exactly */
7796 case '<': /* must be at least one digit */
7798 * According to the manual, if the shift amount is greater
7799 * than 31 or less than 0, then the shift amount should be
7800 * mod 32. In reality the mips assembler issues an error.
7801 * We issue a warning and mask out all but the low 5 bits.
7803 my_getExpression (&imm_expr, s);
7804 check_absolute_expr (ip, &imm_expr);
7805 if ((unsigned long) imm_expr.X_add_number > 31)
7807 as_warn (_("Improper shift amount (%ld)"),
7808 (long) imm_expr.X_add_number);
7809 imm_expr.X_add_number &= OP_MASK_SHAMT;
7811 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7812 imm_expr.X_op = O_absent;
7816 case '>': /* shift amount minus 32 */
7817 my_getExpression (&imm_expr, s);
7818 check_absolute_expr (ip, &imm_expr);
7819 if ((unsigned long) imm_expr.X_add_number < 32
7820 || (unsigned long) imm_expr.X_add_number > 63)
7822 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7823 imm_expr.X_op = O_absent;
7827 case 'k': /* cache code */
7828 case 'h': /* prefx code */
7829 my_getExpression (&imm_expr, s);
7830 check_absolute_expr (ip, &imm_expr);
7831 if ((unsigned long) imm_expr.X_add_number > 31)
7833 as_warn (_("Invalid value for `%s' (%lu)"),
7835 (unsigned long) imm_expr.X_add_number);
7836 imm_expr.X_add_number &= 0x1f;
7839 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7841 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7842 imm_expr.X_op = O_absent;
7846 case 'c': /* break code */
7847 my_getExpression (&imm_expr, s);
7848 check_absolute_expr (ip, &imm_expr);
7849 if ((unsigned) imm_expr.X_add_number > 1023)
7851 as_warn (_("Illegal break code (%ld)"),
7852 (long) imm_expr.X_add_number);
7853 imm_expr.X_add_number &= OP_MASK_CODE;
7855 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7856 imm_expr.X_op = O_absent;
7860 case 'q': /* lower break code */
7861 my_getExpression (&imm_expr, s);
7862 check_absolute_expr (ip, &imm_expr);
7863 if ((unsigned) imm_expr.X_add_number > 1023)
7865 as_warn (_("Illegal lower break code (%ld)"),
7866 (long) imm_expr.X_add_number);
7867 imm_expr.X_add_number &= OP_MASK_CODE2;
7869 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7870 imm_expr.X_op = O_absent;
7874 case 'B': /* 20-bit syscall/break code. */
7875 my_getExpression (&imm_expr, s);
7876 check_absolute_expr (ip, &imm_expr);
7877 if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20)
7878 as_warn (_("Illegal 20-bit code (%ld)"),
7879 (long) imm_expr.X_add_number);
7880 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7881 imm_expr.X_op = O_absent;
7885 case 'C': /* Coprocessor code */
7886 my_getExpression (&imm_expr, s);
7887 check_absolute_expr (ip, &imm_expr);
7888 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
7890 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7891 (long) imm_expr.X_add_number);
7892 imm_expr.X_add_number &= ((1 << 25) - 1);
7894 ip->insn_opcode |= imm_expr.X_add_number;
7895 imm_expr.X_op = O_absent;
7899 case 'J': /* 19-bit wait code. */
7900 my_getExpression (&imm_expr, s);
7901 check_absolute_expr (ip, &imm_expr);
7902 if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19)
7903 as_warn (_("Illegal 19-bit code (%ld)"),
7904 (long) imm_expr.X_add_number);
7905 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7906 imm_expr.X_op = O_absent;
7910 case 'P': /* Performance register */
7911 my_getExpression (&imm_expr, s);
7912 check_absolute_expr (ip, &imm_expr);
7913 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7915 as_warn (_("Invalid performance register (%ld)"),
7916 (long) imm_expr.X_add_number);
7917 imm_expr.X_add_number &= OP_MASK_PERFREG;
7919 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7920 imm_expr.X_op = O_absent;
7924 case 'b': /* base register */
7925 case 'd': /* destination register */
7926 case 's': /* source register */
7927 case 't': /* target register */
7928 case 'r': /* both target and source */
7929 case 'v': /* both dest and source */
7930 case 'w': /* both dest and target */
7931 case 'E': /* coprocessor target register */
7932 case 'G': /* coprocessor destination register */
7933 case 'x': /* ignore register name */
7934 case 'z': /* must be zero register */
7935 case 'U': /* destination register (clo/clz). */
7950 while (ISDIGIT (*s));
7952 as_bad (_("Invalid register number (%d)"), regno);
7954 else if (*args == 'E' || *args == 'G')
7958 if (s[1] == 'f' && s[2] == 'p')
7963 else if (s[1] == 's' && s[2] == 'p')
7968 else if (s[1] == 'g' && s[2] == 'p')
7973 else if (s[1] == 'a' && s[2] == 't')
7978 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
7983 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
7988 else if (itbl_have_entries)
7993 p = s + 1; /* advance past '$' */
7994 n = itbl_get_field (&p); /* n is name */
7996 /* See if this is a register defined in an
7998 if (itbl_get_reg_val (n, &r))
8000 /* Get_field advances to the start of
8001 the next field, so we need to back
8002 rack to the end of the last field. */
8006 s = strchr (s, '\0');
8019 as_warn (_("Used $at without \".set noat\""));
8025 if (c == 'r' || c == 'v' || c == 'w')
8032 /* 'z' only matches $0. */
8033 if (c == 'z' && regno != 0)
8036 /* Now that we have assembled one operand, we use the args string
8037 * to figure out where it goes in the instruction. */
8044 ip->insn_opcode |= regno << OP_SH_RS;
8048 ip->insn_opcode |= regno << OP_SH_RD;
8051 ip->insn_opcode |= regno << OP_SH_RD;
8052 ip->insn_opcode |= regno << OP_SH_RT;
8057 ip->insn_opcode |= regno << OP_SH_RT;
8060 /* This case exists because on the r3000 trunc
8061 expands into a macro which requires a gp
8062 register. On the r6000 or r4000 it is
8063 assembled into a single instruction which
8064 ignores the register. Thus the insn version
8065 is MIPS_ISA2 and uses 'x', and the macro
8066 version is MIPS_ISA1 and uses 't'. */
8069 /* This case is for the div instruction, which
8070 acts differently if the destination argument
8071 is $0. This only matches $0, and is checked
8072 outside the switch. */
8075 /* Itbl operand; not yet implemented. FIXME ?? */
8077 /* What about all other operands like 'i', which
8078 can be specified in the opcode table? */
8088 ip->insn_opcode |= lastregno << OP_SH_RS;
8091 ip->insn_opcode |= lastregno << OP_SH_RT;
8096 case 'D': /* floating point destination register */
8097 case 'S': /* floating point source register */
8098 case 'T': /* floating point target register */
8099 case 'R': /* floating point source register */
8103 if (s[0] == '$' && s[1] == 'f'
8114 while (ISDIGIT (*s));
8117 as_bad (_("Invalid float register number (%d)"), regno);
8119 if ((regno & 1) != 0
8121 && ! (strcmp (str, "mtc1") == 0
8122 || strcmp (str, "mfc1") == 0
8123 || strcmp (str, "lwc1") == 0
8124 || strcmp (str, "swc1") == 0
8125 || strcmp (str, "l.s") == 0
8126 || strcmp (str, "s.s") == 0))
8127 as_warn (_("Float register should be even, was %d"),
8135 if (c == 'V' || c == 'W')
8145 ip->insn_opcode |= regno << OP_SH_FD;
8149 ip->insn_opcode |= regno << OP_SH_FS;
8153 ip->insn_opcode |= regno << OP_SH_FT;
8156 ip->insn_opcode |= regno << OP_SH_FR;
8166 ip->insn_opcode |= lastregno << OP_SH_FS;
8169 ip->insn_opcode |= lastregno << OP_SH_FT;
8175 my_getExpression (&imm_expr, s);
8176 if (imm_expr.X_op != O_big
8177 && imm_expr.X_op != O_constant)
8178 insn_error = _("absolute expression required");
8183 my_getExpression (&offset_expr, s);
8184 *imm_reloc = BFD_RELOC_32;
8197 unsigned char temp[8];
8199 unsigned int length;
8204 /* These only appear as the last operand in an
8205 instruction, and every instruction that accepts
8206 them in any variant accepts them in all variants.
8207 This means we don't have to worry about backing out
8208 any changes if the instruction does not match.
8210 The difference between them is the size of the
8211 floating point constant and where it goes. For 'F'
8212 and 'L' the constant is 64 bits; for 'f' and 'l' it
8213 is 32 bits. Where the constant is placed is based
8214 on how the MIPS assembler does things:
8217 f -- immediate value
8220 The .lit4 and .lit8 sections are only used if
8221 permitted by the -G argument.
8223 When generating embedded PIC code, we use the
8224 .lit8 section but not the .lit4 section (we can do
8225 .lit4 inline easily; we need to put .lit8
8226 somewhere in the data segment, and using .lit8
8227 permits the linker to eventually combine identical
8230 The code below needs to know whether the target register
8231 is 32 or 64 bits wide. It relies on the fact 'f' and
8232 'F' are used with GPR-based instructions and 'l' and
8233 'L' are used with FPR-based instructions. */
8235 f64 = *args == 'F' || *args == 'L';
8236 using_gprs = *args == 'F' || *args == 'f';
8238 save_in = input_line_pointer;
8239 input_line_pointer = s;
8240 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8242 s = input_line_pointer;
8243 input_line_pointer = save_in;
8244 if (err != NULL && *err != '\0')
8246 as_bad (_("Bad floating point constant: %s"), err);
8247 memset (temp, '\0', sizeof temp);
8248 length = f64 ? 8 : 4;
8251 assert (length == (unsigned) (f64 ? 8 : 4));
8255 && (! USE_GLOBAL_POINTER_OPT
8256 || mips_pic == EMBEDDED_PIC
8257 || g_switch_value < 4
8258 || (temp[0] == 0 && temp[1] == 0)
8259 || (temp[2] == 0 && temp[3] == 0))))
8261 imm_expr.X_op = O_constant;
8262 if (! target_big_endian)
8263 imm_expr.X_add_number = bfd_getl32 (temp);
8265 imm_expr.X_add_number = bfd_getb32 (temp);
8268 && ! mips_disable_float_construction
8269 /* Constants can only be constructed in GPRs and
8270 copied to FPRs if the GPRs are at least as wide
8271 as the FPRs. Force the constant into memory if
8272 we are using 64-bit FPRs but the GPRs are only
8275 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8276 && ((temp[0] == 0 && temp[1] == 0)
8277 || (temp[2] == 0 && temp[3] == 0))
8278 && ((temp[4] == 0 && temp[5] == 0)
8279 || (temp[6] == 0 && temp[7] == 0)))
8281 /* The value is simple enough to load with a couple of
8282 instructions. If using 32-bit registers, set
8283 imm_expr to the high order 32 bits and offset_expr to
8284 the low order 32 bits. Otherwise, set imm_expr to
8285 the entire 64 bit constant. */
8286 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8288 imm_expr.X_op = O_constant;
8289 offset_expr.X_op = O_constant;
8290 if (! target_big_endian)
8292 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8293 offset_expr.X_add_number = bfd_getl32 (temp);
8297 imm_expr.X_add_number = bfd_getb32 (temp);
8298 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8300 if (offset_expr.X_add_number == 0)
8301 offset_expr.X_op = O_absent;
8303 else if (sizeof (imm_expr.X_add_number) > 4)
8305 imm_expr.X_op = O_constant;
8306 if (! target_big_endian)
8307 imm_expr.X_add_number = bfd_getl64 (temp);
8309 imm_expr.X_add_number = bfd_getb64 (temp);
8313 imm_expr.X_op = O_big;
8314 imm_expr.X_add_number = 4;
8315 if (! target_big_endian)
8317 generic_bignum[0] = bfd_getl16 (temp);
8318 generic_bignum[1] = bfd_getl16 (temp + 2);
8319 generic_bignum[2] = bfd_getl16 (temp + 4);
8320 generic_bignum[3] = bfd_getl16 (temp + 6);
8324 generic_bignum[0] = bfd_getb16 (temp + 6);
8325 generic_bignum[1] = bfd_getb16 (temp + 4);
8326 generic_bignum[2] = bfd_getb16 (temp + 2);
8327 generic_bignum[3] = bfd_getb16 (temp);
8333 const char *newname;
8336 /* Switch to the right section. */
8338 subseg = now_subseg;
8341 default: /* unused default case avoids warnings. */
8343 newname = RDATA_SECTION_NAME;
8344 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8345 || mips_pic == EMBEDDED_PIC)
8349 if (mips_pic == EMBEDDED_PIC)
8352 newname = RDATA_SECTION_NAME;
8355 assert (!USE_GLOBAL_POINTER_OPT
8356 || g_switch_value >= 4);
8360 new_seg = subseg_new (newname, (subsegT) 0);
8361 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8362 bfd_set_section_flags (stdoutput, new_seg,
8367 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8368 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8369 && strcmp (TARGET_OS, "elf") != 0)
8370 record_alignment (new_seg, 4);
8372 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8374 as_bad (_("Can't use floating point insn in this section"));
8376 /* Set the argument to the current address in the
8378 offset_expr.X_op = O_symbol;
8379 offset_expr.X_add_symbol =
8380 symbol_new ("L0\001", now_seg,
8381 (valueT) frag_now_fix (), frag_now);
8382 offset_expr.X_add_number = 0;
8384 /* Put the floating point number into the section. */
8385 p = frag_more ((int) length);
8386 memcpy (p, temp, length);
8388 /* Switch back to the original section. */
8389 subseg_set (seg, subseg);
8394 case 'i': /* 16 bit unsigned immediate */
8395 case 'j': /* 16 bit signed immediate */
8396 *imm_reloc = BFD_RELOC_LO16;
8397 c = my_getSmallExpression (&imm_expr, s);
8402 if (imm_expr.X_op == O_constant)
8403 imm_expr.X_add_number =
8404 (imm_expr.X_add_number >> 16) & 0xffff;
8406 else if (c == S_EX_HIGHEST)
8407 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8408 else if (c == S_EX_HIGHER)
8409 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8410 else if (c == S_EX_GP_REL)
8412 /* This occurs in NewABI only. */
8413 c = my_getSmallExpression (&imm_expr, s);
8415 as_bad (_("bad composition of relocations"));
8418 c = my_getSmallExpression (&imm_expr, s);
8420 as_bad (_("bad composition of relocations"));
8423 imm_reloc[0] = BFD_RELOC_GPREL16;
8424 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8425 imm_reloc[2] = BFD_RELOC_LO16;
8430 else if (c == S_EX_HI)
8432 *imm_reloc = BFD_RELOC_HI16_S;
8433 imm_unmatched_hi = true;
8436 *imm_reloc = BFD_RELOC_HI16;
8438 else if (imm_expr.X_op == O_constant)
8439 imm_expr.X_add_number &= 0xffff;
8443 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8444 || ((imm_expr.X_add_number < 0
8445 || imm_expr.X_add_number >= 0x10000)
8446 && imm_expr.X_op == O_constant))
8448 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8449 !strcmp (insn->name, insn[1].name))
8451 if (imm_expr.X_op == O_constant
8452 || imm_expr.X_op == O_big)
8453 as_bad (_("16 bit expression not in range 0..65535"));
8461 /* The upper bound should be 0x8000, but
8462 unfortunately the MIPS assembler accepts numbers
8463 from 0x8000 to 0xffff and sign extends them, and
8464 we want to be compatible. We only permit this
8465 extended range for an instruction which does not
8466 provide any further alternates, since those
8467 alternates may handle other cases. People should
8468 use the numbers they mean, rather than relying on
8469 a mysterious sign extension. */
8470 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8471 strcmp (insn->name, insn[1].name) == 0);
8476 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8477 || ((imm_expr.X_add_number < -0x8000
8478 || imm_expr.X_add_number >= max)
8479 && imm_expr.X_op == O_constant)
8481 && imm_expr.X_add_number < 0
8483 && imm_expr.X_unsigned
8484 && sizeof (imm_expr.X_add_number) <= 4))
8488 if (imm_expr.X_op == O_constant
8489 || imm_expr.X_op == O_big)
8490 as_bad (_("16 bit expression not in range -32768..32767"));
8496 case 'o': /* 16 bit offset */
8497 c = my_getSmallExpression (&offset_expr, s);
8499 /* If this value won't fit into a 16 bit offset, then go
8500 find a macro that will generate the 32 bit offset
8503 && (offset_expr.X_op != O_constant
8504 || offset_expr.X_add_number >= 0x8000
8505 || offset_expr.X_add_number < -0x8000))
8510 if (offset_expr.X_op != O_constant)
8512 offset_expr.X_add_number =
8513 (offset_expr.X_add_number >> 16) & 0xffff;
8515 *offset_reloc = BFD_RELOC_LO16;
8519 case 'p': /* pc relative offset */
8520 if (mips_pic == EMBEDDED_PIC)
8521 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8523 *offset_reloc = BFD_RELOC_16_PCREL;
8524 my_getExpression (&offset_expr, s);
8528 case 'u': /* upper 16 bits */
8529 c = my_getSmallExpression (&imm_expr, s);
8530 *imm_reloc = BFD_RELOC_LO16;
8535 if (imm_expr.X_op == O_constant)
8536 imm_expr.X_add_number =
8537 (imm_expr.X_add_number >> 16) & 0xffff;
8538 else if (c == S_EX_HI)
8540 *imm_reloc = BFD_RELOC_HI16_S;
8541 imm_unmatched_hi = true;
8544 else if (c == S_EX_HIGHEST)
8545 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8546 else if (c == S_EX_GP_REL)
8548 /* This occurs in NewABI only. */
8549 c = my_getSmallExpression (&imm_expr, s);
8551 as_bad (_("bad composition of relocations"));
8554 c = my_getSmallExpression (&imm_expr, s);
8556 as_bad (_("bad composition of relocations"));
8559 imm_reloc[0] = BFD_RELOC_GPREL16;
8560 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8561 imm_reloc[2] = BFD_RELOC_HI16_S;
8567 *imm_reloc = BFD_RELOC_HI16;
8569 else if (imm_expr.X_op == O_constant)
8570 imm_expr.X_add_number &= 0xffff;
8572 if (imm_expr.X_op == O_constant
8573 && (imm_expr.X_add_number < 0
8574 || imm_expr.X_add_number >= 0x10000))
8575 as_bad (_("lui expression not in range 0..65535"));
8579 case 'a': /* 26 bit address */
8580 my_getExpression (&offset_expr, s);
8582 *offset_reloc = BFD_RELOC_MIPS_JMP;
8585 case 'N': /* 3 bit branch condition code */
8586 case 'M': /* 3 bit compare condition code */
8587 if (strncmp (s, "$fcc", 4) != 0)
8597 while (ISDIGIT (*s));
8599 as_bad (_("invalid condition code register $fcc%d"), regno);
8601 ip->insn_opcode |= regno << OP_SH_BCC;
8603 ip->insn_opcode |= regno << OP_SH_CCC;
8607 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8618 while (ISDIGIT (*s));
8621 c = 8; /* Invalid sel value. */
8624 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8625 ip->insn_opcode |= c;
8629 as_bad (_("bad char = '%c'\n"), *args);
8634 /* Args don't match. */
8635 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8636 !strcmp (insn->name, insn[1].name))
8640 insn_error = _("illegal operands");
8645 insn_error = _("illegal operands");
8650 /* This routine assembles an instruction into its binary format when
8651 assembling for the mips16. As a side effect, it sets one of the
8652 global variables imm_reloc or offset_reloc to the type of
8653 relocation to do if one of the operands is an address expression.
8654 It also sets mips16_small and mips16_ext if the user explicitly
8655 requested a small or extended instruction. */
8660 struct mips_cl_insn *ip;
8664 struct mips_opcode *insn;
8667 unsigned int lastregno = 0;
8672 mips16_small = false;
8675 for (s = str; ISLOWER (*s); ++s)
8687 if (s[1] == 't' && s[2] == ' ')
8690 mips16_small = true;
8694 else if (s[1] == 'e' && s[2] == ' ')
8703 insn_error = _("unknown opcode");
8707 if (mips_opts.noautoextend && ! mips16_ext)
8708 mips16_small = true;
8710 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8712 insn_error = _("unrecognized opcode");
8719 assert (strcmp (insn->name, str) == 0);
8722 ip->insn_opcode = insn->match;
8723 ip->use_extend = false;
8724 imm_expr.X_op = O_absent;
8725 imm_reloc[0] = BFD_RELOC_UNUSED;
8726 imm_reloc[1] = BFD_RELOC_UNUSED;
8727 imm_reloc[2] = BFD_RELOC_UNUSED;
8728 offset_expr.X_op = O_absent;
8729 offset_reloc[0] = BFD_RELOC_UNUSED;
8730 offset_reloc[1] = BFD_RELOC_UNUSED;
8731 offset_reloc[2] = BFD_RELOC_UNUSED;
8732 for (args = insn->args; 1; ++args)
8739 /* In this switch statement we call break if we did not find
8740 a match, continue if we did find a match, or return if we
8749 /* Stuff the immediate value in now, if we can. */
8750 if (imm_expr.X_op == O_constant
8751 && *imm_reloc > BFD_RELOC_UNUSED
8752 && insn->pinfo != INSN_MACRO)
8754 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8755 imm_expr.X_add_number, true, mips16_small,
8756 mips16_ext, &ip->insn_opcode,
8757 &ip->use_extend, &ip->extend);
8758 imm_expr.X_op = O_absent;
8759 *imm_reloc = BFD_RELOC_UNUSED;
8773 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8776 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8792 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8794 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8821 while (ISDIGIT (*s));
8824 as_bad (_("invalid register number (%d)"), regno);
8830 if (s[1] == 'f' && s[2] == 'p')
8835 else if (s[1] == 's' && s[2] == 'p')
8840 else if (s[1] == 'g' && s[2] == 'p')
8845 else if (s[1] == 'a' && s[2] == 't')
8850 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8855 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8868 if (c == 'v' || c == 'w')
8870 regno = mips16_to_32_reg_map[lastregno];
8884 regno = mips32_to_16_reg_map[regno];
8889 regno = ILLEGAL_REG;
8894 regno = ILLEGAL_REG;
8899 regno = ILLEGAL_REG;
8904 if (regno == AT && ! mips_opts.noat)
8905 as_warn (_("used $at without \".set noat\""));
8912 if (regno == ILLEGAL_REG)
8919 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
8923 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
8926 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
8929 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
8935 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
8938 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
8939 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
8949 if (strncmp (s, "$pc", 3) == 0)
8973 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
8975 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8976 and generate the appropriate reloc. If the text
8977 inside %gprel is not a symbol name with an
8978 optional offset, then we generate a normal reloc
8979 and will probably fail later. */
8980 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
8981 if (imm_expr.X_op == O_symbol)
8984 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
8986 ip->use_extend = true;
8993 /* Just pick up a normal expression. */
8994 my_getExpression (&imm_expr, s);
8997 if (imm_expr.X_op == O_register)
8999 /* What we thought was an expression turned out to
9002 if (s[0] == '(' && args[1] == '(')
9004 /* It looks like the expression was omitted
9005 before a register indirection, which means
9006 that the expression is implicitly zero. We
9007 still set up imm_expr, so that we handle
9008 explicit extensions correctly. */
9009 imm_expr.X_op = O_constant;
9010 imm_expr.X_add_number = 0;
9011 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9018 /* We need to relax this instruction. */
9019 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9028 /* We use offset_reloc rather than imm_reloc for the PC
9029 relative operands. This lets macros with both
9030 immediate and address operands work correctly. */
9031 my_getExpression (&offset_expr, s);
9033 if (offset_expr.X_op == O_register)
9036 /* We need to relax this instruction. */
9037 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9041 case '6': /* break code */
9042 my_getExpression (&imm_expr, s);
9043 check_absolute_expr (ip, &imm_expr);
9044 if ((unsigned long) imm_expr.X_add_number > 63)
9046 as_warn (_("Invalid value for `%s' (%lu)"),
9048 (unsigned long) imm_expr.X_add_number);
9049 imm_expr.X_add_number &= 0x3f;
9051 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9052 imm_expr.X_op = O_absent;
9056 case 'a': /* 26 bit address */
9057 my_getExpression (&offset_expr, s);
9059 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9060 ip->insn_opcode <<= 16;
9063 case 'l': /* register list for entry macro */
9064 case 'L': /* register list for exit macro */
9074 int freg, reg1, reg2;
9076 while (*s == ' ' || *s == ',')
9080 as_bad (_("can't parse register list"));
9092 while (ISDIGIT (*s))
9114 as_bad (_("invalid register list"));
9119 while (ISDIGIT (*s))
9126 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9131 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9136 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9137 mask |= (reg2 - 3) << 3;
9138 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9139 mask |= (reg2 - 15) << 1;
9140 else if (reg1 == 31 && reg2 == 31)
9144 as_bad (_("invalid register list"));
9148 /* The mask is filled in in the opcode table for the
9149 benefit of the disassembler. We remove it before
9150 applying the actual mask. */
9151 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9152 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9156 case 'e': /* extend code */
9157 my_getExpression (&imm_expr, s);
9158 check_absolute_expr (ip, &imm_expr);
9159 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9161 as_warn (_("Invalid value for `%s' (%lu)"),
9163 (unsigned long) imm_expr.X_add_number);
9164 imm_expr.X_add_number &= 0x7ff;
9166 ip->insn_opcode |= imm_expr.X_add_number;
9167 imm_expr.X_op = O_absent;
9177 /* Args don't match. */
9178 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9179 strcmp (insn->name, insn[1].name) == 0)
9186 insn_error = _("illegal operands");
9192 /* This structure holds information we know about a mips16 immediate
9195 struct mips16_immed_operand
9197 /* The type code used in the argument string in the opcode table. */
9199 /* The number of bits in the short form of the opcode. */
9201 /* The number of bits in the extended form of the opcode. */
9203 /* The amount by which the short form is shifted when it is used;
9204 for example, the sw instruction has a shift count of 2. */
9206 /* The amount by which the short form is shifted when it is stored
9207 into the instruction code. */
9209 /* Non-zero if the short form is unsigned. */
9211 /* Non-zero if the extended form is unsigned. */
9213 /* Non-zero if the value is PC relative. */
9217 /* The mips16 immediate operand types. */
9219 static const struct mips16_immed_operand mips16_immed_operands[] =
9221 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9222 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9223 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9224 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9225 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9226 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9227 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9228 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9229 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9230 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9231 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9232 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9233 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9234 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9235 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9236 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9237 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9238 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9239 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9240 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9241 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9244 #define MIPS16_NUM_IMMED \
9245 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9247 /* Handle a mips16 instruction with an immediate value. This or's the
9248 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9249 whether an extended value is needed; if one is needed, it sets
9250 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9251 If SMALL is true, an unextended opcode was explicitly requested.
9252 If EXT is true, an extended opcode was explicitly requested. If
9253 WARN is true, warn if EXT does not match reality. */
9256 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9265 unsigned long *insn;
9266 boolean *use_extend;
9267 unsigned short *extend;
9269 register const struct mips16_immed_operand *op;
9270 int mintiny, maxtiny;
9273 op = mips16_immed_operands;
9274 while (op->type != type)
9277 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9282 if (type == '<' || type == '>' || type == '[' || type == ']')
9285 maxtiny = 1 << op->nbits;
9290 maxtiny = (1 << op->nbits) - 1;
9295 mintiny = - (1 << (op->nbits - 1));
9296 maxtiny = (1 << (op->nbits - 1)) - 1;
9299 /* Branch offsets have an implicit 0 in the lowest bit. */
9300 if (type == 'p' || type == 'q')
9303 if ((val & ((1 << op->shift) - 1)) != 0
9304 || val < (mintiny << op->shift)
9305 || val > (maxtiny << op->shift))
9310 if (warn && ext && ! needext)
9311 as_warn_where (file, line,
9312 _("extended operand requested but not required"));
9313 if (small && needext)
9314 as_bad_where (file, line, _("invalid unextended operand value"));
9316 if (small || (! ext && ! needext))
9320 *use_extend = false;
9321 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9322 insnval <<= op->op_shift;
9327 long minext, maxext;
9333 maxext = (1 << op->extbits) - 1;
9337 minext = - (1 << (op->extbits - 1));
9338 maxext = (1 << (op->extbits - 1)) - 1;
9340 if (val < minext || val > maxext)
9341 as_bad_where (file, line,
9342 _("operand value out of range for instruction"));
9345 if (op->extbits == 16)
9347 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9350 else if (op->extbits == 15)
9352 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9357 extval = ((val & 0x1f) << 6) | (val & 0x20);
9361 *extend = (unsigned short) extval;
9366 static struct percent_op_match
9369 const enum small_ex_type type;
9374 {"%call_hi", S_EX_CALL_HI},
9375 {"%call_lo", S_EX_CALL_LO},
9376 {"%call16", S_EX_CALL16},
9377 {"%got_disp", S_EX_GOT_DISP},
9378 {"%got_page", S_EX_GOT_PAGE},
9379 {"%got_ofst", S_EX_GOT_OFST},
9380 {"%got_hi", S_EX_GOT_HI},
9381 {"%got_lo", S_EX_GOT_LO},
9383 {"%gp_rel", S_EX_GP_REL},
9384 {"%half", S_EX_HALF},
9385 {"%highest", S_EX_HIGHEST},
9386 {"%higher", S_EX_HIGHER},
9392 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9393 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9394 can be nested, this is handled by blanking the innermost, parsing the
9395 rest by subsequent calls. */
9398 my_getSmallParser (str, len, nestlevel)
9404 *str += strspn (*str, " \t");
9405 /* Check for expression in parentheses. */
9408 char *b = *str + 1 + strspn (*str + 1, " \t");
9411 /* Check for base register. */
9415 && (e = b + strcspn (b, ") \t"))
9416 && e - b > 1 && e - b < 4)
9419 && ((b[1] == 'f' && b[2] == 'p')
9420 || (b[1] == 's' && b[2] == 'p')
9421 || (b[1] == 'g' && b[2] == 'p')
9422 || (b[1] == 'a' && b[2] == 't')
9424 && ISDIGIT (b[2]))))
9425 || (ISDIGIT (b[1])))
9427 *len = strcspn (*str, ")") + 1;
9428 return S_EX_REGISTER;
9432 /* Check for percent_op (in parentheses). */
9433 else if (b[0] == '%')
9436 return my_getPercentOp (str, len, nestlevel);
9439 /* Some other expression in the parentheses, which can contain
9440 parentheses itself. Attempt to find the matching one. */
9446 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9455 /* Check for percent_op (outside of parentheses). */
9456 else if (*str[0] == '%')
9457 return my_getPercentOp (str, len, nestlevel);
9459 /* Any other expression. */
9464 my_getPercentOp (str, len, nestlevel)
9469 char *tmp = *str + 1;
9472 while (ISALPHA (*tmp) || *tmp == '_')
9474 *tmp = TOLOWER (*tmp);
9477 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9479 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9483 int type = percent_op[i].type;
9485 /* Only %hi and %lo are allowed for OldABI. */
9486 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9489 *len = strlen (percent_op[i].str);
9498 my_getSmallExpression (ep, str)
9502 static char *oldstr = NULL;
9508 /* Don't update oldstr if the last call had nested percent_op's. We need
9509 it to parse the outer ones later. */
9516 c = my_getSmallParser (&str, &len, &nestlevel);
9517 if (c != S_EX_NONE && c != S_EX_REGISTER)
9520 while (c != S_EX_NONE && c != S_EX_REGISTER);
9524 /* A percent_op was encountered. Don't try to get an expression if
9525 it is already blanked out. */
9526 if (*(str + strspn (str + 1, " )")) != ')')
9530 /* Let my_getExpression() stop at the closing parenthesis. */
9531 save = *(str + len);
9532 *(str + len) = '\0';
9533 my_getExpression (ep, str);
9534 *(str + len) = save;
9538 /* Blank out including the % sign and the proper matching
9541 char *s = strrchr (oldstr, '%');
9544 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9548 else if (*end == ')')
9552 memset (s, ' ', end - s);
9556 expr_end = str + len;
9560 else if (c == S_EX_NONE)
9562 my_getExpression (ep, str);
9564 else if (c == S_EX_REGISTER)
9566 ep->X_op = O_constant;
9568 ep->X_add_symbol = NULL;
9569 ep->X_op_symbol = NULL;
9570 ep->X_add_number = 0;
9574 as_fatal (_("internal error"));
9578 /* All percent_op's have been handled. */
9585 my_getExpression (ep, str)
9592 save_in = input_line_pointer;
9593 input_line_pointer = str;
9595 expr_end = input_line_pointer;
9596 input_line_pointer = save_in;
9598 /* If we are in mips16 mode, and this is an expression based on `.',
9599 then we bump the value of the symbol by 1 since that is how other
9600 text symbols are handled. We don't bother to handle complex
9601 expressions, just `.' plus or minus a constant. */
9602 if (mips_opts.mips16
9603 && ep->X_op == O_symbol
9604 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9605 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9606 && symbol_get_frag (ep->X_add_symbol) == frag_now
9607 && symbol_constant_p (ep->X_add_symbol)
9608 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9609 S_SET_VALUE (ep->X_add_symbol, val + 1);
9612 /* Turn a string in input_line_pointer into a floating point constant
9613 of type TYPE, and store the appropriate bytes in *LITP. The number
9614 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9615 returned, or NULL on OK. */
9618 md_atof (type, litP, sizeP)
9624 LITTLENUM_TYPE words[4];
9640 return _("bad call to md_atof");
9643 t = atof_ieee (input_line_pointer, type, words);
9645 input_line_pointer = t;
9649 if (! target_big_endian)
9651 for (i = prec - 1; i >= 0; i--)
9653 md_number_to_chars (litP, (valueT) words[i], 2);
9659 for (i = 0; i < prec; i++)
9661 md_number_to_chars (litP, (valueT) words[i], 2);
9670 md_number_to_chars (buf, val, n)
9675 if (target_big_endian)
9676 number_to_chars_bigendian (buf, val, n);
9678 number_to_chars_littleendian (buf, val, n);
9682 static int support_64bit_objects(void)
9684 const char **list, **l;
9686 list = bfd_target_list ();
9687 for (l = list; *l != NULL; l++)
9689 /* This is traditional mips */
9690 if (strcmp (*l, "elf64-tradbigmips") == 0
9691 || strcmp (*l, "elf64-tradlittlemips") == 0)
9693 if (strcmp (*l, "elf64-bigmips") == 0
9694 || strcmp (*l, "elf64-littlemips") == 0)
9698 return (*l != NULL);
9700 #endif /* OBJ_ELF */
9702 CONST char *md_shortopts = "nO::g::G:";
9704 struct option md_longopts[] =
9706 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9707 {"mips0", no_argument, NULL, OPTION_MIPS1},
9708 {"mips1", no_argument, NULL, OPTION_MIPS1},
9709 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9710 {"mips2", no_argument, NULL, OPTION_MIPS2},
9711 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9712 {"mips3", no_argument, NULL, OPTION_MIPS3},
9713 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9714 {"mips4", no_argument, NULL, OPTION_MIPS4},
9715 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9716 {"mips5", no_argument, NULL, OPTION_MIPS5},
9717 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9718 {"mips32", no_argument, NULL, OPTION_MIPS32},
9719 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9720 {"mips64", no_argument, NULL, OPTION_MIPS64},
9721 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9722 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9723 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9724 {"trap", no_argument, NULL, OPTION_TRAP},
9725 {"no-break", no_argument, NULL, OPTION_TRAP},
9726 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9727 {"break", no_argument, NULL, OPTION_BREAK},
9728 {"no-trap", no_argument, NULL, OPTION_BREAK},
9729 #define OPTION_EB (OPTION_MD_BASE + 11)
9730 {"EB", no_argument, NULL, OPTION_EB},
9731 #define OPTION_EL (OPTION_MD_BASE + 12)
9732 {"EL", no_argument, NULL, OPTION_EL},
9733 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9734 {"mips16", no_argument, NULL, OPTION_MIPS16},
9735 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9736 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9737 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9738 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9739 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16)
9740 {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX},
9741 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9742 {"mfp32", no_argument, NULL, OPTION_FP32},
9743 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9744 {"mgp32", no_argument, NULL, OPTION_GP32},
9745 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9746 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9747 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9748 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9749 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9750 {"march", required_argument, NULL, OPTION_MARCH},
9751 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9752 {"mtune", required_argument, NULL, OPTION_MTUNE},
9753 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9754 {"mcpu", required_argument, NULL, OPTION_MCPU},
9755 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9756 {"m4650", no_argument, NULL, OPTION_M4650},
9757 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9758 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9759 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9760 {"m4010", no_argument, NULL, OPTION_M4010},
9761 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9762 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9763 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9764 {"m4100", no_argument, NULL, OPTION_M4100},
9765 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9766 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9767 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9768 {"m3900", no_argument, NULL, OPTION_M3900},
9769 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9770 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9771 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9772 {"mgp64", no_argument, NULL, OPTION_GP64},
9773 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9774 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
9775 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9776 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
9778 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
9779 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9780 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9781 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9782 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9783 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
9784 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9785 {"xgot", no_argument, NULL, OPTION_XGOT},
9786 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9787 {"mabi", required_argument, NULL, OPTION_MABI},
9788 #define OPTION_32 (OPTION_ELF_BASE + 4)
9789 {"32", no_argument, NULL, OPTION_32},
9790 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9791 {"n32", no_argument, NULL, OPTION_N32},
9792 #define OPTION_64 (OPTION_ELF_BASE + 6)
9793 {"64", no_argument, NULL, OPTION_64},
9794 #endif /* OBJ_ELF */
9795 {NULL, no_argument, NULL, 0}
9797 size_t md_longopts_size = sizeof (md_longopts);
9800 md_parse_option (c, arg)
9806 case OPTION_CONSTRUCT_FLOATS:
9807 mips_disable_float_construction = 0;
9810 case OPTION_NO_CONSTRUCT_FLOATS:
9811 mips_disable_float_construction = 1;
9823 target_big_endian = 1;
9827 target_big_endian = 0;
9835 if (arg && arg[1] == '0')
9845 mips_debug = atoi (arg);
9846 /* When the MIPS assembler sees -g or -g2, it does not do
9847 optimizations which limit full symbolic debugging. We take
9848 that to be equivalent to -O0. */
9849 if (mips_debug == 2)
9854 mips_opts.isa = ISA_MIPS1;
9858 mips_opts.isa = ISA_MIPS2;
9862 mips_opts.isa = ISA_MIPS3;
9866 mips_opts.isa = ISA_MIPS4;
9870 mips_opts.isa = ISA_MIPS5;
9874 mips_opts.isa = ISA_MIPS32;
9878 mips_opts.isa = ISA_MIPS64;
9885 int cpu = CPU_UNKNOWN;
9887 /* Identify the processor type. */
9888 if (strcasecmp (arg, "default") != 0)
9890 const struct mips_cpu_info *ci;
9892 ci = mips_cpu_info_from_name (arg);
9893 if (ci == NULL || ci->is_isa)
9898 as_fatal (_("invalid architecture -mtune=%s"), arg);
9901 as_fatal (_("invalid architecture -march=%s"), arg);
9904 as_fatal (_("invalid architecture -mcpu=%s"), arg);
9915 if (mips_tune != CPU_UNKNOWN && mips_tune != cpu)
9916 as_warn (_("A different -mtune= was already specified, is now "
9921 if (mips_arch != CPU_UNKNOWN && mips_arch != cpu)
9922 as_warn (_("A different -march= was already specified, is now "
9927 if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu)
9928 as_warn (_("A different -mcpu= was already specified, is now "
9936 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650)
9937 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650))
9938 as_warn (_("A different -march= or -mtune= was already specified, "
9940 mips_arch = CPU_R4650;
9941 mips_tune = CPU_R4650;
9944 case OPTION_NO_M4650:
9948 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010)
9949 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010))
9950 as_warn (_("A different -march= or -mtune= was already specified, "
9952 mips_arch = CPU_R4010;
9953 mips_tune = CPU_R4010;
9956 case OPTION_NO_M4010:
9960 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100)
9961 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100))
9962 as_warn (_("A different -march= or -mtune= was already specified, "
9964 mips_arch = CPU_VR4100;
9965 mips_tune = CPU_VR4100;
9968 case OPTION_NO_M4100:
9972 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900)
9973 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900))
9974 as_warn (_("A different -march= or -mtune= was already specified, "
9976 mips_arch = CPU_R3900;
9977 mips_tune = CPU_R3900;
9980 case OPTION_NO_M3900:
9984 mips_opts.mips16 = 1;
9985 mips_no_prev_insn (false);
9988 case OPTION_NO_MIPS16:
9989 mips_opts.mips16 = 0;
9990 mips_no_prev_insn (false);
9994 mips_opts.ase_mips3d = 1;
9997 case OPTION_NO_MIPS3D:
9998 mips_opts.ase_mips3d = 0;
10001 case OPTION_MEMBEDDED_PIC:
10002 mips_pic = EMBEDDED_PIC;
10003 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10005 as_bad (_("-G may not be used with embedded PIC code"));
10008 g_switch_value = 0x7fffffff;
10012 /* When generating ELF code, we permit -KPIC and -call_shared to
10013 select SVR4_PIC, and -non_shared to select no PIC. This is
10014 intended to be compatible with Irix 5. */
10015 case OPTION_CALL_SHARED:
10016 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10018 as_bad (_("-call_shared is supported only for ELF format"));
10021 mips_pic = SVR4_PIC;
10022 if (g_switch_seen && g_switch_value != 0)
10024 as_bad (_("-G may not be used with SVR4 PIC code"));
10027 g_switch_value = 0;
10030 case OPTION_NON_SHARED:
10031 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10033 as_bad (_("-non_shared is supported only for ELF format"));
10039 /* The -xgot option tells the assembler to use 32 offsets when
10040 accessing the got in SVR4_PIC mode. It is for Irix
10045 #endif /* OBJ_ELF */
10048 if (! USE_GLOBAL_POINTER_OPT)
10050 as_bad (_("-G is not supported for this configuration"));
10053 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10055 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10059 g_switch_value = atoi (arg);
10064 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10067 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10069 as_bad (_("-32 is supported for ELF format only"));
10072 mips_opts.abi = O32_ABI;
10076 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10078 as_bad (_("-n32 is supported for ELF format only"));
10081 mips_opts.abi = N32_ABI;
10085 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10087 as_bad (_("-64 is supported for ELF format only"));
10090 mips_opts.abi = N64_ABI;
10091 if (! support_64bit_objects())
10092 as_fatal (_("No compiled in support for 64 bit object file format"));
10094 #endif /* OBJ_ELF */
10097 file_mips_gp32 = 1;
10098 if (mips_opts.abi != O32_ABI)
10099 mips_opts.abi = NO_ABI;
10103 file_mips_gp32 = 0;
10104 if (mips_opts.abi == O32_ABI)
10105 mips_opts.abi = NO_ABI;
10109 file_mips_fp32 = 1;
10110 if (mips_opts.abi != O32_ABI)
10111 mips_opts.abi = NO_ABI;
10116 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10118 as_bad (_("-mabi is supported for ELF format only"));
10121 if (strcmp (arg, "32") == 0)
10122 mips_opts.abi = O32_ABI;
10123 else if (strcmp (arg, "o64") == 0)
10124 mips_opts.abi = O64_ABI;
10125 else if (strcmp (arg, "n32") == 0)
10126 mips_opts.abi = N32_ABI;
10127 else if (strcmp (arg, "64") == 0)
10129 mips_opts.abi = N64_ABI;
10130 if (! support_64bit_objects())
10131 as_fatal (_("No compiled in support for 64 bit object file "
10134 else if (strcmp (arg, "eabi") == 0)
10135 mips_opts.abi = EABI_ABI;
10138 as_fatal (_("invalid abi -mabi=%s"), arg);
10142 #endif /* OBJ_ELF */
10144 case OPTION_M7000_HILO_FIX:
10145 mips_7000_hilo_fix = true;
10148 case OPTION_NO_M7000_HILO_FIX:
10149 mips_7000_hilo_fix = false;
10160 show (stream, string, col_p, first_p)
10168 fprintf (stream, "%24s", "");
10173 fprintf (stream, ", ");
10177 if (*col_p + strlen (string) > 72)
10179 fprintf (stream, "\n%24s", "");
10183 fprintf (stream, "%s", string);
10184 *col_p += strlen (string);
10190 md_show_usage (stream)
10195 fprintf (stream, _("\
10197 -membedded-pic generate embedded position independent code\n\
10198 -EB generate big endian output\n\
10199 -EL generate little endian output\n\
10200 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10201 -G NUM allow referencing objects up to NUM bytes\n\
10202 implicitly with the gp register [default 8]\n"));
10203 fprintf (stream, _("\
10204 -mips1 generate MIPS ISA I instructions\n\
10205 -mips2 generate MIPS ISA II instructions\n\
10206 -mips3 generate MIPS ISA III instructions\n\
10207 -mips4 generate MIPS ISA IV instructions\n\
10208 -mips5 generate MIPS ISA V instructions\n\
10209 -mips32 generate MIPS32 ISA instructions\n\
10210 -mips64 generate MIPS64 ISA instructions\n\
10211 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10215 show (stream, "2000", &column, &first);
10216 show (stream, "3000", &column, &first);
10217 show (stream, "3900", &column, &first);
10218 show (stream, "4000", &column, &first);
10219 show (stream, "4010", &column, &first);
10220 show (stream, "4100", &column, &first);
10221 show (stream, "4111", &column, &first);
10222 show (stream, "4300", &column, &first);
10223 show (stream, "4400", &column, &first);
10224 show (stream, "4600", &column, &first);
10225 show (stream, "4650", &column, &first);
10226 show (stream, "5000", &column, &first);
10227 show (stream, "5200", &column, &first);
10228 show (stream, "5230", &column, &first);
10229 show (stream, "5231", &column, &first);
10230 show (stream, "5261", &column, &first);
10231 show (stream, "5721", &column, &first);
10232 show (stream, "6000", &column, &first);
10233 show (stream, "8000", &column, &first);
10234 show (stream, "10000", &column, &first);
10235 show (stream, "12000", &column, &first);
10236 show (stream, "sb1", &column, &first);
10237 fputc ('\n', stream);
10239 fprintf (stream, _("\
10240 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10241 -no-mCPU don't generate code specific to CPU.\n\
10242 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10246 show (stream, "3900", &column, &first);
10247 show (stream, "4010", &column, &first);
10248 show (stream, "4100", &column, &first);
10249 show (stream, "4650", &column, &first);
10250 fputc ('\n', stream);
10252 fprintf (stream, _("\
10253 -mips16 generate mips16 instructions\n\
10254 -no-mips16 do not generate mips16 instructions\n"));
10255 fprintf (stream, _("\
10256 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10257 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10258 -O0 remove unneeded NOPs, do not swap branches\n\
10259 -O remove unneeded NOPs and swap branches\n\
10260 -n warn about NOPs generated from macros\n\
10261 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10262 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10263 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10265 fprintf (stream, _("\
10266 -KPIC, -call_shared generate SVR4 position independent code\n\
10267 -non_shared do not generate position independent code\n\
10268 -xgot assume a 32 bit GOT\n\
10269 -mabi=ABI create ABI conformant object file for:\n"));
10273 show (stream, "32", &column, &first);
10274 show (stream, "o64", &column, &first);
10275 show (stream, "n32", &column, &first);
10276 show (stream, "64", &column, &first);
10277 show (stream, "eabi", &column, &first);
10279 fputc ('\n', stream);
10281 fprintf (stream, _("\
10282 -32 create o32 ABI object file (default)\n\
10283 -n32 create n32 ABI object file\n\
10284 -64 create 64 ABI object file\n"));
10289 mips_init_after_args ()
10291 /* initialize opcodes */
10292 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10293 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10297 md_pcrel_from (fixP)
10300 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10301 && fixP->fx_addsy != (symbolS *) NULL
10302 && ! S_IS_DEFINED (fixP->fx_addsy))
10304 /* This makes a branch to an undefined symbol be a branch to the
10305 current location. */
10306 if (mips_pic == EMBEDDED_PIC)
10312 /* return the address of the delay slot */
10313 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10316 /* This is called before the symbol table is processed. In order to
10317 work with gcc when using mips-tfile, we must keep all local labels.
10318 However, in other cases, we want to discard them. If we were
10319 called with -g, but we didn't see any debugging information, it may
10320 mean that gcc is smuggling debugging information through to
10321 mips-tfile, in which case we must generate all local labels. */
10324 mips_frob_file_before_adjust ()
10326 #ifndef NO_ECOFF_DEBUGGING
10327 if (ECOFF_DEBUGGING
10329 && ! ecoff_debugging_seen)
10330 flag_keep_locals = 1;
10334 /* Sort any unmatched HI16_S relocs so that they immediately precede
10335 the corresponding LO reloc. This is called before md_apply_fix3 and
10336 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10337 explicit use of the %hi modifier. */
10342 struct mips_hi_fixup *l;
10344 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10346 segment_info_type *seginfo;
10349 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10351 /* Check quickly whether the next fixup happens to be a matching
10353 if (l->fixp->fx_next != NULL
10354 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10355 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10356 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10359 /* Look through the fixups for this segment for a matching %lo.
10360 When we find one, move the %hi just in front of it. We do
10361 this in two passes. In the first pass, we try to find a
10362 unique %lo. In the second pass, we permit multiple %hi
10363 relocs for a single %lo (this is a GNU extension). */
10364 seginfo = seg_info (l->seg);
10365 for (pass = 0; pass < 2; pass++)
10370 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10372 /* Check whether this is a %lo fixup which matches l->fixp. */
10373 if (f->fx_r_type == BFD_RELOC_LO16
10374 && f->fx_addsy == l->fixp->fx_addsy
10375 && f->fx_offset == l->fixp->fx_offset
10378 || prev->fx_r_type != BFD_RELOC_HI16_S
10379 || prev->fx_addsy != f->fx_addsy
10380 || prev->fx_offset != f->fx_offset))
10384 /* Move l->fixp before f. */
10385 for (pf = &seginfo->fix_root;
10387 pf = &(*pf)->fx_next)
10388 assert (*pf != NULL);
10390 *pf = l->fixp->fx_next;
10392 l->fixp->fx_next = f;
10394 seginfo->fix_root = l->fixp;
10396 prev->fx_next = l->fixp;
10407 #if 0 /* GCC code motion plus incomplete dead code elimination
10408 can leave a %hi without a %lo. */
10410 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10411 _("Unmatched %%hi reloc"));
10417 /* When generating embedded PIC code we need to use a special
10418 relocation to represent the difference of two symbols in the .text
10419 section (switch tables use a difference of this sort). See
10420 include/coff/mips.h for details. This macro checks whether this
10421 fixup requires the special reloc. */
10422 #define SWITCH_TABLE(fixp) \
10423 ((fixp)->fx_r_type == BFD_RELOC_32 \
10424 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10425 && (fixp)->fx_addsy != NULL \
10426 && (fixp)->fx_subsy != NULL \
10427 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10428 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10430 /* When generating embedded PIC code we must keep all PC relative
10431 relocations, in case the linker has to relax a call. We also need
10432 to keep relocations for switch table entries.
10434 We may have combined relocations without symbols in the N32/N64 ABI.
10435 We have to prevent gas from dropping them. */
10438 mips_force_relocation (fixp)
10441 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10442 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10446 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10447 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10448 || fixp->fx_r_type == BFD_RELOC_HI16_S
10449 || fixp->fx_r_type == BFD_RELOC_LO16))
10452 return (mips_pic == EMBEDDED_PIC
10454 || SWITCH_TABLE (fixp)
10455 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10456 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10461 mips_need_elf_addend_fixup (fixP)
10464 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10466 if (mips_pic == EMBEDDED_PIC
10467 && S_IS_WEAK (fixP->fx_addsy))
10469 if (mips_pic != EMBEDDED_PIC
10470 && (S_IS_WEAK (fixP->fx_addsy)
10471 || S_IS_EXTERN (fixP->fx_addsy))
10472 && !S_IS_COMMON (fixP->fx_addsy))
10474 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10475 && (((bfd_get_section_flags (stdoutput,
10476 S_GET_SEGMENT (fixP->fx_addsy))
10477 & SEC_LINK_ONCE) != 0)
10478 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10480 sizeof (".gnu.linkonce") - 1)))
10486 /* Apply a fixup to the object file. */
10489 md_apply_fix3 (fixP, valP, seg)
10492 segT seg ATTRIBUTE_UNUSED;
10498 assert (fixP->fx_size == 4
10499 || fixP->fx_r_type == BFD_RELOC_16
10500 || fixP->fx_r_type == BFD_RELOC_32
10501 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10502 || fixP->fx_r_type == BFD_RELOC_HI16_S
10503 || fixP->fx_r_type == BFD_RELOC_LO16
10504 || fixP->fx_r_type == BFD_RELOC_GPREL16
10505 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10506 || fixP->fx_r_type == BFD_RELOC_GPREL32
10507 || fixP->fx_r_type == BFD_RELOC_64
10508 || fixP->fx_r_type == BFD_RELOC_CTOR
10509 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10510 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10511 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10512 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10513 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10514 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10515 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10516 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
10520 /* If we aren't adjusting this fixup to be against the section
10521 symbol, we need to adjust the value. */
10523 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10525 if (mips_need_elf_addend_fixup (fixP))
10527 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10530 if (value != 0 && ! fixP->fx_pcrel)
10532 /* In this case, the bfd_install_relocation routine will
10533 incorrectly add the symbol value back in. We just want
10534 the addend to appear in the object file. */
10537 /* Make sure the addend is still non-zero. If it became zero
10538 after the last operation, set it to a spurious value and
10539 subtract the same value from the object file's contents. */
10544 /* The in-place addends for LO16 relocations are signed;
10545 leave the matching HI16 in-place addends as zero. */
10546 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10548 reloc_howto_type *howto;
10549 bfd_vma contents, mask, field;
10551 howto = bfd_reloc_type_lookup (stdoutput,
10554 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10557 target_big_endian);
10559 /* MASK has bits set where the relocation should go.
10560 FIELD is -value, shifted into the appropriate place
10561 for this relocation. */
10562 mask = 1 << (howto->bitsize - 1);
10563 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10564 field = (-value >> howto->rightshift) << howto->bitpos;
10566 bfd_put_bits ((field & mask) | (contents & ~mask),
10567 fixP->fx_frag->fr_literal + fixP->fx_where,
10569 target_big_endian);
10575 /* This code was generated using trial and error and so is
10576 fragile and not trustworthy. If you change it, you should
10577 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10578 they still pass. */
10579 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10581 value += fixP->fx_frag->fr_address + fixP->fx_where;
10583 /* BFD's REL handling, for MIPS, is _very_ weird.
10584 This gives the right results, but it can't possibly
10585 be the way things are supposed to work. */
10586 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10587 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10588 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10589 value += fixP->fx_frag->fr_address + fixP->fx_where;
10594 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10596 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
10599 switch (fixP->fx_r_type)
10601 case BFD_RELOC_MIPS_JMP:
10602 case BFD_RELOC_MIPS_SHIFT5:
10603 case BFD_RELOC_MIPS_SHIFT6:
10604 case BFD_RELOC_MIPS_GOT_DISP:
10605 case BFD_RELOC_MIPS_GOT_PAGE:
10606 case BFD_RELOC_MIPS_GOT_OFST:
10607 case BFD_RELOC_MIPS_SUB:
10608 case BFD_RELOC_MIPS_INSERT_A:
10609 case BFD_RELOC_MIPS_INSERT_B:
10610 case BFD_RELOC_MIPS_DELETE:
10611 case BFD_RELOC_MIPS_HIGHEST:
10612 case BFD_RELOC_MIPS_HIGHER:
10613 case BFD_RELOC_MIPS_SCN_DISP:
10614 case BFD_RELOC_MIPS_REL16:
10615 case BFD_RELOC_MIPS_RELGOT:
10616 case BFD_RELOC_MIPS_JALR:
10617 case BFD_RELOC_HI16:
10618 case BFD_RELOC_HI16_S:
10619 case BFD_RELOC_GPREL16:
10620 case BFD_RELOC_MIPS_LITERAL:
10621 case BFD_RELOC_MIPS_CALL16:
10622 case BFD_RELOC_MIPS_GOT16:
10623 case BFD_RELOC_GPREL32:
10624 case BFD_RELOC_MIPS_GOT_HI16:
10625 case BFD_RELOC_MIPS_GOT_LO16:
10626 case BFD_RELOC_MIPS_CALL_HI16:
10627 case BFD_RELOC_MIPS_CALL_LO16:
10628 case BFD_RELOC_MIPS16_GPREL:
10629 if (fixP->fx_pcrel)
10630 as_bad_where (fixP->fx_file, fixP->fx_line,
10631 _("Invalid PC relative reloc"));
10632 /* Nothing needed to do. The value comes from the reloc entry */
10635 case BFD_RELOC_MIPS16_JMP:
10636 /* We currently always generate a reloc against a symbol, which
10637 means that we don't want an addend even if the symbol is
10639 fixP->fx_addnumber = 0;
10642 case BFD_RELOC_PCREL_HI16_S:
10643 /* The addend for this is tricky if it is internal, so we just
10644 do everything here rather than in bfd_install_relocation. */
10645 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10650 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10652 /* For an external symbol adjust by the address to make it
10653 pcrel_offset. We use the address of the RELLO reloc
10654 which follows this one. */
10655 value += (fixP->fx_next->fx_frag->fr_address
10656 + fixP->fx_next->fx_where);
10658 value = ((value + 0x8000) >> 16) & 0xffff;
10659 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10660 if (target_big_endian)
10662 md_number_to_chars ((char *) buf, value, 2);
10665 case BFD_RELOC_PCREL_LO16:
10666 /* The addend for this is tricky if it is internal, so we just
10667 do everything here rather than in bfd_install_relocation. */
10668 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10673 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10674 value += fixP->fx_frag->fr_address + fixP->fx_where;
10675 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10676 if (target_big_endian)
10678 md_number_to_chars ((char *) buf, value, 2);
10682 /* This is handled like BFD_RELOC_32, but we output a sign
10683 extended value if we are only 32 bits. */
10685 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10687 if (8 <= sizeof (valueT))
10688 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10695 w1 = w2 = fixP->fx_where;
10696 if (target_big_endian)
10700 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
10701 if ((value & 0x80000000) != 0)
10705 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
10710 case BFD_RELOC_RVA:
10712 /* If we are deleting this reloc entry, we must fill in the
10713 value now. This can happen if we have a .word which is not
10714 resolved when it appears but is later defined. We also need
10715 to fill in the value if this is an embedded PIC switch table
10718 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10719 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10724 /* If we are deleting this reloc entry, we must fill in the
10726 assert (fixP->fx_size == 2);
10728 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10732 case BFD_RELOC_LO16:
10733 /* When handling an embedded PIC switch statement, we can wind
10734 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10737 if (value + 0x8000 > 0xffff)
10738 as_bad_where (fixP->fx_file, fixP->fx_line,
10739 _("relocation overflow"));
10740 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10741 if (target_big_endian)
10743 md_number_to_chars ((char *) buf, value, 2);
10747 case BFD_RELOC_16_PCREL_S2:
10748 if ((value & 0x3) != 0)
10749 as_bad_where (fixP->fx_file, fixP->fx_line,
10750 _("Branch to odd address (%lx)"), (long) value);
10752 /* Fall through. */
10754 case BFD_RELOC_16_PCREL:
10756 * We need to save the bits in the instruction since fixup_segment()
10757 * might be deleting the relocation entry (i.e., a branch within
10758 * the current segment).
10760 if (!fixP->fx_done && value != 0)
10762 /* If 'value' is zero, the remaining reloc code won't actually
10763 do the store, so it must be done here. This is probably
10764 a bug somewhere. */
10766 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
10767 || fixP->fx_addsy == NULL /* ??? */
10768 || ! S_IS_DEFINED (fixP->fx_addsy)))
10769 value -= fixP->fx_frag->fr_address + fixP->fx_where;
10771 value = (offsetT) value >> 2;
10773 /* update old instruction data */
10774 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
10775 if (target_big_endian)
10776 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
10778 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
10780 if (value + 0x8000 <= 0xffff)
10781 insn |= value & 0xffff;
10784 /* The branch offset is too large. If this is an
10785 unconditional branch, and we are not generating PIC code,
10786 we can convert it to an absolute jump instruction. */
10787 if (mips_pic == NO_PIC
10789 && fixP->fx_frag->fr_address >= text_section->vma
10790 && (fixP->fx_frag->fr_address
10791 < text_section->vma + text_section->_raw_size)
10792 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
10793 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
10794 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
10796 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
10797 insn = 0x0c000000; /* jal */
10799 insn = 0x08000000; /* j */
10800 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
10802 fixP->fx_addsy = section_symbol (text_section);
10803 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
10807 /* FIXME. It would be possible in principle to handle
10808 conditional branches which overflow. They could be
10809 transformed into a branch around a jump. This would
10810 require setting up variant frags for each different
10811 branch type. The native MIPS assembler attempts to
10812 handle these cases, but it appears to do it
10814 as_bad_where (fixP->fx_file, fixP->fx_line,
10815 _("Branch out of range"));
10819 md_number_to_chars ((char *) buf, (valueT) insn, 4);
10822 case BFD_RELOC_VTABLE_INHERIT:
10825 && !S_IS_DEFINED (fixP->fx_addsy)
10826 && !S_IS_WEAK (fixP->fx_addsy))
10827 S_SET_WEAK (fixP->fx_addsy);
10830 case BFD_RELOC_VTABLE_ENTRY:
10844 const struct mips_opcode *p;
10845 int treg, sreg, dreg, shamt;
10850 for (i = 0; i < NUMOPCODES; ++i)
10852 p = &mips_opcodes[i];
10853 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
10855 printf ("%08lx %s\t", oc, p->name);
10856 treg = (oc >> 16) & 0x1f;
10857 sreg = (oc >> 21) & 0x1f;
10858 dreg = (oc >> 11) & 0x1f;
10859 shamt = (oc >> 6) & 0x1f;
10861 for (args = p->args;; ++args)
10872 printf ("%c", *args);
10876 assert (treg == sreg);
10877 printf ("$%d,$%d", treg, sreg);
10882 printf ("$%d", dreg);
10887 printf ("$%d", treg);
10891 printf ("0x%x", treg);
10896 printf ("$%d", sreg);
10900 printf ("0x%08lx", oc & 0x1ffffff);
10907 printf ("%d", imm);
10912 printf ("$%d", shamt);
10923 printf (_("%08lx UNDEFINED\n"), oc);
10934 name = input_line_pointer;
10935 c = get_symbol_end ();
10936 p = (symbolS *) symbol_find_or_make (name);
10937 *input_line_pointer = c;
10941 /* Align the current frag to a given power of two. The MIPS assembler
10942 also automatically adjusts any preceding label. */
10945 mips_align (to, fill, label)
10950 mips_emit_delays (false);
10951 frag_align (to, fill, 0);
10952 record_alignment (now_seg, to);
10955 assert (S_GET_SEGMENT (label) == now_seg);
10956 symbol_set_frag (label, frag_now);
10957 S_SET_VALUE (label, (valueT) frag_now_fix ());
10961 /* Align to a given power of two. .align 0 turns off the automatic
10962 alignment used by the data creating pseudo-ops. */
10966 int x ATTRIBUTE_UNUSED;
10969 register long temp_fill;
10970 long max_alignment = 15;
10974 o Note that the assembler pulls down any immediately preceeding label
10975 to the aligned address.
10976 o It's not documented but auto alignment is reinstated by
10977 a .align pseudo instruction.
10978 o Note also that after auto alignment is turned off the mips assembler
10979 issues an error on attempt to assemble an improperly aligned data item.
10984 temp = get_absolute_expression ();
10985 if (temp > max_alignment)
10986 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
10989 as_warn (_("Alignment negative: 0 assumed."));
10992 if (*input_line_pointer == ',')
10994 input_line_pointer++;
10995 temp_fill = get_absolute_expression ();
11002 mips_align (temp, (int) temp_fill,
11003 insn_labels != NULL ? insn_labels->label : NULL);
11010 demand_empty_rest_of_line ();
11014 mips_flush_pending_output ()
11016 mips_emit_delays (false);
11017 mips_clear_insn_labels ();
11026 /* When generating embedded PIC code, we only use the .text, .lit8,
11027 .sdata and .sbss sections. We change the .data and .rdata
11028 pseudo-ops to use .sdata. */
11029 if (mips_pic == EMBEDDED_PIC
11030 && (sec == 'd' || sec == 'r'))
11034 /* The ELF backend needs to know that we are changing sections, so
11035 that .previous works correctly. We could do something like check
11036 for an obj_section_change_hook macro, but that might be confusing
11037 as it would not be appropriate to use it in the section changing
11038 functions in read.c, since obj-elf.c intercepts those. FIXME:
11039 This should be cleaner, somehow. */
11040 obj_elf_section_change_hook ();
11043 mips_emit_delays (false);
11053 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11054 demand_empty_rest_of_line ();
11058 if (USE_GLOBAL_POINTER_OPT)
11060 seg = subseg_new (RDATA_SECTION_NAME,
11061 (subsegT) get_absolute_expression ());
11062 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11064 bfd_set_section_flags (stdoutput, seg,
11070 if (strcmp (TARGET_OS, "elf") != 0)
11071 record_alignment (seg, 4);
11073 demand_empty_rest_of_line ();
11077 as_bad (_("No read only data section in this object file format"));
11078 demand_empty_rest_of_line ();
11084 if (USE_GLOBAL_POINTER_OPT)
11086 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11087 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11089 bfd_set_section_flags (stdoutput, seg,
11090 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11092 if (strcmp (TARGET_OS, "elf") != 0)
11093 record_alignment (seg, 4);
11095 demand_empty_rest_of_line ();
11100 as_bad (_("Global pointers not supported; recompile -G 0"));
11101 demand_empty_rest_of_line ();
11110 mips_enable_auto_align ()
11121 label = insn_labels != NULL ? insn_labels->label : NULL;
11122 mips_emit_delays (false);
11123 if (log_size > 0 && auto_align)
11124 mips_align (log_size, 0, label);
11125 mips_clear_insn_labels ();
11126 cons (1 << log_size);
11130 s_float_cons (type)
11135 label = insn_labels != NULL ? insn_labels->label : NULL;
11137 mips_emit_delays (false);
11142 mips_align (3, 0, label);
11144 mips_align (2, 0, label);
11147 mips_clear_insn_labels ();
11152 /* Handle .globl. We need to override it because on Irix 5 you are
11155 where foo is an undefined symbol, to mean that foo should be
11156 considered to be the address of a function. */
11160 int x ATTRIBUTE_UNUSED;
11167 name = input_line_pointer;
11168 c = get_symbol_end ();
11169 symbolP = symbol_find_or_make (name);
11170 *input_line_pointer = c;
11171 SKIP_WHITESPACE ();
11173 /* On Irix 5, every global symbol that is not explicitly labelled as
11174 being a function is apparently labelled as being an object. */
11177 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11182 secname = input_line_pointer;
11183 c = get_symbol_end ();
11184 sec = bfd_get_section_by_name (stdoutput, secname);
11186 as_bad (_("%s: no such section"), secname);
11187 *input_line_pointer = c;
11189 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11190 flag = BSF_FUNCTION;
11193 symbol_get_bfdsym (symbolP)->flags |= flag;
11195 S_SET_EXTERNAL (symbolP);
11196 demand_empty_rest_of_line ();
11201 int x ATTRIBUTE_UNUSED;
11206 opt = input_line_pointer;
11207 c = get_symbol_end ();
11211 /* FIXME: What does this mean? */
11213 else if (strncmp (opt, "pic", 3) == 0)
11217 i = atoi (opt + 3);
11221 mips_pic = SVR4_PIC;
11223 as_bad (_(".option pic%d not supported"), i);
11225 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11227 if (g_switch_seen && g_switch_value != 0)
11228 as_warn (_("-G may not be used with SVR4 PIC code"));
11229 g_switch_value = 0;
11230 bfd_set_gp_size (stdoutput, 0);
11234 as_warn (_("Unrecognized option \"%s\""), opt);
11236 *input_line_pointer = c;
11237 demand_empty_rest_of_line ();
11240 /* This structure is used to hold a stack of .set values. */
11242 struct mips_option_stack
11244 struct mips_option_stack *next;
11245 struct mips_set_options options;
11248 static struct mips_option_stack *mips_opts_stack;
11250 /* Handle the .set pseudo-op. */
11254 int x ATTRIBUTE_UNUSED;
11256 char *name = input_line_pointer, ch;
11258 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11259 input_line_pointer++;
11260 ch = *input_line_pointer;
11261 *input_line_pointer = '\0';
11263 if (strcmp (name, "reorder") == 0)
11265 if (mips_opts.noreorder && prev_nop_frag != NULL)
11267 /* If we still have pending nops, we can discard them. The
11268 usual nop handling will insert any that are still
11270 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11271 * (mips_opts.mips16 ? 2 : 4));
11272 prev_nop_frag = NULL;
11274 mips_opts.noreorder = 0;
11276 else if (strcmp (name, "noreorder") == 0)
11278 mips_emit_delays (true);
11279 mips_opts.noreorder = 1;
11280 mips_any_noreorder = 1;
11282 else if (strcmp (name, "at") == 0)
11284 mips_opts.noat = 0;
11286 else if (strcmp (name, "noat") == 0)
11288 mips_opts.noat = 1;
11290 else if (strcmp (name, "macro") == 0)
11292 mips_opts.warn_about_macros = 0;
11294 else if (strcmp (name, "nomacro") == 0)
11296 if (mips_opts.noreorder == 0)
11297 as_bad (_("`noreorder' must be set before `nomacro'"));
11298 mips_opts.warn_about_macros = 1;
11300 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11302 mips_opts.nomove = 0;
11304 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11306 mips_opts.nomove = 1;
11308 else if (strcmp (name, "bopt") == 0)
11310 mips_opts.nobopt = 0;
11312 else if (strcmp (name, "nobopt") == 0)
11314 mips_opts.nobopt = 1;
11316 else if (strcmp (name, "mips16") == 0
11317 || strcmp (name, "MIPS-16") == 0)
11318 mips_opts.mips16 = 1;
11319 else if (strcmp (name, "nomips16") == 0
11320 || strcmp (name, "noMIPS-16") == 0)
11321 mips_opts.mips16 = 0;
11322 else if (strcmp (name, "mips3d") == 0)
11323 mips_opts.ase_mips3d = 1;
11324 else if (strcmp (name, "nomips3d") == 0)
11325 mips_opts.ase_mips3d = 0;
11326 else if (strncmp (name, "mips", 4) == 0)
11330 /* Permit the user to change the ISA on the fly. Needless to
11331 say, misuse can cause serious problems. */
11332 isa = atoi (name + 4);
11336 mips_opts.gp32 = file_mips_gp32;
11337 mips_opts.fp32 = file_mips_fp32;
11338 mips_opts.abi = file_mips_abi;
11343 mips_opts.gp32 = 1;
11344 mips_opts.fp32 = 1;
11350 /* Loosen ABI register width restriction. */
11351 if (mips_opts.abi == O32_ABI)
11352 mips_opts.abi = NO_ABI;
11353 mips_opts.gp32 = 0;
11354 mips_opts.fp32 = 0;
11357 as_bad (_("unknown ISA level %s"), name + 4);
11363 case 0: mips_opts.isa = file_mips_isa; break;
11364 case 1: mips_opts.isa = ISA_MIPS1; break;
11365 case 2: mips_opts.isa = ISA_MIPS2; break;
11366 case 3: mips_opts.isa = ISA_MIPS3; break;
11367 case 4: mips_opts.isa = ISA_MIPS4; break;
11368 case 5: mips_opts.isa = ISA_MIPS5; break;
11369 case 32: mips_opts.isa = ISA_MIPS32; break;
11370 case 64: mips_opts.isa = ISA_MIPS64; break;
11371 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11374 else if (strcmp (name, "autoextend") == 0)
11375 mips_opts.noautoextend = 0;
11376 else if (strcmp (name, "noautoextend") == 0)
11377 mips_opts.noautoextend = 1;
11378 else if (strcmp (name, "push") == 0)
11380 struct mips_option_stack *s;
11382 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11383 s->next = mips_opts_stack;
11384 s->options = mips_opts;
11385 mips_opts_stack = s;
11387 else if (strcmp (name, "pop") == 0)
11389 struct mips_option_stack *s;
11391 s = mips_opts_stack;
11393 as_bad (_(".set pop with no .set push"));
11396 /* If we're changing the reorder mode we need to handle
11397 delay slots correctly. */
11398 if (s->options.noreorder && ! mips_opts.noreorder)
11399 mips_emit_delays (true);
11400 else if (! s->options.noreorder && mips_opts.noreorder)
11402 if (prev_nop_frag != NULL)
11404 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11405 * (mips_opts.mips16 ? 2 : 4));
11406 prev_nop_frag = NULL;
11410 mips_opts = s->options;
11411 mips_opts_stack = s->next;
11417 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11419 *input_line_pointer = ch;
11420 demand_empty_rest_of_line ();
11423 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11424 .option pic2. It means to generate SVR4 PIC calls. */
11427 s_abicalls (ignore)
11428 int ignore ATTRIBUTE_UNUSED;
11430 mips_pic = SVR4_PIC;
11431 if (USE_GLOBAL_POINTER_OPT)
11433 if (g_switch_seen && g_switch_value != 0)
11434 as_warn (_("-G may not be used with SVR4 PIC code"));
11435 g_switch_value = 0;
11437 bfd_set_gp_size (stdoutput, 0);
11438 demand_empty_rest_of_line ();
11441 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11442 PIC code. It sets the $gp register for the function based on the
11443 function address, which is in the register named in the argument.
11444 This uses a relocation against _gp_disp, which is handled specially
11445 by the linker. The result is:
11446 lui $gp,%hi(_gp_disp)
11447 addiu $gp,$gp,%lo(_gp_disp)
11448 addu $gp,$gp,.cpload argument
11449 The .cpload argument is normally $25 == $t9. */
11453 int ignore ATTRIBUTE_UNUSED;
11458 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11459 .cpload is ignored. */
11460 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11466 /* .cpload should be in a .set noreorder section. */
11467 if (mips_opts.noreorder == 0)
11468 as_warn (_(".cpload not in noreorder section"));
11470 ex.X_op = O_symbol;
11471 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11472 ex.X_op_symbol = NULL;
11473 ex.X_add_number = 0;
11475 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11476 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11478 macro_build_lui (NULL, &icnt, &ex, GP);
11479 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP,
11480 (int) BFD_RELOC_LO16);
11482 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11483 GP, GP, tc_get_register (0));
11485 demand_empty_rest_of_line ();
11488 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11489 .cpsetup $reg1, offset|$reg2, label
11491 If offset is given, this results in:
11492 sd $gp, offset($sp)
11493 lui $gp, %hi(%neg(%gp_rel(label)))
11494 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11495 addu $gp, $gp, $reg1
11497 If $reg2 is given, this results in:
11498 daddu $reg2, $gp, $0
11499 lui $gp, %hi(%neg(%gp_rel(label)))
11500 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11501 addu $gp, $gp, $reg1
11505 int ignore ATTRIBUTE_UNUSED;
11507 expressionS ex_off;
11508 expressionS ex_sym;
11513 /* If we are not generating SVR4 PIC code, .cpload is ignored.
11514 We also need NewABI support. */
11515 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11521 reg1 = tc_get_register (0);
11522 SKIP_WHITESPACE ();
11523 if (*input_line_pointer != ',')
11525 as_bad (_("missing argument separator ',' for .cpsetup"));
11529 input_line_pointer++;
11530 SKIP_WHITESPACE ();
11531 if (*input_line_pointer == '$')
11532 mips_cpreturn_register = tc_get_register (0);
11534 mips_cpreturn_offset = get_absolute_expression ();
11535 SKIP_WHITESPACE ();
11536 if (*input_line_pointer != ',')
11538 as_bad (_("missing argument separator ',' for .cpsetup"));
11542 input_line_pointer++;
11543 SKIP_WHITESPACE ();
11544 sym = input_line_pointer;
11545 while (ISALNUM (*input_line_pointer))
11546 input_line_pointer++;
11547 *input_line_pointer = 0;
11549 ex_sym.X_op = O_symbol;
11550 ex_sym.X_add_symbol = symbol_find_or_make (sym);
11551 ex_sym.X_op_symbol = NULL;
11552 ex_sym.X_add_number = 0;
11554 if (mips_cpreturn_register == -1)
11556 ex_off.X_op = O_constant;
11557 ex_off.X_add_symbol = NULL;
11558 ex_off.X_op_symbol = NULL;
11559 ex_off.X_add_number = mips_cpreturn_offset;
11561 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11562 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11565 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11566 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11568 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11569 (int) BFD_RELOC_GPREL16);
11570 fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0,
11571 NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11572 fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0,
11573 NULL, 0, 0, BFD_RELOC_HI16_S);
11574 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11575 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11576 fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0,
11577 NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11578 fix_new (frag_now, (char *) prev_insn_fixp - 4 - frag_now->fr_literal, 0,
11579 NULL, 0, 0, BFD_RELOC_LO16);
11580 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11581 "d,v,t", mips_gp_register, mips_gp_register, reg1);
11583 demand_empty_rest_of_line ();
11588 int ignore ATTRIBUTE_UNUSED;
11590 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11591 .cplocal is ignored. */
11592 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11598 mips_gp_register = tc_get_register (0);
11601 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11602 offset from $sp. The offset is remembered, and after making a PIC
11603 call $gp is restored from that location. */
11606 s_cprestore (ignore)
11607 int ignore ATTRIBUTE_UNUSED;
11612 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11613 .cprestore is ignored. */
11614 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11620 mips_cprestore_offset = get_absolute_expression ();
11621 mips_cprestore_valid = 1;
11623 ex.X_op = O_constant;
11624 ex.X_add_symbol = NULL;
11625 ex.X_op_symbol = NULL;
11626 ex.X_add_number = mips_cprestore_offset;
11628 macro_build ((char *) NULL, &icnt, &ex,
11629 HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11630 "t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
11632 demand_empty_rest_of_line ();
11635 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11636 was given in the preceeding .gpsetup, it results in:
11637 ld $gp, offset($sp)
11639 If a register $reg2 was given there, it results in:
11640 daddiu $gp, $gp, $reg2
11643 s_cpreturn (ignore)
11644 int ignore ATTRIBUTE_UNUSED;
11649 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11650 We also need NewABI support. */
11651 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11657 if (mips_cpreturn_register == -1)
11659 ex.X_op = O_constant;
11660 ex.X_add_symbol = NULL;
11661 ex.X_op_symbol = NULL;
11662 ex.X_add_number = mips_cpreturn_offset;
11664 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
11665 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11668 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11669 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
11671 demand_empty_rest_of_line ();
11674 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11675 code. It sets the offset to use in gp_rel relocations. */
11679 int ignore ATTRIBUTE_UNUSED;
11681 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11682 We also need NewABI support. */
11683 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11689 mips_cpreturn_offset = get_absolute_expression ();
11691 demand_empty_rest_of_line ();
11694 /* Handle the .gpword pseudo-op. This is used when generating PIC
11695 code. It generates a 32 bit GP relative reloc. */
11699 int ignore ATTRIBUTE_UNUSED;
11705 /* When not generating PIC code, this is treated as .word. */
11706 if (mips_pic != SVR4_PIC)
11712 label = insn_labels != NULL ? insn_labels->label : NULL;
11713 mips_emit_delays (true);
11715 mips_align (2, 0, label);
11716 mips_clear_insn_labels ();
11720 if (ex.X_op != O_symbol || ex.X_add_number != 0)
11722 as_bad (_("Unsupported use of .gpword"));
11723 ignore_rest_of_line ();
11727 md_number_to_chars (p, (valueT) 0, 4);
11728 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0,
11729 BFD_RELOC_GPREL32);
11731 demand_empty_rest_of_line ();
11734 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11735 tables in SVR4 PIC code. */
11739 int ignore ATTRIBUTE_UNUSED;
11744 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11746 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11752 /* Add $gp to the register named as an argument. */
11753 reg = tc_get_register (0);
11754 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11755 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
11756 "d,v,t", reg, reg, GP);
11758 demand_empty_rest_of_line ();
11761 /* Handle the .insn pseudo-op. This marks instruction labels in
11762 mips16 mode. This permits the linker to handle them specially,
11763 such as generating jalx instructions when needed. We also make
11764 them odd for the duration of the assembly, in order to generate the
11765 right sort of code. We will make them even in the adjust_symtab
11766 routine, while leaving them marked. This is convenient for the
11767 debugger and the disassembler. The linker knows to make them odd
11772 int ignore ATTRIBUTE_UNUSED;
11774 if (mips_opts.mips16)
11775 mips16_mark_labels ();
11777 demand_empty_rest_of_line ();
11780 /* Handle a .stabn directive. We need these in order to mark a label
11781 as being a mips16 text label correctly. Sometimes the compiler
11782 will emit a label, followed by a .stabn, and then switch sections.
11783 If the label and .stabn are in mips16 mode, then the label is
11784 really a mips16 text label. */
11790 if (type == 'n' && mips_opts.mips16)
11791 mips16_mark_labels ();
11796 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11800 s_mips_weakext (ignore)
11801 int ignore ATTRIBUTE_UNUSED;
11808 name = input_line_pointer;
11809 c = get_symbol_end ();
11810 symbolP = symbol_find_or_make (name);
11811 S_SET_WEAK (symbolP);
11812 *input_line_pointer = c;
11814 SKIP_WHITESPACE ();
11816 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11818 if (S_IS_DEFINED (symbolP))
11820 as_bad ("ignoring attempt to redefine symbol %s",
11821 S_GET_NAME (symbolP));
11822 ignore_rest_of_line ();
11826 if (*input_line_pointer == ',')
11828 ++input_line_pointer;
11829 SKIP_WHITESPACE ();
11833 if (exp.X_op != O_symbol)
11835 as_bad ("bad .weakext directive");
11836 ignore_rest_of_line ();
11839 symbol_set_value_expression (symbolP, &exp);
11842 demand_empty_rest_of_line ();
11845 /* Parse a register string into a number. Called from the ECOFF code
11846 to parse .frame. The argument is non-zero if this is the frame
11847 register, so that we can record it in mips_frame_reg. */
11850 tc_get_register (frame)
11855 SKIP_WHITESPACE ();
11856 if (*input_line_pointer++ != '$')
11858 as_warn (_("expected `$'"));
11861 else if (ISDIGIT (*input_line_pointer))
11863 reg = get_absolute_expression ();
11864 if (reg < 0 || reg >= 32)
11866 as_warn (_("Bad register number"));
11872 if (strncmp (input_line_pointer, "fp", 2) == 0)
11874 else if (strncmp (input_line_pointer, "sp", 2) == 0)
11876 else if (strncmp (input_line_pointer, "gp", 2) == 0)
11878 else if (strncmp (input_line_pointer, "at", 2) == 0)
11882 as_warn (_("Unrecognized register name"));
11885 input_line_pointer += 2;
11889 mips_frame_reg = reg != 0 ? reg : SP;
11890 mips_frame_reg_valid = 1;
11891 mips_cprestore_valid = 0;
11897 md_section_align (seg, addr)
11901 int align = bfd_get_section_alignment (stdoutput, seg);
11904 /* We don't need to align ELF sections to the full alignment.
11905 However, Irix 5 may prefer that we align them at least to a 16
11906 byte boundary. We don't bother to align the sections if we are
11907 targeted for an embedded system. */
11908 if (strcmp (TARGET_OS, "elf") == 0)
11914 return ((addr + (1 << align) - 1) & (-1 << align));
11917 /* Utility routine, called from above as well. If called while the
11918 input file is still being read, it's only an approximation. (For
11919 example, a symbol may later become defined which appeared to be
11920 undefined earlier.) */
11923 nopic_need_relax (sym, before_relaxing)
11925 int before_relaxing;
11930 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
11932 const char *symname;
11935 /* Find out whether this symbol can be referenced off the GP
11936 register. It can be if it is smaller than the -G size or if
11937 it is in the .sdata or .sbss section. Certain symbols can
11938 not be referenced off the GP, although it appears as though
11940 symname = S_GET_NAME (sym);
11941 if (symname != (const char *) NULL
11942 && (strcmp (symname, "eprol") == 0
11943 || strcmp (symname, "etext") == 0
11944 || strcmp (symname, "_gp") == 0
11945 || strcmp (symname, "edata") == 0
11946 || strcmp (symname, "_fbss") == 0
11947 || strcmp (symname, "_fdata") == 0
11948 || strcmp (symname, "_ftext") == 0
11949 || strcmp (symname, "end") == 0
11950 || strcmp (symname, "_gp_disp") == 0))
11952 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
11954 #ifndef NO_ECOFF_DEBUGGING
11955 || (symbol_get_obj (sym)->ecoff_extern_size != 0
11956 && (symbol_get_obj (sym)->ecoff_extern_size
11957 <= g_switch_value))
11959 /* We must defer this decision until after the whole
11960 file has been read, since there might be a .extern
11961 after the first use of this symbol. */
11962 || (before_relaxing
11963 #ifndef NO_ECOFF_DEBUGGING
11964 && symbol_get_obj (sym)->ecoff_extern_size == 0
11966 && S_GET_VALUE (sym) == 0)
11967 || (S_GET_VALUE (sym) != 0
11968 && S_GET_VALUE (sym) <= g_switch_value)))
11972 const char *segname;
11974 segname = segment_name (S_GET_SEGMENT (sym));
11975 assert (strcmp (segname, ".lit8") != 0
11976 && strcmp (segname, ".lit4") != 0);
11977 change = (strcmp (segname, ".sdata") != 0
11978 && strcmp (segname, ".sbss") != 0
11979 && strncmp (segname, ".sdata.", 7) != 0
11980 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
11985 /* We are not optimizing for the GP register. */
11989 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11990 extended opcode. SEC is the section the frag is in. */
11993 mips16_extended_frag (fragp, sec, stretch)
11999 register const struct mips16_immed_operand *op;
12001 int mintiny, maxtiny;
12005 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12007 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12010 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12011 op = mips16_immed_operands;
12012 while (op->type != type)
12015 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12020 if (type == '<' || type == '>' || type == '[' || type == ']')
12023 maxtiny = 1 << op->nbits;
12028 maxtiny = (1 << op->nbits) - 1;
12033 mintiny = - (1 << (op->nbits - 1));
12034 maxtiny = (1 << (op->nbits - 1)) - 1;
12037 sym_frag = symbol_get_frag (fragp->fr_symbol);
12038 val = S_GET_VALUE (fragp->fr_symbol);
12039 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12045 /* We won't have the section when we are called from
12046 mips_relax_frag. However, we will always have been called
12047 from md_estimate_size_before_relax first. If this is a
12048 branch to a different section, we mark it as such. If SEC is
12049 NULL, and the frag is not marked, then it must be a branch to
12050 the same section. */
12053 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12058 /* Must have been called from md_estimate_size_before_relax. */
12061 fragp->fr_subtype =
12062 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12064 /* FIXME: We should support this, and let the linker
12065 catch branches and loads that are out of range. */
12066 as_bad_where (fragp->fr_file, fragp->fr_line,
12067 _("unsupported PC relative reference to different section"));
12071 if (fragp != sym_frag && sym_frag->fr_address == 0)
12072 /* Assume non-extended on the first relaxation pass.
12073 The address we have calculated will be bogus if this is
12074 a forward branch to another frag, as the forward frag
12075 will have fr_address == 0. */
12079 /* In this case, we know for sure that the symbol fragment is in
12080 the same section. If the relax_marker of the symbol fragment
12081 differs from the relax_marker of this fragment, we have not
12082 yet adjusted the symbol fragment fr_address. We want to add
12083 in STRETCH in order to get a better estimate of the address.
12084 This particularly matters because of the shift bits. */
12086 && sym_frag->relax_marker != fragp->relax_marker)
12090 /* Adjust stretch for any alignment frag. Note that if have
12091 been expanding the earlier code, the symbol may be
12092 defined in what appears to be an earlier frag. FIXME:
12093 This doesn't handle the fr_subtype field, which specifies
12094 a maximum number of bytes to skip when doing an
12096 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12098 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12101 stretch = - ((- stretch)
12102 & ~ ((1 << (int) f->fr_offset) - 1));
12104 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12113 addr = fragp->fr_address + fragp->fr_fix;
12115 /* The base address rules are complicated. The base address of
12116 a branch is the following instruction. The base address of a
12117 PC relative load or add is the instruction itself, but if it
12118 is in a delay slot (in which case it can not be extended) use
12119 the address of the instruction whose delay slot it is in. */
12120 if (type == 'p' || type == 'q')
12124 /* If we are currently assuming that this frag should be
12125 extended, then, the current address is two bytes
12127 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12130 /* Ignore the low bit in the target, since it will be set
12131 for a text label. */
12132 if ((val & 1) != 0)
12135 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12137 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12140 val -= addr & ~ ((1 << op->shift) - 1);
12142 /* Branch offsets have an implicit 0 in the lowest bit. */
12143 if (type == 'p' || type == 'q')
12146 /* If any of the shifted bits are set, we must use an extended
12147 opcode. If the address depends on the size of this
12148 instruction, this can lead to a loop, so we arrange to always
12149 use an extended opcode. We only check this when we are in
12150 the main relaxation loop, when SEC is NULL. */
12151 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12153 fragp->fr_subtype =
12154 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12158 /* If we are about to mark a frag as extended because the value
12159 is precisely maxtiny + 1, then there is a chance of an
12160 infinite loop as in the following code:
12165 In this case when the la is extended, foo is 0x3fc bytes
12166 away, so the la can be shrunk, but then foo is 0x400 away, so
12167 the la must be extended. To avoid this loop, we mark the
12168 frag as extended if it was small, and is about to become
12169 extended with a value of maxtiny + 1. */
12170 if (val == ((maxtiny + 1) << op->shift)
12171 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12174 fragp->fr_subtype =
12175 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12179 else if (symsec != absolute_section && sec != NULL)
12180 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12182 if ((val & ((1 << op->shift) - 1)) != 0
12183 || val < (mintiny << op->shift)
12184 || val > (maxtiny << op->shift))
12190 /* Estimate the size of a frag before relaxing. Unless this is the
12191 mips16, we are not really relaxing here, and the final size is
12192 encoded in the subtype information. For the mips16, we have to
12193 decide whether we are using an extended opcode or not. */
12196 md_estimate_size_before_relax (fragp, segtype)
12201 boolean linkonce = false;
12203 if (RELAX_MIPS16_P (fragp->fr_subtype))
12204 /* We don't want to modify the EXTENDED bit here; it might get us
12205 into infinite loops. We change it only in mips_relax_frag(). */
12206 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12208 if (mips_pic == NO_PIC)
12210 change = nopic_need_relax (fragp->fr_symbol, 0);
12212 else if (mips_pic == SVR4_PIC)
12217 sym = fragp->fr_symbol;
12219 /* Handle the case of a symbol equated to another symbol. */
12220 while (symbol_equated_reloc_p (sym))
12224 /* It's possible to get a loop here in a badly written
12226 n = symbol_get_value_expression (sym)->X_add_symbol;
12232 symsec = S_GET_SEGMENT (sym);
12234 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12235 if (symsec != segtype && ! S_IS_LOCAL (sym))
12237 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12241 /* The GNU toolchain uses an extension for ELF: a section
12242 beginning with the magic string .gnu.linkonce is a linkonce
12244 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12245 sizeof ".gnu.linkonce" - 1) == 0)
12249 /* This must duplicate the test in adjust_reloc_syms. */
12250 change = (symsec != &bfd_und_section
12251 && symsec != &bfd_abs_section
12252 && ! bfd_is_com_section (symsec)
12255 /* A global or weak symbol is treated as external. */
12256 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12257 || (! S_IS_WEAK (sym)
12258 && (! S_IS_EXTERN (sym) || mips_pic == EMBEDDED_PIC)))
12267 /* Record the offset to the first reloc in the fr_opcode field.
12268 This lets md_convert_frag and tc_gen_reloc know that the code
12269 must be expanded. */
12270 fragp->fr_opcode = (fragp->fr_literal
12272 - RELAX_OLD (fragp->fr_subtype)
12273 + RELAX_RELOC1 (fragp->fr_subtype));
12274 /* FIXME: This really needs as_warn_where. */
12275 if (RELAX_WARN (fragp->fr_subtype))
12276 as_warn (_("AT used after \".set noat\" or macro used after "
12277 "\".set nomacro\""));
12279 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12285 /* This is called to see whether a reloc against a defined symbol
12286 should be converted into a reloc against a section. Don't adjust
12287 MIPS16 jump relocations, so we don't have to worry about the format
12288 of the offset in the .o file. Don't adjust relocations against
12289 mips16 symbols, so that the linker can find them if it needs to set
12293 mips_fix_adjustable (fixp)
12297 /* Prevent all adjustments to global symbols. */
12298 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12299 && mips_pic != EMBEDDED_PIC
12300 && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)))
12303 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12305 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12306 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12308 if (fixp->fx_addsy == NULL)
12311 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12312 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12313 && fixp->fx_subsy == NULL)
12319 /* Translate internal representation of relocation info to BFD target
12323 tc_gen_reloc (section, fixp)
12324 asection *section ATTRIBUTE_UNUSED;
12327 static arelent *retval[4];
12329 bfd_reloc_code_real_type code;
12331 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12334 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12335 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12336 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12338 if (mips_pic == EMBEDDED_PIC
12339 && SWITCH_TABLE (fixp))
12341 /* For a switch table entry we use a special reloc. The addend
12342 is actually the difference between the reloc address and the
12344 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12345 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12346 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12347 fixp->fx_r_type = BFD_RELOC_GPREL32;
12349 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12351 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12352 reloc->addend = fixp->fx_addnumber;
12355 /* We use a special addend for an internal RELLO reloc. */
12356 if (symbol_section_p (fixp->fx_addsy))
12357 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12359 reloc->addend = fixp->fx_addnumber + reloc->address;
12362 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12364 assert (fixp->fx_next != NULL
12365 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12367 /* The reloc is relative to the RELLO; adjust the addend
12369 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12370 reloc->addend = fixp->fx_next->fx_addnumber;
12373 /* We use a special addend for an internal RELHI reloc. */
12374 if (symbol_section_p (fixp->fx_addsy))
12375 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12376 + fixp->fx_next->fx_where
12377 - S_GET_VALUE (fixp->fx_subsy));
12379 reloc->addend = (fixp->fx_addnumber
12380 + fixp->fx_next->fx_frag->fr_address
12381 + fixp->fx_next->fx_where);
12384 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12385 reloc->addend = fixp->fx_addnumber;
12388 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12389 /* A gruesome hack which is a result of the gruesome gas reloc
12391 reloc->addend = reloc->address;
12393 reloc->addend = -reloc->address;
12396 /* If this is a variant frag, we may need to adjust the existing
12397 reloc and generate a new one. */
12398 if (fixp->fx_frag->fr_opcode != NULL
12399 && (fixp->fx_r_type == BFD_RELOC_GPREL16
12400 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12401 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12402 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12403 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12404 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12405 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12410 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12412 /* If this is not the last reloc in this frag, then we have two
12413 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12414 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12415 the second one handle all of them. */
12416 if (fixp->fx_next != NULL
12417 && fixp->fx_frag == fixp->fx_next->fx_frag)
12419 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12420 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12421 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12422 && (fixp->fx_next->fx_r_type
12423 == BFD_RELOC_MIPS_GOT_LO16))
12424 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12425 && (fixp->fx_next->fx_r_type
12426 == BFD_RELOC_MIPS_CALL_LO16)));
12431 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12432 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12433 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12435 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12436 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12437 reloc2->address = (reloc->address
12438 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12439 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12440 reloc2->addend = fixp->fx_addnumber;
12441 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12442 assert (reloc2->howto != NULL);
12444 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12448 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12451 reloc3->address += 4;
12454 if (mips_pic == NO_PIC)
12456 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12457 fixp->fx_r_type = BFD_RELOC_HI16_S;
12459 else if (mips_pic == SVR4_PIC)
12461 switch (fixp->fx_r_type)
12465 case BFD_RELOC_MIPS_GOT16:
12467 case BFD_RELOC_MIPS_CALL16:
12468 case BFD_RELOC_MIPS_GOT_LO16:
12469 case BFD_RELOC_MIPS_CALL_LO16:
12470 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12478 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12479 to be used in the relocation's section offset. */
12480 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12482 reloc->address = reloc->addend;
12486 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12487 fixup_segment converted a non-PC relative reloc into a PC
12488 relative reloc. In such a case, we need to convert the reloc
12490 code = fixp->fx_r_type;
12491 if (fixp->fx_pcrel)
12496 code = BFD_RELOC_8_PCREL;
12499 code = BFD_RELOC_16_PCREL;
12502 code = BFD_RELOC_32_PCREL;
12505 code = BFD_RELOC_64_PCREL;
12507 case BFD_RELOC_8_PCREL:
12508 case BFD_RELOC_16_PCREL:
12509 case BFD_RELOC_32_PCREL:
12510 case BFD_RELOC_64_PCREL:
12511 case BFD_RELOC_16_PCREL_S2:
12512 case BFD_RELOC_PCREL_HI16_S:
12513 case BFD_RELOC_PCREL_LO16:
12516 as_bad_where (fixp->fx_file, fixp->fx_line,
12517 _("Cannot make %s relocation PC relative"),
12518 bfd_get_reloc_code_name (code));
12523 /* md_apply_fix3 has a double-subtraction hack to get
12524 bfd_install_relocation to behave nicely. GPREL relocations are
12525 handled correctly without this hack, so undo it here. We can't
12526 stop md_apply_fix3 from subtracting twice in the first place since
12527 the fake addend is required for variant frags above. */
12528 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12529 && code == BFD_RELOC_GPREL16
12530 && reloc->addend != 0
12531 && mips_need_elf_addend_fixup (fixp))
12532 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12535 /* To support a PC relative reloc when generating embedded PIC code
12536 for ECOFF, we use a Cygnus extension. We check for that here to
12537 make sure that we don't let such a reloc escape normally. */
12538 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12539 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12540 && code == BFD_RELOC_16_PCREL_S2
12541 && mips_pic != EMBEDDED_PIC)
12542 reloc->howto = NULL;
12544 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12546 if (reloc->howto == NULL)
12548 as_bad_where (fixp->fx_file, fixp->fx_line,
12549 _("Can not represent %s relocation in this object file format"),
12550 bfd_get_reloc_code_name (code));
12557 /* Relax a machine dependent frag. This returns the amount by which
12558 the current size of the frag should change. */
12561 mips_relax_frag (fragp, stretch)
12565 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12568 if (mips16_extended_frag (fragp, NULL, stretch))
12570 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12572 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12577 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12579 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12586 /* Convert a machine dependent frag. */
12589 md_convert_frag (abfd, asec, fragp)
12590 bfd *abfd ATTRIBUTE_UNUSED;
12597 if (RELAX_MIPS16_P (fragp->fr_subtype))
12600 register const struct mips16_immed_operand *op;
12601 boolean small, ext;
12604 unsigned long insn;
12605 boolean use_extend;
12606 unsigned short extend;
12608 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12609 op = mips16_immed_operands;
12610 while (op->type != type)
12613 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12624 resolve_symbol_value (fragp->fr_symbol);
12625 val = S_GET_VALUE (fragp->fr_symbol);
12630 addr = fragp->fr_address + fragp->fr_fix;
12632 /* The rules for the base address of a PC relative reloc are
12633 complicated; see mips16_extended_frag. */
12634 if (type == 'p' || type == 'q')
12639 /* Ignore the low bit in the target, since it will be
12640 set for a text label. */
12641 if ((val & 1) != 0)
12644 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12646 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12649 addr &= ~ (addressT) ((1 << op->shift) - 1);
12652 /* Make sure the section winds up with the alignment we have
12655 record_alignment (asec, op->shift);
12659 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
12660 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
12661 as_warn_where (fragp->fr_file, fragp->fr_line,
12662 _("extended instruction in delay slot"));
12664 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
12666 if (target_big_endian)
12667 insn = bfd_getb16 (buf);
12669 insn = bfd_getl16 (buf);
12671 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
12672 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
12673 small, ext, &insn, &use_extend, &extend);
12677 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
12678 fragp->fr_fix += 2;
12682 md_number_to_chars ((char *) buf, insn, 2);
12683 fragp->fr_fix += 2;
12688 if (fragp->fr_opcode == NULL)
12691 old = RELAX_OLD (fragp->fr_subtype);
12692 new = RELAX_NEW (fragp->fr_subtype);
12693 fixptr = fragp->fr_literal + fragp->fr_fix;
12696 memcpy (fixptr - old, fixptr, new);
12698 fragp->fr_fix += new - old;
12704 /* This function is called after the relocs have been generated.
12705 We've been storing mips16 text labels as odd. Here we convert them
12706 back to even for the convenience of the debugger. */
12709 mips_frob_file_after_relocs ()
12712 unsigned int count, i;
12714 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
12717 syms = bfd_get_outsymbols (stdoutput);
12718 count = bfd_get_symcount (stdoutput);
12719 for (i = 0; i < count; i++, syms++)
12721 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
12722 && ((*syms)->value & 1) != 0)
12724 (*syms)->value &= ~1;
12725 /* If the symbol has an odd size, it was probably computed
12726 incorrectly, so adjust that as well. */
12727 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
12728 ++elf_symbol (*syms)->internal_elf_sym.st_size;
12735 /* This function is called whenever a label is defined. It is used
12736 when handling branch delays; if a branch has a label, we assume we
12737 can not move it. */
12740 mips_define_label (sym)
12743 struct insn_label_list *l;
12745 if (free_insn_labels == NULL)
12746 l = (struct insn_label_list *) xmalloc (sizeof *l);
12749 l = free_insn_labels;
12750 free_insn_labels = l->next;
12754 l->next = insn_labels;
12758 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12760 /* Some special processing for a MIPS ELF file. */
12763 mips_elf_final_processing ()
12765 /* Write out the register information. */
12766 if (file_mips_abi != N64_ABI)
12770 s.ri_gprmask = mips_gprmask;
12771 s.ri_cprmask[0] = mips_cprmask[0];
12772 s.ri_cprmask[1] = mips_cprmask[1];
12773 s.ri_cprmask[2] = mips_cprmask[2];
12774 s.ri_cprmask[3] = mips_cprmask[3];
12775 /* The gp_value field is set by the MIPS ELF backend. */
12777 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
12778 ((Elf32_External_RegInfo *)
12779 mips_regmask_frag));
12783 Elf64_Internal_RegInfo s;
12785 s.ri_gprmask = mips_gprmask;
12787 s.ri_cprmask[0] = mips_cprmask[0];
12788 s.ri_cprmask[1] = mips_cprmask[1];
12789 s.ri_cprmask[2] = mips_cprmask[2];
12790 s.ri_cprmask[3] = mips_cprmask[3];
12791 /* The gp_value field is set by the MIPS ELF backend. */
12793 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
12794 ((Elf64_External_RegInfo *)
12795 mips_regmask_frag));
12798 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12799 sort of BFD interface for this. */
12800 if (mips_any_noreorder)
12801 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
12802 if (mips_pic != NO_PIC)
12803 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
12805 /* Set MIPS ELF flags for ASEs. */
12806 #if 0 /* XXX FIXME */
12807 if (file_ase_mips3d)
12808 elf_elfheader (stdoutput)->e_flags |= ???;
12811 /* Set the MIPS ELF ABI flags. */
12812 if (file_mips_abi == NO_ABI)
12814 else if (file_mips_abi == O32_ABI)
12815 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
12816 else if (file_mips_abi == O64_ABI)
12817 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
12818 else if (file_mips_abi == EABI_ABI)
12821 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
12823 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
12825 else if (file_mips_abi == N32_ABI)
12826 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
12828 /* Nothing to do for "64". */
12830 if (mips_32bitmode)
12831 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
12834 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12836 typedef struct proc {
12838 unsigned long reg_mask;
12839 unsigned long reg_offset;
12840 unsigned long fpreg_mask;
12841 unsigned long fpreg_offset;
12842 unsigned long frame_offset;
12843 unsigned long frame_reg;
12844 unsigned long pc_reg;
12847 static procS cur_proc;
12848 static procS *cur_proc_ptr;
12849 static int numprocs;
12851 /* Fill in an rs_align_code fragment. */
12854 mips_handle_align (fragp)
12857 if (fragp->fr_type != rs_align_code)
12860 if (mips_opts.mips16)
12862 static const unsigned char be_nop[] = { 0x65, 0x00 };
12863 static const unsigned char le_nop[] = { 0x00, 0x65 };
12868 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
12869 p = fragp->fr_literal + fragp->fr_fix;
12874 fragp->fr_fix += 1;
12877 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
12881 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12892 /* check for premature end, nesting errors, etc */
12894 as_warn (_("missing .end at end of assembly"));
12903 if (*input_line_pointer == '-')
12905 ++input_line_pointer;
12908 if (!ISDIGIT (*input_line_pointer))
12909 as_bad (_("expected simple number"));
12910 if (input_line_pointer[0] == '0')
12912 if (input_line_pointer[1] == 'x')
12914 input_line_pointer += 2;
12915 while (ISXDIGIT (*input_line_pointer))
12918 val |= hex_value (*input_line_pointer++);
12920 return negative ? -val : val;
12924 ++input_line_pointer;
12925 while (ISDIGIT (*input_line_pointer))
12928 val |= *input_line_pointer++ - '0';
12930 return negative ? -val : val;
12933 if (!ISDIGIT (*input_line_pointer))
12935 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12936 *input_line_pointer, *input_line_pointer);
12937 as_warn (_("invalid number"));
12940 while (ISDIGIT (*input_line_pointer))
12943 val += *input_line_pointer++ - '0';
12945 return negative ? -val : val;
12948 /* The .file directive; just like the usual .file directive, but there
12949 is an initial number which is the ECOFF file index. */
12953 int x ATTRIBUTE_UNUSED;
12959 /* The .end directive. */
12963 int x ATTRIBUTE_UNUSED;
12968 /* Following functions need their own .frame and .cprestore directives. */
12969 mips_frame_reg_valid = 0;
12970 mips_cprestore_valid = 0;
12972 if (!is_end_of_line[(unsigned char) *input_line_pointer])
12975 demand_empty_rest_of_line ();
12980 #ifdef BFD_ASSEMBLER
12981 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
12986 if (now_seg != data_section && now_seg != bss_section)
12993 as_warn (_(".end not in text section"));
12997 as_warn (_(".end directive without a preceding .ent directive."));
12998 demand_empty_rest_of_line ();
13004 assert (S_GET_NAME (p));
13005 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13006 as_warn (_(".end symbol does not match .ent symbol."));
13009 as_warn (_(".end directive missing or unknown symbol"));
13011 #ifdef MIPS_STABS_ELF
13013 segT saved_seg = now_seg;
13014 subsegT saved_subseg = now_subseg;
13019 dot = frag_now_fix ();
13021 #ifdef md_flush_pending_output
13022 md_flush_pending_output ();
13026 subseg_set (pdr_seg, 0);
13028 /* Write the symbol. */
13029 exp.X_op = O_symbol;
13030 exp.X_add_symbol = p;
13031 exp.X_add_number = 0;
13032 emit_expr (&exp, 4);
13034 fragp = frag_more (7 * 4);
13036 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13037 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13038 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13039 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13040 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13041 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13042 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13044 subseg_set (saved_seg, saved_subseg);
13048 cur_proc_ptr = NULL;
13051 /* The .aent and .ent directives. */
13060 symbolP = get_symbol ();
13061 if (*input_line_pointer == ',')
13062 input_line_pointer++;
13063 SKIP_WHITESPACE ();
13064 if (ISDIGIT (*input_line_pointer)
13065 || *input_line_pointer == '-')
13068 #ifdef BFD_ASSEMBLER
13069 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13074 if (now_seg != data_section && now_seg != bss_section)
13081 as_warn (_(".ent or .aent not in text section."));
13083 if (!aent && cur_proc_ptr)
13084 as_warn (_("missing .end"));
13088 /* This function needs its own .frame and .cprestore directives. */
13089 mips_frame_reg_valid = 0;
13090 mips_cprestore_valid = 0;
13092 cur_proc_ptr = &cur_proc;
13093 memset (cur_proc_ptr, '\0', sizeof (procS));
13095 cur_proc_ptr->isym = symbolP;
13097 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13102 demand_empty_rest_of_line ();
13105 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13106 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13107 s_mips_frame is used so that we can set the PDR information correctly.
13108 We can't use the ecoff routines because they make reference to the ecoff
13109 symbol table (in the mdebug section). */
13112 s_mips_frame (ignore)
13113 int ignore ATTRIBUTE_UNUSED;
13115 #ifdef MIPS_STABS_ELF
13119 if (cur_proc_ptr == (procS *) NULL)
13121 as_warn (_(".frame outside of .ent"));
13122 demand_empty_rest_of_line ();
13126 cur_proc_ptr->frame_reg = tc_get_register (1);
13128 SKIP_WHITESPACE ();
13129 if (*input_line_pointer++ != ','
13130 || get_absolute_expression_and_terminator (&val) != ',')
13132 as_warn (_("Bad .frame directive"));
13133 --input_line_pointer;
13134 demand_empty_rest_of_line ();
13138 cur_proc_ptr->frame_offset = val;
13139 cur_proc_ptr->pc_reg = tc_get_register (0);
13141 demand_empty_rest_of_line ();
13144 #endif /* MIPS_STABS_ELF */
13147 /* The .fmask and .mask directives. If the mdebug section is present
13148 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13149 embedded targets, s_mips_mask is used so that we can set the PDR
13150 information correctly. We can't use the ecoff routines because they
13151 make reference to the ecoff symbol table (in the mdebug section). */
13154 s_mips_mask (reg_type)
13157 #ifdef MIPS_STABS_ELF
13160 if (cur_proc_ptr == (procS *) NULL)
13162 as_warn (_(".mask/.fmask outside of .ent"));
13163 demand_empty_rest_of_line ();
13167 if (get_absolute_expression_and_terminator (&mask) != ',')
13169 as_warn (_("Bad .mask/.fmask directive"));
13170 --input_line_pointer;
13171 demand_empty_rest_of_line ();
13175 off = get_absolute_expression ();
13177 if (reg_type == 'F')
13179 cur_proc_ptr->fpreg_mask = mask;
13180 cur_proc_ptr->fpreg_offset = off;
13184 cur_proc_ptr->reg_mask = mask;
13185 cur_proc_ptr->reg_offset = off;
13188 demand_empty_rest_of_line ();
13190 s_ignore (reg_type);
13191 #endif /* MIPS_STABS_ELF */
13194 /* The .loc directive. */
13205 assert (now_seg == text_section);
13207 lineno = get_number ();
13208 addroff = frag_now_fix ();
13210 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13211 S_SET_TYPE (symbolP, N_SLINE);
13212 S_SET_OTHER (symbolP, 0);
13213 S_SET_DESC (symbolP, lineno);
13214 symbolP->sy_segment = now_seg;
13218 /* CPU name/ISA/number mapping table.
13220 Entries are grouped by type. The first matching CPU or ISA entry
13221 gets chosen by CPU or ISA, so it should be the 'canonical' name
13222 for that type. Entries after that within the type are sorted
13225 Case is ignored in comparison, so put the canonical entry in the
13226 appropriate case but everything else in lower case to ease eye pain. */
13227 static const struct mips_cpu_info mips_cpu_info_table[] =
13230 { "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
13231 { "mips", 1, ISA_MIPS1, CPU_R3000, },
13234 { "MIPS2", 1, ISA_MIPS2, CPU_R6000, },
13237 { "MIPS3", 1, ISA_MIPS3, CPU_R4000, },
13240 { "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
13243 { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
13244 { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
13247 { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
13248 { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, },
13249 { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
13250 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13251 { "4km", 0, ISA_MIPS32, CPU_MIPS32, },
13252 { "4kp", 0, ISA_MIPS32, CPU_MIPS32, },
13254 /* For historical reasons. */
13255 { "MIPS64", 1, ISA_MIPS3, CPU_R4000, },
13258 { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, },
13259 { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
13260 { "5kc", 0, ISA_MIPS64, CPU_MIPS64, },
13261 { "20kc", 0, ISA_MIPS64, CPU_MIPS64, },
13264 { "R2000", 0, ISA_MIPS1, CPU_R2000, },
13265 { "2000", 0, ISA_MIPS1, CPU_R2000, },
13266 { "2k", 0, ISA_MIPS1, CPU_R2000, },
13267 { "r2k", 0, ISA_MIPS1, CPU_R2000, },
13270 { "R3000", 0, ISA_MIPS1, CPU_R3000, },
13271 { "3000", 0, ISA_MIPS1, CPU_R3000, },
13272 { "3k", 0, ISA_MIPS1, CPU_R3000, },
13273 { "r3k", 0, ISA_MIPS1, CPU_R3000, },
13276 { "R3900", 0, ISA_MIPS1, CPU_R3900, },
13277 { "3900", 0, ISA_MIPS1, CPU_R3900, },
13278 { "mipstx39", 0, ISA_MIPS1, CPU_R3900, },
13281 { "R4000", 0, ISA_MIPS3, CPU_R4000, },
13282 { "4000", 0, ISA_MIPS3, CPU_R4000, },
13283 { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */
13284 { "r4k", 0, ISA_MIPS3, CPU_R4000, },
13287 { "R4010", 0, ISA_MIPS2, CPU_R4010, },
13288 { "4010", 0, ISA_MIPS2, CPU_R4010, },
13291 { "R4400", 0, ISA_MIPS3, CPU_R4400, },
13292 { "4400", 0, ISA_MIPS3, CPU_R4400, },
13295 { "R4600", 0, ISA_MIPS3, CPU_R4600, },
13296 { "4600", 0, ISA_MIPS3, CPU_R4600, },
13297 { "mips64orion", 0, ISA_MIPS3, CPU_R4600, },
13298 { "orion", 0, ISA_MIPS3, CPU_R4600, },
13301 { "R4650", 0, ISA_MIPS3, CPU_R4650, },
13302 { "4650", 0, ISA_MIPS3, CPU_R4650, },
13305 { "R6000", 0, ISA_MIPS2, CPU_R6000, },
13306 { "6000", 0, ISA_MIPS2, CPU_R6000, },
13307 { "6k", 0, ISA_MIPS2, CPU_R6000, },
13308 { "r6k", 0, ISA_MIPS2, CPU_R6000, },
13311 { "R8000", 0, ISA_MIPS4, CPU_R8000, },
13312 { "8000", 0, ISA_MIPS4, CPU_R8000, },
13313 { "8k", 0, ISA_MIPS4, CPU_R8000, },
13314 { "r8k", 0, ISA_MIPS4, CPU_R8000, },
13317 { "R10000", 0, ISA_MIPS4, CPU_R10000, },
13318 { "10000", 0, ISA_MIPS4, CPU_R10000, },
13319 { "10k", 0, ISA_MIPS4, CPU_R10000, },
13320 { "r10k", 0, ISA_MIPS4, CPU_R10000, },
13323 { "R12000", 0, ISA_MIPS4, CPU_R12000, },
13324 { "12000", 0, ISA_MIPS4, CPU_R12000, },
13325 { "12k", 0, ISA_MIPS4, CPU_R12000, },
13326 { "r12k", 0, ISA_MIPS4, CPU_R12000, },
13329 { "VR4100", 0, ISA_MIPS3, CPU_VR4100, },
13330 { "4100", 0, ISA_MIPS3, CPU_VR4100, },
13331 { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, },
13332 { "r4100", 0, ISA_MIPS3, CPU_VR4100, },
13335 { "VR4111", 0, ISA_MIPS3, CPU_R4111, },
13336 { "4111", 0, ISA_MIPS3, CPU_R4111, },
13337 { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, },
13338 { "r4111", 0, ISA_MIPS3, CPU_R4111, },
13341 { "VR4300", 0, ISA_MIPS3, CPU_R4300, },
13342 { "4300", 0, ISA_MIPS3, CPU_R4300, },
13343 { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, },
13344 { "r4300", 0, ISA_MIPS3, CPU_R4300, },
13347 { "VR5000", 0, ISA_MIPS4, CPU_R5000, },
13348 { "5000", 0, ISA_MIPS4, CPU_R5000, },
13349 { "5k", 0, ISA_MIPS4, CPU_R5000, },
13350 { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, },
13351 { "r5000", 0, ISA_MIPS4, CPU_R5000, },
13352 { "r5200", 0, ISA_MIPS4, CPU_R5000, },
13353 { "rm5200", 0, ISA_MIPS4, CPU_R5000, },
13354 { "r5230", 0, ISA_MIPS4, CPU_R5000, },
13355 { "rm5230", 0, ISA_MIPS4, CPU_R5000, },
13356 { "r5231", 0, ISA_MIPS4, CPU_R5000, },
13357 { "rm5231", 0, ISA_MIPS4, CPU_R5000, },
13358 { "r5261", 0, ISA_MIPS4, CPU_R5000, },
13359 { "rm5261", 0, ISA_MIPS4, CPU_R5000, },
13360 { "r5721", 0, ISA_MIPS4, CPU_R5000, },
13361 { "rm5721", 0, ISA_MIPS4, CPU_R5000, },
13362 { "r5k", 0, ISA_MIPS4, CPU_R5000, },
13363 { "r7000", 0, ISA_MIPS4, CPU_R5000, },
13365 /* Broadcom SB-1 CPU */
13366 { "SB-1", 0, ISA_MIPS64, CPU_SB1, },
13367 { "sb-1250", 0, ISA_MIPS64, CPU_SB1, },
13368 { "sb1", 0, ISA_MIPS64, CPU_SB1, },
13369 { "sb1250", 0, ISA_MIPS64, CPU_SB1, },
13372 { NULL, 0, 0, 0, },
13375 static const struct mips_cpu_info *
13376 mips_cpu_info_from_name (name)
13381 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13382 if (strcasecmp (name, mips_cpu_info_table[i].name) == 0)
13383 return (&mips_cpu_info_table[i]);
13388 static const struct mips_cpu_info *
13389 mips_cpu_info_from_isa (isa)
13394 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13395 if (mips_cpu_info_table[i].is_isa
13396 && isa == mips_cpu_info_table[i].isa)
13397 return (&mips_cpu_info_table[i]);
13402 static const struct mips_cpu_info *
13403 mips_cpu_info_from_cpu (cpu)
13408 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13409 if (!mips_cpu_info_table[i].is_isa
13410 && cpu == mips_cpu_info_table[i].cpu)
13411 return (&mips_cpu_info_table[i]);