1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2016 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode *insn_mo;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p : 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p : 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p : 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p : 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p : 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi = NO_ABI;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls = FALSE;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared = TRUE;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked = FALSE;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008 = -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts =
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune = CPU_UNKNOWN;
342 static const char *mips_tune_string;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode = 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got = 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap = 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value = 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen = 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS *, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control *op_hash = NULL;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control *mips16_op_hash = NULL;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control *micromips_op_hash = NULL;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format {
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error {
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error;
737 static int auto_align = 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset = -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset = -1;
749 static int mips_cpreturn_register = -1;
750 static int mips_gp_register = GP;
751 static int mips_gprel_offset = 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid = 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg = SP;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid = 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize = 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug = 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history[1 + MAX_NOPS];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array {
797 const struct mips_operand *operand[MAX_OPERANDS];
799 static struct mips_operand_array *mips_operands;
800 static struct mips_operand_array *mips16_operands;
801 static struct mips_operand_array *micromips_operands;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn;
805 static struct mips_cl_insn mips16_nop_insn;
806 static struct mips_cl_insn micromips_nop16_insn;
807 static struct mips_cl_insn micromips_nop32_insn;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS *prev_nop_frag;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup *next;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup *mips_hi_fixup_list;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS *prev_reloc_op_frag;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch;
947 /* The expansion of many macros depends on the type of symbol that
948 they refer to. For example, when generating position-dependent code,
949 a macro that refers to a symbol may have two different expansions,
950 one which uses GP-relative addresses and one which uses absolute
951 addresses. When generating SVR4-style PIC, a macro may have
952 different expansions for local and global symbols.
954 We handle these situations by generating both sequences and putting
955 them in variant frags. In position-dependent code, the first sequence
956 will be the GP-relative one and the second sequence will be the
957 absolute one. In SVR4 PIC, the first sequence will be for global
958 symbols and the second will be for local symbols.
960 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
961 SECOND are the lengths of the two sequences in bytes. These fields
962 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
963 the subtype has the following flags:
966 Set if it has been decided that we should use the second
967 sequence instead of the first.
970 Set in the first variant frag if the macro's second implementation
971 is longer than its first. This refers to the macro as a whole,
972 not an individual relaxation.
975 Set in the first variant frag if the macro appeared in a .set nomacro
976 block and if one alternative requires a warning but the other does not.
979 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
982 RELAX_DELAY_SLOT_16BIT
983 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
986 RELAX_DELAY_SLOT_SIZE_FIRST
987 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
988 the macro is of the wrong size for the branch delay slot.
990 RELAX_DELAY_SLOT_SIZE_SECOND
991 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
992 the macro is of the wrong size for the branch delay slot.
994 The frag's "opcode" points to the first fixup for relaxable code.
996 Relaxable macros are generated using a sequence such as:
998 relax_start (SYMBOL);
999 ... generate first expansion ...
1001 ... generate second expansion ...
1004 The code and fixups for the unwanted alternative are discarded
1005 by md_convert_frag. */
1006 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1008 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1009 #define RELAX_SECOND(X) ((X) & 0xff)
1010 #define RELAX_USE_SECOND 0x10000
1011 #define RELAX_SECOND_LONGER 0x20000
1012 #define RELAX_NOMACRO 0x40000
1013 #define RELAX_DELAY_SLOT 0x80000
1014 #define RELAX_DELAY_SLOT_16BIT 0x100000
1015 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1016 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1018 /* Branch without likely bit. If label is out of range, we turn:
1020 beq reg1, reg2, label
1030 with the following opcode replacements:
1037 bltzal <-> bgezal (with jal label instead of j label)
1039 Even though keeping the delay slot instruction in the delay slot of
1040 the branch would be more efficient, it would be very tricky to do
1041 correctly, because we'd have to introduce a variable frag *after*
1042 the delay slot instruction, and expand that instead. Let's do it
1043 the easy way for now, even if the branch-not-taken case now costs
1044 one additional instruction. Out-of-range branches are not supposed
1045 to be common, anyway.
1047 Branch likely. If label is out of range, we turn:
1049 beql reg1, reg2, label
1050 delay slot (annulled if branch not taken)
1059 delay slot (executed only if branch taken)
1062 It would be possible to generate a shorter sequence by losing the
1063 likely bit, generating something like:
1068 delay slot (executed only if branch taken)
1080 bltzall -> bgezal (with jal label instead of j label)
1081 bgezall -> bltzal (ditto)
1084 but it's not clear that it would actually improve performance. */
1085 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1086 ((relax_substateT) \
1089 | ((toofar) ? 0x20 : 0) \
1090 | ((link) ? 0x40 : 0) \
1091 | ((likely) ? 0x80 : 0) \
1092 | ((uncond) ? 0x100 : 0)))
1093 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1094 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1095 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1096 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1097 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1098 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1100 /* For mips16 code, we use an entirely different form of relaxation.
1101 mips16 supports two versions of most instructions which take
1102 immediate values: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. Since branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both mips16 and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use the high bit of the subtype field to distinguish these cases.
1111 The information we store for this type of relaxation is the
1112 argument code found in the opcode file for this relocation, whether
1113 the user explicitly requested a small or extended form, and whether
1114 the relocation is in a jump or jal delay slot. That tells us the
1115 size of the value, and how it should be stored. We also store
1116 whether the fragment is considered to be extended or not. We also
1117 store whether this is known to be a branch to a different section,
1118 whether we have tried to relax this frag yet, and whether we have
1119 ever extended a PC relative fragment because of a shift count. */
1120 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1123 | ((small) ? 0x100 : 0) \
1124 | ((ext) ? 0x200 : 0) \
1125 | ((dslot) ? 0x400 : 0) \
1126 | ((jal_dslot) ? 0x800 : 0))
1127 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1128 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1129 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1130 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1131 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1132 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1133 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1134 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1135 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1136 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1138 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1140 /* For microMIPS code, we use relaxation similar to one we use for
1141 MIPS16 code. Some instructions that take immediate values support
1142 two encodings: a small one which takes some small value, and a
1143 larger one which takes a 16 bit value. As some branches also follow
1144 this pattern, relaxing these values is required.
1146 We can assemble both microMIPS and normal MIPS code in a single
1147 object. Therefore, we need to support this type of relaxation at
1148 the same time that we support the relaxation described above. We
1149 use one of the high bits of the subtype field to distinguish these
1152 The information we store for this type of relaxation is the argument
1153 code found in the opcode file for this relocation, the register
1154 selected as the assembler temporary, whether the branch is
1155 unconditional, whether it is compact, whether it stores the link
1156 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1157 branches to a sequence of instructions is enabled, and whether the
1158 displacement of a branch is too large to fit as an immediate argument
1159 of a 16-bit and a 32-bit branch, respectively. */
1160 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1161 relax32, toofar16, toofar32) \
1164 | (((at) & 0x1f) << 8) \
1165 | ((uncond) ? 0x2000 : 0) \
1166 | ((compact) ? 0x4000 : 0) \
1167 | ((link) ? 0x8000 : 0) \
1168 | ((relax32) ? 0x10000 : 0) \
1169 | ((toofar16) ? 0x20000 : 0) \
1170 | ((toofar32) ? 0x40000 : 0))
1171 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1172 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1173 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1174 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1175 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1176 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1177 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1179 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1180 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1181 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1182 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1186 /* Sign-extend 16-bit value X. */
1187 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1189 /* Is the given value a sign-extended 32-bit value? */
1190 #define IS_SEXT_32BIT_NUM(x) \
1191 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1192 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1194 /* Is the given value a sign-extended 16-bit value? */
1195 #define IS_SEXT_16BIT_NUM(x) \
1196 (((x) &~ (offsetT) 0x7fff) == 0 \
1197 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1199 /* Is the given value a sign-extended 12-bit value? */
1200 #define IS_SEXT_12BIT_NUM(x) \
1201 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1203 /* Is the given value a sign-extended 9-bit value? */
1204 #define IS_SEXT_9BIT_NUM(x) \
1205 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1207 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1208 #define IS_ZEXT_32BIT_NUM(x) \
1209 (((x) &~ (offsetT) 0xffffffff) == 0 \
1210 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1212 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1214 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1215 (((STRUCT) >> (SHIFT)) & (MASK))
1217 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1218 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1220 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1221 : EXTRACT_BITS ((INSN).insn_opcode, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1223 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1224 EXTRACT_BITS ((INSN).insn_opcode, \
1225 MIPS16OP_MASK_##FIELD, \
1226 MIPS16OP_SH_##FIELD)
1228 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1229 #define MIPS16_EXTEND (0xf000U << 16)
1231 /* Whether or not we are emitting a branch-likely macro. */
1232 static bfd_boolean emit_branch_likely_macro = FALSE;
1234 /* Global variables used when generating relaxable macros. See the
1235 comment above RELAX_ENCODE for more details about how relaxation
1238 /* 0 if we're not emitting a relaxable macro.
1239 1 if we're emitting the first of the two relaxation alternatives.
1240 2 if we're emitting the second alternative. */
1243 /* The first relaxable fixup in the current frag. (In other words,
1244 the first fixup that refers to relaxable code.) */
1247 /* sizes[0] says how many bytes of the first alternative are stored in
1248 the current frag. Likewise sizes[1] for the second alternative. */
1249 unsigned int sizes[2];
1251 /* The symbol on which the choice of sequence depends. */
1255 /* Global variables used to decide whether a macro needs a warning. */
1257 /* True if the macro is in a branch delay slot. */
1258 bfd_boolean delay_slot_p;
1260 /* Set to the length in bytes required if the macro is in a delay slot
1261 that requires a specific length of instruction, otherwise zero. */
1262 unsigned int delay_slot_length;
1264 /* For relaxable macros, sizes[0] is the length of the first alternative
1265 in bytes and sizes[1] is the length of the second alternative.
1266 For non-relaxable macros, both elements give the length of the
1268 unsigned int sizes[2];
1270 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1271 instruction of the first alternative in bytes and first_insn_sizes[1]
1272 is the length of the first instruction of the second alternative.
1273 For non-relaxable macros, both elements give the length of the first
1274 instruction in bytes.
1276 Set to zero if we haven't yet seen the first instruction. */
1277 unsigned int first_insn_sizes[2];
1279 /* For relaxable macros, insns[0] is the number of instructions for the
1280 first alternative and insns[1] is the number of instructions for the
1283 For non-relaxable macros, both elements give the number of
1284 instructions for the macro. */
1285 unsigned int insns[2];
1287 /* The first variant frag for this macro. */
1289 } mips_macro_warning;
1291 /* Prototypes for static functions. */
1293 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1295 static void append_insn
1296 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1297 bfd_boolean expansionp);
1298 static void mips_no_prev_insn (void);
1299 static void macro_build (expressionS *, const char *, const char *, ...);
1300 static void mips16_macro_build
1301 (expressionS *, const char *, const char *, va_list *);
1302 static void load_register (int, expressionS *, int);
1303 static void macro_start (void);
1304 static void macro_end (void);
1305 static void macro (struct mips_cl_insn *ip, char *str);
1306 static void mips16_macro (struct mips_cl_insn * ip);
1307 static void mips_ip (char *str, struct mips_cl_insn * ip);
1308 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1309 static void mips16_immed
1310 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1311 unsigned int, unsigned long *);
1312 static size_t my_getSmallExpression
1313 (expressionS *, bfd_reloc_code_real_type *, char *);
1314 static void my_getExpression (expressionS *, char *);
1315 static void s_align (int);
1316 static void s_change_sec (int);
1317 static void s_change_section (int);
1318 static void s_cons (int);
1319 static void s_float_cons (int);
1320 static void s_mips_globl (int);
1321 static void s_option (int);
1322 static void s_mipsset (int);
1323 static void s_abicalls (int);
1324 static void s_cpload (int);
1325 static void s_cpsetup (int);
1326 static void s_cplocal (int);
1327 static void s_cprestore (int);
1328 static void s_cpreturn (int);
1329 static void s_dtprelword (int);
1330 static void s_dtpreldword (int);
1331 static void s_tprelword (int);
1332 static void s_tpreldword (int);
1333 static void s_gpvalue (int);
1334 static void s_gpword (int);
1335 static void s_gpdword (int);
1336 static void s_ehword (int);
1337 static void s_cpadd (int);
1338 static void s_insn (int);
1339 static void s_nan (int);
1340 static void s_module (int);
1341 static void s_mips_ent (int);
1342 static void s_mips_end (int);
1343 static void s_mips_frame (int);
1344 static void s_mips_mask (int reg_type);
1345 static void s_mips_stab (int);
1346 static void s_mips_weakext (int);
1347 static void s_mips_file (int);
1348 static void s_mips_loc (int);
1349 static bfd_boolean pic_need_relax (symbolS *, asection *);
1350 static int relaxed_branch_length (fragS *, asection *, int);
1351 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1352 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1353 static void file_mips_check_options (void);
1355 /* Table and functions used to map between CPU/ISA names, and
1356 ISA levels, and CPU numbers. */
1358 struct mips_cpu_info
1360 const char *name; /* CPU or ISA name. */
1361 int flags; /* MIPS_CPU_* flags. */
1362 int ase; /* Set of ASEs implemented by the CPU. */
1363 int isa; /* ISA level. */
1364 int cpu; /* CPU number (default CPU if ISA). */
1367 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1369 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1371 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1373 /* Command-line options. */
1374 const char *md_shortopts = "O::g::G:";
1378 OPTION_MARCH = OPTION_MD_BASE,
1410 OPTION_NO_SMARTMIPS,
1420 OPTION_NO_MICROMIPS,
1423 OPTION_COMPAT_ARCH_BASE,
1432 OPTION_M7000_HILO_FIX,
1433 OPTION_MNO_7000_HILO_FIX,
1437 OPTION_NO_FIX_RM7000,
1438 OPTION_FIX_LOONGSON2F_JUMP,
1439 OPTION_NO_FIX_LOONGSON2F_JUMP,
1440 OPTION_FIX_LOONGSON2F_NOP,
1441 OPTION_NO_FIX_LOONGSON2F_NOP,
1443 OPTION_NO_FIX_VR4120,
1445 OPTION_NO_FIX_VR4130,
1446 OPTION_FIX_CN63XXP1,
1447 OPTION_NO_FIX_CN63XXP1,
1454 OPTION_CONSTRUCT_FLOATS,
1455 OPTION_NO_CONSTRUCT_FLOATS,
1459 OPTION_RELAX_BRANCH,
1460 OPTION_NO_RELAX_BRANCH,
1469 OPTION_SINGLE_FLOAT,
1470 OPTION_DOUBLE_FLOAT,
1483 OPTION_MVXWORKS_PIC,
1486 OPTION_NO_ODD_SPREG,
1490 struct option md_longopts[] =
1492 /* Options which specify architecture. */
1493 {"march", required_argument, NULL, OPTION_MARCH},
1494 {"mtune", required_argument, NULL, OPTION_MTUNE},
1495 {"mips0", no_argument, NULL, OPTION_MIPS1},
1496 {"mips1", no_argument, NULL, OPTION_MIPS1},
1497 {"mips2", no_argument, NULL, OPTION_MIPS2},
1498 {"mips3", no_argument, NULL, OPTION_MIPS3},
1499 {"mips4", no_argument, NULL, OPTION_MIPS4},
1500 {"mips5", no_argument, NULL, OPTION_MIPS5},
1501 {"mips32", no_argument, NULL, OPTION_MIPS32},
1502 {"mips64", no_argument, NULL, OPTION_MIPS64},
1503 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1504 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1505 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1506 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1507 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1508 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1509 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1510 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1512 /* Options which specify Application Specific Extensions (ASEs). */
1513 {"mips16", no_argument, NULL, OPTION_MIPS16},
1514 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1515 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1516 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1517 {"mdmx", no_argument, NULL, OPTION_MDMX},
1518 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1519 {"mdsp", no_argument, NULL, OPTION_DSP},
1520 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1521 {"mmt", no_argument, NULL, OPTION_MT},
1522 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1523 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1524 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1525 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1526 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1527 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1528 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1529 {"meva", no_argument, NULL, OPTION_EVA},
1530 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1531 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1532 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1533 {"mmcu", no_argument, NULL, OPTION_MCU},
1534 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1535 {"mvirt", no_argument, NULL, OPTION_VIRT},
1536 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1537 {"mmsa", no_argument, NULL, OPTION_MSA},
1538 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1539 {"mxpa", no_argument, NULL, OPTION_XPA},
1540 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1542 /* Old-style architecture options. Don't add more of these. */
1543 {"m4650", no_argument, NULL, OPTION_M4650},
1544 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1545 {"m4010", no_argument, NULL, OPTION_M4010},
1546 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1547 {"m4100", no_argument, NULL, OPTION_M4100},
1548 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1549 {"m3900", no_argument, NULL, OPTION_M3900},
1550 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1552 /* Options which enable bug fixes. */
1553 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1554 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1555 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1556 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1557 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1558 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1559 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1560 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1561 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1562 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1563 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1564 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1565 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1566 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1567 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1568 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1569 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1571 /* Miscellaneous options. */
1572 {"trap", no_argument, NULL, OPTION_TRAP},
1573 {"no-break", no_argument, NULL, OPTION_TRAP},
1574 {"break", no_argument, NULL, OPTION_BREAK},
1575 {"no-trap", no_argument, NULL, OPTION_BREAK},
1576 {"EB", no_argument, NULL, OPTION_EB},
1577 {"EL", no_argument, NULL, OPTION_EL},
1578 {"mfp32", no_argument, NULL, OPTION_FP32},
1579 {"mgp32", no_argument, NULL, OPTION_GP32},
1580 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1581 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1582 {"mfp64", no_argument, NULL, OPTION_FP64},
1583 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1584 {"mgp64", no_argument, NULL, OPTION_GP64},
1585 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1586 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1587 {"minsn32", no_argument, NULL, OPTION_INSN32},
1588 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1589 {"mshared", no_argument, NULL, OPTION_MSHARED},
1590 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1591 {"msym32", no_argument, NULL, OPTION_MSYM32},
1592 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1593 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1594 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1595 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1596 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1597 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1598 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1600 /* Strictly speaking this next option is ELF specific,
1601 but we allow it for other ports as well in order to
1602 make testing easier. */
1603 {"32", no_argument, NULL, OPTION_32},
1605 /* ELF-specific options. */
1606 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1607 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1608 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1609 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1610 {"xgot", no_argument, NULL, OPTION_XGOT},
1611 {"mabi", required_argument, NULL, OPTION_MABI},
1612 {"n32", no_argument, NULL, OPTION_N32},
1613 {"64", no_argument, NULL, OPTION_64},
1614 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1615 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1616 {"mpdr", no_argument, NULL, OPTION_PDR},
1617 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1618 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1619 {"mnan", required_argument, NULL, OPTION_NAN},
1621 {NULL, no_argument, NULL, 0}
1623 size_t md_longopts_size = sizeof (md_longopts);
1625 /* Information about either an Application Specific Extension or an
1626 optional architecture feature that, for simplicity, we treat in the
1627 same way as an ASE. */
1630 /* The name of the ASE, used in both the command-line and .set options. */
1633 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1634 and 64-bit architectures, the flags here refer to the subset that
1635 is available on both. */
1638 /* The ASE_* flag used for instructions that are available on 64-bit
1639 architectures but that are not included in FLAGS. */
1640 unsigned int flags64;
1642 /* The command-line options that turn the ASE on and off. */
1646 /* The minimum required architecture revisions for MIPS32, MIPS64,
1647 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1650 int micromips32_rev;
1651 int micromips64_rev;
1653 /* The architecture where the ASE was removed or -1 if the extension has not
1658 /* A table of all supported ASEs. */
1659 static const struct mips_ase mips_ases[] = {
1660 { "dsp", ASE_DSP, ASE_DSP64,
1661 OPTION_DSP, OPTION_NO_DSP,
1665 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1666 OPTION_DSPR2, OPTION_NO_DSPR2,
1670 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1671 OPTION_DSPR3, OPTION_NO_DSPR3,
1675 { "eva", ASE_EVA, 0,
1676 OPTION_EVA, OPTION_NO_EVA,
1680 { "mcu", ASE_MCU, 0,
1681 OPTION_MCU, OPTION_NO_MCU,
1685 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1686 { "mdmx", ASE_MDMX, 0,
1687 OPTION_MDMX, OPTION_NO_MDMX,
1691 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1692 { "mips3d", ASE_MIPS3D, 0,
1693 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1698 OPTION_MT, OPTION_NO_MT,
1702 { "smartmips", ASE_SMARTMIPS, 0,
1703 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1707 { "virt", ASE_VIRT, ASE_VIRT64,
1708 OPTION_VIRT, OPTION_NO_VIRT,
1712 { "msa", ASE_MSA, ASE_MSA64,
1713 OPTION_MSA, OPTION_NO_MSA,
1717 { "xpa", ASE_XPA, 0,
1718 OPTION_XPA, OPTION_NO_XPA,
1723 /* The set of ASEs that require -mfp64. */
1724 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1726 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1727 static const unsigned int mips_ase_groups[] = {
1728 ASE_DSP | ASE_DSPR2 | ASE_DSPR3
1733 The following pseudo-ops from the Kane and Heinrich MIPS book
1734 should be defined here, but are currently unsupported: .alias,
1735 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1737 The following pseudo-ops from the Kane and Heinrich MIPS book are
1738 specific to the type of debugging information being generated, and
1739 should be defined by the object format: .aent, .begin, .bend,
1740 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1743 The following pseudo-ops from the Kane and Heinrich MIPS book are
1744 not MIPS CPU specific, but are also not specific to the object file
1745 format. This file is probably the best place to define them, but
1746 they are not currently supported: .asm0, .endr, .lab, .struct. */
1748 static const pseudo_typeS mips_pseudo_table[] =
1750 /* MIPS specific pseudo-ops. */
1751 {"option", s_option, 0},
1752 {"set", s_mipsset, 0},
1753 {"rdata", s_change_sec, 'r'},
1754 {"sdata", s_change_sec, 's'},
1755 {"livereg", s_ignore, 0},
1756 {"abicalls", s_abicalls, 0},
1757 {"cpload", s_cpload, 0},
1758 {"cpsetup", s_cpsetup, 0},
1759 {"cplocal", s_cplocal, 0},
1760 {"cprestore", s_cprestore, 0},
1761 {"cpreturn", s_cpreturn, 0},
1762 {"dtprelword", s_dtprelword, 0},
1763 {"dtpreldword", s_dtpreldword, 0},
1764 {"tprelword", s_tprelword, 0},
1765 {"tpreldword", s_tpreldword, 0},
1766 {"gpvalue", s_gpvalue, 0},
1767 {"gpword", s_gpword, 0},
1768 {"gpdword", s_gpdword, 0},
1769 {"ehword", s_ehword, 0},
1770 {"cpadd", s_cpadd, 0},
1771 {"insn", s_insn, 0},
1773 {"module", s_module, 0},
1775 /* Relatively generic pseudo-ops that happen to be used on MIPS
1777 {"asciiz", stringer, 8 + 1},
1778 {"bss", s_change_sec, 'b'},
1780 {"half", s_cons, 1},
1781 {"dword", s_cons, 3},
1782 {"weakext", s_mips_weakext, 0},
1783 {"origin", s_org, 0},
1784 {"repeat", s_rept, 0},
1786 /* For MIPS this is non-standard, but we define it for consistency. */
1787 {"sbss", s_change_sec, 'B'},
1789 /* These pseudo-ops are defined in read.c, but must be overridden
1790 here for one reason or another. */
1791 {"align", s_align, 0},
1792 {"byte", s_cons, 0},
1793 {"data", s_change_sec, 'd'},
1794 {"double", s_float_cons, 'd'},
1795 {"float", s_float_cons, 'f'},
1796 {"globl", s_mips_globl, 0},
1797 {"global", s_mips_globl, 0},
1798 {"hword", s_cons, 1},
1800 {"long", s_cons, 2},
1801 {"octa", s_cons, 4},
1802 {"quad", s_cons, 3},
1803 {"section", s_change_section, 0},
1804 {"short", s_cons, 1},
1805 {"single", s_float_cons, 'f'},
1806 {"stabd", s_mips_stab, 'd'},
1807 {"stabn", s_mips_stab, 'n'},
1808 {"stabs", s_mips_stab, 's'},
1809 {"text", s_change_sec, 't'},
1810 {"word", s_cons, 2},
1812 { "extern", ecoff_directive_extern, 0},
1817 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1819 /* These pseudo-ops should be defined by the object file format.
1820 However, a.out doesn't support them, so we have versions here. */
1821 {"aent", s_mips_ent, 1},
1822 {"bgnb", s_ignore, 0},
1823 {"end", s_mips_end, 0},
1824 {"endb", s_ignore, 0},
1825 {"ent", s_mips_ent, 0},
1826 {"file", s_mips_file, 0},
1827 {"fmask", s_mips_mask, 'F'},
1828 {"frame", s_mips_frame, 0},
1829 {"loc", s_mips_loc, 0},
1830 {"mask", s_mips_mask, 'R'},
1831 {"verstamp", s_ignore, 0},
1835 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1836 purpose of the `.dc.a' internal pseudo-op. */
1839 mips_address_bytes (void)
1841 file_mips_check_options ();
1842 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1845 extern void pop_insert (const pseudo_typeS *);
1848 mips_pop_insert (void)
1850 pop_insert (mips_pseudo_table);
1851 if (! ECOFF_DEBUGGING)
1852 pop_insert (mips_nonecoff_pseudo_table);
1855 /* Symbols labelling the current insn. */
1857 struct insn_label_list
1859 struct insn_label_list *next;
1863 static struct insn_label_list *free_insn_labels;
1864 #define label_list tc_segment_info_data.labels
1866 static void mips_clear_insn_labels (void);
1867 static void mips_mark_labels (void);
1868 static void mips_compressed_mark_labels (void);
1871 mips_clear_insn_labels (void)
1873 struct insn_label_list **pl;
1874 segment_info_type *si;
1878 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1881 si = seg_info (now_seg);
1882 *pl = si->label_list;
1883 si->label_list = NULL;
1887 /* Mark instruction labels in MIPS16/microMIPS mode. */
1890 mips_mark_labels (void)
1892 if (HAVE_CODE_COMPRESSION)
1893 mips_compressed_mark_labels ();
1896 static char *expr_end;
1898 /* An expression in a macro instruction. This is set by mips_ip and
1899 mips16_ip and when populated is always an O_constant. */
1901 static expressionS imm_expr;
1903 /* The relocatable field in an instruction and the relocs associated
1904 with it. These variables are used for instructions like LUI and
1905 JAL as well as true offsets. They are also used for address
1906 operands in macros. */
1908 static expressionS offset_expr;
1909 static bfd_reloc_code_real_type offset_reloc[3]
1910 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1912 /* This is set to the resulting size of the instruction to be produced
1913 by mips16_ip if an explicit extension is used or by mips_ip if an
1914 explicit size is supplied. */
1916 static unsigned int forced_insn_length;
1918 /* True if we are assembling an instruction. All dot symbols defined during
1919 this time should be treated as code labels. */
1921 static bfd_boolean mips_assembling_insn;
1923 /* The pdr segment for per procedure frame/regmask info. Not used for
1926 static segT pdr_seg;
1928 /* The default target format to use. */
1930 #if defined (TE_FreeBSD)
1931 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1932 #elif defined (TE_TMIPS)
1933 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1935 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1939 mips_target_format (void)
1941 switch (OUTPUT_FLAVOR)
1943 case bfd_target_elf_flavour:
1945 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1946 return (target_big_endian
1947 ? "elf32-bigmips-vxworks"
1948 : "elf32-littlemips-vxworks");
1950 return (target_big_endian
1951 ? (HAVE_64BIT_OBJECTS
1952 ? ELF_TARGET ("elf64-", "big")
1954 ? ELF_TARGET ("elf32-n", "big")
1955 : ELF_TARGET ("elf32-", "big")))
1956 : (HAVE_64BIT_OBJECTS
1957 ? ELF_TARGET ("elf64-", "little")
1959 ? ELF_TARGET ("elf32-n", "little")
1960 : ELF_TARGET ("elf32-", "little"))));
1967 /* Return the ISA revision that is currently in use, or 0 if we are
1968 generating code for MIPS V or below. */
1973 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1976 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1979 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
1982 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
1985 /* microMIPS implies revision 2 or above. */
1986 if (mips_opts.micromips)
1989 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1995 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1998 mips_ase_mask (unsigned int flags)
2002 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2003 if (flags & mips_ase_groups[i])
2004 flags |= mips_ase_groups[i];
2008 /* Check whether the current ISA supports ASE. Issue a warning if
2012 mips_check_isa_supports_ase (const struct mips_ase *ase)
2016 static unsigned int warned_isa;
2017 static unsigned int warned_fp32;
2019 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2020 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2022 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2023 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2024 && (warned_isa & ase->flags) != ase->flags)
2026 warned_isa |= ase->flags;
2027 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2028 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2030 as_warn (_("the %d-bit %s architecture does not support the"
2031 " `%s' extension"), size, base, ase->name);
2033 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2034 ase->name, base, size, min_rev);
2036 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2037 && (warned_isa & ase->flags) != ase->flags)
2039 warned_isa |= ase->flags;
2040 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2041 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2042 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2043 ase->name, base, size, ase->rem_rev);
2046 if ((ase->flags & FP64_ASES)
2047 && mips_opts.fp != 64
2048 && (warned_fp32 & ase->flags) != ase->flags)
2050 warned_fp32 |= ase->flags;
2051 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2055 /* Check all enabled ASEs to see whether they are supported by the
2056 chosen architecture. */
2059 mips_check_isa_supports_ases (void)
2061 unsigned int i, mask;
2063 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2065 mask = mips_ase_mask (mips_ases[i].flags);
2066 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2067 mips_check_isa_supports_ase (&mips_ases[i]);
2071 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2072 that were affected. */
2075 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2076 bfd_boolean enabled_p)
2080 mask = mips_ase_mask (ase->flags);
2083 opts->ase |= ase->flags;
2087 /* Return the ASE called NAME, or null if none. */
2089 static const struct mips_ase *
2090 mips_lookup_ase (const char *name)
2094 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2095 if (strcmp (name, mips_ases[i].name) == 0)
2096 return &mips_ases[i];
2100 /* Return the length of a microMIPS instruction in bytes. If bits of
2101 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2102 otherwise it is a 32-bit instruction. */
2104 static inline unsigned int
2105 micromips_insn_length (const struct mips_opcode *mo)
2107 return (mo->mask >> 16) == 0 ? 2 : 4;
2110 /* Return the length of MIPS16 instruction OPCODE. */
2112 static inline unsigned int
2113 mips16_opcode_length (unsigned long opcode)
2115 return (opcode >> 16) == 0 ? 2 : 4;
2118 /* Return the length of instruction INSN. */
2120 static inline unsigned int
2121 insn_length (const struct mips_cl_insn *insn)
2123 if (mips_opts.micromips)
2124 return micromips_insn_length (insn->insn_mo);
2125 else if (mips_opts.mips16)
2126 return mips16_opcode_length (insn->insn_opcode);
2131 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2134 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2139 insn->insn_opcode = mo->match;
2142 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2143 insn->fixp[i] = NULL;
2144 insn->fixed_p = (mips_opts.noreorder > 0);
2145 insn->noreorder_p = (mips_opts.noreorder > 0);
2146 insn->mips16_absolute_jump_p = 0;
2147 insn->complete_p = 0;
2148 insn->cleared_p = 0;
2151 /* Get a list of all the operands in INSN. */
2153 static const struct mips_operand_array *
2154 insn_operands (const struct mips_cl_insn *insn)
2156 if (insn->insn_mo >= &mips_opcodes[0]
2157 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2158 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2160 if (insn->insn_mo >= &mips16_opcodes[0]
2161 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2162 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2164 if (insn->insn_mo >= µmips_opcodes[0]
2165 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2166 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2171 /* Get a description of operand OPNO of INSN. */
2173 static const struct mips_operand *
2174 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2176 const struct mips_operand_array *operands;
2178 operands = insn_operands (insn);
2179 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2181 return operands->operand[opno];
2184 /* Install UVAL as the value of OPERAND in INSN. */
2187 insn_insert_operand (struct mips_cl_insn *insn,
2188 const struct mips_operand *operand, unsigned int uval)
2190 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2193 /* Extract the value of OPERAND from INSN. */
2195 static inline unsigned
2196 insn_extract_operand (const struct mips_cl_insn *insn,
2197 const struct mips_operand *operand)
2199 return mips_extract_operand (operand, insn->insn_opcode);
2202 /* Record the current MIPS16/microMIPS mode in now_seg. */
2205 mips_record_compressed_mode (void)
2207 segment_info_type *si;
2209 si = seg_info (now_seg);
2210 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2211 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2212 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2213 si->tc_segment_info_data.micromips = mips_opts.micromips;
2216 /* Read a standard MIPS instruction from BUF. */
2218 static unsigned long
2219 read_insn (char *buf)
2221 if (target_big_endian)
2222 return bfd_getb32 ((bfd_byte *) buf);
2224 return bfd_getl32 ((bfd_byte *) buf);
2227 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2231 write_insn (char *buf, unsigned int insn)
2233 md_number_to_chars (buf, insn, 4);
2237 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2238 has length LENGTH. */
2240 static unsigned long
2241 read_compressed_insn (char *buf, unsigned int length)
2247 for (i = 0; i < length; i += 2)
2250 if (target_big_endian)
2251 insn |= bfd_getb16 ((char *) buf);
2253 insn |= bfd_getl16 ((char *) buf);
2259 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2260 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2263 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2267 for (i = 0; i < length; i += 2)
2268 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2269 return buf + length;
2272 /* Install INSN at the location specified by its "frag" and "where" fields. */
2275 install_insn (const struct mips_cl_insn *insn)
2277 char *f = insn->frag->fr_literal + insn->where;
2278 if (HAVE_CODE_COMPRESSION)
2279 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2281 write_insn (f, insn->insn_opcode);
2282 mips_record_compressed_mode ();
2285 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2286 and install the opcode in the new location. */
2289 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2294 insn->where = where;
2295 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2296 if (insn->fixp[i] != NULL)
2298 insn->fixp[i]->fx_frag = frag;
2299 insn->fixp[i]->fx_where = where;
2301 install_insn (insn);
2304 /* Add INSN to the end of the output. */
2307 add_fixed_insn (struct mips_cl_insn *insn)
2309 char *f = frag_more (insn_length (insn));
2310 move_insn (insn, frag_now, f - frag_now->fr_literal);
2313 /* Start a variant frag and move INSN to the start of the variant part,
2314 marking it as fixed. The other arguments are as for frag_var. */
2317 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2318 relax_substateT subtype, symbolS *symbol, offsetT offset)
2320 frag_grow (max_chars);
2321 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2323 frag_var (rs_machine_dependent, max_chars, var,
2324 subtype, symbol, offset, NULL);
2327 /* Insert N copies of INSN into the history buffer, starting at
2328 position FIRST. Neither FIRST nor N need to be clipped. */
2331 insert_into_history (unsigned int first, unsigned int n,
2332 const struct mips_cl_insn *insn)
2334 if (mips_relax.sequence != 2)
2338 for (i = ARRAY_SIZE (history); i-- > first;)
2340 history[i] = history[i - n];
2346 /* Clear the error in insn_error. */
2349 clear_insn_error (void)
2351 memset (&insn_error, 0, sizeof (insn_error));
2354 /* Possibly record error message MSG for the current instruction.
2355 If the error is about a particular argument, ARGNUM is the 1-based
2356 number of that argument, otherwise it is 0. FORMAT is the format
2357 of MSG. Return true if MSG was used, false if the current message
2361 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2366 /* Give priority to errors against specific arguments, and to
2367 the first whole-instruction message. */
2373 /* Keep insn_error if it is against a later argument. */
2374 if (argnum < insn_error.min_argnum)
2377 /* If both errors are against the same argument but are different,
2378 give up on reporting a specific error for this argument.
2379 See the comment about mips_insn_error for details. */
2380 if (argnum == insn_error.min_argnum
2382 && strcmp (insn_error.msg, msg) != 0)
2385 insn_error.min_argnum += 1;
2389 insn_error.min_argnum = argnum;
2390 insn_error.format = format;
2391 insn_error.msg = msg;
2395 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2396 as for set_insn_error_format. */
2399 set_insn_error (int argnum, const char *msg)
2401 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2404 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2405 as for set_insn_error_format. */
2408 set_insn_error_i (int argnum, const char *msg, int i)
2410 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2414 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2415 are as for set_insn_error_format. */
2418 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2420 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2422 insn_error.u.ss[0] = s1;
2423 insn_error.u.ss[1] = s2;
2427 /* Report the error in insn_error, which is against assembly code STR. */
2430 report_insn_error (const char *str)
2432 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2434 switch (insn_error.format)
2441 as_bad (msg, insn_error.u.i, str);
2445 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2449 free ((char *) msg);
2452 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2453 the idea is to make it obvious at a glance that each errata is
2457 init_vr4120_conflicts (void)
2459 #define CONFLICT(FIRST, SECOND) \
2460 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2462 /* Errata 21 - [D]DIV[U] after [D]MACC */
2463 CONFLICT (MACC, DIV);
2464 CONFLICT (DMACC, DIV);
2466 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2467 CONFLICT (DMULT, DMULT);
2468 CONFLICT (DMULT, DMACC);
2469 CONFLICT (DMACC, DMULT);
2470 CONFLICT (DMACC, DMACC);
2472 /* Errata 24 - MT{LO,HI} after [D]MACC */
2473 CONFLICT (MACC, MTHILO);
2474 CONFLICT (DMACC, MTHILO);
2476 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2477 instruction is executed immediately after a MACC or DMACC
2478 instruction, the result of [either instruction] is incorrect." */
2479 CONFLICT (MACC, MULT);
2480 CONFLICT (MACC, DMULT);
2481 CONFLICT (DMACC, MULT);
2482 CONFLICT (DMACC, DMULT);
2484 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2485 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2486 DDIV or DDIVU instruction, the result of the MACC or
2487 DMACC instruction is incorrect.". */
2488 CONFLICT (DMULT, MACC);
2489 CONFLICT (DMULT, DMACC);
2490 CONFLICT (DIV, MACC);
2491 CONFLICT (DIV, DMACC);
2501 #define RNUM_MASK 0x00000ff
2502 #define RTYPE_MASK 0x0ffff00
2503 #define RTYPE_NUM 0x0000100
2504 #define RTYPE_FPU 0x0000200
2505 #define RTYPE_FCC 0x0000400
2506 #define RTYPE_VEC 0x0000800
2507 #define RTYPE_GP 0x0001000
2508 #define RTYPE_CP0 0x0002000
2509 #define RTYPE_PC 0x0004000
2510 #define RTYPE_ACC 0x0008000
2511 #define RTYPE_CCC 0x0010000
2512 #define RTYPE_VI 0x0020000
2513 #define RTYPE_VF 0x0040000
2514 #define RTYPE_R5900_I 0x0080000
2515 #define RTYPE_R5900_Q 0x0100000
2516 #define RTYPE_R5900_R 0x0200000
2517 #define RTYPE_R5900_ACC 0x0400000
2518 #define RTYPE_MSA 0x0800000
2519 #define RWARN 0x8000000
2521 #define GENERIC_REGISTER_NUMBERS \
2522 {"$0", RTYPE_NUM | 0}, \
2523 {"$1", RTYPE_NUM | 1}, \
2524 {"$2", RTYPE_NUM | 2}, \
2525 {"$3", RTYPE_NUM | 3}, \
2526 {"$4", RTYPE_NUM | 4}, \
2527 {"$5", RTYPE_NUM | 5}, \
2528 {"$6", RTYPE_NUM | 6}, \
2529 {"$7", RTYPE_NUM | 7}, \
2530 {"$8", RTYPE_NUM | 8}, \
2531 {"$9", RTYPE_NUM | 9}, \
2532 {"$10", RTYPE_NUM | 10}, \
2533 {"$11", RTYPE_NUM | 11}, \
2534 {"$12", RTYPE_NUM | 12}, \
2535 {"$13", RTYPE_NUM | 13}, \
2536 {"$14", RTYPE_NUM | 14}, \
2537 {"$15", RTYPE_NUM | 15}, \
2538 {"$16", RTYPE_NUM | 16}, \
2539 {"$17", RTYPE_NUM | 17}, \
2540 {"$18", RTYPE_NUM | 18}, \
2541 {"$19", RTYPE_NUM | 19}, \
2542 {"$20", RTYPE_NUM | 20}, \
2543 {"$21", RTYPE_NUM | 21}, \
2544 {"$22", RTYPE_NUM | 22}, \
2545 {"$23", RTYPE_NUM | 23}, \
2546 {"$24", RTYPE_NUM | 24}, \
2547 {"$25", RTYPE_NUM | 25}, \
2548 {"$26", RTYPE_NUM | 26}, \
2549 {"$27", RTYPE_NUM | 27}, \
2550 {"$28", RTYPE_NUM | 28}, \
2551 {"$29", RTYPE_NUM | 29}, \
2552 {"$30", RTYPE_NUM | 30}, \
2553 {"$31", RTYPE_NUM | 31}
2555 #define FPU_REGISTER_NAMES \
2556 {"$f0", RTYPE_FPU | 0}, \
2557 {"$f1", RTYPE_FPU | 1}, \
2558 {"$f2", RTYPE_FPU | 2}, \
2559 {"$f3", RTYPE_FPU | 3}, \
2560 {"$f4", RTYPE_FPU | 4}, \
2561 {"$f5", RTYPE_FPU | 5}, \
2562 {"$f6", RTYPE_FPU | 6}, \
2563 {"$f7", RTYPE_FPU | 7}, \
2564 {"$f8", RTYPE_FPU | 8}, \
2565 {"$f9", RTYPE_FPU | 9}, \
2566 {"$f10", RTYPE_FPU | 10}, \
2567 {"$f11", RTYPE_FPU | 11}, \
2568 {"$f12", RTYPE_FPU | 12}, \
2569 {"$f13", RTYPE_FPU | 13}, \
2570 {"$f14", RTYPE_FPU | 14}, \
2571 {"$f15", RTYPE_FPU | 15}, \
2572 {"$f16", RTYPE_FPU | 16}, \
2573 {"$f17", RTYPE_FPU | 17}, \
2574 {"$f18", RTYPE_FPU | 18}, \
2575 {"$f19", RTYPE_FPU | 19}, \
2576 {"$f20", RTYPE_FPU | 20}, \
2577 {"$f21", RTYPE_FPU | 21}, \
2578 {"$f22", RTYPE_FPU | 22}, \
2579 {"$f23", RTYPE_FPU | 23}, \
2580 {"$f24", RTYPE_FPU | 24}, \
2581 {"$f25", RTYPE_FPU | 25}, \
2582 {"$f26", RTYPE_FPU | 26}, \
2583 {"$f27", RTYPE_FPU | 27}, \
2584 {"$f28", RTYPE_FPU | 28}, \
2585 {"$f29", RTYPE_FPU | 29}, \
2586 {"$f30", RTYPE_FPU | 30}, \
2587 {"$f31", RTYPE_FPU | 31}
2589 #define FPU_CONDITION_CODE_NAMES \
2590 {"$fcc0", RTYPE_FCC | 0}, \
2591 {"$fcc1", RTYPE_FCC | 1}, \
2592 {"$fcc2", RTYPE_FCC | 2}, \
2593 {"$fcc3", RTYPE_FCC | 3}, \
2594 {"$fcc4", RTYPE_FCC | 4}, \
2595 {"$fcc5", RTYPE_FCC | 5}, \
2596 {"$fcc6", RTYPE_FCC | 6}, \
2597 {"$fcc7", RTYPE_FCC | 7}
2599 #define COPROC_CONDITION_CODE_NAMES \
2600 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2601 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2602 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2603 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2604 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2605 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2606 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2607 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2609 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2610 {"$a4", RTYPE_GP | 8}, \
2611 {"$a5", RTYPE_GP | 9}, \
2612 {"$a6", RTYPE_GP | 10}, \
2613 {"$a7", RTYPE_GP | 11}, \
2614 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2615 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2616 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2617 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2618 {"$t0", RTYPE_GP | 12}, \
2619 {"$t1", RTYPE_GP | 13}, \
2620 {"$t2", RTYPE_GP | 14}, \
2621 {"$t3", RTYPE_GP | 15}
2623 #define O32_SYMBOLIC_REGISTER_NAMES \
2624 {"$t0", RTYPE_GP | 8}, \
2625 {"$t1", RTYPE_GP | 9}, \
2626 {"$t2", RTYPE_GP | 10}, \
2627 {"$t3", RTYPE_GP | 11}, \
2628 {"$t4", RTYPE_GP | 12}, \
2629 {"$t5", RTYPE_GP | 13}, \
2630 {"$t6", RTYPE_GP | 14}, \
2631 {"$t7", RTYPE_GP | 15}, \
2632 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2633 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2634 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2635 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2637 /* Remaining symbolic register names */
2638 #define SYMBOLIC_REGISTER_NAMES \
2639 {"$zero", RTYPE_GP | 0}, \
2640 {"$at", RTYPE_GP | 1}, \
2641 {"$AT", RTYPE_GP | 1}, \
2642 {"$v0", RTYPE_GP | 2}, \
2643 {"$v1", RTYPE_GP | 3}, \
2644 {"$a0", RTYPE_GP | 4}, \
2645 {"$a1", RTYPE_GP | 5}, \
2646 {"$a2", RTYPE_GP | 6}, \
2647 {"$a3", RTYPE_GP | 7}, \
2648 {"$s0", RTYPE_GP | 16}, \
2649 {"$s1", RTYPE_GP | 17}, \
2650 {"$s2", RTYPE_GP | 18}, \
2651 {"$s3", RTYPE_GP | 19}, \
2652 {"$s4", RTYPE_GP | 20}, \
2653 {"$s5", RTYPE_GP | 21}, \
2654 {"$s6", RTYPE_GP | 22}, \
2655 {"$s7", RTYPE_GP | 23}, \
2656 {"$t8", RTYPE_GP | 24}, \
2657 {"$t9", RTYPE_GP | 25}, \
2658 {"$k0", RTYPE_GP | 26}, \
2659 {"$kt0", RTYPE_GP | 26}, \
2660 {"$k1", RTYPE_GP | 27}, \
2661 {"$kt1", RTYPE_GP | 27}, \
2662 {"$gp", RTYPE_GP | 28}, \
2663 {"$sp", RTYPE_GP | 29}, \
2664 {"$s8", RTYPE_GP | 30}, \
2665 {"$fp", RTYPE_GP | 30}, \
2666 {"$ra", RTYPE_GP | 31}
2668 #define MIPS16_SPECIAL_REGISTER_NAMES \
2669 {"$pc", RTYPE_PC | 0}
2671 #define MDMX_VECTOR_REGISTER_NAMES \
2672 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2673 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2674 {"$v2", RTYPE_VEC | 2}, \
2675 {"$v3", RTYPE_VEC | 3}, \
2676 {"$v4", RTYPE_VEC | 4}, \
2677 {"$v5", RTYPE_VEC | 5}, \
2678 {"$v6", RTYPE_VEC | 6}, \
2679 {"$v7", RTYPE_VEC | 7}, \
2680 {"$v8", RTYPE_VEC | 8}, \
2681 {"$v9", RTYPE_VEC | 9}, \
2682 {"$v10", RTYPE_VEC | 10}, \
2683 {"$v11", RTYPE_VEC | 11}, \
2684 {"$v12", RTYPE_VEC | 12}, \
2685 {"$v13", RTYPE_VEC | 13}, \
2686 {"$v14", RTYPE_VEC | 14}, \
2687 {"$v15", RTYPE_VEC | 15}, \
2688 {"$v16", RTYPE_VEC | 16}, \
2689 {"$v17", RTYPE_VEC | 17}, \
2690 {"$v18", RTYPE_VEC | 18}, \
2691 {"$v19", RTYPE_VEC | 19}, \
2692 {"$v20", RTYPE_VEC | 20}, \
2693 {"$v21", RTYPE_VEC | 21}, \
2694 {"$v22", RTYPE_VEC | 22}, \
2695 {"$v23", RTYPE_VEC | 23}, \
2696 {"$v24", RTYPE_VEC | 24}, \
2697 {"$v25", RTYPE_VEC | 25}, \
2698 {"$v26", RTYPE_VEC | 26}, \
2699 {"$v27", RTYPE_VEC | 27}, \
2700 {"$v28", RTYPE_VEC | 28}, \
2701 {"$v29", RTYPE_VEC | 29}, \
2702 {"$v30", RTYPE_VEC | 30}, \
2703 {"$v31", RTYPE_VEC | 31}
2705 #define R5900_I_NAMES \
2706 {"$I", RTYPE_R5900_I | 0}
2708 #define R5900_Q_NAMES \
2709 {"$Q", RTYPE_R5900_Q | 0}
2711 #define R5900_R_NAMES \
2712 {"$R", RTYPE_R5900_R | 0}
2714 #define R5900_ACC_NAMES \
2715 {"$ACC", RTYPE_R5900_ACC | 0 }
2717 #define MIPS_DSP_ACCUMULATOR_NAMES \
2718 {"$ac0", RTYPE_ACC | 0}, \
2719 {"$ac1", RTYPE_ACC | 1}, \
2720 {"$ac2", RTYPE_ACC | 2}, \
2721 {"$ac3", RTYPE_ACC | 3}
2723 static const struct regname reg_names[] = {
2724 GENERIC_REGISTER_NUMBERS,
2726 FPU_CONDITION_CODE_NAMES,
2727 COPROC_CONDITION_CODE_NAMES,
2729 /* The $txx registers depends on the abi,
2730 these will be added later into the symbol table from
2731 one of the tables below once mips_abi is set after
2732 parsing of arguments from the command line. */
2733 SYMBOLIC_REGISTER_NAMES,
2735 MIPS16_SPECIAL_REGISTER_NAMES,
2736 MDMX_VECTOR_REGISTER_NAMES,
2741 MIPS_DSP_ACCUMULATOR_NAMES,
2745 static const struct regname reg_names_o32[] = {
2746 O32_SYMBOLIC_REGISTER_NAMES,
2750 static const struct regname reg_names_n32n64[] = {
2751 N32N64_SYMBOLIC_REGISTER_NAMES,
2755 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2756 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2757 of these register symbols, return the associated vector register,
2758 otherwise return SYMVAL itself. */
2761 mips_prefer_vec_regno (unsigned int symval)
2763 if ((symval & -2) == (RTYPE_GP | 2))
2764 return RTYPE_VEC | (symval & 1);
2768 /* Return true if string [S, E) is a valid register name, storing its
2769 symbol value in *SYMVAL_PTR if so. */
2772 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2777 /* Terminate name. */
2781 /* Look up the name. */
2782 symbol = symbol_find (s);
2785 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2788 *symval_ptr = S_GET_VALUE (symbol);
2792 /* Return true if the string at *SPTR is a valid register name. Allow it
2793 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2796 When returning true, move *SPTR past the register, store the
2797 register's symbol value in *SYMVAL_PTR and the channel mask in
2798 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2799 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2800 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2803 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2804 unsigned int *channels_ptr)
2808 unsigned int channels, symval, bit;
2810 /* Find end of name. */
2812 if (is_name_beginner (*e))
2814 while (is_part_of_name (*e))
2818 if (!mips_parse_register_1 (s, e, &symval))
2823 /* Eat characters from the end of the string that are valid
2824 channel suffixes. The preceding register must be $ACC or
2825 end with a digit, so there is no ambiguity. */
2828 for (q = "wzyx"; *q; q++, bit <<= 1)
2829 if (m > s && m[-1] == *q)
2836 || !mips_parse_register_1 (s, m, &symval)
2837 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2842 *symval_ptr = symval;
2844 *channels_ptr = channels;
2848 /* Check if SPTR points at a valid register specifier according to TYPES.
2849 If so, then return 1, advance S to consume the specifier and store
2850 the register's number in REGNOP, otherwise return 0. */
2853 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2857 if (mips_parse_register (s, ®no, NULL))
2859 if (types & RTYPE_VEC)
2860 regno = mips_prefer_vec_regno (regno);
2869 as_warn (_("unrecognized register name `%s'"), *s);
2874 return regno <= RNUM_MASK;
2877 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2878 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2881 mips_parse_vu0_channels (char *s, unsigned int *channels)
2886 for (i = 0; i < 4; i++)
2887 if (*s == "xyzw"[i])
2889 *channels |= 1 << (3 - i);
2895 /* Token types for parsed operand lists. */
2896 enum mips_operand_token_type {
2897 /* A plain register, e.g. $f2. */
2900 /* A 4-bit XYZW channel mask. */
2903 /* A constant vector index, e.g. [1]. */
2906 /* A register vector index, e.g. [$2]. */
2909 /* A continuous range of registers, e.g. $s0-$s4. */
2912 /* A (possibly relocated) expression. */
2915 /* A floating-point value. */
2918 /* A single character. This can be '(', ')' or ',', but '(' only appears
2922 /* A doubled character, either "--" or "++". */
2925 /* The end of the operand list. */
2929 /* A parsed operand token. */
2930 struct mips_operand_token
2932 /* The type of token. */
2933 enum mips_operand_token_type type;
2936 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2939 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2940 unsigned int channels;
2942 /* The integer value of an OT_INTEGER_INDEX. */
2945 /* The two register symbol values involved in an OT_REG_RANGE. */
2947 unsigned int regno1;
2948 unsigned int regno2;
2951 /* The value of an OT_INTEGER. The value is represented as an
2952 expression and the relocation operators that were applied to
2953 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2954 relocation operators were used. */
2957 bfd_reloc_code_real_type relocs[3];
2960 /* The binary data for an OT_FLOAT constant, and the number of bytes
2963 unsigned char data[8];
2967 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2972 /* An obstack used to construct lists of mips_operand_tokens. */
2973 static struct obstack mips_operand_tokens;
2975 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2978 mips_add_token (struct mips_operand_token *token,
2979 enum mips_operand_token_type type)
2982 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2985 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2986 and OT_REG tokens for them if so, and return a pointer to the first
2987 unconsumed character. Return null otherwise. */
2990 mips_parse_base_start (char *s)
2992 struct mips_operand_token token;
2993 unsigned int regno, channels;
2994 bfd_boolean decrement_p;
3000 SKIP_SPACE_TABS (s);
3002 /* Only match "--" as part of a base expression. In other contexts "--X"
3003 is a double negative. */
3004 decrement_p = (s[0] == '-' && s[1] == '-');
3008 SKIP_SPACE_TABS (s);
3011 /* Allow a channel specifier because that leads to better error messages
3012 than treating something like "$vf0x++" as an expression. */
3013 if (!mips_parse_register (&s, ®no, &channels))
3017 mips_add_token (&token, OT_CHAR);
3022 mips_add_token (&token, OT_DOUBLE_CHAR);
3025 token.u.regno = regno;
3026 mips_add_token (&token, OT_REG);
3030 token.u.channels = channels;
3031 mips_add_token (&token, OT_CHANNELS);
3034 /* For consistency, only match "++" as part of base expressions too. */
3035 SKIP_SPACE_TABS (s);
3036 if (s[0] == '+' && s[1] == '+')
3040 mips_add_token (&token, OT_DOUBLE_CHAR);
3046 /* Parse one or more tokens from S. Return a pointer to the first
3047 unconsumed character on success. Return null if an error was found
3048 and store the error text in insn_error. FLOAT_FORMAT is as for
3049 mips_parse_arguments. */
3052 mips_parse_argument_token (char *s, char float_format)
3054 char *end, *save_in;
3056 unsigned int regno1, regno2, channels;
3057 struct mips_operand_token token;
3059 /* First look for "($reg", since we want to treat that as an
3060 OT_CHAR and OT_REG rather than an expression. */
3061 end = mips_parse_base_start (s);
3065 /* Handle other characters that end up as OT_CHARs. */
3066 if (*s == ')' || *s == ',')
3069 mips_add_token (&token, OT_CHAR);
3074 /* Handle tokens that start with a register. */
3075 if (mips_parse_register (&s, ®no1, &channels))
3079 /* A register and a VU0 channel suffix. */
3080 token.u.regno = regno1;
3081 mips_add_token (&token, OT_REG);
3083 token.u.channels = channels;
3084 mips_add_token (&token, OT_CHANNELS);
3088 SKIP_SPACE_TABS (s);
3091 /* A register range. */
3093 SKIP_SPACE_TABS (s);
3094 if (!mips_parse_register (&s, ®no2, NULL))
3096 set_insn_error (0, _("invalid register range"));
3100 token.u.reg_range.regno1 = regno1;
3101 token.u.reg_range.regno2 = regno2;
3102 mips_add_token (&token, OT_REG_RANGE);
3106 /* Add the register itself. */
3107 token.u.regno = regno1;
3108 mips_add_token (&token, OT_REG);
3110 /* Check for a vector index. */
3114 SKIP_SPACE_TABS (s);
3115 if (mips_parse_register (&s, &token.u.regno, NULL))
3116 mips_add_token (&token, OT_REG_INDEX);
3119 expressionS element;
3121 my_getExpression (&element, s);
3122 if (element.X_op != O_constant)
3124 set_insn_error (0, _("vector element must be constant"));
3128 token.u.index = element.X_add_number;
3129 mips_add_token (&token, OT_INTEGER_INDEX);
3131 SKIP_SPACE_TABS (s);
3134 set_insn_error (0, _("missing `]'"));
3144 /* First try to treat expressions as floats. */
3145 save_in = input_line_pointer;
3146 input_line_pointer = s;
3147 err = md_atof (float_format, (char *) token.u.flt.data,
3148 &token.u.flt.length);
3149 end = input_line_pointer;
3150 input_line_pointer = save_in;
3153 set_insn_error (0, err);
3158 mips_add_token (&token, OT_FLOAT);
3163 /* Treat everything else as an integer expression. */
3164 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3165 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3166 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3167 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3169 mips_add_token (&token, OT_INTEGER);
3173 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3174 if expressions should be treated as 32-bit floating-point constants,
3175 'd' if they should be treated as 64-bit floating-point constants,
3176 or 0 if they should be treated as integer expressions (the usual case).
3178 Return a list of tokens on success, otherwise return 0. The caller
3179 must obstack_free the list after use. */
3181 static struct mips_operand_token *
3182 mips_parse_arguments (char *s, char float_format)
3184 struct mips_operand_token token;
3186 SKIP_SPACE_TABS (s);
3189 s = mips_parse_argument_token (s, float_format);
3192 obstack_free (&mips_operand_tokens,
3193 obstack_finish (&mips_operand_tokens));
3196 SKIP_SPACE_TABS (s);
3198 mips_add_token (&token, OT_END);
3199 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3202 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3203 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3206 is_opcode_valid (const struct mips_opcode *mo)
3208 int isa = mips_opts.isa;
3209 int ase = mips_opts.ase;
3213 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3214 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3215 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3216 ase |= mips_ases[i].flags64;
3218 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3221 /* Check whether the instruction or macro requires single-precision or
3222 double-precision floating-point support. Note that this information is
3223 stored differently in the opcode table for insns and macros. */
3224 if (mo->pinfo == INSN_MACRO)
3226 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3227 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3231 fp_s = mo->pinfo & FP_S;
3232 fp_d = mo->pinfo & FP_D;
3235 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3238 if (fp_s && mips_opts.soft_float)
3244 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3245 selected ISA and architecture. */
3248 is_opcode_valid_16 (const struct mips_opcode *mo)
3250 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3253 /* Return TRUE if the size of the microMIPS opcode MO matches one
3254 explicitly requested. Always TRUE in the standard MIPS mode. */
3257 is_size_valid (const struct mips_opcode *mo)
3259 if (!mips_opts.micromips)
3262 if (mips_opts.insn32)
3264 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3266 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3269 if (!forced_insn_length)
3271 if (mo->pinfo == INSN_MACRO)
3273 return forced_insn_length == micromips_insn_length (mo);
3276 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3277 of the preceding instruction. Always TRUE in the standard MIPS mode.
3279 We don't accept macros in 16-bit delay slots to avoid a case where
3280 a macro expansion fails because it relies on a preceding 32-bit real
3281 instruction to have matched and does not handle the operands correctly.
3282 The only macros that may expand to 16-bit instructions are JAL that
3283 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3284 and BGT (that likewise cannot be placed in a delay slot) that decay to
3285 a NOP. In all these cases the macros precede any corresponding real
3286 instruction definitions in the opcode table, so they will match in the
3287 second pass where the size of the delay slot is ignored and therefore
3288 produce correct code. */
3291 is_delay_slot_valid (const struct mips_opcode *mo)
3293 if (!mips_opts.micromips)
3296 if (mo->pinfo == INSN_MACRO)
3297 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3298 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3299 && micromips_insn_length (mo) != 4)
3301 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3302 && micromips_insn_length (mo) != 2)
3308 /* For consistency checking, verify that all bits of OPCODE are specified
3309 either by the match/mask part of the instruction definition, or by the
3310 operand list. Also build up a list of operands in OPERANDS.
3312 INSN_BITS says which bits of the instruction are significant.
3313 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3314 provides the mips_operand description of each operand. DECODE_OPERAND
3315 is null for MIPS16 instructions. */
3318 validate_mips_insn (const struct mips_opcode *opcode,
3319 unsigned long insn_bits,
3320 const struct mips_operand *(*decode_operand) (const char *),
3321 struct mips_operand_array *operands)
3324 unsigned long used_bits, doubled, undefined, opno, mask;
3325 const struct mips_operand *operand;
3327 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3328 if ((mask & opcode->match) != opcode->match)
3330 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3331 opcode->name, opcode->args);
3336 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3337 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3338 for (s = opcode->args; *s; ++s)
3351 if (!decode_operand)
3352 operand = decode_mips16_operand (*s, FALSE);
3354 operand = decode_operand (s);
3355 if (!operand && opcode->pinfo != INSN_MACRO)
3357 as_bad (_("internal: unknown operand type: %s %s"),
3358 opcode->name, opcode->args);
3361 gas_assert (opno < MAX_OPERANDS);
3362 operands->operand[opno] = operand;
3363 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3365 used_bits = mips_insert_operand (operand, used_bits, -1);
3366 if (operand->type == OP_MDMX_IMM_REG)
3367 /* Bit 5 is the format selector (OB vs QH). The opcode table
3368 has separate entries for each format. */
3369 used_bits &= ~(1 << (operand->lsb + 5));
3370 if (operand->type == OP_ENTRY_EXIT_LIST)
3371 used_bits &= ~(mask & 0x700);
3373 /* Skip prefix characters. */
3374 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3379 doubled = used_bits & mask & insn_bits;
3382 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3383 " %s %s"), doubled, opcode->name, opcode->args);
3387 undefined = ~used_bits & insn_bits;
3388 if (opcode->pinfo != INSN_MACRO && undefined)
3390 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3391 undefined, opcode->name, opcode->args);
3394 used_bits &= ~insn_bits;
3397 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3398 used_bits, opcode->name, opcode->args);
3404 /* The MIPS16 version of validate_mips_insn. */
3407 validate_mips16_insn (const struct mips_opcode *opcode,
3408 struct mips_operand_array *operands)
3410 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3412 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3413 instruction. Use TMP to describe the full instruction. */
3414 struct mips_opcode tmp;
3419 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3421 return validate_mips_insn (opcode, 0xffff, 0, operands);
3424 /* The microMIPS version of validate_mips_insn. */
3427 validate_micromips_insn (const struct mips_opcode *opc,
3428 struct mips_operand_array *operands)
3430 unsigned long insn_bits;
3431 unsigned long major;
3432 unsigned int length;
3434 if (opc->pinfo == INSN_MACRO)
3435 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3438 length = micromips_insn_length (opc);
3439 if (length != 2 && length != 4)
3441 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3442 "%s %s"), length, opc->name, opc->args);
3445 major = opc->match >> (10 + 8 * (length - 2));
3446 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3447 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3449 as_bad (_("internal error: bad microMIPS opcode "
3450 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3454 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3455 insn_bits = 1 << 4 * length;
3456 insn_bits <<= 4 * length;
3458 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3462 /* This function is called once, at assembler startup time. It should set up
3463 all the tables, etc. that the MD part of the assembler will need. */
3468 const char *retval = NULL;
3472 if (mips_pic != NO_PIC)
3474 if (g_switch_seen && g_switch_value != 0)
3475 as_bad (_("-G may not be used in position-independent code"));
3478 else if (mips_abicalls)
3480 if (g_switch_seen && g_switch_value != 0)
3481 as_bad (_("-G may not be used with abicalls"));
3485 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3486 as_warn (_("could not set architecture and machine"));
3488 op_hash = hash_new ();
3490 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3491 for (i = 0; i < NUMOPCODES;)
3493 const char *name = mips_opcodes[i].name;
3495 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3498 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3499 mips_opcodes[i].name, retval);
3500 /* Probably a memory allocation problem? Give up now. */
3501 as_fatal (_("broken assembler, no assembly attempted"));
3505 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3506 decode_mips_operand, &mips_operands[i]))
3508 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3510 create_insn (&nop_insn, mips_opcodes + i);
3511 if (mips_fix_loongson2f_nop)
3512 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3513 nop_insn.fixed_p = 1;
3517 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3520 mips16_op_hash = hash_new ();
3521 mips16_operands = XCNEWVEC (struct mips_operand_array,
3522 bfd_mips16_num_opcodes);
3525 while (i < bfd_mips16_num_opcodes)
3527 const char *name = mips16_opcodes[i].name;
3529 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3531 as_fatal (_("internal: can't hash `%s': %s"),
3532 mips16_opcodes[i].name, retval);
3535 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3537 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3539 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3540 mips16_nop_insn.fixed_p = 1;
3544 while (i < bfd_mips16_num_opcodes
3545 && strcmp (mips16_opcodes[i].name, name) == 0);
3548 micromips_op_hash = hash_new ();
3549 micromips_operands = XCNEWVEC (struct mips_operand_array,
3550 bfd_micromips_num_opcodes);
3553 while (i < bfd_micromips_num_opcodes)
3555 const char *name = micromips_opcodes[i].name;
3557 retval = hash_insert (micromips_op_hash, name,
3558 (void *) µmips_opcodes[i]);
3560 as_fatal (_("internal: can't hash `%s': %s"),
3561 micromips_opcodes[i].name, retval);
3564 struct mips_cl_insn *micromips_nop_insn;
3566 if (!validate_micromips_insn (µmips_opcodes[i],
3567 µmips_operands[i]))
3570 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3572 if (micromips_insn_length (micromips_opcodes + i) == 2)
3573 micromips_nop_insn = µmips_nop16_insn;
3574 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3575 micromips_nop_insn = µmips_nop32_insn;
3579 if (micromips_nop_insn->insn_mo == NULL
3580 && strcmp (name, "nop") == 0)
3582 create_insn (micromips_nop_insn, micromips_opcodes + i);
3583 micromips_nop_insn->fixed_p = 1;
3587 while (++i < bfd_micromips_num_opcodes
3588 && strcmp (micromips_opcodes[i].name, name) == 0);
3592 as_fatal (_("broken assembler, no assembly attempted"));
3594 /* We add all the general register names to the symbol table. This
3595 helps us detect invalid uses of them. */
3596 for (i = 0; reg_names[i].name; i++)
3597 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3598 reg_names[i].num, /* & RNUM_MASK, */
3599 &zero_address_frag));
3601 for (i = 0; reg_names_n32n64[i].name; i++)
3602 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3603 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3604 &zero_address_frag));
3606 for (i = 0; reg_names_o32[i].name; i++)
3607 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3608 reg_names_o32[i].num, /* & RNUM_MASK, */
3609 &zero_address_frag));
3611 for (i = 0; i < 32; i++)
3615 /* R5900 VU0 floating-point register. */
3616 sprintf (regname, "$vf%d", i);
3617 symbol_table_insert (symbol_new (regname, reg_section,
3618 RTYPE_VF | i, &zero_address_frag));
3620 /* R5900 VU0 integer register. */
3621 sprintf (regname, "$vi%d", i);
3622 symbol_table_insert (symbol_new (regname, reg_section,
3623 RTYPE_VI | i, &zero_address_frag));
3626 sprintf (regname, "$w%d", i);
3627 symbol_table_insert (symbol_new (regname, reg_section,
3628 RTYPE_MSA | i, &zero_address_frag));
3631 obstack_init (&mips_operand_tokens);
3633 mips_no_prev_insn ();
3636 mips_cprmask[0] = 0;
3637 mips_cprmask[1] = 0;
3638 mips_cprmask[2] = 0;
3639 mips_cprmask[3] = 0;
3641 /* set the default alignment for the text section (2**2) */
3642 record_alignment (text_section, 2);
3644 bfd_set_gp_size (stdoutput, g_switch_value);
3646 /* On a native system other than VxWorks, sections must be aligned
3647 to 16 byte boundaries. When configured for an embedded ELF
3648 target, we don't bother. */
3649 if (strncmp (TARGET_OS, "elf", 3) != 0
3650 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3652 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3653 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3654 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3657 /* Create a .reginfo section for register masks and a .mdebug
3658 section for debugging information. */
3666 subseg = now_subseg;
3668 /* The ABI says this section should be loaded so that the
3669 running program can access it. However, we don't load it
3670 if we are configured for an embedded target */
3671 flags = SEC_READONLY | SEC_DATA;
3672 if (strncmp (TARGET_OS, "elf", 3) != 0)
3673 flags |= SEC_ALLOC | SEC_LOAD;
3675 if (mips_abi != N64_ABI)
3677 sec = subseg_new (".reginfo", (subsegT) 0);
3679 bfd_set_section_flags (stdoutput, sec, flags);
3680 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3682 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3686 /* The 64-bit ABI uses a .MIPS.options section rather than
3687 .reginfo section. */
3688 sec = subseg_new (".MIPS.options", (subsegT) 0);
3689 bfd_set_section_flags (stdoutput, sec, flags);
3690 bfd_set_section_alignment (stdoutput, sec, 3);
3692 /* Set up the option header. */
3694 Elf_Internal_Options opthdr;
3697 opthdr.kind = ODK_REGINFO;
3698 opthdr.size = (sizeof (Elf_External_Options)
3699 + sizeof (Elf64_External_RegInfo));
3702 f = frag_more (sizeof (Elf_External_Options));
3703 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3704 (Elf_External_Options *) f);
3706 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3710 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3711 bfd_set_section_flags (stdoutput, sec,
3712 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3713 bfd_set_section_alignment (stdoutput, sec, 3);
3714 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3716 if (ECOFF_DEBUGGING)
3718 sec = subseg_new (".mdebug", (subsegT) 0);
3719 (void) bfd_set_section_flags (stdoutput, sec,
3720 SEC_HAS_CONTENTS | SEC_READONLY);
3721 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3723 else if (mips_flag_pdr)
3725 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3726 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3727 SEC_READONLY | SEC_RELOC
3729 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3732 subseg_set (seg, subseg);
3735 if (mips_fix_vr4120)
3736 init_vr4120_conflicts ();
3740 fpabi_incompatible_with (int fpabi, const char *what)
3742 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3743 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3747 fpabi_requires (int fpabi, const char *what)
3749 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3750 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3753 /* Check -mabi and register sizes against the specified FP ABI. */
3755 check_fpabi (int fpabi)
3759 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3760 if (file_mips_opts.soft_float)
3761 fpabi_incompatible_with (fpabi, "softfloat");
3762 else if (file_mips_opts.single_float)
3763 fpabi_incompatible_with (fpabi, "singlefloat");
3764 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3765 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3766 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3767 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3770 case Val_GNU_MIPS_ABI_FP_XX:
3771 if (mips_abi != O32_ABI)
3772 fpabi_requires (fpabi, "-mabi=32");
3773 else if (file_mips_opts.soft_float)
3774 fpabi_incompatible_with (fpabi, "softfloat");
3775 else if (file_mips_opts.single_float)
3776 fpabi_incompatible_with (fpabi, "singlefloat");
3777 else if (file_mips_opts.fp != 0)
3778 fpabi_requires (fpabi, "fp=xx");
3781 case Val_GNU_MIPS_ABI_FP_64A:
3782 case Val_GNU_MIPS_ABI_FP_64:
3783 if (mips_abi != O32_ABI)
3784 fpabi_requires (fpabi, "-mabi=32");
3785 else if (file_mips_opts.soft_float)
3786 fpabi_incompatible_with (fpabi, "softfloat");
3787 else if (file_mips_opts.single_float)
3788 fpabi_incompatible_with (fpabi, "singlefloat");
3789 else if (file_mips_opts.fp != 64)
3790 fpabi_requires (fpabi, "fp=64");
3791 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
3792 fpabi_incompatible_with (fpabi, "nooddspreg");
3793 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
3794 fpabi_requires (fpabi, "nooddspreg");
3797 case Val_GNU_MIPS_ABI_FP_SINGLE:
3798 if (file_mips_opts.soft_float)
3799 fpabi_incompatible_with (fpabi, "softfloat");
3800 else if (!file_mips_opts.single_float)
3801 fpabi_requires (fpabi, "singlefloat");
3804 case Val_GNU_MIPS_ABI_FP_SOFT:
3805 if (!file_mips_opts.soft_float)
3806 fpabi_requires (fpabi, "softfloat");
3809 case Val_GNU_MIPS_ABI_FP_OLD_64:
3810 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3811 Tag_GNU_MIPS_ABI_FP, fpabi);
3814 case Val_GNU_MIPS_ABI_FP_NAN2008:
3815 /* Silently ignore compatibility value. */
3819 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3820 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
3825 /* Perform consistency checks on the current options. */
3828 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
3830 /* Check the size of integer registers agrees with the ABI and ISA. */
3831 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3832 as_bad (_("`gp=64' used with a 32-bit processor"));
3834 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
3835 as_bad (_("`gp=32' used with a 64-bit ABI"));
3837 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
3838 as_bad (_("`gp=64' used with a 32-bit ABI"));
3840 /* Check the size of the float registers agrees with the ABI and ISA. */
3844 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
3845 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3846 else if (opts->single_float == 1)
3847 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3850 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3851 as_bad (_("`fp=64' used with a 32-bit fpu"));
3853 && ABI_NEEDS_32BIT_REGS (mips_abi)
3854 && !ISA_HAS_MXHC1 (opts->isa))
3855 as_warn (_("`fp=64' used with a 32-bit ABI"));
3859 && ABI_NEEDS_64BIT_REGS (mips_abi))
3860 as_warn (_("`fp=32' used with a 64-bit ABI"));
3861 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
3862 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3865 as_bad (_("Unknown size of floating point registers"));
3869 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
3870 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3872 if (opts->micromips == 1 && opts->mips16 == 1)
3873 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3874 else if (ISA_IS_R6 (opts->isa)
3875 && (opts->micromips == 1
3876 || opts->mips16 == 1))
3877 as_fatal (_("`%s' cannot be used with `%s'"),
3878 opts->micromips ? "micromips" : "mips16",
3879 mips_cpu_info_from_isa (opts->isa)->name);
3881 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3882 as_fatal (_("branch relaxation is not supported in `%s'"),
3883 mips_cpu_info_from_isa (opts->isa)->name);
3886 /* Perform consistency checks on the module level options exactly once.
3887 This is a deferred check that happens:
3888 at the first .set directive
3889 or, at the first pseudo op that generates code (inc .dc.a)
3890 or, at the first instruction
3894 file_mips_check_options (void)
3896 const struct mips_cpu_info *arch_info = 0;
3898 if (file_mips_opts_checked)
3901 /* The following code determines the register size.
3902 Similar code was added to GCC 3.3 (see override_options() in
3903 config/mips/mips.c). The GAS and GCC code should be kept in sync
3904 as much as possible. */
3906 if (file_mips_opts.gp < 0)
3908 /* Infer the integer register size from the ABI and processor.
3909 Restrict ourselves to 32-bit registers if that's all the
3910 processor has, or if the ABI cannot handle 64-bit registers. */
3911 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
3912 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3916 if (file_mips_opts.fp < 0)
3918 /* No user specified float register size.
3919 ??? GAS treats single-float processors as though they had 64-bit
3920 float registers (although it complains when double-precision
3921 instructions are used). As things stand, saying they have 32-bit
3922 registers would lead to spurious "register must be even" messages.
3923 So here we assume float registers are never smaller than the
3925 if (file_mips_opts.gp == 64)
3926 /* 64-bit integer registers implies 64-bit float registers. */
3927 file_mips_opts.fp = 64;
3928 else if ((file_mips_opts.ase & FP64_ASES)
3929 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3930 /* Handle ASEs that require 64-bit float registers, if possible. */
3931 file_mips_opts.fp = 64;
3932 else if (ISA_IS_R6 (mips_opts.isa))
3933 /* R6 implies 64-bit float registers. */
3934 file_mips_opts.fp = 64;
3936 /* 32-bit float registers. */
3937 file_mips_opts.fp = 32;
3940 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
3942 /* Disable operations on odd-numbered floating-point registers by default
3943 when using the FPXX ABI. */
3944 if (file_mips_opts.oddspreg < 0)
3946 if (file_mips_opts.fp == 0)
3947 file_mips_opts.oddspreg = 0;
3949 file_mips_opts.oddspreg = 1;
3952 /* End of GCC-shared inference code. */
3954 /* This flag is set when we have a 64-bit capable CPU but use only
3955 32-bit wide registers. Note that EABI does not use it. */
3956 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3957 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
3958 || mips_abi == O32_ABI))
3961 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3962 as_bad (_("trap exception not supported at ISA 1"));
3964 /* If the selected architecture includes support for ASEs, enable
3965 generation of code for them. */
3966 if (file_mips_opts.mips16 == -1)
3967 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
3968 if (file_mips_opts.micromips == -1)
3969 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
3972 if (mips_nan2008 == -1)
3973 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
3974 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
3975 as_fatal (_("`%s' does not support legacy NaN"),
3976 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
3978 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
3979 being selected implicitly. */
3980 if (file_mips_opts.fp != 64)
3981 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
3983 /* If the user didn't explicitly select or deselect a particular ASE,
3984 use the default setting for the CPU. */
3985 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
3987 /* Set up the current options. These may change throughout assembly. */
3988 mips_opts = file_mips_opts;
3990 mips_check_isa_supports_ases ();
3991 mips_check_options (&file_mips_opts, TRUE);
3992 file_mips_opts_checked = TRUE;
3994 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3995 as_warn (_("could not set architecture and machine"));
3999 md_assemble (char *str)
4001 struct mips_cl_insn insn;
4002 bfd_reloc_code_real_type unused_reloc[3]
4003 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4005 file_mips_check_options ();
4007 imm_expr.X_op = O_absent;
4008 offset_expr.X_op = O_absent;
4009 offset_reloc[0] = BFD_RELOC_UNUSED;
4010 offset_reloc[1] = BFD_RELOC_UNUSED;
4011 offset_reloc[2] = BFD_RELOC_UNUSED;
4013 mips_mark_labels ();
4014 mips_assembling_insn = TRUE;
4015 clear_insn_error ();
4017 if (mips_opts.mips16)
4018 mips16_ip (str, &insn);
4021 mips_ip (str, &insn);
4022 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4023 str, insn.insn_opcode));
4027 report_insn_error (str);
4028 else if (insn.insn_mo->pinfo == INSN_MACRO)
4031 if (mips_opts.mips16)
4032 mips16_macro (&insn);
4039 if (offset_expr.X_op != O_absent)
4040 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
4042 append_insn (&insn, NULL, unused_reloc, FALSE);
4045 mips_assembling_insn = FALSE;
4048 /* Convenience functions for abstracting away the differences between
4049 MIPS16 and non-MIPS16 relocations. */
4051 static inline bfd_boolean
4052 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4056 case BFD_RELOC_MIPS16_JMP:
4057 case BFD_RELOC_MIPS16_GPREL:
4058 case BFD_RELOC_MIPS16_GOT16:
4059 case BFD_RELOC_MIPS16_CALL16:
4060 case BFD_RELOC_MIPS16_HI16_S:
4061 case BFD_RELOC_MIPS16_HI16:
4062 case BFD_RELOC_MIPS16_LO16:
4070 static inline bfd_boolean
4071 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4075 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4076 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4077 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4078 case BFD_RELOC_MICROMIPS_GPREL16:
4079 case BFD_RELOC_MICROMIPS_JMP:
4080 case BFD_RELOC_MICROMIPS_HI16:
4081 case BFD_RELOC_MICROMIPS_HI16_S:
4082 case BFD_RELOC_MICROMIPS_LO16:
4083 case BFD_RELOC_MICROMIPS_LITERAL:
4084 case BFD_RELOC_MICROMIPS_GOT16:
4085 case BFD_RELOC_MICROMIPS_CALL16:
4086 case BFD_RELOC_MICROMIPS_GOT_HI16:
4087 case BFD_RELOC_MICROMIPS_GOT_LO16:
4088 case BFD_RELOC_MICROMIPS_CALL_HI16:
4089 case BFD_RELOC_MICROMIPS_CALL_LO16:
4090 case BFD_RELOC_MICROMIPS_SUB:
4091 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4092 case BFD_RELOC_MICROMIPS_GOT_OFST:
4093 case BFD_RELOC_MICROMIPS_GOT_DISP:
4094 case BFD_RELOC_MICROMIPS_HIGHEST:
4095 case BFD_RELOC_MICROMIPS_HIGHER:
4096 case BFD_RELOC_MICROMIPS_SCN_DISP:
4097 case BFD_RELOC_MICROMIPS_JALR:
4105 static inline bfd_boolean
4106 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4108 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4111 static inline bfd_boolean
4112 got16_reloc_p (bfd_reloc_code_real_type reloc)
4114 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4115 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4118 static inline bfd_boolean
4119 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4121 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4122 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4125 static inline bfd_boolean
4126 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4128 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4129 || reloc == BFD_RELOC_MICROMIPS_LO16);
4132 static inline bfd_boolean
4133 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4135 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4138 static inline bfd_boolean
4139 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4141 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4142 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4145 /* Return true if RELOC is a PC-relative relocation that does not have
4146 full address range. */
4148 static inline bfd_boolean
4149 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4153 case BFD_RELOC_16_PCREL_S2:
4154 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4155 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4156 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4157 case BFD_RELOC_MIPS_21_PCREL_S2:
4158 case BFD_RELOC_MIPS_26_PCREL_S2:
4159 case BFD_RELOC_MIPS_18_PCREL_S3:
4160 case BFD_RELOC_MIPS_19_PCREL_S2:
4163 case BFD_RELOC_32_PCREL:
4164 case BFD_RELOC_HI16_S_PCREL:
4165 case BFD_RELOC_LO16_PCREL:
4166 return HAVE_64BIT_ADDRESSES;
4173 /* Return true if the given relocation might need a matching %lo().
4174 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4175 need a matching %lo() when applied to local symbols. */
4177 static inline bfd_boolean
4178 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4180 return (HAVE_IN_PLACE_ADDENDS
4181 && (hi16_reloc_p (reloc)
4182 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4183 all GOT16 relocations evaluate to "G". */
4184 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4187 /* Return the type of %lo() reloc needed by RELOC, given that
4188 reloc_needs_lo_p. */
4190 static inline bfd_reloc_code_real_type
4191 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4193 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4194 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4198 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4201 static inline bfd_boolean
4202 fixup_has_matching_lo_p (fixS *fixp)
4204 return (fixp->fx_next != NULL
4205 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4206 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4207 && fixp->fx_offset == fixp->fx_next->fx_offset);
4210 /* Move all labels in LABELS to the current insertion point. TEXT_P
4211 says whether the labels refer to text or data. */
4214 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
4216 struct insn_label_list *l;
4219 for (l = labels; l != NULL; l = l->next)
4221 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4222 symbol_set_frag (l->label, frag_now);
4223 val = (valueT) frag_now_fix ();
4224 /* MIPS16/microMIPS text labels are stored as odd. */
4225 if (text_p && HAVE_CODE_COMPRESSION)
4227 S_SET_VALUE (l->label, val);
4231 /* Move all labels in insn_labels to the current insertion point
4232 and treat them as text labels. */
4235 mips_move_text_labels (void)
4237 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
4241 s_is_linkonce (symbolS *sym, segT from_seg)
4243 bfd_boolean linkonce = FALSE;
4244 segT symseg = S_GET_SEGMENT (sym);
4246 if (symseg != from_seg && !S_IS_LOCAL (sym))
4248 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
4250 /* The GNU toolchain uses an extension for ELF: a section
4251 beginning with the magic string .gnu.linkonce is a
4252 linkonce section. */
4253 if (strncmp (segment_name (symseg), ".gnu.linkonce",
4254 sizeof ".gnu.linkonce" - 1) == 0)
4260 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4261 linker to handle them specially, such as generating jalx instructions
4262 when needed. We also make them odd for the duration of the assembly,
4263 in order to generate the right sort of code. We will make them even
4264 in the adjust_symtab routine, while leaving them marked. This is
4265 convenient for the debugger and the disassembler. The linker knows
4266 to make them odd again. */
4269 mips_compressed_mark_label (symbolS *label)
4271 gas_assert (HAVE_CODE_COMPRESSION);
4273 if (mips_opts.mips16)
4274 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4276 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4277 if ((S_GET_VALUE (label) & 1) == 0
4278 /* Don't adjust the address if the label is global or weak, or
4279 in a link-once section, since we'll be emitting symbol reloc
4280 references to it which will be patched up by the linker, and
4281 the final value of the symbol may or may not be MIPS16/microMIPS. */
4282 && !S_IS_WEAK (label)
4283 && !S_IS_EXTERNAL (label)
4284 && !s_is_linkonce (label, now_seg))
4285 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4288 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4291 mips_compressed_mark_labels (void)
4293 struct insn_label_list *l;
4295 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4296 mips_compressed_mark_label (l->label);
4299 /* End the current frag. Make it a variant frag and record the
4303 relax_close_frag (void)
4305 mips_macro_warning.first_frag = frag_now;
4306 frag_var (rs_machine_dependent, 0, 0,
4307 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
4308 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4310 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4311 mips_relax.first_fixup = 0;
4314 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4315 See the comment above RELAX_ENCODE for more details. */
4318 relax_start (symbolS *symbol)
4320 gas_assert (mips_relax.sequence == 0);
4321 mips_relax.sequence = 1;
4322 mips_relax.symbol = symbol;
4325 /* Start generating the second version of a relaxable sequence.
4326 See the comment above RELAX_ENCODE for more details. */
4331 gas_assert (mips_relax.sequence == 1);
4332 mips_relax.sequence = 2;
4335 /* End the current relaxable sequence. */
4340 gas_assert (mips_relax.sequence == 2);
4341 relax_close_frag ();
4342 mips_relax.sequence = 0;
4345 /* Return true if IP is a delayed branch or jump. */
4347 static inline bfd_boolean
4348 delayed_branch_p (const struct mips_cl_insn *ip)
4350 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4351 | INSN_COND_BRANCH_DELAY
4352 | INSN_COND_BRANCH_LIKELY)) != 0;
4355 /* Return true if IP is a compact branch or jump. */
4357 static inline bfd_boolean
4358 compact_branch_p (const struct mips_cl_insn *ip)
4360 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4361 | INSN2_COND_BRANCH)) != 0;
4364 /* Return true if IP is an unconditional branch or jump. */
4366 static inline bfd_boolean
4367 uncond_branch_p (const struct mips_cl_insn *ip)
4369 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4370 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4373 /* Return true if IP is a branch-likely instruction. */
4375 static inline bfd_boolean
4376 branch_likely_p (const struct mips_cl_insn *ip)
4378 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4381 /* Return the type of nop that should be used to fill the delay slot
4382 of delayed branch IP. */
4384 static struct mips_cl_insn *
4385 get_delay_slot_nop (const struct mips_cl_insn *ip)
4387 if (mips_opts.micromips
4388 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4389 return µmips_nop32_insn;
4393 /* Return a mask that has bit N set if OPCODE reads the register(s)
4397 insn_read_mask (const struct mips_opcode *opcode)
4399 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4402 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4406 insn_write_mask (const struct mips_opcode *opcode)
4408 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4411 /* Return a mask of the registers specified by operand OPERAND of INSN.
4412 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4416 operand_reg_mask (const struct mips_cl_insn *insn,
4417 const struct mips_operand *operand,
4418 unsigned int type_mask)
4420 unsigned int uval, vsel;
4422 switch (operand->type)
4429 case OP_ADDIUSP_INT:
4430 case OP_ENTRY_EXIT_LIST:
4431 case OP_REPEAT_DEST_REG:
4432 case OP_REPEAT_PREV_REG:
4435 case OP_VU0_MATCH_SUFFIX:
4440 case OP_OPTIONAL_REG:
4442 const struct mips_reg_operand *reg_op;
4444 reg_op = (const struct mips_reg_operand *) operand;
4445 if (!(type_mask & (1 << reg_op->reg_type)))
4447 uval = insn_extract_operand (insn, operand);
4448 return 1 << mips_decode_reg_operand (reg_op, uval);
4453 const struct mips_reg_pair_operand *pair_op;
4455 pair_op = (const struct mips_reg_pair_operand *) operand;
4456 if (!(type_mask & (1 << pair_op->reg_type)))
4458 uval = insn_extract_operand (insn, operand);
4459 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4462 case OP_CLO_CLZ_DEST:
4463 if (!(type_mask & (1 << OP_REG_GP)))
4465 uval = insn_extract_operand (insn, operand);
4466 return (1 << (uval & 31)) | (1 << (uval >> 5));
4469 if (!(type_mask & (1 << OP_REG_GP)))
4471 uval = insn_extract_operand (insn, operand);
4472 gas_assert ((uval & 31) == (uval >> 5));
4473 return 1 << (uval & 31);
4476 case OP_NON_ZERO_REG:
4477 if (!(type_mask & (1 << OP_REG_GP)))
4479 uval = insn_extract_operand (insn, operand);
4480 return 1 << (uval & 31);
4482 case OP_LWM_SWM_LIST:
4485 case OP_SAVE_RESTORE_LIST:
4488 case OP_MDMX_IMM_REG:
4489 if (!(type_mask & (1 << OP_REG_VEC)))
4491 uval = insn_extract_operand (insn, operand);
4493 if ((vsel & 0x18) == 0x18)
4495 return 1 << (uval & 31);
4498 if (!(type_mask & (1 << OP_REG_GP)))
4500 return 1 << insn_extract_operand (insn, operand);
4505 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4506 where bit N of OPNO_MASK is set if operand N should be included.
4507 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4511 insn_reg_mask (const struct mips_cl_insn *insn,
4512 unsigned int type_mask, unsigned int opno_mask)
4514 unsigned int opno, reg_mask;
4518 while (opno_mask != 0)
4521 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4528 /* Return the mask of core registers that IP reads. */
4531 gpr_read_mask (const struct mips_cl_insn *ip)
4533 unsigned long pinfo, pinfo2;
4536 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4537 pinfo = ip->insn_mo->pinfo;
4538 pinfo2 = ip->insn_mo->pinfo2;
4539 if (pinfo & INSN_UDI)
4541 /* UDI instructions have traditionally been assumed to read RS
4543 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4544 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4546 if (pinfo & INSN_READ_GPR_24)
4548 if (pinfo2 & INSN2_READ_GPR_16)
4550 if (pinfo2 & INSN2_READ_SP)
4552 if (pinfo2 & INSN2_READ_GPR_31)
4554 /* Don't include register 0. */
4558 /* Return the mask of core registers that IP writes. */
4561 gpr_write_mask (const struct mips_cl_insn *ip)
4563 unsigned long pinfo, pinfo2;
4566 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4567 pinfo = ip->insn_mo->pinfo;
4568 pinfo2 = ip->insn_mo->pinfo2;
4569 if (pinfo & INSN_WRITE_GPR_24)
4571 if (pinfo & INSN_WRITE_GPR_31)
4573 if (pinfo & INSN_UDI)
4574 /* UDI instructions have traditionally been assumed to write to RD. */
4575 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4576 if (pinfo2 & INSN2_WRITE_SP)
4578 /* Don't include register 0. */
4582 /* Return the mask of floating-point registers that IP reads. */
4585 fpr_read_mask (const struct mips_cl_insn *ip)
4587 unsigned long pinfo;
4590 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4591 | (1 << OP_REG_MSA)),
4592 insn_read_mask (ip->insn_mo));
4593 pinfo = ip->insn_mo->pinfo;
4594 /* Conservatively treat all operands to an FP_D instruction are doubles.
4595 (This is overly pessimistic for things like cvt.d.s.) */
4596 if (FPR_SIZE != 64 && (pinfo & FP_D))
4601 /* Return the mask of floating-point registers that IP writes. */
4604 fpr_write_mask (const struct mips_cl_insn *ip)
4606 unsigned long pinfo;
4609 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4610 | (1 << OP_REG_MSA)),
4611 insn_write_mask (ip->insn_mo));
4612 pinfo = ip->insn_mo->pinfo;
4613 /* Conservatively treat all operands to an FP_D instruction are doubles.
4614 (This is overly pessimistic for things like cvt.s.d.) */
4615 if (FPR_SIZE != 64 && (pinfo & FP_D))
4620 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4621 Check whether that is allowed. */
4624 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4626 const char *s = insn->name;
4627 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4629 && mips_opts.oddspreg;
4631 if (insn->pinfo == INSN_MACRO)
4632 /* Let a macro pass, we'll catch it later when it is expanded. */
4635 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4636 otherwise it depends on oddspreg. */
4637 if ((insn->pinfo & FP_S)
4638 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4639 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4640 return FPR_SIZE == 32 || oddspreg;
4642 /* Allow odd registers for single-precision ops and double-precision if the
4643 floating-point registers are 64-bit wide. */
4644 switch (insn->pinfo & (FP_S | FP_D))
4650 return FPR_SIZE == 64;
4655 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4656 s = strchr (insn->name, '.');
4657 if (s != NULL && opnum == 2)
4658 s = strchr (s + 1, '.');
4659 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4662 return FPR_SIZE == 64;
4665 /* Information about an instruction argument that we're trying to match. */
4666 struct mips_arg_info
4668 /* The instruction so far. */
4669 struct mips_cl_insn *insn;
4671 /* The first unconsumed operand token. */
4672 struct mips_operand_token *token;
4674 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4677 /* The 1-based argument number, for error reporting. This does not
4678 count elided optional registers, etc.. */
4681 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4682 unsigned int last_regno;
4684 /* If the first operand was an OP_REG, this is the register that it
4685 specified, otherwise it is ILLEGAL_REG. */
4686 unsigned int dest_regno;
4688 /* The value of the last OP_INT operand. Only used for OP_MSB,
4689 where it gives the lsb position. */
4690 unsigned int last_op_int;
4692 /* If true, match routines should assume that no later instruction
4693 alternative matches and should therefore be as accomodating as
4694 possible. Match routines should not report errors if something
4695 is only invalid for !LAX_MATCH. */
4696 bfd_boolean lax_match;
4698 /* True if a reference to the current AT register was seen. */
4699 bfd_boolean seen_at;
4702 /* Record that the argument is out of range. */
4705 match_out_of_range (struct mips_arg_info *arg)
4707 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4710 /* Record that the argument isn't constant but needs to be. */
4713 match_not_constant (struct mips_arg_info *arg)
4715 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4719 /* Try to match an OT_CHAR token for character CH. Consume the token
4720 and return true on success, otherwise return false. */
4723 match_char (struct mips_arg_info *arg, char ch)
4725 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4735 /* Try to get an expression from the next tokens in ARG. Consume the
4736 tokens and return true on success, storing the expression value in
4737 VALUE and relocation types in R. */
4740 match_expression (struct mips_arg_info *arg, expressionS *value,
4741 bfd_reloc_code_real_type *r)
4743 /* If the next token is a '(' that was parsed as being part of a base
4744 expression, assume we have an elided offset. The later match will fail
4745 if this turns out to be wrong. */
4746 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4748 value->X_op = O_constant;
4749 value->X_add_number = 0;
4750 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4754 /* Reject register-based expressions such as "0+$2" and "(($2))".
4755 For plain registers the default error seems more appropriate. */
4756 if (arg->token->type == OT_INTEGER
4757 && arg->token->u.integer.value.X_op == O_register)
4759 set_insn_error (arg->argnum, _("register value used as expression"));
4763 if (arg->token->type == OT_INTEGER)
4765 *value = arg->token->u.integer.value;
4766 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4772 (arg->argnum, _("operand %d must be an immediate expression"),
4777 /* Try to get a constant expression from the next tokens in ARG. Consume
4778 the tokens and return return true on success, storing the constant value
4779 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4783 match_const_int (struct mips_arg_info *arg, offsetT *value)
4786 bfd_reloc_code_real_type r[3];
4788 if (!match_expression (arg, &ex, r))
4791 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4792 *value = ex.X_add_number;
4795 match_not_constant (arg);
4801 /* Return the RTYPE_* flags for a register operand of type TYPE that
4802 appears in instruction OPCODE. */
4805 convert_reg_type (const struct mips_opcode *opcode,
4806 enum mips_reg_operand_type type)
4811 return RTYPE_NUM | RTYPE_GP;
4814 /* Allow vector register names for MDMX if the instruction is a 64-bit
4815 FPR load, store or move (including moves to and from GPRs). */
4816 if ((mips_opts.ase & ASE_MDMX)
4817 && (opcode->pinfo & FP_D)
4818 && (opcode->pinfo & (INSN_COPROC_MOVE
4819 | INSN_COPROC_MEMORY_DELAY
4822 | INSN_STORE_MEMORY)))
4823 return RTYPE_FPU | RTYPE_VEC;
4827 if (opcode->pinfo & (FP_D | FP_S))
4828 return RTYPE_CCC | RTYPE_FCC;
4832 if (opcode->membership & INSN_5400)
4834 return RTYPE_FPU | RTYPE_VEC;
4840 if (opcode->name[strlen (opcode->name) - 1] == '0')
4841 return RTYPE_NUM | RTYPE_CP0;
4848 return RTYPE_NUM | RTYPE_VI;
4851 return RTYPE_NUM | RTYPE_VF;
4853 case OP_REG_R5900_I:
4854 return RTYPE_R5900_I;
4856 case OP_REG_R5900_Q:
4857 return RTYPE_R5900_Q;
4859 case OP_REG_R5900_R:
4860 return RTYPE_R5900_R;
4862 case OP_REG_R5900_ACC:
4863 return RTYPE_R5900_ACC;
4868 case OP_REG_MSA_CTRL:
4874 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4877 check_regno (struct mips_arg_info *arg,
4878 enum mips_reg_operand_type type, unsigned int regno)
4880 if (AT && type == OP_REG_GP && regno == AT)
4881 arg->seen_at = TRUE;
4883 if (type == OP_REG_FP
4885 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4887 /* This was a warning prior to introducing O32 FPXX and FP64 support
4888 so maintain a warning for FP32 but raise an error for the new
4891 as_warn (_("float register should be even, was %d"), regno);
4893 as_bad (_("float register should be even, was %d"), regno);
4896 if (type == OP_REG_CCC)
4901 name = arg->insn->insn_mo->name;
4902 length = strlen (name);
4903 if ((regno & 1) != 0
4904 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4905 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4906 as_warn (_("condition code register should be even for %s, was %d"),
4909 if ((regno & 3) != 0
4910 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4911 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4916 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4917 a register of type TYPE. Return true on success, storing the register
4918 number in *REGNO and warning about any dubious uses. */
4921 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4922 unsigned int symval, unsigned int *regno)
4924 if (type == OP_REG_VEC)
4925 symval = mips_prefer_vec_regno (symval);
4926 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4929 *regno = symval & RNUM_MASK;
4930 check_regno (arg, type, *regno);
4934 /* Try to interpret the next token in ARG as a register of type TYPE.
4935 Consume the token and return true on success, storing the register
4936 number in *REGNO. Return false on failure. */
4939 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4940 unsigned int *regno)
4942 if (arg->token->type == OT_REG
4943 && match_regno (arg, type, arg->token->u.regno, regno))
4951 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4952 Consume the token and return true on success, storing the register numbers
4953 in *REGNO1 and *REGNO2. Return false on failure. */
4956 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4957 unsigned int *regno1, unsigned int *regno2)
4959 if (match_reg (arg, type, regno1))
4964 if (arg->token->type == OT_REG_RANGE
4965 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4966 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4967 && *regno1 <= *regno2)
4975 /* OP_INT matcher. */
4978 match_int_operand (struct mips_arg_info *arg,
4979 const struct mips_operand *operand_base)
4981 const struct mips_int_operand *operand;
4983 int min_val, max_val, factor;
4986 operand = (const struct mips_int_operand *) operand_base;
4987 factor = 1 << operand->shift;
4988 min_val = mips_int_operand_min (operand);
4989 max_val = mips_int_operand_max (operand);
4991 if (operand_base->lsb == 0
4992 && operand_base->size == 16
4993 && operand->shift == 0
4994 && operand->bias == 0
4995 && (operand->max_val == 32767 || operand->max_val == 65535))
4997 /* The operand can be relocated. */
4998 if (!match_expression (arg, &offset_expr, offset_reloc))
5001 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5002 /* Relocation operators were used. Accept the arguent and
5003 leave the relocation value in offset_expr and offset_relocs
5004 for the caller to process. */
5007 if (offset_expr.X_op != O_constant)
5009 /* Accept non-constant operands if no later alternative matches,
5010 leaving it for the caller to process. */
5011 if (!arg->lax_match)
5013 offset_reloc[0] = BFD_RELOC_LO16;
5017 /* Clear the global state; we're going to install the operand
5019 sval = offset_expr.X_add_number;
5020 offset_expr.X_op = O_absent;
5022 /* For compatibility with older assemblers, we accept
5023 0x8000-0xffff as signed 16-bit numbers when only
5024 signed numbers are allowed. */
5027 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5028 if (!arg->lax_match && sval <= max_val)
5034 if (!match_const_int (arg, &sval))
5038 arg->last_op_int = sval;
5040 if (sval < min_val || sval > max_val || sval % factor)
5042 match_out_of_range (arg);
5046 uval = (unsigned int) sval >> operand->shift;
5047 uval -= operand->bias;
5049 /* Handle -mfix-cn63xxp1. */
5051 && mips_fix_cn63xxp1
5052 && !mips_opts.micromips
5053 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5068 /* The rest must be changed to 28. */
5073 insn_insert_operand (arg->insn, operand_base, uval);
5077 /* OP_MAPPED_INT matcher. */
5080 match_mapped_int_operand (struct mips_arg_info *arg,
5081 const struct mips_operand *operand_base)
5083 const struct mips_mapped_int_operand *operand;
5084 unsigned int uval, num_vals;
5087 operand = (const struct mips_mapped_int_operand *) operand_base;
5088 if (!match_const_int (arg, &sval))
5091 num_vals = 1 << operand_base->size;
5092 for (uval = 0; uval < num_vals; uval++)
5093 if (operand->int_map[uval] == sval)
5095 if (uval == num_vals)
5097 match_out_of_range (arg);
5101 insn_insert_operand (arg->insn, operand_base, uval);
5105 /* OP_MSB matcher. */
5108 match_msb_operand (struct mips_arg_info *arg,
5109 const struct mips_operand *operand_base)
5111 const struct mips_msb_operand *operand;
5112 int min_val, max_val, max_high;
5113 offsetT size, sval, high;
5115 operand = (const struct mips_msb_operand *) operand_base;
5116 min_val = operand->bias;
5117 max_val = min_val + (1 << operand_base->size) - 1;
5118 max_high = operand->opsize;
5120 if (!match_const_int (arg, &size))
5123 high = size + arg->last_op_int;
5124 sval = operand->add_lsb ? high : size;
5126 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5128 match_out_of_range (arg);
5131 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5135 /* OP_REG matcher. */
5138 match_reg_operand (struct mips_arg_info *arg,
5139 const struct mips_operand *operand_base)
5141 const struct mips_reg_operand *operand;
5142 unsigned int regno, uval, num_vals;
5144 operand = (const struct mips_reg_operand *) operand_base;
5145 if (!match_reg (arg, operand->reg_type, ®no))
5148 if (operand->reg_map)
5150 num_vals = 1 << operand->root.size;
5151 for (uval = 0; uval < num_vals; uval++)
5152 if (operand->reg_map[uval] == regno)
5154 if (num_vals == uval)
5160 arg->last_regno = regno;
5161 if (arg->opnum == 1)
5162 arg->dest_regno = regno;
5163 insn_insert_operand (arg->insn, operand_base, uval);
5167 /* OP_REG_PAIR matcher. */
5170 match_reg_pair_operand (struct mips_arg_info *arg,
5171 const struct mips_operand *operand_base)
5173 const struct mips_reg_pair_operand *operand;
5174 unsigned int regno1, regno2, uval, num_vals;
5176 operand = (const struct mips_reg_pair_operand *) operand_base;
5177 if (!match_reg (arg, operand->reg_type, ®no1)
5178 || !match_char (arg, ',')
5179 || !match_reg (arg, operand->reg_type, ®no2))
5182 num_vals = 1 << operand_base->size;
5183 for (uval = 0; uval < num_vals; uval++)
5184 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5186 if (uval == num_vals)
5189 insn_insert_operand (arg->insn, operand_base, uval);
5193 /* OP_PCREL matcher. The caller chooses the relocation type. */
5196 match_pcrel_operand (struct mips_arg_info *arg)
5198 bfd_reloc_code_real_type r[3];
5200 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5203 /* OP_PERF_REG matcher. */
5206 match_perf_reg_operand (struct mips_arg_info *arg,
5207 const struct mips_operand *operand)
5211 if (!match_const_int (arg, &sval))
5216 || (mips_opts.arch == CPU_R5900
5217 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5218 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5220 set_insn_error (arg->argnum, _("invalid performance register"));
5224 insn_insert_operand (arg->insn, operand, sval);
5228 /* OP_ADDIUSP matcher. */
5231 match_addiusp_operand (struct mips_arg_info *arg,
5232 const struct mips_operand *operand)
5237 if (!match_const_int (arg, &sval))
5242 match_out_of_range (arg);
5247 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5249 match_out_of_range (arg);
5253 uval = (unsigned int) sval;
5254 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5255 insn_insert_operand (arg->insn, operand, uval);
5259 /* OP_CLO_CLZ_DEST matcher. */
5262 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5263 const struct mips_operand *operand)
5267 if (!match_reg (arg, OP_REG_GP, ®no))
5270 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5274 /* OP_CHECK_PREV matcher. */
5277 match_check_prev_operand (struct mips_arg_info *arg,
5278 const struct mips_operand *operand_base)
5280 const struct mips_check_prev_operand *operand;
5283 operand = (const struct mips_check_prev_operand *) operand_base;
5285 if (!match_reg (arg, OP_REG_GP, ®no))
5288 if (!operand->zero_ok && regno == 0)
5291 if ((operand->less_than_ok && regno < arg->last_regno)
5292 || (operand->greater_than_ok && regno > arg->last_regno)
5293 || (operand->equal_ok && regno == arg->last_regno))
5295 arg->last_regno = regno;
5296 insn_insert_operand (arg->insn, operand_base, regno);
5303 /* OP_SAME_RS_RT matcher. */
5306 match_same_rs_rt_operand (struct mips_arg_info *arg,
5307 const struct mips_operand *operand)
5311 if (!match_reg (arg, OP_REG_GP, ®no))
5316 set_insn_error (arg->argnum, _("the source register must not be $0"));
5320 arg->last_regno = regno;
5322 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5326 /* OP_LWM_SWM_LIST matcher. */
5329 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5330 const struct mips_operand *operand)
5332 unsigned int reglist, sregs, ra, regno1, regno2;
5333 struct mips_arg_info reset;
5336 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5340 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5345 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5348 while (match_char (arg, ',')
5349 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5352 if (operand->size == 2)
5354 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5360 and any permutations of these. */
5361 if ((reglist & 0xfff1ffff) != 0x80010000)
5364 sregs = (reglist >> 17) & 7;
5369 /* The list must include at least one of ra and s0-sN,
5370 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5371 which are $23 and $30 respectively.) E.g.:
5379 and any permutations of these. */
5380 if ((reglist & 0x3f00ffff) != 0)
5383 ra = (reglist >> 27) & 0x10;
5384 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5387 if ((sregs & -sregs) != sregs)
5390 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5394 /* OP_ENTRY_EXIT_LIST matcher. */
5397 match_entry_exit_operand (struct mips_arg_info *arg,
5398 const struct mips_operand *operand)
5401 bfd_boolean is_exit;
5403 /* The format is the same for both ENTRY and EXIT, but the constraints
5405 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5406 mask = (is_exit ? 7 << 3 : 0);
5409 unsigned int regno1, regno2;
5410 bfd_boolean is_freg;
5412 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5414 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5419 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5422 mask |= (5 + regno2) << 3;
5424 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5425 mask |= (regno2 - 3) << 3;
5426 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5427 mask |= (regno2 - 15) << 1;
5428 else if (regno1 == RA && regno2 == RA)
5433 while (match_char (arg, ','));
5435 insn_insert_operand (arg->insn, operand, mask);
5439 /* OP_SAVE_RESTORE_LIST matcher. */
5442 match_save_restore_list_operand (struct mips_arg_info *arg)
5444 unsigned int opcode, args, statics, sregs;
5445 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5448 opcode = arg->insn->insn_opcode;
5450 num_frame_sizes = 0;
5456 unsigned int regno1, regno2;
5458 if (arg->token->type == OT_INTEGER)
5460 /* Handle the frame size. */
5461 if (!match_const_int (arg, &frame_size))
5463 num_frame_sizes += 1;
5467 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5470 while (regno1 <= regno2)
5472 if (regno1 >= 4 && regno1 <= 7)
5474 if (num_frame_sizes == 0)
5476 args |= 1 << (regno1 - 4);
5478 /* statics $a0-$a3 */
5479 statics |= 1 << (regno1 - 4);
5481 else if (regno1 >= 16 && regno1 <= 23)
5483 sregs |= 1 << (regno1 - 16);
5484 else if (regno1 == 30)
5487 else if (regno1 == 31)
5488 /* Add $ra to insn. */
5498 while (match_char (arg, ','));
5500 /* Encode args/statics combination. */
5503 else if (args == 0xf)
5504 /* All $a0-$a3 are args. */
5505 opcode |= MIPS16_ALL_ARGS << 16;
5506 else if (statics == 0xf)
5507 /* All $a0-$a3 are statics. */
5508 opcode |= MIPS16_ALL_STATICS << 16;
5511 /* Count arg registers. */
5521 /* Count static registers. */
5523 while (statics & 0x8)
5525 statics = (statics << 1) & 0xf;
5531 /* Encode args/statics. */
5532 opcode |= ((num_args << 2) | num_statics) << 16;
5535 /* Encode $s0/$s1. */
5536 if (sregs & (1 << 0)) /* $s0 */
5538 if (sregs & (1 << 1)) /* $s1 */
5542 /* Encode $s2-$s8. */
5551 opcode |= num_sregs << 24;
5553 /* Encode frame size. */
5554 if (num_frame_sizes == 0)
5556 set_insn_error (arg->argnum, _("missing frame size"));
5559 if (num_frame_sizes > 1)
5561 set_insn_error (arg->argnum, _("frame size specified twice"));
5564 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5566 set_insn_error (arg->argnum, _("invalid frame size"));
5569 if (frame_size != 128 || (opcode >> 16) != 0)
5572 opcode |= (((frame_size & 0xf0) << 16)
5573 | (frame_size & 0x0f));
5576 /* Finally build the instruction. */
5577 if ((opcode >> 16) != 0 || frame_size == 0)
5578 opcode |= MIPS16_EXTEND;
5579 arg->insn->insn_opcode = opcode;
5583 /* OP_MDMX_IMM_REG matcher. */
5586 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5587 const struct mips_operand *operand)
5589 unsigned int regno, uval;
5591 const struct mips_opcode *opcode;
5593 /* The mips_opcode records whether this is an octobyte or quadhalf
5594 instruction. Start out with that bit in place. */
5595 opcode = arg->insn->insn_mo;
5596 uval = mips_extract_operand (operand, opcode->match);
5597 is_qh = (uval != 0);
5599 if (arg->token->type == OT_REG)
5601 if ((opcode->membership & INSN_5400)
5602 && strcmp (opcode->name, "rzu.ob") == 0)
5604 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5609 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5613 /* Check whether this is a vector register or a broadcast of
5614 a single element. */
5615 if (arg->token->type == OT_INTEGER_INDEX)
5617 if (arg->token->u.index > (is_qh ? 3 : 7))
5619 set_insn_error (arg->argnum, _("invalid element selector"));
5622 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5627 /* A full vector. */
5628 if ((opcode->membership & INSN_5400)
5629 && (strcmp (opcode->name, "sll.ob") == 0
5630 || strcmp (opcode->name, "srl.ob") == 0))
5632 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5638 uval |= MDMX_FMTSEL_VEC_QH << 5;
5640 uval |= MDMX_FMTSEL_VEC_OB << 5;
5648 if (!match_const_int (arg, &sval))
5650 if (sval < 0 || sval > 31)
5652 match_out_of_range (arg);
5655 uval |= (sval & 31);
5657 uval |= MDMX_FMTSEL_IMM_QH << 5;
5659 uval |= MDMX_FMTSEL_IMM_OB << 5;
5661 insn_insert_operand (arg->insn, operand, uval);
5665 /* OP_IMM_INDEX matcher. */
5668 match_imm_index_operand (struct mips_arg_info *arg,
5669 const struct mips_operand *operand)
5671 unsigned int max_val;
5673 if (arg->token->type != OT_INTEGER_INDEX)
5676 max_val = (1 << operand->size) - 1;
5677 if (arg->token->u.index > max_val)
5679 match_out_of_range (arg);
5682 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5687 /* OP_REG_INDEX matcher. */
5690 match_reg_index_operand (struct mips_arg_info *arg,
5691 const struct mips_operand *operand)
5695 if (arg->token->type != OT_REG_INDEX)
5698 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
5701 insn_insert_operand (arg->insn, operand, regno);
5706 /* OP_PC matcher. */
5709 match_pc_operand (struct mips_arg_info *arg)
5711 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5719 /* OP_NON_ZERO_REG matcher. */
5722 match_non_zero_reg_operand (struct mips_arg_info *arg,
5723 const struct mips_operand *operand)
5727 if (!match_reg (arg, OP_REG_GP, ®no))
5733 arg->last_regno = regno;
5734 insn_insert_operand (arg->insn, operand, regno);
5738 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5739 register that we need to match. */
5742 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5746 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5749 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5750 the length of the value in bytes (4 for float, 8 for double) and
5751 USING_GPRS says whether the destination is a GPR rather than an FPR.
5753 Return the constant in IMM and OFFSET as follows:
5755 - If the constant should be loaded via memory, set IMM to O_absent and
5756 OFFSET to the memory address.
5758 - Otherwise, if the constant should be loaded into two 32-bit registers,
5759 set IMM to the O_constant to load into the high register and OFFSET
5760 to the corresponding value for the low register.
5762 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5764 These constants only appear as the last operand in an instruction,
5765 and every instruction that accepts them in any variant accepts them
5766 in all variants. This means we don't have to worry about backing out
5767 any changes if the instruction does not match. We just match
5768 unconditionally and report an error if the constant is invalid. */
5771 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5772 expressionS *offset, int length, bfd_boolean using_gprs)
5777 const char *newname;
5778 unsigned char *data;
5780 /* Where the constant is placed is based on how the MIPS assembler
5783 length == 4 && using_gprs -- immediate value only
5784 length == 8 && using_gprs -- .rdata or immediate value
5785 length == 4 && !using_gprs -- .lit4 or immediate value
5786 length == 8 && !using_gprs -- .lit8 or immediate value
5788 The .lit4 and .lit8 sections are only used if permitted by the
5790 if (arg->token->type != OT_FLOAT)
5792 set_insn_error (arg->argnum, _("floating-point expression required"));
5796 gas_assert (arg->token->u.flt.length == length);
5797 data = arg->token->u.flt.data;
5800 /* Handle 32-bit constants for which an immediate value is best. */
5803 || g_switch_value < 4
5804 || (data[0] == 0 && data[1] == 0)
5805 || (data[2] == 0 && data[3] == 0)))
5807 imm->X_op = O_constant;
5808 if (!target_big_endian)
5809 imm->X_add_number = bfd_getl32 (data);
5811 imm->X_add_number = bfd_getb32 (data);
5812 offset->X_op = O_absent;
5816 /* Handle 64-bit constants for which an immediate value is best. */
5818 && !mips_disable_float_construction
5819 /* Constants can only be constructed in GPRs and copied to FPRs if the
5820 GPRs are at least as wide as the FPRs or MTHC1 is available.
5821 Unlike most tests for 32-bit floating-point registers this check
5822 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5823 permit 64-bit moves without MXHC1.
5824 Force the constant into memory otherwise. */
5827 || ISA_HAS_MXHC1 (mips_opts.isa)
5829 && ((data[0] == 0 && data[1] == 0)
5830 || (data[2] == 0 && data[3] == 0))
5831 && ((data[4] == 0 && data[5] == 0)
5832 || (data[6] == 0 && data[7] == 0)))
5834 /* The value is simple enough to load with a couple of instructions.
5835 If using 32-bit registers, set IMM to the high order 32 bits and
5836 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5838 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
5840 imm->X_op = O_constant;
5841 offset->X_op = O_constant;
5842 if (!target_big_endian)
5844 imm->X_add_number = bfd_getl32 (data + 4);
5845 offset->X_add_number = bfd_getl32 (data);
5849 imm->X_add_number = bfd_getb32 (data);
5850 offset->X_add_number = bfd_getb32 (data + 4);
5852 if (offset->X_add_number == 0)
5853 offset->X_op = O_absent;
5857 imm->X_op = O_constant;
5858 if (!target_big_endian)
5859 imm->X_add_number = bfd_getl64 (data);
5861 imm->X_add_number = bfd_getb64 (data);
5862 offset->X_op = O_absent;
5867 /* Switch to the right section. */
5869 subseg = now_subseg;
5872 gas_assert (!using_gprs && g_switch_value >= 4);
5877 if (using_gprs || g_switch_value < 8)
5878 newname = RDATA_SECTION_NAME;
5883 new_seg = subseg_new (newname, (subsegT) 0);
5884 bfd_set_section_flags (stdoutput, new_seg,
5885 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5886 frag_align (length == 4 ? 2 : 3, 0, 0);
5887 if (strncmp (TARGET_OS, "elf", 3) != 0)
5888 record_alignment (new_seg, 4);
5890 record_alignment (new_seg, length == 4 ? 2 : 3);
5892 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
5894 /* Set the argument to the current address in the section. */
5895 imm->X_op = O_absent;
5896 offset->X_op = O_symbol;
5897 offset->X_add_symbol = symbol_temp_new_now ();
5898 offset->X_add_number = 0;
5900 /* Put the floating point number into the section. */
5901 p = frag_more (length);
5902 memcpy (p, data, length);
5904 /* Switch back to the original section. */
5905 subseg_set (seg, subseg);
5909 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5913 match_vu0_suffix_operand (struct mips_arg_info *arg,
5914 const struct mips_operand *operand,
5915 bfd_boolean match_p)
5919 /* The operand can be an XYZW mask or a single 2-bit channel index
5920 (with X being 0). */
5921 gas_assert (operand->size == 2 || operand->size == 4);
5923 /* The suffix can be omitted when it is already part of the opcode. */
5924 if (arg->token->type != OT_CHANNELS)
5927 uval = arg->token->u.channels;
5928 if (operand->size == 2)
5930 /* Check that a single bit is set and convert it into a 2-bit index. */
5931 if ((uval & -uval) != uval)
5933 uval = 4 - ffs (uval);
5936 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5941 insn_insert_operand (arg->insn, operand, uval);
5945 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5946 of the argument text if the match is successful, otherwise return null. */
5949 match_operand (struct mips_arg_info *arg,
5950 const struct mips_operand *operand)
5952 switch (operand->type)
5955 return match_int_operand (arg, operand);
5958 return match_mapped_int_operand (arg, operand);
5961 return match_msb_operand (arg, operand);
5964 case OP_OPTIONAL_REG:
5965 return match_reg_operand (arg, operand);
5968 return match_reg_pair_operand (arg, operand);
5971 return match_pcrel_operand (arg);
5974 return match_perf_reg_operand (arg, operand);
5976 case OP_ADDIUSP_INT:
5977 return match_addiusp_operand (arg, operand);
5979 case OP_CLO_CLZ_DEST:
5980 return match_clo_clz_dest_operand (arg, operand);
5982 case OP_LWM_SWM_LIST:
5983 return match_lwm_swm_list_operand (arg, operand);
5985 case OP_ENTRY_EXIT_LIST:
5986 return match_entry_exit_operand (arg, operand);
5988 case OP_SAVE_RESTORE_LIST:
5989 return match_save_restore_list_operand (arg);
5991 case OP_MDMX_IMM_REG:
5992 return match_mdmx_imm_reg_operand (arg, operand);
5994 case OP_REPEAT_DEST_REG:
5995 return match_tied_reg_operand (arg, arg->dest_regno);
5997 case OP_REPEAT_PREV_REG:
5998 return match_tied_reg_operand (arg, arg->last_regno);
6001 return match_pc_operand (arg);
6004 return match_vu0_suffix_operand (arg, operand, FALSE);
6006 case OP_VU0_MATCH_SUFFIX:
6007 return match_vu0_suffix_operand (arg, operand, TRUE);
6010 return match_imm_index_operand (arg, operand);
6013 return match_reg_index_operand (arg, operand);
6016 return match_same_rs_rt_operand (arg, operand);
6019 return match_check_prev_operand (arg, operand);
6021 case OP_NON_ZERO_REG:
6022 return match_non_zero_reg_operand (arg, operand);
6027 /* ARG is the state after successfully matching an instruction.
6028 Issue any queued-up warnings. */
6031 check_completed_insn (struct mips_arg_info *arg)
6036 as_warn (_("used $at without \".set noat\""));
6038 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6042 /* Return true if modifying general-purpose register REG needs a delay. */
6045 reg_needs_delay (unsigned int reg)
6047 unsigned long prev_pinfo;
6049 prev_pinfo = history[0].insn_mo->pinfo;
6050 if (!mips_opts.noreorder
6051 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6052 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6053 && (gpr_write_mask (&history[0]) & (1 << reg)))
6059 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6060 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6061 by VR4120 errata. */
6064 classify_vr4120_insn (const char *name)
6066 if (strncmp (name, "macc", 4) == 0)
6067 return FIX_VR4120_MACC;
6068 if (strncmp (name, "dmacc", 5) == 0)
6069 return FIX_VR4120_DMACC;
6070 if (strncmp (name, "mult", 4) == 0)
6071 return FIX_VR4120_MULT;
6072 if (strncmp (name, "dmult", 5) == 0)
6073 return FIX_VR4120_DMULT;
6074 if (strstr (name, "div"))
6075 return FIX_VR4120_DIV;
6076 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6077 return FIX_VR4120_MTHILO;
6078 return NUM_FIX_VR4120_CLASSES;
6081 #define INSN_ERET 0x42000018
6082 #define INSN_DERET 0x4200001f
6083 #define INSN_DMULT 0x1c
6084 #define INSN_DMULTU 0x1d
6086 /* Return the number of instructions that must separate INSN1 and INSN2,
6087 where INSN1 is the earlier instruction. Return the worst-case value
6088 for any INSN2 if INSN2 is null. */
6091 insns_between (const struct mips_cl_insn *insn1,
6092 const struct mips_cl_insn *insn2)
6094 unsigned long pinfo1, pinfo2;
6097 /* If INFO2 is null, pessimistically assume that all flags are set for
6098 the second instruction. */
6099 pinfo1 = insn1->insn_mo->pinfo;
6100 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6102 /* For most targets, write-after-read dependencies on the HI and LO
6103 registers must be separated by at least two instructions. */
6104 if (!hilo_interlocks)
6106 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6108 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6112 /* If we're working around r7000 errata, there must be two instructions
6113 between an mfhi or mflo and any instruction that uses the result. */
6114 if (mips_7000_hilo_fix
6115 && !mips_opts.micromips
6116 && MF_HILO_INSN (pinfo1)
6117 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6120 /* If we're working around 24K errata, one instruction is required
6121 if an ERET or DERET is followed by a branch instruction. */
6122 if (mips_fix_24k && !mips_opts.micromips)
6124 if (insn1->insn_opcode == INSN_ERET
6125 || insn1->insn_opcode == INSN_DERET)
6128 || insn2->insn_opcode == INSN_ERET
6129 || insn2->insn_opcode == INSN_DERET
6130 || delayed_branch_p (insn2))
6135 /* If we're working around PMC RM7000 errata, there must be three
6136 nops between a dmult and a load instruction. */
6137 if (mips_fix_rm7000 && !mips_opts.micromips)
6139 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6140 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6142 if (pinfo2 & INSN_LOAD_MEMORY)
6147 /* If working around VR4120 errata, check for combinations that need
6148 a single intervening instruction. */
6149 if (mips_fix_vr4120 && !mips_opts.micromips)
6151 unsigned int class1, class2;
6153 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6154 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6158 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6159 if (vr4120_conflicts[class1] & (1 << class2))
6164 if (!HAVE_CODE_COMPRESSION)
6166 /* Check for GPR or coprocessor load delays. All such delays
6167 are on the RT register. */
6168 /* Itbl support may require additional care here. */
6169 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6170 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6172 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6176 /* Check for generic coprocessor hazards.
6178 This case is not handled very well. There is no special
6179 knowledge of CP0 handling, and the coprocessors other than
6180 the floating point unit are not distinguished at all. */
6181 /* Itbl support may require additional care here. FIXME!
6182 Need to modify this to include knowledge about
6183 user specified delays! */
6184 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6185 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6187 /* Handle cases where INSN1 writes to a known general coprocessor
6188 register. There must be a one instruction delay before INSN2
6189 if INSN2 reads that register, otherwise no delay is needed. */
6190 mask = fpr_write_mask (insn1);
6193 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6198 /* Read-after-write dependencies on the control registers
6199 require a two-instruction gap. */
6200 if ((pinfo1 & INSN_WRITE_COND_CODE)
6201 && (pinfo2 & INSN_READ_COND_CODE))
6204 /* We don't know exactly what INSN1 does. If INSN2 is
6205 also a coprocessor instruction, assume there must be
6206 a one instruction gap. */
6207 if (pinfo2 & INSN_COP)
6212 /* Check for read-after-write dependencies on the coprocessor
6213 control registers in cases where INSN1 does not need a general
6214 coprocessor delay. This means that INSN1 is a floating point
6215 comparison instruction. */
6216 /* Itbl support may require additional care here. */
6217 else if (!cop_interlocks
6218 && (pinfo1 & INSN_WRITE_COND_CODE)
6219 && (pinfo2 & INSN_READ_COND_CODE))
6223 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6224 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6226 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6227 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6228 || (insn2 && delayed_branch_p (insn2))))
6234 /* Return the number of nops that would be needed to work around the
6235 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6236 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6237 that are contained within the first IGNORE instructions of HIST. */
6240 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6241 const struct mips_cl_insn *insn)
6246 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6247 are not affected by the errata. */
6249 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6250 || strcmp (insn->insn_mo->name, "mtlo") == 0
6251 || strcmp (insn->insn_mo->name, "mthi") == 0))
6254 /* Search for the first MFLO or MFHI. */
6255 for (i = 0; i < MAX_VR4130_NOPS; i++)
6256 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6258 /* Extract the destination register. */
6259 mask = gpr_write_mask (&hist[i]);
6261 /* No nops are needed if INSN reads that register. */
6262 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6265 /* ...or if any of the intervening instructions do. */
6266 for (j = 0; j < i; j++)
6267 if (gpr_read_mask (&hist[j]) & mask)
6271 return MAX_VR4130_NOPS - i;
6276 #define BASE_REG_EQ(INSN1, INSN2) \
6277 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6278 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6280 /* Return the minimum alignment for this store instruction. */
6283 fix_24k_align_to (const struct mips_opcode *mo)
6285 if (strcmp (mo->name, "sh") == 0)
6288 if (strcmp (mo->name, "swc1") == 0
6289 || strcmp (mo->name, "swc2") == 0
6290 || strcmp (mo->name, "sw") == 0
6291 || strcmp (mo->name, "sc") == 0
6292 || strcmp (mo->name, "s.s") == 0)
6295 if (strcmp (mo->name, "sdc1") == 0
6296 || strcmp (mo->name, "sdc2") == 0
6297 || strcmp (mo->name, "s.d") == 0)
6304 struct fix_24k_store_info
6306 /* Immediate offset, if any, for this store instruction. */
6308 /* Alignment required by this store instruction. */
6310 /* True for register offsets. */
6311 int register_offset;
6314 /* Comparison function used by qsort. */
6317 fix_24k_sort (const void *a, const void *b)
6319 const struct fix_24k_store_info *pos1 = a;
6320 const struct fix_24k_store_info *pos2 = b;
6322 return (pos1->off - pos2->off);
6325 /* INSN is a store instruction. Try to record the store information
6326 in STINFO. Return false if the information isn't known. */
6329 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6330 const struct mips_cl_insn *insn)
6332 /* The instruction must have a known offset. */
6333 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6336 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6337 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6341 /* Return the number of nops that would be needed to work around the 24k
6342 "lost data on stores during refill" errata if instruction INSN
6343 immediately followed the 2 instructions described by HIST.
6344 Ignore hazards that are contained within the first IGNORE
6345 instructions of HIST.
6347 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6348 for the data cache refills and store data. The following describes
6349 the scenario where the store data could be lost.
6351 * A data cache miss, due to either a load or a store, causing fill
6352 data to be supplied by the memory subsystem
6353 * The first three doublewords of fill data are returned and written
6355 * A sequence of four stores occurs in consecutive cycles around the
6356 final doubleword of the fill:
6360 * Zero, One or more instructions
6363 The four stores A-D must be to different doublewords of the line that
6364 is being filled. The fourth instruction in the sequence above permits
6365 the fill of the final doubleword to be transferred from the FSB into
6366 the cache. In the sequence above, the stores may be either integer
6367 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6368 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6369 different doublewords on the line. If the floating point unit is
6370 running in 1:2 mode, it is not possible to create the sequence above
6371 using only floating point store instructions.
6373 In this case, the cache line being filled is incorrectly marked
6374 invalid, thereby losing the data from any store to the line that
6375 occurs between the original miss and the completion of the five
6376 cycle sequence shown above.
6378 The workarounds are:
6380 * Run the data cache in write-through mode.
6381 * Insert a non-store instruction between
6382 Store A and Store B or Store B and Store C. */
6385 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6386 const struct mips_cl_insn *insn)
6388 struct fix_24k_store_info pos[3];
6389 int align, i, base_offset;
6394 /* If the previous instruction wasn't a store, there's nothing to
6396 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6399 /* If the instructions after the previous one are unknown, we have
6400 to assume the worst. */
6404 /* Check whether we are dealing with three consecutive stores. */
6405 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6406 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6409 /* If we don't know the relationship between the store addresses,
6410 assume the worst. */
6411 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6412 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6415 if (!fix_24k_record_store_info (&pos[0], insn)
6416 || !fix_24k_record_store_info (&pos[1], &hist[0])
6417 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6420 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6422 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6423 X bytes and such that the base register + X is known to be aligned
6426 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6430 align = pos[0].align_to;
6431 base_offset = pos[0].off;
6432 for (i = 1; i < 3; i++)
6433 if (align < pos[i].align_to)
6435 align = pos[i].align_to;
6436 base_offset = pos[i].off;
6438 for (i = 0; i < 3; i++)
6439 pos[i].off -= base_offset;
6442 pos[0].off &= ~align + 1;
6443 pos[1].off &= ~align + 1;
6444 pos[2].off &= ~align + 1;
6446 /* If any two stores write to the same chunk, they also write to the
6447 same doubleword. The offsets are still sorted at this point. */
6448 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6451 /* A range of at least 9 bytes is needed for the stores to be in
6452 non-overlapping doublewords. */
6453 if (pos[2].off - pos[0].off <= 8)
6456 if (pos[2].off - pos[1].off >= 24
6457 || pos[1].off - pos[0].off >= 24
6458 || pos[2].off - pos[0].off >= 32)
6464 /* Return the number of nops that would be needed if instruction INSN
6465 immediately followed the MAX_NOPS instructions given by HIST,
6466 where HIST[0] is the most recent instruction. Ignore hazards
6467 between INSN and the first IGNORE instructions in HIST.
6469 If INSN is null, return the worse-case number of nops for any
6473 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6474 const struct mips_cl_insn *insn)
6476 int i, nops, tmp_nops;
6479 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6481 tmp_nops = insns_between (hist + i, insn) - i;
6482 if (tmp_nops > nops)
6486 if (mips_fix_vr4130 && !mips_opts.micromips)
6488 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6489 if (tmp_nops > nops)
6493 if (mips_fix_24k && !mips_opts.micromips)
6495 tmp_nops = nops_for_24k (ignore, hist, insn);
6496 if (tmp_nops > nops)
6503 /* The variable arguments provide NUM_INSNS extra instructions that
6504 might be added to HIST. Return the largest number of nops that
6505 would be needed after the extended sequence, ignoring hazards
6506 in the first IGNORE instructions. */
6509 nops_for_sequence (int num_insns, int ignore,
6510 const struct mips_cl_insn *hist, ...)
6513 struct mips_cl_insn buffer[MAX_NOPS];
6514 struct mips_cl_insn *cursor;
6517 va_start (args, hist);
6518 cursor = buffer + num_insns;
6519 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6520 while (cursor > buffer)
6521 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6523 nops = nops_for_insn (ignore, buffer, NULL);
6528 /* Like nops_for_insn, but if INSN is a branch, take into account the
6529 worst-case delay for the branch target. */
6532 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6533 const struct mips_cl_insn *insn)
6537 nops = nops_for_insn (ignore, hist, insn);
6538 if (delayed_branch_p (insn))
6540 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6541 hist, insn, get_delay_slot_nop (insn));
6542 if (tmp_nops > nops)
6545 else if (compact_branch_p (insn))
6547 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6548 if (tmp_nops > nops)
6554 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6557 fix_loongson2f_nop (struct mips_cl_insn * ip)
6559 gas_assert (!HAVE_CODE_COMPRESSION);
6560 if (strcmp (ip->insn_mo->name, "nop") == 0)
6561 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6564 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6565 jr target pc &= 'hffff_ffff_cfff_ffff. */
6568 fix_loongson2f_jump (struct mips_cl_insn * ip)
6570 gas_assert (!HAVE_CODE_COMPRESSION);
6571 if (strcmp (ip->insn_mo->name, "j") == 0
6572 || strcmp (ip->insn_mo->name, "jr") == 0
6573 || strcmp (ip->insn_mo->name, "jalr") == 0)
6581 sreg = EXTRACT_OPERAND (0, RS, *ip);
6582 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6585 ep.X_op = O_constant;
6586 ep.X_add_number = 0xcfff0000;
6587 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6588 ep.X_add_number = 0xffff;
6589 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6590 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6595 fix_loongson2f (struct mips_cl_insn * ip)
6597 if (mips_fix_loongson2f_nop)
6598 fix_loongson2f_nop (ip);
6600 if (mips_fix_loongson2f_jump)
6601 fix_loongson2f_jump (ip);
6604 /* IP is a branch that has a delay slot, and we need to fill it
6605 automatically. Return true if we can do that by swapping IP
6606 with the previous instruction.
6607 ADDRESS_EXPR is an operand of the instruction to be used with
6611 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6612 bfd_reloc_code_real_type *reloc_type)
6614 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6615 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6616 unsigned int fpr_read, prev_fpr_write;
6618 /* -O2 and above is required for this optimization. */
6619 if (mips_optimize < 2)
6622 /* If we have seen .set volatile or .set nomove, don't optimize. */
6623 if (mips_opts.nomove)
6626 /* We can't swap if the previous instruction's position is fixed. */
6627 if (history[0].fixed_p)
6630 /* If the previous previous insn was in a .set noreorder, we can't
6631 swap. Actually, the MIPS assembler will swap in this situation.
6632 However, gcc configured -with-gnu-as will generate code like
6640 in which we can not swap the bne and INSN. If gcc is not configured
6641 -with-gnu-as, it does not output the .set pseudo-ops. */
6642 if (history[1].noreorder_p)
6645 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6646 This means that the previous instruction was a 4-byte one anyhow. */
6647 if (mips_opts.mips16 && history[0].fixp[0])
6650 /* If the branch is itself the target of a branch, we can not swap.
6651 We cheat on this; all we check for is whether there is a label on
6652 this instruction. If there are any branches to anything other than
6653 a label, users must use .set noreorder. */
6654 if (seg_info (now_seg)->label_list)
6657 /* If the previous instruction is in a variant frag other than this
6658 branch's one, we cannot do the swap. This does not apply to
6659 MIPS16 code, which uses variant frags for different purposes. */
6660 if (!mips_opts.mips16
6662 && history[0].frag->fr_type == rs_machine_dependent)
6665 /* We do not swap with instructions that cannot architecturally
6666 be placed in a branch delay slot, such as SYNC or ERET. We
6667 also refrain from swapping with a trap instruction, since it
6668 complicates trap handlers to have the trap instruction be in
6670 prev_pinfo = history[0].insn_mo->pinfo;
6671 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6674 /* Check for conflicts between the branch and the instructions
6675 before the candidate delay slot. */
6676 if (nops_for_insn (0, history + 1, ip) > 0)
6679 /* Check for conflicts between the swapped sequence and the
6680 target of the branch. */
6681 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6684 /* If the branch reads a register that the previous
6685 instruction sets, we can not swap. */
6686 gpr_read = gpr_read_mask (ip);
6687 prev_gpr_write = gpr_write_mask (&history[0]);
6688 if (gpr_read & prev_gpr_write)
6691 fpr_read = fpr_read_mask (ip);
6692 prev_fpr_write = fpr_write_mask (&history[0]);
6693 if (fpr_read & prev_fpr_write)
6696 /* If the branch writes a register that the previous
6697 instruction sets, we can not swap. */
6698 gpr_write = gpr_write_mask (ip);
6699 if (gpr_write & prev_gpr_write)
6702 /* If the branch writes a register that the previous
6703 instruction reads, we can not swap. */
6704 prev_gpr_read = gpr_read_mask (&history[0]);
6705 if (gpr_write & prev_gpr_read)
6708 /* If one instruction sets a condition code and the
6709 other one uses a condition code, we can not swap. */
6710 pinfo = ip->insn_mo->pinfo;
6711 if ((pinfo & INSN_READ_COND_CODE)
6712 && (prev_pinfo & INSN_WRITE_COND_CODE))
6714 if ((pinfo & INSN_WRITE_COND_CODE)
6715 && (prev_pinfo & INSN_READ_COND_CODE))
6718 /* If the previous instruction uses the PC, we can not swap. */
6719 prev_pinfo2 = history[0].insn_mo->pinfo2;
6720 if (prev_pinfo2 & INSN2_READ_PC)
6723 /* If the previous instruction has an incorrect size for a fixed
6724 branch delay slot in microMIPS mode, we cannot swap. */
6725 pinfo2 = ip->insn_mo->pinfo2;
6726 if (mips_opts.micromips
6727 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6728 && insn_length (history) != 2)
6730 if (mips_opts.micromips
6731 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6732 && insn_length (history) != 4)
6735 /* On R5900 short loops need to be fixed by inserting a nop in
6736 the branch delay slots.
6737 A short loop can be terminated too early. */
6738 if (mips_opts.arch == CPU_R5900
6739 /* Check if instruction has a parameter, ignore "j $31". */
6740 && (address_expr != NULL)
6741 /* Parameter must be 16 bit. */
6742 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6743 /* Branch to same segment. */
6744 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
6745 /* Branch to same code fragment. */
6746 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
6747 /* Can only calculate branch offset if value is known. */
6748 && symbol_constant_p (address_expr->X_add_symbol)
6749 /* Check if branch is really conditional. */
6750 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6751 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6752 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6755 /* Check if loop is shorter than 6 instructions including
6756 branch and delay slot. */
6757 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
6764 /* When the loop includes branches or jumps,
6765 it is not a short loop. */
6766 for (i = 0; i < (distance / 4); i++)
6768 if ((history[i].cleared_p)
6769 || delayed_branch_p (&history[i]))
6777 /* Insert nop after branch to fix short loop. */
6786 /* Decide how we should add IP to the instruction stream.
6787 ADDRESS_EXPR is an operand of the instruction to be used with
6790 static enum append_method
6791 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6792 bfd_reloc_code_real_type *reloc_type)
6794 /* The relaxed version of a macro sequence must be inherently
6796 if (mips_relax.sequence == 2)
6799 /* We must not dabble with instructions in a ".set norerorder" block. */
6800 if (mips_opts.noreorder)
6803 /* Otherwise, it's our responsibility to fill branch delay slots. */
6804 if (delayed_branch_p (ip))
6806 if (!branch_likely_p (ip)
6807 && can_swap_branch_p (ip, address_expr, reloc_type))
6810 if (mips_opts.mips16
6811 && ISA_SUPPORTS_MIPS16E
6812 && gpr_read_mask (ip) != 0)
6813 return APPEND_ADD_COMPACT;
6815 return APPEND_ADD_WITH_NOP;
6821 /* IP is a MIPS16 instruction whose opcode we have just changed.
6822 Point IP->insn_mo to the new opcode's definition. */
6825 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6827 const struct mips_opcode *mo, *end;
6829 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6830 for (mo = ip->insn_mo; mo < end; mo++)
6831 if ((ip->insn_opcode & mo->mask) == mo->match)
6839 /* For microMIPS macros, we need to generate a local number label
6840 as the target of branches. */
6841 #define MICROMIPS_LABEL_CHAR '\037'
6842 static unsigned long micromips_target_label;
6843 static char micromips_target_name[32];
6846 micromips_label_name (void)
6848 char *p = micromips_target_name;
6849 char symbol_name_temporary[24];
6857 l = micromips_target_label;
6858 #ifdef LOCAL_LABEL_PREFIX
6859 *p++ = LOCAL_LABEL_PREFIX;
6862 *p++ = MICROMIPS_LABEL_CHAR;
6865 symbol_name_temporary[i++] = l % 10 + '0';
6870 *p++ = symbol_name_temporary[--i];
6873 return micromips_target_name;
6877 micromips_label_expr (expressionS *label_expr)
6879 label_expr->X_op = O_symbol;
6880 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6881 label_expr->X_add_number = 0;
6885 micromips_label_inc (void)
6887 micromips_target_label++;
6888 *micromips_target_name = '\0';
6892 micromips_add_label (void)
6896 s = colon (micromips_label_name ());
6897 micromips_label_inc ();
6898 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6901 /* If assembling microMIPS code, then return the microMIPS reloc
6902 corresponding to the requested one if any. Otherwise return
6903 the reloc unchanged. */
6905 static bfd_reloc_code_real_type
6906 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6908 static const bfd_reloc_code_real_type relocs[][2] =
6910 /* Keep sorted incrementally by the left-hand key. */
6911 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6912 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6913 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6914 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6915 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6916 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6917 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6918 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6919 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6920 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6921 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6922 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6923 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6924 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6925 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6926 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6927 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6928 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6929 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6930 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6931 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6932 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6933 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6934 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6935 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6936 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6937 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6939 bfd_reloc_code_real_type r;
6942 if (!mips_opts.micromips)
6944 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6950 return relocs[i][1];
6955 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6956 Return true on success, storing the resolved value in RESULT. */
6959 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6964 case BFD_RELOC_MIPS_HIGHEST:
6965 case BFD_RELOC_MICROMIPS_HIGHEST:
6966 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6969 case BFD_RELOC_MIPS_HIGHER:
6970 case BFD_RELOC_MICROMIPS_HIGHER:
6971 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6974 case BFD_RELOC_HI16_S:
6975 case BFD_RELOC_MICROMIPS_HI16_S:
6976 case BFD_RELOC_MIPS16_HI16_S:
6977 *result = ((operand + 0x8000) >> 16) & 0xffff;
6980 case BFD_RELOC_HI16:
6981 case BFD_RELOC_MICROMIPS_HI16:
6982 case BFD_RELOC_MIPS16_HI16:
6983 *result = (operand >> 16) & 0xffff;
6986 case BFD_RELOC_LO16:
6987 case BFD_RELOC_MICROMIPS_LO16:
6988 case BFD_RELOC_MIPS16_LO16:
6989 *result = operand & 0xffff;
6992 case BFD_RELOC_UNUSED:
7001 /* Output an instruction. IP is the instruction information.
7002 ADDRESS_EXPR is an operand of the instruction to be used with
7003 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7004 a macro expansion. */
7007 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7008 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
7010 unsigned long prev_pinfo2, pinfo;
7011 bfd_boolean relaxed_branch = FALSE;
7012 enum append_method method;
7013 bfd_boolean relax32;
7016 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7017 fix_loongson2f (ip);
7019 file_ase_mips16 |= mips_opts.mips16;
7020 file_ase_micromips |= mips_opts.micromips;
7022 prev_pinfo2 = history[0].insn_mo->pinfo2;
7023 pinfo = ip->insn_mo->pinfo;
7025 if (mips_opts.micromips
7027 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7028 && micromips_insn_length (ip->insn_mo) != 2)
7029 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7030 && micromips_insn_length (ip->insn_mo) != 4)))
7031 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7032 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7034 if (address_expr == NULL)
7036 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7037 && reloc_type[1] == BFD_RELOC_UNUSED
7038 && reloc_type[2] == BFD_RELOC_UNUSED
7039 && address_expr->X_op == O_constant)
7041 switch (*reloc_type)
7043 case BFD_RELOC_MIPS_JMP:
7047 /* Shift is 2, unusually, for microMIPS JALX. */
7048 shift = (mips_opts.micromips
7049 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7050 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7051 as_bad (_("jump to misaligned address (0x%lx)"),
7052 (unsigned long) address_expr->X_add_number);
7053 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7059 case BFD_RELOC_MIPS16_JMP:
7060 if ((address_expr->X_add_number & 3) != 0)
7061 as_bad (_("jump to misaligned address (0x%lx)"),
7062 (unsigned long) address_expr->X_add_number);
7064 (((address_expr->X_add_number & 0x7c0000) << 3)
7065 | ((address_expr->X_add_number & 0xf800000) >> 7)
7066 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7070 case BFD_RELOC_16_PCREL_S2:
7074 shift = mips_opts.micromips ? 1 : 2;
7075 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7076 as_bad (_("branch to misaligned address (0x%lx)"),
7077 (unsigned long) address_expr->X_add_number);
7078 if (!mips_relax_branch)
7080 if ((address_expr->X_add_number + (1 << (shift + 15)))
7081 & ~((1 << (shift + 16)) - 1))
7082 as_bad (_("branch address range overflow (0x%lx)"),
7083 (unsigned long) address_expr->X_add_number);
7084 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7090 case BFD_RELOC_MIPS_21_PCREL_S2:
7095 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7096 as_bad (_("branch to misaligned address (0x%lx)"),
7097 (unsigned long) address_expr->X_add_number);
7098 if ((address_expr->X_add_number + (1 << (shift + 20)))
7099 & ~((1 << (shift + 21)) - 1))
7100 as_bad (_("branch address range overflow (0x%lx)"),
7101 (unsigned long) address_expr->X_add_number);
7102 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7107 case BFD_RELOC_MIPS_26_PCREL_S2:
7112 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7113 as_bad (_("branch to misaligned address (0x%lx)"),
7114 (unsigned long) address_expr->X_add_number);
7115 if ((address_expr->X_add_number + (1 << (shift + 25)))
7116 & ~((1 << (shift + 26)) - 1))
7117 as_bad (_("branch address range overflow (0x%lx)"),
7118 (unsigned long) address_expr->X_add_number);
7119 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7128 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7131 ip->insn_opcode |= value & 0xffff;
7139 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7141 /* There are a lot of optimizations we could do that we don't.
7142 In particular, we do not, in general, reorder instructions.
7143 If you use gcc with optimization, it will reorder
7144 instructions and generally do much more optimization then we
7145 do here; repeating all that work in the assembler would only
7146 benefit hand written assembly code, and does not seem worth
7148 int nops = (mips_optimize == 0
7149 ? nops_for_insn (0, history, NULL)
7150 : nops_for_insn_or_target (0, history, ip));
7154 unsigned long old_frag_offset;
7157 old_frag = frag_now;
7158 old_frag_offset = frag_now_fix ();
7160 for (i = 0; i < nops; i++)
7161 add_fixed_insn (NOP_INSN);
7162 insert_into_history (0, nops, NOP_INSN);
7166 listing_prev_line ();
7167 /* We may be at the start of a variant frag. In case we
7168 are, make sure there is enough space for the frag
7169 after the frags created by listing_prev_line. The
7170 argument to frag_grow here must be at least as large
7171 as the argument to all other calls to frag_grow in
7172 this file. We don't have to worry about being in the
7173 middle of a variant frag, because the variants insert
7174 all needed nop instructions themselves. */
7178 mips_move_text_labels ();
7180 #ifndef NO_ECOFF_DEBUGGING
7181 if (ECOFF_DEBUGGING)
7182 ecoff_fix_loc (old_frag, old_frag_offset);
7186 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7190 /* Work out how many nops in prev_nop_frag are needed by IP,
7191 ignoring hazards generated by the first prev_nop_frag_since
7193 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7194 gas_assert (nops <= prev_nop_frag_holds);
7196 /* Enforce NOPS as a minimum. */
7197 if (nops > prev_nop_frag_required)
7198 prev_nop_frag_required = nops;
7200 if (prev_nop_frag_holds == prev_nop_frag_required)
7202 /* Settle for the current number of nops. Update the history
7203 accordingly (for the benefit of any future .set reorder code). */
7204 prev_nop_frag = NULL;
7205 insert_into_history (prev_nop_frag_since,
7206 prev_nop_frag_holds, NOP_INSN);
7210 /* Allow this instruction to replace one of the nops that was
7211 tentatively added to prev_nop_frag. */
7212 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7213 prev_nop_frag_holds--;
7214 prev_nop_frag_since++;
7218 method = get_append_method (ip, address_expr, reloc_type);
7219 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7221 dwarf2_emit_insn (0);
7222 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7223 so "move" the instruction address accordingly.
7225 Also, it doesn't seem appropriate for the assembler to reorder .loc
7226 entries. If this instruction is a branch that we are going to swap
7227 with the previous instruction, the two instructions should be
7228 treated as a unit, and the debug information for both instructions
7229 should refer to the start of the branch sequence. Using the
7230 current position is certainly wrong when swapping a 32-bit branch
7231 and a 16-bit delay slot, since the current position would then be
7232 in the middle of a branch. */
7233 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7235 relax32 = (mips_relax_branch
7236 /* Don't try branch relaxation within .set nomacro, or within
7237 .set noat if we use $at for PIC computations. If it turns
7238 out that the branch was out-of-range, we'll get an error. */
7239 && !mips_opts.warn_about_macros
7240 && (mips_opts.at || mips_pic == NO_PIC)
7241 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7242 as they have no complementing branches. */
7243 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7245 if (!HAVE_CODE_COMPRESSION
7248 && *reloc_type == BFD_RELOC_16_PCREL_S2
7249 && delayed_branch_p (ip))
7251 relaxed_branch = TRUE;
7252 add_relaxed_insn (ip, (relaxed_branch_length
7254 uncond_branch_p (ip) ? -1
7255 : branch_likely_p (ip) ? 1
7259 uncond_branch_p (ip),
7260 branch_likely_p (ip),
7261 pinfo & INSN_WRITE_GPR_31,
7263 address_expr->X_add_symbol,
7264 address_expr->X_add_number);
7265 *reloc_type = BFD_RELOC_UNUSED;
7267 else if (mips_opts.micromips
7269 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7270 || *reloc_type > BFD_RELOC_UNUSED)
7271 && (delayed_branch_p (ip) || compact_branch_p (ip))
7272 /* Don't try branch relaxation when users specify
7273 16-bit/32-bit instructions. */
7274 && !forced_insn_length)
7276 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
7277 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7278 int uncond = uncond_branch_p (ip) ? -1 : 0;
7279 int compact = compact_branch_p (ip);
7280 int al = pinfo & INSN_WRITE_GPR_31;
7283 gas_assert (address_expr != NULL);
7284 gas_assert (!mips_relax.sequence);
7286 relaxed_branch = TRUE;
7287 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7288 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
7289 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
7291 address_expr->X_add_symbol,
7292 address_expr->X_add_number);
7293 *reloc_type = BFD_RELOC_UNUSED;
7295 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7297 /* We need to set up a variant frag. */
7298 gas_assert (address_expr != NULL);
7299 add_relaxed_insn (ip, 4, 0,
7301 (*reloc_type - BFD_RELOC_UNUSED,
7302 forced_insn_length == 2, forced_insn_length == 4,
7303 delayed_branch_p (&history[0]),
7304 history[0].mips16_absolute_jump_p),
7305 make_expr_symbol (address_expr), 0);
7307 else if (mips_opts.mips16 && insn_length (ip) == 2)
7309 if (!delayed_branch_p (ip))
7310 /* Make sure there is enough room to swap this instruction with
7311 a following jump instruction. */
7313 add_fixed_insn (ip);
7317 if (mips_opts.mips16
7318 && mips_opts.noreorder
7319 && delayed_branch_p (&history[0]))
7320 as_warn (_("extended instruction in delay slot"));
7322 if (mips_relax.sequence)
7324 /* If we've reached the end of this frag, turn it into a variant
7325 frag and record the information for the instructions we've
7327 if (frag_room () < 4)
7328 relax_close_frag ();
7329 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7332 if (mips_relax.sequence != 2)
7334 if (mips_macro_warning.first_insn_sizes[0] == 0)
7335 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7336 mips_macro_warning.sizes[0] += insn_length (ip);
7337 mips_macro_warning.insns[0]++;
7339 if (mips_relax.sequence != 1)
7341 if (mips_macro_warning.first_insn_sizes[1] == 0)
7342 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7343 mips_macro_warning.sizes[1] += insn_length (ip);
7344 mips_macro_warning.insns[1]++;
7347 if (mips_opts.mips16)
7350 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7352 add_fixed_insn (ip);
7355 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7357 bfd_reloc_code_real_type final_type[3];
7358 reloc_howto_type *howto0;
7359 reloc_howto_type *howto;
7362 /* Perform any necessary conversion to microMIPS relocations
7363 and find out how many relocations there actually are. */
7364 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7365 final_type[i] = micromips_map_reloc (reloc_type[i]);
7367 /* In a compound relocation, it is the final (outermost)
7368 operator that determines the relocated field. */
7369 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7374 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7375 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7376 bfd_get_reloc_size (howto),
7378 howto0 && howto0->pc_relative,
7381 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7382 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7383 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7385 /* These relocations can have an addend that won't fit in
7386 4 octets for 64bit assembly. */
7388 && ! howto->partial_inplace
7389 && (reloc_type[0] == BFD_RELOC_16
7390 || reloc_type[0] == BFD_RELOC_32
7391 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7392 || reloc_type[0] == BFD_RELOC_GPREL16
7393 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7394 || reloc_type[0] == BFD_RELOC_GPREL32
7395 || reloc_type[0] == BFD_RELOC_64
7396 || reloc_type[0] == BFD_RELOC_CTOR
7397 || reloc_type[0] == BFD_RELOC_MIPS_SUB
7398 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
7399 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
7400 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
7401 || reloc_type[0] == BFD_RELOC_MIPS_REL16
7402 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
7403 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
7404 || hi16_reloc_p (reloc_type[0])
7405 || lo16_reloc_p (reloc_type[0])))
7406 ip->fixp[0]->fx_no_overflow = 1;
7408 /* These relocations can have an addend that won't fit in 2 octets. */
7409 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7410 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
7411 ip->fixp[0]->fx_no_overflow = 1;
7413 if (mips_relax.sequence)
7415 if (mips_relax.first_fixup == 0)
7416 mips_relax.first_fixup = ip->fixp[0];
7418 else if (reloc_needs_lo_p (*reloc_type))
7420 struct mips_hi_fixup *hi_fixup;
7422 /* Reuse the last entry if it already has a matching %lo. */
7423 hi_fixup = mips_hi_fixup_list;
7425 || !fixup_has_matching_lo_p (hi_fixup->fixp))
7427 hi_fixup = XNEW (struct mips_hi_fixup);
7428 hi_fixup->next = mips_hi_fixup_list;
7429 mips_hi_fixup_list = hi_fixup;
7431 hi_fixup->fixp = ip->fixp[0];
7432 hi_fixup->seg = now_seg;
7435 /* Add fixups for the second and third relocations, if given.
7436 Note that the ABI allows the second relocation to be
7437 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7438 moment we only use RSS_UNDEF, but we could add support
7439 for the others if it ever becomes necessary. */
7440 for (i = 1; i < 3; i++)
7441 if (reloc_type[i] != BFD_RELOC_UNUSED)
7443 ip->fixp[i] = fix_new (ip->frag, ip->where,
7444 ip->fixp[0]->fx_size, NULL, 0,
7445 FALSE, final_type[i]);
7447 /* Use fx_tcbit to mark compound relocs. */
7448 ip->fixp[0]->fx_tcbit = 1;
7449 ip->fixp[i]->fx_tcbit = 1;
7454 /* Update the register mask information. */
7455 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
7456 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
7461 insert_into_history (0, 1, ip);
7464 case APPEND_ADD_WITH_NOP:
7466 struct mips_cl_insn *nop;
7468 insert_into_history (0, 1, ip);
7469 nop = get_delay_slot_nop (ip);
7470 add_fixed_insn (nop);
7471 insert_into_history (0, 1, nop);
7472 if (mips_relax.sequence)
7473 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
7477 case APPEND_ADD_COMPACT:
7478 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7479 gas_assert (mips_opts.mips16);
7480 ip->insn_opcode |= 0x0080;
7481 find_altered_mips16_opcode (ip);
7483 insert_into_history (0, 1, ip);
7488 struct mips_cl_insn delay = history[0];
7489 if (mips_opts.mips16)
7491 know (delay.frag == ip->frag);
7492 move_insn (ip, delay.frag, delay.where);
7493 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
7495 else if (relaxed_branch || delay.frag != ip->frag)
7497 /* Add the delay slot instruction to the end of the
7498 current frag and shrink the fixed part of the
7499 original frag. If the branch occupies the tail of
7500 the latter, move it backwards to cover the gap. */
7501 delay.frag->fr_fix -= branch_disp;
7502 if (delay.frag == ip->frag)
7503 move_insn (ip, ip->frag, ip->where - branch_disp);
7504 add_fixed_insn (&delay);
7508 move_insn (&delay, ip->frag,
7509 ip->where - branch_disp + insn_length (ip));
7510 move_insn (ip, history[0].frag, history[0].where);
7514 insert_into_history (0, 1, &delay);
7519 /* If we have just completed an unconditional branch, clear the history. */
7520 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
7521 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
7525 mips_no_prev_insn ();
7527 for (i = 0; i < ARRAY_SIZE (history); i++)
7528 history[i].cleared_p = 1;
7531 /* We need to emit a label at the end of branch-likely macros. */
7532 if (emit_branch_likely_macro)
7534 emit_branch_likely_macro = FALSE;
7535 micromips_add_label ();
7538 /* We just output an insn, so the next one doesn't have a label. */
7539 mips_clear_insn_labels ();
7542 /* Forget that there was any previous instruction or label.
7543 When BRANCH is true, the branch history is also flushed. */
7546 mips_no_prev_insn (void)
7548 prev_nop_frag = NULL;
7549 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
7550 mips_clear_insn_labels ();
7553 /* This function must be called before we emit something other than
7554 instructions. It is like mips_no_prev_insn except that it inserts
7555 any NOPS that might be needed by previous instructions. */
7558 mips_emit_delays (void)
7560 if (! mips_opts.noreorder)
7562 int nops = nops_for_insn (0, history, NULL);
7566 add_fixed_insn (NOP_INSN);
7567 mips_move_text_labels ();
7570 mips_no_prev_insn ();
7573 /* Start a (possibly nested) noreorder block. */
7576 start_noreorder (void)
7578 if (mips_opts.noreorder == 0)
7583 /* None of the instructions before the .set noreorder can be moved. */
7584 for (i = 0; i < ARRAY_SIZE (history); i++)
7585 history[i].fixed_p = 1;
7587 /* Insert any nops that might be needed between the .set noreorder
7588 block and the previous instructions. We will later remove any
7589 nops that turn out not to be needed. */
7590 nops = nops_for_insn (0, history, NULL);
7593 if (mips_optimize != 0)
7595 /* Record the frag which holds the nop instructions, so
7596 that we can remove them if we don't need them. */
7597 frag_grow (nops * NOP_INSN_SIZE);
7598 prev_nop_frag = frag_now;
7599 prev_nop_frag_holds = nops;
7600 prev_nop_frag_required = 0;
7601 prev_nop_frag_since = 0;
7604 for (; nops > 0; --nops)
7605 add_fixed_insn (NOP_INSN);
7607 /* Move on to a new frag, so that it is safe to simply
7608 decrease the size of prev_nop_frag. */
7609 frag_wane (frag_now);
7611 mips_move_text_labels ();
7613 mips_mark_labels ();
7614 mips_clear_insn_labels ();
7616 mips_opts.noreorder++;
7617 mips_any_noreorder = 1;
7620 /* End a nested noreorder block. */
7623 end_noreorder (void)
7625 mips_opts.noreorder--;
7626 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7628 /* Commit to inserting prev_nop_frag_required nops and go back to
7629 handling nop insertion the .set reorder way. */
7630 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7632 insert_into_history (prev_nop_frag_since,
7633 prev_nop_frag_required, NOP_INSN);
7634 prev_nop_frag = NULL;
7638 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7639 higher bits unset. */
7642 normalize_constant_expr (expressionS *ex)
7644 if (ex->X_op == O_constant
7645 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7646 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7650 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7651 all higher bits unset. */
7654 normalize_address_expr (expressionS *ex)
7656 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7657 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7658 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7659 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7663 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7664 Return true if the match was successful.
7666 OPCODE_EXTRA is a value that should be ORed into the opcode
7667 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7668 there are more alternatives after OPCODE and SOFT_MATCH is
7669 as for mips_arg_info. */
7672 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7673 struct mips_operand_token *tokens, unsigned int opcode_extra,
7674 bfd_boolean lax_match, bfd_boolean complete_p)
7677 struct mips_arg_info arg;
7678 const struct mips_operand *operand;
7681 imm_expr.X_op = O_absent;
7682 offset_expr.X_op = O_absent;
7683 offset_reloc[0] = BFD_RELOC_UNUSED;
7684 offset_reloc[1] = BFD_RELOC_UNUSED;
7685 offset_reloc[2] = BFD_RELOC_UNUSED;
7687 create_insn (insn, opcode);
7688 /* When no opcode suffix is specified, assume ".xyzw". */
7689 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
7690 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
7692 insn->insn_opcode |= opcode_extra;
7693 memset (&arg, 0, sizeof (arg));
7697 arg.last_regno = ILLEGAL_REG;
7698 arg.dest_regno = ILLEGAL_REG;
7699 arg.lax_match = lax_match;
7700 for (args = opcode->args;; ++args)
7702 if (arg.token->type == OT_END)
7704 /* Handle unary instructions in which only one operand is given.
7705 The source is then the same as the destination. */
7706 if (arg.opnum == 1 && *args == ',')
7708 operand = (mips_opts.micromips
7709 ? decode_micromips_operand (args + 1)
7710 : decode_mips_operand (args + 1));
7711 if (operand && mips_optional_operand_p (operand))
7719 /* Treat elided base registers as $0. */
7720 if (strcmp (args, "(b)") == 0)
7728 /* The register suffix is optional. */
7733 /* Fail the match if there were too few operands. */
7737 /* Successful match. */
7740 clear_insn_error ();
7741 if (arg.dest_regno == arg.last_regno
7742 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7746 (0, _("source and destination must be different"));
7747 else if (arg.last_regno == 31)
7749 (0, _("a destination register must be supplied"));
7751 else if (arg.last_regno == 31
7752 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0
7753 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
7754 set_insn_error (0, _("the source register must not be $31"));
7755 check_completed_insn (&arg);
7759 /* Fail the match if the line has too many operands. */
7763 /* Handle characters that need to match exactly. */
7764 if (*args == '(' || *args == ')' || *args == ',')
7766 if (match_char (&arg, *args))
7773 if (arg.token->type == OT_DOUBLE_CHAR
7774 && arg.token->u.ch == *args)
7782 /* Handle special macro operands. Work out the properties of
7791 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
7795 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
7804 *offset_reloc = BFD_RELOC_MIPS_JMP;
7808 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
7812 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
7818 if (!match_const_int (&arg, &imm_expr.X_add_number))
7820 imm_expr.X_op = O_constant;
7822 normalize_constant_expr (&imm_expr);
7826 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7828 /* Assume that the offset has been elided and that what
7829 we saw was a base register. The match will fail later
7830 if that assumption turns out to be wrong. */
7831 offset_expr.X_op = O_constant;
7832 offset_expr.X_add_number = 0;
7836 if (!match_expression (&arg, &offset_expr, offset_reloc))
7838 normalize_address_expr (&offset_expr);
7843 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7849 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7855 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7861 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7867 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7871 *offset_reloc = BFD_RELOC_MIPS_JMP;
7875 gas_assert (mips_opts.micromips);
7881 if (!forced_insn_length)
7882 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7884 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7886 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7892 operand = (mips_opts.micromips
7893 ? decode_micromips_operand (args)
7894 : decode_mips_operand (args));
7898 /* Skip prefixes. */
7899 if (*args == '+' || *args == 'm' || *args == '-')
7902 if (mips_optional_operand_p (operand)
7904 && (arg.token[0].type != OT_REG
7905 || arg.token[1].type == OT_END))
7907 /* Assume that the register has been elided and is the
7908 same as the first operand. */
7913 if (!match_operand (&arg, operand))
7918 /* Like match_insn, but for MIPS16. */
7921 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7922 struct mips_operand_token *tokens)
7925 const struct mips_operand *operand;
7926 const struct mips_operand *ext_operand;
7927 struct mips_arg_info arg;
7930 create_insn (insn, opcode);
7931 imm_expr.X_op = O_absent;
7932 offset_expr.X_op = O_absent;
7933 offset_reloc[0] = BFD_RELOC_UNUSED;
7934 offset_reloc[1] = BFD_RELOC_UNUSED;
7935 offset_reloc[2] = BFD_RELOC_UNUSED;
7938 memset (&arg, 0, sizeof (arg));
7942 arg.last_regno = ILLEGAL_REG;
7943 arg.dest_regno = ILLEGAL_REG;
7945 for (args = opcode->args;; ++args)
7949 if (arg.token->type == OT_END)
7953 /* Handle unary instructions in which only one operand is given.
7954 The source is then the same as the destination. */
7955 if (arg.opnum == 1 && *args == ',')
7957 operand = decode_mips16_operand (args[1], FALSE);
7958 if (operand && mips_optional_operand_p (operand))
7966 /* Fail the match if there were too few operands. */
7970 /* Successful match. Stuff the immediate value in now, if
7972 clear_insn_error ();
7973 if (opcode->pinfo == INSN_MACRO)
7975 gas_assert (relax_char == 0 || relax_char == 'p');
7976 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7979 && offset_expr.X_op == O_constant
7980 && calculate_reloc (*offset_reloc,
7981 offset_expr.X_add_number,
7984 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7985 forced_insn_length, &insn->insn_opcode);
7986 offset_expr.X_op = O_absent;
7987 *offset_reloc = BFD_RELOC_UNUSED;
7989 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7991 if (forced_insn_length == 2)
7992 set_insn_error (0, _("invalid unextended operand value"));
7993 forced_insn_length = 4;
7994 insn->insn_opcode |= MIPS16_EXTEND;
7996 else if (relax_char)
7997 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7999 check_completed_insn (&arg);
8003 /* Fail the match if the line has too many operands. */
8007 /* Handle characters that need to match exactly. */
8008 if (*args == '(' || *args == ')' || *args == ',')
8010 if (match_char (&arg, *args))
8028 if (!match_const_int (&arg, &imm_expr.X_add_number))
8030 imm_expr.X_op = O_constant;
8032 normalize_constant_expr (&imm_expr);
8037 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8038 insn->insn_opcode <<= 16;
8042 operand = decode_mips16_operand (c, FALSE);
8046 /* '6' is a special case. It is used for BREAK and SDBBP,
8047 whose operands are only meaningful to the software that decodes
8048 them. This means that there is no architectural reason why
8049 they cannot be prefixed by EXTEND, but in practice,
8050 exception handlers will only look at the instruction
8051 itself. We therefore allow '6' to be extended when
8052 disassembling but not when assembling. */
8053 if (operand->type != OP_PCREL && c != '6')
8055 ext_operand = decode_mips16_operand (c, TRUE);
8056 if (operand != ext_operand)
8058 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8060 offset_expr.X_op = O_constant;
8061 offset_expr.X_add_number = 0;
8066 /* We need the OT_INTEGER check because some MIPS16
8067 immediate variants are listed before the register ones. */
8068 if (arg.token->type != OT_INTEGER
8069 || !match_expression (&arg, &offset_expr, offset_reloc))
8072 /* '8' is used for SLTI(U) and has traditionally not
8073 been allowed to take relocation operators. */
8074 if (offset_reloc[0] != BFD_RELOC_UNUSED
8075 && (ext_operand->size != 16 || c == '8'))
8083 if (mips_optional_operand_p (operand)
8085 && (arg.token[0].type != OT_REG
8086 || arg.token[1].type == OT_END))
8088 /* Assume that the register has been elided and is the
8089 same as the first operand. */
8094 if (!match_operand (&arg, operand))
8099 /* Record that the current instruction is invalid for the current ISA. */
8102 match_invalid_for_isa (void)
8105 (0, _("opcode not supported on this processor: %s (%s)"),
8106 mips_cpu_info_from_arch (mips_opts.arch)->name,
8107 mips_cpu_info_from_isa (mips_opts.isa)->name);
8110 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8111 Return true if a definite match or failure was found, storing any match
8112 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8113 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8114 tried and failed to match under normal conditions and now want to try a
8115 more relaxed match. */
8118 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8119 const struct mips_opcode *past, struct mips_operand_token *tokens,
8120 int opcode_extra, bfd_boolean lax_match)
8122 const struct mips_opcode *opcode;
8123 const struct mips_opcode *invalid_delay_slot;
8124 bfd_boolean seen_valid_for_isa, seen_valid_for_size;
8126 /* Search for a match, ignoring alternatives that don't satisfy the
8127 current ISA or forced_length. */
8128 invalid_delay_slot = 0;
8129 seen_valid_for_isa = FALSE;
8130 seen_valid_for_size = FALSE;
8134 gas_assert (strcmp (opcode->name, first->name) == 0);
8135 if (is_opcode_valid (opcode))
8137 seen_valid_for_isa = TRUE;
8138 if (is_size_valid (opcode))
8140 bfd_boolean delay_slot_ok;
8142 seen_valid_for_size = TRUE;
8143 delay_slot_ok = is_delay_slot_valid (opcode);
8144 if (match_insn (insn, opcode, tokens, opcode_extra,
8145 lax_match, delay_slot_ok))
8149 if (!invalid_delay_slot)
8150 invalid_delay_slot = opcode;
8159 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8161 /* If the only matches we found had the wrong length for the delay slot,
8162 pick the first such match. We'll issue an appropriate warning later. */
8163 if (invalid_delay_slot)
8165 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8171 /* Handle the case where we didn't try to match an instruction because
8172 all the alternatives were incompatible with the current ISA. */
8173 if (!seen_valid_for_isa)
8175 match_invalid_for_isa ();
8179 /* Handle the case where we didn't try to match an instruction because
8180 all the alternatives were of the wrong size. */
8181 if (!seen_valid_for_size)
8183 if (mips_opts.insn32)
8184 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8187 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8188 8 * forced_insn_length);
8195 /* Like match_insns, but for MIPS16. */
8198 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8199 struct mips_operand_token *tokens)
8201 const struct mips_opcode *opcode;
8202 bfd_boolean seen_valid_for_isa;
8204 /* Search for a match, ignoring alternatives that don't satisfy the
8205 current ISA. There are no separate entries for extended forms so
8206 we deal with forced_length later. */
8207 seen_valid_for_isa = FALSE;
8211 gas_assert (strcmp (opcode->name, first->name) == 0);
8212 if (is_opcode_valid_16 (opcode))
8214 seen_valid_for_isa = TRUE;
8215 if (match_mips16_insn (insn, opcode, tokens))
8220 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8221 && strcmp (opcode->name, first->name) == 0);
8223 /* Handle the case where we didn't try to match an instruction because
8224 all the alternatives were incompatible with the current ISA. */
8225 if (!seen_valid_for_isa)
8227 match_invalid_for_isa ();
8234 /* Set up global variables for the start of a new macro. */
8239 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8240 memset (&mips_macro_warning.first_insn_sizes, 0,
8241 sizeof (mips_macro_warning.first_insn_sizes));
8242 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8243 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8244 && delayed_branch_p (&history[0]));
8245 switch (history[0].insn_mo->pinfo2
8246 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8248 case INSN2_BRANCH_DELAY_32BIT:
8249 mips_macro_warning.delay_slot_length = 4;
8251 case INSN2_BRANCH_DELAY_16BIT:
8252 mips_macro_warning.delay_slot_length = 2;
8255 mips_macro_warning.delay_slot_length = 0;
8258 mips_macro_warning.first_frag = NULL;
8261 /* Given that a macro is longer than one instruction or of the wrong size,
8262 return the appropriate warning for it. Return null if no warning is
8263 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8264 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8265 and RELAX_NOMACRO. */
8268 macro_warning (relax_substateT subtype)
8270 if (subtype & RELAX_DELAY_SLOT)
8271 return _("macro instruction expanded into multiple instructions"
8272 " in a branch delay slot");
8273 else if (subtype & RELAX_NOMACRO)
8274 return _("macro instruction expanded into multiple instructions");
8275 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8276 | RELAX_DELAY_SLOT_SIZE_SECOND))
8277 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8278 ? _("macro instruction expanded into a wrong size instruction"
8279 " in a 16-bit branch delay slot")
8280 : _("macro instruction expanded into a wrong size instruction"
8281 " in a 32-bit branch delay slot"));
8286 /* Finish up a macro. Emit warnings as appropriate. */
8291 /* Relaxation warning flags. */
8292 relax_substateT subtype = 0;
8294 /* Check delay slot size requirements. */
8295 if (mips_macro_warning.delay_slot_length == 2)
8296 subtype |= RELAX_DELAY_SLOT_16BIT;
8297 if (mips_macro_warning.delay_slot_length != 0)
8299 if (mips_macro_warning.delay_slot_length
8300 != mips_macro_warning.first_insn_sizes[0])
8301 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8302 if (mips_macro_warning.delay_slot_length
8303 != mips_macro_warning.first_insn_sizes[1])
8304 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8307 /* Check instruction count requirements. */
8308 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8310 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8311 subtype |= RELAX_SECOND_LONGER;
8312 if (mips_opts.warn_about_macros)
8313 subtype |= RELAX_NOMACRO;
8314 if (mips_macro_warning.delay_slot_p)
8315 subtype |= RELAX_DELAY_SLOT;
8318 /* If both alternatives fail to fill a delay slot correctly,
8319 emit the warning now. */
8320 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
8321 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
8326 s = subtype & (RELAX_DELAY_SLOT_16BIT
8327 | RELAX_DELAY_SLOT_SIZE_FIRST
8328 | RELAX_DELAY_SLOT_SIZE_SECOND);
8329 msg = macro_warning (s);
8331 as_warn ("%s", msg);
8335 /* If both implementations are longer than 1 instruction, then emit the
8337 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
8342 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
8343 msg = macro_warning (s);
8345 as_warn ("%s", msg);
8349 /* If any flags still set, then one implementation might need a warning
8350 and the other either will need one of a different kind or none at all.
8351 Pass any remaining flags over to relaxation. */
8352 if (mips_macro_warning.first_frag != NULL)
8353 mips_macro_warning.first_frag->fr_subtype |= subtype;
8356 /* Instruction operand formats used in macros that vary between
8357 standard MIPS and microMIPS code. */
8359 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
8360 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
8361 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
8362 static const char * const lui_fmt[2] = { "t,u", "s,u" };
8363 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
8364 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
8365 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
8366 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
8368 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8369 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8370 : cop12_fmt[mips_opts.micromips])
8371 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8372 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8373 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8374 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8375 : mem12_fmt[mips_opts.micromips])
8376 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8377 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8378 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8380 /* Read a macro's relocation codes from *ARGS and store them in *R.
8381 The first argument in *ARGS will be either the code for a single
8382 relocation or -1 followed by the three codes that make up a
8383 composite relocation. */
8386 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
8390 next = va_arg (*args, int);
8392 r[0] = (bfd_reloc_code_real_type) next;
8395 for (i = 0; i < 3; i++)
8396 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
8397 /* This function is only used for 16-bit relocation fields.
8398 To make the macro code simpler, treat an unrelocated value
8399 in the same way as BFD_RELOC_LO16. */
8400 if (r[0] == BFD_RELOC_UNUSED)
8401 r[0] = BFD_RELOC_LO16;
8405 /* Build an instruction created by a macro expansion. This is passed
8406 a pointer to the count of instructions created so far, an
8407 expression, the name of the instruction to build, an operand format
8408 string, and corresponding arguments. */
8411 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
8413 const struct mips_opcode *mo = NULL;
8414 bfd_reloc_code_real_type r[3];
8415 const struct mips_opcode *amo;
8416 const struct mips_operand *operand;
8417 struct hash_control *hash;
8418 struct mips_cl_insn insn;
8422 va_start (args, fmt);
8424 if (mips_opts.mips16)
8426 mips16_macro_build (ep, name, fmt, &args);
8431 r[0] = BFD_RELOC_UNUSED;
8432 r[1] = BFD_RELOC_UNUSED;
8433 r[2] = BFD_RELOC_UNUSED;
8434 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
8435 amo = (struct mips_opcode *) hash_find (hash, name);
8437 gas_assert (strcmp (name, amo->name) == 0);
8441 /* Search until we get a match for NAME. It is assumed here that
8442 macros will never generate MDMX, MIPS-3D, or MT instructions.
8443 We try to match an instruction that fulfils the branch delay
8444 slot instruction length requirement (if any) of the previous
8445 instruction. While doing this we record the first instruction
8446 seen that matches all the other conditions and use it anyway
8447 if the requirement cannot be met; we will issue an appropriate
8448 warning later on. */
8449 if (strcmp (fmt, amo->args) == 0
8450 && amo->pinfo != INSN_MACRO
8451 && is_opcode_valid (amo)
8452 && is_size_valid (amo))
8454 if (is_delay_slot_valid (amo))
8464 gas_assert (amo->name);
8466 while (strcmp (name, amo->name) == 0);
8469 create_insn (&insn, mo);
8482 macro_read_relocs (&args, r);
8483 gas_assert (*r == BFD_RELOC_GPREL16
8484 || *r == BFD_RELOC_MIPS_HIGHER
8485 || *r == BFD_RELOC_HI16_S
8486 || *r == BFD_RELOC_LO16
8487 || *r == BFD_RELOC_MIPS_GOT_OFST);
8491 macro_read_relocs (&args, r);
8495 macro_read_relocs (&args, r);
8496 gas_assert (ep != NULL
8497 && (ep->X_op == O_constant
8498 || (ep->X_op == O_symbol
8499 && (*r == BFD_RELOC_MIPS_HIGHEST
8500 || *r == BFD_RELOC_HI16_S
8501 || *r == BFD_RELOC_HI16
8502 || *r == BFD_RELOC_GPREL16
8503 || *r == BFD_RELOC_MIPS_GOT_HI16
8504 || *r == BFD_RELOC_MIPS_CALL_HI16))));
8508 gas_assert (ep != NULL);
8511 * This allows macro() to pass an immediate expression for
8512 * creating short branches without creating a symbol.
8514 * We don't allow branch relaxation for these branches, as
8515 * they should only appear in ".set nomacro" anyway.
8517 if (ep->X_op == O_constant)
8519 /* For microMIPS we always use relocations for branches.
8520 So we should not resolve immediate values. */
8521 gas_assert (!mips_opts.micromips);
8523 if ((ep->X_add_number & 3) != 0)
8524 as_bad (_("branch to misaligned address (0x%lx)"),
8525 (unsigned long) ep->X_add_number);
8526 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
8527 as_bad (_("branch address range overflow (0x%lx)"),
8528 (unsigned long) ep->X_add_number);
8529 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
8533 *r = BFD_RELOC_16_PCREL_S2;
8537 gas_assert (ep != NULL);
8538 *r = BFD_RELOC_MIPS_JMP;
8542 operand = (mips_opts.micromips
8543 ? decode_micromips_operand (fmt)
8544 : decode_mips_operand (fmt));
8548 uval = va_arg (args, int);
8549 if (operand->type == OP_CLO_CLZ_DEST)
8550 uval |= (uval << 5);
8551 insn_insert_operand (&insn, operand, uval);
8553 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
8559 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8561 append_insn (&insn, ep, r, TRUE);
8565 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
8568 struct mips_opcode *mo;
8569 struct mips_cl_insn insn;
8570 const struct mips_operand *operand;
8571 bfd_reloc_code_real_type r[3]
8572 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
8574 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
8576 gas_assert (strcmp (name, mo->name) == 0);
8578 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
8581 gas_assert (mo->name);
8582 gas_assert (strcmp (name, mo->name) == 0);
8585 create_insn (&insn, mo);
8623 gas_assert (ep != NULL);
8625 if (ep->X_op != O_constant)
8626 *r = (int) BFD_RELOC_UNUSED + c;
8627 else if (calculate_reloc (*r, ep->X_add_number, &value))
8629 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
8631 *r = BFD_RELOC_UNUSED;
8637 operand = decode_mips16_operand (c, FALSE);
8641 insn_insert_operand (&insn, operand, va_arg (*args, int));
8646 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
8648 append_insn (&insn, ep, r, TRUE);
8652 * Generate a "jalr" instruction with a relocation hint to the called
8653 * function. This occurs in NewABI PIC code.
8656 macro_build_jalr (expressionS *ep, int cprestore)
8658 static const bfd_reloc_code_real_type jalr_relocs[2]
8659 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
8660 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
8664 if (MIPS_JALR_HINT_P (ep))
8669 if (mips_opts.micromips)
8671 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
8672 ? "jalr" : "jalrs");
8673 if (MIPS_JALR_HINT_P (ep)
8675 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8676 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
8678 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
8681 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
8682 if (MIPS_JALR_HINT_P (ep))
8683 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
8687 * Generate a "lui" instruction.
8690 macro_build_lui (expressionS *ep, int regnum)
8692 gas_assert (! mips_opts.mips16);
8694 if (ep->X_op != O_constant)
8696 gas_assert (ep->X_op == O_symbol);
8697 /* _gp_disp is a special case, used from s_cpload.
8698 __gnu_local_gp is used if mips_no_shared. */
8699 gas_assert (mips_pic == NO_PIC
8701 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
8702 || (! mips_in_shared
8703 && strcmp (S_GET_NAME (ep->X_add_symbol),
8704 "__gnu_local_gp") == 0));
8707 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
8710 /* Generate a sequence of instructions to do a load or store from a constant
8711 offset off of a base register (breg) into/from a target register (treg),
8712 using AT if necessary. */
8714 macro_build_ldst_constoffset (expressionS *ep, const char *op,
8715 int treg, int breg, int dbl)
8717 gas_assert (ep->X_op == O_constant);
8719 /* Sign-extending 32-bit constants makes their handling easier. */
8721 normalize_constant_expr (ep);
8723 /* Right now, this routine can only handle signed 32-bit constants. */
8724 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
8725 as_warn (_("operand overflow"));
8727 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
8729 /* Signed 16-bit offset will fit in the op. Easy! */
8730 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8734 /* 32-bit offset, need multiple instructions and AT, like:
8735 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8736 addu $tempreg,$tempreg,$breg
8737 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8738 to handle the complete offset. */
8739 macro_build_lui (ep, AT);
8740 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8741 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8744 as_bad (_("macro used $at after \".set noat\""));
8749 * Generates code to set the $at register to true (one)
8750 * if reg is less than the immediate expression.
8753 set_at (int reg, int unsignedp)
8755 if (imm_expr.X_add_number >= -0x8000
8756 && imm_expr.X_add_number < 0x8000)
8757 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8758 AT, reg, BFD_RELOC_LO16);
8761 load_register (AT, &imm_expr, GPR_SIZE == 64);
8762 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8766 /* Count the leading zeroes by performing a binary chop. This is a
8767 bulky bit of source, but performance is a LOT better for the
8768 majority of values than a simple loop to count the bits:
8769 for (lcnt = 0; (lcnt < 32); lcnt++)
8770 if ((v) & (1 << (31 - lcnt)))
8772 However it is not code size friendly, and the gain will drop a bit
8773 on certain cached systems.
8775 #define COUNT_TOP_ZEROES(v) \
8776 (((v) & ~0xffff) == 0 \
8777 ? ((v) & ~0xff) == 0 \
8778 ? ((v) & ~0xf) == 0 \
8779 ? ((v) & ~0x3) == 0 \
8780 ? ((v) & ~0x1) == 0 \
8785 : ((v) & ~0x7) == 0 \
8788 : ((v) & ~0x3f) == 0 \
8789 ? ((v) & ~0x1f) == 0 \
8792 : ((v) & ~0x7f) == 0 \
8795 : ((v) & ~0xfff) == 0 \
8796 ? ((v) & ~0x3ff) == 0 \
8797 ? ((v) & ~0x1ff) == 0 \
8800 : ((v) & ~0x7ff) == 0 \
8803 : ((v) & ~0x3fff) == 0 \
8804 ? ((v) & ~0x1fff) == 0 \
8807 : ((v) & ~0x7fff) == 0 \
8810 : ((v) & ~0xffffff) == 0 \
8811 ? ((v) & ~0xfffff) == 0 \
8812 ? ((v) & ~0x3ffff) == 0 \
8813 ? ((v) & ~0x1ffff) == 0 \
8816 : ((v) & ~0x7ffff) == 0 \
8819 : ((v) & ~0x3fffff) == 0 \
8820 ? ((v) & ~0x1fffff) == 0 \
8823 : ((v) & ~0x7fffff) == 0 \
8826 : ((v) & ~0xfffffff) == 0 \
8827 ? ((v) & ~0x3ffffff) == 0 \
8828 ? ((v) & ~0x1ffffff) == 0 \
8831 : ((v) & ~0x7ffffff) == 0 \
8834 : ((v) & ~0x3fffffff) == 0 \
8835 ? ((v) & ~0x1fffffff) == 0 \
8838 : ((v) & ~0x7fffffff) == 0 \
8843 * This routine generates the least number of instructions necessary to load
8844 * an absolute expression value into a register.
8847 load_register (int reg, expressionS *ep, int dbl)
8850 expressionS hi32, lo32;
8852 if (ep->X_op != O_big)
8854 gas_assert (ep->X_op == O_constant);
8856 /* Sign-extending 32-bit constants makes their handling easier. */
8858 normalize_constant_expr (ep);
8860 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8862 /* We can handle 16 bit signed values with an addiu to
8863 $zero. No need to ever use daddiu here, since $zero and
8864 the result are always correct in 32 bit mode. */
8865 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8868 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8870 /* We can handle 16 bit unsigned values with an ori to
8872 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8875 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8877 /* 32 bit values require an lui. */
8878 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8879 if ((ep->X_add_number & 0xffff) != 0)
8880 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8885 /* The value is larger than 32 bits. */
8887 if (!dbl || GPR_SIZE == 32)
8891 sprintf_vma (value, ep->X_add_number);
8892 as_bad (_("number (0x%s) larger than 32 bits"), value);
8893 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8897 if (ep->X_op != O_big)
8900 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8901 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8902 hi32.X_add_number &= 0xffffffff;
8904 lo32.X_add_number &= 0xffffffff;
8908 gas_assert (ep->X_add_number > 2);
8909 if (ep->X_add_number == 3)
8910 generic_bignum[3] = 0;
8911 else if (ep->X_add_number > 4)
8912 as_bad (_("number larger than 64 bits"));
8913 lo32.X_op = O_constant;
8914 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8915 hi32.X_op = O_constant;
8916 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8919 if (hi32.X_add_number == 0)
8924 unsigned long hi, lo;
8926 if (hi32.X_add_number == (offsetT) 0xffffffff)
8928 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8930 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8933 if (lo32.X_add_number & 0x80000000)
8935 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8936 if (lo32.X_add_number & 0xffff)
8937 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8942 /* Check for 16bit shifted constant. We know that hi32 is
8943 non-zero, so start the mask on the first bit of the hi32
8948 unsigned long himask, lomask;
8952 himask = 0xffff >> (32 - shift);
8953 lomask = (0xffff << shift) & 0xffffffff;
8957 himask = 0xffff << (shift - 32);
8960 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8961 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8965 tmp.X_op = O_constant;
8967 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8968 | (lo32.X_add_number >> shift));
8970 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
8971 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8972 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8973 reg, reg, (shift >= 32) ? shift - 32 : shift);
8978 while (shift <= (64 - 16));
8980 /* Find the bit number of the lowest one bit, and store the
8981 shifted value in hi/lo. */
8982 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8983 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8987 while ((lo & 1) == 0)
8992 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8998 while ((hi & 1) == 0)
9007 /* Optimize if the shifted value is a (power of 2) - 1. */
9008 if ((hi == 0 && ((lo + 1) & lo) == 0)
9009 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9011 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9016 /* This instruction will set the register to be all
9018 tmp.X_op = O_constant;
9019 tmp.X_add_number = (offsetT) -1;
9020 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9024 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9025 reg, reg, (bit >= 32) ? bit - 32 : bit);
9027 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9028 reg, reg, (shift >= 32) ? shift - 32 : shift);
9033 /* Sign extend hi32 before calling load_register, because we can
9034 generally get better code when we load a sign extended value. */
9035 if ((hi32.X_add_number & 0x80000000) != 0)
9036 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9037 load_register (reg, &hi32, 0);
9040 if ((lo32.X_add_number & 0xffff0000) == 0)
9044 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9052 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9054 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9055 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9061 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9065 mid16.X_add_number >>= 16;
9066 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9067 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9070 if ((lo32.X_add_number & 0xffff) != 0)
9071 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9075 load_delay_nop (void)
9077 if (!gpr_interlocks)
9078 macro_build (NULL, "nop", "");
9081 /* Load an address into a register. */
9084 load_address (int reg, expressionS *ep, int *used_at)
9086 if (ep->X_op != O_constant
9087 && ep->X_op != O_symbol)
9089 as_bad (_("expression too complex"));
9090 ep->X_op = O_constant;
9093 if (ep->X_op == O_constant)
9095 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9099 if (mips_pic == NO_PIC)
9101 /* If this is a reference to a GP relative symbol, we want
9102 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9104 lui $reg,<sym> (BFD_RELOC_HI16_S)
9105 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9106 If we have an addend, we always use the latter form.
9108 With 64bit address space and a usable $at we want
9109 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9110 lui $at,<sym> (BFD_RELOC_HI16_S)
9111 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9112 daddiu $at,<sym> (BFD_RELOC_LO16)
9116 If $at is already in use, we use a path which is suboptimal
9117 on superscalar processors.
9118 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9119 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9121 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9123 daddiu $reg,<sym> (BFD_RELOC_LO16)
9125 For GP relative symbols in 64bit address space we can use
9126 the same sequence as in 32bit address space. */
9127 if (HAVE_64BIT_SYMBOLS)
9129 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9130 && !nopic_need_relax (ep->X_add_symbol, 1))
9132 relax_start (ep->X_add_symbol);
9133 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9134 mips_gp_register, BFD_RELOC_GPREL16);
9138 if (*used_at == 0 && mips_opts.at)
9140 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9141 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9142 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9143 BFD_RELOC_MIPS_HIGHER);
9144 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9145 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9146 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9151 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9152 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9153 BFD_RELOC_MIPS_HIGHER);
9154 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9155 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9156 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9157 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9160 if (mips_relax.sequence)
9165 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9166 && !nopic_need_relax (ep->X_add_symbol, 1))
9168 relax_start (ep->X_add_symbol);
9169 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9170 mips_gp_register, BFD_RELOC_GPREL16);
9173 macro_build_lui (ep, reg);
9174 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9175 reg, reg, BFD_RELOC_LO16);
9176 if (mips_relax.sequence)
9180 else if (!mips_big_got)
9184 /* If this is a reference to an external symbol, we want
9185 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9187 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9189 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9190 If there is a constant, it must be added in after.
9192 If we have NewABI, we want
9193 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9194 unless we're referencing a global symbol with a non-zero
9195 offset, in which case cst must be added separately. */
9198 if (ep->X_add_number)
9200 ex.X_add_number = ep->X_add_number;
9201 ep->X_add_number = 0;
9202 relax_start (ep->X_add_symbol);
9203 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9204 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9205 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9206 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9207 ex.X_op = O_constant;
9208 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9209 reg, reg, BFD_RELOC_LO16);
9210 ep->X_add_number = ex.X_add_number;
9213 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9214 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9215 if (mips_relax.sequence)
9220 ex.X_add_number = ep->X_add_number;
9221 ep->X_add_number = 0;
9222 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9223 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9225 relax_start (ep->X_add_symbol);
9227 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9231 if (ex.X_add_number != 0)
9233 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9234 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9235 ex.X_op = O_constant;
9236 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9237 reg, reg, BFD_RELOC_LO16);
9241 else if (mips_big_got)
9245 /* This is the large GOT case. If this is a reference to an
9246 external symbol, we want
9247 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9249 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9251 Otherwise, for a reference to a local symbol in old ABI, we want
9252 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9254 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9255 If there is a constant, it must be added in after.
9257 In the NewABI, for local symbols, with or without offsets, we want:
9258 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9259 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9263 ex.X_add_number = ep->X_add_number;
9264 ep->X_add_number = 0;
9265 relax_start (ep->X_add_symbol);
9266 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9267 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9268 reg, reg, mips_gp_register);
9269 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9270 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9271 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9272 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9273 else if (ex.X_add_number)
9275 ex.X_op = O_constant;
9276 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9280 ep->X_add_number = ex.X_add_number;
9282 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9283 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9284 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9285 BFD_RELOC_MIPS_GOT_OFST);
9290 ex.X_add_number = ep->X_add_number;
9291 ep->X_add_number = 0;
9292 relax_start (ep->X_add_symbol);
9293 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9294 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9295 reg, reg, mips_gp_register);
9296 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9297 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9299 if (reg_needs_delay (mips_gp_register))
9301 /* We need a nop before loading from $gp. This special
9302 check is required because the lui which starts the main
9303 instruction stream does not refer to $gp, and so will not
9304 insert the nop which may be required. */
9305 macro_build (NULL, "nop", "");
9307 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9308 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9310 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9314 if (ex.X_add_number != 0)
9316 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9317 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9318 ex.X_op = O_constant;
9319 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9327 if (!mips_opts.at && *used_at == 1)
9328 as_bad (_("macro used $at after \".set noat\""));
9331 /* Move the contents of register SOURCE into register DEST. */
9334 move_register (int dest, int source)
9336 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9337 instruction specifically requires a 32-bit one. */
9338 if (mips_opts.micromips
9339 && !mips_opts.insn32
9340 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9341 macro_build (NULL, "move", "mp,mj", dest, source);
9343 macro_build (NULL, "or", "d,v,t", dest, source, 0);
9346 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9347 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9348 The two alternatives are:
9350 Global symbol Local sybmol
9351 ------------- ------------
9352 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9354 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9356 load_got_offset emits the first instruction and add_got_offset
9357 emits the second for a 16-bit offset or add_got_offset_hilo emits
9358 a sequence to add a 32-bit offset using a scratch register. */
9361 load_got_offset (int dest, expressionS *local)
9366 global.X_add_number = 0;
9368 relax_start (local->X_add_symbol);
9369 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9370 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9372 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
9373 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9378 add_got_offset (int dest, expressionS *local)
9382 global.X_op = O_constant;
9383 global.X_op_symbol = NULL;
9384 global.X_add_symbol = NULL;
9385 global.X_add_number = local->X_add_number;
9387 relax_start (local->X_add_symbol);
9388 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
9389 dest, dest, BFD_RELOC_LO16);
9391 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
9396 add_got_offset_hilo (int dest, expressionS *local, int tmp)
9399 int hold_mips_optimize;
9401 global.X_op = O_constant;
9402 global.X_op_symbol = NULL;
9403 global.X_add_symbol = NULL;
9404 global.X_add_number = local->X_add_number;
9406 relax_start (local->X_add_symbol);
9407 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
9409 /* Set mips_optimize around the lui instruction to avoid
9410 inserting an unnecessary nop after the lw. */
9411 hold_mips_optimize = mips_optimize;
9413 macro_build_lui (&global, tmp);
9414 mips_optimize = hold_mips_optimize;
9415 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
9418 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
9421 /* Emit a sequence of instructions to emulate a branch likely operation.
9422 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9423 is its complementing branch with the original condition negated.
9424 CALL is set if the original branch specified the link operation.
9425 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9427 Code like this is produced in the noreorder mode:
9432 delay slot (executed only if branch taken)
9440 delay slot (executed only if branch taken)
9443 In the reorder mode the delay slot would be filled with a nop anyway,
9444 so code produced is simply:
9449 This function is used when producing code for the microMIPS ASE that
9450 does not implement branch likely instructions in hardware. */
9453 macro_build_branch_likely (const char *br, const char *brneg,
9454 int call, expressionS *ep, const char *fmt,
9455 unsigned int sreg, unsigned int treg)
9457 int noreorder = mips_opts.noreorder;
9460 gas_assert (mips_opts.micromips);
9464 micromips_label_expr (&expr1);
9465 macro_build (&expr1, brneg, fmt, sreg, treg);
9466 macro_build (NULL, "nop", "");
9467 macro_build (ep, call ? "bal" : "b", "p");
9469 /* Set to true so that append_insn adds a label. */
9470 emit_branch_likely_macro = TRUE;
9474 macro_build (ep, br, fmt, sreg, treg);
9475 macro_build (NULL, "nop", "");
9480 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9481 the condition code tested. EP specifies the branch target. */
9484 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
9511 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
9514 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9515 the register tested. EP specifies the branch target. */
9518 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
9520 const char *brneg = NULL;
9530 br = mips_opts.micromips ? "bgez" : "bgezl";
9534 gas_assert (mips_opts.micromips);
9535 br = mips_opts.insn32 ? "bgezal" : "bgezals";
9543 br = mips_opts.micromips ? "bgtz" : "bgtzl";
9550 br = mips_opts.micromips ? "blez" : "blezl";
9557 br = mips_opts.micromips ? "bltz" : "bltzl";
9561 gas_assert (mips_opts.micromips);
9562 br = mips_opts.insn32 ? "bltzal" : "bltzals";
9569 if (mips_opts.micromips && brneg)
9570 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
9572 macro_build (ep, br, "s,p", sreg);
9575 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9576 TREG as the registers tested. EP specifies the branch target. */
9579 macro_build_branch_rsrt (int type, expressionS *ep,
9580 unsigned int sreg, unsigned int treg)
9582 const char *brneg = NULL;
9594 br = mips_opts.micromips ? "beq" : "beql";
9603 br = mips_opts.micromips ? "bne" : "bnel";
9609 if (mips_opts.micromips && brneg)
9610 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
9612 macro_build (ep, br, "s,t,p", sreg, treg);
9615 /* Return the high part that should be loaded in order to make the low
9616 part of VALUE accessible using an offset of OFFBITS bits. */
9619 offset_high_part (offsetT value, unsigned int offbits)
9626 bias = 1 << (offbits - 1);
9627 low_mask = bias * 2 - 1;
9628 return (value + bias) & ~low_mask;
9631 /* Return true if the value stored in offset_expr and offset_reloc
9632 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9633 amount that the caller wants to add without inducing overflow
9634 and ALIGN is the known alignment of the value in bytes. */
9637 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
9641 /* Accept any relocation operator if overflow isn't a concern. */
9642 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
9645 /* These relocations are guaranteed not to overflow in correct links. */
9646 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
9647 || gprel16_reloc_p (*offset_reloc))
9650 if (offset_expr.X_op == O_constant
9651 && offset_high_part (offset_expr.X_add_number, offbits) == 0
9652 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
9659 * This routine implements the seemingly endless macro or synthesized
9660 * instructions and addressing modes in the mips assembly language. Many
9661 * of these macros are simple and are similar to each other. These could
9662 * probably be handled by some kind of table or grammar approach instead of
9663 * this verbose method. Others are not simple macros but are more like
9664 * optimizing code generation.
9665 * One interesting optimization is when several store macros appear
9666 * consecutively that would load AT with the upper half of the same address.
9667 * The ensuing load upper instructions are ommited. This implies some kind
9668 * of global optimization. We currently only optimize within a single macro.
9669 * For many of the load and store macros if the address is specified as a
9670 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9671 * first load register 'at' with zero and use it as the base register. The
9672 * mips assembler simply uses register $zero. Just one tiny optimization
9676 macro (struct mips_cl_insn *ip, char *str)
9678 const struct mips_operand_array *operands;
9679 unsigned int breg, i;
9680 unsigned int tempreg;
9683 expressionS label_expr;
9698 bfd_boolean large_offset;
9700 int hold_mips_optimize;
9702 unsigned int op[MAX_OPERANDS];
9704 gas_assert (! mips_opts.mips16);
9706 operands = insn_operands (ip);
9707 for (i = 0; i < MAX_OPERANDS; i++)
9708 if (operands->operand[i])
9709 op[i] = insn_extract_operand (ip, operands->operand[i]);
9713 mask = ip->insn_mo->mask;
9715 label_expr.X_op = O_constant;
9716 label_expr.X_op_symbol = NULL;
9717 label_expr.X_add_symbol = NULL;
9718 label_expr.X_add_number = 0;
9720 expr1.X_op = O_constant;
9721 expr1.X_op_symbol = NULL;
9722 expr1.X_add_symbol = NULL;
9723 expr1.X_add_number = 1;
9739 if (mips_opts.micromips)
9740 micromips_label_expr (&label_expr);
9742 label_expr.X_add_number = 8;
9743 macro_build (&label_expr, "bgez", "s,p", op[1]);
9745 macro_build (NULL, "nop", "");
9747 move_register (op[0], op[1]);
9748 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
9749 if (mips_opts.micromips)
9750 micromips_add_label ();
9767 if (!mips_opts.micromips)
9769 if (imm_expr.X_add_number >= -0x200
9770 && imm_expr.X_add_number < 0x200)
9772 macro_build (NULL, s, "t,r,.", op[0], op[1],
9773 (int) imm_expr.X_add_number);
9782 if (imm_expr.X_add_number >= -0x8000
9783 && imm_expr.X_add_number < 0x8000)
9785 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9790 load_register (AT, &imm_expr, dbl);
9791 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9810 if (imm_expr.X_add_number >= 0
9811 && imm_expr.X_add_number < 0x10000)
9813 if (mask != M_NOR_I)
9814 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9817 macro_build (&imm_expr, "ori", "t,r,i",
9818 op[0], op[1], BFD_RELOC_LO16);
9819 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9825 load_register (AT, &imm_expr, GPR_SIZE == 64);
9826 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9830 switch (imm_expr.X_add_number)
9833 macro_build (NULL, "nop", "");
9836 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9840 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9841 (int) imm_expr.X_add_number);
9844 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9845 (unsigned long) imm_expr.X_add_number);
9854 gas_assert (mips_opts.micromips);
9855 macro_build_branch_ccl (mask, &offset_expr,
9856 EXTRACT_OPERAND (1, BCC, *ip));
9863 if (imm_expr.X_add_number == 0)
9869 load_register (op[1], &imm_expr, GPR_SIZE == 64);
9874 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9881 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9882 else if (op[0] == 0)
9883 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9887 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9888 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9889 &offset_expr, AT, ZERO);
9899 macro_build_branch_rs (mask, &offset_expr, op[0]);
9905 /* Check for > max integer. */
9906 if (imm_expr.X_add_number >= GPR_SMAX)
9909 /* Result is always false. */
9911 macro_build (NULL, "nop", "");
9913 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9916 ++imm_expr.X_add_number;
9920 if (mask == M_BGEL_I)
9922 if (imm_expr.X_add_number == 0)
9924 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9925 &offset_expr, op[0]);
9928 if (imm_expr.X_add_number == 1)
9930 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9931 &offset_expr, op[0]);
9934 if (imm_expr.X_add_number <= GPR_SMIN)
9937 /* result is always true */
9938 as_warn (_("branch %s is always true"), ip->insn_mo->name);
9939 macro_build (&offset_expr, "b", "p");
9944 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9945 &offset_expr, AT, ZERO);
9953 else if (op[0] == 0)
9954 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9955 &offset_expr, ZERO, op[1]);
9959 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9960 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9961 &offset_expr, AT, ZERO);
9970 && imm_expr.X_add_number == -1))
9972 ++imm_expr.X_add_number;
9976 if (mask == M_BGEUL_I)
9978 if (imm_expr.X_add_number == 0)
9980 else if (imm_expr.X_add_number == 1)
9981 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9982 &offset_expr, op[0], ZERO);
9987 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9988 &offset_expr, AT, ZERO);
9996 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9997 else if (op[0] == 0)
9998 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10002 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10003 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10004 &offset_expr, AT, ZERO);
10012 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10013 &offset_expr, op[0], ZERO);
10014 else if (op[0] == 0)
10019 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10020 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10021 &offset_expr, AT, ZERO);
10029 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10030 else if (op[0] == 0)
10031 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10035 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10036 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10037 &offset_expr, AT, ZERO);
10044 if (imm_expr.X_add_number >= GPR_SMAX)
10046 ++imm_expr.X_add_number;
10050 if (mask == M_BLTL_I)
10052 if (imm_expr.X_add_number == 0)
10053 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10054 else if (imm_expr.X_add_number == 1)
10055 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10060 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10061 &offset_expr, AT, ZERO);
10069 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10070 &offset_expr, op[0], ZERO);
10071 else if (op[0] == 0)
10076 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10077 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10078 &offset_expr, AT, ZERO);
10087 && imm_expr.X_add_number == -1))
10089 ++imm_expr.X_add_number;
10093 if (mask == M_BLTUL_I)
10095 if (imm_expr.X_add_number == 0)
10097 else if (imm_expr.X_add_number == 1)
10098 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10099 &offset_expr, op[0], ZERO);
10104 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10105 &offset_expr, AT, ZERO);
10113 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10114 else if (op[0] == 0)
10115 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10119 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10120 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10121 &offset_expr, AT, ZERO);
10130 else if (op[0] == 0)
10131 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10132 &offset_expr, ZERO, op[1]);
10136 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10137 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10138 &offset_expr, AT, ZERO);
10154 as_warn (_("divide by zero"));
10156 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10158 macro_build (NULL, "break", BRK_FMT, 7);
10162 start_noreorder ();
10165 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10166 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10170 if (mips_opts.micromips)
10171 micromips_label_expr (&label_expr);
10173 label_expr.X_add_number = 8;
10174 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10175 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10176 macro_build (NULL, "break", BRK_FMT, 7);
10177 if (mips_opts.micromips)
10178 micromips_add_label ();
10180 expr1.X_add_number = -1;
10182 load_register (AT, &expr1, dbl);
10183 if (mips_opts.micromips)
10184 micromips_label_expr (&label_expr);
10186 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10187 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10190 expr1.X_add_number = 1;
10191 load_register (AT, &expr1, dbl);
10192 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10196 expr1.X_add_number = 0x80000000;
10197 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10201 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10202 /* We want to close the noreorder block as soon as possible, so
10203 that later insns are available for delay slot filling. */
10208 if (mips_opts.micromips)
10209 micromips_label_expr (&label_expr);
10211 label_expr.X_add_number = 8;
10212 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10213 macro_build (NULL, "nop", "");
10215 /* We want to close the noreorder block as soon as possible, so
10216 that later insns are available for delay slot filling. */
10219 macro_build (NULL, "break", BRK_FMT, 6);
10221 if (mips_opts.micromips)
10222 micromips_add_label ();
10223 macro_build (NULL, s, MFHL_FMT, op[0]);
10262 if (imm_expr.X_add_number == 0)
10264 as_warn (_("divide by zero"));
10266 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10268 macro_build (NULL, "break", BRK_FMT, 7);
10271 if (imm_expr.X_add_number == 1)
10273 if (strcmp (s2, "mflo") == 0)
10274 move_register (op[0], op[1]);
10276 move_register (op[0], ZERO);
10279 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
10281 if (strcmp (s2, "mflo") == 0)
10282 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
10284 move_register (op[0], ZERO);
10289 load_register (AT, &imm_expr, dbl);
10290 macro_build (NULL, s, "z,s,t", op[1], AT);
10291 macro_build (NULL, s2, MFHL_FMT, op[0]);
10310 start_noreorder ();
10313 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10314 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10315 /* We want to close the noreorder block as soon as possible, so
10316 that later insns are available for delay slot filling. */
10321 if (mips_opts.micromips)
10322 micromips_label_expr (&label_expr);
10324 label_expr.X_add_number = 8;
10325 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10326 macro_build (NULL, s, "z,s,t", op[1], op[2]);
10328 /* We want to close the noreorder block as soon as possible, so
10329 that later insns are available for delay slot filling. */
10331 macro_build (NULL, "break", BRK_FMT, 7);
10332 if (mips_opts.micromips)
10333 micromips_add_label ();
10335 macro_build (NULL, s2, MFHL_FMT, op[0]);
10347 /* Load the address of a symbol into a register. If breg is not
10348 zero, we then add a base register to it. */
10351 if (dbl && GPR_SIZE == 32)
10352 as_warn (_("dla used to load 32-bit register; recommend using la "
10355 if (!dbl && HAVE_64BIT_OBJECTS)
10356 as_warn (_("la used to load 64-bit address; recommend using dla "
10359 if (small_offset_p (0, align, 16))
10361 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
10362 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10366 if (mips_opts.at && (op[0] == breg))
10374 if (offset_expr.X_op != O_symbol
10375 && offset_expr.X_op != O_constant)
10377 as_bad (_("expression too complex"));
10378 offset_expr.X_op = O_constant;
10381 if (offset_expr.X_op == O_constant)
10382 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
10383 else if (mips_pic == NO_PIC)
10385 /* If this is a reference to a GP relative symbol, we want
10386 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10388 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10389 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10390 If we have a constant, we need two instructions anyhow,
10391 so we may as well always use the latter form.
10393 With 64bit address space and a usable $at we want
10394 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10395 lui $at,<sym> (BFD_RELOC_HI16_S)
10396 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10397 daddiu $at,<sym> (BFD_RELOC_LO16)
10399 daddu $tempreg,$tempreg,$at
10401 If $at is already in use, we use a path which is suboptimal
10402 on superscalar processors.
10403 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10404 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10406 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10408 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10410 For GP relative symbols in 64bit address space we can use
10411 the same sequence as in 32bit address space. */
10412 if (HAVE_64BIT_SYMBOLS)
10414 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10415 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10417 relax_start (offset_expr.X_add_symbol);
10418 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10419 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10423 if (used_at == 0 && mips_opts.at)
10425 macro_build (&offset_expr, "lui", LUI_FMT,
10426 tempreg, BFD_RELOC_MIPS_HIGHEST);
10427 macro_build (&offset_expr, "lui", LUI_FMT,
10428 AT, BFD_RELOC_HI16_S);
10429 macro_build (&offset_expr, "daddiu", "t,r,j",
10430 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10431 macro_build (&offset_expr, "daddiu", "t,r,j",
10432 AT, AT, BFD_RELOC_LO16);
10433 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
10434 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
10439 macro_build (&offset_expr, "lui", LUI_FMT,
10440 tempreg, BFD_RELOC_MIPS_HIGHEST);
10441 macro_build (&offset_expr, "daddiu", "t,r,j",
10442 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
10443 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10444 macro_build (&offset_expr, "daddiu", "t,r,j",
10445 tempreg, tempreg, BFD_RELOC_HI16_S);
10446 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
10447 macro_build (&offset_expr, "daddiu", "t,r,j",
10448 tempreg, tempreg, BFD_RELOC_LO16);
10451 if (mips_relax.sequence)
10456 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
10457 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
10459 relax_start (offset_expr.X_add_symbol);
10460 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10461 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
10464 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10465 as_bad (_("offset too large"));
10466 macro_build_lui (&offset_expr, tempreg);
10467 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10468 tempreg, tempreg, BFD_RELOC_LO16);
10469 if (mips_relax.sequence)
10473 else if (!mips_big_got && !HAVE_NEWABI)
10475 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10477 /* If this is a reference to an external symbol, and there
10478 is no constant, we want
10479 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10480 or for lca or if tempreg is PIC_CALL_REG
10481 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10482 For a local symbol, we want
10483 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10485 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10487 If we have a small constant, and this is a reference to
10488 an external symbol, we want
10489 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10491 addiu $tempreg,$tempreg,<constant>
10492 For a local symbol, we want the same instruction
10493 sequence, but we output a BFD_RELOC_LO16 reloc on the
10496 If we have a large constant, and this is a reference to
10497 an external symbol, we want
10498 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10499 lui $at,<hiconstant>
10500 addiu $at,$at,<loconstant>
10501 addu $tempreg,$tempreg,$at
10502 For a local symbol, we want the same instruction
10503 sequence, but we output a BFD_RELOC_LO16 reloc on the
10507 if (offset_expr.X_add_number == 0)
10509 if (mips_pic == SVR4_PIC
10511 && (call || tempreg == PIC_CALL_REG))
10512 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
10514 relax_start (offset_expr.X_add_symbol);
10515 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10516 lw_reloc_type, mips_gp_register);
10519 /* We're going to put in an addu instruction using
10520 tempreg, so we may as well insert the nop right
10525 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10526 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
10528 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10529 tempreg, tempreg, BFD_RELOC_LO16);
10531 /* FIXME: If breg == 0, and the next instruction uses
10532 $tempreg, then if this variant case is used an extra
10533 nop will be generated. */
10535 else if (offset_expr.X_add_number >= -0x8000
10536 && offset_expr.X_add_number < 0x8000)
10538 load_got_offset (tempreg, &offset_expr);
10540 add_got_offset (tempreg, &offset_expr);
10544 expr1.X_add_number = offset_expr.X_add_number;
10545 offset_expr.X_add_number =
10546 SEXT_16BIT (offset_expr.X_add_number);
10547 load_got_offset (tempreg, &offset_expr);
10548 offset_expr.X_add_number = expr1.X_add_number;
10549 /* If we are going to add in a base register, and the
10550 target register and the base register are the same,
10551 then we are using AT as a temporary register. Since
10552 we want to load the constant into AT, we add our
10553 current AT (from the global offset table) and the
10554 register into the register now, and pretend we were
10555 not using a base register. */
10559 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10564 add_got_offset_hilo (tempreg, &offset_expr, AT);
10568 else if (!mips_big_got && HAVE_NEWABI)
10570 int add_breg_early = 0;
10572 /* If this is a reference to an external, and there is no
10573 constant, or local symbol (*), with or without a
10575 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10576 or for lca or if tempreg is PIC_CALL_REG
10577 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10579 If we have a small constant, and this is a reference to
10580 an external symbol, we want
10581 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10582 addiu $tempreg,$tempreg,<constant>
10584 If we have a large constant, and this is a reference to
10585 an external symbol, we want
10586 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10587 lui $at,<hiconstant>
10588 addiu $at,$at,<loconstant>
10589 addu $tempreg,$tempreg,$at
10591 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10592 local symbols, even though it introduces an additional
10595 if (offset_expr.X_add_number)
10597 expr1.X_add_number = offset_expr.X_add_number;
10598 offset_expr.X_add_number = 0;
10600 relax_start (offset_expr.X_add_symbol);
10601 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10602 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10604 if (expr1.X_add_number >= -0x8000
10605 && expr1.X_add_number < 0x8000)
10607 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10608 tempreg, tempreg, BFD_RELOC_LO16);
10610 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10614 /* If we are going to add in a base register, and the
10615 target register and the base register are the same,
10616 then we are using AT as a temporary register. Since
10617 we want to load the constant into AT, we add our
10618 current AT (from the global offset table) and the
10619 register into the register now, and pretend we were
10620 not using a base register. */
10625 gas_assert (tempreg == AT);
10626 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10629 add_breg_early = 1;
10632 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10633 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10639 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10642 offset_expr.X_add_number = expr1.X_add_number;
10644 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10645 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10646 if (add_breg_early)
10648 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10649 op[0], tempreg, breg);
10655 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10657 relax_start (offset_expr.X_add_symbol);
10658 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10659 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10661 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10662 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10667 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10668 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10671 else if (mips_big_got && !HAVE_NEWABI)
10674 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10675 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10676 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10678 /* This is the large GOT case. If this is a reference to an
10679 external symbol, and there is no constant, we want
10680 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10681 addu $tempreg,$tempreg,$gp
10682 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10683 or for lca or if tempreg is PIC_CALL_REG
10684 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10685 addu $tempreg,$tempreg,$gp
10686 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10687 For a local symbol, we want
10688 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10690 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10692 If we have a small constant, and this is a reference to
10693 an external symbol, we want
10694 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10695 addu $tempreg,$tempreg,$gp
10696 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10698 addiu $tempreg,$tempreg,<constant>
10699 For a local symbol, we want
10700 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10702 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10704 If we have a large constant, and this is a reference to
10705 an external symbol, we want
10706 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10707 addu $tempreg,$tempreg,$gp
10708 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10709 lui $at,<hiconstant>
10710 addiu $at,$at,<loconstant>
10711 addu $tempreg,$tempreg,$at
10712 For a local symbol, we want
10713 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10714 lui $at,<hiconstant>
10715 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10716 addu $tempreg,$tempreg,$at
10719 expr1.X_add_number = offset_expr.X_add_number;
10720 offset_expr.X_add_number = 0;
10721 relax_start (offset_expr.X_add_symbol);
10722 gpdelay = reg_needs_delay (mips_gp_register);
10723 if (expr1.X_add_number == 0 && breg == 0
10724 && (call || tempreg == PIC_CALL_REG))
10726 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10727 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10729 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10730 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10731 tempreg, tempreg, mips_gp_register);
10732 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10733 tempreg, lw_reloc_type, tempreg);
10734 if (expr1.X_add_number == 0)
10738 /* We're going to put in an addu instruction using
10739 tempreg, so we may as well insert the nop right
10744 else if (expr1.X_add_number >= -0x8000
10745 && expr1.X_add_number < 0x8000)
10748 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10749 tempreg, tempreg, BFD_RELOC_LO16);
10755 /* If we are going to add in a base register, and the
10756 target register and the base register are the same,
10757 then we are using AT as a temporary register. Since
10758 we want to load the constant into AT, we add our
10759 current AT (from the global offset table) and the
10760 register into the register now, and pretend we were
10761 not using a base register. */
10766 gas_assert (tempreg == AT);
10768 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10773 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10774 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10778 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10783 /* This is needed because this instruction uses $gp, but
10784 the first instruction on the main stream does not. */
10785 macro_build (NULL, "nop", "");
10788 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10789 local_reloc_type, mips_gp_register);
10790 if (expr1.X_add_number >= -0x8000
10791 && expr1.X_add_number < 0x8000)
10794 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10795 tempreg, tempreg, BFD_RELOC_LO16);
10796 /* FIXME: If add_number is 0, and there was no base
10797 register, the external symbol case ended with a load,
10798 so if the symbol turns out to not be external, and
10799 the next instruction uses tempreg, an unnecessary nop
10800 will be inserted. */
10806 /* We must add in the base register now, as in the
10807 external symbol case. */
10808 gas_assert (tempreg == AT);
10810 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10813 /* We set breg to 0 because we have arranged to add
10814 it in in both cases. */
10818 macro_build_lui (&expr1, AT);
10819 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10820 AT, AT, BFD_RELOC_LO16);
10821 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10822 tempreg, tempreg, AT);
10827 else if (mips_big_got && HAVE_NEWABI)
10829 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10830 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10831 int add_breg_early = 0;
10833 /* This is the large GOT case. If this is a reference to an
10834 external symbol, and there is no constant, we want
10835 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10836 add $tempreg,$tempreg,$gp
10837 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10838 or for lca or if tempreg is PIC_CALL_REG
10839 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10840 add $tempreg,$tempreg,$gp
10841 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10843 If we have a small constant, and this is a reference to
10844 an external symbol, we want
10845 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10846 add $tempreg,$tempreg,$gp
10847 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10848 addi $tempreg,$tempreg,<constant>
10850 If we have a large constant, and this is a reference to
10851 an external symbol, we want
10852 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10853 addu $tempreg,$tempreg,$gp
10854 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10855 lui $at,<hiconstant>
10856 addi $at,$at,<loconstant>
10857 add $tempreg,$tempreg,$at
10859 If we have NewABI, and we know it's a local symbol, we want
10860 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10861 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10862 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10864 relax_start (offset_expr.X_add_symbol);
10866 expr1.X_add_number = offset_expr.X_add_number;
10867 offset_expr.X_add_number = 0;
10869 if (expr1.X_add_number == 0 && breg == 0
10870 && (call || tempreg == PIC_CALL_REG))
10872 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10873 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10875 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10876 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10877 tempreg, tempreg, mips_gp_register);
10878 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10879 tempreg, lw_reloc_type, tempreg);
10881 if (expr1.X_add_number == 0)
10883 else if (expr1.X_add_number >= -0x8000
10884 && expr1.X_add_number < 0x8000)
10886 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10887 tempreg, tempreg, BFD_RELOC_LO16);
10889 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10893 /* If we are going to add in a base register, and the
10894 target register and the base register are the same,
10895 then we are using AT as a temporary register. Since
10896 we want to load the constant into AT, we add our
10897 current AT (from the global offset table) and the
10898 register into the register now, and pretend we were
10899 not using a base register. */
10904 gas_assert (tempreg == AT);
10905 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10908 add_breg_early = 1;
10911 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10912 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10917 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10920 offset_expr.X_add_number = expr1.X_add_number;
10921 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10922 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10923 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10924 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10925 if (add_breg_early)
10927 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10928 op[0], tempreg, breg);
10938 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10942 gas_assert (!mips_opts.micromips);
10943 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10947 gas_assert (!mips_opts.micromips);
10948 macro_build (NULL, "c2", "C", 0x02);
10952 gas_assert (!mips_opts.micromips);
10953 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10957 gas_assert (!mips_opts.micromips);
10958 macro_build (NULL, "c2", "C", 3);
10962 gas_assert (!mips_opts.micromips);
10963 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
10967 /* The j instruction may not be used in PIC code, since it
10968 requires an absolute address. We convert it to a b
10970 if (mips_pic == NO_PIC)
10971 macro_build (&offset_expr, "j", "a");
10973 macro_build (&offset_expr, "b", "p");
10976 /* The jal instructions must be handled as macros because when
10977 generating PIC code they expand to multi-instruction
10978 sequences. Normally they are simple instructions. */
10982 /* Fall through. */
10984 gas_assert (mips_opts.micromips);
10985 if (mips_opts.insn32)
10987 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
10995 /* Fall through. */
10998 if (mips_pic == NO_PIC)
11000 s = jals ? "jalrs" : "jalr";
11001 if (mips_opts.micromips
11002 && !mips_opts.insn32
11004 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11005 macro_build (NULL, s, "mj", op[1]);
11007 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11011 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11012 && mips_cprestore_offset >= 0);
11014 if (op[1] != PIC_CALL_REG)
11015 as_warn (_("MIPS PIC call to register other than $25"));
11017 s = ((mips_opts.micromips
11018 && !mips_opts.insn32
11019 && (!mips_opts.noreorder || cprestore))
11020 ? "jalrs" : "jalr");
11021 if (mips_opts.micromips
11022 && !mips_opts.insn32
11024 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11025 macro_build (NULL, s, "mj", op[1]);
11027 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11028 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11030 if (mips_cprestore_offset < 0)
11031 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11034 if (!mips_frame_reg_valid)
11036 as_warn (_("no .frame pseudo-op used in PIC code"));
11037 /* Quiet this warning. */
11038 mips_frame_reg_valid = 1;
11040 if (!mips_cprestore_valid)
11042 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11043 /* Quiet this warning. */
11044 mips_cprestore_valid = 1;
11046 if (mips_opts.noreorder)
11047 macro_build (NULL, "nop", "");
11048 expr1.X_add_number = mips_cprestore_offset;
11049 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11052 HAVE_64BIT_ADDRESSES);
11060 gas_assert (mips_opts.micromips);
11061 if (mips_opts.insn32)
11063 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11067 /* Fall through. */
11069 if (mips_pic == NO_PIC)
11070 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11071 else if (mips_pic == SVR4_PIC)
11073 /* If this is a reference to an external symbol, and we are
11074 using a small GOT, we want
11075 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11079 lw $gp,cprestore($sp)
11080 The cprestore value is set using the .cprestore
11081 pseudo-op. If we are using a big GOT, we want
11082 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11084 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11088 lw $gp,cprestore($sp)
11089 If the symbol is not external, we want
11090 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11092 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11095 lw $gp,cprestore($sp)
11097 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11098 sequences above, minus nops, unless the symbol is local,
11099 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11105 relax_start (offset_expr.X_add_symbol);
11106 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11107 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11110 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11111 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11117 relax_start (offset_expr.X_add_symbol);
11118 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11119 BFD_RELOC_MIPS_CALL_HI16);
11120 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11121 PIC_CALL_REG, mips_gp_register);
11122 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11123 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11126 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11127 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11129 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11130 PIC_CALL_REG, PIC_CALL_REG,
11131 BFD_RELOC_MIPS_GOT_OFST);
11135 macro_build_jalr (&offset_expr, 0);
11139 relax_start (offset_expr.X_add_symbol);
11142 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11143 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11152 gpdelay = reg_needs_delay (mips_gp_register);
11153 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11154 BFD_RELOC_MIPS_CALL_HI16);
11155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11156 PIC_CALL_REG, mips_gp_register);
11157 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11158 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11163 macro_build (NULL, "nop", "");
11165 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11166 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11169 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11170 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11172 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11174 if (mips_cprestore_offset < 0)
11175 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11178 if (!mips_frame_reg_valid)
11180 as_warn (_("no .frame pseudo-op used in PIC code"));
11181 /* Quiet this warning. */
11182 mips_frame_reg_valid = 1;
11184 if (!mips_cprestore_valid)
11186 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11187 /* Quiet this warning. */
11188 mips_cprestore_valid = 1;
11190 if (mips_opts.noreorder)
11191 macro_build (NULL, "nop", "");
11192 expr1.X_add_number = mips_cprestore_offset;
11193 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11196 HAVE_64BIT_ADDRESSES);
11200 else if (mips_pic == VXWORKS_PIC)
11201 as_bad (_("non-PIC jump used in PIC library"));
11308 gas_assert (!mips_opts.micromips);
11311 /* Itbl support may require additional care here. */
11317 /* Itbl support may require additional care here. */
11323 offbits = (mips_opts.micromips ? 12
11324 : ISA_IS_R6 (mips_opts.isa) ? 11
11326 /* Itbl support may require additional care here. */
11330 gas_assert (!mips_opts.micromips);
11333 /* Itbl support may require additional care here. */
11339 offbits = (mips_opts.micromips ? 12 : 16);
11344 offbits = (mips_opts.micromips ? 12 : 16);
11349 /* Itbl support may require additional care here. */
11355 offbits = (mips_opts.micromips ? 12
11356 : ISA_IS_R6 (mips_opts.isa) ? 11
11358 /* Itbl support may require additional care here. */
11364 /* Itbl support may require additional care here. */
11370 /* Itbl support may require additional care here. */
11376 offbits = (mips_opts.micromips ? 12 : 16);
11381 offbits = (mips_opts.micromips ? 12 : 16);
11386 offbits = (mips_opts.micromips ? 12
11387 : ISA_IS_R6 (mips_opts.isa) ? 9
11393 offbits = (mips_opts.micromips ? 12
11394 : ISA_IS_R6 (mips_opts.isa) ? 9
11400 offbits = (mips_opts.micromips ? 12 : 16);
11403 gas_assert (mips_opts.micromips);
11410 gas_assert (mips_opts.micromips);
11417 gas_assert (mips_opts.micromips);
11423 gas_assert (mips_opts.micromips);
11430 /* We don't want to use $0 as tempreg. */
11431 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
11434 tempreg = op[0] + lp;
11450 gas_assert (!mips_opts.micromips);
11453 /* Itbl support may require additional care here. */
11459 /* Itbl support may require additional care here. */
11465 offbits = (mips_opts.micromips ? 12
11466 : ISA_IS_R6 (mips_opts.isa) ? 11
11468 /* Itbl support may require additional care here. */
11472 gas_assert (!mips_opts.micromips);
11475 /* Itbl support may require additional care here. */
11481 offbits = (mips_opts.micromips ? 12 : 16);
11486 offbits = (mips_opts.micromips ? 12 : 16);
11491 offbits = (mips_opts.micromips ? 12
11492 : ISA_IS_R6 (mips_opts.isa) ? 9
11498 offbits = (mips_opts.micromips ? 12
11499 : ISA_IS_R6 (mips_opts.isa) ? 9
11504 fmt = (mips_opts.micromips ? "k,~(b)"
11505 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11507 offbits = (mips_opts.micromips ? 12
11508 : ISA_IS_R6 (mips_opts.isa) ? 9
11518 fmt = (mips_opts.micromips ? "k,~(b)"
11519 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11521 offbits = (mips_opts.micromips ? 12
11522 : ISA_IS_R6 (mips_opts.isa) ? 9
11534 /* Itbl support may require additional care here. */
11539 offbits = (mips_opts.micromips ? 12
11540 : ISA_IS_R6 (mips_opts.isa) ? 11
11542 /* Itbl support may require additional care here. */
11548 /* Itbl support may require additional care here. */
11552 gas_assert (!mips_opts.micromips);
11555 /* Itbl support may require additional care here. */
11561 offbits = (mips_opts.micromips ? 12 : 16);
11566 offbits = (mips_opts.micromips ? 12 : 16);
11569 gas_assert (mips_opts.micromips);
11575 gas_assert (mips_opts.micromips);
11581 gas_assert (mips_opts.micromips);
11587 gas_assert (mips_opts.micromips);
11596 if (small_offset_p (0, align, 16))
11598 /* The first case exists for M_LD_AB and M_SD_AB, which are
11599 macros for o32 but which should act like normal instructions
11602 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
11603 offset_reloc[1], offset_reloc[2], breg);
11604 else if (small_offset_p (0, align, offbits))
11607 macro_build (NULL, s, fmt, op[0], breg);
11609 macro_build (NULL, s, fmt, op[0],
11610 (int) offset_expr.X_add_number, breg);
11616 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11617 tempreg, breg, -1, offset_reloc[0],
11618 offset_reloc[1], offset_reloc[2]);
11620 macro_build (NULL, s, fmt, op[0], tempreg);
11622 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11630 if (offset_expr.X_op != O_constant
11631 && offset_expr.X_op != O_symbol)
11633 as_bad (_("expression too complex"));
11634 offset_expr.X_op = O_constant;
11637 if (HAVE_32BIT_ADDRESSES
11638 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11642 sprintf_vma (value, offset_expr.X_add_number);
11643 as_bad (_("number (0x%s) larger than 32 bits"), value);
11646 /* A constant expression in PIC code can be handled just as it
11647 is in non PIC code. */
11648 if (offset_expr.X_op == O_constant)
11650 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
11651 offbits == 0 ? 16 : offbits);
11652 offset_expr.X_add_number -= expr1.X_add_number;
11654 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
11656 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11657 tempreg, tempreg, breg);
11660 if (offset_expr.X_add_number != 0)
11661 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
11662 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
11663 macro_build (NULL, s, fmt, op[0], tempreg);
11665 else if (offbits == 16)
11666 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11668 macro_build (NULL, s, fmt, op[0],
11669 (int) offset_expr.X_add_number, tempreg);
11671 else if (offbits != 16)
11673 /* The offset field is too narrow to be used for a low-part
11674 relocation, so load the whole address into the auxillary
11676 load_address (tempreg, &offset_expr, &used_at);
11678 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11679 tempreg, tempreg, breg);
11681 macro_build (NULL, s, fmt, op[0], tempreg);
11683 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11685 else if (mips_pic == NO_PIC)
11687 /* If this is a reference to a GP relative symbol, and there
11688 is no base register, we want
11689 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11690 Otherwise, if there is no base register, we want
11691 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11692 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11693 If we have a constant, we need two instructions anyhow,
11694 so we always use the latter form.
11696 If we have a base register, and this is a reference to a
11697 GP relative symbol, we want
11698 addu $tempreg,$breg,$gp
11699 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11701 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11702 addu $tempreg,$tempreg,$breg
11703 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11704 With a constant we always use the latter case.
11706 With 64bit address space and no base register and $at usable,
11708 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11709 lui $at,<sym> (BFD_RELOC_HI16_S)
11710 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11713 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11714 If we have a base register, we want
11715 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11716 lui $at,<sym> (BFD_RELOC_HI16_S)
11717 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11721 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11723 Without $at we can't generate the optimal path for superscalar
11724 processors here since this would require two temporary registers.
11725 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11726 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11728 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11730 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11731 If we have a base register, we want
11732 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11733 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11735 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11737 daddu $tempreg,$tempreg,$breg
11738 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11740 For GP relative symbols in 64bit address space we can use
11741 the same sequence as in 32bit address space. */
11742 if (HAVE_64BIT_SYMBOLS)
11744 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11745 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11747 relax_start (offset_expr.X_add_symbol);
11750 macro_build (&offset_expr, s, fmt, op[0],
11751 BFD_RELOC_GPREL16, mips_gp_register);
11755 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11756 tempreg, breg, mips_gp_register);
11757 macro_build (&offset_expr, s, fmt, op[0],
11758 BFD_RELOC_GPREL16, tempreg);
11763 if (used_at == 0 && mips_opts.at)
11765 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11766 BFD_RELOC_MIPS_HIGHEST);
11767 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11769 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11770 tempreg, BFD_RELOC_MIPS_HIGHER);
11772 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11773 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11774 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11775 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11781 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11782 BFD_RELOC_MIPS_HIGHEST);
11783 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11784 tempreg, BFD_RELOC_MIPS_HIGHER);
11785 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11786 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11787 tempreg, BFD_RELOC_HI16_S);
11788 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11790 macro_build (NULL, "daddu", "d,v,t",
11791 tempreg, tempreg, breg);
11792 macro_build (&offset_expr, s, fmt, op[0],
11793 BFD_RELOC_LO16, tempreg);
11796 if (mips_relax.sequence)
11803 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11804 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11806 relax_start (offset_expr.X_add_symbol);
11807 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11811 macro_build_lui (&offset_expr, tempreg);
11812 macro_build (&offset_expr, s, fmt, op[0],
11813 BFD_RELOC_LO16, tempreg);
11814 if (mips_relax.sequence)
11819 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11820 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11822 relax_start (offset_expr.X_add_symbol);
11823 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11824 tempreg, breg, mips_gp_register);
11825 macro_build (&offset_expr, s, fmt, op[0],
11826 BFD_RELOC_GPREL16, tempreg);
11829 macro_build_lui (&offset_expr, tempreg);
11830 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11831 tempreg, tempreg, breg);
11832 macro_build (&offset_expr, s, fmt, op[0],
11833 BFD_RELOC_LO16, tempreg);
11834 if (mips_relax.sequence)
11838 else if (!mips_big_got)
11840 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11842 /* If this is a reference to an external symbol, we want
11843 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11845 <op> op[0],0($tempreg)
11847 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11849 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11850 <op> op[0],0($tempreg)
11852 For NewABI, we want
11853 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11854 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11856 If there is a base register, we add it to $tempreg before
11857 the <op>. If there is a constant, we stick it in the
11858 <op> instruction. We don't handle constants larger than
11859 16 bits, because we have no way to load the upper 16 bits
11860 (actually, we could handle them for the subset of cases
11861 in which we are not using $at). */
11862 gas_assert (offset_expr.X_op == O_symbol);
11865 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11866 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11868 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11869 tempreg, tempreg, breg);
11870 macro_build (&offset_expr, s, fmt, op[0],
11871 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11874 expr1.X_add_number = offset_expr.X_add_number;
11875 offset_expr.X_add_number = 0;
11876 if (expr1.X_add_number < -0x8000
11877 || expr1.X_add_number >= 0x8000)
11878 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11879 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11880 lw_reloc_type, mips_gp_register);
11882 relax_start (offset_expr.X_add_symbol);
11884 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11885 tempreg, BFD_RELOC_LO16);
11888 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11889 tempreg, tempreg, breg);
11890 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11892 else if (mips_big_got && !HAVE_NEWABI)
11896 /* If this is a reference to an external symbol, we want
11897 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11898 addu $tempreg,$tempreg,$gp
11899 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11900 <op> op[0],0($tempreg)
11902 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11904 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11905 <op> op[0],0($tempreg)
11906 If there is a base register, we add it to $tempreg before
11907 the <op>. If there is a constant, we stick it in the
11908 <op> instruction. We don't handle constants larger than
11909 16 bits, because we have no way to load the upper 16 bits
11910 (actually, we could handle them for the subset of cases
11911 in which we are not using $at). */
11912 gas_assert (offset_expr.X_op == O_symbol);
11913 expr1.X_add_number = offset_expr.X_add_number;
11914 offset_expr.X_add_number = 0;
11915 if (expr1.X_add_number < -0x8000
11916 || expr1.X_add_number >= 0x8000)
11917 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11918 gpdelay = reg_needs_delay (mips_gp_register);
11919 relax_start (offset_expr.X_add_symbol);
11920 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11921 BFD_RELOC_MIPS_GOT_HI16);
11922 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11924 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11925 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11928 macro_build (NULL, "nop", "");
11929 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11930 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11932 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11933 tempreg, BFD_RELOC_LO16);
11937 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11938 tempreg, tempreg, breg);
11939 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11941 else if (mips_big_got && HAVE_NEWABI)
11943 /* If this is a reference to an external symbol, we want
11944 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11945 add $tempreg,$tempreg,$gp
11946 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11947 <op> op[0],<ofst>($tempreg)
11948 Otherwise, for local symbols, we want:
11949 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11950 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11951 gas_assert (offset_expr.X_op == O_symbol);
11952 expr1.X_add_number = offset_expr.X_add_number;
11953 offset_expr.X_add_number = 0;
11954 if (expr1.X_add_number < -0x8000
11955 || expr1.X_add_number >= 0x8000)
11956 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11957 relax_start (offset_expr.X_add_symbol);
11958 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11959 BFD_RELOC_MIPS_GOT_HI16);
11960 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11962 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11963 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11965 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11966 tempreg, tempreg, breg);
11967 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11970 offset_expr.X_add_number = expr1.X_add_number;
11971 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11972 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11975 tempreg, tempreg, breg);
11976 macro_build (&offset_expr, s, fmt, op[0],
11977 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11986 gas_assert (mips_opts.micromips);
11987 gas_assert (mips_opts.insn32);
11988 start_noreorder ();
11989 macro_build (NULL, "jr", "s", RA);
11990 expr1.X_add_number = op[0] << 2;
11991 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11996 gas_assert (mips_opts.micromips);
11997 gas_assert (mips_opts.insn32);
11998 macro_build (NULL, "jr", "s", op[0]);
11999 if (mips_opts.noreorder)
12000 macro_build (NULL, "nop", "");
12005 load_register (op[0], &imm_expr, 0);
12009 load_register (op[0], &imm_expr, 1);
12013 if (imm_expr.X_op == O_constant)
12016 load_register (AT, &imm_expr, 0);
12017 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12022 gas_assert (imm_expr.X_op == O_absent
12023 && offset_expr.X_op == O_symbol
12024 && strcmp (segment_name (S_GET_SEGMENT
12025 (offset_expr.X_add_symbol)),
12027 && offset_expr.X_add_number == 0);
12028 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12029 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12034 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12035 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12036 order 32 bits of the value and the low order 32 bits are either
12037 zero or in OFFSET_EXPR. */
12038 if (imm_expr.X_op == O_constant)
12040 if (GPR_SIZE == 64)
12041 load_register (op[0], &imm_expr, 1);
12046 if (target_big_endian)
12058 load_register (hreg, &imm_expr, 0);
12061 if (offset_expr.X_op == O_absent)
12062 move_register (lreg, 0);
12065 gas_assert (offset_expr.X_op == O_constant);
12066 load_register (lreg, &offset_expr, 0);
12072 gas_assert (imm_expr.X_op == O_absent);
12074 /* We know that sym is in the .rdata section. First we get the
12075 upper 16 bits of the address. */
12076 if (mips_pic == NO_PIC)
12078 macro_build_lui (&offset_expr, AT);
12083 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12084 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12088 /* Now we load the register(s). */
12089 if (GPR_SIZE == 64)
12092 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12093 BFD_RELOC_LO16, AT);
12098 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12099 BFD_RELOC_LO16, AT);
12102 /* FIXME: How in the world do we deal with the possible
12104 offset_expr.X_add_number += 4;
12105 macro_build (&offset_expr, "lw", "t,o(b)",
12106 op[0] + 1, BFD_RELOC_LO16, AT);
12112 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12113 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12114 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12115 the value and the low order 32 bits are either zero or in
12117 if (imm_expr.X_op == O_constant)
12120 load_register (AT, &imm_expr, FPR_SIZE == 64);
12121 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12122 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
12125 if (ISA_HAS_MXHC1 (mips_opts.isa))
12126 macro_build (NULL, "mthc1", "t,G", AT, op[0]);
12127 else if (FPR_SIZE != 32)
12128 as_bad (_("Unable to generate `%s' compliant code "
12130 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12132 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
12133 if (offset_expr.X_op == O_absent)
12134 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12137 gas_assert (offset_expr.X_op == O_constant);
12138 load_register (AT, &offset_expr, 0);
12139 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12145 gas_assert (imm_expr.X_op == O_absent
12146 && offset_expr.X_op == O_symbol
12147 && offset_expr.X_add_number == 0);
12148 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12149 if (strcmp (s, ".lit8") == 0)
12151 op[2] = mips_gp_register;
12152 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12153 offset_reloc[1] = BFD_RELOC_UNUSED;
12154 offset_reloc[2] = BFD_RELOC_UNUSED;
12158 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12160 if (mips_pic != NO_PIC)
12161 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12162 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12165 /* FIXME: This won't work for a 64 bit address. */
12166 macro_build_lui (&offset_expr, AT);
12170 offset_reloc[0] = BFD_RELOC_LO16;
12171 offset_reloc[1] = BFD_RELOC_UNUSED;
12172 offset_reloc[2] = BFD_RELOC_UNUSED;
12179 * The MIPS assembler seems to check for X_add_number not
12180 * being double aligned and generating:
12181 * lui at,%hi(foo+1)
12183 * addiu at,at,%lo(foo+1)
12186 * But, the resulting address is the same after relocation so why
12187 * generate the extra instruction?
12189 /* Itbl support may require additional care here. */
12192 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12201 gas_assert (!mips_opts.micromips);
12202 /* Itbl support may require additional care here. */
12205 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12225 if (GPR_SIZE == 64)
12235 if (GPR_SIZE == 64)
12243 /* Even on a big endian machine $fn comes before $fn+1. We have
12244 to adjust when loading from memory. We set coproc if we must
12245 load $fn+1 first. */
12246 /* Itbl support may require additional care here. */
12247 if (!target_big_endian)
12251 if (small_offset_p (0, align, 16))
12254 if (!small_offset_p (4, align, 16))
12256 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
12257 -1, offset_reloc[0], offset_reloc[1],
12259 expr1.X_add_number = 0;
12263 offset_reloc[0] = BFD_RELOC_LO16;
12264 offset_reloc[1] = BFD_RELOC_UNUSED;
12265 offset_reloc[2] = BFD_RELOC_UNUSED;
12267 if (strcmp (s, "lw") == 0 && op[0] == breg)
12269 ep->X_add_number += 4;
12270 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
12271 offset_reloc[1], offset_reloc[2], breg);
12272 ep->X_add_number -= 4;
12273 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
12274 offset_reloc[1], offset_reloc[2], breg);
12278 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
12279 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12281 ep->X_add_number += 4;
12282 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
12283 offset_reloc[0], offset_reloc[1], offset_reloc[2],
12289 if (offset_expr.X_op != O_symbol
12290 && offset_expr.X_op != O_constant)
12292 as_bad (_("expression too complex"));
12293 offset_expr.X_op = O_constant;
12296 if (HAVE_32BIT_ADDRESSES
12297 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12301 sprintf_vma (value, offset_expr.X_add_number);
12302 as_bad (_("number (0x%s) larger than 32 bits"), value);
12305 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
12307 /* If this is a reference to a GP relative symbol, we want
12308 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12309 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12310 If we have a base register, we use this
12312 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12313 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12314 If this is not a GP relative symbol, we want
12315 lui $at,<sym> (BFD_RELOC_HI16_S)
12316 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12317 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12318 If there is a base register, we add it to $at after the
12319 lui instruction. If there is a constant, we always use
12321 if (offset_expr.X_op == O_symbol
12322 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12323 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12325 relax_start (offset_expr.X_add_symbol);
12328 tempreg = mips_gp_register;
12332 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12333 AT, breg, mips_gp_register);
12338 /* Itbl support may require additional care here. */
12339 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12340 BFD_RELOC_GPREL16, tempreg);
12341 offset_expr.X_add_number += 4;
12343 /* Set mips_optimize to 2 to avoid inserting an
12345 hold_mips_optimize = mips_optimize;
12347 /* Itbl support may require additional care here. */
12348 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12349 BFD_RELOC_GPREL16, tempreg);
12350 mips_optimize = hold_mips_optimize;
12354 offset_expr.X_add_number -= 4;
12357 if (offset_high_part (offset_expr.X_add_number, 16)
12358 != offset_high_part (offset_expr.X_add_number + 4, 16))
12360 load_address (AT, &offset_expr, &used_at);
12361 offset_expr.X_op = O_constant;
12362 offset_expr.X_add_number = 0;
12365 macro_build_lui (&offset_expr, AT);
12367 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12368 /* Itbl support may require additional care here. */
12369 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12370 BFD_RELOC_LO16, AT);
12371 /* FIXME: How do we handle overflow here? */
12372 offset_expr.X_add_number += 4;
12373 /* Itbl support may require additional care here. */
12374 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12375 BFD_RELOC_LO16, AT);
12376 if (mips_relax.sequence)
12379 else if (!mips_big_got)
12381 /* If this is a reference to an external symbol, we want
12382 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12385 <op> op[0]+1,4($at)
12387 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12389 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12390 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12391 If there is a base register we add it to $at before the
12392 lwc1 instructions. If there is a constant we include it
12393 in the lwc1 instructions. */
12395 expr1.X_add_number = offset_expr.X_add_number;
12396 if (expr1.X_add_number < -0x8000
12397 || expr1.X_add_number >= 0x8000 - 4)
12398 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12399 load_got_offset (AT, &offset_expr);
12402 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12404 /* Set mips_optimize to 2 to avoid inserting an undesired
12406 hold_mips_optimize = mips_optimize;
12409 /* Itbl support may require additional care here. */
12410 relax_start (offset_expr.X_add_symbol);
12411 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12412 BFD_RELOC_LO16, AT);
12413 expr1.X_add_number += 4;
12414 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12415 BFD_RELOC_LO16, AT);
12417 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12418 BFD_RELOC_LO16, AT);
12419 offset_expr.X_add_number += 4;
12420 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12421 BFD_RELOC_LO16, AT);
12424 mips_optimize = hold_mips_optimize;
12426 else if (mips_big_got)
12430 /* If this is a reference to an external symbol, we want
12431 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12433 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12436 <op> op[0]+1,4($at)
12438 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12440 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12441 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12442 If there is a base register we add it to $at before the
12443 lwc1 instructions. If there is a constant we include it
12444 in the lwc1 instructions. */
12446 expr1.X_add_number = offset_expr.X_add_number;
12447 offset_expr.X_add_number = 0;
12448 if (expr1.X_add_number < -0x8000
12449 || expr1.X_add_number >= 0x8000 - 4)
12450 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12451 gpdelay = reg_needs_delay (mips_gp_register);
12452 relax_start (offset_expr.X_add_symbol);
12453 macro_build (&offset_expr, "lui", LUI_FMT,
12454 AT, BFD_RELOC_MIPS_GOT_HI16);
12455 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12456 AT, AT, mips_gp_register);
12457 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
12458 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
12461 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12462 /* Itbl support may require additional care here. */
12463 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
12464 BFD_RELOC_LO16, AT);
12465 expr1.X_add_number += 4;
12467 /* Set mips_optimize to 2 to avoid inserting an undesired
12469 hold_mips_optimize = mips_optimize;
12471 /* Itbl support may require additional care here. */
12472 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
12473 BFD_RELOC_LO16, AT);
12474 mips_optimize = hold_mips_optimize;
12475 expr1.X_add_number -= 4;
12478 offset_expr.X_add_number = expr1.X_add_number;
12480 macro_build (NULL, "nop", "");
12481 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12482 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12485 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
12486 /* Itbl support may require additional care here. */
12487 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
12488 BFD_RELOC_LO16, AT);
12489 offset_expr.X_add_number += 4;
12491 /* Set mips_optimize to 2 to avoid inserting an undesired
12493 hold_mips_optimize = mips_optimize;
12495 /* Itbl support may require additional care here. */
12496 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
12497 BFD_RELOC_LO16, AT);
12498 mips_optimize = hold_mips_optimize;
12512 gas_assert (!mips_opts.micromips);
12517 /* New code added to support COPZ instructions.
12518 This code builds table entries out of the macros in mip_opcodes.
12519 R4000 uses interlocks to handle coproc delays.
12520 Other chips (like the R3000) require nops to be inserted for delays.
12522 FIXME: Currently, we require that the user handle delays.
12523 In order to fill delay slots for non-interlocked chips,
12524 we must have a way to specify delays based on the coprocessor.
12525 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12526 What are the side-effects of the cop instruction?
12527 What cache support might we have and what are its effects?
12528 Both coprocessor & memory require delays. how long???
12529 What registers are read/set/modified?
12531 If an itbl is provided to interpret cop instructions,
12532 this knowledge can be encoded in the itbl spec. */
12546 gas_assert (!mips_opts.micromips);
12547 /* For now we just do C (same as Cz). The parameter will be
12548 stored in insn_opcode by mips_ip. */
12549 macro_build (NULL, s, "C", (int) ip->insn_opcode);
12553 move_register (op[0], op[1]);
12557 gas_assert (mips_opts.micromips);
12558 gas_assert (mips_opts.insn32);
12559 move_register (micromips_to_32_reg_h_map1[op[0]],
12560 micromips_to_32_reg_m_map[op[1]]);
12561 move_register (micromips_to_32_reg_h_map2[op[0]],
12562 micromips_to_32_reg_n_map[op[2]]);
12568 if (mips_opts.arch == CPU_R5900)
12569 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
12573 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
12574 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12581 /* The MIPS assembler some times generates shifts and adds. I'm
12582 not trying to be that fancy. GCC should do this for us
12585 load_register (AT, &imm_expr, dbl);
12586 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
12587 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12600 start_noreorder ();
12603 load_register (AT, &imm_expr, dbl);
12604 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
12605 op[1], imm ? AT : op[2]);
12606 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12607 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
12608 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12610 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
12613 if (mips_opts.micromips)
12614 micromips_label_expr (&label_expr);
12616 label_expr.X_add_number = 8;
12617 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
12618 macro_build (NULL, "nop", "");
12619 macro_build (NULL, "break", BRK_FMT, 6);
12620 if (mips_opts.micromips)
12621 micromips_add_label ();
12624 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12637 start_noreorder ();
12640 load_register (AT, &imm_expr, dbl);
12641 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
12642 op[1], imm ? AT : op[2]);
12643 macro_build (NULL, "mfhi", MFHL_FMT, AT);
12644 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
12646 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
12649 if (mips_opts.micromips)
12650 micromips_label_expr (&label_expr);
12652 label_expr.X_add_number = 8;
12653 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
12654 macro_build (NULL, "nop", "");
12655 macro_build (NULL, "break", BRK_FMT, 6);
12656 if (mips_opts.micromips)
12657 micromips_add_label ();
12663 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12665 if (op[0] == op[1])
12672 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
12673 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12677 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12678 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12679 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12680 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12684 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12686 if (op[0] == op[1])
12693 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12694 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12698 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12699 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12700 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12701 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12710 rot = imm_expr.X_add_number & 0x3f;
12711 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12713 rot = (64 - rot) & 0x3f;
12715 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12717 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12722 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12725 l = (rot < 0x20) ? "dsll" : "dsll32";
12726 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12729 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12730 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12731 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12739 rot = imm_expr.X_add_number & 0x1f;
12740 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12742 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12743 (32 - rot) & 0x1f);
12748 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12752 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12753 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12754 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12759 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12761 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12765 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12766 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12767 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12768 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12772 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12774 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12778 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12779 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12780 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12781 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12790 rot = imm_expr.X_add_number & 0x3f;
12791 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12794 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12796 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12801 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12804 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12805 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12808 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12809 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12810 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12818 rot = imm_expr.X_add_number & 0x1f;
12819 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12821 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12826 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12830 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12831 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12832 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12838 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12839 else if (op[2] == 0)
12840 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12843 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12844 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12849 if (imm_expr.X_add_number == 0)
12851 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12856 as_warn (_("instruction %s: result is always false"),
12857 ip->insn_mo->name);
12858 move_register (op[0], 0);
12861 if (CPU_HAS_SEQ (mips_opts.arch)
12862 && -512 <= imm_expr.X_add_number
12863 && imm_expr.X_add_number < 512)
12865 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12866 (int) imm_expr.X_add_number);
12869 if (imm_expr.X_add_number >= 0
12870 && imm_expr.X_add_number < 0x10000)
12871 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12872 else if (imm_expr.X_add_number > -0x8000
12873 && imm_expr.X_add_number < 0)
12875 imm_expr.X_add_number = -imm_expr.X_add_number;
12876 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
12877 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12879 else if (CPU_HAS_SEQ (mips_opts.arch))
12882 load_register (AT, &imm_expr, GPR_SIZE == 64);
12883 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12888 load_register (AT, &imm_expr, GPR_SIZE == 64);
12889 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12892 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12895 case M_SGE: /* X >= Y <==> not (X < Y) */
12901 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12902 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12905 case M_SGE_I: /* X >= I <==> not (X < I) */
12907 if (imm_expr.X_add_number >= -0x8000
12908 && imm_expr.X_add_number < 0x8000)
12909 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12910 op[0], op[1], BFD_RELOC_LO16);
12913 load_register (AT, &imm_expr, GPR_SIZE == 64);
12914 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12918 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12921 case M_SGT: /* X > Y <==> Y < X */
12927 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12930 case M_SGT_I: /* X > I <==> I < X */
12937 load_register (AT, &imm_expr, GPR_SIZE == 64);
12938 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12941 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12947 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12948 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12951 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12958 load_register (AT, &imm_expr, GPR_SIZE == 64);
12959 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12960 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12964 if (imm_expr.X_add_number >= -0x8000
12965 && imm_expr.X_add_number < 0x8000)
12967 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12972 load_register (AT, &imm_expr, GPR_SIZE == 64);
12973 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
12977 if (imm_expr.X_add_number >= -0x8000
12978 && imm_expr.X_add_number < 0x8000)
12980 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
12985 load_register (AT, &imm_expr, GPR_SIZE == 64);
12986 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
12991 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12992 else if (op[2] == 0)
12993 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12996 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12997 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13002 if (imm_expr.X_add_number == 0)
13004 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13009 as_warn (_("instruction %s: result is always true"),
13010 ip->insn_mo->name);
13011 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13012 op[0], 0, BFD_RELOC_LO16);
13015 if (CPU_HAS_SEQ (mips_opts.arch)
13016 && -512 <= imm_expr.X_add_number
13017 && imm_expr.X_add_number < 512)
13019 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13020 (int) imm_expr.X_add_number);
13023 if (imm_expr.X_add_number >= 0
13024 && imm_expr.X_add_number < 0x10000)
13026 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13029 else if (imm_expr.X_add_number > -0x8000
13030 && imm_expr.X_add_number < 0)
13032 imm_expr.X_add_number = -imm_expr.X_add_number;
13033 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13034 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13036 else if (CPU_HAS_SEQ (mips_opts.arch))
13039 load_register (AT, &imm_expr, GPR_SIZE == 64);
13040 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13045 load_register (AT, &imm_expr, GPR_SIZE == 64);
13046 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13049 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13064 if (!mips_opts.micromips)
13066 if (imm_expr.X_add_number > -0x200
13067 && imm_expr.X_add_number <= 0x200)
13069 macro_build (NULL, s, "t,r,.", op[0], op[1],
13070 (int) -imm_expr.X_add_number);
13079 if (imm_expr.X_add_number > -0x8000
13080 && imm_expr.X_add_number <= 0x8000)
13082 imm_expr.X_add_number = -imm_expr.X_add_number;
13083 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13088 load_register (AT, &imm_expr, dbl);
13089 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13111 load_register (AT, &imm_expr, GPR_SIZE == 64);
13112 macro_build (NULL, s, "s,t", op[0], AT);
13117 gas_assert (!mips_opts.micromips);
13118 gas_assert (mips_opts.isa == ISA_MIPS1);
13122 * Is the double cfc1 instruction a bug in the mips assembler;
13123 * or is there a reason for it?
13125 start_noreorder ();
13126 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13127 macro_build (NULL, "cfc1", "t,G", op[2], RA);
13128 macro_build (NULL, "nop", "");
13129 expr1.X_add_number = 3;
13130 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13131 expr1.X_add_number = 2;
13132 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13133 macro_build (NULL, "ctc1", "t,G", AT, RA);
13134 macro_build (NULL, "nop", "");
13135 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13137 macro_build (NULL, "ctc1", "t,G", op[2], RA);
13138 macro_build (NULL, "nop", "");
13155 offbits = (mips_opts.micromips ? 12 : 16);
13161 offbits = (mips_opts.micromips ? 12 : 16);
13173 offbits = (mips_opts.micromips ? 12 : 16);
13180 offbits = (mips_opts.micromips ? 12 : 16);
13186 large_offset = !small_offset_p (off, align, offbits);
13188 expr1.X_add_number = 0;
13193 if (small_offset_p (0, align, 16))
13194 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
13195 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
13198 load_address (tempreg, ep, &used_at);
13200 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13201 tempreg, tempreg, breg);
13203 offset_reloc[0] = BFD_RELOC_LO16;
13204 offset_reloc[1] = BFD_RELOC_UNUSED;
13205 offset_reloc[2] = BFD_RELOC_UNUSED;
13210 else if (!ust && op[0] == breg)
13221 if (!target_big_endian)
13222 ep->X_add_number += off;
13224 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
13226 macro_build (ep, s, "t,o(b)", tempreg, -1,
13227 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13229 if (!target_big_endian)
13230 ep->X_add_number -= off;
13232 ep->X_add_number += off;
13234 macro_build (NULL, s2, "t,~(b)",
13235 tempreg, (int) ep->X_add_number, breg);
13237 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13238 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13240 /* If necessary, move the result in tempreg to the final destination. */
13241 if (!ust && op[0] != tempreg)
13243 /* Protect second load's delay slot. */
13245 move_register (op[0], tempreg);
13251 if (target_big_endian == ust)
13252 ep->X_add_number += off;
13253 tempreg = ust || large_offset ? op[0] : AT;
13254 macro_build (ep, s, "t,o(b)", tempreg, -1,
13255 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13257 /* For halfword transfers we need a temporary register to shuffle
13258 bytes. Unfortunately for M_USH_A we have none available before
13259 the next store as AT holds the base address. We deal with this
13260 case by clobbering TREG and then restoring it as with ULH. */
13261 tempreg = ust == large_offset ? op[0] : AT;
13263 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
13265 if (target_big_endian == ust)
13266 ep->X_add_number -= off;
13268 ep->X_add_number += off;
13269 macro_build (ep, s2, "t,o(b)", tempreg, -1,
13270 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
13272 /* For M_USH_A re-retrieve the LSB. */
13273 if (ust && large_offset)
13275 if (target_big_endian)
13276 ep->X_add_number += off;
13278 ep->X_add_number -= off;
13279 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
13280 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
13282 /* For ULH and M_USH_A OR the LSB in. */
13283 if (!ust || large_offset)
13285 tempreg = !large_offset ? AT : op[0];
13286 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
13287 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13292 /* FIXME: Check if this is one of the itbl macros, since they
13293 are added dynamically. */
13294 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
13297 if (!mips_opts.at && used_at)
13298 as_bad (_("macro used $at after \".set noat\""));
13301 /* Implement macros in mips16 mode. */
13304 mips16_macro (struct mips_cl_insn *ip)
13306 const struct mips_operand_array *operands;
13311 const char *s, *s2, *s3;
13312 unsigned int op[MAX_OPERANDS];
13315 mask = ip->insn_mo->mask;
13317 operands = insn_operands (ip);
13318 for (i = 0; i < MAX_OPERANDS; i++)
13319 if (operands->operand[i])
13320 op[i] = insn_extract_operand (ip, operands->operand[i]);
13324 expr1.X_op = O_constant;
13325 expr1.X_op_symbol = NULL;
13326 expr1.X_add_symbol = NULL;
13327 expr1.X_add_number = 1;
13346 start_noreorder ();
13347 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
13348 expr1.X_add_number = 2;
13349 macro_build (&expr1, "bnez", "x,p", op[2]);
13350 macro_build (NULL, "break", "6", 7);
13352 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13353 since that causes an overflow. We should do that as well,
13354 but I don't see how to do the comparisons without a temporary
13357 macro_build (NULL, s, "x", op[0]);
13376 start_noreorder ();
13377 macro_build (NULL, s, "0,x,y", op[1], op[2]);
13378 expr1.X_add_number = 2;
13379 macro_build (&expr1, "bnez", "x,p", op[2]);
13380 macro_build (NULL, "break", "6", 7);
13382 macro_build (NULL, s2, "x", op[0]);
13388 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
13389 macro_build (NULL, "mflo", "x", op[0]);
13397 imm_expr.X_add_number = -imm_expr.X_add_number;
13398 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
13402 imm_expr.X_add_number = -imm_expr.X_add_number;
13403 macro_build (&imm_expr, "addiu", "x,k", op[0]);
13407 imm_expr.X_add_number = -imm_expr.X_add_number;
13408 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
13430 goto do_reverse_branch;
13434 goto do_reverse_branch;
13446 goto do_reverse_branch;
13457 macro_build (NULL, s, "x,y", op[0], op[1]);
13458 macro_build (&offset_expr, s2, "p");
13485 goto do_addone_branch_i;
13490 goto do_addone_branch_i;
13505 goto do_addone_branch_i;
13511 do_addone_branch_i:
13512 ++imm_expr.X_add_number;
13515 macro_build (&imm_expr, s, s3, op[0]);
13516 macro_build (&offset_expr, s2, "p");
13520 expr1.X_add_number = 0;
13521 macro_build (&expr1, "slti", "x,8", op[1]);
13522 if (op[0] != op[1])
13523 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
13524 expr1.X_add_number = 2;
13525 macro_build (&expr1, "bteqz", "p");
13526 macro_build (NULL, "neg", "x,w", op[0], op[0]);
13531 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13532 opcode bits in *OPCODE_EXTRA. */
13534 static struct mips_opcode *
13535 mips_lookup_insn (struct hash_control *hash, const char *start,
13536 ssize_t length, unsigned int *opcode_extra)
13538 char *name, *dot, *p;
13539 unsigned int mask, suffix;
13541 struct mips_opcode *insn;
13543 /* Make a copy of the instruction so that we can fiddle with it. */
13544 name = xstrndup (start, length);
13546 /* Look up the instruction as-is. */
13547 insn = (struct mips_opcode *) hash_find (hash, name);
13551 dot = strchr (name, '.');
13554 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13555 p = mips_parse_vu0_channels (dot + 1, &mask);
13556 if (*p == 0 && mask != 0)
13559 insn = (struct mips_opcode *) hash_find (hash, name);
13561 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
13563 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
13569 if (mips_opts.micromips)
13571 /* See if there's an instruction size override suffix,
13572 either `16' or `32', at the end of the mnemonic proper,
13573 that defines the operation, i.e. before the first `.'
13574 character if any. Strip it and retry. */
13575 opend = dot != NULL ? dot - name : length;
13576 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
13578 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
13584 memcpy (name + opend - 2, name + opend, length - opend + 1);
13585 insn = (struct mips_opcode *) hash_find (hash, name);
13588 forced_insn_length = suffix;
13600 /* Assemble an instruction into its binary format. If the instruction
13601 is a macro, set imm_expr and offset_expr to the values associated
13602 with "I" and "A" operands respectively. Otherwise store the value
13603 of the relocatable field (if any) in offset_expr. In both cases
13604 set offset_reloc to the relocation operators applied to offset_expr. */
13607 mips_ip (char *str, struct mips_cl_insn *insn)
13609 const struct mips_opcode *first, *past;
13610 struct hash_control *hash;
13613 struct mips_operand_token *tokens;
13614 unsigned int opcode_extra;
13616 if (mips_opts.micromips)
13618 hash = micromips_op_hash;
13619 past = µmips_opcodes[bfd_micromips_num_opcodes];
13624 past = &mips_opcodes[NUMOPCODES];
13626 forced_insn_length = 0;
13629 /* We first try to match an instruction up to a space or to the end. */
13630 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
13633 first = mips_lookup_insn (hash, str, end, &opcode_extra);
13636 set_insn_error (0, _("unrecognized opcode"));
13640 if (strcmp (first->name, "li.s") == 0)
13642 else if (strcmp (first->name, "li.d") == 0)
13646 tokens = mips_parse_arguments (str + end, format);
13650 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
13651 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
13652 set_insn_error (0, _("invalid operands"));
13654 obstack_free (&mips_operand_tokens, tokens);
13657 /* As for mips_ip, but used when assembling MIPS16 code.
13658 Also set forced_insn_length to the resulting instruction size in
13659 bytes if the user explicitly requested a small or extended instruction. */
13662 mips16_ip (char *str, struct mips_cl_insn *insn)
13665 struct mips_opcode *first;
13666 struct mips_operand_token *tokens;
13668 forced_insn_length = 0;
13670 for (s = str; ISLOWER (*s); ++s)
13684 if (s[1] == 't' && s[2] == ' ')
13686 forced_insn_length = 2;
13690 else if (s[1] == 'e' && s[2] == ' ')
13692 forced_insn_length = 4;
13696 /* Fall through. */
13698 set_insn_error (0, _("unrecognized opcode"));
13702 if (mips_opts.noautoextend && !forced_insn_length)
13703 forced_insn_length = 2;
13706 first = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13711 set_insn_error (0, _("unrecognized opcode"));
13715 tokens = mips_parse_arguments (s, 0);
13719 if (!match_mips16_insns (insn, first, tokens))
13720 set_insn_error (0, _("invalid operands"));
13722 obstack_free (&mips_operand_tokens, tokens);
13725 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13726 NBITS is the number of significant bits in VAL. */
13728 static unsigned long
13729 mips16_immed_extend (offsetT val, unsigned int nbits)
13734 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13737 else if (nbits == 15)
13739 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13744 extval = ((val & 0x1f) << 6) | (val & 0x20);
13747 return (extval << 16) | val;
13750 /* Like decode_mips16_operand, but require the operand to be defined and
13751 require it to be an integer. */
13753 static const struct mips_int_operand *
13754 mips16_immed_operand (int type, bfd_boolean extended_p)
13756 const struct mips_operand *operand;
13758 operand = decode_mips16_operand (type, extended_p);
13759 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13761 return (const struct mips_int_operand *) operand;
13764 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13767 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13768 bfd_reloc_code_real_type reloc, offsetT sval)
13770 int min_val, max_val;
13772 min_val = mips_int_operand_min (operand);
13773 max_val = mips_int_operand_max (operand);
13774 if (reloc != BFD_RELOC_UNUSED)
13777 sval = SEXT_16BIT (sval);
13782 return (sval >= min_val
13784 && (sval & ((1 << operand->shift) - 1)) == 0);
13787 /* Install immediate value VAL into MIPS16 instruction *INSN,
13788 extending it if necessary. The instruction in *INSN may
13789 already be extended.
13791 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13792 if none. In the former case, VAL is a 16-bit number with no
13793 defined signedness.
13795 TYPE is the type of the immediate field. USER_INSN_LENGTH
13796 is the length that the user requested, or 0 if none. */
13799 mips16_immed (const char *file, unsigned int line, int type,
13800 bfd_reloc_code_real_type reloc, offsetT val,
13801 unsigned int user_insn_length, unsigned long *insn)
13803 const struct mips_int_operand *operand;
13804 unsigned int uval, length;
13806 operand = mips16_immed_operand (type, FALSE);
13807 if (!mips16_immed_in_range_p (operand, reloc, val))
13809 /* We need an extended instruction. */
13810 if (user_insn_length == 2)
13811 as_bad_where (file, line, _("invalid unextended operand value"));
13813 *insn |= MIPS16_EXTEND;
13815 else if (user_insn_length == 4)
13817 /* The operand doesn't force an unextended instruction to be extended.
13818 Warn if the user wanted an extended instruction anyway. */
13819 *insn |= MIPS16_EXTEND;
13820 as_warn_where (file, line,
13821 _("extended operand requested but not required"));
13824 length = mips16_opcode_length (*insn);
13827 operand = mips16_immed_operand (type, TRUE);
13828 if (!mips16_immed_in_range_p (operand, reloc, val))
13829 as_bad_where (file, line,
13830 _("operand value out of range for instruction"));
13832 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13834 *insn = mips_insert_operand (&operand->root, *insn, uval);
13836 *insn |= mips16_immed_extend (uval, operand->root.size);
13839 struct percent_op_match
13842 bfd_reloc_code_real_type reloc;
13845 static const struct percent_op_match mips_percent_op[] =
13847 {"%lo", BFD_RELOC_LO16},
13848 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13849 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13850 {"%call16", BFD_RELOC_MIPS_CALL16},
13851 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13852 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13853 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13854 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13855 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13856 {"%got", BFD_RELOC_MIPS_GOT16},
13857 {"%gp_rel", BFD_RELOC_GPREL16},
13858 {"%half", BFD_RELOC_16},
13859 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13860 {"%higher", BFD_RELOC_MIPS_HIGHER},
13861 {"%neg", BFD_RELOC_MIPS_SUB},
13862 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13863 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13864 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13865 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13866 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13867 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13868 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13869 {"%hi", BFD_RELOC_HI16_S},
13870 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
13871 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
13874 static const struct percent_op_match mips16_percent_op[] =
13876 {"%lo", BFD_RELOC_MIPS16_LO16},
13877 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13878 {"%got", BFD_RELOC_MIPS16_GOT16},
13879 {"%call16", BFD_RELOC_MIPS16_CALL16},
13880 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13881 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13882 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13883 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13884 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13885 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13886 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13887 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13891 /* Return true if *STR points to a relocation operator. When returning true,
13892 move *STR over the operator and store its relocation code in *RELOC.
13893 Leave both *STR and *RELOC alone when returning false. */
13896 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13898 const struct percent_op_match *percent_op;
13901 if (mips_opts.mips16)
13903 percent_op = mips16_percent_op;
13904 limit = ARRAY_SIZE (mips16_percent_op);
13908 percent_op = mips_percent_op;
13909 limit = ARRAY_SIZE (mips_percent_op);
13912 for (i = 0; i < limit; i++)
13913 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13915 int len = strlen (percent_op[i].str);
13917 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13920 *str += strlen (percent_op[i].str);
13921 *reloc = percent_op[i].reloc;
13923 /* Check whether the output BFD supports this relocation.
13924 If not, issue an error and fall back on something safe. */
13925 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13927 as_bad (_("relocation %s isn't supported by the current ABI"),
13928 percent_op[i].str);
13929 *reloc = BFD_RELOC_UNUSED;
13937 /* Parse string STR as a 16-bit relocatable operand. Store the
13938 expression in *EP and the relocations in the array starting
13939 at RELOC. Return the number of relocation operators used.
13941 On exit, EXPR_END points to the first character after the expression. */
13944 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13947 bfd_reloc_code_real_type reversed_reloc[3];
13948 size_t reloc_index, i;
13949 int crux_depth, str_depth;
13952 /* Search for the start of the main expression, recoding relocations
13953 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13954 of the main expression and with CRUX_DEPTH containing the number
13955 of open brackets at that point. */
13962 crux_depth = str_depth;
13964 /* Skip over whitespace and brackets, keeping count of the number
13966 while (*str == ' ' || *str == '\t' || *str == '(')
13971 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13972 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13974 my_getExpression (ep, crux);
13977 /* Match every open bracket. */
13978 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13982 if (crux_depth > 0)
13983 as_bad (_("unclosed '('"));
13987 if (reloc_index != 0)
13989 prev_reloc_op_frag = frag_now;
13990 for (i = 0; i < reloc_index; i++)
13991 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13994 return reloc_index;
13998 my_getExpression (expressionS *ep, char *str)
14002 save_in = input_line_pointer;
14003 input_line_pointer = str;
14005 expr_end = input_line_pointer;
14006 input_line_pointer = save_in;
14010 md_atof (int type, char *litP, int *sizeP)
14012 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14016 md_number_to_chars (char *buf, valueT val, int n)
14018 if (target_big_endian)
14019 number_to_chars_bigendian (buf, val, n);
14021 number_to_chars_littleendian (buf, val, n);
14024 static int support_64bit_objects(void)
14026 const char **list, **l;
14029 list = bfd_target_list ();
14030 for (l = list; *l != NULL; l++)
14031 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14032 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14034 yes = (*l != NULL);
14039 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14040 NEW_VALUE. Warn if another value was already specified. Note:
14041 we have to defer parsing the -march and -mtune arguments in order
14042 to handle 'from-abi' correctly, since the ABI might be specified
14043 in a later argument. */
14046 mips_set_option_string (const char **string_ptr, const char *new_value)
14048 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14049 as_warn (_("a different %s was already specified, is now %s"),
14050 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14053 *string_ptr = new_value;
14057 md_parse_option (int c, const char *arg)
14061 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14062 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14064 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14065 c == mips_ases[i].option_on);
14071 case OPTION_CONSTRUCT_FLOATS:
14072 mips_disable_float_construction = 0;
14075 case OPTION_NO_CONSTRUCT_FLOATS:
14076 mips_disable_float_construction = 1;
14088 target_big_endian = 1;
14092 target_big_endian = 0;
14098 else if (arg[0] == '0')
14100 else if (arg[0] == '1')
14110 mips_debug = atoi (arg);
14114 file_mips_opts.isa = ISA_MIPS1;
14118 file_mips_opts.isa = ISA_MIPS2;
14122 file_mips_opts.isa = ISA_MIPS3;
14126 file_mips_opts.isa = ISA_MIPS4;
14130 file_mips_opts.isa = ISA_MIPS5;
14133 case OPTION_MIPS32:
14134 file_mips_opts.isa = ISA_MIPS32;
14137 case OPTION_MIPS32R2:
14138 file_mips_opts.isa = ISA_MIPS32R2;
14141 case OPTION_MIPS32R3:
14142 file_mips_opts.isa = ISA_MIPS32R3;
14145 case OPTION_MIPS32R5:
14146 file_mips_opts.isa = ISA_MIPS32R5;
14149 case OPTION_MIPS32R6:
14150 file_mips_opts.isa = ISA_MIPS32R6;
14153 case OPTION_MIPS64R2:
14154 file_mips_opts.isa = ISA_MIPS64R2;
14157 case OPTION_MIPS64R3:
14158 file_mips_opts.isa = ISA_MIPS64R3;
14161 case OPTION_MIPS64R5:
14162 file_mips_opts.isa = ISA_MIPS64R5;
14165 case OPTION_MIPS64R6:
14166 file_mips_opts.isa = ISA_MIPS64R6;
14169 case OPTION_MIPS64:
14170 file_mips_opts.isa = ISA_MIPS64;
14174 mips_set_option_string (&mips_tune_string, arg);
14178 mips_set_option_string (&mips_arch_string, arg);
14182 mips_set_option_string (&mips_arch_string, "4650");
14183 mips_set_option_string (&mips_tune_string, "4650");
14186 case OPTION_NO_M4650:
14190 mips_set_option_string (&mips_arch_string, "4010");
14191 mips_set_option_string (&mips_tune_string, "4010");
14194 case OPTION_NO_M4010:
14198 mips_set_option_string (&mips_arch_string, "4100");
14199 mips_set_option_string (&mips_tune_string, "4100");
14202 case OPTION_NO_M4100:
14206 mips_set_option_string (&mips_arch_string, "3900");
14207 mips_set_option_string (&mips_tune_string, "3900");
14210 case OPTION_NO_M3900:
14213 case OPTION_MICROMIPS:
14214 if (file_mips_opts.mips16 == 1)
14216 as_bad (_("-mmicromips cannot be used with -mips16"));
14219 file_mips_opts.micromips = 1;
14220 mips_no_prev_insn ();
14223 case OPTION_NO_MICROMIPS:
14224 file_mips_opts.micromips = 0;
14225 mips_no_prev_insn ();
14228 case OPTION_MIPS16:
14229 if (file_mips_opts.micromips == 1)
14231 as_bad (_("-mips16 cannot be used with -micromips"));
14234 file_mips_opts.mips16 = 1;
14235 mips_no_prev_insn ();
14238 case OPTION_NO_MIPS16:
14239 file_mips_opts.mips16 = 0;
14240 mips_no_prev_insn ();
14243 case OPTION_FIX_24K:
14247 case OPTION_NO_FIX_24K:
14251 case OPTION_FIX_RM7000:
14252 mips_fix_rm7000 = 1;
14255 case OPTION_NO_FIX_RM7000:
14256 mips_fix_rm7000 = 0;
14259 case OPTION_FIX_LOONGSON2F_JUMP:
14260 mips_fix_loongson2f_jump = TRUE;
14263 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14264 mips_fix_loongson2f_jump = FALSE;
14267 case OPTION_FIX_LOONGSON2F_NOP:
14268 mips_fix_loongson2f_nop = TRUE;
14271 case OPTION_NO_FIX_LOONGSON2F_NOP:
14272 mips_fix_loongson2f_nop = FALSE;
14275 case OPTION_FIX_VR4120:
14276 mips_fix_vr4120 = 1;
14279 case OPTION_NO_FIX_VR4120:
14280 mips_fix_vr4120 = 0;
14283 case OPTION_FIX_VR4130:
14284 mips_fix_vr4130 = 1;
14287 case OPTION_NO_FIX_VR4130:
14288 mips_fix_vr4130 = 0;
14291 case OPTION_FIX_CN63XXP1:
14292 mips_fix_cn63xxp1 = TRUE;
14295 case OPTION_NO_FIX_CN63XXP1:
14296 mips_fix_cn63xxp1 = FALSE;
14299 case OPTION_RELAX_BRANCH:
14300 mips_relax_branch = 1;
14303 case OPTION_NO_RELAX_BRANCH:
14304 mips_relax_branch = 0;
14307 case OPTION_INSN32:
14308 file_mips_opts.insn32 = TRUE;
14311 case OPTION_NO_INSN32:
14312 file_mips_opts.insn32 = FALSE;
14315 case OPTION_MSHARED:
14316 mips_in_shared = TRUE;
14319 case OPTION_MNO_SHARED:
14320 mips_in_shared = FALSE;
14323 case OPTION_MSYM32:
14324 file_mips_opts.sym32 = TRUE;
14327 case OPTION_MNO_SYM32:
14328 file_mips_opts.sym32 = FALSE;
14331 /* When generating ELF code, we permit -KPIC and -call_shared to
14332 select SVR4_PIC, and -non_shared to select no PIC. This is
14333 intended to be compatible with Irix 5. */
14334 case OPTION_CALL_SHARED:
14335 mips_pic = SVR4_PIC;
14336 mips_abicalls = TRUE;
14339 case OPTION_CALL_NONPIC:
14341 mips_abicalls = TRUE;
14344 case OPTION_NON_SHARED:
14346 mips_abicalls = FALSE;
14349 /* The -xgot option tells the assembler to use 32 bit offsets
14350 when accessing the got in SVR4_PIC mode. It is for Irix
14357 g_switch_value = atoi (arg);
14361 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14364 mips_abi = O32_ABI;
14368 mips_abi = N32_ABI;
14372 mips_abi = N64_ABI;
14373 if (!support_64bit_objects())
14374 as_fatal (_("no compiled in support for 64 bit object file format"));
14378 file_mips_opts.gp = 32;
14382 file_mips_opts.gp = 64;
14386 file_mips_opts.fp = 32;
14390 file_mips_opts.fp = 0;
14394 file_mips_opts.fp = 64;
14397 case OPTION_ODD_SPREG:
14398 file_mips_opts.oddspreg = 1;
14401 case OPTION_NO_ODD_SPREG:
14402 file_mips_opts.oddspreg = 0;
14405 case OPTION_SINGLE_FLOAT:
14406 file_mips_opts.single_float = 1;
14409 case OPTION_DOUBLE_FLOAT:
14410 file_mips_opts.single_float = 0;
14413 case OPTION_SOFT_FLOAT:
14414 file_mips_opts.soft_float = 1;
14417 case OPTION_HARD_FLOAT:
14418 file_mips_opts.soft_float = 0;
14422 if (strcmp (arg, "32") == 0)
14423 mips_abi = O32_ABI;
14424 else if (strcmp (arg, "o64") == 0)
14425 mips_abi = O64_ABI;
14426 else if (strcmp (arg, "n32") == 0)
14427 mips_abi = N32_ABI;
14428 else if (strcmp (arg, "64") == 0)
14430 mips_abi = N64_ABI;
14431 if (! support_64bit_objects())
14432 as_fatal (_("no compiled in support for 64 bit object file "
14435 else if (strcmp (arg, "eabi") == 0)
14436 mips_abi = EABI_ABI;
14439 as_fatal (_("invalid abi -mabi=%s"), arg);
14444 case OPTION_M7000_HILO_FIX:
14445 mips_7000_hilo_fix = TRUE;
14448 case OPTION_MNO_7000_HILO_FIX:
14449 mips_7000_hilo_fix = FALSE;
14452 case OPTION_MDEBUG:
14453 mips_flag_mdebug = TRUE;
14456 case OPTION_NO_MDEBUG:
14457 mips_flag_mdebug = FALSE;
14461 mips_flag_pdr = TRUE;
14464 case OPTION_NO_PDR:
14465 mips_flag_pdr = FALSE;
14468 case OPTION_MVXWORKS_PIC:
14469 mips_pic = VXWORKS_PIC;
14473 if (strcmp (arg, "2008") == 0)
14475 else if (strcmp (arg, "legacy") == 0)
14479 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
14488 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14493 /* Set up globals to tune for the ISA or processor described by INFO. */
14496 mips_set_tune (const struct mips_cpu_info *info)
14499 mips_tune = info->cpu;
14504 mips_after_parse_args (void)
14506 const struct mips_cpu_info *arch_info = 0;
14507 const struct mips_cpu_info *tune_info = 0;
14509 /* GP relative stuff not working for PE */
14510 if (strncmp (TARGET_OS, "pe", 2) == 0)
14512 if (g_switch_seen && g_switch_value != 0)
14513 as_bad (_("-G not supported in this configuration"));
14514 g_switch_value = 0;
14517 if (mips_abi == NO_ABI)
14518 mips_abi = MIPS_DEFAULT_ABI;
14520 /* The following code determines the architecture.
14521 Similar code was added to GCC 3.3 (see override_options() in
14522 config/mips/mips.c). The GAS and GCC code should be kept in sync
14523 as much as possible. */
14525 if (mips_arch_string != 0)
14526 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14528 if (file_mips_opts.isa != ISA_UNKNOWN)
14530 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14531 ISA level specified by -mipsN, while arch_info->isa contains
14532 the -march selection (if any). */
14533 if (arch_info != 0)
14535 /* -march takes precedence over -mipsN, since it is more descriptive.
14536 There's no harm in specifying both as long as the ISA levels
14538 if (file_mips_opts.isa != arch_info->isa)
14539 as_bad (_("-%s conflicts with the other architecture options,"
14540 " which imply -%s"),
14541 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14542 mips_cpu_info_from_isa (arch_info->isa)->name);
14545 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14548 if (arch_info == 0)
14550 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14551 gas_assert (arch_info);
14554 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14555 as_bad (_("-march=%s is not compatible with the selected ABI"),
14558 file_mips_opts.arch = arch_info->cpu;
14559 file_mips_opts.isa = arch_info->isa;
14561 /* Set up initial mips_opts state. */
14562 mips_opts = file_mips_opts;
14564 /* The register size inference code is now placed in
14565 file_mips_check_options. */
14567 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14569 if (mips_tune_string != 0)
14570 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14572 if (tune_info == 0)
14573 mips_set_tune (arch_info);
14575 mips_set_tune (tune_info);
14577 if (mips_flag_mdebug < 0)
14578 mips_flag_mdebug = 0;
14582 mips_init_after_args (void)
14584 /* initialize opcodes */
14585 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14586 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14590 md_pcrel_from (fixS *fixP)
14592 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14593 switch (fixP->fx_r_type)
14595 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14596 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14597 /* Return the address of the delay slot. */
14600 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14601 case BFD_RELOC_MICROMIPS_JMP:
14602 case BFD_RELOC_16_PCREL_S2:
14603 case BFD_RELOC_MIPS_21_PCREL_S2:
14604 case BFD_RELOC_MIPS_26_PCREL_S2:
14605 case BFD_RELOC_MIPS_JMP:
14606 /* Return the address of the delay slot. */
14614 /* This is called before the symbol table is processed. In order to
14615 work with gcc when using mips-tfile, we must keep all local labels.
14616 However, in other cases, we want to discard them. If we were
14617 called with -g, but we didn't see any debugging information, it may
14618 mean that gcc is smuggling debugging information through to
14619 mips-tfile, in which case we must generate all local labels. */
14622 mips_frob_file_before_adjust (void)
14624 #ifndef NO_ECOFF_DEBUGGING
14625 if (ECOFF_DEBUGGING
14627 && ! ecoff_debugging_seen)
14628 flag_keep_locals = 1;
14632 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14633 the corresponding LO16 reloc. This is called before md_apply_fix and
14634 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14635 relocation operators.
14637 For our purposes, a %lo() expression matches a %got() or %hi()
14640 (a) it refers to the same symbol; and
14641 (b) the offset applied in the %lo() expression is no lower than
14642 the offset applied in the %got() or %hi().
14644 (b) allows us to cope with code like:
14647 lh $4,%lo(foo+2)($4)
14649 ...which is legal on RELA targets, and has a well-defined behaviour
14650 if the user knows that adding 2 to "foo" will not induce a carry to
14653 When several %lo()s match a particular %got() or %hi(), we use the
14654 following rules to distinguish them:
14656 (1) %lo()s with smaller offsets are a better match than %lo()s with
14659 (2) %lo()s with no matching %got() or %hi() are better than those
14660 that already have a matching %got() or %hi().
14662 (3) later %lo()s are better than earlier %lo()s.
14664 These rules are applied in order.
14666 (1) means, among other things, that %lo()s with identical offsets are
14667 chosen if they exist.
14669 (2) means that we won't associate several high-part relocations with
14670 the same low-part relocation unless there's no alternative. Having
14671 several high parts for the same low part is a GNU extension; this rule
14672 allows careful users to avoid it.
14674 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14675 with the last high-part relocation being at the front of the list.
14676 It therefore makes sense to choose the last matching low-part
14677 relocation, all other things being equal. It's also easier
14678 to code that way. */
14681 mips_frob_file (void)
14683 struct mips_hi_fixup *l;
14684 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14686 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14688 segment_info_type *seginfo;
14689 bfd_boolean matched_lo_p;
14690 fixS **hi_pos, **lo_pos, **pos;
14692 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14694 /* If a GOT16 relocation turns out to be against a global symbol,
14695 there isn't supposed to be a matching LO. Ignore %gots against
14696 constants; we'll report an error for those later. */
14697 if (got16_reloc_p (l->fixp->fx_r_type)
14698 && !(l->fixp->fx_addsy
14699 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14702 /* Check quickly whether the next fixup happens to be a matching %lo. */
14703 if (fixup_has_matching_lo_p (l->fixp))
14706 seginfo = seg_info (l->seg);
14708 /* Set HI_POS to the position of this relocation in the chain.
14709 Set LO_POS to the position of the chosen low-part relocation.
14710 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14711 relocation that matches an immediately-preceding high-part
14715 matched_lo_p = FALSE;
14716 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14718 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14720 if (*pos == l->fixp)
14723 if ((*pos)->fx_r_type == looking_for_rtype
14724 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14725 && (*pos)->fx_offset >= l->fixp->fx_offset
14727 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14729 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14732 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14733 && fixup_has_matching_lo_p (*pos));
14736 /* If we found a match, remove the high-part relocation from its
14737 current position and insert it before the low-part relocation.
14738 Make the offsets match so that fixup_has_matching_lo_p()
14741 We don't warn about unmatched high-part relocations since some
14742 versions of gcc have been known to emit dead "lui ...%hi(...)"
14744 if (lo_pos != NULL)
14746 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14747 if (l->fixp->fx_next != *lo_pos)
14749 *hi_pos = l->fixp->fx_next;
14750 l->fixp->fx_next = *lo_pos;
14758 mips_force_relocation (fixS *fixp)
14760 if (generic_force_reloc (fixp))
14763 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14764 so that the linker relaxation can update targets. */
14765 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14766 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14767 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14770 /* We want all PC-relative relocations to be kept for R6 relaxation. */
14771 if (ISA_IS_R6 (mips_opts.isa)
14772 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
14773 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
14774 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
14775 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
14776 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
14777 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
14778 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
14784 /* Read the instruction associated with RELOC from BUF. */
14786 static unsigned int
14787 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14789 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14790 return read_compressed_insn (buf, 4);
14792 return read_insn (buf);
14795 /* Write instruction INSN to BUF, given that it has been relocated
14799 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14800 unsigned long insn)
14802 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14803 write_compressed_insn (buf, insn, 4);
14805 write_insn (buf, insn);
14808 /* Apply a fixup to the object file. */
14811 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14814 unsigned long insn;
14815 reloc_howto_type *howto;
14817 if (fixP->fx_pcrel)
14818 switch (fixP->fx_r_type)
14820 case BFD_RELOC_16_PCREL_S2:
14821 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14822 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14823 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14824 case BFD_RELOC_32_PCREL:
14825 case BFD_RELOC_MIPS_21_PCREL_S2:
14826 case BFD_RELOC_MIPS_26_PCREL_S2:
14827 case BFD_RELOC_MIPS_18_PCREL_S3:
14828 case BFD_RELOC_MIPS_19_PCREL_S2:
14829 case BFD_RELOC_HI16_S_PCREL:
14830 case BFD_RELOC_LO16_PCREL:
14834 fixP->fx_r_type = BFD_RELOC_32_PCREL;
14838 as_bad_where (fixP->fx_file, fixP->fx_line,
14839 _("PC-relative reference to a different section"));
14843 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14844 that have no MIPS ELF equivalent. */
14845 if (fixP->fx_r_type != BFD_RELOC_8)
14847 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14852 gas_assert (fixP->fx_size == 2
14853 || fixP->fx_size == 4
14854 || fixP->fx_r_type == BFD_RELOC_8
14855 || fixP->fx_r_type == BFD_RELOC_16
14856 || fixP->fx_r_type == BFD_RELOC_64
14857 || fixP->fx_r_type == BFD_RELOC_CTOR
14858 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14859 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14860 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14861 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14862 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
14863 || fixP->fx_r_type == BFD_RELOC_NONE);
14865 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14867 /* Don't treat parts of a composite relocation as done. There are two
14870 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14871 should nevertheless be emitted if the first part is.
14873 (2) In normal usage, composite relocations are never assembly-time
14874 constants. The easiest way of dealing with the pathological
14875 exceptions is to generate a relocation against STN_UNDEF and
14876 leave everything up to the linker. */
14877 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14880 switch (fixP->fx_r_type)
14882 case BFD_RELOC_MIPS_TLS_GD:
14883 case BFD_RELOC_MIPS_TLS_LDM:
14884 case BFD_RELOC_MIPS_TLS_DTPREL32:
14885 case BFD_RELOC_MIPS_TLS_DTPREL64:
14886 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14887 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14888 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14889 case BFD_RELOC_MIPS_TLS_TPREL32:
14890 case BFD_RELOC_MIPS_TLS_TPREL64:
14891 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14892 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14893 case BFD_RELOC_MICROMIPS_TLS_GD:
14894 case BFD_RELOC_MICROMIPS_TLS_LDM:
14895 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14896 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14897 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14898 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14899 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14900 case BFD_RELOC_MIPS16_TLS_GD:
14901 case BFD_RELOC_MIPS16_TLS_LDM:
14902 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14903 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14904 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14905 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14906 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14907 if (!fixP->fx_addsy)
14909 as_bad_where (fixP->fx_file, fixP->fx_line,
14910 _("TLS relocation against a constant"));
14913 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14916 case BFD_RELOC_MIPS_JMP:
14917 case BFD_RELOC_MIPS_SHIFT5:
14918 case BFD_RELOC_MIPS_SHIFT6:
14919 case BFD_RELOC_MIPS_GOT_DISP:
14920 case BFD_RELOC_MIPS_GOT_PAGE:
14921 case BFD_RELOC_MIPS_GOT_OFST:
14922 case BFD_RELOC_MIPS_SUB:
14923 case BFD_RELOC_MIPS_INSERT_A:
14924 case BFD_RELOC_MIPS_INSERT_B:
14925 case BFD_RELOC_MIPS_DELETE:
14926 case BFD_RELOC_MIPS_HIGHEST:
14927 case BFD_RELOC_MIPS_HIGHER:
14928 case BFD_RELOC_MIPS_SCN_DISP:
14929 case BFD_RELOC_MIPS_REL16:
14930 case BFD_RELOC_MIPS_RELGOT:
14931 case BFD_RELOC_MIPS_JALR:
14932 case BFD_RELOC_HI16:
14933 case BFD_RELOC_HI16_S:
14934 case BFD_RELOC_LO16:
14935 case BFD_RELOC_GPREL16:
14936 case BFD_RELOC_MIPS_LITERAL:
14937 case BFD_RELOC_MIPS_CALL16:
14938 case BFD_RELOC_MIPS_GOT16:
14939 case BFD_RELOC_GPREL32:
14940 case BFD_RELOC_MIPS_GOT_HI16:
14941 case BFD_RELOC_MIPS_GOT_LO16:
14942 case BFD_RELOC_MIPS_CALL_HI16:
14943 case BFD_RELOC_MIPS_CALL_LO16:
14944 case BFD_RELOC_MIPS16_GPREL:
14945 case BFD_RELOC_MIPS16_GOT16:
14946 case BFD_RELOC_MIPS16_CALL16:
14947 case BFD_RELOC_MIPS16_HI16:
14948 case BFD_RELOC_MIPS16_HI16_S:
14949 case BFD_RELOC_MIPS16_LO16:
14950 case BFD_RELOC_MIPS16_JMP:
14951 case BFD_RELOC_MICROMIPS_JMP:
14952 case BFD_RELOC_MICROMIPS_GOT_DISP:
14953 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14954 case BFD_RELOC_MICROMIPS_GOT_OFST:
14955 case BFD_RELOC_MICROMIPS_SUB:
14956 case BFD_RELOC_MICROMIPS_HIGHEST:
14957 case BFD_RELOC_MICROMIPS_HIGHER:
14958 case BFD_RELOC_MICROMIPS_SCN_DISP:
14959 case BFD_RELOC_MICROMIPS_JALR:
14960 case BFD_RELOC_MICROMIPS_HI16:
14961 case BFD_RELOC_MICROMIPS_HI16_S:
14962 case BFD_RELOC_MICROMIPS_LO16:
14963 case BFD_RELOC_MICROMIPS_GPREL16:
14964 case BFD_RELOC_MICROMIPS_LITERAL:
14965 case BFD_RELOC_MICROMIPS_CALL16:
14966 case BFD_RELOC_MICROMIPS_GOT16:
14967 case BFD_RELOC_MICROMIPS_GOT_HI16:
14968 case BFD_RELOC_MICROMIPS_GOT_LO16:
14969 case BFD_RELOC_MICROMIPS_CALL_HI16:
14970 case BFD_RELOC_MICROMIPS_CALL_LO16:
14971 case BFD_RELOC_MIPS_EH:
14976 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14978 insn = read_reloc_insn (buf, fixP->fx_r_type);
14979 if (mips16_reloc_p (fixP->fx_r_type))
14980 insn |= mips16_immed_extend (value, 16);
14982 insn |= (value & 0xffff);
14983 write_reloc_insn (buf, fixP->fx_r_type, insn);
14986 as_bad_where (fixP->fx_file, fixP->fx_line,
14987 _("unsupported constant in relocation"));
14992 /* This is handled like BFD_RELOC_32, but we output a sign
14993 extended value if we are only 32 bits. */
14996 if (8 <= sizeof (valueT))
14997 md_number_to_chars (buf, *valP, 8);
15002 if ((*valP & 0x80000000) != 0)
15006 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15007 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15012 case BFD_RELOC_RVA:
15014 case BFD_RELOC_32_PCREL:
15017 /* If we are deleting this reloc entry, we must fill in the
15018 value now. This can happen if we have a .word which is not
15019 resolved when it appears but is later defined. */
15021 md_number_to_chars (buf, *valP, fixP->fx_size);
15024 case BFD_RELOC_MIPS_21_PCREL_S2:
15025 case BFD_RELOC_MIPS_26_PCREL_S2:
15026 if ((*valP & 0x3) != 0)
15027 as_bad_where (fixP->fx_file, fixP->fx_line,
15028 _("branch to misaligned address (%lx)"), (long) *valP);
15030 gas_assert (!fixP->fx_done);
15033 case BFD_RELOC_MIPS_18_PCREL_S3:
15034 if ((S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
15035 as_bad_where (fixP->fx_file, fixP->fx_line,
15036 _("PC-relative access using misaligned symbol (%lx)"),
15037 (long) S_GET_VALUE (fixP->fx_addsy));
15038 if ((fixP->fx_offset & 0x7) != 0)
15039 as_bad_where (fixP->fx_file, fixP->fx_line,
15040 _("PC-relative access using misaligned offset (%lx)"),
15041 (long) fixP->fx_offset);
15043 gas_assert (!fixP->fx_done);
15046 case BFD_RELOC_MIPS_19_PCREL_S2:
15047 if ((*valP & 0x3) != 0)
15048 as_bad_where (fixP->fx_file, fixP->fx_line,
15049 _("PC-relative access to misaligned address (%lx)"),
15050 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset));
15052 gas_assert (!fixP->fx_done);
15055 case BFD_RELOC_HI16_S_PCREL:
15056 case BFD_RELOC_LO16_PCREL:
15057 gas_assert (!fixP->fx_done);
15060 case BFD_RELOC_16_PCREL_S2:
15061 if ((*valP & 0x3) != 0)
15062 as_bad_where (fixP->fx_file, fixP->fx_line,
15063 _("branch to misaligned address (%lx)"), (long) *valP);
15065 /* We need to save the bits in the instruction since fixup_segment()
15066 might be deleting the relocation entry (i.e., a branch within
15067 the current segment). */
15068 if (! fixP->fx_done)
15071 /* Update old instruction data. */
15072 insn = read_insn (buf);
15074 if (*valP + 0x20000 <= 0x3ffff)
15076 insn |= (*valP >> 2) & 0xffff;
15077 write_insn (buf, insn);
15079 else if (mips_pic == NO_PIC
15081 && fixP->fx_frag->fr_address >= text_section->vma
15082 && (fixP->fx_frag->fr_address
15083 < text_section->vma + bfd_get_section_size (text_section))
15084 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15085 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15086 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15088 /* The branch offset is too large. If this is an
15089 unconditional branch, and we are not generating PIC code,
15090 we can convert it to an absolute jump instruction. */
15091 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15092 insn = 0x0c000000; /* jal */
15094 insn = 0x08000000; /* j */
15095 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15097 fixP->fx_addsy = section_symbol (text_section);
15098 *valP += md_pcrel_from (fixP);
15099 write_insn (buf, insn);
15103 /* If we got here, we have branch-relaxation disabled,
15104 and there's nothing we can do to fix this instruction
15105 without turning it into a longer sequence. */
15106 as_bad_where (fixP->fx_file, fixP->fx_line,
15107 _("branch out of range"));
15111 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15112 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15113 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15114 /* We adjust the offset back to even. */
15115 if ((*valP & 0x1) != 0)
15118 if (! fixP->fx_done)
15121 /* Should never visit here, because we keep the relocation. */
15125 case BFD_RELOC_VTABLE_INHERIT:
15128 && !S_IS_DEFINED (fixP->fx_addsy)
15129 && !S_IS_WEAK (fixP->fx_addsy))
15130 S_SET_WEAK (fixP->fx_addsy);
15133 case BFD_RELOC_NONE:
15134 case BFD_RELOC_VTABLE_ENTRY:
15142 /* Remember value for tc_gen_reloc. */
15143 fixP->fx_addnumber = *valP;
15153 c = get_symbol_name (&name);
15154 p = (symbolS *) symbol_find_or_make (name);
15155 (void) restore_line_pointer (c);
15159 /* Align the current frag to a given power of two. If a particular
15160 fill byte should be used, FILL points to an integer that contains
15161 that byte, otherwise FILL is null.
15163 This function used to have the comment:
15165 The MIPS assembler also automatically adjusts any preceding label.
15167 The implementation therefore applied the adjustment to a maximum of
15168 one label. However, other label adjustments are applied to batches
15169 of labels, and adjusting just one caused problems when new labels
15170 were added for the sake of debugging or unwind information.
15171 We therefore adjust all preceding labels (given as LABELS) instead. */
15174 mips_align (int to, int *fill, struct insn_label_list *labels)
15176 mips_emit_delays ();
15177 mips_record_compressed_mode ();
15178 if (fill == NULL && subseg_text_p (now_seg))
15179 frag_align_code (to, 0);
15181 frag_align (to, fill ? *fill : 0, 0);
15182 record_alignment (now_seg, to);
15183 mips_move_labels (labels, FALSE);
15186 /* Align to a given power of two. .align 0 turns off the automatic
15187 alignment used by the data creating pseudo-ops. */
15190 s_align (int x ATTRIBUTE_UNUSED)
15192 int temp, fill_value, *fill_ptr;
15193 long max_alignment = 28;
15195 /* o Note that the assembler pulls down any immediately preceding label
15196 to the aligned address.
15197 o It's not documented but auto alignment is reinstated by
15198 a .align pseudo instruction.
15199 o Note also that after auto alignment is turned off the mips assembler
15200 issues an error on attempt to assemble an improperly aligned data item.
15203 temp = get_absolute_expression ();
15204 if (temp > max_alignment)
15205 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
15208 as_warn (_("alignment negative, 0 assumed"));
15211 if (*input_line_pointer == ',')
15213 ++input_line_pointer;
15214 fill_value = get_absolute_expression ();
15215 fill_ptr = &fill_value;
15221 segment_info_type *si = seg_info (now_seg);
15222 struct insn_label_list *l = si->label_list;
15223 /* Auto alignment should be switched on by next section change. */
15225 mips_align (temp, fill_ptr, l);
15232 demand_empty_rest_of_line ();
15236 s_change_sec (int sec)
15240 /* The ELF backend needs to know that we are changing sections, so
15241 that .previous works correctly. We could do something like check
15242 for an obj_section_change_hook macro, but that might be confusing
15243 as it would not be appropriate to use it in the section changing
15244 functions in read.c, since obj-elf.c intercepts those. FIXME:
15245 This should be cleaner, somehow. */
15246 obj_elf_section_change_hook ();
15248 mips_emit_delays ();
15259 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15260 demand_empty_rest_of_line ();
15264 seg = subseg_new (RDATA_SECTION_NAME,
15265 (subsegT) get_absolute_expression ());
15266 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15267 | SEC_READONLY | SEC_RELOC
15269 if (strncmp (TARGET_OS, "elf", 3) != 0)
15270 record_alignment (seg, 4);
15271 demand_empty_rest_of_line ();
15275 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15276 bfd_set_section_flags (stdoutput, seg,
15277 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15278 if (strncmp (TARGET_OS, "elf", 3) != 0)
15279 record_alignment (seg, 4);
15280 demand_empty_rest_of_line ();
15284 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15285 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15286 if (strncmp (TARGET_OS, "elf", 3) != 0)
15287 record_alignment (seg, 4);
15288 demand_empty_rest_of_line ();
15296 s_change_section (int ignore ATTRIBUTE_UNUSED)
15299 char *section_name;
15304 int section_entry_size;
15305 int section_alignment;
15307 saved_ilp = input_line_pointer;
15308 endc = get_symbol_name (§ion_name);
15309 c = (endc == '"' ? input_line_pointer[1] : endc);
15311 next_c = input_line_pointer [(endc == '"' ? 2 : 1)];
15313 /* Do we have .section Name<,"flags">? */
15314 if (c != ',' || (c == ',' && next_c == '"'))
15316 /* Just after name is now '\0'. */
15317 (void) restore_line_pointer (endc);
15318 input_line_pointer = saved_ilp;
15319 obj_elf_section (ignore);
15323 section_name = xstrdup (section_name);
15324 c = restore_line_pointer (endc);
15326 input_line_pointer++;
15328 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15330 section_type = get_absolute_expression ();
15334 if (*input_line_pointer++ == ',')
15335 section_flag = get_absolute_expression ();
15339 if (*input_line_pointer++ == ',')
15340 section_entry_size = get_absolute_expression ();
15342 section_entry_size = 0;
15344 if (*input_line_pointer++ == ',')
15345 section_alignment = get_absolute_expression ();
15347 section_alignment = 0;
15349 /* FIXME: really ignore? */
15350 (void) section_alignment;
15352 /* When using the generic form of .section (as implemented by obj-elf.c),
15353 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15354 traditionally had to fall back on the more common @progbits instead.
15356 There's nothing really harmful in this, since bfd will correct
15357 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15358 means that, for backwards compatibility, the special_section entries
15359 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15361 Even so, we shouldn't force users of the MIPS .section syntax to
15362 incorrectly label the sections as SHT_PROGBITS. The best compromise
15363 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15364 generic type-checking code. */
15365 if (section_type == SHT_MIPS_DWARF)
15366 section_type = SHT_PROGBITS;
15368 obj_elf_change_section (section_name, section_type, section_flag,
15369 section_entry_size, 0, 0, 0);
15371 if (now_seg->name != section_name)
15372 free (section_name);
15376 mips_enable_auto_align (void)
15382 s_cons (int log_size)
15384 segment_info_type *si = seg_info (now_seg);
15385 struct insn_label_list *l = si->label_list;
15387 mips_emit_delays ();
15388 if (log_size > 0 && auto_align)
15389 mips_align (log_size, 0, l);
15390 cons (1 << log_size);
15391 mips_clear_insn_labels ();
15395 s_float_cons (int type)
15397 segment_info_type *si = seg_info (now_seg);
15398 struct insn_label_list *l = si->label_list;
15400 mips_emit_delays ();
15405 mips_align (3, 0, l);
15407 mips_align (2, 0, l);
15411 mips_clear_insn_labels ();
15414 /* Handle .globl. We need to override it because on Irix 5 you are
15417 where foo is an undefined symbol, to mean that foo should be
15418 considered to be the address of a function. */
15421 s_mips_globl (int x ATTRIBUTE_UNUSED)
15430 c = get_symbol_name (&name);
15431 symbolP = symbol_find_or_make (name);
15432 S_SET_EXTERNAL (symbolP);
15434 *input_line_pointer = c;
15435 SKIP_WHITESPACE_AFTER_NAME ();
15437 /* On Irix 5, every global symbol that is not explicitly labelled as
15438 being a function is apparently labelled as being an object. */
15441 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15442 && (*input_line_pointer != ','))
15447 c = get_symbol_name (&secname);
15448 sec = bfd_get_section_by_name (stdoutput, secname);
15450 as_bad (_("%s: no such section"), secname);
15451 (void) restore_line_pointer (c);
15453 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15454 flag = BSF_FUNCTION;
15457 symbol_get_bfdsym (symbolP)->flags |= flag;
15459 c = *input_line_pointer;
15462 input_line_pointer++;
15463 SKIP_WHITESPACE ();
15464 if (is_end_of_line[(unsigned char) *input_line_pointer])
15470 demand_empty_rest_of_line ();
15474 s_option (int x ATTRIBUTE_UNUSED)
15479 c = get_symbol_name (&opt);
15483 /* FIXME: What does this mean? */
15485 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0')
15489 i = atoi (opt + 3);
15490 if (i != 0 && i != 2)
15491 as_bad (_(".option pic%d not supported"), i);
15492 else if (mips_pic == VXWORKS_PIC)
15493 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
15498 mips_pic = SVR4_PIC;
15499 mips_abicalls = TRUE;
15502 if (mips_pic == SVR4_PIC)
15504 if (g_switch_seen && g_switch_value != 0)
15505 as_warn (_("-G may not be used with SVR4 PIC code"));
15506 g_switch_value = 0;
15507 bfd_set_gp_size (stdoutput, 0);
15511 as_warn (_("unrecognized option \"%s\""), opt);
15513 (void) restore_line_pointer (c);
15514 demand_empty_rest_of_line ();
15517 /* This structure is used to hold a stack of .set values. */
15519 struct mips_option_stack
15521 struct mips_option_stack *next;
15522 struct mips_set_options options;
15525 static struct mips_option_stack *mips_opts_stack;
15527 /* Return status for .set/.module option handling. */
15529 enum code_option_type
15531 /* Unrecognized option. */
15532 OPTION_TYPE_BAD = -1,
15534 /* Ordinary option. */
15535 OPTION_TYPE_NORMAL,
15537 /* ISA changing option. */
15541 /* Handle common .set/.module options. Return status indicating option
15544 static enum code_option_type
15545 parse_code_option (char * name)
15547 bfd_boolean isa_set = FALSE;
15548 const struct mips_ase *ase;
15550 if (strncmp (name, "at=", 3) == 0)
15552 char *s = name + 3;
15554 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15555 as_bad (_("unrecognized register name `%s'"), s);
15557 else if (strcmp (name, "at") == 0)
15558 mips_opts.at = ATREG;
15559 else if (strcmp (name, "noat") == 0)
15560 mips_opts.at = ZERO;
15561 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15562 mips_opts.nomove = 0;
15563 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15564 mips_opts.nomove = 1;
15565 else if (strcmp (name, "bopt") == 0)
15566 mips_opts.nobopt = 0;
15567 else if (strcmp (name, "nobopt") == 0)
15568 mips_opts.nobopt = 1;
15569 else if (strcmp (name, "gp=32") == 0)
15571 else if (strcmp (name, "gp=64") == 0)
15573 else if (strcmp (name, "fp=32") == 0)
15575 else if (strcmp (name, "fp=xx") == 0)
15577 else if (strcmp (name, "fp=64") == 0)
15579 else if (strcmp (name, "softfloat") == 0)
15580 mips_opts.soft_float = 1;
15581 else if (strcmp (name, "hardfloat") == 0)
15582 mips_opts.soft_float = 0;
15583 else if (strcmp (name, "singlefloat") == 0)
15584 mips_opts.single_float = 1;
15585 else if (strcmp (name, "doublefloat") == 0)
15586 mips_opts.single_float = 0;
15587 else if (strcmp (name, "nooddspreg") == 0)
15588 mips_opts.oddspreg = 0;
15589 else if (strcmp (name, "oddspreg") == 0)
15590 mips_opts.oddspreg = 1;
15591 else if (strcmp (name, "mips16") == 0
15592 || strcmp (name, "MIPS-16") == 0)
15593 mips_opts.mips16 = 1;
15594 else if (strcmp (name, "nomips16") == 0
15595 || strcmp (name, "noMIPS-16") == 0)
15596 mips_opts.mips16 = 0;
15597 else if (strcmp (name, "micromips") == 0)
15598 mips_opts.micromips = 1;
15599 else if (strcmp (name, "nomicromips") == 0)
15600 mips_opts.micromips = 0;
15601 else if (name[0] == 'n'
15603 && (ase = mips_lookup_ase (name + 2)))
15604 mips_set_ase (ase, &mips_opts, FALSE);
15605 else if ((ase = mips_lookup_ase (name)))
15606 mips_set_ase (ase, &mips_opts, TRUE);
15607 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
15609 /* Permit the user to change the ISA and architecture on the fly.
15610 Needless to say, misuse can cause serious problems. */
15611 if (strncmp (name, "arch=", 5) == 0)
15613 const struct mips_cpu_info *p;
15615 p = mips_parse_cpu ("internal use", name + 5);
15617 as_bad (_("unknown architecture %s"), name + 5);
15620 mips_opts.arch = p->cpu;
15621 mips_opts.isa = p->isa;
15625 else if (strncmp (name, "mips", 4) == 0)
15627 const struct mips_cpu_info *p;
15629 p = mips_parse_cpu ("internal use", name);
15631 as_bad (_("unknown ISA level %s"), name + 4);
15634 mips_opts.arch = p->cpu;
15635 mips_opts.isa = p->isa;
15640 as_bad (_("unknown ISA or architecture %s"), name);
15642 else if (strcmp (name, "autoextend") == 0)
15643 mips_opts.noautoextend = 0;
15644 else if (strcmp (name, "noautoextend") == 0)
15645 mips_opts.noautoextend = 1;
15646 else if (strcmp (name, "insn32") == 0)
15647 mips_opts.insn32 = TRUE;
15648 else if (strcmp (name, "noinsn32") == 0)
15649 mips_opts.insn32 = FALSE;
15650 else if (strcmp (name, "sym32") == 0)
15651 mips_opts.sym32 = TRUE;
15652 else if (strcmp (name, "nosym32") == 0)
15653 mips_opts.sym32 = FALSE;
15655 return OPTION_TYPE_BAD;
15657 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
15660 /* Handle the .set pseudo-op. */
15663 s_mipsset (int x ATTRIBUTE_UNUSED)
15665 enum code_option_type type = OPTION_TYPE_NORMAL;
15666 char *name = input_line_pointer, ch;
15668 file_mips_check_options ();
15670 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15671 ++input_line_pointer;
15672 ch = *input_line_pointer;
15673 *input_line_pointer = '\0';
15675 if (strchr (name, ','))
15677 /* Generic ".set" directive; use the generic handler. */
15678 *input_line_pointer = ch;
15679 input_line_pointer = name;
15684 if (strcmp (name, "reorder") == 0)
15686 if (mips_opts.noreorder)
15689 else if (strcmp (name, "noreorder") == 0)
15691 if (!mips_opts.noreorder)
15692 start_noreorder ();
15694 else if (strcmp (name, "macro") == 0)
15695 mips_opts.warn_about_macros = 0;
15696 else if (strcmp (name, "nomacro") == 0)
15698 if (mips_opts.noreorder == 0)
15699 as_bad (_("`noreorder' must be set before `nomacro'"));
15700 mips_opts.warn_about_macros = 1;
15702 else if (strcmp (name, "gp=default") == 0)
15703 mips_opts.gp = file_mips_opts.gp;
15704 else if (strcmp (name, "fp=default") == 0)
15705 mips_opts.fp = file_mips_opts.fp;
15706 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15708 mips_opts.isa = file_mips_opts.isa;
15709 mips_opts.arch = file_mips_opts.arch;
15710 mips_opts.gp = file_mips_opts.gp;
15711 mips_opts.fp = file_mips_opts.fp;
15713 else if (strcmp (name, "push") == 0)
15715 struct mips_option_stack *s;
15717 s = XNEW (struct mips_option_stack);
15718 s->next = mips_opts_stack;
15719 s->options = mips_opts;
15720 mips_opts_stack = s;
15722 else if (strcmp (name, "pop") == 0)
15724 struct mips_option_stack *s;
15726 s = mips_opts_stack;
15728 as_bad (_(".set pop with no .set push"));
15731 /* If we're changing the reorder mode we need to handle
15732 delay slots correctly. */
15733 if (s->options.noreorder && ! mips_opts.noreorder)
15734 start_noreorder ();
15735 else if (! s->options.noreorder && mips_opts.noreorder)
15738 mips_opts = s->options;
15739 mips_opts_stack = s->next;
15745 type = parse_code_option (name);
15746 if (type == OPTION_TYPE_BAD)
15747 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
15750 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
15751 registers based on what is supported by the arch/cpu. */
15752 if (type == OPTION_TYPE_ISA)
15754 switch (mips_opts.isa)
15759 /* MIPS I cannot support FPXX. */
15761 /* fall-through. */
15768 if (mips_opts.fp != 0)
15784 if (mips_opts.fp != 0)
15786 if (mips_opts.arch == CPU_R5900)
15793 as_bad (_("unknown ISA level %s"), name + 4);
15798 mips_check_options (&mips_opts, FALSE);
15800 mips_check_isa_supports_ases ();
15801 *input_line_pointer = ch;
15802 demand_empty_rest_of_line ();
15805 /* Handle the .module pseudo-op. */
15808 s_module (int ignore ATTRIBUTE_UNUSED)
15810 char *name = input_line_pointer, ch;
15812 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15813 ++input_line_pointer;
15814 ch = *input_line_pointer;
15815 *input_line_pointer = '\0';
15817 if (!file_mips_opts_checked)
15819 if (parse_code_option (name) == OPTION_TYPE_BAD)
15820 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
15822 /* Update module level settings from mips_opts. */
15823 file_mips_opts = mips_opts;
15826 as_bad (_(".module is not permitted after generating code"));
15828 *input_line_pointer = ch;
15829 demand_empty_rest_of_line ();
15832 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15833 .option pic2. It means to generate SVR4 PIC calls. */
15836 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15838 mips_pic = SVR4_PIC;
15839 mips_abicalls = TRUE;
15841 if (g_switch_seen && g_switch_value != 0)
15842 as_warn (_("-G may not be used with SVR4 PIC code"));
15843 g_switch_value = 0;
15845 bfd_set_gp_size (stdoutput, 0);
15846 demand_empty_rest_of_line ();
15849 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15850 PIC code. It sets the $gp register for the function based on the
15851 function address, which is in the register named in the argument.
15852 This uses a relocation against _gp_disp, which is handled specially
15853 by the linker. The result is:
15854 lui $gp,%hi(_gp_disp)
15855 addiu $gp,$gp,%lo(_gp_disp)
15856 addu $gp,$gp,.cpload argument
15857 The .cpload argument is normally $25 == $t9.
15859 The -mno-shared option changes this to:
15860 lui $gp,%hi(__gnu_local_gp)
15861 addiu $gp,$gp,%lo(__gnu_local_gp)
15862 and the argument is ignored. This saves an instruction, but the
15863 resulting code is not position independent; it uses an absolute
15864 address for __gnu_local_gp. Thus code assembled with -mno-shared
15865 can go into an ordinary executable, but not into a shared library. */
15868 s_cpload (int ignore ATTRIBUTE_UNUSED)
15874 file_mips_check_options ();
15876 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15877 .cpload is ignored. */
15878 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15884 if (mips_opts.mips16)
15886 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15887 ignore_rest_of_line ();
15891 /* .cpload should be in a .set noreorder section. */
15892 if (mips_opts.noreorder == 0)
15893 as_warn (_(".cpload not in noreorder section"));
15895 reg = tc_get_register (0);
15897 /* If we need to produce a 64-bit address, we are better off using
15898 the default instruction sequence. */
15899 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15901 ex.X_op = O_symbol;
15902 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15904 ex.X_op_symbol = NULL;
15905 ex.X_add_number = 0;
15907 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15908 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15910 mips_mark_labels ();
15911 mips_assembling_insn = TRUE;
15914 macro_build_lui (&ex, mips_gp_register);
15915 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15916 mips_gp_register, BFD_RELOC_LO16);
15918 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15919 mips_gp_register, reg);
15922 mips_assembling_insn = FALSE;
15923 demand_empty_rest_of_line ();
15926 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15927 .cpsetup $reg1, offset|$reg2, label
15929 If offset is given, this results in:
15930 sd $gp, offset($sp)
15931 lui $gp, %hi(%neg(%gp_rel(label)))
15932 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15933 daddu $gp, $gp, $reg1
15935 If $reg2 is given, this results in:
15937 lui $gp, %hi(%neg(%gp_rel(label)))
15938 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15939 daddu $gp, $gp, $reg1
15940 $reg1 is normally $25 == $t9.
15942 The -mno-shared option replaces the last three instructions with
15944 addiu $gp,$gp,%lo(_gp) */
15947 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
15949 expressionS ex_off;
15950 expressionS ex_sym;
15953 file_mips_check_options ();
15955 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15956 We also need NewABI support. */
15957 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15963 if (mips_opts.mips16)
15965 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15966 ignore_rest_of_line ();
15970 reg1 = tc_get_register (0);
15971 SKIP_WHITESPACE ();
15972 if (*input_line_pointer != ',')
15974 as_bad (_("missing argument separator ',' for .cpsetup"));
15978 ++input_line_pointer;
15979 SKIP_WHITESPACE ();
15980 if (*input_line_pointer == '$')
15982 mips_cpreturn_register = tc_get_register (0);
15983 mips_cpreturn_offset = -1;
15987 mips_cpreturn_offset = get_absolute_expression ();
15988 mips_cpreturn_register = -1;
15990 SKIP_WHITESPACE ();
15991 if (*input_line_pointer != ',')
15993 as_bad (_("missing argument separator ',' for .cpsetup"));
15997 ++input_line_pointer;
15998 SKIP_WHITESPACE ();
15999 expression (&ex_sym);
16001 mips_mark_labels ();
16002 mips_assembling_insn = TRUE;
16005 if (mips_cpreturn_register == -1)
16007 ex_off.X_op = O_constant;
16008 ex_off.X_add_symbol = NULL;
16009 ex_off.X_op_symbol = NULL;
16010 ex_off.X_add_number = mips_cpreturn_offset;
16012 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16013 BFD_RELOC_LO16, SP);
16016 move_register (mips_cpreturn_register, mips_gp_register);
16018 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16020 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16021 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16024 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16025 mips_gp_register, -1, BFD_RELOC_GPREL16,
16026 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16028 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16029 mips_gp_register, reg1);
16035 ex.X_op = O_symbol;
16036 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16037 ex.X_op_symbol = NULL;
16038 ex.X_add_number = 0;
16040 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16041 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16043 macro_build_lui (&ex, mips_gp_register);
16044 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16045 mips_gp_register, BFD_RELOC_LO16);
16050 mips_assembling_insn = FALSE;
16051 demand_empty_rest_of_line ();
16055 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16057 file_mips_check_options ();
16059 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16060 .cplocal is ignored. */
16061 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16067 if (mips_opts.mips16)
16069 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16070 ignore_rest_of_line ();
16074 mips_gp_register = tc_get_register (0);
16075 demand_empty_rest_of_line ();
16078 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16079 offset from $sp. The offset is remembered, and after making a PIC
16080 call $gp is restored from that location. */
16083 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16087 file_mips_check_options ();
16089 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16090 .cprestore is ignored. */
16091 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16097 if (mips_opts.mips16)
16099 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16100 ignore_rest_of_line ();
16104 mips_cprestore_offset = get_absolute_expression ();
16105 mips_cprestore_valid = 1;
16107 ex.X_op = O_constant;
16108 ex.X_add_symbol = NULL;
16109 ex.X_op_symbol = NULL;
16110 ex.X_add_number = mips_cprestore_offset;
16112 mips_mark_labels ();
16113 mips_assembling_insn = TRUE;
16116 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16117 SP, HAVE_64BIT_ADDRESSES);
16120 mips_assembling_insn = FALSE;
16121 demand_empty_rest_of_line ();
16124 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16125 was given in the preceding .cpsetup, it results in:
16126 ld $gp, offset($sp)
16128 If a register $reg2 was given there, it results in:
16129 or $gp, $reg2, $0 */
16132 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16136 file_mips_check_options ();
16138 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16139 We also need NewABI support. */
16140 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16146 if (mips_opts.mips16)
16148 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16149 ignore_rest_of_line ();
16153 mips_mark_labels ();
16154 mips_assembling_insn = TRUE;
16157 if (mips_cpreturn_register == -1)
16159 ex.X_op = O_constant;
16160 ex.X_add_symbol = NULL;
16161 ex.X_op_symbol = NULL;
16162 ex.X_add_number = mips_cpreturn_offset;
16164 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16167 move_register (mips_gp_register, mips_cpreturn_register);
16171 mips_assembling_insn = FALSE;
16172 demand_empty_rest_of_line ();
16175 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16176 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16177 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16178 debug information or MIPS16 TLS. */
16181 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16182 bfd_reloc_code_real_type rtype)
16189 if (ex.X_op != O_symbol)
16191 as_bad (_("unsupported use of %s"), dirstr);
16192 ignore_rest_of_line ();
16195 p = frag_more (bytes);
16196 md_number_to_chars (p, 0, bytes);
16197 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16198 demand_empty_rest_of_line ();
16199 mips_clear_insn_labels ();
16202 /* Handle .dtprelword. */
16205 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16207 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16210 /* Handle .dtpreldword. */
16213 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16215 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16218 /* Handle .tprelword. */
16221 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16223 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16226 /* Handle .tpreldword. */
16229 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16231 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16234 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16235 code. It sets the offset to use in gp_rel relocations. */
16238 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16240 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16241 We also need NewABI support. */
16242 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16248 mips_gprel_offset = get_absolute_expression ();
16250 demand_empty_rest_of_line ();
16253 /* Handle the .gpword pseudo-op. This is used when generating PIC
16254 code. It generates a 32 bit GP relative reloc. */
16257 s_gpword (int ignore ATTRIBUTE_UNUSED)
16259 segment_info_type *si;
16260 struct insn_label_list *l;
16264 /* When not generating PIC code, this is treated as .word. */
16265 if (mips_pic != SVR4_PIC)
16271 si = seg_info (now_seg);
16272 l = si->label_list;
16273 mips_emit_delays ();
16275 mips_align (2, 0, l);
16278 mips_clear_insn_labels ();
16280 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16282 as_bad (_("unsupported use of .gpword"));
16283 ignore_rest_of_line ();
16287 md_number_to_chars (p, 0, 4);
16288 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16289 BFD_RELOC_GPREL32);
16291 demand_empty_rest_of_line ();
16295 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16297 segment_info_type *si;
16298 struct insn_label_list *l;
16302 /* When not generating PIC code, this is treated as .dword. */
16303 if (mips_pic != SVR4_PIC)
16309 si = seg_info (now_seg);
16310 l = si->label_list;
16311 mips_emit_delays ();
16313 mips_align (3, 0, l);
16316 mips_clear_insn_labels ();
16318 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16320 as_bad (_("unsupported use of .gpdword"));
16321 ignore_rest_of_line ();
16325 md_number_to_chars (p, 0, 8);
16326 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16327 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16329 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16330 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16331 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16333 demand_empty_rest_of_line ();
16336 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16337 tables. It generates a R_MIPS_EH reloc. */
16340 s_ehword (int ignore ATTRIBUTE_UNUSED)
16345 mips_emit_delays ();
16348 mips_clear_insn_labels ();
16350 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16352 as_bad (_("unsupported use of .ehword"));
16353 ignore_rest_of_line ();
16357 md_number_to_chars (p, 0, 4);
16358 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16359 BFD_RELOC_32_PCREL);
16361 demand_empty_rest_of_line ();
16364 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16365 tables in SVR4 PIC code. */
16368 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16372 file_mips_check_options ();
16374 /* This is ignored when not generating SVR4 PIC code. */
16375 if (mips_pic != SVR4_PIC)
16381 mips_mark_labels ();
16382 mips_assembling_insn = TRUE;
16384 /* Add $gp to the register named as an argument. */
16386 reg = tc_get_register (0);
16387 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16390 mips_assembling_insn = FALSE;
16391 demand_empty_rest_of_line ();
16394 /* Handle the .insn pseudo-op. This marks instruction labels in
16395 mips16/micromips mode. This permits the linker to handle them specially,
16396 such as generating jalx instructions when needed. We also make
16397 them odd for the duration of the assembly, in order to generate the
16398 right sort of code. We will make them even in the adjust_symtab
16399 routine, while leaving them marked. This is convenient for the
16400 debugger and the disassembler. The linker knows to make them odd
16404 s_insn (int ignore ATTRIBUTE_UNUSED)
16406 file_mips_check_options ();
16407 file_ase_mips16 |= mips_opts.mips16;
16408 file_ase_micromips |= mips_opts.micromips;
16410 mips_mark_labels ();
16412 demand_empty_rest_of_line ();
16415 /* Handle the .nan pseudo-op. */
16418 s_nan (int ignore ATTRIBUTE_UNUSED)
16420 static const char str_legacy[] = "legacy";
16421 static const char str_2008[] = "2008";
16424 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
16426 if (i == sizeof (str_2008) - 1
16427 && memcmp (input_line_pointer, str_2008, i) == 0)
16429 else if (i == sizeof (str_legacy) - 1
16430 && memcmp (input_line_pointer, str_legacy, i) == 0)
16432 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16435 as_bad (_("`%s' does not support legacy NaN"),
16436 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16439 as_bad (_("bad .nan directive"));
16441 input_line_pointer += i;
16442 demand_empty_rest_of_line ();
16445 /* Handle a .stab[snd] directive. Ideally these directives would be
16446 implemented in a transparent way, so that removing them would not
16447 have any effect on the generated instructions. However, s_stab
16448 internally changes the section, so in practice we need to decide
16449 now whether the preceding label marks compressed code. We do not
16450 support changing the compression mode of a label after a .stab*
16451 directive, such as in:
16457 so the current mode wins. */
16460 s_mips_stab (int type)
16462 mips_mark_labels ();
16466 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16469 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16476 c = get_symbol_name (&name);
16477 symbolP = symbol_find_or_make (name);
16478 S_SET_WEAK (symbolP);
16479 *input_line_pointer = c;
16481 SKIP_WHITESPACE_AFTER_NAME ();
16483 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16485 if (S_IS_DEFINED (symbolP))
16487 as_bad (_("ignoring attempt to redefine symbol %s"),
16488 S_GET_NAME (symbolP));
16489 ignore_rest_of_line ();
16493 if (*input_line_pointer == ',')
16495 ++input_line_pointer;
16496 SKIP_WHITESPACE ();
16500 if (exp.X_op != O_symbol)
16502 as_bad (_("bad .weakext directive"));
16503 ignore_rest_of_line ();
16506 symbol_set_value_expression (symbolP, &exp);
16509 demand_empty_rest_of_line ();
16512 /* Parse a register string into a number. Called from the ECOFF code
16513 to parse .frame. The argument is non-zero if this is the frame
16514 register, so that we can record it in mips_frame_reg. */
16517 tc_get_register (int frame)
16521 SKIP_WHITESPACE ();
16522 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16526 mips_frame_reg = reg != 0 ? reg : SP;
16527 mips_frame_reg_valid = 1;
16528 mips_cprestore_valid = 0;
16534 md_section_align (asection *seg, valueT addr)
16536 int align = bfd_get_section_alignment (stdoutput, seg);
16538 /* We don't need to align ELF sections to the full alignment.
16539 However, Irix 5 may prefer that we align them at least to a 16
16540 byte boundary. We don't bother to align the sections if we
16541 are targeted for an embedded system. */
16542 if (strncmp (TARGET_OS, "elf", 3) == 0)
16547 return ((addr + (1 << align) - 1) & -(1 << align));
16550 /* Utility routine, called from above as well. If called while the
16551 input file is still being read, it's only an approximation. (For
16552 example, a symbol may later become defined which appeared to be
16553 undefined earlier.) */
16556 nopic_need_relax (symbolS *sym, int before_relaxing)
16561 if (g_switch_value > 0)
16563 const char *symname;
16566 /* Find out whether this symbol can be referenced off the $gp
16567 register. It can be if it is smaller than the -G size or if
16568 it is in the .sdata or .sbss section. Certain symbols can
16569 not be referenced off the $gp, although it appears as though
16571 symname = S_GET_NAME (sym);
16572 if (symname != (const char *) NULL
16573 && (strcmp (symname, "eprol") == 0
16574 || strcmp (symname, "etext") == 0
16575 || strcmp (symname, "_gp") == 0
16576 || strcmp (symname, "edata") == 0
16577 || strcmp (symname, "_fbss") == 0
16578 || strcmp (symname, "_fdata") == 0
16579 || strcmp (symname, "_ftext") == 0
16580 || strcmp (symname, "end") == 0
16581 || strcmp (symname, "_gp_disp") == 0))
16583 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16585 #ifndef NO_ECOFF_DEBUGGING
16586 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16587 && (symbol_get_obj (sym)->ecoff_extern_size
16588 <= g_switch_value))
16590 /* We must defer this decision until after the whole
16591 file has been read, since there might be a .extern
16592 after the first use of this symbol. */
16593 || (before_relaxing
16594 #ifndef NO_ECOFF_DEBUGGING
16595 && symbol_get_obj (sym)->ecoff_extern_size == 0
16597 && S_GET_VALUE (sym) == 0)
16598 || (S_GET_VALUE (sym) != 0
16599 && S_GET_VALUE (sym) <= g_switch_value)))
16603 const char *segname;
16605 segname = segment_name (S_GET_SEGMENT (sym));
16606 gas_assert (strcmp (segname, ".lit8") != 0
16607 && strcmp (segname, ".lit4") != 0);
16608 change = (strcmp (segname, ".sdata") != 0
16609 && strcmp (segname, ".sbss") != 0
16610 && strncmp (segname, ".sdata.", 7) != 0
16611 && strncmp (segname, ".sbss.", 6) != 0
16612 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16613 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16618 /* We are not optimizing for the $gp register. */
16623 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16626 pic_need_relax (symbolS *sym, asection *segtype)
16630 /* Handle the case of a symbol equated to another symbol. */
16631 while (symbol_equated_reloc_p (sym))
16635 /* It's possible to get a loop here in a badly written program. */
16636 n = symbol_get_value_expression (sym)->X_add_symbol;
16642 if (symbol_section_p (sym))
16645 symsec = S_GET_SEGMENT (sym);
16647 /* This must duplicate the test in adjust_reloc_syms. */
16648 return (!bfd_is_und_section (symsec)
16649 && !bfd_is_abs_section (symsec)
16650 && !bfd_is_com_section (symsec)
16651 && !s_is_linkonce (sym, segtype)
16652 /* A global or weak symbol is treated as external. */
16653 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
16657 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16658 extended opcode. SEC is the section the frag is in. */
16661 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16664 const struct mips_int_operand *operand;
16669 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16671 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16674 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16675 operand = mips16_immed_operand (type, FALSE);
16677 sym_frag = symbol_get_frag (fragp->fr_symbol);
16678 val = S_GET_VALUE (fragp->fr_symbol);
16679 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16681 if (operand->root.type == OP_PCREL)
16683 const struct mips_pcrel_operand *pcrel_op;
16687 /* We won't have the section when we are called from
16688 mips_relax_frag. However, we will always have been called
16689 from md_estimate_size_before_relax first. If this is a
16690 branch to a different section, we mark it as such. If SEC is
16691 NULL, and the frag is not marked, then it must be a branch to
16692 the same section. */
16693 pcrel_op = (const struct mips_pcrel_operand *) operand;
16696 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16701 /* Must have been called from md_estimate_size_before_relax. */
16704 fragp->fr_subtype =
16705 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16707 /* FIXME: We should support this, and let the linker
16708 catch branches and loads that are out of range. */
16709 as_bad_where (fragp->fr_file, fragp->fr_line,
16710 _("unsupported PC relative reference to different section"));
16714 if (fragp != sym_frag && sym_frag->fr_address == 0)
16715 /* Assume non-extended on the first relaxation pass.
16716 The address we have calculated will be bogus if this is
16717 a forward branch to another frag, as the forward frag
16718 will have fr_address == 0. */
16722 /* In this case, we know for sure that the symbol fragment is in
16723 the same section. If the relax_marker of the symbol fragment
16724 differs from the relax_marker of this fragment, we have not
16725 yet adjusted the symbol fragment fr_address. We want to add
16726 in STRETCH in order to get a better estimate of the address.
16727 This particularly matters because of the shift bits. */
16729 && sym_frag->relax_marker != fragp->relax_marker)
16733 /* Adjust stretch for any alignment frag. Note that if have
16734 been expanding the earlier code, the symbol may be
16735 defined in what appears to be an earlier frag. FIXME:
16736 This doesn't handle the fr_subtype field, which specifies
16737 a maximum number of bytes to skip when doing an
16739 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16741 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16744 stretch = - ((- stretch)
16745 & ~ ((1 << (int) f->fr_offset) - 1));
16747 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16756 addr = fragp->fr_address + fragp->fr_fix;
16758 /* The base address rules are complicated. The base address of
16759 a branch is the following instruction. The base address of a
16760 PC relative load or add is the instruction itself, but if it
16761 is in a delay slot (in which case it can not be extended) use
16762 the address of the instruction whose delay slot it is in. */
16763 if (pcrel_op->include_isa_bit)
16767 /* If we are currently assuming that this frag should be
16768 extended, then, the current address is two bytes
16770 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16773 /* Ignore the low bit in the target, since it will be set
16774 for a text label. */
16777 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16779 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16782 val -= addr & -(1 << pcrel_op->align_log2);
16784 /* If any of the shifted bits are set, we must use an extended
16785 opcode. If the address depends on the size of this
16786 instruction, this can lead to a loop, so we arrange to always
16787 use an extended opcode. We only check this when we are in
16788 the main relaxation loop, when SEC is NULL. */
16789 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
16791 fragp->fr_subtype =
16792 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16796 /* If we are about to mark a frag as extended because the value
16797 is precisely the next value above maxtiny, then there is a
16798 chance of an infinite loop as in the following code:
16803 In this case when the la is extended, foo is 0x3fc bytes
16804 away, so the la can be shrunk, but then foo is 0x400 away, so
16805 the la must be extended. To avoid this loop, we mark the
16806 frag as extended if it was small, and is about to become
16807 extended with the next value above maxtiny. */
16808 maxtiny = mips_int_operand_max (operand);
16809 if (val == maxtiny + (1 << operand->shift)
16810 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16813 fragp->fr_subtype =
16814 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16818 else if (symsec != absolute_section && sec != NULL)
16819 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16821 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16824 /* Compute the length of a branch sequence, and adjust the
16825 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16826 worst-case length is computed, with UPDATE being used to indicate
16827 whether an unconditional (-1), branch-likely (+1) or regular (0)
16828 branch is to be computed. */
16830 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16832 bfd_boolean toofar;
16836 && S_IS_DEFINED (fragp->fr_symbol)
16837 && !S_IS_WEAK (fragp->fr_symbol)
16838 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16843 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16845 addr = fragp->fr_address + fragp->fr_fix + 4;
16849 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16852 /* If the symbol is not defined or it's in a different segment,
16853 we emit the long sequence. */
16856 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16858 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16859 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16860 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16861 RELAX_BRANCH_LINK (fragp->fr_subtype),
16867 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16870 if (mips_pic != NO_PIC)
16872 /* Additional space for PIC loading of target address. */
16874 if (mips_opts.isa == ISA_MIPS1)
16875 /* Additional space for $at-stabilizing nop. */
16879 /* If branch is conditional. */
16880 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16887 /* Compute the length of a branch sequence, and adjust the
16888 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16889 worst-case length is computed, with UPDATE being used to indicate
16890 whether an unconditional (-1), or regular (0) branch is to be
16894 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16896 bfd_boolean toofar;
16900 && S_IS_DEFINED (fragp->fr_symbol)
16901 && !S_IS_WEAK (fragp->fr_symbol)
16902 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16907 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16908 /* Ignore the low bit in the target, since it will be set
16909 for a text label. */
16910 if ((val & 1) != 0)
16913 addr = fragp->fr_address + fragp->fr_fix + 4;
16917 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16920 /* If the symbol is not defined or it's in a different segment,
16921 we emit the long sequence. */
16924 if (fragp && update
16925 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16926 fragp->fr_subtype = (toofar
16927 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16928 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16933 bfd_boolean compact_known = fragp != NULL;
16934 bfd_boolean compact = FALSE;
16935 bfd_boolean uncond;
16938 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16940 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16942 uncond = update < 0;
16944 /* If label is out of range, we turn branch <br>:
16946 <br> label # 4 bytes
16952 nop # 2 bytes if compact && !PIC
16955 if (mips_pic == NO_PIC && (!compact_known || compact))
16958 /* If assembling PIC code, we further turn:
16964 lw/ld at, %got(label)(gp) # 4 bytes
16965 d/addiu at, %lo(label) # 4 bytes
16968 if (mips_pic != NO_PIC)
16971 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16973 <brneg> 0f # 4 bytes
16974 nop # 2 bytes if !compact
16977 length += (compact_known && compact) ? 4 : 6;
16983 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16984 bit accordingly. */
16987 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16989 bfd_boolean toofar;
16992 && S_IS_DEFINED (fragp->fr_symbol)
16993 && !S_IS_WEAK (fragp->fr_symbol)
16994 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17000 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17001 /* Ignore the low bit in the target, since it will be set
17002 for a text label. */
17003 if ((val & 1) != 0)
17006 /* Assume this is a 2-byte branch. */
17007 addr = fragp->fr_address + fragp->fr_fix + 2;
17009 /* We try to avoid the infinite loop by not adding 2 more bytes for
17014 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17016 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17017 else if (type == 'E')
17018 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17023 /* If the symbol is not defined or it's in a different segment,
17024 we emit a normal 32-bit branch. */
17027 if (fragp && update
17028 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17030 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17031 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17039 /* Estimate the size of a frag before relaxing. Unless this is the
17040 mips16, we are not really relaxing here, and the final size is
17041 encoded in the subtype information. For the mips16, we have to
17042 decide whether we are using an extended opcode or not. */
17045 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17049 if (RELAX_BRANCH_P (fragp->fr_subtype))
17052 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17054 return fragp->fr_var;
17057 if (RELAX_MIPS16_P (fragp->fr_subtype))
17058 /* We don't want to modify the EXTENDED bit here; it might get us
17059 into infinite loops. We change it only in mips_relax_frag(). */
17060 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17062 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17066 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17067 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17068 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17069 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17070 fragp->fr_var = length;
17075 if (mips_pic == NO_PIC)
17076 change = nopic_need_relax (fragp->fr_symbol, 0);
17077 else if (mips_pic == SVR4_PIC)
17078 change = pic_need_relax (fragp->fr_symbol, segtype);
17079 else if (mips_pic == VXWORKS_PIC)
17080 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17087 fragp->fr_subtype |= RELAX_USE_SECOND;
17088 return -RELAX_FIRST (fragp->fr_subtype);
17091 return -RELAX_SECOND (fragp->fr_subtype);
17094 /* This is called to see whether a reloc against a defined symbol
17095 should be converted into a reloc against a section. */
17098 mips_fix_adjustable (fixS *fixp)
17100 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17101 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17104 if (fixp->fx_addsy == NULL)
17107 /* Allow relocs used for EH tables. */
17108 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17111 /* If symbol SYM is in a mergeable section, relocations of the form
17112 SYM + 0 can usually be made section-relative. The mergeable data
17113 is then identified by the section offset rather than by the symbol.
17115 However, if we're generating REL LO16 relocations, the offset is split
17116 between the LO16 and parterning high part relocation. The linker will
17117 need to recalculate the complete offset in order to correctly identify
17120 The linker has traditionally not looked for the parterning high part
17121 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17122 placed anywhere. Rather than break backwards compatibility by changing
17123 this, it seems better not to force the issue, and instead keep the
17124 original symbol. This will work with either linker behavior. */
17125 if ((lo16_reloc_p (fixp->fx_r_type)
17126 || reloc_needs_lo_p (fixp->fx_r_type))
17127 && HAVE_IN_PLACE_ADDENDS
17128 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17131 /* There is no place to store an in-place offset for JALR relocations.
17132 Likewise an in-range offset of limited PC-relative relocations may
17133 overflow the in-place relocatable field if recalculated against the
17134 start address of the symbol's containing section.
17136 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17137 section relative to allow linker relaxations to be performed later on. */
17138 if ((HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (mips_opts.isa))
17139 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17140 || jalr_reloc_p (fixp->fx_r_type)))
17143 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17144 to a floating-point stub. The same is true for non-R_MIPS16_26
17145 relocations against MIPS16 functions; in this case, the stub becomes
17146 the function's canonical address.
17148 Floating-point stubs are stored in unique .mips16.call.* or
17149 .mips16.fn.* sections. If a stub T for function F is in section S,
17150 the first relocation in section S must be against F; this is how the
17151 linker determines the target function. All relocations that might
17152 resolve to T must also be against F. We therefore have the following
17153 restrictions, which are given in an intentionally-redundant way:
17155 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17158 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17159 if that stub might be used.
17161 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17164 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17165 that stub might be used.
17167 There is a further restriction:
17169 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17170 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17171 targets with in-place addends; the relocation field cannot
17172 encode the low bit.
17174 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17175 against a MIPS16 symbol. We deal with (5) by by not reducing any
17176 such relocations on REL targets.
17178 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17179 relocation against some symbol R, no relocation against R may be
17180 reduced. (Note that this deals with (2) as well as (1) because
17181 relocations against global symbols will never be reduced on ELF
17182 targets.) This approach is a little simpler than trying to detect
17183 stub sections, and gives the "all or nothing" per-symbol consistency
17184 that we have for MIPS16 symbols. */
17185 if (fixp->fx_subsy == NULL
17186 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17187 || *symbol_get_tc (fixp->fx_addsy)
17188 || (HAVE_IN_PLACE_ADDENDS
17189 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17190 && jmp_reloc_p (fixp->fx_r_type))))
17196 /* Translate internal representation of relocation info to BFD target
17200 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17202 static arelent *retval[4];
17204 bfd_reloc_code_real_type code;
17206 memset (retval, 0, sizeof(retval));
17207 reloc = retval[0] = XCNEW (arelent);
17208 reloc->sym_ptr_ptr = XNEW (asymbol *);
17209 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17210 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17212 if (fixp->fx_pcrel)
17214 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17215 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17216 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17217 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17218 || fixp->fx_r_type == BFD_RELOC_32_PCREL
17219 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
17220 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
17221 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
17222 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
17223 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
17224 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
17226 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17227 Relocations want only the symbol offset. */
17228 reloc->addend = fixp->fx_addnumber + reloc->address;
17230 else if (HAVE_IN_PLACE_ADDENDS
17231 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
17232 && (read_compressed_insn (fixp->fx_frag->fr_literal
17233 + fixp->fx_where, 4) >> 26) == 0x3c)
17235 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17236 addend accordingly. */
17237 reloc->addend = fixp->fx_addnumber >> 1;
17240 reloc->addend = fixp->fx_addnumber;
17242 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17243 entry to be used in the relocation's section offset. */
17244 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17246 reloc->address = reloc->addend;
17250 code = fixp->fx_r_type;
17252 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17253 if (reloc->howto == NULL)
17255 as_bad_where (fixp->fx_file, fixp->fx_line,
17256 _("cannot represent %s relocation in this object file"
17258 bfd_get_reloc_code_name (code));
17265 /* Relax a machine dependent frag. This returns the amount by which
17266 the current size of the frag should change. */
17269 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17271 if (RELAX_BRANCH_P (fragp->fr_subtype))
17273 offsetT old_var = fragp->fr_var;
17275 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17277 return fragp->fr_var - old_var;
17280 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17282 offsetT old_var = fragp->fr_var;
17283 offsetT new_var = 4;
17285 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17286 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17287 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17288 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17289 fragp->fr_var = new_var;
17291 return new_var - old_var;
17294 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17297 if (mips16_extended_frag (fragp, NULL, stretch))
17299 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17301 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17306 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17308 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17315 /* Convert a machine dependent frag. */
17318 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17320 if (RELAX_BRANCH_P (fragp->fr_subtype))
17323 unsigned long insn;
17327 buf = fragp->fr_literal + fragp->fr_fix;
17328 insn = read_insn (buf);
17330 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17332 /* We generate a fixup instead of applying it right now
17333 because, if there are linker relaxations, we're going to
17334 need the relocations. */
17335 exp.X_op = O_symbol;
17336 exp.X_add_symbol = fragp->fr_symbol;
17337 exp.X_add_number = fragp->fr_offset;
17339 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17340 BFD_RELOC_16_PCREL_S2);
17341 fixp->fx_file = fragp->fr_file;
17342 fixp->fx_line = fragp->fr_line;
17344 buf = write_insn (buf, insn);
17350 as_warn_where (fragp->fr_file, fragp->fr_line,
17351 _("relaxed out-of-range branch into a jump"));
17353 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17356 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17358 /* Reverse the branch. */
17359 switch ((insn >> 28) & 0xf)
17362 if ((insn & 0xff000000) == 0x47000000
17363 || (insn & 0xff600000) == 0x45600000)
17365 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17366 reversed by tweaking bit 23. */
17367 insn ^= 0x00800000;
17371 /* bc[0-3][tf]l? instructions can have the condition
17372 reversed by tweaking a single TF bit, and their
17373 opcodes all have 0x4???????. */
17374 gas_assert ((insn & 0xf3e00000) == 0x41000000);
17375 insn ^= 0x00010000;
17380 /* bltz 0x04000000 bgez 0x04010000
17381 bltzal 0x04100000 bgezal 0x04110000 */
17382 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17383 insn ^= 0x00010000;
17387 /* beq 0x10000000 bne 0x14000000
17388 blez 0x18000000 bgtz 0x1c000000 */
17389 insn ^= 0x04000000;
17397 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17399 /* Clear the and-link bit. */
17400 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17402 /* bltzal 0x04100000 bgezal 0x04110000
17403 bltzall 0x04120000 bgezall 0x04130000 */
17404 insn &= ~0x00100000;
17407 /* Branch over the branch (if the branch was likely) or the
17408 full jump (not likely case). Compute the offset from the
17409 current instruction to branch to. */
17410 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17414 /* How many bytes in instructions we've already emitted? */
17415 i = buf - fragp->fr_literal - fragp->fr_fix;
17416 /* How many bytes in instructions from here to the end? */
17417 i = fragp->fr_var - i;
17419 /* Convert to instruction count. */
17421 /* Branch counts from the next instruction. */
17424 /* Branch over the jump. */
17425 buf = write_insn (buf, insn);
17428 buf = write_insn (buf, 0);
17430 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17432 /* beql $0, $0, 2f */
17434 /* Compute the PC offset from the current instruction to
17435 the end of the variable frag. */
17436 /* How many bytes in instructions we've already emitted? */
17437 i = buf - fragp->fr_literal - fragp->fr_fix;
17438 /* How many bytes in instructions from here to the end? */
17439 i = fragp->fr_var - i;
17440 /* Convert to instruction count. */
17442 /* Don't decrement i, because we want to branch over the
17446 buf = write_insn (buf, insn);
17447 buf = write_insn (buf, 0);
17451 if (mips_pic == NO_PIC)
17454 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17455 ? 0x0c000000 : 0x08000000);
17456 exp.X_op = O_symbol;
17457 exp.X_add_symbol = fragp->fr_symbol;
17458 exp.X_add_number = fragp->fr_offset;
17460 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17461 FALSE, BFD_RELOC_MIPS_JMP);
17462 fixp->fx_file = fragp->fr_file;
17463 fixp->fx_line = fragp->fr_line;
17465 buf = write_insn (buf, insn);
17469 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17471 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17472 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17473 insn |= at << OP_SH_RT;
17474 exp.X_op = O_symbol;
17475 exp.X_add_symbol = fragp->fr_symbol;
17476 exp.X_add_number = fragp->fr_offset;
17478 if (fragp->fr_offset)
17480 exp.X_add_symbol = make_expr_symbol (&exp);
17481 exp.X_add_number = 0;
17484 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17485 FALSE, BFD_RELOC_MIPS_GOT16);
17486 fixp->fx_file = fragp->fr_file;
17487 fixp->fx_line = fragp->fr_line;
17489 buf = write_insn (buf, insn);
17491 if (mips_opts.isa == ISA_MIPS1)
17493 buf = write_insn (buf, 0);
17495 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17496 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17497 insn |= at << OP_SH_RS | at << OP_SH_RT;
17499 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17500 FALSE, BFD_RELOC_LO16);
17501 fixp->fx_file = fragp->fr_file;
17502 fixp->fx_line = fragp->fr_line;
17504 buf = write_insn (buf, insn);
17507 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17511 insn |= at << OP_SH_RS;
17513 buf = write_insn (buf, insn);
17517 fragp->fr_fix += fragp->fr_var;
17518 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17522 /* Relax microMIPS branches. */
17523 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17525 char *buf = fragp->fr_literal + fragp->fr_fix;
17526 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17527 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17528 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17529 bfd_boolean short_ds;
17530 unsigned long insn;
17534 exp.X_op = O_symbol;
17535 exp.X_add_symbol = fragp->fr_symbol;
17536 exp.X_add_number = fragp->fr_offset;
17538 fragp->fr_fix += fragp->fr_var;
17540 /* Handle 16-bit branches that fit or are forced to fit. */
17541 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17543 /* We generate a fixup instead of applying it right now,
17544 because if there is linker relaxation, we're going to
17545 need the relocations. */
17547 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17548 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17549 else if (type == 'E')
17550 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
17551 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17555 fixp->fx_file = fragp->fr_file;
17556 fixp->fx_line = fragp->fr_line;
17558 /* These relocations can have an addend that won't fit in
17560 fixp->fx_no_overflow = 1;
17565 /* Handle 32-bit branches that fit or are forced to fit. */
17566 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17567 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17569 /* We generate a fixup instead of applying it right now,
17570 because if there is linker relaxation, we're going to
17571 need the relocations. */
17572 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17573 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17574 fixp->fx_file = fragp->fr_file;
17575 fixp->fx_line = fragp->fr_line;
17581 /* Relax 16-bit branches to 32-bit branches. */
17584 insn = read_compressed_insn (buf, 2);
17586 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17587 insn = 0x94000000; /* beq */
17588 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17590 unsigned long regno;
17592 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17593 regno = micromips_to_32_reg_d_map [regno];
17594 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17595 insn |= regno << MICROMIPSOP_SH_RS;
17600 /* Nothing else to do, just write it out. */
17601 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17602 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17604 buf = write_compressed_insn (buf, insn, 4);
17605 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17610 insn = read_compressed_insn (buf, 4);
17612 /* Relax 32-bit branches to a sequence of instructions. */
17613 as_warn_where (fragp->fr_file, fragp->fr_line,
17614 _("relaxed out-of-range branch into a jump"));
17616 /* Set the short-delay-slot bit. */
17617 short_ds = al && (insn & 0x02000000) != 0;
17619 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17623 /* Reverse the branch. */
17624 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17625 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17626 insn ^= 0x20000000;
17627 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17628 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17629 || (insn & 0xffe00000) == 0x40800000 /* blez */
17630 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17631 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17632 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17633 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17634 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17635 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17636 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17637 insn ^= 0x00400000;
17638 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17639 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17640 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17641 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17642 insn ^= 0x00200000;
17643 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
17645 || (insn & 0xff600000) == 0x81600000) /* BZ.V
17647 insn ^= 0x00800000;
17653 /* Clear the and-link and short-delay-slot bits. */
17654 gas_assert ((insn & 0xfda00000) == 0x40200000);
17656 /* bltzal 0x40200000 bgezal 0x40600000 */
17657 /* bltzals 0x42200000 bgezals 0x42600000 */
17658 insn &= ~0x02200000;
17661 /* Make a label at the end for use with the branch. */
17662 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17663 micromips_label_inc ();
17664 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17667 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17668 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17669 fixp->fx_file = fragp->fr_file;
17670 fixp->fx_line = fragp->fr_line;
17672 /* Branch over the jump. */
17673 buf = write_compressed_insn (buf, insn, 4);
17676 buf = write_compressed_insn (buf, 0x0c00, 2);
17679 if (mips_pic == NO_PIC)
17681 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17683 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17684 insn = al ? jal : 0xd4000000;
17686 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17687 BFD_RELOC_MICROMIPS_JMP);
17688 fixp->fx_file = fragp->fr_file;
17689 fixp->fx_line = fragp->fr_line;
17691 buf = write_compressed_insn (buf, insn, 4);
17694 buf = write_compressed_insn (buf, 0x0c00, 2);
17698 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17699 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17700 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17702 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17703 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17704 insn |= at << MICROMIPSOP_SH_RT;
17706 if (exp.X_add_number)
17708 exp.X_add_symbol = make_expr_symbol (&exp);
17709 exp.X_add_number = 0;
17712 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17713 BFD_RELOC_MICROMIPS_GOT16);
17714 fixp->fx_file = fragp->fr_file;
17715 fixp->fx_line = fragp->fr_line;
17717 buf = write_compressed_insn (buf, insn, 4);
17719 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17720 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17721 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17723 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17724 BFD_RELOC_MICROMIPS_LO16);
17725 fixp->fx_file = fragp->fr_file;
17726 fixp->fx_line = fragp->fr_line;
17728 buf = write_compressed_insn (buf, insn, 4);
17730 /* jr/jrc/jalr/jalrs $at */
17731 insn = al ? jalr : jr;
17732 insn |= at << MICROMIPSOP_SH_MJ;
17734 buf = write_compressed_insn (buf, insn, 2);
17737 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17741 if (RELAX_MIPS16_P (fragp->fr_subtype))
17744 const struct mips_int_operand *operand;
17747 unsigned int user_length, length;
17748 unsigned long insn;
17751 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17752 operand = mips16_immed_operand (type, FALSE);
17754 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17755 val = resolve_symbol_value (fragp->fr_symbol);
17756 if (operand->root.type == OP_PCREL)
17758 const struct mips_pcrel_operand *pcrel_op;
17761 pcrel_op = (const struct mips_pcrel_operand *) operand;
17762 addr = fragp->fr_address + fragp->fr_fix;
17764 /* The rules for the base address of a PC relative reloc are
17765 complicated; see mips16_extended_frag. */
17766 if (pcrel_op->include_isa_bit)
17771 /* Ignore the low bit in the target, since it will be
17772 set for a text label. */
17775 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17777 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17780 addr &= -(1 << pcrel_op->align_log2);
17783 /* Make sure the section winds up with the alignment we have
17785 if (operand->shift > 0)
17786 record_alignment (asec, operand->shift);
17790 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17791 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17792 as_warn_where (fragp->fr_file, fragp->fr_line,
17793 _("extended instruction in delay slot"));
17795 buf = fragp->fr_literal + fragp->fr_fix;
17797 insn = read_compressed_insn (buf, 2);
17799 insn |= MIPS16_EXTEND;
17801 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17803 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17808 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17809 BFD_RELOC_UNUSED, val, user_length, &insn);
17811 length = (ext ? 4 : 2);
17812 gas_assert (mips16_opcode_length (insn) == length);
17813 write_compressed_insn (buf, insn, length);
17814 fragp->fr_fix += length;
17818 relax_substateT subtype = fragp->fr_subtype;
17819 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17820 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17824 first = RELAX_FIRST (subtype);
17825 second = RELAX_SECOND (subtype);
17826 fixp = (fixS *) fragp->fr_opcode;
17828 /* If the delay slot chosen does not match the size of the instruction,
17829 then emit a warning. */
17830 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17831 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17836 s = subtype & (RELAX_DELAY_SLOT_16BIT
17837 | RELAX_DELAY_SLOT_SIZE_FIRST
17838 | RELAX_DELAY_SLOT_SIZE_SECOND);
17839 msg = macro_warning (s);
17841 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17845 /* Possibly emit a warning if we've chosen the longer option. */
17846 if (use_second == second_longer)
17852 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17853 msg = macro_warning (s);
17855 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17859 /* Go through all the fixups for the first sequence. Disable them
17860 (by marking them as done) if we're going to use the second
17861 sequence instead. */
17863 && fixp->fx_frag == fragp
17864 && fixp->fx_where < fragp->fr_fix - second)
17866 if (subtype & RELAX_USE_SECOND)
17868 fixp = fixp->fx_next;
17871 /* Go through the fixups for the second sequence. Disable them if
17872 we're going to use the first sequence, otherwise adjust their
17873 addresses to account for the relaxation. */
17874 while (fixp && fixp->fx_frag == fragp)
17876 if (subtype & RELAX_USE_SECOND)
17877 fixp->fx_where -= first;
17880 fixp = fixp->fx_next;
17883 /* Now modify the frag contents. */
17884 if (subtype & RELAX_USE_SECOND)
17888 start = fragp->fr_literal + fragp->fr_fix - first - second;
17889 memmove (start, start + first, second);
17890 fragp->fr_fix -= first;
17893 fragp->fr_fix -= second;
17897 /* This function is called after the relocs have been generated.
17898 We've been storing mips16 text labels as odd. Here we convert them
17899 back to even for the convenience of the debugger. */
17902 mips_frob_file_after_relocs (void)
17905 unsigned int count, i;
17907 syms = bfd_get_outsymbols (stdoutput);
17908 count = bfd_get_symcount (stdoutput);
17909 for (i = 0; i < count; i++, syms++)
17910 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17911 && ((*syms)->value & 1) != 0)
17913 (*syms)->value &= ~1;
17914 /* If the symbol has an odd size, it was probably computed
17915 incorrectly, so adjust that as well. */
17916 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17917 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17921 /* This function is called whenever a label is defined, including fake
17922 labels instantiated off the dot special symbol. It is used when
17923 handling branch delays; if a branch has a label, we assume we cannot
17924 move it. This also bumps the value of the symbol by 1 in compressed
17928 mips_record_label (symbolS *sym)
17930 segment_info_type *si = seg_info (now_seg);
17931 struct insn_label_list *l;
17933 if (free_insn_labels == NULL)
17934 l = XNEW (struct insn_label_list);
17937 l = free_insn_labels;
17938 free_insn_labels = l->next;
17942 l->next = si->label_list;
17943 si->label_list = l;
17946 /* This function is called as tc_frob_label() whenever a label is defined
17947 and adds a DWARF-2 record we only want for true labels. */
17950 mips_define_label (symbolS *sym)
17952 mips_record_label (sym);
17953 dwarf2_emit_label (sym);
17956 /* This function is called by tc_new_dot_label whenever a new dot symbol
17960 mips_add_dot_label (symbolS *sym)
17962 mips_record_label (sym);
17963 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17964 mips_compressed_mark_label (sym);
17967 /* Converting ASE flags from internal to .MIPS.abiflags values. */
17968 static unsigned int
17969 mips_convert_ase_flags (int ase)
17971 unsigned int ext_ases = 0;
17974 ext_ases |= AFL_ASE_DSP;
17975 if (ase & ASE_DSPR2)
17976 ext_ases |= AFL_ASE_DSPR2;
17977 if (ase & ASE_DSPR3)
17978 ext_ases |= AFL_ASE_DSPR3;
17980 ext_ases |= AFL_ASE_EVA;
17982 ext_ases |= AFL_ASE_MCU;
17983 if (ase & ASE_MDMX)
17984 ext_ases |= AFL_ASE_MDMX;
17985 if (ase & ASE_MIPS3D)
17986 ext_ases |= AFL_ASE_MIPS3D;
17988 ext_ases |= AFL_ASE_MT;
17989 if (ase & ASE_SMARTMIPS)
17990 ext_ases |= AFL_ASE_SMARTMIPS;
17991 if (ase & ASE_VIRT)
17992 ext_ases |= AFL_ASE_VIRT;
17994 ext_ases |= AFL_ASE_MSA;
17996 ext_ases |= AFL_ASE_XPA;
18000 /* Some special processing for a MIPS ELF file. */
18003 mips_elf_final_processing (void)
18006 Elf_Internal_ABIFlags_v0 flags;
18010 switch (file_mips_opts.isa)
18013 flags.isa_level = 1;
18016 flags.isa_level = 2;
18019 flags.isa_level = 3;
18022 flags.isa_level = 4;
18025 flags.isa_level = 5;
18028 flags.isa_level = 32;
18032 flags.isa_level = 32;
18036 flags.isa_level = 32;
18040 flags.isa_level = 32;
18044 flags.isa_level = 32;
18048 flags.isa_level = 64;
18052 flags.isa_level = 64;
18056 flags.isa_level = 64;
18060 flags.isa_level = 64;
18064 flags.isa_level = 64;
18069 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
18070 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
18071 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
18072 : (file_mips_opts.fp == 64) ? AFL_REG_64
18074 flags.cpr2_size = AFL_REG_NONE;
18075 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18076 Tag_GNU_MIPS_ABI_FP);
18077 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
18078 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
18079 if (file_ase_mips16)
18080 flags.ases |= AFL_ASE_MIPS16;
18081 if (file_ase_micromips)
18082 flags.ases |= AFL_ASE_MICROMIPS;
18084 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18085 || file_mips_opts.fp == 64)
18086 && file_mips_opts.oddspreg)
18087 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
18090 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
18091 ((Elf_External_ABIFlags_v0 *)
18094 /* Write out the register information. */
18095 if (mips_abi != N64_ABI)
18099 s.ri_gprmask = mips_gprmask;
18100 s.ri_cprmask[0] = mips_cprmask[0];
18101 s.ri_cprmask[1] = mips_cprmask[1];
18102 s.ri_cprmask[2] = mips_cprmask[2];
18103 s.ri_cprmask[3] = mips_cprmask[3];
18104 /* The gp_value field is set by the MIPS ELF backend. */
18106 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18107 ((Elf32_External_RegInfo *)
18108 mips_regmask_frag));
18112 Elf64_Internal_RegInfo s;
18114 s.ri_gprmask = mips_gprmask;
18116 s.ri_cprmask[0] = mips_cprmask[0];
18117 s.ri_cprmask[1] = mips_cprmask[1];
18118 s.ri_cprmask[2] = mips_cprmask[2];
18119 s.ri_cprmask[3] = mips_cprmask[3];
18120 /* The gp_value field is set by the MIPS ELF backend. */
18122 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18123 ((Elf64_External_RegInfo *)
18124 mips_regmask_frag));
18127 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18128 sort of BFD interface for this. */
18129 if (mips_any_noreorder)
18130 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18131 if (mips_pic != NO_PIC)
18133 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18134 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18137 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18139 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18140 defined at present; this might need to change in future. */
18141 if (file_ase_mips16)
18142 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18143 if (file_ase_micromips)
18144 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18145 if (file_mips_opts.ase & ASE_MDMX)
18146 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18148 /* Set the MIPS ELF ABI flags. */
18149 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18150 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18151 else if (mips_abi == O64_ABI)
18152 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18153 else if (mips_abi == EABI_ABI)
18155 if (file_mips_opts.gp == 64)
18156 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18158 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18160 else if (mips_abi == N32_ABI)
18161 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18163 /* Nothing to do for N64_ABI. */
18165 if (mips_32bitmode)
18166 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18168 if (mips_nan2008 == 1)
18169 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18171 /* 32 bit code with 64 bit FP registers. */
18172 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
18173 Tag_GNU_MIPS_ABI_FP);
18174 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
18175 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
18178 typedef struct proc {
18180 symbolS *func_end_sym;
18181 unsigned long reg_mask;
18182 unsigned long reg_offset;
18183 unsigned long fpreg_mask;
18184 unsigned long fpreg_offset;
18185 unsigned long frame_offset;
18186 unsigned long frame_reg;
18187 unsigned long pc_reg;
18190 static procS cur_proc;
18191 static procS *cur_proc_ptr;
18192 static int numprocs;
18194 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18195 as "2", and a normal nop as "0". */
18197 #define NOP_OPCODE_MIPS 0
18198 #define NOP_OPCODE_MIPS16 1
18199 #define NOP_OPCODE_MICROMIPS 2
18202 mips_nop_opcode (void)
18204 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18205 return NOP_OPCODE_MICROMIPS;
18206 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18207 return NOP_OPCODE_MIPS16;
18209 return NOP_OPCODE_MIPS;
18212 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18213 32-bit microMIPS NOPs here (if applicable). */
18216 mips_handle_align (fragS *fragp)
18220 int bytes, size, excess;
18223 if (fragp->fr_type != rs_align_code)
18226 p = fragp->fr_literal + fragp->fr_fix;
18228 switch (nop_opcode)
18230 case NOP_OPCODE_MICROMIPS:
18231 opcode = micromips_nop32_insn.insn_opcode;
18234 case NOP_OPCODE_MIPS16:
18235 opcode = mips16_nop_insn.insn_opcode;
18238 case NOP_OPCODE_MIPS:
18240 opcode = nop_insn.insn_opcode;
18245 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18246 excess = bytes % size;
18248 /* Handle the leading part if we're not inserting a whole number of
18249 instructions, and make it the end of the fixed part of the frag.
18250 Try to fit in a short microMIPS NOP if applicable and possible,
18251 and use zeroes otherwise. */
18252 gas_assert (excess < 4);
18253 fragp->fr_fix += excess;
18258 /* Fall through. */
18260 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18262 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18266 /* Fall through. */
18269 /* Fall through. */
18274 md_number_to_chars (p, opcode, size);
18275 fragp->fr_var = size;
18284 if (*input_line_pointer == '-')
18286 ++input_line_pointer;
18289 if (!ISDIGIT (*input_line_pointer))
18290 as_bad (_("expected simple number"));
18291 if (input_line_pointer[0] == '0')
18293 if (input_line_pointer[1] == 'x')
18295 input_line_pointer += 2;
18296 while (ISXDIGIT (*input_line_pointer))
18299 val |= hex_value (*input_line_pointer++);
18301 return negative ? -val : val;
18305 ++input_line_pointer;
18306 while (ISDIGIT (*input_line_pointer))
18309 val |= *input_line_pointer++ - '0';
18311 return negative ? -val : val;
18314 if (!ISDIGIT (*input_line_pointer))
18316 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18317 *input_line_pointer, *input_line_pointer);
18318 as_warn (_("invalid number"));
18321 while (ISDIGIT (*input_line_pointer))
18324 val += *input_line_pointer++ - '0';
18326 return negative ? -val : val;
18329 /* The .file directive; just like the usual .file directive, but there
18330 is an initial number which is the ECOFF file index. In the non-ECOFF
18331 case .file implies DWARF-2. */
18334 s_mips_file (int x ATTRIBUTE_UNUSED)
18336 static int first_file_directive = 0;
18338 if (ECOFF_DEBUGGING)
18347 filename = dwarf2_directive_file (0);
18349 /* Versions of GCC up to 3.1 start files with a ".file"
18350 directive even for stabs output. Make sure that this
18351 ".file" is handled. Note that you need a version of GCC
18352 after 3.1 in order to support DWARF-2 on MIPS. */
18353 if (filename != NULL && ! first_file_directive)
18355 (void) new_logical_line (filename, -1);
18356 s_app_file_string (filename, 0);
18358 first_file_directive = 1;
18362 /* The .loc directive, implying DWARF-2. */
18365 s_mips_loc (int x ATTRIBUTE_UNUSED)
18367 if (!ECOFF_DEBUGGING)
18368 dwarf2_directive_loc (0);
18371 /* The .end directive. */
18374 s_mips_end (int x ATTRIBUTE_UNUSED)
18378 /* Following functions need their own .frame and .cprestore directives. */
18379 mips_frame_reg_valid = 0;
18380 mips_cprestore_valid = 0;
18382 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18385 demand_empty_rest_of_line ();
18390 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18391 as_warn (_(".end not in text section"));
18395 as_warn (_(".end directive without a preceding .ent directive"));
18396 demand_empty_rest_of_line ();
18402 gas_assert (S_GET_NAME (p));
18403 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18404 as_warn (_(".end symbol does not match .ent symbol"));
18406 if (debug_type == DEBUG_STABS)
18407 stabs_generate_asm_endfunc (S_GET_NAME (p),
18411 as_warn (_(".end directive missing or unknown symbol"));
18413 /* Create an expression to calculate the size of the function. */
18414 if (p && cur_proc_ptr)
18416 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18417 expressionS *exp = XNEW (expressionS);
18420 exp->X_op = O_subtract;
18421 exp->X_add_symbol = symbol_temp_new_now ();
18422 exp->X_op_symbol = p;
18423 exp->X_add_number = 0;
18425 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18428 /* Generate a .pdr section. */
18429 if (!ECOFF_DEBUGGING && mips_flag_pdr)
18431 segT saved_seg = now_seg;
18432 subsegT saved_subseg = now_subseg;
18436 #ifdef md_flush_pending_output
18437 md_flush_pending_output ();
18440 gas_assert (pdr_seg);
18441 subseg_set (pdr_seg, 0);
18443 /* Write the symbol. */
18444 exp.X_op = O_symbol;
18445 exp.X_add_symbol = p;
18446 exp.X_add_number = 0;
18447 emit_expr (&exp, 4);
18449 fragp = frag_more (7 * 4);
18451 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18452 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18453 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18454 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18455 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18456 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18457 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18459 subseg_set (saved_seg, saved_subseg);
18462 cur_proc_ptr = NULL;
18465 /* The .aent and .ent directives. */
18468 s_mips_ent (int aent)
18472 symbolP = get_symbol ();
18473 if (*input_line_pointer == ',')
18474 ++input_line_pointer;
18475 SKIP_WHITESPACE ();
18476 if (ISDIGIT (*input_line_pointer)
18477 || *input_line_pointer == '-')
18480 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18481 as_warn (_(".ent or .aent not in text section"));
18483 if (!aent && cur_proc_ptr)
18484 as_warn (_("missing .end"));
18488 /* This function needs its own .frame and .cprestore directives. */
18489 mips_frame_reg_valid = 0;
18490 mips_cprestore_valid = 0;
18492 cur_proc_ptr = &cur_proc;
18493 memset (cur_proc_ptr, '\0', sizeof (procS));
18495 cur_proc_ptr->func_sym = symbolP;
18499 if (debug_type == DEBUG_STABS)
18500 stabs_generate_asm_func (S_GET_NAME (symbolP),
18501 S_GET_NAME (symbolP));
18504 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18506 demand_empty_rest_of_line ();
18509 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18510 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18511 s_mips_frame is used so that we can set the PDR information correctly.
18512 We can't use the ecoff routines because they make reference to the ecoff
18513 symbol table (in the mdebug section). */
18516 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18518 if (ECOFF_DEBUGGING)
18524 if (cur_proc_ptr == (procS *) NULL)
18526 as_warn (_(".frame outside of .ent"));
18527 demand_empty_rest_of_line ();
18531 cur_proc_ptr->frame_reg = tc_get_register (1);
18533 SKIP_WHITESPACE ();
18534 if (*input_line_pointer++ != ','
18535 || get_absolute_expression_and_terminator (&val) != ',')
18537 as_warn (_("bad .frame directive"));
18538 --input_line_pointer;
18539 demand_empty_rest_of_line ();
18543 cur_proc_ptr->frame_offset = val;
18544 cur_proc_ptr->pc_reg = tc_get_register (0);
18546 demand_empty_rest_of_line ();
18550 /* The .fmask and .mask directives. If the mdebug section is present
18551 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18552 embedded targets, s_mips_mask is used so that we can set the PDR
18553 information correctly. We can't use the ecoff routines because they
18554 make reference to the ecoff symbol table (in the mdebug section). */
18557 s_mips_mask (int reg_type)
18559 if (ECOFF_DEBUGGING)
18560 s_ignore (reg_type);
18565 if (cur_proc_ptr == (procS *) NULL)
18567 as_warn (_(".mask/.fmask outside of .ent"));
18568 demand_empty_rest_of_line ();
18572 if (get_absolute_expression_and_terminator (&mask) != ',')
18574 as_warn (_("bad .mask/.fmask directive"));
18575 --input_line_pointer;
18576 demand_empty_rest_of_line ();
18580 off = get_absolute_expression ();
18582 if (reg_type == 'F')
18584 cur_proc_ptr->fpreg_mask = mask;
18585 cur_proc_ptr->fpreg_offset = off;
18589 cur_proc_ptr->reg_mask = mask;
18590 cur_proc_ptr->reg_offset = off;
18593 demand_empty_rest_of_line ();
18597 /* A table describing all the processors gas knows about. Names are
18598 matched in the order listed.
18600 To ease comparison, please keep this table in the same order as
18601 gcc's mips_cpu_info_table[]. */
18602 static const struct mips_cpu_info mips_cpu_info_table[] =
18604 /* Entries for generic ISAs */
18605 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
18606 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
18607 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
18608 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
18609 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
18610 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
18611 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18612 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
18613 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
18614 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
18615 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
18616 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
18617 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
18618 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
18619 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
18622 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
18623 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
18624 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
18627 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
18630 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
18631 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
18632 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
18633 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
18634 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
18635 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
18636 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
18637 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
18638 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
18639 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
18640 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
18641 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
18642 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
18643 /* ST Microelectronics Loongson 2E and 2F cores */
18644 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
18645 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
18648 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
18649 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
18650 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
18651 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
18652 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
18653 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
18654 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
18655 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
18656 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
18657 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
18658 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
18659 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
18660 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
18661 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
18662 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
18665 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18666 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18667 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
18668 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18670 /* MIPS 32 Release 2 */
18671 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18672 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18673 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18674 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18675 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18676 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18677 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18678 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
18679 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18680 ISA_MIPS32R2, CPU_MIPS32R2 },
18681 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
18682 ISA_MIPS32R2, CPU_MIPS32R2 },
18683 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18684 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18685 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18686 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18687 /* Deprecated forms of the above. */
18688 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18689 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18690 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18691 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18692 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18693 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18694 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18695 /* Deprecated forms of the above. */
18696 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18697 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18698 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18699 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18700 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18701 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18702 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18703 /* Deprecated forms of the above. */
18704 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18705 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18706 /* 34Kn is a 34kc without DSP. */
18707 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18708 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18709 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18710 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18711 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18712 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18713 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18714 /* Deprecated forms of the above. */
18715 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18716 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
18717 /* 1004K cores are multiprocessor versions of the 34K. */
18718 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18719 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18720 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18721 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18722 /* interaptiv is the new name for 1004kf */
18723 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
18725 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18726 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
18727 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
18728 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
18731 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18732 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
18733 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18734 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18736 /* Broadcom SB-1 CPU core */
18737 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18738 /* Broadcom SB-1A CPU core */
18739 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
18741 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
18743 /* MIPS 64 Release 2 */
18745 /* Cavium Networks Octeon CPU core */
18746 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
18747 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
18748 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
18749 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
18752 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
18755 XLP is mostly like XLR, with the prominent exception that it is
18756 MIPS64R2 rather than MIPS64. */
18757 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
18760 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
18763 { NULL, 0, 0, 0, 0 }
18767 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18768 with a final "000" replaced by "k". Ignore case.
18770 Note: this function is shared between GCC and GAS. */
18773 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
18775 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18776 given++, canonical++;
18778 return ((*given == 0 && *canonical == 0)
18779 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18783 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18784 CPU name. We've traditionally allowed a lot of variation here.
18786 Note: this function is shared between GCC and GAS. */
18789 mips_matching_cpu_name_p (const char *canonical, const char *given)
18791 /* First see if the name matches exactly, or with a final "000"
18792 turned into "k". */
18793 if (mips_strict_matching_cpu_name_p (canonical, given))
18796 /* If not, try comparing based on numerical designation alone.
18797 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18798 if (TOLOWER (*given) == 'r')
18800 if (!ISDIGIT (*given))
18803 /* Skip over some well-known prefixes in the canonical name,
18804 hoping to find a number there too. */
18805 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18807 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18809 else if (TOLOWER (canonical[0]) == 'r')
18812 return mips_strict_matching_cpu_name_p (canonical, given);
18816 /* Parse an option that takes the name of a processor as its argument.
18817 OPTION is the name of the option and CPU_STRING is the argument.
18818 Return the corresponding processor enumeration if the CPU_STRING is
18819 recognized, otherwise report an error and return null.
18821 A similar function exists in GCC. */
18823 static const struct mips_cpu_info *
18824 mips_parse_cpu (const char *option, const char *cpu_string)
18826 const struct mips_cpu_info *p;
18828 /* 'from-abi' selects the most compatible architecture for the given
18829 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18830 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18831 version. Look first at the -mgp options, if given, otherwise base
18832 the choice on MIPS_DEFAULT_64BIT.
18834 Treat NO_ABI like the EABIs. One reason to do this is that the
18835 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18836 architecture. This code picks MIPS I for 'mips' and MIPS III for
18837 'mips64', just as we did in the days before 'from-abi'. */
18838 if (strcasecmp (cpu_string, "from-abi") == 0)
18840 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18841 return mips_cpu_info_from_isa (ISA_MIPS1);
18843 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18844 return mips_cpu_info_from_isa (ISA_MIPS3);
18846 if (file_mips_opts.gp >= 0)
18847 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
18848 ? ISA_MIPS1 : ISA_MIPS3);
18850 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18855 /* 'default' has traditionally been a no-op. Probably not very useful. */
18856 if (strcasecmp (cpu_string, "default") == 0)
18859 for (p = mips_cpu_info_table; p->name != 0; p++)
18860 if (mips_matching_cpu_name_p (p->name, cpu_string))
18863 as_bad (_("bad value (%s) for %s"), cpu_string, option);
18867 /* Return the canonical processor information for ISA (a member of the
18868 ISA_MIPS* enumeration). */
18870 static const struct mips_cpu_info *
18871 mips_cpu_info_from_isa (int isa)
18875 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18876 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18877 && isa == mips_cpu_info_table[i].isa)
18878 return (&mips_cpu_info_table[i]);
18883 static const struct mips_cpu_info *
18884 mips_cpu_info_from_arch (int arch)
18888 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18889 if (arch == mips_cpu_info_table[i].cpu)
18890 return (&mips_cpu_info_table[i]);
18896 show (FILE *stream, const char *string, int *col_p, int *first_p)
18900 fprintf (stream, "%24s", "");
18905 fprintf (stream, ", ");
18909 if (*col_p + strlen (string) > 72)
18911 fprintf (stream, "\n%24s", "");
18915 fprintf (stream, "%s", string);
18916 *col_p += strlen (string);
18922 md_show_usage (FILE *stream)
18927 fprintf (stream, _("\
18929 -EB generate big endian output\n\
18930 -EL generate little endian output\n\
18931 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18932 -G NUM allow referencing objects up to NUM bytes\n\
18933 implicitly with the gp register [default 8]\n"));
18934 fprintf (stream, _("\
18935 -mips1 generate MIPS ISA I instructions\n\
18936 -mips2 generate MIPS ISA II instructions\n\
18937 -mips3 generate MIPS ISA III instructions\n\
18938 -mips4 generate MIPS ISA IV instructions\n\
18939 -mips5 generate MIPS ISA V instructions\n\
18940 -mips32 generate MIPS32 ISA instructions\n\
18941 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18942 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18943 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18944 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
18945 -mips64 generate MIPS64 ISA instructions\n\
18946 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18947 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18948 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18949 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
18950 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18954 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18955 show (stream, mips_cpu_info_table[i].name, &column, &first);
18956 show (stream, "from-abi", &column, &first);
18957 fputc ('\n', stream);
18959 fprintf (stream, _("\
18960 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18961 -no-mCPU don't generate code specific to CPU.\n\
18962 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18966 show (stream, "3900", &column, &first);
18967 show (stream, "4010", &column, &first);
18968 show (stream, "4100", &column, &first);
18969 show (stream, "4650", &column, &first);
18970 fputc ('\n', stream);
18972 fprintf (stream, _("\
18973 -mips16 generate mips16 instructions\n\
18974 -no-mips16 do not generate mips16 instructions\n"));
18975 fprintf (stream, _("\
18976 -mmicromips generate microMIPS instructions\n\
18977 -mno-micromips do not generate microMIPS instructions\n"));
18978 fprintf (stream, _("\
18979 -msmartmips generate smartmips instructions\n\
18980 -mno-smartmips do not generate smartmips instructions\n"));
18981 fprintf (stream, _("\
18982 -mdsp generate DSP instructions\n\
18983 -mno-dsp do not generate DSP instructions\n"));
18984 fprintf (stream, _("\
18985 -mdspr2 generate DSP R2 instructions\n\
18986 -mno-dspr2 do not generate DSP R2 instructions\n"));
18987 fprintf (stream, _("\
18988 -mdspr3 generate DSP R3 instructions\n\
18989 -mno-dspr3 do not generate DSP R3 instructions\n"));
18990 fprintf (stream, _("\
18991 -mmt generate MT instructions\n\
18992 -mno-mt do not generate MT instructions\n"));
18993 fprintf (stream, _("\
18994 -mmcu generate MCU instructions\n\
18995 -mno-mcu do not generate MCU instructions\n"));
18996 fprintf (stream, _("\
18997 -mmsa generate MSA instructions\n\
18998 -mno-msa do not generate MSA instructions\n"));
18999 fprintf (stream, _("\
19000 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19001 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19002 fprintf (stream, _("\
19003 -mvirt generate Virtualization instructions\n\
19004 -mno-virt do not generate Virtualization instructions\n"));
19005 fprintf (stream, _("\
19006 -minsn32 only generate 32-bit microMIPS instructions\n\
19007 -mno-insn32 generate all microMIPS instructions\n"));
19008 fprintf (stream, _("\
19009 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19010 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19011 -mfix-vr4120 work around certain VR4120 errata\n\
19012 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19013 -mfix-24k insert a nop after ERET and DERET instructions\n\
19014 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19015 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19016 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19017 -msym32 assume all symbols have 32-bit values\n\
19018 -O0 remove unneeded NOPs, do not swap branches\n\
19019 -O remove unneeded NOPs and swap branches\n\
19020 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19021 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19022 fprintf (stream, _("\
19023 -mhard-float allow floating-point instructions\n\
19024 -msoft-float do not allow floating-point instructions\n\
19025 -msingle-float only allow 32-bit floating-point operations\n\
19026 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19027 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19028 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19029 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19033 show (stream, "legacy", &column, &first);
19034 show (stream, "2008", &column, &first);
19036 fputc ('\n', stream);
19038 fprintf (stream, _("\
19039 -KPIC, -call_shared generate SVR4 position independent code\n\
19040 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19041 -mvxworks-pic generate VxWorks position independent code\n\
19042 -non_shared do not generate code that can operate with DSOs\n\
19043 -xgot assume a 32 bit GOT\n\
19044 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19045 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19046 position dependent (non shared) code\n\
19047 -mabi=ABI create ABI conformant object file for:\n"));
19051 show (stream, "32", &column, &first);
19052 show (stream, "o64", &column, &first);
19053 show (stream, "n32", &column, &first);
19054 show (stream, "64", &column, &first);
19055 show (stream, "eabi", &column, &first);
19057 fputc ('\n', stream);
19059 fprintf (stream, _("\
19060 -32 create o32 ABI object file (default)\n\
19061 -n32 create n32 ABI object file\n\
19062 -64 create 64 ABI object file\n"));
19067 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19069 if (HAVE_64BIT_SYMBOLS)
19070 return dwarf2_format_64bit_irix;
19072 return dwarf2_format_32bit;
19077 mips_dwarf2_addr_size (void)
19079 if (HAVE_64BIT_OBJECTS)
19085 /* Standard calling conventions leave the CFA at SP on entry. */
19087 mips_cfi_frame_initial_instructions (void)
19089 cfi_add_CFA_def_cfa_register (SP);
19093 tc_mips_regname_to_dw2regnum (char *regname)
19095 unsigned int regnum = -1;
19098 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
19104 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19105 Given a symbolic attribute NAME, return the proper integer value.
19106 Returns -1 if the attribute is not known. */
19109 mips_convert_symbolic_attribute (const char *name)
19111 static const struct
19116 attribute_table[] =
19118 #define T(tag) {#tag, tag}
19119 T (Tag_GNU_MIPS_ABI_FP),
19120 T (Tag_GNU_MIPS_ABI_MSA),
19128 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
19129 if (streq (name, attribute_table[i].name))
19130 return attribute_table[i].tag;
19138 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
19140 mips_emit_delays ();
19142 as_warn (_("missing .end at end of assembly"));
19144 /* Just in case no code was emitted, do the consistency check. */
19145 file_mips_check_options ();
19147 /* Set a floating-point ABI if the user did not. */
19148 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
19150 /* Perform consistency checks on the floating-point ABI. */
19151 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19152 Tag_GNU_MIPS_ABI_FP);
19153 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
19154 check_fpabi (fpabi);
19158 /* Soft-float gets precedence over single-float, the two options should
19159 not be used together so this should not matter. */
19160 if (file_mips_opts.soft_float == 1)
19161 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
19162 /* Single-float gets precedence over all double_float cases. */
19163 else if (file_mips_opts.single_float == 1)
19164 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
19167 switch (file_mips_opts.fp)
19170 if (file_mips_opts.gp == 32)
19171 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19174 fpabi = Val_GNU_MIPS_ABI_FP_XX;
19177 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
19178 fpabi = Val_GNU_MIPS_ABI_FP_64A;
19179 else if (file_mips_opts.gp == 32)
19180 fpabi = Val_GNU_MIPS_ABI_FP_64;
19182 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
19187 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19188 Tag_GNU_MIPS_ABI_FP, fpabi);
19192 /* Returns the relocation type required for a particular CFI encoding. */
19194 bfd_reloc_code_real_type
19195 mips_cfi_reloc_for_encoding (int encoding)
19197 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
19198 return BFD_RELOC_32_PCREL;
19199 else return BFD_RELOC_NONE;