1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p : 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p : 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p : 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p : 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi = NO_ABI;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls = FALSE;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared = TRUE;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
242 int warn_about_macros;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
262 /* True if ".set sym32" is in effect. */
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float;
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float;
275 /* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
279 /* True if -mgp32 was passed. */
280 static int file_mips_gp32 = -1;
282 /* True if -mfp32 was passed. */
283 static int file_mips_fp32 = -1;
285 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286 static int file_mips_soft_float = 0;
288 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289 static int file_mips_single_float = 0;
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
295 /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG,
296 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
298 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask;
305 unsigned long mips_cprmask[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa = ISA_UNKNOWN;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mips3d;
337 /* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mdmx;
341 /* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_smartmips;
345 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
348 /* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350 static int file_ase_dsp;
352 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2)
355 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
357 /* True if -mdspr2 was passed or implied by arguments passed on the
358 command line (e.g., by -march). */
359 static int file_ase_dspr2;
361 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
362 || mips_opts.isa == ISA_MIPS64R2)
364 /* True if -mmt was passed or implied by arguments passed on the
365 command line (e.g., by -march). */
366 static int file_ase_mt;
368 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
369 || mips_opts.isa == ISA_MIPS64R2)
371 /* The argument of the -march= flag. The architecture we are assembling. */
372 static int file_mips_arch = CPU_UNKNOWN;
373 static const char *mips_arch_string;
375 /* The argument of the -mtune= flag. The architecture for which we
377 static int mips_tune = CPU_UNKNOWN;
378 static const char *mips_tune_string;
380 /* True when generating 32-bit code for a 64-bit processor. */
381 static int mips_32bitmode = 0;
383 /* True if the given ABI requires 32-bit registers. */
384 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
386 /* Likewise 64-bit registers. */
387 #define ABI_NEEDS_64BIT_REGS(ABI) \
389 || (ABI) == N64_ABI \
392 /* Return true if ISA supports 64 bit wide gp registers. */
393 #define ISA_HAS_64BIT_REGS(ISA) \
394 ((ISA) == ISA_MIPS3 \
395 || (ISA) == ISA_MIPS4 \
396 || (ISA) == ISA_MIPS5 \
397 || (ISA) == ISA_MIPS64 \
398 || (ISA) == ISA_MIPS64R2)
400 /* Return true if ISA supports 64 bit wide float registers. */
401 #define ISA_HAS_64BIT_FPRS(ISA) \
402 ((ISA) == ISA_MIPS3 \
403 || (ISA) == ISA_MIPS4 \
404 || (ISA) == ISA_MIPS5 \
405 || (ISA) == ISA_MIPS32R2 \
406 || (ISA) == ISA_MIPS64 \
407 || (ISA) == ISA_MIPS64R2)
409 /* Return true if ISA supports 64-bit right rotate (dror et al.)
411 #define ISA_HAS_DROR(ISA) \
412 ((ISA) == ISA_MIPS64R2 \
413 || (mips_opts.micromips \
414 && ISA_HAS_64BIT_REGS (ISA)) \
417 /* Return true if ISA supports 32-bit right rotate (ror et al.)
419 #define ISA_HAS_ROR(ISA) \
420 ((ISA) == ISA_MIPS32R2 \
421 || (ISA) == ISA_MIPS64R2 \
422 || mips_opts.ase_smartmips \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
428 ((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS64 \
431 || (ISA) == ISA_MIPS64R2)
433 /* Return true if ISA supports move to/from high part of a 64-bit
434 floating-point register. */
435 #define ISA_HAS_MXHC1(ISA) \
436 ((ISA) == ISA_MIPS32R2 \
437 || (ISA) == ISA_MIPS64R2)
439 #define HAVE_32BIT_GPRS \
440 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
442 #define HAVE_32BIT_FPRS \
443 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
445 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
446 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
448 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
450 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
452 /* True if relocations are stored in-place. */
453 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
455 /* The ABI-derived address size. */
456 #define HAVE_64BIT_ADDRESSES \
457 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
458 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
460 /* The size of symbolic constants (i.e., expressions of the form
461 "SYMBOL" or "SYMBOL + OFFSET"). */
462 #define HAVE_32BIT_SYMBOLS \
463 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
464 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
466 /* Addresses are loaded in different ways, depending on the address size
467 in use. The n32 ABI Documentation also mandates the use of additions
468 with overflow checking, but existing implementations don't follow it. */
469 #define ADDRESS_ADD_INSN \
470 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
472 #define ADDRESS_ADDI_INSN \
473 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
475 #define ADDRESS_LOAD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
478 #define ADDRESS_STORE_INSN \
479 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
481 /* Return true if the given CPU supports the MIPS16 ASE. */
482 #define CPU_HAS_MIPS16(cpu) \
483 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
484 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
486 /* Return true if the given CPU supports the microMIPS ASE. */
487 #define CPU_HAS_MICROMIPS(cpu) 0
489 /* True if CPU has a dror instruction. */
490 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
492 /* True if CPU has a ror instruction. */
493 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
495 /* True if CPU has seq/sne and seqi/snei instructions. */
496 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
498 /* True if CPU does not implement the all the coprocessor insns. For these
499 CPUs only those COP insns are accepted that are explicitly marked to be
500 available on the CPU. ISA membership for COP insns is ignored. */
501 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Returns true for a (non floating-point) coprocessor instruction. Reading
574 or writing the condition code is only possible on the coprocessors and
575 these insns are not marked with INSN_COP. Thus for these insns use the
576 condition-code flags. */
577 #define COP_INSN(PINFO) \
578 (PINFO != INSN_MACRO \
579 && ((PINFO) & (FP_S | FP_D)) == 0 \
580 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
582 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
583 has been selected. This implies, in particular, that addresses of text
584 labels have their LSB set. */
585 #define HAVE_CODE_COMPRESSION \
586 ((mips_opts.mips16 | mips_opts.micromips) != 0)
588 /* MIPS PIC level. */
590 enum mips_pic_level mips_pic;
592 /* 1 if we should generate 32 bit offsets from the $gp register in
593 SVR4_PIC mode. Currently has no meaning in other modes. */
594 static int mips_big_got = 0;
596 /* 1 if trap instructions should used for overflow rather than break
598 static int mips_trap = 0;
600 /* 1 if double width floating point constants should not be constructed
601 by assembling two single width halves into two single width floating
602 point registers which just happen to alias the double width destination
603 register. On some architectures this aliasing can be disabled by a bit
604 in the status register, and the setting of this bit cannot be determined
605 automatically at assemble time. */
606 static int mips_disable_float_construction;
608 /* Non-zero if any .set noreorder directives were used. */
610 static int mips_any_noreorder;
612 /* Non-zero if nops should be inserted when the register referenced in
613 an mfhi/mflo instruction is read in the next two instructions. */
614 static int mips_7000_hilo_fix;
616 /* The size of objects in the small data section. */
617 static unsigned int g_switch_value = 8;
618 /* Whether the -G option was used. */
619 static int g_switch_seen = 0;
624 /* If we can determine in advance that GP optimization won't be
625 possible, we can skip the relaxation stuff that tries to produce
626 GP-relative references. This makes delay slot optimization work
629 This function can only provide a guess, but it seems to work for
630 gcc output. It needs to guess right for gcc, otherwise gcc
631 will put what it thinks is a GP-relative instruction in a branch
634 I don't know if a fix is needed for the SVR4_PIC mode. I've only
635 fixed it for the non-PIC mode. KR 95/04/07 */
636 static int nopic_need_relax (symbolS *, int);
638 /* handle of the OPCODE hash table */
639 static struct hash_control *op_hash = NULL;
641 /* The opcode hash table we use for the mips16. */
642 static struct hash_control *mips16_op_hash = NULL;
644 /* The opcode hash table we use for the microMIPS ASE. */
645 static struct hash_control *micromips_op_hash = NULL;
647 /* This array holds the chars that always start a comment. If the
648 pre-processor is disabled, these aren't very useful */
649 const char comment_chars[] = "#";
651 /* This array holds the chars that only start a comment at the beginning of
652 a line. If the line seems to have the form '# 123 filename'
653 .line and .file directives will appear in the pre-processed output */
654 /* Note that input_file.c hand checks for '#' at the beginning of the
655 first line of the input file. This is because the compiler outputs
656 #NO_APP at the beginning of its output. */
657 /* Also note that C style comments are always supported. */
658 const char line_comment_chars[] = "#";
660 /* This array holds machine specific line separator characters. */
661 const char line_separator_chars[] = ";";
663 /* Chars that can be used to separate mant from exp in floating point nums */
664 const char EXP_CHARS[] = "eE";
666 /* Chars that mean this number is a floating point constant */
669 const char FLT_CHARS[] = "rRsSfFdDxXpP";
671 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
672 changed in read.c . Ideally it shouldn't have to know about it at all,
673 but nothing is ideal around here.
676 static char *insn_error;
678 static int auto_align = 1;
680 /* When outputting SVR4 PIC code, the assembler needs to know the
681 offset in the stack frame from which to restore the $gp register.
682 This is set by the .cprestore pseudo-op, and saved in this
684 static offsetT mips_cprestore_offset = -1;
686 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
687 more optimizations, it can use a register value instead of a memory-saved
688 offset and even an other register than $gp as global pointer. */
689 static offsetT mips_cpreturn_offset = -1;
690 static int mips_cpreturn_register = -1;
691 static int mips_gp_register = GP;
692 static int mips_gprel_offset = 0;
694 /* Whether mips_cprestore_offset has been set in the current function
695 (or whether it has already been warned about, if not). */
696 static int mips_cprestore_valid = 0;
698 /* This is the register which holds the stack frame, as set by the
699 .frame pseudo-op. This is needed to implement .cprestore. */
700 static int mips_frame_reg = SP;
702 /* Whether mips_frame_reg has been set in the current function
703 (or whether it has already been warned about, if not). */
704 static int mips_frame_reg_valid = 0;
706 /* To output NOP instructions correctly, we need to keep information
707 about the previous two instructions. */
709 /* Whether we are optimizing. The default value of 2 means to remove
710 unneeded NOPs and swap branch instructions when possible. A value
711 of 1 means to not swap branches. A value of 0 means to always
713 static int mips_optimize = 2;
715 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
716 equivalent to seeing no -g option at all. */
717 static int mips_debug = 0;
719 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
720 #define MAX_VR4130_NOPS 4
722 /* The maximum number of NOPs needed to fill delay slots. */
723 #define MAX_DELAY_NOPS 2
725 /* The maximum number of NOPs needed for any purpose. */
728 /* A list of previous instructions, with index 0 being the most recent.
729 We need to look back MAX_NOPS instructions when filling delay slots
730 or working around processor errata. We need to look back one
731 instruction further if we're thinking about using history[0] to
732 fill a branch delay slot. */
733 static struct mips_cl_insn history[1 + MAX_NOPS];
735 /* Nop instructions used by emit_nop. */
736 static struct mips_cl_insn nop_insn;
737 static struct mips_cl_insn mips16_nop_insn;
738 static struct mips_cl_insn micromips_nop16_insn;
739 static struct mips_cl_insn micromips_nop32_insn;
741 /* The appropriate nop for the current mode. */
742 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
743 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
745 /* The size of NOP_INSN in bytes. */
746 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
748 /* If this is set, it points to a frag holding nop instructions which
749 were inserted before the start of a noreorder section. If those
750 nops turn out to be unnecessary, the size of the frag can be
752 static fragS *prev_nop_frag;
754 /* The number of nop instructions we created in prev_nop_frag. */
755 static int prev_nop_frag_holds;
757 /* The number of nop instructions that we know we need in
759 static int prev_nop_frag_required;
761 /* The number of instructions we've seen since prev_nop_frag. */
762 static int prev_nop_frag_since;
764 /* For ECOFF and ELF, relocations against symbols are done in two
765 parts, with a HI relocation and a LO relocation. Each relocation
766 has only 16 bits of space to store an addend. This means that in
767 order for the linker to handle carries correctly, it must be able
768 to locate both the HI and the LO relocation. This means that the
769 relocations must appear in order in the relocation table.
771 In order to implement this, we keep track of each unmatched HI
772 relocation. We then sort them so that they immediately precede the
773 corresponding LO relocation. */
778 struct mips_hi_fixup *next;
781 /* The section this fixup is in. */
785 /* The list of unmatched HI relocs. */
787 static struct mips_hi_fixup *mips_hi_fixup_list;
789 /* The frag containing the last explicit relocation operator.
790 Null if explicit relocations have not been used. */
792 static fragS *prev_reloc_op_frag;
794 /* Map normal MIPS register numbers to mips16 register numbers. */
796 #define X ILLEGAL_REG
797 static const int mips32_to_16_reg_map[] =
799 X, X, 2, 3, 4, 5, 6, 7,
800 X, X, X, X, X, X, X, X,
801 0, 1, X, X, X, X, X, X,
802 X, X, X, X, X, X, X, X
806 /* Map mips16 register numbers to normal MIPS register numbers. */
808 static const unsigned int mips16_to_32_reg_map[] =
810 16, 17, 2, 3, 4, 5, 6, 7
813 /* Map normal MIPS register numbers to microMIPS register numbers. */
815 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
816 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
818 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
819 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
823 #define X ILLEGAL_REG
824 /* reg type h: 4, 5, 6. */
825 static const int mips32_to_micromips_reg_h_map[] =
827 X, X, X, X, 4, 5, 6, X,
828 X, X, X, X, X, X, X, X,
829 X, X, X, X, X, X, X, X,
830 X, X, X, X, X, X, X, X
833 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
834 static const int mips32_to_micromips_reg_m_map[] =
836 0, X, 2, 3, X, X, X, X,
837 X, X, X, X, X, X, X, X,
838 4, 1, 5, 6, 7, X, X, X,
839 X, X, X, X, X, X, X, X
842 /* reg type q: 0, 2-7. 17. */
843 static const int mips32_to_micromips_reg_q_map[] =
845 0, X, 2, 3, 4, 5, 6, 7,
846 X, X, X, X, X, X, X, X,
847 X, 1, X, X, X, X, X, X,
848 X, X, X, X, X, X, X, X
851 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
854 /* Map microMIPS register numbers to normal MIPS register numbers. */
856 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
857 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
858 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
859 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
860 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
863 /* The microMIPS registers with type h. */
864 static const unsigned int micromips_to_32_reg_h_map[] =
866 5, 5, 6, 4, 4, 4, 4, 4
869 /* The microMIPS registers with type i. */
870 static const unsigned int micromips_to_32_reg_i_map[] =
872 6, 7, 7, 21, 22, 5, 6, 7
875 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
877 /* The microMIPS registers with type m. */
878 static const unsigned int micromips_to_32_reg_m_map[] =
880 0, 17, 2, 3, 16, 18, 19, 20
883 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
885 /* The microMIPS registers with type q. */
886 static const unsigned int micromips_to_32_reg_q_map[] =
888 0, 17, 2, 3, 4, 5, 6, 7
891 /* microMIPS imm type B. */
892 static const int micromips_imm_b_map[] =
894 1, 4, 8, 12, 16, 20, 24, -1
897 /* microMIPS imm type C. */
898 static const int micromips_imm_c_map[] =
900 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
903 /* Classifies the kind of instructions we're interested in when
904 implementing -mfix-vr4120. */
905 enum fix_vr4120_class
913 NUM_FIX_VR4120_CLASSES
916 /* ...likewise -mfix-loongson2f-jump. */
917 static bfd_boolean mips_fix_loongson2f_jump;
919 /* ...likewise -mfix-loongson2f-nop. */
920 static bfd_boolean mips_fix_loongson2f_nop;
922 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
923 static bfd_boolean mips_fix_loongson2f;
925 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
926 there must be at least one other instruction between an instruction
927 of type X and an instruction of type Y. */
928 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
930 /* True if -mfix-vr4120 is in force. */
931 static int mips_fix_vr4120;
933 /* ...likewise -mfix-vr4130. */
934 static int mips_fix_vr4130;
936 /* ...likewise -mfix-24k. */
937 static int mips_fix_24k;
939 /* ...likewise -mfix-cn63xxp1 */
940 static bfd_boolean mips_fix_cn63xxp1;
942 /* We don't relax branches by default, since this causes us to expand
943 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
944 fail to compute the offset before expanding the macro to the most
945 efficient expansion. */
947 static int mips_relax_branch;
949 /* The expansion of many macros depends on the type of symbol that
950 they refer to. For example, when generating position-dependent code,
951 a macro that refers to a symbol may have two different expansions,
952 one which uses GP-relative addresses and one which uses absolute
953 addresses. When generating SVR4-style PIC, a macro may have
954 different expansions for local and global symbols.
956 We handle these situations by generating both sequences and putting
957 them in variant frags. In position-dependent code, the first sequence
958 will be the GP-relative one and the second sequence will be the
959 absolute one. In SVR4 PIC, the first sequence will be for global
960 symbols and the second will be for local symbols.
962 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
963 SECOND are the lengths of the two sequences in bytes. These fields
964 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
965 the subtype has the following flags:
968 Set if it has been decided that we should use the second
969 sequence instead of the first.
972 Set in the first variant frag if the macro's second implementation
973 is longer than its first. This refers to the macro as a whole,
974 not an individual relaxation.
977 Set in the first variant frag if the macro appeared in a .set nomacro
978 block and if one alternative requires a warning but the other does not.
981 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
984 RELAX_DELAY_SLOT_16BIT
985 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
988 RELAX_DELAY_SLOT_SIZE_FIRST
989 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
990 the macro is of the wrong size for the branch delay slot.
992 RELAX_DELAY_SLOT_SIZE_SECOND
993 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
994 the macro is of the wrong size for the branch delay slot.
996 The frag's "opcode" points to the first fixup for relaxable code.
998 Relaxable macros are generated using a sequence such as:
1000 relax_start (SYMBOL);
1001 ... generate first expansion ...
1003 ... generate second expansion ...
1006 The code and fixups for the unwanted alternative are discarded
1007 by md_convert_frag. */
1008 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1010 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1011 #define RELAX_SECOND(X) ((X) & 0xff)
1012 #define RELAX_USE_SECOND 0x10000
1013 #define RELAX_SECOND_LONGER 0x20000
1014 #define RELAX_NOMACRO 0x40000
1015 #define RELAX_DELAY_SLOT 0x80000
1016 #define RELAX_DELAY_SLOT_16BIT 0x100000
1017 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1018 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1020 /* Branch without likely bit. If label is out of range, we turn:
1022 beq reg1, reg2, label
1032 with the following opcode replacements:
1039 bltzal <-> bgezal (with jal label instead of j label)
1041 Even though keeping the delay slot instruction in the delay slot of
1042 the branch would be more efficient, it would be very tricky to do
1043 correctly, because we'd have to introduce a variable frag *after*
1044 the delay slot instruction, and expand that instead. Let's do it
1045 the easy way for now, even if the branch-not-taken case now costs
1046 one additional instruction. Out-of-range branches are not supposed
1047 to be common, anyway.
1049 Branch likely. If label is out of range, we turn:
1051 beql reg1, reg2, label
1052 delay slot (annulled if branch not taken)
1061 delay slot (executed only if branch taken)
1064 It would be possible to generate a shorter sequence by losing the
1065 likely bit, generating something like:
1070 delay slot (executed only if branch taken)
1082 bltzall -> bgezal (with jal label instead of j label)
1083 bgezall -> bltzal (ditto)
1086 but it's not clear that it would actually improve performance. */
1087 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1088 ((relax_substateT) \
1091 | ((toofar) ? 0x20 : 0) \
1092 | ((link) ? 0x40 : 0) \
1093 | ((likely) ? 0x80 : 0) \
1094 | ((uncond) ? 0x100 : 0)))
1095 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1096 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1097 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1098 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1099 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1100 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1102 /* For mips16 code, we use an entirely different form of relaxation.
1103 mips16 supports two versions of most instructions which take
1104 immediate values: a small one which takes some small value, and a
1105 larger one which takes a 16 bit value. Since branches also follow
1106 this pattern, relaxing these values is required.
1108 We can assemble both mips16 and normal MIPS code in a single
1109 object. Therefore, we need to support this type of relaxation at
1110 the same time that we support the relaxation described above. We
1111 use the high bit of the subtype field to distinguish these cases.
1113 The information we store for this type of relaxation is the
1114 argument code found in the opcode file for this relocation, whether
1115 the user explicitly requested a small or extended form, and whether
1116 the relocation is in a jump or jal delay slot. That tells us the
1117 size of the value, and how it should be stored. We also store
1118 whether the fragment is considered to be extended or not. We also
1119 store whether this is known to be a branch to a different section,
1120 whether we have tried to relax this frag yet, and whether we have
1121 ever extended a PC relative fragment because of a shift count. */
1122 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1125 | ((small) ? 0x100 : 0) \
1126 | ((ext) ? 0x200 : 0) \
1127 | ((dslot) ? 0x400 : 0) \
1128 | ((jal_dslot) ? 0x800 : 0))
1129 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1130 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1131 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1132 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1133 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1134 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1135 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1136 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1137 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1138 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1139 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1140 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1142 /* For microMIPS code, we use relaxation similar to one we use for
1143 MIPS16 code. Some instructions that take immediate values support
1144 two encodings: a small one which takes some small value, and a
1145 larger one which takes a 16 bit value. As some branches also follow
1146 this pattern, relaxing these values is required.
1148 We can assemble both microMIPS and normal MIPS code in a single
1149 object. Therefore, we need to support this type of relaxation at
1150 the same time that we support the relaxation described above. We
1151 use one of the high bits of the subtype field to distinguish these
1154 The information we store for this type of relaxation is the argument
1155 code found in the opcode file for this relocation, the register
1156 selected as the assembler temporary, whether the user explicitly
1157 requested a 16-bit form, whether the branch is unconditional, whether
1158 it is compact, whether it stores the link address implicitly in $ra,
1159 whether relaxation of out-of-range 32-bit branches to a sequence of
1160 instructions is enabled, and whether the displacement of a branch is
1161 too large to fit as an immediate argument of a 16-bit and a 32-bit
1162 branch, respectively. */
1163 #define RELAX_MICROMIPS_ENCODE(type, at, u16bit, uncond, compact, link, \
1164 relax32, toofar16, toofar32) \
1167 | (((at) & 0x1f) << 8) \
1168 | ((u16bit) ? 0x2000 : 0) \
1169 | ((uncond) ? 0x4000 : 0) \
1170 | ((compact) ? 0x8000 : 0) \
1171 | ((link) ? 0x10000 : 0) \
1172 | ((relax32) ? 0x20000 : 0) \
1173 | ((toofar16) ? 0x40000 : 0) \
1174 | ((toofar32) ? 0x80000 : 0))
1175 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1176 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1177 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1178 #define RELAX_MICROMIPS_U16BIT(i) (((i) & 0x2000) != 0)
1179 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0)
1180 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0)
1181 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0)
1182 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x20000) != 0)
1184 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x40000) != 0)
1185 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x40000)
1186 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x40000)
1187 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x80000) != 0)
1188 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x80000)
1189 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x80000)
1191 /* Is the given value a sign-extended 32-bit value? */
1192 #define IS_SEXT_32BIT_NUM(x) \
1193 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1194 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1196 /* Is the given value a sign-extended 16-bit value? */
1197 #define IS_SEXT_16BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0x7fff) == 0 \
1199 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1201 /* Is the given value a sign-extended 12-bit value? */
1202 #define IS_SEXT_12BIT_NUM(x) \
1203 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1205 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1206 #define IS_ZEXT_32BIT_NUM(x) \
1207 (((x) &~ (offsetT) 0xffffffff) == 0 \
1208 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1210 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1211 VALUE << SHIFT. VALUE is evaluated exactly once. */
1212 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1213 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1214 | (((VALUE) & (MASK)) << (SHIFT)))
1216 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1218 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1219 (((STRUCT) >> (SHIFT)) & (MASK))
1221 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1222 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1224 include/opcode/mips.h specifies operand fields using the macros
1225 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1226 with "MIPS16OP" instead of "OP". */
1227 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1230 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1231 OP_MASK_##FIELD, OP_SH_##FIELD); \
1233 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1234 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1236 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1237 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1238 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1240 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1241 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1243 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1244 : EXTRACT_BITS ((INSN).insn_opcode, \
1245 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1246 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1247 EXTRACT_BITS ((INSN).insn_opcode, \
1248 MIPS16OP_MASK_##FIELD, \
1249 MIPS16OP_SH_##FIELD)
1251 /* Whether or not we are emitting a branch-likely macro. */
1252 static bfd_boolean emit_branch_likely_macro = FALSE;
1254 /* Global variables used when generating relaxable macros. See the
1255 comment above RELAX_ENCODE for more details about how relaxation
1258 /* 0 if we're not emitting a relaxable macro.
1259 1 if we're emitting the first of the two relaxation alternatives.
1260 2 if we're emitting the second alternative. */
1263 /* The first relaxable fixup in the current frag. (In other words,
1264 the first fixup that refers to relaxable code.) */
1267 /* sizes[0] says how many bytes of the first alternative are stored in
1268 the current frag. Likewise sizes[1] for the second alternative. */
1269 unsigned int sizes[2];
1271 /* The symbol on which the choice of sequence depends. */
1275 /* Global variables used to decide whether a macro needs a warning. */
1277 /* True if the macro is in a branch delay slot. */
1278 bfd_boolean delay_slot_p;
1280 /* Set to the length in bytes required if the macro is in a delay slot
1281 that requires a specific length of instruction, otherwise zero. */
1282 unsigned int delay_slot_length;
1284 /* For relaxable macros, sizes[0] is the length of the first alternative
1285 in bytes and sizes[1] is the length of the second alternative.
1286 For non-relaxable macros, both elements give the length of the
1288 unsigned int sizes[2];
1290 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1291 instruction of the first alternative in bytes and first_insn_sizes[1]
1292 is the length of the first instruction of the second alternative.
1293 For non-relaxable macros, both elements give the length of the first
1294 instruction in bytes.
1296 Set to zero if we haven't yet seen the first instruction. */
1297 unsigned int first_insn_sizes[2];
1299 /* For relaxable macros, insns[0] is the number of instructions for the
1300 first alternative and insns[1] is the number of instructions for the
1303 For non-relaxable macros, both elements give the number of
1304 instructions for the macro. */
1305 unsigned int insns[2];
1307 /* The first variant frag for this macro. */
1309 } mips_macro_warning;
1311 /* Prototypes for static functions. */
1313 #define internalError() \
1314 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1316 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1318 static void append_insn
1319 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1320 bfd_boolean expansionp);
1321 static void mips_no_prev_insn (void);
1322 static void macro_build (expressionS *, const char *, const char *, ...);
1323 static void mips16_macro_build
1324 (expressionS *, const char *, const char *, va_list *);
1325 static void load_register (int, expressionS *, int);
1326 static void macro_start (void);
1327 static void macro_end (void);
1328 static void macro (struct mips_cl_insn * ip);
1329 static void mips16_macro (struct mips_cl_insn * ip);
1330 static void mips_ip (char *str, struct mips_cl_insn * ip);
1331 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1332 static void mips16_immed
1333 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1334 unsigned long *, bfd_boolean *, unsigned short *);
1335 static size_t my_getSmallExpression
1336 (expressionS *, bfd_reloc_code_real_type *, char *);
1337 static void my_getExpression (expressionS *, char *);
1338 static void s_align (int);
1339 static void s_change_sec (int);
1340 static void s_change_section (int);
1341 static void s_cons (int);
1342 static void s_float_cons (int);
1343 static void s_mips_globl (int);
1344 static void s_option (int);
1345 static void s_mipsset (int);
1346 static void s_abicalls (int);
1347 static void s_cpload (int);
1348 static void s_cpsetup (int);
1349 static void s_cplocal (int);
1350 static void s_cprestore (int);
1351 static void s_cpreturn (int);
1352 static void s_dtprelword (int);
1353 static void s_dtpreldword (int);
1354 static void s_gpvalue (int);
1355 static void s_gpword (int);
1356 static void s_gpdword (int);
1357 static void s_cpadd (int);
1358 static void s_insn (int);
1359 static void md_obj_begin (void);
1360 static void md_obj_end (void);
1361 static void s_mips_ent (int);
1362 static void s_mips_end (int);
1363 static void s_mips_frame (int);
1364 static void s_mips_mask (int reg_type);
1365 static void s_mips_stab (int);
1366 static void s_mips_weakext (int);
1367 static void s_mips_file (int);
1368 static void s_mips_loc (int);
1369 static bfd_boolean pic_need_relax (symbolS *, asection *);
1370 static int relaxed_branch_length (fragS *, asection *, int);
1371 static int validate_mips_insn (const struct mips_opcode *);
1372 static int validate_micromips_insn (const struct mips_opcode *);
1373 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1374 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1376 /* Table and functions used to map between CPU/ISA names, and
1377 ISA levels, and CPU numbers. */
1379 struct mips_cpu_info
1381 const char *name; /* CPU or ISA name. */
1382 int flags; /* ASEs available, or ISA flag. */
1383 int isa; /* ISA level. */
1384 int cpu; /* CPU number (default CPU if ISA). */
1387 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1388 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1389 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1390 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1391 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1392 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1393 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1395 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1396 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1397 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1401 The following pseudo-ops from the Kane and Heinrich MIPS book
1402 should be defined here, but are currently unsupported: .alias,
1403 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1405 The following pseudo-ops from the Kane and Heinrich MIPS book are
1406 specific to the type of debugging information being generated, and
1407 should be defined by the object format: .aent, .begin, .bend,
1408 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1411 The following pseudo-ops from the Kane and Heinrich MIPS book are
1412 not MIPS CPU specific, but are also not specific to the object file
1413 format. This file is probably the best place to define them, but
1414 they are not currently supported: .asm0, .endr, .lab, .struct. */
1416 static const pseudo_typeS mips_pseudo_table[] =
1418 /* MIPS specific pseudo-ops. */
1419 {"option", s_option, 0},
1420 {"set", s_mipsset, 0},
1421 {"rdata", s_change_sec, 'r'},
1422 {"sdata", s_change_sec, 's'},
1423 {"livereg", s_ignore, 0},
1424 {"abicalls", s_abicalls, 0},
1425 {"cpload", s_cpload, 0},
1426 {"cpsetup", s_cpsetup, 0},
1427 {"cplocal", s_cplocal, 0},
1428 {"cprestore", s_cprestore, 0},
1429 {"cpreturn", s_cpreturn, 0},
1430 {"dtprelword", s_dtprelword, 0},
1431 {"dtpreldword", s_dtpreldword, 0},
1432 {"gpvalue", s_gpvalue, 0},
1433 {"gpword", s_gpword, 0},
1434 {"gpdword", s_gpdword, 0},
1435 {"cpadd", s_cpadd, 0},
1436 {"insn", s_insn, 0},
1438 /* Relatively generic pseudo-ops that happen to be used on MIPS
1440 {"asciiz", stringer, 8 + 1},
1441 {"bss", s_change_sec, 'b'},
1443 {"half", s_cons, 1},
1444 {"dword", s_cons, 3},
1445 {"weakext", s_mips_weakext, 0},
1446 {"origin", s_org, 0},
1447 {"repeat", s_rept, 0},
1449 /* For MIPS this is non-standard, but we define it for consistency. */
1450 {"sbss", s_change_sec, 'B'},
1452 /* These pseudo-ops are defined in read.c, but must be overridden
1453 here for one reason or another. */
1454 {"align", s_align, 0},
1455 {"byte", s_cons, 0},
1456 {"data", s_change_sec, 'd'},
1457 {"double", s_float_cons, 'd'},
1458 {"float", s_float_cons, 'f'},
1459 {"globl", s_mips_globl, 0},
1460 {"global", s_mips_globl, 0},
1461 {"hword", s_cons, 1},
1463 {"long", s_cons, 2},
1464 {"octa", s_cons, 4},
1465 {"quad", s_cons, 3},
1466 {"section", s_change_section, 0},
1467 {"short", s_cons, 1},
1468 {"single", s_float_cons, 'f'},
1469 {"stabn", s_mips_stab, 'n'},
1470 {"text", s_change_sec, 't'},
1471 {"word", s_cons, 2},
1473 { "extern", ecoff_directive_extern, 0},
1478 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1480 /* These pseudo-ops should be defined by the object file format.
1481 However, a.out doesn't support them, so we have versions here. */
1482 {"aent", s_mips_ent, 1},
1483 {"bgnb", s_ignore, 0},
1484 {"end", s_mips_end, 0},
1485 {"endb", s_ignore, 0},
1486 {"ent", s_mips_ent, 0},
1487 {"file", s_mips_file, 0},
1488 {"fmask", s_mips_mask, 'F'},
1489 {"frame", s_mips_frame, 0},
1490 {"loc", s_mips_loc, 0},
1491 {"mask", s_mips_mask, 'R'},
1492 {"verstamp", s_ignore, 0},
1496 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1497 purpose of the `.dc.a' internal pseudo-op. */
1500 mips_address_bytes (void)
1502 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1505 extern void pop_insert (const pseudo_typeS *);
1508 mips_pop_insert (void)
1510 pop_insert (mips_pseudo_table);
1511 if (! ECOFF_DEBUGGING)
1512 pop_insert (mips_nonecoff_pseudo_table);
1515 /* Symbols labelling the current insn. */
1517 struct insn_label_list
1519 struct insn_label_list *next;
1523 static struct insn_label_list *free_insn_labels;
1524 #define label_list tc_segment_info_data.labels
1526 static void mips_clear_insn_labels (void);
1527 static void mips_mark_labels (void);
1528 static void mips_compressed_mark_labels (void);
1531 mips_clear_insn_labels (void)
1533 register struct insn_label_list **pl;
1534 segment_info_type *si;
1538 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1541 si = seg_info (now_seg);
1542 *pl = si->label_list;
1543 si->label_list = NULL;
1547 /* Mark instruction labels in MIPS16/microMIPS mode. */
1550 mips_mark_labels (void)
1552 if (HAVE_CODE_COMPRESSION)
1553 mips_compressed_mark_labels ();
1556 static char *expr_end;
1558 /* Expressions which appear in instructions. These are set by
1561 static expressionS imm_expr;
1562 static expressionS imm2_expr;
1563 static expressionS offset_expr;
1565 /* Relocs associated with imm_expr and offset_expr. */
1567 static bfd_reloc_code_real_type imm_reloc[3]
1568 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1569 static bfd_reloc_code_real_type offset_reloc[3]
1570 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1572 /* This is set to the resulting size of the instruction to be produced
1573 by mips16_ip if an explicit extension is used or by mips_ip if an
1574 explicit size is supplied. */
1576 static unsigned int forced_insn_length;
1579 /* The pdr segment for per procedure frame/regmask info. Not used for
1582 static segT pdr_seg;
1585 /* The default target format to use. */
1587 #if defined (TE_FreeBSD)
1588 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1589 #elif defined (TE_TMIPS)
1590 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1592 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1596 mips_target_format (void)
1598 switch (OUTPUT_FLAVOR)
1600 case bfd_target_ecoff_flavour:
1601 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1602 case bfd_target_coff_flavour:
1604 case bfd_target_elf_flavour:
1606 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1607 return (target_big_endian
1608 ? "elf32-bigmips-vxworks"
1609 : "elf32-littlemips-vxworks");
1611 return (target_big_endian
1612 ? (HAVE_64BIT_OBJECTS
1613 ? ELF_TARGET ("elf64-", "big")
1615 ? ELF_TARGET ("elf32-n", "big")
1616 : ELF_TARGET ("elf32-", "big")))
1617 : (HAVE_64BIT_OBJECTS
1618 ? ELF_TARGET ("elf64-", "little")
1620 ? ELF_TARGET ("elf32-n", "little")
1621 : ELF_TARGET ("elf32-", "little"))));
1628 /* Return the length of a microMIPS instruction in bytes. If bits of
1629 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1630 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1631 major opcode) will require further modifications to the opcode
1634 static inline unsigned int
1635 micromips_insn_length (const struct mips_opcode *mo)
1637 return (mo->mask >> 16) == 0 ? 2 : 4;
1640 /* Return the length of instruction INSN. */
1642 static inline unsigned int
1643 insn_length (const struct mips_cl_insn *insn)
1645 if (mips_opts.micromips)
1646 return micromips_insn_length (insn->insn_mo);
1647 else if (mips_opts.mips16)
1648 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1653 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1656 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1661 insn->use_extend = FALSE;
1663 insn->insn_opcode = mo->match;
1666 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1667 insn->fixp[i] = NULL;
1668 insn->fixed_p = (mips_opts.noreorder > 0);
1669 insn->noreorder_p = (mips_opts.noreorder > 0);
1670 insn->mips16_absolute_jump_p = 0;
1671 insn->complete_p = 0;
1674 /* Record the current MIPS16/microMIPS mode in now_seg. */
1677 mips_record_compressed_mode (void)
1679 segment_info_type *si;
1681 si = seg_info (now_seg);
1682 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1683 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1684 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1685 si->tc_segment_info_data.micromips = mips_opts.micromips;
1688 /* Install INSN at the location specified by its "frag" and "where" fields. */
1691 install_insn (const struct mips_cl_insn *insn)
1693 char *f = insn->frag->fr_literal + insn->where;
1694 if (!HAVE_CODE_COMPRESSION)
1695 md_number_to_chars (f, insn->insn_opcode, 4);
1696 else if (mips_opts.micromips)
1698 unsigned int length = insn_length (insn);
1700 md_number_to_chars (f, insn->insn_opcode, 2);
1701 else if (length == 4)
1703 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1705 md_number_to_chars (f, insn->insn_opcode & 0xffff, 2);
1708 as_bad (_("48-bit microMIPS instructions are not supported"));
1710 else if (insn->mips16_absolute_jump_p)
1712 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1713 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1717 if (insn->use_extend)
1719 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1722 md_number_to_chars (f, insn->insn_opcode, 2);
1724 mips_record_compressed_mode ();
1727 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1728 and install the opcode in the new location. */
1731 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1736 insn->where = where;
1737 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1738 if (insn->fixp[i] != NULL)
1740 insn->fixp[i]->fx_frag = frag;
1741 insn->fixp[i]->fx_where = where;
1743 install_insn (insn);
1746 /* Add INSN to the end of the output. */
1749 add_fixed_insn (struct mips_cl_insn *insn)
1751 char *f = frag_more (insn_length (insn));
1752 move_insn (insn, frag_now, f - frag_now->fr_literal);
1755 /* Start a variant frag and move INSN to the start of the variant part,
1756 marking it as fixed. The other arguments are as for frag_var. */
1759 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1760 relax_substateT subtype, symbolS *symbol, offsetT offset)
1762 frag_grow (max_chars);
1763 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1765 frag_var (rs_machine_dependent, max_chars, var,
1766 subtype, symbol, offset, NULL);
1769 /* Insert N copies of INSN into the history buffer, starting at
1770 position FIRST. Neither FIRST nor N need to be clipped. */
1773 insert_into_history (unsigned int first, unsigned int n,
1774 const struct mips_cl_insn *insn)
1776 if (mips_relax.sequence != 2)
1780 for (i = ARRAY_SIZE (history); i-- > first;)
1782 history[i] = history[i - n];
1788 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1789 the idea is to make it obvious at a glance that each errata is
1793 init_vr4120_conflicts (void)
1795 #define CONFLICT(FIRST, SECOND) \
1796 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1798 /* Errata 21 - [D]DIV[U] after [D]MACC */
1799 CONFLICT (MACC, DIV);
1800 CONFLICT (DMACC, DIV);
1802 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1803 CONFLICT (DMULT, DMULT);
1804 CONFLICT (DMULT, DMACC);
1805 CONFLICT (DMACC, DMULT);
1806 CONFLICT (DMACC, DMACC);
1808 /* Errata 24 - MT{LO,HI} after [D]MACC */
1809 CONFLICT (MACC, MTHILO);
1810 CONFLICT (DMACC, MTHILO);
1812 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1813 instruction is executed immediately after a MACC or DMACC
1814 instruction, the result of [either instruction] is incorrect." */
1815 CONFLICT (MACC, MULT);
1816 CONFLICT (MACC, DMULT);
1817 CONFLICT (DMACC, MULT);
1818 CONFLICT (DMACC, DMULT);
1820 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1821 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1822 DDIV or DDIVU instruction, the result of the MACC or
1823 DMACC instruction is incorrect.". */
1824 CONFLICT (DMULT, MACC);
1825 CONFLICT (DMULT, DMACC);
1826 CONFLICT (DIV, MACC);
1827 CONFLICT (DIV, DMACC);
1837 #define RTYPE_MASK 0x1ff00
1838 #define RTYPE_NUM 0x00100
1839 #define RTYPE_FPU 0x00200
1840 #define RTYPE_FCC 0x00400
1841 #define RTYPE_VEC 0x00800
1842 #define RTYPE_GP 0x01000
1843 #define RTYPE_CP0 0x02000
1844 #define RTYPE_PC 0x04000
1845 #define RTYPE_ACC 0x08000
1846 #define RTYPE_CCC 0x10000
1847 #define RNUM_MASK 0x000ff
1848 #define RWARN 0x80000
1850 #define GENERIC_REGISTER_NUMBERS \
1851 {"$0", RTYPE_NUM | 0}, \
1852 {"$1", RTYPE_NUM | 1}, \
1853 {"$2", RTYPE_NUM | 2}, \
1854 {"$3", RTYPE_NUM | 3}, \
1855 {"$4", RTYPE_NUM | 4}, \
1856 {"$5", RTYPE_NUM | 5}, \
1857 {"$6", RTYPE_NUM | 6}, \
1858 {"$7", RTYPE_NUM | 7}, \
1859 {"$8", RTYPE_NUM | 8}, \
1860 {"$9", RTYPE_NUM | 9}, \
1861 {"$10", RTYPE_NUM | 10}, \
1862 {"$11", RTYPE_NUM | 11}, \
1863 {"$12", RTYPE_NUM | 12}, \
1864 {"$13", RTYPE_NUM | 13}, \
1865 {"$14", RTYPE_NUM | 14}, \
1866 {"$15", RTYPE_NUM | 15}, \
1867 {"$16", RTYPE_NUM | 16}, \
1868 {"$17", RTYPE_NUM | 17}, \
1869 {"$18", RTYPE_NUM | 18}, \
1870 {"$19", RTYPE_NUM | 19}, \
1871 {"$20", RTYPE_NUM | 20}, \
1872 {"$21", RTYPE_NUM | 21}, \
1873 {"$22", RTYPE_NUM | 22}, \
1874 {"$23", RTYPE_NUM | 23}, \
1875 {"$24", RTYPE_NUM | 24}, \
1876 {"$25", RTYPE_NUM | 25}, \
1877 {"$26", RTYPE_NUM | 26}, \
1878 {"$27", RTYPE_NUM | 27}, \
1879 {"$28", RTYPE_NUM | 28}, \
1880 {"$29", RTYPE_NUM | 29}, \
1881 {"$30", RTYPE_NUM | 30}, \
1882 {"$31", RTYPE_NUM | 31}
1884 #define FPU_REGISTER_NAMES \
1885 {"$f0", RTYPE_FPU | 0}, \
1886 {"$f1", RTYPE_FPU | 1}, \
1887 {"$f2", RTYPE_FPU | 2}, \
1888 {"$f3", RTYPE_FPU | 3}, \
1889 {"$f4", RTYPE_FPU | 4}, \
1890 {"$f5", RTYPE_FPU | 5}, \
1891 {"$f6", RTYPE_FPU | 6}, \
1892 {"$f7", RTYPE_FPU | 7}, \
1893 {"$f8", RTYPE_FPU | 8}, \
1894 {"$f9", RTYPE_FPU | 9}, \
1895 {"$f10", RTYPE_FPU | 10}, \
1896 {"$f11", RTYPE_FPU | 11}, \
1897 {"$f12", RTYPE_FPU | 12}, \
1898 {"$f13", RTYPE_FPU | 13}, \
1899 {"$f14", RTYPE_FPU | 14}, \
1900 {"$f15", RTYPE_FPU | 15}, \
1901 {"$f16", RTYPE_FPU | 16}, \
1902 {"$f17", RTYPE_FPU | 17}, \
1903 {"$f18", RTYPE_FPU | 18}, \
1904 {"$f19", RTYPE_FPU | 19}, \
1905 {"$f20", RTYPE_FPU | 20}, \
1906 {"$f21", RTYPE_FPU | 21}, \
1907 {"$f22", RTYPE_FPU | 22}, \
1908 {"$f23", RTYPE_FPU | 23}, \
1909 {"$f24", RTYPE_FPU | 24}, \
1910 {"$f25", RTYPE_FPU | 25}, \
1911 {"$f26", RTYPE_FPU | 26}, \
1912 {"$f27", RTYPE_FPU | 27}, \
1913 {"$f28", RTYPE_FPU | 28}, \
1914 {"$f29", RTYPE_FPU | 29}, \
1915 {"$f30", RTYPE_FPU | 30}, \
1916 {"$f31", RTYPE_FPU | 31}
1918 #define FPU_CONDITION_CODE_NAMES \
1919 {"$fcc0", RTYPE_FCC | 0}, \
1920 {"$fcc1", RTYPE_FCC | 1}, \
1921 {"$fcc2", RTYPE_FCC | 2}, \
1922 {"$fcc3", RTYPE_FCC | 3}, \
1923 {"$fcc4", RTYPE_FCC | 4}, \
1924 {"$fcc5", RTYPE_FCC | 5}, \
1925 {"$fcc6", RTYPE_FCC | 6}, \
1926 {"$fcc7", RTYPE_FCC | 7}
1928 #define COPROC_CONDITION_CODE_NAMES \
1929 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1930 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1931 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1932 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1933 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1934 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1935 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1936 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1938 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1939 {"$a4", RTYPE_GP | 8}, \
1940 {"$a5", RTYPE_GP | 9}, \
1941 {"$a6", RTYPE_GP | 10}, \
1942 {"$a7", RTYPE_GP | 11}, \
1943 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1944 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1945 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1946 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1947 {"$t0", RTYPE_GP | 12}, \
1948 {"$t1", RTYPE_GP | 13}, \
1949 {"$t2", RTYPE_GP | 14}, \
1950 {"$t3", RTYPE_GP | 15}
1952 #define O32_SYMBOLIC_REGISTER_NAMES \
1953 {"$t0", RTYPE_GP | 8}, \
1954 {"$t1", RTYPE_GP | 9}, \
1955 {"$t2", RTYPE_GP | 10}, \
1956 {"$t3", RTYPE_GP | 11}, \
1957 {"$t4", RTYPE_GP | 12}, \
1958 {"$t5", RTYPE_GP | 13}, \
1959 {"$t6", RTYPE_GP | 14}, \
1960 {"$t7", RTYPE_GP | 15}, \
1961 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1962 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1963 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1964 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1966 /* Remaining symbolic register names */
1967 #define SYMBOLIC_REGISTER_NAMES \
1968 {"$zero", RTYPE_GP | 0}, \
1969 {"$at", RTYPE_GP | 1}, \
1970 {"$AT", RTYPE_GP | 1}, \
1971 {"$v0", RTYPE_GP | 2}, \
1972 {"$v1", RTYPE_GP | 3}, \
1973 {"$a0", RTYPE_GP | 4}, \
1974 {"$a1", RTYPE_GP | 5}, \
1975 {"$a2", RTYPE_GP | 6}, \
1976 {"$a3", RTYPE_GP | 7}, \
1977 {"$s0", RTYPE_GP | 16}, \
1978 {"$s1", RTYPE_GP | 17}, \
1979 {"$s2", RTYPE_GP | 18}, \
1980 {"$s3", RTYPE_GP | 19}, \
1981 {"$s4", RTYPE_GP | 20}, \
1982 {"$s5", RTYPE_GP | 21}, \
1983 {"$s6", RTYPE_GP | 22}, \
1984 {"$s7", RTYPE_GP | 23}, \
1985 {"$t8", RTYPE_GP | 24}, \
1986 {"$t9", RTYPE_GP | 25}, \
1987 {"$k0", RTYPE_GP | 26}, \
1988 {"$kt0", RTYPE_GP | 26}, \
1989 {"$k1", RTYPE_GP | 27}, \
1990 {"$kt1", RTYPE_GP | 27}, \
1991 {"$gp", RTYPE_GP | 28}, \
1992 {"$sp", RTYPE_GP | 29}, \
1993 {"$s8", RTYPE_GP | 30}, \
1994 {"$fp", RTYPE_GP | 30}, \
1995 {"$ra", RTYPE_GP | 31}
1997 #define MIPS16_SPECIAL_REGISTER_NAMES \
1998 {"$pc", RTYPE_PC | 0}
2000 #define MDMX_VECTOR_REGISTER_NAMES \
2001 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2002 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2003 {"$v2", RTYPE_VEC | 2}, \
2004 {"$v3", RTYPE_VEC | 3}, \
2005 {"$v4", RTYPE_VEC | 4}, \
2006 {"$v5", RTYPE_VEC | 5}, \
2007 {"$v6", RTYPE_VEC | 6}, \
2008 {"$v7", RTYPE_VEC | 7}, \
2009 {"$v8", RTYPE_VEC | 8}, \
2010 {"$v9", RTYPE_VEC | 9}, \
2011 {"$v10", RTYPE_VEC | 10}, \
2012 {"$v11", RTYPE_VEC | 11}, \
2013 {"$v12", RTYPE_VEC | 12}, \
2014 {"$v13", RTYPE_VEC | 13}, \
2015 {"$v14", RTYPE_VEC | 14}, \
2016 {"$v15", RTYPE_VEC | 15}, \
2017 {"$v16", RTYPE_VEC | 16}, \
2018 {"$v17", RTYPE_VEC | 17}, \
2019 {"$v18", RTYPE_VEC | 18}, \
2020 {"$v19", RTYPE_VEC | 19}, \
2021 {"$v20", RTYPE_VEC | 20}, \
2022 {"$v21", RTYPE_VEC | 21}, \
2023 {"$v22", RTYPE_VEC | 22}, \
2024 {"$v23", RTYPE_VEC | 23}, \
2025 {"$v24", RTYPE_VEC | 24}, \
2026 {"$v25", RTYPE_VEC | 25}, \
2027 {"$v26", RTYPE_VEC | 26}, \
2028 {"$v27", RTYPE_VEC | 27}, \
2029 {"$v28", RTYPE_VEC | 28}, \
2030 {"$v29", RTYPE_VEC | 29}, \
2031 {"$v30", RTYPE_VEC | 30}, \
2032 {"$v31", RTYPE_VEC | 31}
2034 #define MIPS_DSP_ACCUMULATOR_NAMES \
2035 {"$ac0", RTYPE_ACC | 0}, \
2036 {"$ac1", RTYPE_ACC | 1}, \
2037 {"$ac2", RTYPE_ACC | 2}, \
2038 {"$ac3", RTYPE_ACC | 3}
2040 static const struct regname reg_names[] = {
2041 GENERIC_REGISTER_NUMBERS,
2043 FPU_CONDITION_CODE_NAMES,
2044 COPROC_CONDITION_CODE_NAMES,
2046 /* The $txx registers depends on the abi,
2047 these will be added later into the symbol table from
2048 one of the tables below once mips_abi is set after
2049 parsing of arguments from the command line. */
2050 SYMBOLIC_REGISTER_NAMES,
2052 MIPS16_SPECIAL_REGISTER_NAMES,
2053 MDMX_VECTOR_REGISTER_NAMES,
2054 MIPS_DSP_ACCUMULATOR_NAMES,
2058 static const struct regname reg_names_o32[] = {
2059 O32_SYMBOLIC_REGISTER_NAMES,
2063 static const struct regname reg_names_n32n64[] = {
2064 N32N64_SYMBOLIC_REGISTER_NAMES,
2068 /* Check if S points at a valid register specifier according to TYPES.
2069 If so, then return 1, advance S to consume the specifier and store
2070 the register's number in REGNOP, otherwise return 0. */
2073 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2080 /* Find end of name. */
2082 if (is_name_beginner (*e))
2084 while (is_part_of_name (*e))
2087 /* Terminate name. */
2091 /* Look for a register symbol. */
2092 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2094 int r = S_GET_VALUE (symbolP);
2096 reg = r & RNUM_MASK;
2097 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2098 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2099 reg = (r & RNUM_MASK) - 2;
2101 /* Else see if this is a register defined in an itbl entry. */
2102 else if ((types & RTYPE_GP) && itbl_have_entries)
2109 if (itbl_get_reg_val (n, &r))
2110 reg = r & RNUM_MASK;
2113 /* Advance to next token if a register was recognised. */
2116 else if (types & RWARN)
2117 as_warn (_("Unrecognized register name `%s'"), *s);
2125 /* Check if S points at a valid register list according to TYPES.
2126 If so, then return 1, advance S to consume the list and store
2127 the registers present on the list as a bitmask of ones in REGLISTP,
2128 otherwise return 0. A valid list comprises a comma-separated
2129 enumeration of valid single registers and/or dash-separated
2130 contiguous register ranges as determined by their numbers.
2132 As a special exception if one of s0-s7 registers is specified as
2133 the range's lower delimiter and s8 (fp) is its upper one, then no
2134 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2135 are selected; they have to be listed separately if needed. */
2138 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2140 unsigned int reglist = 0;
2141 unsigned int lastregno;
2142 bfd_boolean ok = TRUE;
2143 unsigned int regmask;
2144 char *s_endlist = *s;
2148 while (reg_lookup (s, types, ®no))
2154 ok = reg_lookup (s, types, &lastregno);
2155 if (ok && lastregno < regno)
2161 if (lastregno == FP && regno >= S0 && regno <= S7)
2166 regmask = 1 << lastregno;
2167 regmask = (regmask << 1) - 1;
2168 regmask ^= (1 << regno) - 1;
2182 *reglistp = reglist;
2183 return ok && reglist != 0;
2186 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2187 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2190 is_opcode_valid (const struct mips_opcode *mo)
2192 int isa = mips_opts.isa;
2195 if (mips_opts.ase_mdmx)
2197 if (mips_opts.ase_dsp)
2199 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2201 if (mips_opts.ase_dspr2)
2203 if (mips_opts.ase_mt)
2205 if (mips_opts.ase_mips3d)
2207 if (mips_opts.ase_smartmips)
2208 isa |= INSN_SMARTMIPS;
2210 /* Don't accept instructions based on the ISA if the CPU does not implement
2211 all the coprocessor insns. */
2212 if (NO_ISA_COP (mips_opts.arch)
2213 && COP_INSN (mo->pinfo))
2216 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
2219 /* Check whether the instruction or macro requires single-precision or
2220 double-precision floating-point support. Note that this information is
2221 stored differently in the opcode table for insns and macros. */
2222 if (mo->pinfo == INSN_MACRO)
2224 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2225 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2229 fp_s = mo->pinfo & FP_S;
2230 fp_d = mo->pinfo & FP_D;
2233 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2236 if (fp_s && mips_opts.soft_float)
2242 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2243 selected ISA and architecture. */
2246 is_opcode_valid_16 (const struct mips_opcode *mo)
2248 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
2251 /* Return TRUE if the size of the microMIPS opcode MO matches one
2252 explicitly requested. Always TRUE in the standard MIPS mode. */
2255 is_size_valid (const struct mips_opcode *mo)
2257 if (!mips_opts.micromips)
2260 if (!forced_insn_length)
2262 if (mo->pinfo == INSN_MACRO)
2264 return forced_insn_length == micromips_insn_length (mo);
2267 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2268 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2271 is_delay_slot_valid (const struct mips_opcode *mo)
2273 if (!mips_opts.micromips)
2276 if (mo->pinfo == INSN_MACRO)
2278 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2279 && micromips_insn_length (mo) != 4)
2281 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2282 && micromips_insn_length (mo) != 2)
2288 /* This function is called once, at assembler startup time. It should set up
2289 all the tables, etc. that the MD part of the assembler will need. */
2294 const char *retval = NULL;
2298 if (mips_pic != NO_PIC)
2300 if (g_switch_seen && g_switch_value != 0)
2301 as_bad (_("-G may not be used in position-independent code"));
2305 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2306 as_warn (_("Could not set architecture and machine"));
2308 op_hash = hash_new ();
2310 for (i = 0; i < NUMOPCODES;)
2312 const char *name = mips_opcodes[i].name;
2314 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2317 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2318 mips_opcodes[i].name, retval);
2319 /* Probably a memory allocation problem? Give up now. */
2320 as_fatal (_("Broken assembler. No assembly attempted."));
2324 if (mips_opcodes[i].pinfo != INSN_MACRO)
2326 if (!validate_mips_insn (&mips_opcodes[i]))
2328 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2330 create_insn (&nop_insn, mips_opcodes + i);
2331 if (mips_fix_loongson2f_nop)
2332 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2333 nop_insn.fixed_p = 1;
2338 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2341 mips16_op_hash = hash_new ();
2344 while (i < bfd_mips16_num_opcodes)
2346 const char *name = mips16_opcodes[i].name;
2348 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2350 as_fatal (_("internal: can't hash `%s': %s"),
2351 mips16_opcodes[i].name, retval);
2354 if (mips16_opcodes[i].pinfo != INSN_MACRO
2355 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2356 != mips16_opcodes[i].match))
2358 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2359 mips16_opcodes[i].name, mips16_opcodes[i].args);
2362 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2364 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2365 mips16_nop_insn.fixed_p = 1;
2369 while (i < bfd_mips16_num_opcodes
2370 && strcmp (mips16_opcodes[i].name, name) == 0);
2373 micromips_op_hash = hash_new ();
2376 while (i < bfd_micromips_num_opcodes)
2378 const char *name = micromips_opcodes[i].name;
2380 retval = hash_insert (micromips_op_hash, name,
2381 (void *) µmips_opcodes[i]);
2383 as_fatal (_("internal: can't hash `%s': %s"),
2384 micromips_opcodes[i].name, retval);
2386 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2388 struct mips_cl_insn *micromips_nop_insn;
2390 if (!validate_micromips_insn (µmips_opcodes[i]))
2393 if (micromips_insn_length (micromips_opcodes + i) == 2)
2394 micromips_nop_insn = µmips_nop16_insn;
2395 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2396 micromips_nop_insn = µmips_nop32_insn;
2400 if (micromips_nop_insn->insn_mo == NULL
2401 && strcmp (name, "nop") == 0)
2403 create_insn (micromips_nop_insn, micromips_opcodes + i);
2404 micromips_nop_insn->fixed_p = 1;
2407 while (++i < bfd_micromips_num_opcodes
2408 && strcmp (micromips_opcodes[i].name, name) == 0);
2412 as_fatal (_("Broken assembler. No assembly attempted."));
2414 /* We add all the general register names to the symbol table. This
2415 helps us detect invalid uses of them. */
2416 for (i = 0; reg_names[i].name; i++)
2417 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2418 reg_names[i].num, /* & RNUM_MASK, */
2419 &zero_address_frag));
2421 for (i = 0; reg_names_n32n64[i].name; i++)
2422 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2423 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2424 &zero_address_frag));
2426 for (i = 0; reg_names_o32[i].name; i++)
2427 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2428 reg_names_o32[i].num, /* & RNUM_MASK, */
2429 &zero_address_frag));
2431 mips_no_prev_insn ();
2434 mips_cprmask[0] = 0;
2435 mips_cprmask[1] = 0;
2436 mips_cprmask[2] = 0;
2437 mips_cprmask[3] = 0;
2439 /* set the default alignment for the text section (2**2) */
2440 record_alignment (text_section, 2);
2442 bfd_set_gp_size (stdoutput, g_switch_value);
2447 /* On a native system other than VxWorks, sections must be aligned
2448 to 16 byte boundaries. When configured for an embedded ELF
2449 target, we don't bother. */
2450 if (strncmp (TARGET_OS, "elf", 3) != 0
2451 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2453 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2454 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2455 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2458 /* Create a .reginfo section for register masks and a .mdebug
2459 section for debugging information. */
2467 subseg = now_subseg;
2469 /* The ABI says this section should be loaded so that the
2470 running program can access it. However, we don't load it
2471 if we are configured for an embedded target */
2472 flags = SEC_READONLY | SEC_DATA;
2473 if (strncmp (TARGET_OS, "elf", 3) != 0)
2474 flags |= SEC_ALLOC | SEC_LOAD;
2476 if (mips_abi != N64_ABI)
2478 sec = subseg_new (".reginfo", (subsegT) 0);
2480 bfd_set_section_flags (stdoutput, sec, flags);
2481 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2483 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2487 /* The 64-bit ABI uses a .MIPS.options section rather than
2488 .reginfo section. */
2489 sec = subseg_new (".MIPS.options", (subsegT) 0);
2490 bfd_set_section_flags (stdoutput, sec, flags);
2491 bfd_set_section_alignment (stdoutput, sec, 3);
2493 /* Set up the option header. */
2495 Elf_Internal_Options opthdr;
2498 opthdr.kind = ODK_REGINFO;
2499 opthdr.size = (sizeof (Elf_External_Options)
2500 + sizeof (Elf64_External_RegInfo));
2503 f = frag_more (sizeof (Elf_External_Options));
2504 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2505 (Elf_External_Options *) f);
2507 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2511 if (ECOFF_DEBUGGING)
2513 sec = subseg_new (".mdebug", (subsegT) 0);
2514 (void) bfd_set_section_flags (stdoutput, sec,
2515 SEC_HAS_CONTENTS | SEC_READONLY);
2516 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2518 else if (mips_flag_pdr)
2520 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2521 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2522 SEC_READONLY | SEC_RELOC
2524 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2527 subseg_set (seg, subseg);
2530 #endif /* OBJ_ELF */
2532 if (! ECOFF_DEBUGGING)
2535 if (mips_fix_vr4120)
2536 init_vr4120_conflicts ();
2542 mips_emit_delays ();
2543 if (! ECOFF_DEBUGGING)
2548 md_assemble (char *str)
2550 struct mips_cl_insn insn;
2551 bfd_reloc_code_real_type unused_reloc[3]
2552 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2554 imm_expr.X_op = O_absent;
2555 imm2_expr.X_op = O_absent;
2556 offset_expr.X_op = O_absent;
2557 imm_reloc[0] = BFD_RELOC_UNUSED;
2558 imm_reloc[1] = BFD_RELOC_UNUSED;
2559 imm_reloc[2] = BFD_RELOC_UNUSED;
2560 offset_reloc[0] = BFD_RELOC_UNUSED;
2561 offset_reloc[1] = BFD_RELOC_UNUSED;
2562 offset_reloc[2] = BFD_RELOC_UNUSED;
2564 if (mips_opts.mips16)
2565 mips16_ip (str, &insn);
2568 mips_ip (str, &insn);
2569 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2570 str, insn.insn_opcode));
2575 as_bad ("%s `%s'", insn_error, str);
2579 if (insn.insn_mo->pinfo == INSN_MACRO)
2582 if (mips_opts.mips16)
2583 mips16_macro (&insn);
2590 if (imm_expr.X_op != O_absent)
2591 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2592 else if (offset_expr.X_op != O_absent)
2593 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2595 append_insn (&insn, NULL, unused_reloc, FALSE);
2599 /* Convenience functions for abstracting away the differences between
2600 MIPS16 and non-MIPS16 relocations. */
2602 static inline bfd_boolean
2603 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2607 case BFD_RELOC_MIPS16_JMP:
2608 case BFD_RELOC_MIPS16_GPREL:
2609 case BFD_RELOC_MIPS16_GOT16:
2610 case BFD_RELOC_MIPS16_CALL16:
2611 case BFD_RELOC_MIPS16_HI16_S:
2612 case BFD_RELOC_MIPS16_HI16:
2613 case BFD_RELOC_MIPS16_LO16:
2621 static inline bfd_boolean
2622 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2626 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2627 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2628 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2629 case BFD_RELOC_MICROMIPS_GPREL16:
2630 case BFD_RELOC_MICROMIPS_JMP:
2631 case BFD_RELOC_MICROMIPS_HI16:
2632 case BFD_RELOC_MICROMIPS_HI16_S:
2633 case BFD_RELOC_MICROMIPS_LO16:
2634 case BFD_RELOC_MICROMIPS_LITERAL:
2635 case BFD_RELOC_MICROMIPS_GOT16:
2636 case BFD_RELOC_MICROMIPS_CALL16:
2637 case BFD_RELOC_MICROMIPS_GOT_HI16:
2638 case BFD_RELOC_MICROMIPS_GOT_LO16:
2639 case BFD_RELOC_MICROMIPS_CALL_HI16:
2640 case BFD_RELOC_MICROMIPS_CALL_LO16:
2641 case BFD_RELOC_MICROMIPS_SUB:
2642 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2643 case BFD_RELOC_MICROMIPS_GOT_OFST:
2644 case BFD_RELOC_MICROMIPS_GOT_DISP:
2645 case BFD_RELOC_MICROMIPS_HIGHEST:
2646 case BFD_RELOC_MICROMIPS_HIGHER:
2647 case BFD_RELOC_MICROMIPS_SCN_DISP:
2648 case BFD_RELOC_MICROMIPS_JALR:
2656 static inline bfd_boolean
2657 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2659 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2662 static inline bfd_boolean
2663 got16_reloc_p (bfd_reloc_code_real_type reloc)
2665 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2666 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2669 static inline bfd_boolean
2670 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2672 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2673 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2676 static inline bfd_boolean
2677 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2679 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2680 || reloc == BFD_RELOC_MICROMIPS_LO16);
2683 static inline bfd_boolean
2684 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2686 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2689 /* Return true if the given relocation might need a matching %lo().
2690 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2691 need a matching %lo() when applied to local symbols. */
2693 static inline bfd_boolean
2694 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2696 return (HAVE_IN_PLACE_ADDENDS
2697 && (hi16_reloc_p (reloc)
2698 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2699 all GOT16 relocations evaluate to "G". */
2700 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2703 /* Return the type of %lo() reloc needed by RELOC, given that
2704 reloc_needs_lo_p. */
2706 static inline bfd_reloc_code_real_type
2707 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2709 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2710 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2714 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2717 static inline bfd_boolean
2718 fixup_has_matching_lo_p (fixS *fixp)
2720 return (fixp->fx_next != NULL
2721 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2722 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2723 && fixp->fx_offset == fixp->fx_next->fx_offset);
2726 /* This function returns true if modifying a register requires a
2730 reg_needs_delay (unsigned int reg)
2732 unsigned long prev_pinfo;
2734 prev_pinfo = history[0].insn_mo->pinfo;
2735 if (! mips_opts.noreorder
2736 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2737 && ! gpr_interlocks)
2738 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2739 && ! cop_interlocks)))
2741 /* A load from a coprocessor or from memory. All load delays
2742 delay the use of general register rt for one instruction. */
2743 /* Itbl support may require additional care here. */
2744 know (prev_pinfo & INSN_WRITE_GPR_T);
2745 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2752 /* Move all labels in insn_labels to the current insertion point. */
2755 mips_move_labels (void)
2757 segment_info_type *si = seg_info (now_seg);
2758 struct insn_label_list *l;
2761 for (l = si->label_list; l != NULL; l = l->next)
2763 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2764 symbol_set_frag (l->label, frag_now);
2765 val = (valueT) frag_now_fix ();
2766 /* MIPS16/microMIPS text labels are stored as odd. */
2767 if (HAVE_CODE_COMPRESSION)
2769 S_SET_VALUE (l->label, val);
2774 s_is_linkonce (symbolS *sym, segT from_seg)
2776 bfd_boolean linkonce = FALSE;
2777 segT symseg = S_GET_SEGMENT (sym);
2779 if (symseg != from_seg && !S_IS_LOCAL (sym))
2781 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2784 /* The GNU toolchain uses an extension for ELF: a section
2785 beginning with the magic string .gnu.linkonce is a
2786 linkonce section. */
2787 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2788 sizeof ".gnu.linkonce" - 1) == 0)
2795 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2796 linker to handle them specially, such as generating jalx instructions
2797 when needed. We also make them odd for the duration of the assembly,
2798 in order to generate the right sort of code. We will make them even
2799 in the adjust_symtab routine, while leaving them marked. This is
2800 convenient for the debugger and the disassembler. The linker knows
2801 to make them odd again. */
2804 mips_compressed_mark_labels (void)
2806 segment_info_type *si = seg_info (now_seg);
2807 struct insn_label_list *l;
2809 gas_assert (HAVE_CODE_COMPRESSION);
2811 for (l = si->label_list; l != NULL; l = l->next)
2813 symbolS *label = l->label;
2815 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2818 if (mips_opts.mips16)
2819 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2821 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2824 if ((S_GET_VALUE (label) & 1) == 0
2825 /* Don't adjust the address if the label is global or weak, or
2826 in a link-once section, since we'll be emitting symbol reloc
2827 references to it which will be patched up by the linker, and
2828 the final value of the symbol may or may not be MIPS16/microMIPS. */
2829 && ! S_IS_WEAK (label)
2830 && ! S_IS_EXTERNAL (label)
2831 && ! s_is_linkonce (label, now_seg))
2832 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2836 /* End the current frag. Make it a variant frag and record the
2840 relax_close_frag (void)
2842 mips_macro_warning.first_frag = frag_now;
2843 frag_var (rs_machine_dependent, 0, 0,
2844 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2845 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2847 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2848 mips_relax.first_fixup = 0;
2851 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2852 See the comment above RELAX_ENCODE for more details. */
2855 relax_start (symbolS *symbol)
2857 gas_assert (mips_relax.sequence == 0);
2858 mips_relax.sequence = 1;
2859 mips_relax.symbol = symbol;
2862 /* Start generating the second version of a relaxable sequence.
2863 See the comment above RELAX_ENCODE for more details. */
2868 gas_assert (mips_relax.sequence == 1);
2869 mips_relax.sequence = 2;
2872 /* End the current relaxable sequence. */
2877 gas_assert (mips_relax.sequence == 2);
2878 relax_close_frag ();
2879 mips_relax.sequence = 0;
2882 /* Return true if IP is a delayed branch or jump. */
2884 static inline bfd_boolean
2885 delayed_branch_p (const struct mips_cl_insn *ip)
2887 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2888 | INSN_COND_BRANCH_DELAY
2889 | INSN_COND_BRANCH_LIKELY)) != 0;
2892 /* Return true if IP is a compact branch or jump. */
2894 static inline bfd_boolean
2895 compact_branch_p (const struct mips_cl_insn *ip)
2897 if (mips_opts.mips16)
2898 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2899 | MIPS16_INSN_COND_BRANCH)) != 0;
2901 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2902 | INSN2_COND_BRANCH)) != 0;
2905 /* Return true if IP is an unconditional branch or jump. */
2907 static inline bfd_boolean
2908 uncond_branch_p (const struct mips_cl_insn *ip)
2910 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2911 || (mips_opts.mips16
2912 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2913 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2916 /* Return true if IP is a branch-likely instruction. */
2918 static inline bfd_boolean
2919 branch_likely_p (const struct mips_cl_insn *ip)
2921 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2924 /* Return the type of nop that should be used to fill the delay slot
2925 of delayed branch IP. */
2927 static struct mips_cl_insn *
2928 get_delay_slot_nop (const struct mips_cl_insn *ip)
2930 if (mips_opts.micromips
2931 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2932 return µmips_nop32_insn;
2936 /* Return the mask of core registers that IP reads or writes. */
2939 gpr_mod_mask (const struct mips_cl_insn *ip)
2941 unsigned long pinfo2;
2945 pinfo2 = ip->insn_mo->pinfo2;
2946 if (mips_opts.micromips)
2948 if (pinfo2 & INSN2_MOD_GPR_MB)
2949 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
2950 if (pinfo2 & INSN2_MOD_GPR_MC)
2951 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
2952 if (pinfo2 & INSN2_MOD_GPR_MD)
2953 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2954 if (pinfo2 & INSN2_MOD_GPR_ME)
2955 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
2956 if (pinfo2 & INSN2_MOD_GPR_MF)
2957 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2958 if (pinfo2 & INSN2_MOD_GPR_MG)
2959 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
2960 if (pinfo2 & INSN2_MOD_GPR_MHI)
2962 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
2963 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
2965 if (pinfo2 & INSN2_MOD_GPR_MJ)
2966 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
2967 if (pinfo2 & INSN2_MOD_GPR_MM)
2968 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
2969 if (pinfo2 & INSN2_MOD_GPR_MN)
2970 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
2971 if (pinfo2 & INSN2_MOD_GPR_MP)
2972 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
2973 if (pinfo2 & INSN2_MOD_GPR_MQ)
2974 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
2975 if (pinfo2 & INSN2_MOD_SP)
2981 /* Return the mask of core registers that IP reads. */
2984 gpr_read_mask (const struct mips_cl_insn *ip)
2986 unsigned long pinfo, pinfo2;
2989 mask = gpr_mod_mask (ip);
2990 pinfo = ip->insn_mo->pinfo;
2991 pinfo2 = ip->insn_mo->pinfo2;
2992 if (mips_opts.mips16)
2994 if (pinfo & MIPS16_INSN_READ_X)
2995 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2996 if (pinfo & MIPS16_INSN_READ_Y)
2997 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2998 if (pinfo & MIPS16_INSN_READ_T)
3000 if (pinfo & MIPS16_INSN_READ_SP)
3002 if (pinfo & MIPS16_INSN_READ_31)
3004 if (pinfo & MIPS16_INSN_READ_Z)
3005 mask |= 1 << (mips16_to_32_reg_map
3006 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3007 if (pinfo & MIPS16_INSN_READ_GPR_X)
3008 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3012 if (pinfo2 & INSN2_READ_GPR_D)
3013 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3014 if (pinfo & INSN_READ_GPR_T)
3015 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3016 if (pinfo & INSN_READ_GPR_S)
3017 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3018 if (pinfo2 & INSN2_READ_GP)
3020 if (pinfo2 & INSN2_READ_GPR_31)
3022 if (pinfo2 & INSN2_READ_GPR_Z)
3023 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3025 /* Don't include register 0. */
3029 /* Return the mask of core registers that IP writes. */
3032 gpr_write_mask (const struct mips_cl_insn *ip)
3034 unsigned long pinfo, pinfo2;
3037 mask = gpr_mod_mask (ip);
3038 pinfo = ip->insn_mo->pinfo;
3039 pinfo2 = ip->insn_mo->pinfo2;
3040 if (mips_opts.mips16)
3042 if (pinfo & MIPS16_INSN_WRITE_X)
3043 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3044 if (pinfo & MIPS16_INSN_WRITE_Y)
3045 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3046 if (pinfo & MIPS16_INSN_WRITE_Z)
3047 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3048 if (pinfo & MIPS16_INSN_WRITE_T)
3050 if (pinfo & MIPS16_INSN_WRITE_SP)
3052 if (pinfo & MIPS16_INSN_WRITE_31)
3054 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3055 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3059 if (pinfo & INSN_WRITE_GPR_D)
3060 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3061 if (pinfo & INSN_WRITE_GPR_T)
3062 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3063 if (pinfo2 & INSN2_WRITE_GPR_S)
3064 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3065 if (pinfo & INSN_WRITE_GPR_31)
3067 if (pinfo2 & INSN2_WRITE_GPR_Z)
3068 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3070 /* Don't include register 0. */
3074 /* Return the mask of floating-point registers that IP reads. */
3077 fpr_read_mask (const struct mips_cl_insn *ip)
3079 unsigned long pinfo, pinfo2;
3083 pinfo = ip->insn_mo->pinfo;
3084 pinfo2 = ip->insn_mo->pinfo2;
3085 if (!mips_opts.mips16)
3087 if (pinfo2 & INSN2_READ_FPR_D)
3088 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3089 if (pinfo & INSN_READ_FPR_S)
3090 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3091 if (pinfo & INSN_READ_FPR_T)
3092 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3093 if (pinfo & INSN_READ_FPR_R)
3094 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3095 if (pinfo2 & INSN2_READ_FPR_Z)
3096 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3098 /* Conservatively treat all operands to an FP_D instruction are doubles.
3099 (This is overly pessimistic for things like cvt.d.s.) */
3100 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3105 /* Return the mask of floating-point registers that IP writes. */
3108 fpr_write_mask (const struct mips_cl_insn *ip)
3110 unsigned long pinfo, pinfo2;
3114 pinfo = ip->insn_mo->pinfo;
3115 pinfo2 = ip->insn_mo->pinfo2;
3116 if (!mips_opts.mips16)
3118 if (pinfo & INSN_WRITE_FPR_D)
3119 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3120 if (pinfo & INSN_WRITE_FPR_S)
3121 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3122 if (pinfo & INSN_WRITE_FPR_T)
3123 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3124 if (pinfo2 & INSN2_WRITE_FPR_Z)
3125 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3127 /* Conservatively treat all operands to an FP_D instruction are doubles.
3128 (This is overly pessimistic for things like cvt.s.d.) */
3129 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3134 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3135 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3136 by VR4120 errata. */
3139 classify_vr4120_insn (const char *name)
3141 if (strncmp (name, "macc", 4) == 0)
3142 return FIX_VR4120_MACC;
3143 if (strncmp (name, "dmacc", 5) == 0)
3144 return FIX_VR4120_DMACC;
3145 if (strncmp (name, "mult", 4) == 0)
3146 return FIX_VR4120_MULT;
3147 if (strncmp (name, "dmult", 5) == 0)
3148 return FIX_VR4120_DMULT;
3149 if (strstr (name, "div"))
3150 return FIX_VR4120_DIV;
3151 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3152 return FIX_VR4120_MTHILO;
3153 return NUM_FIX_VR4120_CLASSES;
3156 #define INSN_ERET 0x42000018
3157 #define INSN_DERET 0x4200001f
3159 /* Return the number of instructions that must separate INSN1 and INSN2,
3160 where INSN1 is the earlier instruction. Return the worst-case value
3161 for any INSN2 if INSN2 is null. */
3164 insns_between (const struct mips_cl_insn *insn1,
3165 const struct mips_cl_insn *insn2)
3167 unsigned long pinfo1, pinfo2;
3170 /* This function needs to know which pinfo flags are set for INSN2
3171 and which registers INSN2 uses. The former is stored in PINFO2 and
3172 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3173 will have every flag set and INSN2_USES_GPR will always return true. */
3174 pinfo1 = insn1->insn_mo->pinfo;
3175 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3177 #define INSN2_USES_GPR(REG) \
3178 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3180 /* For most targets, write-after-read dependencies on the HI and LO
3181 registers must be separated by at least two instructions. */
3182 if (!hilo_interlocks)
3184 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3186 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3190 /* If we're working around r7000 errata, there must be two instructions
3191 between an mfhi or mflo and any instruction that uses the result. */
3192 if (mips_7000_hilo_fix
3193 && !mips_opts.micromips
3194 && MF_HILO_INSN (pinfo1)
3195 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3198 /* If we're working around 24K errata, one instruction is required
3199 if an ERET or DERET is followed by a branch instruction. */
3200 if (mips_fix_24k && !mips_opts.micromips)
3202 if (insn1->insn_opcode == INSN_ERET
3203 || insn1->insn_opcode == INSN_DERET)
3206 || insn2->insn_opcode == INSN_ERET
3207 || insn2->insn_opcode == INSN_DERET
3208 || delayed_branch_p (insn2))
3213 /* If working around VR4120 errata, check for combinations that need
3214 a single intervening instruction. */
3215 if (mips_fix_vr4120 && !mips_opts.micromips)
3217 unsigned int class1, class2;
3219 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3220 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3224 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3225 if (vr4120_conflicts[class1] & (1 << class2))
3230 if (!HAVE_CODE_COMPRESSION)
3232 /* Check for GPR or coprocessor load delays. All such delays
3233 are on the RT register. */
3234 /* Itbl support may require additional care here. */
3235 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3236 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3238 know (pinfo1 & INSN_WRITE_GPR_T);
3239 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3243 /* Check for generic coprocessor hazards.
3245 This case is not handled very well. There is no special
3246 knowledge of CP0 handling, and the coprocessors other than
3247 the floating point unit are not distinguished at all. */
3248 /* Itbl support may require additional care here. FIXME!
3249 Need to modify this to include knowledge about
3250 user specified delays! */
3251 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3252 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3254 /* Handle cases where INSN1 writes to a known general coprocessor
3255 register. There must be a one instruction delay before INSN2
3256 if INSN2 reads that register, otherwise no delay is needed. */
3257 mask = fpr_write_mask (insn1);
3260 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3265 /* Read-after-write dependencies on the control registers
3266 require a two-instruction gap. */
3267 if ((pinfo1 & INSN_WRITE_COND_CODE)
3268 && (pinfo2 & INSN_READ_COND_CODE))
3271 /* We don't know exactly what INSN1 does. If INSN2 is
3272 also a coprocessor instruction, assume there must be
3273 a one instruction gap. */
3274 if (pinfo2 & INSN_COP)
3279 /* Check for read-after-write dependencies on the coprocessor
3280 control registers in cases where INSN1 does not need a general
3281 coprocessor delay. This means that INSN1 is a floating point
3282 comparison instruction. */
3283 /* Itbl support may require additional care here. */
3284 else if (!cop_interlocks
3285 && (pinfo1 & INSN_WRITE_COND_CODE)
3286 && (pinfo2 & INSN_READ_COND_CODE))
3290 #undef INSN2_USES_GPR
3295 /* Return the number of nops that would be needed to work around the
3296 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3297 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3298 that are contained within the first IGNORE instructions of HIST. */
3301 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3302 const struct mips_cl_insn *insn)
3307 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3308 are not affected by the errata. */
3310 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3311 || strcmp (insn->insn_mo->name, "mtlo") == 0
3312 || strcmp (insn->insn_mo->name, "mthi") == 0))
3315 /* Search for the first MFLO or MFHI. */
3316 for (i = 0; i < MAX_VR4130_NOPS; i++)
3317 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3319 /* Extract the destination register. */
3320 mask = gpr_write_mask (&hist[i]);
3322 /* No nops are needed if INSN reads that register. */
3323 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3326 /* ...or if any of the intervening instructions do. */
3327 for (j = 0; j < i; j++)
3328 if (gpr_read_mask (&hist[j]) & mask)
3332 return MAX_VR4130_NOPS - i;
3337 #define BASE_REG_EQ(INSN1, INSN2) \
3338 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3339 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3341 /* Return the minimum alignment for this store instruction. */
3344 fix_24k_align_to (const struct mips_opcode *mo)
3346 if (strcmp (mo->name, "sh") == 0)
3349 if (strcmp (mo->name, "swc1") == 0
3350 || strcmp (mo->name, "swc2") == 0
3351 || strcmp (mo->name, "sw") == 0
3352 || strcmp (mo->name, "sc") == 0
3353 || strcmp (mo->name, "s.s") == 0)
3356 if (strcmp (mo->name, "sdc1") == 0
3357 || strcmp (mo->name, "sdc2") == 0
3358 || strcmp (mo->name, "s.d") == 0)
3365 struct fix_24k_store_info
3367 /* Immediate offset, if any, for this store instruction. */
3369 /* Alignment required by this store instruction. */
3371 /* True for register offsets. */
3372 int register_offset;
3375 /* Comparison function used by qsort. */
3378 fix_24k_sort (const void *a, const void *b)
3380 const struct fix_24k_store_info *pos1 = a;
3381 const struct fix_24k_store_info *pos2 = b;
3383 return (pos1->off - pos2->off);
3386 /* INSN is a store instruction. Try to record the store information
3387 in STINFO. Return false if the information isn't known. */
3390 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3391 const struct mips_cl_insn *insn)
3393 /* The instruction must have a known offset. */
3394 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3397 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3398 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3402 /* Return the number of nops that would be needed to work around the 24k
3403 "lost data on stores during refill" errata if instruction INSN
3404 immediately followed the 2 instructions described by HIST.
3405 Ignore hazards that are contained within the first IGNORE
3406 instructions of HIST.
3408 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3409 for the data cache refills and store data. The following describes
3410 the scenario where the store data could be lost.
3412 * A data cache miss, due to either a load or a store, causing fill
3413 data to be supplied by the memory subsystem
3414 * The first three doublewords of fill data are returned and written
3416 * A sequence of four stores occurs in consecutive cycles around the
3417 final doubleword of the fill:
3421 * Zero, One or more instructions
3424 The four stores A-D must be to different doublewords of the line that
3425 is being filled. The fourth instruction in the sequence above permits
3426 the fill of the final doubleword to be transferred from the FSB into
3427 the cache. In the sequence above, the stores may be either integer
3428 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3429 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3430 different doublewords on the line. If the floating point unit is
3431 running in 1:2 mode, it is not possible to create the sequence above
3432 using only floating point store instructions.
3434 In this case, the cache line being filled is incorrectly marked
3435 invalid, thereby losing the data from any store to the line that
3436 occurs between the original miss and the completion of the five
3437 cycle sequence shown above.
3439 The workarounds are:
3441 * Run the data cache in write-through mode.
3442 * Insert a non-store instruction between
3443 Store A and Store B or Store B and Store C. */
3446 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3447 const struct mips_cl_insn *insn)
3449 struct fix_24k_store_info pos[3];
3450 int align, i, base_offset;
3455 /* If the previous instruction wasn't a store, there's nothing to
3457 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3460 /* If the instructions after the previous one are unknown, we have
3461 to assume the worst. */
3465 /* Check whether we are dealing with three consecutive stores. */
3466 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3467 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3470 /* If we don't know the relationship between the store addresses,
3471 assume the worst. */
3472 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3473 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3476 if (!fix_24k_record_store_info (&pos[0], insn)
3477 || !fix_24k_record_store_info (&pos[1], &hist[0])
3478 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3481 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3483 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3484 X bytes and such that the base register + X is known to be aligned
3487 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3491 align = pos[0].align_to;
3492 base_offset = pos[0].off;
3493 for (i = 1; i < 3; i++)
3494 if (align < pos[i].align_to)
3496 align = pos[i].align_to;
3497 base_offset = pos[i].off;
3499 for (i = 0; i < 3; i++)
3500 pos[i].off -= base_offset;
3503 pos[0].off &= ~align + 1;
3504 pos[1].off &= ~align + 1;
3505 pos[2].off &= ~align + 1;
3507 /* If any two stores write to the same chunk, they also write to the
3508 same doubleword. The offsets are still sorted at this point. */
3509 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3512 /* A range of at least 9 bytes is needed for the stores to be in
3513 non-overlapping doublewords. */
3514 if (pos[2].off - pos[0].off <= 8)
3517 if (pos[2].off - pos[1].off >= 24
3518 || pos[1].off - pos[0].off >= 24
3519 || pos[2].off - pos[0].off >= 32)
3525 /* Return the number of nops that would be needed if instruction INSN
3526 immediately followed the MAX_NOPS instructions given by HIST,
3527 where HIST[0] is the most recent instruction. Ignore hazards
3528 between INSN and the first IGNORE instructions in HIST.
3530 If INSN is null, return the worse-case number of nops for any
3534 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3535 const struct mips_cl_insn *insn)
3537 int i, nops, tmp_nops;
3540 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3542 tmp_nops = insns_between (hist + i, insn) - i;
3543 if (tmp_nops > nops)
3547 if (mips_fix_vr4130 && !mips_opts.micromips)
3549 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3550 if (tmp_nops > nops)
3554 if (mips_fix_24k && !mips_opts.micromips)
3556 tmp_nops = nops_for_24k (ignore, hist, insn);
3557 if (tmp_nops > nops)
3564 /* The variable arguments provide NUM_INSNS extra instructions that
3565 might be added to HIST. Return the largest number of nops that
3566 would be needed after the extended sequence, ignoring hazards
3567 in the first IGNORE instructions. */
3570 nops_for_sequence (int num_insns, int ignore,
3571 const struct mips_cl_insn *hist, ...)
3574 struct mips_cl_insn buffer[MAX_NOPS];
3575 struct mips_cl_insn *cursor;
3578 va_start (args, hist);
3579 cursor = buffer + num_insns;
3580 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3581 while (cursor > buffer)
3582 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3584 nops = nops_for_insn (ignore, buffer, NULL);
3589 /* Like nops_for_insn, but if INSN is a branch, take into account the
3590 worst-case delay for the branch target. */
3593 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3594 const struct mips_cl_insn *insn)
3598 nops = nops_for_insn (ignore, hist, insn);
3599 if (delayed_branch_p (insn))
3601 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3602 hist, insn, get_delay_slot_nop (insn));
3603 if (tmp_nops > nops)
3606 else if (compact_branch_p (insn))
3608 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3609 if (tmp_nops > nops)
3615 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3618 fix_loongson2f_nop (struct mips_cl_insn * ip)
3620 gas_assert (!HAVE_CODE_COMPRESSION);
3621 if (strcmp (ip->insn_mo->name, "nop") == 0)
3622 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3625 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3626 jr target pc &= 'hffff_ffff_cfff_ffff. */
3629 fix_loongson2f_jump (struct mips_cl_insn * ip)
3631 gas_assert (!HAVE_CODE_COMPRESSION);
3632 if (strcmp (ip->insn_mo->name, "j") == 0
3633 || strcmp (ip->insn_mo->name, "jr") == 0
3634 || strcmp (ip->insn_mo->name, "jalr") == 0)
3642 sreg = EXTRACT_OPERAND (0, RS, *ip);
3643 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3646 ep.X_op = O_constant;
3647 ep.X_add_number = 0xcfff0000;
3648 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3649 ep.X_add_number = 0xffff;
3650 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3651 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3656 fix_loongson2f (struct mips_cl_insn * ip)
3658 if (mips_fix_loongson2f_nop)
3659 fix_loongson2f_nop (ip);
3661 if (mips_fix_loongson2f_jump)
3662 fix_loongson2f_jump (ip);
3665 /* IP is a branch that has a delay slot, and we need to fill it
3666 automatically. Return true if we can do that by swapping IP
3667 with the previous instruction. */
3670 can_swap_branch_p (struct mips_cl_insn *ip)
3672 unsigned long pinfo, pinfo2, prev_pinfo;
3673 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3675 /* For microMIPS, disable reordering. */
3676 if (mips_opts.micromips)
3679 /* -O2 and above is required for this optimization. */
3680 if (mips_optimize < 2)
3683 /* If we have seen .set volatile or .set nomove, don't optimize. */
3684 if (mips_opts.nomove)
3687 /* We can't swap if the previous instruction's position is fixed. */
3688 if (history[0].fixed_p)
3691 /* If the previous previous insn was in a .set noreorder, we can't
3692 swap. Actually, the MIPS assembler will swap in this situation.
3693 However, gcc configured -with-gnu-as will generate code like
3701 in which we can not swap the bne and INSN. If gcc is not configured
3702 -with-gnu-as, it does not output the .set pseudo-ops. */
3703 if (history[1].noreorder_p)
3706 /* If the previous instruction had a fixup in mips16 mode, we can not
3707 swap. This normally means that the previous instruction was a 4
3708 byte branch anyhow. */
3709 if (mips_opts.mips16 && history[0].fixp[0])
3712 /* If the branch is itself the target of a branch, we can not swap.
3713 We cheat on this; all we check for is whether there is a label on
3714 this instruction. If there are any branches to anything other than
3715 a label, users must use .set noreorder. */
3716 if (seg_info (now_seg)->label_list)
3719 /* If the previous instruction is in a variant frag other than this
3720 branch's one, we cannot do the swap. This does not apply to
3721 MIPS16/microMIPS code, which uses variant frags for different
3723 if (!HAVE_CODE_COMPRESSION
3725 && history[0].frag->fr_type == rs_machine_dependent)
3728 /* We do not swap with instructions that cannot architecturally
3729 be placed in a branch delay slot, such as SYNC or ERET. We
3730 also refrain from swapping with a trap instruction, since it
3731 complicates trap handlers to have the trap instruction be in
3733 prev_pinfo = history[0].insn_mo->pinfo;
3734 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3737 /* Check for conflicts between the branch and the instructions
3738 before the candidate delay slot. */
3739 if (nops_for_insn (0, history + 1, ip) > 0)
3742 /* Check for conflicts between the swapped sequence and the
3743 target of the branch. */
3744 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3747 /* If the branch reads a register that the previous
3748 instruction sets, we can not swap. */
3749 gpr_read = gpr_read_mask (ip);
3750 prev_gpr_write = gpr_write_mask (&history[0]);
3751 if (gpr_read & prev_gpr_write)
3754 /* If the branch writes a register that the previous
3755 instruction sets, we can not swap. */
3756 gpr_write = gpr_write_mask (ip);
3757 if (gpr_write & prev_gpr_write)
3760 /* If the branch writes a register that the previous
3761 instruction reads, we can not swap. */
3762 prev_gpr_read = gpr_read_mask (&history[0]);
3763 if (gpr_write & prev_gpr_read)
3766 /* If one instruction sets a condition code and the
3767 other one uses a condition code, we can not swap. */
3768 pinfo = ip->insn_mo->pinfo;
3769 if ((pinfo & INSN_READ_COND_CODE)
3770 && (prev_pinfo & INSN_WRITE_COND_CODE))
3772 if ((pinfo & INSN_WRITE_COND_CODE)
3773 && (prev_pinfo & INSN_READ_COND_CODE))
3776 /* If the previous instruction uses the PC, we can not swap. */
3777 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3780 /* If the previous instruction has an incorrect size for a fixed
3781 branch delay slot in microMIPS mode, we cannot swap. */
3782 pinfo2 = ip->insn_mo->pinfo2;
3783 if (mips_opts.micromips
3784 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3785 && insn_length (history) != 2)
3787 if (mips_opts.micromips
3788 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3789 && insn_length (history) != 4)
3795 /* Decide how we should add IP to the instruction stream. */
3797 static enum append_method
3798 get_append_method (struct mips_cl_insn *ip)
3800 unsigned long pinfo;
3802 /* The relaxed version of a macro sequence must be inherently
3804 if (mips_relax.sequence == 2)
3807 /* We must not dabble with instructions in a ".set norerorder" block. */
3808 if (mips_opts.noreorder)
3811 /* Otherwise, it's our responsibility to fill branch delay slots. */
3812 if (delayed_branch_p (ip))
3814 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3817 pinfo = ip->insn_mo->pinfo;
3818 if (mips_opts.mips16
3819 && ISA_SUPPORTS_MIPS16E
3820 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3821 return APPEND_ADD_COMPACT;
3823 return APPEND_ADD_WITH_NOP;
3829 /* IP is a MIPS16 instruction whose opcode we have just changed.
3830 Point IP->insn_mo to the new opcode's definition. */
3833 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3835 const struct mips_opcode *mo, *end;
3837 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3838 for (mo = ip->insn_mo; mo < end; mo++)
3839 if ((ip->insn_opcode & mo->mask) == mo->match)
3847 /* For microMIPS macros, we need to generate a local number label
3848 as the target of branches. */
3849 #define MICROMIPS_LABEL_CHAR '\037'
3850 static unsigned long micromips_target_label;
3851 static char micromips_target_name[32];
3854 micromips_label_name (void)
3856 char *p = micromips_target_name;
3857 char symbol_name_temporary[24];
3865 l = micromips_target_label;
3866 #ifdef LOCAL_LABEL_PREFIX
3867 *p++ = LOCAL_LABEL_PREFIX;
3870 *p++ = MICROMIPS_LABEL_CHAR;
3873 symbol_name_temporary[i++] = l % 10 + '0';
3878 *p++ = symbol_name_temporary[--i];
3881 return micromips_target_name;
3885 micromips_label_expr (expressionS *label_expr)
3887 label_expr->X_op = O_symbol;
3888 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3889 label_expr->X_add_number = 0;
3893 micromips_label_inc (void)
3895 micromips_target_label++;
3896 *micromips_target_name = '\0';
3900 micromips_add_label (void)
3904 s = colon (micromips_label_name ());
3905 micromips_label_inc ();
3906 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3908 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3912 /* If assembling microMIPS code, then return the microMIPS reloc
3913 corresponding to the requested one if any. Otherwise return
3914 the reloc unchanged. */
3916 static bfd_reloc_code_real_type
3917 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3919 static const bfd_reloc_code_real_type relocs[][2] =
3921 /* Keep sorted incrementally by the left-hand key. */
3922 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3923 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3924 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3925 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3926 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3927 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3928 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3929 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3930 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3931 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3932 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3933 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3934 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3935 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3936 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3937 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3938 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3939 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3940 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3941 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3942 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3943 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3944 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3945 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3946 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3947 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3948 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
3950 bfd_reloc_code_real_type r;
3953 if (!mips_opts.micromips)
3955 for (i = 0; i < ARRAY_SIZE (relocs); i++)
3961 return relocs[i][1];
3966 /* Output an instruction. IP is the instruction information.
3967 ADDRESS_EXPR is an operand of the instruction to be used with
3968 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3969 a macro expansion. */
3972 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3973 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
3975 unsigned long prev_pinfo2, pinfo;
3976 bfd_boolean relaxed_branch = FALSE;
3977 enum append_method method;
3978 bfd_boolean relax32;
3980 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
3981 fix_loongson2f (ip);
3983 mips_mark_labels ();
3985 file_ase_mips16 |= mips_opts.mips16;
3986 file_ase_micromips |= mips_opts.micromips;
3988 prev_pinfo2 = history[0].insn_mo->pinfo2;
3989 pinfo = ip->insn_mo->pinfo;
3991 if (mips_opts.micromips
3993 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3994 && micromips_insn_length (ip->insn_mo) != 2)
3995 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3996 && micromips_insn_length (ip->insn_mo) != 4)))
3997 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
3998 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4000 if (address_expr == NULL)
4002 else if (*reloc_type <= BFD_RELOC_UNUSED
4003 && address_expr->X_op == O_constant)
4008 switch (*reloc_type)
4011 ip->insn_opcode |= address_expr->X_add_number;
4014 case BFD_RELOC_MIPS_HIGHEST:
4015 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
4016 ip->insn_opcode |= tmp & 0xffff;
4019 case BFD_RELOC_MIPS_HIGHER:
4020 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
4021 ip->insn_opcode |= tmp & 0xffff;
4024 case BFD_RELOC_HI16_S:
4025 tmp = (address_expr->X_add_number + 0x8000) >> 16;
4026 ip->insn_opcode |= tmp & 0xffff;
4029 case BFD_RELOC_HI16:
4030 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4033 case BFD_RELOC_UNUSED:
4034 case BFD_RELOC_LO16:
4035 case BFD_RELOC_MIPS_GOT_DISP:
4036 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4039 case BFD_RELOC_MIPS_JMP:
4043 shift = mips_opts.micromips ? 1 : 2;
4044 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4045 as_bad (_("jump to misaligned address (0x%lx)"),
4046 (unsigned long) address_expr->X_add_number);
4047 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4053 case BFD_RELOC_MIPS16_JMP:
4054 if ((address_expr->X_add_number & 3) != 0)
4055 as_bad (_("jump to misaligned address (0x%lx)"),
4056 (unsigned long) address_expr->X_add_number);
4058 (((address_expr->X_add_number & 0x7c0000) << 3)
4059 | ((address_expr->X_add_number & 0xf800000) >> 7)
4060 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4064 case BFD_RELOC_16_PCREL_S2:
4068 shift = mips_opts.micromips ? 1 : 2;
4069 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4070 as_bad (_("branch to misaligned address (0x%lx)"),
4071 (unsigned long) address_expr->X_add_number);
4072 if (!mips_relax_branch)
4074 if ((address_expr->X_add_number + (1 << (shift + 15)))
4075 & ~((1 << (shift + 16)) - 1))
4076 as_bad (_("branch address range overflow (0x%lx)"),
4077 (unsigned long) address_expr->X_add_number);
4078 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4090 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4092 /* There are a lot of optimizations we could do that we don't.
4093 In particular, we do not, in general, reorder instructions.
4094 If you use gcc with optimization, it will reorder
4095 instructions and generally do much more optimization then we
4096 do here; repeating all that work in the assembler would only
4097 benefit hand written assembly code, and does not seem worth
4099 int nops = (mips_optimize == 0
4100 ? nops_for_insn (0, history, NULL)
4101 : nops_for_insn_or_target (0, history, ip));
4105 unsigned long old_frag_offset;
4108 old_frag = frag_now;
4109 old_frag_offset = frag_now_fix ();
4111 for (i = 0; i < nops; i++)
4112 add_fixed_insn (NOP_INSN);
4113 insert_into_history (0, nops, NOP_INSN);
4117 listing_prev_line ();
4118 /* We may be at the start of a variant frag. In case we
4119 are, make sure there is enough space for the frag
4120 after the frags created by listing_prev_line. The
4121 argument to frag_grow here must be at least as large
4122 as the argument to all other calls to frag_grow in
4123 this file. We don't have to worry about being in the
4124 middle of a variant frag, because the variants insert
4125 all needed nop instructions themselves. */
4129 mips_move_labels ();
4131 #ifndef NO_ECOFF_DEBUGGING
4132 if (ECOFF_DEBUGGING)
4133 ecoff_fix_loc (old_frag, old_frag_offset);
4137 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4141 /* Work out how many nops in prev_nop_frag are needed by IP,
4142 ignoring hazards generated by the first prev_nop_frag_since
4144 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4145 gas_assert (nops <= prev_nop_frag_holds);
4147 /* Enforce NOPS as a minimum. */
4148 if (nops > prev_nop_frag_required)
4149 prev_nop_frag_required = nops;
4151 if (prev_nop_frag_holds == prev_nop_frag_required)
4153 /* Settle for the current number of nops. Update the history
4154 accordingly (for the benefit of any future .set reorder code). */
4155 prev_nop_frag = NULL;
4156 insert_into_history (prev_nop_frag_since,
4157 prev_nop_frag_holds, NOP_INSN);
4161 /* Allow this instruction to replace one of the nops that was
4162 tentatively added to prev_nop_frag. */
4163 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4164 prev_nop_frag_holds--;
4165 prev_nop_frag_since++;
4169 method = get_append_method (ip);
4172 /* The value passed to dwarf2_emit_insn is the distance between
4173 the beginning of the current instruction and the address that
4174 should be recorded in the debug tables. This is normally the
4177 For MIPS16/microMIPS debug info we want to use ISA-encoded
4178 addresses, so we use -1 for an address higher by one than the
4181 If the instruction produced is a branch that we will swap with
4182 the preceding instruction, then we add the displacement by which
4183 the branch will be moved backwards. This is more appropriate
4184 and for MIPS16/microMIPS code also prevents a debugger from
4185 placing a breakpoint in the middle of the branch (and corrupting
4186 code if software breakpoints are used). */
4187 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0)
4188 + (method == APPEND_SWAP ? insn_length (history) : 0));
4191 relax32 = (mips_relax_branch
4192 /* Don't try branch relaxation within .set nomacro, or within
4193 .set noat if we use $at for PIC computations. If it turns
4194 out that the branch was out-of-range, we'll get an error. */
4195 && !mips_opts.warn_about_macros
4196 && (mips_opts.at || mips_pic == NO_PIC)
4197 /* Don't relax BPOSGE32/64 as they have no complementing
4199 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
4200 /* Don't try 32-bit branch relaxation when users specify
4201 16-bit/32-bit instructions. */
4202 && !forced_insn_length);
4204 if (!HAVE_CODE_COMPRESSION
4207 && *reloc_type == BFD_RELOC_16_PCREL_S2
4208 && delayed_branch_p (ip))
4210 relaxed_branch = TRUE;
4211 add_relaxed_insn (ip, (relaxed_branch_length
4213 uncond_branch_p (ip) ? -1
4214 : branch_likely_p (ip) ? 1
4218 uncond_branch_p (ip),
4219 branch_likely_p (ip),
4220 pinfo & INSN_WRITE_GPR_31,
4222 address_expr->X_add_symbol,
4223 address_expr->X_add_number);
4224 *reloc_type = BFD_RELOC_UNUSED;
4226 else if (mips_opts.micromips
4228 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4229 || *reloc_type > BFD_RELOC_UNUSED)
4230 && (delayed_branch_p (ip) || compact_branch_p (ip)))
4232 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4233 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4234 int uncond = uncond_branch_p (ip) ? -1 : 0;
4235 int compact = compact_branch_p (ip);
4236 int al = pinfo & INSN_WRITE_GPR_31;
4239 gas_assert (address_expr != NULL);
4240 gas_assert (!mips_relax.sequence);
4242 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4243 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4244 RELAX_MICROMIPS_ENCODE (type, AT,
4245 forced_insn_length == 2,
4246 uncond, compact, al, relax32,
4248 address_expr->X_add_symbol,
4249 address_expr->X_add_number);
4250 *reloc_type = BFD_RELOC_UNUSED;
4252 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4254 /* We need to set up a variant frag. */
4255 gas_assert (address_expr != NULL);
4256 add_relaxed_insn (ip, 4, 0,
4258 (*reloc_type - BFD_RELOC_UNUSED,
4259 forced_insn_length == 2, forced_insn_length == 4,
4260 delayed_branch_p (&history[0]),
4261 history[0].mips16_absolute_jump_p),
4262 make_expr_symbol (address_expr), 0);
4264 else if (mips_opts.mips16
4266 && *reloc_type != BFD_RELOC_MIPS16_JMP)
4268 if (!delayed_branch_p (ip))
4269 /* Make sure there is enough room to swap this instruction with
4270 a following jump instruction. */
4272 add_fixed_insn (ip);
4276 if (mips_opts.mips16
4277 && mips_opts.noreorder
4278 && delayed_branch_p (&history[0]))
4279 as_warn (_("extended instruction in delay slot"));
4281 if (mips_relax.sequence)
4283 /* If we've reached the end of this frag, turn it into a variant
4284 frag and record the information for the instructions we've
4286 if (frag_room () < 4)
4287 relax_close_frag ();
4288 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4291 if (mips_relax.sequence != 2)
4293 if (mips_macro_warning.first_insn_sizes[0] == 0)
4294 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4295 mips_macro_warning.sizes[0] += insn_length (ip);
4296 mips_macro_warning.insns[0]++;
4298 if (mips_relax.sequence != 1)
4300 if (mips_macro_warning.first_insn_sizes[1] == 0)
4301 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4302 mips_macro_warning.sizes[1] += insn_length (ip);
4303 mips_macro_warning.insns[1]++;
4306 if (mips_opts.mips16)
4309 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4311 add_fixed_insn (ip);
4314 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4316 bfd_reloc_code_real_type final_type[3];
4317 reloc_howto_type *howto0;
4318 reloc_howto_type *howto;
4321 /* Perform any necessary conversion to microMIPS relocations
4322 and find out how many relocations there actually are. */
4323 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4324 final_type[i] = micromips_map_reloc (reloc_type[i]);
4326 /* In a compound relocation, it is the final (outermost)
4327 operator that determines the relocated field. */
4328 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4332 /* To reproduce this failure try assembling gas/testsuites/
4333 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4335 as_bad (_("Unsupported MIPS relocation number %d"),
4337 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4341 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4342 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4343 bfd_get_reloc_size (howto),
4345 howto0 && howto0->pc_relative,
4348 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4349 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4350 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4352 /* These relocations can have an addend that won't fit in
4353 4 octets for 64bit assembly. */
4355 && ! howto->partial_inplace
4356 && (reloc_type[0] == BFD_RELOC_16
4357 || reloc_type[0] == BFD_RELOC_32
4358 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4359 || reloc_type[0] == BFD_RELOC_GPREL16
4360 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4361 || reloc_type[0] == BFD_RELOC_GPREL32
4362 || reloc_type[0] == BFD_RELOC_64
4363 || reloc_type[0] == BFD_RELOC_CTOR
4364 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4365 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4366 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4367 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4368 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4369 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4370 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4371 || hi16_reloc_p (reloc_type[0])
4372 || lo16_reloc_p (reloc_type[0])))
4373 ip->fixp[0]->fx_no_overflow = 1;
4375 if (mips_relax.sequence)
4377 if (mips_relax.first_fixup == 0)
4378 mips_relax.first_fixup = ip->fixp[0];
4380 else if (reloc_needs_lo_p (*reloc_type))
4382 struct mips_hi_fixup *hi_fixup;
4384 /* Reuse the last entry if it already has a matching %lo. */
4385 hi_fixup = mips_hi_fixup_list;
4387 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4389 hi_fixup = ((struct mips_hi_fixup *)
4390 xmalloc (sizeof (struct mips_hi_fixup)));
4391 hi_fixup->next = mips_hi_fixup_list;
4392 mips_hi_fixup_list = hi_fixup;
4394 hi_fixup->fixp = ip->fixp[0];
4395 hi_fixup->seg = now_seg;
4398 /* Add fixups for the second and third relocations, if given.
4399 Note that the ABI allows the second relocation to be
4400 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4401 moment we only use RSS_UNDEF, but we could add support
4402 for the others if it ever becomes necessary. */
4403 for (i = 1; i < 3; i++)
4404 if (reloc_type[i] != BFD_RELOC_UNUSED)
4406 ip->fixp[i] = fix_new (ip->frag, ip->where,
4407 ip->fixp[0]->fx_size, NULL, 0,
4408 FALSE, final_type[i]);
4410 /* Use fx_tcbit to mark compound relocs. */
4411 ip->fixp[0]->fx_tcbit = 1;
4412 ip->fixp[i]->fx_tcbit = 1;
4417 /* Update the register mask information. */
4418 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4419 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4424 insert_into_history (0, 1, ip);
4427 case APPEND_ADD_WITH_NOP:
4429 struct mips_cl_insn *nop;
4431 insert_into_history (0, 1, ip);
4432 nop = get_delay_slot_nop (ip);
4433 add_fixed_insn (nop);
4434 insert_into_history (0, 1, nop);
4435 if (mips_relax.sequence)
4436 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4440 case APPEND_ADD_COMPACT:
4441 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4442 gas_assert (mips_opts.mips16);
4443 ip->insn_opcode |= 0x0080;
4444 find_altered_mips16_opcode (ip);
4446 insert_into_history (0, 1, ip);
4451 struct mips_cl_insn delay = history[0];
4452 if (mips_opts.mips16)
4454 know (delay.frag == ip->frag);
4455 move_insn (ip, delay.frag, delay.where);
4456 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4458 else if (mips_opts.micromips)
4460 /* We don't reorder for micromips. */
4463 else if (relaxed_branch)
4465 /* Add the delay slot instruction to the end of the
4466 current frag and shrink the fixed part of the
4467 original frag. If the branch occupies the tail of
4468 the latter, move it backwards to cover the gap. */
4469 delay.frag->fr_fix -= 4;
4470 if (delay.frag == ip->frag)
4471 move_insn (ip, ip->frag, ip->where - 4);
4472 add_fixed_insn (&delay);
4476 move_insn (&delay, ip->frag, ip->where);
4477 move_insn (ip, history[0].frag, history[0].where);
4481 insert_into_history (0, 1, &delay);
4486 /* If we have just completed an unconditional branch, clear the history. */
4487 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4488 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4489 mips_no_prev_insn ();
4491 /* We need to emit a label at the end of branch-likely macros. */
4492 if (emit_branch_likely_macro)
4494 emit_branch_likely_macro = FALSE;
4495 micromips_add_label ();
4498 /* We just output an insn, so the next one doesn't have a label. */
4499 mips_clear_insn_labels ();
4502 /* Forget that there was any previous instruction or label. */
4505 mips_no_prev_insn (void)
4507 prev_nop_frag = NULL;
4508 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4509 mips_clear_insn_labels ();
4512 /* This function must be called before we emit something other than
4513 instructions. It is like mips_no_prev_insn except that it inserts
4514 any NOPS that might be needed by previous instructions. */
4517 mips_emit_delays (void)
4519 if (! mips_opts.noreorder)
4521 int nops = nops_for_insn (0, history, NULL);
4525 add_fixed_insn (NOP_INSN);
4526 mips_move_labels ();
4529 mips_no_prev_insn ();
4532 /* Start a (possibly nested) noreorder block. */
4535 start_noreorder (void)
4537 if (mips_opts.noreorder == 0)
4542 /* None of the instructions before the .set noreorder can be moved. */
4543 for (i = 0; i < ARRAY_SIZE (history); i++)
4544 history[i].fixed_p = 1;
4546 /* Insert any nops that might be needed between the .set noreorder
4547 block and the previous instructions. We will later remove any
4548 nops that turn out not to be needed. */
4549 nops = nops_for_insn (0, history, NULL);
4552 if (mips_optimize != 0)
4554 /* Record the frag which holds the nop instructions, so
4555 that we can remove them if we don't need them. */
4556 frag_grow (nops * NOP_INSN_SIZE);
4557 prev_nop_frag = frag_now;
4558 prev_nop_frag_holds = nops;
4559 prev_nop_frag_required = 0;
4560 prev_nop_frag_since = 0;
4563 for (; nops > 0; --nops)
4564 add_fixed_insn (NOP_INSN);
4566 /* Move on to a new frag, so that it is safe to simply
4567 decrease the size of prev_nop_frag. */
4568 frag_wane (frag_now);
4570 mips_move_labels ();
4572 mips_mark_labels ();
4573 mips_clear_insn_labels ();
4575 mips_opts.noreorder++;
4576 mips_any_noreorder = 1;
4579 /* End a nested noreorder block. */
4582 end_noreorder (void)
4585 mips_opts.noreorder--;
4586 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4588 /* Commit to inserting prev_nop_frag_required nops and go back to
4589 handling nop insertion the .set reorder way. */
4590 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4592 insert_into_history (prev_nop_frag_since,
4593 prev_nop_frag_required, NOP_INSN);
4594 prev_nop_frag = NULL;
4598 /* Set up global variables for the start of a new macro. */
4603 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4604 memset (&mips_macro_warning.first_insn_sizes, 0,
4605 sizeof (mips_macro_warning.first_insn_sizes));
4606 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4607 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4608 && delayed_branch_p (&history[0]));
4609 switch (history[0].insn_mo->pinfo2
4610 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4612 case INSN2_BRANCH_DELAY_32BIT:
4613 mips_macro_warning.delay_slot_length = 4;
4615 case INSN2_BRANCH_DELAY_16BIT:
4616 mips_macro_warning.delay_slot_length = 2;
4619 mips_macro_warning.delay_slot_length = 0;
4622 mips_macro_warning.first_frag = NULL;
4625 /* Given that a macro is longer than one instruction or of the wrong size,
4626 return the appropriate warning for it. Return null if no warning is
4627 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4628 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4629 and RELAX_NOMACRO. */
4632 macro_warning (relax_substateT subtype)
4634 if (subtype & RELAX_DELAY_SLOT)
4635 return _("Macro instruction expanded into multiple instructions"
4636 " in a branch delay slot");
4637 else if (subtype & RELAX_NOMACRO)
4638 return _("Macro instruction expanded into multiple instructions");
4639 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4640 | RELAX_DELAY_SLOT_SIZE_SECOND))
4641 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4642 ? _("Macro instruction expanded into a wrong size instruction"
4643 " in a 16-bit branch delay slot")
4644 : _("Macro instruction expanded into a wrong size instruction"
4645 " in a 32-bit branch delay slot"));
4650 /* Finish up a macro. Emit warnings as appropriate. */
4655 /* Relaxation warning flags. */
4656 relax_substateT subtype = 0;
4658 /* Check delay slot size requirements. */
4659 if (mips_macro_warning.delay_slot_length == 2)
4660 subtype |= RELAX_DELAY_SLOT_16BIT;
4661 if (mips_macro_warning.delay_slot_length != 0)
4663 if (mips_macro_warning.delay_slot_length
4664 != mips_macro_warning.first_insn_sizes[0])
4665 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4666 if (mips_macro_warning.delay_slot_length
4667 != mips_macro_warning.first_insn_sizes[1])
4668 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4671 /* Check instruction count requirements. */
4672 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4674 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4675 subtype |= RELAX_SECOND_LONGER;
4676 if (mips_opts.warn_about_macros)
4677 subtype |= RELAX_NOMACRO;
4678 if (mips_macro_warning.delay_slot_p)
4679 subtype |= RELAX_DELAY_SLOT;
4682 /* If both alternatives fail to fill a delay slot correctly,
4683 emit the warning now. */
4684 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4685 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4690 s = subtype & (RELAX_DELAY_SLOT_16BIT
4691 | RELAX_DELAY_SLOT_SIZE_FIRST
4692 | RELAX_DELAY_SLOT_SIZE_SECOND);
4693 msg = macro_warning (s);
4695 as_warn ("%s", msg);
4699 /* If both implementations are longer than 1 instruction, then emit the
4701 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4706 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4707 msg = macro_warning (s);
4709 as_warn ("%s", msg);
4713 /* If any flags still set, then one implementation might need a warning
4714 and the other either will need one of a different kind or none at all.
4715 Pass any remaining flags over to relaxation. */
4716 if (mips_macro_warning.first_frag != NULL)
4717 mips_macro_warning.first_frag->fr_subtype |= subtype;
4720 /* Instruction operand formats used in macros that vary between
4721 standard MIPS and microMIPS code. */
4723 static const char * const brk_fmt[2] = { "c", "mF" };
4724 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4725 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4726 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4727 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4728 static const char * const mfhl_fmt[2] = { "d", "mj" };
4729 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4730 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4732 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4733 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4734 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4735 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4736 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4737 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4738 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4739 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4741 /* Read a macro's relocation codes from *ARGS and store them in *R.
4742 The first argument in *ARGS will be either the code for a single
4743 relocation or -1 followed by the three codes that make up a
4744 composite relocation. */
4747 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4751 next = va_arg (*args, int);
4753 r[0] = (bfd_reloc_code_real_type) next;
4755 for (i = 0; i < 3; i++)
4756 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4759 /* Build an instruction created by a macro expansion. This is passed
4760 a pointer to the count of instructions created so far, an
4761 expression, the name of the instruction to build, an operand format
4762 string, and corresponding arguments. */
4765 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4767 const struct mips_opcode *mo = NULL;
4768 bfd_reloc_code_real_type r[3];
4769 const struct mips_opcode *amo;
4770 struct hash_control *hash;
4771 struct mips_cl_insn insn;
4774 va_start (args, fmt);
4776 if (mips_opts.mips16)
4778 mips16_macro_build (ep, name, fmt, &args);
4783 r[0] = BFD_RELOC_UNUSED;
4784 r[1] = BFD_RELOC_UNUSED;
4785 r[2] = BFD_RELOC_UNUSED;
4786 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4787 amo = (struct mips_opcode *) hash_find (hash, name);
4789 gas_assert (strcmp (name, amo->name) == 0);
4793 /* Search until we get a match for NAME. It is assumed here that
4794 macros will never generate MDMX, MIPS-3D, or MT instructions.
4795 We try to match an instruction that fulfils the branch delay
4796 slot instruction length requirement (if any) of the previous
4797 instruction. While doing this we record the first instruction
4798 seen that matches all the other conditions and use it anyway
4799 if the requirement cannot be met; we will issue an appropriate
4800 warning later on. */
4801 if (strcmp (fmt, amo->args) == 0
4802 && amo->pinfo != INSN_MACRO
4803 && is_opcode_valid (amo)
4804 && is_size_valid (amo))
4806 if (is_delay_slot_valid (amo))
4816 gas_assert (amo->name);
4818 while (strcmp (name, amo->name) == 0);
4821 create_insn (&insn, mo);
4839 INSERT_OPERAND (mips_opts.micromips,
4840 EXTLSB, insn, va_arg (args, int));
4845 /* Note that in the macro case, these arguments are already
4846 in MSB form. (When handling the instruction in the
4847 non-macro case, these arguments are sizes from which
4848 MSB values must be calculated.) */
4849 INSERT_OPERAND (mips_opts.micromips,
4850 INSMSB, insn, va_arg (args, int));
4856 /* Note that in the macro case, these arguments are already
4857 in MSBD form. (When handling the instruction in the
4858 non-macro case, these arguments are sizes from which
4859 MSBD values must be calculated.) */
4860 INSERT_OPERAND (mips_opts.micromips,
4861 EXTMSBD, insn, va_arg (args, int));
4865 gas_assert (!mips_opts.micromips);
4866 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4875 gas_assert (!mips_opts.micromips);
4876 INSERT_OPERAND (0, BP, insn, va_arg (args, int));
4880 gas_assert (mips_opts.micromips);
4884 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4888 gas_assert (!mips_opts.micromips);
4889 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4893 gas_assert (!mips_opts.micromips);
4895 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4899 if (mips_opts.micromips)
4900 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4902 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4906 gas_assert (!mips_opts.micromips);
4908 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
4912 gas_assert (!mips_opts.micromips);
4914 int tmp = va_arg (args, int);
4916 INSERT_OPERAND (0, RT, insn, tmp);
4917 INSERT_OPERAND (0, RD, insn, tmp);
4923 gas_assert (!mips_opts.micromips);
4924 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
4931 INSERT_OPERAND (mips_opts.micromips,
4932 SHAMT, insn, va_arg (args, int));
4936 gas_assert (!mips_opts.micromips);
4937 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
4941 gas_assert (!mips_opts.micromips);
4942 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
4946 gas_assert (!mips_opts.micromips);
4947 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4951 gas_assert (!mips_opts.micromips);
4952 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
4959 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
4964 macro_read_relocs (&args, r);
4965 gas_assert (*r == BFD_RELOC_GPREL16
4966 || *r == BFD_RELOC_MIPS_HIGHER
4967 || *r == BFD_RELOC_HI16_S
4968 || *r == BFD_RELOC_LO16
4969 || *r == BFD_RELOC_MIPS_GOT_OFST);
4973 macro_read_relocs (&args, r);
4977 macro_read_relocs (&args, r);
4978 gas_assert (ep != NULL
4979 && (ep->X_op == O_constant
4980 || (ep->X_op == O_symbol
4981 && (*r == BFD_RELOC_MIPS_HIGHEST
4982 || *r == BFD_RELOC_HI16_S
4983 || *r == BFD_RELOC_HI16
4984 || *r == BFD_RELOC_GPREL16
4985 || *r == BFD_RELOC_MIPS_GOT_HI16
4986 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4990 gas_assert (ep != NULL);
4993 * This allows macro() to pass an immediate expression for
4994 * creating short branches without creating a symbol.
4996 * We don't allow branch relaxation for these branches, as
4997 * they should only appear in ".set nomacro" anyway.
4999 if (ep->X_op == O_constant)
5001 /* For microMIPS we always use relocations for branches.
5002 So we should not resolve immediate values. */
5003 gas_assert (!mips_opts.micromips);
5005 if ((ep->X_add_number & 3) != 0)
5006 as_bad (_("branch to misaligned address (0x%lx)"),
5007 (unsigned long) ep->X_add_number);
5008 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5009 as_bad (_("branch address range overflow (0x%lx)"),
5010 (unsigned long) ep->X_add_number);
5011 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5015 *r = BFD_RELOC_16_PCREL_S2;
5019 gas_assert (ep != NULL);
5020 *r = BFD_RELOC_MIPS_JMP;
5024 gas_assert (!mips_opts.micromips);
5025 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5029 INSERT_OPERAND (mips_opts.micromips,
5030 CACHE, insn, va_arg (args, unsigned long));
5034 gas_assert (mips_opts.micromips);
5035 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5039 gas_assert (mips_opts.micromips);
5040 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5044 gas_assert (mips_opts.micromips);
5045 INSERT_OPERAND (1, OFFSET12, insn, va_arg (args, unsigned long));
5049 gas_assert (mips_opts.micromips);
5050 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5053 case 'm': /* Opcode extension character. */
5054 gas_assert (mips_opts.micromips);
5058 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5062 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5066 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5080 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5082 append_insn (&insn, ep, r, TRUE);
5086 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5089 struct mips_opcode *mo;
5090 struct mips_cl_insn insn;
5091 bfd_reloc_code_real_type r[3]
5092 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5094 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5096 gas_assert (strcmp (name, mo->name) == 0);
5098 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5101 gas_assert (mo->name);
5102 gas_assert (strcmp (name, mo->name) == 0);
5105 create_insn (&insn, mo);
5123 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5128 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5132 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5136 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5146 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5153 regno = va_arg (*args, int);
5154 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5155 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5176 gas_assert (ep != NULL);
5178 if (ep->X_op != O_constant)
5179 *r = (int) BFD_RELOC_UNUSED + c;
5182 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
5183 FALSE, &insn.insn_opcode, &insn.use_extend,
5186 *r = BFD_RELOC_UNUSED;
5192 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5199 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5201 append_insn (&insn, ep, r, TRUE);
5205 * Sign-extend 32-bit mode constants that have bit 31 set and all
5206 * higher bits unset.
5209 normalize_constant_expr (expressionS *ex)
5211 if (ex->X_op == O_constant
5212 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5213 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5218 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5219 * all higher bits unset.
5222 normalize_address_expr (expressionS *ex)
5224 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5225 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5226 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5227 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5232 * Generate a "jalr" instruction with a relocation hint to the called
5233 * function. This occurs in NewABI PIC code.
5236 macro_build_jalr (expressionS *ep, int cprestore)
5238 static const bfd_reloc_code_real_type jalr_relocs[2]
5239 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5240 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5244 if (MIPS_JALR_HINT_P (ep))
5249 if (!mips_opts.micromips)
5250 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5253 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5254 if (MIPS_JALR_HINT_P (ep))
5255 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5257 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5259 if (MIPS_JALR_HINT_P (ep))
5260 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5264 * Generate a "lui" instruction.
5267 macro_build_lui (expressionS *ep, int regnum)
5269 gas_assert (! mips_opts.mips16);
5271 if (ep->X_op != O_constant)
5273 gas_assert (ep->X_op == O_symbol);
5274 /* _gp_disp is a special case, used from s_cpload.
5275 __gnu_local_gp is used if mips_no_shared. */
5276 gas_assert (mips_pic == NO_PIC
5278 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5279 || (! mips_in_shared
5280 && strcmp (S_GET_NAME (ep->X_add_symbol),
5281 "__gnu_local_gp") == 0));
5284 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5287 /* Generate a sequence of instructions to do a load or store from a constant
5288 offset off of a base register (breg) into/from a target register (treg),
5289 using AT if necessary. */
5291 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5292 int treg, int breg, int dbl)
5294 gas_assert (ep->X_op == O_constant);
5296 /* Sign-extending 32-bit constants makes their handling easier. */
5298 normalize_constant_expr (ep);
5300 /* Right now, this routine can only handle signed 32-bit constants. */
5301 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5302 as_warn (_("operand overflow"));
5304 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5306 /* Signed 16-bit offset will fit in the op. Easy! */
5307 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5311 /* 32-bit offset, need multiple instructions and AT, like:
5312 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5313 addu $tempreg,$tempreg,$breg
5314 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5315 to handle the complete offset. */
5316 macro_build_lui (ep, AT);
5317 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5318 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5321 as_bad (_("Macro used $at after \".set noat\""));
5326 * Generates code to set the $at register to true (one)
5327 * if reg is less than the immediate expression.
5330 set_at (int reg, int unsignedp)
5332 if (imm_expr.X_op == O_constant
5333 && imm_expr.X_add_number >= -0x8000
5334 && imm_expr.X_add_number < 0x8000)
5335 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5336 AT, reg, BFD_RELOC_LO16);
5339 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5340 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5344 /* Warn if an expression is not a constant. */
5347 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5349 if (ex->X_op == O_big)
5350 as_bad (_("unsupported large constant"));
5351 else if (ex->X_op != O_constant)
5352 as_bad (_("Instruction %s requires absolute expression"),
5355 if (HAVE_32BIT_GPRS)
5356 normalize_constant_expr (ex);
5359 /* Count the leading zeroes by performing a binary chop. This is a
5360 bulky bit of source, but performance is a LOT better for the
5361 majority of values than a simple loop to count the bits:
5362 for (lcnt = 0; (lcnt < 32); lcnt++)
5363 if ((v) & (1 << (31 - lcnt)))
5365 However it is not code size friendly, and the gain will drop a bit
5366 on certain cached systems.
5368 #define COUNT_TOP_ZEROES(v) \
5369 (((v) & ~0xffff) == 0 \
5370 ? ((v) & ~0xff) == 0 \
5371 ? ((v) & ~0xf) == 0 \
5372 ? ((v) & ~0x3) == 0 \
5373 ? ((v) & ~0x1) == 0 \
5378 : ((v) & ~0x7) == 0 \
5381 : ((v) & ~0x3f) == 0 \
5382 ? ((v) & ~0x1f) == 0 \
5385 : ((v) & ~0x7f) == 0 \
5388 : ((v) & ~0xfff) == 0 \
5389 ? ((v) & ~0x3ff) == 0 \
5390 ? ((v) & ~0x1ff) == 0 \
5393 : ((v) & ~0x7ff) == 0 \
5396 : ((v) & ~0x3fff) == 0 \
5397 ? ((v) & ~0x1fff) == 0 \
5400 : ((v) & ~0x7fff) == 0 \
5403 : ((v) & ~0xffffff) == 0 \
5404 ? ((v) & ~0xfffff) == 0 \
5405 ? ((v) & ~0x3ffff) == 0 \
5406 ? ((v) & ~0x1ffff) == 0 \
5409 : ((v) & ~0x7ffff) == 0 \
5412 : ((v) & ~0x3fffff) == 0 \
5413 ? ((v) & ~0x1fffff) == 0 \
5416 : ((v) & ~0x7fffff) == 0 \
5419 : ((v) & ~0xfffffff) == 0 \
5420 ? ((v) & ~0x3ffffff) == 0 \
5421 ? ((v) & ~0x1ffffff) == 0 \
5424 : ((v) & ~0x7ffffff) == 0 \
5427 : ((v) & ~0x3fffffff) == 0 \
5428 ? ((v) & ~0x1fffffff) == 0 \
5431 : ((v) & ~0x7fffffff) == 0 \
5436 * This routine generates the least number of instructions necessary to load
5437 * an absolute expression value into a register.
5440 load_register (int reg, expressionS *ep, int dbl)
5443 expressionS hi32, lo32;
5445 if (ep->X_op != O_big)
5447 gas_assert (ep->X_op == O_constant);
5449 /* Sign-extending 32-bit constants makes their handling easier. */
5451 normalize_constant_expr (ep);
5453 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5455 /* We can handle 16 bit signed values with an addiu to
5456 $zero. No need to ever use daddiu here, since $zero and
5457 the result are always correct in 32 bit mode. */
5458 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5461 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5463 /* We can handle 16 bit unsigned values with an ori to
5465 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5468 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5470 /* 32 bit values require an lui. */
5471 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5472 if ((ep->X_add_number & 0xffff) != 0)
5473 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5478 /* The value is larger than 32 bits. */
5480 if (!dbl || HAVE_32BIT_GPRS)
5484 sprintf_vma (value, ep->X_add_number);
5485 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5486 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5490 if (ep->X_op != O_big)
5493 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5494 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5495 hi32.X_add_number &= 0xffffffff;
5497 lo32.X_add_number &= 0xffffffff;
5501 gas_assert (ep->X_add_number > 2);
5502 if (ep->X_add_number == 3)
5503 generic_bignum[3] = 0;
5504 else if (ep->X_add_number > 4)
5505 as_bad (_("Number larger than 64 bits"));
5506 lo32.X_op = O_constant;
5507 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5508 hi32.X_op = O_constant;
5509 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5512 if (hi32.X_add_number == 0)
5517 unsigned long hi, lo;
5519 if (hi32.X_add_number == (offsetT) 0xffffffff)
5521 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5523 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5526 if (lo32.X_add_number & 0x80000000)
5528 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5529 if (lo32.X_add_number & 0xffff)
5530 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5535 /* Check for 16bit shifted constant. We know that hi32 is
5536 non-zero, so start the mask on the first bit of the hi32
5541 unsigned long himask, lomask;
5545 himask = 0xffff >> (32 - shift);
5546 lomask = (0xffff << shift) & 0xffffffff;
5550 himask = 0xffff << (shift - 32);
5553 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5554 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5558 tmp.X_op = O_constant;
5560 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5561 | (lo32.X_add_number >> shift));
5563 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5564 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5565 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5566 reg, reg, (shift >= 32) ? shift - 32 : shift);
5571 while (shift <= (64 - 16));
5573 /* Find the bit number of the lowest one bit, and store the
5574 shifted value in hi/lo. */
5575 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5576 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5580 while ((lo & 1) == 0)
5585 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5591 while ((hi & 1) == 0)
5600 /* Optimize if the shifted value is a (power of 2) - 1. */
5601 if ((hi == 0 && ((lo + 1) & lo) == 0)
5602 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5604 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5609 /* This instruction will set the register to be all
5611 tmp.X_op = O_constant;
5612 tmp.X_add_number = (offsetT) -1;
5613 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5617 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5618 reg, reg, (bit >= 32) ? bit - 32 : bit);
5620 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5621 reg, reg, (shift >= 32) ? shift - 32 : shift);
5626 /* Sign extend hi32 before calling load_register, because we can
5627 generally get better code when we load a sign extended value. */
5628 if ((hi32.X_add_number & 0x80000000) != 0)
5629 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5630 load_register (reg, &hi32, 0);
5633 if ((lo32.X_add_number & 0xffff0000) == 0)
5637 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5645 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5647 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5648 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5654 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5658 mid16.X_add_number >>= 16;
5659 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5660 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5663 if ((lo32.X_add_number & 0xffff) != 0)
5664 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5668 load_delay_nop (void)
5670 if (!gpr_interlocks)
5671 macro_build (NULL, "nop", "");
5674 /* Load an address into a register. */
5677 load_address (int reg, expressionS *ep, int *used_at)
5679 if (ep->X_op != O_constant
5680 && ep->X_op != O_symbol)
5682 as_bad (_("expression too complex"));
5683 ep->X_op = O_constant;
5686 if (ep->X_op == O_constant)
5688 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5692 if (mips_pic == NO_PIC)
5694 /* If this is a reference to a GP relative symbol, we want
5695 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5697 lui $reg,<sym> (BFD_RELOC_HI16_S)
5698 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5699 If we have an addend, we always use the latter form.
5701 With 64bit address space and a usable $at we want
5702 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5703 lui $at,<sym> (BFD_RELOC_HI16_S)
5704 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5705 daddiu $at,<sym> (BFD_RELOC_LO16)
5709 If $at is already in use, we use a path which is suboptimal
5710 on superscalar processors.
5711 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5712 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5714 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5716 daddiu $reg,<sym> (BFD_RELOC_LO16)
5718 For GP relative symbols in 64bit address space we can use
5719 the same sequence as in 32bit address space. */
5720 if (HAVE_64BIT_SYMBOLS)
5722 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5723 && !nopic_need_relax (ep->X_add_symbol, 1))
5725 relax_start (ep->X_add_symbol);
5726 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5727 mips_gp_register, BFD_RELOC_GPREL16);
5731 if (*used_at == 0 && mips_opts.at)
5733 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5734 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5735 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5736 BFD_RELOC_MIPS_HIGHER);
5737 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5738 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5739 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5744 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5745 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5746 BFD_RELOC_MIPS_HIGHER);
5747 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5748 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5749 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5750 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5753 if (mips_relax.sequence)
5758 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5759 && !nopic_need_relax (ep->X_add_symbol, 1))
5761 relax_start (ep->X_add_symbol);
5762 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5763 mips_gp_register, BFD_RELOC_GPREL16);
5766 macro_build_lui (ep, reg);
5767 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5768 reg, reg, BFD_RELOC_LO16);
5769 if (mips_relax.sequence)
5773 else if (!mips_big_got)
5777 /* If this is a reference to an external symbol, we want
5778 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5780 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5782 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5783 If there is a constant, it must be added in after.
5785 If we have NewABI, we want
5786 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5787 unless we're referencing a global symbol with a non-zero
5788 offset, in which case cst must be added separately. */
5791 if (ep->X_add_number)
5793 ex.X_add_number = ep->X_add_number;
5794 ep->X_add_number = 0;
5795 relax_start (ep->X_add_symbol);
5796 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5797 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5798 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5799 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5800 ex.X_op = O_constant;
5801 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5802 reg, reg, BFD_RELOC_LO16);
5803 ep->X_add_number = ex.X_add_number;
5806 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5807 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5808 if (mips_relax.sequence)
5813 ex.X_add_number = ep->X_add_number;
5814 ep->X_add_number = 0;
5815 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5816 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5818 relax_start (ep->X_add_symbol);
5820 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5824 if (ex.X_add_number != 0)
5826 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5827 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5828 ex.X_op = O_constant;
5829 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5830 reg, reg, BFD_RELOC_LO16);
5834 else if (mips_big_got)
5838 /* This is the large GOT case. If this is a reference to an
5839 external symbol, we want
5840 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5842 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5844 Otherwise, for a reference to a local symbol in old ABI, we want
5845 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5847 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5848 If there is a constant, it must be added in after.
5850 In the NewABI, for local symbols, with or without offsets, we want:
5851 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5852 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5856 ex.X_add_number = ep->X_add_number;
5857 ep->X_add_number = 0;
5858 relax_start (ep->X_add_symbol);
5859 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5860 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5861 reg, reg, mips_gp_register);
5862 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5863 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5864 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5865 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5866 else if (ex.X_add_number)
5868 ex.X_op = O_constant;
5869 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5873 ep->X_add_number = ex.X_add_number;
5875 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5876 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5877 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5878 BFD_RELOC_MIPS_GOT_OFST);
5883 ex.X_add_number = ep->X_add_number;
5884 ep->X_add_number = 0;
5885 relax_start (ep->X_add_symbol);
5886 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5887 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5888 reg, reg, mips_gp_register);
5889 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5890 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5892 if (reg_needs_delay (mips_gp_register))
5894 /* We need a nop before loading from $gp. This special
5895 check is required because the lui which starts the main
5896 instruction stream does not refer to $gp, and so will not
5897 insert the nop which may be required. */
5898 macro_build (NULL, "nop", "");
5900 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5901 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5903 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5907 if (ex.X_add_number != 0)
5909 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5910 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5911 ex.X_op = O_constant;
5912 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5920 if (!mips_opts.at && *used_at == 1)
5921 as_bad (_("Macro used $at after \".set noat\""));
5924 /* Move the contents of register SOURCE into register DEST. */
5927 move_register (int dest, int source)
5929 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5930 instruction specifically requires a 32-bit one. */
5931 if (mips_opts.micromips
5932 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5933 macro_build (NULL, "move", "mp,mj", dest, source );
5935 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5939 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5940 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5941 The two alternatives are:
5943 Global symbol Local sybmol
5944 ------------- ------------
5945 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5947 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5949 load_got_offset emits the first instruction and add_got_offset
5950 emits the second for a 16-bit offset or add_got_offset_hilo emits
5951 a sequence to add a 32-bit offset using a scratch register. */
5954 load_got_offset (int dest, expressionS *local)
5959 global.X_add_number = 0;
5961 relax_start (local->X_add_symbol);
5962 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5963 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5965 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5966 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5971 add_got_offset (int dest, expressionS *local)
5975 global.X_op = O_constant;
5976 global.X_op_symbol = NULL;
5977 global.X_add_symbol = NULL;
5978 global.X_add_number = local->X_add_number;
5980 relax_start (local->X_add_symbol);
5981 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5982 dest, dest, BFD_RELOC_LO16);
5984 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5989 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5992 int hold_mips_optimize;
5994 global.X_op = O_constant;
5995 global.X_op_symbol = NULL;
5996 global.X_add_symbol = NULL;
5997 global.X_add_number = local->X_add_number;
5999 relax_start (local->X_add_symbol);
6000 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6002 /* Set mips_optimize around the lui instruction to avoid
6003 inserting an unnecessary nop after the lw. */
6004 hold_mips_optimize = mips_optimize;
6006 macro_build_lui (&global, tmp);
6007 mips_optimize = hold_mips_optimize;
6008 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6011 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6014 /* Emit a sequence of instructions to emulate a branch likely operation.
6015 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6016 is its complementing branch with the original condition negated.
6017 CALL is set if the original branch specified the link operation.
6018 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6020 Code like this is produced in the noreorder mode:
6025 delay slot (executed only if branch taken)
6033 delay slot (executed only if branch taken)
6036 In the reorder mode the delay slot would be filled with a nop anyway,
6037 so code produced is simply:
6042 This function is used when producing code for the microMIPS ASE that
6043 does not implement branch likely instructions in hardware. */
6046 macro_build_branch_likely (const char *br, const char *brneg,
6047 int call, expressionS *ep, const char *fmt,
6048 unsigned int sreg, unsigned int treg)
6050 int noreorder = mips_opts.noreorder;
6053 gas_assert (mips_opts.micromips);
6057 micromips_label_expr (&expr1);
6058 macro_build (&expr1, brneg, fmt, sreg, treg);
6059 macro_build (NULL, "nop", "");
6060 macro_build (ep, call ? "bal" : "b", "p");
6062 /* Set to true so that append_insn adds a label. */
6063 emit_branch_likely_macro = TRUE;
6067 macro_build (ep, br, fmt, sreg, treg);
6068 macro_build (NULL, "nop", "");
6073 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6074 the condition code tested. EP specifies the branch target. */
6077 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6104 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6107 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6108 the register tested. EP specifies the branch target. */
6111 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6113 const char *brneg = NULL;
6123 br = mips_opts.micromips ? "bgez" : "bgezl";
6127 gas_assert (mips_opts.micromips);
6136 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6143 br = mips_opts.micromips ? "blez" : "blezl";
6150 br = mips_opts.micromips ? "bltz" : "bltzl";
6154 gas_assert (mips_opts.micromips);
6162 if (mips_opts.micromips && brneg)
6163 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6165 macro_build (ep, br, "s,p", sreg);
6168 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6169 TREG as the registers tested. EP specifies the branch target. */
6172 macro_build_branch_rsrt (int type, expressionS *ep,
6173 unsigned int sreg, unsigned int treg)
6175 const char *brneg = NULL;
6187 br = mips_opts.micromips ? "beq" : "beql";
6196 br = mips_opts.micromips ? "bne" : "bnel";
6202 if (mips_opts.micromips && brneg)
6203 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6205 macro_build (ep, br, "s,t,p", sreg, treg);
6210 * This routine implements the seemingly endless macro or synthesized
6211 * instructions and addressing modes in the mips assembly language. Many
6212 * of these macros are simple and are similar to each other. These could
6213 * probably be handled by some kind of table or grammar approach instead of
6214 * this verbose method. Others are not simple macros but are more like
6215 * optimizing code generation.
6216 * One interesting optimization is when several store macros appear
6217 * consecutively that would load AT with the upper half of the same address.
6218 * The ensuing load upper instructions are ommited. This implies some kind
6219 * of global optimization. We currently only optimize within a single macro.
6220 * For many of the load and store macros if the address is specified as a
6221 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6222 * first load register 'at' with zero and use it as the base register. The
6223 * mips assembler simply uses register $zero. Just one tiny optimization
6227 macro (struct mips_cl_insn *ip)
6229 unsigned int treg, sreg, dreg, breg;
6230 unsigned int tempreg;
6233 expressionS label_expr;
6251 bfd_reloc_code_real_type r;
6252 int hold_mips_optimize;
6254 gas_assert (! mips_opts.mips16);
6256 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6257 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6258 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6259 mask = ip->insn_mo->mask;
6261 label_expr.X_op = O_constant;
6262 label_expr.X_op_symbol = NULL;
6263 label_expr.X_add_symbol = NULL;
6264 label_expr.X_add_number = 0;
6266 expr1.X_op = O_constant;
6267 expr1.X_op_symbol = NULL;
6268 expr1.X_add_symbol = NULL;
6269 expr1.X_add_number = 1;
6284 if (mips_opts.micromips)
6285 micromips_label_expr (&label_expr);
6287 label_expr.X_add_number = 8;
6288 macro_build (&label_expr, "bgez", "s,p", sreg);
6290 macro_build (NULL, "nop", "");
6292 move_register (dreg, sreg);
6293 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6294 if (mips_opts.micromips)
6295 micromips_add_label ();
6312 if (!mips_opts.micromips)
6314 if (imm_expr.X_op == O_constant
6315 && imm_expr.X_add_number >= -0x200
6316 && imm_expr.X_add_number < 0x200)
6318 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6327 if (imm_expr.X_op == O_constant
6328 && imm_expr.X_add_number >= -0x8000
6329 && imm_expr.X_add_number < 0x8000)
6331 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6336 load_register (AT, &imm_expr, dbl);
6337 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6356 if (imm_expr.X_op == O_constant
6357 && imm_expr.X_add_number >= 0
6358 && imm_expr.X_add_number < 0x10000)
6360 if (mask != M_NOR_I)
6361 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6364 macro_build (&imm_expr, "ori", "t,r,i",
6365 treg, sreg, BFD_RELOC_LO16);
6366 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6372 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6373 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6377 switch (imm_expr.X_add_number)
6380 macro_build (NULL, "nop", "");
6383 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6386 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6387 (int) imm_expr.X_add_number);
6396 gas_assert (mips_opts.micromips);
6397 macro_build_branch_ccl (mask, &offset_expr,
6398 EXTRACT_OPERAND (1, BCC, *ip));
6405 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6411 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6416 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6423 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6425 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6429 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6430 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6431 &offset_expr, AT, ZERO);
6441 macro_build_branch_rs (mask, &offset_expr, sreg);
6447 /* Check for > max integer. */
6448 maxnum = 0x7fffffff;
6449 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6456 if (imm_expr.X_op == O_constant
6457 && imm_expr.X_add_number >= maxnum
6458 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6461 /* Result is always false. */
6463 macro_build (NULL, "nop", "");
6465 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6468 if (imm_expr.X_op != O_constant)
6469 as_bad (_("Unsupported large constant"));
6470 ++imm_expr.X_add_number;
6474 if (mask == M_BGEL_I)
6476 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6478 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6479 &offset_expr, sreg);
6482 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6484 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6485 &offset_expr, sreg);
6488 maxnum = 0x7fffffff;
6489 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6496 maxnum = - maxnum - 1;
6497 if (imm_expr.X_op == O_constant
6498 && imm_expr.X_add_number <= maxnum
6499 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6502 /* result is always true */
6503 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6504 macro_build (&offset_expr, "b", "p");
6509 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6510 &offset_expr, AT, ZERO);
6519 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6520 &offset_expr, ZERO, treg);
6524 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6525 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6526 &offset_expr, AT, ZERO);
6535 && imm_expr.X_op == O_constant
6536 && imm_expr.X_add_number == -1))
6538 if (imm_expr.X_op != O_constant)
6539 as_bad (_("Unsupported large constant"));
6540 ++imm_expr.X_add_number;
6544 if (mask == M_BGEUL_I)
6546 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6548 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6549 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6550 &offset_expr, sreg, ZERO);
6555 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6556 &offset_expr, AT, ZERO);
6564 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6566 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6570 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6571 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6572 &offset_expr, AT, ZERO);
6580 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6581 &offset_expr, sreg, ZERO);
6587 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6588 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6589 &offset_expr, AT, ZERO);
6597 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6599 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6603 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6604 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6605 &offset_expr, AT, ZERO);
6612 maxnum = 0x7fffffff;
6613 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6620 if (imm_expr.X_op == O_constant
6621 && imm_expr.X_add_number >= maxnum
6622 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6624 if (imm_expr.X_op != O_constant)
6625 as_bad (_("Unsupported large constant"));
6626 ++imm_expr.X_add_number;
6630 if (mask == M_BLTL_I)
6632 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6633 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6634 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6635 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6640 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6641 &offset_expr, AT, ZERO);
6649 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6650 &offset_expr, sreg, ZERO);
6656 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6657 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6658 &offset_expr, AT, ZERO);
6667 && imm_expr.X_op == O_constant
6668 && imm_expr.X_add_number == -1))
6670 if (imm_expr.X_op != O_constant)
6671 as_bad (_("Unsupported large constant"));
6672 ++imm_expr.X_add_number;
6676 if (mask == M_BLTUL_I)
6678 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6680 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6681 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6682 &offset_expr, sreg, ZERO);
6687 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6688 &offset_expr, AT, ZERO);
6696 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6698 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6702 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6703 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6704 &offset_expr, AT, ZERO);
6714 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6715 &offset_expr, ZERO, treg);
6719 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6720 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6721 &offset_expr, AT, ZERO);
6727 /* Use unsigned arithmetic. */
6731 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6733 as_bad (_("Unsupported large constant"));
6738 pos = imm_expr.X_add_number;
6739 size = imm2_expr.X_add_number;
6744 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6747 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6749 as_bad (_("Improper extract size (%lu, position %lu)"),
6750 (unsigned long) size, (unsigned long) pos);
6754 if (size <= 32 && pos < 32)
6759 else if (size <= 32)
6769 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6776 /* Use unsigned arithmetic. */
6780 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6782 as_bad (_("Unsupported large constant"));
6787 pos = imm_expr.X_add_number;
6788 size = imm2_expr.X_add_number;
6793 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6796 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6798 as_bad (_("Improper insert size (%lu, position %lu)"),
6799 (unsigned long) size, (unsigned long) pos);
6803 if (pos < 32 && (pos + size - 1) < 32)
6818 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6819 (int) (pos + size - 1));
6835 as_warn (_("Divide by zero."));
6837 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6839 macro_build (NULL, "break", BRK_FMT, 7);
6846 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6847 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6851 if (mips_opts.micromips)
6852 micromips_label_expr (&label_expr);
6854 label_expr.X_add_number = 8;
6855 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6856 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6857 macro_build (NULL, "break", BRK_FMT, 7);
6858 if (mips_opts.micromips)
6859 micromips_add_label ();
6861 expr1.X_add_number = -1;
6863 load_register (AT, &expr1, dbl);
6864 if (mips_opts.micromips)
6865 micromips_label_expr (&label_expr);
6867 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6868 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6871 expr1.X_add_number = 1;
6872 load_register (AT, &expr1, dbl);
6873 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6877 expr1.X_add_number = 0x80000000;
6878 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6882 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6883 /* We want to close the noreorder block as soon as possible, so
6884 that later insns are available for delay slot filling. */
6889 if (mips_opts.micromips)
6890 micromips_label_expr (&label_expr);
6892 label_expr.X_add_number = 8;
6893 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6894 macro_build (NULL, "nop", "");
6896 /* We want to close the noreorder block as soon as possible, so
6897 that later insns are available for delay slot filling. */
6900 macro_build (NULL, "break", BRK_FMT, 6);
6902 if (mips_opts.micromips)
6903 micromips_add_label ();
6904 macro_build (NULL, s, MFHL_FMT, dreg);
6943 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6945 as_warn (_("Divide by zero."));
6947 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6949 macro_build (NULL, "break", BRK_FMT, 7);
6952 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6954 if (strcmp (s2, "mflo") == 0)
6955 move_register (dreg, sreg);
6957 move_register (dreg, ZERO);
6960 if (imm_expr.X_op == O_constant
6961 && imm_expr.X_add_number == -1
6962 && s[strlen (s) - 1] != 'u')
6964 if (strcmp (s2, "mflo") == 0)
6966 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
6969 move_register (dreg, ZERO);
6974 load_register (AT, &imm_expr, dbl);
6975 macro_build (NULL, s, "z,s,t", sreg, AT);
6976 macro_build (NULL, s2, MFHL_FMT, dreg);
6998 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6999 macro_build (NULL, s, "z,s,t", sreg, treg);
7000 /* We want to close the noreorder block as soon as possible, so
7001 that later insns are available for delay slot filling. */
7006 if (mips_opts.micromips)
7007 micromips_label_expr (&label_expr);
7009 label_expr.X_add_number = 8;
7010 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7011 macro_build (NULL, s, "z,s,t", sreg, treg);
7013 /* We want to close the noreorder block as soon as possible, so
7014 that later insns are available for delay slot filling. */
7016 macro_build (NULL, "break", BRK_FMT, 7);
7017 if (mips_opts.micromips)
7018 micromips_add_label ();
7020 macro_build (NULL, s2, MFHL_FMT, dreg);
7032 /* Load the address of a symbol into a register. If breg is not
7033 zero, we then add a base register to it. */
7035 if (dbl && HAVE_32BIT_GPRS)
7036 as_warn (_("dla used to load 32-bit register"));
7038 if (!dbl && HAVE_64BIT_OBJECTS)
7039 as_warn (_("la used to load 64-bit address"));
7041 if (offset_expr.X_op == O_constant
7042 && offset_expr.X_add_number >= -0x8000
7043 && offset_expr.X_add_number < 0x8000)
7045 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7046 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7050 if (mips_opts.at && (treg == breg))
7060 if (offset_expr.X_op != O_symbol
7061 && offset_expr.X_op != O_constant)
7063 as_bad (_("Expression too complex"));
7064 offset_expr.X_op = O_constant;
7067 if (offset_expr.X_op == O_constant)
7068 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7069 else if (mips_pic == NO_PIC)
7071 /* If this is a reference to a GP relative symbol, we want
7072 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7074 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7075 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7076 If we have a constant, we need two instructions anyhow,
7077 so we may as well always use the latter form.
7079 With 64bit address space and a usable $at we want
7080 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7081 lui $at,<sym> (BFD_RELOC_HI16_S)
7082 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7083 daddiu $at,<sym> (BFD_RELOC_LO16)
7085 daddu $tempreg,$tempreg,$at
7087 If $at is already in use, we use a path which is suboptimal
7088 on superscalar processors.
7089 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7090 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7092 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7094 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7096 For GP relative symbols in 64bit address space we can use
7097 the same sequence as in 32bit address space. */
7098 if (HAVE_64BIT_SYMBOLS)
7100 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7101 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7103 relax_start (offset_expr.X_add_symbol);
7104 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7105 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7109 if (used_at == 0 && mips_opts.at)
7111 macro_build (&offset_expr, "lui", LUI_FMT,
7112 tempreg, BFD_RELOC_MIPS_HIGHEST);
7113 macro_build (&offset_expr, "lui", LUI_FMT,
7114 AT, BFD_RELOC_HI16_S);
7115 macro_build (&offset_expr, "daddiu", "t,r,j",
7116 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7117 macro_build (&offset_expr, "daddiu", "t,r,j",
7118 AT, AT, BFD_RELOC_LO16);
7119 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7120 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7125 macro_build (&offset_expr, "lui", LUI_FMT,
7126 tempreg, BFD_RELOC_MIPS_HIGHEST);
7127 macro_build (&offset_expr, "daddiu", "t,r,j",
7128 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7129 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7130 macro_build (&offset_expr, "daddiu", "t,r,j",
7131 tempreg, tempreg, BFD_RELOC_HI16_S);
7132 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7133 macro_build (&offset_expr, "daddiu", "t,r,j",
7134 tempreg, tempreg, BFD_RELOC_LO16);
7137 if (mips_relax.sequence)
7142 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7143 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7145 relax_start (offset_expr.X_add_symbol);
7146 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7147 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7150 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7151 as_bad (_("Offset too large"));
7152 macro_build_lui (&offset_expr, tempreg);
7153 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7154 tempreg, tempreg, BFD_RELOC_LO16);
7155 if (mips_relax.sequence)
7159 else if (!mips_big_got && !HAVE_NEWABI)
7161 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7163 /* If this is a reference to an external symbol, and there
7164 is no constant, we want
7165 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7166 or for lca or if tempreg is PIC_CALL_REG
7167 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7168 For a local symbol, we want
7169 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7171 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7173 If we have a small constant, and this is a reference to
7174 an external symbol, we want
7175 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7177 addiu $tempreg,$tempreg,<constant>
7178 For a local symbol, we want the same instruction
7179 sequence, but we output a BFD_RELOC_LO16 reloc on the
7182 If we have a large constant, and this is a reference to
7183 an external symbol, we want
7184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7185 lui $at,<hiconstant>
7186 addiu $at,$at,<loconstant>
7187 addu $tempreg,$tempreg,$at
7188 For a local symbol, we want the same instruction
7189 sequence, but we output a BFD_RELOC_LO16 reloc on the
7193 if (offset_expr.X_add_number == 0)
7195 if (mips_pic == SVR4_PIC
7197 && (call || tempreg == PIC_CALL_REG))
7198 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7200 relax_start (offset_expr.X_add_symbol);
7201 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7202 lw_reloc_type, mips_gp_register);
7205 /* We're going to put in an addu instruction using
7206 tempreg, so we may as well insert the nop right
7211 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7212 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7214 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7215 tempreg, tempreg, BFD_RELOC_LO16);
7217 /* FIXME: If breg == 0, and the next instruction uses
7218 $tempreg, then if this variant case is used an extra
7219 nop will be generated. */
7221 else if (offset_expr.X_add_number >= -0x8000
7222 && offset_expr.X_add_number < 0x8000)
7224 load_got_offset (tempreg, &offset_expr);
7226 add_got_offset (tempreg, &offset_expr);
7230 expr1.X_add_number = offset_expr.X_add_number;
7231 offset_expr.X_add_number =
7232 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
7233 load_got_offset (tempreg, &offset_expr);
7234 offset_expr.X_add_number = expr1.X_add_number;
7235 /* If we are going to add in a base register, and the
7236 target register and the base register are the same,
7237 then we are using AT as a temporary register. Since
7238 we want to load the constant into AT, we add our
7239 current AT (from the global offset table) and the
7240 register into the register now, and pretend we were
7241 not using a base register. */
7245 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7250 add_got_offset_hilo (tempreg, &offset_expr, AT);
7254 else if (!mips_big_got && HAVE_NEWABI)
7256 int add_breg_early = 0;
7258 /* If this is a reference to an external, and there is no
7259 constant, or local symbol (*), with or without a
7261 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7262 or for lca or if tempreg is PIC_CALL_REG
7263 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7265 If we have a small constant, and this is a reference to
7266 an external symbol, we want
7267 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7268 addiu $tempreg,$tempreg,<constant>
7270 If we have a large constant, and this is a reference to
7271 an external symbol, we want
7272 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7273 lui $at,<hiconstant>
7274 addiu $at,$at,<loconstant>
7275 addu $tempreg,$tempreg,$at
7277 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7278 local symbols, even though it introduces an additional
7281 if (offset_expr.X_add_number)
7283 expr1.X_add_number = offset_expr.X_add_number;
7284 offset_expr.X_add_number = 0;
7286 relax_start (offset_expr.X_add_symbol);
7287 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7288 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7290 if (expr1.X_add_number >= -0x8000
7291 && expr1.X_add_number < 0x8000)
7293 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7294 tempreg, tempreg, BFD_RELOC_LO16);
7296 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7298 /* If we are going to add in a base register, and the
7299 target register and the base register are the same,
7300 then we are using AT as a temporary register. Since
7301 we want to load the constant into AT, we add our
7302 current AT (from the global offset table) and the
7303 register into the register now, and pretend we were
7304 not using a base register. */
7309 gas_assert (tempreg == AT);
7310 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7316 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7317 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7323 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7326 offset_expr.X_add_number = expr1.X_add_number;
7328 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7329 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7332 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7333 treg, tempreg, breg);
7339 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7341 relax_start (offset_expr.X_add_symbol);
7342 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7343 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7345 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7346 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7351 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7352 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7355 else if (mips_big_got && !HAVE_NEWABI)
7358 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7359 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7360 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7362 /* This is the large GOT case. If this is a reference to an
7363 external symbol, and there is no constant, we want
7364 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7365 addu $tempreg,$tempreg,$gp
7366 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7367 or for lca or if tempreg is PIC_CALL_REG
7368 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7369 addu $tempreg,$tempreg,$gp
7370 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7371 For a local symbol, we want
7372 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7374 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7376 If we have a small constant, and this is a reference to
7377 an external symbol, we want
7378 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7379 addu $tempreg,$tempreg,$gp
7380 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7382 addiu $tempreg,$tempreg,<constant>
7383 For a local symbol, we want
7384 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7386 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7388 If we have a large constant, and this is a reference to
7389 an external symbol, we want
7390 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7391 addu $tempreg,$tempreg,$gp
7392 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7393 lui $at,<hiconstant>
7394 addiu $at,$at,<loconstant>
7395 addu $tempreg,$tempreg,$at
7396 For a local symbol, we want
7397 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7398 lui $at,<hiconstant>
7399 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7400 addu $tempreg,$tempreg,$at
7403 expr1.X_add_number = offset_expr.X_add_number;
7404 offset_expr.X_add_number = 0;
7405 relax_start (offset_expr.X_add_symbol);
7406 gpdelay = reg_needs_delay (mips_gp_register);
7407 if (expr1.X_add_number == 0 && breg == 0
7408 && (call || tempreg == PIC_CALL_REG))
7410 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7411 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7413 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7414 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7415 tempreg, tempreg, mips_gp_register);
7416 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7417 tempreg, lw_reloc_type, tempreg);
7418 if (expr1.X_add_number == 0)
7422 /* We're going to put in an addu instruction using
7423 tempreg, so we may as well insert the nop right
7428 else if (expr1.X_add_number >= -0x8000
7429 && expr1.X_add_number < 0x8000)
7432 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7433 tempreg, tempreg, BFD_RELOC_LO16);
7437 /* If we are going to add in a base register, and the
7438 target register and the base register are the same,
7439 then we are using AT as a temporary register. Since
7440 we want to load the constant into AT, we add our
7441 current AT (from the global offset table) and the
7442 register into the register now, and pretend we were
7443 not using a base register. */
7448 gas_assert (tempreg == AT);
7450 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7455 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7456 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7460 offset_expr.X_add_number =
7461 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
7466 /* This is needed because this instruction uses $gp, but
7467 the first instruction on the main stream does not. */
7468 macro_build (NULL, "nop", "");
7471 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7472 local_reloc_type, mips_gp_register);
7473 if (expr1.X_add_number >= -0x8000
7474 && expr1.X_add_number < 0x8000)
7477 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7478 tempreg, tempreg, BFD_RELOC_LO16);
7479 /* FIXME: If add_number is 0, and there was no base
7480 register, the external symbol case ended with a load,
7481 so if the symbol turns out to not be external, and
7482 the next instruction uses tempreg, an unnecessary nop
7483 will be inserted. */
7489 /* We must add in the base register now, as in the
7490 external symbol case. */
7491 gas_assert (tempreg == AT);
7493 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7496 /* We set breg to 0 because we have arranged to add
7497 it in in both cases. */
7501 macro_build_lui (&expr1, AT);
7502 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7503 AT, AT, BFD_RELOC_LO16);
7504 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7505 tempreg, tempreg, AT);
7510 else if (mips_big_got && HAVE_NEWABI)
7512 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7513 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7514 int add_breg_early = 0;
7516 /* This is the large GOT case. If this is a reference to an
7517 external symbol, and there is no constant, we want
7518 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7519 add $tempreg,$tempreg,$gp
7520 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7521 or for lca or if tempreg is PIC_CALL_REG
7522 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7523 add $tempreg,$tempreg,$gp
7524 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7526 If we have a small constant, and this is a reference to
7527 an external symbol, we want
7528 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7529 add $tempreg,$tempreg,$gp
7530 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7531 addi $tempreg,$tempreg,<constant>
7533 If we have a large constant, and this is a reference to
7534 an external symbol, we want
7535 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7536 addu $tempreg,$tempreg,$gp
7537 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7538 lui $at,<hiconstant>
7539 addi $at,$at,<loconstant>
7540 add $tempreg,$tempreg,$at
7542 If we have NewABI, and we know it's a local symbol, we want
7543 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7544 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7545 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7547 relax_start (offset_expr.X_add_symbol);
7549 expr1.X_add_number = offset_expr.X_add_number;
7550 offset_expr.X_add_number = 0;
7552 if (expr1.X_add_number == 0 && breg == 0
7553 && (call || tempreg == PIC_CALL_REG))
7555 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7556 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7558 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7559 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7560 tempreg, tempreg, mips_gp_register);
7561 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7562 tempreg, lw_reloc_type, tempreg);
7564 if (expr1.X_add_number == 0)
7566 else if (expr1.X_add_number >= -0x8000
7567 && expr1.X_add_number < 0x8000)
7569 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7570 tempreg, tempreg, BFD_RELOC_LO16);
7572 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7574 /* If we are going to add in a base register, and the
7575 target register and the base register are the same,
7576 then we are using AT as a temporary register. Since
7577 we want to load the constant into AT, we add our
7578 current AT (from the global offset table) and the
7579 register into the register now, and pretend we were
7580 not using a base register. */
7585 gas_assert (tempreg == AT);
7586 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7592 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7593 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7598 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7601 offset_expr.X_add_number = expr1.X_add_number;
7602 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7603 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7604 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7605 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7608 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7609 treg, tempreg, breg);
7619 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7623 gas_assert (!mips_opts.micromips);
7625 unsigned long temp = (treg << 16) | (0x01);
7626 macro_build (NULL, "c2", "C", temp);
7631 gas_assert (!mips_opts.micromips);
7633 unsigned long temp = (0x02);
7634 macro_build (NULL, "c2", "C", temp);
7639 gas_assert (!mips_opts.micromips);
7641 unsigned long temp = (treg << 16) | (0x02);
7642 macro_build (NULL, "c2", "C", temp);
7647 gas_assert (!mips_opts.micromips);
7648 macro_build (NULL, "c2", "C", 3);
7652 gas_assert (!mips_opts.micromips);
7654 unsigned long temp = (treg << 16) | 0x03;
7655 macro_build (NULL, "c2", "C", temp);
7660 /* The j instruction may not be used in PIC code, since it
7661 requires an absolute address. We convert it to a b
7663 if (mips_pic == NO_PIC)
7664 macro_build (&offset_expr, "j", "a");
7666 macro_build (&offset_expr, "b", "p");
7669 /* The jal instructions must be handled as macros because when
7670 generating PIC code they expand to multi-instruction
7671 sequences. Normally they are simple instructions. */
7676 gas_assert (mips_opts.micromips);
7684 if (mips_pic == NO_PIC)
7686 s = jals ? "jalrs" : "jalr";
7687 if (mips_opts.micromips && dreg == RA)
7688 macro_build (NULL, s, "mj", sreg);
7690 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7694 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7695 && mips_cprestore_offset >= 0);
7697 if (sreg != PIC_CALL_REG)
7698 as_warn (_("MIPS PIC call to register other than $25"));
7700 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7701 ? "jalrs" : "jalr");
7702 if (mips_opts.micromips && dreg == RA)
7703 macro_build (NULL, s, "mj", sreg);
7705 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7706 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7708 if (mips_cprestore_offset < 0)
7709 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7712 if (!mips_frame_reg_valid)
7714 as_warn (_("No .frame pseudo-op used in PIC code"));
7715 /* Quiet this warning. */
7716 mips_frame_reg_valid = 1;
7718 if (!mips_cprestore_valid)
7720 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7721 /* Quiet this warning. */
7722 mips_cprestore_valid = 1;
7724 if (mips_opts.noreorder)
7725 macro_build (NULL, "nop", "");
7726 expr1.X_add_number = mips_cprestore_offset;
7727 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7730 HAVE_64BIT_ADDRESSES);
7738 gas_assert (mips_opts.micromips);
7742 if (mips_pic == NO_PIC)
7743 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7744 else if (mips_pic == SVR4_PIC)
7746 /* If this is a reference to an external symbol, and we are
7747 using a small GOT, we want
7748 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7752 lw $gp,cprestore($sp)
7753 The cprestore value is set using the .cprestore
7754 pseudo-op. If we are using a big GOT, we want
7755 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7757 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7761 lw $gp,cprestore($sp)
7762 If the symbol is not external, we want
7763 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7765 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7768 lw $gp,cprestore($sp)
7770 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7771 sequences above, minus nops, unless the symbol is local,
7772 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7778 relax_start (offset_expr.X_add_symbol);
7779 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7780 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7783 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7784 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7790 relax_start (offset_expr.X_add_symbol);
7791 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7792 BFD_RELOC_MIPS_CALL_HI16);
7793 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7794 PIC_CALL_REG, mips_gp_register);
7795 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7796 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7799 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7800 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7802 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7803 PIC_CALL_REG, PIC_CALL_REG,
7804 BFD_RELOC_MIPS_GOT_OFST);
7808 macro_build_jalr (&offset_expr, 0);
7812 relax_start (offset_expr.X_add_symbol);
7815 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7816 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7825 gpdelay = reg_needs_delay (mips_gp_register);
7826 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7827 BFD_RELOC_MIPS_CALL_HI16);
7828 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7829 PIC_CALL_REG, mips_gp_register);
7830 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7831 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7836 macro_build (NULL, "nop", "");
7838 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7839 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7842 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7843 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7845 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7847 if (mips_cprestore_offset < 0)
7848 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7851 if (!mips_frame_reg_valid)
7853 as_warn (_("No .frame pseudo-op used in PIC code"));
7854 /* Quiet this warning. */
7855 mips_frame_reg_valid = 1;
7857 if (!mips_cprestore_valid)
7859 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7860 /* Quiet this warning. */
7861 mips_cprestore_valid = 1;
7863 if (mips_opts.noreorder)
7864 macro_build (NULL, "nop", "");
7865 expr1.X_add_number = mips_cprestore_offset;
7866 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7869 HAVE_64BIT_ADDRESSES);
7873 else if (mips_pic == VXWORKS_PIC)
7874 as_bad (_("Non-PIC jump used in PIC library"));
7907 gas_assert (!mips_opts.micromips);
7910 /* Itbl support may require additional care here. */
7917 /* Itbl support may require additional care here. */
7925 off12 = mips_opts.micromips;
7926 /* Itbl support may require additional care here. */
7931 gas_assert (!mips_opts.micromips);
7934 /* Itbl support may require additional care here. */
7942 off12 = mips_opts.micromips;
7949 off12 = mips_opts.micromips;
7955 /* Itbl support may require additional care here. */
7963 off12 = mips_opts.micromips;
7964 /* Itbl support may require additional care here. */
7971 /* Itbl support may require additional care here. */
7979 off12 = mips_opts.micromips;
7986 off12 = mips_opts.micromips;
7993 off12 = mips_opts.micromips;
8000 off12 = mips_opts.micromips;
8007 off12 = mips_opts.micromips;
8012 gas_assert (mips_opts.micromips);
8021 gas_assert (mips_opts.micromips);
8030 gas_assert (mips_opts.micromips);
8038 gas_assert (mips_opts.micromips);
8045 if (breg == treg + lp)
8048 tempreg = treg + lp;
8068 gas_assert (!mips_opts.micromips);
8071 /* Itbl support may require additional care here. */
8078 /* Itbl support may require additional care here. */
8086 off12 = mips_opts.micromips;
8087 /* Itbl support may require additional care here. */
8092 gas_assert (!mips_opts.micromips);
8095 /* Itbl support may require additional care here. */
8103 off12 = mips_opts.micromips;
8110 off12 = mips_opts.micromips;
8117 off12 = mips_opts.micromips;
8124 off12 = mips_opts.micromips;
8130 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8131 off12 = mips_opts.micromips;
8137 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8138 off12 = mips_opts.micromips;
8145 /* Itbl support may require additional care here. */
8152 off12 = mips_opts.micromips;
8153 /* Itbl support may require additional care here. */
8158 gas_assert (!mips_opts.micromips);
8161 /* Itbl support may require additional care here. */
8169 off12 = mips_opts.micromips;
8176 off12 = mips_opts.micromips;
8181 gas_assert (mips_opts.micromips);
8189 gas_assert (mips_opts.micromips);
8197 gas_assert (mips_opts.micromips);
8205 gas_assert (mips_opts.micromips);
8215 && NO_ISA_COP (mips_opts.arch)
8216 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
8218 as_bad (_("Opcode not supported on this processor: %s"),
8219 mips_cpu_info_from_arch (mips_opts.arch)->name);
8223 if (offset_expr.X_op != O_constant
8224 && offset_expr.X_op != O_symbol)
8226 as_bad (_("Expression too complex"));
8227 offset_expr.X_op = O_constant;
8230 if (HAVE_32BIT_ADDRESSES
8231 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8235 sprintf_vma (value, offset_expr.X_add_number);
8236 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8239 /* A constant expression in PIC code can be handled just as it
8240 is in non PIC code. */
8241 if (offset_expr.X_op == O_constant)
8245 expr1.X_add_number = offset_expr.X_add_number;
8246 normalize_address_expr (&expr1);
8247 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8249 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8250 & ~(bfd_vma) 0xffff);
8253 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8255 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8256 & ~(bfd_vma) 0xfff);
8261 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8263 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8264 tempreg, tempreg, breg);
8268 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8270 macro_build (NULL, s, fmt,
8271 treg, (unsigned long) offset_expr.X_add_number, breg);
8275 /* A 12-bit offset field is too narrow to be used for a low-part
8276 relocation, so load the whole address into the auxillary
8277 register. In the case of "A(b)" addresses, we first load
8278 absolute address "A" into the register and then add base
8279 register "b". In the case of "o(b)" addresses, we simply
8280 need to add 16-bit offset "o" to base register "b", and
8281 offset_reloc already contains the relocations associated
8285 load_address (tempreg, &offset_expr, &used_at);
8287 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8288 tempreg, tempreg, breg);
8291 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8293 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8294 expr1.X_add_number = 0;
8295 macro_build (NULL, s, fmt,
8296 treg, (unsigned long) expr1.X_add_number, tempreg);
8298 else if (mips_pic == NO_PIC)
8300 /* If this is a reference to a GP relative symbol, and there
8301 is no base register, we want
8302 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8303 Otherwise, if there is no base register, we want
8304 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8305 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8306 If we have a constant, we need two instructions anyhow,
8307 so we always use the latter form.
8309 If we have a base register, and this is a reference to a
8310 GP relative symbol, we want
8311 addu $tempreg,$breg,$gp
8312 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8314 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8315 addu $tempreg,$tempreg,$breg
8316 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8317 With a constant we always use the latter case.
8319 With 64bit address space and no base register and $at usable,
8321 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8322 lui $at,<sym> (BFD_RELOC_HI16_S)
8323 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8326 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8327 If we have a base register, we want
8328 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8329 lui $at,<sym> (BFD_RELOC_HI16_S)
8330 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8334 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8336 Without $at we can't generate the optimal path for superscalar
8337 processors here since this would require two temporary registers.
8338 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8339 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8341 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8343 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8344 If we have a base register, we want
8345 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8346 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8348 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8350 daddu $tempreg,$tempreg,$breg
8351 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8353 For GP relative symbols in 64bit address space we can use
8354 the same sequence as in 32bit address space. */
8355 if (HAVE_64BIT_SYMBOLS)
8357 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8358 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8360 relax_start (offset_expr.X_add_symbol);
8363 macro_build (&offset_expr, s, fmt, treg,
8364 BFD_RELOC_GPREL16, mips_gp_register);
8368 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8369 tempreg, breg, mips_gp_register);
8370 macro_build (&offset_expr, s, fmt, treg,
8371 BFD_RELOC_GPREL16, tempreg);
8376 if (used_at == 0 && mips_opts.at)
8378 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8379 BFD_RELOC_MIPS_HIGHEST);
8380 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8382 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8383 tempreg, BFD_RELOC_MIPS_HIGHER);
8385 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8386 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8387 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8388 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8394 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8395 BFD_RELOC_MIPS_HIGHEST);
8396 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8397 tempreg, BFD_RELOC_MIPS_HIGHER);
8398 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8399 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8400 tempreg, BFD_RELOC_HI16_S);
8401 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8403 macro_build (NULL, "daddu", "d,v,t",
8404 tempreg, tempreg, breg);
8405 macro_build (&offset_expr, s, fmt, treg,
8406 BFD_RELOC_LO16, tempreg);
8409 if (mips_relax.sequence)
8416 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8417 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8419 relax_start (offset_expr.X_add_symbol);
8420 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8424 macro_build_lui (&offset_expr, tempreg);
8425 macro_build (&offset_expr, s, fmt, treg,
8426 BFD_RELOC_LO16, tempreg);
8427 if (mips_relax.sequence)
8432 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8433 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8435 relax_start (offset_expr.X_add_symbol);
8436 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8437 tempreg, breg, mips_gp_register);
8438 macro_build (&offset_expr, s, fmt, treg,
8439 BFD_RELOC_GPREL16, tempreg);
8442 macro_build_lui (&offset_expr, tempreg);
8443 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8444 tempreg, tempreg, breg);
8445 macro_build (&offset_expr, s, fmt, treg,
8446 BFD_RELOC_LO16, tempreg);
8447 if (mips_relax.sequence)
8451 else if (!mips_big_got)
8453 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8455 /* If this is a reference to an external symbol, we want
8456 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8458 <op> $treg,0($tempreg)
8460 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8462 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8463 <op> $treg,0($tempreg)
8466 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8467 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8469 If there is a base register, we add it to $tempreg before
8470 the <op>. If there is a constant, we stick it in the
8471 <op> instruction. We don't handle constants larger than
8472 16 bits, because we have no way to load the upper 16 bits
8473 (actually, we could handle them for the subset of cases
8474 in which we are not using $at). */
8475 gas_assert (offset_expr.X_op == O_symbol);
8478 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8479 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8481 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8482 tempreg, tempreg, breg);
8483 macro_build (&offset_expr, s, fmt, treg,
8484 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8487 expr1.X_add_number = offset_expr.X_add_number;
8488 offset_expr.X_add_number = 0;
8489 if (expr1.X_add_number < -0x8000
8490 || expr1.X_add_number >= 0x8000)
8491 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8492 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8493 lw_reloc_type, mips_gp_register);
8495 relax_start (offset_expr.X_add_symbol);
8497 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8498 tempreg, BFD_RELOC_LO16);
8501 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8502 tempreg, tempreg, breg);
8503 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8505 else if (mips_big_got && !HAVE_NEWABI)
8509 /* If this is a reference to an external symbol, we want
8510 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8511 addu $tempreg,$tempreg,$gp
8512 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8513 <op> $treg,0($tempreg)
8515 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8517 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8518 <op> $treg,0($tempreg)
8519 If there is a base register, we add it to $tempreg before
8520 the <op>. If there is a constant, we stick it in the
8521 <op> instruction. We don't handle constants larger than
8522 16 bits, because we have no way to load the upper 16 bits
8523 (actually, we could handle them for the subset of cases
8524 in which we are not using $at). */
8525 gas_assert (offset_expr.X_op == O_symbol);
8526 expr1.X_add_number = offset_expr.X_add_number;
8527 offset_expr.X_add_number = 0;
8528 if (expr1.X_add_number < -0x8000
8529 || expr1.X_add_number >= 0x8000)
8530 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8531 gpdelay = reg_needs_delay (mips_gp_register);
8532 relax_start (offset_expr.X_add_symbol);
8533 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8534 BFD_RELOC_MIPS_GOT_HI16);
8535 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8537 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8538 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8541 macro_build (NULL, "nop", "");
8542 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8543 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8545 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8546 tempreg, BFD_RELOC_LO16);
8550 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8551 tempreg, tempreg, breg);
8552 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8554 else if (mips_big_got && HAVE_NEWABI)
8556 /* If this is a reference to an external symbol, we want
8557 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8558 add $tempreg,$tempreg,$gp
8559 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8560 <op> $treg,<ofst>($tempreg)
8561 Otherwise, for local symbols, we want:
8562 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8563 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8564 gas_assert (offset_expr.X_op == O_symbol);
8565 expr1.X_add_number = offset_expr.X_add_number;
8566 offset_expr.X_add_number = 0;
8567 if (expr1.X_add_number < -0x8000
8568 || expr1.X_add_number >= 0x8000)
8569 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8570 relax_start (offset_expr.X_add_symbol);
8571 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8572 BFD_RELOC_MIPS_GOT_HI16);
8573 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8575 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8576 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8578 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8579 tempreg, tempreg, breg);
8580 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8583 offset_expr.X_add_number = expr1.X_add_number;
8584 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8585 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8587 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8588 tempreg, tempreg, breg);
8589 macro_build (&offset_expr, s, fmt, treg,
8590 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8600 load_register (treg, &imm_expr, 0);
8604 load_register (treg, &imm_expr, 1);
8608 if (imm_expr.X_op == O_constant)
8611 load_register (AT, &imm_expr, 0);
8612 macro_build (NULL, "mtc1", "t,G", AT, treg);
8617 gas_assert (offset_expr.X_op == O_symbol
8618 && strcmp (segment_name (S_GET_SEGMENT
8619 (offset_expr.X_add_symbol)),
8621 && offset_expr.X_add_number == 0);
8622 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8623 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8628 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8629 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8630 order 32 bits of the value and the low order 32 bits are either
8631 zero or in OFFSET_EXPR. */
8632 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8634 if (HAVE_64BIT_GPRS)
8635 load_register (treg, &imm_expr, 1);
8640 if (target_big_endian)
8652 load_register (hreg, &imm_expr, 0);
8655 if (offset_expr.X_op == O_absent)
8656 move_register (lreg, 0);
8659 gas_assert (offset_expr.X_op == O_constant);
8660 load_register (lreg, &offset_expr, 0);
8667 /* We know that sym is in the .rdata section. First we get the
8668 upper 16 bits of the address. */
8669 if (mips_pic == NO_PIC)
8671 macro_build_lui (&offset_expr, AT);
8676 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8677 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8681 /* Now we load the register(s). */
8682 if (HAVE_64BIT_GPRS)
8685 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8690 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8693 /* FIXME: How in the world do we deal with the possible
8695 offset_expr.X_add_number += 4;
8696 macro_build (&offset_expr, "lw", "t,o(b)",
8697 treg + 1, BFD_RELOC_LO16, AT);
8703 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8704 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8705 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8706 the value and the low order 32 bits are either zero or in
8708 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8711 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8712 if (HAVE_64BIT_FPRS)
8714 gas_assert (HAVE_64BIT_GPRS);
8715 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8719 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8720 if (offset_expr.X_op == O_absent)
8721 macro_build (NULL, "mtc1", "t,G", 0, treg);
8724 gas_assert (offset_expr.X_op == O_constant);
8725 load_register (AT, &offset_expr, 0);
8726 macro_build (NULL, "mtc1", "t,G", AT, treg);
8732 gas_assert (offset_expr.X_op == O_symbol
8733 && offset_expr.X_add_number == 0);
8734 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8735 if (strcmp (s, ".lit8") == 0)
8737 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8739 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8740 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8743 breg = mips_gp_register;
8744 r = BFD_RELOC_MIPS_LITERAL;
8749 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8751 if (mips_pic != NO_PIC)
8752 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8753 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8756 /* FIXME: This won't work for a 64 bit address. */
8757 macro_build_lui (&offset_expr, AT);
8760 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8762 macro_build (&offset_expr, "ldc1", "T,o(b)",
8763 treg, BFD_RELOC_LO16, AT);
8772 /* Even on a big endian machine $fn comes before $fn+1. We have
8773 to adjust when loading from memory. */
8776 gas_assert (!mips_opts.micromips);
8777 gas_assert (mips_opts.isa == ISA_MIPS1);
8778 macro_build (&offset_expr, "lwc1", "T,o(b)",
8779 target_big_endian ? treg + 1 : treg, r, breg);
8780 /* FIXME: A possible overflow which I don't know how to deal
8782 offset_expr.X_add_number += 4;
8783 macro_build (&offset_expr, "lwc1", "T,o(b)",
8784 target_big_endian ? treg : treg + 1, r, breg);
8788 gas_assert (!mips_opts.micromips);
8789 gas_assert (mips_opts.isa == ISA_MIPS1);
8790 /* Even on a big endian machine $fn comes before $fn+1. We have
8791 to adjust when storing to memory. */
8792 macro_build (&offset_expr, "swc1", "T,o(b)",
8793 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8794 offset_expr.X_add_number += 4;
8795 macro_build (&offset_expr, "swc1", "T,o(b)",
8796 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8800 gas_assert (!mips_opts.micromips);
8802 * The MIPS assembler seems to check for X_add_number not
8803 * being double aligned and generating:
8806 * addiu at,at,%lo(foo+1)
8809 * But, the resulting address is the same after relocation so why
8810 * generate the extra instruction?
8812 /* Itbl support may require additional care here. */
8815 if (mips_opts.isa != ISA_MIPS1)
8824 gas_assert (!mips_opts.micromips);
8825 /* Itbl support may require additional care here. */
8828 if (mips_opts.isa != ISA_MIPS1)
8838 if (HAVE_64BIT_GPRS)
8848 if (HAVE_64BIT_GPRS)
8856 if (offset_expr.X_op != O_symbol
8857 && offset_expr.X_op != O_constant)
8859 as_bad (_("Expression too complex"));
8860 offset_expr.X_op = O_constant;
8863 if (HAVE_32BIT_ADDRESSES
8864 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8868 sprintf_vma (value, offset_expr.X_add_number);
8869 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8872 /* Even on a big endian machine $fn comes before $fn+1. We have
8873 to adjust when loading from memory. We set coproc if we must
8874 load $fn+1 first. */
8875 /* Itbl support may require additional care here. */
8876 if (!target_big_endian)
8879 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
8881 /* If this is a reference to a GP relative symbol, we want
8882 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8883 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8884 If we have a base register, we use this
8886 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8887 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8888 If this is not a GP relative symbol, we want
8889 lui $at,<sym> (BFD_RELOC_HI16_S)
8890 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8891 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8892 If there is a base register, we add it to $at after the
8893 lui instruction. If there is a constant, we always use
8895 if (offset_expr.X_op == O_symbol
8896 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8897 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8899 relax_start (offset_expr.X_add_symbol);
8902 tempreg = mips_gp_register;
8906 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8907 AT, breg, mips_gp_register);
8912 /* Itbl support may require additional care here. */
8913 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8914 BFD_RELOC_GPREL16, tempreg);
8915 offset_expr.X_add_number += 4;
8917 /* Set mips_optimize to 2 to avoid inserting an
8919 hold_mips_optimize = mips_optimize;
8921 /* Itbl support may require additional care here. */
8922 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8923 BFD_RELOC_GPREL16, tempreg);
8924 mips_optimize = hold_mips_optimize;
8928 offset_expr.X_add_number -= 4;
8931 macro_build_lui (&offset_expr, AT);
8933 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8934 /* Itbl support may require additional care here. */
8935 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8936 BFD_RELOC_LO16, AT);
8937 /* FIXME: How do we handle overflow here? */
8938 offset_expr.X_add_number += 4;
8939 /* Itbl support may require additional care here. */
8940 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8941 BFD_RELOC_LO16, AT);
8942 if (mips_relax.sequence)
8945 else if (!mips_big_got)
8947 /* If this is a reference to an external symbol, we want
8948 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8953 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8955 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8956 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8957 If there is a base register we add it to $at before the
8958 lwc1 instructions. If there is a constant we include it
8959 in the lwc1 instructions. */
8961 expr1.X_add_number = offset_expr.X_add_number;
8962 if (expr1.X_add_number < -0x8000
8963 || expr1.X_add_number >= 0x8000 - 4)
8964 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8965 load_got_offset (AT, &offset_expr);
8968 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8970 /* Set mips_optimize to 2 to avoid inserting an undesired
8972 hold_mips_optimize = mips_optimize;
8975 /* Itbl support may require additional care here. */
8976 relax_start (offset_expr.X_add_symbol);
8977 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
8978 BFD_RELOC_LO16, AT);
8979 expr1.X_add_number += 4;
8980 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
8981 BFD_RELOC_LO16, AT);
8983 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8984 BFD_RELOC_LO16, AT);
8985 offset_expr.X_add_number += 4;
8986 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8987 BFD_RELOC_LO16, AT);
8990 mips_optimize = hold_mips_optimize;
8992 else if (mips_big_got)
8996 /* If this is a reference to an external symbol, we want
8997 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8999 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9004 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9006 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9007 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9008 If there is a base register we add it to $at before the
9009 lwc1 instructions. If there is a constant we include it
9010 in the lwc1 instructions. */
9012 expr1.X_add_number = offset_expr.X_add_number;
9013 offset_expr.X_add_number = 0;
9014 if (expr1.X_add_number < -0x8000
9015 || expr1.X_add_number >= 0x8000 - 4)
9016 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9017 gpdelay = reg_needs_delay (mips_gp_register);
9018 relax_start (offset_expr.X_add_symbol);
9019 macro_build (&offset_expr, "lui", LUI_FMT,
9020 AT, BFD_RELOC_MIPS_GOT_HI16);
9021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9022 AT, AT, mips_gp_register);
9023 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9024 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9027 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9028 /* Itbl support may require additional care here. */
9029 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9030 BFD_RELOC_LO16, AT);
9031 expr1.X_add_number += 4;
9033 /* Set mips_optimize to 2 to avoid inserting an undesired
9035 hold_mips_optimize = mips_optimize;
9037 /* Itbl support may require additional care here. */
9038 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9039 BFD_RELOC_LO16, AT);
9040 mips_optimize = hold_mips_optimize;
9041 expr1.X_add_number -= 4;
9044 offset_expr.X_add_number = expr1.X_add_number;
9046 macro_build (NULL, "nop", "");
9047 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9048 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9051 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9052 /* Itbl support may require additional care here. */
9053 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9054 BFD_RELOC_LO16, AT);
9055 offset_expr.X_add_number += 4;
9057 /* Set mips_optimize to 2 to avoid inserting an undesired
9059 hold_mips_optimize = mips_optimize;
9061 /* Itbl support may require additional care here. */
9062 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9063 BFD_RELOC_LO16, AT);
9064 mips_optimize = hold_mips_optimize;
9073 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9076 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9078 macro_build (&offset_expr, s, "t,o(b)", treg,
9079 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9081 if (!HAVE_64BIT_GPRS)
9083 offset_expr.X_add_number += 4;
9084 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9085 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9090 /* New code added to support COPZ instructions.
9091 This code builds table entries out of the macros in mip_opcodes.
9092 R4000 uses interlocks to handle coproc delays.
9093 Other chips (like the R3000) require nops to be inserted for delays.
9095 FIXME: Currently, we require that the user handle delays.
9096 In order to fill delay slots for non-interlocked chips,
9097 we must have a way to specify delays based on the coprocessor.
9098 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9099 What are the side-effects of the cop instruction?
9100 What cache support might we have and what are its effects?
9101 Both coprocessor & memory require delays. how long???
9102 What registers are read/set/modified?
9104 If an itbl is provided to interpret cop instructions,
9105 this knowledge can be encoded in the itbl spec. */
9119 gas_assert (!mips_opts.micromips);
9120 if (NO_ISA_COP (mips_opts.arch)
9121 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
9123 as_bad (_("opcode not supported on this processor: %s"),
9124 mips_cpu_info_from_arch (mips_opts.arch)->name);
9128 /* For now we just do C (same as Cz). The parameter will be
9129 stored in insn_opcode by mips_ip. */
9130 macro_build (NULL, s, "C", ip->insn_opcode);
9134 move_register (dreg, sreg);
9140 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9141 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9147 /* The MIPS assembler some times generates shifts and adds. I'm
9148 not trying to be that fancy. GCC should do this for us
9151 load_register (AT, &imm_expr, dbl);
9152 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9153 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9169 load_register (AT, &imm_expr, dbl);
9170 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9171 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9172 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9173 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9175 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9178 if (mips_opts.micromips)
9179 micromips_label_expr (&label_expr);
9181 label_expr.X_add_number = 8;
9182 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9183 macro_build (NULL, "nop", "");
9184 macro_build (NULL, "break", BRK_FMT, 6);
9185 if (mips_opts.micromips)
9186 micromips_add_label ();
9189 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9205 load_register (AT, &imm_expr, dbl);
9206 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9207 sreg, imm ? AT : treg);
9208 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9209 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9211 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9214 if (mips_opts.micromips)
9215 micromips_label_expr (&label_expr);
9217 label_expr.X_add_number = 8;
9218 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9219 macro_build (NULL, "nop", "");
9220 macro_build (NULL, "break", BRK_FMT, 6);
9221 if (mips_opts.micromips)
9222 micromips_add_label ();
9228 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9239 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9240 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9244 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9245 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9246 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9247 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9251 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9262 macro_build (NULL, "negu", "d,w", tempreg, treg);
9263 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9267 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9268 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9269 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9270 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9279 if (imm_expr.X_op != O_constant)
9280 as_bad (_("Improper rotate count"));
9281 rot = imm_expr.X_add_number & 0x3f;
9282 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9284 rot = (64 - rot) & 0x3f;
9286 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9288 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9293 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9296 l = (rot < 0x20) ? "dsll" : "dsll32";
9297 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9300 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9301 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9302 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9310 if (imm_expr.X_op != O_constant)
9311 as_bad (_("Improper rotate count"));
9312 rot = imm_expr.X_add_number & 0x1f;
9313 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9315 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9320 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9324 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9325 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9326 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9331 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9333 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9337 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9338 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9339 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9340 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9344 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9346 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9350 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9351 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9352 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9353 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9362 if (imm_expr.X_op != O_constant)
9363 as_bad (_("Improper rotate count"));
9364 rot = imm_expr.X_add_number & 0x3f;
9365 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9368 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9370 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9375 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9378 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9379 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9382 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9383 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9384 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9392 if (imm_expr.X_op != O_constant)
9393 as_bad (_("Improper rotate count"));
9394 rot = imm_expr.X_add_number & 0x1f;
9395 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9397 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9402 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9406 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9407 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9408 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9414 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9416 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9419 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9420 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9425 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9427 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9432 as_warn (_("Instruction %s: result is always false"),
9434 move_register (dreg, 0);
9437 if (CPU_HAS_SEQ (mips_opts.arch)
9438 && -512 <= imm_expr.X_add_number
9439 && imm_expr.X_add_number < 512)
9441 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9442 (int) imm_expr.X_add_number);
9445 if (imm_expr.X_op == O_constant
9446 && imm_expr.X_add_number >= 0
9447 && imm_expr.X_add_number < 0x10000)
9449 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9451 else if (imm_expr.X_op == O_constant
9452 && imm_expr.X_add_number > -0x8000
9453 && imm_expr.X_add_number < 0)
9455 imm_expr.X_add_number = -imm_expr.X_add_number;
9456 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9457 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9459 else if (CPU_HAS_SEQ (mips_opts.arch))
9462 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9463 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9468 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9469 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9472 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9475 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9481 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9482 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9485 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9487 if (imm_expr.X_op == O_constant
9488 && imm_expr.X_add_number >= -0x8000
9489 && imm_expr.X_add_number < 0x8000)
9491 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9492 dreg, sreg, BFD_RELOC_LO16);
9496 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9497 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9501 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9504 case M_SGT: /* sreg > treg <==> treg < sreg */
9510 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9513 case M_SGT_I: /* sreg > I <==> I < sreg */
9520 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9521 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9524 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9530 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9531 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9534 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9541 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9542 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9543 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9547 if (imm_expr.X_op == O_constant
9548 && imm_expr.X_add_number >= -0x8000
9549 && imm_expr.X_add_number < 0x8000)
9551 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9555 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9556 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9560 if (imm_expr.X_op == O_constant
9561 && imm_expr.X_add_number >= -0x8000
9562 && imm_expr.X_add_number < 0x8000)
9564 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9569 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9570 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9575 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9577 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9580 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9581 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9586 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9588 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9593 as_warn (_("Instruction %s: result is always true"),
9595 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9596 dreg, 0, BFD_RELOC_LO16);
9599 if (CPU_HAS_SEQ (mips_opts.arch)
9600 && -512 <= imm_expr.X_add_number
9601 && imm_expr.X_add_number < 512)
9603 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9604 (int) imm_expr.X_add_number);
9607 if (imm_expr.X_op == O_constant
9608 && imm_expr.X_add_number >= 0
9609 && imm_expr.X_add_number < 0x10000)
9611 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9613 else if (imm_expr.X_op == O_constant
9614 && imm_expr.X_add_number > -0x8000
9615 && imm_expr.X_add_number < 0)
9617 imm_expr.X_add_number = -imm_expr.X_add_number;
9618 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9619 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9621 else if (CPU_HAS_SEQ (mips_opts.arch))
9624 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9625 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9630 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9631 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9634 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9649 if (!mips_opts.micromips)
9651 if (imm_expr.X_op == O_constant
9652 && imm_expr.X_add_number > -0x200
9653 && imm_expr.X_add_number <= 0x200)
9655 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9664 if (imm_expr.X_op == O_constant
9665 && imm_expr.X_add_number > -0x8000
9666 && imm_expr.X_add_number <= 0x8000)
9668 imm_expr.X_add_number = -imm_expr.X_add_number;
9669 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9674 load_register (AT, &imm_expr, dbl);
9675 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9697 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9698 macro_build (NULL, s, "s,t", sreg, AT);
9703 gas_assert (!mips_opts.micromips);
9704 gas_assert (mips_opts.isa == ISA_MIPS1);
9706 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9707 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9710 * Is the double cfc1 instruction a bug in the mips assembler;
9711 * or is there a reason for it?
9714 macro_build (NULL, "cfc1", "t,G", treg, RA);
9715 macro_build (NULL, "cfc1", "t,G", treg, RA);
9716 macro_build (NULL, "nop", "");
9717 expr1.X_add_number = 3;
9718 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9719 expr1.X_add_number = 2;
9720 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9721 macro_build (NULL, "ctc1", "t,G", AT, RA);
9722 macro_build (NULL, "nop", "");
9723 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9725 macro_build (NULL, "ctc1", "t,G", treg, RA);
9726 macro_build (NULL, "nop", "");
9749 off12 = mips_opts.micromips;
9757 off12 = mips_opts.micromips;
9773 off12 = mips_opts.micromips;
9782 off12 = mips_opts.micromips;
9787 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9788 as_bad (_("Operand overflow"));
9791 expr1.X_add_number = 0;
9796 load_address (tempreg, ep, &used_at);
9798 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9799 tempreg, tempreg, breg);
9805 && (offset_expr.X_op != O_constant
9806 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9807 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9811 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9812 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9817 else if (!ust && treg == breg)
9828 if (!target_big_endian)
9829 ep->X_add_number += off;
9831 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9833 macro_build (NULL, s, "t,~(b)",
9834 tempreg, (unsigned long) ep->X_add_number, breg);
9836 if (!target_big_endian)
9837 ep->X_add_number -= off;
9839 ep->X_add_number += off;
9841 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9843 macro_build (NULL, s2, "t,~(b)",
9844 tempreg, (unsigned long) ep->X_add_number, breg);
9846 /* If necessary, move the result in tempreg to the final destination. */
9847 if (!ust && treg != tempreg)
9849 /* Protect second load's delay slot. */
9851 move_register (treg, tempreg);
9857 if (target_big_endian == ust)
9858 ep->X_add_number += off;
9859 tempreg = ust || ab ? treg : AT;
9860 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9862 /* For halfword transfers we need a temporary register to shuffle
9863 bytes. Unfortunately for M_USH_A we have none available before
9864 the next store as AT holds the base address. We deal with this
9865 case by clobbering TREG and then restoring it as with ULH. */
9866 tempreg = ust == ab ? treg : AT;
9868 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9870 if (target_big_endian == ust)
9871 ep->X_add_number -= off;
9873 ep->X_add_number += off;
9874 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9876 /* For M_USH_A re-retrieve the LSB. */
9879 if (target_big_endian)
9880 ep->X_add_number += off;
9882 ep->X_add_number -= off;
9883 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9885 /* For ULH and M_USH_A OR the LSB in. */
9888 tempreg = !ab ? AT : treg;
9889 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9890 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9895 /* FIXME: Check if this is one of the itbl macros, since they
9896 are added dynamically. */
9897 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9900 if (!mips_opts.at && used_at)
9901 as_bad (_("Macro used $at after \".set noat\""));
9904 /* Implement macros in mips16 mode. */
9907 mips16_macro (struct mips_cl_insn *ip)
9910 int xreg, yreg, zreg, tmp;
9913 const char *s, *s2, *s3;
9915 mask = ip->insn_mo->mask;
9917 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
9918 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
9919 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
9921 expr1.X_op = O_constant;
9922 expr1.X_op_symbol = NULL;
9923 expr1.X_add_symbol = NULL;
9924 expr1.X_add_number = 1;
9944 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
9945 expr1.X_add_number = 2;
9946 macro_build (&expr1, "bnez", "x,p", yreg);
9947 macro_build (NULL, "break", "6", 7);
9949 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9950 since that causes an overflow. We should do that as well,
9951 but I don't see how to do the comparisons without a temporary
9954 macro_build (NULL, s, "x", zreg);
9974 macro_build (NULL, s, "0,x,y", xreg, yreg);
9975 expr1.X_add_number = 2;
9976 macro_build (&expr1, "bnez", "x,p", yreg);
9977 macro_build (NULL, "break", "6", 7);
9979 macro_build (NULL, s2, "x", zreg);
9985 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
9986 macro_build (NULL, "mflo", "x", zreg);
9994 if (imm_expr.X_op != O_constant)
9995 as_bad (_("Unsupported large constant"));
9996 imm_expr.X_add_number = -imm_expr.X_add_number;
9997 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10001 if (imm_expr.X_op != O_constant)
10002 as_bad (_("Unsupported large constant"));
10003 imm_expr.X_add_number = -imm_expr.X_add_number;
10004 macro_build (&imm_expr, "addiu", "x,k", xreg);
10008 if (imm_expr.X_op != O_constant)
10009 as_bad (_("Unsupported large constant"));
10010 imm_expr.X_add_number = -imm_expr.X_add_number;
10011 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10033 goto do_reverse_branch;
10037 goto do_reverse_branch;
10049 goto do_reverse_branch;
10060 macro_build (NULL, s, "x,y", xreg, yreg);
10061 macro_build (&offset_expr, s2, "p");
10088 goto do_addone_branch_i;
10093 goto do_addone_branch_i;
10108 goto do_addone_branch_i;
10114 do_addone_branch_i:
10115 if (imm_expr.X_op != O_constant)
10116 as_bad (_("Unsupported large constant"));
10117 ++imm_expr.X_add_number;
10120 macro_build (&imm_expr, s, s3, xreg);
10121 macro_build (&offset_expr, s2, "p");
10125 expr1.X_add_number = 0;
10126 macro_build (&expr1, "slti", "x,8", yreg);
10128 move_register (xreg, yreg);
10129 expr1.X_add_number = 2;
10130 macro_build (&expr1, "bteqz", "p");
10131 macro_build (NULL, "neg", "x,w", xreg, xreg);
10135 /* For consistency checking, verify that all bits are specified either
10136 by the match/mask part of the instruction definition, or by the
10139 validate_mips_insn (const struct mips_opcode *opc)
10141 const char *p = opc->args;
10143 unsigned long used_bits = opc->mask;
10145 if ((used_bits & opc->match) != opc->match)
10147 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10148 opc->name, opc->args);
10151 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10161 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10162 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10163 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10164 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10165 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10166 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10167 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10168 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10169 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10170 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10171 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10172 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10173 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10175 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10176 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10177 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10178 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10179 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10180 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10181 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10182 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10183 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10184 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10185 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10186 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10187 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10188 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10189 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10192 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10193 c, opc->name, opc->args);
10197 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10198 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10200 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10201 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10202 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10203 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10205 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10206 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10208 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10209 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10211 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10212 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10213 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10214 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10215 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10216 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10217 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10218 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10219 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10220 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10221 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10222 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10223 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10224 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10225 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10226 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10227 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10229 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10230 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10231 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10232 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10234 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10235 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10236 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10237 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10238 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10239 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10240 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10241 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10242 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10245 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10246 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10247 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10248 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10249 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10252 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10253 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10254 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10255 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10256 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10257 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10258 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10259 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10260 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10261 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10262 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10263 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10264 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10265 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10266 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10267 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10268 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10269 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10271 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10272 c, opc->name, opc->args);
10276 if (used_bits != 0xffffffff)
10278 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10279 ~used_bits & 0xffffffff, opc->name, opc->args);
10285 /* For consistency checking, verify that the length implied matches the
10286 major opcode and that all bits are specified either by the match/mask
10287 part of the instruction definition, or by the operand list. */
10290 validate_micromips_insn (const struct mips_opcode *opc)
10292 unsigned long match = opc->match;
10293 unsigned long mask = opc->mask;
10294 const char *p = opc->args;
10295 unsigned long insn_bits;
10296 unsigned long used_bits;
10297 unsigned long major;
10298 unsigned int length;
10302 if ((mask & match) != match)
10304 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10305 opc->name, opc->args);
10308 length = micromips_insn_length (opc);
10309 if (length != 2 && length != 4)
10311 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10312 "%s %s"), length, opc->name, opc->args);
10315 major = match >> (10 + 8 * (length - 2));
10316 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10317 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10319 as_bad (_("Internal error: bad microMIPS opcode "
10320 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10324 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10325 insn_bits = 1 << 4 * length;
10326 insn_bits <<= 4 * length;
10329 #define USE_BITS(field) \
10330 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10341 case 'A': USE_BITS (EXTLSB); break;
10342 case 'B': USE_BITS (INSMSB); break;
10343 case 'C': USE_BITS (EXTMSBD); break;
10344 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10345 case 'E': USE_BITS (EXTLSB); break;
10346 case 'F': USE_BITS (INSMSB); break;
10347 case 'G': USE_BITS (EXTMSBD); break;
10348 case 'H': USE_BITS (EXTMSBD); break;
10350 as_bad (_("Internal error: bad mips opcode "
10351 "(unknown extension operand type `%c%c'): %s %s"),
10352 e, c, opc->name, opc->args);
10360 case 'A': USE_BITS (IMMA); break;
10361 case 'B': USE_BITS (IMMB); break;
10362 case 'C': USE_BITS (IMMC); break;
10363 case 'D': USE_BITS (IMMD); break;
10364 case 'E': USE_BITS (IMME); break;
10365 case 'F': USE_BITS (IMMF); break;
10366 case 'G': USE_BITS (IMMG); break;
10367 case 'H': USE_BITS (IMMH); break;
10368 case 'I': USE_BITS (IMMI); break;
10369 case 'J': USE_BITS (IMMJ); break;
10370 case 'L': USE_BITS (IMML); break;
10371 case 'M': USE_BITS (IMMM); break;
10372 case 'N': USE_BITS (IMMN); break;
10373 case 'O': USE_BITS (IMMO); break;
10374 case 'P': USE_BITS (IMMP); break;
10375 case 'Q': USE_BITS (IMMQ); break;
10376 case 'U': USE_BITS (IMMU); break;
10377 case 'W': USE_BITS (IMMW); break;
10378 case 'X': USE_BITS (IMMX); break;
10379 case 'Y': USE_BITS (IMMY); break;
10382 case 'b': USE_BITS (MB); break;
10383 case 'c': USE_BITS (MC); break;
10384 case 'd': USE_BITS (MD); break;
10385 case 'e': USE_BITS (ME); break;
10386 case 'f': USE_BITS (MF); break;
10387 case 'g': USE_BITS (MG); break;
10388 case 'h': USE_BITS (MH); break;
10389 case 'i': USE_BITS (MI); break;
10390 case 'j': USE_BITS (MJ); break;
10391 case 'l': USE_BITS (ML); break;
10392 case 'm': USE_BITS (MM); break;
10393 case 'n': USE_BITS (MN); break;
10394 case 'p': USE_BITS (MP); break;
10395 case 'q': USE_BITS (MQ); break;
10403 as_bad (_("Internal error: bad mips opcode "
10404 "(unknown extension operand type `%c%c'): %s %s"),
10405 e, c, opc->name, opc->args);
10409 case '.': USE_BITS (OFFSET10); break;
10410 case '1': USE_BITS (STYPE); break;
10411 case '<': USE_BITS (SHAMT); break;
10412 case '>': USE_BITS (SHAMT); break;
10413 case 'B': USE_BITS (CODE10); break;
10414 case 'C': USE_BITS (COPZ); break;
10415 case 'D': USE_BITS (FD); break;
10416 case 'E': USE_BITS (RT); break;
10417 case 'G': USE_BITS (RS); break;
10418 case 'H': USE_BITS (SEL); break;
10419 case 'K': USE_BITS (RS); break;
10420 case 'M': USE_BITS (CCC); break;
10421 case 'N': USE_BITS (BCC); break;
10422 case 'R': USE_BITS (FR); break;
10423 case 'S': USE_BITS (FS); break;
10424 case 'T': USE_BITS (FT); break;
10425 case 'V': USE_BITS (FS); break;
10426 case 'a': USE_BITS (TARGET); break;
10427 case 'b': USE_BITS (RS); break;
10428 case 'c': USE_BITS (CODE); break;
10429 case 'd': USE_BITS (RD); break;
10430 case 'h': USE_BITS (PREFX); break;
10431 case 'i': USE_BITS (IMMEDIATE); break;
10432 case 'j': USE_BITS (DELTA); break;
10433 case 'k': USE_BITS (CACHE); break;
10434 case 'n': USE_BITS (RT); break;
10435 case 'o': USE_BITS (DELTA); break;
10436 case 'p': USE_BITS (DELTA); break;
10437 case 'q': USE_BITS (CODE2); break;
10438 case 'r': USE_BITS (RS); break;
10439 case 's': USE_BITS (RS); break;
10440 case 't': USE_BITS (RT); break;
10441 case 'u': USE_BITS (IMMEDIATE); break;
10442 case 'v': USE_BITS (RS); break;
10443 case 'w': USE_BITS (RT); break;
10444 case 'y': USE_BITS (RS3); break;
10446 case '|': USE_BITS (TRAP); break;
10447 case '~': USE_BITS (OFFSET12); break;
10449 as_bad (_("Internal error: bad microMIPS opcode "
10450 "(unknown operand type `%c'): %s %s"),
10451 c, opc->name, opc->args);
10455 if (used_bits != insn_bits)
10457 if (~used_bits & insn_bits)
10458 as_bad (_("Internal error: bad microMIPS opcode "
10459 "(bits 0x%lx undefined): %s %s"),
10460 ~used_bits & insn_bits, opc->name, opc->args);
10461 if (used_bits & ~insn_bits)
10462 as_bad (_("Internal error: bad microMIPS opcode "
10463 "(bits 0x%lx defined): %s %s"),
10464 used_bits & ~insn_bits, opc->name, opc->args);
10470 /* UDI immediates. */
10471 struct mips_immed {
10473 unsigned int shift;
10474 unsigned long mask;
10478 static const struct mips_immed mips_immed[] = {
10479 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10480 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10481 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10482 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10486 /* Check whether an odd floating-point register is allowed. */
10488 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10490 const char *s = insn->name;
10492 if (insn->pinfo == INSN_MACRO)
10493 /* Let a macro pass, we'll catch it later when it is expanded. */
10496 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10498 /* Allow odd registers for single-precision ops. */
10499 switch (insn->pinfo & (FP_S | FP_D))
10503 return 1; /* both single precision - ok */
10505 return 0; /* both double precision - fail */
10510 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10511 s = strchr (insn->name, '.');
10513 s = s != NULL ? strchr (s + 1, '.') : NULL;
10514 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10517 /* Single-precision coprocessor loads and moves are OK too. */
10518 if ((insn->pinfo & FP_S)
10519 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10520 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10526 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10527 taking bits from BIT up. */
10529 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10531 return (ep->X_op == O_constant
10532 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10533 && ep->X_add_number >= min << bit
10534 && ep->X_add_number < max << bit);
10537 /* This routine assembles an instruction into its binary format. As a
10538 side effect, it sets one of the global variables imm_reloc or
10539 offset_reloc to the type of relocation to do if one of the operands
10540 is an address expression. */
10543 mips_ip (char *str, struct mips_cl_insn *ip)
10545 bfd_boolean wrong_delay_slot_insns = FALSE;
10546 bfd_boolean need_delay_slot_ok = TRUE;
10547 struct mips_opcode *firstinsn = NULL;
10548 const struct mips_opcode *past;
10549 struct hash_control *hash;
10553 struct mips_opcode *insn;
10555 unsigned int regno;
10556 unsigned int lastregno;
10557 unsigned int destregno = 0;
10558 unsigned int lastpos = 0;
10559 unsigned int limlo, limhi;
10561 offsetT min_range, max_range;
10565 unsigned int rtype;
10571 if (mips_opts.micromips)
10573 hash = micromips_op_hash;
10574 past = µmips_opcodes[bfd_micromips_num_opcodes];
10579 past = &mips_opcodes[NUMOPCODES];
10581 forced_insn_length = 0;
10584 /* We first try to match an instruction up to a space or to the end. */
10585 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10588 /* Make a copy of the instruction so that we can fiddle with it. */
10589 name = alloca (end + 1);
10590 memcpy (name, str, end);
10595 insn = (struct mips_opcode *) hash_find (hash, name);
10597 if (insn != NULL || !mips_opts.micromips)
10599 if (forced_insn_length)
10602 /* See if there's an instruction size override suffix,
10603 either `16' or `32', at the end of the mnemonic proper,
10604 that defines the operation, i.e. before the first `.'
10605 character if any. Strip it and retry. */
10606 dot = strchr (name, '.');
10607 opend = dot != NULL ? dot - name : end;
10610 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10611 forced_insn_length = 2;
10612 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10613 forced_insn_length = 4;
10616 memcpy (name + opend - 2, name + opend, end - opend + 1);
10620 insn_error = _("Unrecognized opcode");
10624 /* For microMIPS instructions placed in a fixed-length branch delay slot
10625 we make up to two passes over the relevant fragment of the opcode
10626 table. First we try instructions that meet the delay slot's length
10627 requirement. If none matched, then we retry with the remaining ones
10628 and if one matches, then we use it and then issue an appropriate
10629 warning later on. */
10630 argsStart = s = str + end;
10633 bfd_boolean delay_slot_ok;
10634 bfd_boolean size_ok;
10637 gas_assert (strcmp (insn->name, name) == 0);
10639 ok = is_opcode_valid (insn);
10640 size_ok = is_size_valid (insn);
10641 delay_slot_ok = is_delay_slot_valid (insn);
10642 if (!delay_slot_ok && !wrong_delay_slot_insns)
10645 wrong_delay_slot_insns = TRUE;
10647 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10649 static char buf[256];
10651 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10656 if (wrong_delay_slot_insns && need_delay_slot_ok)
10658 gas_assert (firstinsn);
10659 need_delay_slot_ok = FALSE;
10669 sprintf (buf, _("opcode not supported on this processor: %s (%s)"),
10670 mips_cpu_info_from_arch (mips_opts.arch)->name,
10671 mips_cpu_info_from_isa (mips_opts.isa)->name);
10673 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10674 8 * forced_insn_length);
10680 create_insn (ip, insn);
10683 lastregno = 0xffffffff;
10684 for (args = insn->args;; ++args)
10688 s += strspn (s, " \t");
10692 case '\0': /* end of args */
10697 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
10698 gas_assert (!mips_opts.micromips);
10699 my_getExpression (&imm_expr, s);
10700 check_absolute_expr (ip, &imm_expr);
10701 if ((unsigned long) imm_expr.X_add_number != 1
10702 && (unsigned long) imm_expr.X_add_number != 3)
10704 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10705 (unsigned long) imm_expr.X_add_number);
10707 INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number);
10708 imm_expr.X_op = O_absent;
10712 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
10713 gas_assert (!mips_opts.micromips);
10714 my_getExpression (&imm_expr, s);
10715 check_absolute_expr (ip, &imm_expr);
10716 if (imm_expr.X_add_number & ~OP_MASK_SA3)
10718 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10719 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
10721 INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number);
10722 imm_expr.X_op = O_absent;
10726 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
10727 gas_assert (!mips_opts.micromips);
10728 my_getExpression (&imm_expr, s);
10729 check_absolute_expr (ip, &imm_expr);
10730 if (imm_expr.X_add_number & ~OP_MASK_SA4)
10732 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10733 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
10735 INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number);
10736 imm_expr.X_op = O_absent;
10740 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
10741 gas_assert (!mips_opts.micromips);
10742 my_getExpression (&imm_expr, s);
10743 check_absolute_expr (ip, &imm_expr);
10744 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
10746 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10747 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
10749 INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number);
10750 imm_expr.X_op = O_absent;
10754 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
10755 gas_assert (!mips_opts.micromips);
10756 my_getExpression (&imm_expr, s);
10757 check_absolute_expr (ip, &imm_expr);
10758 if (imm_expr.X_add_number & ~OP_MASK_RS)
10760 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10761 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
10763 INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number);
10764 imm_expr.X_op = O_absent;
10768 case '7': /* Four DSP accumulators in bits 11,12. */
10769 gas_assert (!mips_opts.micromips);
10770 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10771 s[3] >= '0' && s[3] <= '3')
10773 regno = s[3] - '0';
10775 INSERT_OPERAND (0, DSPACC, *ip, regno);
10779 as_bad (_("Invalid dsp acc register"));
10782 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
10783 gas_assert (!mips_opts.micromips);
10784 my_getExpression (&imm_expr, s);
10785 check_absolute_expr (ip, &imm_expr);
10786 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
10788 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10790 (unsigned long) imm_expr.X_add_number);
10792 INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number);
10793 imm_expr.X_op = O_absent;
10797 case '9': /* Four DSP accumulators in bits 21,22. */
10798 gas_assert (!mips_opts.micromips);
10799 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10800 s[3] >= '0' && s[3] <= '3')
10802 regno = s[3] - '0';
10804 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10808 as_bad (_("Invalid dsp acc register"));
10811 case '0': /* DSP 6-bit signed immediate in bit 20. */
10812 gas_assert (!mips_opts.micromips);
10813 my_getExpression (&imm_expr, s);
10814 check_absolute_expr (ip, &imm_expr);
10815 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
10816 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
10817 if (imm_expr.X_add_number < min_range ||
10818 imm_expr.X_add_number > max_range)
10820 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10821 (long) min_range, (long) max_range,
10822 (long) imm_expr.X_add_number);
10824 INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number);
10825 imm_expr.X_op = O_absent;
10829 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10830 gas_assert (!mips_opts.micromips);
10831 my_getExpression (&imm_expr, s);
10832 check_absolute_expr (ip, &imm_expr);
10833 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10835 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10837 (unsigned long) imm_expr.X_add_number);
10839 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
10840 imm_expr.X_op = O_absent;
10844 case ':': /* DSP 7-bit signed immediate in bit 19. */
10845 gas_assert (!mips_opts.micromips);
10846 my_getExpression (&imm_expr, s);
10847 check_absolute_expr (ip, &imm_expr);
10848 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10849 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10850 if (imm_expr.X_add_number < min_range ||
10851 imm_expr.X_add_number > max_range)
10853 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10854 (long) min_range, (long) max_range,
10855 (long) imm_expr.X_add_number);
10857 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
10858 imm_expr.X_op = O_absent;
10862 case '@': /* DSP 10-bit signed immediate in bit 16. */
10863 gas_assert (!mips_opts.micromips);
10864 my_getExpression (&imm_expr, s);
10865 check_absolute_expr (ip, &imm_expr);
10866 min_range = -((OP_MASK_IMM10 + 1) >> 1);
10867 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
10868 if (imm_expr.X_add_number < min_range ||
10869 imm_expr.X_add_number > max_range)
10871 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10872 (long) min_range, (long) max_range,
10873 (long) imm_expr.X_add_number);
10875 INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number);
10876 imm_expr.X_op = O_absent;
10880 case '!': /* MT usermode flag bit. */
10881 gas_assert (!mips_opts.micromips);
10882 my_getExpression (&imm_expr, s);
10883 check_absolute_expr (ip, &imm_expr);
10884 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
10885 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10886 (unsigned long) imm_expr.X_add_number);
10887 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
10888 imm_expr.X_op = O_absent;
10892 case '$': /* MT load high flag bit. */
10893 gas_assert (!mips_opts.micromips);
10894 my_getExpression (&imm_expr, s);
10895 check_absolute_expr (ip, &imm_expr);
10896 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
10897 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10898 (unsigned long) imm_expr.X_add_number);
10899 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
10900 imm_expr.X_op = O_absent;
10904 case '*': /* Four DSP accumulators in bits 18,19. */
10905 gas_assert (!mips_opts.micromips);
10906 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10907 s[3] >= '0' && s[3] <= '3')
10909 regno = s[3] - '0';
10911 INSERT_OPERAND (0, MTACC_T, *ip, regno);
10915 as_bad (_("Invalid dsp/smartmips acc register"));
10918 case '&': /* Four DSP accumulators in bits 13,14. */
10919 gas_assert (!mips_opts.micromips);
10920 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10921 s[3] >= '0' && s[3] <= '3')
10923 regno = s[3] - '0';
10925 INSERT_OPERAND (0, MTACC_D, *ip, regno);
10929 as_bad (_("Invalid dsp/smartmips acc register"));
10941 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
10945 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
10949 gas_assert (!mips_opts.micromips);
10950 INSERT_OPERAND (0, FT, *ip, lastregno);
10954 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
10960 /* Handle optional base register.
10961 Either the base register is omitted or
10962 we must have a left paren. */
10963 /* This is dependent on the next operand specifier
10964 is a base register specification. */
10965 gas_assert (args[1] == 'b'
10966 || (mips_opts.micromips
10968 && (args[2] == 'l' || args[2] == 'n'
10969 || args[2] == 's' || args[2] == 'a')));
10970 if (*s == '\0' && args[1] == 'b')
10972 /* Fall through. */
10974 case ')': /* These must match exactly. */
10979 case '[': /* These must match exactly. */
10981 gas_assert (!mips_opts.micromips);
10986 case '+': /* Opcode extension character. */
10989 case '1': /* UDI immediates. */
10993 gas_assert (!mips_opts.micromips);
10995 const struct mips_immed *imm = mips_immed;
10997 while (imm->type && imm->type != *args)
11001 my_getExpression (&imm_expr, s);
11002 check_absolute_expr (ip, &imm_expr);
11003 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11005 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11006 imm->desc ? imm->desc : ip->insn_mo->name,
11007 (unsigned long) imm_expr.X_add_number,
11008 (unsigned long) imm_expr.X_add_number);
11009 imm_expr.X_add_number &= imm->mask;
11011 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11013 imm_expr.X_op = O_absent;
11018 case 'A': /* ins/ext position, becomes LSB. */
11027 my_getExpression (&imm_expr, s);
11028 check_absolute_expr (ip, &imm_expr);
11029 if ((unsigned long) imm_expr.X_add_number < limlo
11030 || (unsigned long) imm_expr.X_add_number > limhi)
11032 as_bad (_("Improper position (%lu)"),
11033 (unsigned long) imm_expr.X_add_number);
11034 imm_expr.X_add_number = limlo;
11036 lastpos = imm_expr.X_add_number;
11037 INSERT_OPERAND (mips_opts.micromips,
11038 EXTLSB, *ip, imm_expr.X_add_number);
11039 imm_expr.X_op = O_absent;
11043 case 'B': /* ins size, becomes MSB. */
11052 my_getExpression (&imm_expr, s);
11053 check_absolute_expr (ip, &imm_expr);
11054 /* Check for negative input so that small negative numbers
11055 will not succeed incorrectly. The checks against
11056 (pos+size) transitively check "size" itself,
11057 assuming that "pos" is reasonable. */
11058 if ((long) imm_expr.X_add_number < 0
11059 || ((unsigned long) imm_expr.X_add_number
11061 || ((unsigned long) imm_expr.X_add_number
11062 + lastpos) > limhi)
11064 as_bad (_("Improper insert size (%lu, position %lu)"),
11065 (unsigned long) imm_expr.X_add_number,
11066 (unsigned long) lastpos);
11067 imm_expr.X_add_number = limlo - lastpos;
11069 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11070 lastpos + imm_expr.X_add_number - 1);
11071 imm_expr.X_op = O_absent;
11075 case 'C': /* ext size, becomes MSBD. */
11088 my_getExpression (&imm_expr, s);
11089 check_absolute_expr (ip, &imm_expr);
11090 /* Check for negative input so that small negative numbers
11091 will not succeed incorrectly. The checks against
11092 (pos+size) transitively check "size" itself,
11093 assuming that "pos" is reasonable. */
11094 if ((long) imm_expr.X_add_number < 0
11095 || ((unsigned long) imm_expr.X_add_number
11097 || ((unsigned long) imm_expr.X_add_number
11098 + lastpos) > limhi)
11100 as_bad (_("Improper extract size (%lu, position %lu)"),
11101 (unsigned long) imm_expr.X_add_number,
11102 (unsigned long) lastpos);
11103 imm_expr.X_add_number = limlo - lastpos;
11105 INSERT_OPERAND (mips_opts.micromips,
11106 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11107 imm_expr.X_op = O_absent;
11112 /* +D is for disassembly only; never match. */
11116 /* "+I" is like "I", except that imm2_expr is used. */
11117 my_getExpression (&imm2_expr, s);
11118 if (imm2_expr.X_op != O_big
11119 && imm2_expr.X_op != O_constant)
11120 insn_error = _("absolute expression required");
11121 if (HAVE_32BIT_GPRS)
11122 normalize_constant_expr (&imm2_expr);
11126 case 'T': /* Coprocessor register. */
11127 gas_assert (!mips_opts.micromips);
11128 /* +T is for disassembly only; never match. */
11131 case 't': /* Coprocessor register number. */
11132 gas_assert (!mips_opts.micromips);
11133 if (s[0] == '$' && ISDIGIT (s[1]))
11143 while (ISDIGIT (*s));
11145 as_bad (_("Invalid register number (%d)"), regno);
11148 INSERT_OPERAND (0, RT, *ip, regno);
11153 as_bad (_("Invalid coprocessor 0 register number"));
11157 /* bbit[01] and bbit[01]32 bit index. Give error if index
11158 is not in the valid range. */
11159 gas_assert (!mips_opts.micromips);
11160 my_getExpression (&imm_expr, s);
11161 check_absolute_expr (ip, &imm_expr);
11162 if ((unsigned) imm_expr.X_add_number > 31)
11164 as_bad (_("Improper bit index (%lu)"),
11165 (unsigned long) imm_expr.X_add_number);
11166 imm_expr.X_add_number = 0;
11168 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11169 imm_expr.X_op = O_absent;
11174 /* bbit[01] bit index when bbit is used but we generate
11175 bbit[01]32 because the index is over 32. Move to the
11176 next candidate if index is not in the valid range. */
11177 gas_assert (!mips_opts.micromips);
11178 my_getExpression (&imm_expr, s);
11179 check_absolute_expr (ip, &imm_expr);
11180 if ((unsigned) imm_expr.X_add_number < 32
11181 || (unsigned) imm_expr.X_add_number > 63)
11183 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11184 imm_expr.X_op = O_absent;
11189 /* cins, cins32, exts and exts32 position field. Give error
11190 if it's not in the valid range. */
11191 gas_assert (!mips_opts.micromips);
11192 my_getExpression (&imm_expr, s);
11193 check_absolute_expr (ip, &imm_expr);
11194 if ((unsigned) imm_expr.X_add_number > 31)
11196 as_bad (_("Improper position (%lu)"),
11197 (unsigned long) imm_expr.X_add_number);
11198 imm_expr.X_add_number = 0;
11200 /* Make the pos explicit to simplify +S. */
11201 lastpos = imm_expr.X_add_number + 32;
11202 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11203 imm_expr.X_op = O_absent;
11208 /* cins, cins32, exts and exts32 position field. Move to
11209 the next candidate if it's not in the valid range. */
11210 gas_assert (!mips_opts.micromips);
11211 my_getExpression (&imm_expr, s);
11212 check_absolute_expr (ip, &imm_expr);
11213 if ((unsigned) imm_expr.X_add_number < 32
11214 || (unsigned) imm_expr.X_add_number > 63)
11216 lastpos = imm_expr.X_add_number;
11217 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11218 imm_expr.X_op = O_absent;
11223 /* cins and exts length-minus-one field. */
11224 gas_assert (!mips_opts.micromips);
11225 my_getExpression (&imm_expr, s);
11226 check_absolute_expr (ip, &imm_expr);
11227 if ((unsigned long) imm_expr.X_add_number > 31)
11229 as_bad (_("Improper size (%lu)"),
11230 (unsigned long) imm_expr.X_add_number);
11231 imm_expr.X_add_number = 0;
11233 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11234 imm_expr.X_op = O_absent;
11239 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11240 length-minus-one field. */
11241 gas_assert (!mips_opts.micromips);
11242 my_getExpression (&imm_expr, s);
11243 check_absolute_expr (ip, &imm_expr);
11244 if ((long) imm_expr.X_add_number < 0
11245 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11247 as_bad (_("Improper size (%lu)"),
11248 (unsigned long) imm_expr.X_add_number);
11249 imm_expr.X_add_number = 0;
11251 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11252 imm_expr.X_op = O_absent;
11257 /* seqi/snei immediate field. */
11258 gas_assert (!mips_opts.micromips);
11259 my_getExpression (&imm_expr, s);
11260 check_absolute_expr (ip, &imm_expr);
11261 if ((long) imm_expr.X_add_number < -512
11262 || (long) imm_expr.X_add_number >= 512)
11264 as_bad (_("Improper immediate (%ld)"),
11265 (long) imm_expr.X_add_number);
11266 imm_expr.X_add_number = 0;
11268 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11269 imm_expr.X_op = O_absent;
11273 case 'a': /* 8-bit signed offset in bit 6 */
11274 gas_assert (!mips_opts.micromips);
11275 my_getExpression (&imm_expr, s);
11276 check_absolute_expr (ip, &imm_expr);
11277 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11278 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11279 if (imm_expr.X_add_number < min_range
11280 || imm_expr.X_add_number > max_range)
11282 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11283 (long) min_range, (long) max_range,
11284 (long) imm_expr.X_add_number);
11286 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11287 imm_expr.X_op = O_absent;
11291 case 'b': /* 8-bit signed offset in bit 3 */
11292 gas_assert (!mips_opts.micromips);
11293 my_getExpression (&imm_expr, s);
11294 check_absolute_expr (ip, &imm_expr);
11295 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11296 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11297 if (imm_expr.X_add_number < min_range
11298 || imm_expr.X_add_number > max_range)
11300 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11301 (long) min_range, (long) max_range,
11302 (long) imm_expr.X_add_number);
11304 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11305 imm_expr.X_op = O_absent;
11309 case 'c': /* 9-bit signed offset in bit 6 */
11310 gas_assert (!mips_opts.micromips);
11311 my_getExpression (&imm_expr, s);
11312 check_absolute_expr (ip, &imm_expr);
11313 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11314 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11315 /* We check the offset range before adjusted. */
11318 if (imm_expr.X_add_number < min_range
11319 || imm_expr.X_add_number > max_range)
11321 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11322 (long) min_range, (long) max_range,
11323 (long) imm_expr.X_add_number);
11325 if (imm_expr.X_add_number & 0xf)
11327 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11328 (long) imm_expr.X_add_number);
11330 /* Right shift 4 bits to adjust the offset operand. */
11331 INSERT_OPERAND (0, OFFSET_C, *ip,
11332 imm_expr.X_add_number >> 4);
11333 imm_expr.X_op = O_absent;
11338 gas_assert (!mips_opts.micromips);
11339 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11341 if (regno == AT && mips_opts.at)
11343 if (mips_opts.at == ATREG)
11344 as_warn (_("used $at without \".set noat\""));
11346 as_warn (_("used $%u with \".set at=$%u\""),
11347 regno, mips_opts.at);
11349 INSERT_OPERAND (0, RZ, *ip, regno);
11353 gas_assert (!mips_opts.micromips);
11354 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11356 INSERT_OPERAND (0, FZ, *ip, regno);
11360 as_bad (_("Internal error: bad %s opcode "
11361 "(unknown extension operand type `+%c'): %s %s"),
11362 mips_opts.micromips ? "microMIPS" : "MIPS",
11363 *args, insn->name, insn->args);
11364 /* Further processing is fruitless. */
11369 case '.': /* 10-bit offset. */
11370 case '~': /* 12-bit offset. */
11371 gas_assert (mips_opts.micromips);
11373 int shift = *args == '.' ? 9 : 11;
11376 /* Check whether there is only a single bracketed expression
11377 left. If so, it must be the base register and the
11378 constant must be zero. */
11379 if (*s == '(' && strchr (s + 1, '(') == 0)
11382 /* If this value won't fit into the offset, then go find
11383 a macro that will generate a 16- or 32-bit offset code
11385 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11386 if ((i == 0 && (imm_expr.X_op != O_constant
11387 || imm_expr.X_add_number >= 1 << shift
11388 || imm_expr.X_add_number < -1 << shift))
11391 imm_expr.X_op = O_absent;
11395 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11397 INSERT_OPERAND (1, OFFSET12, *ip, imm_expr.X_add_number);
11398 imm_expr.X_op = O_absent;
11403 case '<': /* must be at least one digit */
11405 * According to the manual, if the shift amount is greater
11406 * than 31 or less than 0, then the shift amount should be
11407 * mod 32. In reality the mips assembler issues an error.
11408 * We issue a warning and mask out all but the low 5 bits.
11410 my_getExpression (&imm_expr, s);
11411 check_absolute_expr (ip, &imm_expr);
11412 if ((unsigned long) imm_expr.X_add_number > 31)
11413 as_warn (_("Improper shift amount (%lu)"),
11414 (unsigned long) imm_expr.X_add_number);
11415 INSERT_OPERAND (mips_opts.micromips,
11416 SHAMT, *ip, imm_expr.X_add_number);
11417 imm_expr.X_op = O_absent;
11421 case '>': /* shift amount minus 32 */
11422 my_getExpression (&imm_expr, s);
11423 check_absolute_expr (ip, &imm_expr);
11424 if ((unsigned long) imm_expr.X_add_number < 32
11425 || (unsigned long) imm_expr.X_add_number > 63)
11427 INSERT_OPERAND (mips_opts.micromips,
11428 SHAMT, *ip, imm_expr.X_add_number - 32);
11429 imm_expr.X_op = O_absent;
11433 case 'k': /* CACHE code. */
11434 case 'h': /* PREFX code. */
11435 case '1': /* SYNC type. */
11436 my_getExpression (&imm_expr, s);
11437 check_absolute_expr (ip, &imm_expr);
11438 if ((unsigned long) imm_expr.X_add_number > 31)
11439 as_warn (_("Invalid value for `%s' (%lu)"),
11441 (unsigned long) imm_expr.X_add_number);
11445 if (mips_fix_cn63xxp1
11446 && !mips_opts.micromips
11447 && strcmp ("pref", insn->name) == 0)
11448 switch (imm_expr.X_add_number)
11457 case 31: /* These are ok. */
11460 default: /* The rest must be changed to 28. */
11461 imm_expr.X_add_number = 28;
11464 INSERT_OPERAND (mips_opts.micromips,
11465 CACHE, *ip, imm_expr.X_add_number);
11468 INSERT_OPERAND (mips_opts.micromips,
11469 PREFX, *ip, imm_expr.X_add_number);
11472 INSERT_OPERAND (mips_opts.micromips,
11473 STYPE, *ip, imm_expr.X_add_number);
11476 imm_expr.X_op = O_absent;
11480 case 'c': /* BREAK code. */
11482 unsigned long mask = (mips_opts.micromips
11483 ? MICROMIPSOP_MASK_CODE
11486 my_getExpression (&imm_expr, s);
11487 check_absolute_expr (ip, &imm_expr);
11488 if ((unsigned long) imm_expr.X_add_number > mask)
11489 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11491 mask, (unsigned long) imm_expr.X_add_number);
11492 INSERT_OPERAND (mips_opts.micromips,
11493 CODE, *ip, imm_expr.X_add_number);
11494 imm_expr.X_op = O_absent;
11499 case 'q': /* Lower BREAK code. */
11501 unsigned long mask = (mips_opts.micromips
11502 ? MICROMIPSOP_MASK_CODE2
11505 my_getExpression (&imm_expr, s);
11506 check_absolute_expr (ip, &imm_expr);
11507 if ((unsigned long) imm_expr.X_add_number > mask)
11508 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11510 mask, (unsigned long) imm_expr.X_add_number);
11511 INSERT_OPERAND (mips_opts.micromips,
11512 CODE2, *ip, imm_expr.X_add_number);
11513 imm_expr.X_op = O_absent;
11518 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11520 unsigned long mask = (mips_opts.micromips
11521 ? MICROMIPSOP_MASK_CODE10
11524 my_getExpression (&imm_expr, s);
11525 check_absolute_expr (ip, &imm_expr);
11526 if ((unsigned long) imm_expr.X_add_number > mask)
11527 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11529 mask, (unsigned long) imm_expr.X_add_number);
11530 if (mips_opts.micromips)
11531 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11533 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11534 imm_expr.X_op = O_absent;
11539 case 'C': /* 25- or 23-bit coprocessor code. */
11541 unsigned long mask = (mips_opts.micromips
11542 ? MICROMIPSOP_MASK_COPZ
11545 my_getExpression (&imm_expr, s);
11546 check_absolute_expr (ip, &imm_expr);
11547 if ((unsigned long) imm_expr.X_add_number > mask)
11548 as_warn (_("Coproccesor code > %u bits (%lu)"),
11549 mips_opts.micromips ? 23U : 25U,
11550 (unsigned long) imm_expr.X_add_number);
11551 INSERT_OPERAND (mips_opts.micromips,
11552 COPZ, *ip, imm_expr.X_add_number);
11553 imm_expr.X_op = O_absent;
11558 case 'J': /* 19-bit WAIT code. */
11559 gas_assert (!mips_opts.micromips);
11560 my_getExpression (&imm_expr, s);
11561 check_absolute_expr (ip, &imm_expr);
11562 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11564 as_warn (_("Illegal 19-bit code (%lu)"),
11565 (unsigned long) imm_expr.X_add_number);
11566 imm_expr.X_add_number &= OP_MASK_CODE19;
11568 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11569 imm_expr.X_op = O_absent;
11573 case 'P': /* Performance register. */
11574 gas_assert (!mips_opts.micromips);
11575 my_getExpression (&imm_expr, s);
11576 check_absolute_expr (ip, &imm_expr);
11577 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11578 as_warn (_("Invalid performance register (%lu)"),
11579 (unsigned long) imm_expr.X_add_number);
11580 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11581 imm_expr.X_op = O_absent;
11585 case 'G': /* Coprocessor destination register. */
11587 unsigned long opcode = ip->insn_opcode;
11588 unsigned long mask;
11589 unsigned int types;
11592 if (mips_opts.micromips)
11594 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11595 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11596 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11600 case 0x000000fc: /* mfc0 */
11601 case 0x000002fc: /* mtc0 */
11602 case 0x580000fc: /* dmfc0 */
11603 case 0x580002fc: /* dmtc0 */
11613 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11614 cop0 = opcode == OP_OP_COP0;
11616 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11617 ok = reg_lookup (&s, types, ®no);
11618 if (mips_opts.micromips)
11619 INSERT_OPERAND (1, RS, *ip, regno);
11621 INSERT_OPERAND (0, RD, *ip, regno);
11630 case 'y': /* ALNV.PS source register. */
11631 gas_assert (mips_opts.micromips);
11633 case 'x': /* Ignore register name. */
11634 case 'U': /* Destination register (CLO/CLZ). */
11635 case 'g': /* Coprocessor destination register. */
11636 gas_assert (!mips_opts.micromips);
11637 case 'b': /* Base register. */
11638 case 'd': /* Destination register. */
11639 case 's': /* Source register. */
11640 case 't': /* Target register. */
11641 case 'r': /* Both target and source. */
11642 case 'v': /* Both dest and source. */
11643 case 'w': /* Both dest and target. */
11644 case 'E': /* Coprocessor target register. */
11645 case 'K': /* RDHWR destination register. */
11646 case 'z': /* Must be zero register. */
11649 if (*args == 'E' || *args == 'K')
11650 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11653 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11654 if (regno == AT && mips_opts.at)
11656 if (mips_opts.at == ATREG)
11657 as_warn (_("Used $at without \".set noat\""));
11659 as_warn (_("Used $%u with \".set at=$%u\""),
11660 regno, mips_opts.at);
11670 if (c == 'r' || c == 'v' || c == 'w')
11677 /* 'z' only matches $0. */
11678 if (c == 'z' && regno != 0)
11681 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11683 if (regno == lastregno)
11686 = _("Source and destination must be different");
11689 if (regno == 31 && lastregno == 0xffffffff)
11692 = _("A destination register must be supplied");
11696 /* Now that we have assembled one operand, we use the args
11697 string to figure out where it goes in the instruction. */
11704 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11708 if (mips_opts.micromips)
11709 INSERT_OPERAND (1, RS, *ip, regno);
11711 INSERT_OPERAND (0, RD, *ip, regno);
11716 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11720 gas_assert (!mips_opts.micromips);
11721 INSERT_OPERAND (0, RD, *ip, regno);
11722 INSERT_OPERAND (0, RT, *ip, regno);
11728 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11732 gas_assert (mips_opts.micromips);
11733 INSERT_OPERAND (1, RS3, *ip, regno);
11737 /* This case exists because on the r3000 trunc
11738 expands into a macro which requires a gp
11739 register. On the r6000 or r4000 it is
11740 assembled into a single instruction which
11741 ignores the register. Thus the insn version
11742 is MIPS_ISA2 and uses 'x', and the macro
11743 version is MIPS_ISA1 and uses 't'. */
11747 /* This case is for the div instruction, which
11748 acts differently if the destination argument
11749 is $0. This only matches $0, and is checked
11750 outside the switch. */
11760 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11764 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11769 case 'O': /* MDMX alignment immediate constant. */
11770 gas_assert (!mips_opts.micromips);
11771 my_getExpression (&imm_expr, s);
11772 check_absolute_expr (ip, &imm_expr);
11773 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11774 as_warn (_("Improper align amount (%ld), using low bits"),
11775 (long) imm_expr.X_add_number);
11776 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11777 imm_expr.X_op = O_absent;
11781 case 'Q': /* MDMX vector, element sel, or const. */
11784 /* MDMX Immediate. */
11785 gas_assert (!mips_opts.micromips);
11786 my_getExpression (&imm_expr, s);
11787 check_absolute_expr (ip, &imm_expr);
11788 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
11789 as_warn (_("Invalid MDMX Immediate (%ld)"),
11790 (long) imm_expr.X_add_number);
11791 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
11792 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11793 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11795 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
11796 imm_expr.X_op = O_absent;
11800 /* Not MDMX Immediate. Fall through. */
11801 case 'X': /* MDMX destination register. */
11802 case 'Y': /* MDMX source register. */
11803 case 'Z': /* MDMX target register. */
11806 gas_assert (!mips_opts.micromips);
11807 case 'D': /* Floating point destination register. */
11808 case 'S': /* Floating point source register. */
11809 case 'T': /* Floating point target register. */
11810 case 'R': /* Floating point source register. */
11814 || (mips_opts.ase_mdmx
11815 && (ip->insn_mo->pinfo & FP_D)
11816 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11817 | INSN_COPROC_MEMORY_DELAY
11818 | INSN_LOAD_COPROC_DELAY
11819 | INSN_LOAD_MEMORY_DELAY
11820 | INSN_STORE_MEMORY))))
11821 rtype |= RTYPE_VEC;
11823 if (reg_lookup (&s, rtype, ®no))
11825 if ((regno & 1) != 0
11827 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
11828 as_warn (_("Float register should be even, was %d"),
11836 if (c == 'V' || c == 'W')
11847 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
11853 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
11857 /* This is like 'Z', but also needs to fix the MDMX
11858 vector/scalar select bits. Note that the
11859 scalar immediate case is handled above. */
11862 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
11863 int max_el = (is_qh ? 3 : 7);
11865 my_getExpression(&imm_expr, s);
11866 check_absolute_expr (ip, &imm_expr);
11868 if (imm_expr.X_add_number > max_el)
11869 as_bad (_("Bad element selector %ld"),
11870 (long) imm_expr.X_add_number);
11871 imm_expr.X_add_number &= max_el;
11872 ip->insn_opcode |= (imm_expr.X_add_number
11875 imm_expr.X_op = O_absent;
11877 as_warn (_("Expecting ']' found '%s'"), s);
11883 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11884 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
11887 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
11890 /* Fall through. */
11894 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
11898 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
11908 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11912 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
11918 my_getExpression (&imm_expr, s);
11919 if (imm_expr.X_op != O_big
11920 && imm_expr.X_op != O_constant)
11921 insn_error = _("absolute expression required");
11922 if (HAVE_32BIT_GPRS)
11923 normalize_constant_expr (&imm_expr);
11928 my_getExpression (&offset_expr, s);
11929 normalize_address_expr (&offset_expr);
11930 *imm_reloc = BFD_RELOC_32;
11943 unsigned char temp[8];
11945 unsigned int length;
11950 /* These only appear as the last operand in an
11951 instruction, and every instruction that accepts
11952 them in any variant accepts them in all variants.
11953 This means we don't have to worry about backing out
11954 any changes if the instruction does not match.
11956 The difference between them is the size of the
11957 floating point constant and where it goes. For 'F'
11958 and 'L' the constant is 64 bits; for 'f' and 'l' it
11959 is 32 bits. Where the constant is placed is based
11960 on how the MIPS assembler does things:
11963 f -- immediate value
11966 The .lit4 and .lit8 sections are only used if
11967 permitted by the -G argument.
11969 The code below needs to know whether the target register
11970 is 32 or 64 bits wide. It relies on the fact 'f' and
11971 'F' are used with GPR-based instructions and 'l' and
11972 'L' are used with FPR-based instructions. */
11974 f64 = *args == 'F' || *args == 'L';
11975 using_gprs = *args == 'F' || *args == 'f';
11977 save_in = input_line_pointer;
11978 input_line_pointer = s;
11979 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
11981 s = input_line_pointer;
11982 input_line_pointer = save_in;
11983 if (err != NULL && *err != '\0')
11985 as_bad (_("Bad floating point constant: %s"), err);
11986 memset (temp, '\0', sizeof temp);
11987 length = f64 ? 8 : 4;
11990 gas_assert (length == (unsigned) (f64 ? 8 : 4));
11994 && (g_switch_value < 4
11995 || (temp[0] == 0 && temp[1] == 0)
11996 || (temp[2] == 0 && temp[3] == 0))))
11998 imm_expr.X_op = O_constant;
11999 if (!target_big_endian)
12000 imm_expr.X_add_number = bfd_getl32 (temp);
12002 imm_expr.X_add_number = bfd_getb32 (temp);
12004 else if (length > 4
12005 && !mips_disable_float_construction
12006 /* Constants can only be constructed in GPRs and
12007 copied to FPRs if the GPRs are at least as wide
12008 as the FPRs. Force the constant into memory if
12009 we are using 64-bit FPRs but the GPRs are only
12012 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12013 && ((temp[0] == 0 && temp[1] == 0)
12014 || (temp[2] == 0 && temp[3] == 0))
12015 && ((temp[4] == 0 && temp[5] == 0)
12016 || (temp[6] == 0 && temp[7] == 0)))
12018 /* The value is simple enough to load with a couple of
12019 instructions. If using 32-bit registers, set
12020 imm_expr to the high order 32 bits and offset_expr to
12021 the low order 32 bits. Otherwise, set imm_expr to
12022 the entire 64 bit constant. */
12023 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12025 imm_expr.X_op = O_constant;
12026 offset_expr.X_op = O_constant;
12027 if (!target_big_endian)
12029 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12030 offset_expr.X_add_number = bfd_getl32 (temp);
12034 imm_expr.X_add_number = bfd_getb32 (temp);
12035 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12037 if (offset_expr.X_add_number == 0)
12038 offset_expr.X_op = O_absent;
12040 else if (sizeof (imm_expr.X_add_number) > 4)
12042 imm_expr.X_op = O_constant;
12043 if (!target_big_endian)
12044 imm_expr.X_add_number = bfd_getl64 (temp);
12046 imm_expr.X_add_number = bfd_getb64 (temp);
12050 imm_expr.X_op = O_big;
12051 imm_expr.X_add_number = 4;
12052 if (!target_big_endian)
12054 generic_bignum[0] = bfd_getl16 (temp);
12055 generic_bignum[1] = bfd_getl16 (temp + 2);
12056 generic_bignum[2] = bfd_getl16 (temp + 4);
12057 generic_bignum[3] = bfd_getl16 (temp + 6);
12061 generic_bignum[0] = bfd_getb16 (temp + 6);
12062 generic_bignum[1] = bfd_getb16 (temp + 4);
12063 generic_bignum[2] = bfd_getb16 (temp + 2);
12064 generic_bignum[3] = bfd_getb16 (temp);
12070 const char *newname;
12073 /* Switch to the right section. */
12075 subseg = now_subseg;
12078 default: /* unused default case avoids warnings. */
12080 newname = RDATA_SECTION_NAME;
12081 if (g_switch_value >= 8)
12085 newname = RDATA_SECTION_NAME;
12088 gas_assert (g_switch_value >= 4);
12092 new_seg = subseg_new (newname, (subsegT) 0);
12094 bfd_set_section_flags (stdoutput, new_seg,
12099 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12100 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12101 record_alignment (new_seg, 4);
12103 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12104 if (seg == now_seg)
12105 as_bad (_("Can't use floating point insn in this section"));
12107 /* Set the argument to the current address in the
12109 offset_expr.X_op = O_symbol;
12110 offset_expr.X_add_symbol = symbol_temp_new_now ();
12111 offset_expr.X_add_number = 0;
12113 /* Put the floating point number into the section. */
12114 p = frag_more ((int) length);
12115 memcpy (p, temp, length);
12117 /* Switch back to the original section. */
12118 subseg_set (seg, subseg);
12123 case 'i': /* 16-bit unsigned immediate. */
12124 case 'j': /* 16-bit signed immediate. */
12125 *imm_reloc = BFD_RELOC_LO16;
12126 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12129 offsetT minval, maxval;
12131 more = (insn + 1 < past
12132 && strcmp (insn->name, insn[1].name) == 0);
12134 /* If the expression was written as an unsigned number,
12135 only treat it as signed if there are no more
12139 && sizeof (imm_expr.X_add_number) <= 4
12140 && imm_expr.X_op == O_constant
12141 && imm_expr.X_add_number < 0
12142 && imm_expr.X_unsigned
12143 && HAVE_64BIT_GPRS)
12146 /* For compatibility with older assemblers, we accept
12147 0x8000-0xffff as signed 16-bit numbers when only
12148 signed numbers are allowed. */
12150 minval = 0, maxval = 0xffff;
12152 minval = -0x8000, maxval = 0x7fff;
12154 minval = -0x8000, maxval = 0xffff;
12156 if (imm_expr.X_op != O_constant
12157 || imm_expr.X_add_number < minval
12158 || imm_expr.X_add_number > maxval)
12162 if (imm_expr.X_op == O_constant
12163 || imm_expr.X_op == O_big)
12164 as_bad (_("Expression out of range"));
12170 case 'o': /* 16-bit offset. */
12171 offset_reloc[0] = BFD_RELOC_LO16;
12172 offset_reloc[1] = BFD_RELOC_UNUSED;
12173 offset_reloc[2] = BFD_RELOC_UNUSED;
12175 /* Check whether there is only a single bracketed expression
12176 left. If so, it must be the base register and the
12177 constant must be zero. */
12178 if (*s == '(' && strchr (s + 1, '(') == 0)
12180 offset_expr.X_op = O_constant;
12181 offset_expr.X_add_number = 0;
12185 /* If this value won't fit into a 16 bit offset, then go
12186 find a macro that will generate the 32 bit offset
12188 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12189 && (offset_expr.X_op != O_constant
12190 || offset_expr.X_add_number >= 0x8000
12191 || offset_expr.X_add_number < -0x8000))
12197 case 'p': /* PC-relative offset. */
12198 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12199 my_getExpression (&offset_expr, s);
12203 case 'u': /* Upper 16 bits. */
12204 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12205 && imm_expr.X_op == O_constant
12206 && (imm_expr.X_add_number < 0
12207 || imm_expr.X_add_number >= 0x10000))
12208 as_bad (_("lui expression (%lu) not in range 0..65535"),
12209 (unsigned long) imm_expr.X_add_number);
12213 case 'a': /* 26-bit address. */
12214 *offset_reloc = BFD_RELOC_MIPS_JMP;
12215 my_getExpression (&offset_expr, s);
12219 case 'N': /* 3-bit branch condition code. */
12220 case 'M': /* 3-bit compare condition code. */
12222 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12223 rtype |= RTYPE_FCC;
12224 if (!reg_lookup (&s, rtype, ®no))
12226 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12227 || strcmp (str + strlen (str) - 5, "any2f") == 0
12228 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12229 && (regno & 1) != 0)
12230 as_warn (_("Condition code register should be even for %s, "
12233 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12234 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12235 && (regno & 3) != 0)
12236 as_warn (_("Condition code register should be 0 or 4 for %s, "
12240 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12242 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12246 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12257 while (ISDIGIT (*s));
12260 c = 8; /* Invalid sel value. */
12263 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12264 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12268 gas_assert (!mips_opts.micromips);
12269 /* Must be at least one digit. */
12270 my_getExpression (&imm_expr, s);
12271 check_absolute_expr (ip, &imm_expr);
12273 if ((unsigned long) imm_expr.X_add_number
12274 > (unsigned long) OP_MASK_VECBYTE)
12276 as_bad (_("bad byte vector index (%ld)"),
12277 (long) imm_expr.X_add_number);
12278 imm_expr.X_add_number = 0;
12281 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12282 imm_expr.X_op = O_absent;
12287 gas_assert (!mips_opts.micromips);
12288 my_getExpression (&imm_expr, s);
12289 check_absolute_expr (ip, &imm_expr);
12291 if ((unsigned long) imm_expr.X_add_number
12292 > (unsigned long) OP_MASK_VECALIGN)
12294 as_bad (_("bad byte vector index (%ld)"),
12295 (long) imm_expr.X_add_number);
12296 imm_expr.X_add_number = 0;
12299 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12300 imm_expr.X_op = O_absent;
12304 case 'm': /* Opcode extension character. */
12305 gas_assert (mips_opts.micromips);
12310 if (strncmp (s, "$pc", 3) == 0)
12338 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12339 if (regno == AT && mips_opts.at)
12341 if (mips_opts.at == ATREG)
12342 as_warn (_("Used $at without \".set noat\""));
12344 as_warn (_("Used $%u with \".set at=$%u\""),
12345 regno, mips_opts.at);
12351 gas_assert (args[1] == ',');
12357 gas_assert (args[1] == ',');
12359 continue; /* Nothing to do. */
12365 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12367 if (regno == lastregno)
12370 = _("Source and destination must be different");
12373 if (regno == 31 && lastregno == 0xffffffff)
12376 = _("A destination register must be supplied");
12387 gas_assert (args[1] == ',');
12394 gas_assert (args[1] == ',');
12397 continue; /* Nothing to do. */
12401 /* Make sure regno is the same as lastregno. */
12402 if (c == 't' && regno != lastregno)
12405 /* Make sure regno is the same as destregno. */
12406 if (c == 'x' && regno != destregno)
12409 /* We need to save regno, before regno maps to the
12410 microMIPS register encoding. */
12420 regno = ILLEGAL_REG;
12424 regno = mips32_to_micromips_reg_b_map[regno];
12428 regno = mips32_to_micromips_reg_c_map[regno];
12432 regno = mips32_to_micromips_reg_d_map[regno];
12436 regno = mips32_to_micromips_reg_e_map[regno];
12440 regno = mips32_to_micromips_reg_f_map[regno];
12444 regno = mips32_to_micromips_reg_g_map[regno];
12448 regno = mips32_to_micromips_reg_h_map[regno];
12452 switch (EXTRACT_OPERAND (1, MI, *ip))
12457 else if (regno == 22)
12459 else if (regno == 5)
12461 else if (regno == 6)
12463 else if (regno == 7)
12466 regno = ILLEGAL_REG;
12472 else if (regno == 7)
12475 regno = ILLEGAL_REG;
12482 regno = ILLEGAL_REG;
12486 regno = ILLEGAL_REG;
12492 regno = mips32_to_micromips_reg_l_map[regno];
12496 regno = mips32_to_micromips_reg_m_map[regno];
12500 regno = mips32_to_micromips_reg_n_map[regno];
12504 regno = mips32_to_micromips_reg_q_map[regno];
12509 regno = ILLEGAL_REG;
12514 regno = ILLEGAL_REG;
12519 regno = ILLEGAL_REG;
12522 case 'j': /* Do nothing. */
12532 if (regno == ILLEGAL_REG)
12538 INSERT_OPERAND (1, MB, *ip, regno);
12542 INSERT_OPERAND (1, MC, *ip, regno);
12546 INSERT_OPERAND (1, MD, *ip, regno);
12550 INSERT_OPERAND (1, ME, *ip, regno);
12554 INSERT_OPERAND (1, MF, *ip, regno);
12558 INSERT_OPERAND (1, MG, *ip, regno);
12562 INSERT_OPERAND (1, MH, *ip, regno);
12566 INSERT_OPERAND (1, MI, *ip, regno);
12570 INSERT_OPERAND (1, MJ, *ip, regno);
12574 INSERT_OPERAND (1, ML, *ip, regno);
12578 INSERT_OPERAND (1, MM, *ip, regno);
12582 INSERT_OPERAND (1, MN, *ip, regno);
12586 INSERT_OPERAND (1, MP, *ip, regno);
12590 INSERT_OPERAND (1, MQ, *ip, regno);
12593 case 'a': /* Do nothing. */
12594 case 's': /* Do nothing. */
12595 case 't': /* Do nothing. */
12596 case 'x': /* Do nothing. */
12597 case 'y': /* Do nothing. */
12598 case 'z': /* Do nothing. */
12608 bfd_reloc_code_real_type r[3];
12612 /* Check whether there is only a single bracketed
12613 expression left. If so, it must be the base register
12614 and the constant must be zero. */
12615 if (*s == '(' && strchr (s + 1, '(') == 0)
12617 INSERT_OPERAND (1, IMMA, *ip, 0);
12621 if (my_getSmallExpression (&ep, r, s) > 0
12622 || !expr_const_in_range (&ep, -64, 64, 2))
12625 imm = ep.X_add_number >> 2;
12626 INSERT_OPERAND (1, IMMA, *ip, imm);
12633 bfd_reloc_code_real_type r[3];
12637 if (my_getSmallExpression (&ep, r, s) > 0
12638 || ep.X_op != O_constant)
12641 for (imm = 0; imm < 8; imm++)
12642 if (micromips_imm_b_map[imm] == ep.X_add_number)
12647 INSERT_OPERAND (1, IMMB, *ip, imm);
12654 bfd_reloc_code_real_type r[3];
12658 if (my_getSmallExpression (&ep, r, s) > 0
12659 || ep.X_op != O_constant)
12662 for (imm = 0; imm < 16; imm++)
12663 if (micromips_imm_c_map[imm] == ep.X_add_number)
12668 INSERT_OPERAND (1, IMMC, *ip, imm);
12673 case 'D': /* pc relative offset */
12674 case 'E': /* pc relative offset */
12675 my_getExpression (&offset_expr, s);
12676 if (offset_expr.X_op == O_register)
12679 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12685 bfd_reloc_code_real_type r[3];
12689 if (my_getSmallExpression (&ep, r, s) > 0
12690 || !expr_const_in_range (&ep, 0, 16, 0))
12693 imm = ep.X_add_number;
12694 INSERT_OPERAND (1, IMMF, *ip, imm);
12701 bfd_reloc_code_real_type r[3];
12705 /* Check whether there is only a single bracketed
12706 expression left. If so, it must be the base register
12707 and the constant must be zero. */
12708 if (*s == '(' && strchr (s + 1, '(') == 0)
12710 INSERT_OPERAND (1, IMMG, *ip, 0);
12714 if (my_getSmallExpression (&ep, r, s) > 0
12715 || !expr_const_in_range (&ep, -1, 15, 0))
12718 imm = ep.X_add_number & 15;
12719 INSERT_OPERAND (1, IMMG, *ip, imm);
12726 bfd_reloc_code_real_type r[3];
12730 /* Check whether there is only a single bracketed
12731 expression left. If so, it must be the base register
12732 and the constant must be zero. */
12733 if (*s == '(' && strchr (s + 1, '(') == 0)
12735 INSERT_OPERAND (1, IMMH, *ip, 0);
12739 if (my_getSmallExpression (&ep, r, s) > 0
12740 || !expr_const_in_range (&ep, 0, 16, 1))
12743 imm = ep.X_add_number >> 1;
12744 INSERT_OPERAND (1, IMMH, *ip, imm);
12751 bfd_reloc_code_real_type r[3];
12755 if (my_getSmallExpression (&ep, r, s) > 0
12756 || !expr_const_in_range (&ep, -1, 127, 0))
12759 imm = ep.X_add_number & 127;
12760 INSERT_OPERAND (1, IMMI, *ip, imm);
12767 bfd_reloc_code_real_type r[3];
12771 /* Check whether there is only a single bracketed
12772 expression left. If so, it must be the base register
12773 and the constant must be zero. */
12774 if (*s == '(' && strchr (s + 1, '(') == 0)
12776 INSERT_OPERAND (1, IMMJ, *ip, 0);
12780 if (my_getSmallExpression (&ep, r, s) > 0
12781 || !expr_const_in_range (&ep, 0, 16, 2))
12784 imm = ep.X_add_number >> 2;
12785 INSERT_OPERAND (1, IMMJ, *ip, imm);
12792 bfd_reloc_code_real_type r[3];
12796 /* Check whether there is only a single bracketed
12797 expression left. If so, it must be the base register
12798 and the constant must be zero. */
12799 if (*s == '(' && strchr (s + 1, '(') == 0)
12801 INSERT_OPERAND (1, IMML, *ip, 0);
12805 if (my_getSmallExpression (&ep, r, s) > 0
12806 || !expr_const_in_range (&ep, 0, 16, 0))
12809 imm = ep.X_add_number;
12810 INSERT_OPERAND (1, IMML, *ip, imm);
12817 bfd_reloc_code_real_type r[3];
12821 if (my_getSmallExpression (&ep, r, s) > 0
12822 || !expr_const_in_range (&ep, 1, 9, 0))
12825 imm = ep.X_add_number & 7;
12826 INSERT_OPERAND (1, IMMM, *ip, imm);
12831 case 'N': /* Register list for lwm and swm. */
12833 /* A comma-separated list of registers and/or
12834 dash-separated contiguous ranges including
12835 both ra and a set of one or more registers
12836 starting at s0 up to s3 which have to be
12843 and any permutations of these. */
12844 unsigned int reglist;
12847 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
12850 if ((reglist & 0xfff1ffff) != 0x80010000)
12853 reglist = (reglist >> 17) & 7;
12855 if ((reglist & -reglist) != reglist)
12858 imm = ffs (reglist) - 1;
12859 INSERT_OPERAND (1, IMMN, *ip, imm);
12863 case 'O': /* sdbbp 4-bit code. */
12865 bfd_reloc_code_real_type r[3];
12869 if (my_getSmallExpression (&ep, r, s) > 0
12870 || !expr_const_in_range (&ep, 0, 16, 0))
12873 imm = ep.X_add_number;
12874 INSERT_OPERAND (1, IMMO, *ip, imm);
12881 bfd_reloc_code_real_type r[3];
12885 if (my_getSmallExpression (&ep, r, s) > 0
12886 || !expr_const_in_range (&ep, 0, 32, 2))
12889 imm = ep.X_add_number >> 2;
12890 INSERT_OPERAND (1, IMMP, *ip, imm);
12897 bfd_reloc_code_real_type r[3];
12901 if (my_getSmallExpression (&ep, r, s) > 0
12902 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
12905 imm = ep.X_add_number >> 2;
12906 INSERT_OPERAND (1, IMMQ, *ip, imm);
12913 bfd_reloc_code_real_type r[3];
12917 /* Check whether there is only a single bracketed
12918 expression left. If so, it must be the base register
12919 and the constant must be zero. */
12920 if (*s == '(' && strchr (s + 1, '(') == 0)
12922 INSERT_OPERAND (1, IMMU, *ip, 0);
12926 if (my_getSmallExpression (&ep, r, s) > 0
12927 || !expr_const_in_range (&ep, 0, 32, 2))
12930 imm = ep.X_add_number >> 2;
12931 INSERT_OPERAND (1, IMMU, *ip, imm);
12938 bfd_reloc_code_real_type r[3];
12942 if (my_getSmallExpression (&ep, r, s) > 0
12943 || !expr_const_in_range (&ep, 0, 64, 2))
12946 imm = ep.X_add_number >> 2;
12947 INSERT_OPERAND (1, IMMW, *ip, imm);
12954 bfd_reloc_code_real_type r[3];
12958 if (my_getSmallExpression (&ep, r, s) > 0
12959 || !expr_const_in_range (&ep, -8, 8, 0))
12962 imm = ep.X_add_number;
12963 INSERT_OPERAND (1, IMMX, *ip, imm);
12970 bfd_reloc_code_real_type r[3];
12974 if (my_getSmallExpression (&ep, r, s) > 0
12975 || expr_const_in_range (&ep, -2, 2, 2)
12976 || !expr_const_in_range (&ep, -258, 258, 2))
12979 imm = ep.X_add_number >> 2;
12980 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
12981 INSERT_OPERAND (1, IMMY, *ip, imm);
12988 bfd_reloc_code_real_type r[3];
12991 if (my_getSmallExpression (&ep, r, s) > 0
12992 || !expr_const_in_range (&ep, 0, 1, 0))
12999 as_bad (_("Internal error: bad microMIPS opcode "
13000 "(unknown extension operand type `m%c'): %s %s"),
13001 *args, insn->name, insn->args);
13002 /* Further processing is fruitless. */
13007 case 'n': /* Register list for 32-bit lwm and swm. */
13008 gas_assert (mips_opts.micromips);
13010 /* A comma-separated list of registers and/or
13011 dash-separated contiguous ranges including
13012 at least one of ra and a set of one or more
13013 registers starting at s0 up to s7 and then
13014 s8 which have to be consecutive, e.g.:
13022 and any permutations of these. */
13023 unsigned int reglist;
13027 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13030 if ((reglist & 0x3f00ffff) != 0)
13033 ra = (reglist >> 27) & 0x10;
13034 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13036 if ((reglist & -reglist) != reglist)
13039 imm = (ffs (reglist) - 1) | ra;
13040 INSERT_OPERAND (1, RT, *ip, imm);
13041 imm_expr.X_op = O_absent;
13045 case '|': /* 4-bit trap code. */
13046 gas_assert (mips_opts.micromips);
13047 my_getExpression (&imm_expr, s);
13048 check_absolute_expr (ip, &imm_expr);
13049 if ((unsigned long) imm_expr.X_add_number
13050 > MICROMIPSOP_MASK_TRAP)
13051 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13052 (unsigned long) imm_expr.X_add_number,
13053 ip->insn_mo->name);
13054 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13055 imm_expr.X_op = O_absent;
13060 as_bad (_("Bad char = '%c'\n"), *args);
13065 /* Args don't match. */
13067 insn_error = _("Illegal operands");
13068 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13073 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13075 gas_assert (firstinsn);
13076 need_delay_slot_ok = FALSE;
13085 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13087 /* This routine assembles an instruction into its binary format when
13088 assembling for the mips16. As a side effect, it sets one of the
13089 global variables imm_reloc or offset_reloc to the type of relocation
13090 to do if one of the operands is an address expression. It also sets
13091 forced_insn_length to the resulting instruction size in bytes if the
13092 user explicitly requested a small or extended instruction. */
13095 mips16_ip (char *str, struct mips_cl_insn *ip)
13099 struct mips_opcode *insn;
13101 unsigned int regno;
13102 unsigned int lastregno = 0;
13108 forced_insn_length = 0;
13110 for (s = str; ISLOWER (*s); ++s)
13122 if (s[1] == 't' && s[2] == ' ')
13125 forced_insn_length = 2;
13129 else if (s[1] == 'e' && s[2] == ' ')
13132 forced_insn_length = 4;
13136 /* Fall through. */
13138 insn_error = _("unknown opcode");
13142 if (mips_opts.noautoextend && !forced_insn_length)
13143 forced_insn_length = 2;
13145 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13147 insn_error = _("unrecognized opcode");
13156 gas_assert (strcmp (insn->name, str) == 0);
13158 ok = is_opcode_valid_16 (insn);
13161 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13162 && strcmp (insn->name, insn[1].name) == 0)
13171 static char buf[100];
13173 _("opcode not supported on this processor: %s (%s)"),
13174 mips_cpu_info_from_arch (mips_opts.arch)->name,
13175 mips_cpu_info_from_isa (mips_opts.isa)->name);
13182 create_insn (ip, insn);
13183 imm_expr.X_op = O_absent;
13184 imm_reloc[0] = BFD_RELOC_UNUSED;
13185 imm_reloc[1] = BFD_RELOC_UNUSED;
13186 imm_reloc[2] = BFD_RELOC_UNUSED;
13187 imm2_expr.X_op = O_absent;
13188 offset_expr.X_op = O_absent;
13189 offset_reloc[0] = BFD_RELOC_UNUSED;
13190 offset_reloc[1] = BFD_RELOC_UNUSED;
13191 offset_reloc[2] = BFD_RELOC_UNUSED;
13192 for (args = insn->args; 1; ++args)
13199 /* In this switch statement we call break if we did not find
13200 a match, continue if we did find a match, or return if we
13209 /* Stuff the immediate value in now, if we can. */
13210 if (imm_expr.X_op == O_constant
13211 && *imm_reloc > BFD_RELOC_UNUSED
13212 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13213 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
13214 && insn->pinfo != INSN_MACRO)
13218 switch (*offset_reloc)
13220 case BFD_RELOC_MIPS16_HI16_S:
13221 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13224 case BFD_RELOC_MIPS16_HI16:
13225 tmp = imm_expr.X_add_number >> 16;
13228 case BFD_RELOC_MIPS16_LO16:
13229 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13233 case BFD_RELOC_UNUSED:
13234 tmp = imm_expr.X_add_number;
13240 *offset_reloc = BFD_RELOC_UNUSED;
13242 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13243 tmp, TRUE, forced_insn_length == 2,
13244 forced_insn_length == 4, &ip->insn_opcode,
13245 &ip->use_extend, &ip->extend);
13246 imm_expr.X_op = O_absent;
13247 *imm_reloc = BFD_RELOC_UNUSED;
13261 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13264 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13280 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13282 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13286 /* Fall through. */
13297 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13299 if (c == 'v' || c == 'w')
13302 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13304 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13315 if (c == 'v' || c == 'w')
13317 regno = mips16_to_32_reg_map[lastregno];
13331 regno = mips32_to_16_reg_map[regno];
13336 regno = ILLEGAL_REG;
13341 regno = ILLEGAL_REG;
13346 regno = ILLEGAL_REG;
13351 if (regno == AT && mips_opts.at)
13353 if (mips_opts.at == ATREG)
13354 as_warn (_("used $at without \".set noat\""));
13356 as_warn (_("used $%u with \".set at=$%u\""),
13357 regno, mips_opts.at);
13365 if (regno == ILLEGAL_REG)
13372 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13376 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13379 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13382 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13388 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13391 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13392 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13402 if (strncmp (s, "$pc", 3) == 0)
13419 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13422 if (imm_expr.X_op != O_constant)
13424 forced_insn_length = 4;
13425 ip->use_extend = TRUE;
13430 /* We need to relax this instruction. */
13431 *offset_reloc = *imm_reloc;
13432 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13437 *imm_reloc = BFD_RELOC_UNUSED;
13438 /* Fall through. */
13445 my_getExpression (&imm_expr, s);
13446 if (imm_expr.X_op == O_register)
13448 /* What we thought was an expression turned out to
13451 if (s[0] == '(' && args[1] == '(')
13453 /* It looks like the expression was omitted
13454 before a register indirection, which means
13455 that the expression is implicitly zero. We
13456 still set up imm_expr, so that we handle
13457 explicit extensions correctly. */
13458 imm_expr.X_op = O_constant;
13459 imm_expr.X_add_number = 0;
13460 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13467 /* We need to relax this instruction. */
13468 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13477 /* We use offset_reloc rather than imm_reloc for the PC
13478 relative operands. This lets macros with both
13479 immediate and address operands work correctly. */
13480 my_getExpression (&offset_expr, s);
13482 if (offset_expr.X_op == O_register)
13485 /* We need to relax this instruction. */
13486 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13490 case '6': /* break code */
13491 my_getExpression (&imm_expr, s);
13492 check_absolute_expr (ip, &imm_expr);
13493 if ((unsigned long) imm_expr.X_add_number > 63)
13494 as_warn (_("Invalid value for `%s' (%lu)"),
13496 (unsigned long) imm_expr.X_add_number);
13497 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13498 imm_expr.X_op = O_absent;
13502 case 'a': /* 26 bit address */
13503 my_getExpression (&offset_expr, s);
13505 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13506 ip->insn_opcode <<= 16;
13509 case 'l': /* register list for entry macro */
13510 case 'L': /* register list for exit macro */
13520 unsigned int freg, reg1, reg2;
13522 while (*s == ' ' || *s == ',')
13524 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13526 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13530 as_bad (_("can't parse register list"));
13540 if (!reg_lookup (&s, freg ? RTYPE_FPU
13541 : (RTYPE_GP | RTYPE_NUM), ®2))
13543 as_bad (_("invalid register list"));
13547 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13549 mask &= ~ (7 << 3);
13552 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13554 mask &= ~ (7 << 3);
13557 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13558 mask |= (reg2 - 3) << 3;
13559 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13560 mask |= (reg2 - 15) << 1;
13561 else if (reg1 == RA && reg2 == RA)
13565 as_bad (_("invalid register list"));
13569 /* The mask is filled in in the opcode table for the
13570 benefit of the disassembler. We remove it before
13571 applying the actual mask. */
13572 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13573 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13577 case 'm': /* Register list for save insn. */
13578 case 'M': /* Register list for restore insn. */
13581 int framesz = 0, seen_framesz = 0;
13582 int nargs = 0, statics = 0, sregs = 0;
13586 unsigned int reg1, reg2;
13588 SKIP_SPACE_TABS (s);
13591 SKIP_SPACE_TABS (s);
13593 my_getExpression (&imm_expr, s);
13594 if (imm_expr.X_op == O_constant)
13596 /* Handle the frame size. */
13599 as_bad (_("more than one frame size in list"));
13603 framesz = imm_expr.X_add_number;
13604 imm_expr.X_op = O_absent;
13609 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13611 as_bad (_("can't parse register list"));
13623 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13626 as_bad (_("can't parse register list"));
13631 while (reg1 <= reg2)
13633 if (reg1 >= 4 && reg1 <= 7)
13637 nargs |= 1 << (reg1 - 4);
13639 /* statics $a0-$a3 */
13640 statics |= 1 << (reg1 - 4);
13642 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13645 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13647 else if (reg1 == 31)
13649 /* Add $ra to insn. */
13654 as_bad (_("unexpected register in list"));
13662 /* Encode args/statics combination. */
13663 if (nargs & statics)
13664 as_bad (_("arg/static registers overlap"));
13665 else if (nargs == 0xf)
13666 /* All $a0-$a3 are args. */
13667 opcode |= MIPS16_ALL_ARGS << 16;
13668 else if (statics == 0xf)
13669 /* All $a0-$a3 are statics. */
13670 opcode |= MIPS16_ALL_STATICS << 16;
13673 int narg = 0, nstat = 0;
13675 /* Count arg registers. */
13676 while (nargs & 0x1)
13682 as_bad (_("invalid arg register list"));
13684 /* Count static registers. */
13685 while (statics & 0x8)
13687 statics = (statics << 1) & 0xf;
13691 as_bad (_("invalid static register list"));
13693 /* Encode args/statics. */
13694 opcode |= ((narg << 2) | nstat) << 16;
13697 /* Encode $s0/$s1. */
13698 if (sregs & (1 << 0)) /* $s0 */
13700 if (sregs & (1 << 1)) /* $s1 */
13706 /* Count regs $s2-$s8. */
13714 as_bad (_("invalid static register list"));
13715 /* Encode $s2-$s8. */
13716 opcode |= nsreg << 24;
13719 /* Encode frame size. */
13721 as_bad (_("missing frame size"));
13722 else if ((framesz & 7) != 0 || framesz < 0
13723 || framesz > 0xff * 8)
13724 as_bad (_("invalid frame size"));
13725 else if (framesz != 128 || (opcode >> 16) != 0)
13728 opcode |= (((framesz & 0xf0) << 16)
13729 | (framesz & 0x0f));
13732 /* Finally build the instruction. */
13733 if ((opcode >> 16) != 0 || framesz == 0)
13735 ip->use_extend = TRUE;
13736 ip->extend = opcode >> 16;
13738 ip->insn_opcode |= opcode & 0x7f;
13742 case 'e': /* extend code */
13743 my_getExpression (&imm_expr, s);
13744 check_absolute_expr (ip, &imm_expr);
13745 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13747 as_warn (_("Invalid value for `%s' (%lu)"),
13749 (unsigned long) imm_expr.X_add_number);
13750 imm_expr.X_add_number &= 0x7ff;
13752 ip->insn_opcode |= imm_expr.X_add_number;
13753 imm_expr.X_op = O_absent;
13763 /* Args don't match. */
13764 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13765 strcmp (insn->name, insn[1].name) == 0)
13772 insn_error = _("illegal operands");
13778 /* This structure holds information we know about a mips16 immediate
13781 struct mips16_immed_operand
13783 /* The type code used in the argument string in the opcode table. */
13785 /* The number of bits in the short form of the opcode. */
13787 /* The number of bits in the extended form of the opcode. */
13789 /* The amount by which the short form is shifted when it is used;
13790 for example, the sw instruction has a shift count of 2. */
13792 /* The amount by which the short form is shifted when it is stored
13793 into the instruction code. */
13795 /* Non-zero if the short form is unsigned. */
13797 /* Non-zero if the extended form is unsigned. */
13799 /* Non-zero if the value is PC relative. */
13803 /* The mips16 immediate operand types. */
13805 static const struct mips16_immed_operand mips16_immed_operands[] =
13807 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13808 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13809 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13810 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13811 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13812 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13813 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13814 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13815 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13816 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13817 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13818 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13819 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13820 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13821 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13822 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13823 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13824 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13825 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13826 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13827 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13830 #define MIPS16_NUM_IMMED \
13831 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13833 /* Handle a mips16 instruction with an immediate value. This or's the
13834 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13835 whether an extended value is needed; if one is needed, it sets
13836 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13837 If SMALL is true, an unextended opcode was explicitly requested.
13838 If EXT is true, an extended opcode was explicitly requested. If
13839 WARN is true, warn if EXT does not match reality. */
13842 mips16_immed (char *file, unsigned int line, int type, offsetT val,
13843 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
13844 unsigned long *insn, bfd_boolean *use_extend,
13845 unsigned short *extend)
13847 const struct mips16_immed_operand *op;
13848 int mintiny, maxtiny;
13849 bfd_boolean needext;
13851 op = mips16_immed_operands;
13852 while (op->type != type)
13855 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13860 if (type == '<' || type == '>' || type == '[' || type == ']')
13863 maxtiny = 1 << op->nbits;
13868 maxtiny = (1 << op->nbits) - 1;
13873 mintiny = - (1 << (op->nbits - 1));
13874 maxtiny = (1 << (op->nbits - 1)) - 1;
13877 /* Branch offsets have an implicit 0 in the lowest bit. */
13878 if (type == 'p' || type == 'q')
13881 if ((val & ((1 << op->shift) - 1)) != 0
13882 || val < (mintiny << op->shift)
13883 || val > (maxtiny << op->shift))
13888 if (warn && ext && ! needext)
13889 as_warn_where (file, line,
13890 _("extended operand requested but not required"));
13891 if (small && needext)
13892 as_bad_where (file, line, _("invalid unextended operand value"));
13894 if (small || (! ext && ! needext))
13898 *use_extend = FALSE;
13899 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
13900 insnval <<= op->op_shift;
13905 long minext, maxext;
13911 maxext = (1 << op->extbits) - 1;
13915 minext = - (1 << (op->extbits - 1));
13916 maxext = (1 << (op->extbits - 1)) - 1;
13918 if (val < minext || val > maxext)
13919 as_bad_where (file, line,
13920 _("operand value out of range for instruction"));
13922 *use_extend = TRUE;
13923 if (op->extbits == 16)
13925 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13928 else if (op->extbits == 15)
13930 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13935 extval = ((val & 0x1f) << 6) | (val & 0x20);
13939 *extend = (unsigned short) extval;
13944 struct percent_op_match
13947 bfd_reloc_code_real_type reloc;
13950 static const struct percent_op_match mips_percent_op[] =
13952 {"%lo", BFD_RELOC_LO16},
13954 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13955 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13956 {"%call16", BFD_RELOC_MIPS_CALL16},
13957 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13958 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13959 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13960 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13961 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13962 {"%got", BFD_RELOC_MIPS_GOT16},
13963 {"%gp_rel", BFD_RELOC_GPREL16},
13964 {"%half", BFD_RELOC_16},
13965 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13966 {"%higher", BFD_RELOC_MIPS_HIGHER},
13967 {"%neg", BFD_RELOC_MIPS_SUB},
13968 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13969 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13970 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13971 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13972 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13973 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13974 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13976 {"%hi", BFD_RELOC_HI16_S}
13979 static const struct percent_op_match mips16_percent_op[] =
13981 {"%lo", BFD_RELOC_MIPS16_LO16},
13982 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13983 {"%got", BFD_RELOC_MIPS16_GOT16},
13984 {"%call16", BFD_RELOC_MIPS16_CALL16},
13985 {"%hi", BFD_RELOC_MIPS16_HI16_S}
13989 /* Return true if *STR points to a relocation operator. When returning true,
13990 move *STR over the operator and store its relocation code in *RELOC.
13991 Leave both *STR and *RELOC alone when returning false. */
13994 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13996 const struct percent_op_match *percent_op;
13999 if (mips_opts.mips16)
14001 percent_op = mips16_percent_op;
14002 limit = ARRAY_SIZE (mips16_percent_op);
14006 percent_op = mips_percent_op;
14007 limit = ARRAY_SIZE (mips_percent_op);
14010 for (i = 0; i < limit; i++)
14011 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14013 int len = strlen (percent_op[i].str);
14015 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14018 *str += strlen (percent_op[i].str);
14019 *reloc = percent_op[i].reloc;
14021 /* Check whether the output BFD supports this relocation.
14022 If not, issue an error and fall back on something safe. */
14023 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14025 as_bad (_("relocation %s isn't supported by the current ABI"),
14026 percent_op[i].str);
14027 *reloc = BFD_RELOC_UNUSED;
14035 /* Parse string STR as a 16-bit relocatable operand. Store the
14036 expression in *EP and the relocations in the array starting
14037 at RELOC. Return the number of relocation operators used.
14039 On exit, EXPR_END points to the first character after the expression. */
14042 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14045 bfd_reloc_code_real_type reversed_reloc[3];
14046 size_t reloc_index, i;
14047 int crux_depth, str_depth;
14050 /* Search for the start of the main expression, recoding relocations
14051 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14052 of the main expression and with CRUX_DEPTH containing the number
14053 of open brackets at that point. */
14060 crux_depth = str_depth;
14062 /* Skip over whitespace and brackets, keeping count of the number
14064 while (*str == ' ' || *str == '\t' || *str == '(')
14069 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14070 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14072 my_getExpression (ep, crux);
14075 /* Match every open bracket. */
14076 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14080 if (crux_depth > 0)
14081 as_bad (_("unclosed '('"));
14085 if (reloc_index != 0)
14087 prev_reloc_op_frag = frag_now;
14088 for (i = 0; i < reloc_index; i++)
14089 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14092 return reloc_index;
14096 my_getExpression (expressionS *ep, char *str)
14100 save_in = input_line_pointer;
14101 input_line_pointer = str;
14103 expr_end = input_line_pointer;
14104 input_line_pointer = save_in;
14108 md_atof (int type, char *litP, int *sizeP)
14110 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14114 md_number_to_chars (char *buf, valueT val, int n)
14116 if (target_big_endian)
14117 number_to_chars_bigendian (buf, val, n);
14119 number_to_chars_littleendian (buf, val, n);
14123 static int support_64bit_objects(void)
14125 const char **list, **l;
14128 list = bfd_target_list ();
14129 for (l = list; *l != NULL; l++)
14130 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14131 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14133 yes = (*l != NULL);
14137 #endif /* OBJ_ELF */
14139 const char *md_shortopts = "O::g::G:";
14143 OPTION_MARCH = OPTION_MD_BASE,
14165 OPTION_NO_SMARTMIPS,
14169 OPTION_NO_MICROMIPS,
14170 OPTION_COMPAT_ARCH_BASE,
14179 OPTION_M7000_HILO_FIX,
14180 OPTION_MNO_7000_HILO_FIX,
14183 OPTION_FIX_LOONGSON2F_JUMP,
14184 OPTION_NO_FIX_LOONGSON2F_JUMP,
14185 OPTION_FIX_LOONGSON2F_NOP,
14186 OPTION_NO_FIX_LOONGSON2F_NOP,
14188 OPTION_NO_FIX_VR4120,
14190 OPTION_NO_FIX_VR4130,
14191 OPTION_FIX_CN63XXP1,
14192 OPTION_NO_FIX_CN63XXP1,
14199 OPTION_CONSTRUCT_FLOATS,
14200 OPTION_NO_CONSTRUCT_FLOATS,
14203 OPTION_RELAX_BRANCH,
14204 OPTION_NO_RELAX_BRANCH,
14211 OPTION_SINGLE_FLOAT,
14212 OPTION_DOUBLE_FLOAT,
14215 OPTION_CALL_SHARED,
14216 OPTION_CALL_NONPIC,
14226 OPTION_MVXWORKS_PIC,
14227 #endif /* OBJ_ELF */
14231 struct option md_longopts[] =
14233 /* Options which specify architecture. */
14234 {"march", required_argument, NULL, OPTION_MARCH},
14235 {"mtune", required_argument, NULL, OPTION_MTUNE},
14236 {"mips0", no_argument, NULL, OPTION_MIPS1},
14237 {"mips1", no_argument, NULL, OPTION_MIPS1},
14238 {"mips2", no_argument, NULL, OPTION_MIPS2},
14239 {"mips3", no_argument, NULL, OPTION_MIPS3},
14240 {"mips4", no_argument, NULL, OPTION_MIPS4},
14241 {"mips5", no_argument, NULL, OPTION_MIPS5},
14242 {"mips32", no_argument, NULL, OPTION_MIPS32},
14243 {"mips64", no_argument, NULL, OPTION_MIPS64},
14244 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14245 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14247 /* Options which specify Application Specific Extensions (ASEs). */
14248 {"mips16", no_argument, NULL, OPTION_MIPS16},
14249 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14250 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14251 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14252 {"mdmx", no_argument, NULL, OPTION_MDMX},
14253 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14254 {"mdsp", no_argument, NULL, OPTION_DSP},
14255 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14256 {"mmt", no_argument, NULL, OPTION_MT},
14257 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14258 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14259 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14260 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14261 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14262 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14263 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14265 /* Old-style architecture options. Don't add more of these. */
14266 {"m4650", no_argument, NULL, OPTION_M4650},
14267 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14268 {"m4010", no_argument, NULL, OPTION_M4010},
14269 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14270 {"m4100", no_argument, NULL, OPTION_M4100},
14271 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14272 {"m3900", no_argument, NULL, OPTION_M3900},
14273 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14275 /* Options which enable bug fixes. */
14276 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14277 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14278 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14279 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14280 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14281 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14282 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14283 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14284 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14285 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14286 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14287 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14288 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14289 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14290 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14292 /* Miscellaneous options. */
14293 {"trap", no_argument, NULL, OPTION_TRAP},
14294 {"no-break", no_argument, NULL, OPTION_TRAP},
14295 {"break", no_argument, NULL, OPTION_BREAK},
14296 {"no-trap", no_argument, NULL, OPTION_BREAK},
14297 {"EB", no_argument, NULL, OPTION_EB},
14298 {"EL", no_argument, NULL, OPTION_EL},
14299 {"mfp32", no_argument, NULL, OPTION_FP32},
14300 {"mgp32", no_argument, NULL, OPTION_GP32},
14301 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14302 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14303 {"mfp64", no_argument, NULL, OPTION_FP64},
14304 {"mgp64", no_argument, NULL, OPTION_GP64},
14305 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14306 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14307 {"mshared", no_argument, NULL, OPTION_MSHARED},
14308 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14309 {"msym32", no_argument, NULL, OPTION_MSYM32},
14310 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14311 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14312 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14313 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14314 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14316 /* Strictly speaking this next option is ELF specific,
14317 but we allow it for other ports as well in order to
14318 make testing easier. */
14319 {"32", no_argument, NULL, OPTION_32},
14321 /* ELF-specific options. */
14323 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14324 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14325 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14326 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14327 {"xgot", no_argument, NULL, OPTION_XGOT},
14328 {"mabi", required_argument, NULL, OPTION_MABI},
14329 {"n32", no_argument, NULL, OPTION_N32},
14330 {"64", no_argument, NULL, OPTION_64},
14331 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14332 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14333 {"mpdr", no_argument, NULL, OPTION_PDR},
14334 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14335 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14336 #endif /* OBJ_ELF */
14338 {NULL, no_argument, NULL, 0}
14340 size_t md_longopts_size = sizeof (md_longopts);
14342 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14343 NEW_VALUE. Warn if another value was already specified. Note:
14344 we have to defer parsing the -march and -mtune arguments in order
14345 to handle 'from-abi' correctly, since the ABI might be specified
14346 in a later argument. */
14349 mips_set_option_string (const char **string_ptr, const char *new_value)
14351 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14352 as_warn (_("A different %s was already specified, is now %s"),
14353 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14356 *string_ptr = new_value;
14360 md_parse_option (int c, char *arg)
14364 case OPTION_CONSTRUCT_FLOATS:
14365 mips_disable_float_construction = 0;
14368 case OPTION_NO_CONSTRUCT_FLOATS:
14369 mips_disable_float_construction = 1;
14381 target_big_endian = 1;
14385 target_big_endian = 0;
14391 else if (arg[0] == '0')
14393 else if (arg[0] == '1')
14403 mips_debug = atoi (arg);
14407 file_mips_isa = ISA_MIPS1;
14411 file_mips_isa = ISA_MIPS2;
14415 file_mips_isa = ISA_MIPS3;
14419 file_mips_isa = ISA_MIPS4;
14423 file_mips_isa = ISA_MIPS5;
14426 case OPTION_MIPS32:
14427 file_mips_isa = ISA_MIPS32;
14430 case OPTION_MIPS32R2:
14431 file_mips_isa = ISA_MIPS32R2;
14434 case OPTION_MIPS64R2:
14435 file_mips_isa = ISA_MIPS64R2;
14438 case OPTION_MIPS64:
14439 file_mips_isa = ISA_MIPS64;
14443 mips_set_option_string (&mips_tune_string, arg);
14447 mips_set_option_string (&mips_arch_string, arg);
14451 mips_set_option_string (&mips_arch_string, "4650");
14452 mips_set_option_string (&mips_tune_string, "4650");
14455 case OPTION_NO_M4650:
14459 mips_set_option_string (&mips_arch_string, "4010");
14460 mips_set_option_string (&mips_tune_string, "4010");
14463 case OPTION_NO_M4010:
14467 mips_set_option_string (&mips_arch_string, "4100");
14468 mips_set_option_string (&mips_tune_string, "4100");
14471 case OPTION_NO_M4100:
14475 mips_set_option_string (&mips_arch_string, "3900");
14476 mips_set_option_string (&mips_tune_string, "3900");
14479 case OPTION_NO_M3900:
14483 mips_opts.ase_mdmx = 1;
14486 case OPTION_NO_MDMX:
14487 mips_opts.ase_mdmx = 0;
14491 mips_opts.ase_dsp = 1;
14492 mips_opts.ase_dspr2 = 0;
14495 case OPTION_NO_DSP:
14496 mips_opts.ase_dsp = 0;
14497 mips_opts.ase_dspr2 = 0;
14501 mips_opts.ase_dspr2 = 1;
14502 mips_opts.ase_dsp = 1;
14505 case OPTION_NO_DSPR2:
14506 mips_opts.ase_dspr2 = 0;
14507 mips_opts.ase_dsp = 0;
14511 mips_opts.ase_mt = 1;
14515 mips_opts.ase_mt = 0;
14518 case OPTION_MICROMIPS:
14519 if (mips_opts.mips16 == 1)
14521 as_bad (_("-mmicromips cannot be used with -mips16"));
14524 mips_opts.micromips = 1;
14525 mips_no_prev_insn ();
14528 case OPTION_NO_MICROMIPS:
14529 mips_opts.micromips = 0;
14530 mips_no_prev_insn ();
14533 case OPTION_MIPS16:
14534 if (mips_opts.micromips == 1)
14536 as_bad (_("-mips16 cannot be used with -micromips"));
14539 mips_opts.mips16 = 1;
14540 mips_no_prev_insn ();
14543 case OPTION_NO_MIPS16:
14544 mips_opts.mips16 = 0;
14545 mips_no_prev_insn ();
14548 case OPTION_MIPS3D:
14549 mips_opts.ase_mips3d = 1;
14552 case OPTION_NO_MIPS3D:
14553 mips_opts.ase_mips3d = 0;
14556 case OPTION_SMARTMIPS:
14557 mips_opts.ase_smartmips = 1;
14560 case OPTION_NO_SMARTMIPS:
14561 mips_opts.ase_smartmips = 0;
14564 case OPTION_FIX_24K:
14568 case OPTION_NO_FIX_24K:
14572 case OPTION_FIX_LOONGSON2F_JUMP:
14573 mips_fix_loongson2f_jump = TRUE;
14576 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14577 mips_fix_loongson2f_jump = FALSE;
14580 case OPTION_FIX_LOONGSON2F_NOP:
14581 mips_fix_loongson2f_nop = TRUE;
14584 case OPTION_NO_FIX_LOONGSON2F_NOP:
14585 mips_fix_loongson2f_nop = FALSE;
14588 case OPTION_FIX_VR4120:
14589 mips_fix_vr4120 = 1;
14592 case OPTION_NO_FIX_VR4120:
14593 mips_fix_vr4120 = 0;
14596 case OPTION_FIX_VR4130:
14597 mips_fix_vr4130 = 1;
14600 case OPTION_NO_FIX_VR4130:
14601 mips_fix_vr4130 = 0;
14604 case OPTION_FIX_CN63XXP1:
14605 mips_fix_cn63xxp1 = TRUE;
14608 case OPTION_NO_FIX_CN63XXP1:
14609 mips_fix_cn63xxp1 = FALSE;
14612 case OPTION_RELAX_BRANCH:
14613 mips_relax_branch = 1;
14616 case OPTION_NO_RELAX_BRANCH:
14617 mips_relax_branch = 0;
14620 case OPTION_MSHARED:
14621 mips_in_shared = TRUE;
14624 case OPTION_MNO_SHARED:
14625 mips_in_shared = FALSE;
14628 case OPTION_MSYM32:
14629 mips_opts.sym32 = TRUE;
14632 case OPTION_MNO_SYM32:
14633 mips_opts.sym32 = FALSE;
14637 /* When generating ELF code, we permit -KPIC and -call_shared to
14638 select SVR4_PIC, and -non_shared to select no PIC. This is
14639 intended to be compatible with Irix 5. */
14640 case OPTION_CALL_SHARED:
14643 as_bad (_("-call_shared is supported only for ELF format"));
14646 mips_pic = SVR4_PIC;
14647 mips_abicalls = TRUE;
14650 case OPTION_CALL_NONPIC:
14653 as_bad (_("-call_nonpic is supported only for ELF format"));
14657 mips_abicalls = TRUE;
14660 case OPTION_NON_SHARED:
14663 as_bad (_("-non_shared is supported only for ELF format"));
14667 mips_abicalls = FALSE;
14670 /* The -xgot option tells the assembler to use 32 bit offsets
14671 when accessing the got in SVR4_PIC mode. It is for Irix
14676 #endif /* OBJ_ELF */
14679 g_switch_value = atoi (arg);
14683 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14687 mips_abi = O32_ABI;
14688 /* We silently ignore -32 for non-ELF targets. This greatly
14689 simplifies the construction of the MIPS GAS test cases. */
14696 as_bad (_("-n32 is supported for ELF format only"));
14699 mips_abi = N32_ABI;
14705 as_bad (_("-64 is supported for ELF format only"));
14708 mips_abi = N64_ABI;
14709 if (!support_64bit_objects())
14710 as_fatal (_("No compiled in support for 64 bit object file format"));
14712 #endif /* OBJ_ELF */
14715 file_mips_gp32 = 1;
14719 file_mips_gp32 = 0;
14723 file_mips_fp32 = 1;
14727 file_mips_fp32 = 0;
14730 case OPTION_SINGLE_FLOAT:
14731 file_mips_single_float = 1;
14734 case OPTION_DOUBLE_FLOAT:
14735 file_mips_single_float = 0;
14738 case OPTION_SOFT_FLOAT:
14739 file_mips_soft_float = 1;
14742 case OPTION_HARD_FLOAT:
14743 file_mips_soft_float = 0;
14750 as_bad (_("-mabi is supported for ELF format only"));
14753 if (strcmp (arg, "32") == 0)
14754 mips_abi = O32_ABI;
14755 else if (strcmp (arg, "o64") == 0)
14756 mips_abi = O64_ABI;
14757 else if (strcmp (arg, "n32") == 0)
14758 mips_abi = N32_ABI;
14759 else if (strcmp (arg, "64") == 0)
14761 mips_abi = N64_ABI;
14762 if (! support_64bit_objects())
14763 as_fatal (_("No compiled in support for 64 bit object file "
14766 else if (strcmp (arg, "eabi") == 0)
14767 mips_abi = EABI_ABI;
14770 as_fatal (_("invalid abi -mabi=%s"), arg);
14774 #endif /* OBJ_ELF */
14776 case OPTION_M7000_HILO_FIX:
14777 mips_7000_hilo_fix = TRUE;
14780 case OPTION_MNO_7000_HILO_FIX:
14781 mips_7000_hilo_fix = FALSE;
14785 case OPTION_MDEBUG:
14786 mips_flag_mdebug = TRUE;
14789 case OPTION_NO_MDEBUG:
14790 mips_flag_mdebug = FALSE;
14794 mips_flag_pdr = TRUE;
14797 case OPTION_NO_PDR:
14798 mips_flag_pdr = FALSE;
14801 case OPTION_MVXWORKS_PIC:
14802 mips_pic = VXWORKS_PIC;
14804 #endif /* OBJ_ELF */
14810 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14815 /* Set up globals to generate code for the ISA or processor
14816 described by INFO. */
14819 mips_set_architecture (const struct mips_cpu_info *info)
14823 file_mips_arch = info->cpu;
14824 mips_opts.arch = info->cpu;
14825 mips_opts.isa = info->isa;
14830 /* Likewise for tuning. */
14833 mips_set_tune (const struct mips_cpu_info *info)
14836 mips_tune = info->cpu;
14841 mips_after_parse_args (void)
14843 const struct mips_cpu_info *arch_info = 0;
14844 const struct mips_cpu_info *tune_info = 0;
14846 /* GP relative stuff not working for PE */
14847 if (strncmp (TARGET_OS, "pe", 2) == 0)
14849 if (g_switch_seen && g_switch_value != 0)
14850 as_bad (_("-G not supported in this configuration."));
14851 g_switch_value = 0;
14854 if (mips_abi == NO_ABI)
14855 mips_abi = MIPS_DEFAULT_ABI;
14857 /* The following code determines the architecture and register size.
14858 Similar code was added to GCC 3.3 (see override_options() in
14859 config/mips/mips.c). The GAS and GCC code should be kept in sync
14860 as much as possible. */
14862 if (mips_arch_string != 0)
14863 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14865 if (file_mips_isa != ISA_UNKNOWN)
14867 /* Handle -mipsN. At this point, file_mips_isa contains the
14868 ISA level specified by -mipsN, while arch_info->isa contains
14869 the -march selection (if any). */
14870 if (arch_info != 0)
14872 /* -march takes precedence over -mipsN, since it is more descriptive.
14873 There's no harm in specifying both as long as the ISA levels
14875 if (file_mips_isa != arch_info->isa)
14876 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
14877 mips_cpu_info_from_isa (file_mips_isa)->name,
14878 mips_cpu_info_from_isa (arch_info->isa)->name);
14881 arch_info = mips_cpu_info_from_isa (file_mips_isa);
14884 if (arch_info == 0)
14885 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14887 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14888 as_bad (_("-march=%s is not compatible with the selected ABI"),
14891 mips_set_architecture (arch_info);
14893 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
14894 if (mips_tune_string != 0)
14895 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14897 if (tune_info == 0)
14898 mips_set_tune (arch_info);
14900 mips_set_tune (tune_info);
14902 if (file_mips_gp32 >= 0)
14904 /* The user specified the size of the integer registers. Make sure
14905 it agrees with the ABI and ISA. */
14906 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14907 as_bad (_("-mgp64 used with a 32-bit processor"));
14908 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14909 as_bad (_("-mgp32 used with a 64-bit ABI"));
14910 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14911 as_bad (_("-mgp64 used with a 32-bit ABI"));
14915 /* Infer the integer register size from the ABI and processor.
14916 Restrict ourselves to 32-bit registers if that's all the
14917 processor has, or if the ABI cannot handle 64-bit registers. */
14918 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14919 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
14922 switch (file_mips_fp32)
14926 /* No user specified float register size.
14927 ??? GAS treats single-float processors as though they had 64-bit
14928 float registers (although it complains when double-precision
14929 instructions are used). As things stand, saying they have 32-bit
14930 registers would lead to spurious "register must be even" messages.
14931 So here we assume float registers are never smaller than the
14933 if (file_mips_gp32 == 0)
14934 /* 64-bit integer registers implies 64-bit float registers. */
14935 file_mips_fp32 = 0;
14936 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
14937 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
14938 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14939 file_mips_fp32 = 0;
14941 /* 32-bit float registers. */
14942 file_mips_fp32 = 1;
14945 /* The user specified the size of the float registers. Check if it
14946 agrees with the ABI and ISA. */
14948 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14949 as_bad (_("-mfp64 used with a 32-bit fpu"));
14950 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
14951 && !ISA_HAS_MXHC1 (mips_opts.isa))
14952 as_warn (_("-mfp64 used with a 32-bit ABI"));
14955 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14956 as_warn (_("-mfp32 used with a 64-bit ABI"));
14960 /* End of GCC-shared inference code. */
14962 /* This flag is set when we have a 64-bit capable CPU but use only
14963 32-bit wide registers. Note that EABI does not use it. */
14964 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
14965 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
14966 || mips_abi == O32_ABI))
14967 mips_32bitmode = 1;
14969 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
14970 as_bad (_("trap exception not supported at ISA 1"));
14972 /* If the selected architecture includes support for ASEs, enable
14973 generation of code for them. */
14974 if (mips_opts.mips16 == -1)
14975 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
14976 if (mips_opts.micromips == -1)
14977 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
14978 if (mips_opts.ase_mips3d == -1)
14979 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
14980 && file_mips_fp32 == 0) ? 1 : 0;
14981 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
14982 as_bad (_("-mfp32 used with -mips3d"));
14984 if (mips_opts.ase_mdmx == -1)
14985 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
14986 && file_mips_fp32 == 0) ? 1 : 0;
14987 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
14988 as_bad (_("-mfp32 used with -mdmx"));
14990 if (mips_opts.ase_smartmips == -1)
14991 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
14992 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
14993 as_warn (_("%s ISA does not support SmartMIPS"),
14994 mips_cpu_info_from_isa (mips_opts.isa)->name);
14996 if (mips_opts.ase_dsp == -1)
14997 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
14998 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
14999 as_warn (_("%s ISA does not support DSP ASE"),
15000 mips_cpu_info_from_isa (mips_opts.isa)->name);
15002 if (mips_opts.ase_dspr2 == -1)
15004 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15005 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15007 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15008 as_warn (_("%s ISA does not support DSP R2 ASE"),
15009 mips_cpu_info_from_isa (mips_opts.isa)->name);
15011 if (mips_opts.ase_mt == -1)
15012 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15013 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15014 as_warn (_("%s ISA does not support MT ASE"),
15015 mips_cpu_info_from_isa (mips_opts.isa)->name);
15017 file_mips_isa = mips_opts.isa;
15018 file_ase_mips3d = mips_opts.ase_mips3d;
15019 file_ase_mdmx = mips_opts.ase_mdmx;
15020 file_ase_smartmips = mips_opts.ase_smartmips;
15021 file_ase_dsp = mips_opts.ase_dsp;
15022 file_ase_dspr2 = mips_opts.ase_dspr2;
15023 file_ase_mt = mips_opts.ase_mt;
15024 mips_opts.gp32 = file_mips_gp32;
15025 mips_opts.fp32 = file_mips_fp32;
15026 mips_opts.soft_float = file_mips_soft_float;
15027 mips_opts.single_float = file_mips_single_float;
15029 if (mips_flag_mdebug < 0)
15031 #ifdef OBJ_MAYBE_ECOFF
15032 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15033 mips_flag_mdebug = 1;
15035 #endif /* OBJ_MAYBE_ECOFF */
15036 mips_flag_mdebug = 0;
15041 mips_init_after_args (void)
15043 /* initialize opcodes */
15044 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15045 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15049 md_pcrel_from (fixS *fixP)
15051 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15052 switch (fixP->fx_r_type)
15054 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15055 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15056 /* Return the address of the delay slot. */
15059 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15060 case BFD_RELOC_MICROMIPS_JMP:
15061 case BFD_RELOC_16_PCREL_S2:
15062 case BFD_RELOC_MIPS_JMP:
15063 /* Return the address of the delay slot. */
15067 /* We have no relocation type for PC relative MIPS16 instructions. */
15068 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15069 as_bad_where (fixP->fx_file, fixP->fx_line,
15070 _("PC relative MIPS16 instruction references a different section"));
15075 /* This is called before the symbol table is processed. In order to
15076 work with gcc when using mips-tfile, we must keep all local labels.
15077 However, in other cases, we want to discard them. If we were
15078 called with -g, but we didn't see any debugging information, it may
15079 mean that gcc is smuggling debugging information through to
15080 mips-tfile, in which case we must generate all local labels. */
15083 mips_frob_file_before_adjust (void)
15085 #ifndef NO_ECOFF_DEBUGGING
15086 if (ECOFF_DEBUGGING
15088 && ! ecoff_debugging_seen)
15089 flag_keep_locals = 1;
15093 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15094 the corresponding LO16 reloc. This is called before md_apply_fix and
15095 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15096 relocation operators.
15098 For our purposes, a %lo() expression matches a %got() or %hi()
15101 (a) it refers to the same symbol; and
15102 (b) the offset applied in the %lo() expression is no lower than
15103 the offset applied in the %got() or %hi().
15105 (b) allows us to cope with code like:
15108 lh $4,%lo(foo+2)($4)
15110 ...which is legal on RELA targets, and has a well-defined behaviour
15111 if the user knows that adding 2 to "foo" will not induce a carry to
15114 When several %lo()s match a particular %got() or %hi(), we use the
15115 following rules to distinguish them:
15117 (1) %lo()s with smaller offsets are a better match than %lo()s with
15120 (2) %lo()s with no matching %got() or %hi() are better than those
15121 that already have a matching %got() or %hi().
15123 (3) later %lo()s are better than earlier %lo()s.
15125 These rules are applied in order.
15127 (1) means, among other things, that %lo()s with identical offsets are
15128 chosen if they exist.
15130 (2) means that we won't associate several high-part relocations with
15131 the same low-part relocation unless there's no alternative. Having
15132 several high parts for the same low part is a GNU extension; this rule
15133 allows careful users to avoid it.
15135 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15136 with the last high-part relocation being at the front of the list.
15137 It therefore makes sense to choose the last matching low-part
15138 relocation, all other things being equal. It's also easier
15139 to code that way. */
15142 mips_frob_file (void)
15144 struct mips_hi_fixup *l;
15145 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15147 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15149 segment_info_type *seginfo;
15150 bfd_boolean matched_lo_p;
15151 fixS **hi_pos, **lo_pos, **pos;
15153 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15155 /* If a GOT16 relocation turns out to be against a global symbol,
15156 there isn't supposed to be a matching LO. */
15157 if (got16_reloc_p (l->fixp->fx_r_type)
15158 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15161 /* Check quickly whether the next fixup happens to be a matching %lo. */
15162 if (fixup_has_matching_lo_p (l->fixp))
15165 seginfo = seg_info (l->seg);
15167 /* Set HI_POS to the position of this relocation in the chain.
15168 Set LO_POS to the position of the chosen low-part relocation.
15169 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15170 relocation that matches an immediately-preceding high-part
15174 matched_lo_p = FALSE;
15175 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15177 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15179 if (*pos == l->fixp)
15182 if ((*pos)->fx_r_type == looking_for_rtype
15183 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15184 && (*pos)->fx_offset >= l->fixp->fx_offset
15186 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15188 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15191 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15192 && fixup_has_matching_lo_p (*pos));
15195 /* If we found a match, remove the high-part relocation from its
15196 current position and insert it before the low-part relocation.
15197 Make the offsets match so that fixup_has_matching_lo_p()
15200 We don't warn about unmatched high-part relocations since some
15201 versions of gcc have been known to emit dead "lui ...%hi(...)"
15203 if (lo_pos != NULL)
15205 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15206 if (l->fixp->fx_next != *lo_pos)
15208 *hi_pos = l->fixp->fx_next;
15209 l->fixp->fx_next = *lo_pos;
15216 /* We may have combined relocations without symbols in the N32/N64 ABI.
15217 We have to prevent gas from dropping them. */
15220 mips_force_relocation (fixS *fixp)
15222 if (generic_force_reloc (fixp))
15225 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15226 so that the linker relaxation can update targets. */
15227 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15228 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15229 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15233 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15234 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
15235 || hi16_reloc_p (fixp->fx_r_type)
15236 || lo16_reloc_p (fixp->fx_r_type)))
15242 /* Apply a fixup to the object file. */
15245 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15249 reloc_howto_type *howto;
15251 /* We ignore generic BFD relocations we don't know about. */
15252 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15256 gas_assert (fixP->fx_size == 2
15257 || fixP->fx_size == 4
15258 || fixP->fx_r_type == BFD_RELOC_16
15259 || fixP->fx_r_type == BFD_RELOC_64
15260 || fixP->fx_r_type == BFD_RELOC_CTOR
15261 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15262 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15263 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15264 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15265 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15267 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
15269 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15270 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15271 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15272 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15274 /* Don't treat parts of a composite relocation as done. There are two
15277 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15278 should nevertheless be emitted if the first part is.
15280 (2) In normal usage, composite relocations are never assembly-time
15281 constants. The easiest way of dealing with the pathological
15282 exceptions is to generate a relocation against STN_UNDEF and
15283 leave everything up to the linker. */
15284 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15287 switch (fixP->fx_r_type)
15289 case BFD_RELOC_MIPS_TLS_GD:
15290 case BFD_RELOC_MIPS_TLS_LDM:
15291 case BFD_RELOC_MIPS_TLS_DTPREL32:
15292 case BFD_RELOC_MIPS_TLS_DTPREL64:
15293 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15294 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15295 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15296 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15297 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15298 case BFD_RELOC_MICROMIPS_TLS_GD:
15299 case BFD_RELOC_MICROMIPS_TLS_LDM:
15300 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15301 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15302 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15303 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15304 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15305 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15308 case BFD_RELOC_MIPS_JMP:
15309 case BFD_RELOC_MIPS_SHIFT5:
15310 case BFD_RELOC_MIPS_SHIFT6:
15311 case BFD_RELOC_MIPS_GOT_DISP:
15312 case BFD_RELOC_MIPS_GOT_PAGE:
15313 case BFD_RELOC_MIPS_GOT_OFST:
15314 case BFD_RELOC_MIPS_SUB:
15315 case BFD_RELOC_MIPS_INSERT_A:
15316 case BFD_RELOC_MIPS_INSERT_B:
15317 case BFD_RELOC_MIPS_DELETE:
15318 case BFD_RELOC_MIPS_HIGHEST:
15319 case BFD_RELOC_MIPS_HIGHER:
15320 case BFD_RELOC_MIPS_SCN_DISP:
15321 case BFD_RELOC_MIPS_REL16:
15322 case BFD_RELOC_MIPS_RELGOT:
15323 case BFD_RELOC_MIPS_JALR:
15324 case BFD_RELOC_HI16:
15325 case BFD_RELOC_HI16_S:
15326 case BFD_RELOC_GPREL16:
15327 case BFD_RELOC_MIPS_LITERAL:
15328 case BFD_RELOC_MIPS_CALL16:
15329 case BFD_RELOC_MIPS_GOT16:
15330 case BFD_RELOC_GPREL32:
15331 case BFD_RELOC_MIPS_GOT_HI16:
15332 case BFD_RELOC_MIPS_GOT_LO16:
15333 case BFD_RELOC_MIPS_CALL_HI16:
15334 case BFD_RELOC_MIPS_CALL_LO16:
15335 case BFD_RELOC_MIPS16_GPREL:
15336 case BFD_RELOC_MIPS16_GOT16:
15337 case BFD_RELOC_MIPS16_CALL16:
15338 case BFD_RELOC_MIPS16_HI16:
15339 case BFD_RELOC_MIPS16_HI16_S:
15340 case BFD_RELOC_MIPS16_JMP:
15341 case BFD_RELOC_MICROMIPS_JMP:
15342 case BFD_RELOC_MICROMIPS_GOT_DISP:
15343 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15344 case BFD_RELOC_MICROMIPS_GOT_OFST:
15345 case BFD_RELOC_MICROMIPS_SUB:
15346 case BFD_RELOC_MICROMIPS_HIGHEST:
15347 case BFD_RELOC_MICROMIPS_HIGHER:
15348 case BFD_RELOC_MICROMIPS_SCN_DISP:
15349 case BFD_RELOC_MICROMIPS_JALR:
15350 case BFD_RELOC_MICROMIPS_HI16:
15351 case BFD_RELOC_MICROMIPS_HI16_S:
15352 case BFD_RELOC_MICROMIPS_GPREL16:
15353 case BFD_RELOC_MICROMIPS_LITERAL:
15354 case BFD_RELOC_MICROMIPS_CALL16:
15355 case BFD_RELOC_MICROMIPS_GOT16:
15356 case BFD_RELOC_MICROMIPS_GOT_HI16:
15357 case BFD_RELOC_MICROMIPS_GOT_LO16:
15358 case BFD_RELOC_MICROMIPS_CALL_HI16:
15359 case BFD_RELOC_MICROMIPS_CALL_LO16:
15360 /* Nothing needed to do. The value comes from the reloc entry. */
15364 /* This is handled like BFD_RELOC_32, but we output a sign
15365 extended value if we are only 32 bits. */
15368 if (8 <= sizeof (valueT))
15369 md_number_to_chars ((char *) buf, *valP, 8);
15374 if ((*valP & 0x80000000) != 0)
15378 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
15380 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
15386 case BFD_RELOC_RVA:
15389 /* If we are deleting this reloc entry, we must fill in the
15390 value now. This can happen if we have a .word which is not
15391 resolved when it appears but is later defined. */
15393 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
15396 case BFD_RELOC_LO16:
15397 case BFD_RELOC_MIPS16_LO16:
15398 case BFD_RELOC_MICROMIPS_LO16:
15399 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15400 may be safe to remove, but if so it's not obvious. */
15401 /* When handling an embedded PIC switch statement, we can wind
15402 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15405 if (*valP + 0x8000 > 0xffff)
15406 as_bad_where (fixP->fx_file, fixP->fx_line,
15407 _("relocation overflow"));
15408 /* 32-bit microMIPS instructions are divided into two halfwords.
15409 Relocations always refer to the second halfword, regardless
15411 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
15413 md_number_to_chars ((char *) buf, *valP, 2);
15417 case BFD_RELOC_16_PCREL_S2:
15418 if ((*valP & 0x3) != 0)
15419 as_bad_where (fixP->fx_file, fixP->fx_line,
15420 _("Branch to misaligned address (%lx)"), (long) *valP);
15422 /* We need to save the bits in the instruction since fixup_segment()
15423 might be deleting the relocation entry (i.e., a branch within
15424 the current segment). */
15425 if (! fixP->fx_done)
15428 /* Update old instruction data. */
15429 if (target_big_endian)
15430 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
15432 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
15434 if (*valP + 0x20000 <= 0x3ffff)
15436 insn |= (*valP >> 2) & 0xffff;
15437 md_number_to_chars ((char *) buf, insn, 4);
15439 else if (mips_pic == NO_PIC
15441 && fixP->fx_frag->fr_address >= text_section->vma
15442 && (fixP->fx_frag->fr_address
15443 < text_section->vma + bfd_get_section_size (text_section))
15444 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15445 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15446 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15448 /* The branch offset is too large. If this is an
15449 unconditional branch, and we are not generating PIC code,
15450 we can convert it to an absolute jump instruction. */
15451 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15452 insn = 0x0c000000; /* jal */
15454 insn = 0x08000000; /* j */
15455 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15457 fixP->fx_addsy = section_symbol (text_section);
15458 *valP += md_pcrel_from (fixP);
15459 md_number_to_chars ((char *) buf, insn, 4);
15463 /* If we got here, we have branch-relaxation disabled,
15464 and there's nothing we can do to fix this instruction
15465 without turning it into a longer sequence. */
15466 as_bad_where (fixP->fx_file, fixP->fx_line,
15467 _("Branch out of range"));
15471 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15472 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15473 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15474 /* We adjust the offset back to even. */
15475 if ((*valP & 0x1) != 0)
15478 if (! fixP->fx_done)
15481 /* Should never visit here, because we keep the relocation. */
15485 case BFD_RELOC_VTABLE_INHERIT:
15488 && !S_IS_DEFINED (fixP->fx_addsy)
15489 && !S_IS_WEAK (fixP->fx_addsy))
15490 S_SET_WEAK (fixP->fx_addsy);
15493 case BFD_RELOC_VTABLE_ENTRY:
15501 /* Remember value for tc_gen_reloc. */
15502 fixP->fx_addnumber = *valP;
15512 name = input_line_pointer;
15513 c = get_symbol_end ();
15514 p = (symbolS *) symbol_find_or_make (name);
15515 *input_line_pointer = c;
15519 /* Align the current frag to a given power of two. If a particular
15520 fill byte should be used, FILL points to an integer that contains
15521 that byte, otherwise FILL is null.
15523 The MIPS assembler also automatically adjusts any preceding
15527 mips_align (int to, int *fill, symbolS *label)
15529 mips_emit_delays ();
15530 mips_record_compressed_mode ();
15531 if (fill == NULL && subseg_text_p (now_seg))
15532 frag_align_code (to, 0);
15534 frag_align (to, fill ? *fill : 0, 0);
15535 record_alignment (now_seg, to);
15538 gas_assert (S_GET_SEGMENT (label) == now_seg);
15539 symbol_set_frag (label, frag_now);
15540 S_SET_VALUE (label, (valueT) frag_now_fix ());
15544 /* Align to a given power of two. .align 0 turns off the automatic
15545 alignment used by the data creating pseudo-ops. */
15548 s_align (int x ATTRIBUTE_UNUSED)
15550 int temp, fill_value, *fill_ptr;
15551 long max_alignment = 28;
15553 /* o Note that the assembler pulls down any immediately preceding label
15554 to the aligned address.
15555 o It's not documented but auto alignment is reinstated by
15556 a .align pseudo instruction.
15557 o Note also that after auto alignment is turned off the mips assembler
15558 issues an error on attempt to assemble an improperly aligned data item.
15561 temp = get_absolute_expression ();
15562 if (temp > max_alignment)
15563 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15566 as_warn (_("Alignment negative: 0 assumed."));
15569 if (*input_line_pointer == ',')
15571 ++input_line_pointer;
15572 fill_value = get_absolute_expression ();
15573 fill_ptr = &fill_value;
15579 segment_info_type *si = seg_info (now_seg);
15580 struct insn_label_list *l = si->label_list;
15581 /* Auto alignment should be switched on by next section change. */
15583 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
15590 demand_empty_rest_of_line ();
15594 s_change_sec (int sec)
15599 /* The ELF backend needs to know that we are changing sections, so
15600 that .previous works correctly. We could do something like check
15601 for an obj_section_change_hook macro, but that might be confusing
15602 as it would not be appropriate to use it in the section changing
15603 functions in read.c, since obj-elf.c intercepts those. FIXME:
15604 This should be cleaner, somehow. */
15606 obj_elf_section_change_hook ();
15609 mips_emit_delays ();
15620 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15621 demand_empty_rest_of_line ();
15625 seg = subseg_new (RDATA_SECTION_NAME,
15626 (subsegT) get_absolute_expression ());
15629 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15630 | SEC_READONLY | SEC_RELOC
15632 if (strncmp (TARGET_OS, "elf", 3) != 0)
15633 record_alignment (seg, 4);
15635 demand_empty_rest_of_line ();
15639 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15642 bfd_set_section_flags (stdoutput, seg,
15643 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15644 if (strncmp (TARGET_OS, "elf", 3) != 0)
15645 record_alignment (seg, 4);
15647 demand_empty_rest_of_line ();
15651 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15654 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15655 if (strncmp (TARGET_OS, "elf", 3) != 0)
15656 record_alignment (seg, 4);
15658 demand_empty_rest_of_line ();
15666 s_change_section (int ignore ATTRIBUTE_UNUSED)
15669 char *section_name;
15674 int section_entry_size;
15675 int section_alignment;
15680 section_name = input_line_pointer;
15681 c = get_symbol_end ();
15683 next_c = *(input_line_pointer + 1);
15685 /* Do we have .section Name<,"flags">? */
15686 if (c != ',' || (c == ',' && next_c == '"'))
15688 /* just after name is now '\0'. */
15689 *input_line_pointer = c;
15690 input_line_pointer = section_name;
15691 obj_elf_section (ignore);
15694 input_line_pointer++;
15696 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15698 section_type = get_absolute_expression ();
15701 if (*input_line_pointer++ == ',')
15702 section_flag = get_absolute_expression ();
15705 if (*input_line_pointer++ == ',')
15706 section_entry_size = get_absolute_expression ();
15708 section_entry_size = 0;
15709 if (*input_line_pointer++ == ',')
15710 section_alignment = get_absolute_expression ();
15712 section_alignment = 0;
15713 /* FIXME: really ignore? */
15714 (void) section_alignment;
15716 section_name = xstrdup (section_name);
15718 /* When using the generic form of .section (as implemented by obj-elf.c),
15719 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15720 traditionally had to fall back on the more common @progbits instead.
15722 There's nothing really harmful in this, since bfd will correct
15723 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15724 means that, for backwards compatibility, the special_section entries
15725 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15727 Even so, we shouldn't force users of the MIPS .section syntax to
15728 incorrectly label the sections as SHT_PROGBITS. The best compromise
15729 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15730 generic type-checking code. */
15731 if (section_type == SHT_MIPS_DWARF)
15732 section_type = SHT_PROGBITS;
15734 obj_elf_change_section (section_name, section_type, section_flag,
15735 section_entry_size, 0, 0, 0);
15737 if (now_seg->name != section_name)
15738 free (section_name);
15739 #endif /* OBJ_ELF */
15743 mips_enable_auto_align (void)
15749 s_cons (int log_size)
15751 segment_info_type *si = seg_info (now_seg);
15752 struct insn_label_list *l = si->label_list;
15755 label = l != NULL ? l->label : NULL;
15756 mips_emit_delays ();
15757 if (log_size > 0 && auto_align)
15758 mips_align (log_size, 0, label);
15759 cons (1 << log_size);
15760 mips_clear_insn_labels ();
15764 s_float_cons (int type)
15766 segment_info_type *si = seg_info (now_seg);
15767 struct insn_label_list *l = si->label_list;
15770 label = l != NULL ? l->label : NULL;
15772 mips_emit_delays ();
15777 mips_align (3, 0, label);
15779 mips_align (2, 0, label);
15783 mips_clear_insn_labels ();
15786 /* Handle .globl. We need to override it because on Irix 5 you are
15789 where foo is an undefined symbol, to mean that foo should be
15790 considered to be the address of a function. */
15793 s_mips_globl (int x ATTRIBUTE_UNUSED)
15802 name = input_line_pointer;
15803 c = get_symbol_end ();
15804 symbolP = symbol_find_or_make (name);
15805 S_SET_EXTERNAL (symbolP);
15807 *input_line_pointer = c;
15808 SKIP_WHITESPACE ();
15810 /* On Irix 5, every global symbol that is not explicitly labelled as
15811 being a function is apparently labelled as being an object. */
15814 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15815 && (*input_line_pointer != ','))
15820 secname = input_line_pointer;
15821 c = get_symbol_end ();
15822 sec = bfd_get_section_by_name (stdoutput, secname);
15824 as_bad (_("%s: no such section"), secname);
15825 *input_line_pointer = c;
15827 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15828 flag = BSF_FUNCTION;
15831 symbol_get_bfdsym (symbolP)->flags |= flag;
15833 c = *input_line_pointer;
15836 input_line_pointer++;
15837 SKIP_WHITESPACE ();
15838 if (is_end_of_line[(unsigned char) *input_line_pointer])
15844 demand_empty_rest_of_line ();
15848 s_option (int x ATTRIBUTE_UNUSED)
15853 opt = input_line_pointer;
15854 c = get_symbol_end ();
15858 /* FIXME: What does this mean? */
15860 else if (strncmp (opt, "pic", 3) == 0)
15864 i = atoi (opt + 3);
15869 mips_pic = SVR4_PIC;
15870 mips_abicalls = TRUE;
15873 as_bad (_(".option pic%d not supported"), i);
15875 if (mips_pic == SVR4_PIC)
15877 if (g_switch_seen && g_switch_value != 0)
15878 as_warn (_("-G may not be used with SVR4 PIC code"));
15879 g_switch_value = 0;
15880 bfd_set_gp_size (stdoutput, 0);
15884 as_warn (_("Unrecognized option \"%s\""), opt);
15886 *input_line_pointer = c;
15887 demand_empty_rest_of_line ();
15890 /* This structure is used to hold a stack of .set values. */
15892 struct mips_option_stack
15894 struct mips_option_stack *next;
15895 struct mips_set_options options;
15898 static struct mips_option_stack *mips_opts_stack;
15900 /* Handle the .set pseudo-op. */
15903 s_mipsset (int x ATTRIBUTE_UNUSED)
15905 char *name = input_line_pointer, ch;
15907 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15908 ++input_line_pointer;
15909 ch = *input_line_pointer;
15910 *input_line_pointer = '\0';
15912 if (strcmp (name, "reorder") == 0)
15914 if (mips_opts.noreorder)
15917 else if (strcmp (name, "noreorder") == 0)
15919 if (!mips_opts.noreorder)
15920 start_noreorder ();
15922 else if (strncmp (name, "at=", 3) == 0)
15924 char *s = name + 3;
15926 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15927 as_bad (_("Unrecognized register name `%s'"), s);
15929 else if (strcmp (name, "at") == 0)
15931 mips_opts.at = ATREG;
15933 else if (strcmp (name, "noat") == 0)
15935 mips_opts.at = ZERO;
15937 else if (strcmp (name, "macro") == 0)
15939 mips_opts.warn_about_macros = 0;
15941 else if (strcmp (name, "nomacro") == 0)
15943 if (mips_opts.noreorder == 0)
15944 as_bad (_("`noreorder' must be set before `nomacro'"));
15945 mips_opts.warn_about_macros = 1;
15947 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15949 mips_opts.nomove = 0;
15951 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15953 mips_opts.nomove = 1;
15955 else if (strcmp (name, "bopt") == 0)
15957 mips_opts.nobopt = 0;
15959 else if (strcmp (name, "nobopt") == 0)
15961 mips_opts.nobopt = 1;
15963 else if (strcmp (name, "gp=default") == 0)
15964 mips_opts.gp32 = file_mips_gp32;
15965 else if (strcmp (name, "gp=32") == 0)
15966 mips_opts.gp32 = 1;
15967 else if (strcmp (name, "gp=64") == 0)
15969 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
15970 as_warn (_("%s isa does not support 64-bit registers"),
15971 mips_cpu_info_from_isa (mips_opts.isa)->name);
15972 mips_opts.gp32 = 0;
15974 else if (strcmp (name, "fp=default") == 0)
15975 mips_opts.fp32 = file_mips_fp32;
15976 else if (strcmp (name, "fp=32") == 0)
15977 mips_opts.fp32 = 1;
15978 else if (strcmp (name, "fp=64") == 0)
15980 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15981 as_warn (_("%s isa does not support 64-bit floating point registers"),
15982 mips_cpu_info_from_isa (mips_opts.isa)->name);
15983 mips_opts.fp32 = 0;
15985 else if (strcmp (name, "softfloat") == 0)
15986 mips_opts.soft_float = 1;
15987 else if (strcmp (name, "hardfloat") == 0)
15988 mips_opts.soft_float = 0;
15989 else if (strcmp (name, "singlefloat") == 0)
15990 mips_opts.single_float = 1;
15991 else if (strcmp (name, "doublefloat") == 0)
15992 mips_opts.single_float = 0;
15993 else if (strcmp (name, "mips16") == 0
15994 || strcmp (name, "MIPS-16") == 0)
15996 if (mips_opts.micromips == 1)
15997 as_fatal (_("`mips16' cannot be used with `micromips'"));
15998 mips_opts.mips16 = 1;
16000 else if (strcmp (name, "nomips16") == 0
16001 || strcmp (name, "noMIPS-16") == 0)
16002 mips_opts.mips16 = 0;
16003 else if (strcmp (name, "micromips") == 0)
16005 if (mips_opts.mips16 == 1)
16006 as_fatal (_("`micromips' cannot be used with `mips16'"));
16007 mips_opts.micromips = 1;
16009 else if (strcmp (name, "nomicromips") == 0)
16010 mips_opts.micromips = 0;
16011 else if (strcmp (name, "smartmips") == 0)
16013 if (!ISA_SUPPORTS_SMARTMIPS)
16014 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16015 mips_cpu_info_from_isa (mips_opts.isa)->name);
16016 mips_opts.ase_smartmips = 1;
16018 else if (strcmp (name, "nosmartmips") == 0)
16019 mips_opts.ase_smartmips = 0;
16020 else if (strcmp (name, "mips3d") == 0)
16021 mips_opts.ase_mips3d = 1;
16022 else if (strcmp (name, "nomips3d") == 0)
16023 mips_opts.ase_mips3d = 0;
16024 else if (strcmp (name, "mdmx") == 0)
16025 mips_opts.ase_mdmx = 1;
16026 else if (strcmp (name, "nomdmx") == 0)
16027 mips_opts.ase_mdmx = 0;
16028 else if (strcmp (name, "dsp") == 0)
16030 if (!ISA_SUPPORTS_DSP_ASE)
16031 as_warn (_("%s ISA does not support DSP ASE"),
16032 mips_cpu_info_from_isa (mips_opts.isa)->name);
16033 mips_opts.ase_dsp = 1;
16034 mips_opts.ase_dspr2 = 0;
16036 else if (strcmp (name, "nodsp") == 0)
16038 mips_opts.ase_dsp = 0;
16039 mips_opts.ase_dspr2 = 0;
16041 else if (strcmp (name, "dspr2") == 0)
16043 if (!ISA_SUPPORTS_DSPR2_ASE)
16044 as_warn (_("%s ISA does not support DSP R2 ASE"),
16045 mips_cpu_info_from_isa (mips_opts.isa)->name);
16046 mips_opts.ase_dspr2 = 1;
16047 mips_opts.ase_dsp = 1;
16049 else if (strcmp (name, "nodspr2") == 0)
16051 mips_opts.ase_dspr2 = 0;
16052 mips_opts.ase_dsp = 0;
16054 else if (strcmp (name, "mt") == 0)
16056 if (!ISA_SUPPORTS_MT_ASE)
16057 as_warn (_("%s ISA does not support MT ASE"),
16058 mips_cpu_info_from_isa (mips_opts.isa)->name);
16059 mips_opts.ase_mt = 1;
16061 else if (strcmp (name, "nomt") == 0)
16062 mips_opts.ase_mt = 0;
16063 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16067 /* Permit the user to change the ISA and architecture on the fly.
16068 Needless to say, misuse can cause serious problems. */
16069 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16072 mips_opts.isa = file_mips_isa;
16073 mips_opts.arch = file_mips_arch;
16075 else if (strncmp (name, "arch=", 5) == 0)
16077 const struct mips_cpu_info *p;
16079 p = mips_parse_cpu("internal use", name + 5);
16081 as_bad (_("unknown architecture %s"), name + 5);
16084 mips_opts.arch = p->cpu;
16085 mips_opts.isa = p->isa;
16088 else if (strncmp (name, "mips", 4) == 0)
16090 const struct mips_cpu_info *p;
16092 p = mips_parse_cpu("internal use", name);
16094 as_bad (_("unknown ISA level %s"), name + 4);
16097 mips_opts.arch = p->cpu;
16098 mips_opts.isa = p->isa;
16102 as_bad (_("unknown ISA or architecture %s"), name);
16104 switch (mips_opts.isa)
16112 mips_opts.gp32 = 1;
16113 mips_opts.fp32 = 1;
16120 mips_opts.gp32 = 0;
16121 mips_opts.fp32 = 0;
16124 as_bad (_("unknown ISA level %s"), name + 4);
16129 mips_opts.gp32 = file_mips_gp32;
16130 mips_opts.fp32 = file_mips_fp32;
16133 else if (strcmp (name, "autoextend") == 0)
16134 mips_opts.noautoextend = 0;
16135 else if (strcmp (name, "noautoextend") == 0)
16136 mips_opts.noautoextend = 1;
16137 else if (strcmp (name, "push") == 0)
16139 struct mips_option_stack *s;
16141 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16142 s->next = mips_opts_stack;
16143 s->options = mips_opts;
16144 mips_opts_stack = s;
16146 else if (strcmp (name, "pop") == 0)
16148 struct mips_option_stack *s;
16150 s = mips_opts_stack;
16152 as_bad (_(".set pop with no .set push"));
16155 /* If we're changing the reorder mode we need to handle
16156 delay slots correctly. */
16157 if (s->options.noreorder && ! mips_opts.noreorder)
16158 start_noreorder ();
16159 else if (! s->options.noreorder && mips_opts.noreorder)
16162 mips_opts = s->options;
16163 mips_opts_stack = s->next;
16167 else if (strcmp (name, "sym32") == 0)
16168 mips_opts.sym32 = TRUE;
16169 else if (strcmp (name, "nosym32") == 0)
16170 mips_opts.sym32 = FALSE;
16171 else if (strchr (name, ','))
16173 /* Generic ".set" directive; use the generic handler. */
16174 *input_line_pointer = ch;
16175 input_line_pointer = name;
16181 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16183 *input_line_pointer = ch;
16184 demand_empty_rest_of_line ();
16187 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16188 .option pic2. It means to generate SVR4 PIC calls. */
16191 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16193 mips_pic = SVR4_PIC;
16194 mips_abicalls = TRUE;
16196 if (g_switch_seen && g_switch_value != 0)
16197 as_warn (_("-G may not be used with SVR4 PIC code"));
16198 g_switch_value = 0;
16200 bfd_set_gp_size (stdoutput, 0);
16201 demand_empty_rest_of_line ();
16204 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16205 PIC code. It sets the $gp register for the function based on the
16206 function address, which is in the register named in the argument.
16207 This uses a relocation against _gp_disp, which is handled specially
16208 by the linker. The result is:
16209 lui $gp,%hi(_gp_disp)
16210 addiu $gp,$gp,%lo(_gp_disp)
16211 addu $gp,$gp,.cpload argument
16212 The .cpload argument is normally $25 == $t9.
16214 The -mno-shared option changes this to:
16215 lui $gp,%hi(__gnu_local_gp)
16216 addiu $gp,$gp,%lo(__gnu_local_gp)
16217 and the argument is ignored. This saves an instruction, but the
16218 resulting code is not position independent; it uses an absolute
16219 address for __gnu_local_gp. Thus code assembled with -mno-shared
16220 can go into an ordinary executable, but not into a shared library. */
16223 s_cpload (int ignore ATTRIBUTE_UNUSED)
16229 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16230 .cpload is ignored. */
16231 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16237 /* .cpload should be in a .set noreorder section. */
16238 if (mips_opts.noreorder == 0)
16239 as_warn (_(".cpload not in noreorder section"));
16241 reg = tc_get_register (0);
16243 /* If we need to produce a 64-bit address, we are better off using
16244 the default instruction sequence. */
16245 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16247 ex.X_op = O_symbol;
16248 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16250 ex.X_op_symbol = NULL;
16251 ex.X_add_number = 0;
16253 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16254 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16257 macro_build_lui (&ex, mips_gp_register);
16258 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16259 mips_gp_register, BFD_RELOC_LO16);
16261 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16262 mips_gp_register, reg);
16265 demand_empty_rest_of_line ();
16268 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16269 .cpsetup $reg1, offset|$reg2, label
16271 If offset is given, this results in:
16272 sd $gp, offset($sp)
16273 lui $gp, %hi(%neg(%gp_rel(label)))
16274 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16275 daddu $gp, $gp, $reg1
16277 If $reg2 is given, this results in:
16278 daddu $reg2, $gp, $0
16279 lui $gp, %hi(%neg(%gp_rel(label)))
16280 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16281 daddu $gp, $gp, $reg1
16282 $reg1 is normally $25 == $t9.
16284 The -mno-shared option replaces the last three instructions with
16286 addiu $gp,$gp,%lo(_gp) */
16289 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16291 expressionS ex_off;
16292 expressionS ex_sym;
16295 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16296 We also need NewABI support. */
16297 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16303 reg1 = tc_get_register (0);
16304 SKIP_WHITESPACE ();
16305 if (*input_line_pointer != ',')
16307 as_bad (_("missing argument separator ',' for .cpsetup"));
16311 ++input_line_pointer;
16312 SKIP_WHITESPACE ();
16313 if (*input_line_pointer == '$')
16315 mips_cpreturn_register = tc_get_register (0);
16316 mips_cpreturn_offset = -1;
16320 mips_cpreturn_offset = get_absolute_expression ();
16321 mips_cpreturn_register = -1;
16323 SKIP_WHITESPACE ();
16324 if (*input_line_pointer != ',')
16326 as_bad (_("missing argument separator ',' for .cpsetup"));
16330 ++input_line_pointer;
16331 SKIP_WHITESPACE ();
16332 expression (&ex_sym);
16335 if (mips_cpreturn_register == -1)
16337 ex_off.X_op = O_constant;
16338 ex_off.X_add_symbol = NULL;
16339 ex_off.X_op_symbol = NULL;
16340 ex_off.X_add_number = mips_cpreturn_offset;
16342 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16343 BFD_RELOC_LO16, SP);
16346 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16347 mips_gp_register, 0);
16349 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16351 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16352 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16355 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16356 mips_gp_register, -1, BFD_RELOC_GPREL16,
16357 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16359 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16360 mips_gp_register, reg1);
16366 ex.X_op = O_symbol;
16367 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16368 ex.X_op_symbol = NULL;
16369 ex.X_add_number = 0;
16371 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16372 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16374 macro_build_lui (&ex, mips_gp_register);
16375 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16376 mips_gp_register, BFD_RELOC_LO16);
16381 demand_empty_rest_of_line ();
16385 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16387 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16388 .cplocal is ignored. */
16389 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16395 mips_gp_register = tc_get_register (0);
16396 demand_empty_rest_of_line ();
16399 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16400 offset from $sp. The offset is remembered, and after making a PIC
16401 call $gp is restored from that location. */
16404 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16408 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16409 .cprestore is ignored. */
16410 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16416 mips_cprestore_offset = get_absolute_expression ();
16417 mips_cprestore_valid = 1;
16419 ex.X_op = O_constant;
16420 ex.X_add_symbol = NULL;
16421 ex.X_op_symbol = NULL;
16422 ex.X_add_number = mips_cprestore_offset;
16425 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16426 SP, HAVE_64BIT_ADDRESSES);
16429 demand_empty_rest_of_line ();
16432 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16433 was given in the preceding .cpsetup, it results in:
16434 ld $gp, offset($sp)
16436 If a register $reg2 was given there, it results in:
16437 daddu $gp, $reg2, $0 */
16440 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16444 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16445 We also need NewABI support. */
16446 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16453 if (mips_cpreturn_register == -1)
16455 ex.X_op = O_constant;
16456 ex.X_add_symbol = NULL;
16457 ex.X_op_symbol = NULL;
16458 ex.X_add_number = mips_cpreturn_offset;
16460 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16463 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16464 mips_cpreturn_register, 0);
16467 demand_empty_rest_of_line ();
16470 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
16471 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
16472 use in DWARF debug information. */
16475 s_dtprel_internal (size_t bytes)
16482 if (ex.X_op != O_symbol)
16484 as_bad (_("Unsupported use of %s"), (bytes == 8
16487 ignore_rest_of_line ();
16490 p = frag_more (bytes);
16491 md_number_to_chars (p, 0, bytes);
16492 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
16494 ? BFD_RELOC_MIPS_TLS_DTPREL64
16495 : BFD_RELOC_MIPS_TLS_DTPREL32));
16497 demand_empty_rest_of_line ();
16500 /* Handle .dtprelword. */
16503 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16505 s_dtprel_internal (4);
16508 /* Handle .dtpreldword. */
16511 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16513 s_dtprel_internal (8);
16516 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16517 code. It sets the offset to use in gp_rel relocations. */
16520 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16522 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16523 We also need NewABI support. */
16524 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16530 mips_gprel_offset = get_absolute_expression ();
16532 demand_empty_rest_of_line ();
16535 /* Handle the .gpword pseudo-op. This is used when generating PIC
16536 code. It generates a 32 bit GP relative reloc. */
16539 s_gpword (int ignore ATTRIBUTE_UNUSED)
16541 segment_info_type *si;
16542 struct insn_label_list *l;
16547 /* When not generating PIC code, this is treated as .word. */
16548 if (mips_pic != SVR4_PIC)
16554 si = seg_info (now_seg);
16555 l = si->label_list;
16556 label = l != NULL ? l->label : NULL;
16557 mips_emit_delays ();
16559 mips_align (2, 0, label);
16562 mips_clear_insn_labels ();
16564 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16566 as_bad (_("Unsupported use of .gpword"));
16567 ignore_rest_of_line ();
16571 md_number_to_chars (p, 0, 4);
16572 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16573 BFD_RELOC_GPREL32);
16575 demand_empty_rest_of_line ();
16579 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16581 segment_info_type *si;
16582 struct insn_label_list *l;
16587 /* When not generating PIC code, this is treated as .dword. */
16588 if (mips_pic != SVR4_PIC)
16594 si = seg_info (now_seg);
16595 l = si->label_list;
16596 label = l != NULL ? l->label : NULL;
16597 mips_emit_delays ();
16599 mips_align (3, 0, label);
16602 mips_clear_insn_labels ();
16604 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16606 as_bad (_("Unsupported use of .gpdword"));
16607 ignore_rest_of_line ();
16611 md_number_to_chars (p, 0, 8);
16612 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16613 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16615 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16616 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16617 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16619 demand_empty_rest_of_line ();
16622 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16623 tables in SVR4 PIC code. */
16626 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16630 /* This is ignored when not generating SVR4 PIC code. */
16631 if (mips_pic != SVR4_PIC)
16637 /* Add $gp to the register named as an argument. */
16639 reg = tc_get_register (0);
16640 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16643 demand_empty_rest_of_line ();
16646 /* Handle the .insn pseudo-op. This marks instruction labels in
16647 mips16/micromips mode. This permits the linker to handle them specially,
16648 such as generating jalx instructions when needed. We also make
16649 them odd for the duration of the assembly, in order to generate the
16650 right sort of code. We will make them even in the adjust_symtab
16651 routine, while leaving them marked. This is convenient for the
16652 debugger and the disassembler. The linker knows to make them odd
16656 s_insn (int ignore ATTRIBUTE_UNUSED)
16658 mips_mark_labels ();
16660 demand_empty_rest_of_line ();
16663 /* Handle a .stabn directive. We need these in order to mark a label
16664 as being a mips16 text label correctly. Sometimes the compiler
16665 will emit a label, followed by a .stabn, and then switch sections.
16666 If the label and .stabn are in mips16 mode, then the label is
16667 really a mips16 text label. */
16670 s_mips_stab (int type)
16673 mips_mark_labels ();
16678 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16681 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16688 name = input_line_pointer;
16689 c = get_symbol_end ();
16690 symbolP = symbol_find_or_make (name);
16691 S_SET_WEAK (symbolP);
16692 *input_line_pointer = c;
16694 SKIP_WHITESPACE ();
16696 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16698 if (S_IS_DEFINED (symbolP))
16700 as_bad (_("ignoring attempt to redefine symbol %s"),
16701 S_GET_NAME (symbolP));
16702 ignore_rest_of_line ();
16706 if (*input_line_pointer == ',')
16708 ++input_line_pointer;
16709 SKIP_WHITESPACE ();
16713 if (exp.X_op != O_symbol)
16715 as_bad (_("bad .weakext directive"));
16716 ignore_rest_of_line ();
16719 symbol_set_value_expression (symbolP, &exp);
16722 demand_empty_rest_of_line ();
16725 /* Parse a register string into a number. Called from the ECOFF code
16726 to parse .frame. The argument is non-zero if this is the frame
16727 register, so that we can record it in mips_frame_reg. */
16730 tc_get_register (int frame)
16734 SKIP_WHITESPACE ();
16735 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16739 mips_frame_reg = reg != 0 ? reg : SP;
16740 mips_frame_reg_valid = 1;
16741 mips_cprestore_valid = 0;
16747 md_section_align (asection *seg, valueT addr)
16749 int align = bfd_get_section_alignment (stdoutput, seg);
16753 /* We don't need to align ELF sections to the full alignment.
16754 However, Irix 5 may prefer that we align them at least to a 16
16755 byte boundary. We don't bother to align the sections if we
16756 are targeted for an embedded system. */
16757 if (strncmp (TARGET_OS, "elf", 3) == 0)
16763 return ((addr + (1 << align) - 1) & (-1 << align));
16766 /* Utility routine, called from above as well. If called while the
16767 input file is still being read, it's only an approximation. (For
16768 example, a symbol may later become defined which appeared to be
16769 undefined earlier.) */
16772 nopic_need_relax (symbolS *sym, int before_relaxing)
16777 if (g_switch_value > 0)
16779 const char *symname;
16782 /* Find out whether this symbol can be referenced off the $gp
16783 register. It can be if it is smaller than the -G size or if
16784 it is in the .sdata or .sbss section. Certain symbols can
16785 not be referenced off the $gp, although it appears as though
16787 symname = S_GET_NAME (sym);
16788 if (symname != (const char *) NULL
16789 && (strcmp (symname, "eprol") == 0
16790 || strcmp (symname, "etext") == 0
16791 || strcmp (symname, "_gp") == 0
16792 || strcmp (symname, "edata") == 0
16793 || strcmp (symname, "_fbss") == 0
16794 || strcmp (symname, "_fdata") == 0
16795 || strcmp (symname, "_ftext") == 0
16796 || strcmp (symname, "end") == 0
16797 || strcmp (symname, "_gp_disp") == 0))
16799 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16801 #ifndef NO_ECOFF_DEBUGGING
16802 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16803 && (symbol_get_obj (sym)->ecoff_extern_size
16804 <= g_switch_value))
16806 /* We must defer this decision until after the whole
16807 file has been read, since there might be a .extern
16808 after the first use of this symbol. */
16809 || (before_relaxing
16810 #ifndef NO_ECOFF_DEBUGGING
16811 && symbol_get_obj (sym)->ecoff_extern_size == 0
16813 && S_GET_VALUE (sym) == 0)
16814 || (S_GET_VALUE (sym) != 0
16815 && S_GET_VALUE (sym) <= g_switch_value)))
16819 const char *segname;
16821 segname = segment_name (S_GET_SEGMENT (sym));
16822 gas_assert (strcmp (segname, ".lit8") != 0
16823 && strcmp (segname, ".lit4") != 0);
16824 change = (strcmp (segname, ".sdata") != 0
16825 && strcmp (segname, ".sbss") != 0
16826 && strncmp (segname, ".sdata.", 7) != 0
16827 && strncmp (segname, ".sbss.", 6) != 0
16828 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16829 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16834 /* We are not optimizing for the $gp register. */
16839 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16842 pic_need_relax (symbolS *sym, asection *segtype)
16846 /* Handle the case of a symbol equated to another symbol. */
16847 while (symbol_equated_reloc_p (sym))
16851 /* It's possible to get a loop here in a badly written program. */
16852 n = symbol_get_value_expression (sym)->X_add_symbol;
16858 if (symbol_section_p (sym))
16861 symsec = S_GET_SEGMENT (sym);
16863 /* This must duplicate the test in adjust_reloc_syms. */
16864 return (symsec != &bfd_und_section
16865 && symsec != &bfd_abs_section
16866 && !bfd_is_com_section (symsec)
16867 && !s_is_linkonce (sym, segtype)
16869 /* A global or weak symbol is treated as external. */
16870 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
16876 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16877 extended opcode. SEC is the section the frag is in. */
16880 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16883 const struct mips16_immed_operand *op;
16885 int mintiny, maxtiny;
16889 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16891 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16894 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16895 op = mips16_immed_operands;
16896 while (op->type != type)
16899 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
16904 if (type == '<' || type == '>' || type == '[' || type == ']')
16907 maxtiny = 1 << op->nbits;
16912 maxtiny = (1 << op->nbits) - 1;
16917 mintiny = - (1 << (op->nbits - 1));
16918 maxtiny = (1 << (op->nbits - 1)) - 1;
16921 sym_frag = symbol_get_frag (fragp->fr_symbol);
16922 val = S_GET_VALUE (fragp->fr_symbol);
16923 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16929 /* We won't have the section when we are called from
16930 mips_relax_frag. However, we will always have been called
16931 from md_estimate_size_before_relax first. If this is a
16932 branch to a different section, we mark it as such. If SEC is
16933 NULL, and the frag is not marked, then it must be a branch to
16934 the same section. */
16937 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16942 /* Must have been called from md_estimate_size_before_relax. */
16945 fragp->fr_subtype =
16946 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16948 /* FIXME: We should support this, and let the linker
16949 catch branches and loads that are out of range. */
16950 as_bad_where (fragp->fr_file, fragp->fr_line,
16951 _("unsupported PC relative reference to different section"));
16955 if (fragp != sym_frag && sym_frag->fr_address == 0)
16956 /* Assume non-extended on the first relaxation pass.
16957 The address we have calculated will be bogus if this is
16958 a forward branch to another frag, as the forward frag
16959 will have fr_address == 0. */
16963 /* In this case, we know for sure that the symbol fragment is in
16964 the same section. If the relax_marker of the symbol fragment
16965 differs from the relax_marker of this fragment, we have not
16966 yet adjusted the symbol fragment fr_address. We want to add
16967 in STRETCH in order to get a better estimate of the address.
16968 This particularly matters because of the shift bits. */
16970 && sym_frag->relax_marker != fragp->relax_marker)
16974 /* Adjust stretch for any alignment frag. Note that if have
16975 been expanding the earlier code, the symbol may be
16976 defined in what appears to be an earlier frag. FIXME:
16977 This doesn't handle the fr_subtype field, which specifies
16978 a maximum number of bytes to skip when doing an
16980 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16982 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16985 stretch = - ((- stretch)
16986 & ~ ((1 << (int) f->fr_offset) - 1));
16988 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16997 addr = fragp->fr_address + fragp->fr_fix;
16999 /* The base address rules are complicated. The base address of
17000 a branch is the following instruction. The base address of a
17001 PC relative load or add is the instruction itself, but if it
17002 is in a delay slot (in which case it can not be extended) use
17003 the address of the instruction whose delay slot it is in. */
17004 if (type == 'p' || type == 'q')
17008 /* If we are currently assuming that this frag should be
17009 extended, then, the current address is two bytes
17011 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17014 /* Ignore the low bit in the target, since it will be set
17015 for a text label. */
17016 if ((val & 1) != 0)
17019 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17021 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17024 val -= addr & ~ ((1 << op->shift) - 1);
17026 /* Branch offsets have an implicit 0 in the lowest bit. */
17027 if (type == 'p' || type == 'q')
17030 /* If any of the shifted bits are set, we must use an extended
17031 opcode. If the address depends on the size of this
17032 instruction, this can lead to a loop, so we arrange to always
17033 use an extended opcode. We only check this when we are in
17034 the main relaxation loop, when SEC is NULL. */
17035 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17037 fragp->fr_subtype =
17038 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17042 /* If we are about to mark a frag as extended because the value
17043 is precisely maxtiny + 1, then there is a chance of an
17044 infinite loop as in the following code:
17049 In this case when the la is extended, foo is 0x3fc bytes
17050 away, so the la can be shrunk, but then foo is 0x400 away, so
17051 the la must be extended. To avoid this loop, we mark the
17052 frag as extended if it was small, and is about to become
17053 extended with a value of maxtiny + 1. */
17054 if (val == ((maxtiny + 1) << op->shift)
17055 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17058 fragp->fr_subtype =
17059 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17063 else if (symsec != absolute_section && sec != NULL)
17064 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17066 if ((val & ((1 << op->shift) - 1)) != 0
17067 || val < (mintiny << op->shift)
17068 || val > (maxtiny << op->shift))
17074 /* Compute the length of a branch sequence, and adjust the
17075 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17076 worst-case length is computed, with UPDATE being used to indicate
17077 whether an unconditional (-1), branch-likely (+1) or regular (0)
17078 branch is to be computed. */
17080 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17082 bfd_boolean toofar;
17086 && S_IS_DEFINED (fragp->fr_symbol)
17087 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17092 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17094 addr = fragp->fr_address + fragp->fr_fix + 4;
17098 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17101 /* If the symbol is not defined or it's in a different segment,
17102 assume the user knows what's going on and emit a short
17108 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17110 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17111 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17112 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17113 RELAX_BRANCH_LINK (fragp->fr_subtype),
17119 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17122 if (mips_pic != NO_PIC)
17124 /* Additional space for PIC loading of target address. */
17126 if (mips_opts.isa == ISA_MIPS1)
17127 /* Additional space for $at-stabilizing nop. */
17131 /* If branch is conditional. */
17132 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17139 /* Compute the length of a branch sequence, and adjust the
17140 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17141 worst-case length is computed, with UPDATE being used to indicate
17142 whether an unconditional (-1), or regular (0) branch is to be
17146 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17148 bfd_boolean toofar;
17152 && S_IS_DEFINED (fragp->fr_symbol)
17153 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17158 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17159 /* Ignore the low bit in the target, since it will be set
17160 for a text label. */
17161 if ((val & 1) != 0)
17164 addr = fragp->fr_address + fragp->fr_fix + 4;
17168 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17171 /* If the symbol is not defined or it's in a different segment,
17172 assume the user knows what's going on and emit a short
17178 if (fragp && update
17179 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17180 fragp->fr_subtype = (toofar
17181 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17182 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17187 bfd_boolean compact_known = fragp != NULL;
17188 bfd_boolean compact = FALSE;
17189 bfd_boolean uncond;
17192 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17194 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17196 uncond = update < 0;
17198 /* If label is out of range, we turn branch <br>:
17200 <br> label # 4 bytes
17206 nop # 2 bytes if compact && !PIC
17209 if (mips_pic == NO_PIC && (!compact_known || compact))
17212 /* If assembling PIC code, we further turn:
17218 lw/ld at, %got(label)(gp) # 4 bytes
17219 d/addiu at, %lo(label) # 4 bytes
17222 if (mips_pic != NO_PIC)
17225 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17227 <brneg> 0f # 4 bytes
17228 nop # 2 bytes if !compact
17231 length += (compact_known && compact) ? 4 : 6;
17237 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17238 bit accordingly. */
17241 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17243 bfd_boolean toofar;
17245 if (RELAX_MICROMIPS_U16BIT (fragp->fr_subtype))
17249 && S_IS_DEFINED (fragp->fr_symbol)
17250 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17256 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17257 /* Ignore the low bit in the target, since it will be set
17258 for a text label. */
17259 if ((val & 1) != 0)
17262 /* Assume this is a 2-byte branch. */
17263 addr = fragp->fr_address + fragp->fr_fix + 2;
17265 /* We try to avoid the infinite loop by not adding 2 more bytes for
17270 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17272 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17273 else if (type == 'E')
17274 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17279 /* If the symbol is not defined or it's in a different segment,
17280 we emit a normal 32-bit branch. */
17283 if (fragp && update
17284 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17286 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17287 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17295 /* Estimate the size of a frag before relaxing. Unless this is the
17296 mips16, we are not really relaxing here, and the final size is
17297 encoded in the subtype information. For the mips16, we have to
17298 decide whether we are using an extended opcode or not. */
17301 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17305 if (RELAX_BRANCH_P (fragp->fr_subtype))
17308 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17310 return fragp->fr_var;
17313 if (RELAX_MIPS16_P (fragp->fr_subtype))
17314 /* We don't want to modify the EXTENDED bit here; it might get us
17315 into infinite loops. We change it only in mips_relax_frag(). */
17316 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17318 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17322 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17323 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17324 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17325 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17326 fragp->fr_var = length;
17331 if (mips_pic == NO_PIC)
17332 change = nopic_need_relax (fragp->fr_symbol, 0);
17333 else if (mips_pic == SVR4_PIC)
17334 change = pic_need_relax (fragp->fr_symbol, segtype);
17335 else if (mips_pic == VXWORKS_PIC)
17336 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17343 fragp->fr_subtype |= RELAX_USE_SECOND;
17344 return -RELAX_FIRST (fragp->fr_subtype);
17347 return -RELAX_SECOND (fragp->fr_subtype);
17350 /* This is called to see whether a reloc against a defined symbol
17351 should be converted into a reloc against a section. */
17354 mips_fix_adjustable (fixS *fixp)
17356 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17357 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17360 if (fixp->fx_addsy == NULL)
17363 /* If symbol SYM is in a mergeable section, relocations of the form
17364 SYM + 0 can usually be made section-relative. The mergeable data
17365 is then identified by the section offset rather than by the symbol.
17367 However, if we're generating REL LO16 relocations, the offset is split
17368 between the LO16 and parterning high part relocation. The linker will
17369 need to recalculate the complete offset in order to correctly identify
17372 The linker has traditionally not looked for the parterning high part
17373 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17374 placed anywhere. Rather than break backwards compatibility by changing
17375 this, it seems better not to force the issue, and instead keep the
17376 original symbol. This will work with either linker behavior. */
17377 if ((lo16_reloc_p (fixp->fx_r_type)
17378 || reloc_needs_lo_p (fixp->fx_r_type))
17379 && HAVE_IN_PLACE_ADDENDS
17380 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17383 /* There is no place to store an in-place offset for JALR relocations.
17384 Likewise an in-range offset of PC-relative relocations may overflow
17385 the in-place relocatable field if recalculated against the start
17386 address of the symbol's containing section. */
17387 if (HAVE_IN_PLACE_ADDENDS
17388 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17392 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17393 to a floating-point stub. The same is true for non-R_MIPS16_26
17394 relocations against MIPS16 functions; in this case, the stub becomes
17395 the function's canonical address.
17397 Floating-point stubs are stored in unique .mips16.call.* or
17398 .mips16.fn.* sections. If a stub T for function F is in section S,
17399 the first relocation in section S must be against F; this is how the
17400 linker determines the target function. All relocations that might
17401 resolve to T must also be against F. We therefore have the following
17402 restrictions, which are given in an intentionally-redundant way:
17404 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17407 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17408 if that stub might be used.
17410 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17413 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17414 that stub might be used.
17416 There is a further restriction:
17418 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17419 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17420 targets with in-place addends; the relocation field cannot
17421 encode the low bit.
17423 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17424 against a MIPS16 symbol. We deal with (5) by by not reducing any
17425 such relocations on REL targets.
17427 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17428 relocation against some symbol R, no relocation against R may be
17429 reduced. (Note that this deals with (2) as well as (1) because
17430 relocations against global symbols will never be reduced on ELF
17431 targets.) This approach is a little simpler than trying to detect
17432 stub sections, and gives the "all or nothing" per-symbol consistency
17433 that we have for MIPS16 symbols. */
17435 && fixp->fx_subsy == NULL
17436 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17437 || *symbol_get_tc (fixp->fx_addsy)
17438 || (HAVE_IN_PLACE_ADDENDS
17439 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17440 && jmp_reloc_p (fixp->fx_r_type))))
17447 /* Translate internal representation of relocation info to BFD target
17451 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17453 static arelent *retval[4];
17455 bfd_reloc_code_real_type code;
17457 memset (retval, 0, sizeof(retval));
17458 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17459 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17460 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17461 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17463 if (fixp->fx_pcrel)
17465 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17466 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17467 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17468 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17470 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17471 Relocations want only the symbol offset. */
17472 reloc->addend = fixp->fx_addnumber + reloc->address;
17475 /* A gruesome hack which is a result of the gruesome gas
17476 reloc handling. What's worse, for COFF (as opposed to
17477 ECOFF), we might need yet another copy of reloc->address.
17478 See bfd_install_relocation. */
17479 reloc->addend += reloc->address;
17483 reloc->addend = fixp->fx_addnumber;
17485 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17486 entry to be used in the relocation's section offset. */
17487 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17489 reloc->address = reloc->addend;
17493 code = fixp->fx_r_type;
17495 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17496 if (reloc->howto == NULL)
17498 as_bad_where (fixp->fx_file, fixp->fx_line,
17499 _("Can not represent %s relocation in this object file format"),
17500 bfd_get_reloc_code_name (code));
17507 /* Relax a machine dependent frag. This returns the amount by which
17508 the current size of the frag should change. */
17511 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17513 if (RELAX_BRANCH_P (fragp->fr_subtype))
17515 offsetT old_var = fragp->fr_var;
17517 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17519 return fragp->fr_var - old_var;
17522 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17524 offsetT old_var = fragp->fr_var;
17525 offsetT new_var = 4;
17527 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17528 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17529 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17530 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17531 fragp->fr_var = new_var;
17533 return new_var - old_var;
17536 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17539 if (mips16_extended_frag (fragp, NULL, stretch))
17541 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17543 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17548 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17550 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17557 /* Convert a machine dependent frag. */
17560 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17562 if (RELAX_BRANCH_P (fragp->fr_subtype))
17565 unsigned long insn;
17569 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
17571 if (target_big_endian)
17572 insn = bfd_getb32 (buf);
17574 insn = bfd_getl32 (buf);
17576 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17578 /* We generate a fixup instead of applying it right now
17579 because, if there are linker relaxations, we're going to
17580 need the relocations. */
17581 exp.X_op = O_symbol;
17582 exp.X_add_symbol = fragp->fr_symbol;
17583 exp.X_add_number = fragp->fr_offset;
17585 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17586 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
17587 fixp->fx_file = fragp->fr_file;
17588 fixp->fx_line = fragp->fr_line;
17590 md_number_to_chars ((char *) buf, insn, 4);
17597 as_warn_where (fragp->fr_file, fragp->fr_line,
17598 _("Relaxed out-of-range branch into a jump"));
17600 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17603 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17605 /* Reverse the branch. */
17606 switch ((insn >> 28) & 0xf)
17609 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17610 have the condition reversed by tweaking a single
17611 bit, and their opcodes all have 0x4???????. */
17612 gas_assert ((insn & 0xf1000000) == 0x41000000);
17613 insn ^= 0x00010000;
17617 /* bltz 0x04000000 bgez 0x04010000
17618 bltzal 0x04100000 bgezal 0x04110000 */
17619 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17620 insn ^= 0x00010000;
17624 /* beq 0x10000000 bne 0x14000000
17625 blez 0x18000000 bgtz 0x1c000000 */
17626 insn ^= 0x04000000;
17634 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17636 /* Clear the and-link bit. */
17637 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17639 /* bltzal 0x04100000 bgezal 0x04110000
17640 bltzall 0x04120000 bgezall 0x04130000 */
17641 insn &= ~0x00100000;
17644 /* Branch over the branch (if the branch was likely) or the
17645 full jump (not likely case). Compute the offset from the
17646 current instruction to branch to. */
17647 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17651 /* How many bytes in instructions we've already emitted? */
17652 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17653 /* How many bytes in instructions from here to the end? */
17654 i = fragp->fr_var - i;
17656 /* Convert to instruction count. */
17658 /* Branch counts from the next instruction. */
17661 /* Branch over the jump. */
17662 md_number_to_chars ((char *) buf, insn, 4);
17666 md_number_to_chars ((char *) buf, 0, 4);
17669 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17671 /* beql $0, $0, 2f */
17673 /* Compute the PC offset from the current instruction to
17674 the end of the variable frag. */
17675 /* How many bytes in instructions we've already emitted? */
17676 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17677 /* How many bytes in instructions from here to the end? */
17678 i = fragp->fr_var - i;
17679 /* Convert to instruction count. */
17681 /* Don't decrement i, because we want to branch over the
17685 md_number_to_chars ((char *) buf, insn, 4);
17688 md_number_to_chars ((char *) buf, 0, 4);
17693 if (mips_pic == NO_PIC)
17696 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17697 ? 0x0c000000 : 0x08000000);
17698 exp.X_op = O_symbol;
17699 exp.X_add_symbol = fragp->fr_symbol;
17700 exp.X_add_number = fragp->fr_offset;
17702 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17703 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
17704 fixp->fx_file = fragp->fr_file;
17705 fixp->fx_line = fragp->fr_line;
17707 md_number_to_chars ((char *) buf, insn, 4);
17712 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17714 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17715 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17716 insn |= at << OP_SH_RT;
17717 exp.X_op = O_symbol;
17718 exp.X_add_symbol = fragp->fr_symbol;
17719 exp.X_add_number = fragp->fr_offset;
17721 if (fragp->fr_offset)
17723 exp.X_add_symbol = make_expr_symbol (&exp);
17724 exp.X_add_number = 0;
17727 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17728 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
17729 fixp->fx_file = fragp->fr_file;
17730 fixp->fx_line = fragp->fr_line;
17732 md_number_to_chars ((char *) buf, insn, 4);
17735 if (mips_opts.isa == ISA_MIPS1)
17738 md_number_to_chars ((char *) buf, 0, 4);
17742 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17743 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17744 insn |= at << OP_SH_RS | at << OP_SH_RT;
17746 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17747 4, &exp, FALSE, BFD_RELOC_LO16);
17748 fixp->fx_file = fragp->fr_file;
17749 fixp->fx_line = fragp->fr_line;
17751 md_number_to_chars ((char *) buf, insn, 4);
17755 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17759 insn |= at << OP_SH_RS;
17761 md_number_to_chars ((char *) buf, insn, 4);
17766 gas_assert (buf == (bfd_byte *)fragp->fr_literal
17767 + fragp->fr_fix + fragp->fr_var);
17769 fragp->fr_fix += fragp->fr_var;
17774 /* Relax microMIPS branches. */
17775 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17777 bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
17778 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17779 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17780 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17781 bfd_boolean short_ds;
17782 unsigned long insn;
17786 exp.X_op = O_symbol;
17787 exp.X_add_symbol = fragp->fr_symbol;
17788 exp.X_add_number = fragp->fr_offset;
17790 fragp->fr_fix += fragp->fr_var;
17792 /* Handle 16-bit branches that fit or are forced to fit. */
17793 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17795 /* We generate a fixup instead of applying it right now,
17796 because if there is linker relaxation, we're going to
17797 need the relocations. */
17799 fixp = fix_new_exp (fragp,
17800 buf - (bfd_byte *) fragp->fr_literal,
17802 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17803 else if (type == 'E')
17804 fixp = fix_new_exp (fragp,
17805 buf - (bfd_byte *) fragp->fr_literal,
17807 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17811 fixp->fx_file = fragp->fr_file;
17812 fixp->fx_line = fragp->fr_line;
17814 /* These relocations can have an addend that won't fit in
17816 fixp->fx_no_overflow = 1;
17821 /* Handle 32-bit branches that fit or are forced to fit. */
17822 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17823 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17825 /* We generate a fixup instead of applying it right now,
17826 because if there is linker relaxation, we're going to
17827 need the relocations. */
17828 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17829 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17830 fixp->fx_file = fragp->fr_file;
17831 fixp->fx_line = fragp->fr_line;
17837 /* Relax 16-bit branches to 32-bit branches. */
17840 if (target_big_endian)
17841 insn = bfd_getb16 (buf);
17843 insn = bfd_getl16 (buf);
17845 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17846 insn = 0x94000000; /* beq */
17847 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17849 unsigned long regno;
17851 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17852 regno = micromips_to_32_reg_d_map [regno];
17853 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17854 insn |= regno << MICROMIPSOP_SH_RS;
17859 /* Nothing else to do, just write it out. */
17860 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17861 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17863 md_number_to_chars ((char *) buf, insn >> 16, 2);
17865 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17868 gas_assert (buf == ((bfd_byte *) fragp->fr_literal
17875 unsigned long next;
17877 if (target_big_endian)
17879 insn = bfd_getb16 (buf);
17880 next = bfd_getb16 (buf + 2);
17884 insn = bfd_getl16 (buf);
17885 next = bfd_getl16 (buf + 2);
17887 insn = (insn << 16) | next;
17890 /* Relax 32-bit branches to a sequence of instructions. */
17891 as_warn_where (fragp->fr_file, fragp->fr_line,
17892 _("Relaxed out-of-range branch into a jump"));
17894 /* Set the short-delay-slot bit. */
17895 short_ds = al && (insn & 0x02000000) != 0;
17897 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17901 /* Reverse the branch. */
17902 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17903 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17904 insn ^= 0x20000000;
17905 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17906 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17907 || (insn & 0xffe00000) == 0x40800000 /* blez */
17908 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17909 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17910 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17911 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17912 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17913 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17914 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17915 insn ^= 0x00400000;
17916 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17917 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17918 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17919 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17920 insn ^= 0x00200000;
17926 /* Clear the and-link and short-delay-slot bits. */
17927 gas_assert ((insn & 0xfda00000) == 0x40200000);
17929 /* bltzal 0x40200000 bgezal 0x40600000 */
17930 /* bltzals 0x42200000 bgezals 0x42600000 */
17931 insn &= ~0x02200000;
17934 /* Make a label at the end for use with the branch. */
17935 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17936 micromips_label_inc ();
17937 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
17939 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17943 fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
17944 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17945 fixp->fx_file = fragp->fr_file;
17946 fixp->fx_line = fragp->fr_line;
17948 /* Branch over the jump. */
17949 md_number_to_chars ((char *) buf, insn >> 16, 2);
17951 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17958 md_number_to_chars ((char *) buf, insn, 2);
17963 if (mips_pic == NO_PIC)
17965 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17967 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17968 insn = al ? jal : 0xd4000000;
17970 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17971 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
17972 fixp->fx_file = fragp->fr_file;
17973 fixp->fx_line = fragp->fr_line;
17975 md_number_to_chars ((char *) buf, insn >> 16, 2);
17977 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17984 md_number_to_chars ((char *) buf, insn, 2);
17990 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17991 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17992 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17994 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17995 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17996 insn |= at << MICROMIPSOP_SH_RT;
17998 if (exp.X_add_number)
18000 exp.X_add_symbol = make_expr_symbol (&exp);
18001 exp.X_add_number = 0;
18004 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18005 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
18006 fixp->fx_file = fragp->fr_file;
18007 fixp->fx_line = fragp->fr_line;
18009 md_number_to_chars ((char *) buf, insn >> 16, 2);
18011 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18014 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18015 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18016 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18018 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18019 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
18020 fixp->fx_file = fragp->fr_file;
18021 fixp->fx_line = fragp->fr_line;
18023 md_number_to_chars ((char *) buf, insn >> 16, 2);
18025 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18028 /* jr/jrc/jalr/jalrs $at */
18029 insn = al ? jalr : jr;
18030 insn |= at << MICROMIPSOP_SH_MJ;
18032 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18036 gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
18040 if (RELAX_MIPS16_P (fragp->fr_subtype))
18043 const struct mips16_immed_operand *op;
18044 bfd_boolean small, ext;
18047 unsigned long insn;
18048 bfd_boolean use_extend;
18049 unsigned short extend;
18051 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18052 op = mips16_immed_operands;
18053 while (op->type != type)
18056 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18067 val = resolve_symbol_value (fragp->fr_symbol);
18072 addr = fragp->fr_address + fragp->fr_fix;
18074 /* The rules for the base address of a PC relative reloc are
18075 complicated; see mips16_extended_frag. */
18076 if (type == 'p' || type == 'q')
18081 /* Ignore the low bit in the target, since it will be
18082 set for a text label. */
18083 if ((val & 1) != 0)
18086 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18088 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18091 addr &= ~ (addressT) ((1 << op->shift) - 1);
18094 /* Make sure the section winds up with the alignment we have
18097 record_alignment (asec, op->shift);
18101 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18102 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18103 as_warn_where (fragp->fr_file, fragp->fr_line,
18104 _("extended instruction in delay slot"));
18106 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
18108 if (target_big_endian)
18109 insn = bfd_getb16 (buf);
18111 insn = bfd_getl16 (buf);
18113 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
18114 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
18115 small, ext, &insn, &use_extend, &extend);
18119 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
18120 fragp->fr_fix += 2;
18124 md_number_to_chars ((char *) buf, insn, 2);
18125 fragp->fr_fix += 2;
18130 relax_substateT subtype = fragp->fr_subtype;
18131 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18132 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18136 first = RELAX_FIRST (subtype);
18137 second = RELAX_SECOND (subtype);
18138 fixp = (fixS *) fragp->fr_opcode;
18140 /* If the delay slot chosen does not match the size of the instruction,
18141 then emit a warning. */
18142 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18143 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18148 s = subtype & (RELAX_DELAY_SLOT_16BIT
18149 | RELAX_DELAY_SLOT_SIZE_FIRST
18150 | RELAX_DELAY_SLOT_SIZE_SECOND);
18151 msg = macro_warning (s);
18153 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
18157 /* Possibly emit a warning if we've chosen the longer option. */
18158 if (use_second == second_longer)
18164 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18165 msg = macro_warning (s);
18167 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
18171 /* Go through all the fixups for the first sequence. Disable them
18172 (by marking them as done) if we're going to use the second
18173 sequence instead. */
18175 && fixp->fx_frag == fragp
18176 && fixp->fx_where < fragp->fr_fix - second)
18178 if (subtype & RELAX_USE_SECOND)
18180 fixp = fixp->fx_next;
18183 /* Go through the fixups for the second sequence. Disable them if
18184 we're going to use the first sequence, otherwise adjust their
18185 addresses to account for the relaxation. */
18186 while (fixp && fixp->fx_frag == fragp)
18188 if (subtype & RELAX_USE_SECOND)
18189 fixp->fx_where -= first;
18192 fixp = fixp->fx_next;
18195 /* Now modify the frag contents. */
18196 if (subtype & RELAX_USE_SECOND)
18200 start = fragp->fr_literal + fragp->fr_fix - first - second;
18201 memmove (start, start + first, second);
18202 fragp->fr_fix -= first;
18205 fragp->fr_fix -= second;
18211 /* This function is called after the relocs have been generated.
18212 We've been storing mips16 text labels as odd. Here we convert them
18213 back to even for the convenience of the debugger. */
18216 mips_frob_file_after_relocs (void)
18219 unsigned int count, i;
18224 syms = bfd_get_outsymbols (stdoutput);
18225 count = bfd_get_symcount (stdoutput);
18226 for (i = 0; i < count; i++, syms++)
18227 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18228 && ((*syms)->value & 1) != 0)
18230 (*syms)->value &= ~1;
18231 /* If the symbol has an odd size, it was probably computed
18232 incorrectly, so adjust that as well. */
18233 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18234 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18240 /* This function is called whenever a label is defined, including fake
18241 labels instantiated off the dot special symbol. It is used when
18242 handling branch delays; if a branch has a label, we assume we cannot
18243 move it. This also bumps the value of the symbol by 1 in compressed
18247 mips_record_label (symbolS *sym)
18249 segment_info_type *si = seg_info (now_seg);
18250 struct insn_label_list *l;
18252 if (free_insn_labels == NULL)
18253 l = (struct insn_label_list *) xmalloc (sizeof *l);
18256 l = free_insn_labels;
18257 free_insn_labels = l->next;
18261 l->next = si->label_list;
18262 si->label_list = l;
18265 /* This function is called as tc_frob_label() whenever a label is defined
18266 and adds a DWARF-2 record we only want for true labels. */
18269 mips_define_label (symbolS *sym)
18271 mips_record_label (sym);
18273 dwarf2_emit_label (sym);
18277 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18279 /* Some special processing for a MIPS ELF file. */
18282 mips_elf_final_processing (void)
18284 /* Write out the register information. */
18285 if (mips_abi != N64_ABI)
18289 s.ri_gprmask = mips_gprmask;
18290 s.ri_cprmask[0] = mips_cprmask[0];
18291 s.ri_cprmask[1] = mips_cprmask[1];
18292 s.ri_cprmask[2] = mips_cprmask[2];
18293 s.ri_cprmask[3] = mips_cprmask[3];
18294 /* The gp_value field is set by the MIPS ELF backend. */
18296 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18297 ((Elf32_External_RegInfo *)
18298 mips_regmask_frag));
18302 Elf64_Internal_RegInfo s;
18304 s.ri_gprmask = mips_gprmask;
18306 s.ri_cprmask[0] = mips_cprmask[0];
18307 s.ri_cprmask[1] = mips_cprmask[1];
18308 s.ri_cprmask[2] = mips_cprmask[2];
18309 s.ri_cprmask[3] = mips_cprmask[3];
18310 /* The gp_value field is set by the MIPS ELF backend. */
18312 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18313 ((Elf64_External_RegInfo *)
18314 mips_regmask_frag));
18317 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18318 sort of BFD interface for this. */
18319 if (mips_any_noreorder)
18320 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18321 if (mips_pic != NO_PIC)
18323 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18324 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18327 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18329 /* Set MIPS ELF flags for ASEs. */
18330 /* We may need to define a new flag for DSP ASE, and set this flag when
18331 file_ase_dsp is true. */
18332 /* Same for DSP R2. */
18333 /* We may need to define a new flag for MT ASE, and set this flag when
18334 file_ase_mt is true. */
18335 if (file_ase_mips16)
18336 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18337 if (file_ase_micromips)
18338 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18339 #if 0 /* XXX FIXME */
18340 if (file_ase_mips3d)
18341 elf_elfheader (stdoutput)->e_flags |= ???;
18344 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18346 /* Set the MIPS ELF ABI flags. */
18347 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18348 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18349 else if (mips_abi == O64_ABI)
18350 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18351 else if (mips_abi == EABI_ABI)
18353 if (!file_mips_gp32)
18354 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18356 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18358 else if (mips_abi == N32_ABI)
18359 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18361 /* Nothing to do for N64_ABI. */
18363 if (mips_32bitmode)
18364 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18366 #if 0 /* XXX FIXME */
18367 /* 32 bit code with 64 bit FP registers. */
18368 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18369 elf_elfheader (stdoutput)->e_flags |= ???;
18373 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18375 typedef struct proc {
18377 symbolS *func_end_sym;
18378 unsigned long reg_mask;
18379 unsigned long reg_offset;
18380 unsigned long fpreg_mask;
18381 unsigned long fpreg_offset;
18382 unsigned long frame_offset;
18383 unsigned long frame_reg;
18384 unsigned long pc_reg;
18387 static procS cur_proc;
18388 static procS *cur_proc_ptr;
18389 static int numprocs;
18391 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18392 as "2", and a normal nop as "0". */
18394 #define NOP_OPCODE_MIPS 0
18395 #define NOP_OPCODE_MIPS16 1
18396 #define NOP_OPCODE_MICROMIPS 2
18399 mips_nop_opcode (void)
18401 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18402 return NOP_OPCODE_MICROMIPS;
18403 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18404 return NOP_OPCODE_MIPS16;
18406 return NOP_OPCODE_MIPS;
18409 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18410 32-bit microMIPS NOPs here (if applicable). */
18413 mips_handle_align (fragS *fragp)
18417 int bytes, size, excess;
18420 if (fragp->fr_type != rs_align_code)
18423 p = fragp->fr_literal + fragp->fr_fix;
18425 switch (nop_opcode)
18427 case NOP_OPCODE_MICROMIPS:
18428 opcode = micromips_nop32_insn.insn_opcode;
18431 case NOP_OPCODE_MIPS16:
18432 opcode = mips16_nop_insn.insn_opcode;
18435 case NOP_OPCODE_MIPS:
18437 opcode = nop_insn.insn_opcode;
18442 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18443 excess = bytes % size;
18445 /* Handle the leading part if we're not inserting a whole number of
18446 instructions, and make it the end of the fixed part of the frag.
18447 Try to fit in a short microMIPS NOP if applicable and possible,
18448 and use zeroes otherwise. */
18449 gas_assert (excess < 4);
18450 fragp->fr_fix += excess;
18455 /* Fall through. */
18457 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18459 md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
18464 /* Fall through. */
18467 /* Fall through. */
18472 md_number_to_chars (p, opcode, size);
18473 fragp->fr_var = size;
18477 md_obj_begin (void)
18484 /* Check for premature end, nesting errors, etc. */
18486 as_warn (_("missing .end at end of assembly"));
18495 if (*input_line_pointer == '-')
18497 ++input_line_pointer;
18500 if (!ISDIGIT (*input_line_pointer))
18501 as_bad (_("expected simple number"));
18502 if (input_line_pointer[0] == '0')
18504 if (input_line_pointer[1] == 'x')
18506 input_line_pointer += 2;
18507 while (ISXDIGIT (*input_line_pointer))
18510 val |= hex_value (*input_line_pointer++);
18512 return negative ? -val : val;
18516 ++input_line_pointer;
18517 while (ISDIGIT (*input_line_pointer))
18520 val |= *input_line_pointer++ - '0';
18522 return negative ? -val : val;
18525 if (!ISDIGIT (*input_line_pointer))
18527 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18528 *input_line_pointer, *input_line_pointer);
18529 as_warn (_("invalid number"));
18532 while (ISDIGIT (*input_line_pointer))
18535 val += *input_line_pointer++ - '0';
18537 return negative ? -val : val;
18540 /* The .file directive; just like the usual .file directive, but there
18541 is an initial number which is the ECOFF file index. In the non-ECOFF
18542 case .file implies DWARF-2. */
18545 s_mips_file (int x ATTRIBUTE_UNUSED)
18547 static int first_file_directive = 0;
18549 if (ECOFF_DEBUGGING)
18558 filename = dwarf2_directive_file (0);
18560 /* Versions of GCC up to 3.1 start files with a ".file"
18561 directive even for stabs output. Make sure that this
18562 ".file" is handled. Note that you need a version of GCC
18563 after 3.1 in order to support DWARF-2 on MIPS. */
18564 if (filename != NULL && ! first_file_directive)
18566 (void) new_logical_line (filename, -1);
18567 s_app_file_string (filename, 0);
18569 first_file_directive = 1;
18573 /* The .loc directive, implying DWARF-2. */
18576 s_mips_loc (int x ATTRIBUTE_UNUSED)
18578 if (!ECOFF_DEBUGGING)
18579 dwarf2_directive_loc (0);
18582 /* The .end directive. */
18585 s_mips_end (int x ATTRIBUTE_UNUSED)
18589 /* Following functions need their own .frame and .cprestore directives. */
18590 mips_frame_reg_valid = 0;
18591 mips_cprestore_valid = 0;
18593 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18596 demand_empty_rest_of_line ();
18601 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18602 as_warn (_(".end not in text section"));
18606 as_warn (_(".end directive without a preceding .ent directive."));
18607 demand_empty_rest_of_line ();
18613 gas_assert (S_GET_NAME (p));
18614 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18615 as_warn (_(".end symbol does not match .ent symbol."));
18617 if (debug_type == DEBUG_STABS)
18618 stabs_generate_asm_endfunc (S_GET_NAME (p),
18622 as_warn (_(".end directive missing or unknown symbol"));
18625 /* Create an expression to calculate the size of the function. */
18626 if (p && cur_proc_ptr)
18628 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18629 expressionS *exp = xmalloc (sizeof (expressionS));
18632 exp->X_op = O_subtract;
18633 exp->X_add_symbol = symbol_temp_new_now ();
18634 exp->X_op_symbol = p;
18635 exp->X_add_number = 0;
18637 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18640 /* Generate a .pdr section. */
18641 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18643 segT saved_seg = now_seg;
18644 subsegT saved_subseg = now_subseg;
18648 #ifdef md_flush_pending_output
18649 md_flush_pending_output ();
18652 gas_assert (pdr_seg);
18653 subseg_set (pdr_seg, 0);
18655 /* Write the symbol. */
18656 exp.X_op = O_symbol;
18657 exp.X_add_symbol = p;
18658 exp.X_add_number = 0;
18659 emit_expr (&exp, 4);
18661 fragp = frag_more (7 * 4);
18663 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18664 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18665 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18666 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18667 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18668 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18669 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18671 subseg_set (saved_seg, saved_subseg);
18673 #endif /* OBJ_ELF */
18675 cur_proc_ptr = NULL;
18678 /* The .aent and .ent directives. */
18681 s_mips_ent (int aent)
18685 symbolP = get_symbol ();
18686 if (*input_line_pointer == ',')
18687 ++input_line_pointer;
18688 SKIP_WHITESPACE ();
18689 if (ISDIGIT (*input_line_pointer)
18690 || *input_line_pointer == '-')
18693 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18694 as_warn (_(".ent or .aent not in text section."));
18696 if (!aent && cur_proc_ptr)
18697 as_warn (_("missing .end"));
18701 /* This function needs its own .frame and .cprestore directives. */
18702 mips_frame_reg_valid = 0;
18703 mips_cprestore_valid = 0;
18705 cur_proc_ptr = &cur_proc;
18706 memset (cur_proc_ptr, '\0', sizeof (procS));
18708 cur_proc_ptr->func_sym = symbolP;
18712 if (debug_type == DEBUG_STABS)
18713 stabs_generate_asm_func (S_GET_NAME (symbolP),
18714 S_GET_NAME (symbolP));
18717 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18719 demand_empty_rest_of_line ();
18722 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18723 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18724 s_mips_frame is used so that we can set the PDR information correctly.
18725 We can't use the ecoff routines because they make reference to the ecoff
18726 symbol table (in the mdebug section). */
18729 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18732 if (IS_ELF && !ECOFF_DEBUGGING)
18736 if (cur_proc_ptr == (procS *) NULL)
18738 as_warn (_(".frame outside of .ent"));
18739 demand_empty_rest_of_line ();
18743 cur_proc_ptr->frame_reg = tc_get_register (1);
18745 SKIP_WHITESPACE ();
18746 if (*input_line_pointer++ != ','
18747 || get_absolute_expression_and_terminator (&val) != ',')
18749 as_warn (_("Bad .frame directive"));
18750 --input_line_pointer;
18751 demand_empty_rest_of_line ();
18755 cur_proc_ptr->frame_offset = val;
18756 cur_proc_ptr->pc_reg = tc_get_register (0);
18758 demand_empty_rest_of_line ();
18761 #endif /* OBJ_ELF */
18765 /* The .fmask and .mask directives. If the mdebug section is present
18766 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18767 embedded targets, s_mips_mask is used so that we can set the PDR
18768 information correctly. We can't use the ecoff routines because they
18769 make reference to the ecoff symbol table (in the mdebug section). */
18772 s_mips_mask (int reg_type)
18775 if (IS_ELF && !ECOFF_DEBUGGING)
18779 if (cur_proc_ptr == (procS *) NULL)
18781 as_warn (_(".mask/.fmask outside of .ent"));
18782 demand_empty_rest_of_line ();
18786 if (get_absolute_expression_and_terminator (&mask) != ',')
18788 as_warn (_("Bad .mask/.fmask directive"));
18789 --input_line_pointer;
18790 demand_empty_rest_of_line ();
18794 off = get_absolute_expression ();
18796 if (reg_type == 'F')
18798 cur_proc_ptr->fpreg_mask = mask;
18799 cur_proc_ptr->fpreg_offset = off;
18803 cur_proc_ptr->reg_mask = mask;
18804 cur_proc_ptr->reg_offset = off;
18807 demand_empty_rest_of_line ();
18810 #endif /* OBJ_ELF */
18811 s_ignore (reg_type);
18814 /* A table describing all the processors gas knows about. Names are
18815 matched in the order listed.
18817 To ease comparison, please keep this table in the same order as
18818 gcc's mips_cpu_info_table[]. */
18819 static const struct mips_cpu_info mips_cpu_info_table[] =
18821 /* Entries for generic ISAs */
18822 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
18823 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
18824 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
18825 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
18826 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
18827 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
18828 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
18829 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
18830 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
18833 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
18834 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
18835 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
18838 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
18841 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
18842 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
18843 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
18844 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
18845 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
18846 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
18847 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
18848 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
18849 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
18850 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
18851 { "orion", 0, ISA_MIPS3, CPU_R4600 },
18852 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
18853 /* ST Microelectronics Loongson 2E and 2F cores */
18854 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
18855 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
18858 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
18859 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
18860 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
18861 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
18862 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
18863 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
18864 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
18865 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
18866 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
18867 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
18868 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
18869 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
18870 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
18871 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
18872 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
18875 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
18876 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
18877 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
18878 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18880 /* MIPS 32 Release 2 */
18881 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18882 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18883 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18884 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18885 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18886 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18887 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18888 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18889 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18890 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18891 /* Deprecated forms of the above. */
18892 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18893 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18894 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18895 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18896 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18897 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18898 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18899 /* Deprecated forms of the above. */
18900 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18901 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18902 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18903 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18904 ISA_MIPS32R2, CPU_MIPS32R2 },
18905 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18906 ISA_MIPS32R2, CPU_MIPS32R2 },
18907 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18908 ISA_MIPS32R2, CPU_MIPS32R2 },
18909 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18910 ISA_MIPS32R2, CPU_MIPS32R2 },
18911 /* Deprecated forms of the above. */
18912 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18913 ISA_MIPS32R2, CPU_MIPS32R2 },
18914 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18915 ISA_MIPS32R2, CPU_MIPS32R2 },
18916 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18917 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18918 ISA_MIPS32R2, CPU_MIPS32R2 },
18919 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18920 ISA_MIPS32R2, CPU_MIPS32R2 },
18921 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18922 ISA_MIPS32R2, CPU_MIPS32R2 },
18923 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18924 ISA_MIPS32R2, CPU_MIPS32R2 },
18925 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18926 ISA_MIPS32R2, CPU_MIPS32R2 },
18927 /* Deprecated forms of the above. */
18928 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18929 ISA_MIPS32R2, CPU_MIPS32R2 },
18930 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18931 ISA_MIPS32R2, CPU_MIPS32R2 },
18932 /* 1004K cores are multiprocessor versions of the 34K. */
18933 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18934 ISA_MIPS32R2, CPU_MIPS32R2 },
18935 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18936 ISA_MIPS32R2, CPU_MIPS32R2 },
18937 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18938 ISA_MIPS32R2, CPU_MIPS32R2 },
18939 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18940 ISA_MIPS32R2, CPU_MIPS32R2 },
18943 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
18944 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
18945 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18946 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
18948 /* Broadcom SB-1 CPU core */
18949 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
18950 ISA_MIPS64, CPU_SB1 },
18951 /* Broadcom SB-1A CPU core */
18952 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
18953 ISA_MIPS64, CPU_SB1 },
18955 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
18957 /* MIPS 64 Release 2 */
18959 /* Cavium Networks Octeon CPU core */
18960 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
18963 { "xlr", 0, ISA_MIPS64, CPU_XLR },
18970 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18971 with a final "000" replaced by "k". Ignore case.
18973 Note: this function is shared between GCC and GAS. */
18976 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
18978 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
18979 given++, canonical++;
18981 return ((*given == 0 && *canonical == 0)
18982 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
18986 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18987 CPU name. We've traditionally allowed a lot of variation here.
18989 Note: this function is shared between GCC and GAS. */
18992 mips_matching_cpu_name_p (const char *canonical, const char *given)
18994 /* First see if the name matches exactly, or with a final "000"
18995 turned into "k". */
18996 if (mips_strict_matching_cpu_name_p (canonical, given))
18999 /* If not, try comparing based on numerical designation alone.
19000 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19001 if (TOLOWER (*given) == 'r')
19003 if (!ISDIGIT (*given))
19006 /* Skip over some well-known prefixes in the canonical name,
19007 hoping to find a number there too. */
19008 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19010 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19012 else if (TOLOWER (canonical[0]) == 'r')
19015 return mips_strict_matching_cpu_name_p (canonical, given);
19019 /* Parse an option that takes the name of a processor as its argument.
19020 OPTION is the name of the option and CPU_STRING is the argument.
19021 Return the corresponding processor enumeration if the CPU_STRING is
19022 recognized, otherwise report an error and return null.
19024 A similar function exists in GCC. */
19026 static const struct mips_cpu_info *
19027 mips_parse_cpu (const char *option, const char *cpu_string)
19029 const struct mips_cpu_info *p;
19031 /* 'from-abi' selects the most compatible architecture for the given
19032 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19033 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19034 version. Look first at the -mgp options, if given, otherwise base
19035 the choice on MIPS_DEFAULT_64BIT.
19037 Treat NO_ABI like the EABIs. One reason to do this is that the
19038 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19039 architecture. This code picks MIPS I for 'mips' and MIPS III for
19040 'mips64', just as we did in the days before 'from-abi'. */
19041 if (strcasecmp (cpu_string, "from-abi") == 0)
19043 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19044 return mips_cpu_info_from_isa (ISA_MIPS1);
19046 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19047 return mips_cpu_info_from_isa (ISA_MIPS3);
19049 if (file_mips_gp32 >= 0)
19050 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19052 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19057 /* 'default' has traditionally been a no-op. Probably not very useful. */
19058 if (strcasecmp (cpu_string, "default") == 0)
19061 for (p = mips_cpu_info_table; p->name != 0; p++)
19062 if (mips_matching_cpu_name_p (p->name, cpu_string))
19065 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19069 /* Return the canonical processor information for ISA (a member of the
19070 ISA_MIPS* enumeration). */
19072 static const struct mips_cpu_info *
19073 mips_cpu_info_from_isa (int isa)
19077 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19078 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19079 && isa == mips_cpu_info_table[i].isa)
19080 return (&mips_cpu_info_table[i]);
19085 static const struct mips_cpu_info *
19086 mips_cpu_info_from_arch (int arch)
19090 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19091 if (arch == mips_cpu_info_table[i].cpu)
19092 return (&mips_cpu_info_table[i]);
19098 show (FILE *stream, const char *string, int *col_p, int *first_p)
19102 fprintf (stream, "%24s", "");
19107 fprintf (stream, ", ");
19111 if (*col_p + strlen (string) > 72)
19113 fprintf (stream, "\n%24s", "");
19117 fprintf (stream, "%s", string);
19118 *col_p += strlen (string);
19124 md_show_usage (FILE *stream)
19129 fprintf (stream, _("\
19131 -EB generate big endian output\n\
19132 -EL generate little endian output\n\
19133 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19134 -G NUM allow referencing objects up to NUM bytes\n\
19135 implicitly with the gp register [default 8]\n"));
19136 fprintf (stream, _("\
19137 -mips1 generate MIPS ISA I instructions\n\
19138 -mips2 generate MIPS ISA II instructions\n\
19139 -mips3 generate MIPS ISA III instructions\n\
19140 -mips4 generate MIPS ISA IV instructions\n\
19141 -mips5 generate MIPS ISA V instructions\n\
19142 -mips32 generate MIPS32 ISA instructions\n\
19143 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19144 -mips64 generate MIPS64 ISA instructions\n\
19145 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19146 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19150 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19151 show (stream, mips_cpu_info_table[i].name, &column, &first);
19152 show (stream, "from-abi", &column, &first);
19153 fputc ('\n', stream);
19155 fprintf (stream, _("\
19156 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19157 -no-mCPU don't generate code specific to CPU.\n\
19158 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19162 show (stream, "3900", &column, &first);
19163 show (stream, "4010", &column, &first);
19164 show (stream, "4100", &column, &first);
19165 show (stream, "4650", &column, &first);
19166 fputc ('\n', stream);
19168 fprintf (stream, _("\
19169 -mips16 generate mips16 instructions\n\
19170 -no-mips16 do not generate mips16 instructions\n"));
19171 fprintf (stream, _("\
19172 -mmicromips generate microMIPS instructions\n\
19173 -mno-micromips do not generate microMIPS instructions\n"));
19174 fprintf (stream, _("\
19175 -msmartmips generate smartmips instructions\n\
19176 -mno-smartmips do not generate smartmips instructions\n"));
19177 fprintf (stream, _("\
19178 -mdsp generate DSP instructions\n\
19179 -mno-dsp do not generate DSP instructions\n"));
19180 fprintf (stream, _("\
19181 -mdspr2 generate DSP R2 instructions\n\
19182 -mno-dspr2 do not generate DSP R2 instructions\n"));
19183 fprintf (stream, _("\
19184 -mmt generate MT instructions\n\
19185 -mno-mt do not generate MT instructions\n"));
19186 fprintf (stream, _("\
19187 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19188 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19189 -mfix-vr4120 work around certain VR4120 errata\n\
19190 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19191 -mfix-24k insert a nop after ERET and DERET instructions\n\
19192 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19193 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19194 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19195 -msym32 assume all symbols have 32-bit values\n\
19196 -O0 remove unneeded NOPs, do not swap branches\n\
19197 -O remove unneeded NOPs and swap branches\n\
19198 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19199 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19200 fprintf (stream, _("\
19201 -mhard-float allow floating-point instructions\n\
19202 -msoft-float do not allow floating-point instructions\n\
19203 -msingle-float only allow 32-bit floating-point operations\n\
19204 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19205 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19208 fprintf (stream, _("\
19209 -KPIC, -call_shared generate SVR4 position independent code\n\
19210 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19211 -mvxworks-pic generate VxWorks position independent code\n\
19212 -non_shared do not generate code that can operate with DSOs\n\
19213 -xgot assume a 32 bit GOT\n\
19214 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19215 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19216 position dependent (non shared) code\n\
19217 -mabi=ABI create ABI conformant object file for:\n"));
19221 show (stream, "32", &column, &first);
19222 show (stream, "o64", &column, &first);
19223 show (stream, "n32", &column, &first);
19224 show (stream, "64", &column, &first);
19225 show (stream, "eabi", &column, &first);
19227 fputc ('\n', stream);
19229 fprintf (stream, _("\
19230 -32 create o32 ABI object file (default)\n\
19231 -n32 create n32 ABI object file\n\
19232 -64 create 64 ABI object file\n"));
19238 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19240 if (HAVE_64BIT_SYMBOLS)
19241 return dwarf2_format_64bit_irix;
19243 return dwarf2_format_32bit;
19248 mips_dwarf2_addr_size (void)
19250 if (HAVE_64BIT_OBJECTS)
19256 /* Standard calling conventions leave the CFA at SP on entry. */
19258 mips_cfi_frame_initial_instructions (void)
19260 cfi_add_CFA_def_cfa_register (SP);
19264 tc_mips_regname_to_dw2regnum (char *regname)
19266 unsigned int regnum = -1;
19269 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))